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-rw-r--r--tools/perf/pmu-events/arch/x86/nehalemex/other.json170
1 files changed, 53 insertions, 117 deletions
diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/other.json b/tools/perf/pmu-events/arch/x86/nehalemex/other.json
index af0860622445..f6887b234b0e 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemex/other.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemex/other.json
@@ -1,210 +1,146 @@
[
{
- "EventCode": "0xE8",
+ "BriefDescription": "ES segment renames",
"Counter": "0,1,2,3",
- "UMask": "0x1",
- "EventName": "BPU_CLEARS.EARLY",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Early Branch Prediciton Unit clears"
- },
- {
- "EventCode": "0xE8",
- "Counter": "0,1,2,3",
- "UMask": "0x2",
- "EventName": "BPU_CLEARS.LATE",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Late Branch Prediction Unit clears"
- },
- {
- "EventCode": "0xE5",
- "Counter": "0,1,2,3",
- "UMask": "0x1",
- "EventName": "BPU_MISSED_CALL_RET",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Branch prediction unit missed call or return"
- },
- {
"EventCode": "0xD5",
- "Counter": "0,1,2,3",
- "UMask": "0x1",
"EventName": "ES_REG_RENAMES",
"SampleAfterValue": "2000000",
- "BriefDescription": "ES segment renames"
+ "UMask": "0x1"
},
{
- "EventCode": "0x6C",
+ "BriefDescription": "I/O transactions",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0x6C",
"EventName": "IO_TRANSACTIONS",
"SampleAfterValue": "2000000",
- "BriefDescription": "I/O transactions"
+ "UMask": "0x1"
},
{
- "EventCode": "0x80",
+ "BriefDescription": "L1I instruction fetch stall cycles",
"Counter": "0,1,2,3",
- "UMask": "0x4",
+ "EventCode": "0x80",
"EventName": "L1I.CYCLES_STALLED",
"SampleAfterValue": "2000000",
- "BriefDescription": "L1I instruction fetch stall cycles"
+ "UMask": "0x4"
},
{
- "EventCode": "0x80",
+ "BriefDescription": "L1I instruction fetch hits",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0x80",
"EventName": "L1I.HITS",
"SampleAfterValue": "2000000",
- "BriefDescription": "L1I instruction fetch hits"
+ "UMask": "0x1"
},
{
- "EventCode": "0x80",
+ "BriefDescription": "L1I instruction fetch misses",
"Counter": "0,1,2,3",
- "UMask": "0x2",
+ "EventCode": "0x80",
"EventName": "L1I.MISSES",
"SampleAfterValue": "2000000",
- "BriefDescription": "L1I instruction fetch misses"
+ "UMask": "0x2"
},
{
- "EventCode": "0x80",
+ "BriefDescription": "L1I Instruction fetches",
"Counter": "0,1,2,3",
- "UMask": "0x3",
+ "EventCode": "0x80",
"EventName": "L1I.READS",
"SampleAfterValue": "2000000",
- "BriefDescription": "L1I Instruction fetches"
+ "UMask": "0x3"
},
{
- "EventCode": "0x82",
+ "BriefDescription": "Large ITLB hit",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0x82",
"EventName": "LARGE_ITLB.HIT",
"SampleAfterValue": "200000",
- "BriefDescription": "Large ITLB hit"
+ "UMask": "0x1"
},
{
- "EventCode": "0x13",
+ "BriefDescription": "All loads dispatched",
"Counter": "0,1,2,3",
- "UMask": "0x7",
+ "EventCode": "0x13",
"EventName": "LOAD_DISPATCH.ANY",
"SampleAfterValue": "2000000",
- "BriefDescription": "All loads dispatched"
+ "UMask": "0x7"
},
{
- "EventCode": "0x13",
+ "BriefDescription": "Loads dispatched from the MOB",
"Counter": "0,1,2,3",
- "UMask": "0x4",
+ "EventCode": "0x13",
"EventName": "LOAD_DISPATCH.MOB",
"SampleAfterValue": "2000000",
- "BriefDescription": "Loads dispatched from the MOB"
+ "UMask": "0x4"
},
{
- "EventCode": "0x13",
+ "BriefDescription": "Loads dispatched that bypass the MOB",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS",
"SampleAfterValue": "2000000",
- "BriefDescription": "Loads dispatched that bypass the MOB"
+ "UMask": "0x1"
},
{
- "EventCode": "0x13",
+ "BriefDescription": "Loads dispatched from stage 305",
"Counter": "0,1,2,3",
- "UMask": "0x2",
+ "EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS_DELAYED",
"SampleAfterValue": "2000000",
- "BriefDescription": "Loads dispatched from stage 305"
+ "UMask": "0x2"
},
{
- "EventCode": "0x7",
+ "BriefDescription": "False dependencies due to partial address aliasing",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0x7",
"EventName": "PARTIAL_ADDRESS_ALIAS",
"SampleAfterValue": "200000",
- "BriefDescription": "False dependencies due to partial address aliasing"
- },
- {
- "EventCode": "0xD2",
- "Counter": "0,1,2,3",
- "UMask": "0xf",
- "EventName": "RAT_STALLS.ANY",
- "SampleAfterValue": "2000000",
- "BriefDescription": "All RAT stall cycles"
- },
- {
- "EventCode": "0xD2",
- "Counter": "0,1,2,3",
- "UMask": "0x1",
- "EventName": "RAT_STALLS.FLAGS",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Flag stall cycles"
- },
- {
- "EventCode": "0xD2",
- "Counter": "0,1,2,3",
- "UMask": "0x2",
- "EventName": "RAT_STALLS.REGISTERS",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Partial register stall cycles"
- },
- {
- "EventCode": "0xD2",
- "Counter": "0,1,2,3",
- "UMask": "0x4",
- "EventName": "RAT_STALLS.ROB_READ_PORT",
- "SampleAfterValue": "2000000",
- "BriefDescription": "ROB read port stalls cycles"
+ "UMask": "0x1"
},
{
- "EventCode": "0xD2",
+ "BriefDescription": "All Store buffer stall cycles",
"Counter": "0,1,2,3",
- "UMask": "0x8",
- "EventName": "RAT_STALLS.SCOREBOARD",
- "SampleAfterValue": "2000000",
- "BriefDescription": "Scoreboard stall cycles"
- },
- {
"EventCode": "0x4",
- "Counter": "0,1,2,3",
- "UMask": "0x7",
"EventName": "SB_DRAIN.ANY",
"SampleAfterValue": "200000",
- "BriefDescription": "All Store buffer stall cycles"
+ "UMask": "0x7"
},
{
- "EventCode": "0xD4",
+ "BriefDescription": "Segment rename stall cycles",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0xD4",
"EventName": "SEG_RENAME_STALLS",
"SampleAfterValue": "2000000",
- "BriefDescription": "Segment rename stall cycles"
+ "UMask": "0x1"
},
{
- "EventCode": "0xB8",
+ "BriefDescription": "Thread responded HIT to snoop",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HIT",
"SampleAfterValue": "100000",
- "BriefDescription": "Thread responded HIT to snoop"
+ "UMask": "0x1"
},
{
- "EventCode": "0xB8",
+ "BriefDescription": "Thread responded HITE to snoop",
"Counter": "0,1,2,3",
- "UMask": "0x2",
+ "EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITE",
"SampleAfterValue": "100000",
- "BriefDescription": "Thread responded HITE to snoop"
+ "UMask": "0x2"
},
{
- "EventCode": "0xB8",
+ "BriefDescription": "Thread responded HITM to snoop",
"Counter": "0,1,2,3",
- "UMask": "0x4",
+ "EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITM",
"SampleAfterValue": "100000",
- "BriefDescription": "Thread responded HITM to snoop"
+ "UMask": "0x4"
},
{
- "EventCode": "0xF6",
+ "BriefDescription": "Super Queue full stall cycles",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0xF6",
"EventName": "SQ_FULL_STALL_CYCLES",
"SampleAfterValue": "2000000",
- "BriefDescription": "Super Queue full stall cycles"
+ "UMask": "0x1"
}
-] \ No newline at end of file
+]
generated by cgit v1.2.3 (git 2.39.0) at 2025-01-05 05:56:20 +0300