diff options
Diffstat (limited to 'sound')
| -rw-r--r-- | sound/soc/sunxi/sun8i-codec.c | 317 |
1 files changed, 207 insertions, 110 deletions
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 178f6fb31fd4..7590c4b04d14 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -24,10 +24,13 @@ #define SUN8I_SYSCLK_CTL 0x00c #define SUN8I_SYSCLK_CTL_AIF1CLK_ENA 11 -#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL 9 -#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC 8 +#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL (0x2 << 8) +#define SUN8I_SYSCLK_CTL_AIF2CLK_ENA 7 +#define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_PLL (0x2 << 4) #define SUN8I_SYSCLK_CTL_SYSCLK_ENA 3 #define SUN8I_SYSCLK_CTL_SYSCLK_SRC 0 +#define SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF1CLK (0x0 << 0) +#define SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF2CLK (0x1 << 0) #define SUN8I_MOD_CLK_ENA 0x010 #define SUN8I_MOD_CLK_ENA_AIF1 15 #define SUN8I_MOD_CLK_ENA_ADC 3 @@ -51,9 +54,13 @@ #define SUN8I_AIF1_ADCDAT_CTRL 0x044 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14 +#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC 10 +#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC 8 #define SUN8I_AIF1_DACDAT_CTRL 0x048 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14 +#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_SRC 10 +#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_SRC 8 #define SUN8I_AIF1_MXR_SRC 0x04c #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L 15 #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL 14 @@ -79,6 +86,8 @@ #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8 +#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK GENMASK(9, 8) +#define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK GENMASK(5, 4) #define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9) @@ -158,7 +167,7 @@ static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params) static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { - struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component); + struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); u32 value; /* clock masters */ @@ -290,7 +299,7 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { - struct sun8i_codec *scodec = snd_soc_component_get_drvdata(dai->component); + struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); int sample_rate, lrck_div; u8 bclk_div; @@ -323,36 +332,31 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, SUN8I_SYS_SR_CTRL_AIF1_FS_MASK, sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS); - regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, - SUN8I_SYS_SR_CTRL_AIF2_FS_MASK, - sample_rate << SUN8I_SYS_SR_CTRL_AIF2_FS); return 0; } -static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { - SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch", - SUN8I_DAC_MXR_SRC, - SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L, - SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0), - SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch", - SUN8I_DAC_MXR_SRC, - SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L, - SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0), - SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, - SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL, - SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0), - SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, - SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL, - SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0), +static const char *const sun8i_aif_stereo_mux_enum_values[] = { + "Stereo", "Reverse Stereo", "Sum Mono", "Mix Mono" }; -static const struct snd_kcontrol_new sun8i_input_mixer_controls[] = { +static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_ad0_stereo_mux_enum, + SUN8I_AIF1_ADCDAT_CTRL, + SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC, + SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC, + sun8i_aif_stereo_mux_enum_values); + +static const struct snd_kcontrol_new sun8i_aif1_ad0_stereo_mux_control = + SOC_DAPM_ENUM("AIF1 AD0 Stereo Capture Route", + sun8i_aif1_ad0_stereo_mux_enum); + +static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC, SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L, SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R, 1, 0), - SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC, + SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch", + SUN8I_AIF1_MXR_SRC, SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL, SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR, 1, 0), SOC_DAPM_DOUBLE("AIF1 Data Digital ADC Capture Switch", @@ -365,31 +369,108 @@ static const struct snd_kcontrol_new sun8i_input_mixer_controls[] = { SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0), }; +static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_da0_stereo_mux_enum, + SUN8I_AIF1_DACDAT_CTRL, + SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_SRC, + SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_SRC, + sun8i_aif_stereo_mux_enum_values); + +static const struct snd_kcontrol_new sun8i_aif1_da0_stereo_mux_control = + SOC_DAPM_ENUM("AIF1 DA0 Stereo Playback Route", + sun8i_aif1_da0_stereo_mux_enum); + +static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { + SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch", + SUN8I_DAC_MXR_SRC, + SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L, + SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0), + SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch", + SUN8I_DAC_MXR_SRC, + SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L, + SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0), + SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, + SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL, + SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0), + SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, + SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL, + SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0), +}; + static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { + /* System Clocks */ SND_SOC_DAPM_CLOCK_SUPPLY("mod"), - /* Digital parts of the DACs and ADC */ - SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA, - 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("ADC", SUN8I_ADC_DIG_CTRL, SUN8I_ADC_DIG_CTRL_ENAD, - 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("AIF1CLK", + SUN8I_SYSCLK_CTL, + SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("SYSCLK", + SUN8I_SYSCLK_CTL, + SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0), + + /* Module Clocks */ + SND_SOC_DAPM_SUPPLY("CLK AIF1", + SUN8I_MOD_CLK_ENA, + SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("CLK ADC", + SUN8I_MOD_CLK_ENA, + SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("CLK DAC", + SUN8I_MOD_CLK_ENA, + SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0), + + /* Module Resets */ + SND_SOC_DAPM_SUPPLY("RST AIF1", + SUN8I_MOD_RST_CTL, + SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("RST ADC", + SUN8I_MOD_RST_CTL, + SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("RST DAC", + SUN8I_MOD_RST_CTL, + SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0), + + /* Module Supplies */ + SND_SOC_DAPM_SUPPLY("ADC", + SUN8I_ADC_DIG_CTRL, + SUN8I_ADC_DIG_CTRL_ENAD, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("DAC", + SUN8I_DAC_DIG_CTRL, + SUN8I_DAC_DIG_CTRL_ENDA, 0, NULL, 0), + + /* AIF "ADC" Outputs */ + SND_SOC_DAPM_AIF_OUT("AIF1 AD0L", "Capture", 0, + SUN8I_AIF1_ADCDAT_CTRL, + SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0), + SND_SOC_DAPM_AIF_OUT("AIF1 AD0R", "Capture", 1, + SUN8I_AIF1_ADCDAT_CTRL, + SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0), + + /* AIF "ADC" Mono/Stereo Muxes */ + SND_SOC_DAPM_MUX("AIF1 AD0L Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif1_ad0_stereo_mux_control), + SND_SOC_DAPM_MUX("AIF1 AD0R Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif1_ad0_stereo_mux_control), + + /* AIF "ADC" Mixers */ + SOC_MIXER_ARRAY("AIF1 AD0L Mixer", SND_SOC_NOPM, 0, 0, + sun8i_aif1_ad0_mixer_controls), + SOC_MIXER_ARRAY("AIF1 AD0R Mixer", SND_SOC_NOPM, 0, 0, + sun8i_aif1_ad0_mixer_controls), + + /* AIF "DAC" Mono/Stereo Muxes */ + SND_SOC_DAPM_MUX("AIF1 DA0L Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif1_da0_stereo_mux_control), + SND_SOC_DAPM_MUX("AIF1 DA0R Stereo Mux", SND_SOC_NOPM, 0, 0, + &sun8i_aif1_da0_stereo_mux_control), /* AIF "DAC" Inputs */ SND_SOC_DAPM_AIF_IN("AIF1 DA0L", "Playback", 0, SUN8I_AIF1_DACDAT_CTRL, SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0), - SND_SOC_DAPM_AIF_IN("AIF1 DA0R", "Playback", 0, + SND_SOC_DAPM_AIF_IN("AIF1 DA0R", "Playback", 1, SUN8I_AIF1_DACDAT_CTRL, SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0), - /* AIF "ADC" Outputs */ - SND_SOC_DAPM_AIF_IN("AIF1 AD0L", "Capture", 0, - SUN8I_AIF1_ADCDAT_CTRL, - SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0), - SND_SOC_DAPM_AIF_IN("AIF1 AD0R", "Capture", 0, - SUN8I_AIF1_ADCDAT_CTRL, - SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0), - /* ADC Inputs (connected to analog codec DAPM context) */ SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), @@ -398,91 +479,90 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), - /* DAC and ADC Mixers */ - SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0, + /* DAC Mixers */ + SOC_MIXER_ARRAY("DACL Mixer", SND_SOC_NOPM, 0, 0, sun8i_dac_mixer_controls), - SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0, + SOC_MIXER_ARRAY("DACR Mixer", SND_SOC_NOPM, 0, 0, sun8i_dac_mixer_controls), - SOC_MIXER_ARRAY("Left Digital ADC Mixer", SND_SOC_NOPM, 0, 0, - sun8i_input_mixer_controls), - SOC_MIXER_ARRAY("Right Digital ADC Mixer", SND_SOC_NOPM, 0, 0, - sun8i_input_mixer_controls), - - /* Clocks */ - SND_SOC_DAPM_SUPPLY("MODCLK AIF1", SUN8I_MOD_CLK_ENA, - SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA, - SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("MODCLK ADC", SUN8I_MOD_CLK_ENA, - SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("AIF1", SUN8I_SYSCLK_CTL, - SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL, - SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0), - - SND_SOC_DAPM_SUPPLY("AIF1 PLL", SUN8I_SYSCLK_CTL, - SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL, 0, NULL, 0), - /* Inversion as 0=AIF1, 1=AIF2 */ - SND_SOC_DAPM_SUPPLY("SYSCLK AIF1", SUN8I_SYSCLK_CTL, - SUN8I_SYSCLK_CTL_SYSCLK_SRC, 1, NULL, 0), - - /* Module reset */ - SND_SOC_DAPM_SUPPLY("RST AIF1", SUN8I_MOD_RST_CTL, - SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL, - SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("RST ADC", SUN8I_MOD_RST_CTL, - SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0), }; static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { /* Clock Routes */ - { "AIF1", NULL, "mod" }, - - { "AIF1", NULL, "SYSCLK AIF1" }, - { "AIF1 PLL", NULL, "AIF1" }, - { "SYSCLK", NULL, "AIF1 PLL" }, - - { "RST AIF1", NULL, "SYSCLK" }, - { "MODCLK AIF1", NULL, "RST AIF1" }, - { "AIF1 AD0L", NULL, "MODCLK AIF1" }, - { "AIF1 AD0R", NULL, "MODCLK AIF1" }, - { "AIF1 DA0L", NULL, "MODCLK AIF1" }, - { "AIF1 DA0R", NULL, "MODCLK AIF1" }, - - { "RST DAC", NULL, "SYSCLK" }, - { "MODCLK DAC", NULL, "RST DAC" }, - { "DAC", NULL, "MODCLK DAC" }, - { "DACL", NULL, "DAC" }, - { "DACR", NULL, "DAC" }, + { "AIF1CLK", NULL, "mod" }, - { "RST ADC", NULL, "SYSCLK" }, - { "MODCLK ADC", NULL, "RST ADC" }, - { "ADC", NULL, "MODCLK ADC" }, - { "ADCL", NULL, "ADC" }, - { "ADCR", NULL, "ADC" }, + { "SYSCLK", NULL, "AIF1CLK" }, - /* DAC Routes */ - { "DACL", NULL, "Left Digital DAC Mixer" }, - { "DACR", NULL, "Right Digital DAC Mixer" }, + { "CLK AIF1", NULL, "AIF1CLK" }, + { "CLK AIF1", NULL, "SYSCLK" }, + { "RST AIF1", NULL, "CLK AIF1" }, + { "AIF1 AD0L", NULL, "RST AIF1" }, + { "AIF1 AD0R", NULL, "RST AIF1" }, + { "AIF1 DA0L", NULL, "RST AIF1" }, + { "AIF1 DA0R", NULL, "RST AIF1" }, - /* DAC Mixer Routes */ - { "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0L" }, - { "Left Digital DAC Mixer", "ADC Digital DAC Playback Switch", "ADCL" }, + { "CLK ADC", NULL, "SYSCLK" }, + { "RST ADC", NULL, "CLK ADC" }, + { "ADC", NULL, "RST ADC" }, + { "ADCL", NULL, "ADC" }, + { "ADCR", NULL, "ADC" }, - { "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0R" }, - { "Right Digital DAC Mixer", "ADC Digital DAC Playback Switch", "ADCR" }, + { "CLK DAC", NULL, "SYSCLK" }, + { "RST DAC", NULL, "CLK DAC" }, + { "DAC", NULL, "RST DAC" }, + { "DACL", NULL, "DAC" }, + { "DACR", NULL, "DAC" }, - /* ADC Routes */ - { "AIF1 AD0L", NULL, "Left Digital ADC Mixer" }, - { "AIF1 AD0R", NULL, "Right Digital ADC Mixer" }, + /* AIF "ADC" Output Routes */ + { "AIF1 AD0L", NULL, "AIF1 AD0L Stereo Mux" }, + { "AIF1 AD0R", NULL, "AIF1 AD0R Stereo Mux" }, + + /* AIF "ADC" Mono/Stereo Mux Routes */ + { "AIF1 AD0L Stereo Mux", "Stereo", "AIF1 AD0L Mixer" }, + { "AIF1 AD0L Stereo Mux", "Reverse Stereo", "AIF1 AD0R Mixer" }, + { "AIF1 AD0L Stereo Mux", "Sum Mono", "AIF1 AD0L Mixer" }, + { "AIF1 AD0L Stereo Mux", "Sum Mono", "AIF1 AD0R Mixer" }, + { "AIF1 AD0L Stereo Mux", "Mix Mono", "AIF1 AD0L Mixer" }, + { "AIF1 AD0L Stereo Mux", "Mix Mono", "AIF1 AD0R Mixer" }, + + { "AIF1 AD0R Stereo Mux", "Stereo", "AIF1 AD0R Mixer" }, + { "AIF1 AD0R Stereo Mux", "Reverse Stereo", "AIF1 AD0L Mixer" }, + { "AIF1 AD0R Stereo Mux", "Sum Mono", "AIF1 AD0L Mixer" }, + { "AIF1 AD0R Stereo Mux", "Sum Mono", "AIF1 AD0R Mixer" }, + { "AIF1 AD0R Stereo Mux", "Mix Mono", "AIF1 AD0L Mixer" }, + { "AIF1 AD0R Stereo Mux", "Mix Mono", "AIF1 AD0R Mixer" }, + + /* AIF "ADC" Mixer Routes */ + { "AIF1 AD0L Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0L Stereo Mux" }, + { "AIF1 AD0L Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCL" }, + + { "AIF1 AD0R Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0R Stereo Mux" }, + { "AIF1 AD0R Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCR" }, + + /* AIF "DAC" Mono/Stereo Mux Routes */ + { "AIF1 DA0L Stereo Mux", "Stereo", "AIF1 DA0L" }, + { "AIF1 DA0L Stereo Mux", "Reverse Stereo", "AIF1 DA0R" }, + { "AIF1 DA0L Stereo Mux", "Sum Mono", "AIF1 DA0L" }, + { "AIF1 DA0L Stereo Mux", "Sum Mono", "AIF1 DA0R" }, + { "AIF1 DA0L Stereo Mux", "Mix Mono", "AIF1 DA0L" }, + { "AIF1 DA0L Stereo Mux", "Mix Mono", "AIF1 DA0R" }, + + { "AIF1 DA0R Stereo Mux", "Stereo", "AIF1 DA0R" }, + { "AIF1 DA0R Stereo Mux", "Reverse Stereo", "AIF1 DA0L" }, + { "AIF1 DA0R Stereo Mux", "Sum Mono", "AIF1 DA0L" }, + { "AIF1 DA0R Stereo Mux", "Sum Mono", "AIF1 DA0R" }, + { "AIF1 DA0R Stereo Mux", "Mix Mono", "AIF1 DA0L" }, + { "AIF1 DA0R Stereo Mux", "Mix Mono", "AIF1 DA0R" }, + + /* DAC Output Routes */ + { "DACL", NULL, "DACL Mixer" }, + { "DACR", NULL, "DACR Mixer" }, - /* ADC Mixer Routes */ - { "Left Digital ADC Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0L" }, - { "Left Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCL" }, + /* DAC Mixer Routes */ + { "DACL Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0L Stereo Mux" }, + { "DACL Mixer", "ADC Digital DAC Playback Switch", "ADCL" }, - { "Right Digital ADC Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0R" }, - { "Right Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCR" }, + { "DACR Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0R Stereo Mux" }, + { "DACR Mixer", "ADC Digital DAC Playback Switch", "ADCR" }, }; static const struct snd_soc_dapm_widget sun8i_codec_legacy_widgets[] = { @@ -524,6 +604,23 @@ static int sun8i_codec_component_probe(struct snd_soc_component *component) return ret; } + /* + * AIF1CLK and AIF2CLK share a pair of clock parents: PLL_AUDIO ("mod") + * and MCLK (from the CPU DAI connected to AIF1). MCLK's parent is also + * PLL_AUDIO, so using it adds no additional flexibility. Use PLL_AUDIO + * directly to simplify the clock tree. + */ + regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL, + SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK | + SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK, + SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL | + SUN8I_SYSCLK_CTL_AIF2CLK_SRC_PLL); + + /* Use AIF1CLK as the SYSCLK parent since AIF1 is used most often. */ + regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL, + BIT(SUN8I_SYSCLK_CTL_SYSCLK_SRC), + SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF1CLK); + return 0; } |