diff options
Diffstat (limited to 'include/linux/mfd/intel-m10-bmc.h')
| -rw-r--r-- | include/linux/mfd/intel-m10-bmc.h | 205 |
1 files changed, 167 insertions, 38 deletions
diff --git a/include/linux/mfd/intel-m10-bmc.h b/include/linux/mfd/intel-m10-bmc.h index f0044b14136e..1812ebfa11a8 100644 --- a/include/linux/mfd/intel-m10-bmc.h +++ b/include/linux/mfd/intel-m10-bmc.h @@ -7,40 +7,43 @@ #ifndef __MFD_INTEL_M10_BMC_H #define __MFD_INTEL_M10_BMC_H +#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/dev_printk.h> #include <linux/regmap.h> -#define M10BMC_LEGACY_BUILD_VER 0x300468 -#define M10BMC_SYS_BASE 0x300800 -#define M10BMC_SYS_END 0x300fff -#define M10BMC_FLASH_BASE 0x10000000 -#define M10BMC_FLASH_END 0x1fffffff -#define M10BMC_MEM_END M10BMC_FLASH_END +#define M10BMC_N3000_LEGACY_BUILD_VER 0x300468 +#define M10BMC_N3000_SYS_BASE 0x300800 +#define M10BMC_N3000_SYS_END 0x300fff +#define M10BMC_N3000_FLASH_BASE 0x10000000 +#define M10BMC_N3000_FLASH_END 0x1fffffff +#define M10BMC_N3000_MEM_END M10BMC_N3000_FLASH_END #define M10BMC_STAGING_BASE 0x18000000 #define M10BMC_STAGING_SIZE 0x3800000 /* Register offset of system registers */ -#define NIOS2_FW_VERSION 0x0 -#define M10BMC_MAC_LOW 0x10 -#define M10BMC_MAC_BYTE4 GENMASK(7, 0) -#define M10BMC_MAC_BYTE3 GENMASK(15, 8) -#define M10BMC_MAC_BYTE2 GENMASK(23, 16) -#define M10BMC_MAC_BYTE1 GENMASK(31, 24) -#define M10BMC_MAC_HIGH 0x14 -#define M10BMC_MAC_BYTE6 GENMASK(7, 0) -#define M10BMC_MAC_BYTE5 GENMASK(15, 8) -#define M10BMC_MAC_COUNT GENMASK(23, 16) -#define M10BMC_TEST_REG 0x3c -#define M10BMC_BUILD_VER 0x68 -#define M10BMC_VER_MAJOR_MSK GENMASK(23, 16) -#define M10BMC_VER_PCB_INFO_MSK GENMASK(31, 24) -#define M10BMC_VER_LEGACY_INVALID 0xffffffff +#define NIOS2_N3000_FW_VERSION 0x0 +#define M10BMC_N3000_MAC_LOW 0x10 +#define M10BMC_N3000_MAC_BYTE4 GENMASK(7, 0) +#define M10BMC_N3000_MAC_BYTE3 GENMASK(15, 8) +#define M10BMC_N3000_MAC_BYTE2 GENMASK(23, 16) +#define M10BMC_N3000_MAC_BYTE1 GENMASK(31, 24) +#define M10BMC_N3000_MAC_HIGH 0x14 +#define M10BMC_N3000_MAC_BYTE6 GENMASK(7, 0) +#define M10BMC_N3000_MAC_BYTE5 GENMASK(15, 8) +#define M10BMC_N3000_MAC_COUNT GENMASK(23, 16) +#define M10BMC_N3000_TEST_REG 0x3c +#define M10BMC_N3000_BUILD_VER 0x68 +#define M10BMC_N3000_VER_MAJOR_MSK GENMASK(23, 16) +#define M10BMC_N3000_VER_PCB_INFO_MSK GENMASK(31, 24) +#define M10BMC_N3000_VER_LEGACY_INVALID 0xffffffff /* Secure update doorbell register, in system register region */ -#define M10BMC_DOORBELL 0x400 +#define M10BMC_N3000_DOORBELL 0x400 /* Authorization Result register, in system register region */ -#define M10BMC_AUTH_RESULT 0x404 +#define M10BMC_N3000_AUTH_RESULT 0x404 /* Doorbell register fields */ #define DRBL_RSU_REQUEST BIT(0) @@ -88,7 +91,6 @@ #define HOST_STATUS_ABORT_RSU 0x2 #define rsu_prog(doorbell) FIELD_GET(DRBL_RSU_PROGRESS, doorbell) -#define rsu_stat(doorbell) FIELD_GET(DRBL_RSU_STATUS, doorbell) /* interval 100ms and timeout 5s */ #define NIOS_HANDSHAKE_INTERVAL_US (100 * 1000) @@ -103,29 +105,145 @@ #define RSU_COMPLETE_TIMEOUT_MS (40 * 60 * 1000) /* Addresses for security related data in FLASH */ -#define BMC_REH_ADDR 0x17ffc004 -#define BMC_PROG_ADDR 0x17ffc000 -#define BMC_PROG_MAGIC 0x5746 +#define M10BMC_N3000_BMC_REH_ADDR 0x17ffc004 +#define M10BMC_N3000_BMC_PROG_ADDR 0x17ffc000 +#define M10BMC_N3000_BMC_PROG_MAGIC 0x5746 -#define SR_REH_ADDR 0x17ffd004 -#define SR_PROG_ADDR 0x17ffd000 -#define SR_PROG_MAGIC 0x5253 +#define M10BMC_N3000_SR_REH_ADDR 0x17ffd004 +#define M10BMC_N3000_SR_PROG_ADDR 0x17ffd000 +#define M10BMC_N3000_SR_PROG_MAGIC 0x5253 -#define PR_REH_ADDR 0x17ffe004 -#define PR_PROG_ADDR 0x17ffe000 -#define PR_PROG_MAGIC 0x5250 +#define M10BMC_N3000_PR_REH_ADDR 0x17ffe004 +#define M10BMC_N3000_PR_PROG_ADDR 0x17ffe000 +#define M10BMC_N3000_PR_PROG_MAGIC 0x5250 /* Address of 4KB inverted bit vector containing staging area FLASH count */ -#define STAGING_FLASH_COUNT 0x17ffb000 +#define M10BMC_N3000_STAGING_FLASH_COUNT 0x17ffb000 + +#define M10BMC_N6000_INDIRECT_BASE 0x400 + +#define M10BMC_N6000_SYS_BASE 0x0 +#define M10BMC_N6000_SYS_END 0xfff + +#define M10BMC_N6000_DOORBELL 0x1c0 +#define M10BMC_N6000_AUTH_RESULT 0x1c4 +#define AUTH_RESULT_RSU_STATUS GENMASK(23, 16) + +#define M10BMC_N6000_BUILD_VER 0x0 +#define NIOS2_N6000_FW_VERSION 0x4 +#define M10BMC_N6000_MAC_LOW 0x20 +#define M10BMC_N6000_MAC_HIGH (M10BMC_N6000_MAC_LOW + 4) + +/* Addresses for security related data in FLASH */ +#define M10BMC_N6000_BMC_REH_ADDR 0x7ffc004 +#define M10BMC_N6000_BMC_PROG_ADDR 0x7ffc000 +#define M10BMC_N6000_BMC_PROG_MAGIC 0x5746 + +#define M10BMC_N6000_SR_REH_ADDR 0x7ffd004 +#define M10BMC_N6000_SR_PROG_ADDR 0x7ffd000 +#define M10BMC_N6000_SR_PROG_MAGIC 0x5253 + +#define M10BMC_N6000_PR_REH_ADDR 0x7ffe004 +#define M10BMC_N6000_PR_PROG_ADDR 0x7ffe000 +#define M10BMC_N6000_PR_PROG_MAGIC 0x5250 + +#define M10BMC_N6000_STAGING_FLASH_COUNT 0x7ff5000 + +#define M10BMC_N6000_FLASH_MUX_CTRL 0x1d0 +#define M10BMC_N6000_FLASH_MUX_SELECTION GENMASK(2, 0) +#define M10BMC_N6000_FLASH_MUX_IDLE 0 +#define M10BMC_N6000_FLASH_MUX_NIOS 1 +#define M10BMC_N6000_FLASH_MUX_HOST 2 +#define M10BMC_N6000_FLASH_MUX_PFL 4 +#define get_flash_mux(mux) FIELD_GET(M10BMC_N6000_FLASH_MUX_SELECTION, mux) + +#define M10BMC_N6000_FLASH_NIOS_REQUEST BIT(4) +#define M10BMC_N6000_FLASH_HOST_REQUEST BIT(5) + +#define M10BMC_N6000_FLASH_CTRL 0x40 +#define M10BMC_N6000_FLASH_WR_MODE BIT(0) +#define M10BMC_N6000_FLASH_RD_MODE BIT(1) +#define M10BMC_N6000_FLASH_BUSY BIT(2) +#define M10BMC_N6000_FLASH_FIFO_SPACE GENMASK(13, 4) +#define M10BMC_N6000_FLASH_READ_COUNT GENMASK(25, 16) + +#define M10BMC_N6000_FLASH_ADDR 0x44 +#define M10BMC_N6000_FLASH_FIFO 0x800 +#define M10BMC_N6000_READ_BLOCK_SIZE 0x800 +#define M10BMC_N6000_FIFO_MAX_BYTES 0x800 +#define M10BMC_N6000_FIFO_WORD_SIZE 4 +#define M10BMC_N6000_FIFO_MAX_WORDS (M10BMC_N6000_FIFO_MAX_BYTES / \ + M10BMC_N6000_FIFO_WORD_SIZE) + +#define M10BMC_FLASH_INT_US 1 +#define M10BMC_FLASH_TIMEOUT_US 10000 + +/** + * struct m10bmc_csr_map - Intel MAX 10 BMC CSR register map + */ +struct m10bmc_csr_map { + unsigned int base; + unsigned int build_version; + unsigned int fw_version; + unsigned int mac_low; + unsigned int mac_high; + unsigned int doorbell; + unsigned int auth_result; + unsigned int bmc_prog_addr; + unsigned int bmc_reh_addr; + unsigned int bmc_magic; + unsigned int sr_prog_addr; + unsigned int sr_reh_addr; + unsigned int sr_magic; + unsigned int pr_prog_addr; + unsigned int pr_reh_addr; + unsigned int pr_magic; + unsigned int rsu_update_counter; +}; + +/** + * struct intel_m10bmc_platform_info - Intel MAX 10 BMC platform specific information + * @cells: MFD cells + * @n_cells: MFD cells ARRAY_SIZE() + * @csr_map: the mappings for register definition of MAX10 BMC + */ +struct intel_m10bmc_platform_info { + struct mfd_cell *cells; + int n_cells; + const struct m10bmc_csr_map *csr_map; +}; + +struct intel_m10bmc; + +/** + * struct intel_m10bmc_flash_bulk_ops - device specific operations for flash R/W + * @read: read a block of data from flash + * @write: write a block of data to flash + * @lock_write: locks flash access for erase+write + * @unlock_write: unlock flash access + * + * Write must be protected with @lock_write and @unlock_write. While the flash + * is locked, @read returns -EBUSY. + */ +struct intel_m10bmc_flash_bulk_ops { + int (*read)(struct intel_m10bmc *m10bmc, u8 *buf, u32 addr, u32 size); + int (*write)(struct intel_m10bmc *m10bmc, const u8 *buf, u32 offset, u32 size); + int (*lock_write)(struct intel_m10bmc *m10bmc); + void (*unlock_write)(struct intel_m10bmc *m10bmc); +}; /** * struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure * @dev: this device * @regmap: the regmap used to access registers by m10bmc itself + * @info: the platform information for MAX10 BMC + * @flash_bulk_ops: optional device specific operations for flash R/W */ struct intel_m10bmc { struct device *dev; struct regmap *regmap; + const struct intel_m10bmc_platform_info *info; + const struct intel_m10bmc_flash_bulk_ops *flash_bulk_ops; }; /* @@ -152,11 +270,22 @@ m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr, * The base of the system registers could be configured by HW developers, and * in HW SPEC, the base is not added to the addresses of the system registers. * - * This macro helps to simplify the accessing of the system registers. And if + * This function helps to simplify the accessing of the system registers. And if * the base is reconfigured in HW, SW developers could simply change the - * M10BMC_SYS_BASE accordingly. + * csr_map's base accordingly. + */ +static inline int m10bmc_sys_read(struct intel_m10bmc *m10bmc, unsigned int offset, + unsigned int *val) +{ + const struct m10bmc_csr_map *csr_map = m10bmc->info->csr_map; + + return m10bmc_raw_read(m10bmc, csr_map->base + offset, val); +} + +/* + * MAX10 BMC Core support */ -#define m10bmc_sys_read(m10bmc, offset, val) \ - m10bmc_raw_read(m10bmc, M10BMC_SYS_BASE + (offset), val) +int m10bmc_dev_init(struct intel_m10bmc *m10bmc, const struct intel_m10bmc_platform_info *info); +extern const struct attribute_group *m10bmc_dev_groups[]; #endif /* __MFD_INTEL_M10_BMC_H */ |