diff options
Diffstat (limited to 'include/dt-bindings/clock')
25 files changed, 1374 insertions, 36 deletions
diff --git a/include/dt-bindings/clock/ath79-clk.h b/include/dt-bindings/clock/ath79-clk.h new file mode 100644 index 000000000000..27359ad83904 --- /dev/null +++ b/include/dt-bindings/clock/ath79-clk.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2014, 2016 Antony Pavlov <antonynpavlov@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_ATH79_CLK_H +#define __DT_BINDINGS_ATH79_CLK_H + +#define ATH79_CLK_CPU 0 +#define ATH79_CLK_DDR 1 +#define ATH79_CLK_AHB 2 + +#define ATH79_CLK_END 3 + +#endif /* __DT_BINDINGS_ATH79_CLK_H */ diff --git a/include/dt-bindings/clock/axis,artpec6-clkctrl.h b/include/dt-bindings/clock/axis,artpec6-clkctrl.h new file mode 100644 index 000000000000..f9f04dccc996 --- /dev/null +++ b/include/dt-bindings/clock/axis,artpec6-clkctrl.h @@ -0,0 +1,38 @@ +/* + * ARTPEC-6 clock controller indexes + * + * Copyright 2016 Axis Comunications AB. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H +#define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H + +#define ARTPEC6_CLK_CPU 0 +#define ARTPEC6_CLK_CPU_PERIPH 1 +#define ARTPEC6_CLK_NAND_CLKA 2 +#define ARTPEC6_CLK_NAND_CLKB 3 +#define ARTPEC6_CLK_ETH_ACLK 4 +#define ARTPEC6_CLK_DMA_ACLK 5 +#define ARTPEC6_CLK_PTP_REF 6 +#define ARTPEC6_CLK_SD_PCLK 7 +#define ARTPEC6_CLK_SD_IMCLK 8 +#define ARTPEC6_CLK_I2S_HST 9 +#define ARTPEC6_CLK_I2S0_CLK 10 +#define ARTPEC6_CLK_I2S1_CLK 11 +#define ARTPEC6_CLK_UART_PCLK 12 +#define ARTPEC6_CLK_UART_REFCLK 13 +#define ARTPEC6_CLK_I2C 14 +#define ARTPEC6_CLK_SPI_PCLK 15 +#define ARTPEC6_CLK_SPI_SSPCLK 16 +#define ARTPEC6_CLK_SYS_TIMER 17 +#define ARTPEC6_CLK_FRACDIV_IN 18 +#define ARTPEC6_CLK_DBG_PCLK 19 + +/* This must be the highest clock index plus one. */ +#define ARTPEC6_CLK_NUMCLOCKS 20 + +#endif diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h index 61f1d20c2a67..360e00cefd35 100644 --- a/include/dt-bindings/clock/bcm2835.h +++ b/include/dt-bindings/clock/bcm2835.h @@ -44,5 +44,23 @@ #define BCM2835_CLOCK_EMMC 28 #define BCM2835_CLOCK_PERI_IMAGE 29 #define BCM2835_CLOCK_PWM 30 +#define BCM2835_CLOCK_PCM 31 -#define BCM2835_CLOCK_COUNT 31 +#define BCM2835_PLLA_DSI0 32 +#define BCM2835_PLLA_CCP2 33 +#define BCM2835_PLLD_DSI0 34 +#define BCM2835_PLLD_DSI1 35 + +#define BCM2835_CLOCK_AVEO 36 +#define BCM2835_CLOCK_DFT 37 +#define BCM2835_CLOCK_GP0 38 +#define BCM2835_CLOCK_GP1 39 +#define BCM2835_CLOCK_GP2 40 +#define BCM2835_CLOCK_SLIM 41 +#define BCM2835_CLOCK_SMI 42 +#define BCM2835_CLOCK_TEC 43 +#define BCM2835_CLOCK_DPI 44 +#define BCM2835_CLOCK_CAM0 45 +#define BCM2835_CLOCK_CAM1 46 +#define BCM2835_CLOCK_DSI0E 47 +#define BCM2835_CLOCK_DSI1E 48 diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h index 63d01c15d2b3..c796ff02ceeb 100644 --- a/include/dt-bindings/clock/exynos3250.h +++ b/include/dt-bindings/clock/exynos3250.h @@ -79,6 +79,8 @@ #define CLK_MOUT_CORE 58 #define CLK_MOUT_APLL 59 #define CLK_MOUT_ACLK_266_SUB 60 +#define CLK_MOUT_UART2 61 +#define CLK_MOUT_MMC2 62 /* Dividers */ #define CLK_DIV_GPL 64 @@ -127,6 +129,9 @@ #define CLK_DIV_CORE 107 #define CLK_DIV_HPM 108 #define CLK_DIV_COPY 109 +#define CLK_DIV_UART2 110 +#define CLK_DIV_MMC2_PRE 111 +#define CLK_DIV_MMC2 112 /* Gates */ #define CLK_ASYNC_G3D 128 @@ -223,6 +228,8 @@ #define CLK_BLOCK_MFC 219 #define CLK_BLOCK_CAM 220 #define CLK_SMIES 221 +#define CLK_UART2 222 +#define CLK_SDMMC2 223 /* Special clocks */ #define CLK_SCLK_JPEG 224 @@ -249,12 +256,14 @@ #define CLK_SCLK_SPI0 245 #define CLK_SCLK_UART1 246 #define CLK_SCLK_UART0 247 +#define CLK_SCLK_UART2 248 +#define CLK_SCLK_MMC2 249 /* * Total number of clocks of main CMU. * NOTE: Must be equal to last clock ID increased by one. */ -#define CLK_NR_CLKS 248 +#define CLK_NR_CLKS 250 /* * CMU DMC diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h index 9b180f032e2d..85b467b3a207 100644 --- a/include/dt-bindings/clock/exynos5410.h +++ b/include/dt-bindings/clock/exynos5410.h @@ -1,33 +1,65 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * Copyright (c) 2016 Krzysztof Kozlowski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants for Exynos5421 clock controller. +*/ + #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H #define _DT_BINDINGS_CLOCK_EXYNOS_5410_H /* core clocks */ -#define CLK_FIN_PLL 1 -#define CLK_FOUT_APLL 2 -#define CLK_FOUT_CPLL 3 -#define CLK_FOUT_MPLL 4 -#define CLK_FOUT_BPLL 5 -#define CLK_FOUT_KPLL 6 +#define CLK_FIN_PLL 1 +#define CLK_FOUT_APLL 2 +#define CLK_FOUT_CPLL 3 +#define CLK_FOUT_MPLL 4 +#define CLK_FOUT_BPLL 5 +#define CLK_FOUT_KPLL 6 /* gate for special clocks (sclk) */ -#define CLK_SCLK_UART0 128 -#define CLK_SCLK_UART1 129 -#define CLK_SCLK_UART2 130 -#define CLK_SCLK_UART3 131 -#define CLK_SCLK_MMC0 132 -#define CLK_SCLK_MMC1 133 -#define CLK_SCLK_MMC2 134 +#define CLK_SCLK_UART0 128 +#define CLK_SCLK_UART1 129 +#define CLK_SCLK_UART2 130 +#define CLK_SCLK_UART3 131 +#define CLK_SCLK_MMC0 132 +#define CLK_SCLK_MMC1 133 +#define CLK_SCLK_MMC2 134 +#define CLK_SCLK_USBD300 150 +#define CLK_SCLK_USBD301 151 +#define CLK_SCLK_USBPHY300 152 +#define CLK_SCLK_USBPHY301 153 +#define CLK_SCLK_PWM 155 /* gate clocks */ -#define CLK_UART0 257 -#define CLK_UART1 258 -#define CLK_UART2 259 -#define CLK_UART3 260 -#define CLK_MCT 315 -#define CLK_MMC0 351 -#define CLK_MMC1 352 -#define CLK_MMC2 353 +#define CLK_UART0 257 +#define CLK_UART1 258 +#define CLK_UART2 259 +#define CLK_I2C0 261 +#define CLK_I2C1 262 +#define CLK_I2C2 263 +#define CLK_I2C3 264 +#define CLK_USI0 265 +#define CLK_USI1 266 +#define CLK_USI2 267 +#define CLK_USI3 268 +#define CLK_UART3 260 +#define CLK_PWM 279 +#define CLK_MCT 315 +#define CLK_WDT 316 +#define CLK_RTC 317 +#define CLK_TMU 318 +#define CLK_MMC0 351 +#define CLK_MMC1 352 +#define CLK_MMC2 353 +#define CLK_USBH20 365 +#define CLK_USBD300 366 +#define CLK_USBD301 367 +#define CLK_SSS 471 -#define CLK_NR_CLKS 512 +#define CLK_NR_CLKS 512 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */ diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 7699ee9c16c0..17ab8394bec7 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -217,8 +217,30 @@ /* divider clocks */ #define CLK_DOUT_PIXEL 768 +#define CLK_DOUT_ACLK400_WCORE 769 +#define CLK_DOUT_ACLK400_ISP 770 +#define CLK_DOUT_ACLK400_MSCL 771 +#define CLK_DOUT_ACLK200 772 +#define CLK_DOUT_ACLK200_FSYS2 773 +#define CLK_DOUT_ACLK100_NOC 774 +#define CLK_DOUT_PCLK200_FSYS 775 +#define CLK_DOUT_ACLK200_FSYS 776 +#define CLK_DOUT_ACLK333_432_GSCL 777 +#define CLK_DOUT_ACLK333_432_ISP 778 +#define CLK_DOUT_ACLK66 779 +#define CLK_DOUT_ACLK333_432_ISP0 780 +#define CLK_DOUT_ACLK266 781 +#define CLK_DOUT_ACLK166 782 +#define CLK_DOUT_ACLK333 783 +#define CLK_DOUT_ACLK333_G2D 784 +#define CLK_DOUT_ACLK266_G2D 785 +#define CLK_DOUT_ACLK_G3D 786 +#define CLK_DOUT_ACLK300_JPEG 787 +#define CLK_DOUT_ACLK300_DISP1 788 +#define CLK_DOUT_ACLK300_GSCL 789 +#define CLK_DOUT_ACLK400_DISP1 790 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 769 +#define CLK_NR_CLKS 791 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 8e024fea26e7..4fa6bb2136e3 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -622,8 +622,9 @@ #define CLK_SCLK_UFSUNIPRO 112 #define CLK_SCLK_USBHOST30 113 #define CLK_SCLK_USBDRD30 114 +#define CLK_PCIE 115 -#define FSYS_NR_CLK 115 +#define FSYS_NR_CLK 116 /* CMU_G2D */ #define CLK_MUX_ACLK_G2D_266_USER 1 diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h new file mode 100644 index 000000000000..f889d80246cb --- /dev/null +++ b/include/dt-bindings/clock/gxbb-clkc.h @@ -0,0 +1,12 @@ +/* + * GXBB clock tree IDs + */ + +#ifndef __GXBB_CLKC_H +#define __GXBB_CLKC_H + +#define CLKID_CPUCLK 1 +#define CLKID_CLK81 12 +#define CLKID_ETH 36 + +#endif /* __GXBB_CLKC_H */ diff --git a/include/dt-bindings/clock/hi3519-clock.h b/include/dt-bindings/clock/hi3519-clock.h new file mode 100644 index 000000000000..14f4d2184e5a --- /dev/null +++ b/include/dt-bindings/clock/hi3519-clock.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __DTS_HI3519_CLOCK_H +#define __DTS_HI3519_CLOCK_H + +#define HI3519_FMC_CLK 1 +#define HI3519_SPI0_CLK 2 +#define HI3519_SPI1_CLK 3 +#define HI3519_SPI2_CLK 4 +#define HI3519_UART0_CLK 5 +#define HI3519_UART1_CLK 6 +#define HI3519_UART2_CLK 7 +#define HI3519_UART3_CLK 8 +#define HI3519_UART4_CLK 9 +#define HI3519_PWM_CLK 10 +#define HI3519_DMA_CLK 11 +#define HI3519_IR_CLK 12 +#define HI3519_ETH_PHY_CLK 13 +#define HI3519_ETH_MAC_CLK 14 +#define HI3519_ETH_MACIF_CLK 15 +#define HI3519_USB2_BUS_CLK 16 +#define HI3519_USB2_PORT_CLK 17 +#define HI3519_USB3_CLK 18 + +#endif /* __DTS_HI3519_CLOCK_H */ diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h index 70ee3833a7a0..6b03c84f4278 100644 --- a/include/dt-bindings/clock/hi6220-clock.h +++ b/include/dt-bindings/clock/hi6220-clock.h @@ -55,8 +55,9 @@ #define HI6220_TIMER7_PCLK 34 #define HI6220_TIMER8_PCLK 35 #define HI6220_UART0_PCLK 36 - -#define HI6220_AO_NR_CLKS 37 +#define HI6220_RTC0_PCLK 37 +#define HI6220_RTC1_PCLK 38 +#define HI6220_AO_NR_CLKS 39 /* clk in Hi6220 systrl */ /* gate clock */ diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h index edca8985c50e..1183347c383f 100644 --- a/include/dt-bindings/clock/imx7d-clock.h +++ b/include/dt-bindings/clock/imx7d-clock.h @@ -448,5 +448,6 @@ #define IMX7D_PLL_DRAM_TEST_DIV 435 #define IMX7D_ADC_ROOT_CLK 436 #define IMX7D_CLK_ARM 437 -#define IMX7D_CLK_END 438 +#define IMX7D_CKIL 438 +#define IMX7D_CLK_END 439 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ diff --git a/include/dt-bindings/clock/lpc32xx-clock.h b/include/dt-bindings/clock/lpc32xx-clock.h index d41b6fea1450..e624d3a52798 100644 --- a/include/dt-bindings/clock/lpc32xx-clock.h +++ b/include/dt-bindings/clock/lpc32xx-clock.h @@ -48,6 +48,7 @@ #define LPC32XX_CLK_PWM2 33 #define LPC32XX_CLK_ADC 34 #define LPC32XX_CLK_HCLK_PLL 35 +#define LPC32XX_CLK_PERIPH 36 /* LPC32XX USB clocks */ #define LPC32XX_USB_CLK_I2C 1 diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index bd2720d58e0c..595a58d0969a 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -19,7 +19,9 @@ #define CLKID_MALI 11 #define CLKID_CPUCLK 12 #define CLKID_ZERO 13 +#define CLKID_MPEG_SEL 14 +#define CLKID_MPEG_DIV 15 -#define CLK_NR_CLKS (CLKID_ZERO + 1) +#define CLK_NR_CLKS (CLKID_MPEG_DIV + 1) #endif /* __MESON8B_CLKC_H */ diff --git a/include/dt-bindings/clock/microchip,pic32-clock.h b/include/dt-bindings/clock/microchip,pic32-clock.h new file mode 100644 index 000000000000..184647a6a8de --- /dev/null +++ b/include/dt-bindings/clock/microchip,pic32-clock.h @@ -0,0 +1,42 @@ +/* + * Purna Chandra Mandal,<purna.mandal@microchip.com> + * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ +#define _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ + +/* clock output indices */ +#define POSCCLK 0 +#define FRCCLK 1 +#define BFRCCLK 2 +#define LPRCCLK 3 +#define SOSCCLK 4 +#define FRCDIVCLK 5 +#define PLLCLK 6 +#define SCLK 7 +#define PB1CLK 8 +#define PB2CLK 9 +#define PB3CLK 10 +#define PB4CLK 11 +#define PB5CLK 12 +#define PB6CLK 13 +#define PB7CLK 14 +#define REF1CLK 15 +#define REF2CLK 16 +#define REF3CLK 17 +#define REF4CLK 18 +#define REF5CLK 19 +#define UPLLCLK 20 +#define MAXCLKS 21 + +#endif /* _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ */ diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h index 7956ba1bc974..6094bf7e50ab 100644 --- a/include/dt-bindings/clock/mt8173-clk.h +++ b/include/dt-bindings/clock/mt8173-clk.h @@ -176,7 +176,8 @@ #define CLK_APMIXED_LVDSPLL 13 #define CLK_APMIXED_MSDCPLL2 14 #define CLK_APMIXED_REF2USB_TX 15 -#define CLK_APMIXED_NR_CLK 16 +#define CLK_APMIXED_HDMI_REF 16 +#define CLK_APMIXED_NR_CLK 17 /* INFRA_SYS */ diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h index 7b1ad8922eec..fa5e8da809f2 100644 --- a/include/dt-bindings/clock/r8a7790-clock.h +++ b/include/dt-bindings/clock/r8a7790-clock.h @@ -66,6 +66,7 @@ #define R8A7790_CLK_IIC2 0 #define R8A7790_CLK_TPU0 4 #define R8A7790_CLK_MMCIF1 5 +#define R8A7790_CLK_SCIF2 10 #define R8A7790_CLK_SDHI3 11 #define R8A7790_CLK_SDHI2 12 #define R8A7790_CLK_SDHI1 13 diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h new file mode 100644 index 000000000000..9a8b392ceb00 --- /dev/null +++ b/include/dt-bindings/clock/r8a7792-clock.h @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__ +#define __DT_BINDINGS_CLOCK_R8A7792_H__ + +/* CPG */ +#define R8A7792_CLK_MAIN 0 +#define R8A7792_CLK_PLL0 1 +#define R8A7792_CLK_PLL1 2 +#define R8A7792_CLK_PLL3 3 +#define R8A7792_CLK_LB 4 +#define R8A7792_CLK_QSPI 5 +#define R8A7792_CLK_Z 6 + +/* MSTP0 */ +#define R8A7792_CLK_MSIOF0 0 + +/* MSTP1 */ +#define R8A7792_CLK_JPU 6 +#define R8A7792_CLK_TMU1 11 +#define R8A7792_CLK_TMU3 21 +#define R8A7792_CLK_TMU2 22 +#define R8A7792_CLK_CMT0 24 +#define R8A7792_CLK_TMU0 25 +#define R8A7792_CLK_VSP1DU1 27 +#define R8A7792_CLK_VSP1DU0 28 +#define R8A7792_CLK_VSP1_SY 31 + +/* MSTP2 */ +#define R8A7792_CLK_MSIOF1 8 +#define R8A7792_CLK_SYS_DMAC1 18 +#define R8A7792_CLK_SYS_DMAC0 19 + +/* MSTP3 */ +#define R8A7792_CLK_TPU0 4 +#define R8A7792_CLK_SDHI0 14 +#define R8A7792_CLK_CMT1 29 + +/* MSTP4 */ +#define R8A7792_CLK_IRQC 7 + +/* MSTP5 */ +#define R8A7792_CLK_AUDIO_DMAC0 2 +#define R8A7792_CLK_THERMAL 22 +#define R8A7792_CLK_PWM 23 + +/* MSTP7 */ +#define R8A7792_CLK_HSCIF1 16 +#define R8A7792_CLK_HSCIF0 17 +#define R8A7792_CLK_SCIF3 18 +#define R8A7792_CLK_SCIF2 19 +#define R8A7792_CLK_SCIF1 20 +#define R8A7792_CLK_SCIF0 21 +#define R8A7792_CLK_DU1 23 +#define R8A7792_CLK_DU0 24 + +/* MSTP8 */ +#define R8A7792_CLK_VIN5 4 +#define R8A7792_CLK_VIN4 5 +#define R8A7792_CLK_VIN3 8 +#define R8A7792_CLK_VIN2 9 +#define R8A7792_CLK_VIN1 10 +#define R8A7792_CLK_VIN0 11 +#define R8A7792_CLK_ETHERAVB 12 + +/* MSTP9 */ +#define R8A7792_CLK_GPIO7 4 +#define R8A7792_CLK_GPIO6 5 +#define R8A7792_CLK_GPIO5 7 +#define R8A7792_CLK_GPIO4 8 +#define R8A7792_CLK_GPIO3 9 +#define R8A7792_CLK_GPIO2 10 +#define R8A7792_CLK_GPIO1 11 +#define R8A7792_CLK_GPIO0 12 +#define R8A7792_CLK_GPIO11 13 +#define R8A7792_CLK_GPIO10 14 +#define R8A7792_CLK_CAN1 15 +#define R8A7792_CLK_CAN0 16 +#define R8A7792_CLK_QSPI_MOD 17 +#define R8A7792_CLK_GPIO9 19 +#define R8A7792_CLK_GPIO8 21 +#define R8A7792_CLK_I2C5 25 +#define R8A7792_CLK_IICDVFS 26 +#define R8A7792_CLK_I2C4 27 +#define R8A7792_CLK_I2C3 28 +#define R8A7792_CLK_I2C2 29 +#define R8A7792_CLK_I2C1 30 +#define R8A7792_CLK_I2C0 31 + +/* MSTP10 */ +#define R8A7792_CLK_SSI_ALL 5 +#define R8A7792_CLK_SSI4 11 +#define R8A7792_CLK_SSI3 12 + +#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */ diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index f843de6bf377..a3491ba2f6ec 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -21,6 +21,7 @@ #define R8A7794_CLK_SDH 6 #define R8A7794_CLK_SD0 7 #define R8A7794_CLK_Z 8 +#define R8A7794_CLK_RCAN 9 /* MSTP0 */ #define R8A7794_CLK_MSIOF0 0 @@ -56,6 +57,8 @@ #define R8A7794_CLK_SDHI1 12 #define R8A7794_CLK_SDHI0 14 #define R8A7794_CLK_MMCIF0 15 +#define R8A7794_CLK_IIC0 18 +#define R8A7794_CLK_IIC1 23 #define R8A7794_CLK_CMT1 29 #define R8A7794_CLK_USBDMAC0 30 #define R8A7794_CLK_USBDMAC1 31 @@ -64,7 +67,6 @@ #define R8A7794_CLK_IRQC 7 /* MSTP5 */ -#define R8A7794_CLK_THERMAL 22 #define R8A7794_CLK_PWM 23 /* MSTP7 */ @@ -95,6 +97,8 @@ #define R8A7794_CLK_GPIO2 10 #define R8A7794_CLK_GPIO1 11 #define R8A7794_CLK_GPIO0 12 +#define R8A7794_CLK_RCAN1 15 +#define R8A7794_CLK_RCAN0 16 #define R8A7794_CLK_QSPI_MOD 17 #define R8A7794_CLK_I2C5 25 #define R8A7794_CLK_I2C4 27 diff --git a/include/dt-bindings/clock/r8a7796-cpg-mssr.h b/include/dt-bindings/clock/r8a7796-cpg-mssr.h new file mode 100644 index 000000000000..1e5942695f0d --- /dev/null +++ b/include/dt-bindings/clock/r8a7796-cpg-mssr.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2016 Renesas Electronics Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a7796 CPG Core Clocks */ +#define R8A7796_CLK_Z 0 +#define R8A7796_CLK_Z2 1 +#define R8A7796_CLK_ZR 2 +#define R8A7796_CLK_ZG 3 +#define R8A7796_CLK_ZTR 4 +#define R8A7796_CLK_ZTRD2 5 +#define R8A7796_CLK_ZT 6 +#define R8A7796_CLK_ZX 7 +#define R8A7796_CLK_S0D1 8 +#define R8A7796_CLK_S0D2 9 +#define R8A7796_CLK_S0D3 10 +#define R8A7796_CLK_S0D4 11 +#define R8A7796_CLK_S0D6 12 +#define R8A7796_CLK_S0D8 13 +#define R8A7796_CLK_S0D12 14 +#define R8A7796_CLK_S1D1 15 +#define R8A7796_CLK_S1D2 16 +#define R8A7796_CLK_S1D4 17 +#define R8A7796_CLK_S2D1 18 +#define R8A7796_CLK_S2D2 19 +#define R8A7796_CLK_S2D4 20 +#define R8A7796_CLK_S3D1 21 +#define R8A7796_CLK_S3D2 22 +#define R8A7796_CLK_S3D4 23 +#define R8A7796_CLK_LB 24 +#define R8A7796_CLK_CL 25 +#define R8A7796_CLK_ZB3 26 +#define R8A7796_CLK_ZB3D2 27 +#define R8A7796_CLK_ZB3D4 28 +#define R8A7796_CLK_CR 29 +#define R8A7796_CLK_CRD2 30 +#define R8A7796_CLK_SD0H 31 +#define R8A7796_CLK_SD0 32 +#define R8A7796_CLK_SD1H 33 +#define R8A7796_CLK_SD1 34 +#define R8A7796_CLK_SD2H 35 +#define R8A7796_CLK_SD2 36 +#define R8A7796_CLK_SD3H 37 +#define R8A7796_CLK_SD3 38 +#define R8A7796_CLK_SSP2 39 +#define R8A7796_CLK_SSP1 40 +#define R8A7796_CLK_SSPRS 41 +#define R8A7796_CLK_RPC 42 +#define R8A7796_CLK_RPCD2 43 +#define R8A7796_CLK_MSO 44 +#define R8A7796_CLK_CANFD 45 +#define R8A7796_CLK_HDMI 46 +#define R8A7796_CLK_CSI0 47 +#define R8A7796_CLK_CSIREF 48 +#define R8A7796_CLK_CP 49 +#define R8A7796_CLK_CPEX 50 +#define R8A7796_CLK_R 51 +#define R8A7796_CLK_OSC 52 + +#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index 5d43ed9b05ad..b27e2b1a65e3 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -52,6 +52,15 @@ #define SCLK_EMMC_SAMPLE 121 #define SCLK_VOP 122 #define SCLK_HDMI_HDCP 123 +#define SCLK_MAC_SRC 124 +#define SCLK_MAC_EXTCLK 125 +#define SCLK_MAC 126 +#define SCLK_MAC_REFOUT 127 +#define SCLK_MAC_REF 128 +#define SCLK_MAC_RX 129 +#define SCLK_MAC_TX 130 +#define SCLK_MAC_PHY 131 +#define SCLK_MAC_OUT 132 /* dclk gates */ #define DCLK_VOP 190 @@ -61,6 +70,7 @@ #define ACLK_DMAC 194 #define ACLK_PERI 210 #define ACLK_VOP 211 +#define ACLK_GMAC 212 /* pclk gates */ #define PCLK_GPIO0 320 @@ -82,8 +92,13 @@ #define PCLK_PERI 363 #define PCLK_HDMI_CTRL 364 #define PCLK_HDMI_PHY 365 +#define PCLK_GMAC 367 /* hclk gates */ +#define HCLK_I2S0_8CH 442 +#define HCLK_I2S1_8CH 443 +#define HCLK_I2S2_2CH 444 +#define HCLK_SPDIF_8CH 445 #define HCLK_VOP 452 #define HCLK_NANDC 453 #define HCLK_SDMMC 456 diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h new file mode 100644 index 000000000000..50a44cffb070 --- /dev/null +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -0,0 +1,755 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng <zhengxing@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H + +/* core clocks */ +#define PLL_APLLL 1 +#define PLL_APLLB 2 +#define PLL_DPLL 3 +#define PLL_CPLL 4 +#define PLL_GPLL 5 +#define PLL_NPLL 6 +#define PLL_VPLL 7 +#define ARMCLKL 8 +#define ARMCLKB 9 + +/* sclk gates (special clocks) */ +#define SCLK_I2C1 65 +#define SCLK_I2C2 66 +#define SCLK_I2C3 67 +#define SCLK_I2C5 68 +#define SCLK_I2C6 69 +#define SCLK_I2C7 70 +#define SCLK_SPI0 71 +#define SCLK_SPI1 72 +#define SCLK_SPI2 73 +#define SCLK_SPI4 74 +#define SCLK_SPI5 75 +#define SCLK_SDMMC 76 +#define SCLK_SDIO 77 +#define SCLK_EMMC 78 +#define SCLK_TSADC 79 +#define SCLK_SARADC 80 +#define SCLK_UART0 81 +#define SCLK_UART1 82 +#define SCLK_UART2 83 +#define SCLK_UART3 84 +#define SCLK_SPDIF_8CH 85 +#define SCLK_I2S0_8CH 86 +#define SCLK_I2S1_8CH 87 +#define SCLK_I2S2_8CH 88 +#define SCLK_I2S_8CH_OUT 89 +#define SCLK_TIMER00 90 +#define SCLK_TIMER01 91 +#define SCLK_TIMER02 92 +#define SCLK_TIMER03 93 +#define SCLK_TIMER04 94 +#define SCLK_TIMER05 95 +#define SCLK_TIMER06 96 +#define SCLK_TIMER07 97 +#define SCLK_TIMER08 98 +#define SCLK_TIMER09 99 +#define SCLK_TIMER10 100 +#define SCLK_TIMER11 101 +#define SCLK_MACREF 102 +#define SCLK_MAC_RX 103 +#define SCLK_MAC_TX 104 +#define SCLK_MAC 105 +#define SCLK_MACREF_OUT 106 +#define SCLK_VOP0_PWM 107 +#define SCLK_VOP1_PWM 108 +#define SCLK_RGA_CORE 109 +#define SCLK_ISP0 110 +#define SCLK_ISP1 111 +#define SCLK_HDMI_CEC 112 +#define SCLK_HDMI_SFR 113 +#define SCLK_DP_CORE 114 +#define SCLK_PVTM_CORE_L 115 +#define SCLK_PVTM_CORE_B 116 +#define SCLK_PVTM_GPU 117 +#define SCLK_PVTM_DDR 118 +#define SCLK_MIPIDPHY_REF 119 +#define SCLK_MIPIDPHY_CFG 120 +#define SCLK_HSICPHY 121 +#define SCLK_USBPHY480M 122 +#define SCLK_USB2PHY0_REF 123 +#define SCLK_USB2PHY1_REF 124 +#define SCLK_UPHY0_TCPDPHY_REF 125 +#define SCLK_UPHY0_TCPDCORE 126 +#define SCLK_UPHY1_TCPDPHY_REF 127 +#define SCLK_UPHY1_TCPDCORE 128 +#define SCLK_USB3OTG0_REF 129 +#define SCLK_USB3OTG1_REF 130 +#define SCLK_USB3OTG0_SUSPEND 131 +#define SCLK_USB3OTG1_SUSPEND 132 +#define SCLK_CRYPTO0 133 +#define SCLK_CRYPTO1 134 +#define SCLK_CCI_TRACE 135 +#define SCLK_CS 136 +#define SCLK_CIF_OUT 137 +#define SCLK_PCIEPHY_REF 138 +#define SCLK_PCIE_CORE 139 +#define SCLK_M0_PERILP 140 +#define SCLK_M0_PERILP_DEC 141 +#define SCLK_CM0S 142 +#define SCLK_DBG_NOC 143 +#define SCLK_DBG_PD_CORE_B 144 +#define SCLK_DBG_PD_CORE_L 145 +#define SCLK_DFIMON0_TIMER 146 +#define SCLK_DFIMON1_TIMER 147 +#define SCLK_INTMEM0 148 +#define SCLK_INTMEM1 149 +#define SCLK_INTMEM2 150 +#define SCLK_INTMEM3 151 +#define SCLK_INTMEM4 152 +#define SCLK_INTMEM5 153 +#define SCLK_SDMMC_DRV 154 +#define SCLK_SDMMC_SAMPLE 155 +#define SCLK_SDIO_DRV 156 +#define SCLK_SDIO_SAMPLE 157 +#define SCLK_VDU_CORE 158 +#define SCLK_VDU_CA 159 +#define SCLK_PCIE_PM 160 +#define SCLK_SPDIF_REC_DPTX 161 +#define SCLK_DPHY_PLL 162 +#define SCLK_DPHY_TX0_CFG 163 +#define SCLK_DPHY_TX1RX1_CFG 164 +#define SCLK_DPHY_RX0_CFG 165 +#define SCLK_RMII_SRC 166 +#define SCLK_PCIEPHY_REF100M 167 + +#define DCLK_VOP0 180 +#define DCLK_VOP1 181 +#define DCLK_VOP0_DIV 182 +#define DCLK_VOP1_DIV 183 +#define DCLK_M0_PERILP 184 + +#define FCLK_CM0S 190 + +/* aclk gates */ +#define ACLK_PERIHP 192 +#define ACLK_PERIHP_NOC 193 +#define ACLK_PERILP0 194 +#define ACLK_PERILP0_NOC 195 +#define ACLK_PERF_PCIE 196 +#define ACLK_PCIE 197 +#define ACLK_INTMEM 198 +#define ACLK_TZMA 199 +#define ACLK_DCF 200 +#define ACLK_CCI 201 +#define ACLK_CCI_NOC0 202 +#define ACLK_CCI_NOC1 203 +#define ACLK_CCI_GRF 204 +#define ACLK_CENTER 205 +#define ACLK_CENTER_MAIN_NOC 206 +#define ACLK_CENTER_PERI_NOC 207 +#define ACLK_GPU 208 +#define ACLK_PERF_GPU 209 +#define ACLK_GPU_GRF 210 +#define ACLK_DMAC0_PERILP 211 +#define ACLK_DMAC1_PERILP 212 +#define ACLK_GMAC 213 +#define ACLK_GMAC_NOC 214 +#define ACLK_PERF_GMAC 215 +#define ACLK_VOP0_NOC 216 +#define ACLK_VOP0 217 +#define ACLK_VOP1_NOC 218 +#define ACLK_VOP1 219 +#define ACLK_RGA 220 +#define ACLK_RGA_NOC 221 +#define ACLK_HDCP 222 +#define ACLK_HDCP_NOC 223 +#define ACLK_HDCP22 224 +#define ACLK_IEP 225 +#define ACLK_IEP_NOC 226 +#define ACLK_VIO 227 +#define ACLK_VIO_NOC 228 +#define ACLK_ISP0 229 +#define ACLK_ISP1 230 +#define ACLK_ISP0_NOC 231 +#define ACLK_ISP1_NOC 232 +#define ACLK_ISP0_WRAPPER 233 +#define ACLK_ISP1_WRAPPER 234 +#define ACLK_VCODEC 235 +#define ACLK_VCODEC_NOC 236 +#define ACLK_VDU 237 +#define ACLK_VDU_NOC 238 +#define ACLK_PERI 239 +#define ACLK_EMMC 240 +#define ACLK_EMMC_CORE 241 +#define ACLK_EMMC_NOC 242 +#define ACLK_EMMC_GRF 243 +#define ACLK_USB3 244 +#define ACLK_USB3_NOC 245 +#define ACLK_USB3OTG0 246 +#define ACLK_USB3OTG1 247 +#define ACLK_USB3_RKSOC_AXI_PERF 248 +#define ACLK_USB3_GRF 249 +#define ACLK_GIC 250 +#define ACLK_GIC_NOC 251 +#define ACLK_GIC_ADB400_CORE_L_2_GIC 252 +#define ACLK_GIC_ADB400_CORE_B_2_GIC 253 +#define ACLK_GIC_ADB400_GIC_2_CORE_L 254 +#define ACLK_GIC_ADB400_GIC_2_CORE_B 255 +#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 +#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 +#define ACLK_ADB400M_PD_CORE_L 258 +#define ACLK_ADB400M_PD_CORE_B 259 +#define ACLK_PERF_CORE_L 260 +#define ACLK_PERF_CORE_B 261 +#define ACLK_GIC_PRE 262 +#define ACLK_VOP0_PRE 263 +#define ACLK_VOP1_PRE 264 + +/* pclk gates */ +#define PCLK_PERIHP 320 +#define PCLK_PERIHP_NOC 321 +#define PCLK_PERILP0 322 +#define PCLK_PERILP1 323 +#define PCLK_PERILP1_NOC 324 +#define PCLK_PERILP_SGRF 325 +#define PCLK_PERIHP_GRF 326 +#define PCLK_PCIE 327 +#define PCLK_SGRF 328 +#define PCLK_INTR_ARB 329 +#define PCLK_CENTER_MAIN_NOC 330 +#define PCLK_CIC 331 +#define PCLK_COREDBG_B 332 +#define PCLK_COREDBG_L 333 +#define PCLK_DBG_CXCS_PD_CORE_B 334 +#define PCLK_DCF 335 +#define PCLK_GPIO2 336 +#define PCLK_GPIO3 337 +#define PCLK_GPIO4 338 +#define PCLK_GRF 339 +#define PCLK_HSICPHY 340 +#define PCLK_I2C1 341 +#define PCLK_I2C2 342 +#define PCLK_I2C3 343 +#define PCLK_I2C5 344 +#define PCLK_I2C6 345 +#define PCLK_I2C7 346 +#define PCLK_SPI0 347 +#define PCLK_SPI1 348 +#define PCLK_SPI2 349 +#define PCLK_SPI4 350 +#define PCLK_SPI5 351 +#define PCLK_UART0 352 +#define PCLK_UART1 353 +#define PCLK_UART2 354 +#define PCLK_UART3 355 +#define PCLK_TSADC 356 +#define PCLK_SARADC 357 +#define PCLK_GMAC 358 +#define PCLK_GMAC_NOC 359 +#define PCLK_TIMER0 360 +#define PCLK_TIMER1 361 +#define PCLK_EDP 362 +#define PCLK_EDP_NOC 363 +#define PCLK_EDP_CTRL 364 +#define PCLK_VIO 365 +#define PCLK_VIO_NOC 366 +#define PCLK_VIO_GRF 367 +#define PCLK_MIPI_DSI0 368 +#define PCLK_MIPI_DSI1 369 +#define PCLK_HDCP 370 +#define PCLK_HDCP_NOC 371 +#define PCLK_HDMI_CTRL 372 +#define PCLK_DP_CTRL 373 +#define PCLK_HDCP22 374 +#define PCLK_GASKET 375 +#define PCLK_DDR 376 +#define PCLK_DDR_MON 377 +#define PCLK_DDR_SGRF 378 +#define PCLK_ISP1_WRAPPER 379 +#define PCLK_WDT 380 +#define PCLK_EFUSE1024NS 381 +#define PCLK_EFUSE1024S 382 +#define PCLK_PMU_INTR_ARB 383 +#define PCLK_MAILBOX0 384 +#define PCLK_USBPHY_MUX_G 385 +#define PCLK_UPHY0_TCPHY_G 386 +#define PCLK_UPHY0_TCPD_G 387 +#define PCLK_UPHY1_TCPHY_G 388 +#define PCLK_UPHY1_TCPD_G 389 +#define PCLK_ALIVE 390 + +/* hclk gates */ +#define HCLK_PERIHP 448 +#define HCLK_PERILP0 449 +#define HCLK_PERILP1 450 +#define HCLK_PERILP0_NOC 451 +#define HCLK_PERILP1_NOC 452 +#define HCLK_M0_PERILP 453 +#define HCLK_M0_PERILP_NOC 454 +#define HCLK_AHB1TOM 455 +#define HCLK_HOST0 456 +#define HCLK_HOST0_ARB 457 +#define HCLK_HOST1 458 +#define HCLK_HOST1_ARB 459 +#define HCLK_HSIC 460 +#define HCLK_SD 461 +#define HCLK_SDMMC 462 +#define HCLK_SDMMC_NOC 463 +#define HCLK_M_CRYPTO0 464 +#define HCLK_M_CRYPTO1 465 +#define HCLK_S_CRYPTO0 466 +#define HCLK_S_CRYPTO1 467 +#define HCLK_I2S0_8CH 468 +#define HCLK_I2S1_8CH 469 +#define HCLK_I2S2_8CH 470 +#define HCLK_SPDIF 471 +#define HCLK_VOP0_NOC 472 +#define HCLK_VOP0 473 +#define HCLK_VOP1_NOC 474 +#define HCLK_VOP1 475 +#define HCLK_ROM 476 +#define HCLK_IEP 477 +#define HCLK_IEP_NOC 478 +#define HCLK_ISP0 479 +#define HCLK_ISP1 480 +#define HCLK_ISP0_NOC 481 +#define HCLK_ISP1_NOC 482 +#define HCLK_ISP0_WRAPPER 483 +#define HCLK_ISP1_WRAPPER 484 +#define HCLK_RGA 485 +#define HCLK_RGA_NOC 486 +#define HCLK_HDCP 487 +#define HCLK_HDCP_NOC 488 +#define HCLK_HDCP22 489 +#define HCLK_VCODEC 490 +#define HCLK_VCODEC_NOC 491 +#define HCLK_VDU 492 +#define HCLK_VDU_NOC 493 +#define HCLK_SDIO 494 +#define HCLK_SDIO_NOC 495 +#define HCLK_SDIOAUDIO_NOC 496 + +#define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) + +/* pmu-clocks indices */ + +#define PLL_PPLL 1 + +#define SCLK_32K_SUSPEND_PMU 2 +#define SCLK_SPI3_PMU 3 +#define SCLK_TIMER12_PMU 4 +#define SCLK_TIMER13_PMU 5 +#define SCLK_UART4_PMU 6 +#define SCLK_PVTM_PMU 7 +#define SCLK_WIFI_PMU 8 +#define SCLK_I2C0_PMU 9 +#define SCLK_I2C4_PMU 10 +#define SCLK_I2C8_PMU 11 + +#define PCLK_SRC_PMU 19 +#define PCLK_PMU 20 +#define PCLK_PMUGRF_PMU 21 +#define PCLK_INTMEM1_PMU 22 +#define PCLK_GPIO0_PMU 23 +#define PCLK_GPIO1_PMU 24 +#define PCLK_SGRF_PMU 25 +#define PCLK_NOC_PMU 26 +#define PCLK_I2C0_PMU 27 +#define PCLK_I2C4_PMU 28 +#define PCLK_I2C8_PMU 29 +#define PCLK_RKPWM_PMU 30 +#define PCLK_SPI3_PMU 31 +#define PCLK_TIMER_PMU 32 +#define PCLK_MAILBOX_PMU 33 +#define PCLK_UART4_PMU 34 +#define PCLK_WDT_M0_PMU 35 + +#define FCLK_CM0S_SRC_PMU 44 +#define FCLK_CM0S_PMU 45 +#define SCLK_CM0S_PMU 46 +#define HCLK_CM0S_PMU 47 +#define DCLK_CM0S_PMU 48 +#define PCLK_INTR_ARB_PMU 49 +#define HCLK_NOC_PMU 50 + +#define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1) + +/* soft-reset indices */ + +/* cru_softrst_con0 */ +#define SRST_CORE_L0 0 +#define SRST_CORE_B0 1 +#define SRST_CORE_PO_L0 2 +#define SRST_CORE_PO_B0 3 +#define SRST_L2_L 4 +#define SRST_L2_B 5 +#define SRST_ADB_L 6 +#define SRST_ADB_B 7 +#define SRST_A_CCI 8 +#define SRST_A_CCIM0_NOC 9 +#define SRST_A_CCIM1_NOC 10 +#define SRST_DBG_NOC 11 + +/* cru_softrst_con1 */ +#define SRST_CORE_L0_T 16 +#define SRST_CORE_L1 17 +#define SRST_CORE_L2 18 +#define SRST_CORE_L3 19 +#define SRST_CORE_PO_L0_T 20 +#define SRST_CORE_PO_L1 21 +#define SRST_CORE_PO_L2 22 +#define SRST_CORE_PO_L3 23 +#define SRST_A_ADB400_GIC2COREL 24 +#define SRST_A_ADB400_COREL2GIC 25 +#define SRST_P_DBG_L 26 +#define SRST_L2_L_T 28 +#define SRST_ADB_L_T 29 +#define SRST_A_RKPERF_L 30 +#define SRST_PVTM_CORE_L 31 + +/* cru_softrst_con2 */ +#define SRST_CORE_B0_T 32 +#define SRST_CORE_B1 33 +#define SRST_CORE_PO_B0_T 36 +#define SRST_CORE_PO_B1 37 +#define SRST_A_ADB400_GIC2COREB 40 +#define SRST_A_ADB400_COREB2GIC 41 +#define SRST_P_DBG_B 42 +#define SRST_L2_B_T 43 +#define SRST_ADB_B_T 45 +#define SRST_A_RKPERF_B 46 +#define SRST_PVTM_CORE_B 47 + +/* cru_softrst_con3 */ +#define SRST_A_CCI_T 50 +#define SRST_A_CCIM0_NOC_T 51 +#define SRST_A_CCIM1_NOC_T 52 +#define SRST_A_ADB400M_PD_CORE_B_T 53 +#define SRST_A_ADB400M_PD_CORE_L_T 54 +#define SRST_DBG_NOC_T 55 +#define SRST_DBG_CXCS 56 +#define SRST_CCI_TRACE 57 +#define SRST_P_CCI_GRF 58 + +/* cru_softrst_con4 */ +#define SRST_A_CENTER_MAIN_NOC 64 +#define SRST_A_CENTER_PERI_NOC 65 +#define SRST_P_CENTER_MAIN 66 +#define SRST_P_DDRMON 67 +#define SRST_P_CIC 68 +#define SRST_P_CENTER_SGRF 69 +#define SRST_DDR0_MSCH 70 +#define SRST_DDRCFG0_MSCH 71 +#define SRST_DDR0 72 +#define SRST_DDRPHY0 73 +#define SRST_DDR1_MSCH 74 +#define SRST_DDRCFG1_MSCH 75 +#define SRST_DDR1 76 +#define SRST_DDRPHY1 77 +#define SRST_DDR_CIC 78 +#define SRST_PVTM_DDR 79 + +/* cru_softrst_con5 */ +#define SRST_A_VCODEC_NOC 80 +#define SRST_A_VCODEC 81 +#define SRST_H_VCODEC_NOC 82 +#define SRST_H_VCODEC 83 +#define SRST_A_VDU_NOC 88 +#define SRST_A_VDU 89 +#define SRST_H_VDU_NOC 90 +#define SRST_H_VDU 91 +#define SRST_VDU_CORE 92 +#define SRST_VDU_CA 93 + +/* cru_softrst_con6 */ +#define SRST_A_IEP_NOC 96 +#define SRST_A_VOP_IEP 97 +#define SRST_A_IEP 98 +#define SRST_H_IEP_NOC 99 +#define SRST_H_IEP 100 +#define SRST_A_RGA_NOC 102 +#define SRST_A_RGA 103 +#define SRST_H_RGA_NOC 104 +#define SRST_H_RGA 105 +#define SRST_RGA_CORE 106 +#define SRST_EMMC_NOC 108 +#define SRST_EMMC 109 +#define SRST_EMMC_GRF 110 + +/* cru_softrst_con7 */ +#define SRST_A_PERIHP_NOC 112 +#define SRST_P_PERIHP_GRF 113 +#define SRST_H_PERIHP_NOC 114 +#define SRST_USBHOST0 115 +#define SRST_HOSTC0_AUX 116 +#define SRST_HOST0_ARB 117 +#define SRST_USBHOST1 118 +#define SRST_HOSTC1_AUX 119 +#define SRST_HOST1_ARB 120 +#define SRST_SDIO0 121 +#define SRST_SDMMC 122 +#define SRST_HSIC 123 +#define SRST_HSIC_AUX 124 +#define SRST_AHB1TOM 125 +#define SRST_P_PERIHP_NOC 126 +#define SRST_HSICPHY 127 + +/* cru_softrst_con8 */ +#define SRST_A_PCIE 128 +#define SRST_P_PCIE 129 +#define SRST_PCIE_CORE 130 +#define SRST_PCIE_MGMT 131 +#define SRST_PCIE_MGMT_STICKY 132 +#define SRST_PCIE_PIPE 133 +#define SRST_PCIE_PM 134 +#define SRST_PCIEPHY 135 +#define SRST_A_GMAC_NOC 136 +#define SRST_A_GMAC 137 +#define SRST_P_GMAC_NOC 138 +#define SRST_P_GMAC_GRF 140 +#define SRST_HSICPHY_POR 142 +#define SRST_HSICPHY_UTMI 143 + +/* cru_softrst_con9 */ +#define SRST_USB2PHY0_POR 144 +#define SRST_USB2PHY0_UTMI_PORT0 145 +#define SRST_USB2PHY0_UTMI_PORT1 146 +#define SRST_USB2PHY0_EHCIPHY 147 +#define SRST_UPHY0_PIPE_L00 148 +#define SRST_UPHY0 149 +#define SRST_UPHY0_TCPDPWRUP 150 +#define SRST_USB2PHY1_POR 152 +#define SRST_USB2PHY1_UTMI_PORT0 153 +#define SRST_USB2PHY1_UTMI_PORT1 154 +#define SRST_USB2PHY1_EHCIPHY 155 +#define SRST_UPHY1_PIPE_L00 156 +#define SRST_UPHY1 157 +#define SRST_UPHY1_TCPDPWRUP 158 + +/* cru_softrst_con10 */ +#define SRST_A_PERILP0_NOC 160 +#define SRST_A_DCF 161 +#define SRST_GIC500 162 +#define SRST_DMAC0_PERILP0 163 +#define SRST_DMAC1_PERILP0 164 +#define SRST_TZMA 165 +#define SRST_INTMEM 166 +#define SRST_ADB400_MST0 167 +#define SRST_ADB400_MST1 168 +#define SRST_ADB400_SLV0 169 +#define SRST_ADB400_SLV1 170 +#define SRST_H_PERILP0 171 +#define SRST_H_PERILP0_NOC 172 +#define SRST_ROM 173 +#define SRST_CRYPTO_S 174 +#define SRST_CRYPTO_M 175 + +/* cru_softrst_con11 */ +#define SRST_P_DCF 176 +#define SRST_CM0S_NOC 177 +#define SRST_CM0S 178 +#define SRST_CM0S_DBG 179 +#define SRST_CM0S_PO 180 +#define SRST_CRYPTO 181 +#define SRST_P_PERILP1_SGRF 182 +#define SRST_P_PERILP1_GRF 183 +#define SRST_CRYPTO1_S 184 +#define SRST_CRYPTO1_M 185 +#define SRST_CRYPTO1 186 +#define SRST_GIC_NOC 188 +#define SRST_SD_NOC 189 +#define SRST_SDIOAUDIO_BRG 190 + +/* cru_softrst_con12 */ +#define SRST_H_PERILP1 192 +#define SRST_H_PERILP1_NOC 193 +#define SRST_H_I2S0_8CH 194 +#define SRST_H_I2S1_8CH 195 +#define SRST_H_I2S2_8CH 196 +#define SRST_H_SPDIF_8CH 197 +#define SRST_P_PERILP1_NOC 198 +#define SRST_P_EFUSE_1024 199 +#define SRST_P_EFUSE_1024S 200 +#define SRST_P_I2C0 201 +#define SRST_P_I2C1 202 +#define SRST_P_I2C2 203 +#define SRST_P_I2C3 204 +#define SRST_P_I2C4 205 +#define SRST_P_I2C5 206 +#define SRST_P_MAILBOX0 207 + +/* cru_softrst_con13 */ +#define SRST_P_UART0 208 +#define SRST_P_UART1 209 +#define SRST_P_UART2 210 +#define SRST_P_UART3 211 +#define SRST_P_SARADC 212 +#define SRST_P_TSADC 213 +#define SRST_P_SPI0 214 +#define SRST_P_SPI1 215 +#define SRST_P_SPI2 216 +#define SRST_P_SPI3 217 +#define SRST_P_SPI4 218 +#define SRST_SPI0 219 +#define SRST_SPI1 220 +#define SRST_SPI2 221 +#define SRST_SPI3 222 +#define SRST_SPI4 223 + +/* cru_softrst_con14 */ +#define SRST_I2S0_8CH 224 +#define SRST_I2S1_8CH 225 +#define SRST_I2S2_8CH 226 +#define SRST_SPDIF_8CH 227 +#define SRST_UART0 228 +#define SRST_UART1 229 +#define SRST_UART2 230 +#define SRST_UART3 231 +#define SRST_TSADC 232 +#define SRST_I2C0 233 +#define SRST_I2C1 234 +#define SRST_I2C2 235 +#define SRST_I2C3 236 +#define SRST_I2C4 237 +#define SRST_I2C5 238 +#define SRST_SDIOAUDIO_NOC 239 + +/* cru_softrst_con15 */ +#define SRST_A_VIO_NOC 240 +#define SRST_A_HDCP_NOC 241 +#define SRST_A_HDCP 242 +#define SRST_H_HDCP_NOC 243 +#define SRST_H_HDCP 244 +#define SRST_P_HDCP_NOC 245 +#define SRST_P_HDCP 246 +#define SRST_P_HDMI_CTRL 247 +#define SRST_P_DP_CTRL 248 +#define SRST_S_DP_CTRL 249 +#define SRST_C_DP_CTRL 250 +#define SRST_P_MIPI_DSI0 251 +#define SRST_P_MIPI_DSI1 252 +#define SRST_DP_CORE 253 +#define SRST_DP_I2S 254 + +/* cru_softrst_con16 */ +#define SRST_GASKET 256 +#define SRST_VIO_GRF 258 +#define SRST_DPTX_SPDIF_REC 259 +#define SRST_HDMI_CTRL 260 +#define SRST_HDCP_CTRL 261 +#define SRST_A_ISP0_NOC 262 +#define SRST_A_ISP1_NOC 263 +#define SRST_H_ISP0_NOC 266 +#define SRST_H_ISP1_NOC 267 +#define SRST_H_ISP0 268 +#define SRST_H_ISP1 269 +#define SRST_ISP0 270 +#define SRST_ISP1 271 + +/* cru_softrst_con17 */ +#define SRST_A_VOP0_NOC 272 +#define SRST_A_VOP1_NOC 273 +#define SRST_A_VOP0 274 +#define SRST_A_VOP1 275 +#define SRST_H_VOP0_NOC 276 +#define SRST_H_VOP1_NOC 277 +#define SRST_H_VOP0 278 +#define SRST_H_VOP1 279 +#define SRST_D_VOP0 280 +#define SRST_D_VOP1 281 +#define SRST_VOP0_PWM 282 +#define SRST_VOP1_PWM 283 +#define SRST_P_EDP_NOC 284 +#define SRST_P_EDP_CTRL 285 + +/* cru_softrst_con18 */ +#define SRST_A_GPU 288 +#define SRST_A_GPU_NOC 289 +#define SRST_A_GPU_GRF 290 +#define SRST_PVTM_GPU 291 +#define SRST_A_USB3_NOC 292 +#define SRST_A_USB3_OTG0 293 +#define SRST_A_USB3_OTG1 294 +#define SRST_A_USB3_GRF 295 +#define SRST_PMU 296 + +/* cru_softrst_con19 */ +#define SRST_P_TIMER0_5 304 +#define SRST_TIMER0 305 +#define SRST_TIMER1 306 +#define SRST_TIMER2 307 +#define SRST_TIMER3 308 +#define SRST_TIMER4 309 +#define SRST_TIMER5 310 +#define SRST_P_TIMER6_11 311 +#define SRST_TIMER6 312 +#define SRST_TIMER7 313 +#define SRST_TIMER8 314 +#define SRST_TIMER9 315 +#define SRST_TIMER10 316 +#define SRST_TIMER11 317 +#define SRST_P_INTR_ARB_PMU 318 +#define SRST_P_ALIVE_SGRF 319 + +/* cru_softrst_con20 */ +#define SRST_P_GPIO2 320 +#define SRST_P_GPIO3 321 +#define SRST_P_GPIO4 322 +#define SRST_P_GRF 323 +#define SRST_P_ALIVE_NOC 324 +#define SRST_P_WDT0 325 +#define SRST_P_WDT1 326 +#define SRST_P_INTR_ARB 327 +#define SRST_P_UPHY0_DPTX 328 +#define SRST_P_UPHY0_APB 330 +#define SRST_P_UPHY0_TCPHY 332 +#define SRST_P_UPHY1_TCPHY 333 +#define SRST_P_UPHY0_TCPDCTRL 334 +#define SRST_P_UPHY1_TCPDCTRL 335 + +/* pmu soft-reset indices */ + +/* pmu_cru_softrst_con0 */ +#define SRST_P_NOC 0 +#define SRST_P_INTMEM 1 +#define SRST_H_CM0S 2 +#define SRST_H_CM0S_NOC 3 +#define SRST_DBG_CM0S 4 +#define SRST_PO_CM0S 5 +#define SRST_P_SPI6 6 +#define SRST_SPI6 7 +#define SRST_P_TIMER_0_1 8 +#define SRST_P_TIMER_0 9 +#define SRST_P_TIMER_1 10 +#define SRST_P_UART4 11 +#define SRST_UART4 12 +#define SRST_P_WDT 13 + +/* pmu_cru_softrst_con1 */ +#define SRST_P_I2C6 16 +#define SRST_P_I2C7 17 +#define SRST_P_I2C8 18 +#define SRST_P_MAILBOX 19 +#define SRST_P_RKPWM 20 +#define SRST_P_PMUGRF 21 +#define SRST_P_SGRF 22 +#define SRST_P_GPIO0 23 +#define SRST_P_GPIO1 24 +#define SRST_P_CRU 25 +#define SRST_P_INTR 26 +#define SRST_PVTM 27 +#define SRST_I2C6 28 +#define SRST_I2C7 29 +#define SRST_I2C8 30 + +#endif diff --git a/include/dt-bindings/clock/stih407-clks.h b/include/dt-bindings/clock/stih407-clks.h index 7af2b717b3b2..082edd9badfa 100644 --- a/include/dt-bindings/clock/stih407-clks.h +++ b/include/dt-bindings/clock/stih407-clks.h @@ -5,6 +5,10 @@ #ifndef _DT_BINDINGS_CLK_STIH407 #define _DT_BINDINGS_CLK_STIH407 +/* CLOCKGEN A0 */ +#define CLK_IC_LMI0 0 +#define CLK_IC_LMI1 1 + /* CLOCKGEN C0 */ #define CLK_ICN_GPU 0 #define CLK_FDMA 1 diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h new file mode 100644 index 000000000000..efb7ba2bd515 --- /dev/null +++ b/include/dt-bindings/clock/sun8i-h3-ccu.h @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_ +#define _DT_BINDINGS_CLK_SUN8I_H3_H_ + +#define CLK_CPUX 14 + +#define CLK_BUS_CE 20 +#define CLK_BUS_DMA 21 +#define CLK_BUS_MMC0 22 +#define CLK_BUS_MMC1 23 +#define CLK_BUS_MMC2 24 +#define CLK_BUS_NAND 25 +#define CLK_BUS_DRAM 26 +#define CLK_BUS_EMAC 27 +#define CLK_BUS_TS 28 +#define CLK_BUS_HSTIMER 29 +#define CLK_BUS_SPI0 30 +#define CLK_BUS_SPI1 31 +#define CLK_BUS_OTG 32 +#define CLK_BUS_EHCI0 33 +#define CLK_BUS_EHCI1 34 +#define CLK_BUS_EHCI2 35 +#define CLK_BUS_EHCI3 36 +#define CLK_BUS_OHCI0 37 +#define CLK_BUS_OHCI1 38 +#define CLK_BUS_OHCI2 39 +#define CLK_BUS_OHCI3 40 +#define CLK_BUS_VE 41 +#define CLK_BUS_TCON0 42 +#define CLK_BUS_TCON1 43 +#define CLK_BUS_DEINTERLACE 44 +#define CLK_BUS_CSI 45 +#define CLK_BUS_TVE 46 +#define CLK_BUS_HDMI 47 +#define CLK_BUS_DE 48 +#define CLK_BUS_GPU 49 +#define CLK_BUS_MSGBOX 50 +#define CLK_BUS_SPINLOCK 51 +#define CLK_BUS_CODEC 52 +#define CLK_BUS_SPDIF 53 +#define CLK_BUS_PIO 54 +#define CLK_BUS_THS 55 +#define CLK_BUS_I2S0 56 +#define CLK_BUS_I2S1 57 +#define CLK_BUS_I2S2 58 +#define CLK_BUS_I2C0 59 +#define CLK_BUS_I2C1 60 +#define CLK_BUS_I2C2 61 +#define CLK_BUS_UART0 62 +#define CLK_BUS_UART1 63 +#define CLK_BUS_UART2 64 +#define CLK_BUS_UART3 65 +#define CLK_BUS_SCR 66 +#define CLK_BUS_EPHY 67 +#define CLK_BUS_DBG 68 + +#define CLK_THS 69 +#define CLK_NAND 70 +#define CLK_MMC0 71 +#define CLK_MMC0_SAMPLE 72 +#define CLK_MMC0_OUTPUT 73 +#define CLK_MMC1 74 +#define CLK_MMC1_SAMPLE 75 +#define CLK_MMC1_OUTPUT 76 +#define CLK_MMC2 77 +#define CLK_MMC2_SAMPLE 78 +#define CLK_MMC2_OUTPUT 79 +#define CLK_TS 80 +#define CLK_CE 81 +#define CLK_SPI0 82 +#define CLK_SPI1 83 +#define CLK_I2S0 84 +#define CLK_I2S1 85 +#define CLK_I2S2 86 +#define CLK_SPDIF 87 +#define CLK_USB_PHY0 88 +#define CLK_USB_PHY1 89 +#define CLK_USB_PHY2 90 +#define CLK_USB_PHY3 91 +#define CLK_USB_OHCI0 92 +#define CLK_USB_OHCI1 93 +#define CLK_USB_OHCI2 94 +#define CLK_USB_OHCI3 95 + +#define CLK_DRAM_VE 97 +#define CLK_DRAM_CSI 98 +#define CLK_DRAM_DEINTERLACE 99 +#define CLK_DRAM_TS 100 +#define CLK_DE 101 +#define CLK_TCON0 102 +#define CLK_TVE 103 +#define CLK_DEINTERLACE 104 +#define CLK_CSI_MISC 105 +#define CLK_CSI_SCLK 106 +#define CLK_CSI_MCLK 107 +#define CLK_VE 108 +#define CLK_AC_DIG 109 +#define CLK_AVS 110 +#define CLK_HDMI 111 +#define CLK_HDMI_DDC 112 + +#define CLK_GPU 114 + +#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */ diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 0a05b0d36ae7..35288b20f2c9 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -308,7 +308,7 @@ #define TEGRA210_CLK_CLK_OUT_3 279 #define TEGRA210_CLK_BLINK 280 /* 281 */ -/* 282 */ +#define TEGRA210_CLK_SOR1_SRC 282 /* 283 */ #define TEGRA210_CLK_XUSB_HOST_SRC 284 #define TEGRA210_CLK_XUSB_FALCON_SRC 285 @@ -346,7 +346,7 @@ #define TEGRA210_CLK_PLL_P_OUT_HSIO 316 #define TEGRA210_CLK_PLL_P_OUT_XUSB 317 #define TEGRA210_CLK_XUSB_SSP_SRC 318 -/* 319 */ +#define TEGRA210_CLK_PLL_RE_OUT1 319 /* 320 */ /* 321 */ /* 322 */ diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h index 56c16aaea112..45997750c8a0 100644 --- a/include/dt-bindings/clock/vf610-clock.h +++ b/include/dt-bindings/clock/vf610-clock.h @@ -194,7 +194,11 @@ #define VF610_PLL7_BYPASS 181 #define VF610_CLK_SNVS 182 #define VF610_CLK_DAP 183 -#define VF610_CLK_OCOTP 184 -#define VF610_CLK_END 185 +#define VF610_CLK_OCOTP 184 +#define VF610_CLK_DDRMC 185 +#define VF610_CLK_WKPU 186 +#define VF610_CLK_TCON0 187 +#define VF610_CLK_TCON1 188 +#define VF610_CLK_END 189 #endif /* __DT_BINDINGS_CLOCK_VF610_H */ |