diff options
Diffstat (limited to 'include/dt-bindings/clock')
46 files changed, 3663 insertions, 10 deletions
diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h index 6ede88c3992d..f2a7b7d39c0d 100644 --- a/include/dt-bindings/clock/at91.h +++ b/include/dt-bindings/clock/at91.h @@ -42,6 +42,10 @@ #define PMC_PLLADIV2 (PMC_MAIN + 11) #define PMC_LVDSPLL (PMC_MAIN + 12) +/* SAMA7D65 */ +#define PMC_MCK3 (PMC_MAIN + 13) +#define PMC_MCK5 (PMC_MAIN + 14) + #ifndef AT91_PMC_MOSCS #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ #define AT91_PMC_LOCKA 1 /* PLLA Lock */ @@ -55,4 +59,8 @@ #define AT91_PMC_GCKRDY 24 /* Generated Clocks */ #endif +/* Slow clock. */ +#define SCKC_MD_SLCK 0 +#define SCKC_TD_SLCK 1 + #endif diff --git a/include/dt-bindings/clock/en7523-clk.h b/include/dt-bindings/clock/en7523-clk.h index 717d23a5e5ae..edfa64045f52 100644 --- a/include/dt-bindings/clock/en7523-clk.h +++ b/include/dt-bindings/clock/en7523-clk.h @@ -12,6 +12,6 @@ #define EN7523_CLK_CRYPTO 6 #define EN7523_CLK_PCIE 7 -#define EN7523_NUM_CLOCKS 8 +#define EN7581_CLK_EMMC 8 #endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */ diff --git a/include/dt-bindings/clock/mediatek,mt8188-clk.h b/include/dt-bindings/clock/mediatek,mt8188-clk.h index bd5cd100b796..0e87f61c90f4 100644 --- a/include/dt-bindings/clock/mediatek,mt8188-clk.h +++ b/include/dt-bindings/clock/mediatek,mt8188-clk.h @@ -721,6 +721,6 @@ #define CLK_VDO1_DPINTF 58 #define CLK_VDO1_DISP_MONITOR_DPINTF 59 #define CLK_VDO1_26M_SLOW 60 -#define CLK_VDO1_NR_CLK 61 +#define CLK_VDO1_DPI1_HDMI 61 #endif /* _DT_BINDINGS_CLK_MT8188_H */ diff --git a/include/dt-bindings/clock/mediatek,mtmips-sysc.h b/include/dt-bindings/clock/mediatek,mtmips-sysc.h new file mode 100644 index 000000000000..a03335b0e077 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mtmips-sysc.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com> + */ + +#ifndef _DT_BINDINGS_CLK_MTMIPS_H +#define _DT_BINDINGS_CLK_MTMIPS_H + +/* Ralink RT-2880 clocks */ + +#define RT2880_CLK_XTAL 0 +#define RT2880_CLK_CPU 1 +#define RT2880_CLK_BUS 2 +#define RT2880_CLK_TIMER 3 +#define RT2880_CLK_WATCHDOG 4 +#define RT2880_CLK_UART 5 +#define RT2880_CLK_I2C 6 +#define RT2880_CLK_UARTLITE 7 +#define RT2880_CLK_ETHERNET 8 +#define RT2880_CLK_WMAC 9 + +/* Ralink RT-305X clocks */ + +#define RT305X_CLK_XTAL 0 +#define RT305X_CLK_CPU 1 +#define RT305X_CLK_BUS 2 +#define RT305X_CLK_TIMER 3 +#define RT305X_CLK_WATCHDOG 4 +#define RT305X_CLK_UART 5 +#define RT305X_CLK_I2C 6 +#define RT305X_CLK_I2S 7 +#define RT305X_CLK_SPI1 8 +#define RT305X_CLK_SPI2 9 +#define RT305X_CLK_UARTLITE 10 +#define RT305X_CLK_ETHERNET 11 +#define RT305X_CLK_WMAC 12 + +/* Ralink RT-3352 clocks */ + +#define RT3352_CLK_XTAL 0 +#define RT3352_CLK_CPU 1 +#define RT3352_CLK_PERIPH 2 +#define RT3352_CLK_BUS 3 +#define RT3352_CLK_TIMER 4 +#define RT3352_CLK_WATCHDOG 5 +#define RT3352_CLK_UART 6 +#define RT3352_CLK_I2C 7 +#define RT3352_CLK_I2S 8 +#define RT3352_CLK_SPI1 9 +#define RT3352_CLK_SPI2 10 +#define RT3352_CLK_UARTLITE 11 +#define RT3352_CLK_ETHERNET 12 +#define RT3352_CLK_WMAC 13 + +/* Ralink RT-3883 clocks */ + +#define RT3883_CLK_XTAL 0 +#define RT3883_CLK_CPU 1 +#define RT3883_CLK_BUS 2 +#define RT3883_CLK_PERIPH 3 +#define RT3883_CLK_TIMER 4 +#define RT3883_CLK_WATCHDOG 5 +#define RT3883_CLK_UART 6 +#define RT3883_CLK_I2C 7 +#define RT3883_CLK_I2S 8 +#define RT3883_CLK_SPI1 9 +#define RT3883_CLK_SPI2 10 +#define RT3883_CLK_UARTLITE 11 +#define RT3883_CLK_ETHERNET 12 +#define RT3883_CLK_WMAC 13 + +/* Ralink RT-5350 clocks */ + +#define RT5350_CLK_XTAL 0 +#define RT5350_CLK_CPU 1 +#define RT5350_CLK_BUS 2 +#define RT5350_CLK_PERIPH 3 +#define RT5350_CLK_TIMER 4 +#define RT5350_CLK_WATCHDOG 5 +#define RT5350_CLK_UART 6 +#define RT5350_CLK_I2C 7 +#define RT5350_CLK_I2S 8 +#define RT5350_CLK_SPI1 9 +#define RT5350_CLK_SPI2 10 +#define RT5350_CLK_UARTLITE 11 +#define RT5350_CLK_ETHERNET 12 +#define RT5350_CLK_WMAC 13 + +/* Ralink MT-7620 clocks */ + +#define MT7620_CLK_XTAL 0 +#define MT7620_CLK_PLL 1 +#define MT7620_CLK_CPU 2 +#define MT7620_CLK_PERIPH 3 +#define MT7620_CLK_BUS 4 +#define MT7620_CLK_BBPPLL 5 +#define MT7620_CLK_SDHC 6 +#define MT7620_CLK_TIMER 7 +#define MT7620_CLK_WATCHDOG 8 +#define MT7620_CLK_UART 9 +#define MT7620_CLK_I2C 10 +#define MT7620_CLK_I2S 11 +#define MT7620_CLK_SPI1 12 +#define MT7620_CLK_SPI2 13 +#define MT7620_CLK_UARTLITE 14 +#define MT7620_CLK_MMC 15 +#define MT7620_CLK_WMAC 16 + +/* Ralink MT-76X8 clocks */ + +#define MT76X8_CLK_XTAL 0 +#define MT76X8_CLK_CPU 1 +#define MT76X8_CLK_BBPPLL 2 +#define MT76X8_CLK_PCMI2S 3 +#define MT76X8_CLK_PERIPH 4 +#define MT76X8_CLK_BUS 5 +#define MT76X8_CLK_SDHC 6 +#define MT76X8_CLK_TIMER 7 +#define MT76X8_CLK_WATCHDOG 8 +#define MT76X8_CLK_I2C 9 +#define MT76X8_CLK_I2S 10 +#define MT76X8_CLK_SPI1 11 +#define MT76X8_CLK_SPI2 12 +#define MT76X8_CLK_UART0 13 +#define MT76X8_CLK_UART1 14 +#define MT76X8_CLK_UART2 15 +#define MT76X8_CLK_MMC 16 +#define MT76X8_CLK_WMAC 17 + +#endif /* _DT_BINDINGS_CLK_MTMIPS_H */ diff --git a/include/dt-bindings/clock/qcom,dsi-phy-28nm.h b/include/dt-bindings/clock/qcom,dsi-phy-28nm.h new file mode 100644 index 000000000000..ab94d58377a1 --- /dev/null +++ b/include/dt-bindings/clock/qcom,dsi-phy-28nm.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DSI_PHY_28NM_H +#define _DT_BINDINGS_CLK_QCOM_DSI_PHY_28NM_H + +#define DSI_BYTE_PLL_CLK 0 +#define DSI_PIXEL_PLL_CLK 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h index df8a6f3d367e..74c22f67da21 100644 --- a/include/dt-bindings/clock/qcom,gcc-sdm660.h +++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h @@ -153,5 +153,7 @@ #define GCC_USB_30_BCR 7 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 8 #define GCC_MSS_RESTART 9 +#define GCC_SDCC1_BCR 10 +#define GCC_SDCC2_BCR 11 #endif diff --git a/include/dt-bindings/clock/qcom,ipq-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h new file mode 100644 index 000000000000..936e92b3b62c --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H +#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H + +/* CMN PLL core clock. */ +#define CMN_PLL_CLK 0 + +/* The output clocks from CMN PLL of IPQ9574. */ +#define XO_24MHZ_CLK 1 +#define SLEEP_32KHZ_CLK 2 +#define PCS_31P25MHZ_CLK 3 +#define NSS_1200MHZ_CLK 4 +#define PPE_353MHZ_CLK 5 +#define ETH0_50MHZ_CLK 6 +#define ETH1_50MHZ_CLK 7 +#define ETH2_50MHZ_CLK 8 +#define ETH_25MHZ_CLK 9 +#endif diff --git a/include/dt-bindings/clock/qcom,ipq5424-gcc.h b/include/dt-bindings/clock/qcom,ipq5424-gcc.h index 755ce7a71c7c..c15ad16923bd 100644 --- a/include/dt-bindings/clock/qcom,ipq5424-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq5424-gcc.h @@ -12,7 +12,6 @@ #define GPLL2 2 #define GPLL2_OUT_MAIN 3 #define GCC_SLEEP_CLK_SRC 4 -#define GCC_APSS_DBG_CLK 5 #define GCC_USB0_EUD_AT_CLK 6 #define GCC_PCIE0_AXI_M_CLK_SRC 7 #define GCC_PCIE0_AXI_M_CLK 8 @@ -152,5 +151,6 @@ #define GCC_PCIE3_RCHNG_CLK_SRC 142 #define GCC_PCIE3_RCHNG_CLK 143 #define GCC_IM_SLEEP_CLK 144 +#define GCC_XO_CLK 145 #endif diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index f238aa4794a8..0e7c319897f3 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -202,4 +202,5 @@ #define GCC_PCIE1_PIPE_CLK 211 #define GCC_PCIE2_PIPE_CLK 212 #define GCC_PCIE3_PIPE_CLK 213 +#define GPLL0_OUT_AUX 214 #endif diff --git a/include/dt-bindings/clock/qcom,ipq9574-nsscc.h b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h new file mode 100644 index 000000000000..21a16dc0e64c --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H +#define _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H + +#define NSS_CC_CE_APB_CLK 0 +#define NSS_CC_CE_AXI_CLK 1 +#define NSS_CC_CE_CLK_SRC 2 +#define NSS_CC_CFG_CLK_SRC 3 +#define NSS_CC_CLC_AXI_CLK 4 +#define NSS_CC_CLC_CLK_SRC 5 +#define NSS_CC_CRYPTO_CLK 6 +#define NSS_CC_CRYPTO_CLK_SRC 7 +#define NSS_CC_CRYPTO_PPE_CLK 8 +#define NSS_CC_HAQ_AHB_CLK 9 +#define NSS_CC_HAQ_AXI_CLK 10 +#define NSS_CC_HAQ_CLK_SRC 11 +#define NSS_CC_IMEM_AHB_CLK 12 +#define NSS_CC_IMEM_CLK_SRC 13 +#define NSS_CC_IMEM_QSB_CLK 14 +#define NSS_CC_INT_CFG_CLK_SRC 15 +#define NSS_CC_NSS_CSR_CLK 16 +#define NSS_CC_NSSNOC_CE_APB_CLK 17 +#define NSS_CC_NSSNOC_CE_AXI_CLK 18 +#define NSS_CC_NSSNOC_CLC_AXI_CLK 19 +#define NSS_CC_NSSNOC_CRYPTO_CLK 20 +#define NSS_CC_NSSNOC_HAQ_AHB_CLK 21 +#define NSS_CC_NSSNOC_HAQ_AXI_CLK 22 +#define NSS_CC_NSSNOC_IMEM_AHB_CLK 23 +#define NSS_CC_NSSNOC_IMEM_QSB_CLK 24 +#define NSS_CC_NSSNOC_NSS_CSR_CLK 25 +#define NSS_CC_NSSNOC_PPE_CFG_CLK 26 +#define NSS_CC_NSSNOC_PPE_CLK 27 +#define NSS_CC_NSSNOC_UBI32_AHB0_CLK 28 +#define NSS_CC_NSSNOC_UBI32_AXI0_CLK 29 +#define NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK 30 +#define NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK 31 +#define NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK 32 +#define NSS_CC_PORT1_MAC_CLK 33 +#define NSS_CC_PORT1_RX_CLK 34 +#define NSS_CC_PORT1_RX_CLK_SRC 35 +#define NSS_CC_PORT1_RX_DIV_CLK_SRC 36 +#define NSS_CC_PORT1_TX_CLK 37 +#define NSS_CC_PORT1_TX_CLK_SRC 38 +#define NSS_CC_PORT1_TX_DIV_CLK_SRC 39 +#define NSS_CC_PORT2_MAC_CLK 40 +#define NSS_CC_PORT2_RX_CLK 41 +#define NSS_CC_PORT2_RX_CLK_SRC 42 +#define NSS_CC_PORT2_RX_DIV_CLK_SRC 43 +#define NSS_CC_PORT2_TX_CLK 44 +#define NSS_CC_PORT2_TX_CLK_SRC 45 +#define NSS_CC_PORT2_TX_DIV_CLK_SRC 46 +#define NSS_CC_PORT3_MAC_CLK 47 +#define NSS_CC_PORT3_RX_CLK 48 +#define NSS_CC_PORT3_RX_CLK_SRC 49 +#define NSS_CC_PORT3_RX_DIV_CLK_SRC 50 +#define NSS_CC_PORT3_TX_CLK 51 +#define NSS_CC_PORT3_TX_CLK_SRC 52 +#define NSS_CC_PORT3_TX_DIV_CLK_SRC 53 +#define NSS_CC_PORT4_MAC_CLK 54 +#define NSS_CC_PORT4_RX_CLK 55 +#define NSS_CC_PORT4_RX_CLK_SRC 56 +#define NSS_CC_PORT4_RX_DIV_CLK_SRC 57 +#define NSS_CC_PORT4_TX_CLK 58 +#define NSS_CC_PORT4_TX_CLK_SRC 59 +#define NSS_CC_PORT4_TX_DIV_CLK_SRC 60 +#define NSS_CC_PORT5_MAC_CLK 61 +#define NSS_CC_PORT5_RX_CLK 62 +#define NSS_CC_PORT5_RX_CLK_SRC 63 +#define NSS_CC_PORT5_RX_DIV_CLK_SRC 64 +#define NSS_CC_PORT5_TX_CLK 65 +#define NSS_CC_PORT5_TX_CLK_SRC 66 +#define NSS_CC_PORT5_TX_DIV_CLK_SRC 67 +#define NSS_CC_PORT6_MAC_CLK 68 +#define NSS_CC_PORT6_RX_CLK 69 +#define NSS_CC_PORT6_RX_CLK_SRC 70 +#define NSS_CC_PORT6_RX_DIV_CLK_SRC 71 +#define NSS_CC_PORT6_TX_CLK 72 +#define NSS_CC_PORT6_TX_CLK_SRC 73 +#define NSS_CC_PORT6_TX_DIV_CLK_SRC 74 +#define NSS_CC_PPE_CLK_SRC 75 +#define NSS_CC_PPE_EDMA_CFG_CLK 76 +#define NSS_CC_PPE_EDMA_CLK 77 +#define NSS_CC_PPE_SWITCH_BTQ_CLK 78 +#define NSS_CC_PPE_SWITCH_CFG_CLK 79 +#define NSS_CC_PPE_SWITCH_CLK 80 +#define NSS_CC_PPE_SWITCH_IPE_CLK 81 +#define NSS_CC_UBI0_CLK_SRC 82 +#define NSS_CC_UBI0_DIV_CLK_SRC 83 +#define NSS_CC_UBI1_CLK_SRC 84 +#define NSS_CC_UBI1_DIV_CLK_SRC 85 +#define NSS_CC_UBI2_CLK_SRC 86 +#define NSS_CC_UBI2_DIV_CLK_SRC 87 +#define NSS_CC_UBI32_AHB0_CLK 88 +#define NSS_CC_UBI32_AHB1_CLK 89 +#define NSS_CC_UBI32_AHB2_CLK 90 +#define NSS_CC_UBI32_AHB3_CLK 91 +#define NSS_CC_UBI32_AXI0_CLK 92 +#define NSS_CC_UBI32_AXI1_CLK 93 +#define NSS_CC_UBI32_AXI2_CLK 94 +#define NSS_CC_UBI32_AXI3_CLK 95 +#define NSS_CC_UBI32_CORE0_CLK 96 +#define NSS_CC_UBI32_CORE1_CLK 97 +#define NSS_CC_UBI32_CORE2_CLK 98 +#define NSS_CC_UBI32_CORE3_CLK 99 +#define NSS_CC_UBI32_INTR0_AHB_CLK 100 +#define NSS_CC_UBI32_INTR1_AHB_CLK 101 +#define NSS_CC_UBI32_INTR2_AHB_CLK 102 +#define NSS_CC_UBI32_INTR3_AHB_CLK 103 +#define NSS_CC_UBI32_NC_AXI0_CLK 104 +#define NSS_CC_UBI32_NC_AXI1_CLK 105 +#define NSS_CC_UBI32_NC_AXI2_CLK 106 +#define NSS_CC_UBI32_NC_AXI3_CLK 107 +#define NSS_CC_UBI32_UTCM0_CLK 108 +#define NSS_CC_UBI32_UTCM1_CLK 109 +#define NSS_CC_UBI32_UTCM2_CLK 110 +#define NSS_CC_UBI32_UTCM3_CLK 111 +#define NSS_CC_UBI3_CLK_SRC 112 +#define NSS_CC_UBI3_DIV_CLK_SRC 113 +#define NSS_CC_UBI_AXI_CLK_SRC 114 +#define NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC 115 +#define NSS_CC_UNIPHY_PORT1_RX_CLK 116 +#define NSS_CC_UNIPHY_PORT1_TX_CLK 117 +#define NSS_CC_UNIPHY_PORT2_RX_CLK 118 +#define NSS_CC_UNIPHY_PORT2_TX_CLK 119 +#define NSS_CC_UNIPHY_PORT3_RX_CLK 120 +#define NSS_CC_UNIPHY_PORT3_TX_CLK 121 +#define NSS_CC_UNIPHY_PORT4_RX_CLK 122 +#define NSS_CC_UNIPHY_PORT4_TX_CLK 123 +#define NSS_CC_UNIPHY_PORT5_RX_CLK 124 +#define NSS_CC_UNIPHY_PORT5_TX_CLK 125 +#define NSS_CC_UNIPHY_PORT6_RX_CLK 126 +#define NSS_CC_UNIPHY_PORT6_TX_CLK 127 +#define NSS_CC_XGMAC0_PTP_REF_CLK 128 +#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 129 +#define NSS_CC_XGMAC1_PTP_REF_CLK 130 +#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 131 +#define NSS_CC_XGMAC2_PTP_REF_CLK 132 +#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 133 +#define NSS_CC_XGMAC3_PTP_REF_CLK 134 +#define NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC 135 +#define NSS_CC_XGMAC4_PTP_REF_CLK 136 +#define NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC 137 +#define NSS_CC_XGMAC5_PTP_REF_CLK 138 +#define NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC 139 +#define UBI32_PLL 140 +#define UBI32_PLL_MAIN 141 + +#endif diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8960.h b/include/dt-bindings/clock/qcom,mmcc-msm8960.h index 81714fc859c5..717431d735c1 100644 --- a/include/dt-bindings/clock/qcom,mmcc-msm8960.h +++ b/include/dt-bindings/clock/qcom,mmcc-msm8960.h @@ -133,5 +133,7 @@ #define VCAP_CLK 124 #define VCAP_NPL_CLK 125 #define PLL15 126 +#define DSI2_PIXEL_LVDS_SRC 127 +#define LVDS_CLK 128 #endif diff --git a/include/dt-bindings/clock/qcom,qcs615-gcc.h b/include/dt-bindings/clock/qcom,qcs615-gcc.h new file mode 100644 index 000000000000..9704091636b8 --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs615-gcc.h @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS615_H +#define _DT_BINDINGS_CLK_QCOM_GCC_QCS615_H + +/* GCC clocks */ +#define GPLL0_OUT_AUX2_DIV 0 +#define GPLL3_OUT_AUX2_DIV 1 +#define GPLL0 2 +#define GPLL3 3 +#define GPLL4 4 +#define GPLL6 5 +#define GPLL6_OUT_MAIN 6 +#define GPLL7 7 +#define GPLL8 8 +#define GPLL8_OUT_MAIN 9 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 10 +#define GCC_AGGRE_USB2_SEC_AXI_CLK 11 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 12 +#define GCC_AHB2PHY_EAST_CLK 13 +#define GCC_AHB2PHY_WEST_CLK 14 +#define GCC_BOOT_ROM_AHB_CLK 15 +#define GCC_CAMERA_AHB_CLK 16 +#define GCC_CAMERA_HF_AXI_CLK 17 +#define GCC_CAMERA_XO_CLK 18 +#define GCC_CE1_AHB_CLK 19 +#define GCC_CE1_AXI_CLK 20 +#define GCC_CE1_CLK 21 +#define GCC_CFG_NOC_USB2_SEC_AXI_CLK 22 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 23 +#define GCC_CPUSS_AHB_CLK 24 +#define GCC_CPUSS_AHB_CLK_SRC 25 +#define GCC_CPUSS_GNOC_CLK 26 +#define GCC_DDRSS_GPU_AXI_CLK 27 +#define GCC_DISP_AHB_CLK 28 +#define GCC_DISP_GPLL0_DIV_CLK_SRC 29 +#define GCC_DISP_HF_AXI_CLK 30 +#define GCC_DISP_XO_CLK 31 +#define GCC_EMAC_AXI_CLK 32 +#define GCC_EMAC_PTP_CLK 33 +#define GCC_EMAC_PTP_CLK_SRC 34 +#define GCC_EMAC_RGMII_CLK 35 +#define GCC_EMAC_RGMII_CLK_SRC 36 +#define GCC_EMAC_SLV_AHB_CLK 37 +#define GCC_GP1_CLK 38 +#define GCC_GP1_CLK_SRC 39 +#define GCC_GP2_CLK 40 +#define GCC_GP2_CLK_SRC 41 +#define GCC_GP3_CLK 42 +#define GCC_GP3_CLK_SRC 43 +#define GCC_GPU_CFG_AHB_CLK 44 +#define GCC_GPU_GPLL0_CLK_SRC 45 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 46 +#define GCC_GPU_IREF_CLK 47 +#define GCC_GPU_MEMNOC_GFX_CLK 48 +#define GCC_GPU_SNOC_DVM_GFX_CLK 49 +#define GCC_PCIE0_PHY_REFGEN_CLK 50 +#define GCC_PCIE_0_AUX_CLK 51 +#define GCC_PCIE_0_AUX_CLK_SRC 52 +#define GCC_PCIE_0_CFG_AHB_CLK 53 +#define GCC_PCIE_0_CLKREF_CLK 54 +#define GCC_PCIE_0_MSTR_AXI_CLK 55 +#define GCC_PCIE_0_PIPE_CLK 56 +#define GCC_PCIE_0_SLV_AXI_CLK 57 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 58 +#define GCC_PCIE_PHY_AUX_CLK 59 +#define GCC_PCIE_PHY_REFGEN_CLK_SRC 60 +#define GCC_PDM2_CLK 61 +#define GCC_PDM2_CLK_SRC 62 +#define GCC_PDM_AHB_CLK 63 +#define GCC_PDM_XO4_CLK 64 +#define GCC_PRNG_AHB_CLK 65 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 66 +#define GCC_QMIP_DISP_AHB_CLK 67 +#define GCC_QMIP_PCIE_AHB_CLK 68 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 69 +#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 70 +#define GCC_QSPI_CORE_CLK 71 +#define GCC_QSPI_CORE_CLK_SRC 72 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 73 +#define GCC_QUPV3_WRAP0_CORE_CLK 74 +#define GCC_QUPV3_WRAP0_S0_CLK 75 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 76 +#define GCC_QUPV3_WRAP0_S1_CLK 77 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 78 +#define GCC_QUPV3_WRAP0_S2_CLK 79 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 80 +#define GCC_QUPV3_WRAP0_S3_CLK 81 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 82 +#define GCC_QUPV3_WRAP0_S4_CLK 83 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 84 +#define GCC_QUPV3_WRAP0_S5_CLK 85 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 86 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 87 +#define GCC_QUPV3_WRAP1_CORE_CLK 88 +#define GCC_QUPV3_WRAP1_S0_CLK 89 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 90 +#define GCC_QUPV3_WRAP1_S1_CLK 91 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 92 +#define GCC_QUPV3_WRAP1_S2_CLK 93 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 94 +#define GCC_QUPV3_WRAP1_S3_CLK 95 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 96 +#define GCC_QUPV3_WRAP1_S4_CLK 97 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 98 +#define GCC_QUPV3_WRAP1_S5_CLK 99 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 100 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 101 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 102 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 103 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 104 +#define GCC_RX1_USB2_CLKREF_CLK 105 +#define GCC_RX3_USB2_CLKREF_CLK 106 +#define GCC_SDCC1_AHB_CLK 107 +#define GCC_SDCC1_APPS_CLK 108 +#define GCC_SDCC1_APPS_CLK_SRC 109 +#define GCC_SDCC1_ICE_CORE_CLK 110 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 111 +#define GCC_SDCC2_AHB_CLK 112 +#define GCC_SDCC2_APPS_CLK 113 +#define GCC_SDCC2_APPS_CLK_SRC 114 +#define GCC_SDR_CORE_CLK 115 +#define GCC_SDR_CSR_HCLK 116 +#define GCC_SDR_PRI_MI2S_CLK 117 +#define GCC_SDR_SEC_MI2S_CLK 118 +#define GCC_SDR_WR0_MEM_CLK 119 +#define GCC_SDR_WR1_MEM_CLK 120 +#define GCC_SDR_WR2_MEM_CLK 121 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 122 +#define GCC_UFS_CARD_CLKREF_CLK 123 +#define GCC_UFS_MEM_CLKREF_CLK 124 +#define GCC_UFS_PHY_AHB_CLK 125 +#define GCC_UFS_PHY_AXI_CLK 126 +#define GCC_UFS_PHY_AXI_CLK_SRC 127 +#define GCC_UFS_PHY_ICE_CORE_CLK 128 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 129 +#define GCC_UFS_PHY_PHY_AUX_CLK 130 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 131 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 132 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 133 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 134 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 135 +#define GCC_USB20_SEC_MASTER_CLK 136 +#define GCC_USB20_SEC_MASTER_CLK_SRC 137 +#define GCC_USB20_SEC_MOCK_UTMI_CLK 138 +#define GCC_USB20_SEC_MOCK_UTMI_CLK_SRC 139 +#define GCC_USB20_SEC_SLEEP_CLK 140 +#define GCC_USB2_PRIM_CLKREF_CLK 141 +#define GCC_USB2_SEC_CLKREF_CLK 142 +#define GCC_USB2_SEC_PHY_AUX_CLK 143 +#define GCC_USB2_SEC_PHY_AUX_CLK_SRC 144 +#define GCC_USB2_SEC_PHY_COM_AUX_CLK 145 +#define GCC_USB2_SEC_PHY_PIPE_CLK 146 +#define GCC_USB30_PRIM_MASTER_CLK 147 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 148 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 149 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 150 +#define GCC_USB30_PRIM_SLEEP_CLK 151 +#define GCC_USB3_PRIM_CLKREF_CLK 152 +#define GCC_USB3_PRIM_PHY_AUX_CLK 153 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 154 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 155 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 156 +#define GCC_USB3_SEC_CLKREF_CLK 157 +#define GCC_VIDEO_AHB_CLK 158 +#define GCC_VIDEO_AXI0_CLK 159 +#define GCC_VIDEO_XO_CLK 160 +#define GCC_VSENSOR_CLK_SRC 161 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 162 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 163 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 164 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 165 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 166 + +/* GCC Resets */ +#define GCC_EMAC_BCR 0 +#define GCC_QUSB2PHY_PRIM_BCR 1 +#define GCC_QUSB2PHY_SEC_BCR 2 +#define GCC_USB30_PRIM_BCR 3 +#define GCC_USB2_PHY_SEC_BCR 4 +#define GCC_USB3_DP_PHY_SEC_BCR 5 +#define GCC_USB3PHY_PHY_SEC_BCR 6 +#define GCC_PCIE_0_BCR 7 +#define GCC_PCIE_0_PHY_BCR 8 +#define GCC_PCIE_PHY_BCR 9 +#define GCC_PCIE_PHY_COM_BCR 10 +#define GCC_UFS_PHY_BCR 11 +#define GCC_USB20_SEC_BCR 12 +#define GCC_USB3_PHY_PRIM_SP0_BCR 13 +#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 14 +#define GCC_SDCC1_BCR 15 +#define GCC_SDCC2_BCR 16 + +/* GCC power domains */ +#define EMAC_GDSC 0 +#define PCIE_0_GDSC 1 +#define UFS_PHY_GDSC 2 +#define USB20_SEC_GDSC 3 +#define USB30_PRIM_GDSC 4 +#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 5 +#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 6 +#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 7 +#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 8 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 9 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 10 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11 + +#endif diff --git a/include/dt-bindings/clock/qcom,qcs8300-camcc.h b/include/dt-bindings/clock/qcom,qcs8300-camcc.h new file mode 100644 index 000000000000..fc535c847859 --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs8300-camcc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_QCS8300_CAM_CC_H +#define _DT_BINDINGS_CLK_QCOM_QCS8300_CAM_CC_H + +#include "qcom,sa8775p-camcc.h" + +/* QCS8300 introduces below new clocks compared to SA8775P */ + +/* CAM_CC clocks */ +#define CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK 86 + +#endif diff --git a/include/dt-bindings/clock/qcom,qcs8300-gpucc.h b/include/dt-bindings/clock/qcom,qcs8300-gpucc.h new file mode 100644 index 000000000000..afa187467b4c --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs8300-gpucc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPUCC_QCS8300_H +#define _DT_BINDINGS_CLK_QCOM_GPUCC_QCS8300_H + +#include "qcom,sa8775p-gpucc.h" + +/* QCS8300 introduces below new clocks compared to SA8775P */ + +/* GPU_CC clocks */ +#define GPU_CC_CX_ACCU_SHIFT_CLK 23 +#define GPU_CC_GX_ACCU_SHIFT_CLK 24 + +#endif diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index 46309c9953b2..1477a75e7f6d 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -170,5 +170,9 @@ #define RPM_SMD_BIMC_FREQ_LOG 124 #define RPM_SMD_LN_BB_CLK_PIN 125 #define RPM_SMD_LN_BB_A_CLK_PIN 126 +#define RPM_SMD_BB_CLK3 127 +#define RPM_SMD_BB_CLK3_A 128 +#define RPM_SMD_BB_CLK3_PIN 129 +#define RPM_SMD_BB_CLK3_A_PIN 130 #endif diff --git a/include/dt-bindings/clock/qcom,sm6115-lpasscc.h b/include/dt-bindings/clock/qcom,sm6115-lpasscc.h new file mode 100644 index 000000000000..799274517c9a --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6115-lpasscc.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Linaro Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SM6115_H +#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SM6115_H + +/* LPASS CC */ +#define LPASS_SWR_TX_CONFIG_CGCR 0 + +/* LPASS_AUDIO CC */ +#define LPASS_AUDIO_SWR_RX_CGCR 0 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm6350-videocc.h b/include/dt-bindings/clock/qcom,sm6350-videocc.h new file mode 100644 index 000000000000..2af7f91fa023 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6350-videocc.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM6350_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM6350_H + +/* VIDEO_CC clocks */ +#define VIDEO_PLL0 0 +#define VIDEO_PLL0_OUT_EVEN 1 +#define VIDEO_CC_IRIS_AHB_CLK 2 +#define VIDEO_CC_IRIS_CLK_SRC 3 +#define VIDEO_CC_MVS0_AXI_CLK 4 +#define VIDEO_CC_MVS0_CORE_CLK 5 +#define VIDEO_CC_MVSC_CORE_CLK 6 +#define VIDEO_CC_MVSC_CTL_AXI_CLK 7 +#define VIDEO_CC_SLEEP_CLK 8 +#define VIDEO_CC_SLEEP_CLK_SRC 9 +#define VIDEO_CC_VENUS_AHB_CLK 10 + +/* GDSCs */ +#define MVSC_GDSC 0 +#define MVS0_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm8750-dispcc.h b/include/dt-bindings/clock/qcom,sm8750-dispcc.h new file mode 100644 index 000000000000..dafb5069c96a --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8750-dispcc.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Linaro Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_SM8750_DISP_CC_H +#define _DT_BINDINGS_CLK_QCOM_SM8750_DISP_CC_H + +/* DISP_CC clocks */ +#define DISP_CC_ESYNC0_CLK 0 +#define DISP_CC_ESYNC0_CLK_SRC 1 +#define DISP_CC_ESYNC1_CLK 2 +#define DISP_CC_ESYNC1_CLK_SRC 3 +#define DISP_CC_MDSS_ACCU_SHIFT_CLK 4 +#define DISP_CC_MDSS_AHB1_CLK 5 +#define DISP_CC_MDSS_AHB_CLK 6 +#define DISP_CC_MDSS_AHB_CLK_SRC 7 +#define DISP_CC_MDSS_BYTE0_CLK 8 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 9 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 10 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 11 +#define DISP_CC_MDSS_BYTE1_CLK 12 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 13 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 14 +#define DISP_CC_MDSS_BYTE1_INTF_CLK 15 +#define DISP_CC_MDSS_DPTX0_AUX_CLK 16 +#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 17 +#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 18 +#define DISP_CC_MDSS_DPTX0_LINK_CLK 19 +#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 20 +#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 21 +#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 22 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 23 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 24 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 25 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 26 +#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 27 +#define DISP_CC_MDSS_DPTX1_AUX_CLK 28 +#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 29 +#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 30 +#define DISP_CC_MDSS_DPTX1_LINK_CLK 31 +#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 32 +#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 33 +#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 34 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 35 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 36 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 37 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 38 +#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 39 +#define DISP_CC_MDSS_DPTX2_AUX_CLK 40 +#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 41 +#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 42 +#define DISP_CC_MDSS_DPTX2_LINK_CLK 43 +#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 44 +#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 45 +#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 46 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 47 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 48 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 49 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 50 +#define DISP_CC_MDSS_DPTX3_AUX_CLK 51 +#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 52 +#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 53 +#define DISP_CC_MDSS_DPTX3_LINK_CLK 54 +#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 55 +#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 56 +#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 57 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 58 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 59 +#define DISP_CC_MDSS_ESC0_CLK 60 +#define DISP_CC_MDSS_ESC0_CLK_SRC 61 +#define DISP_CC_MDSS_ESC1_CLK 62 +#define DISP_CC_MDSS_ESC1_CLK_SRC 63 +#define DISP_CC_MDSS_MDP1_CLK 64 +#define DISP_CC_MDSS_MDP_CLK 65 +#define DISP_CC_MDSS_MDP_CLK_SRC 66 +#define DISP_CC_MDSS_MDP_LUT1_CLK 67 +#define DISP_CC_MDSS_MDP_LUT_CLK 68 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 69 +#define DISP_CC_MDSS_PCLK0_CLK 70 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 71 +#define DISP_CC_MDSS_PCLK1_CLK 72 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 73 +#define DISP_CC_MDSS_PCLK2_CLK 74 +#define DISP_CC_MDSS_PCLK2_CLK_SRC 75 +#define DISP_CC_MDSS_RSCC_AHB_CLK 76 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 77 +#define DISP_CC_MDSS_VSYNC1_CLK 78 +#define DISP_CC_MDSS_VSYNC_CLK 79 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 80 +#define DISP_CC_OSC_CLK 81 +#define DISP_CC_OSC_CLK_SRC 82 +#define DISP_CC_PLL0 83 +#define DISP_CC_PLL1 84 +#define DISP_CC_PLL2 85 +#define DISP_CC_SLEEP_CLK 86 +#define DISP_CC_SLEEP_CLK_SRC 87 +#define DISP_CC_XO_CLK 88 +#define DISP_CC_XO_CLK_SRC 89 + +/* DISP_CC resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_CORE_INT2_BCR 1 +#define DISP_CC_MDSS_RSCC_BCR 2 + +/* DISP_CC GDSCR */ +#define MDSS_GDSC 0 +#define MDSS_INT2_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm8750-gcc.h b/include/dt-bindings/clock/qcom,sm8750-gcc.h new file mode 100644 index 000000000000..e234595d7f42 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8750-gcc.h @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8750_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SM8750_H + +/* GCC clocks */ +#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 1 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 2 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3 +#define GCC_BOOT_ROM_AHB_CLK 4 +#define GCC_CAM_BIST_MCLK_AHB_CLK 5 +#define GCC_CAMERA_AHB_CLK 6 +#define GCC_CAMERA_HF_AXI_CLK 7 +#define GCC_CAMERA_SF_AXI_CLK 8 +#define GCC_CAMERA_XO_CLK 9 +#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 10 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 11 +#define GCC_CNOC_PCIE_SF_AXI_CLK 12 +#define GCC_DDRSS_GPU_AXI_CLK 13 +#define GCC_DDRSS_PCIE_SF_QTB_CLK 14 +#define GCC_DISP_AHB_CLK 15 +#define GCC_DISP_HF_AXI_CLK 16 +#define GCC_EVA_AHB_CLK 17 +#define GCC_EVA_AXI0_CLK 18 +#define GCC_EVA_AXI0C_CLK 19 +#define GCC_EVA_XO_CLK 20 +#define GCC_GP1_CLK 21 +#define GCC_GP1_CLK_SRC 22 +#define GCC_GP2_CLK 23 +#define GCC_GP2_CLK_SRC 24 +#define GCC_GP3_CLK 25 +#define GCC_GP3_CLK_SRC 26 +#define GCC_GPLL0 27 +#define GCC_GPLL0_OUT_EVEN 28 +#define GCC_GPLL1 29 +#define GCC_GPLL4 30 +#define GCC_GPLL7 31 +#define GCC_GPLL9 32 +#define GCC_GPU_CFG_AHB_CLK 33 +#define GCC_GPU_GEMNOC_GFX_CLK 34 +#define GCC_GPU_GPLL0_CLK_SRC 35 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 36 +#define GCC_PCIE_0_AUX_CLK 37 +#define GCC_PCIE_0_AUX_CLK_SRC 38 +#define GCC_PCIE_0_CFG_AHB_CLK 39 +#define GCC_PCIE_0_MSTR_AXI_CLK 40 +#define GCC_PCIE_0_PHY_RCHNG_CLK 41 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42 +#define GCC_PCIE_0_PIPE_CLK 43 +#define GCC_PCIE_0_PIPE_CLK_SRC 44 +#define GCC_PCIE_0_SLV_AXI_CLK 45 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 46 +#define GCC_PCIE_RSCC_CFG_AHB_CLK 47 +#define GCC_PCIE_RSCC_XO_CLK 48 +#define GCC_PDM2_CLK 49 +#define GCC_PDM2_CLK_SRC 50 +#define GCC_PDM_AHB_CLK 51 +#define GCC_PDM_XO4_CLK 52 +#define GCC_QMIP_CAMERA_CMD_AHB_CLK 53 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 54 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 55 +#define GCC_QMIP_GPU_AHB_CLK 56 +#define GCC_QMIP_PCIE_AHB_CLK 57 +#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 58 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 59 +#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 60 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 61 +#define GCC_QUPV3_I2C_CORE_CLK 62 +#define GCC_QUPV3_I2C_S0_CLK 63 +#define GCC_QUPV3_I2C_S0_CLK_SRC 64 +#define GCC_QUPV3_I2C_S1_CLK 65 +#define GCC_QUPV3_I2C_S1_CLK_SRC 66 +#define GCC_QUPV3_I2C_S2_CLK 67 +#define GCC_QUPV3_I2C_S2_CLK_SRC 68 +#define GCC_QUPV3_I2C_S3_CLK 69 +#define GCC_QUPV3_I2C_S3_CLK_SRC 70 +#define GCC_QUPV3_I2C_S4_CLK 71 +#define GCC_QUPV3_I2C_S4_CLK_SRC 72 +#define GCC_QUPV3_I2C_S5_CLK 73 +#define GCC_QUPV3_I2C_S5_CLK_SRC 74 +#define GCC_QUPV3_I2C_S6_CLK 75 +#define GCC_QUPV3_I2C_S6_CLK_SRC 76 +#define GCC_QUPV3_I2C_S7_CLK 77 +#define GCC_QUPV3_I2C_S7_CLK_SRC 78 +#define GCC_QUPV3_I2C_S8_CLK 79 +#define GCC_QUPV3_I2C_S8_CLK_SRC 80 +#define GCC_QUPV3_I2C_S9_CLK 81 +#define GCC_QUPV3_I2C_S9_CLK_SRC 82 +#define GCC_QUPV3_I2C_S_AHB_CLK 83 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 84 +#define GCC_QUPV3_WRAP1_CORE_CLK 85 +#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 86 +#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 87 +#define GCC_QUPV3_WRAP1_S0_CLK 88 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 89 +#define GCC_QUPV3_WRAP1_S1_CLK 90 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 91 +#define GCC_QUPV3_WRAP1_S2_CLK 92 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 93 +#define GCC_QUPV3_WRAP1_S3_CLK 94 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 95 +#define GCC_QUPV3_WRAP1_S4_CLK 96 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 97 +#define GCC_QUPV3_WRAP1_S5_CLK 98 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 99 +#define GCC_QUPV3_WRAP1_S6_CLK 100 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 101 +#define GCC_QUPV3_WRAP1_S7_CLK 102 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 103 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 104 +#define GCC_QUPV3_WRAP2_CORE_CLK 105 +#define GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC 106 +#define GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK 107 +#define GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK 108 +#define GCC_QUPV3_WRAP2_S0_CLK 109 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 110 +#define GCC_QUPV3_WRAP2_S1_CLK 111 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 112 +#define GCC_QUPV3_WRAP2_S2_CLK 113 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 114 +#define GCC_QUPV3_WRAP2_S3_CLK 115 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 116 +#define GCC_QUPV3_WRAP2_S4_CLK 117 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 118 +#define GCC_QUPV3_WRAP2_S5_CLK 119 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 120 +#define GCC_QUPV3_WRAP2_S6_CLK 121 +#define GCC_QUPV3_WRAP2_S6_CLK_SRC 122 +#define GCC_QUPV3_WRAP2_S7_CLK 123 +#define GCC_QUPV3_WRAP2_S7_CLK_SRC 124 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 125 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 126 +#define GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK 127 +#define GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK 128 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 129 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 130 +#define GCC_SDCC2_AHB_CLK 131 +#define GCC_SDCC2_APPS_CLK 132 +#define GCC_SDCC2_APPS_CLK_SRC 133 +#define GCC_SDCC4_AHB_CLK 134 +#define GCC_SDCC4_APPS_CLK 135 +#define GCC_SDCC4_APPS_CLK_SRC 136 +#define GCC_UFS_PHY_AHB_CLK 137 +#define GCC_UFS_PHY_AXI_CLK 138 +#define GCC_UFS_PHY_AXI_CLK_SRC 139 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 140 +#define GCC_UFS_PHY_ICE_CORE_CLK 141 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 142 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 143 +#define GCC_UFS_PHY_PHY_AUX_CLK 144 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 145 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 146 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 147 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 148 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 149 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 150 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 151 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 152 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 153 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 154 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 155 +#define GCC_USB30_PRIM_MASTER_CLK 156 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 157 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 158 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 159 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 160 +#define GCC_USB30_PRIM_SLEEP_CLK 161 +#define GCC_USB3_PRIM_PHY_AUX_CLK 162 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 163 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 164 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 165 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 166 +#define GCC_VIDEO_AHB_CLK 167 +#define GCC_VIDEO_AXI0_CLK 168 +#define GCC_VIDEO_AXI1_CLK 169 +#define GCC_VIDEO_XO_CLK 170 + +/* GCC power domains */ +#define GCC_PCIE_0_GDSC 0 +#define GCC_PCIE_0_PHY_GDSC 1 +#define GCC_UFS_MEM_PHY_GDSC 2 +#define GCC_UFS_PHY_GDSC 3 +#define GCC_USB30_PRIM_GDSC 4 +#define GCC_USB3_PHY_GDSC 5 + +/* GCC resets */ +#define GCC_CAMERA_BCR 0 +#define GCC_DISPLAY_BCR 1 +#define GCC_EVA_BCR 2 +#define GCC_GPU_BCR 3 +#define GCC_PCIE_0_BCR 4 +#define GCC_PCIE_0_LINK_DOWN_BCR 5 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6 +#define GCC_PCIE_0_PHY_BCR 7 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8 +#define GCC_PCIE_PHY_BCR 9 +#define GCC_PCIE_PHY_CFG_AHB_BCR 10 +#define GCC_PCIE_PHY_COM_BCR 11 +#define GCC_PCIE_RSCC_BCR 12 +#define GCC_PDM_BCR 13 +#define GCC_QUPV3_WRAPPER_1_BCR 14 +#define GCC_QUPV3_WRAPPER_2_BCR 15 +#define GCC_QUPV3_WRAPPER_I2C_BCR 16 +#define GCC_QUSB2PHY_PRIM_BCR 17 +#define GCC_QUSB2PHY_SEC_BCR 18 +#define GCC_SDCC2_BCR 19 +#define GCC_SDCC4_BCR 20 +#define GCC_UFS_PHY_BCR 21 +#define GCC_USB30_PRIM_BCR 22 +#define GCC_USB3_DP_PHY_PRIM_BCR 23 +#define GCC_USB3_DP_PHY_SEC_BCR 24 +#define GCC_USB3_PHY_PRIM_BCR 25 +#define GCC_USB3_PHY_SEC_BCR 26 +#define GCC_USB3PHY_PHY_PRIM_BCR 27 +#define GCC_USB3PHY_PHY_SEC_BCR 28 +#define GCC_VIDEO_AXI0_CLK_ARES 29 +#define GCC_VIDEO_AXI1_CLK_ARES 30 +#define GCC_VIDEO_BCR 31 +#define GCC_EVA_AXI0_CLK_ARES 32 +#define GCC_EVA_AXI0C_CLK_ARES 33 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm8750-tcsr.h b/include/dt-bindings/clock/qcom,sm8750-tcsr.h new file mode 100644 index 000000000000..1c502ac7c7f4 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8750-tcsr.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8750_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8750_H + +/* TCSR_CC clocks */ +#define TCSR_PCIE_0_CLKREF_EN 0 +#define TCSR_UFS_CLKREF_EN 1 +#define TCSR_USB2_CLKREF_EN 2 +#define TCSR_USB3_CLKREF_EN 3 + +#endif diff --git a/include/dt-bindings/clock/qcom,x1e80100-gpucc.h b/include/dt-bindings/clock/qcom,x1e80100-gpucc.h index 61a3a8f3ac43..27b8f50541fd 100644 --- a/include/dt-bindings/clock/qcom,x1e80100-gpucc.h +++ b/include/dt-bindings/clock/qcom,x1e80100-gpucc.h @@ -33,9 +33,22 @@ #define GPU_CC_SLEEP_CLK 23 #define GPU_CC_XO_CLK_SRC 24 #define GPU_CC_XO_DIV_CLK_SRC 25 +#define GPU_CC_CX_ACCU_SHIFT_CLK 26 +#define GPU_CC_GX_ACCU_SHIFT_CLK 27 /* GDSCs */ #define GPU_CX_GDSC 0 #define GPU_GX_GDSC 1 +/* GPU_CC resets */ +#define GPU_CC_ACD_BCR 0 +#define GPU_CC_CB_BCR 1 +#define GPU_CC_CX_BCR 2 +#define GPU_CC_FAST_HUB_BCR 3 +#define GPU_CC_FF_BCR 4 +#define GPU_CC_GFX3D_AON_BCR 5 +#define GPU_CC_GMU_BCR 6 +#define GPU_CC_GX_BCR 7 +#define GPU_CC_XO_BCR 8 + #endif diff --git a/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h index 67774eafad06..4cc8fc34b23c 100644 --- a/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h +++ b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h @@ -2,12 +2,12 @@ * * Copyright (C) 2024 Renesas Electronics Corp. */ -#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ -#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A08G045_VBATTB_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A08G045_VBATTB_H__ #define VBATTB_XC 0 #define VBATTB_XBYP 1 #define VBATTB_MUX 2 #define VBATTB_VBATTCLK 3 -#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */ +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A08G045_VBATTB_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h new file mode 100644 index 000000000000..a27132f9a6c8 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* Core Clock list */ +#define R9A09G047_SYS_0_PCLK 0 +#define R9A09G047_CA55_0_CORECLK0 1 +#define R9A09G047_CA55_0_CORECLK1 2 +#define R9A09G047_CA55_0_CORECLK2 3 +#define R9A09G047_CA55_0_CORECLK3 4 +#define R9A09G047_CA55_0_PERIPHCLK 5 +#define R9A09G047_CM33_CLK0 6 +#define R9A09G047_CST_0_SWCLKTCK 7 +#define R9A09G047_IOTOP_0_SHCLK 8 +#define R9A09G047_SPI_CLK_SPI 9 +#define R9A09G047_GBETH_0_CLK_PTP_REF_I 10 +#define R9A09G047_GBETH_1_CLK_PTP_REF_I 11 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g056-cpg.h b/include/dt-bindings/clock/renesas,r9a09g056-cpg.h new file mode 100644 index 000000000000..f4905b27f8d9 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a09g056-cpg.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* Core Clock list */ +#define R9A09G056_SYS_0_PCLK 0 +#define R9A09G056_CA55_0_CORE_CLK0 1 +#define R9A09G056_CA55_0_CORE_CLK1 2 +#define R9A09G056_CA55_0_CORE_CLK2 3 +#define R9A09G056_CA55_0_CORE_CLK3 4 +#define R9A09G056_CA55_0_PERIPHCLK 5 +#define R9A09G056_CM33_CLK0 6 +#define R9A09G056_CST_0_SWCLKTCK 7 +#define R9A09G056_IOTOP_0_SHCLK 8 +#define R9A09G056_USB2_0_CLK_CORE0 9 +#define R9A09G056_GBETH_0_CLK_PTP_REF_I 10 +#define R9A09G056_GBETH_1_CLK_PTP_REF_I 11 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h index 541e6d719bd6..884dbeb1e139 100644 --- a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h +++ b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h @@ -17,5 +17,9 @@ #define R9A09G057_CM33_CLK0 6 #define R9A09G057_CST_0_SWCLKTCK 7 #define R9A09G057_IOTOP_0_SHCLK 8 +#define R9A09G057_USB2_0_CLK_CORE0 9 +#define R9A09G057_USB2_0_CLK_CORE1 10 +#define R9A09G057_GBETH_0_CLK_PTP_REF_I 11 +#define R9A09G057_GBETH_1_CLK_PTP_REF_I 12 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */ diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h index 99cc617e1e54..5cbc0e2b08ff 100644 --- a/include/dt-bindings/clock/rk3036-cru.h +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -47,6 +47,7 @@ #define SCLK_MACREF 152 #define SCLK_MACPLL 153 #define SCLK_SFC 160 +#define SCLK_USB480M 161 /* aclk gates */ #define ACLK_DMAC2 194 diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index 01e14ab252a7..dd988cc9d582 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -103,6 +103,8 @@ #define PCLK_PERI 351 #define PCLK_DDRUPCTL 352 #define PCLK_PUBL 353 +#define PCLK_CIF0 354 +#define PCLK_CIF1 355 /* hclk gates */ #define HCLK_SDMMC 448 diff --git a/include/dt-bindings/clock/rockchip,rk3528-cru.h b/include/dt-bindings/clock/rockchip,rk3528-cru.h new file mode 100644 index 000000000000..0245a53fc334 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3528-cru.h @@ -0,0 +1,459 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> + * Author: Joseph Chen <chenjh@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H + +/* cru-clocks indices */ +#define PLL_APLL 0 +#define PLL_CPLL 1 +#define PLL_GPLL 2 +#define PLL_PPLL 3 +#define PLL_DPLL 4 +#define ARMCLK 5 +#define XIN_OSC0_HALF 6 +#define CLK_MATRIX_50M_SRC 7 +#define CLK_MATRIX_100M_SRC 8 +#define CLK_MATRIX_150M_SRC 9 +#define CLK_MATRIX_200M_SRC 10 +#define CLK_MATRIX_250M_SRC 11 +#define CLK_MATRIX_300M_SRC 12 +#define CLK_MATRIX_339M_SRC 13 +#define CLK_MATRIX_400M_SRC 14 +#define CLK_MATRIX_500M_SRC 15 +#define CLK_MATRIX_600M_SRC 16 +#define CLK_UART0_SRC 17 +#define CLK_UART0_FRAC 18 +#define SCLK_UART0 19 +#define CLK_UART1_SRC 20 +#define CLK_UART1_FRAC 21 +#define SCLK_UART1 22 +#define CLK_UART2_SRC 23 +#define CLK_UART2_FRAC 24 +#define SCLK_UART2 25 +#define CLK_UART3_SRC 26 +#define CLK_UART3_FRAC 27 +#define SCLK_UART3 28 +#define CLK_UART4_SRC 29 +#define CLK_UART4_FRAC 30 +#define SCLK_UART4 31 +#define CLK_UART5_SRC 32 +#define CLK_UART5_FRAC 33 +#define SCLK_UART5 34 +#define CLK_UART6_SRC 35 +#define CLK_UART6_FRAC 36 +#define SCLK_UART6 37 +#define CLK_UART7_SRC 38 +#define CLK_UART7_FRAC 39 +#define SCLK_UART7 40 +#define CLK_I2S0_2CH_SRC 41 +#define CLK_I2S0_2CH_FRAC 42 +#define MCLK_I2S0_2CH_SAI_SRC 43 +#define CLK_I2S3_8CH_SRC 44 +#define CLK_I2S3_8CH_FRAC 45 +#define MCLK_I2S3_8CH_SAI_SRC 46 +#define CLK_I2S1_8CH_SRC 47 +#define CLK_I2S1_8CH_FRAC 48 +#define MCLK_I2S1_8CH_SAI_SRC 49 +#define CLK_I2S2_2CH_SRC 50 +#define CLK_I2S2_2CH_FRAC 51 +#define MCLK_I2S2_2CH_SAI_SRC 52 +#define CLK_SPDIF_SRC 53 +#define CLK_SPDIF_FRAC 54 +#define MCLK_SPDIF_SRC 55 +#define DCLK_VOP_SRC0 56 +#define DCLK_VOP_SRC1 57 +#define CLK_HSM 58 +#define CLK_CORE_SRC_ACS 59 +#define CLK_CORE_SRC_PVTMUX 60 +#define CLK_CORE_SRC 61 +#define CLK_CORE 62 +#define ACLK_M_CORE_BIU 63 +#define CLK_CORE_PVTPLL_SRC 64 +#define PCLK_DBG 65 +#define SWCLKTCK 66 +#define CLK_SCANHS_CORE 67 +#define CLK_SCANHS_ACLKM_CORE 68 +#define CLK_SCANHS_PCLK_DBG 69 +#define CLK_SCANHS_PCLK_CPU_BIU 70 +#define PCLK_CPU_ROOT 71 +#define PCLK_CORE_GRF 72 +#define PCLK_DAPLITE_BIU 73 +#define PCLK_CPU_BIU 74 +#define CLK_REF_PVTPLL_CORE 75 +#define ACLK_BUS_VOPGL_ROOT 76 +#define ACLK_BUS_VOPGL_BIU 77 +#define ACLK_BUS_H_ROOT 78 +#define ACLK_BUS_H_BIU 79 +#define ACLK_BUS_ROOT 80 +#define HCLK_BUS_ROOT 81 +#define PCLK_BUS_ROOT 82 +#define ACLK_BUS_M_ROOT 83 +#define ACLK_SYSMEM_BIU 84 +#define CLK_TIMER_ROOT 85 +#define ACLK_BUS_BIU 86 +#define HCLK_BUS_BIU 87 +#define PCLK_BUS_BIU 88 +#define PCLK_DFT2APB 89 +#define PCLK_BUS_GRF 90 +#define ACLK_BUS_M_BIU 91 +#define ACLK_GIC 92 +#define ACLK_SPINLOCK 93 +#define ACLK_DMAC 94 +#define PCLK_TIMER 95 +#define CLK_TIMER0 96 +#define CLK_TIMER1 97 +#define CLK_TIMER2 98 +#define CLK_TIMER3 99 +#define CLK_TIMER4 100 +#define CLK_TIMER5 101 +#define PCLK_JDBCK_DAP 102 +#define CLK_JDBCK_DAP 103 +#define PCLK_WDT_NS 104 +#define TCLK_WDT_NS 105 +#define HCLK_TRNG_NS 106 +#define PCLK_UART0 107 +#define PCLK_DMA2DDR 108 +#define ACLK_DMA2DDR 109 +#define PCLK_PWM0 110 +#define CLK_PWM0 111 +#define CLK_CAPTURE_PWM0 112 +#define PCLK_PWM1 113 +#define CLK_PWM1 114 +#define CLK_CAPTURE_PWM1 115 +#define PCLK_SCR 116 +#define ACLK_DCF 117 +#define PCLK_INTMUX 118 +#define CLK_PPLL_I 119 +#define CLK_PPLL_MUX 120 +#define CLK_PPLL_100M_MATRIX 121 +#define CLK_PPLL_50M_MATRIX 122 +#define CLK_REF_PCIE_INNER_PHY 123 +#define CLK_REF_PCIE_100M_PHY 124 +#define ACLK_VPU_L_ROOT 125 +#define CLK_GMAC1_VPU_25M 126 +#define CLK_PPLL_125M_MATRIX 127 +#define ACLK_VPU_ROOT 128 +#define HCLK_VPU_ROOT 129 +#define PCLK_VPU_ROOT 130 +#define ACLK_VPU_BIU 131 +#define HCLK_VPU_BIU 132 +#define PCLK_VPU_BIU 133 +#define ACLK_VPU 134 +#define HCLK_VPU 135 +#define PCLK_CRU_PCIE 136 +#define PCLK_VPU_GRF 137 +#define HCLK_SFC 138 +#define SCLK_SFC 139 +#define CCLK_SRC_EMMC 140 +#define HCLK_EMMC 141 +#define ACLK_EMMC 142 +#define BCLK_EMMC 143 +#define TCLK_EMMC 144 +#define PCLK_GPIO1 145 +#define DBCLK_GPIO1 146 +#define ACLK_VPU_L_BIU 147 +#define PCLK_VPU_IOC 148 +#define HCLK_SAI_I2S0 149 +#define MCLK_SAI_I2S0 150 +#define HCLK_SAI_I2S2 151 +#define MCLK_SAI_I2S2 152 +#define PCLK_ACODEC 153 +#define MCLK_ACODEC_TX 154 +#define PCLK_GPIO3 155 +#define DBCLK_GPIO3 156 +#define PCLK_SPI1 157 +#define CLK_SPI1 158 +#define SCLK_IN_SPI1 159 +#define PCLK_UART2 160 +#define PCLK_UART5 161 +#define PCLK_UART6 162 +#define PCLK_UART7 163 +#define PCLK_I2C3 164 +#define CLK_I2C3 165 +#define PCLK_I2C5 166 +#define CLK_I2C5 167 +#define PCLK_I2C6 168 +#define CLK_I2C6 169 +#define ACLK_MAC_VPU 170 +#define PCLK_MAC_VPU 171 +#define CLK_GMAC1_RMII_VPU 172 +#define CLK_GMAC1_SRC_VPU 173 +#define PCLK_PCIE 174 +#define CLK_PCIE_AUX 175 +#define ACLK_PCIE 176 +#define HCLK_PCIE_SLV 177 +#define HCLK_PCIE_DBI 178 +#define PCLK_PCIE_PHY 179 +#define PCLK_PIPE_GRF 180 +#define CLK_PIPE_USB3OTG_COMBO 181 +#define CLK_UTMI_USB3OTG 182 +#define CLK_PCIE_PIPE_PHY 183 +#define CCLK_SRC_SDIO0 184 +#define HCLK_SDIO0 185 +#define CCLK_SRC_SDIO1 186 +#define HCLK_SDIO1 187 +#define CLK_TS_0 188 +#define CLK_TS_1 189 +#define PCLK_CAN2 190 +#define CLK_CAN2 191 +#define PCLK_CAN3 192 +#define CLK_CAN3 193 +#define PCLK_SARADC 194 +#define CLK_SARADC 195 +#define PCLK_TSADC 196 +#define CLK_TSADC 197 +#define CLK_TSADC_TSEN 198 +#define ACLK_USB3OTG 199 +#define CLK_REF_USB3OTG 200 +#define CLK_SUSPEND_USB3OTG 201 +#define ACLK_GPU_ROOT 202 +#define PCLK_GPU_ROOT 203 +#define ACLK_GPU_BIU 204 +#define PCLK_GPU_BIU 205 +#define ACLK_GPU 206 +#define CLK_GPU_PVTPLL_SRC 207 +#define ACLK_GPU_MALI 208 +#define HCLK_RKVENC_ROOT 209 +#define ACLK_RKVENC_ROOT 210 +#define PCLK_RKVENC_ROOT 211 +#define HCLK_RKVENC_BIU 212 +#define ACLK_RKVENC_BIU 213 +#define PCLK_RKVENC_BIU 214 +#define HCLK_RKVENC 215 +#define ACLK_RKVENC 216 +#define CLK_CORE_RKVENC 217 +#define HCLK_SAI_I2S1 218 +#define MCLK_SAI_I2S1 219 +#define PCLK_I2C1 220 +#define CLK_I2C1 221 +#define PCLK_I2C0 222 +#define CLK_I2C0 223 +#define CLK_UART_JTAG 224 +#define PCLK_SPI0 225 +#define CLK_SPI0 226 +#define SCLK_IN_SPI0 227 +#define PCLK_GPIO4 228 +#define DBCLK_GPIO4 229 +#define PCLK_RKVENC_IOC 230 +#define HCLK_SPDIF 231 +#define MCLK_SPDIF 232 +#define HCLK_PDM 233 +#define MCLK_PDM 234 +#define PCLK_UART1 235 +#define PCLK_UART3 236 +#define PCLK_RKVENC_GRF 237 +#define PCLK_CAN0 238 +#define CLK_CAN0 239 +#define PCLK_CAN1 240 +#define CLK_CAN1 241 +#define ACLK_VO_ROOT 242 +#define HCLK_VO_ROOT 243 +#define PCLK_VO_ROOT 244 +#define ACLK_VO_BIU 245 +#define HCLK_VO_BIU 246 +#define PCLK_VO_BIU 247 +#define HCLK_RGA2E 248 +#define ACLK_RGA2E 249 +#define CLK_CORE_RGA2E 250 +#define HCLK_VDPP 251 +#define ACLK_VDPP 252 +#define CLK_CORE_VDPP 253 +#define PCLK_VO_GRF 254 +#define PCLK_CRU 255 +#define ACLK_VOP_ROOT 256 +#define ACLK_VOP_BIU 257 +#define HCLK_VOP 258 +#define DCLK_VOP0 259 +#define DCLK_VOP1 260 +#define ACLK_VOP 261 +#define PCLK_HDMI 262 +#define CLK_SFR_HDMI 263 +#define CLK_CEC_HDMI 264 +#define CLK_SPDIF_HDMI 265 +#define CLK_HDMIPHY_TMDSSRC 266 +#define CLK_HDMIPHY_PREP 267 +#define PCLK_HDMIPHY 268 +#define HCLK_HDCP_KEY 269 +#define ACLK_HDCP 270 +#define HCLK_HDCP 271 +#define PCLK_HDCP 272 +#define HCLK_CVBS 273 +#define DCLK_CVBS 274 +#define DCLK_4X_CVBS 275 +#define ACLK_JPEG_DECODER 276 +#define HCLK_JPEG_DECODER 277 +#define ACLK_VO_L_ROOT 278 +#define ACLK_VO_L_BIU 279 +#define ACLK_MAC_VO 280 +#define PCLK_MAC_VO 281 +#define CLK_GMAC0_SRC 282 +#define CLK_GMAC0_RMII_50M 283 +#define CLK_GMAC0_TX 284 +#define CLK_GMAC0_RX 285 +#define ACLK_JPEG_ROOT 286 +#define ACLK_JPEG_BIU 287 +#define HCLK_SAI_I2S3 288 +#define MCLK_SAI_I2S3 289 +#define CLK_MACPHY 290 +#define PCLK_VCDCPHY 291 +#define PCLK_GPIO2 292 +#define DBCLK_GPIO2 293 +#define PCLK_VO_IOC 294 +#define CCLK_SRC_SDMMC0 295 +#define HCLK_SDMMC0 296 +#define PCLK_OTPC_NS 297 +#define CLK_SBPI_OTPC_NS 298 +#define CLK_USER_OTPC_NS 299 +#define CLK_HDMIHDP0 300 +#define HCLK_USBHOST 301 +#define HCLK_USBHOST_ARB 302 +#define CLK_USBHOST_OHCI 303 +#define CLK_USBHOST_UTMI 304 +#define PCLK_UART4 305 +#define PCLK_I2C4 306 +#define CLK_I2C4 307 +#define PCLK_I2C7 308 +#define CLK_I2C7 309 +#define PCLK_USBPHY 310 +#define CLK_REF_USBPHY 311 +#define HCLK_RKVDEC_ROOT 312 +#define ACLK_RKVDEC_ROOT_NDFT 313 +#define PCLK_DDRPHY_CRU 314 +#define HCLK_RKVDEC_BIU 315 +#define ACLK_RKVDEC_BIU 316 +#define ACLK_RKVDEC 317 +#define HCLK_RKVDEC 318 +#define CLK_HEVC_CA_RKVDEC 319 +#define ACLK_RKVDEC_PVTMUX_ROOT 320 +#define CLK_RKVDEC_PVTPLL_SRC 321 +#define PCLK_DDR_ROOT 322 +#define PCLK_DDR_BIU 323 +#define PCLK_DDRC 324 +#define PCLK_DDRMON 325 +#define CLK_TIMER_DDRMON 326 +#define PCLK_MSCH_BIU 327 +#define PCLK_DDR_GRF 328 +#define PCLK_DDR_HWLP 329 +#define PCLK_DDRPHY 330 +#define CLK_MSCH_BIU 331 +#define ACLK_DDR_UPCTL 332 +#define CLK_DDR_UPCTL 333 +#define CLK_DDRMON 334 +#define ACLK_DDR_SCRAMBLE 335 +#define ACLK_SPLIT 336 +#define CLK_DDRC_SRC 337 +#define CLK_DDR_PHY 338 +#define PCLK_OTPC_S 339 +#define CLK_SBPI_OTPC_S 340 +#define CLK_USER_OTPC_S 341 +#define PCLK_KEYREADER 342 +#define PCLK_BUS_SGRF 343 +#define PCLK_STIMER 344 +#define CLK_STIMER0 345 +#define CLK_STIMER1 346 +#define PCLK_WDT_S 347 +#define TCLK_WDT_S 348 +#define HCLK_TRNG_S 349 +#define HCLK_BOOTROM 350 +#define PCLK_DCF 351 +#define ACLK_SYSMEM 352 +#define HCLK_TSP 353 +#define ACLK_TSP 354 +#define CLK_CORE_TSP 355 +#define CLK_OTPC_ARB 356 +#define PCLK_OTP_MASK 357 +#define CLK_PMC_OTP 358 +#define PCLK_PMU_ROOT 359 +#define HCLK_PMU_ROOT 360 +#define PCLK_I2C2 361 +#define CLK_I2C2 362 +#define HCLK_PMU_BIU 363 +#define PCLK_PMU_BIU 364 +#define FCLK_MCU 365 +#define RTC_CLK_MCU 366 +#define PCLK_OSCCHK 367 +#define CLK_PMU_MCU_JTAG 368 +#define PCLK_PMU 369 +#define PCLK_GPIO0 370 +#define DBCLK_GPIO0 371 +#define XIN_OSC0_DIV 372 +#define CLK_DEEPSLOW 373 +#define CLK_DDR_FAIL_SAFE 374 +#define PCLK_PMU_HP_TIMER 375 +#define CLK_PMU_HP_TIMER 376 +#define CLK_PMU_32K_HP_TIMER 377 +#define PCLK_PMU_IOC 378 +#define PCLK_PMU_CRU 379 +#define PCLK_PMU_GRF 380 +#define PCLK_PMU_WDT 381 +#define TCLK_PMU_WDT 382 +#define PCLK_PMU_MAILBOX 383 +#define PCLK_SCRKEYGEN 384 +#define CLK_SCRKEYGEN 385 +#define CLK_PVTM_OSCCHK 386 +#define CLK_REFOUT 387 +#define CLK_PVTM_PMU 388 +#define PCLK_PVTM_PMU 389 +#define PCLK_PMU_SGRF 390 +#define HCLK_PMU_SRAM 391 +#define CLK_UART0 392 +#define CLK_UART1 393 +#define CLK_UART2 394 +#define CLK_UART3 395 +#define CLK_UART4 396 +#define CLK_UART5 397 +#define CLK_UART6 398 +#define CLK_UART7 399 +#define MCLK_I2S0_2CH_SAI_SRC_PRE 400 +#define MCLK_I2S1_8CH_SAI_SRC_PRE 401 +#define MCLK_I2S2_2CH_SAI_SRC_PRE 402 +#define MCLK_I2S3_8CH_SAI_SRC_PRE 403 +#define MCLK_SDPDIF_SRC_PRE 404 +#define SCLK_SDMMC_DRV 405 +#define SCLK_SDMMC_SAMPLE 406 +#define SCLK_SDIO0_DRV 407 +#define SCLK_SDIO0_SAMPLE 408 +#define SCLK_SDIO1_DRV 409 +#define SCLK_SDIO1_SAMPLE 410 + +/* scmi-clocks indices */ +#define SCMI_PCLK_KEYREADER 0 +#define SCMI_HCLK_KLAD 1 +#define SCMI_PCLK_KLAD 2 +#define SCMI_HCLK_TRNG_S 3 +#define SCMI_HCLK_CRYPTO_S 4 +#define SCMI_PCLK_WDT_S 5 +#define SCMI_TCLK_WDT_S 6 +#define SCMI_PCLK_STIMER 7 +#define SCMI_CLK_STIMER0 8 +#define SCMI_CLK_STIMER1 9 +#define SCMI_PCLK_OTP_MASK 10 +#define SCMI_PCLK_OTPC_S 11 +#define SCMI_CLK_SBPI_OTPC_S 12 +#define SCMI_CLK_USER_OTPC_S 13 +#define SCMI_CLK_PMC_OTP 14 +#define SCMI_CLK_OTPC_ARB 15 +#define SCMI_CLK_CORE_TSP 16 +#define SCMI_ACLK_TSP 17 +#define SCMI_HCLK_TSP 18 +#define SCMI_PCLK_DCF 19 +#define SCMI_CLK_DDR 20 +#define SCMI_CLK_CPU 21 +#define SCMI_CLK_GPU 22 +#define SCMI_CORE_CRYPTO 23 +#define SCMI_ACLK_CRYPTO 24 +#define SCMI_PKA_CRYPTO 25 +#define SCMI_HCLK_CRYPTO 26 +#define SCMI_CORE_CRYPTO_S 27 +#define SCMI_ACLK_CRYPTO_S 28 +#define SCMI_PKA_CRYPTO_S 29 +#define SCMI_CORE_KLAD 30 +#define SCMI_ACLK_KLAD 31 +#define SCMI_HCLK_TRNG 32 + +#endif // _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H diff --git a/include/dt-bindings/clock/rockchip,rk3562-cru.h b/include/dt-bindings/clock/rockchip,rk3562-cru.h new file mode 100644 index 000000000000..a5b0b153209c --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3562-cru.h @@ -0,0 +1,379 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022-2025 Rockchip Electronics Co., Ltd. + * Author: Finley Xiao <finley.xiao@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H + +/* cru-clocks indices */ + +/* cru plls */ +#define PLL_DMPLL0 0 +#define PLL_APLL 1 +#define PLL_GPLL 2 +#define PLL_VPLL 3 +#define PLL_HPLL 4 +#define PLL_CPLL 5 +#define PLL_DPLL 6 +#define PLL_DMPLL1 7 + +/* cru clocks */ +#define ARMCLK 8 +#define CLK_GPU 9 +#define ACLK_RKNN 10 +#define CLK_DDR 11 +#define CLK_MATRIX_50M_SRC 12 +#define CLK_MATRIX_100M_SRC 13 +#define CLK_MATRIX_125M_SRC 14 +#define CLK_MATRIX_200M_SRC 15 +#define CLK_MATRIX_300M_SRC 16 +#define ACLK_TOP 17 +#define ACLK_TOP_VIO 18 +#define CLK_CAM0_OUT2IO 19 +#define CLK_CAM1_OUT2IO 20 +#define CLK_CAM2_OUT2IO 21 +#define CLK_CAM3_OUT2IO 22 +#define ACLK_BUS 23 +#define HCLK_BUS 24 +#define PCLK_BUS 25 +#define PCLK_I2C1 26 +#define PCLK_I2C2 27 +#define PCLK_I2C3 28 +#define PCLK_I2C4 29 +#define PCLK_I2C5 30 +#define CLK_I2C 31 +#define CLK_I2C1 32 +#define CLK_I2C2 33 +#define CLK_I2C3 34 +#define CLK_I2C4 35 +#define CLK_I2C5 36 +#define DCLK_BUS_GPIO 37 +#define DCLK_BUS_GPIO3 38 +#define DCLK_BUS_GPIO4 39 +#define PCLK_TIMER 40 +#define CLK_TIMER0 41 +#define CLK_TIMER1 42 +#define CLK_TIMER2 43 +#define CLK_TIMER3 44 +#define CLK_TIMER4 45 +#define CLK_TIMER5 46 +#define PCLK_STIMER 47 +#define CLK_STIMER0 48 +#define CLK_STIMER1 49 +#define PCLK_WDTNS 50 +#define CLK_WDTNS 51 +#define PCLK_GRF 52 +#define PCLK_SGRF 53 +#define PCLK_MAILBOX 54 +#define PCLK_INTC 55 +#define ACLK_BUS_GIC400 56 +#define ACLK_BUS_SPINLOCK 57 +#define ACLK_DCF 58 +#define PCLK_DCF 59 +#define FCLK_BUS_CM0_CORE 60 +#define CLK_BUS_CM0_RTC 61 +#define HCLK_ICACHE 62 +#define HCLK_DCACHE 63 +#define PCLK_TSADC 64 +#define CLK_TSADC 65 +#define CLK_TSADC_TSEN 66 +#define PCLK_DFT2APB 67 +#define CLK_SARADC_VCCIO156 68 +#define PCLK_GMAC 69 +#define ACLK_GMAC 70 +#define CLK_GMAC_125M_CRU_I 71 +#define CLK_GMAC_50M_CRU_I 72 +#define CLK_GMAC_50M_O 73 +#define CLK_GMAC_ETH_OUT2IO 74 +#define PCLK_APB2ASB_VCCIO156 75 +#define PCLK_TO_VCCIO156 76 +#define PCLK_DSIPHY 77 +#define PCLK_DSITX 78 +#define PCLK_CPU_EMA_DET 79 +#define PCLK_HASH 80 +#define PCLK_TOPCRU 81 +#define PCLK_ASB2APB_VCCIO156 82 +#define PCLK_IOC_VCCIO156 83 +#define PCLK_GPIO3_VCCIO156 84 +#define PCLK_GPIO4_VCCIO156 85 +#define PCLK_SARADC_VCCIO156 86 +#define PCLK_MAC100 87 +#define ACLK_MAC100 89 +#define CLK_MAC100_50M_MATRIX 90 +#define HCLK_CORE 91 +#define PCLK_DDR 92 +#define CLK_MSCH_BRG_BIU 93 +#define PCLK_DDR_HWLP 94 +#define PCLK_DDR_UPCTL 95 +#define PCLK_DDR_PHY 96 +#define PCLK_DDR_DFICTL 97 +#define PCLK_DDR_DMA2DDR 98 +#define PCLK_DDR_MON 99 +#define TMCLK_DDR_MON 100 +#define PCLK_DDR_GRF 101 +#define PCLK_DDR_CRU 102 +#define PCLK_SUBDDR_CRU 103 +#define CLK_GPU_PRE 104 +#define ACLK_GPU_PRE 105 +#define CLK_GPU_BRG 107 +#define CLK_NPU_PRE 108 +#define HCLK_NPU_PRE 109 +#define HCLK_RKNN 111 +#define ACLK_PERI 112 +#define HCLK_PERI 113 +#define PCLK_PERI 114 +#define PCLK_PERICRU 115 +#define HCLK_SAI0 116 +#define CLK_SAI0_SRC 117 +#define CLK_SAI0_FRAC 118 +#define CLK_SAI0 119 +#define MCLK_SAI0 120 +#define MCLK_SAI0_OUT2IO 121 +#define HCLK_SAI1 122 +#define CLK_SAI1_SRC 123 +#define CLK_SAI1_FRAC 124 +#define CLK_SAI1 125 +#define MCLK_SAI1 126 +#define MCLK_SAI1_OUT2IO 127 +#define HCLK_SAI2 128 +#define CLK_SAI2_SRC 129 +#define CLK_SAI2_FRAC 130 +#define CLK_SAI2 131 +#define MCLK_SAI2 132 +#define MCLK_SAI2_OUT2IO 133 +#define HCLK_DSM 134 +#define CLK_DSM 135 +#define HCLK_PDM 136 +#define MCLK_PDM 137 +#define HCLK_SPDIF 138 +#define CLK_SPDIF_SRC 139 +#define CLK_SPDIF_FRAC 140 +#define CLK_SPDIF 141 +#define MCLK_SPDIF 142 +#define HCLK_SDMMC0 143 +#define CCLK_SDMMC0 144 +#define HCLK_SDMMC1 145 +#define CCLK_SDMMC1 146 +#define SCLK_SDMMC0_DRV 147 +#define SCLK_SDMMC0_SAMPLE 148 +#define SCLK_SDMMC1_DRV 149 +#define SCLK_SDMMC1_SAMPLE 150 +#define HCLK_EMMC 151 +#define ACLK_EMMC 152 +#define CCLK_EMMC 153 +#define BCLK_EMMC 154 +#define TMCLK_EMMC 155 +#define SCLK_SFC 156 +#define HCLK_SFC 157 +#define HCLK_USB2HOST 158 +#define HCLK_USB2HOST_ARB 159 +#define PCLK_SPI1 160 +#define CLK_SPI1 161 +#define SCLK_IN_SPI1 162 +#define PCLK_SPI2 163 +#define CLK_SPI2 164 +#define SCLK_IN_SPI2 165 +#define PCLK_UART1 166 +#define PCLK_UART2 167 +#define PCLK_UART3 168 +#define PCLK_UART4 169 +#define PCLK_UART5 170 +#define PCLK_UART6 171 +#define PCLK_UART7 172 +#define PCLK_UART8 173 +#define PCLK_UART9 174 +#define CLK_UART1_SRC 175 +#define CLK_UART1_FRAC 176 +#define CLK_UART1 177 +#define SCLK_UART1 178 +#define CLK_UART2_SRC 179 +#define CLK_UART2_FRAC 180 +#define CLK_UART2 181 +#define SCLK_UART2 182 +#define CLK_UART3_SRC 183 +#define CLK_UART3_FRAC 184 +#define CLK_UART3 185 +#define SCLK_UART3 186 +#define CLK_UART4_SRC 187 +#define CLK_UART4_FRAC 188 +#define CLK_UART4 189 +#define SCLK_UART4 190 +#define CLK_UART5_SRC 191 +#define CLK_UART5_FRAC 192 +#define CLK_UART5 193 +#define SCLK_UART5 194 +#define CLK_UART6_SRC 195 +#define CLK_UART6_FRAC 196 +#define CLK_UART6 197 +#define SCLK_UART6 198 +#define CLK_UART7_SRC 199 +#define CLK_UART7_FRAC 200 +#define CLK_UART7 201 +#define SCLK_UART7 202 +#define CLK_UART8_SRC 203 +#define CLK_UART8_FRAC 204 +#define CLK_UART8 205 +#define SCLK_UART8 206 +#define CLK_UART9_SRC 207 +#define CLK_UART9_FRAC 208 +#define CLK_UART9 209 +#define SCLK_UART9 210 +#define PCLK_PWM1_PERI 211 +#define CLK_PWM1_PERI 212 +#define CLK_CAPTURE_PWM1_PERI 213 +#define PCLK_PWM2_PERI 214 +#define CLK_PWM2_PERI 215 +#define CLK_CAPTURE_PWM2_PERI 216 +#define PCLK_PWM3_PERI 217 +#define CLK_PWM3_PERI 218 +#define CLK_CAPTURE_PWM3_PERI 219 +#define PCLK_CAN0 220 +#define CLK_CAN0 221 +#define PCLK_CAN1 222 +#define CLK_CAN1 223 +#define ACLK_CRYPTO 224 +#define HCLK_CRYPTO 225 +#define PCLK_CRYPTO 226 +#define CLK_CORE_CRYPTO 227 +#define CLK_PKA_CRYPTO 228 +#define HCLK_KLAD 229 +#define PCLK_KEY_READER 230 +#define HCLK_RK_RNG_NS 231 +#define HCLK_RK_RNG_S 232 +#define HCLK_TRNG_NS 233 +#define HCLK_TRNG_S 234 +#define HCLK_CRYPTO_S 235 +#define PCLK_PERI_WDT 236 +#define TCLK_PERI_WDT 237 +#define ACLK_SYSMEM 238 +#define HCLK_BOOTROM 239 +#define PCLK_PERI_GRF 240 +#define ACLK_DMAC 241 +#define ACLK_RKDMAC 242 +#define PCLK_OTPC_NS 243 +#define CLK_SBPI_OTPC_NS 244 +#define CLK_USER_OTPC_NS 245 +#define PCLK_OTPC_S 246 +#define CLK_SBPI_OTPC_S 247 +#define CLK_USER_OTPC_S 248 +#define CLK_OTPC_ARB 249 +#define PCLK_OTPPHY 250 +#define PCLK_USB2PHY 251 +#define PCLK_PIPEPHY 252 +#define PCLK_SARADC 253 +#define CLK_SARADC 254 +#define PCLK_IOC_VCCIO234 255 +#define PCLK_PERI_GPIO1 256 +#define PCLK_PERI_GPIO2 257 +#define DCLK_PERI_GPIO 258 +#define DCLK_PERI_GPIO1 259 +#define DCLK_PERI_GPIO2 260 +#define ACLK_PHP 261 +#define PCLK_PHP 262 +#define ACLK_PCIE20_MST 263 +#define ACLK_PCIE20_SLV 264 +#define ACLK_PCIE20_DBI 265 +#define PCLK_PCIE20 266 +#define CLK_PCIE20_AUX 267 +#define ACLK_USB3OTG 268 +#define CLK_USB3OTG_SUSPEND 269 +#define CLK_USB3OTG_REF 270 +#define CLK_PIPEPHY_REF_FUNC 271 +#define CLK_200M_PMU 272 +#define CLK_RTC_32K 273 +#define CLK_RTC32K_FRAC 274 +#define BUSCLK_PDPMU0 275 +#define PCLK_PMU0_CRU 276 +#define PCLK_PMU0_PMU 277 +#define CLK_PMU0_PMU 278 +#define PCLK_PMU0_HP_TIMER 279 +#define CLK_PMU0_HP_TIMER 280 +#define CLK_PMU0_32K_HP_TIMER 281 +#define PCLK_PMU0_PVTM 282 +#define CLK_PMU0_PVTM 283 +#define PCLK_IOC_PMUIO 284 +#define PCLK_PMU0_GPIO0 285 +#define DBCLK_PMU0_GPIO0 286 +#define PCLK_PMU0_GRF 287 +#define PCLK_PMU0_SGRF 288 +#define CLK_DDR_FAIL_SAFE 289 +#define PCLK_PMU0_SCRKEYGEN 290 +#define PCLK_PMU1_CRU 291 +#define HCLK_PMU1_MEM 292 +#define PCLK_PMU0_I2C0 293 +#define CLK_PMU0_I2C0 294 +#define PCLK_PMU1_UART0 295 +#define CLK_PMU1_UART0_SRC 296 +#define CLK_PMU1_UART0_FRAC 297 +#define CLK_PMU1_UART0 298 +#define SCLK_PMU1_UART0 299 +#define PCLK_PMU1_SPI0 300 +#define CLK_PMU1_SPI0 301 +#define SCLK_IN_PMU1_SPI0 302 +#define PCLK_PMU1_PWM0 303 +#define CLK_PMU1_PWM0 304 +#define CLK_CAPTURE_PMU1_PWM0 305 +#define CLK_PMU1_WIFI 306 +#define FCLK_PMU1_CM0_CORE 307 +#define CLK_PMU1_CM0_RTC 308 +#define PCLK_PMU1_WDTNS 309 +#define CLK_PMU1_WDTNS 310 +#define PCLK_PMU1_MAILBOX 311 +#define CLK_PIPEPHY_DIV 312 +#define CLK_PIPEPHY_XIN24M 313 +#define CLK_PIPEPHY_REF 314 +#define CLK_24M_SSCSRC 315 +#define CLK_USB2PHY_XIN24M 316 +#define CLK_USB2PHY_REF 317 +#define CLK_MIPIDSIPHY_XIN24M 318 +#define CLK_MIPIDSIPHY_REF 319 +#define ACLK_RGA_PRE 320 +#define HCLK_RGA_PRE 321 +#define ACLK_RGA 322 +#define HCLK_RGA 323 +#define CLK_RGA_CORE 324 +#define ACLK_JDEC 325 +#define HCLK_JDEC 326 +#define ACLK_VDPU_PRE 327 +#define CLK_RKVDEC_HEVC_CA 328 +#define HCLK_VDPU_PRE 329 +#define ACLK_RKVDEC 330 +#define HCLK_RKVDEC 331 +#define CLK_RKVENC_CORE 332 +#define ACLK_VEPU_PRE 333 +#define HCLK_VEPU_PRE 334 +#define ACLK_RKVENC 335 +#define HCLK_RKVENC 336 +#define ACLK_VI 337 +#define HCLK_VI 338 +#define PCLK_VI 339 +#define ACLK_ISP 340 +#define HCLK_ISP 341 +#define CLK_ISP 342 +#define ACLK_VICAP 343 +#define HCLK_VICAP 344 +#define DCLK_VICAP 345 +#define CSIRX0_CLK_DATA 346 +#define CSIRX1_CLK_DATA 347 +#define CSIRX2_CLK_DATA 348 +#define CSIRX3_CLK_DATA 349 +#define PCLK_CSIHOST0 350 +#define PCLK_CSIHOST1 351 +#define PCLK_CSIHOST2 352 +#define PCLK_CSIHOST3 353 +#define PCLK_CSIPHY0 354 +#define PCLK_CSIPHY1 355 +#define ACLK_VO_PRE 356 +#define HCLK_VO_PRE 357 +#define ACLK_VOP 358 +#define HCLK_VOP 359 +#define DCLK_VOP 360 +#define DCLK_VOP1 361 +#define ACLK_CRYPTO_S 362 +#define PCLK_CRYPTO_S 363 +#define CLK_CORE_CRYPTO_S 364 +#define CLK_PKA_CRYPTO_S 365 + +#endif diff --git a/include/dt-bindings/clock/rockchip,rk3576-cru.h b/include/dt-bindings/clock/rockchip,rk3576-cru.h index 25aed298ac2c..ded5ce42e62a 100644 --- a/include/dt-bindings/clock/rockchip,rk3576-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h @@ -589,4 +589,19 @@ #define PCLK_EDP_S 569 #define ACLK_KLAD 570 +/* SCMI clocks, use these when changing clocks through SCMI */ +#define SCMI_ARMCLK_L 10 +#define SCMI_ARMCLK_B 11 +#define SCMI_CLK_GPU 456 + +/* IOC-controlled output clocks */ +#define CLK_SAI0_MCLKOUT_TO_IO 571 +#define CLK_SAI1_MCLKOUT_TO_IO 572 +#define CLK_SAI2_MCLKOUT_TO_IO 573 +#define CLK_SAI3_MCLKOUT_TO_IO 574 +#define CLK_SAI4_MCLKOUT_TO_IO 575 +#define CLK_SAI4_MCLKOUT_TO_IO 575 +#define CLK_FSPI0_TO_IO 576 +#define CLK_FSPI1_TO_IO 577 + #endif diff --git a/include/dt-bindings/clock/samsung,exynos2200-cmu.h b/include/dt-bindings/clock/samsung,exynos2200-cmu.h new file mode 100644 index 000000000000..310552be0c8c --- /dev/null +++ b/include/dt-bindings/clock/samsung,exynos2200-cmu.h @@ -0,0 +1,431 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> + * Author: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> + * + * Device Tree binding constants for Exynos2200 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS2200_H +#define _DT_BINDINGS_CLOCK_EXYNOS2200_H + +/* CMU_TOP */ +#define CLK_FOUT_SHARED0_PLL 1 +#define CLK_FOUT_SHARED1_PLL 2 +#define CLK_FOUT_SHARED2_PLL 3 +#define CLK_FOUT_SHARED3_PLL 4 +#define CLK_FOUT_SHARED4_PLL 5 +#define CLK_FOUT_MMC_PLL 6 +#define CLK_FOUT_SHARED_MIF_PLL 7 + +#define CLK_MOUT_CMU_CP_MPLL_CLK_D2_USER 8 +#define CLK_MOUT_CMU_CP_MPLL_CLK_USER 9 +#define CLK_MOUT_CMU_AUD_AUDIF0 10 +#define CLK_MOUT_CMU_AUD_AUDIF1 11 +#define CLK_MOUT_CMU_AUD_CPU 12 +#define CLK_MOUT_CMU_CPUCL0_DBG_NOC 13 +#define CLK_MOUT_CMU_CPUCL0_SWITCH 14 +#define CLK_MOUT_CMU_CPUCL1_SWITCH 15 +#define CLK_MOUT_CMU_CPUCL2_SWITCH 16 +#define CLK_MOUT_CMU_DNC_NOC 17 +#define CLK_MOUT_CMU_DPUB_NOC 18 +#define CLK_MOUT_CMU_DPUF_NOC 19 +#define CLK_MOUT_CMU_DSP_NOC 20 +#define CLK_MOUT_CMU_DSU_SWITCH 21 +#define CLK_MOUT_CMU_G3D_SWITCH 22 +#define CLK_MOUT_CMU_GNPU_NOC 23 +#define CLK_MOUT_CMU_UFS_MMC_CARD 24 +#define CLK_MOUT_CMU_M2M_NOC 25 +#define CLK_MOUT_CMU_NOCL0_NOC 26 +#define CLK_MOUT_CMU_NOCL1A_NOC 27 +#define CLK_MOUT_CMU_NOCL1B_NOC0 28 +#define CLK_MOUT_CMU_NOCL1C_NOC 29 +#define CLK_MOUT_CMU_SDMA_NOC 30 +#define CLK_MOUT_CMU_CP_HISPEEDY_CLK 31 +#define CLK_MOUT_CMU_CP_SHARED0_CLK 32 +#define CLK_MOUT_CMU_CP_SHARED2_CLK 33 +#define CLK_MOUT_CMU_MUX_ALIVE_NOC 34 +#define CLK_MOUT_CMU_MUX_AUD_AUDIF0 35 +#define CLK_MOUT_CMU_MUX_AUD_AUDIF1 36 +#define CLK_MOUT_CMU_MUX_AUD_CPU 37 +#define CLK_MOUT_CMU_MUX_AUD_NOC 38 +#define CLK_MOUT_CMU_MUX_BRP_NOC 39 +#define CLK_MOUT_CMU_MUX_CIS_CLK0 40 +#define CLK_MOUT_CMU_MUX_CIS_CLK1 41 +#define CLK_MOUT_CMU_MUX_CIS_CLK2 42 +#define CLK_MOUT_CMU_MUX_CIS_CLK3 43 +#define CLK_MOUT_CMU_MUX_CIS_CLK4 44 +#define CLK_MOUT_CMU_MUX_CIS_CLK5 45 +#define CLK_MOUT_CMU_MUX_CIS_CLK6 46 +#define CLK_MOUT_CMU_MUX_CIS_CLK7 47 +#define CLK_MOUT_CMU_MUX_CMU_BOOST 48 +#define CLK_MOUT_CMU_MUX_CMU_BOOST_CAM 49 +#define CLK_MOUT_CMU_MUX_CMU_BOOST_CPU 50 +#define CLK_MOUT_CMU_MUX_CMU_BOOST_MIF 51 +#define CLK_MOUT_CMU_MUX_CPUCL0_DBG_NOC 52 +#define CLK_MOUT_CMU_MUX_CPUCL0_NOCP 53 +#define CLK_MOUT_CMU_MUX_CPUCL0_SWITCH 54 +#define CLK_MOUT_CMU_MUX_CPUCL1_SWITCH 55 +#define CLK_MOUT_CMU_MUX_CPUCL2_SWITCH 56 +#define CLK_MOUT_CMU_MUX_CSIS_DCPHY 57 +#define CLK_MOUT_CMU_MUX_CSIS_NOC 58 +#define CLK_MOUT_CMU_MUX_CSIS_OIS_MCU 59 +#define CLK_MOUT_CMU_MUX_CSTAT_NOC 60 +#define CLK_MOUT_CMU_MUX_DNC_NOC 61 +#define CLK_MOUT_CMU_MUX_DPUB 62 +#define CLK_MOUT_CMU_MUX_DPUB_ALT 63 +#define CLK_MOUT_CMU_MUX_DPUB_DSIM 64 +#define CLK_MOUT_CMU_MUX_DPUF 65 +#define CLK_MOUT_CMU_MUX_DPUF_ALT 66 +#define CLK_MOUT_CMU_MUX_DSP_NOC 67 +#define CLK_MOUT_CMU_MUX_DSU_SWITCH 68 +#define CLK_MOUT_CMU_MUX_G3D_NOCP 69 +#define CLK_MOUT_CMU_MUX_G3D_SWITCH 70 +#define CLK_MOUT_CMU_MUX_GNPU_NOC 71 +#define CLK_MOUT_CMU_MUX_HSI0_DPGTC 72 +#define CLK_MOUT_CMU_MUX_HSI0_DPOSC 73 +#define CLK_MOUT_CMU_MUX_HSI0_NOC 74 +#define CLK_MOUT_CMU_MUX_HSI0_USB32DRD 75 +#define CLK_MOUT_CMU_MUX_UFS_MMC_CARD 76 +#define CLK_MOUT_CMU_MUX_HSI1_NOC 77 +#define CLK_MOUT_CMU_MUX_HSI1_PCIE 78 +#define CLK_MOUT_CMU_MUX_UFS_UFS_EMBD 79 +#define CLK_MOUT_CMU_MUX_LME_LME 80 +#define CLK_MOUT_CMU_MUX_LME_NOC 81 +#define CLK_MOUT_CMU_MUX_M2M_NOC 82 +#define CLK_MOUT_CMU_MUX_MCSC_MCSC 83 +#define CLK_MOUT_CMU_MUX_MCSC_NOC 84 +#define CLK_MOUT_CMU_MUX_MFC0_MFC0 85 +#define CLK_MOUT_CMU_MUX_MFC0_WFD 86 +#define CLK_MOUT_CMU_MUX_MFC1_MFC1 87 +#define CLK_MOUT_CMU_MUX_MIF_NOCP 88 +#define CLK_MOUT_CMU_MUX_MIF_SWITCH 89 +#define CLK_MOUT_CMU_MUX_NOCL0_NOC 90 +#define CLK_MOUT_CMU_MUX_NOCL1A_NOC 91 +#define CLK_MOUT_CMU_MUX_NOCL1B_NOC0 92 +#define CLK_MOUT_CMU_MUX_NOCL1B_NOC1 93 +#define CLK_MOUT_CMU_MUX_NOCL1C_NOC 94 +#define CLK_MOUT_CMU_MUX_PERIC0_IP0 95 +#define CLK_MOUT_CMU_MUX_PERIC0_IP1 96 +#define CLK_MOUT_CMU_MUX_PERIC0_NOC 97 +#define CLK_MOUT_CMU_MUX_PERIC1_IP0 98 +#define CLK_MOUT_CMU_MUX_PERIC1_IP1 99 +#define CLK_MOUT_CMU_MUX_PERIC1_NOC 100 +#define CLK_MOUT_CMU_MUX_PERIC2_IP0 101 +#define CLK_MOUT_CMU_MUX_PERIC2_IP1 102 +#define CLK_MOUT_CMU_MUX_PERIC2_NOC 103 +#define CLK_MOUT_CMU_MUX_PERIS_GIC 104 +#define CLK_MOUT_CMU_MUX_PERIS_NOC 105 +#define CLK_MOUT_CMU_MUX_SDMA_NOC 106 +#define CLK_MOUT_CMU_MUX_SSP_NOC 107 +#define CLK_MOUT_CMU_MUX_VTS_DMIC 108 +#define CLK_MOUT_CMU_MUX_YUVP_NOC 109 +#define CLK_MOUT_CMU_MUX_CMU_CMUREF 110 +#define CLK_MOUT_CMU_MUX_CP_HISPEEDY_CLK 111 +#define CLK_MOUT_CMU_MUX_CP_SHARED0_CLK 112 +#define CLK_MOUT_CMU_MUX_CP_SHARED1_CLK 113 +#define CLK_MOUT_CMU_MUX_CP_SHARED2_CLK 114 +#define CLK_MOUT_CMU_M2M_FRC 115 +#define CLK_MOUT_CMU_MCSC_MCSC 116 +#define CLK_MOUT_CMU_MCSC_NOC 117 +#define CLK_MOUT_CMU_MUX_M2M_FRC 118 +#define CLK_MOUT_CMU_MUX_UFS_NOC 119 + +#define CLK_DOUT_CMU_ALIVE_NOC 120 +#define CLK_DOUT_CMU_AUD_NOC 121 +#define CLK_DOUT_CMU_BRP_NOC 122 +#define CLK_DOUT_CMU_CMU_BOOST 123 +#define CLK_DOUT_CMU_CMU_BOOST_CAM 124 +#define CLK_DOUT_CMU_CMU_BOOST_CPU 125 +#define CLK_DOUT_CMU_CMU_BOOST_MIF 126 +#define CLK_DOUT_CMU_CPUCL0_NOCP 127 +#define CLK_DOUT_CMU_CSIS_DCPHY 128 +#define CLK_DOUT_CMU_CSIS_NOC 129 +#define CLK_DOUT_CMU_CSIS_OIS_MCU 130 +#define CLK_DOUT_CMU_CSTAT_NOC 131 +#define CLK_DOUT_CMU_DPUB_DSIM 132 +#define CLK_DOUT_CMU_LME_LME 133 +#define CLK_DOUT_CMU_G3D_NOCP 134 +#define CLK_DOUT_CMU_HSI0_DPGTC 135 +#define CLK_DOUT_CMU_HSI0_DPOSC 136 +#define CLK_DOUT_CMU_HSI0_NOC 137 +#define CLK_DOUT_CMU_HSI0_USB32DRD 138 +#define CLK_DOUT_CMU_HSI1_NOC 139 +#define CLK_DOUT_CMU_HSI1_PCIE 140 +#define CLK_DOUT_CMU_UFS_UFS_EMBD 141 +#define CLK_DOUT_CMU_LME_NOC 142 +#define CLK_DOUT_CMU_MFC0_MFC0 143 +#define CLK_DOUT_CMU_MFC0_WFD 144 +#define CLK_DOUT_CMU_MFC1_MFC1 145 +#define CLK_DOUT_CMU_MIF_NOCP 146 +#define CLK_DOUT_CMU_NOCL1B_NOC1 147 +#define CLK_DOUT_CMU_PERIC0_IP0 148 +#define CLK_DOUT_CMU_PERIC0_IP1 149 +#define CLK_DOUT_CMU_PERIC0_NOC 150 +#define CLK_DOUT_CMU_PERIC1_IP0 151 +#define CLK_DOUT_CMU_PERIC1_IP1 152 +#define CLK_DOUT_CMU_PERIC1_NOC 153 +#define CLK_DOUT_CMU_PERIC2_IP0 154 +#define CLK_DOUT_CMU_PERIC2_IP1 155 +#define CLK_DOUT_CMU_PERIC2_NOC 156 +#define CLK_DOUT_CMU_PERIS_GIC 157 +#define CLK_DOUT_CMU_PERIS_NOC 158 +#define CLK_DOUT_CMU_SSP_NOC 159 +#define CLK_DOUT_CMU_VTS_DMIC 160 +#define CLK_DOUT_CMU_YUVP_NOC 161 +#define CLK_DOUT_CMU_CP_SHARED1_CLK 162 +#define CLK_DOUT_CMU_DIV_AUD_AUDIF0 163 +#define CLK_DOUT_CMU_DIV_AUD_AUDIF0_SM 164 +#define CLK_DOUT_CMU_DIV_AUD_AUDIF1 165 +#define CLK_DOUT_CMU_DIV_AUD_AUDIF1_SM 166 +#define CLK_DOUT_CMU_DIV_AUD_CPU 167 +#define CLK_DOUT_CMU_DIV_AUD_CPU_SM 168 +#define CLK_DOUT_CMU_DIV_CIS_CLK0 169 +#define CLK_DOUT_CMU_DIV_CIS_CLK1 170 +#define CLK_DOUT_CMU_DIV_CIS_CLK2 171 +#define CLK_DOUT_CMU_DIV_CIS_CLK3 172 +#define CLK_DOUT_CMU_DIV_CIS_CLK4 173 +#define CLK_DOUT_CMU_DIV_CIS_CLK5 174 +#define CLK_DOUT_CMU_DIV_CIS_CLK6 175 +#define CLK_DOUT_CMU_DIV_CIS_CLK7 176 +#define CLK_DOUT_CMU_DIV_CPUCL0_DBG_NOC 177 +#define CLK_DOUT_CMU_DIV_CPUCL0_DBG_NOC_SM 178 +#define CLK_DOUT_CMU_DIV_CPUCL0_SWITCH 179 +#define CLK_DOUT_CMU_DIV_CPUCL0_SWITCH_SM 180 +#define CLK_DOUT_CMU_DIV_CPUCL1_SWITCH 181 +#define CLK_DOUT_CMU_DIV_CPUCL1_SWITCH_SM 182 +#define CLK_DOUT_CMU_DIV_CPUCL2_SWITCH 183 +#define CLK_DOUT_CMU_DIV_CPUCL2_SWITCH_SM 184 +#define CLK_DOUT_CMU_DIV_DNC_NOC 185 +#define CLK_DOUT_CMU_DIV_DNC_NOC_SM 186 +#define CLK_DOUT_CMU_DIV_DPUB 187 +#define CLK_DOUT_CMU_DIV_DPUB_ALT 188 +#define CLK_DOUT_CMU_DIV_DPUF 189 +#define CLK_DOUT_CMU_DIV_DPUF_ALT 190 +#define CLK_DOUT_CMU_DIV_DSP_NOC 191 +#define CLK_DOUT_CMU_DIV_DSP_NOC_SM 192 +#define CLK_DOUT_CMU_DIV_DSU_SWITCH 193 +#define CLK_DOUT_CMU_DIV_DSU_SWITCH_SM 194 +#define CLK_DOUT_CMU_DIV_G3D_SWITCH 195 +#define CLK_DOUT_CMU_DIV_G3D_SWITCH_SM 196 +#define CLK_DOUT_CMU_DIV_GNPU_NOC 197 +#define CLK_DOUT_CMU_DIV_GNPU_NOC_SM 198 +#define CLK_DOUT_CMU_DIV_UFS_MMC_CARD 199 +#define CLK_DOUT_CMU_DIV_UFS_MMC_CARD_SM 200 +#define CLK_DOUT_CMU_DIV_M2M_NOC 201 +#define CLK_DOUT_CMU_DIV_M2M_NOC_SM 202 +#define CLK_DOUT_CMU_DIV_NOCL0_NOC 203 +#define CLK_DOUT_CMU_DIV_NOCL0_NOC_SM 204 +#define CLK_DOUT_CMU_DIV_NOCL1A_NOC 205 +#define CLK_DOUT_CMU_DIV_NOCL1A_NOC_SM 206 +#define CLK_DOUT_CMU_DIV_NOCL1B_NOC0 207 +#define CLK_DOUT_CMU_DIV_NOCL1B_NOC0_SM 208 +#define CLK_DOUT_CMU_DIV_NOCL1C_NOC 209 +#define CLK_DOUT_CMU_DIV_NOCL1C_NOC_SM 210 +#define CLK_DOUT_CMU_DIV_SDMA_NOC 211 +#define CLK_DOUT_CMU_DIV_SDMA_NOC_SM 212 +#define CLK_DOUT_CMU_DIV_CP_HISPEEDY_CLK 213 +#define CLK_DOUT_CMU_DIV_CP_HISPEEDY_CLK_SM 214 +#define CLK_DOUT_CMU_DIV_CP_SHARED0_CLK 215 +#define CLK_DOUT_CMU_DIV_CP_SHARED0_CLK_SM 216 +#define CLK_DOUT_CMU_DIV_CP_SHARED2_CLK 217 +#define CLK_DOUT_CMU_DIV_CP_SHARED2_CLK_SM 218 +#define CLK_DOUT_CMU_UFS_NOC 219 +#define CLK_DOUT_CMU_DIV_M2M_FRC 220 +#define CLK_DOUT_CMU_DIV_M2M_FRC_SM 221 +#define CLK_DOUT_CMU_DIV_MCSC_MCSC 222 +#define CLK_DOUT_CMU_DIV_MCSC_MCSC_SM 223 +#define CLK_DOUT_CMU_DIV_MCSC_NOC 224 +#define CLK_DOUT_CMU_DIV_MCSC_NOC_SM 225 +#define CLK_DOUT_SHARED0_DIV1 226 +#define CLK_DOUT_SHARED0_DIV2 227 +#define CLK_DOUT_SHARED0_DIV4 228 +#define CLK_DOUT_SHARED1_DIV1 229 +#define CLK_DOUT_SHARED1_DIV2 230 +#define CLK_DOUT_SHARED1_DIV4 231 +#define CLK_DOUT_SHARED2_DIV1 232 +#define CLK_DOUT_SHARED2_DIV2 233 +#define CLK_DOUT_SHARED2_DIV4 234 +#define CLK_DOUT_SHARED3_DIV1 235 +#define CLK_DOUT_SHARED3_DIV2 236 +#define CLK_DOUT_SHARED3_DIV4 237 +#define CLK_DOUT_SHARED4_DIV1 238 +#define CLK_DOUT_SHARED4_DIV2 239 +#define CLK_DOUT_SHARED4_DIV4 240 +#define CLK_DOUT_SHARED_MIF_DIV1 241 +#define CLK_DOUT_SHARED_MIF_DIV2 242 +#define CLK_DOUT_SHARED_MIF_DIV4 243 +#define CLK_DOUT_TCXO_DIV3 244 +#define CLK_DOUT_TCXO_DIV4 245 + +/* CMU_ALIVE */ +#define CLK_MOUT_ALIVE_NOC_USER 1 +#define CLK_MOUT_ALIVE_RCO_SPMI_USER 2 +#define CLK_MOUT_RCO_ALIVE_USER 3 +#define CLK_MOUT_ALIVE_CHUB_PERI 4 +#define CLK_MOUT_ALIVE_CMGP_NOC 5 +#define CLK_MOUT_ALIVE_CMGP_PERI 6 +#define CLK_MOUT_ALIVE_DBGCORE_NOC 7 +#define CLK_MOUT_ALIVE_DNC_NOC 8 +#define CLK_MOUT_ALIVE_CHUBVTS_NOC 9 +#define CLK_MOUT_ALIVE_GNPU_NOC 10 +#define CLK_MOUT_ALIVE_GNSS_NOC 11 +#define CLK_MOUT_ALIVE_SDMA_NOC 12 +#define CLK_MOUT_ALIVE_UFD_NOC 13 +#define CLK_MOUT_ALIVE_DBGCORE_UART 14 +#define CLK_MOUT_ALIVE_NOC 15 +#define CLK_MOUT_ALIVE_PMU_SUB 16 +#define CLK_MOUT_ALIVE_SPMI 17 +#define CLK_MOUT_ALIVE_TIMER 18 +#define CLK_MOUT_ALIVE_CSIS_NOC 19 +#define CLK_MOUT_ALIVE_DSP_NOC 20 + +#define CLK_DOUT_ALIVE_CHUB_PERI 21 +#define CLK_DOUT_ALIVE_CMGP_NOC 22 +#define CLK_DOUT_ALIVE_CMGP_PERI 23 +#define CLK_DOUT_ALIVE_DBGCORE_NOC 24 +#define CLK_DOUT_ALIVE_DNC_NOC 25 +#define CLK_DOUT_ALIVE_CHUBVTS_NOC 26 +#define CLK_DOUT_ALIVE_GNPU_NOC 27 +#define CLK_DOUT_ALIVE_SDMA_NOC 28 +#define CLK_DOUT_ALIVE_UFD_NOC 29 +#define CLK_DOUT_ALIVE_DBGCORE_UART 30 +#define CLK_DOUT_ALIVE_NOC 31 +#define CLK_DOUT_ALIVE_PMU_SUB 32 +#define CLK_DOUT_ALIVE_SPMI 33 +#define CLK_DOUT_ALIVE_CSIS_NOC 34 +#define CLK_DOUT_ALIVE_DSP_NOC 35 + +/* CMU_PERIS */ +#define CLK_MOUT_PERIS_GIC_USER 1 +#define CLK_MOUT_PERIS_NOC_USER 2 +#define CLK_MOUT_PERIS_GIC 3 + +#define CLK_DOUT_PERIS_OTP 4 +#define CLK_DOUT_PERIS_DDD_CTRL 5 + +/* CMU_CMGP */ +#define CLK_MOUT_CMGP_CLKALIVE_NOC_USER 1 +#define CLK_MOUT_CMGP_CLKALIVE_PERI_USER 2 +#define CLK_MOUT_CMGP_I2C 3 +#define CLK_MOUT_CMGP_SPI_I2C0 4 +#define CLK_MOUT_CMGP_SPI_I2C1 5 +#define CLK_MOUT_CMGP_SPI_MS_CTRL 6 +#define CLK_MOUT_CMGP_USI0 7 +#define CLK_MOUT_CMGP_USI1 8 +#define CLK_MOUT_CMGP_USI2 9 +#define CLK_MOUT_CMGP_USI3 10 +#define CLK_MOUT_CMGP_USI4 11 +#define CLK_MOUT_CMGP_USI5 12 +#define CLK_MOUT_CMGP_USI6 13 + +#define CLK_DOUT_CMGP_I2C 14 +#define CLK_DOUT_CMGP_SPI_I2C0 15 +#define CLK_DOUT_CMGP_SPI_I2C1 16 +#define CLK_DOUT_CMGP_SPI_MS_CTRL 17 +#define CLK_DOUT_CMGP_USI0 18 +#define CLK_DOUT_CMGP_USI1 19 +#define CLK_DOUT_CMGP_USI2 20 +#define CLK_DOUT_CMGP_USI3 21 +#define CLK_DOUT_CMGP_USI4 22 +#define CLK_DOUT_CMGP_USI5 23 +#define CLK_DOUT_CMGP_USI6 24 + +/* CMU_HSI0 */ +#define CLK_MOUT_CLKCMU_HSI0_DPGTC_USER 1 +#define CLK_MOUT_CLKCMU_HSI0_DPOSC_USER 2 +#define CLK_MOUT_CLKCMU_HSI0_NOC_USER 3 +#define CLK_MOUT_CLKCMU_HSI0_USB32DRD_USER 4 +#define CLK_MOUT_HSI0_NOC 5 +#define CLK_MOUT_HSI0_RTCCLK 6 +#define CLK_MOUT_HSI0_USB32DRD 7 + +#define CLK_DOUT_DIV_CLK_HSI0_EUSB 8 + +/* CMU_PERIC0 */ +#define CLK_MOUT_PERIC0_IP0_USER 1 +#define CLK_MOUT_PERIC0_IP1_USER 2 +#define CLK_MOUT_PERIC0_NOC_USER 3 +#define CLK_MOUT_PERIC0_I2C 4 +#define CLK_MOUT_PERIC0_USI04 5 + +#define CLK_DOUT_PERIC0_I2C 6 +#define CLK_DOUT_PERIC0_USI04 7 + +/* CMU_PERIC1 */ +#define CLK_MOUT_PERIC1_IP0_USER 1 +#define CLK_MOUT_PERIC1_IP1_USER 2 +#define CLK_MOUT_PERIC1_NOC_USER 3 +#define CLK_MOUT_PERIC1_I2C 4 +#define CLK_MOUT_PERIC1_SPI_MS_CTRL 5 +#define CLK_MOUT_PERIC1_UART_BT 6 +#define CLK_MOUT_PERIC1_USI07 7 +#define CLK_MOUT_PERIC1_USI07_SPI_I2C 8 +#define CLK_MOUT_PERIC1_USI08 9 +#define CLK_MOUT_PERIC1_USI08_SPI_I2C 10 +#define CLK_MOUT_PERIC1_USI09 11 +#define CLK_MOUT_PERIC1_USI10 12 + +#define CLK_DOUT_PERIC1_I2C 13 +#define CLK_DOUT_PERIC1_SPI_MS_CTRL 14 +#define CLK_DOUT_PERIC1_UART_BT 15 +#define CLK_DOUT_PERIC1_USI07 16 +#define CLK_DOUT_PERIC1_USI07_SPI_I2C 17 +#define CLK_DOUT_PERIC1_USI08 18 +#define CLK_DOUT_PERIC1_USI08_SPI_I2C 19 +#define CLK_DOUT_PERIC1_USI09 20 +#define CLK_DOUT_PERIC1_USI10 21 + +/* CMU_PERIC2 */ +#define CLK_MOUT_PERIC2_IP0_USER 1 +#define CLK_MOUT_PERIC2_IP1_USER 2 +#define CLK_MOUT_PERIC2_NOC_USER 3 +#define CLK_MOUT_PERIC2_I2C 4 +#define CLK_MOUT_PERIC2_SPI_MS_CTRL 5 +#define CLK_MOUT_PERIC2_UART_DBG 6 +#define CLK_MOUT_PERIC2_USI00 7 +#define CLK_MOUT_PERIC2_USI00_SPI_I2C 8 +#define CLK_MOUT_PERIC2_USI01 9 +#define CLK_MOUT_PERIC2_USI01_SPI_I2C 10 +#define CLK_MOUT_PERIC2_USI02 11 +#define CLK_MOUT_PERIC2_USI03 12 +#define CLK_MOUT_PERIC2_USI05 13 +#define CLK_MOUT_PERIC2_USI06 14 +#define CLK_MOUT_PERIC2_USI11 15 + +#define CLK_DOUT_PERIC2_I2C 16 +#define CLK_DOUT_PERIC2_SPI_MS_CTRL 17 +#define CLK_DOUT_PERIC2_UART_DBG 18 +#define CLK_DOUT_PERIC2_USI00 19 +#define CLK_DOUT_PERIC2_USI00_SPI_I2C 20 +#define CLK_DOUT_PERIC2_USI01 21 +#define CLK_DOUT_PERIC2_USI01_SPI_I2C 22 +#define CLK_DOUT_PERIC2_USI02 23 +#define CLK_DOUT_PERIC2_USI03 24 +#define CLK_DOUT_PERIC2_USI05 25 +#define CLK_DOUT_PERIC2_USI06 26 +#define CLK_DOUT_PERIC2_USI11 27 + +/* CMU_UFS */ +#define CLK_MOUT_UFS_MMC_CARD_USER 1 +#define CLK_MOUT_UFS_NOC_USER 2 +#define CLK_MOUT_UFS_UFS_EMBD_USER 3 + +/* CMU_VTS */ +#define CLK_MOUT_CLKALIVE_VTS_NOC_USER 1 +#define CLK_MOUT_CLKALIVE_VTS_RCO_USER 2 +#define CLK_MOUT_CLKCMU_VTS_DMIC_USER 3 +#define CLK_MOUT_CLKVTS_AUD_DMIC1 4 +#define CLK_MOUT_CLKVTS_NOC 5 +#define CLK_MOUT_CLKVTS_DMIC_PAD 6 + +#define CLK_DOUT_CLKVTS_AUD_DMIC0 7 +#define CLK_DOUT_CLKVTS_AUD_DMIC1 8 +#define CLK_DOUT_CLKVTS_CPU 9 +#define CLK_DOUT_CLKVTS_DMIC_IF 10 +#define CLK_DOUT_CLKVTS_DMIC_IF_DIV2 11 +#define CLK_DOUT_CLKVTS_NOC 12 +#define CLK_DOUT_CLKVTS_SERIAL_LIF 13 +#define CLK_DOUT_CLKVTS_SERIAL_LIF_CORE 14 + +#endif diff --git a/include/dt-bindings/clock/samsung,exynos7870-cmu.h b/include/dt-bindings/clock/samsung,exynos7870-cmu.h new file mode 100644 index 000000000000..57d04bbe342d --- /dev/null +++ b/include/dt-bindings/clock/samsung,exynos7870-cmu.h @@ -0,0 +1,324 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2015 Samsung Electronics Co., Ltd. + * Author: Kaustabh Chakraborty <kauschluss@disroot.org> + * + * Device Tree binding constants for Exynos7870 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS7870_H +#define _DT_BINDINGS_CLOCK_EXYNOS7870_H + +/* CMU_MIF */ +#define CLK_DOUT_MIF_APB 1 +#define CLK_DOUT_MIF_BUSD 2 +#define CLK_DOUT_MIF_CMU_DISPAUD_BUS 3 +#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_ECLK 4 +#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_VCLK 5 +#define CLK_DOUT_MIF_CMU_FSYS_BUS 6 +#define CLK_DOUT_MIF_CMU_FSYS_MMC0 7 +#define CLK_DOUT_MIF_CMU_FSYS_MMC1 8 +#define CLK_DOUT_MIF_CMU_FSYS_MMC2 9 +#define CLK_DOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 10 +#define CLK_DOUT_MIF_CMU_G3D_SWITCH 11 +#define CLK_DOUT_MIF_CMU_ISP_CAM 12 +#define CLK_DOUT_MIF_CMU_ISP_ISP 13 +#define CLK_DOUT_MIF_CMU_ISP_SENSOR0 14 +#define CLK_DOUT_MIF_CMU_ISP_SENSOR1 15 +#define CLK_DOUT_MIF_CMU_ISP_SENSOR2 16 +#define CLK_DOUT_MIF_CMU_ISP_VRA 17 +#define CLK_DOUT_MIF_CMU_MFCMSCL_MFC 18 +#define CLK_DOUT_MIF_CMU_MFCMSCL_MSCL 19 +#define CLK_DOUT_MIF_CMU_PERI_BUS 20 +#define CLK_DOUT_MIF_CMU_PERI_SPI0 21 +#define CLK_DOUT_MIF_CMU_PERI_SPI1 22 +#define CLK_DOUT_MIF_CMU_PERI_SPI2 23 +#define CLK_DOUT_MIF_CMU_PERI_SPI3 24 +#define CLK_DOUT_MIF_CMU_PERI_SPI4 25 +#define CLK_DOUT_MIF_CMU_PERI_UART0 26 +#define CLK_DOUT_MIF_CMU_PERI_UART1 27 +#define CLK_DOUT_MIF_CMU_PERI_UART2 28 +#define CLK_DOUT_MIF_HSI2C 29 +#define CLK_FOUT_MIF_BUS_PLL 30 +#define CLK_FOUT_MIF_MEDIA_PLL 31 +#define CLK_FOUT_MIF_MEM_PLL 32 +#define CLK_GOUT_MIF_CMU_DISPAUD_BUS 33 +#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK 34 +#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK 35 +#define CLK_GOUT_MIF_CMU_FSYS_BUS 36 +#define CLK_GOUT_MIF_CMU_FSYS_MMC0 37 +#define CLK_GOUT_MIF_CMU_FSYS_MMC1 38 +#define CLK_GOUT_MIF_CMU_FSYS_MMC2 39 +#define CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 40 +#define CLK_GOUT_MIF_CMU_G3D_SWITCH 41 +#define CLK_GOUT_MIF_CMU_ISP_CAM 42 +#define CLK_GOUT_MIF_CMU_ISP_ISP 43 +#define CLK_GOUT_MIF_CMU_ISP_SENSOR0 44 +#define CLK_GOUT_MIF_CMU_ISP_SENSOR1 45 +#define CLK_GOUT_MIF_CMU_ISP_SENSOR2 46 +#define CLK_GOUT_MIF_CMU_ISP_VRA 47 +#define CLK_GOUT_MIF_CMU_MFCMSCL_MFC 48 +#define CLK_GOUT_MIF_CMU_MFCMSCL_MSCL 49 +#define CLK_GOUT_MIF_CMU_PERI_BUS 50 +#define CLK_GOUT_MIF_CMU_PERI_SPI0 51 +#define CLK_GOUT_MIF_CMU_PERI_SPI1 52 +#define CLK_GOUT_MIF_CMU_PERI_SPI2 53 +#define CLK_GOUT_MIF_CMU_PERI_SPI3 54 +#define CLK_GOUT_MIF_CMU_PERI_SPI4 55 +#define CLK_GOUT_MIF_CMU_PERI_UART0 56 +#define CLK_GOUT_MIF_CMU_PERI_UART1 57 +#define CLK_GOUT_MIF_CMU_PERI_UART2 58 +#define CLK_GOUT_MIF_CP_PCLK_HSI2C 59 +#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_0 60 +#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_1 61 +#define CLK_GOUT_MIF_HSI2C_AP_PCLKM 62 +#define CLK_GOUT_MIF_HSI2C_AP_PCLKS 63 +#define CLK_GOUT_MIF_HSI2C_CP_PCLKM 64 +#define CLK_GOUT_MIF_HSI2C_CP_PCLKS 65 +#define CLK_GOUT_MIF_HSI2C_IPCLK 66 +#define CLK_GOUT_MIF_HSI2C_ITCLK 67 +#define CLK_GOUT_MIF_MUX_BUSD 68 +#define CLK_GOUT_MIF_MUX_BUS_PLL 69 +#define CLK_GOUT_MIF_MUX_BUS_PLL_CON 70 +#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_BUS 71 +#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_ECLK 72 +#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_VCLK 73 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_BUS 74 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC0 75 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC1 76 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC2 77 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK 78 +#define CLK_GOUT_MIF_MUX_CMU_ISP_CAM 79 +#define CLK_GOUT_MIF_MUX_CMU_ISP_ISP 80 +#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR0 81 +#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR1 82 +#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR2 83 +#define CLK_GOUT_MIF_MUX_CMU_ISP_VRA 84 +#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MFC 85 +#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MSCL 86 +#define CLK_GOUT_MIF_MUX_CMU_PERI_BUS 87 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI0 88 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI1 89 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI2 90 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI3 91 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI4 92 +#define CLK_GOUT_MIF_MUX_CMU_PERI_UART0 93 +#define CLK_GOUT_MIF_MUX_CMU_PERI_UART1 94 +#define CLK_GOUT_MIF_MUX_CMU_PERI_UART2 95 +#define CLK_GOUT_MIF_MUX_MEDIA_PLL 96 +#define CLK_GOUT_MIF_MUX_MEDIA_PLL_CON 97 +#define CLK_GOUT_MIF_MUX_MEM_PLL 98 +#define CLK_GOUT_MIF_MUX_MEM_PLL_CON 99 +#define CLK_GOUT_MIF_WRAP_ADC_IF_OSC_SYS 100 +#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S0 101 +#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S1 102 +#define CLK_MOUT_MIF_BUSD 103 +#define CLK_MOUT_MIF_CMU_DISPAUD_BUS 104 +#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_ECLK 105 +#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_VCLK 106 +#define CLK_MOUT_MIF_CMU_FSYS_BUS 107 +#define CLK_MOUT_MIF_CMU_FSYS_MMC0 108 +#define CLK_MOUT_MIF_CMU_FSYS_MMC1 109 +#define CLK_MOUT_MIF_CMU_FSYS_MMC2 110 +#define CLK_MOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 111 +#define CLK_MOUT_MIF_CMU_ISP_CAM 112 +#define CLK_MOUT_MIF_CMU_ISP_ISP 113 +#define CLK_MOUT_MIF_CMU_ISP_SENSOR0 114 +#define CLK_MOUT_MIF_CMU_ISP_SENSOR1 115 +#define CLK_MOUT_MIF_CMU_ISP_SENSOR2 116 +#define CLK_MOUT_MIF_CMU_ISP_VRA 117 +#define CLK_MOUT_MIF_CMU_MFCMSCL_MFC 118 +#define CLK_MOUT_MIF_CMU_MFCMSCL_MSCL 119 +#define CLK_MOUT_MIF_CMU_PERI_BUS 120 +#define CLK_MOUT_MIF_CMU_PERI_SPI0 121 +#define CLK_MOUT_MIF_CMU_PERI_SPI1 122 +#define CLK_MOUT_MIF_CMU_PERI_SPI2 123 +#define CLK_MOUT_MIF_CMU_PERI_SPI3 124 +#define CLK_MOUT_MIF_CMU_PERI_SPI4 125 +#define CLK_MOUT_MIF_CMU_PERI_UART0 126 +#define CLK_MOUT_MIF_CMU_PERI_UART1 127 +#define CLK_MOUT_MIF_CMU_PERI_UART2 128 +#define MIF_NR_CLK 129 + +/* CMU_DISPAUD */ +#define CLK_DOUT_DISPAUD_APB 1 +#define CLK_DOUT_DISPAUD_DECON_ECLK 2 +#define CLK_DOUT_DISPAUD_DECON_VCLK 3 +#define CLK_DOUT_DISPAUD_MI2S 4 +#define CLK_DOUT_DISPAUD_MIXER 5 +#define CLK_FOUT_DISPAUD_AUD_PLL 6 +#define CLK_FOUT_DISPAUD_PLL 7 +#define CLK_GOUT_DISPAUD_APB_AUD 8 +#define CLK_GOUT_DISPAUD_APB_AUD_AMP 9 +#define CLK_GOUT_DISPAUD_APB_DISP 10 +#define CLK_GOUT_DISPAUD_BUS 11 +#define CLK_GOUT_DISPAUD_BUS_DISP 12 +#define CLK_GOUT_DISPAUD_BUS_PPMU 13 +#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN 14 +#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN 15 +#define CLK_GOUT_DISPAUD_CON_CP2AUD_BCK 16 +#define CLK_GOUT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S 17 +#define CLK_GOUT_DISPAUD_DECON_ECLK 18 +#define CLK_GOUT_DISPAUD_DECON_VCLK 19 +#define CLK_GOUT_DISPAUD_MI2S_AMP_I2SCODCLKI 20 +#define CLK_GOUT_DISPAUD_MI2S_AUD_I2SCODCLKI 21 +#define CLK_GOUT_DISPAUD_MIXER_AUD_SYSCLK 22 +#define CLK_GOUT_DISPAUD_MUX_AUD_PLL 23 +#define CLK_GOUT_DISPAUD_MUX_AUD_PLL_CON 24 +#define CLK_GOUT_DISPAUD_MUX_BUS_USER 25 +#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK 26 +#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK_USER 27 +#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK 28 +#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK_USER 29 +#define CLK_GOUT_DISPAUD_MUX_MI2S 30 +#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER 31 +#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON 32 +#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER 33 +#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON 34 +#define CLK_GOUT_DISPAUD_MUX_PLL 35 +#define CLK_GOUT_DISPAUD_MUX_PLL_CON 36 +#define CLK_MOUT_DISPAUD_BUS_USER 37 +#define CLK_MOUT_DISPAUD_DECON_ECLK 38 +#define CLK_MOUT_DISPAUD_DECON_ECLK_USER 39 +#define CLK_MOUT_DISPAUD_DECON_VCLK 40 +#define CLK_MOUT_DISPAUD_DECON_VCLK_USER 41 +#define CLK_MOUT_DISPAUD_MI2S 42 +#define DISPAUD_NR_CLK 43 + +/* CMU_FSYS */ +#define CLK_FOUT_FSYS_USB_PLL 1 +#define CLK_GOUT_FSYS_BUSP3_HCLK 2 +#define CLK_GOUT_FSYS_MMC0_ACLK 3 +#define CLK_GOUT_FSYS_MMC1_ACLK 4 +#define CLK_GOUT_FSYS_MMC2_ACLK 5 +#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER 6 +#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON 7 +#define CLK_GOUT_FSYS_MUX_USB_PLL 8 +#define CLK_GOUT_FSYS_MUX_USB_PLL_CON 9 +#define CLK_GOUT_FSYS_PDMA0_ACLK_PDMA0 10 +#define CLK_GOUT_FSYS_PPMU_ACLK 11 +#define CLK_GOUT_FSYS_PPMU_PCLK 12 +#define CLK_GOUT_FSYS_SROMC_HCLK 13 +#define CLK_GOUT_FSYS_UPSIZER_BUS1_ACLK 14 +#define CLK_GOUT_FSYS_USB20DRD_ACLK_HSDRD 15 +#define CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL 16 +#define CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK 17 +#define FSYS_NR_CLK 18 + +/* CMU_G3D */ +#define CLK_DOUT_G3D_APB 1 +#define CLK_DOUT_G3D_BUS 2 +#define CLK_FOUT_G3D_PLL 3 +#define CLK_GOUT_G3D_ASYNCS_D0_CLK 4 +#define CLK_GOUT_G3D_ASYNC_PCLKM 5 +#define CLK_GOUT_G3D_CLK 6 +#define CLK_GOUT_G3D_MUX 7 +#define CLK_GOUT_G3D_MUX_PLL 8 +#define CLK_GOUT_G3D_MUX_PLL_CON 9 +#define CLK_GOUT_G3D_MUX_SWITCH_USER 10 +#define CLK_GOUT_G3D_PPMU_ACLK 11 +#define CLK_GOUT_G3D_PPMU_PCLK 12 +#define CLK_GOUT_G3D_QE_ACLK 13 +#define CLK_GOUT_G3D_QE_PCLK 14 +#define CLK_GOUT_G3D_SYSREG_PCLK 15 +#define CLK_MOUT_G3D 16 +#define CLK_MOUT_G3D_SWITCH_USER 17 +#define G3D_NR_CLK 18 + +/* CMU_ISP */ +#define CLK_DOUT_ISP_APB 1 +#define CLK_DOUT_ISP_CAM_HALF 2 +#define CLK_FOUT_ISP_PLL 3 +#define CLK_GOUT_ISP_CAM 4 +#define CLK_GOUT_ISP_CAM_HALF 5 +#define CLK_GOUT_ISP_ISPD 6 +#define CLK_GOUT_ISP_ISPD_PPMU 7 +#define CLK_GOUT_ISP_MUX_CAM 8 +#define CLK_GOUT_ISP_MUX_CAM_USER 9 +#define CLK_GOUT_ISP_MUX_ISP 10 +#define CLK_GOUT_ISP_MUX_ISPD 11 +#define CLK_GOUT_ISP_MUX_PLL 12 +#define CLK_GOUT_ISP_MUX_PLL_CON 13 +#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER 14 +#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON 15 +#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER 16 +#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON 17 +#define CLK_GOUT_ISP_MUX_USER 18 +#define CLK_GOUT_ISP_MUX_VRA 19 +#define CLK_GOUT_ISP_MUX_VRA_USER 20 +#define CLK_GOUT_ISP_VRA 21 +#define CLK_MOUT_ISP_CAM 22 +#define CLK_MOUT_ISP_CAM_USER 23 +#define CLK_MOUT_ISP_ISP 24 +#define CLK_MOUT_ISP_ISPD 25 +#define CLK_MOUT_ISP_USER 26 +#define CLK_MOUT_ISP_VRA 27 +#define CLK_MOUT_ISP_VRA_USER 28 +#define ISP_NR_CLK 29 + +/* CMU_MFCMSCL */ +#define CLK_DOUT_MFCMSCL_APB 1 +#define CLK_GOUT_MFCMSCL_MFC 2 +#define CLK_GOUT_MFCMSCL_MSCL 3 +#define CLK_GOUT_MFCMSCL_MSCL_BI 4 +#define CLK_GOUT_MFCMSCL_MSCL_D 5 +#define CLK_GOUT_MFCMSCL_MSCL_JPEG 6 +#define CLK_GOUT_MFCMSCL_MSCL_POLY 7 +#define CLK_GOUT_MFCMSCL_MSCL_PPMU 8 +#define CLK_GOUT_MFCMSCL_MUX_MFC_USER 9 +#define CLK_GOUT_MFCMSCL_MUX_MSCL_USER 10 +#define CLK_MOUT_MFCMSCL_MFC_USER 11 +#define CLK_MOUT_MFCMSCL_MSCL_USER 12 +#define MFCMSCL_NR_CLK 13 + +/* CMU_PERI */ +#define CLK_GOUT_PERI_BUSP1_PERIC0_HCLK 1 +#define CLK_GOUT_PERI_GPIO2_PCLK 2 +#define CLK_GOUT_PERI_GPIO5_PCLK 3 +#define CLK_GOUT_PERI_GPIO6_PCLK 4 +#define CLK_GOUT_PERI_GPIO7_PCLK 5 +#define CLK_GOUT_PERI_HSI2C1_IPCLK 6 +#define CLK_GOUT_PERI_HSI2C2_IPCLK 7 +#define CLK_GOUT_PERI_HSI2C3_IPCLK 8 +#define CLK_GOUT_PERI_HSI2C4_IPCLK 9 +#define CLK_GOUT_PERI_HSI2C5_IPCLK 10 +#define CLK_GOUT_PERI_HSI2C6_IPCLK 11 +#define CLK_GOUT_PERI_I2C0_PCLK 12 +#define CLK_GOUT_PERI_I2C1_PCLK 13 +#define CLK_GOUT_PERI_I2C2_PCLK 14 +#define CLK_GOUT_PERI_I2C3_PCLK 15 +#define CLK_GOUT_PERI_I2C4_PCLK 16 +#define CLK_GOUT_PERI_I2C5_PCLK 17 +#define CLK_GOUT_PERI_I2C6_PCLK 18 +#define CLK_GOUT_PERI_I2C7_PCLK 19 +#define CLK_GOUT_PERI_I2C8_PCLK 20 +#define CLK_GOUT_PERI_MCT_PCLK 21 +#define CLK_GOUT_PERI_PWM_MOTOR_OSCCLK 22 +#define CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0 23 +#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL0_PCLK 24 +#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL1_PCLK 25 +#define CLK_GOUT_PERI_SFRIF_TMU_PCLK 26 +#define CLK_GOUT_PERI_SPI0_PCLK 27 +#define CLK_GOUT_PERI_SPI0_SPI_EXT_CLK 28 +#define CLK_GOUT_PERI_SPI1_PCLK 29 +#define CLK_GOUT_PERI_SPI1_SPI_EXT_CLK 30 +#define CLK_GOUT_PERI_SPI2_PCLK 31 +#define CLK_GOUT_PERI_SPI2_SPI_EXT_CLK 32 +#define CLK_GOUT_PERI_SPI3_PCLK 33 +#define CLK_GOUT_PERI_SPI3_SPI_EXT_CLK 34 +#define CLK_GOUT_PERI_SPI4_PCLK 35 +#define CLK_GOUT_PERI_SPI4_SPI_EXT_CLK 36 +#define CLK_GOUT_PERI_TMU_CLK 37 +#define CLK_GOUT_PERI_TMU_CPUCL0_CLK 38 +#define CLK_GOUT_PERI_TMU_CPUCL1_CLK 39 +#define CLK_GOUT_PERI_UART0_EXT_UCLK 40 +#define CLK_GOUT_PERI_UART0_PCLK 41 +#define CLK_GOUT_PERI_UART1_EXT_UCLK 42 +#define CLK_GOUT_PERI_UART1_PCLK 43 +#define CLK_GOUT_PERI_UART2_EXT_UCLK 44 +#define CLK_GOUT_PERI_UART2_PCLK 45 +#define CLK_GOUT_PERI_WDT_CPUCL0_PCLK 46 +#define CLK_GOUT_PERI_WDT_CPUCL1_PCLK 47 +#define PERI_NR_CLK 48 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS7870_H */ diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bindings/clock/samsung,exynos990.h new file mode 100644 index 000000000000..6b9df09d2822 --- /dev/null +++ b/include/dt-bindings/clock/samsung,exynos990.h @@ -0,0 +1,257 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2024 Igor Belwon <igor.belwon@mentallysanemainliners.org> + * + * Device Tree binding constants for Exynos990 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_990_H +#define _DT_BINDINGS_CLOCK_EXYNOS_990_H + +/* CMU_TOP */ +#define CLK_FOUT_SHARED0_PLL 1 +#define CLK_FOUT_SHARED1_PLL 2 +#define CLK_FOUT_SHARED2_PLL 3 +#define CLK_FOUT_SHARED3_PLL 4 +#define CLK_FOUT_SHARED4_PLL 5 +#define CLK_FOUT_G3D_PLL 6 +#define CLK_FOUT_MMC_PLL 7 +#define CLK_MOUT_PLL_SHARED0 8 +#define CLK_MOUT_PLL_SHARED1 9 +#define CLK_MOUT_PLL_SHARED2 10 +#define CLK_MOUT_PLL_SHARED3 11 +#define CLK_MOUT_PLL_SHARED4 12 +#define CLK_MOUT_PLL_MMC 13 +#define CLK_MOUT_PLL_G3D 14 +#define CLK_MOUT_CMU_APM_BUS 15 +#define CLK_MOUT_CMU_AUD_CPU 16 +#define CLK_MOUT_CMU_BUS0_BUS 17 +#define CLK_MOUT_CMU_BUS1_BUS 18 +#define CLK_MOUT_CMU_BUS1_SSS 19 +#define CLK_MOUT_CMU_CIS_CLK0 20 +#define CLK_MOUT_CMU_CIS_CLK1 21 +#define CLK_MOUT_CMU_CIS_CLK2 22 +#define CLK_MOUT_CMU_CIS_CLK3 23 +#define CLK_MOUT_CMU_CIS_CLK4 24 +#define CLK_MOUT_CMU_CIS_CLK5 25 +#define CLK_MOUT_CMU_CMU_BOOST 26 +#define CLK_MOUT_CMU_CORE_BUS 27 +#define CLK_MOUT_CMU_CPUCL0_DBG_BUS 28 +#define CLK_MOUT_CMU_CPUCL0_SWITCH 29 +#define CLK_MOUT_CMU_CPUCL1_SWITCH 30 +#define CLK_MOUT_CMU_CPUCL2_BUSP 31 +#define CLK_MOUT_CMU_CPUCL2_SWITCH 32 +#define CLK_MOUT_CMU_CSIS_BUS 33 +#define CLK_MOUT_CMU_CSIS_OIS_MCU 34 +#define CLK_MOUT_CMU_DNC_BUS 35 +#define CLK_MOUT_CMU_DNC_BUSM 36 +#define CLK_MOUT_CMU_DNS_BUS 37 +#define CLK_MOUT_CMU_DPU 38 +#define CLK_MOUT_CMU_DPU_ALT 39 +#define CLK_MOUT_CMU_DSP_BUS 40 +#define CLK_MOUT_CMU_G2D_G2D 41 +#define CLK_MOUT_CMU_G2D_MSCL 42 +#define CLK_MOUT_CMU_HPM 43 +#define CLK_MOUT_CMU_HSI0_BUS 44 +#define CLK_MOUT_CMU_HSI0_DPGTC 45 +#define CLK_MOUT_CMU_HSI0_USB31DRD 46 +#define CLK_MOUT_CMU_HSI0_USBDP_DEBUG 47 +#define CLK_MOUT_CMU_HSI1_BUS 48 +#define CLK_MOUT_CMU_HSI1_MMC_CARD 49 +#define CLK_MOUT_CMU_HSI1_PCIE 50 +#define CLK_MOUT_CMU_HSI1_UFS_CARD 51 +#define CLK_MOUT_CMU_HSI1_UFS_EMBD 52 +#define CLK_MOUT_CMU_HSI2_BUS 53 +#define CLK_MOUT_CMU_HSI2_PCIE 54 +#define CLK_MOUT_CMU_IPP_BUS 55 +#define CLK_MOUT_CMU_ITP_BUS 56 +#define CLK_MOUT_CMU_MCSC_BUS 57 +#define CLK_MOUT_CMU_MCSC_GDC 58 +#define CLK_MOUT_CMU_CMU_BOOST_CPU 59 +#define CLK_MOUT_CMU_MFC0_MFC0 60 +#define CLK_MOUT_CMU_MFC0_WFD 61 +#define CLK_MOUT_CMU_MIF_BUSP 62 +#define CLK_MOUT_CMU_MIF_SWITCH 63 +#define CLK_MOUT_CMU_NPU_BUS 64 +#define CLK_MOUT_CMU_PERIC0_BUS 65 +#define CLK_MOUT_CMU_PERIC0_IP 66 +#define CLK_MOUT_CMU_PERIC1_BUS 67 +#define CLK_MOUT_CMU_PERIC1_IP 68 +#define CLK_MOUT_CMU_PERIS_BUS 69 +#define CLK_MOUT_CMU_SSP_BUS 70 +#define CLK_MOUT_CMU_TNR_BUS 71 +#define CLK_MOUT_CMU_VRA_BUS 72 +#define CLK_DOUT_CMU_APM_BUS 73 +#define CLK_DOUT_CMU_AUD_CPU 74 +#define CLK_DOUT_CMU_BUS0_BUS 75 +#define CLK_DOUT_CMU_BUS1_BUS 76 +#define CLK_DOUT_CMU_BUS1_SSS 77 +#define CLK_DOUT_CMU_CIS_CLK0 78 +#define CLK_DOUT_CMU_CIS_CLK1 79 +#define CLK_DOUT_CMU_CIS_CLK2 80 +#define CLK_DOUT_CMU_CIS_CLK3 81 +#define CLK_DOUT_CMU_CIS_CLK4 82 +#define CLK_DOUT_CMU_CIS_CLK5 83 +#define CLK_DOUT_CMU_CMU_BOOST 84 +#define CLK_DOUT_CMU_CORE_BUS 85 +#define CLK_DOUT_CMU_CPUCL0_DBG_BUS 86 +#define CLK_DOUT_CMU_CPUCL0_SWITCH 87 +#define CLK_DOUT_CMU_CPUCL1_SWITCH 88 +#define CLK_DOUT_CMU_CPUCL2_BUSP 89 +#define CLK_DOUT_CMU_CPUCL2_SWITCH 90 +#define CLK_DOUT_CMU_CSIS_BUS 91 +#define CLK_DOUT_CMU_CSIS_OIS_MCU 92 +#define CLK_DOUT_CMU_DNC_BUS 93 +#define CLK_DOUT_CMU_DNC_BUSM 94 +#define CLK_DOUT_CMU_DNS_BUS 95 +#define CLK_DOUT_CMU_DSP_BUS 96 +#define CLK_DOUT_CMU_G2D_G2D 97 +#define CLK_DOUT_CMU_G2D_MSCL 98 +#define CLK_DOUT_CMU_G3D_SWITCH 99 +#define CLK_DOUT_CMU_HPM 100 +#define CLK_DOUT_CMU_HSI0_BUS 101 +#define CLK_DOUT_CMU_HSI0_DPGTC 102 +#define CLK_DOUT_CMU_HSI0_USB31DRD 103 +#define CLK_DOUT_CMU_HSI0_USBDP_DEBUG 104 +#define CLK_DOUT_CMU_HSI1_BUS 105 +#define CLK_DOUT_CMU_HSI1_MMC_CARD 106 +#define CLK_DOUT_CMU_HSI1_PCIE 107 +#define CLK_DOUT_CMU_HSI1_UFS_CARD 108 +#define CLK_DOUT_CMU_HSI1_UFS_EMBD 109 +#define CLK_DOUT_CMU_HSI2_BUS 110 +#define CLK_DOUT_CMU_HSI2_PCIE 111 +#define CLK_DOUT_CMU_IPP_BUS 112 +#define CLK_DOUT_CMU_ITP_BUS 113 +#define CLK_DOUT_CMU_MCSC_BUS 114 +#define CLK_DOUT_CMU_MCSC_GDC 115 +#define CLK_DOUT_CMU_CMU_BOOST_CPU 116 +#define CLK_DOUT_CMU_MFC0_MFC0 117 +#define CLK_DOUT_CMU_MFC0_WFD 118 +#define CLK_DOUT_CMU_MIF_BUSP 119 +#define CLK_DOUT_CMU_NPU_BUS 120 +#define CLK_DOUT_CMU_OTP 121 +#define CLK_DOUT_CMU_PERIC0_BUS 122 +#define CLK_DOUT_CMU_PERIC0_IP 123 +#define CLK_DOUT_CMU_PERIC1_BUS 124 +#define CLK_DOUT_CMU_PERIC1_IP 125 +#define CLK_DOUT_CMU_PERIS_BUS 126 +#define CLK_DOUT_CMU_SSP_BUS 127 +#define CLK_DOUT_CMU_TNR_BUS 128 +#define CLK_DOUT_CMU_VRA_BUS 129 +#define CLK_DOUT_CMU_DPU 130 +#define CLK_DOUT_CMU_DPU_ALT 131 +#define CLK_DOUT_CMU_SHARED0_DIV2 132 +#define CLK_DOUT_CMU_SHARED0_DIV3 133 +#define CLK_DOUT_CMU_SHARED0_DIV4 134 +#define CLK_DOUT_CMU_SHARED1_DIV2 135 +#define CLK_DOUT_CMU_SHARED1_DIV3 136 +#define CLK_DOUT_CMU_SHARED1_DIV4 137 +#define CLK_DOUT_CMU_SHARED2_DIV2 138 +#define CLK_DOUT_CMU_SHARED4_DIV2 139 +#define CLK_DOUT_CMU_SHARED4_DIV3 140 +#define CLK_DOUT_CMU_SHARED4_DIV4 141 +#define CLK_GOUT_CMU_G3D_BUS 142 +#define CLK_GOUT_CMU_MIF_SWITCH 143 +#define CLK_GOUT_CMU_APM_BUS 144 +#define CLK_GOUT_CMU_AUD_CPU 145 +#define CLK_GOUT_CMU_BUS0_BUS 146 +#define CLK_GOUT_CMU_BUS1_BUS 147 +#define CLK_GOUT_CMU_BUS1_SSS 148 +#define CLK_GOUT_CMU_CIS_CLK0 149 +#define CLK_GOUT_CMU_CIS_CLK1 150 +#define CLK_GOUT_CMU_CIS_CLK2 151 +#define CLK_GOUT_CMU_CIS_CLK3 152 +#define CLK_GOUT_CMU_CIS_CLK4 153 +#define CLK_GOUT_CMU_CIS_CLK5 154 +#define CLK_GOUT_CMU_CORE_BUS 155 +#define CLK_GOUT_CMU_CPUCL0_DBG_BUS 156 +#define CLK_GOUT_CMU_CPUCL0_SWITCH 157 +#define CLK_GOUT_CMU_CPUCL1_SWITCH 158 +#define CLK_GOUT_CMU_CPUCL2_BUSP 159 +#define CLK_GOUT_CMU_CPUCL2_SWITCH 160 +#define CLK_GOUT_CMU_CSIS_BUS 161 +#define CLK_GOUT_CMU_CSIS_OIS_MCU 162 +#define CLK_GOUT_CMU_DNC_BUS 163 +#define CLK_GOUT_CMU_DNC_BUSM 164 +#define CLK_GOUT_CMU_DNS_BUS 165 +#define CLK_GOUT_CMU_DPU 166 +#define CLK_GOUT_CMU_DPU_BUS 167 +#define CLK_GOUT_CMU_DSP_BUS 168 +#define CLK_GOUT_CMU_G2D_G2D 169 +#define CLK_GOUT_CMU_G2D_MSCL 170 +#define CLK_GOUT_CMU_G3D_SWITCH 171 +#define CLK_GOUT_CMU_HPM 172 +#define CLK_GOUT_CMU_HSI0_BUS 173 +#define CLK_GOUT_CMU_HSI0_DPGTC 174 +#define CLK_GOUT_CMU_HSI0_USB31DRD 175 +#define CLK_GOUT_CMU_HSI0_USBDP_DEBUG 176 +#define CLK_GOUT_CMU_HSI1_BUS 177 +#define CLK_GOUT_CMU_HSI1_MMC_CARD 178 +#define CLK_GOUT_CMU_HSI1_PCIE 179 +#define CLK_GOUT_CMU_HSI1_UFS_CARD 180 +#define CLK_GOUT_CMU_HSI1_UFS_EMBD 181 +#define CLK_GOUT_CMU_HSI2_BUS 182 +#define CLK_GOUT_CMU_HSI2_PCIE 183 +#define CLK_GOUT_CMU_IPP_BUS 184 +#define CLK_GOUT_CMU_ITP_BUS 185 +#define CLK_GOUT_CMU_MCSC_BUS 186 +#define CLK_GOUT_CMU_MCSC_GDC 187 +#define CLK_GOUT_CMU_MFC0_MFC0 188 +#define CLK_GOUT_CMU_MFC0_WFD 189 +#define CLK_GOUT_CMU_MIF_BUSP 190 +#define CLK_GOUT_CMU_NPU_BUS 191 +#define CLK_GOUT_CMU_PERIC0_BUS 192 +#define CLK_GOUT_CMU_PERIC0_IP 193 +#define CLK_GOUT_CMU_PERIC1_BUS 194 +#define CLK_GOUT_CMU_PERIC1_IP 195 +#define CLK_GOUT_CMU_PERIS_BUS 196 +#define CLK_GOUT_CMU_SSP_BUS 197 +#define CLK_GOUT_CMU_TNR_BUS 198 +#define CLK_GOUT_CMU_VRA_BUS 199 + +/* CMU_HSI0 */ +#define CLK_MOUT_HSI0_BUS_USER 1 +#define CLK_MOUT_HSI0_USB31DRD_USER 2 +#define CLK_MOUT_HSI0_USBDP_DEBUG_USER 3 +#define CLK_MOUT_HSI0_DPGTC_USER 4 +#define CLK_GOUT_HSI0_DP_LINK_DP_GTC_CLK 5 +#define CLK_GOUT_HSI0_DP_LINK_PCLK 6 +#define CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK 7 +#define CLK_GOUT_HSI0_LHM_AXI_P_HSI0_CLK 8 +#define CLK_GOUT_HSI0_PPMU_HSI0_BUS1_ACLK 9 +#define CLK_GOUT_HSI0_PPMU_HSI0_BUS1_PCLK 10 +#define CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK 11 +#define CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2 12 +#define CLK_GOUT_HSI0_SYSREG_HSI0_PCLK 13 +#define CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL 14 +#define CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY 15 +#define CLK_GOUT_HSI0_USB31DRD_USB31DRD_REF_CLK_40 16 +#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_REF_SOC_PLL 17 +#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_SCL_APB 18 +#define CLK_GOUT_HSI0_USB31DRD_USBPCS_APB_CLK 19 +#define CLK_GOUT_HSI0_VGEN_LITE_HSI0_CLK 20 +#define CLK_GOUT_HSI0_CMU_HSI0_PCLK 21 +#define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22 + +/* CMU_PERIS */ +#define CLK_MOUT_PERIS_BUS_USER 1 +#define CLK_MOUT_PERIS_CLK_PERIS_GIC 2 +#define CLK_GOUT_PERIS_SYSREG_PERIS_PCLK 3 +#define CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK 4 +#define CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK 5 +#define CLK_CLK_PERIS_PERIS_CMU_PERIS_PCLK 6 +#define CLK_GOUT_PERIS_CLK_PERIS_BUSP_CLK 7 +#define CLK_GOUT_PERIS_CLK_PERIS_OSCCLK_CLK 8 +#define CLK_GOUT_PERIS_CLK_PERIS_GIC_CLK 9 +#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM 10 +#define CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK 11 +#define CLK_GOUT_PERIS_GIC_CLK 12 +#define CLK_GOUT_PERIS_LHM_AXI_P_PERIS_CLK 13 +#define CLK_GOUT_PERIS_MCT_PCLK 14 +#define CLK_GOUT_PERIS_OTP_CON_TOP_PCLK 15 +#define CLK_GOUT_PERIS_D_TZPC_PERIS_PCLK 16 +#define CLK_GOUT_PERIS_TMU_TOP_PCLK 17 +#define CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK 18 +#define CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK 19 + +#endif diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h index 0c681f2ba3d0..5e6896e9627f 100644 --- a/include/dt-bindings/clock/samsung,exynosautov920.h +++ b/include/dt-bindings/clock/samsung,exynosautov920.h @@ -162,6 +162,57 @@ #define DOUT_CLKCMU_TAA_NOC 146 #define DOUT_TCXO_DIV2 147 +/* CMU_CPUCL0 */ +#define CLK_FOUT_CPUCL0_PLL 1 + +#define CLK_MOUT_PLL_CPUCL0 2 +#define CLK_MOUT_CPUCL0_CLUSTER_USER 3 +#define CLK_MOUT_CPUCL0_DBG_USER 4 +#define CLK_MOUT_CPUCL0_SWITCH_USER 5 +#define CLK_MOUT_CPUCL0_CLUSTER 6 +#define CLK_MOUT_CPUCL0_CORE 7 + +#define CLK_DOUT_CLUSTER0_ACLK 8 +#define CLK_DOUT_CLUSTER0_ATCLK 9 +#define CLK_DOUT_CLUSTER0_MPCLK 10 +#define CLK_DOUT_CLUSTER0_PCLK 11 +#define CLK_DOUT_CLUSTER0_PERIPHCLK 12 +#define CLK_DOUT_CPUCL0_DBG_NOC 13 +#define CLK_DOUT_CPUCL0_DBG_PCLKDBG 14 +#define CLK_DOUT_CPUCL0_NOCP 15 + +/* CMU_CPUCL1 */ +#define CLK_FOUT_CPUCL1_PLL 1 + +#define CLK_MOUT_PLL_CPUCL1 2 +#define CLK_MOUT_CPUCL1_CLUSTER_USER 3 +#define CLK_MOUT_CPUCL1_SWITCH_USER 4 +#define CLK_MOUT_CPUCL1_CLUSTER 5 +#define CLK_MOUT_CPUCL1_CORE 6 + +#define CLK_DOUT_CLUSTER1_ACLK 7 +#define CLK_DOUT_CLUSTER1_ATCLK 8 +#define CLK_DOUT_CLUSTER1_MPCLK 9 +#define CLK_DOUT_CLUSTER1_PCLK 10 +#define CLK_DOUT_CLUSTER1_PERIPHCLK 11 +#define CLK_DOUT_CPUCL1_NOCP 12 + +/* CMU_CPUCL2 */ +#define CLK_FOUT_CPUCL2_PLL 1 + +#define CLK_MOUT_PLL_CPUCL2 2 +#define CLK_MOUT_CPUCL2_CLUSTER_USER 3 +#define CLK_MOUT_CPUCL2_SWITCH_USER 4 +#define CLK_MOUT_CPUCL2_CLUSTER 5 +#define CLK_MOUT_CPUCL2_CORE 6 + +#define CLK_DOUT_CLUSTER2_ACLK 7 +#define CLK_DOUT_CLUSTER2_ATCLK 8 +#define CLK_DOUT_CLUSTER2_MPCLK 9 +#define CLK_DOUT_CLUSTER2_PCLK 10 +#define CLK_DOUT_CLUSTER2_PERIPHCLK 11 +#define CLK_DOUT_CPUCL2_NOCP 12 + /* CMU_PERIC0 */ #define CLK_MOUT_PERIC0_IP_USER 1 #define CLK_MOUT_PERIC0_NOC_USER 2 diff --git a/include/dt-bindings/clock/sophgo,sg2044-clk.h b/include/dt-bindings/clock/sophgo,sg2044-clk.h new file mode 100644 index 000000000000..d9adca42548e --- /dev/null +++ b/include/dt-bindings/clock/sophgo,sg2044-clk.h @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (C) 2024 Inochi Amaoto <inochiama@gmail.com> + */ + +#ifndef __DT_BINDINGS_SOPHGO_SG2044_CLK_H__ +#define __DT_BINDINGS_SOPHGO_SG2044_CLK_H__ + +#define CLK_DIV_AP_SYS_FIXED 0 +#define CLK_DIV_AP_SYS_MAIN 1 +#define CLK_DIV_RP_SYS_FIXED 2 +#define CLK_DIV_RP_SYS_MAIN 3 +#define CLK_DIV_TPU_SYS_FIXED 4 +#define CLK_DIV_TPU_SYS_MAIN 5 +#define CLK_DIV_NOC_SYS_FIXED 6 +#define CLK_DIV_NOC_SYS_MAIN 7 +#define CLK_DIV_VC_SRC0_FIXED 8 +#define CLK_DIV_VC_SRC0_MAIN 9 +#define CLK_DIV_VC_SRC1_FIXED 10 +#define CLK_DIV_VC_SRC1_MAIN 11 +#define CLK_DIV_CXP_MAC_FIXED 12 +#define CLK_DIV_CXP_MAC_MAIN 13 +#define CLK_DIV_DDR0_FIXED 14 +#define CLK_DIV_DDR0_MAIN 15 +#define CLK_DIV_DDR1_FIXED 16 +#define CLK_DIV_DDR1_MAIN 17 +#define CLK_DIV_DDR2_FIXED 18 +#define CLK_DIV_DDR2_MAIN 19 +#define CLK_DIV_DDR3_FIXED 20 +#define CLK_DIV_DDR3_MAIN 21 +#define CLK_DIV_DDR4_FIXED 22 +#define CLK_DIV_DDR4_MAIN 23 +#define CLK_DIV_DDR5_FIXED 24 +#define CLK_DIV_DDR5_MAIN 25 +#define CLK_DIV_DDR6_FIXED 26 +#define CLK_DIV_DDR6_MAIN 27 +#define CLK_DIV_DDR7_FIXED 28 +#define CLK_DIV_DDR7_MAIN 29 +#define CLK_DIV_TOP_50M 30 +#define CLK_DIV_TOP_AXI0 31 +#define CLK_DIV_TOP_AXI_HSPERI 32 +#define CLK_DIV_TIMER0 33 +#define CLK_DIV_TIMER1 34 +#define CLK_DIV_TIMER2 35 +#define CLK_DIV_TIMER3 36 +#define CLK_DIV_TIMER4 37 +#define CLK_DIV_TIMER5 38 +#define CLK_DIV_TIMER6 39 +#define CLK_DIV_TIMER7 40 +#define CLK_DIV_CXP_TEST_PHY 41 +#define CLK_DIV_CXP_TEST_ETH_PHY 42 +#define CLK_DIV_C2C0_TEST_PHY 43 +#define CLK_DIV_C2C1_TEST_PHY 44 +#define CLK_DIV_PCIE_1G 45 +#define CLK_DIV_UART_500M 46 +#define CLK_DIV_GPIO_DB 47 +#define CLK_DIV_SD 48 +#define CLK_DIV_SD_100K 49 +#define CLK_DIV_EMMC 50 +#define CLK_DIV_EMMC_100K 51 +#define CLK_DIV_EFUSE 52 +#define CLK_DIV_TX_ETH0 53 +#define CLK_DIV_PTP_REF_I_ETH0 54 +#define CLK_DIV_REF_ETH0 55 +#define CLK_DIV_PKA 56 +#define CLK_MUX_DDR0 57 +#define CLK_MUX_DDR1 58 +#define CLK_MUX_DDR2 59 +#define CLK_MUX_DDR3 60 +#define CLK_MUX_DDR4 61 +#define CLK_MUX_DDR5 62 +#define CLK_MUX_DDR6 63 +#define CLK_MUX_DDR7 64 +#define CLK_MUX_NOC_SYS 65 +#define CLK_MUX_TPU_SYS 66 +#define CLK_MUX_RP_SYS 67 +#define CLK_MUX_AP_SYS 68 +#define CLK_MUX_VC_SRC0 69 +#define CLK_MUX_VC_SRC1 70 +#define CLK_MUX_CXP_MAC 71 +#define CLK_GATE_AP_SYS 72 +#define CLK_GATE_RP_SYS 73 +#define CLK_GATE_TPU_SYS 74 +#define CLK_GATE_NOC_SYS 75 +#define CLK_GATE_VC_SRC0 76 +#define CLK_GATE_VC_SRC1 77 +#define CLK_GATE_DDR0 78 +#define CLK_GATE_DDR1 79 +#define CLK_GATE_DDR2 80 +#define CLK_GATE_DDR3 81 +#define CLK_GATE_DDR4 82 +#define CLK_GATE_DDR5 83 +#define CLK_GATE_DDR6 84 +#define CLK_GATE_DDR7 85 +#define CLK_GATE_TOP_50M 86 +#define CLK_GATE_SC_RX 87 +#define CLK_GATE_SC_RX_X0Y1 88 +#define CLK_GATE_TOP_AXI0 89 +#define CLK_GATE_INTC0 90 +#define CLK_GATE_INTC1 91 +#define CLK_GATE_INTC2 92 +#define CLK_GATE_INTC3 93 +#define CLK_GATE_MAILBOX0 94 +#define CLK_GATE_MAILBOX1 95 +#define CLK_GATE_MAILBOX2 96 +#define CLK_GATE_MAILBOX3 97 +#define CLK_GATE_TOP_AXI_HSPERI 98 +#define CLK_GATE_APB_TIMER 99 +#define CLK_GATE_TIMER0 100 +#define CLK_GATE_TIMER1 101 +#define CLK_GATE_TIMER2 102 +#define CLK_GATE_TIMER3 103 +#define CLK_GATE_TIMER4 104 +#define CLK_GATE_TIMER5 105 +#define CLK_GATE_TIMER6 106 +#define CLK_GATE_TIMER7 107 +#define CLK_GATE_CXP_CFG 108 +#define CLK_GATE_CXP_MAC 109 +#define CLK_GATE_CXP_TEST_PHY 110 +#define CLK_GATE_CXP_TEST_ETH_PHY 111 +#define CLK_GATE_PCIE_1G 112 +#define CLK_GATE_C2C0_TEST_PHY 113 +#define CLK_GATE_C2C1_TEST_PHY 114 +#define CLK_GATE_UART_500M 115 +#define CLK_GATE_APB_UART 116 +#define CLK_GATE_APB_SPI 117 +#define CLK_GATE_AHB_SPIFMC 118 +#define CLK_GATE_APB_I2C 119 +#define CLK_GATE_AXI_DBG_I2C 120 +#define CLK_GATE_GPIO_DB 121 +#define CLK_GATE_APB_GPIO_INTR 122 +#define CLK_GATE_APB_GPIO 123 +#define CLK_GATE_SD 124 +#define CLK_GATE_AXI_SD 125 +#define CLK_GATE_SD_100K 126 +#define CLK_GATE_EMMC 127 +#define CLK_GATE_AXI_EMMC 128 +#define CLK_GATE_EMMC_100K 129 +#define CLK_GATE_EFUSE 130 +#define CLK_GATE_APB_EFUSE 131 +#define CLK_GATE_SYSDMA_AXI 132 +#define CLK_GATE_TX_ETH0 133 +#define CLK_GATE_AXI_ETH0 134 +#define CLK_GATE_PTP_REF_I_ETH0 135 +#define CLK_GATE_REF_ETH0 136 +#define CLK_GATE_APB_RTC 137 +#define CLK_GATE_APB_PWM 138 +#define CLK_GATE_APB_WDT 139 +#define CLK_GATE_AXI_SRAM 140 +#define CLK_GATE_AHB_ROM 141 +#define CLK_GATE_PKA 142 + +#endif /* __DT_BINDINGS_SOPHGO_SG2044_CLK_H__ */ diff --git a/include/dt-bindings/clock/sophgo,sg2044-pll.h b/include/dt-bindings/clock/sophgo,sg2044-pll.h new file mode 100644 index 000000000000..817d45e700cc --- /dev/null +++ b/include/dt-bindings/clock/sophgo,sg2044-pll.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (C) 2024 Inochi Amaoto <inochiama@gmail.com> + */ + +#ifndef __DT_BINDINGS_SOPHGO_SG2044_PLL_H__ +#define __DT_BINDINGS_SOPHGO_SG2044_PLL_H__ + +#define CLK_FPLL0 0 +#define CLK_FPLL1 1 +#define CLK_FPLL2 2 +#define CLK_DPLL0 3 +#define CLK_DPLL1 4 +#define CLK_DPLL2 5 +#define CLK_DPLL3 6 +#define CLK_DPLL4 7 +#define CLK_DPLL5 8 +#define CLK_DPLL6 9 +#define CLK_DPLL7 10 +#define CLK_MPLL0 11 +#define CLK_MPLL1 12 +#define CLK_MPLL2 13 +#define CLK_MPLL3 14 +#define CLK_MPLL4 15 +#define CLK_MPLL5 16 + +#endif /* __DT_BINDINGS_SOPHGO_SG2044_PLL_H__ */ diff --git a/include/dt-bindings/clock/spacemit,k1-syscon.h b/include/dt-bindings/clock/spacemit,k1-syscon.h new file mode 100644 index 000000000000..35968ae98246 --- /dev/null +++ b/include/dt-bindings/clock/spacemit,k1-syscon.h @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2024-2025 Haylen Chu <heylenay@outlook.com> + */ + +#ifndef _DT_BINDINGS_SPACEMIT_CCU_H_ +#define _DT_BINDINGS_SPACEMIT_CCU_H_ + +/* APBS (PLL) clocks */ +#define CLK_PLL1 0 +#define CLK_PLL2 1 +#define CLK_PLL3 2 +#define CLK_PLL1_D2 3 +#define CLK_PLL1_D3 4 +#define CLK_PLL1_D4 5 +#define CLK_PLL1_D5 6 +#define CLK_PLL1_D6 7 +#define CLK_PLL1_D7 8 +#define CLK_PLL1_D8 9 +#define CLK_PLL1_D11 10 +#define CLK_PLL1_D13 11 +#define CLK_PLL1_D23 12 +#define CLK_PLL1_D64 13 +#define CLK_PLL1_D10_AUD 14 +#define CLK_PLL1_D100_AUD 15 +#define CLK_PLL2_D1 16 +#define CLK_PLL2_D2 17 +#define CLK_PLL2_D3 18 +#define CLK_PLL2_D4 19 +#define CLK_PLL2_D5 20 +#define CLK_PLL2_D6 21 +#define CLK_PLL2_D7 22 +#define CLK_PLL2_D8 23 +#define CLK_PLL3_D1 24 +#define CLK_PLL3_D2 25 +#define CLK_PLL3_D3 26 +#define CLK_PLL3_D4 27 +#define CLK_PLL3_D5 28 +#define CLK_PLL3_D6 29 +#define CLK_PLL3_D7 30 +#define CLK_PLL3_D8 31 +#define CLK_PLL3_80 32 +#define CLK_PLL3_40 33 +#define CLK_PLL3_20 34 + +/* MPMU clocks */ +#define CLK_PLL1_307P2 0 +#define CLK_PLL1_76P8 1 +#define CLK_PLL1_61P44 2 +#define CLK_PLL1_153P6 3 +#define CLK_PLL1_102P4 4 +#define CLK_PLL1_51P2 5 +#define CLK_PLL1_51P2_AP 6 +#define CLK_PLL1_57P6 7 +#define CLK_PLL1_25P6 8 +#define CLK_PLL1_12P8 9 +#define CLK_PLL1_12P8_WDT 10 +#define CLK_PLL1_6P4 11 +#define CLK_PLL1_3P2 12 +#define CLK_PLL1_1P6 13 +#define CLK_PLL1_0P8 14 +#define CLK_PLL1_409P6 15 +#define CLK_PLL1_204P8 16 +#define CLK_PLL1_491 17 +#define CLK_PLL1_245P76 18 +#define CLK_PLL1_614 19 +#define CLK_PLL1_47P26 20 +#define CLK_PLL1_31P5 21 +#define CLK_PLL1_819 22 +#define CLK_PLL1_1228 23 +#define CLK_SLOW_UART 24 +#define CLK_SLOW_UART1 25 +#define CLK_SLOW_UART2 26 +#define CLK_WDT 27 +#define CLK_RIPC 28 +#define CLK_I2S_SYSCLK 29 +#define CLK_I2S_BCLK 30 +#define CLK_APB 31 +#define CLK_WDT_BUS 32 + +/* APBC clocks */ +#define CLK_UART0 0 +#define CLK_UART2 1 +#define CLK_UART3 2 +#define CLK_UART4 3 +#define CLK_UART5 4 +#define CLK_UART6 5 +#define CLK_UART7 6 +#define CLK_UART8 7 +#define CLK_UART9 8 +#define CLK_GPIO 9 +#define CLK_PWM0 10 +#define CLK_PWM1 11 +#define CLK_PWM2 12 +#define CLK_PWM3 13 +#define CLK_PWM4 14 +#define CLK_PWM5 15 +#define CLK_PWM6 16 +#define CLK_PWM7 17 +#define CLK_PWM8 18 +#define CLK_PWM9 19 +#define CLK_PWM10 20 +#define CLK_PWM11 21 +#define CLK_PWM12 22 +#define CLK_PWM13 23 +#define CLK_PWM14 24 +#define CLK_PWM15 25 +#define CLK_PWM16 26 +#define CLK_PWM17 27 +#define CLK_PWM18 28 +#define CLK_PWM19 29 +#define CLK_SSP3 30 +#define CLK_RTC 31 +#define CLK_TWSI0 32 +#define CLK_TWSI1 33 +#define CLK_TWSI2 34 +#define CLK_TWSI4 35 +#define CLK_TWSI5 36 +#define CLK_TWSI6 37 +#define CLK_TWSI7 38 +#define CLK_TWSI8 39 +#define CLK_TIMERS1 40 +#define CLK_TIMERS2 41 +#define CLK_AIB 42 +#define CLK_ONEWIRE 43 +#define CLK_SSPA0 44 +#define CLK_SSPA1 45 +#define CLK_DRO 46 +#define CLK_IR 47 +#define CLK_TSEN 48 +#define CLK_IPC_AP2AUD 49 +#define CLK_CAN0 50 +#define CLK_CAN0_BUS 51 +#define CLK_UART0_BUS 52 +#define CLK_UART2_BUS 53 +#define CLK_UART3_BUS 54 +#define CLK_UART4_BUS 55 +#define CLK_UART5_BUS 56 +#define CLK_UART6_BUS 57 +#define CLK_UART7_BUS 58 +#define CLK_UART8_BUS 59 +#define CLK_UART9_BUS 60 +#define CLK_GPIO_BUS 61 +#define CLK_PWM0_BUS 62 +#define CLK_PWM1_BUS 63 +#define CLK_PWM2_BUS 64 +#define CLK_PWM3_BUS 65 +#define CLK_PWM4_BUS 66 +#define CLK_PWM5_BUS 67 +#define CLK_PWM6_BUS 68 +#define CLK_PWM7_BUS 69 +#define CLK_PWM8_BUS 70 +#define CLK_PWM9_BUS 71 +#define CLK_PWM10_BUS 72 +#define CLK_PWM11_BUS 73 +#define CLK_PWM12_BUS 74 +#define CLK_PWM13_BUS 75 +#define CLK_PWM14_BUS 76 +#define CLK_PWM15_BUS 77 +#define CLK_PWM16_BUS 78 +#define CLK_PWM17_BUS 79 +#define CLK_PWM18_BUS 80 +#define CLK_PWM19_BUS 81 +#define CLK_SSP3_BUS 82 +#define CLK_RTC_BUS 83 +#define CLK_TWSI0_BUS 84 +#define CLK_TWSI1_BUS 85 +#define CLK_TWSI2_BUS 86 +#define CLK_TWSI4_BUS 87 +#define CLK_TWSI5_BUS 88 +#define CLK_TWSI6_BUS 89 +#define CLK_TWSI7_BUS 90 +#define CLK_TWSI8_BUS 91 +#define CLK_TIMERS1_BUS 92 +#define CLK_TIMERS2_BUS 93 +#define CLK_AIB_BUS 94 +#define CLK_ONEWIRE_BUS 95 +#define CLK_SSPA0_BUS 96 +#define CLK_SSPA1_BUS 97 +#define CLK_TSEN_BUS 98 +#define CLK_IPC_AP2AUD_BUS 99 + +/* APMU clocks */ +#define CLK_CCI550 0 +#define CLK_CPU_C0_HI 1 +#define CLK_CPU_C0_CORE 2 +#define CLK_CPU_C0_ACE 3 +#define CLK_CPU_C0_TCM 4 +#define CLK_CPU_C1_HI 5 +#define CLK_CPU_C1_CORE 6 +#define CLK_CPU_C1_ACE 7 +#define CLK_CCIC_4X 8 +#define CLK_CCIC1PHY 9 +#define CLK_SDH_AXI 10 +#define CLK_SDH0 11 +#define CLK_SDH1 12 +#define CLK_SDH2 13 +#define CLK_USB_P1 14 +#define CLK_USB_AXI 15 +#define CLK_USB30 16 +#define CLK_QSPI 17 +#define CLK_QSPI_BUS 18 +#define CLK_DMA 19 +#define CLK_AES 20 +#define CLK_VPU 21 +#define CLK_GPU 22 +#define CLK_EMMC 23 +#define CLK_EMMC_X 24 +#define CLK_AUDIO 25 +#define CLK_HDMI 26 +#define CLK_PMUA_ACLK 27 +#define CLK_PCIE0_MASTER 28 +#define CLK_PCIE0_SLAVE 29 +#define CLK_PCIE0_DBI 30 +#define CLK_PCIE1_MASTER 31 +#define CLK_PCIE1_SLAVE 32 +#define CLK_PCIE1_DBI 33 +#define CLK_PCIE2_MASTER 34 +#define CLK_PCIE2_SLAVE 35 +#define CLK_PCIE2_DBI 36 +#define CLK_EMAC0_BUS 37 +#define CLK_EMAC0_PTP 38 +#define CLK_EMAC1_BUS 39 +#define CLK_EMAC1_PTP 40 +#define CLK_JPG 41 +#define CLK_CCIC2PHY 42 +#define CLK_CCIC3PHY 43 +#define CLK_CSI 44 +#define CLK_CAMM0 45 +#define CLK_CAMM1 46 +#define CLK_CAMM2 47 +#define CLK_ISP_CPP 48 +#define CLK_ISP_BUS 49 +#define CLK_ISP 50 +#define CLK_DPU_MCLK 51 +#define CLK_DPU_ESC 52 +#define CLK_DPU_BIT 53 +#define CLK_DPU_PXCLK 54 +#define CLK_DPU_HCLK 55 +#define CLK_DPU_SPI 56 +#define CLK_DPU_SPI_HBUS 57 +#define CLK_DPU_SPIBUS 58 +#define CLK_DPU_SPI_ACLK 59 +#define CLK_V2D 60 +#define CLK_EMMC_BUS 61 + +#endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */ diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h index e5dad050d518..b6ff9c68cb3f 100644 --- a/include/dt-bindings/clock/stm32fx-clock.h +++ b/include/dt-bindings/clock/stm32fx-clock.h @@ -10,7 +10,7 @@ * List of clocks which are not derived from system clock (SYSCLOCK) * * The index of these clocks is the secondary index of DT bindings - * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt) + * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml) * * e.g: <assigned-clocks = <&rcc 1 CLK_LSE>; diff --git a/include/dt-bindings/clock/stm32h7-clks.h b/include/dt-bindings/clock/stm32h7-clks.h index 6637272b3242..330b39c2c303 100644 --- a/include/dt-bindings/clock/stm32h7-clks.h +++ b/include/dt-bindings/clock/stm32h7-clks.h @@ -126,8 +126,8 @@ #define ADC3_CK 128 #define DSI_CK 129 #define LTDC_CK 130 -#define USART8_CK 131 -#define USART7_CK 132 +#define UART8_CK 131 +#define UART7_CK 132 #define HDMICEC_CK 133 #define I2C3_CK 134 #define I2C2_CK 135 diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h index 175892189e9d..4f220ea7a23c 100644 --- a/include/dt-bindings/clock/sun50i-a64-ccu.h +++ b/include/dt-bindings/clock/sun50i-a64-ccu.h @@ -44,7 +44,9 @@ #define _DT_BINDINGS_CLK_SUN50I_A64_H_ #define CLK_PLL_VIDEO0 7 +#define CLK_PLL_VIDEO0_2X 8 #define CLK_PLL_PERIPH0 11 +#define CLK_PLL_MIPI 17 #define CLK_CPUX 21 #define CLK_BUS_MIPI_DSI 28 diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h index ebb146ab7f8c..6889405f9fec 100644 --- a/include/dt-bindings/clock/sun50i-h616-ccu.h +++ b/include/dt-bindings/clock/sun50i-h616-ccu.h @@ -113,5 +113,9 @@ #define CLK_BUS_HDCP 127 #define CLK_PLL_SYSTEM_32K 128 #define CLK_BUS_GPADC 129 +#define CLK_TCON_LCD0 130 +#define CLK_BUS_TCON_LCD0 131 +#define CLK_TCON_LCD1 132 +#define CLK_BUS_TCON_LCD1 133 #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/clock/sun55i-a523-ccu.h b/include/dt-bindings/clock/sun55i-a523-ccu.h new file mode 100644 index 000000000000..c8259ac5ada7 --- /dev/null +++ b/include/dt-bindings/clock/sun55i-a523-ccu.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2024 Arm Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ +#define _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ + +#define CLK_PLL_DDR0 0 +#define CLK_PLL_PERIPH0_4X 1 +#define CLK_PLL_PERIPH0_2X 2 +#define CLK_PLL_PERIPH0_800M 3 +#define CLK_PLL_PERIPH0_480M 4 +#define CLK_PLL_PERIPH0_600M 5 +#define CLK_PLL_PERIPH0_400M 6 +#define CLK_PLL_PERIPH0_300M 7 +#define CLK_PLL_PERIPH0_200M 8 +#define CLK_PLL_PERIPH0_160M 9 +#define CLK_PLL_PERIPH0_150M 10 +#define CLK_PLL_PERIPH1_4X 11 +#define CLK_PLL_PERIPH1_2X 12 +#define CLK_PLL_PERIPH1_800M 13 +#define CLK_PLL_PERIPH1_480M 14 +#define CLK_PLL_PERIPH1_600M 15 +#define CLK_PLL_PERIPH1_400M 16 +#define CLK_PLL_PERIPH1_300M 17 +#define CLK_PLL_PERIPH1_200M 18 +#define CLK_PLL_PERIPH1_160M 19 +#define CLK_PLL_PERIPH1_150M 20 +#define CLK_PLL_GPU 21 +#define CLK_PLL_VIDEO0_8X 22 +#define CLK_PLL_VIDEO0_4X 23 +#define CLK_PLL_VIDEO0_3X 24 +#define CLK_PLL_VIDEO1_8X 25 +#define CLK_PLL_VIDEO1_4X 26 +#define CLK_PLL_VIDEO1_3X 27 +#define CLK_PLL_VIDEO2_8X 28 +#define CLK_PLL_VIDEO2_4X 29 +#define CLK_PLL_VIDEO2_3X 30 +#define CLK_PLL_VIDEO3_8X 31 +#define CLK_PLL_VIDEO3_4X 32 +#define CLK_PLL_VIDEO3_3X 33 +#define CLK_PLL_VE 34 +#define CLK_PLL_AUDIO0_4X 35 +#define CLK_PLL_AUDIO0_2X 36 +#define CLK_PLL_AUDIO0 37 +#define CLK_PLL_NPU_4X 38 +#define CLK_PLL_NPU_2X 39 +#define CLK_PLL_NPU 40 +#define CLK_AHB 41 +#define CLK_APB0 42 +#define CLK_APB1 43 +#define CLK_MBUS 44 +#define CLK_DE 45 +#define CLK_BUS_DE 46 +#define CLK_DI 47 +#define CLK_BUS_DI 48 +#define CLK_G2D 49 +#define CLK_BUS_G2D 50 +#define CLK_GPU 51 +#define CLK_BUS_GPU 52 +#define CLK_CE 53 +#define CLK_BUS_CE 54 +#define CLK_BUS_CE_SYS 55 +#define CLK_VE 56 +#define CLK_BUS_VE 57 +#define CLK_BUS_DMA 58 +#define CLK_BUS_MSGBOX 59 +#define CLK_BUS_SPINLOCK 60 +#define CLK_HSTIMER0 61 +#define CLK_HSTIMER1 62 +#define CLK_HSTIMER2 63 +#define CLK_HSTIMER3 64 +#define CLK_HSTIMER4 65 +#define CLK_HSTIMER5 66 +#define CLK_BUS_HSTIMER 67 +#define CLK_BUS_DBG 68 +#define CLK_BUS_PWM0 69 +#define CLK_BUS_PWM1 70 +#define CLK_IOMMU 71 +#define CLK_BUS_IOMMU 72 +#define CLK_DRAM 73 +#define CLK_MBUS_DMA 74 +#define CLK_MBUS_VE 75 +#define CLK_MBUS_CE 76 +#define CLK_MBUS_CSI 77 +#define CLK_MBUS_ISP 78 +#define CLK_MBUS_EMAC1 79 +#define CLK_BUS_DRAM 80 +#define CLK_NAND0 81 +#define CLK_NAND1 82 +#define CLK_BUS_NAND 83 +#define CLK_MMC0 84 +#define CLK_MMC1 85 +#define CLK_MMC2 86 +#define CLK_BUS_SYSDAP 87 +#define CLK_BUS_MMC0 88 +#define CLK_BUS_MMC1 89 +#define CLK_BUS_MMC2 90 +#define CLK_BUS_UART0 91 +#define CLK_BUS_UART1 92 +#define CLK_BUS_UART2 93 +#define CLK_BUS_UART3 94 +#define CLK_BUS_UART4 95 +#define CLK_BUS_UART5 96 +#define CLK_BUS_UART6 97 +#define CLK_BUS_UART7 98 +#define CLK_BUS_I2C0 99 +#define CLK_BUS_I2C1 100 +#define CLK_BUS_I2C2 101 +#define CLK_BUS_I2C3 102 +#define CLK_BUS_I2C4 103 +#define CLK_BUS_I2C5 104 +#define CLK_BUS_CAN 105 +#define CLK_SPI0 106 +#define CLK_SPI1 107 +#define CLK_SPI2 108 +#define CLK_SPIFC 109 +#define CLK_BUS_SPI0 110 +#define CLK_BUS_SPI1 111 +#define CLK_BUS_SPI2 112 +#define CLK_BUS_SPIFC 113 +#define CLK_EMAC0_25M 114 +#define CLK_EMAC1_25M 115 +#define CLK_BUS_EMAC0 116 +#define CLK_BUS_EMAC1 117 +#define CLK_IR_RX 118 +#define CLK_BUS_IR_RX 119 +#define CLK_IR_TX 120 +#define CLK_BUS_IR_TX 121 +#define CLK_GPADC0 122 +#define CLK_GPADC1 123 +#define CLK_BUS_GPADC0 124 +#define CLK_BUS_GPADC1 125 +#define CLK_BUS_THS 126 +#define CLK_USB_OHCI0 127 +#define CLK_USB_OHCI1 128 +#define CLK_BUS_OHCI0 129 +#define CLK_BUS_OHCI1 130 +#define CLK_BUS_EHCI0 131 +#define CLK_BUS_EHCI1 132 +#define CLK_BUS_OTG 133 +#define CLK_BUS_LRADC 134 +#define CLK_PCIE_AUX 135 +#define CLK_BUS_DISPLAY0_TOP 136 +#define CLK_BUS_DISPLAY1_TOP 137 +#define CLK_HDMI_24M 138 +#define CLK_HDMI_CEC_32K 139 +#define CLK_HDMI_CEC 140 +#define CLK_BUS_HDMI 141 +#define CLK_MIPI_DSI0 142 +#define CLK_MIPI_DSI1 143 +#define CLK_BUS_MIPI_DSI0 144 +#define CLK_BUS_MIPI_DSI1 145 +#define CLK_TCON_LCD0 146 +#define CLK_TCON_LCD1 147 +#define CLK_TCON_LCD2 148 +#define CLK_COMBOPHY_DSI0 149 +#define CLK_COMBOPHY_DSI1 150 +#define CLK_BUS_TCON_LCD0 151 +#define CLK_BUS_TCON_LCD1 152 +#define CLK_BUS_TCON_LCD2 153 +#define CLK_TCON_TV0 154 +#define CLK_TCON_TV1 155 +#define CLK_BUS_TCON_TV0 156 +#define CLK_BUS_TCON_TV1 157 +#define CLK_EDP 158 +#define CLK_BUS_EDP 159 +#define CLK_LEDC 160 +#define CLK_BUS_LEDC 161 +#define CLK_CSI_TOP 162 +#define CLK_CSI_MCLK0 163 +#define CLK_CSI_MCLK1 164 +#define CLK_CSI_MCLK2 165 +#define CLK_CSI_MCLK3 166 +#define CLK_BUS_CSI 167 +#define CLK_ISP 168 +#define CLK_DSP 169 +#define CLK_FANOUT_24M 170 +#define CLK_FANOUT_12M 171 +#define CLK_FANOUT_16M 172 +#define CLK_FANOUT_25M 173 +#define CLK_FANOUT_27M 174 +#define CLK_FANOUT_PCLK 175 +#define CLK_FANOUT0 176 +#define CLK_FANOUT1 177 +#define CLK_FANOUT2 178 + +#endif /* _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun55i-a523-r-ccu.h b/include/dt-bindings/clock/sun55i-a523-r-ccu.h new file mode 100644 index 000000000000..365647499b9a --- /dev/null +++ b/include/dt-bindings/clock/sun55i-a523-r-ccu.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2024 Arm Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_SUN55I_A523_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN55I_A523_R_CCU_H_ + +#define CLK_R_AHB 0 +#define CLK_R_APB0 1 +#define CLK_R_APB1 2 +#define CLK_R_TIMER0 3 +#define CLK_R_TIMER1 4 +#define CLK_R_TIMER2 5 +#define CLK_BUS_R_TIMER 6 +#define CLK_BUS_R_TWD 7 +#define CLK_R_PWMCTRL 8 +#define CLK_BUS_R_PWMCTRL 9 +#define CLK_R_SPI 10 +#define CLK_BUS_R_SPI 11 +#define CLK_BUS_R_SPINLOCK 12 +#define CLK_BUS_R_MSGBOX 13 +#define CLK_BUS_R_UART0 14 +#define CLK_BUS_R_UART1 15 +#define CLK_BUS_R_I2C0 16 +#define CLK_BUS_R_I2C1 17 +#define CLK_BUS_R_I2C2 18 +#define CLK_BUS_R_PPU0 19 +#define CLK_BUS_R_PPU1 20 +#define CLK_BUS_R_CPU_BIST 21 +#define CLK_R_IR_RX 22 +#define CLK_BUS_R_IR_RX 23 +#define CLK_BUS_R_DMA 24 +#define CLK_BUS_R_RTC 25 +#define CLK_BUS_R_CPUCFG 26 + +#endif /* _DT_BINDINGS_CLK_SUN55I_A523_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h index 014ac6123d17..c4055629c9f9 100644 --- a/include/dt-bindings/clock/sun8i-v3s-ccu.h +++ b/include/dt-bindings/clock/sun8i-v3s-ccu.h @@ -96,7 +96,7 @@ #define CLK_TCON0 64 #define CLK_CSI_MISC 65 #define CLK_CSI0_MCLK 66 -#define CLK_CSI1_SCLK 67 +#define CLK_CSI_SCLK 67 #define CLK_CSI1_MCLK 68 #define CLK_VE 69 #define CLK_AC_DIG 70 diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h index a199784b3512..09a9aa7b3ab1 100644 --- a/include/dt-bindings/clock/thead,th1520-clk-ap.h +++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h @@ -93,4 +93,38 @@ #define CLK_SRAM3 83 #define CLK_PLL_GMAC_100M 84 #define CLK_UART_SCLK 85 + +/* VO clocks */ +#define CLK_AXI4_VO_ACLK 0 +#define CLK_GPU_MEM 1 +#define CLK_GPU_CORE 2 +#define CLK_GPU_CFG_ACLK 3 +#define CLK_DPU_PIXELCLK0 4 +#define CLK_DPU_PIXELCLK1 5 +#define CLK_DPU_HCLK 6 +#define CLK_DPU_ACLK 7 +#define CLK_DPU_CCLK 8 +#define CLK_HDMI_SFR 9 +#define CLK_HDMI_PCLK 10 +#define CLK_HDMI_CEC 11 +#define CLK_MIPI_DSI0_PCLK 12 +#define CLK_MIPI_DSI1_PCLK 13 +#define CLK_MIPI_DSI0_CFG 14 +#define CLK_MIPI_DSI1_CFG 15 +#define CLK_MIPI_DSI0_REFCLK 16 +#define CLK_MIPI_DSI1_REFCLK 17 +#define CLK_HDMI_I2S 18 +#define CLK_X2H_DPU1_ACLK 19 +#define CLK_X2H_DPU_ACLK 20 +#define CLK_AXI4_VO_PCLK 21 +#define CLK_IOPMP_VOSYS_DPU_PCLK 22 +#define CLK_IOPMP_VOSYS_DPU1_PCLK 23 +#define CLK_IOPMP_VOSYS_GPU_PCLK 24 +#define CLK_IOPMP_DPU1_ACLK 25 +#define CLK_IOPMP_DPU_ACLK 26 +#define CLK_IOPMP_GPU_ACLK 27 +#define CLK_MIPIDSI0_PIXCLK 28 +#define CLK_MIPIDSI1_PIXCLK 29 +#define CLK_HDMI_PIXCLK 30 + #endif diff --git a/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/include/dt-bindings/clock/xlnx-zynqmp-clk.h index cdc4c0b9a374..f0f7ddd3dcbd 100644 --- a/include/dt-bindings/clock/xlnx-zynqmp-clk.h +++ b/include/dt-bindings/clock/xlnx-zynqmp-clk.h @@ -9,6 +9,13 @@ #ifndef _DT_BINDINGS_CLK_ZYNQMP_H #define _DT_BINDINGS_CLK_ZYNQMP_H +/* + * These bindings are deprecated, because they do not match the actual + * concept of bindings but rather contain pure firmware values. + * Instead include the header in the DTS source directory. + */ +#warning "These bindings are deprecated. Instead use the header in the DTS source directory." + #define IOPLL 0 #define RPLL 1 #define APLL 2 |