diff options
Diffstat (limited to 'include/asm-blackfin')
56 files changed, 657 insertions, 326 deletions
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h index 14cb8d35924e..6ae0619d7696 100644 --- a/include/asm-blackfin/bfin-global.h +++ b/include/asm-blackfin/bfin-global.h @@ -50,8 +50,8 @@ extern unsigned long get_sclk(void); extern unsigned long sclk_to_usecs(unsigned long sclk); extern unsigned long usecs_to_sclk(unsigned long usecs); -extern void dump_thread(struct pt_regs *regs, struct user *dump); -extern void dump_bfin_regs(struct pt_regs *fp, void *retaddr); +extern void dump_bfin_process(struct pt_regs *regs); +extern void dump_bfin_mem(struct pt_regs *regs); extern void dump_bfin_trace_buffer(void); extern int init_arch_irq(void); @@ -63,6 +63,7 @@ extern void bfin_dcache_init(void); extern int read_iloc(void); extern int bfin_console_init(void); extern asmlinkage void lower_to_irq14(void); +extern asmlinkage void bfin_return_from_exception(void); extern void init_exception_vectors(void); extern void init_dma(void); extern void program_IAR(void); @@ -80,6 +81,7 @@ extern int atomic_sub32(void); extern int atomic_ior32(void); extern int atomic_and32(void); extern int atomic_xor32(void); +extern void safe_user_instruction(void); extern void sigreturn_stub(void); extern void *l1_data_A_sram_alloc(size_t); diff --git a/include/asm-blackfin/bfin5xx_spi.h b/include/asm-blackfin/bfin5xx_spi.h index f617d8765451..1a0b57f6a3d4 100644 --- a/include/asm-blackfin/bfin5xx_spi.h +++ b/include/asm-blackfin/bfin5xx_spi.h @@ -152,6 +152,7 @@ struct bfin5xx_spi_master { u16 num_chipselect; u8 enable_dma; + u16 pin_req[4]; }; /* spi_board_info.controller_data for SPI slave devices, @@ -162,7 +163,7 @@ struct bfin5xx_spi_chip { u8 enable_dma; u8 bits_per_word; u8 cs_change_per_word; - u8 cs_chg_udelay; + u16 cs_chg_udelay; /* Some devices require 16-bit delays */ }; #endif /* _SPI_CHANNEL_H_ */ diff --git a/include/asm-blackfin/cplb-mpu.h b/include/asm-blackfin/cplb-mpu.h new file mode 100644 index 000000000000..75c67b99d607 --- /dev/null +++ b/include/asm-blackfin/cplb-mpu.h @@ -0,0 +1,61 @@ +/* + * File: include/asm-blackfin/cplbinit.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef __ASM_BFIN_CPLB_MPU_H +#define __ASM_BFIN_CPLB_MPU_H + +struct cplb_entry { + unsigned long data, addr; +}; + +struct mem_region { + unsigned long start, end; + unsigned long dcplb_data; + unsigned long icplb_data; +}; + +extern struct cplb_entry dcplb_tbl[MAX_CPLBS]; +extern struct cplb_entry icplb_tbl[MAX_CPLBS]; +extern int first_switched_icplb; +extern int first_mask_dcplb; +extern int first_switched_dcplb; + +extern int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot; +extern int nr_cplb_flush; + +extern int page_mask_order; +extern int page_mask_nelts; + +extern unsigned long *current_rwx_mask; + +extern void flush_switched_cplbs(void); +extern void set_mask_dcplbs(unsigned long *); + +extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *); + +#endif /* __ASM_BFIN_CPLB_MPU_H */ diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h index 06828d77a58f..654375c2b746 100644 --- a/include/asm-blackfin/cplb.h +++ b/include/asm-blackfin/cplb.h @@ -65,7 +65,11 @@ #define SIZE_1M 0x00100000 /* 1M */ #define SIZE_4M 0x00400000 /* 4M */ +#ifdef CONFIG_MPU +#define MAX_CPLBS 16 +#else #define MAX_CPLBS (16 * 2) +#endif #define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M) diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h index bec6ecdf1bdb..0eb1c1b685a7 100644 --- a/include/asm-blackfin/cplbinit.h +++ b/include/asm-blackfin/cplbinit.h @@ -27,9 +27,18 @@ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef __ASM_CPLBINIT_H__ +#define __ASM_CPLBINIT_H__ + #include <asm/blackfin.h> #include <asm/cplb.h> +#ifdef CONFIG_MPU + +#include <asm/cplb-mpu.h> + +#else + #define INITIAL_T 0x1 #define SWITCH_T 0x2 #define I_CPLB 0x4 @@ -57,8 +66,8 @@ struct cplb_tab { u16 size; }; -extern u_long icplb_table[MAX_CPLBS+1]; -extern u_long dcplb_table[MAX_CPLBS+1]; +extern u_long icplb_table[]; +extern u_long dcplb_table[]; /* Till here we are discussing about the static memory management model. * However, the operating envoronments commonly define more CPLB @@ -69,28 +78,18 @@ extern u_long dcplb_table[MAX_CPLBS+1]; * This is how Page descriptor Table is implemented in uClinux/Blackfin. */ -#ifdef CONFIG_CPLB_SWITCH_TAB_L1 -extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data)); -extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data)); - +extern u_long ipdt_table[]; +extern u_long dpdt_table[]; #ifdef CONFIG_CPLB_INFO -extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data)); -extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data)); -#endif /* CONFIG_CPLB_INFO */ +extern u_long ipdt_swapcount_table[]; +extern u_long dpdt_swapcount_table[]; +#endif -#else - -extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]; -extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]; - -#ifdef CONFIG_CPLB_INFO -extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]; -extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]; -#endif /* CONFIG_CPLB_INFO */ - -#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/ +#endif /* CONFIG_MPU */ extern unsigned long reserved_mem_dcache_on; extern unsigned long reserved_mem_icache_on; extern void generate_cpl_tables(void); + +#endif diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h index 52e7a10d7ff8..473a8113277f 100644 --- a/include/asm-blackfin/delay.h +++ b/include/asm-blackfin/delay.h @@ -1,29 +1,47 @@ -#ifndef _BLACKFIN_DELAY_H -#define _BLACKFIN_DELAY_H - -static inline void __delay(unsigned long loops) -{ - -/* FIXME: Currently the assembler doesn't recognize Loop Register Clobbers, - uncomment this as soon those are implemented */ /* - __asm__ __volatile__ ( "\t LSETUP (1f,1f) LC0= %0\n\t" - "1:\t NOP;\n\t" - : :"a" (loops) - : "LT0","LB0","LC0"); + * delay.h - delay functions + * + * Copyright (c) 2004-2007 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_DELAY_H__ +#define __ASM_DELAY_H__ -*/ +#include <asm/mach/anomaly.h> - __asm__ __volatile__("[--SP] = LC0;\n\t" - "[--SP] = LT0;\n\t" - "[--SP] = LB0;\n\t" - "LSETUP (1f,1f) LC0 = %0;\n\t" - "1:\t NOP;\n\t" - "LB0 = [SP++];\n\t" - "LT0 = [SP++];\n\t" - "LC0 = [SP++];\n" - : - :"a" (loops)); +static inline void __delay(unsigned long loops) +{ + if (ANOMALY_05000312) { + /* Interrupted loads to loop registers -> bad */ + unsigned long tmp; + __asm__ __volatile__( + "[--SP] = LC0;" + "[--SP] = LT0;" + "[--SP] = LB0;" + "LSETUP (1f,1f) LC0 = %1;" + "1: NOP;" + /* We take advantage of the fact that LC0 is 0 at + * the end of the loop. Otherwise we'd need some + * NOPs after the CLI here. + */ + "CLI %0;" + "LB0 = [SP++];" + "LT0 = [SP++];" + "LC0 = [SP++];" + "STI %0;" + : "=d" (tmp) + : "a" (loops) + ); + } else + __asm__ __volatile__ ( + "LSETUP(1f, 1f) LC0 = %0;" + "1: NOP;" + : + : "a" (loops) + : "LT0", "LB0", "LC0" + ); } #include <linux/param.h> /* needed for HZ */ @@ -41,4 +59,4 @@ static inline void udelay(unsigned long usecs) __delay(usecs * loops_per_jiffy / (1000000 / HZ)); } -#endif /* defined(_BLACKFIN_DELAY_H) */ +#endif diff --git a/include/asm-blackfin/dma.h b/include/asm-blackfin/dma.h index b469505af364..5abaa2cee8db 100644 --- a/include/asm-blackfin/dma.h +++ b/include/asm-blackfin/dma.h @@ -76,6 +76,9 @@ enum dma_chan_status { #define INTR_ON_BUF 2 #define INTR_ON_ROW 3 +#define DMA_NOSYNC_KEEP_DMA_BUF 0 +#define DMA_SYNC_RESTART 1 + struct dmasg { unsigned long next_desc_addr; unsigned long start_addr; @@ -157,7 +160,8 @@ void set_dma_y_count(unsigned int channel, unsigned short y_count); void set_dma_y_modify(unsigned int channel, short y_modify); void set_dma_config(unsigned int channel, unsigned short config); unsigned short set_bfin_dma_config(char direction, char flow_mode, - char intr_mode, char dma_mode, char width); + char intr_mode, char dma_mode, char width, + char syncmode); void set_dma_curr_addr(unsigned int channel, unsigned long addr); /* get curr status for polling */ diff --git a/include/asm-blackfin/fixed_code.h b/include/asm-blackfin/fixed_code.h index e6df84ee1557..37db66c7030d 100644 --- a/include/asm-blackfin/fixed_code.h +++ b/include/asm-blackfin/fixed_code.h @@ -17,4 +17,6 @@ #define ATOMIC_SEQS_END 0x480 -#define FIXED_CODE_END 0x480 +#define SAFE_USER_INSTRUCTION 0x480 + +#define FIXED_CODE_END 0x490 diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h index 33ce98ef7e0f..d0426c108262 100644 --- a/include/asm-blackfin/gpio.h +++ b/include/asm-blackfin/gpio.h @@ -7,7 +7,7 @@ * Description: * * Modified: - * Copyright 2004-2006 Analog Devices Inc. + * Copyright 2004-2008 Analog Devices Inc. * * Bugs: Enter bugs at http://blackfin.uclinux.org/ * @@ -304,39 +304,39 @@ **************************************************************/ #ifndef BF548_FAMILY -void set_gpio_dir(unsigned short, unsigned short); -void set_gpio_inen(unsigned short, unsigned short); -void set_gpio_polar(unsigned short, unsigned short); -void set_gpio_edge(unsigned short, unsigned short); -void set_gpio_both(unsigned short, unsigned short); -void set_gpio_data(unsigned short, unsigned short); -void set_gpio_maska(unsigned short, unsigned short); -void set_gpio_maskb(unsigned short, unsigned short); -void set_gpio_toggle(unsigned short); -void set_gpiop_dir(unsigned short, unsigned short); -void set_gpiop_inen(unsigned short, unsigned short); -void set_gpiop_polar(unsigned short, unsigned short); -void set_gpiop_edge(unsigned short, unsigned short); -void set_gpiop_both(unsigned short, unsigned short); -void set_gpiop_data(unsigned short, unsigned short); -void set_gpiop_maska(unsigned short, unsigned short); -void set_gpiop_maskb(unsigned short, unsigned short); -unsigned short get_gpio_dir(unsigned short); -unsigned short get_gpio_inen(unsigned short); -unsigned short get_gpio_polar(unsigned short); -unsigned short get_gpio_edge(unsigned short); -unsigned short get_gpio_both(unsigned short); -unsigned short get_gpio_maska(unsigned short); -unsigned short get_gpio_maskb(unsigned short); -unsigned short get_gpio_data(unsigned short); -unsigned short get_gpiop_dir(unsigned short); -unsigned short get_gpiop_inen(unsigned short); -unsigned short get_gpiop_polar(unsigned short); -unsigned short get_gpiop_edge(unsigned short); -unsigned short get_gpiop_both(unsigned short); -unsigned short get_gpiop_maska(unsigned short); -unsigned short get_gpiop_maskb(unsigned short); -unsigned short get_gpiop_data(unsigned short); +void set_gpio_dir(unsigned, unsigned short); +void set_gpio_inen(unsigned, unsigned short); +void set_gpio_polar(unsigned, unsigned short); +void set_gpio_edge(unsigned, unsigned short); +void set_gpio_both(unsigned, unsigned short); +void set_gpio_data(unsigned, unsigned short); +void set_gpio_maska(unsigned, unsigned short); +void set_gpio_maskb(unsigned, unsigned short); +void set_gpio_toggle(unsigned); +void set_gpiop_dir(unsigned, unsigned short); +void set_gpiop_inen(unsigned, unsigned short); +void set_gpiop_polar(unsigned, unsigned short); +void set_gpiop_edge(unsigned, unsigned short); +void set_gpiop_both(unsigned, unsigned short); +void set_gpiop_data(unsigned, unsigned short); +void set_gpiop_maska(unsigned, unsigned short); +void set_gpiop_maskb(unsigned, unsigned short); +unsigned short get_gpio_dir(unsigned); +unsigned short get_gpio_inen(unsigned); +unsigned short get_gpio_polar(unsigned); +unsigned short get_gpio_edge(unsigned); +unsigned short get_gpio_both(unsigned); +unsigned short get_gpio_maska(unsigned); +unsigned short get_gpio_maskb(unsigned); +unsigned short get_gpio_data(unsigned); +unsigned short get_gpiop_dir(unsigned); +unsigned short get_gpiop_inen(unsigned); +unsigned short get_gpiop_polar(unsigned); +unsigned short get_gpiop_edge(unsigned); +unsigned short get_gpiop_both(unsigned); +unsigned short get_gpiop_maska(unsigned); +unsigned short get_gpiop_maskb(unsigned); +unsigned short get_gpiop_data(unsigned); struct gpio_port_t { unsigned short data; @@ -382,8 +382,8 @@ struct gpio_port_t { #define PM_WAKE_LOW 0x8 #define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING) -int gpio_pm_wakeup_request(unsigned short gpio, unsigned char type); -void gpio_pm_wakeup_free(unsigned short gpio); +int gpio_pm_wakeup_request(unsigned gpio, unsigned char type); +void gpio_pm_wakeup_free(unsigned gpio); unsigned int gpio_pm_setup(void); void gpio_pm_restore(void); @@ -426,19 +426,19 @@ struct gpio_port_s { * MODIFICATION HISTORY : **************************************************************/ -int gpio_request(unsigned short, const char *); -void gpio_free(unsigned short); +int gpio_request(unsigned, const char *); +void gpio_free(unsigned); -void gpio_set_value(unsigned short gpio, unsigned short arg); -unsigned short gpio_get_value(unsigned short gpio); +void gpio_set_value(unsigned gpio, int arg); +int gpio_get_value(unsigned gpio); #ifndef BF548_FAMILY #define gpio_get_value(gpio) get_gpio_data(gpio) #define gpio_set_value(gpio, value) set_gpio_data(gpio, value) #endif -void gpio_direction_input(unsigned short gpio); -void gpio_direction_output(unsigned short gpio); +int gpio_direction_input(unsigned gpio); +int gpio_direction_output(unsigned gpio, int value); #include <asm-generic/gpio.h> /* cansleep wrappers */ #include <asm/irq.h> diff --git a/include/asm-blackfin/gptimers.h b/include/asm-blackfin/gptimers.h index c97ab03e43a6..8265ea473d5b 100644 --- a/include/asm-blackfin/gptimers.h +++ b/include/asm-blackfin/gptimers.h @@ -197,6 +197,8 @@ uint32_t get_gptimer_period (int timer_id); uint32_t get_gptimer_count (int timer_id); uint16_t get_gptimer_intr (int timer_id); void clear_gptimer_intr (int timer_id); +uint16_t get_gptimer_over (int timer_id); +void clear_gptimer_over (int timer_id); void set_gptimer_config (int timer_id, uint16_t config); uint16_t get_gptimer_config (int timer_id); void set_gptimer_pulse_hi (int timer_id); diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h index d1d2e6be3b59..1601d62f39a5 100644 --- a/include/asm-blackfin/io.h +++ b/include/asm-blackfin/io.h @@ -122,6 +122,7 @@ extern void outsl(unsigned long port, const void *addr, unsigned long count); extern void insb(unsigned long port, void *addr, unsigned long count); extern void insw(unsigned long port, void *addr, unsigned long count); extern void insl(unsigned long port, void *addr, unsigned long count); +extern void insl_16(unsigned long port, void *addr, unsigned long count); extern void dma_outsb(unsigned long port, const void *addr, unsigned short count); extern void dma_outsw(unsigned long port, const void *addr, unsigned short count); diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h index 0b867e6a76c4..15dbc21eed8b 100644 --- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h @@ -146,7 +146,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart) if (uart->rts_pin >= 0) { gpio_request(uart->rts_pin, DRIVER_NAME); - gpio_direction_output(uart->rts_pin); + gpio_direction_output(uart->rts_pin, 0); } #endif } diff --git a/include/asm-blackfin/mach-bf527/defBF52x_base.h b/include/asm-blackfin/mach-bf527/defBF52x_base.h index d6c24c54699d..fc69cf93f149 100644 --- a/include/asm-blackfin/mach-bf527/defBF52x_base.h +++ b/include/asm-blackfin/mach-bf527/defBF52x_base.h @@ -1718,55 +1718,55 @@ /* Bit masks for HOST_CONTROL */ -#define HOST_EN 0x1 /* Host Enable */ -#define nHOST_EN 0x0 -#define HOST_END 0x2 /* Host Endianess */ -#define nHOST_END 0x0 -#define DATA_SIZE 0x4 /* Data Size */ -#define nDATA_SIZE 0x0 -#define HOST_RST 0x8 /* Host Reset */ -#define nHOST_RST 0x0 -#define HRDY_OVR 0x20 /* Host Ready Override */ -#define nHRDY_OVR 0x0 -#define INT_MODE 0x40 /* Interrupt Mode */ -#define nINT_MODE 0x0 -#define BT_EN 0x80 /* Bus Timeout Enable */ -#define nBT_EN 0x0 -#define EHW 0x100 /* Enable Host Write */ -#define nEHW 0x0 -#define EHR 0x200 /* Enable Host Read */ -#define nEHR 0x0 -#define BDR 0x400 /* Burst DMA Requests */ -#define nBDR 0x0 +#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */ +#define HOST_CNTR_nHOST_EN 0x0 +#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */ +#define HOST_CNTR_nHOST_END 0x0 +#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */ +#define HOST_CNTR_nDATA_SIZE 0x0 +#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */ +#define HOST_CNTR_nHOST_RST 0x0 +#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */ +#define HOST_CNTR_nHRDY_OVR 0x0 +#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */ +#define HOST_CNTR_nINT_MODE 0x0 +#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */ +#define HOST_CNTR_ nBT_EN 0x0 +#define HOST_CNTR_EHW 0x100 /* Enable Host Write */ +#define HOST_CNTR_nEHW 0x0 +#define HOST_CNTR_EHR 0x200 /* Enable Host Read */ +#define HOST_CNTR_nEHR 0x0 +#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */ +#define HOST_CNTR_nBDR 0x0 /* Bit masks for HOST_STATUS */ -#define READY 0x1 /* DMA Ready */ -#define nREADY 0x0 -#define FIFOFULL 0x2 /* FIFO Full */ -#define nFIFOFULL 0x0 -#define FIFOEMPTY 0x4 /* FIFO Empty */ -#define nFIFOEMPTY 0x0 -#define COMPLETE 0x8 /* DMA Complete */ -#define nCOMPLETE 0x0 -#define HSHK 0x10 /* Host Handshake */ -#define nHSHK 0x0 -#define TIMEOUT 0x20 /* Host Timeout */ -#define nTIMEOUT 0x0 -#define HIRQ 0x40 /* Host Interrupt Request */ -#define nHIRQ 0x0 -#define ALLOW_CNFG 0x80 /* Allow New Configuration */ -#define nALLOW_CNFG 0x0 -#define DMA_DIR 0x100 /* DMA Direction */ -#define nDMA_DIR 0x0 -#define BTE 0x200 /* Bus Timeout Enabled */ -#define nBTE 0x0 -#define HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */ -#define nHOSTRD_DONE 0x0 +#define HOST_STAT_READY 0x1 /* DMA Ready */ +#define HOST_STAT_nREADY 0x0 +#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */ +#define HOST_STAT_nFIFOFULL 0x0 +#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */ +#define HOST_STAT_nFIFOEMPTY 0x0 +#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */ +#define HOST_STAT_nCOMPLETE 0x0 +#define HOST_STAT_HSHK 0x10 /* Host Handshake */ +#define HOST_STAT_nHSHK 0x0 +#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */ +#define HOST_STAT_nTIMEOUT 0x0 +#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */ +#define HOST_STAT_nHIRQ 0x0 +#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */ +#define HOST_STAT_nALLOW_CNFG 0x0 +#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */ +#define HOST_STAT_nDMA_DIR 0x0 +#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */ +#define HOST_STAT_nBTE 0x0 +#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */ +#define HOST_STAT_nHOSTRD_DONE 0x0 /* Bit masks for HOST_TIMEOUT */ -#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */ +#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */ /* Bit masks for CNT_CONFIG */ diff --git a/include/asm-blackfin/mach-bf527/dma.h b/include/asm-blackfin/mach-bf527/dma.h index a41627ae9134..2dfee12864f6 100644 --- a/include/asm-blackfin/mach-bf527/dma.h +++ b/include/asm-blackfin/mach-bf527/dma.h @@ -35,7 +35,6 @@ #define MAX_BLACKFIN_DMA_CHANNEL 16 #define CH_PPI 0 /* PPI receive/transmit or NFC */ -#define CH_NFC 0 /* PPI receive/transmit or NFC */ #define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */ #define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */ #define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */ @@ -54,6 +53,12 @@ #define CH_MEM_STREAM1_DEST 14 /* TX */ #define CH_MEM_STREAM1_SRC 15 /* RX */ +#if defined(CONFIG_BF527_NAND_D_PORTF) +#define CH_NFC CH_PPI /* PPI receive/transmit or NFC */ +#elif defined(CONFIG_BF527_NAND_D_PORTH) +#define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */ +#endif + extern int channel2irq(unsigned int channel); extern struct dma_register *base_addr[]; diff --git a/include/asm-blackfin/mach-bf527/irq.h b/include/asm-blackfin/mach-bf527/irq.h index 304f5bcfebe4..4e2b3f2020e5 100644 --- a/include/asm-blackfin/mach-bf527/irq.h +++ b/include/asm-blackfin/mach-bf527/irq.h @@ -176,11 +176,7 @@ #define GPIO_IRQ_BASE IRQ_PF0 -#ifdef CONFIG_IRQCHIP_DEMUX_GPIO #define NR_IRQS (IRQ_PH15+1) -#else -#define NR_IRQS (SYS_IRQS+1) -#endif #define IVG7 7 #define IVG8 8 diff --git a/include/asm-blackfin/mach-bf527/mem_map.h b/include/asm-blackfin/mach-bf527/mem_map.h index c5aa20102b24..193082deaa4e 100644 --- a/include/asm-blackfin/mach-bf527/mem_map.h +++ b/include/asm-blackfin/mach-bf527/mem_map.h @@ -47,6 +47,7 @@ /* Boot ROM Memory */ #define BOOT_ROM_START 0xEF000000 +#define BOOT_ROM_LENGTH 0x8000 /* Level 1 Memory */ @@ -90,9 +91,7 @@ /* Scratch Pad Memory */ -#if defined(CONFIG_BF527) || defined(CONFIG_BF536) || defined(CONFIG_BF534) #define L1_SCRATCH_START 0xFFB00000 #define L1_SCRATCH_LENGTH 0x1000 -#endif #endif /* _MEM_MAP_527_H_ */ diff --git a/include/asm-blackfin/mach-bf527/portmux.h b/include/asm-blackfin/mach-bf527/portmux.h index dcf001adc63c..ae4d205bfcf5 100644 --- a/include/asm-blackfin/mach-bf527/portmux.h +++ b/include/asm-blackfin/mach-bf527/portmux.h @@ -1,6 +1,8 @@ #ifndef _MACH_PORTMUX_H_ #define _MACH_PORTMUX_H_ +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + #define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) #define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) #define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h index f36ff5af1b91..98209d40abba 100644 --- a/include/asm-blackfin/mach-bf533/anomaly.h +++ b/include/asm-blackfin/mach-bf533/anomaly.h @@ -7,9 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision X, March 23, 2007; ADSP-BF533 Blackfin Processor Anomaly List - * - Revision AB, March 23, 2007; ADSP-BF532 Blackfin Processor Anomaly List - * - Revision W, March 23, 2007; ADSP-BF531 Blackfin Processor Anomaly List + * - Revision B, 12/10/2007; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -17,7 +15,7 @@ /* We do not support 0.1 or 0.2 silicon - sorry */ #if __SILICON_REVISION__ < 3 -# error Kernel will not work on BF533 silicon version 0.0, 0.1, or 0.2 +# error will not work on BF533 silicon version 0.0, 0.1, or 0.2 #endif #if defined(__ADSPBF531__) @@ -251,6 +249,12 @@ #define ANOMALY_05000192 (__SILICON_REVISION__ < 3) /* Internal Voltage Regulator may not start up */ #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) +/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ +#define ANOMALY_05000357 (1) +/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ +#define ANOMALY_05000366 (1) +/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ +#define ANOMALY_05000371 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000266 (0) diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h index 69b9f8e120e9..7871d4313f49 100644 --- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h @@ -111,7 +111,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart) } if (uart->rts_pin >= 0) { gpio_request(uart->rts_pin, DRIVER_NAME); - gpio_direction_input(uart->rts_pin); + gpio_direction_input(uart->rts_pin, 0); } #endif } diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h index 452fb825d891..832e6f6122da 100644 --- a/include/asm-blackfin/mach-bf533/irq.h +++ b/include/asm-blackfin/mach-bf533/irq.h @@ -130,11 +130,7 @@ Core Emulation ** #define GPIO_IRQ_BASE IRQ_PF0 -#ifdef CONFIG_IRQCHIP_DEMUX_GPIO #define NR_IRQS (IRQ_PF15+1) -#else -#define NR_IRQS SYS_IRQS -#endif #define IVG7 7 #define IVG8 8 diff --git a/include/asm-blackfin/mach-bf533/mem_map.h b/include/asm-blackfin/mach-bf533/mem_map.h index 94d8c4062eb7..bd30b6f3be00 100644 --- a/include/asm-blackfin/mach-bf533/mem_map.h +++ b/include/asm-blackfin/mach-bf533/mem_map.h @@ -1,4 +1,3 @@ - /* * File: include/asm-blackfin/mach-bf533/mem_map.h * Based on: @@ -48,6 +47,7 @@ /* Boot ROM Memory */ #define BOOT_ROM_START 0xEF000000 +#define BOOT_ROM_LENGTH 0x400 /* Level 1 Memory */ @@ -160,9 +160,7 @@ /* Scratch Pad Memory */ -#if defined(CONFIG_BF533) || defined(CONFIG_BF532) || defined(CONFIG_BF531) #define L1_SCRATCH_START 0xFFB00000 #define L1_SCRATCH_LENGTH 0x1000 -#endif #endif /* _MEM_MAP_533_H_ */ diff --git a/include/asm-blackfin/mach-bf533/portmux.h b/include/asm-blackfin/mach-bf533/portmux.h index b88d7a03ee3e..685a2651dcda 100644 --- a/include/asm-blackfin/mach-bf533/portmux.h +++ b/include/asm-blackfin/mach-bf533/portmux.h @@ -1,6 +1,8 @@ #ifndef _MACH_PORTMUX_H_ #define _MACH_PORTMUX_H_ +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + #define P_PPI0_CLK (P_DONTCARE) #define P_PPI0_FS1 (P_DONTCARE) #define P_PPI0_FS2 (P_DONTCARE) @@ -42,7 +44,7 @@ #define P_SPORT0_DRPRI (P_DONTCARE) #define P_SPI0_MOSI (P_DONTCARE) -#define P_SPI0_MIS0 (P_DONTCARE) +#define P_SPI0_MISO (P_DONTCARE) #define P_SPI0_SCK (P_DONTCARE) #define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) #define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h index 2b66ecf489f7..746a794b3119 100644 --- a/include/asm-blackfin/mach-bf537/anomaly.h +++ b/include/asm-blackfin/mach-bf537/anomaly.h @@ -7,9 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision M, March 13, 2007; ADSP-BF537 Blackfin Processor Anomaly List - * - Revision L, March 13, 2007; ADSP-BF536 Blackfin Processor Anomaly List - * - Revision M, March 13, 2007; ADSP-BF534 Blackfin Processor Anomaly List + * - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -17,7 +15,7 @@ /* We do not support 0.1 silicon - sorry */ #if __SILICON_REVISION__ < 2 -# error Kernel will not work on BF537 silicon version 0.0 or 0.1 +# error will not work on BF537 silicon version 0.0 or 0.1 #endif #if defined(__ADSPBF534__) @@ -44,6 +42,8 @@ #define ANOMALY_05000122 (1) /* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ #define ANOMALY_05000157 (__SILICON_REVISION__ < 2) +/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ +#define ANOMALY_05000167 (1) /* PPI_DELAY not functional in PPI modes with 0 frame syncs */ #define ANOMALY_05000180 (1) /* Instruction Cache Is Not Functional */ @@ -130,6 +130,12 @@ #define ANOMALY_05000321 (__SILICON_REVISION__ < 3) /* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ #define ANOMALY_05000322 (1) +/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ +#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) +/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ +#define ANOMALY_05000357 (1) +/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ +#define ANOMALY_05000359 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h index 6fb328f5186a..86e45c379838 100644 --- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h @@ -146,7 +146,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart) if (uart->rts_pin >= 0) { gpio_request(uart->rts_pin, DRIVER_NAME); - gpio_direction_output(uart->rts_pin); + gpio_direction_output(uart->rts_pin, 0); } #endif } diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h index 36c44bc1a917..be6f2ff77f31 100644 --- a/include/asm-blackfin/mach-bf537/irq.h +++ b/include/asm-blackfin/mach-bf537/irq.h @@ -162,11 +162,7 @@ Core Emulation ** #define GPIO_IRQ_BASE IRQ_PF0 -#ifdef CONFIG_IRQCHIP_DEMUX_GPIO #define NR_IRQS (IRQ_PH15+1) -#else -#define NR_IRQS (IRQ_UART1_ERROR+1) -#endif #define IVG7 7 #define IVG8 8 diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h index 18759e38eaae..5c6726d6f3b1 100644 --- a/include/asm-blackfin/mach-bf537/mem_map.h +++ b/include/asm-blackfin/mach-bf537/mem_map.h @@ -47,6 +47,7 @@ /* Boot ROM Memory */ #define BOOT_ROM_START 0xEF000000 +#define BOOT_ROM_LENGTH 0x800 /* Level 1 Memory */ @@ -167,9 +168,7 @@ /* Scratch Pad Memory */ -#if defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534) #define L1_SCRATCH_START 0xFFB00000 #define L1_SCRATCH_LENGTH 0x1000 -#endif #endif /* _MEM_MAP_537_H_ */ diff --git a/include/asm-blackfin/mach-bf537/portmux.h b/include/asm-blackfin/mach-bf537/portmux.h index 5a3f7d3bf73d..78fee6e0f237 100644 --- a/include/asm-blackfin/mach-bf537/portmux.h +++ b/include/asm-blackfin/mach-bf537/portmux.h @@ -1,6 +1,8 @@ #ifndef _MACH_PORTMUX_H_ #define _MACH_PORTMUX_H_ +#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */ + #define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) #define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) #define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index c5b63759cdee..850dc12eb7f2 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision C, July 16, 2007; ADSP-BF549 Silicon Anomaly List + * - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -26,47 +26,59 @@ /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) /* False Hardware Error Exception when ISR context is not restored */ -#define ANOMALY_05000281 (1) +#define ANOMALY_05000281 (__SILICON_REVISION__ < 1) /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ -#define ANOMALY_05000304 (1) +#define ANOMALY_05000304 (__SILICON_REVISION__ < 1) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (1) +#define ANOMALY_05000312 (__SILICON_REVISION__ < 1) /* TWI Slave Boot Mode Is Not Functional */ -#define ANOMALY_05000324 (1) +#define ANOMALY_05000324 (__SILICON_REVISION__ < 1) /* External FIFO Boot Mode Is Not Functional */ -#define ANOMALY_05000325 (1) +#define ANOMALY_05000325 (__SILICON_REVISION__ < 1) /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ -#define ANOMALY_05000327 (1) +#define ANOMALY_05000327 (__SILICON_REVISION__ < 1) /* Incorrect Access of OTP_STATUS During otp_write() Function */ -#define ANOMALY_05000328 (1) +#define ANOMALY_05000328 (__SILICON_REVISION__ < 1) /* Synchronous Burst Flash Boot Mode Is Not Functional */ -#define ANOMALY_05000329 (1) +#define ANOMALY_05000329 (__SILICON_REVISION__ < 1) /* Host DMA Boot Mode Is Not Functional */ -#define ANOMALY_05000330 (1) +#define ANOMALY_05000330 (__SILICON_REVISION__ < 1) /* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ -#define ANOMALY_05000334 (1) +#define ANOMALY_05000334 (__SILICON_REVISION__ < 1) /* Inadequate Rotary Debounce Logic Duration */ -#define ANOMALY_05000335 (1) +#define ANOMALY_05000335 (__SILICON_REVISION__ < 1) /* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ -#define ANOMALY_05000336 (1) +#define ANOMALY_05000336 (__SILICON_REVISION__ < 1) /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ -#define ANOMALY_05000337 (1) +#define ANOMALY_05000337 (__SILICON_REVISION__ < 1) /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ -#define ANOMALY_05000338 (1) +#define ANOMALY_05000338 (__SILICON_REVISION__ < 1) /* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ -#define ANOMALY_05000340 (1) +#define ANOMALY_05000340 (__SILICON_REVISION__ < 1) /* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ -#define ANOMALY_05000344 (1) +#define ANOMALY_05000344 (__SILICON_REVISION__ < 1) /* USB Calibration Value Is Not Intialized */ -#define ANOMALY_05000346 (1) +#define ANOMALY_05000346 (__SILICON_REVISION__ < 1) /* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ -#define ANOMALY_05000347 (1) +#define ANOMALY_05000347 (__SILICON_REVISION__ < 1) /* Data Lost when Core Reads SDH Data FIFO */ -#define ANOMALY_05000349 (1) +#define ANOMALY_05000349 (__SILICON_REVISION__ < 1) /* PLL Status Register Is Inaccurate */ -#define ANOMALY_05000351 (1) +#define ANOMALY_05000351 (__SILICON_REVISION__ < 1) +/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ +#define ANOMALY_05000357 (1) +/* External Memory Read Access Hangs Core With PLL Bypass */ +#define ANOMALY_05000360 (1) +/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ +#define ANOMALY_05000365 (1) +/* Addressing Conflict between Boot ROM and Asynchronous Memory */ +#define ANOMALY_05000369 (1) +/* Mobile DDR Operation Not Functional */ +#define ANOMALY_05000377 (1) +/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ +#define ANOMALY_05000378 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h index 7e6d349beb08..e748588e8930 100644 --- a/include/asm-blackfin/mach-bf548/bf548.h +++ b/include/asm-blackfin/mach-bf548/bf548.h @@ -106,24 +106,22 @@ #define AMGCTLVAL (V_AMBEN | V_AMCKEN) -#ifdef CONFIG_BF542 -#define CPU "BF542" -#define CPUID 0x027c8000 -#endif -#ifdef CONFIG_BF544 -#define CPU "BF544" -#define CPUID 0x027c8000 -#endif -#ifdef CONFIG_BF548 -#define CPU "BF548" -#define CPUID 0x027c6000 -#endif -#ifdef CONFIG_BF549 -#define CPU "BF549" -#endif -#ifndef CPU -#define CPU "UNKNOWN" -#define CPUID 0x0 +#if defined(CONFIG_BF542) +# define CPU "BF542" +# define CPUID 0x027c8000 +#elif defined(CONFIG_BF544) +# define CPU "BF544" +# define CPUID 0x027c8000 +#elif defined(CONFIG_BF547) +# define CPU "BF547" +#elif defined(CONFIG_BF548) +# define CPU "BF548" +# define CPUID 0x027c6000 +#elif defined(CONFIG_BF549) +# define CPU "BF549" +#else +# define CPU "UNKNOWN" +# define CPUID 0x0 #endif #endif /* __MACH_BF48_H__ */ diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h index f21a1620e6bd..3770aa38ee9f 100644 --- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h @@ -186,7 +186,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart) if (uart->rts_pin >= 0) { gpio_request(uart->rts_pin, DRIVER_NAME); - gpio_direction_output(uart->rts_pin); + gpio_direction_output(uart->rts_pin, 0); } #endif } diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h index aefab3f618c1..19ddcd83c71f 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h @@ -244,39 +244,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) #define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) -#define bfin_read_TWI_CLKDIV() bfin_read16(TWI0_CLKDIV) -#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) -#define bfin_read_TWI_CONTROL() bfin_read16(TWI0_CONTROL) -#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI0_CONTROL, val) -#define bfin_read_TWI_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL) -#define bfin_write_TWI_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val) -#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) -#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) -#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) -#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) -#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI0_MASTER_CTRL) -#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTRL, val) -#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) -#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) -#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) -#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) -#define bfin_read_TWI_INT_STAT() bfin_read16(TWI0_INT_STAT) -#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) -#define bfin_read_TWI_INT_MASK() bfin_read16(TWI0_INT_MASK) -#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) -#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI0_FIFO_CTRL) -#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTRL, val) -#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) -#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) -#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) -#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) -#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) -#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) -#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) -#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) -#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) -#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) - /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ /* SPORT1 Registers */ diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h index 32d07130200c..a7c809f29ede 100644 --- a/include/asm-blackfin/mach-bf548/defBF542.h +++ b/include/asm-blackfin/mach-bf548/defBF542.h @@ -432,8 +432,8 @@ #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ -#define CMD_TIMEOUT 0x4 /* CMD Time Out */ -#define DAT_TIMEOUT 0x8 /* Data Time Out */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ #define TX_UNDERRUN 0x10 /* Transmit Underrun */ #define RX_OVERRUN 0x20 /* Receive Overrun */ #define CMD_RESP_END 0x40 /* CMD Response End */ diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h index 760307e34b9e..b8b9870e2697 100644 --- a/include/asm-blackfin/mach-bf548/defBF544.h +++ b/include/asm-blackfin/mach-bf548/defBF544.h @@ -645,7 +645,7 @@ /* Bit masks for HOST_STATUS */ -#define READY 0x1 /* DMA Ready */ +#define DMA_READY 0x1 /* DMA Ready */ #define FIFOFULL 0x2 /* FIFO Full */ #define FIFOEMPTY 0x4 /* FIFO Empty */ #define COMPLETE 0x8 /* DMA Complete */ diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h index 70af33c963b0..e46f56891e6a 100644 --- a/include/asm-blackfin/mach-bf548/defBF548.h +++ b/include/asm-blackfin/mach-bf548/defBF548.h @@ -1007,7 +1007,7 @@ /* Bit masks for HOST_STATUS */ -#define READY 0x1 /* DMA Ready */ +#define DMA_READY 0x1 /* DMA Ready */ #define FIFOFULL 0x2 /* FIFO Full */ #define FIFOEMPTY 0x4 /* FIFO Empty */ #define COMPLETE 0x8 /* DMA Complete */ @@ -1095,8 +1095,8 @@ #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ -#define CMD_TIMEOUT 0x4 /* CMD Time Out */ -#define DAT_TIMEOUT 0x8 /* Data Time Out */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ #define TX_UNDERRUN 0x10 /* Transmit Underrun */ #define RX_OVERRUN 0x20 /* Receive Overrun */ #define CMD_RESP_END 0x40 /* CMD Response End */ diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h index 4e46d657e50e..fcb72b41e007 100644 --- a/include/asm-blackfin/mach-bf548/defBF549.h +++ b/include/asm-blackfin/mach-bf548/defBF549.h @@ -1671,7 +1671,7 @@ /* Bit masks for MXVR_DMAx_CONFIG */ #define MDMAEN 0x1 /* DMA Channel Enable */ -#define DD 0x2 /* DMA Channel Direction */ +#define DMADD 0x2 /* DMA Channel Direction */ #define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */ #define LCHAN 0x3c0 /* DMA Channel Logical Channel */ #define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */ diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h index 1d365c844ffe..08f90c21fe8a 100644 --- a/include/asm-blackfin/mach-bf548/defBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h @@ -1644,8 +1644,25 @@ #define RESTART 0x20 /* Work Unit Transitions */ #define DI_SEL 0x40 /* Data Interrupt Timing Select */ #define DI_EN 0x80 /* Data Interrupt Enable */ + #define NDSIZE 0xf00 /* Flex Descriptor Size */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ + #define DMAFLOW 0xf000 /* Next Operation */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ /* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ @@ -1755,17 +1772,36 @@ #define TRP 0x3c0000 /* Pre charge-to-active command period */ #define TRAS 0x3c00000 /* Min Active-to-pre charge time */ #define TRC 0x3c000000 /* Active-to-active time */ +#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */ +#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */ +#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */ +#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */ +#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */ /* Bit masks for EBIU_DDRCTL1 */ #define TRCD 0xf /* Active-to-Read/write delay */ -#define MRD 0xf0 /* Mode register set to active */ +#define TMRD 0xf0 /* Mode register set to active */ #define TWR 0x300 /* Write Recovery time */ #define DDRDATWIDTH 0x3000 /* DDR data width */ #define EXTBANKS 0xc000 /* External banks */ #define DDRDEVWIDTH 0x30000 /* DDR device width */ #define DDRDEVSIZE 0xc0000 /* DDR device size */ -#define TWWTR 0xf0000000 /* Write-to-read delay */ +#define TWTR 0xf0000000 /* Write-to-read delay */ +#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */ +#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */ +#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */ +#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */ +#define DDR_DATWIDTH 0x2000 /* DDR data width */ +#define EXTBANK_1 0 /* 1 external bank */ +#define EXTBANK_2 0x4000 /* 2 external banks */ +#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */ +#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */ +#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */ +#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */ +#define DEVWD_4 0 /* DDR Device Width = 4 Bits */ +#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */ +#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */ /* Bit masks for EBIU_DDRCTL2 */ @@ -1773,6 +1809,10 @@ #define CASLATENCY 0x70 /* CAS latency */ #define DLLRESET 0x100 /* DLL Reset */ #define REGE 0x1000 /* Register mode enable */ +#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */ +#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */ +#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */ +#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */ /* Bit masks for EBIU_DDRCTL3 */ @@ -2240,6 +2280,10 @@ #define CSEL 0x30 /* Core Select */ #define SSEL 0xf /* System Select */ +#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ +#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ +#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ +#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ /* Bit masks for PLL_CTL */ @@ -2252,6 +2296,13 @@ #define PLL_OFF 0x2 /* Disable PLL */ #define DF 0x1 /* Divide Frequency */ +/* SWRST Masks */ +#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ +#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ +#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ +#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ +#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ + /* Bit masks for PLL_STAT */ #define PLL_LOCKED 0x20 /* PLL Locked Status */ diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h index 3b08cf9bd6f3..c34507a3f1df 100644 --- a/include/asm-blackfin/mach-bf548/irq.h +++ b/include/asm-blackfin/mach-bf548/irq.h @@ -88,7 +88,7 @@ Events (highest priority) EMU 0 #define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ #define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ #define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ -#define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */ +#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */ #define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ #define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ #define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ @@ -338,11 +338,7 @@ Events (highest priority) EMU 0 #define GPIO_IRQ_BASE IRQ_PA0 -#ifdef CONFIG_IRQCHIP_DEMUX_GPIO #define NR_IRQS (IRQ_PJ15+1) -#else -#define NR_IRQS (SYS_IRQS+1) -#endif /* For compatibility reasons with existing code */ @@ -410,7 +406,7 @@ Events (highest priority) EMU 0 #define IRQ_PINT1_POS 16 #define IRQ_MDMAS0_POS 20 #define IRQ_MDMAS1_POS 24 -#define IRQ_WATCHDOG_POS 28 +#define IRQ_WATCH_POS 28 /* IAR3 BIT FIELDS */ #define IRQ_DMAC1_ERR_POS 0 diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h index 0cb279e973d7..befc2903d5a5 100644 --- a/include/asm-blackfin/mach-bf548/mem_init.h +++ b/include/asm-blackfin/mach-bf548/mem_init.h @@ -28,8 +28,68 @@ * If not, write to the Free Software Foundation, * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1) + +#if (CONFIG_MEM_MT46V32M16_6T) +#define DDR_SIZE DEVSZ_512 +#define DDR_WIDTH DEVWD_16 + +#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60)) +#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42)) +#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) +#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72)) +#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800)) + +#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) +#define DDR_tWTR DDR_TWTR(1) +#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12)) +#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) +#endif + +#if (CONFIG_MEM_MT46V32M16_5B) +#define DDR_SIZE DEVSZ_512 +#define DDR_WIDTH DEVWD_16 + +#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55)) +#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40)) +#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) +#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70)) +#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800)) + +#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) +#define DDR_tWTR DDR_TWTR(2) +#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10)) +#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) +#endif + +#if (CONFIG_MEM_GENERIC_BOARD) +#define DDR_SIZE DEVSZ_512 +#define DDR_WIDTH DEVWD_16 + +#define DDR_tRCD DDR_TRCD(3) +#define DDR_tWTR DDR_TWTR(2) +#define DDR_tWR DDR_TWR(2) +#define DDR_tMRD DDR_TMRD(2) +#define DDR_tRP DDR_TRP(3) +#define DDR_tRAS DDR_TRAS(7) +#define DDR_tRC DDR_TRC(10) +#define DDR_tRFC DDR_TRFC(12) +#define DDR_tREFI DDR_TREFI(1288) +#endif + +#if (CONFIG_SCLK_HZ <= 133333333) +#define DDR_CL CL_2 +#elif (CONFIG_SCLK_HZ <= 166666666) +#define DDR_CL CL_2_5 +#else +#define DDR_CL CL_3 +#endif + +#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI) +#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \ + | DDR_tMRD | DDR_tWR | DDR_tRCD) +#define mem_DDRCTL2 DDR_CL -#if (CONFIG_MEM_MT46V32M16) #if defined CONFIG_CLKIN_HALF #define CLKIN_HALF 1 diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h index ec1597e31831..f99f47bc3a07 100644 --- a/include/asm-blackfin/mach-bf548/mem_map.h +++ b/include/asm-blackfin/mach-bf548/mem_map.h @@ -47,6 +47,12 @@ /* Boot ROM Memory */ #define BOOT_ROM_START 0xEF000000 +#define BOOT_ROM_LENGTH 0x1000 + +/* L1 Instruction ROM */ + +#define L1_ROM_START 0xFFA14000 +#define L1_ROM_LENGTH 0x10000 /* Level 1 Memory */ @@ -87,11 +93,19 @@ #define BFIN_DSUPBANKS 0 #endif /*CONFIG_BFIN_DCACHE*/ +/* Level 2 Memory */ +#if !defined(CONFIG_BF542) +# define L2_START 0xFEB00000 +# if defined(CONFIG_BF544) +# define L2_LENGTH 0x10000 +# else +# define L2_LENGTH 0x20000 +# endif +#endif + /* Scratch Pad Memory */ -#if defined(CONFIG_BF54x) #define L1_SCRATCH_START 0xFFB00000 #define L1_SCRATCH_LENGTH 0x1000 -#endif #endif/* _MEM_MAP_548_H_ */ diff --git a/include/asm-blackfin/mach-bf548/portmux.h b/include/asm-blackfin/mach-bf548/portmux.h index b382deb501a7..8177a567dcdb 100644 --- a/include/asm-blackfin/mach-bf548/portmux.h +++ b/include/asm-blackfin/mach-bf548/portmux.h @@ -1,6 +1,8 @@ #ifndef _MACH_PORTMUX_H_ #define _MACH_PORTMUX_H_ +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + #define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) #define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) #define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0)) @@ -267,4 +269,18 @@ #define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0)) #define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0)) + +#define P_NAND_D0 (P_DONTCARE) +#define P_NAND_D1 (P_DONTCARE) +#define P_NAND_D2 (P_DONTCARE) +#define P_NAND_D3 (P_DONTCARE) +#define P_NAND_D4 (P_DONTCARE) +#define P_NAND_D5 (P_DONTCARE) +#define P_NAND_D6 (P_DONTCARE) +#define P_NAND_D7 (P_DONTCARE) +#define P_NAND_WE (P_DONTCARE) +#define P_NAND_RE (P_DONTCARE) +#define P_NAND_CLE (P_DONTCARE) +#define P_NAND_ALE (P_DONTCARE) + #endif /* _MACH_PORTMUX_H_ */ diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h index bed956456884..0c1d46193939 100644 --- a/include/asm-blackfin/mach-bf561/anomaly.h +++ b/include/asm-blackfin/mach-bf561/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision N, March 28, 2007; ADSP-BF561 Silicon Anomaly List + * - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -15,7 +15,7 @@ /* We do not support 0.1, 0.2, or 0.4 silicon - sorry */ #if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4 -# error Kernel will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 +# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 #endif /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ @@ -208,6 +208,8 @@ #define ANOMALY_05000275 (__SILICON_REVISION__ > 2) /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ #define ANOMALY_05000276 (__SILICON_REVISION__ < 5) +/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */ +#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 5) /* False Hardware Error Exception When ISR Context Is Not Restored */ @@ -246,6 +248,18 @@ #define ANOMALY_05000332 (__SILICON_REVISION__ < 5) /* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */ #define ANOMALY_05000333 (__SILICON_REVISION__ < 5) +/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */ +#define ANOMALY_05000339 (__SILICON_REVISION__ < 5) +/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */ +#define ANOMALY_05000343 (__SILICON_REVISION__ < 5) +/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ +#define ANOMALY_05000357 (1) +/* Conflicting Column Address Widths Causes SDRAM Errors */ +#define ANOMALY_05000362 (1) +/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ +#define ANOMALY_05000366 (1) +/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ +#define ANOMALY_05000371 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000158 (0) diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h index 17e1d5dcef02..3ef9e5f36136 100644 --- a/include/asm-blackfin/mach-bf561/bf561.h +++ b/include/asm-blackfin/mach-bf561/bf561.h @@ -33,25 +33,6 @@ #define SUPPORTED_REVID 0x3 #define OFFSET_(x) ((x) & 0x0000FFFF) -#define L1_ISRAM 0xFFA00000 -#define L1_ISRAM_END 0xFFA04000 -#define DATA_BANKA_SRAM 0xFF800000 -#define DATA_BANKA_SRAM_END 0xFF804000 -#define DATA_BANKB_SRAM 0xFF900000 -#define DATA_BANKB_SRAM_END 0xFF904000 -#define L1_DSRAMA 0xFF800000 -#define L1_DSRAMA_END 0xFF804000 -#define L1_DSRAMB 0xFF900000 -#define L1_DSRAMB_END 0xFF904000 -#define L2_SRAM 0xFEB00000 -#define L2_SRAM_END 0xFEB20000 -#define AMB_FLASH 0x20000000 -#define AMB_FLASH_END 0x21000000 -#define AMB_FLASH_LENGTH 0x01000000 -#define L1_ISRAM_LENGTH 0x4000 -#define L1_DSRAMA_LENGTH 0x4000 -#define L1_DSRAMB_LENGTH 0x4000 -#define L2_SRAM_LENGTH 0x20000 /*some misc defines*/ #define IMASK_IVG15 0x8000 diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h index 69b9f8e120e9..7871d4313f49 100644 --- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h @@ -111,7 +111,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart) } if (uart->rts_pin >= 0) { gpio_request(uart->rts_pin, DRIVER_NAME); - gpio_direction_input(uart->rts_pin); + gpio_direction_input(uart->rts_pin, 0); } #endif } diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h index bf7dc4e00065..c3c0eb13c819 100644 --- a/include/asm-blackfin/mach-bf561/defBF561.h +++ b/include/asm-blackfin/mach-bf561/defBF561.h @@ -55,6 +55,10 @@ /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ #define SWRST SICA_SWRST #define SYSCR SICA_SYSCR +#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A) +#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) +#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) +#define RESET_SOFTWARE (SWRST_OCCURRED) /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ #define SICA_SWRST 0xFFC00100 /* Software Reset register */ @@ -874,12 +878,14 @@ #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ /* SWRST Mask */ -#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */ -#define SWRST_DBL_FAULT_B 0x00000800 /* SWRST Core B Double Fault */ -#define SWRST_DBL_FAULT_A 0x00001000 /* SWRST Core A Double Fault */ -#define SWRST_WDT_B 0x00002000 /* SWRST Watchdog B */ -#define SWRST_WDT_A 0x00004000 /* SWRST Watchdog A */ -#define SWRST_OCCURRED 0x00008000 /* SWRST Status */ +#define SYSTEM_RESET 0x0007 /* Initiates a system software reset */ +#define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */ +#define DOUBLE_FAULT_B 0x0010 /* Core B Double Fault Causes Reset */ +#define SWRST_DBL_FAULT_A 0x0800 /* SWRST Core A Double Fault */ +#define SWRST_DBL_FAULT_B 0x1000 /* SWRST Core B Double Fault */ +#define SWRST_WDT_B 0x2000 /* SWRST Watchdog B */ +#define SWRST_WDT_A 0x4000 /* SWRST Watchdog A */ +#define SWRST_OCCURRED 0x8000 /* SWRST Status */ /* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h index 12789927db3d..83f0383957d2 100644 --- a/include/asm-blackfin/mach-bf561/irq.h +++ b/include/asm-blackfin/mach-bf561/irq.h @@ -291,11 +291,7 @@ #define GPIO_IRQ_BASE IRQ_PF0 -#ifdef CONFIG_IRQCHIP_DEMUX_GPIO #define NR_IRQS (IRQ_PF47 + 1) -#else -#define NR_IRQS SYS_IRQS -#endif #define IVG7 7 #define IVG8 8 diff --git a/include/asm-blackfin/mach-bf561/mem_map.h b/include/asm-blackfin/mach-bf561/mem_map.h index f7ac09cf2c3d..c26d8486cc4b 100644 --- a/include/asm-blackfin/mach-bf561/mem_map.h +++ b/include/asm-blackfin/mach-bf561/mem_map.h @@ -19,6 +19,11 @@ #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ #define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ +/* Boot ROM Memory */ + +#define BOOT_ROM_START 0xEF000000 +#define BOOT_ROM_LENGTH 0x800 + /* Level 1 Memory */ #ifdef CONFIG_BFIN_ICACHE @@ -67,9 +72,7 @@ /* Scratch Pad Memory */ -#if defined(CONFIG_BF561) #define L1_SCRATCH_START 0xFFB00000 #define L1_SCRATCH_LENGTH 0x1000 -#endif #endif /* _MEM_MAP_533_H_ */ diff --git a/include/asm-blackfin/mach-bf561/portmux.h b/include/asm-blackfin/mach-bf561/portmux.h index 132ad31665e3..a6ee8206efb6 100644 --- a/include/asm-blackfin/mach-bf561/portmux.h +++ b/include/asm-blackfin/mach-bf561/portmux.h @@ -1,6 +1,8 @@ #ifndef _MACH_PORTMUX_H_ #define _MACH_PORTMUX_H_ +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + #define P_PPI0_CLK (P_DONTCARE) #define P_PPI0_FS1 (P_DONTCARE) #define P_PPI0_FS2 (P_DONTCARE) diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h index c1d8c4a78fcf..e8967f6124f7 100644 --- a/include/asm-blackfin/mach-common/def_LPBlackfin.h +++ b/include/asm-blackfin/mach-common/def_LPBlackfin.h @@ -46,7 +46,7 @@ #endif #define bfin_read8(addr) ({ \ - uint8_t __v; \ + uint32_t __v; \ __asm__ __volatile__( \ NOP_PAD_ANOMALY_05000198 \ "%0 = b[%1] (z);" \ @@ -56,7 +56,7 @@ __v; }) #define bfin_read16(addr) ({ \ - uint16_t __v; \ + uint32_t __v; \ __asm__ __volatile__( \ NOP_PAD_ANOMALY_05000198 \ "%0 = w[%1] (z);" \ @@ -80,7 +80,7 @@ NOP_PAD_ANOMALY_05000198 \ "b[%0] = %1;" \ : \ - : "a" (addr), "d" (val) \ + : "a" (addr), "d" ((uint8_t)(val)) \ : "memory" \ ) @@ -89,7 +89,7 @@ NOP_PAD_ANOMALY_05000198 \ "w[%0] = %1;" \ : \ - : "a" (addr), "d" (val) \ + : "a" (addr), "d" ((uint16_t)(val)) \ : "memory" \ ) diff --git a/include/asm-blackfin/mmu.h b/include/asm-blackfin/mmu.h index 11d52f1167d0..757e43906ed4 100644 --- a/include/asm-blackfin/mmu.h +++ b/include/asm-blackfin/mmu.h @@ -24,7 +24,9 @@ typedef struct { unsigned long exec_fdpic_loadmap; unsigned long interp_fdpic_loadmap; #endif - +#ifdef CONFIG_MPU + unsigned long *page_rwx_mask; +#endif } mm_context_t; #endif diff --git a/include/asm-blackfin/mmu_context.h b/include/asm-blackfin/mmu_context.h index c5c71a6aaf19..b5eb67596ad5 100644 --- a/include/asm-blackfin/mmu_context.h +++ b/include/asm-blackfin/mmu_context.h @@ -30,9 +30,12 @@ #ifndef __BLACKFIN_MMU_CONTEXT_H__ #define __BLACKFIN_MMU_CONTEXT_H__ +#include <linux/gfp.h> +#include <linux/sched.h> #include <asm/setup.h> #include <asm/page.h> #include <asm/pgalloc.h> +#include <asm/cplbinit.h> extern void *current_l1_stack_save; extern int nr_l1stack_tasks; @@ -50,6 +53,12 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm) { +#ifdef CONFIG_MPU + unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order); + mm->context.page_rwx_mask = (unsigned long *)p; + memset(mm->context.page_rwx_mask, 0, + page_mask_nelts * 3 * sizeof(long)); +#endif return 0; } @@ -73,6 +82,11 @@ static inline void destroy_context(struct mm_struct *mm) sram_free(tmp->addr); kfree(tmp); } +#ifdef CONFIG_MPU + if (current_rwx_mask == mm->context.page_rwx_mask) + current_rwx_mask = NULL; + free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order); +#endif } static inline unsigned long @@ -106,9 +120,21 @@ activate_l1stack(struct mm_struct *mm, unsigned long sp_base) #define deactivate_mm(tsk,mm) do { } while (0) -static inline void activate_mm(struct mm_struct *prev_mm, - struct mm_struct *next_mm) +#define activate_mm(prev, next) switch_mm(prev, next, NULL) + +static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, + struct task_struct *tsk) { + if (prev_mm == next_mm) + return; +#ifdef CONFIG_MPU + if (prev_mm->context.page_rwx_mask == current_rwx_mask) { + flush_switched_cplbs(); + set_mask_dcplbs(next_mm->context.page_rwx_mask); + } +#endif + + /* L1 stack switching. */ if (!next_mm->context.l1_stack_save) return; if (next_mm->context.l1_stack_save == current_l1_stack_save) @@ -120,10 +146,36 @@ static inline void activate_mm(struct mm_struct *prev_mm, memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len); } -static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) +#ifdef CONFIG_MPU +static inline void protect_page(struct mm_struct *mm, unsigned long addr, + unsigned long flags) +{ + unsigned long *mask = mm->context.page_rwx_mask; + unsigned long page = addr >> 12; + unsigned long idx = page >> 5; + unsigned long bit = 1 << (page & 31); + + if (flags & VM_MAYREAD) + mask[idx] |= bit; + else + mask[idx] &= ~bit; + mask += page_mask_nelts; + if (flags & VM_MAYWRITE) + mask[idx] |= bit; + else + mask[idx] &= ~bit; + mask += page_mask_nelts; + if (flags & VM_MAYEXEC) + mask[idx] |= bit; + else + mask[idx] &= ~bit; +} + +static inline void update_protections(struct mm_struct *mm) { - activate_mm(prev, next); + flush_switched_cplbs(); + set_mask_dcplbs(mm->context.page_rwx_mask); } +#endif #endif diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h index 3b671d5fd70d..cbaff24b4b25 100644 --- a/include/asm-blackfin/page_offset.h +++ b/include/asm-blackfin/page_offset.h @@ -1,6 +1,6 @@ /* This handles the memory map.. */ -#ifdef CONFIG_BFIN +#ifdef CONFIG_BLACKFIN #define PAGE_OFFSET_RAW 0x00000000 #endif diff --git a/include/asm-blackfin/socket.h b/include/asm-blackfin/socket.h index 5213c9652186..2ca702e44d47 100644 --- a/include/asm-blackfin/socket.h +++ b/include/asm-blackfin/socket.h @@ -50,4 +50,7 @@ #define SO_PASSSEC 34 #define SO_TIMESTAMPNS 35 #define SCM_TIMESTAMPNS SO_TIMESTAMPNS + +#define SO_MARK 36 + #endif /* _ASM_SOCKET_H */ diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h index e8ada91ab002..321f4d96e4ae 100644 --- a/include/asm-blackfin/string.h +++ b/include/asm-blackfin/string.h @@ -1,6 +1,8 @@ #ifndef _BLACKFIN_STRING_H_ #define _BLACKFIN_STRING_H_ +#include <linux/types.h> + #ifdef __KERNEL__ /* only set these up for kernel code */ #define __HAVE_ARCH_STRCPY diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h index fe365b1b7ca8..f0e5f940d9ca 100644 --- a/include/asm-blackfin/traps.h +++ b/include/asm-blackfin/traps.h @@ -45,31 +45,87 @@ #define VEC_CPLB_I_M (44) #define VEC_CPLB_I_MHIT (45) #define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */ +/* The hardware reserves (63) for future use - we use it to tell our + * normal exception handling code we have a hardware error + */ +#define VEC_HWERR (63) #ifndef __ASSEMBLY__ -#define HWC_x2 "System MMR Error\nAn error occurred due to an invalid access to an System MMR location\nPossible reason: a 32-bit register is accessed with a 16-bit instruction,\nor a 16-bit register is accessed with a 32-bit instruction.\n" -#define HWC_x3 "External Memory Addressing Error\n" -#define HWC_x12 "Performance Monitor Overflow\n" -#define HWC_x18 "RAISE 5 instruction\n Software issued a RAISE 5 instruction to invoke the Hardware\n" -#define HWC_default "Reserved\n" - -#define EXC_0x03 "Application stack overflow\n - Please increase the stack size of the application using elf2flt -s option,\n and/or reduce the stack use of the application.\n" -#define EXC_0x10 "Single step\n - When the processor is in single step mode, every instruction\n generates an exception. Primarily used for debugging.\n" -#define EXC_0x11 "Exception caused by a trace buffer full condition\n - The processor takes this exception when the trace\n buffer overflows (only when enabled by the Trace Unit Control register).\n" -#define EXC_0x21 "Undefined instruction\n - May be used to emulate instructions that are not defined for\n a particular processor implementation.\n" -#define EXC_0x22 "Illegal instruction combination\n - See section for multi-issue rules in the ADSP-BF53x Blackfin\n Processor Instruction Set Reference.\n" -#define EXC_0x23 "Data access CPLB protection violation\n - Attempted read or write to Supervisor resource,\n or illegal data memory access. \n" -#define EXC_0x24 "Data access misaligned address violation\n - Attempted misaligned data memory or data cache access.\n" -#define EXC_0x25 "Unrecoverable event\n - For example, an exception generated while processing a previous exception.\n" -#define EXC_0x26 "Data access CPLB miss\n - Used by the MMU to signal a CPLB miss on a data access.\n" -#define EXC_0x27 "Data access multiple CPLB hits\n - More than one CPLB entry matches data fetch address.\n" -#define EXC_0x28 "Program Sequencer Exception caused by an emulation watchpoint match\n - There is a watchpoint match, and one of the EMUSW\n bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" -#define EXC_0x2A "Instruction fetch misaligned address violation\n - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch exception,\n the return address provided in RETX is the destination address which is misaligned, rather than the address of the offending instruction.\n" -#define EXC_0x2B "CPLB protection violation\n - Illegal instruction fetch access (memory protection violation).\n" -#define EXC_0x2C "Instruction fetch CPLB miss\n - CPLB miss on an instruction fetch.\n" -#define EXC_0x2D "Instruction fetch multiple CPLB hits\n - More than one CPLB entry matches instruction fetch address.\n" -#define EXC_0x2E "Illegal use of supervisor resource\n - Attempted to use a Supervisor register or instruction from User mode.\n Supervisor resources are registers and instructions that are reserved\n for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n only instructions.\n" +#define HWC_x2(level) \ + "System MMR Error\n" \ + level " - An error occurred due to an invalid access to an System MMR location\n" \ + level " Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \ + level " or a 16-bit register is accessed with a 32-bit instruction.\n" +#define HWC_x3(level) \ + "External Memory Addressing Error\n" +#define HWC_x12(level) \ + "Performance Monitor Overflow\n" +#define HWC_x18(level) \ + "RAISE 5 instruction\n" \ + level " Software issued a RAISE 5 instruction to invoke the Hardware\n" +#define HWC_default(level) \ + "Reserved\n" +#define EXC_0x03(level) \ + "Application stack overflow\n" \ + level " - Please increase the stack size of the application using elf2flt -s option,\n" \ + level " and/or reduce the stack use of the application.\n" +#define EXC_0x10(level) \ + "Single step\n" \ + level " - When the processor is in single step mode, every instruction\n" \ + level " generates an exception. Primarily used for debugging.\n" +#define EXC_0x11(level) \ + "Exception caused by a trace buffer full condition\n" \ + level " - The processor takes this exception when the trace\n" \ + level " buffer overflows (only when enabled by the Trace Unit Control register).\n" +#define EXC_0x21(level) \ + "Undefined instruction\n" \ + level " - May be used to emulate instructions that are not defined for\n" \ + level " a particular processor implementation.\n" +#define EXC_0x22(level) \ + "Illegal instruction combination\n" \ + level " - See section for multi-issue rules in the ADSP-BF53x Blackfin\n" \ + level " Processor Instruction Set Reference.\n" +#define EXC_0x23(level) \ + "Data access CPLB protection violation\n" \ + level " - Attempted read or write to Supervisor resource,\n" \ + level " or illegal data memory access. \n" +#define EXC_0x24(level) \ + "Data access misaligned address violation\n" \ + level " - Attempted misaligned data memory or data cache access.\n" +#define EXC_0x25(level) \ + "Unrecoverable event\n" \ + level " - For example, an exception generated while processing a previous exception.\n" +#define EXC_0x26(level) \ + "Data access CPLB miss\n" \ + level " - Used by the MMU to signal a CPLB miss on a data access.\n" +#define EXC_0x27(level) \ + "Data access multiple CPLB hits\n" \ + level " - More than one CPLB entry matches data fetch address.\n" +#define EXC_0x28(level) \ + "Program Sequencer Exception caused by an emulation watchpoint match\n" \ + level " - There is a watchpoint match, and one of the EMUSW\n" \ + level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" +#define EXC_0x2A(level) \ + "Instruction fetch misaligned address violation\n" \ + level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \ + level " exception, the return address provided in RETX is the destination address which is\n" \ + level " misaligned, rather than the address of the offending instruction.\n" +#define EXC_0x2B(level) \ + "CPLB protection violation\n" \ + level " - Illegal instruction fetch access (memory protection violation).\n" +#define EXC_0x2C(level) \ + "Instruction fetch CPLB miss\n" \ + level " - CPLB miss on an instruction fetch.\n" +#define EXC_0x2D(level) \ + "Instruction fetch multiple CPLB hits\n" \ + level " - More than one CPLB entry matches instruction fetch address.\n" +#define EXC_0x2E(level) \ + "Illegal use of supervisor resource\n" \ + level " - Attempted to use a Supervisor register or instruction from User mode.\n" \ + level " Supervisor resources are registers and instructions that are reserved\n" \ + level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \ + level " only instructions.\n" #endif /* __ASSEMBLY__ */ #endif /* _BFIN_TRAPS_H */ diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h index 2233f8f9314d..22a410b8003b 100644 --- a/include/asm-blackfin/uaccess.h +++ b/include/asm-blackfin/uaccess.h @@ -31,7 +31,7 @@ static inline void set_fs(mm_segment_t fs) #define VERIFY_READ 0 #define VERIFY_WRITE 1 -#define access_ok(type,addr,size) _access_ok((unsigned long)(addr),(size)) +#define access_ok(type, addr, size) _access_ok((unsigned long)(addr), (size)) static inline int is_in_rom(unsigned long addr) { diff --git a/include/asm-blackfin/unistd.h b/include/asm-blackfin/unistd.h index 07ffe8b718c5..e98167358d26 100644 --- a/include/asm-blackfin/unistd.h +++ b/include/asm-blackfin/unistd.h @@ -369,8 +369,9 @@ #define __NR_set_robust_list 354 #define __NR_get_robust_list 355 #define __NR_fallocate 356 +#define __NR_semtimedop 357 -#define __NR_syscall 357 +#define __NR_syscall 358 #define NR_syscalls __NR_syscall /* Old optional stuff no one actually uses */ |