diff options
Diffstat (limited to 'drivers')
89 files changed, 9831 insertions, 1014 deletions
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 83082e2f2e44..15b138326ecc 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -812,6 +812,120 @@ int zynqmp_pm_fpga_get_status(u32 *value) EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_status); /** + * zynqmp_pm_pinctrl_request - Request Pin from firmware + * @pin: Pin number to request + * + * This function requests pin from firmware. + * + * Return: Returns status, either success or error+reason. + */ +int zynqmp_pm_pinctrl_request(const u32 pin) +{ + return zynqmp_pm_invoke_fn(PM_PINCTRL_REQUEST, pin, 0, 0, 0, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_request); + +/** + * zynqmp_pm_pinctrl_release - Inform firmware that Pin control is released + * @pin: Pin number to release + * + * This function release pin from firmware. + * + * Return: Returns status, either success or error+reason. + */ +int zynqmp_pm_pinctrl_release(const u32 pin) +{ + return zynqmp_pm_invoke_fn(PM_PINCTRL_RELEASE, pin, 0, 0, 0, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_release); + +/** + * zynqmp_pm_pinctrl_get_function - Read function id set for the given pin + * @pin: Pin number + * @id: Buffer to store function ID + * + * This function provides the function currently set for the given pin. + * + * Return: Returns status, either success or error+reason + */ +int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + if (!id) + return -EINVAL; + + ret = zynqmp_pm_invoke_fn(PM_PINCTRL_GET_FUNCTION, pin, 0, + 0, 0, ret_payload); + *id = ret_payload[1]; + + return ret; +} +EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_get_function); + +/** + * zynqmp_pm_pinctrl_set_function - Set requested function for the pin + * @pin: Pin number + * @id: Function ID to set + * + * This function sets requested function for the given pin. + * + * Return: Returns status, either success or error+reason. + */ +int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id) +{ + return zynqmp_pm_invoke_fn(PM_PINCTRL_SET_FUNCTION, pin, id, + 0, 0, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_set_function); + +/** + * zynqmp_pm_pinctrl_get_config - Get configuration parameter for the pin + * @pin: Pin number + * @param: Parameter to get + * @value: Buffer to store parameter value + * + * This function gets requested configuration parameter for the given pin. + * + * Return: Returns status, either success or error+reason. + */ +int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param, + u32 *value) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + if (!value) + return -EINVAL; + + ret = zynqmp_pm_invoke_fn(PM_PINCTRL_CONFIG_PARAM_GET, pin, param, + 0, 0, ret_payload); + *value = ret_payload[1]; + + return ret; +} +EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_get_config); + +/** + * zynqmp_pm_pinctrl_set_config - Set configuration parameter for the pin + * @pin: Pin number + * @param: Parameter to set + * @value: Parameter value to set + * + * This function sets requested configuration parameter for the given pin. + * + * Return: Returns status, either success or error+reason. + */ +int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, + u32 value) +{ + return zynqmp_pm_invoke_fn(PM_PINCTRL_CONFIG_PARAM_SET, pin, + param, value, 0, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_set_config); + +/** * zynqmp_pm_init_finalize() - PM call to inform firmware that the caller * master has initialized its own power management * diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c index 5412cb3b0b2a..134cedf151a7 100644 --- a/drivers/gpio/gpio-regmap.c +++ b/drivers/gpio/gpio-regmap.c @@ -254,6 +254,11 @@ struct gpio_regmap *gpio_regmap_register(const struct gpio_regmap_config *config chip->names = config->names; chip->label = config->label ?: dev_name(config->parent); +#if defined(CONFIG_OF_GPIO) + /* gpiolib will use of_node of the parent if chip->of_node is NULL */ + chip->of_node = to_of_node(config->fwnode); +#endif /* CONFIG_OF_GPIO */ + /* * If our regmap is fast_io we should probably set can_sleep to false. * Right now, the regmap doesn't save this property, nor is there any diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index b7675cce0027..c2c7e7963ed0 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -208,13 +208,18 @@ config PINCTRL_OXNAS select MFD_SYSCON config PINCTRL_ROCKCHIP - bool + tristate "Rockchip gpio and pinctrl driver" + depends on ARCH_ROCKCHIP || COMPILE_TEST depends on OF + select GPIOLIB select PINMUX select GENERIC_PINCONF select GENERIC_IRQ_CHIP select MFD_SYSCON select OF_GPIO + default ARCH_ROCKCHIP + help + This support pinctrl and gpio driver for Rockchip SoCs. config PINCTRL_SINGLE tristate "One-register-per-pin type device tree based pinctrl driver" @@ -318,6 +323,20 @@ config PINCTRL_ZYNQ help This selects the pinctrl driver for Xilinx Zynq. +config PINCTRL_ZYNQMP + tristate "Pinctrl driver for Xilinx ZynqMP" + depends on ZYNQMP_FIRMWARE + select PINMUX + select GENERIC_PINCONF + default ZYNQMP_FIRMWARE + help + This selects the pinctrl driver for Xilinx ZynqMP platform. + This driver will query the pin information from the firmware + and allow configuring the pins. + Configuration can include the mux function to select on those + pin(s)/group(s), and various pin configuration parameters + such as pull-up, slew rate, etc. + config PINCTRL_INGENIC bool "Pinctrl driver for the Ingenic JZ47xx SoCs" default MACH_INGENIC diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 8bf459c32a76..5ef5334a797f 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o +obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig index 0ed14de0134c..c9c5efc92731 100644 --- a/drivers/pinctrl/bcm/Kconfig +++ b/drivers/pinctrl/bcm/Kconfig @@ -29,6 +29,68 @@ config PINCTRL_BCM2835 help Say Y here to enable the Broadcom BCM2835 GPIO driver. +config PINCTRL_BCM63XX + bool + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIO_REGMAP + +config PINCTRL_BCM6318 + bool "Broadcom BCM6318 GPIO driver" + depends on (BMIPS_GENERIC || COMPILE_TEST) + depends on OF + select PINCTRL_BCM63XX + default BMIPS_GENERIC + help + Say Y here to enable the Broadcom BCM6318 GPIO driver. + +config PINCTRL_BCM6328 + bool "Broadcom BCM6328 GPIO driver" + depends on (BMIPS_GENERIC || COMPILE_TEST) + depends on OF + select PINCTRL_BCM63XX + default BMIPS_GENERIC + help + Say Y here to enable the Broadcom BCM6328 GPIO driver. + +config PINCTRL_BCM6358 + bool "Broadcom BCM6358 GPIO driver" + depends on (BMIPS_GENERIC || COMPILE_TEST) + depends on OF + select PINCTRL_BCM63XX + default BMIPS_GENERIC + help + Say Y here to enable the Broadcom BCM6358 GPIO driver. + +config PINCTRL_BCM6362 + bool "Broadcom BCM6362 GPIO driver" + depends on (BMIPS_GENERIC || COMPILE_TEST) + depends on OF + select PINCTRL_BCM63XX + default BMIPS_GENERIC + help + Say Y here to enable the Broadcom BCM6362 GPIO driver. + +config PINCTRL_BCM6368 + bool "Broadcom BCM6368 GPIO driver" + depends on (BMIPS_GENERIC || COMPILE_TEST) + depends on OF + select PINCTRL_BCM63XX + default BMIPS_GENERIC + help + Say Y here to enable the Broadcom BCM6368 GPIO driver. + +config PINCTRL_BCM63268 + bool "Broadcom BCM63268 GPIO driver" + depends on (BMIPS_GENERIC || COMPILE_TEST) + depends on OF + select PINCTRL_BCM63XX + default BMIPS_GENERIC + help + Say Y here to enable the Broadcom BCM63268 GPIO driver. + config PINCTRL_IPROC_GPIO bool "Broadcom iProc GPIO (with PINCONF) driver" depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST) diff --git a/drivers/pinctrl/bcm/Makefile b/drivers/pinctrl/bcm/Makefile index 79d5e49fdd9a..00c7b7775e63 100644 --- a/drivers/pinctrl/bcm/Makefile +++ b/drivers/pinctrl/bcm/Makefile @@ -3,6 +3,13 @@ obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o +obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o +obj-$(CONFIG_PINCTRL_BCM6318) += pinctrl-bcm6318.o +obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o +obj-$(CONFIG_PINCTRL_BCM6358) += pinctrl-bcm6358.o +obj-$(CONFIG_PINCTRL_BCM6362) += pinctrl-bcm6362.o +obj-$(CONFIG_PINCTRL_BCM6368) += pinctrl-bcm6368.o +obj-$(CONFIG_PINCTRL_BCM63268) += pinctrl-bcm63268.o obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o diff --git a/drivers/pinctrl/bcm/pinctrl-bcm6318.c b/drivers/pinctrl/bcm/pinctrl-bcm6318.c new file mode 100644 index 000000000000..77fd9b58067d --- /dev/null +++ b/drivers/pinctrl/bcm/pinctrl-bcm6318.c @@ -0,0 +1,498 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for BCM6318 GPIO unit (pinctrl + GPIO) + * + * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com> + * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com> + */ + +#include <linux/bits.h> +#include <linux/gpio/driver.h> +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include "../pinctrl-utils.h" + +#include "pinctrl-bcm63xx.h" + +#define BCM6318_NUM_GPIOS 50 +#define BCM6318_NUM_MUX 48 + +#define BCM6318_MODE_REG 0x18 +#define BCM6318_MUX_REG 0x1c +#define BCM6328_MUX_MASK GENMASK(1, 0) +#define BCM6318_PAD_REG 0x54 +#define BCM6328_PAD_MASK GENMASK(3, 0) + +struct bcm6318_pingroup { + const char *name; + const unsigned * const pins; + const unsigned num_pins; +}; + +struct bcm6318_function { + const char *name; + const char * const *groups; + const unsigned num_groups; + + unsigned mode_val:1; + unsigned mux_val:2; +}; + +static const struct pinctrl_pin_desc bcm6318_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), + PINCTRL_PIN(23, "gpio23"), + PINCTRL_PIN(24, "gpio24"), + PINCTRL_PIN(25, "gpio25"), + PINCTRL_PIN(26, "gpio26"), + PINCTRL_PIN(27, "gpio27"), + PINCTRL_PIN(28, "gpio28"), + PINCTRL_PIN(29, "gpio29"), + PINCTRL_PIN(30, "gpio30"), + PINCTRL_PIN(31, "gpio31"), + PINCTRL_PIN(32, "gpio32"), + PINCTRL_PIN(33, "gpio33"), + PINCTRL_PIN(34, "gpio34"), + PINCTRL_PIN(35, "gpio35"), + PINCTRL_PIN(36, "gpio36"), + PINCTRL_PIN(37, "gpio37"), + PINCTRL_PIN(38, "gpio38"), + PINCTRL_PIN(39, "gpio39"), + PINCTRL_PIN(40, "gpio40"), + PINCTRL_PIN(41, "gpio41"), + PINCTRL_PIN(42, "gpio42"), + PINCTRL_PIN(43, "gpio43"), + PINCTRL_PIN(44, "gpio44"), + PINCTRL_PIN(45, "gpio45"), + PINCTRL_PIN(46, "gpio46"), + PINCTRL_PIN(47, "gpio47"), + PINCTRL_PIN(48, "gpio48"), + PINCTRL_PIN(49, "gpio49"), +}; + +static unsigned gpio0_pins[] = { 0 }; +static unsigned gpio1_pins[] = { 1 }; +static unsigned gpio2_pins[] = { 2 }; +static unsigned gpio3_pins[] = { 3 }; +static unsigned gpio4_pins[] = { 4 }; +static unsigned gpio5_pins[] = { 5 }; +static unsigned gpio6_pins[] = { 6 }; +static unsigned gpio7_pins[] = { 7 }; +static unsigned gpio8_pins[] = { 8 }; +static unsigned gpio9_pins[] = { 9 }; +static unsigned gpio10_pins[] = { 10 }; +static unsigned gpio11_pins[] = { 11 }; +static unsigned gpio12_pins[] = { 12 }; +static unsigned gpio13_pins[] = { 13 }; +static unsigned gpio14_pins[] = { 14 }; +static unsigned gpio15_pins[] = { 15 }; +static unsigned gpio16_pins[] = { 16 }; +static unsigned gpio17_pins[] = { 17 }; +static unsigned gpio18_pins[] = { 18 }; +static unsigned gpio19_pins[] = { 19 }; +static unsigned gpio20_pins[] = { 20 }; +static unsigned gpio21_pins[] = { 21 }; +static unsigned gpio22_pins[] = { 22 }; +static unsigned gpio23_pins[] = { 23 }; +static unsigned gpio24_pins[] = { 24 }; +static unsigned gpio25_pins[] = { 25 }; +static unsigned gpio26_pins[] = { 26 }; +static unsigned gpio27_pins[] = { 27 }; +static unsigned gpio28_pins[] = { 28 }; +static unsigned gpio29_pins[] = { 29 }; +static unsigned gpio30_pins[] = { 30 }; +static unsigned gpio31_pins[] = { 31 }; +static unsigned gpio32_pins[] = { 32 }; +static unsigned gpio33_pins[] = { 33 }; +static unsigned gpio34_pins[] = { 34 }; +static unsigned gpio35_pins[] = { 35 }; +static unsigned gpio36_pins[] = { 36 }; +static unsigned gpio37_pins[] = { 37 }; +static unsigned gpio38_pins[] = { 38 }; +static unsigned gpio39_pins[] = { 39 }; +static unsigned gpio40_pins[] = { 40 }; +static unsigned gpio41_pins[] = { 41 }; +static unsigned gpio42_pins[] = { 42 }; +static unsigned gpio43_pins[] = { 43 }; +static unsigned gpio44_pins[] = { 44 }; +static unsigned gpio45_pins[] = { 45 }; +static unsigned gpio46_pins[] = { 46 }; +static unsigned gpio47_pins[] = { 47 }; +static unsigned gpio48_pins[] = { 48 }; +static unsigned gpio49_pins[] = { 49 }; + +#define BCM6318_GROUP(n) \ + { \ + .name = #n, \ + .pins = n##_pins, \ + .num_pins = ARRAY_SIZE(n##_pins), \ + } + +static struct bcm6318_pingroup bcm6318_groups[] = { + BCM6318_GROUP(gpio0), + BCM6318_GROUP(gpio1), + BCM6318_GROUP(gpio2), + BCM6318_GROUP(gpio3), + BCM6318_GROUP(gpio4), + BCM6318_GROUP(gpio5), + BCM6318_GROUP(gpio6), + BCM6318_GROUP(gpio7), + BCM6318_GROUP(gpio8), + BCM6318_GROUP(gpio9), + BCM6318_GROUP(gpio10), + BCM6318_GROUP(gpio11), + BCM6318_GROUP(gpio12), + BCM6318_GROUP(gpio13), + BCM6318_GROUP(gpio14), + BCM6318_GROUP(gpio15), + BCM6318_GROUP(gpio16), + BCM6318_GROUP(gpio17), + BCM6318_GROUP(gpio18), + BCM6318_GROUP(gpio19), + BCM6318_GROUP(gpio20), + BCM6318_GROUP(gpio21), + BCM6318_GROUP(gpio22), + BCM6318_GROUP(gpio23), + BCM6318_GROUP(gpio24), + BCM6318_GROUP(gpio25), + BCM6318_GROUP(gpio26), + BCM6318_GROUP(gpio27), + BCM6318_GROUP(gpio28), + BCM6318_GROUP(gpio29), + BCM6318_GROUP(gpio30), + BCM6318_GROUP(gpio31), + BCM6318_GROUP(gpio32), + BCM6318_GROUP(gpio33), + BCM6318_GROUP(gpio34), + BCM6318_GROUP(gpio35), + BCM6318_GROUP(gpio36), + BCM6318_GROUP(gpio37), + BCM6318_GROUP(gpio38), + BCM6318_GROUP(gpio39), + BCM6318_GROUP(gpio40), + BCM6318_GROUP(gpio41), + BCM6318_GROUP(gpio42), + BCM6318_GROUP(gpio43), + BCM6318_GROUP(gpio44), + BCM6318_GROUP(gpio45), + BCM6318_GROUP(gpio46), + BCM6318_GROUP(gpio47), + BCM6318_GROUP(gpio48), + BCM6318_GROUP(gpio49), +}; + +/* GPIO_MODE */ +static const char * const led_groups[] = { + "gpio0", + "gpio1", + "gpio2", + "gpio3", + "gpio4", + "gpio5", + "gpio6", + "gpio7", + "gpio8", + "gpio9", + "gpio10", + "gpio11", + "gpio12", + "gpio13", + "gpio14", + "gpio15", + "gpio16", + "gpio17", + "gpio18", + "gpio19", + "gpio20", + "gpio21", + "gpio22", + "gpio23", +}; + +/* PINMUX_SEL */ +static const char * const ephy0_spd_led_groups[] = { + "gpio0", +}; + +static const char * const ephy1_spd_led_groups[] = { + "gpio1", +}; + +static const char * const ephy2_spd_led_groups[] = { + "gpio2", +}; + +static const char * const ephy3_spd_led_groups[] = { + "gpio3", +}; + +static const char * const ephy0_act_led_groups[] = { + "gpio4", +}; + +static const char * const ephy1_act_led_groups[] = { + "gpio5", +}; + +static const char * const ephy2_act_led_groups[] = { + "gpio6", +}; + +static const char * const ephy3_act_led_groups[] = { + "gpio7", +}; + +static const char * const serial_led_data_groups[] = { + "gpio6", +}; + +static const char * const serial_led_clk_groups[] = { + "gpio7", +}; + +static const char * const inet_act_led_groups[] = { + "gpio8", +}; + +static const char * const inet_fail_led_groups[] = { + "gpio9", +}; + +static const char * const dsl_led_groups[] = { + "gpio10", +}; + +static const char * const post_fail_led_groups[] = { + "gpio11", +}; + +static const char * const wlan_wps_led_groups[] = { + "gpio12", +}; + +static const char * const usb_pwron_groups[] = { + "gpio13", +}; + +static const char * const usb_device_led_groups[] = { + "gpio13", +}; + +static const char * const usb_active_groups[] = { + "gpio40", +}; + +#define BCM6318_MODE_FUN(n) \ + { \ + .name = #n, \ + .groups = n##_groups, \ + .num_groups = ARRAY_SIZE(n##_groups), \ + .mode_val = 1, \ + } + +#define BCM6318_MUX_FUN(n, mux) \ + { \ + .name = #n, \ + .groups = n##_groups, \ + .num_groups = ARRAY_SIZE(n##_groups), \ + .mux_val = mux, \ + } + +static const struct bcm6318_function bcm6318_funcs[] = { + BCM6318_MODE_FUN(led), + BCM6318_MUX_FUN(ephy0_spd_led, 1), + BCM6318_MUX_FUN(ephy1_spd_led, 1), + BCM6318_MUX_FUN(ephy2_spd_led, 1), + BCM6318_MUX_FUN(ephy3_spd_led, 1), + BCM6318_MUX_FUN(ephy0_act_led, 1), + BCM6318_MUX_FUN(ephy1_act_led, 1), + BCM6318_MUX_FUN(ephy2_act_led, 1), + BCM6318_MUX_FUN(ephy3_act_led, 1), + BCM6318_MUX_FUN(serial_led_data, 3), + BCM6318_MUX_FUN(serial_led_clk, 3), + BCM6318_MUX_FUN(inet_act_led, 1), + BCM6318_MUX_FUN(inet_fail_led, 1), + BCM6318_MUX_FUN(dsl_led, 1), + BCM6318_MUX_FUN(post_fail_led, 1), + BCM6318_MUX_FUN(wlan_wps_led, 1), + BCM6318_MUX_FUN(usb_pwron, 1), + BCM6318_MUX_FUN(usb_device_led, 2), + BCM6318_MUX_FUN(usb_active, 2), +}; + +static inline unsigned int bcm6318_mux_off(unsigned int pin) +{ + return BCM6318_MUX_REG + (pin / 16) * 4; +} + +static inline unsigned int bcm6318_pad_off(unsigned int pin) +{ + return BCM6318_PAD_REG + (pin / 8) * 4; +} + +static int bcm6318_pinctrl_get_group_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(bcm6318_groups); +} + +static const char *bcm6318_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + return bcm6318_groups[group].name; +} + +static int bcm6318_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, const unsigned **pins, + unsigned *num_pins) +{ + *pins = bcm6318_groups[group].pins; + *num_pins = bcm6318_groups[group].num_pins; + + return 0; +} + +static int bcm6318_pinctrl_get_func_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(bcm6318_funcs); +} + +static const char *bcm6318_pinctrl_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return bcm6318_funcs[selector].name; +} + +static int bcm6318_pinctrl_get_groups(struct pinctrl_dev *pctldev, + unsigned selector, + const char * const **groups, + unsigned * const num_groups) +{ + *groups = bcm6318_funcs[selector].groups; + *num_groups = bcm6318_funcs[selector].num_groups; + + return 0; +} + +static inline void bcm6318_rmw_mux(struct bcm63xx_pinctrl *pc, unsigned pin, + unsigned int mode, unsigned int mux) +{ + if (pin < BCM63XX_BANK_GPIOS) + regmap_update_bits(pc->regs, BCM6318_MODE_REG, BIT(pin), + mode ? BIT(pin) : 0); + + if (pin < BCM6318_NUM_MUX) + regmap_update_bits(pc->regs, + bcm6318_mux_off(pin), + BCM6328_MUX_MASK << ((pin % 16) * 2), + mux << ((pin % 16) * 2)); +} + +static inline void bcm6318_set_pad(struct bcm63xx_pinctrl *pc, unsigned pin, + uint8_t val) +{ + regmap_update_bits(pc->regs, bcm6318_pad_off(pin), + BCM6328_PAD_MASK << ((pin % 8) * 4), + val << ((pin % 8) * 4)); +} + +static int bcm6318_pinctrl_set_mux(struct pinctrl_dev *pctldev, + unsigned selector, unsigned group) +{ + struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + const struct bcm6318_pingroup *pg = &bcm6318_groups[group]; + const struct bcm6318_function *f = &bcm6318_funcs[selector]; + + bcm6318_rmw_mux(pc, pg->pins[0], f->mode_val, f->mux_val); + + return 0; +} + +static int bcm6318_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + + /* disable all functions using this pin */ + if (offset < 13) { + /* GPIOs 0-12 use mux 0 as GPIO function */ + bcm6318_rmw_mux(pc, offset, 0, 0); + } else if (offset < 42) { + /* GPIOs 13-41 use mux 3 as GPIO function */ + bcm6318_rmw_mux(pc, offset, 0, 3); + + bcm6318_set_pad(pc, offset, 0); + } + + return 0; +} + +static struct pinctrl_ops bcm6318_pctl_ops = { + .dt_free_map = pinctrl_utils_free_map, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .get_group_name = bcm6318_pinctrl_get_group_name, + .get_group_pins = bcm6318_pinctrl_get_group_pins, + .get_groups_count = bcm6318_pinctrl_get_group_count, +}; + +static struct pinmux_ops bcm6318_pmx_ops = { + .get_function_groups = bcm6318_pinctrl_get_groups, + .get_function_name = bcm6318_pinctrl_get_func_name, + .get_functions_count = bcm6318_pinctrl_get_func_count, + .gpio_request_enable = bcm6318_gpio_request_enable, + .set_mux = bcm6318_pinctrl_set_mux, + .strict = true, +}; + +static const struct bcm63xx_pinctrl_soc bcm6318_soc = { + .ngpios = BCM6318_NUM_GPIOS, + .npins = ARRAY_SIZE(bcm6318_pins), + .pctl_ops = &bcm6318_pctl_ops, + .pins = bcm6318_pins, + .pmx_ops = &bcm6318_pmx_ops, +}; + +static int bcm6318_pinctrl_probe(struct platform_device *pdev) +{ + return bcm63xx_pinctrl_probe(pdev, &bcm6318_soc, NULL); +} + +static const struct of_device_id bcm6318_pinctrl_match[] = { + { .compatible = "brcm,bcm6318-pinctrl", }, + { /* sentinel */ } +}; + +static struct platform_driver bcm6318_pinctrl_driver = { + .probe = bcm6318_pinctrl_probe, + .driver = { + .name = "bcm6318-pinctrl", + .of_match_table = bcm6318_pinctrl_match, + }, +}; + +builtin_platform_driver(bcm6318_pinctrl_driver); diff --git a/drivers/pinctrl/bcm/pinctrl-bcm63268.c b/drivers/pinctrl/bcm/pinctrl-bcm63268.c new file mode 100644 index 000000000000..d4c5fad7fb7d --- /dev/null +++ b/drivers/pinctrl/bcm/pinctrl-bcm63268.c @@ -0,0 +1,643 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for BCM63268 GPIO unit (pinctrl + GPIO) + * + * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com> + * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com> + */ + +#include <linux/bits.h> +#include <linux/gpio/driver.h> +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include "../pinctrl-utils.h" + +#include "pinctrl-bcm63xx.h" + +#define BCM63268_NUM_GPIOS 52 +#define BCM63268_NUM_LEDS 24 + +#define BCM63268_LED_REG 0x10 +#define BCM63268_MODE_REG 0x18 +#define BCM63268_CTRL_REG 0x1c +#define BCM63268_BASEMODE_REG 0x38 +#define BCM63268_BASEMODE_NAND BIT(2) /* GPIOs 2-7, 24-31 */ +#define BCM63268_BASEMODE_GPIO35 BIT(4) /* GPIO 35 */ +#define BCM63268_BASEMODE_DECTPD BIT(5) /* GPIOs 8/9 */ +#define BCM63268_BASEMODE_VDSL_PHY_0 BIT(6) /* GPIOs 10/11 */ +#define BCM63268_BASEMODE_VDSL_PHY_1 BIT(7) /* GPIOs 12/13 */ +#define BCM63268_BASEMODE_VDSL_PHY_2 BIT(8) /* GPIOs 24/25 */ +#define BCM63268_BASEMODE_VDSL_PHY_3 BIT(9) /* GPIOs 26/27 */ + +enum bcm63268_pinctrl_reg { + BCM63268_LEDCTRL, + BCM63268_MODE, + BCM63268_CTRL, + BCM63268_BASEMODE, +}; + +struct bcm63268_pingroup { + const char *name; + const unsigned * const pins; + const unsigned num_pins; +}; + +struct bcm63268_function { + const char *name; + const char * const *groups; + const unsigned num_groups; + + enum bcm63268_pinctrl_reg reg; + uint32_t mask; +}; + +#define BCM63268_PIN(a, b, basemode) \ + { \ + .number = a, \ + .name = b, \ + .drv_data = (void *)(basemode) \ + } + +static const struct pinctrl_pin_desc bcm63268_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + BCM63268_PIN(2, "gpio2", BCM63268_BASEMODE_NAND), + BCM63268_PIN(3, "gpio3", BCM63268_BASEMODE_NAND), + BCM63268_PIN(4, "gpio4", BCM63268_BASEMODE_NAND), + BCM63268_PIN(5, "gpio5", BCM63268_BASEMODE_NAND), + BCM63268_PIN(6, "gpio6", BCM63268_BASEMODE_NAND), + BCM63268_PIN(7, "gpio7", BCM63268_BASEMODE_NAND), + BCM63268_PIN(8, "gpio8", BCM63268_BASEMODE_DECTPD), + BCM63268_PIN(9, "gpio9", BCM63268_BASEMODE_DECTPD), + BCM63268_PIN(10, "gpio10", BCM63268_BASEMODE_VDSL_PHY_0), + BCM63268_PIN(11, "gpio11", BCM63268_BASEMODE_VDSL_PHY_0), + BCM63268_PIN(12, "gpio12", BCM63268_BASEMODE_VDSL_PHY_1), + BCM63268_PIN(13, "gpio13", BCM63268_BASEMODE_VDSL_PHY_1), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), + PINCTRL_PIN(23, "gpio23"), + BCM63268_PIN(24, "gpio24", + BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_2), + BCM63268_PIN(25, "gpio25", + BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_2), + BCM63268_PIN(26, "gpio26", + BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_3), + BCM63268_PIN(27, "gpio27", + BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_3), + BCM63268_PIN(28, "gpio28", BCM63268_BASEMODE_NAND), + BCM63268_PIN(29, "gpio29", BCM63268_BASEMODE_NAND), + BCM63268_PIN(30, "gpio30", BCM63268_BASEMODE_NAND), + BCM63268_PIN(31, "gpio31", BCM63268_BASEMODE_NAND), + PINCTRL_PIN(32, "gpio32"), + PINCTRL_PIN(33, "gpio33"), + PINCTRL_PIN(34, "gpio34"), + PINCTRL_PIN(35, "gpio35"), + PINCTRL_PIN(36, "gpio36"), + PINCTRL_PIN(37, "gpio37"), + PINCTRL_PIN(38, "gpio38"), + PINCTRL_PIN(39, "gpio39"), + PINCTRL_PIN(40, "gpio40"), + PINCTRL_PIN(41, "gpio41"), + PINCTRL_PIN(42, "gpio42"), + PINCTRL_PIN(43, "gpio43"), + PINCTRL_PIN(44, "gpio44"), + PINCTRL_PIN(45, "gpio45"), + PINCTRL_PIN(46, "gpio46"), + PINCTRL_PIN(47, "gpio47"), + PINCTRL_PIN(48, "gpio48"), + PINCTRL_PIN(49, "gpio49"), + PINCTRL_PIN(50, "gpio50"), + PINCTRL_PIN(51, "gpio51"), +}; + +static unsigned gpio0_pins[] = { 0 }; +static unsigned gpio1_pins[] = { 1 }; +static unsigned gpio2_pins[] = { 2 }; +static unsigned gpio3_pins[] = { 3 }; +static unsigned gpio4_pins[] = { 4 }; +static unsigned gpio5_pins[] = { 5 }; +static unsigned gpio6_pins[] = { 6 }; +static unsigned gpio7_pins[] = { 7 }; +static unsigned gpio8_pins[] = { 8 }; +static unsigned gpio9_pins[] = { 9 }; +static unsigned gpio10_pins[] = { 10 }; +static unsigned gpio11_pins[] = { 11 }; +static unsigned gpio12_pins[] = { 12 }; +static unsigned gpio13_pins[] = { 13 }; +static unsigned gpio14_pins[] = { 14 }; +static unsigned gpio15_pins[] = { 15 }; +static unsigned gpio16_pins[] = { 16 }; +static unsigned gpio17_pins[] = { 17 }; +static unsigned gpio18_pins[] = { 18 }; +static unsigned gpio19_pins[] = { 19 }; +static unsigned gpio20_pins[] = { 20 }; +static unsigned gpio21_pins[] = { 21 }; +static unsigned gpio22_pins[] = { 22 }; +static unsigned gpio23_pins[] = { 23 }; +static unsigned gpio24_pins[] = { 24 }; +static unsigned gpio25_pins[] = { 25 }; +static unsigned gpio26_pins[] = { 26 }; +static unsigned gpio27_pins[] = { 27 }; +static unsigned gpio28_pins[] = { 28 }; +static unsigned gpio29_pins[] = { 29 }; +static unsigned gpio30_pins[] = { 30 }; +static unsigned gpio31_pins[] = { 31 }; +static unsigned gpio32_pins[] = { 32 }; +static unsigned gpio33_pins[] = { 33 }; +static unsigned gpio34_pins[] = { 34 }; +static unsigned gpio35_pins[] = { 35 }; +static unsigned gpio36_pins[] = { 36 }; +static unsigned gpio37_pins[] = { 37 }; +static unsigned gpio38_pins[] = { 38 }; +static unsigned gpio39_pins[] = { 39 }; +static unsigned gpio40_pins[] = { 40 }; +static unsigned gpio41_pins[] = { 41 }; +static unsigned gpio42_pins[] = { 42 }; +static unsigned gpio43_pins[] = { 43 }; +static unsigned gpio44_pins[] = { 44 }; +static unsigned gpio45_pins[] = { 45 }; +static unsigned gpio46_pins[] = { 46 }; +static unsigned gpio47_pins[] = { 47 }; +static unsigned gpio48_pins[] = { 48 }; +static unsigned gpio49_pins[] = { 49 }; +static unsigned gpio50_pins[] = { 50 }; +static unsigned gpio51_pins[] = { 51 }; + +static unsigned nand_grp_pins[] = { + 2, 3, 4, 5, 6, 7, 24, + 25, 26, 27, 28, 29, 30, 31, +}; + +static unsigned dectpd_grp_pins[] = { 8, 9 }; +static unsigned vdsl_phy0_grp_pins[] = { 10, 11 }; +static unsigned vdsl_phy1_grp_pins[] = { 12, 13 }; +static unsigned vdsl_phy2_grp_pins[] = { 24, 25 }; +static unsigned vdsl_phy3_grp_pins[] = { 26, 27 }; + +#define BCM63268_GROUP(n) \ + { \ + .name = #n, \ + .pins = n##_pins, \ + .num_pins = ARRAY_SIZE(n##_pins), \ + } + +static struct bcm63268_pingroup bcm63268_groups[] = { + BCM63268_GROUP(gpio0), + BCM63268_GROUP(gpio1), + BCM63268_GROUP(gpio2), + BCM63268_GROUP(gpio3), + BCM63268_GROUP(gpio4), + BCM63268_GROUP(gpio5), + BCM63268_GROUP(gpio6), + BCM63268_GROUP(gpio7), + BCM63268_GROUP(gpio8), + BCM63268_GROUP(gpio9), + BCM63268_GROUP(gpio10), + BCM63268_GROUP(gpio11), + BCM63268_GROUP(gpio12), + BCM63268_GROUP(gpio13), + BCM63268_GROUP(gpio14), + BCM63268_GROUP(gpio15), + BCM63268_GROUP(gpio16), + BCM63268_GROUP(gpio17), + BCM63268_GROUP(gpio18), + BCM63268_GROUP(gpio19), + BCM63268_GROUP(gpio20), + BCM63268_GROUP(gpio21), + BCM63268_GROUP(gpio22), + BCM63268_GROUP(gpio23), + BCM63268_GROUP(gpio24), + BCM63268_GROUP(gpio25), + BCM63268_GROUP(gpio26), + BCM63268_GROUP(gpio27), + BCM63268_GROUP(gpio28), + BCM63268_GROUP(gpio29), + BCM63268_GROUP(gpio30), + BCM63268_GROUP(gpio31), + BCM63268_GROUP(gpio32), + BCM63268_GROUP(gpio33), + BCM63268_GROUP(gpio34), + BCM63268_GROUP(gpio35), + BCM63268_GROUP(gpio36), + BCM63268_GROUP(gpio37), + BCM63268_GROUP(gpio38), + BCM63268_GROUP(gpio39), + BCM63268_GROUP(gpio40), + BCM63268_GROUP(gpio41), + BCM63268_GROUP(gpio42), + BCM63268_GROUP(gpio43), + BCM63268_GROUP(gpio44), + BCM63268_GROUP(gpio45), + BCM63268_GROUP(gpio46), + BCM63268_GROUP(gpio47), + BCM63268_GROUP(gpio48), + BCM63268_GROUP(gpio49), + BCM63268_GROUP(gpio50), + BCM63268_GROUP(gpio51), + + /* multi pin groups */ + BCM63268_GROUP(nand_grp), + BCM63268_GROUP(dectpd_grp), + BCM63268_GROUP(vdsl_phy0_grp), + BCM63268_GROUP(vdsl_phy1_grp), + BCM63268_GROUP(vdsl_phy2_grp), + BCM63268_GROUP(vdsl_phy3_grp), +}; + +static const char * const led_groups[] = { + "gpio0", + "gpio1", + "gpio2", + "gpio3", + "gpio4", + "gpio5", + "gpio6", + "gpio7", + "gpio8", + "gpio9", + "gpio10", + "gpio11", + "gpio12", + "gpio13", + "gpio14", + "gpio15", + "gpio16", + "gpio17", + "gpio18", + "gpio19", + "gpio20", + "gpio21", + "gpio22", + "gpio23", +}; + +static const char * const serial_led_clk_groups[] = { + "gpio0", +}; + +static const char * const serial_led_data_groups[] = { + "gpio1", +}; + +static const char * const hsspi_cs4_groups[] = { + "gpio16", +}; + +static const char * const hsspi_cs5_groups[] = { + "gpio17", +}; + +static const char * const hsspi_cs6_groups[] = { + "gpio8", +}; + +static const char * const hsspi_cs7_groups[] = { + "gpio9", +}; + +static const char * const uart1_scts_groups[] = { + "gpio10", + "gpio24", +}; + +static const char * const uart1_srts_groups[] = { + "gpio11", + "gpio25", +}; + +static const char * const uart1_sdin_groups[] = { + "gpio12", + "gpio26", +}; + +static const char * const uart1_sdout_groups[] = { + "gpio13", + "gpio27", +}; + +static const char * const ntr_pulse_in_groups[] = { + "gpio14", + "gpio28", +}; + +static const char * const dsl_ntr_pulse_out_groups[] = { + "gpio15", + "gpio29", +}; + +static const char * const adsl_spi_miso_groups[] = { + "gpio18", +}; + +static const char * const adsl_spi_mosi_groups[] = { + "gpio19", +}; + +static const char * const vreg_clk_groups[] = { + "gpio22", +}; + +static const char * const pcie_clkreq_b_groups[] = { + "gpio23", +}; + +static const char * const switch_led_clk_groups[] = { + "gpio30", +}; + +static const char * const switch_led_data_groups[] = { + "gpio31", +}; + +static const char * const wifi_groups[] = { + "gpio32", + "gpio33", + "gpio34", + "gpio35", + "gpio36", + "gpio37", + "gpio38", + "gpio39", + "gpio40", + "gpio41", + "gpio42", + "gpio43", + "gpio44", + "gpio45", + "gpio46", + "gpio47", + "gpio48", + "gpio49", + "gpio50", + "gpio51", +}; + +static const char * const nand_groups[] = { + "nand_grp", +}; + +static const char * const dectpd_groups[] = { + "dectpd_grp", +}; + +static const char * const vdsl_phy_override_0_groups[] = { + "vdsl_phy_override_0_grp", +}; + +static const char * const vdsl_phy_override_1_groups[] = { + "vdsl_phy_override_1_grp", +}; + +static const char * const vdsl_phy_override_2_groups[] = { + "vdsl_phy_override_2_grp", +}; + +static const char * const vdsl_phy_override_3_groups[] = { + "vdsl_phy_override_3_grp", +}; + +#define BCM63268_LED_FUN(n) \ + { \ + .name = #n, \ + .groups = n##_groups, \ + .num_groups = ARRAY_SIZE(n##_groups), \ + .reg = BCM63268_LEDCTRL, \ + } + +#define BCM63268_MODE_FUN(n) \ + { \ + .name = #n, \ + .groups = n##_groups, \ + .num_groups = ARRAY_SIZE(n##_groups), \ + .reg = BCM63268_MODE, \ + } + +#define BCM63268_CTRL_FUN(n) \ + { \ + .name = #n, \ + .groups = n##_groups, \ + .num_groups = ARRAY_SIZE(n##_groups), \ + .reg = BCM63268_CTRL, \ + } + +#define BCM63268_BASEMODE_FUN(n, val) \ + { \ + .name = #n, \ + .groups = n##_groups, \ + .num_groups = ARRAY_SIZE(n##_groups), \ + .reg = BCM63268_BASEMODE, \ + .mask = val, \ + } + +static const struct bcm63268_function bcm63268_funcs[] = { + BCM63268_LED_FUN(led), + BCM63268_MODE_FUN(serial_led_clk), + BCM63268_MODE_FUN(serial_led_data), + BCM63268_MODE_FUN(hsspi_cs6), + BCM63268_MODE_FUN(hsspi_cs7), + BCM63268_MODE_FUN(uart1_scts), + BCM63268_MODE_FUN(uart1_srts), + BCM63268_MODE_FUN(uart1_sdin), + BCM63268_MODE_FUN(uart1_sdout), + BCM63268_MODE_FUN(ntr_pulse_in), + BCM63268_MODE_FUN(dsl_ntr_pulse_out), + BCM63268_MODE_FUN(hsspi_cs4), + BCM63268_MODE_FUN(hsspi_cs5), + BCM63268_MODE_FUN(adsl_spi_miso), + BCM63268_MODE_FUN(adsl_spi_mosi), + BCM63268_MODE_FUN(vreg_clk), + BCM63268_MODE_FUN(pcie_clkreq_b), + BCM63268_MODE_FUN(switch_led_clk), + BCM63268_MODE_FUN(switch_led_data), + BCM63268_CTRL_FUN(wifi), + BCM63268_BASEMODE_FUN(nand, BCM63268_BASEMODE_NAND), + BCM63268_BASEMODE_FUN(dectpd, BCM63268_BASEMODE_DECTPD), + BCM63268_BASEMODE_FUN(vdsl_phy_override_0, + BCM63268_BASEMODE_VDSL_PHY_0), + BCM63268_BASEMODE_FUN(vdsl_phy_override_1, + BCM63268_BASEMODE_VDSL_PHY_1), + BCM63268_BASEMODE_FUN(vdsl_phy_override_2, + BCM63268_BASEMODE_VDSL_PHY_2), + BCM63268_BASEMODE_FUN(vdsl_phy_override_3, + BCM63268_BASEMODE_VDSL_PHY_3), +}; + +static int bcm63268_pinctrl_get_group_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(bcm63268_groups); +} + +static const char *bcm63268_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + return bcm63268_groups[group].name; +} + +static int bcm63268_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + *pins = bcm63268_groups[group].pins; + *num_pins = bcm63268_groups[group].num_pins; + + return 0; +} + +static int bcm63268_pinctrl_get_func_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(bcm63268_funcs); +} + +static const char *bcm63268_pinctrl_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return bcm63268_funcs[selector].name; +} + +static int bcm63268_pinctrl_get_groups(struct pinctrl_dev *pctldev, + unsigned selector, + const char * const **groups, + unsigned * const num_groups) +{ + *groups = bcm63268_funcs[selector].groups; + *num_groups = bcm63268_funcs[selector].num_groups; + + return 0; +} + +static void bcm63268_set_gpio(struct bcm63xx_pinctrl *pc, unsigned pin) +{ + const struct pinctrl_pin_desc *desc = &bcm63268_pins[pin]; + unsigned int basemode = (unsigned long) desc->drv_data; + unsigned int mask = BIT(bcm63xx_bank_pin(pin)); + + if (basemode) + regmap_update_bits(pc->regs, BCM63268_BASEMODE_REG, basemode, + 0); + + if (pin < BCM63XX_BANK_GPIOS) { + /* base mode: 0 => gpio, 1 => mux function */ + regmap_update_bits(pc->regs, BCM63268_MODE_REG, mask, 0); + + /* pins 0-23 might be muxed to led */ + if (pin < BCM63268_NUM_LEDS) + regmap_update_bits(pc->regs, BCM63268_LED_REG, mask, + 0); + } else if (pin < BCM63268_NUM_GPIOS) { + /* ctrl reg: 0 => wifi function, 1 => gpio */ + regmap_update_bits(pc->regs, BCM63268_CTRL_REG, mask, mask); + } +} + +static int bcm63268_pinctrl_set_mux(struct pinctrl_dev *pctldev, + unsigned selector, unsigned group) +{ + struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + const struct bcm63268_pingroup *pg = &bcm63268_groups[group]; + const struct bcm63268_function *f = &bcm63268_funcs[selector]; + unsigned i; + unsigned int reg; + unsigned int val, mask; + + for (i = 0; i < pg->num_pins; i++) + bcm63268_set_gpio(pc, pg->pins[i]); + + switch (f->reg) { + case BCM63268_LEDCTRL: + reg = BCM63268_LED_REG; + mask = BIT(pg->pins[0]); + val = BIT(pg->pins[0]); + break; + case BCM63268_MODE: + reg = BCM63268_MODE_REG; + mask = BIT(pg->pins[0]); + val = BIT(pg->pins[0]); + break; + case BCM63268_CTRL: + reg = BCM63268_CTRL_REG; + mask = BIT(pg->pins[0]); + val = 0; + break; + case BCM63268_BASEMODE: + reg = BCM63268_BASEMODE_REG; + mask = f->mask; + val = f->mask; + break; + default: + WARN_ON(1); + return -EINVAL; + } + + regmap_update_bits(pc->regs, reg, mask, val); + + return 0; +} + +static int bcm63268_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + + /* disable all functions using this pin */ + bcm63268_set_gpio(pc, offset); + + return 0; +} + +static struct pinctrl_ops bcm63268_pctl_ops = { + .dt_free_map = pinctrl_utils_free_map, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .get_group_name = bcm63268_pinctrl_get_group_name, + .get_group_pins = bcm63268_pinctrl_get_group_pins, + .get_groups_count = bcm63268_pinctrl_get_group_count, +}; + +static struct pinmux_ops bcm63268_pmx_ops = { + .get_function_groups = bcm63268_pinctrl_get_groups, + .get_function_name = bcm63268_pinctrl_get_func_name, + .get_functions_count = bcm63268_pinctrl_get_func_count, + .gpio_request_enable = bcm63268_gpio_request_enable, + .set_mux = bcm63268_pinctrl_set_mux, + .strict = true, +}; + +static const struct bcm63xx_pinctrl_soc bcm63268_soc = { + .ngpios = BCM63268_NUM_GPIOS, + .npins = ARRAY_SIZE(bcm63268_pins), + .pctl_ops = &bcm63268_pctl_ops, + .pins = bcm63268_pins, + .pmx_ops = &bcm63268_pmx_ops, +}; + +static int bcm63268_pinctrl_probe(struct platform_device *pdev) +{ + return bcm63xx_pinctrl_probe(pdev, &bcm63268_soc, NULL); +} + +static const struct of_device_id bcm63268_pinctrl_match[] = { + { .compatible = "brcm,bcm63268-pinctrl", }, + { /* sentinel */ } +}; + +static struct platform_driver bcm63268_pinctrl_driver = { + .probe = bcm63268_pinctrl_probe, + .driver = { + .name = "bcm63268-pinctrl", + .of_match_table = bcm63268_pinctrl_match, + }, +}; + +builtin_platform_driver(bcm63268_pinctrl_driver); diff --git a/drivers/pinctrl/bcm/pinctrl-bcm6328.c b/drivers/pinctrl/bcm/pinctrl-bcm6328.c new file mode 100644 index 000000000000..c9efce600550 --- /dev/null +++ b/drivers/pinctrl/bcm/pinctrl-bcm6328.c @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for BCM6328 GPIO unit (pinctrl + GPIO) + * + * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com> + * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com> + */ + +#include <linux/bits.h> +#include <linux/gpio/driver.h> +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include "../pinctrl-utils.h" + +#include "pinctrl-bcm63xx.h" + +#define BCM6328_NUM_GPIOS 32 + +#define BCM6328_MODE_REG 0x18 +#define BCM6328_MUX_HI_REG 0x1c +#define BCM6328_MUX_LO_REG 0x20 +#define BCM6328_MUX_OTHER_REG 0x24 +#define BCM6328_MUX_MASK GENMASK(1, 0) + +struct bcm6328_pingroup { + const char *name; + const unsigned * const pins; + const unsigned num_pins; +}; + +struct bcm6328_function { + const char *name; + const char * const *groups; + const unsigned num_groups; + + unsigned mode_val:1; + unsigned mux_val:2; +}; + +static const unsigned int bcm6328_mux[] = { + BCM6328_MUX_LO_REG, + BCM6328_MUX_HI_REG, + BCM6328_MUX_OTHER_REG +}; + +static const struct pinctrl_pin_desc bcm6328_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), + PINCTRL_PIN(23, "gpio23"), + PINCTRL_PIN(24, "gpio24"), + PINCTRL_PIN(25, "gpio25"), + PINCTRL_PIN(26, "gpio26"), + PINCTRL_PIN(27, "gpio27"), + PINCTRL_PIN(28, "gpio28"), + PINCTRL_PIN(29, "gpio29"), + PINCTRL_PIN(30, "gpio30"), + PINCTRL_PIN(31, "gpio31"), + + /* + * No idea where they really are; so let's put them according + * to their mux offsets. + */ + PINCTRL_PIN(36, "hsspi_cs1"), + PINCTRL_PIN(38, "usb_p2"), +}; + +static unsigned gpio0_pins[] = { 0 }; +static unsigned gpio1_pins[] = { 1 }; +static unsigned gpio2_pins[] = { 2 }; +static unsigned gpio3_pins[] = { 3 }; +static unsigned gpio4_pins[] = { 4 }; +static unsigned gpio5_pins[] = { 5 }; +static unsigned gpio6_pins[] = { 6 }; +static unsigned gpio7_pins[] = { 7 }; +static unsigned gpio8_pins[] = { 8 }; +static unsigned gpio9_pins[] = { 9 }; +static unsigned gpio10_pins[] = { 10 }; +static unsigned gpio11_pins[] = { 11 }; +static unsigned gpio12_pins[] = { 12 }; +static unsigned gpio13_pins[] = { 13 }; +static unsigned gpio14_pins[] = { 14 }; +static unsigned gpio15_pins[] = { 15 }; +static unsigned gpio16_pins[] = { 16 }; +static unsigned gpio17_pins[] = { 17 }; +static unsigned gpio18_pins[] = { 18 }; +static unsigned gpio19_pins[] = { 19 }; +static unsigned gpio20_pins[] = { 20 }; +static unsigned gpio21_pins[] = { 21 }; +static unsigned gpio22_pins[] = { 22 }; +static unsigned gpio23_pins[] = { 23 }; +static unsigned gpio24_pins[] = { 24 }; +static unsigned gpio25_pins[] = { 25 }; +static unsigned gpio26_pins[] = { 26 }; +static unsigned gpio27_pins[] = { 27 }; +static unsigned gpio28_pins[] = { 28 }; +static unsigned gpio29_pins[] = { 29 }; +static unsigned gpio30_pins[] = { 30 }; +static unsigned gpio31_pins[] = { 31 }; + +static unsigned hsspi_cs1_pins[] = { 36 }; +static unsigned usb_port1_pins[] = { 38 }; + +#define BCM6328_GROUP(n) \ + { \ + .name = #n, \ + .pins = n##_pins, \ + .num_pins = ARRAY_SIZE(n##_pins), \ + } + +static struct bcm6328_pingroup bcm6328_groups[] = { + BCM6328_GROUP(gpio0), + BCM6328_GROUP(gpio1), + BCM6328_GROUP(gpio2), + BCM6328_GROUP(gpio3), + BCM6328_GROUP(gpio4), + BCM6328_GROUP(gpio5), + BCM6328_GROUP(gpio6), + BCM6328_GROUP(gpio7), + BCM6328_GROUP(gpio8), + BCM6328_GROUP(gpio9), + BCM6328_GROUP(gpio10), + BCM6328_GROUP(gpio11), + BCM6328_GROUP(gpio12), + BCM6328_GROUP(gpio13), + BCM6328_GROUP(gpio14), + BCM6328_GROUP(gpio15), + BCM6328_GROUP(gpio16), + BCM6328_GROUP(gpio17), + BCM6328_GROUP(gpio18), + BCM6328_GROUP(gpio19), + BCM6328_GROUP(gpio20), + BCM6328_GROUP(gpio21), + BCM6328_GROUP(gpio22), + BCM6328_GROUP(gpio23), + BCM6328_GROUP(gpio24), + BCM6328_GROUP(gpio25), + BCM6328_GROUP(gpio26), + BCM6328_GROUP(gpio27), + BCM6328_GROUP(gpio28), + BCM6328_GROUP(gpio29), + BCM6328_GROUP(gpio30), + BCM6328_GROUP(gpio31), + + BCM6328_GROUP(hsspi_cs1), + BCM6328_GROUP(usb_port1), +}; + +/* GPIO_MODE */ +static const char * const led_groups[] = { + "gpio0", + "gpio1", + "gpio2", + "gpio3", + "gpio4", + "gpio5", + "gpio6", + "gpio7", + "gpio8", + "gpio9", + "gpio10", + "gpio11", + "gpio12", + "gpio13", + "gpio14", + "gpio15", + "gpio16", + "gpio17", + "gpio18", + "gpio19", + "gpio20", + "gpio21", + "gpio22", + "gpio23", +}; + +/* PINMUX_SEL */ +static const char * const serial_led_data_groups[] = { + "gpio6", +}; + +static const char * const serial_led_clk_groups[] = { + "gpio7", +}; + +static const char * const inet_act_led_groups[] = { + "gpio11", +}; + +static const char * const pcie_clkreq_groups[] = { + "gpio16", +}; + +static const char * const ephy0_act_led_groups[] = { + "gpio25", +}; + +static const char * const ephy1_act_led_groups[] = { + "gpio26", +}; + +static const char * const ephy2_act_led_groups[] = { + "gpio27", +}; + +static const char * const ephy3_act_led_groups[] = { + "gpio28", +}; + +static const char * const hsspi_cs1_groups[] = { + "hsspi_cs1" +}; + +static const char * const usb_host_port_groups[] = { + "usb_port1", +}; + +static const char * const usb_device_port_groups[] = { + "usb_port1", +}; + +#define BCM6328_MODE_FUN(n) \ + { \ + .name = #n, \ + .groups = n##_groups, \ + .num_groups = ARRAY_SIZE(n##_groups), \ + .mode_val = 1, \ + } + +#define BCM6328_MUX_FUN(n, mux) \ + { \ + .name = #n, \ + .groups = n##_groups, \ + .num_groups = ARRAY_SIZE(n##_groups), \ + .mux_val = mux, \ + } + +static const struct bcm6328_function bcm6328_funcs[] = { + BCM6328_MODE_FUN(led), + BCM6328_MUX_FUN(serial_led_data, 2), + BCM6328_MUX_FUN(serial_led_clk, 2), + BCM6328_MUX_FUN(inet_act_led, 1), + BCM6328_MUX_FUN(pcie_clkreq, 2), + BCM6328_MUX_FUN(ephy0_act_led, 1), + BCM6328_MUX_FUN(ephy1_act_led, 1), + BCM6328_MUX_FUN(ephy2_act_led, 1), + BCM6328_MUX_FUN(ephy3_act_led, 1), + BCM6328_MUX_FUN(hsspi_cs1, 2), + BCM6328_MUX_FUN(usb_host_port, 1), + BCM6328_MUX_FUN(usb_device_port, 2), +}; + +static inline unsigned int bcm6328_mux_off(unsigned int pin) +{ + return bcm6328_mux[pin / 16]; +} + +static int bcm6328_pinctrl_get_group_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(bcm6328_groups); +} + +static const char *bcm6328_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + return bcm6328_groups[group].name; +} + +static int bcm6328_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, const unsigned **pins, + unsigned *num_pins) +{ + *pins = bcm6328_groups[group].pins; + *num_pins = bcm6328_groups[group].num_pins; + + return 0; +} + +static int bcm6328_pinctrl_get_func_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(bcm6328_funcs); +} + +static const char *bcm6328_pinctrl_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return bcm6328_funcs[selector].name; +} + +static int bcm6328_pinctrl_get_groups(struct pinctrl_dev *pctldev, + unsigned selector, + const char * const **groups, + unsigned * const num_groups) +{ + *groups = bcm6328_funcs[selector].groups; + *num_groups = bcm6328_funcs[selector].num_groups; + + return 0; +} + +static void bcm6328_rmw_mux(struct bcm63xx_pinctrl *pc, unsigned pin, + unsigned int mode, unsigned int mux) +{ + if (pin < BCM6328_NUM_GPIOS) + regmap_update_bits(pc->regs, BCM6328_MODE_REG, BIT(pin), + mode ? BIT(pin) : 0); + + regmap_update_bits(pc->regs, bcm6328_mux_off(pin), + BCM6328_MUX_MASK << ((pin % 16) * 2), + mux << ((pin % 16) * 2)); +} + +static int bcm6328_pinctrl_set_mux(struct pinctrl_dev *pctldev, + unsigned selector, unsigned group) +{ + struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + const struct bcm6328_pingroup *pg = &bcm6328_groups[group]; + const struct bcm6328_function *f = &bcm6328_funcs[selector]; + + bcm6328_rmw_mux(pc, pg->pins[0], f->mode_val, f->mux_val); + + return 0; +} + +static int bcm6328_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + + /* disable all functions using this pin */ + bcm6328_rmw_mux(pc, offset, 0, 0); + + return 0; +} + +static struct pinctrl_ops bcm6328_pctl_ops = { + .dt_free_map = pinctrl_utils_free_map, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .get_group_name = bcm6328_pinctrl_get_group_name, + .get_group_pins = bcm6328_pinctrl_get_group_pins, + .get_groups_count = bcm6328_pinctrl_get_group_count, +}; + +static struct pinmux_ops bcm6328_pmx_ops = { + .get_function_groups = bcm6328_pinctrl_get_groups, + .get_function_name = bcm6328_pinctrl_get_func_name, + .get_functions_count = bcm6328_pinctrl_get_func_count, + .gpio_request_enable = bcm6328_gpio_request_enable, + .set_mux = bcm6328_pinctrl_set_mux, + .strict = true, +}; + +static const struct bcm63xx_pinctrl_soc bcm6328_soc = { + .ngpios = BCM6328_NUM_GPIOS, + .npins = ARRAY_SIZE(bcm6328_pins), + .pctl_ops = &bcm6328_pctl_ops, + .pins = bcm6328_pins, + .pmx_ops = &bcm6328_pmx_ops, +}; + +static int bcm6328_pinctrl_probe(struct platform_device *pdev) +{ + return bcm63xx_pinctrl_probe(pdev, &bcm6328_soc, NULL); +} + +static const struct of_device_id bcm6328_pinctrl_match[] = { + { .compatible = "brcm,bcm6328-pinctrl", }, + { /* sentinel */ } +}; + +static struct platform_driver bcm6328_pinctrl_driver = { + .probe = bcm6328_pinctrl_probe, + .driver = { + .name = "bcm6328-pinctrl", + .of_match_table = bcm6328_pinctrl_match, + }, +}; + +builtin_platform_driver(bcm6328_pinctrl_driver); diff --git a/drivers/pinctrl/bcm/pinctrl-bcm6358.c b/drivers/pinctrl/bcm/pinctrl-bcm6358.c new file mode 100644 index 000000000000..d638578727f3 --- /dev/null +++ b/drivers/pinctrl/bcm/pinctrl-bcm6358.c @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for BCM6358 GPIO unit (pinctrl + GPIO) + * + * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com> + * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com> + */ + +#include <linux/bits.h> +#include <linux/gpio/driver.h> +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include "../pinctrl-utils.h" + +#include "pinctrl-bcm63xx.h" + +#define BCM6358_NUM_GPIOS 40 + +#define BCM6358_MODE_REG 0x18 +#define BCM6358_MODE_MUX_NONE 0 +#define BCM6358_MODE_MUX_EBI_CS BIT(5) +#define BCM6358_MODE_MUX_UART1 BIT(6) +#define BCM6358_MODE_MUX_SPI_CS BIT(7) +#define BCM6358_MODE_MUX_ASYNC_MODEM BIT(8) +#define BCM6358_MODE_MUX_LEGACY_LED BIT(9) +#define BCM6358_MODE_MUX_SERIAL_LED BIT(10) +#define BCM6358_MODE_MUX_LED BIT(11) +#define BCM6358_MODE_MUX_UTOPIA BIT(12) +#define BCM6358_MODE_MUX_CLKRST BIT(13) +#define BCM6358_MODE_MUX_PWM_SYN_CLK BIT(14) +#define BCM6358_MODE_MUX_SYS_IRQ BIT(15) + +struct bcm6358_pingroup { + const char *name; + const unsigned * const pins; + const unsigned num_pins; + + const uint16_t mode_val; + + /* non-GPIO function muxes require the gpio direction to be set */ + const uint16_t direction; +}; + +struct bcm6358_function { + const char *name; + const char * const *groups; + const unsigned num_groups; +}; + +struct bcm6358_priv { + struct regmap_field *overlays; +}; + +#define BCM6358_GPIO_PIN(a, b, bit1, bit2, bit3) \ + { \ + .number = a, \ + .name = b, \ + .drv_data = (void *)(BCM6358_MODE_MUX_##bit1 | \ + BCM6358_MODE_MUX_##bit2 | \ + BCM6358_MODE_MUX_##bit3), \ + } + +static const struct pinctrl_pin_desc bcm6358_pins[] = { + BCM6358_GPIO_PIN(0, "gpio0", LED, NONE, NONE), + BCM6358_GPIO_PIN(1, "gpio1", LED, NONE, NONE), + BCM6358_GPIO_PIN(2, "gpio2", LED, NONE, NONE), + BCM6358_GPIO_PIN(3, "gpio3", LED, NONE, NONE), + PINCTRL_PIN(4, "gpio4"), + BCM6358_GPIO_PIN(5, "gpio5", SYS_IRQ, NONE, NONE), + BCM6358_GPIO_PIN(6, "gpio6", SERIAL_LED, NONE, NONE), + BCM6358_GPIO_PIN(7, "gpio7", SERIAL_LED, NONE, NONE), + BCM6358_GPIO_PIN(8, "gpio8", PWM_SYN_CLK, NONE, NONE), + BCM6358_GPIO_PIN(9, "gpio09", LEGACY_LED, NONE, NONE), + BCM6358_GPIO_PIN(10, "gpio10", LEGACY_LED, NONE, NONE), + BCM6358_GPIO_PIN(11, "gpio11", LEGACY_LED, NONE, NONE), + BCM6358_GPIO_PIN(12, "gpio12", LEGACY_LED, ASYNC_MODEM, UTOPIA), + BCM6358_GPIO_PIN(13, "gpio13", LEGACY_LED, ASYNC_MODEM, UTOPIA), + BCM6358_GPIO_PIN(14, "gpio14", LEGACY_LED, ASYNC_MODEM, UTOPIA), + BCM6358_GPIO_PIN(15, "gpio15", LEGACY_LED, ASYNC_MODEM, UTOPIA), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + BCM6358_GPIO_PIN(22, "gpio22", UTOPIA, NONE, NONE), + BCM6358_GPIO_PIN(23, "gpio23", UTOPIA, NONE, NONE), + BCM6358_GPIO_PIN(24, "gpio24", UTOPIA, NONE, NONE), + BCM6358_GPIO_PIN(25, "gpio25", UTOPIA, NONE, NONE), + BCM6358_GPIO_PIN(26, "gpio26", UTOPIA, NONE, NONE), + BCM6358_GPIO_PIN(27, "gpio27", UTOPIA, NONE, NONE), + BCM6358_GPIO_PIN(28, "gpio28", UTOPIA, UART1, NONE), + BCM6358_GPIO_PIN(29, "gpio29", UTOPIA, UART1, NONE), + BCM6358_GPIO_PIN(30, "gpio30", UTOPIA, UART1, EBI_CS), + BCM6358_GPIO_PIN(31, "gpio31", UTOPIA, UART1, EBI_CS), + BCM6358_GPIO_PIN(32, "gpio32", SPI_CS, NONE, NONE), + BCM6358_GPIO_PIN(33, "gpio33", SPI_CS, NONE, NONE), + PINCTRL_PIN(34, "gpio34"), + PINCTRL_PIN(35, "gpio35"), + PINCTRL_PIN(36, "gpio36"), + PINCTRL_PIN(37, "gpio37"), + PINCTRL_PIN(38, "gpio38"), + PINCTRL_PIN(39, "gpio39"), +}; + +static unsigned ebi_cs_grp_pins[] = { 30, 31 }; + +static unsigned uart1_grp_pins[] = { 28, 29, 30, 31 }; + +static unsigned spi_cs_grp_pins[] = { 32, 33 }; + +static unsigned async_modem_grp_pins[] = { 12, 13, 14, 15 }; + +static unsigned serial_led_grp_pins[] = { 6, 7 }; + +static unsigned legacy_led_grp_pins[] = { 9, 10, 11, 12, 13, 14, 15 }; + +static unsigned led_grp_pins[] = { 0, 1, 2, 3 }; + +static unsigned utopia_grp_pins[] = { + 12, 13, 14, 15, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, +}; + +static unsigned pwm_syn_clk_grp_pins[] = { 8 }; + +static unsigned sys_irq_grp_pins[] = { 5 }; + +#define BCM6358_GPIO_MUX_GROUP(n, bit, dir) \ + { \ + .name = #n, \ + .pins = n##_pins, \ + .num_pins = ARRAY_SIZE(n##_pins), \ + .mode_val = BCM6358_MODE_MUX_##bit, \ + .direction = dir, \ + } + +static const struct bcm6358_pingroup bcm6358_groups[] = { + BCM6358_GPIO_MUX_GROUP(ebi_cs_grp, EBI_CS, 0x3), + BCM6358_GPIO_MUX_GROUP(uart1_grp, UART1, 0x2), + BCM6358_GPIO_MUX_GROUP(spi_cs_grp, SPI_CS, 0x6), + BCM6358_GPIO_MUX_GROUP(async_modem_grp, ASYNC_MODEM, 0x6), + BCM6358_GPIO_MUX_GROUP(legacy_led_grp, LEGACY_LED, 0x7f), + BCM6358_GPIO_MUX_GROUP(serial_led_grp, SERIAL_LED, 0x3), + BCM6358_GPIO_MUX_GROUP(led_grp, LED, 0xf), + BCM6358_GPIO_MUX_GROUP(utopia_grp, UTOPIA, 0x000f), + BCM6358_GPIO_MUX_GROUP(pwm_syn_clk_grp, PWM_SYN_CLK, 0x1), + BCM6358_GPIO_MUX_GROUP(sys_irq_grp, SYS_IRQ, 0x1), +}; + +static const char * const ebi_cs_groups[] = { + "ebi_cs_grp" +}; + +static const char * const uart1_groups[] = { + "uart1_grp" +}; + +static const char * const spi_cs_2_3_groups[] = { + "spi_cs_2_3_grp" +}; + +static const char * const async_modem_groups[] = { + "async_modem_grp" +}; + +static const char * const legacy_led_groups[] = { + "legacy_led_grp", +}; + +static const char * const serial_led_groups[] = { + "serial_led_grp", +}; + +static const char * const led_groups[] = { + "led_grp", +}; + +static const char * const clkrst_groups[] = { + "clkrst_grp", +}; + +static const char * const pwm_syn_clk_groups[] = { + "pwm_syn_clk_grp", +}; + +static const char * const sys_irq_groups[] = { + "sys_irq_grp", +}; + +#define BCM6358_FUN(n) \ + { \ + .name = #n, \ + .groups = n##_groups, \ + .num_groups = ARRAY_SIZE(n##_groups), \ + } + +static const struct bcm6358_function bcm6358_funcs[] = { + BCM6358_FUN(ebi_cs), + BCM6358_FUN(uart1), + BCM6358_FUN(spi_cs_2_3), + BCM6358_FUN(async_modem), + BCM6358_FUN(legacy_led), + BCM6358_FUN(serial_led), + BCM6358_FUN(led), + BCM6358_FUN(clkrst), + BCM6358_FUN(pwm_syn_clk), + BCM6358_FUN(sys_irq), +}; + +static int bcm6358_pinctrl_get_group_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(bcm6358_groups); +} + +static const char *bcm6358_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + return bcm6358_groups[group].name; +} + +static int bcm6358_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, const unsigned **pins, + unsigned *num_pins) +{ + *pins = bcm6358_groups[group].pins; + *num_pins = bcm6358_groups[group].num_pins; + + return 0; +} + +static int bcm6358_pinctrl_get_func_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(bcm6358_funcs); +} + +static const char *bcm6358_pinctrl_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return bcm6358_funcs[selector].name; +} + +static int bcm6358_pinctrl_get_groups(struct pinctrl_dev *pctldev, + unsigned selector, + const char * const **groups, + unsigned * const num_groups) +{ + *groups = bcm6358_funcs[selector].groups; + *num_groups = bcm6358_funcs[selector].num_groups; + + return 0; +} + +static int bcm6358_pinctrl_set_mux(struct pinctrl_dev *pctldev, + unsigned selector, unsigned group) +{ + struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + struct bcm6358_priv *priv = pc->driver_data; + const struct bcm6358_pingroup *pg = &bcm6358_groups[group]; + unsigned int val = pg->mode_val; + unsigned int mask = val; + unsigned pin; + + for (pin = 0; pin < pg->num_pins; pin++) + mask |= (unsigned long)bcm6358_pins[pin].drv_data; + + regmap_field_update_bits(priv->overlays, mask, val); + + for (pin = 0; pin < pg->num_pins; pin++) { + struct pinctrl_gpio_range *range; + unsigned int hw_gpio = bcm6358_pins[pin].number; + + range = pinctrl_find_gpio_range_from_pin(pctldev, hw_gpio); + if (range) { + struct gpio_chip *gc = range->gc; + + if (pg->direction & BIT(pin)) + gc->direction_output(gc, hw_gpio, 0); + else + gc->direction_input(gc, hw_gpio); + } + } + + return 0; +} + +static int bcm6358_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + struct bcm6358_priv *priv = pc->driver_data; + unsigned int mask; + + mask = (unsigned long) bcm6358_pins[offset].drv_data; + if (!mask) + return 0; + + /* disable all functions using this pin */ + return regmap_field_update_bits(priv->overlays, mask, 0); +} + +static struct pinctrl_ops bcm6358_pctl_ops = { + .dt_free_map = pinctrl_utils_free_map, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .get_group_name = bcm6358_pinctrl_get_group_name, + .get_group_pins = bcm6358_pinctrl_get_group_pins, + .get_groups_count = bcm6358_pinctrl_get_group_count, +}; + +static struct pinmux_ops bcm6358_pmx_ops = { + .get_function_groups = bcm6358_pinctrl_get_groups, + .get_function_name = bcm6358_pinctrl_get_func_name, + .get_functions_count = bcm6358_pinctrl_get_func_count, + .gpio_request_enable = bcm6358_gpio_request_enable, + .set_mux = bcm6358_pinctrl_set_mux, + .strict = true, +}; + +static const struct bcm63xx_pinctrl_soc bcm6358_soc = { + .ngpios = BCM6358_NUM_GPIOS, + .npins = ARRAY_SIZE(bcm6358_pins), + .pctl_ops = &bcm6358_pctl_ops, + .pins = bcm6358_pins, + .pmx_ops = &bcm6358_pmx_ops, +}; + +static int bcm6358_pinctrl_probe(struct platform_device *pdev) +{ + struct reg_field overlays = REG_FIELD(BCM6358_MODE_REG, 0, 15); + struct device *dev = &pdev->dev; + struct bcm63xx_pinctrl *pc; + struct bcm6358_priv *priv; + int err; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + err = bcm63xx_pinctrl_probe(pdev, &bcm6358_soc, (void *) priv); + if (err) + return err; + + pc = platform_get_drvdata(pdev); + + priv->overlays = devm_regmap_field_alloc(dev, pc->regs, overlays); + if (IS_ERR(priv->overlays)) + return PTR_ERR(priv->overlays); + + return 0; +} + +static const struct of_device_id bcm6358_pinctrl_match[] = { + { .compatible = "brcm,bcm6358-pinctrl", }, + { /* sentinel */ } +}; + +static struct platform_driver bcm6358_pinctrl_driver = { + .probe = bcm6358_pinctrl_probe, + .driver = { + .name = "bcm6358-pinctrl", + .of_match_table = bcm6358_pinctrl_match, + }, +}; + +builtin_platform_driver(bcm6358_pinctrl_driver); diff --git a/drivers/pinctrl/bcm/pinctrl-bcm6362.c b/drivers/pinctrl/bcm/pinctrl-bcm6362.c new file mode 100644 index 000000000000..40ef495b6301 --- /dev/null +++ b/drivers/pinctrl/bcm/pinctrl-bcm6362.c @@ -0,0 +1,617 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for BCM6362 GPIO unit (pinctrl + GPIO) + * + * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com> + * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com> + */ + +#include <linux/bits.h> +#include <linux/gpio/driver.h> +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include "../pinctrl-utils.h" + +#include "pinctrl-bcm63xx.h" + +#define BCM6362_BANK_GPIOS 32 +#define BCM6362_NUM_GPIOS 48 +#define BCM6362_NUM_LEDS 24 + +#define BCM6362_LED_REG 0x10 +#define BCM6362_MODE_REG 0x18 +#define BCM6362_CTRL_REG 0x1c +#define BCM6362_BASEMODE_REG 0x38 +#define BASEMODE_NAND BIT(2) + +enum bcm6362_pinctrl_reg { + BCM6362_LEDCTRL, + BCM6362_MODE, + BCM6362_CTRL, + BCM6362_BASEMODE, +}; + +struct bcm6362_pingroup { + const char *name; + const unsigned * const pins; + const unsigned num_pins; +}; + +struct bcm6362_function { + const char *name; + const char * const *groups; + const unsigned num_groups; + + enum bcm6362_pinctrl_reg reg; + uint32_t basemode_mask; +}; + +#define BCM6362_PIN(a, b, mask) \ + { \ + .number = a, \ + .name = b, \ + .drv_data = (void *)(mask), \ + } + +static const struct pinctrl_pin_desc bcm6362_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + BCM6362_PIN(8, "gpio8", BASEMODE_NAND), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + BCM6362_PIN(12, "gpio12", BASEMODE_NAND), + BCM6362_PIN(13, "gpio13", BASEMODE_NAND), + BCM6362_PIN(14, "gpio14", BASEMODE_NAND), + BCM6362_PIN(15, "gpio15", BASEMODE_NAND), + BCM6362_PIN(16, "gpio16", BASEMODE_NAND), + BCM6362_PIN(17, "gpio17", BASEMODE_NAND), + BCM6362_PIN(18, "gpio18", BASEMODE_NAND), + BCM6362_PIN(19, "gpio19", BASEMODE_NAND), + BCM6362_PIN(20, "gpio20", BASEMODE_NAND), + BCM6362_PIN(21, "gpio21", BASEMODE_NAND), + BCM6362_PIN(22, "gpio22", BASEMODE_NAND), + BCM6362_PIN(23, "gpio23", BASEMODE_NAND), + PINCTRL_PIN(24, "gpio24"), + PINCTRL_PIN(25, "gpio25"), + PINCTRL_PIN(26, "gpio26"), + BCM6362_PIN(27, "gpio27", BASEMODE_NAND), + PINCTRL_PIN(28, "gpio28"), + PINCTRL_PIN(29, "gpio29"), + PINCTRL_PIN(30, "gpio30"), + PINCTRL_PIN(31, "gpio31"), + PINCTRL_PIN(32, "gpio32"), + PINCTRL_PIN(33, "gpio33"), + PINCTRL_PIN(34, "gpio34"), + PINCTRL_PIN(35, "gpio35"), + PINCTRL_PIN(36, "gpio36"), + PINCTRL_PIN(37, "gpio37"), + PINCTRL_PIN(38, "gpio38"), + PINCTRL_PIN(39, "gpio39"), + PINCTRL_PIN(40, "gpio40"), + PINCTRL_PIN(41, "gpio41"), + PINCTRL_PIN(42, "gpio42"), + PINCTRL_PIN(43, "gpio43"), + PINCTRL_PIN(44, "gpio44"), + PINCTRL_PIN(45, "gpio45"), + PINCTRL_PIN(46, "gpio46"), + PINCTRL_PIN(47, "gpio47"), +}; + +static unsigned gpio0_pins[] = { 0 }; +static unsigned gpio1_pins[] = { 1 }; +static unsigned gpio2_pins[] = { 2 }; +static unsigned gpio3_pins[] = { 3 }; +static unsigned gpio4_pins[] = { 4 }; +static unsigned gpio5_pins[] = { 5 }; +static unsigned gpio6_pins[] = { 6 }; +static unsigned gpio7_pins[] = { 7 }; +static unsigned gpio8_pins[] = { 8 }; +static unsigned gpio9_pins[] = { 9 }; +static unsigned gpio10_pins[] = { 10 }; +static unsigned gpio11_pins[] = { 11 }; +static unsigned gpio12_pins[] = { 12 }; +static unsigned gpio13_pins[] = { 13 }; +static unsigned gpio14_pins[] = { 14 }; +static unsigned gpio15_pins[] = { 15 }; +static unsigned gpio16_pins[] = { 16 }; +static unsigned gpio17_pins[] = { 17 }; +static unsigned gpio18_pins[] = { 18 }; +static unsigned gpio19_pins[] = { 19 }; +static unsigned gpio20_pins[] = { 20 }; +static unsigned gpio21_pins[] = { 21 }; +static unsigned gpio22_pins[] = { 22 }; +static unsigned gpio23_pins[] = { 23 }; +static unsigned gpio24_pins[] = { 24 }; +static unsigned gpio25_pins[] = { 25 }; +static unsigned gpio26_pins[] = { 26 }; +static unsigned gpio27_pins[] = { 27 }; +static unsigned gpio28_pins[] = { 28 }; +static unsigned gpio29_pins[] = { 29 }; +static unsigned gpio30_pins[] = { 30 }; +static unsigned gpio31_pins[] = { 31 }; +static unsigned gpio32_pins[] = { 32 }; +static unsigned gpio33_pins[] = { 33 }; +static unsigned gpio34_pins[] = { 34 }; +static unsigned gpio35_pins[] = { 35 }; +static unsigned gpio36_pins[] = { 36 }; +static unsigned gpio37_pins[] = { 37 }; +static unsigned gpio38_pins[] = { 38 }; +static unsigned gpio39_pins[] = { 39 }; +static unsigned gpio40_pins[] = { 40 }; +static unsigned gpio41_pins[] = { 41 }; +static unsigned gpio42_pins[] = { 42 }; +static unsigned gpio43_pins[] = { 43 }; +static unsigned gpio44_pins[] = { 44 }; +static unsigned gpio45_pins[] = { 45 }; +static unsigned gpio46_pins[] = { 46 }; +static unsigned gpio47_pins[] = { 47 }; + +static unsigned nand_grp_pins[] = { + 8, 12, 13, 14, 15, 16, 17, + 18, 19, 20, 21, 22, 23, 27, +}; + +#define BCM6362_GROUP(n) \ + { \ + .name = #n, \ + .pins = n##_pins, \ + .num_pins = ARRAY_SIZE(n##_pins), \ + } + +static struct bcm6362_pingroup bcm6362_groups[] = { + BCM6362_GROUP(gpio0), + BCM6362_GROUP(gpio1), + BCM6362_GROUP(gpio2), + BCM6362_GROUP(gpio3), + BCM6362_GROUP(gpio4), + BCM6362_GROUP(gpio5), + BCM6362_GROUP(gpio6), + BCM6362_GROUP(gpio7), + BCM6362_GROUP(gpio8), + BCM6362_GROUP(gpio9), + BCM6362_GROUP(gpio10), + BCM6362_GROUP(gpio11), + BCM6362_GROUP(gpio12), + BCM6362_GROUP(gpio13), + BCM6362_GROUP(gpio14), + BCM6362_GROUP(gpio15), + BCM6362_GROUP(gpio16), + BCM6362_GROUP(gpio17), + BCM6362_GROUP(gpio18), + BCM6362_GROUP(gpio19), + BCM6362_GROUP(gpio20), + BCM6362_GROUP(gpio21), + BCM6362_GROUP(gpio22), + BCM6362_GROUP(gpio23), + BCM6362_GROUP(gpio24), + BCM6362_GROUP(gpio25), + BCM6362_GROUP(gpio26), + BCM6362_GROUP(gpio27), + BCM6362_GROUP(gpio28), + BCM6362_GROUP(gpio29), + BCM6362_GROUP(gpio30), + BCM6362_GROUP(gpio31), + BCM6362_GROUP(gpio32), + BCM6362_GROUP(gpio33), + BCM6362_GROUP(gpio34), + BCM6362_GROUP(gpio35), + BCM6362_GROUP(gpio36), + BCM6362_GROUP(gpio37), + BCM6362_GROUP(gpio38), + BCM6362_GROUP(gpio39), + BCM6362_GROUP(gpio40), + BCM6362_GROUP(gpio41), + BCM6362_GROUP(gpio42), + BCM6362_GROUP(gpio43), + BCM6362_GROUP(gpio44), + BCM6362_GROUP(gpio45), + BCM6362_GROUP(gpio46), + BCM6362_GROUP(gpio47), + BCM6362_GROUP(nand_grp), +}; + +static const char * const led_groups[] = { + "gpio0", + "gpio1", + "gpio2", + "gpio3", + "gpio4", + "gpio5", + "gpio6", + "gpio7", + "gpio8", + "gpio9", + "gpio10", + "gpio11", + "gpio12", + "gpio13", + "gpio14", + "gpio15", + "gpio16", + "gpio17", + "gpio18", + "gpio19", + "gpio20", + "gpio21", + "gpio22", + "gpio23", +}; + +static const char * const usb_device_led_groups[] = { + "gpio0", +}; + +static const char * const sys_irq_groups[] = { + "gpio1", +}; + +static const char * const serial_led_clk_groups[] = { + "gpio2", +}; + +static const char * const serial_led_data_groups[] = { + "gpio3", +}; + +static const char * const robosw_led_data_groups[] = { + "gpio4", +}; + +static const char * const robosw_led_clk_groups[] = { + "gpio5", +}; + +static const char * const robosw_led0_groups[] = { + "gpio6", +}; + +static const char * const robosw_led1_groups[] = { + "gpio7", +}; + +static const char * const inet_led_groups[] = { + "gpio8", +}; + +static const char * const spi_cs2_groups[] = { + "gpio9", +}; + +static const char * const spi_cs3_groups[] = { + "gpio10", +}; + +static const char * const ntr_pulse_groups[] = { + "gpio11", +}; + +static const char * const uart1_scts_groups[] = { + "gpio12", +}; + +static const char * const uart1_srts_groups[] = { + "gpio13", +}; + +static const char * const uart1_sdin_groups[] = { + "gpio14", +}; + +static const char * const uart1_sdout_groups[] = { + "gpio15", +}; + +static const char * const adsl_spi_miso_groups[] = { + "gpio16", +}; + +static const char * const adsl_spi_mosi_groups[] = { + "gpio17", +}; + +static const char * const adsl_spi_clk_groups[] = { + "gpio18", +}; + +static const char * const adsl_spi_cs_groups[] = { + "gpio19", +}; + +static const char * const ephy0_led_groups[] = { + "gpio20", +}; + +static const char * const ephy1_led_groups[] = { + "gpio21", +}; + +static const char * const ephy2_led_groups[] = { + "gpio22", +}; + +static const char * const ephy3_led_groups[] = { + "gpio23", +}; + +static const char * const ext_irq0_groups[] = { + "gpio24", +}; + +static const char * const ext_irq1_groups[] = { + "gpio25", +}; + +static const char * const ext_irq2_groups[] = { + "gpio26", +}; + +static const char * const ext_irq3_groups[] = { + "gpio27", +}; + +static const char * const wifi_groups[] = { + "gpio32", + "gpio33", + "gpio34", + "gpio35", + "gpio36", + "gpio37", + "gpio38", + "gpio39", + "gpio40", + "gpio41", + "gpio42", + "gpio43", + "gpio44", + "gpio45", + "gpio46", + "gpio47", +}; + +static const char * const nand_groups[] = { + "nand_grp", +}; + +#define BCM6362_LED_FUN(n) \ + { \ + .name = #n, \ + .groups = n##_groups, \ + .num_groups = ARRAY_SIZE(n##_groups), \ + .reg = BCM6362_LEDCTRL, \ + } + +#define BCM6362_MODE_FUN(n) \ + { \ + .name = #n, \ + .groups = n##_groups, \ + .num_groups = ARRAY_SIZE(n##_groups), \ + .reg = BCM6362_MODE, \ + } + +#define BCM6362_CTRL_FUN(n) \ + { \ + .name = #n, \ + .groups = n##_groups, \ + .num_groups = ARRAY_SIZE(n##_groups), \ + .reg = BCM6362_CTRL, \ + } + +#define BCM6362_BASEMODE_FUN(n, mask) \ + { \ + .name = #n, \ + .groups = n##_groups, \ + .num_groups = ARRAY_SIZE(n##_groups), \ + .reg = BCM6362_BASEMODE, \ + .basemode_mask = (mask), \ + } + +static const struct bcm6362_function bcm6362_funcs[] = { + BCM6362_LED_FUN(led), + BCM6362_MODE_FUN(usb_device_led), + BCM6362_MODE_FUN(sys_irq), + BCM6362_MODE_FUN(serial_led_clk), + BCM6362_MODE_FUN(serial_led_data), + BCM6362_MODE_FUN(robosw_led_data), + BCM6362_MODE_FUN(robosw_led_clk), + BCM6362_MODE_FUN(robosw_led0), + BCM6362_MODE_FUN(robosw_led1), + BCM6362_MODE_FUN(inet_led), + BCM6362_MODE_FUN(spi_cs2), + BCM6362_MODE_FUN(spi_cs3), + BCM6362_MODE_FUN(ntr_pulse), + BCM6362_MODE_FUN(uart1_scts), + BCM6362_MODE_FUN(uart1_srts), + BCM6362_MODE_FUN(uart1_sdin), + BCM6362_MODE_FUN(uart1_sdout), + BCM6362_MODE_FUN(adsl_spi_miso), + BCM6362_MODE_FUN(adsl_spi_mosi), + BCM6362_MODE_FUN(adsl_spi_clk), + BCM6362_MODE_FUN(adsl_spi_cs), + BCM6362_MODE_FUN(ephy0_led), + BCM6362_MODE_FUN(ephy1_led), + BCM6362_MODE_FUN(ephy2_led), + BCM6362_MODE_FUN(ephy3_led), + BCM6362_MODE_FUN(ext_irq0), + BCM6362_MODE_FUN(ext_irq1), + BCM6362_MODE_FUN(ext_irq2), + BCM6362_MODE_FUN(ext_irq3), + BCM6362_CTRL_FUN(wifi), + BCM6362_BASEMODE_FUN(nand, BASEMODE_NAND), +}; + +static int bcm6362_pinctrl_get_group_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(bcm6362_groups); +} + +static const char *bcm6362_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + return bcm6362_groups[group].name; +} + +static int bcm6362_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, const unsigned **pins, + unsigned *num_pins) +{ + *pins = bcm6362_groups[group].pins; + *num_pins = bcm6362_groups[group].num_pins; + + return 0; +} + +static int bcm6362_pinctrl_get_func_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(bcm6362_funcs); +} + +static const char *bcm6362_pinctrl_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return bcm6362_funcs[selector].name; +} + +static int bcm6362_pinctrl_get_groups(struct pinctrl_dev *pctldev, + unsigned selector, + const char * const **groups, + unsigned * const num_groups) +{ + *groups = bcm6362_funcs[selector].groups; + *num_groups = bcm6362_funcs[selector].num_groups; + + return 0; +} + +static void bcm6362_set_gpio(struct bcm63xx_pinctrl *pc, unsigned pin) +{ + const struct pinctrl_pin_desc *desc = &bcm6362_pins[pin]; + unsigned int basemode = (uintptr_t)desc->drv_data; + unsigned int mask = bcm63xx_bank_pin(pin); + + if (basemode) + regmap_update_bits(pc->regs, BCM6362_BASEMODE_REG, basemode, 0); + + if (pin < BCM63XX_BANK_GPIOS) { + /* base mode 0 => gpio 1 => mux function */ + regmap_update_bits(pc->regs, BCM6362_MODE_REG, mask, 0); + + /* pins 0-23 might be muxed to led */ + if (pin < BCM6362_NUM_LEDS) + regmap_update_bits(pc->regs, BCM6362_LED_REG, mask, 0); + } else { + /* ctrl reg 0 => wifi function 1 => gpio */ + regmap_update_bits(pc->regs, BCM6362_CTRL_REG, mask, mask); + } +} + +static int bcm6362_pinctrl_set_mux(struct pinctrl_dev *pctldev, + unsigned selector, unsigned group) +{ + struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + const struct bcm6362_pingroup *pg = &bcm6362_groups[group]; + const struct bcm6362_function *f = &bcm6362_funcs[selector]; + unsigned i; + unsigned int reg; + unsigned int val, mask; + + for (i = 0; i < pg->num_pins; i++) + bcm6362_set_gpio(pc, pg->pins[i]); + + switch (f->reg) { + case BCM6362_LEDCTRL: + reg = BCM6362_LED_REG; + mask = BIT(pg->pins[0]); + val = BIT(pg->pins[0]); + break; + case BCM6362_MODE: + reg = BCM6362_MODE_REG; + mask = BIT(pg->pins[0]); + val = BIT(pg->pins[0]); + break; + case BCM6362_CTRL: + reg = BCM6362_CTRL_REG; + mask = BIT(pg->pins[0]); + val = 0; + break; + case BCM6362_BASEMODE: + reg = BCM6362_BASEMODE_REG; + mask = f->basemode_mask; + val = f->basemode_mask; + break; + default: + WARN_ON(1); + return -EINVAL; + } + + regmap_update_bits(pc->regs, reg, mask, val); + + return 0; +} + +static int bcm6362_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + + /* disable all functions using this pin */ + bcm6362_set_gpio(pc, offset); + + return 0; +} + +static struct pinctrl_ops bcm6362_pctl_ops = { + .dt_free_map = pinctrl_utils_free_map, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .get_group_name = bcm6362_pinctrl_get_group_name, + .get_group_pins = bcm6362_pinctrl_get_group_pins, + .get_groups_count = bcm6362_pinctrl_get_group_count, +}; + +static struct pinmux_ops bcm6362_pmx_ops = { + .get_function_groups = bcm6362_pinctrl_get_groups, + .get_function_name = bcm6362_pinctrl_get_func_name, + .get_functions_count = bcm6362_pinctrl_get_func_count, + .gpio_request_enable = bcm6362_gpio_request_enable, + .set_mux = bcm6362_pinctrl_set_mux, + .strict = true, +}; + +static const struct bcm63xx_pinctrl_soc bcm6362_soc = { + .ngpios = BCM6362_NUM_GPIOS, + .npins = ARRAY_SIZE(bcm6362_pins), + .pctl_ops = &bcm6362_pctl_ops, + .pins = bcm6362_pins, + .pmx_ops = &bcm6362_pmx_ops, +}; + +static int bcm6362_pinctrl_probe(struct platform_device *pdev) +{ + return bcm63xx_pinctrl_probe(pdev, &bcm6362_soc, NULL); +} + +static const struct of_device_id bcm6362_pinctrl_match[] = { + { .compatible = "brcm,bcm6362-pinctrl", }, + { /* sentinel */ } +}; + +static struct platform_driver bcm6362_pinctrl_driver = { + .probe = bcm6362_pinctrl_probe, + .driver = { + .name = "bcm6362-pinctrl", + .of_match_table = bcm6362_pinctrl_match, + }, +}; + +builtin_platform_driver(bcm6362_pinctrl_driver); diff --git a/drivers/pinctrl/bcm/pinctrl-bcm6368.c b/drivers/pinctrl/bcm/pinctrl-bcm6368.c new file mode 100644 index 000000000000..838095f9e890 --- /dev/null +++ b/drivers/pinctrl/bcm/pinctrl-bcm6368.c @@ -0,0 +1,523 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for BCM6368 GPIO unit (pinctrl + GPIO) + * + * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com> + * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com> + */ + +#include <linux/bits.h> +#include <linux/gpio/driver.h> +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include "../pinctrl-utils.h" + +#include "pinctrl-bcm63xx.h" + +#define BCM6368_NUM_GPIOS 38 + +#define BCM6368_MODE_REG 0x18 +#define BCM6368_BASEMODE_REG 0x38 +#define BCM6368_BASEMODE_MASK 0x7 +#define BCM6368_BASEMODE_GPIO 0x0 +#define BCM6368_BASEMODE_UART1 0x1 + +struct bcm6368_pingroup { + const char *name; + const unsigned * const pins; + const unsigned num_pins; +}; + +struct bcm6368_function { + const char *name; + const char * const *groups; + const unsigned num_groups; + + unsigned dir_out:16; + unsigned basemode:3; +}; + +struct bcm6368_priv { + struct regmap_field *overlays; +}; + +#define BCM6368_BASEMODE_PIN(a, b) \ + { \ + .number = a, \ + .name = b, \ + .drv_data = (void *)true \ + } + +static const struct pinctrl_pin_desc bcm6368_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), + PINCTRL_PIN(23, "gpio23"), + PINCTRL_PIN(24, "gpio24"), + PINCTRL_PIN(25, "gpio25"), + PINCTRL_PIN(26, "gpio26"), + PINCTRL_PIN(27, "gpio27"), + PINCTRL_PIN(28, "gpio28"), + PINCTRL_PIN(29, "gpio29"), + BCM6368_BASEMODE_PIN(30, "gpio30"), + BCM6368_BASEMODE_PIN(31, "gpio31"), + BCM6368_BASEMODE_PIN(32, "gpio32"), + BCM6368_BASEMODE_PIN(33, "gpio33"), + PINCTRL_PIN(34, "gpio34"), + PINCTRL_PIN(35, "gpio35"), + PINCTRL_PIN(36, "gpio36"), + PINCTRL_PIN(37, "gpio37"), +}; + +static unsigned gpio0_pins[] = { 0 }; +static unsigned gpio1_pins[] = { 1 }; +static unsigned gpio2_pins[] = { 2 }; +static unsigned gpio3_pins[] = { 3 }; +static unsigned gpio4_pins[] = { 4 }; +static unsigned gpio5_pins[] = { 5 }; +static unsigned gpio6_pins[] = { 6 }; +static unsigned gpio7_pins[] = { 7 }; +static unsigned gpio8_pins[] = { 8 }; +static unsigned gpio9_pins[] = { 9 }; +static unsigned gpio10_pins[] = { 10 }; +static unsigned gpio11_pins[] = { 11 }; +static unsigned gpio12_pins[] = { 12 }; +static unsigned gpio13_pins[] = { 13 }; +static unsigned gpio14_pins[] = { 14 }; +static unsigned gpio15_pins[] = { 15 }; +static unsigned gpio16_pins[] = { 16 }; +static unsigned gpio17_pins[] = { 17 }; +static unsigned gpio18_pins[] = { 18 }; +static unsigned gpio19_pins[] = { 19 }; +static unsigned gpio20_pins[] = { 20 }; +static unsigned gpio21_pins[] = { 21 }; +static unsigned gpio22_pins[] = { 22 }; +static unsigned gpio23_pins[] = { 23 }; +static unsigned gpio24_pins[] = { 24 }; +static unsigned gpio25_pins[] = { 25 }; +static unsigned gpio26_pins[] = { 26 }; +static unsigned gpio27_pins[] = { 27 }; +static unsigned gpio28_pins[] = { 28 }; +static unsigned gpio29_pins[] = { 29 }; +static unsigned gpio30_pins[] = { 30 }; +static unsigned gpio31_pins[] = { 31 }; +static unsigned uart1_grp_pins[] = { 30, 31, 32, 33 }; + +#define BCM6368_GROUP(n) \ + { \ + .name = #n, \ + .pins = n##_pins, \ + .num_pins = ARRAY_SIZE(n##_pins), \ + } + +static struct bcm6368_pingroup bcm6368_groups[] = { + BCM6368_GROUP(gpio0), + BCM6368_GROUP(gpio1), + BCM6368_GROUP(gpio2), + BCM6368_GROUP(gpio3), + BCM6368_GROUP(gpio4), + BCM6368_GROUP(gpio5), + BCM6368_GROUP(gpio6), + BCM6368_GROUP(gpio7), + BCM6368_GROUP(gpio8), + BCM6368_GROUP(gpio9), + BCM6368_GROUP(gpio10), + BCM6368_GROUP(gpio11), + BCM6368_GROUP(gpio12), + BCM6368_GROUP(gpio13), + BCM6368_GROUP(gpio14), + BCM6368_GROUP(gpio15), + BCM6368_GROUP(gpio16), + BCM6368_GROUP(gpio17), + BCM6368_GROUP(gpio18), + BCM6368_GROUP(gpio19), + BCM6368_GROUP(gpio20), + BCM6368_GROUP(gpio21), + BCM6368_GROUP(gpio22), + BCM6368_GROUP(gpio23), + BCM6368_GROUP(gpio24), + BCM6368_GROUP(gpio25), + BCM6368_GROUP(gpio26), + BCM6368_GROUP(gpio27), + BCM6368_GROUP(gpio28), + BCM6368_GROUP(gpio29), + BCM6368_GROUP(gpio30), + BCM6368_GROUP(gpio31), + BCM6368_GROUP(uart1_grp), +}; + +static const char * const analog_afe_0_groups[] = { + "gpio0", +}; + +static const char * const analog_afe_1_groups[] = { + "gpio1", +}; + +static const char * const sys_irq_groups[] = { + "gpio2", +}; + +static const char * const serial_led_data_groups[] = { + "gpio3", +}; + +static const char * const serial_led_clk_groups[] = { + "gpio4", +}; + +static const char * const inet_led_groups[] = { + "gpio5", +}; + +static const char * const ephy0_led_groups[] = { + "gpio6", +}; + +static const char * const ephy1_led_groups[] = { + "gpio7", +}; + +static const char * const ephy2_led_groups[] = { + "gpio8", +}; + +static const char * const ephy3_led_groups[] = { + "gpio9", +}; + +static const char * const robosw_led_data_groups[] = { + "gpio10", +}; + +static const char * const robosw_led_clk_groups[] = { + "gpio11", +}; + +static const char * const robosw_led0_groups[] = { + "gpio12", +}; + +static const char * const robosw_led1_groups[] = { + "gpio13", +}; + +static const char * const usb_device_led_groups[] = { + "gpio14", +}; + +static const char * const pci_req1_groups[] = { + "gpio16", +}; + +static const char * const pci_gnt1_groups[] = { + "gpio17", +}; + +static const char * const pci_intb_groups[] = { + "gpio18", +}; + +static const char * const pci_req0_groups[] = { + "gpio19", +}; + +static const char * const pci_gnt0_groups[] = { + "gpio20", +}; + +static const char * const pcmcia_cd1_groups[] = { + "gpio22", +}; + +static const char * const pcmcia_cd2_groups[] = { + "gpio23", +}; + +static const char * const pcmcia_vs1_groups[] = { + "gpio24", +}; + +static const char * const pcmcia_vs2_groups[] = { + "gpio25", +}; + +static const char * const ebi_cs2_groups[] = { + "gpio26", +}; + +static const char * const ebi_cs3_groups[] = { + "gpio27", +}; + +static const char * const spi_cs2_groups[] = { + "gpio28", +}; + +static const char * const spi_cs3_groups[] = { + "gpio29", +}; + +static const char * const spi_cs4_groups[] = { + "gpio30", +}; + +static const char * const spi_cs5_groups[] = { + "gpio31", +}; + +static const char * const uart1_groups[] = { + "uart1_grp", +}; + +#define BCM6368_FUN(n, out) \ + { \ + .name = #n, \ + .groups = n##_groups, \ + .num_groups = ARRAY_SIZE(n##_groups), \ + .dir_out = out, \ + } + +#define BCM6368_BASEMODE_FUN(n, val, out) \ + { \ + .name = #n, \ + .groups = n##_groups, \ + .num_groups = ARRAY_SIZE(n##_groups), \ + .basemode = BCM6368_BASEMODE_##val, \ + .dir_out = out, \ + } + +static const struct bcm6368_function bcm6368_funcs[] = { + BCM6368_FUN(analog_afe_0, 1), + BCM6368_FUN(analog_afe_1, 1), + BCM6368_FUN(sys_irq, 1), + BCM6368_FUN(serial_led_data, 1), + BCM6368_FUN(serial_led_clk, 1), + BCM6368_FUN(inet_led, 1), + BCM6368_FUN(ephy0_led, 1), + BCM6368_FUN(ephy1_led, 1), + BCM6368_FUN(ephy2_led, 1), + BCM6368_FUN(ephy3_led, 1), + BCM6368_FUN(robosw_led_data, 1), + BCM6368_FUN(robosw_led_clk, 1), + BCM6368_FUN(robosw_led0, 1), + BCM6368_FUN(robosw_led1, 1), + BCM6368_FUN(usb_device_led, 1), + BCM6368_FUN(pci_req1, 0), + BCM6368_FUN(pci_gnt1, 0), + BCM6368_FUN(pci_intb, 0), + BCM6368_FUN(pci_req0, 0), + BCM6368_FUN(pci_gnt0, 0), + BCM6368_FUN(pcmcia_cd1, 0), + BCM6368_FUN(pcmcia_cd2, 0), + BCM6368_FUN(pcmcia_vs1, 0), + BCM6368_FUN(pcmcia_vs2, 0), + BCM6368_FUN(ebi_cs2, 1), + BCM6368_FUN(ebi_cs3, 1), + BCM6368_FUN(spi_cs2, 1), + BCM6368_FUN(spi_cs3, 1), + BCM6368_FUN(spi_cs4, 1), + BCM6368_FUN(spi_cs5, 1), + BCM6368_BASEMODE_FUN(uart1, UART1, 0x6), +}; + +static int bcm6368_pinctrl_get_group_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(bcm6368_groups); +} + +static const char *bcm6368_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + return bcm6368_groups[group].name; +} + +static int bcm6368_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, const unsigned **pins, + unsigned *num_pins) +{ + *pins = bcm6368_groups[group].pins; + *num_pins = bcm6368_groups[group].num_pins; + + return 0; +} + +static int bcm6368_pinctrl_get_func_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(bcm6368_funcs); +} + +static const char *bcm6368_pinctrl_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return bcm6368_funcs[selector].name; +} + +static int bcm6368_pinctrl_get_groups(struct pinctrl_dev *pctldev, + unsigned selector, + const char * const **groups, + unsigned * const num_groups) +{ + *groups = bcm6368_funcs[selector].groups; + *num_groups = bcm6368_funcs[selector].num_groups; + + return 0; +} + +static int bcm6368_pinctrl_set_mux(struct pinctrl_dev *pctldev, + unsigned selector, unsigned group) +{ + struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + struct bcm6368_priv *priv = pc->driver_data; + const struct bcm6368_pingroup *pg = &bcm6368_groups[group]; + const struct bcm6368_function *fun = &bcm6368_funcs[selector]; + int i, pin; + + if (fun->basemode) { + unsigned int mask = 0; + + for (i = 0; i < pg->num_pins; i++) { + pin = pg->pins[i]; + if (pin < BCM63XX_BANK_GPIOS) + mask |= BIT(pin); + } + + regmap_update_bits(pc->regs, BCM6368_MODE_REG, mask, 0); + regmap_field_write(priv->overlays, fun->basemode); + } else { + pin = pg->pins[0]; + + if (bcm6368_pins[pin].drv_data) + regmap_field_write(priv->overlays, + BCM6368_BASEMODE_GPIO); + + regmap_update_bits(pc->regs, BCM6368_MODE_REG, BIT(pin), + BIT(pin)); + } + + for (pin = 0; pin < pg->num_pins; pin++) { + struct pinctrl_gpio_range *range; + int hw_gpio = bcm6368_pins[pin].number; + + range = pinctrl_find_gpio_range_from_pin(pctldev, hw_gpio); + if (range) { + struct gpio_chip *gc = range->gc; + + if (fun->dir_out & BIT(pin)) + gc->direction_output(gc, hw_gpio, 0); + else + gc->direction_input(gc, hw_gpio); + } + } + + return 0; +} + +static int bcm6368_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + struct bcm6368_priv *priv = pc->driver_data; + + if (offset >= BCM63XX_BANK_GPIOS && !bcm6368_pins[offset].drv_data) + return 0; + + /* disable all functions using this pin */ + if (offset < BCM63XX_BANK_GPIOS) + regmap_update_bits(pc->regs, BCM6368_MODE_REG, BIT(offset), 0); + + if (bcm6368_pins[offset].drv_data) + regmap_field_write(priv->overlays, BCM6368_BASEMODE_GPIO); + + return 0; +} + +static struct pinctrl_ops bcm6368_pctl_ops = { + .dt_free_map = pinctrl_utils_free_map, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .get_group_name = bcm6368_pinctrl_get_group_name, + .get_group_pins = bcm6368_pinctrl_get_group_pins, + .get_groups_count = bcm6368_pinctrl_get_group_count, +}; + +static struct pinmux_ops bcm6368_pmx_ops = { + .get_function_groups = bcm6368_pinctrl_get_groups, + .get_function_name = bcm6368_pinctrl_get_func_name, + .get_functions_count = bcm6368_pinctrl_get_func_count, + .gpio_request_enable = bcm6368_gpio_request_enable, + .set_mux = bcm6368_pinctrl_set_mux, + .strict = true, +}; + +static const struct bcm63xx_pinctrl_soc bcm6368_soc = { + .ngpios = BCM6368_NUM_GPIOS, + .npins = ARRAY_SIZE(bcm6368_pins), + .pctl_ops = &bcm6368_pctl_ops, + .pins = bcm6368_pins, + .pmx_ops = &bcm6368_pmx_ops, +}; + +static int bcm6368_pinctrl_probe(struct platform_device *pdev) +{ + struct reg_field overlays = REG_FIELD(BCM6368_BASEMODE_REG, 0, 15); + struct device *dev = &pdev->dev; + struct bcm63xx_pinctrl *pc; + struct bcm6368_priv *priv; + int err; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + err = bcm63xx_pinctrl_probe(pdev, &bcm6368_soc, (void *) priv); + if (err) + return err; + + pc = platform_get_drvdata(pdev); + + priv->overlays = devm_regmap_field_alloc(dev, pc->regs, overlays); + if (IS_ERR(priv->overlays)) + return PTR_ERR(priv->overlays); + + return 0; +} + +static const struct of_device_id bcm6368_pinctrl_match[] = { + { .compatible = "brcm,bcm6368-pinctrl", }, + { /* sentinel */ } +}; + +static struct platform_driver bcm6368_pinctrl_driver = { + .probe = bcm6368_pinctrl_probe, + .driver = { + .name = "bcm6368-pinctrl", + .of_match_table = bcm6368_pinctrl_match, + }, +}; + +builtin_platform_driver(bcm6368_pinctrl_driver); diff --git a/drivers/pinctrl/bcm/pinctrl-bcm63xx.c b/drivers/pinctrl/bcm/pinctrl-bcm63xx.c new file mode 100644 index 000000000000..e1285fe2fbc0 --- /dev/null +++ b/drivers/pinctrl/bcm/pinctrl-bcm63xx.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for BCM63xx GPIO unit (pinctrl + GPIO) + * + * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com> + * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com> + */ + +#include <linux/gpio/regmap.h> +#include <linux/mfd/syscon.h> +#include <linux/mod_devicetable.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-bcm63xx.h" + +#define BCM63XX_BANK_SIZE 4 + +#define BCM63XX_DIROUT_REG 0x04 +#define BCM63XX_DATA_REG 0x0c + +static int bcm63xx_reg_mask_xlate(struct gpio_regmap *gpio, + unsigned int base, unsigned int offset, + unsigned int *reg, unsigned int *mask) +{ + unsigned int line = offset % BCM63XX_BANK_GPIOS; + unsigned int stride = offset / BCM63XX_BANK_GPIOS; + + *reg = base - stride * BCM63XX_BANK_SIZE; + *mask = BIT(line); + + return 0; +} + +static const struct of_device_id bcm63xx_gpio_of_match[] = { + { .compatible = "brcm,bcm6318-gpio", }, + { .compatible = "brcm,bcm6328-gpio", }, + { .compatible = "brcm,bcm6358-gpio", }, + { .compatible = "brcm,bcm6362-gpio", }, + { .compatible = "brcm,bcm6368-gpio", }, + { .compatible = "brcm,bcm63268-gpio", }, + { /* sentinel */ } +}; + +static int bcm63xx_gpio_probe(struct device *dev, struct device_node *node, + const struct bcm63xx_pinctrl_soc *soc, + struct bcm63xx_pinctrl *pc) +{ + struct gpio_regmap_config grc = {0}; + + grc.parent = dev; + grc.fwnode = &node->fwnode; + grc.ngpio = soc->ngpios; + grc.ngpio_per_reg = BCM63XX_BANK_GPIOS; + grc.regmap = pc->regs; + grc.reg_dat_base = BCM63XX_DATA_REG; + grc.reg_dir_out_base = BCM63XX_DIROUT_REG; + grc.reg_set_base = BCM63XX_DATA_REG; + grc.reg_mask_xlate = bcm63xx_reg_mask_xlate; + + return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &grc)); +} + +int bcm63xx_pinctrl_probe(struct platform_device *pdev, + const struct bcm63xx_pinctrl_soc *soc, + void *driver_data) +{ + struct device *dev = &pdev->dev; + struct bcm63xx_pinctrl *pc; + struct device_node *node; + int err; + + pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL); + if (!pc) + return -ENOMEM; + + platform_set_drvdata(pdev, pc); + + pc->dev = dev; + pc->driver_data = driver_data; + + pc->regs = syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(pc->regs)) + return PTR_ERR(pc->regs); + + pc->pctl_desc.name = dev_name(dev); + pc->pctl_desc.pins = soc->pins; + pc->pctl_desc.npins = soc->npins; + pc->pctl_desc.pctlops = soc->pctl_ops; + pc->pctl_desc.pmxops = soc->pmx_ops; + pc->pctl_desc.owner = THIS_MODULE; + + pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc); + if (IS_ERR(pc->pctl_dev)) + return PTR_ERR(pc->pctl_dev); + + for_each_child_of_node(dev->parent->of_node, node) { + if (of_match_node(bcm63xx_gpio_of_match, node)) { + err = bcm63xx_gpio_probe(dev, node, soc, pc); + if (err) { + dev_err(dev, "could not add GPIO chip\n"); + of_node_put(node); + return err; + } + } + } + + return 0; +} diff --git a/drivers/pinctrl/bcm/pinctrl-bcm63xx.h b/drivers/pinctrl/bcm/pinctrl-bcm63xx.h new file mode 100644 index 000000000000..3bdb50021f1b --- /dev/null +++ b/drivers/pinctrl/bcm/pinctrl-bcm63xx.h @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com> + * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com> + */ + +#ifndef __PINCTRL_BCM63XX_H__ +#define __PINCTRL_BCM63XX_H__ + +#include <linux/pinctrl/pinctrl.h> + +#define BCM63XX_BANK_GPIOS 32 + +struct bcm63xx_pinctrl_soc { + struct pinctrl_ops *pctl_ops; + struct pinmux_ops *pmx_ops; + + const struct pinctrl_pin_desc *pins; + unsigned npins; + + unsigned int ngpios; +}; + +struct bcm63xx_pinctrl { + struct device *dev; + struct regmap *regs; + + struct pinctrl_desc pctl_desc; + struct pinctrl_dev *pctl_dev; + + void *driver_data; +}; + +static inline unsigned int bcm63xx_bank_pin(unsigned int pin) +{ + return pin % BCM63XX_BANK_GPIOS; +} + +int bcm63xx_pinctrl_probe(struct platform_device *pdev, + const struct bcm63xx_pinctrl_soc *soc, + void *driver_data); + +#endif /* __PINCTRL_BCM63XX_H__ */ diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 6e6825d17a1d..a4ac87c8b4f8 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -160,7 +160,7 @@ int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name) } /** - * pin_get_name_from_id() - look up a pin name from a pin id + * pin_get_name() - look up a pin name from a pin id * @pctldev: the pin control device to lookup the pin on * @pin: pin number/id to look up */ @@ -1258,7 +1258,7 @@ static int pinctrl_commit_state(struct pinctrl *p, struct pinctrl_state *state) p->state = NULL; - /* Apply all the settings for the new state */ + /* Apply all the settings for the new state - pinmux first */ list_for_each_entry(setting, &state->settings, node) { switch (setting->type) { case PIN_MAP_TYPE_MUX_GROUP: @@ -1266,6 +1266,29 @@ static int pinctrl_commit_state(struct pinctrl *p, struct pinctrl_state *state) break; case PIN_MAP_TYPE_CONFIGS_PIN: case PIN_MAP_TYPE_CONFIGS_GROUP: + ret = 0; + break; + default: + ret = -EINVAL; + break; + } + + if (ret < 0) + goto unapply_new_state; + + /* Do not link hogs (circular dependency) */ + if (p != setting->pctldev->p) + pinctrl_link_add(setting->pctldev, p->dev); + } + + /* Apply all the settings for the new state - pinconf after */ + list_for_each_entry(setting, &state->settings, node) { + switch (setting->type) { + case PIN_MAP_TYPE_MUX_GROUP: + ret = 0; + break; + case PIN_MAP_TYPE_CONFIGS_PIN: + case PIN_MAP_TYPE_CONFIGS_GROUP: ret = pinconf_apply_setting(setting); break; default: @@ -1892,11 +1915,11 @@ static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev) dev_name(pctldev->dev)); return; } - debugfs_create_file("pins", S_IFREG | S_IRUGO, + debugfs_create_file("pins", 0444, device_root, pctldev, &pinctrl_pins_fops); - debugfs_create_file("pingroups", S_IFREG | S_IRUGO, + debugfs_create_file("pingroups", 0444, device_root, pctldev, &pinctrl_groups_fops); - debugfs_create_file("gpio-ranges", S_IFREG | S_IRUGO, + debugfs_create_file("gpio-ranges", 0444, device_root, pctldev, &pinctrl_gpioranges_fops); if (pctldev->desc->pmxops) pinmux_init_device_debugfs(device_root, pctldev); @@ -1918,11 +1941,11 @@ static void pinctrl_init_debugfs(void) return; } - debugfs_create_file("pinctrl-devices", S_IFREG | S_IRUGO, + debugfs_create_file("pinctrl-devices", 0444, debugfs_root, NULL, &pinctrl_devices_fops); - debugfs_create_file("pinctrl-maps", S_IFREG | S_IRUGO, + debugfs_create_file("pinctrl-maps", 0444, debugfs_root, NULL, &pinctrl_maps_fops); - debugfs_create_file("pinctrl-handles", S_IFREG | S_IRUGO, + debugfs_create_file("pinctrl-handles", 0444, debugfs_root, NULL, &pinctrl_fops); } diff --git a/drivers/pinctrl/freescale/pinctrl-imx1.c b/drivers/pinctrl/freescale/pinctrl-imx1.c index faf770f13bc7..1e2b0fe9ffd6 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx1.c +++ b/drivers/pinctrl/freescale/pinctrl-imx1.c @@ -262,6 +262,7 @@ static struct platform_driver imx1_pinctrl_driver = { .driver = { .name = "imx1-pinctrl", .of_match_table = imx1_pinctrl_of_match, + .suppress_bind_attrs = true, }, }; builtin_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe); diff --git a/drivers/pinctrl/freescale/pinctrl-imx25.c b/drivers/pinctrl/freescale/pinctrl-imx25.c index a899a398b6bb..51748da1668f 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx25.c +++ b/drivers/pinctrl/freescale/pinctrl-imx25.c @@ -323,7 +323,8 @@ static int imx25_pinctrl_probe(struct platform_device *pdev) static struct platform_driver imx25_pinctrl_driver = { .driver = { .name = "imx25-pinctrl", - .of_match_table = of_match_ptr(imx25_pinctrl_of_match), + .of_match_table = imx25_pinctrl_of_match, + .suppress_bind_attrs = true, }, .probe = imx25_pinctrl_probe, }; diff --git a/drivers/pinctrl/freescale/pinctrl-imx27.c b/drivers/pinctrl/freescale/pinctrl-imx27.c index b4dfc1676cbc..67e7105be4f3 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx27.c +++ b/drivers/pinctrl/freescale/pinctrl-imx27.c @@ -396,7 +396,8 @@ static int imx27_pinctrl_probe(struct platform_device *pdev) static struct platform_driver imx27_pinctrl_driver = { .driver = { .name = "imx27-pinctrl", - .of_match_table = of_match_ptr(imx27_pinctrl_of_match), + .of_match_table = imx27_pinctrl_of_match, + .suppress_bind_attrs = true, }, .probe = imx27_pinctrl_probe, }; diff --git a/drivers/pinctrl/freescale/pinctrl-imx35.c b/drivers/pinctrl/freescale/pinctrl-imx35.c index 871bb419e2f0..c8671ad5214c 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx35.c +++ b/drivers/pinctrl/freescale/pinctrl-imx35.c @@ -1014,6 +1014,7 @@ static struct platform_driver imx35_pinctrl_driver = { .driver = { .name = "imx35-pinctrl", .of_match_table = imx35_pinctrl_of_match, + .suppress_bind_attrs = true, }, .probe = imx35_pinctrl_probe, }; diff --git a/drivers/pinctrl/freescale/pinctrl-imx50.c b/drivers/pinctrl/freescale/pinctrl-imx50.c index cf182c040e0b..a245b4011c00 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx50.c +++ b/drivers/pinctrl/freescale/pinctrl-imx50.c @@ -399,7 +399,8 @@ static int imx50_pinctrl_probe(struct platform_device *pdev) static struct platform_driver imx50_pinctrl_driver = { .driver = { .name = "imx50-pinctrl", - .of_match_table = of_match_ptr(imx50_pinctrl_of_match), + .of_match_table = imx50_pinctrl_of_match, + .suppress_bind_attrs = true, }, .probe = imx50_pinctrl_probe, }; diff --git a/drivers/pinctrl/freescale/pinctrl-imx51.c b/drivers/pinctrl/freescale/pinctrl-imx51.c index e5c261e2bf1e..307cf5fe4d15 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx51.c +++ b/drivers/pinctrl/freescale/pinctrl-imx51.c @@ -776,6 +776,7 @@ static struct platform_driver imx51_pinctrl_driver = { .driver = { .name = "imx51-pinctrl", .of_match_table = imx51_pinctrl_of_match, + .suppress_bind_attrs = true, }, .probe = imx51_pinctrl_probe, }; diff --git a/drivers/pinctrl/freescale/pinctrl-imx53.c b/drivers/pinctrl/freescale/pinctrl-imx53.c index 64c97aaf20c7..02bf3bda69ac 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx53.c +++ b/drivers/pinctrl/freescale/pinctrl-imx53.c @@ -463,6 +463,7 @@ static struct platform_driver imx53_pinctrl_driver = { .driver = { .name = "imx53-pinctrl", .of_match_table = imx53_pinctrl_of_match, + .suppress_bind_attrs = true, }, .probe = imx53_pinctrl_probe, }; diff --git a/drivers/pinctrl/freescale/pinctrl-imx6dl.c b/drivers/pinctrl/freescale/pinctrl-imx6dl.c index 0858b4d79ed2..2b6d5141a477 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6dl.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6dl.c @@ -473,6 +473,7 @@ static struct platform_driver imx6dl_pinctrl_driver = { .driver = { .name = "imx6dl-pinctrl", .of_match_table = imx6dl_pinctrl_of_match, + .suppress_bind_attrs = true, }, .probe = imx6dl_pinctrl_probe, }; diff --git a/drivers/pinctrl/freescale/pinctrl-imx6q.c b/drivers/pinctrl/freescale/pinctrl-imx6q.c index 078ed6a331fd..a7507def26a9 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6q.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6q.c @@ -475,6 +475,7 @@ static struct platform_driver imx6q_pinctrl_driver = { .driver = { .name = "imx6q-pinctrl", .of_match_table = imx6q_pinctrl_of_match, + .suppress_bind_attrs = true, }, .probe = imx6q_pinctrl_probe, }; diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sl.c b/drivers/pinctrl/freescale/pinctrl-imx6sl.c index 9d2e6f987aa7..236f3bf120c2 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6sl.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6sl.c @@ -379,6 +379,7 @@ static struct platform_driver imx6sl_pinctrl_driver = { .driver = { .name = "imx6sl-pinctrl", .of_match_table = imx6sl_pinctrl_of_match, + .suppress_bind_attrs = true, }, .probe = imx6sl_pinctrl_probe, }; diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sll.c b/drivers/pinctrl/freescale/pinctrl-imx6sll.c index 0618f4d887fd..dfefcecbe072 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6sll.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6sll.c @@ -345,7 +345,7 @@ static int imx6sll_pinctrl_probe(struct platform_device *pdev) static struct platform_driver imx6sll_pinctrl_driver = { .driver = { .name = "imx6sll-pinctrl", - .of_match_table = of_match_ptr(imx6sll_pinctrl_of_match), + .of_match_table = imx6sll_pinctrl_of_match, .suppress_bind_attrs = true, }, .probe = imx6sll_pinctrl_probe, diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sx.c b/drivers/pinctrl/freescale/pinctrl-imx6sx.c index c7e2b1f94f01..b7b97c274dcc 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6sx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6sx.c @@ -382,7 +382,8 @@ static int imx6sx_pinctrl_probe(struct platform_device *pdev) static struct platform_driver imx6sx_pinctrl_driver = { .driver = { .name = "imx6sx-pinctrl", - .of_match_table = of_match_ptr(imx6sx_pinctrl_of_match), + .of_match_table = imx6sx_pinctrl_of_match, + .suppress_bind_attrs = true, }, .probe = imx6sx_pinctrl_probe, }; diff --git a/drivers/pinctrl/freescale/pinctrl-imx6ul.c b/drivers/pinctrl/freescale/pinctrl-imx6ul.c index 7e37627c63f5..3b8747482e36 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx6ul.c +++ b/drivers/pinctrl/freescale/pinctrl-imx6ul.c @@ -342,7 +342,8 @@ static int imx6ul_pinctrl_probe(struct platform_device *pdev) static struct platform_driver imx6ul_pinctrl_driver = { .driver = { .name = "imx6ul-pinctrl", - .of_match_table = of_match_ptr(imx6ul_pinctrl_of_match), + .of_match_table = imx6ul_pinctrl_of_match, + .suppress_bind_attrs = true, }, .probe = imx6ul_pinctrl_probe, }; diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c b/drivers/pinctrl/freescale/pinctrl-imx7d.c index 369d3e59fdd6..4126387344cb 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx7d.c +++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c @@ -386,7 +386,8 @@ static int imx7d_pinctrl_probe(struct platform_device *pdev) static struct platform_driver imx7d_pinctrl_driver = { .driver = { .name = "imx7d-pinctrl", - .of_match_table = of_match_ptr(imx7d_pinctrl_of_match), + .of_match_table = imx7d_pinctrl_of_match, + .suppress_bind_attrs = true, }, .probe = imx7d_pinctrl_probe, }; diff --git a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c index 922ff73c7087..1915378d92b2 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c +++ b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c @@ -303,7 +303,7 @@ static int imx7ulp_pinctrl_probe(struct platform_device *pdev) static struct platform_driver imx7ulp_pinctrl_driver = { .driver = { .name = "imx7ulp-pinctrl", - .of_match_table = of_match_ptr(imx7ulp_pinctrl_of_match), + .of_match_table = imx7ulp_pinctrl_of_match, .suppress_bind_attrs = true, }, .probe = imx7ulp_pinctrl_probe, diff --git a/drivers/pinctrl/freescale/pinctrl-imx8dxl.c b/drivers/pinctrl/freescale/pinctrl-imx8dxl.c index d3020c0cd55d..041455c13d0d 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8dxl.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8dxl.c @@ -184,7 +184,7 @@ static int imx8dxl_pinctrl_probe(struct platform_device *pdev) static struct platform_driver imx8dxl_pinctrl_driver = { .driver = { .name = "fsl,imx8dxl-iomuxc", - .of_match_table = of_match_ptr(imx8dxl_pinctrl_of_match), + .of_match_table = imx8dxl_pinctrl_of_match, .suppress_bind_attrs = true, }, .probe = imx8dxl_pinctrl_probe, diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mm.c b/drivers/pinctrl/freescale/pinctrl-imx8mm.c index 31c5d8861406..39dc73281ce6 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8mm.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8mm.c @@ -337,7 +337,7 @@ static int imx8mm_pinctrl_probe(struct platform_device *pdev) static struct platform_driver imx8mm_pinctrl_driver = { .driver = { .name = "imx8mm-pinctrl", - .of_match_table = of_match_ptr(imx8mm_pinctrl_of_match), + .of_match_table = imx8mm_pinctrl_of_match, .suppress_bind_attrs = true, }, .probe = imx8mm_pinctrl_probe, diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mn.c b/drivers/pinctrl/freescale/pinctrl-imx8mn.c index 14c9deb51fec..448a79eb4568 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8mn.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8mn.c @@ -337,7 +337,7 @@ static int imx8mn_pinctrl_probe(struct platform_device *pdev) static struct platform_driver imx8mn_pinctrl_driver = { .driver = { .name = "imx8mn-pinctrl", - .of_match_table = of_match_ptr(imx8mn_pinctrl_of_match), + .of_match_table = imx8mn_pinctrl_of_match, .suppress_bind_attrs = true, }, .probe = imx8mn_pinctrl_probe, diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mp.c b/drivers/pinctrl/freescale/pinctrl-imx8mp.c index bf4bbb5e2446..88abc257318f 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8mp.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8mp.c @@ -335,7 +335,8 @@ static int imx8mp_pinctrl_probe(struct platform_device *pdev) static struct platform_driver imx8mp_pinctrl_driver = { .driver = { .name = "imx8mp-pinctrl", - .of_match_table = of_match_ptr(imx8mp_pinctrl_of_match), + .of_match_table = imx8mp_pinctrl_of_match, + .suppress_bind_attrs = true, }, .probe = imx8mp_pinctrl_probe, }; diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mq.c b/drivers/pinctrl/freescale/pinctrl-imx8mq.c index ae3ea5b5c204..3ed3c98bcedb 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8mq.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8mq.c @@ -340,7 +340,7 @@ static int imx8mq_pinctrl_probe(struct platform_device *pdev) static struct platform_driver imx8mq_pinctrl_driver = { .driver = { .name = "imx8mq-pinctrl", - .of_match_table = of_match_ptr(imx8mq_pinctrl_of_match), + .of_match_table = imx8mq_pinctrl_of_match, .pm = &imx_pinctrl_pm_ops, .suppress_bind_attrs = true, }, diff --git a/drivers/pinctrl/freescale/pinctrl-imx8qm.c b/drivers/pinctrl/freescale/pinctrl-imx8qm.c index 8f46b9404cd7..2e2d30dc13f7 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8qm.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8qm.c @@ -317,7 +317,7 @@ static int imx8qm_pinctrl_probe(struct platform_device *pdev) static struct platform_driver imx8qm_pinctrl_driver = { .driver = { .name = "imx8qm-pinctrl", - .of_match_table = of_match_ptr(imx8qm_pinctrl_of_match), + .of_match_table = imx8qm_pinctrl_of_match, .suppress_bind_attrs = true, }, .probe = imx8qm_pinctrl_probe, diff --git a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c index 6776ad6a3a27..4f97813ba8b7 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c @@ -223,7 +223,7 @@ static int imx8qxp_pinctrl_probe(struct platform_device *pdev) static struct platform_driver imx8qxp_pinctrl_driver = { .driver = { .name = "imx8qxp-pinctrl", - .of_match_table = of_match_ptr(imx8qxp_pinctrl_of_match), + .of_match_table = imx8qxp_pinctrl_of_match, .suppress_bind_attrs = true, }, .probe = imx8qxp_pinctrl_probe, diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c index 37602b053ed2..700e5a136814 100644 --- a/drivers/pinctrl/freescale/pinctrl-vf610.c +++ b/drivers/pinctrl/freescale/pinctrl-vf610.c @@ -336,6 +336,7 @@ static struct platform_driver vf610_pinctrl_driver = { .driver = { .name = "vf610-pinctrl", .of_match_table = vf610_pinctrl_of_match, + .suppress_bind_attrs = true, }, .probe = vf610_pinctrl_probe, }; diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 9f3361c13ded..85750974d182 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1173,16 +1173,15 @@ static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, for (gpp = 0; gpp < community->ngpps; gpp++) { const struct intel_padgroup *padgrp = &community->gpps[gpp]; unsigned long pending, enabled, gpp_offset; - unsigned long flags; - raw_spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock(&pctrl->lock); pending = readl(community->regs + community->is_offset + padgrp->reg_num * 4); enabled = readl(community->regs + community->ie_offset + padgrp->reg_num * 4); - raw_spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock(&pctrl->lock); /* Only interrupts that are enabled */ pending &= enabled; diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index eef17f228669..90f0c8255eaf 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -147,6 +147,12 @@ config PINCTRL_MT8192 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS +config PINCTRL_MT8195 + bool "Mediatek MT8195 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + select PINCTRL_MTK_PARIS + config PINCTRL_MT8516 bool "Mediatek MT8516 pin control" depends on OF diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 01218bf4dc30..06fde993ace2 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -21,5 +21,6 @@ obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o +obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index 0fa7de43bc4c..3a4a23c40a71 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -619,6 +619,8 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev, hw->nbase = hw->soc->nbase_names; + spin_lock_init(&hw->lock); + /* Copy from internal struct mtk_pin_desc to register to the core */ pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins), GFP_KERNEL); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8195.c b/drivers/pinctrl/mediatek/pinctrl-mt8195.c new file mode 100644 index 000000000000..a7500e18bb1d --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c @@ -0,0 +1,850 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Zhiyong Tao <zhiyong.tao@mediatek.com> + * + */ + +#include "pinctrl-mtk-mt8195.h" +#include "pinctrl-paris.h" + +/* MT8195 have multiple bases to program pin configuration listed as the below: + * iocfg[0]:0x10005000, iocfg[1]:0x11d10000, iocfg[2]:0x11d30000, + * iocfg[3]:0x11d40000, iocfg[4]:0x11e20000, iocfg[5]:0x11eb0000, + * iocfg[6]:0x11f40000. + * _i_based could be used to indicate what base the pin should be mapped into. + */ + +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ + 32, 0) + +#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ + 32, 1) + +static const struct mtk_pin_field_calc mt8195_pin_mode_range[] = { + PIN_FIELD(0, 144, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt8195_pin_dir_range[] = { + PIN_FIELD(0, 144, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_di_range[] = { + PIN_FIELD(0, 144, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_do_range[] = { + PIN_FIELD(0, 144, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, 4, 0x040, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 4, 0x040, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, 4, 0x040, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, 4, 0x040, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, 4, 0x040, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, 4, 0x040, 0x10, 5, 1), + PIN_FIELD_BASE(6, 6, 4, 0x040, 0x10, 6, 1), + PIN_FIELD_BASE(7, 7, 4, 0x040, 0x10, 7, 1), + PIN_FIELD_BASE(8, 8, 4, 0x040, 0x10, 13, 1), + PIN_FIELD_BASE(9, 9, 4, 0x040, 0x10, 8, 1), + PIN_FIELD_BASE(10, 10, 4, 0x040, 0x10, 14, 1), + PIN_FIELD_BASE(11, 11, 4, 0x040, 0x10, 9, 1), + PIN_FIELD_BASE(12, 12, 4, 0x040, 0x10, 15, 1), + PIN_FIELD_BASE(13, 13, 4, 0x040, 0x10, 10, 1), + PIN_FIELD_BASE(14, 14, 4, 0x040, 0x10, 16, 1), + PIN_FIELD_BASE(15, 15, 4, 0x040, 0x10, 11, 1), + PIN_FIELD_BASE(16, 16, 4, 0x040, 0x10, 17, 1), + PIN_FIELD_BASE(17, 17, 4, 0x040, 0x10, 12, 1), + PIN_FIELD_BASE(18, 18, 2, 0x040, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, 2, 0x040, 0x10, 12, 1), + PIN_FIELD_BASE(20, 20, 2, 0x040, 0x10, 11, 1), + PIN_FIELD_BASE(21, 21, 2, 0x040, 0x10, 10, 1), + PIN_FIELD_BASE(22, 22, 2, 0x040, 0x10, 0, 1), + PIN_FIELD_BASE(23, 23, 2, 0x040, 0x10, 1, 1), + PIN_FIELD_BASE(24, 24, 2, 0x040, 0x10, 2, 1), + PIN_FIELD_BASE(25, 25, 2, 0x040, 0x10, 4, 1), + PIN_FIELD_BASE(26, 26, 2, 0x040, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, 2, 0x040, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, 2, 0x040, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, 2, 0x040, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, 2, 0x040, 0x10, 9, 1), + PIN_FIELD_BASE(31, 31, 1, 0x060, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, 1, 0x060, 0x10, 12, 1), + PIN_FIELD_BASE(33, 33, 1, 0x060, 0x10, 11, 1), + PIN_FIELD_BASE(34, 34, 1, 0x060, 0x10, 14, 1), + PIN_FIELD_BASE(35, 35, 1, 0x060, 0x10, 15, 1), + PIN_FIELD_BASE(36, 36, 1, 0x070, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, 1, 0x070, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, 1, 0x070, 0x10, 4, 1), + PIN_FIELD_BASE(39, 39, 1, 0x070, 0x10, 5, 1), + PIN_FIELD_BASE(40, 40, 1, 0x070, 0x10, 8, 1), + PIN_FIELD_BASE(41, 41, 1, 0x070, 0x10, 7, 1), + PIN_FIELD_BASE(42, 42, 1, 0x070, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, 1, 0x070, 0x10, 9, 1), + PIN_FIELD_BASE(44, 44, 1, 0x070, 0x10, 20, 1), + PIN_FIELD_BASE(45, 45, 1, 0x070, 0x10, 21, 1), + PIN_FIELD_BASE(46, 46, 1, 0x060, 0x10, 18, 1), + PIN_FIELD_BASE(47, 47, 1, 0x060, 0x10, 16, 1), + PIN_FIELD_BASE(48, 48, 1, 0x060, 0x10, 19, 1), + PIN_FIELD_BASE(49, 49, 1, 0x060, 0x10, 17, 1), + PIN_FIELD_BASE(50, 50, 1, 0x060, 0x10, 25, 1), + PIN_FIELD_BASE(51, 51, 1, 0x060, 0x10, 20, 1), + PIN_FIELD_BASE(52, 52, 1, 0x060, 0x10, 26, 1), + PIN_FIELD_BASE(53, 53, 1, 0x060, 0x10, 21, 1), + PIN_FIELD_BASE(54, 54, 1, 0x060, 0x10, 22, 1), + PIN_FIELD_BASE(55, 55, 1, 0x060, 0x10, 23, 1), + PIN_FIELD_BASE(56, 56, 1, 0x060, 0x10, 24, 1), + PIN_FIELD_BASE(57, 57, 1, 0x060, 0x10, 29, 1), + PIN_FIELD_BASE(58, 58, 1, 0x060, 0x10, 27, 1), + PIN_FIELD_BASE(59, 59, 1, 0x060, 0x10, 30, 1), + PIN_FIELD_BASE(60, 60, 1, 0x060, 0x10, 28, 1), + PIN_FIELD_BASE(61, 61, 1, 0x060, 0x10, 8, 1), + PIN_FIELD_BASE(62, 62, 1, 0x060, 0x10, 7, 1), + PIN_FIELD_BASE(63, 63, 1, 0x060, 0x10, 10, 1), + PIN_FIELD_BASE(64, 64, 1, 0x060, 0x10, 9, 1), + PIN_FIELD_BASE(65, 65, 1, 0x070, 0x10, 1, 1), + PIN_FIELD_BASE(66, 66, 1, 0x060, 0x10, 31, 1), + PIN_FIELD_BASE(67, 67, 1, 0x070, 0x10, 0, 1), + PIN_FIELD_BASE(68, 68, 1, 0x070, 0x10, 2, 1), + PIN_FIELD_BASE(69, 69, 1, 0x060, 0x10, 0, 1), + PIN_FIELD_BASE(70, 70, 1, 0x060, 0x10, 6, 1), + PIN_FIELD_BASE(71, 71, 1, 0x060, 0x10, 4, 1), + PIN_FIELD_BASE(72, 72, 1, 0x060, 0x10, 5, 1), + PIN_FIELD_BASE(73, 73, 1, 0x060, 0x10, 1, 1), + PIN_FIELD_BASE(74, 74, 1, 0x060, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, 1, 0x060, 0x10, 3, 1), + PIN_FIELD_BASE(76, 76, 1, 0x070, 0x10, 11, 1), + PIN_FIELD_BASE(77, 77, 3, 0x030, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, 3, 0x030, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, 3, 0x030, 0x10, 9, 1), + PIN_FIELD_BASE(80, 80, 3, 0x030, 0x10, 10, 1), + PIN_FIELD_BASE(81, 81, 3, 0x030, 0x10, 11, 1), + PIN_FIELD_BASE(82, 82, 3, 0x030, 0x10, 12, 1), + PIN_FIELD_BASE(83, 83, 3, 0x030, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, 3, 0x030, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, 3, 0x030, 0x10, 15, 1), + PIN_FIELD_BASE(86, 86, 3, 0x030, 0x10, 16, 1), + PIN_FIELD_BASE(87, 87, 3, 0x030, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, 3, 0x030, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, 3, 0x030, 0x10, 5, 1), + PIN_FIELD_BASE(90, 90, 3, 0x030, 0x10, 6, 1), + PIN_FIELD_BASE(91, 91, 3, 0x030, 0x10, 7, 1), + PIN_FIELD_BASE(92, 92, 3, 0x030, 0x10, 8, 1), + PIN_FIELD_BASE(93, 93, 3, 0x030, 0x10, 18, 1), + PIN_FIELD_BASE(94, 94, 3, 0x030, 0x10, 19, 1), + PIN_FIELD_BASE(95, 95, 3, 0x030, 0x10, 17, 1), + PIN_FIELD_BASE(96, 96, 3, 0x030, 0x10, 0, 1), + PIN_FIELD_BASE(97, 97, 3, 0x030, 0x10, 20, 1), + PIN_FIELD_BASE(98, 98, 3, 0x030, 0x10, 28, 1), + PIN_FIELD_BASE(99, 99, 3, 0x030, 0x10, 27, 1), + PIN_FIELD_BASE(100, 100, 3, 0x030, 0x10, 30, 1), + PIN_FIELD_BASE(101, 101, 3, 0x030, 0x10, 29, 1), + PIN_FIELD_BASE(102, 102, 3, 0x040, 0x10, 0, 1), + PIN_FIELD_BASE(103, 103, 3, 0x030, 0x10, 31, 1), + PIN_FIELD_BASE(104, 104, 3, 0x030, 0x10, 25, 1), + PIN_FIELD_BASE(105, 105, 3, 0x030, 0x10, 26, 1), + PIN_FIELD_BASE(106, 106, 3, 0x030, 0x10, 23, 1), + PIN_FIELD_BASE(107, 107, 3, 0x030, 0x10, 24, 1), + PIN_FIELD_BASE(108, 108, 3, 0x030, 0x10, 22, 1), + PIN_FIELD_BASE(109, 109, 3, 0x030, 0x10, 21, 1), + PIN_FIELD_BASE(110, 110, 5, 0x010, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, 5, 0x010, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, 5, 0x010, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, 5, 0x010, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, 5, 0x010, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, 5, 0x010, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, 6, 0x030, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, 6, 0x030, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, 6, 0x030, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, 6, 0x030, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, 6, 0x030, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, 6, 0x030, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, 6, 0x030, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, 6, 0x030, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, 6, 0x030, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, 6, 0x030, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, 6, 0x030, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, 6, 0x030, 0x10, 10, 1), + PIN_FIELD_BASE(128, 128, 3, 0x040, 0x10, 3, 1), + PIN_FIELD_BASE(129, 129, 3, 0x040, 0x10, 1, 1), + PIN_FIELD_BASE(130, 130, 3, 0x040, 0x10, 4, 1), + PIN_FIELD_BASE(131, 131, 3, 0x040, 0x10, 2, 1), + PIN_FIELD_BASE(132, 132, 6, 0x030, 0x10, 13, 1), + PIN_FIELD_BASE(133, 133, 6, 0x030, 0x10, 12, 1), + PIN_FIELD_BASE(134, 134, 6, 0x030, 0x10, 15, 1), + PIN_FIELD_BASE(135, 135, 6, 0x030, 0x10, 14, 1), + PIN_FIELD_BASE(136, 136, 1, 0x070, 0x10, 13, 1), + PIN_FIELD_BASE(137, 137, 1, 0x070, 0x10, 12, 1), + PIN_FIELD_BASE(138, 138, 1, 0x070, 0x10, 15, 1), + PIN_FIELD_BASE(139, 139, 1, 0x070, 0x10, 14, 1), + PIN_FIELD_BASE(140, 140, 1, 0x070, 0x10, 17, 1), + PIN_FIELD_BASE(141, 141, 1, 0x070, 0x10, 16, 1), + PIN_FIELD_BASE(142, 142, 1, 0x070, 0x10, 19, 1), + PIN_FIELD_BASE(143, 143, 1, 0x070, 0x10, 18, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, 4, 0x0d0, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 4, 0x0d0, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, 4, 0x0d0, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, 4, 0x0d0, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, 4, 0x0d0, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, 4, 0x0d0, 0x10, 5, 1), + PINS_FIELD_BASE(6, 7, 4, 0x0d0, 0x10, 6, 1), + PIN_FIELD_BASE(8, 8, 4, 0x0d0, 0x10, 12, 1), + PIN_FIELD_BASE(9, 9, 4, 0x0d0, 0x10, 7, 1), + PIN_FIELD_BASE(10, 10, 4, 0x0d0, 0x10, 13, 1), + PIN_FIELD_BASE(11, 11, 4, 0x0d0, 0x10, 8, 1), + PIN_FIELD_BASE(12, 12, 4, 0x0d0, 0x10, 14, 1), + PIN_FIELD_BASE(13, 13, 4, 0x0d0, 0x10, 9, 1), + PIN_FIELD_BASE(14, 14, 4, 0x0d0, 0x10, 15, 1), + PIN_FIELD_BASE(15, 15, 4, 0x0d0, 0x10, 10, 1), + PIN_FIELD_BASE(16, 16, 4, 0x0d0, 0x10, 16, 1), + PIN_FIELD_BASE(17, 17, 4, 0x0d0, 0x10, 11, 1), + PIN_FIELD_BASE(18, 18, 2, 0x090, 0x10, 11, 1), + PIN_FIELD_BASE(19, 19, 2, 0x090, 0x10, 10, 1), + PIN_FIELD_BASE(20, 20, 2, 0x090, 0x10, 9, 1), + PIN_FIELD_BASE(21, 21, 2, 0x090, 0x10, 11, 1), + PIN_FIELD_BASE(22, 22, 2, 0x090, 0x10, 0, 1), + PIN_FIELD_BASE(23, 23, 2, 0x090, 0x10, 1, 1), + PIN_FIELD_BASE(24, 24, 2, 0x090, 0x10, 2, 1), + PIN_FIELD_BASE(25, 25, 2, 0x090, 0x10, 4, 1), + PIN_FIELD_BASE(26, 26, 2, 0x090, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, 2, 0x090, 0x10, 5, 1), + PIN_FIELD_BASE(28, 28, 2, 0x090, 0x10, 6, 1), + PIN_FIELD_BASE(29, 29, 2, 0x090, 0x10, 7, 1), + PIN_FIELD_BASE(30, 30, 2, 0x090, 0x10, 8, 1), + PINS_FIELD_BASE(31, 33, 1, 0x0f0, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, 1, 0x0f0, 0x10, 0, 1), + PIN_FIELD_BASE(35, 35, 1, 0x0f0, 0x10, 1, 1), + PIN_FIELD_BASE(36, 36, 1, 0x0f0, 0x10, 4, 1), + PIN_FIELD_BASE(37, 37, 1, 0x0f0, 0x10, 2, 1), + PINS_FIELD_BASE(38, 39, 1, 0x0f0, 0x10, 5, 1), + PIN_FIELD_BASE(40, 40, 1, 0x0f0, 0x10, 14, 1), + PIN_FIELD_BASE(41, 41, 1, 0x0f0, 0x10, 13, 1), + PIN_FIELD_BASE(42, 42, 1, 0x0f0, 0x10, 16, 1), + PIN_FIELD_BASE(43, 43, 1, 0x0f0, 0x10, 15, 1), + PIN_FIELD_BASE(44, 44, 1, 0x0f0, 0x10, 25, 1), + PIN_FIELD_BASE(45, 45, 1, 0x0f0, 0x10, 26, 1), + PINS_FIELD_BASE(46, 47, 1, 0x0f0, 0x10, 5, 1), + PINS_FIELD_BASE(48, 51, 1, 0x0f0, 0x10, 6, 1), + PINS_FIELD_BASE(52, 55, 1, 0x0f0, 0x10, 7, 1), + PINS_FIELD_BASE(56, 59, 1, 0x0f0, 0x10, 8, 1), + PINS_FIELD_BASE(60, 63, 1, 0x0f0, 0x10, 9, 1), + PIN_FIELD_BASE(64, 64, 1, 0x0f0, 0x10, 10, 1), + PINS_FIELD_BASE(65, 68, 1, 0x0f0, 0x10, 3, 1), + PINS_FIELD_BASE(69, 71, 1, 0x0f0, 0x10, 10, 1), + PINS_FIELD_BASE(72, 75, 1, 0x0f0, 0x10, 11, 1), + PIN_FIELD_BASE(76, 76, 1, 0x0f0, 0x10, 12, 1), + PIN_FIELD_BASE(77, 77, 3, 0x0e0, 0x10, 0, 1), + PIN_FIELD_BASE(78, 78, 3, 0x0e0, 0x10, 1, 1), + PIN_FIELD_BASE(79, 79, 3, 0x0e0, 0x10, 6, 1), + PIN_FIELD_BASE(80, 80, 3, 0x0e0, 0x10, 7, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0e0, 0x10, 8, 1), + PIN_FIELD_BASE(82, 82, 3, 0x0e0, 0x10, 9, 1), + PIN_FIELD_BASE(83, 83, 3, 0x0e0, 0x10, 10, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0e0, 0x10, 11, 1), + PINS_FIELD_BASE(85, 88, 3, 0x0e0, 0x10, 14, 1), + PIN_FIELD_BASE(89, 89, 3, 0x0e0, 0x10, 2, 1), + PIN_FIELD_BASE(90, 90, 3, 0x0e0, 0x10, 3, 1), + PIN_FIELD_BASE(91, 91, 3, 0x0e0, 0x10, 4, 1), + PIN_FIELD_BASE(92, 92, 3, 0x0e0, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, 3, 0x0e0, 0x10, 12, 1), + PIN_FIELD_BASE(94, 94, 3, 0x0e0, 0x10, 13, 1), + PINS_FIELD_BASE(95, 98, 3, 0x0e0, 0x10, 15, 1), + PINS_FIELD_BASE(99, 102, 3, 0x0e0, 0x10, 16, 1), + PINS_FIELD_BASE(103, 104, 3, 0x0e0, 0x10, 17, 1), + PIN_FIELD_BASE(105, 105, 3, 0x0e0, 0x10, 18, 1), + PINS_FIELD_BASE(106, 107, 3, 0x0e0, 0x10, 17, 1), + PINS_FIELD_BASE(108, 109, 3, 0x0e0, 0x10, 18, 1), + PIN_FIELD_BASE(110, 110, 5, 0x070, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, 5, 0x070, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, 5, 0x070, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, 5, 0x070, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, 5, 0x070, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, 5, 0x070, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, 6, 0x0c0, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, 6, 0x0c0, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, 6, 0x0c0, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, 6, 0x0c0, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, 6, 0x0c0, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, 6, 0x0c0, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, 6, 0x0c0, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, 6, 0x0c0, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, 6, 0x0c0, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, 6, 0x0c0, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, 6, 0x0c0, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, 6, 0x0c0, 0x10, 10, 1), + PIN_FIELD_BASE(128, 128, 3, 0x0e0, 0x10, 18, 1), + PINS_FIELD_BASE(129, 131, 3, 0x0e0, 0x10, 19, 1), + PIN_FIELD_BASE(132, 132, 6, 0x0c0, 0x10, 13, 1), + PIN_FIELD_BASE(133, 133, 6, 0x0c0, 0x10, 12, 1), + PIN_FIELD_BASE(134, 134, 6, 0x0c0, 0x10, 15, 1), + PIN_FIELD_BASE(135, 135, 6, 0x0c0, 0x10, 14, 1), + PIN_FIELD_BASE(136, 136, 1, 0x0f0, 0x10, 18, 1), + PIN_FIELD_BASE(137, 137, 1, 0x0f0, 0x10, 17, 1), + PIN_FIELD_BASE(138, 138, 1, 0x0f0, 0x10, 20, 1), + PIN_FIELD_BASE(139, 139, 1, 0x0f0, 0x10, 19, 1), + PIN_FIELD_BASE(140, 140, 1, 0x0f0, 0x10, 22, 1), + PIN_FIELD_BASE(141, 141, 1, 0x0f0, 0x10, 21, 1), + PIN_FIELD_BASE(142, 142, 1, 0x0f0, 0x10, 24, 1), + PIN_FIELD_BASE(143, 143, 1, 0x0f0, 0x10, 23, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_pu_range[] = { + PIN_FIELD_BASE(6, 6, 4, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, 4, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(8, 8, 4, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(9, 9, 4, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(10, 10, 4, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, 4, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, 4, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, 4, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(14, 14, 4, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(15, 15, 4, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(16, 16, 4, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(17, 17, 4, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, 2, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, 2, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(20, 20, 2, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(21, 21, 2, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(22, 22, 2, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(23, 23, 2, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(24, 24, 2, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(26, 26, 2, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, 2, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, 2, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, 2, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, 2, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(31, 31, 1, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, 1, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(33, 33, 1, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(34, 34, 1, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(35, 35, 1, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(36, 36, 1, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, 1, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, 1, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(39, 39, 1, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(40, 40, 1, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(41, 41, 1, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(42, 42, 1, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, 1, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(44, 44, 1, 0x00b0, 0x10, 21, 1), + PIN_FIELD_BASE(45, 45, 1, 0x00b0, 0x10, 22, 1), + PIN_FIELD_BASE(46, 46, 1, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(47, 47, 1, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(48, 48, 1, 0x00a0, 0x10, 19, 1), + PIN_FIELD_BASE(49, 49, 1, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(50, 50, 1, 0x00a0, 0x10, 25, 1), + PIN_FIELD_BASE(51, 51, 1, 0x00a0, 0x10, 20, 1), + PIN_FIELD_BASE(52, 52, 1, 0x00a0, 0x10, 26, 1), + PIN_FIELD_BASE(53, 53, 1, 0x00a0, 0x10, 21, 1), + PIN_FIELD_BASE(54, 54, 1, 0x00a0, 0x10, 22, 1), + PIN_FIELD_BASE(55, 55, 1, 0x00a0, 0x10, 23, 1), + PIN_FIELD_BASE(56, 56, 1, 0x00a0, 0x10, 24, 1), + PIN_FIELD_BASE(57, 57, 1, 0x00a0, 0x10, 29, 1), + PIN_FIELD_BASE(58, 58, 1, 0x00a0, 0x10, 27, 1), + PIN_FIELD_BASE(59, 59, 1, 0x00a0, 0x10, 30, 1), + PIN_FIELD_BASE(60, 60, 1, 0x00a0, 0x10, 28, 1), + PIN_FIELD_BASE(61, 61, 1, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(62, 62, 1, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(63, 63, 1, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(64, 64, 1, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(65, 65, 1, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(66, 66, 1, 0x00a0, 0x10, 31, 1), + PIN_FIELD_BASE(67, 67, 1, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(68, 68, 1, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(69, 69, 1, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(70, 70, 1, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(71, 71, 1, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(72, 72, 1, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(73, 73, 1, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(74, 74, 1, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, 1, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(76, 76, 1, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(97, 97, 3, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(98, 98, 3, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(99, 99, 3, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(100, 100, 3, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(101, 101, 3, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(102, 102, 3, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(103, 103, 3, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(108, 108, 3, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(109, 109, 3, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(128, 128, 3, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(129, 129, 3, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(130, 130, 3, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(131, 131, 3, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(132, 132, 6, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(133, 133, 6, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(134, 134, 6, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(135, 135, 6, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(136, 136, 1, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(137, 137, 1, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(138, 138, 1, 0x00b0, 0x10, 16, 1), + PIN_FIELD_BASE(139, 139, 1, 0x00b0, 0x10, 15, 1), + PIN_FIELD_BASE(140, 140, 1, 0x00b0, 0x10, 18, 1), + PIN_FIELD_BASE(141, 141, 1, 0x00b0, 0x10, 17, 1), + PIN_FIELD_BASE(142, 142, 1, 0x00b0, 0x10, 20, 1), + PIN_FIELD_BASE(143, 143, 1, 0x00b0, 0x10, 19, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_pd_range[] = { + PIN_FIELD_BASE(6, 6, 4, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, 4, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(8, 8, 4, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(9, 9, 4, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(10, 10, 4, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, 4, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, 4, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, 4, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(14, 14, 4, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(15, 15, 4, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(16, 16, 4, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(17, 17, 4, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, 2, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, 2, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(20, 20, 2, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(21, 21, 2, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(22, 22, 2, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(23, 23, 2, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(24, 24, 2, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(26, 26, 2, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, 2, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, 2, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, 2, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, 2, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(31, 31, 1, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, 1, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(33, 33, 1, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(34, 34, 1, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(35, 35, 1, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(36, 36, 1, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, 1, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, 1, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(39, 39, 1, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(40, 40, 1, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(41, 41, 1, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(42, 42, 1, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, 1, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(44, 44, 1, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(45, 45, 1, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(46, 46, 1, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(47, 47, 1, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(48, 48, 1, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(49, 49, 1, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(50, 50, 1, 0x0080, 0x10, 25, 1), + PIN_FIELD_BASE(51, 51, 1, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(52, 52, 1, 0x0080, 0x10, 26, 1), + PIN_FIELD_BASE(53, 53, 1, 0x0080, 0x10, 21, 1), + PIN_FIELD_BASE(54, 54, 1, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(55, 55, 1, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(56, 56, 1, 0x0080, 0x10, 24, 1), + PIN_FIELD_BASE(57, 57, 1, 0x0080, 0x10, 29, 1), + PIN_FIELD_BASE(58, 58, 1, 0x0080, 0x10, 27, 1), + PIN_FIELD_BASE(59, 59, 1, 0x0080, 0x10, 30, 1), + PIN_FIELD_BASE(60, 60, 1, 0x0080, 0x10, 28, 1), + PIN_FIELD_BASE(61, 61, 1, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(62, 62, 1, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(63, 63, 1, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(64, 64, 1, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(65, 65, 1, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(66, 66, 1, 0x0080, 0x10, 31, 1), + PIN_FIELD_BASE(67, 67, 1, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(68, 68, 1, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(69, 69, 1, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(70, 70, 1, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(71, 71, 1, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(72, 72, 1, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(73, 73, 1, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(74, 74, 1, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, 1, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(76, 76, 1, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(97, 97, 3, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(98, 98, 3, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(99, 99, 3, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(100, 100, 3, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(101, 101, 3, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(102, 102, 3, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(103, 103, 3, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(108, 108, 3, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(109, 109, 3, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(128, 128, 3, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(129, 129, 3, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(130, 130, 3, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(131, 131, 3, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(132, 132, 6, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(133, 133, 6, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(134, 134, 6, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(135, 135, 6, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(136, 136, 1, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(137, 137, 1, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(138, 138, 1, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(139, 139, 1, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(140, 140, 1, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(141, 141, 1, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(142, 142, 1, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(143, 143, 1, 0x0090, 0x10, 19, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_pupd_range[] = { + PIN_FIELD_BASE(0, 0, 4, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 4, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, 4, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, 4, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, 4, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, 4, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(77, 77, 3, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, 3, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, 3, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(80, 80, 3, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(82, 82, 3, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(83, 83, 3, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, 3, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(86, 86, 3, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(87, 87, 3, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, 3, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, 3, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(90, 90, 3, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(91, 91, 3, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(92, 92, 3, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(93, 93, 3, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(94, 94, 3, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(95, 95, 3, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(96, 96, 3, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, 3, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(105, 105, 3, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(106, 106, 3, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(107, 107, 3, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(110, 110, 5, 0x0020, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, 5, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, 5, 0x0020, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, 5, 0x0020, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, 5, 0x0020, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, 5, 0x0020, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, 6, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, 6, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, 6, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, 6, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, 6, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, 6, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, 6, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, 6, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, 6, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, 6, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, 6, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, 6, 0x0050, 0x10, 10, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_r0_range[] = { + PIN_FIELD_BASE(0, 0, 4, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 4, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, 4, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, 4, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, 4, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, 4, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(77, 77, 3, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, 3, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, 3, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(80, 80, 3, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(82, 82, 3, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(83, 83, 3, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, 3, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(86, 86, 3, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(87, 87, 3, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, 3, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, 3, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(90, 90, 3, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(91, 91, 3, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(92, 92, 3, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(93, 93, 3, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(94, 94, 3, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(95, 95, 3, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(96, 96, 3, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, 3, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(105, 105, 3, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(106, 106, 3, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(107, 107, 3, 0x0080, 0x10, 21, 1), + PIN_FIELD_BASE(110, 110, 5, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, 5, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, 5, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, 5, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, 5, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, 5, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, 6, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, 6, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, 6, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, 6, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, 6, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, 6, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, 6, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, 6, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, 6, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, 6, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, 6, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, 6, 0x0070, 0x10, 10, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_r1_range[] = { + PIN_FIELD_BASE(0, 0, 4, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 4, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, 4, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, 4, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, 4, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, 4, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(77, 77, 3, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, 3, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, 3, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(80, 80, 3, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(82, 82, 3, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(83, 83, 3, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, 3, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(86, 86, 3, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(87, 87, 3, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, 3, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, 3, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(90, 90, 3, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(91, 91, 3, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(92, 92, 3, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(93, 93, 3, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(94, 94, 3, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(95, 95, 3, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(96, 96, 3, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, 3, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(105, 105, 3, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(106, 106, 3, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(107, 107, 3, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(110, 110, 5, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, 5, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, 5, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, 5, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, 5, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, 5, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, 6, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, 6, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, 6, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, 6, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, 6, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, 6, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, 6, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, 6, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, 6, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, 6, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, 6, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, 6, 0x0080, 0x10, 10, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, 4, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(1, 1, 4, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(2, 2, 4, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(3, 3, 4, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(4, 4, 4, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(5, 5, 4, 0x000, 0x10, 15, 3), + PINS_FIELD_BASE(6, 7, 4, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(8, 8, 4, 0x010, 0x10, 6, 3), + PIN_FIELD_BASE(9, 9, 4, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(10, 10, 4, 0x010, 0x10, 9, 3), + PIN_FIELD_BASE(11, 11, 4, 0x000, 0x10, 24, 3), + PIN_FIELD_BASE(12, 12, 4, 0x010, 0x10, 12, 3), + PIN_FIELD_BASE(13, 13, 4, 0x010, 0x10, 27, 3), + PIN_FIELD_BASE(14, 14, 4, 0x010, 0x10, 15, 3), + PIN_FIELD_BASE(15, 15, 4, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(16, 16, 4, 0x010, 0x10, 18, 3), + PIN_FIELD_BASE(17, 17, 4, 0x010, 0x10, 3, 3), + PIN_FIELD_BASE(18, 18, 2, 0x010, 0x10, 6, 3), + PIN_FIELD_BASE(19, 19, 2, 0x010, 0x10, 3, 3), + PIN_FIELD_BASE(20, 20, 2, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(21, 21, 2, 0x000, 0x10, 27, 3), + PIN_FIELD_BASE(22, 22, 2, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(23, 23, 2, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(24, 24, 2, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(25, 25, 2, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(26, 26, 2, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(27, 27, 2, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(28, 28, 2, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(29, 29, 2, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(30, 30, 2, 0x000, 0x10, 24, 3), + PINS_FIELD_BASE(31, 33, 1, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(34, 34, 1, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(35, 35, 1, 0x000, 0x10, 24, 3), + PIN_FIELD_BASE(36, 36, 1, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(37, 37, 1, 0x010, 0x10, 21, 3), + PINS_FIELD_BASE(38, 39, 1, 0x010, 0x10, 3, 3), + PIN_FIELD_BASE(40, 40, 1, 0x010, 0x10, 27, 3), + PIN_FIELD_BASE(41, 41, 1, 0x010, 0x10, 24, 3), + PIN_FIELD_BASE(42, 42, 1, 0x020, 0x10, 3, 3), + PIN_FIELD_BASE(43, 43, 1, 0x020, 0x10, 0, 3), + PIN_FIELD_BASE(44, 44, 1, 0x030, 0x10, 0, 3), + PIN_FIELD_BASE(45, 45, 1, 0x030, 0x10, 3, 3), + PINS_FIELD_BASE(46, 47, 1, 0x010, 0x10, 3, 3), + PINS_FIELD_BASE(48, 51, 1, 0x010, 0x10, 6, 3), + PINS_FIELD_BASE(52, 55, 1, 0x010, 0x10, 9, 3), + PINS_FIELD_BASE(56, 59, 1, 0x010, 0x10, 12, 3), + PINS_FIELD_BASE(60, 63, 1, 0x010, 0x10, 15, 3), + PIN_FIELD_BASE(64, 64, 1, 0x010, 0x10, 18, 3), + PINS_FIELD_BASE(65, 68, 1, 0x000, 0x10, 27, 3), + PIN_FIELD_BASE(69, 69, 1, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(70, 70, 1, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(71, 71, 1, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(72, 72, 1, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(73, 73, 1, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(74, 74, 1, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(75, 75, 1, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(76, 76, 1, 0x010, 0x10, 18, 3), + PIN_FIELD_BASE(77, 77, 3, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(78, 78, 3, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(79, 79, 3, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(80, 80, 3, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(81, 81, 3, 0x000, 0x10, 28, 3), + PIN_FIELD_BASE(82, 82, 3, 0x000, 0x10, 27, 3), + PIN_FIELD_BASE(83, 83, 3, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(84, 84, 3, 0x010, 0x10, 3, 3), + PINS_FIELD_BASE(85, 88, 3, 0x010, 0x10, 15, 3), + PIN_FIELD_BASE(89, 89, 3, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(90, 90, 3, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(91, 91, 3, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(92, 92, 3, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(93, 93, 3, 0x010, 0x10, 6, 3), + PIN_FIELD_BASE(94, 94, 3, 0x010, 0x10, 9, 3), + PINS_FIELD_BASE(95, 98, 3, 0x010, 0x10, 18, 3), + PINS_FIELD_BASE(99, 102, 3, 0x010, 0x10, 21, 3), + PINS_FIELD_BASE(103, 104, 3, 0x010, 0x10, 24, 3), + PIN_FIELD_BASE(105, 105, 3, 0x010, 0x10, 27, 3), + PINS_FIELD_BASE(106, 107, 3, 0x010, 0x10, 24, 3), + PINS_FIELD_BASE(108, 109, 3, 0x010, 0x10, 27, 3), + PIN_FIELD_BASE(110, 110, 5, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(111, 111, 5, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(112, 112, 5, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(113, 113, 5, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(114, 114, 5, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(115, 115, 5, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(116, 116, 6, 0x000, 0x10, 27, 3), + PIN_FIELD_BASE(117, 117, 6, 0x000, 0x10, 24, 3), + PIN_FIELD_BASE(118, 118, 6, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(119, 119, 6, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(120, 120, 6, 0x010, 0x10, 3, 3), + PIN_FIELD_BASE(121, 121, 6, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(122, 122, 6, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(123, 123, 6, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(124, 124, 6, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(125, 125, 6, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(126, 126, 6, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(127, 127, 6, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(128, 128, 3, 0x010, 0x10, 27, 3), + PINS_FIELD_BASE(129, 130, 3, 0x020, 0x10, 0, 3), + PINS_FIELD_BASE(131, 131, 3, 0x010, 0x10, 12, 3), + PIN_FIELD_BASE(132, 132, 6, 0x010, 0x10, 9, 3), + PIN_FIELD_BASE(133, 133, 6, 0x010, 0x10, 6, 3), + PIN_FIELD_BASE(134, 134, 6, 0x010, 0x10, 15, 3), + PIN_FIELD_BASE(135, 135, 6, 0x010, 0x10, 12, 3), + PIN_FIELD_BASE(136, 136, 1, 0x020, 0x10, 9, 3), + PIN_FIELD_BASE(137, 137, 1, 0x020, 0x10, 6, 3), + PIN_FIELD_BASE(138, 138, 1, 0x020, 0x10, 15, 3), + PIN_FIELD_BASE(139, 139, 1, 0x020, 0x10, 12, 3), + PIN_FIELD_BASE(140, 140, 1, 0x020, 0x10, 21, 3), + PIN_FIELD_BASE(141, 141, 1, 0x020, 0x10, 18, 3), + PIN_FIELD_BASE(142, 142, 1, 0x020, 0x10, 27, 3), + PIN_FIELD_BASE(143, 143, 1, 0x020, 0x10, 24, 3), +}; + +static const struct mtk_pin_field_calc mt8195_pin_drv_adv_range[] = { + PIN_FIELD_BASE(8, 8, 4, 0x020, 0x10, 15, 3), + PIN_FIELD_BASE(9, 9, 4, 0x020, 0x10, 0, 3), + PIN_FIELD_BASE(10, 10, 4, 0x020, 0x10, 18, 3), + PIN_FIELD_BASE(11, 11, 4, 0x020, 0x10, 3, 3), + PIN_FIELD_BASE(12, 12, 4, 0x020, 0x10, 21, 3), + PIN_FIELD_BASE(13, 13, 4, 0x020, 0x10, 6, 3), + PIN_FIELD_BASE(14, 14, 4, 0x020, 0x10, 24, 3), + PIN_FIELD_BASE(15, 15, 4, 0x020, 0x10, 9, 3), + PIN_FIELD_BASE(16, 16, 4, 0x020, 0x10, 27, 3), + PIN_FIELD_BASE(17, 17, 4, 0x020, 0x10, 12, 3), + PIN_FIELD_BASE(29, 29, 2, 0x020, 0x10, 0, 3), + PIN_FIELD_BASE(30, 30, 2, 0x020, 0x10, 3, 3), + PIN_FIELD_BASE(34, 34, 1, 0x040, 0x10, 0, 3), + PIN_FIELD_BASE(35, 35, 1, 0x040, 0x10, 3, 3), + PIN_FIELD_BASE(44, 44, 1, 0x040, 0x10, 6, 3), + PIN_FIELD_BASE(45, 45, 1, 0x040, 0x10, 9, 3), +}; + +static const struct mtk_pin_reg_calc mt8195_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8195_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8195_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8195_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8195_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8195_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8195_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8195_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8195_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8195_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8195_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8195_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8195_pin_r1_range), + [PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8195_pin_drv_adv_range), +}; + +static const char * const mt8195_pinctrl_register_base_names[] = { + "iocfg0", "iocfg_bm", "iocfg_bl", "iocfg_br", "iocfg_lm", + "iocfg_rb", "iocfg_tl", +}; + +static const struct mtk_eint_hw mt8195_eint_hw = { + .port_mask = 0xf, + .ports = 7, + .ap_num = 225, + .db_cnt = 32, +}; + +static const struct mtk_pin_soc mt8195_data = { + .reg_cal = mt8195_reg_cals, + .pins = mtk_pins_mt8195, + .npins = ARRAY_SIZE(mtk_pins_mt8195), + .ngrps = ARRAY_SIZE(mtk_pins_mt8195), + .eint_hw = &mt8195_eint_hw, + .nfuncs = 8, + .gpio_m = 0, + .base_names = mt8195_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt8195_pinctrl_register_base_names), + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_drive_get = mtk_pinconf_adv_drive_get_raw, + .adv_drive_set = mtk_pinconf_adv_drive_set_raw, +}; + +static const struct of_device_id mt8195_pinctrl_of_match[] = { + { .compatible = "mediatek,mt8195-pinctrl", }, + { } +}; + +static int mt8195_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_paris_pinctrl_probe(pdev, &mt8195_data); +} + +static struct platform_driver mt8195_pinctrl_driver = { + .driver = { + .name = "mt8195-pinctrl", + .of_match_table = mt8195_pinctrl_of_match, + }, + .probe = mt8195_pinctrl_probe, +}; + +static int __init mt8195_pinctrl_init(void) +{ + return platform_driver_register(&mt8195_pinctrl_driver); +} +arch_initcall(mt8195_pinctrl_init); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index 72f17f26acd8..5b3b048725cc 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -57,11 +57,16 @@ static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg) void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set) { u32 val; + unsigned long flags; + + spin_lock_irqsave(&pctl->lock, flags); val = mtk_r32(pctl, i, reg); val &= ~mask; val |= set; mtk_w32(pctl, i, reg, val); + + spin_unlock_irqrestore(&pctl->lock, flags); } static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, @@ -1027,6 +1032,20 @@ int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, } EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get); +int mtk_pinconf_adv_drive_set_raw(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, u32 arg) +{ + return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_ADV, arg); +} +EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set_raw); + +int mtk_pinconf_adv_drive_get_raw(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, u32 *val) +{ + return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_ADV, val); +} +EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get_raw); + MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); MODULE_DESCRIPTION("Pin configuration library module for mediatek SoCs"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h index e2aae285b5fc..a6f1bdb2083b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h @@ -66,6 +66,7 @@ enum { PINCTRL_PIN_REG_DRV_EN, PINCTRL_PIN_REG_DRV_E0, PINCTRL_PIN_REG_DRV_E1, + PINCTRL_PIN_REG_DRV_ADV, PINCTRL_PIN_REG_MAX, }; @@ -251,6 +252,8 @@ struct mtk_pinctrl { struct mtk_eint *eint; struct mtk_pinctrl_group *groups; const char **grp_names; + /* lock pin's register resource to avoid multiple threads issue*/ + spinlock_t lock; }; void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set); @@ -314,6 +317,10 @@ int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 arg); int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 *val); +int mtk_pinconf_adv_drive_set_raw(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, u32 arg); +int mtk_pinconf_adv_drive_get_raw(struct mtk_pinctrl *hw, + const struct mtk_pin_desc *desc, u32 *val); bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n); #endif /* __PINCTRL_MTK_COMMON_V2_H */ diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8195.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8195.h new file mode 100644 index 000000000000..de4a8a80bf1d --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8195.h @@ -0,0 +1,1669 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Zhiyong Tao <zhiyong.tao@mediatek.com> + * + */ + +#ifndef __PINCTRL_MTK_MT8195_H +#define __PINCTRL_MTK_MT8195_H + +#include "pinctrl-paris.h" + +static const struct mtk_pin_desc mtk_pins_mt8195[] = { + MTK_PIN( + 0, "GPIO0", + MTK_EINT_FUNCTION(0, 0), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "TP_GPIO0_AO"), + MTK_FUNCTION(2, "MSDC2_CMD"), + MTK_FUNCTION(3, "TDMIN_MCK"), + MTK_FUNCTION(4, "CLKM0"), + MTK_FUNCTION(5, "PERSTN_1"), + MTK_FUNCTION(6, "IDDIG_1P"), + MTK_FUNCTION(7, "DMIC4_CLK") + ), + MTK_PIN( + 1, "GPIO1", + MTK_EINT_FUNCTION(0, 1), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "TP_GPIO1_AO"), + MTK_FUNCTION(2, "MSDC2_CLK"), + MTK_FUNCTION(3, "TDMIN_DI"), + MTK_FUNCTION(4, "CLKM1"), + MTK_FUNCTION(5, "CLKREQN_1"), + MTK_FUNCTION(6, "USB_DRVVBUS_1P"), + MTK_FUNCTION(7, "DMIC4_DAT") + ), + MTK_PIN( + 2, "GPIO2", + MTK_EINT_FUNCTION(0, 2), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "TP_GPIO2_AO"), + MTK_FUNCTION(2, "MSDC2_DAT3"), + MTK_FUNCTION(3, "TDMIN_LRCK"), + MTK_FUNCTION(4, "CLKM2"), + MTK_FUNCTION(5, "WAKEN_1"), + MTK_FUNCTION(7, "DMIC2_CLK") + ), + MTK_PIN( + 3, "GPIO3", + MTK_EINT_FUNCTION(0, 3), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "TP_GPIO3_AO"), + MTK_FUNCTION(2, "MSDC2_DAT0"), + MTK_FUNCTION(3, "TDMIN_BCK"), + MTK_FUNCTION(4, "CLKM3"), + MTK_FUNCTION(7, "DMIC2_DAT") + ), + MTK_PIN( + 4, "GPIO4", + MTK_EINT_FUNCTION(0, 4), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "TP_GPIO4_AO"), + MTK_FUNCTION(2, "MSDC2_DAT2"), + MTK_FUNCTION(3, "SPDIF_IN1"), + MTK_FUNCTION(4, "UTXD3"), + MTK_FUNCTION(5, "SDA2"), + MTK_FUNCTION(7, "IDDIG_2P") + ), + MTK_PIN( + 5, "GPIO5", + MTK_EINT_FUNCTION(0, 5), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "TP_GPIO5_AO"), + MTK_FUNCTION(2, "MSDC2_DAT1"), + MTK_FUNCTION(3, "SPDIF_IN0"), + MTK_FUNCTION(4, "URXD3"), + MTK_FUNCTION(5, "SCL2"), + MTK_FUNCTION(7, "USB_DRVVBUS_2P") + ), + MTK_PIN( + 6, "GPIO6", + MTK_EINT_FUNCTION(0, 6), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "TP_GPIO6_AO"), + MTK_FUNCTION(2, "DP_TX_HPD"), + MTK_FUNCTION(3, "I2SO1_D4"), + MTK_FUNCTION(4, "UTXD4"), + MTK_FUNCTION(5, "CMVREF3"), + MTK_FUNCTION(7, "DMIC3_CLK") + ), + MTK_PIN( + 7, "GPIO7", + MTK_EINT_FUNCTION(0, 7), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "TP_GPIO7_AO"), + MTK_FUNCTION(2, "EDP_TX_HPD"), + MTK_FUNCTION(3, "I2SO1_D5"), + MTK_FUNCTION(4, "URXD4"), + MTK_FUNCTION(5, "CMVREF4"), + MTK_FUNCTION(7, "DMIC3_DAT") + ), + MTK_PIN( + 8, "GPIO8", + MTK_EINT_FUNCTION(0, 8), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "SDA0"), + MTK_FUNCTION(2, "PWM_0"), + MTK_FUNCTION(4, "SPDIF_OUT"), + MTK_FUNCTION(6, "LVTS_FOUT"), + MTK_FUNCTION(7, "DBG_MON_A0") + ), + MTK_PIN( + 9, "GPIO9", + MTK_EINT_FUNCTION(0, 9), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "SCL0"), + MTK_FUNCTION(2, "PWM_1"), + MTK_FUNCTION(4, "IR_IN"), + MTK_FUNCTION(6, "LVTS_SDO"), + MTK_FUNCTION(7, "DBG_MON_A1") + ), + MTK_PIN( + 10, "GPIO10", + MTK_EINT_FUNCTION(0, 10), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "SDA1"), + MTK_FUNCTION(2, "PWM_2"), + MTK_FUNCTION(3, "ADSP_URXD0"), + MTK_FUNCTION(4, "SPDIF_IN1"), + MTK_FUNCTION(6, "LVTS_SCF"), + MTK_FUNCTION(7, "DBG_MON_A2") + ), + MTK_PIN( + 11, "GPIO11", + MTK_EINT_FUNCTION(0, 11), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "SCL1"), + MTK_FUNCTION(2, "PWM_3"), + MTK_FUNCTION(3, "ADSP_UTXD0"), + MTK_FUNCTION(4, "SPDIF_IN0"), + MTK_FUNCTION(6, "LVTS_SCK"), + MTK_FUNCTION(7, "DBG_MON_A3") + ), + MTK_PIN( + 12, "GPIO12", + MTK_EINT_FUNCTION(0, 12), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "SDA2"), + MTK_FUNCTION(2, "DMIC3_DAT_R"), + MTK_FUNCTION(3, "I2SO1_D6"), + MTK_FUNCTION(6, "LVTS_SDI"), + MTK_FUNCTION(7, "DBG_MON_A4") + ), + MTK_PIN( + 13, "GPIO13", + MTK_EINT_FUNCTION(0, 13), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "SCL2"), + MTK_FUNCTION(2, "DMIC4_DAT_R"), + MTK_FUNCTION(3, "I2SO1_D7"), + MTK_FUNCTION(7, "DBG_MON_A5") + ), + MTK_PIN( + 14, "GPIO14", + MTK_EINT_FUNCTION(0, 14), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "SDA3"), + MTK_FUNCTION(2, "DMIC3_DAT"), + MTK_FUNCTION(3, "TDMIN_MCK"), + MTK_FUNCTION(7, "DBG_MON_A6") + ), + MTK_PIN( + 15, "GPIO15", + MTK_EINT_FUNCTION(0, 15), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "SCL3"), + MTK_FUNCTION(2, "DMIC3_CLK"), + MTK_FUNCTION(3, "TDMIN_DI"), + MTK_FUNCTION(7, "DBG_MON_A7") + ), + MTK_PIN( + 16, "GPIO16", + MTK_EINT_FUNCTION(0, 16), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "SDA4"), + MTK_FUNCTION(2, "DMIC4_DAT"), + MTK_FUNCTION(3, "TDMIN_LRCK"), + MTK_FUNCTION(7, "DBG_MON_A8") + ), + MTK_PIN( + 17, "GPIO17", + MTK_EINT_FUNCTION(0, 17), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "SCL4"), + MTK_FUNCTION(2, "DMIC4_CLK"), + MTK_FUNCTION(3, "TDMIN_BCK"), + MTK_FUNCTION(7, "DBG_MON_A9") + ), + MTK_PIN( + 18, "GPIO18", + MTK_EINT_FUNCTION(0, 18), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "DP_TX_HPD") + ), + MTK_PIN( + 19, "GPIO19", + MTK_EINT_FUNCTION(0, 19), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "WAKEN"), + MTK_FUNCTION(2, "SCP_SDA1"), + MTK_FUNCTION(3, "MD32_0_JTAG_TCK"), + MTK_FUNCTION(4, "ADSP_JTAG0_TCK"), + MTK_FUNCTION(5, "SDA6") + ), + MTK_PIN( + 20, "GPIO20", + MTK_EINT_FUNCTION(0, 20), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "PERSTN"), + MTK_FUNCTION(2, "SCP_SCL1"), + MTK_FUNCTION(3, "MD32_0_JTAG_TMS"), + MTK_FUNCTION(4, "ADSP_JTAG0_TMS"), + MTK_FUNCTION(5, "SCL6") + ), + MTK_PIN( + 21, "GPIO21", + MTK_EINT_FUNCTION(0, 21), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "CLKREQN"), + MTK_FUNCTION(3, "MD32_0_JTAG_TDI"), + MTK_FUNCTION(4, "ADSP_JTAG0_TDI"), + MTK_FUNCTION(5, "SCP_SDA1") + ), + MTK_PIN( + 22, "GPIO22", + MTK_EINT_FUNCTION(0, 22), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "CMMCLK0"), + MTK_FUNCTION(2, "PERSTN_1"), + MTK_FUNCTION(5, "SCP_SCL1"), + MTK_FUNCTION(7, "MD32_0_GPIO0") + ), + MTK_PIN( + 23, "GPIO23", + MTK_EINT_FUNCTION(0, 23), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "CMMCLK1"), + MTK_FUNCTION(2, "CLKREQN_1"), + MTK_FUNCTION(3, "SDA4"), + MTK_FUNCTION(4, "DMIC1_CLK"), + MTK_FUNCTION(5, "SCP_SDA0"), + MTK_FUNCTION(7, "MD32_0_GPIO1") + ), + MTK_PIN( + 24, "GPIO24", + MTK_EINT_FUNCTION(0, 24), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "CMMCLK2"), + MTK_FUNCTION(2, "WAKEN_1"), + MTK_FUNCTION(3, "SCL4"), + MTK_FUNCTION(4, "DMIC1_DAT"), + MTK_FUNCTION(5, "SCP_SCL0"), + MTK_FUNCTION(6, "LVTS_26M"), + MTK_FUNCTION(7, "MD32_0_GPIO2") + ), + MTK_PIN( + 25, "GPIO25", + MTK_EINT_FUNCTION(0, 25), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "CMMRST"), + MTK_FUNCTION(2, "CMMCLK3"), + MTK_FUNCTION(3, "SPDIF_OUT"), + MTK_FUNCTION(4, "SDA6"), + MTK_FUNCTION(5, "ADSP_JTAG0_TRSTN"), + MTK_FUNCTION(6, "MD32_0_JTAG_TRST") + ), + MTK_PIN( + 26, "GPIO26", + MTK_EINT_FUNCTION(0, 26), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "CMMPDN"), + MTK_FUNCTION(2, "CMMCLK4"), + MTK_FUNCTION(3, "IR_IN"), + MTK_FUNCTION(4, "SCL6"), + MTK_FUNCTION(5, "ADSP_JTAG0_TDO"), + MTK_FUNCTION(6, "MD32_0_JTAG_TDO") + ), + MTK_PIN( + 27, "GPIO27", + MTK_EINT_FUNCTION(0, 27), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "HDMIRX20_HTPLG"), + MTK_FUNCTION(2, "CMFLASH0"), + MTK_FUNCTION(3, "MD32_0_TXD"), + MTK_FUNCTION(4, "TP_UTXD2_AO"), + MTK_FUNCTION(5, "SCL7"), + MTK_FUNCTION(6, "UCTS2"), + MTK_FUNCTION(7, "DBG_MON_A18") + ), + MTK_PIN( + 28, "GPIO28", + MTK_EINT_FUNCTION(0, 28), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "HDMIRX20_PWR5V"), + MTK_FUNCTION(2, "CMFLASH1"), + MTK_FUNCTION(3, "MD32_0_RXD"), + MTK_FUNCTION(4, "TP_URXD2_AO"), + MTK_FUNCTION(5, "SDA7"), + MTK_FUNCTION(6, "URTS2"), + MTK_FUNCTION(7, "DBG_MON_A19") + ), + MTK_PIN( + 29, "GPIO29", + MTK_EINT_FUNCTION(0, 29), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "HDMIRX20_SCL"), + MTK_FUNCTION(2, "CMFLASH2"), + MTK_FUNCTION(3, "SCL5"), + MTK_FUNCTION(4, "TP_URTS2_AO"), + MTK_FUNCTION(6, "UTXD2"), + MTK_FUNCTION(7, "DBG_MON_A20") + ), + MTK_PIN( + 30, "GPIO30", + MTK_EINT_FUNCTION(0, 30), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "HDMIRX20_SDA"), + MTK_FUNCTION(2, "CMFLASH3"), + MTK_FUNCTION(3, "SDA5"), + MTK_FUNCTION(4, "TP_UCTS2_AO"), + MTK_FUNCTION(6, "URXD2"), + MTK_FUNCTION(7, "DBG_MON_A21") + ), + MTK_PIN( + 31, "GPIO31", + MTK_EINT_FUNCTION(0, 31), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "HDMITX20_PWR5V"), + MTK_FUNCTION(2, "DMIC1_DAT_R"), + MTK_FUNCTION(3, "PERSTN"), + MTK_FUNCTION(7, "DBG_MON_A22") + ), + MTK_PIN( + 32, "GPIO32", + MTK_EINT_FUNCTION(0, 32), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "HDMITX20_HTPLG"), + MTK_FUNCTION(3, "CLKREQN"), + MTK_FUNCTION(7, "DBG_MON_A23") + ), + MTK_PIN( + 33, "GPIO33", + MTK_EINT_FUNCTION(0, 33), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "HDMITX20_CEC"), + MTK_FUNCTION(2, "CMVREF0"), + MTK_FUNCTION(3, "WAKEN") + ), + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(0, 34), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "HDMITX20_SCL"), + MTK_FUNCTION(2, "CMVREF1"), + MTK_FUNCTION(3, "SCL7"), + MTK_FUNCTION(4, "SCL6"), + MTK_FUNCTION(7, "DBG_MON_A24") + ), + MTK_PIN( + 35, "GPIO35", + MTK_EINT_FUNCTION(0, 35), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "HDMITX20_SDA"), + MTK_FUNCTION(2, "CMVREF2"), + MTK_FUNCTION(3, "SDA7"), + MTK_FUNCTION(4, "SDA6"), + MTK_FUNCTION(7, "DBG_MON_A25") + ), + MTK_PIN( + 36, "GPIO36", + MTK_EINT_FUNCTION(0, 36), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "RTC32K_CK"), + MTK_FUNCTION(7, "DBG_MON_A27") + ), + MTK_PIN( + 37, "GPIO37", + MTK_EINT_FUNCTION(0, 37), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "WATCHDOG"), + MTK_FUNCTION(7, "DBG_MON_A28") + ), + MTK_PIN( + 38, "GPIO38", + MTK_EINT_FUNCTION(0, 38), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "SRCLKENA0"), + MTK_FUNCTION(7, "DBG_MON_A29") + ), + MTK_PIN( + 39, "GPIO39", + MTK_EINT_FUNCTION(0, 39), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "SRCLKENA1"), + MTK_FUNCTION(2, "DMIC2_DAT_R"), + MTK_FUNCTION(7, "DBG_MON_A30") + ), + MTK_PIN( + 40, "GPIO40", + MTK_EINT_FUNCTION(0, 40), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "PWRAP_SPI0_CSN"), + MTK_FUNCTION(3, "SPIM3_CSB"), + MTK_FUNCTION(7, "DBG_MON_A31") + ), + MTK_PIN( + 41, "GPIO41", + MTK_EINT_FUNCTION(0, 41), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "PWRAP_SPI0_CK"), + MTK_FUNCTION(3, "SPIM3_CLK"), + MTK_FUNCTION(7, "DBG_MON_A32") + ), + MTK_PIN( + 42, "GPIO42", + MTK_EINT_FUNCTION(0, 42), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "PWRAP_SPI0_MO"), + MTK_FUNCTION(2, "PWRAP_SPI0_MI"), + MTK_FUNCTION(3, "SPIM3_MO"), + MTK_FUNCTION(7, "DBG_MON_B0") + ), + MTK_PIN( + 43, "GPIO43", + MTK_EINT_FUNCTION(0, 43), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "PWRAP_SPI0_MI"), + MTK_FUNCTION(2, "PWRAP_SPI0_MO"), + MTK_FUNCTION(3, "SPIM3_MI"), + MTK_FUNCTION(7, "DBG_MON_B1") + ), + MTK_PIN( + 44, "GPIO44", + MTK_EINT_FUNCTION(0, 44), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "SPMI_M_SCL"), + MTK_FUNCTION(2, "I2SI00_DATA1"), + MTK_FUNCTION(3, "SCL5"), + MTK_FUNCTION(4, "UTXD5"), + MTK_FUNCTION(7, "DBG_MON_B2") + ), + MTK_PIN( + 45, "GPIO45", + MTK_EINT_FUNCTION(0, 45), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "SPMI_M_SDA"), + MTK_FUNCTION(2, "I2SI00_DATA2"), + MTK_FUNCTION(3, "SDA5"), + MTK_FUNCTION(4, "URXD5"), + MTK_FUNCTION(7, "DBG_MON_B3") + ), + MTK_PIN( + 46, "GPIO46", + MTK_EINT_FUNCTION(0, 46), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "I2SIN_MCK"), + MTK_FUNCTION(2, "I2SI00_DATA3"), + MTK_FUNCTION(3, "SPLIN_MCK"), + MTK_FUNCTION(7, "DBG_MON_B4") + ), + MTK_PIN( + 47, "GPIO47", + MTK_EINT_FUNCTION(0, 47), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "I2SIN_BCK"), + MTK_FUNCTION(2, "I2SIN0_BCK"), + MTK_FUNCTION(3, "SPLIN_LRCK"), + MTK_FUNCTION(7, "DBG_MON_B5") + ), + MTK_PIN( + 48, "GPIO48", + MTK_EINT_FUNCTION(0, 48), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "I2SIN_WS"), + MTK_FUNCTION(2, "I2SIN0_LRCK"), + MTK_FUNCTION(3, "SPLIN_BCK"), + MTK_FUNCTION(7, "DBG_MON_B6") + ), + MTK_PIN( + 49, "GPIO49", + MTK_EINT_FUNCTION(0, 49), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "I2SIN_D0"), + MTK_FUNCTION(2, "I2SI00_DATA0"), + MTK_FUNCTION(3, "SPLIN_D0"), + MTK_FUNCTION(7, "DBG_MON_B7") + ), + MTK_PIN( + 50, "GPIO50", + MTK_EINT_FUNCTION(0, 50), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "I2SO1_MCK"), + MTK_FUNCTION(2, "I2SI5_D0"), + MTK_FUNCTION(4, "I2SO4_MCK"), + MTK_FUNCTION(7, "DBG_MON_B8") + ), + MTK_PIN( + 51, "GPIO51", + MTK_EINT_FUNCTION(0, 51), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "I2SO1_BCK"), + MTK_FUNCTION(2, "I2SI5_BCK"), + MTK_FUNCTION(7, "DBG_MON_B9") + ), + MTK_PIN( + 52, "GPIO52", + MTK_EINT_FUNCTION(0, 52), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "I2SO1_WS"), + MTK_FUNCTION(2, "I2SI5_WS"), + MTK_FUNCTION(7, "DBG_MON_B10") + ), + MTK_PIN( + 53, "GPIO53", + MTK_EINT_FUNCTION(0, 53), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "I2SO1_D0"), + MTK_FUNCTION(2, "I2SI5_MCK"), + MTK_FUNCTION(7, "DBG_MON_B11") + ), + MTK_PIN( + 54, "GPIO54", + MTK_EINT_FUNCTION(0, 54), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "I2SO1_D1"), + MTK_FUNCTION(2, "I2SI01_DATA1"), + MTK_FUNCTION(3, "SPLIN_D1"), + MTK_FUNCTION(4, "I2SO4_BCK"), + MTK_FUNCTION(7, "DBG_MON_B12") + ), + MTK_PIN( + 55, "GPIO55", + MTK_EINT_FUNCTION(0, 55), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "I2SO1_D2"), + MTK_FUNCTION(2, "I2SI01_DATA2"), + MTK_FUNCTION(3, "SPLIN_D2"), + MTK_FUNCTION(4, "I2SO4_WS"), + MTK_FUNCTION(7, "DBG_MON_B13") + ), + MTK_PIN( + 56, "GPIO56", + MTK_EINT_FUNCTION(0, 56), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "I2SO1_D3"), + MTK_FUNCTION(2, "I2SI01_DATA3"), + MTK_FUNCTION(3, "SPLIN_D3"), + MTK_FUNCTION(4, "I2SO4_D0"), + MTK_FUNCTION(7, "DBG_MON_B14") + ), + MTK_PIN( + 57, "GPIO57", + MTK_EINT_FUNCTION(0, 57), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "I2SO2_MCK"), + MTK_FUNCTION(2, "I2SO1_D12"), + MTK_FUNCTION(3, "LCM1_RST"), + MTK_FUNCTION(7, "DBG_MON_B15") + ), + MTK_PIN( + 58, "GPIO58", + MTK_EINT_FUNCTION(0, 58), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "I2SO2_BCK"), + MTK_FUNCTION(2, "I2SO1_D13"), + MTK_FUNCTION(3, "I2SIN1_BCK"), + MTK_FUNCTION(7, "DBG_MON_B16") + ), + MTK_PIN( + 59, "GPIO59", + MTK_EINT_FUNCTION(0, 59), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "I2SO2_WS"), + MTK_FUNCTION(2, "I2SO1_D14"), + MTK_FUNCTION(3, "I2SIN1_LRCK"), + MTK_FUNCTION(7, "DBG_MON_B17") + ), + MTK_PIN( + 60, "GPIO60", + MTK_EINT_FUNCTION(0, 60), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "I2SO2_D0"), + MTK_FUNCTION(2, "I2SO1_D15"), + MTK_FUNCTION(3, "I2SI01_DATA0"), + MTK_FUNCTION(7, "DBG_MON_B18") + ), + MTK_PIN( + 61, "GPIO61", + MTK_EINT_FUNCTION(0, 61), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "DMIC1_CLK"), + MTK_FUNCTION(2, "I2SO2_BCK"), + MTK_FUNCTION(3, "SCP_SPI2_CK"), + MTK_FUNCTION(7, "DBG_MON_B19") + ), + MTK_PIN( + 62, "GPIO62", + MTK_EINT_FUNCTION(0, 62), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "DMIC1_DAT"), + MTK_FUNCTION(2, "I2SO2_WS"), + MTK_FUNCTION(3, "SCP_SPI2_MI"), + MTK_FUNCTION(7, "DBG_MON_B20") + ), + MTK_PIN( + 63, "GPIO63", + MTK_EINT_FUNCTION(0, 63), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "DMIC2_CLK"), + MTK_FUNCTION(2, "VBUSVALID"), + MTK_FUNCTION(3, "SCP_SPI2_MO"), + MTK_FUNCTION(4, "SCP_SCL2"), + MTK_FUNCTION(5, "SCP_JTAG1_TDO"), + MTK_FUNCTION(6, "JTDO_SEL1"), + MTK_FUNCTION(7, "DBG_MON_B21") + ), + MTK_PIN( + 64, "GPIO64", + MTK_EINT_FUNCTION(0, 64), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "DMIC2_DAT"), + MTK_FUNCTION(2, "VBUSVALID_1P"), + MTK_FUNCTION(3, "SCP_SPI2_CS"), + MTK_FUNCTION(4, "SCP_SDA2"), + MTK_FUNCTION(7, "DBG_MON_B22") + ), + MTK_PIN( + 65, "GPIO65", + MTK_EINT_FUNCTION(0, 65), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "PCM_DO"), + MTK_FUNCTION(2, "AUXIF_ST0"), + MTK_FUNCTION(3, "UCTS2"), + MTK_FUNCTION(5, "SCP_JTAG1_TMS"), + MTK_FUNCTION(6, "JTMS_SEL1"), + MTK_FUNCTION(7, "DBG_MON_B23") + ), + MTK_PIN( + 66, "GPIO66", + MTK_EINT_FUNCTION(0, 66), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "PCM_CLK"), + MTK_FUNCTION(2, "AUXIF_CLK0"), + MTK_FUNCTION(3, "URTS2"), + MTK_FUNCTION(5, "SCP_JTAG1_TCK"), + MTK_FUNCTION(6, "JTCK_SEL1"), + MTK_FUNCTION(7, "DBG_MON_B24") + ), + MTK_PIN( + 67, "GPIO67", + MTK_EINT_FUNCTION(0, 67), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "PCM_DI"), + MTK_FUNCTION(2, "AUXIF_ST1"), + MTK_FUNCTION(3, "UTXD2"), + MTK_FUNCTION(5, "SCP_JTAG1_TRSTN"), + MTK_FUNCTION(6, "JTRSTn_SEL1"), + MTK_FUNCTION(7, "DBG_MON_B25") + ), + MTK_PIN( + 68, "GPIO68", + MTK_EINT_FUNCTION(0, 68), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "PCM_SYNC"), + MTK_FUNCTION(2, "AUXIF_CLK1"), + MTK_FUNCTION(3, "URXD2"), + MTK_FUNCTION(5, "SCP_JTAG1_TDI"), + MTK_FUNCTION(6, "JTDI_SEL1"), + MTK_FUNCTION(7, "DBG_MON_B26") + ), + MTK_PIN( + 69, "GPIO69", + MTK_EINT_FUNCTION(0, 69), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "AUD_CLK_MOSI"), + MTK_FUNCTION(2, "I2SIN2_BCK"), + MTK_FUNCTION(3, "PWM_0"), + MTK_FUNCTION(4, "WAKEN"), + MTK_FUNCTION(7, "DBG_MON_B27") + ), + MTK_PIN( + 70, "GPIO70", + MTK_EINT_FUNCTION(0, 70), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "AUD_SYNC_MOSI"), + MTK_FUNCTION(2, "I2SIN2_LRCK"), + MTK_FUNCTION(3, "PWM_1"), + MTK_FUNCTION(4, "PERSTN"), + MTK_FUNCTION(7, "DBG_MON_B28") + ), + MTK_PIN( + 71, "GPIO71", + MTK_EINT_FUNCTION(0, 71), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "AUD_DAT_MOSI0"), + MTK_FUNCTION(2, "IDDIG_2P"), + MTK_FUNCTION(3, "PWM_2"), + MTK_FUNCTION(4, "CLKREQN"), + MTK_FUNCTION(7, "DBG_MON_B29") + ), + MTK_PIN( + 72, "GPIO72", + MTK_EINT_FUNCTION(0, 72), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "AUD_DAT_MOSI1"), + MTK_FUNCTION(2, "USB_DRVVBUS_2P"), + MTK_FUNCTION(3, "PWM_3"), + MTK_FUNCTION(4, "PERSTN_1"), + MTK_FUNCTION(7, "DBG_MON_B30") + ), + MTK_PIN( + 73, "GPIO73", + MTK_EINT_FUNCTION(0, 73), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "AUD_DAT_MISO0"), + MTK_FUNCTION(2, "I2SI02_DATA0"), + MTK_FUNCTION(4, "CLKREQN_1"), + MTK_FUNCTION(5, "VOW_DAT_MISO"), + MTK_FUNCTION(7, "DBG_MON_B31") + ), + MTK_PIN( + 74, "GPIO74", + MTK_EINT_FUNCTION(0, 74), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "AUD_DAT_MISO1"), + MTK_FUNCTION(2, "I2SI02_DATA1"), + MTK_FUNCTION(4, "WAKEN_1"), + MTK_FUNCTION(5, "VOW_CLK_MISO"), + MTK_FUNCTION(7, "DBG_MON_B32") + ), + MTK_PIN( + 75, "GPIO75", + MTK_EINT_FUNCTION(0, 75), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "AUD_DAT_MISO2"), + MTK_FUNCTION(2, "I2SI02_DATA2") + ), + MTK_PIN( + 76, "GPIO76", + MTK_EINT_FUNCTION(0, 76), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "SCP_VREQ_VAO"), + MTK_FUNCTION(2, "I2SI02_DATA3"), + MTK_FUNCTION(7, "DBG_MON_A26") + ), + MTK_PIN( + 77, "GPIO77", + MTK_EINT_FUNCTION(0, 77), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "DGI_D0"), + MTK_FUNCTION(2, "DPI_D0"), + MTK_FUNCTION(3, "I2SI4_MCK"), + MTK_FUNCTION(4, "SPIM4_CLK"), + MTK_FUNCTION(5, "GBE_TXD3"), + MTK_FUNCTION(6, "SPM_JTAG_TCK") + ), + MTK_PIN( + 78, "GPIO78", + MTK_EINT_FUNCTION(0, 78), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "DGI_D1"), + MTK_FUNCTION(2, "DPI_D1"), + MTK_FUNCTION(3, "I2SI4_BCK"), + MTK_FUNCTION(4, "SPIM4_MO"), + MTK_FUNCTION(5, "GBE_TXD2"), + MTK_FUNCTION(6, "SPM_JTAG_TMS") + ), + MTK_PIN( + 79, "GPIO79", + MTK_EINT_FUNCTION(0, 79), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "DGI_D2"), + MTK_FUNCTION(2, "DPI_D2"), + MTK_FUNCTION(3, "I2SI4_WS"), + MTK_FUNCTION(4, "SPIM4_CSB"), + MTK_FUNCTION(5, "GBE_TXD1"), + MTK_FUNCTION(6, "SPM_JTAG_TDI") + ), + MTK_PIN( + 80, "GPIO80", + MTK_EINT_FUNCTION(0, 80), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "DGI_D3"), + MTK_FUNCTION(2, "DPI_D3"), + MTK_FUNCTION(3, "I2SI4_D0"), + MTK_FUNCTION(4, "SPIM4_MI"), + MTK_FUNCTION(5, "GBE_TXD0"), + MTK_FUNCTION(6, "SPM_JTAG_TDO") + ), + MTK_PIN( + 81, "GPIO81", + MTK_EINT_FUNCTION(0, 81), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "DGI_D4"), + MTK_FUNCTION(2, "DPI_D4"), + MTK_FUNCTION(3, "I2SI5_MCK"), + MTK_FUNCTION(4, "SPIM5_CLK"), + MTK_FUNCTION(5, "GBE_RXD3"), + MTK_FUNCTION(6, "SPM_JTAG_TRSTN") + ), + MTK_PIN( + 82, "GPIO82", + MTK_EINT_FUNCTION(0, 82), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "DGI_D5"), + MTK_FUNCTION(2, "DPI_D5"), + MTK_FUNCTION(3, "I2SI5_BCK"), + MTK_FUNCTION(4, "SPIM5_MO"), + MTK_FUNCTION(5, "GBE_RXD2"), + MTK_FUNCTION(6, "MCUPM_JTAG_TDO") + ), + MTK_PIN( + 83, "GPIO83", + MTK_EINT_FUNCTION(0, 83), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "DGI_D6"), + MTK_FUNCTION(2, "DPI_D6"), + MTK_FUNCTION(3, "I2SI5_WS"), + MTK_FUNCTION(4, "SPIM5_CSB"), + MTK_FUNCTION(5, "GBE_RXD1"), + MTK_FUNCTION(6, "MCUPM_JTAG_TMS") + ), + MTK_PIN( + 84, "GPIO84", + MTK_EINT_FUNCTION(0, 84), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "DGI_D7"), + MTK_FUNCTION(2, "DPI_D7"), + MTK_FUNCTION(3, "I2SI5_D0"), + MTK_FUNCTION(4, "SPIM5_MI"), + MTK_FUNCTION(5, "GBE_RXD0"), + MTK_FUNCTION(6, "MCUPM_JTAG_TCK") + ), + MTK_PIN( + 85, "GPIO85", + MTK_EINT_FUNCTION(0, 85), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "DGI_D8"), + MTK_FUNCTION(2, "DPI_D8"), + MTK_FUNCTION(3, "I2SO4_MCK"), + MTK_FUNCTION(4, "SCP_SPI1_B_CK"), + MTK_FUNCTION(5, "GBE_TXC"), + MTK_FUNCTION(6, "MCUPM_JTAG_TDI") + ), + MTK_PIN( + 86, "GPIO86", + MTK_EINT_FUNCTION(0, 86), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "DGI_D9"), + MTK_FUNCTION(2, "DPI_D9"), + MTK_FUNCTION(3, "I2SO4_BCK"), + MTK_FUNCTION(4, "SCP_SPI1_B_MI"), + MTK_FUNCTION(5, "GBE_RXC"), + MTK_FUNCTION(6, "MCUPM_JTAG_TRSTN") + ), + MTK_PIN( + 87, "GPIO87", + MTK_EINT_FUNCTION(0, 87), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "DGI_D10"), + MTK_FUNCTION(2, "DPI_D10"), + MTK_FUNCTION(3, "I2SO4_WS"), + MTK_FUNCTION(4, "SCP_SPI1_B_CS"), + MTK_FUNCTION(5, "GBE_RXDV"), + MTK_FUNCTION(6, "SSPM_JTAG_TDO") + ), + MTK_PIN( + 88, "GPIO88", + MTK_EINT_FUNCTION(0, 88), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "DGI_D11"), + MTK_FUNCTION(2, "DPI_D11"), + MTK_FUNCTION(3, "I2SO4_D0"), + MTK_FUNCTION(4, "SCP_SPI1_B_MO"), + MTK_FUNCTION(5, "GBE_TXEN"), + MTK_FUNCTION(6, "SSPM_JTAG_TMS") + ), + MTK_PIN( + 89, "GPIO89", + MTK_EINT_FUNCTION(0, 89), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "DGI_D12"), + MTK_FUNCTION(2, "DPI_D12"), + MTK_FUNCTION(3, "MSDC2_CMD_A"), + MTK_FUNCTION(4, "I2SO5_BCK"), + MTK_FUNCTION(5, "GBE_MDC"), + MTK_FUNCTION(6, "SSPM_JTAG_TCK") + ), + MTK_PIN( + 90, "GPIO90", + MTK_EINT_FUNCTION(0, 90), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "DGI_D13"), + MTK_FUNCTION(2, "DPI_D13"), + MTK_FUNCTION(3, "MSDC2_CLK_A"), + MTK_FUNCTION(4, "I2SO5_WS"), + MTK_FUNCTION(5, "GBE_MDIO"), + MTK_FUNCTION(6, "SSPM_JTAG_TDI") + ), + MTK_PIN( + 91, "GPIO91", + MTK_EINT_FUNCTION(0, 91), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "DGI_D14"), + MTK_FUNCTION(2, "DPI_D14"), + MTK_FUNCTION(3, "MSDC2_DAT3_A"), + MTK_FUNCTION(4, "I2SO5_D0"), + MTK_FUNCTION(5, "GBE_TXER"), + MTK_FUNCTION(6, "SSPM_JTAG_TRSTN") + ), + MTK_PIN( + 92, "GPIO92", + MTK_EINT_FUNCTION(0, 92), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "DGI_D15"), + MTK_FUNCTION(2, "DPI_D15"), + MTK_FUNCTION(3, "MSDC2_DAT0_A"), + MTK_FUNCTION(4, "I2SO2_D1"), + MTK_FUNCTION(5, "GBE_RXER"), + MTK_FUNCTION(6, "CCU0_JTAG_TDO") + ), + MTK_PIN( + 93, "GPIO93", + MTK_EINT_FUNCTION(0, 93), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "DGI_HSYNC"), + MTK_FUNCTION(2, "DPI_HSYNC"), + MTK_FUNCTION(3, "MSDC2_DAT2_A"), + MTK_FUNCTION(4, "I2SO2_D2"), + MTK_FUNCTION(5, "GBE_COL"), + MTK_FUNCTION(6, "CCU0_JTAG_TMS") + ), + MTK_PIN( + 94, "GPIO94", + MTK_EINT_FUNCTION(0, 94), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "DGI_VSYNC"), + MTK_FUNCTION(2, "DPI_VSYNC"), + MTK_FUNCTION(3, "MSDC2_DAT1_A"), + MTK_FUNCTION(4, "I2SO2_D3"), + MTK_FUNCTION(5, "GBE_INTR"), + MTK_FUNCTION(6, "CCU0_JTAG_TDI") + ), + MTK_PIN( + 95, "GPIO95", + MTK_EINT_FUNCTION(0, 95), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "DGI_DE"), + MTK_FUNCTION(2, "DPI_DE"), + MTK_FUNCTION(3, "UTXD2"), + MTK_FUNCTION(5, "I2SIN_D1"), + MTK_FUNCTION(6, "CCU0_JTAG_TCK") + ), + MTK_PIN( + 96, "GPIO96", + MTK_EINT_FUNCTION(0, 96), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "DGI_CK"), + MTK_FUNCTION(2, "DPI_CK"), + MTK_FUNCTION(3, "URXD2"), + MTK_FUNCTION(4, "I2SO5_MCK"), + MTK_FUNCTION(5, "I2SIN_D2"), + MTK_FUNCTION(6, "CCU0_JTAG_TRST") + ), + MTK_PIN( + 97, "GPIO97", + MTK_EINT_FUNCTION(0, 97), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "DISP_PWM0"), + MTK_FUNCTION(2, "DVFSRC_EXT_REQ") + ), + MTK_PIN( + 98, "GPIO98", + MTK_EINT_FUNCTION(0, 98), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "UTXD0") + ), + MTK_PIN( + 99, "GPIO99", + MTK_EINT_FUNCTION(0, 99), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "URXD0") + ), + MTK_PIN( + 100, "GPIO100", + MTK_EINT_FUNCTION(0, 100), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "URTS1"), + MTK_FUNCTION(2, "DSI_TE"), + MTK_FUNCTION(3, "I2SO1_D8"), + MTK_FUNCTION(4, "KPROW2"), + MTK_FUNCTION(5, "PWM_0"), + MTK_FUNCTION(6, "TP_URTS1_AO"), + MTK_FUNCTION(7, "I2SIN_D0") + ), + MTK_PIN( + 101, "GPIO101", + MTK_EINT_FUNCTION(0, 101), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "UCTS1"), + MTK_FUNCTION(2, "DSI1_TE"), + MTK_FUNCTION(3, "I2SO1_D9"), + MTK_FUNCTION(4, "KPCOL2"), + MTK_FUNCTION(5, "PWM_1"), + MTK_FUNCTION(6, "TP_UCTS1_AO"), + MTK_FUNCTION(7, "I2SIN_D1") + ), + MTK_PIN( + 102, "GPIO102", + MTK_EINT_FUNCTION(0, 102), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "VBUSVALID_2P"), + MTK_FUNCTION(3, "I2SO1_D10"), + MTK_FUNCTION(4, "SSPM_UTXD_AO"), + MTK_FUNCTION(5, "TP_UTXD1_AO"), + MTK_FUNCTION(6, "MD32_1_TXD"), + MTK_FUNCTION(7, "I2SIN_D2") + ), + MTK_PIN( + 103, "GPIO103", + MTK_EINT_FUNCTION(0, 103), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "VBUSVALID_3P"), + MTK_FUNCTION(3, "I2SO1_D11"), + MTK_FUNCTION(4, "SSPM_URXD_AO"), + MTK_FUNCTION(5, "TP_URXD1_AO"), + MTK_FUNCTION(6, "MD32_1_RXD"), + MTK_FUNCTION(7, "I2SIN_D3") + ), + MTK_PIN( + 104, "GPIO104", + MTK_EINT_FUNCTION(0, 104), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "KPROW0"), + MTK_FUNCTION(2, "DISP_PWM1") + ), + MTK_PIN( + 105, "GPIO105", + MTK_EINT_FUNCTION(0, 105), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "KPROW1"), + MTK_FUNCTION(2, "EDP_TX_HPD"), + MTK_FUNCTION(3, "PWM_2") + ), + MTK_PIN( + 106, "GPIO106", + MTK_EINT_FUNCTION(0, 106), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "KPCOL0") + ), + MTK_PIN( + 107, "GPIO107", + MTK_EINT_FUNCTION(0, 107), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "KPCOL1"), + MTK_FUNCTION(2, "DSI1_TE"), + MTK_FUNCTION(3, "PWM_3"), + MTK_FUNCTION(4, "SCP_SCL3"), + MTK_FUNCTION(5, "I2SIN_MCK") + ), + MTK_PIN( + 108, "GPIO108", + MTK_EINT_FUNCTION(0, 108), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "LCM_RST"), + MTK_FUNCTION(2, "KPCOL1"), + MTK_FUNCTION(4, "SCP_SDA3"), + MTK_FUNCTION(5, "I2SIN_BCK") + ), + MTK_PIN( + 109, "GPIO109", + MTK_EINT_FUNCTION(0, 109), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "DSI_TE"), + MTK_FUNCTION(2, "I2SIN_D3"), + MTK_FUNCTION(5, "I2SIN_WS") + ), + MTK_PIN( + 110, "GPIO110", + MTK_EINT_FUNCTION(0, 110), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(2, "JTMS_SEL3"), + MTK_FUNCTION(3, "UDI_TMS"), + MTK_FUNCTION(5, "CCU1_JTAG_TMS"), + MTK_FUNCTION(6, "IPU_JTAG_TMS") + ), + MTK_PIN( + 111, "GPIO111", + MTK_EINT_FUNCTION(0, 111), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "JTCK_SEL3"), + MTK_FUNCTION(3, "UDI_TCK"), + MTK_FUNCTION(5, "CCU1_JTAG_TCK"), + MTK_FUNCTION(6, "IPU_JTAG_TCK") + ), + MTK_PIN( + 112, "GPIO112", + MTK_EINT_FUNCTION(0, 112), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "JTDI_SEL3"), + MTK_FUNCTION(3, "UDI_TDI"), + MTK_FUNCTION(4, "I2SO2_D0"), + MTK_FUNCTION(5, "CCU1_JTAG_TDI"), + MTK_FUNCTION(6, "IPU_JTAG_TDI") + ), + MTK_PIN( + 113, "GPIO113", + MTK_EINT_FUNCTION(0, 113), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "JTDO_SEL3"), + MTK_FUNCTION(3, "UDI_TDO"), + MTK_FUNCTION(4, "I2SO2_D1"), + MTK_FUNCTION(5, "CCU1_JTAG_TDO"), + MTK_FUNCTION(6, "IPU_JTAG_TDO") + ), + MTK_PIN( + 114, "GPIO114", + MTK_EINT_FUNCTION(0, 114), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "JTRSTn_SEL3"), + MTK_FUNCTION(3, "UDI_NTRST"), + MTK_FUNCTION(4, "I2SO2_D2"), + MTK_FUNCTION(5, "CCU1_JTAG_TRST"), + MTK_FUNCTION(6, "IPU_JTAG_TRST") + ), + MTK_PIN( + 115, "GPIO115", + MTK_EINT_FUNCTION(0, 115), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(4, "I2SO2_D3"), + MTK_FUNCTION(6, "MD32_1_GPIO2") + ), + MTK_PIN( + 116, "GPIO116", + MTK_EINT_FUNCTION(0, 116), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "MSDC0_DAT7") + ), + MTK_PIN( + 117, "GPIO117", + MTK_EINT_FUNCTION(0, 117), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "MSDC0_DAT6") + ), + MTK_PIN( + 118, "GPIO118", + MTK_EINT_FUNCTION(0, 118), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "MSDC0_DAT5") + ), + MTK_PIN( + 119, "GPIO119", + MTK_EINT_FUNCTION(0, 119), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "MSDC0_DAT4") + ), + MTK_PIN( + 120, "GPIO120", + MTK_EINT_FUNCTION(0, 120), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "MSDC0_RSTB") + ), + MTK_PIN( + 121, "GPIO121", + MTK_EINT_FUNCTION(0, 121), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "MSDC0_CMD") + ), + MTK_PIN( + 122, "GPIO122", + MTK_EINT_FUNCTION(0, 122), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "MSDC0_CLK") + ), + MTK_PIN( + 123, "GPIO123", + MTK_EINT_FUNCTION(0, 123), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "MSDC0_DAT3") + ), + MTK_PIN( + 124, "GPIO124", + MTK_EINT_FUNCTION(0, 124), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "MSDC0_DAT2") + ), + MTK_PIN( + 125, "GPIO125", + MTK_EINT_FUNCTION(0, 125), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "MSDC0_DAT1") + ), + MTK_PIN( + 126, "GPIO126", + MTK_EINT_FUNCTION(0, 126), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "MSDC0_DAT0") + ), + MTK_PIN( + 127, "GPIO127", + MTK_EINT_FUNCTION(0, 127), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "MSDC0_DSL") + ), + MTK_PIN( + 128, "GPIO128", + MTK_EINT_FUNCTION(0, 128), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "IDDIG"), + MTK_FUNCTION(2, "UCTS2"), + MTK_FUNCTION(3, "UTXD5"), + MTK_FUNCTION(4, "UFS_MPHY_SCL"), + MTK_FUNCTION(5, "mbistreaden_trigger"), + MTK_FUNCTION(6, "MD32_1_GPIO0"), + MTK_FUNCTION(7, "SCP_SCL2") + ), + MTK_PIN( + 129, "GPIO129", + MTK_EINT_FUNCTION(0, 129), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "USB_DRVVBUS"), + MTK_FUNCTION(2, "URTS2"), + MTK_FUNCTION(3, "URXD5"), + MTK_FUNCTION(4, "UFS_MPHY_SDA"), + MTK_FUNCTION(5, "mbistwriteen_trigger"), + MTK_FUNCTION(6, "MD32_1_GPIO1"), + MTK_FUNCTION(7, "SCP_SDA2") + ), + MTK_PIN( + 130, "GPIO130", + MTK_EINT_FUNCTION(0, 130), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "IDDIG_1P"), + MTK_FUNCTION(2, "SPINOR_IO2"), + MTK_FUNCTION(3, "SNFI_WP"), + MTK_FUNCTION(4, "VPU_UDI_NTRST") + ), + MTK_PIN( + 131, "GPIO131", + MTK_EINT_FUNCTION(0, 131), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "USB_DRVVBUS_1P"), + MTK_FUNCTION(2, "SPINOR_IO3"), + MTK_FUNCTION(3, "SNFI_HOLD"), + MTK_FUNCTION(4, "MD32_1_JTAG_TRST"), + MTK_FUNCTION(5, "SCP_JTAG0_TRSTN"), + MTK_FUNCTION(6, "APU_JTAG_TRST") + ), + MTK_PIN( + 132, "GPIO132", + MTK_EINT_FUNCTION(0, 132), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "SPIM0_CSB"), + MTK_FUNCTION(2, "SCP_SPI0_CS"), + MTK_FUNCTION(3, "SPIS0_CSB"), + MTK_FUNCTION(4, "VPU_UDI_TMS"), + MTK_FUNCTION(6, "I2SO5_D0") + ), + MTK_PIN( + 133, "GPIO133", + MTK_EINT_FUNCTION(0, 133), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "SPIM0_CLK"), + MTK_FUNCTION(2, "SCP_SPI0_CK"), + MTK_FUNCTION(3, "SPIS0_CLK"), + MTK_FUNCTION(4, "VPU_UDI_TCK"), + MTK_FUNCTION(6, "I2SO5_BCK") + ), + MTK_PIN( + 134, "GPIO134", + MTK_EINT_FUNCTION(0, 134), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "SPIM0_MO"), + MTK_FUNCTION(2, "SCP_SPI0_MO"), + MTK_FUNCTION(3, "SPIS0_SI"), + MTK_FUNCTION(4, "VPU_UDI_TDO"), + MTK_FUNCTION(6, "I2SO5_WS") + ), + MTK_PIN( + 135, "GPIO135", + MTK_EINT_FUNCTION(0, 135), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "SPIM0_MI"), + MTK_FUNCTION(2, "SCP_SPI0_MI"), + MTK_FUNCTION(3, "SPIS0_SO"), + MTK_FUNCTION(4, "VPU_UDI_TDI"), + MTK_FUNCTION(6, "I2SO5_MCK") + ), + MTK_PIN( + 136, "GPIO136", + MTK_EINT_FUNCTION(0, 136), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "SPIM1_CSB"), + MTK_FUNCTION(2, "SCP_SPI1_A_CS"), + MTK_FUNCTION(3, "SPIS1_CSB"), + MTK_FUNCTION(4, "MD32_1_JTAG_TMS"), + MTK_FUNCTION(5, "SCP_JTAG0_TMS"), + MTK_FUNCTION(6, "APU_JTAG_TMS"), + MTK_FUNCTION(7, "DBG_MON_A15") + ), + MTK_PIN( + 137, "GPIO137", + MTK_EINT_FUNCTION(0, 137), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "SPIM1_CLK"), + MTK_FUNCTION(2, "SCP_SPI1_A_CK"), + MTK_FUNCTION(3, "SPIS1_CLK"), + MTK_FUNCTION(4, "MD32_1_JTAG_TCK"), + MTK_FUNCTION(5, "SCP_JTAG0_TCK"), + MTK_FUNCTION(6, "APU_JTAG_TCK"), + MTK_FUNCTION(7, "DBG_MON_A14") + ), + MTK_PIN( + 138, "GPIO138", + MTK_EINT_FUNCTION(0, 138), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "SPIM1_MO"), + MTK_FUNCTION(2, "SCP_SPI1_A_MO"), + MTK_FUNCTION(3, "SPIS1_SI"), + MTK_FUNCTION(4, "MD32_1_JTAG_TDO"), + MTK_FUNCTION(5, "SCP_JTAG0_TDO"), + MTK_FUNCTION(6, "APU_JTAG_TDO"), + MTK_FUNCTION(7, "DBG_MON_A16") + ), + MTK_PIN( + 139, "GPIO139", + MTK_EINT_FUNCTION(0, 139), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "SPIM1_MI"), + MTK_FUNCTION(2, "SCP_SPI1_A_MI"), + MTK_FUNCTION(3, "SPIS1_SO"), + MTK_FUNCTION(4, "MD32_1_JTAG_TDI"), + MTK_FUNCTION(5, "SCP_JTAG0_TDI"), + MTK_FUNCTION(6, "APU_JTAG_TDI"), + MTK_FUNCTION(7, "DBG_MON_A17") + ), + MTK_PIN( + 140, "GPIO140", + MTK_EINT_FUNCTION(0, 140), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "SPIM2_CSB"), + MTK_FUNCTION(2, "SPINOR_CS"), + MTK_FUNCTION(3, "SNFI_CS"), + MTK_FUNCTION(4, "DMIC3_DAT"), + MTK_FUNCTION(7, "DBG_MON_A11") + ), + MTK_PIN( + 141, "GPIO141", + MTK_EINT_FUNCTION(0, 141), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "SPIM2_CLK"), + MTK_FUNCTION(2, "SPINOR_CK"), + MTK_FUNCTION(3, "SNFI_CLK"), + MTK_FUNCTION(4, "DMIC3_CLK"), + MTK_FUNCTION(7, "DBG_MON_A10") + ), + MTK_PIN( + 142, "GPIO142", + MTK_EINT_FUNCTION(0, 142), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "SPIM2_MO"), + MTK_FUNCTION(2, "SPINOR_IO0"), + MTK_FUNCTION(3, "SNFI_MOSI"), + MTK_FUNCTION(4, "DMIC4_DAT"), + MTK_FUNCTION(7, "DBG_MON_A12") + ), + MTK_PIN( + 143, "GPIO143", + MTK_EINT_FUNCTION(0, 143), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "SPIM2_MI"), + MTK_FUNCTION(2, "SPINOR_IO1"), + MTK_FUNCTION(3, "SNFI_MISO"), + MTK_FUNCTION(4, "DMIC4_CLK"), + MTK_FUNCTION(7, "DBG_MON_A13") + ), + MTK_PIN( + 144, "GPIO144", + MTK_EINT_FUNCTION(0, 144), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 145, "GPIO145", + MTK_EINT_FUNCTION(0, 145), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 146, "GPIO146", + MTK_EINT_FUNCTION(0, 146), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 147, "GPIO147", + MTK_EINT_FUNCTION(0, 147), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 148, "GPIO148", + MTK_EINT_FUNCTION(0, 148), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 149, "GPIO149", + MTK_EINT_FUNCTION(0, 149), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 150, "GPIO150", + MTK_EINT_FUNCTION(0, 150), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 151, "GPIO151", + MTK_EINT_FUNCTION(0, 151), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 152, "GPIO152", + MTK_EINT_FUNCTION(0, 152), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 153, "GPIO153", + MTK_EINT_FUNCTION(0, 153), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 154, "GPIO154", + MTK_EINT_FUNCTION(0, 154), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 155, "GPIO155", + MTK_EINT_FUNCTION(0, 155), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 156, "GPIO156", + MTK_EINT_FUNCTION(0, 216), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 157, "GPIO157", + MTK_EINT_FUNCTION(0, 217), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 158, "GPIO158", + MTK_EINT_FUNCTION(0, 218), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 159, "GPIO159", + MTK_EINT_FUNCTION(0, 219), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 160, "GPIO160", + MTK_EINT_FUNCTION(0, 220), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 161, "GPIO161", + MTK_EINT_FUNCTION(0, 221), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 162, "GPIO162", + MTK_EINT_FUNCTION(0, 222), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 163, "GPIO163", + MTK_EINT_FUNCTION(0, 223), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 164, "GPIO164", + MTK_EINT_FUNCTION(0, 224), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ) +}; + +#endif /* __PINCTRL_MTK_MT8195_H */ diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index da1f19288aa6..85db2e4377f0 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -970,6 +970,8 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, hw->nbase = hw->soc->nbase_names; + spin_lock_init(&hw->lock); + err = mtk_pctrl_build_state(pdev); if (err) { dev_err(&pdev->dev, "build state failed: %d\n", err); diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c index 17491b27e487..8ba8f3e9121f 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c @@ -519,13 +519,13 @@ static struct mvebu_mpp_mode armada_cp110_mpp_modes[] = { MPP_FUNCTION(4, "synce1", "clk"), MPP_FUNCTION(8, "led", "data"), MPP_FUNCTION(10, "sdio", "hw_rst"), - MPP_FUNCTION(11, "sdio", "wr_protect")), + MPP_FUNCTION(11, "sdio_wp", "wr_protect")), MPP_MODE(55, MPP_FUNCTION(0, "gpio", NULL), MPP_FUNCTION(1, "ge1", "rxctl_rxdv"), MPP_FUNCTION(3, "ptp", "pulse"), MPP_FUNCTION(10, "sdio", "led"), - MPP_FUNCTION(11, "sdio", "card_detect")), + MPP_FUNCTION(11, "sdio_cd", "card_detect")), MPP_MODE(56, MPP_FUNCTION(0, "gpio", NULL), MPP_FUNCTION(4, "tdm", "drx"), diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 1e225d513988..22e8d4c4040e 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -43,7 +43,7 @@ static const struct pin_config_item conf_items[] = { PCONFDUMP(PIN_CONFIG_INPUT_ENABLE, "input enabled", NULL, false), PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL, false), PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL, false), - PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, "pin low power", "mode", true), + PCONFDUMP(PIN_CONFIG_MODE_LOW_POWER, "pin low power", "mode", true), PCONFDUMP(PIN_CONFIG_OUTPUT_ENABLE, "output enabled", NULL, false), PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true), PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true), @@ -174,8 +174,8 @@ static const struct pinconf_generic_params dt_params[] = { { "input-schmitt", PIN_CONFIG_INPUT_SCHMITT, 0 }, { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, - { "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 }, - { "low-power-enable", PIN_CONFIG_LOW_POWER_MODE, 1 }, + { "low-power-disable", PIN_CONFIG_MODE_LOW_POWER, 0 }, + { "low-power-enable", PIN_CONFIG_MODE_LOW_POWER, 1 }, { "output-disable", PIN_CONFIG_OUTPUT_ENABLE, 0 }, { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 }, { "output-high", PIN_CONFIG_OUTPUT, 1, }, diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c index 02c075cc010b..d9d54065472e 100644 --- a/drivers/pinctrl/pinconf.c +++ b/drivers/pinctrl/pinconf.c @@ -370,9 +370,9 @@ DEFINE_SHOW_ATTRIBUTE(pinconf_groups); void pinconf_init_device_debugfs(struct dentry *devroot, struct pinctrl_dev *pctldev) { - debugfs_create_file("pinconf-pins", S_IFREG | S_IRUGO, + debugfs_create_file("pinconf-pins", 0444, devroot, pctldev, &pinconf_pins_fops); - debugfs_create_file("pinconf-groups", S_IFREG | S_IRUGO, + debugfs_create_file("pinconf-groups", 0444, devroot, pctldev, &pinconf_groups_fops); } diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index e71ebccc479c..03c32b2c5d30 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -801,6 +801,10 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, conf = atmel_pin_config_read(pctldev, pin_id); + /* Keep slew rate enabled by default. */ + if (atmel_pioctrl->slew_rate_support) + conf |= ATMEL_PIO_SR_MASK; + for (i = 0; i < num_configs; i++) { unsigned int param = pinconf_to_config_param(configs[i]); unsigned int arg = pinconf_to_config_argument(configs[i]); @@ -808,10 +812,6 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", __func__, pin_id, configs[i]); - /* Keep slew rate enabled by default. */ - if (atmel_pioctrl->slew_rate_support) - conf |= ATMEL_PIO_SR_MASK; - switch (param) { case PIN_CONFIG_BIAS_DISABLE: conf &= (~ATMEL_PIO_PUEN_MASK); diff --git a/drivers/pinctrl/pinctrl-equilibrium.c b/drivers/pinctrl/pinctrl-equilibrium.c index 067271b7d35a..a194d8089b6f 100644 --- a/drivers/pinctrl/pinctrl-equilibrium.c +++ b/drivers/pinctrl/pinctrl-equilibrium.c @@ -628,7 +628,8 @@ static int funcs_utils(struct device *dev, struct eqbr_pmx_func *funcs, break; default: - return -EINVAL; + of_node_put(np); + return -EINVAL; } i++; } @@ -707,34 +708,42 @@ static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata) group.num_pins = of_property_count_u32_elems(np, "pins"); if (group.num_pins < 0) { dev_err(dev, "No pins in the group: %s\n", prop->name); + of_node_put(np); return -EINVAL; } group.name = prop->value; group.pins = devm_kcalloc(dev, group.num_pins, sizeof(*(group.pins)), GFP_KERNEL); - if (!group.pins) + if (!group.pins) { + of_node_put(np); return -ENOMEM; + } pinmux = devm_kcalloc(dev, group.num_pins, sizeof(*pinmux), GFP_KERNEL); - if (!pinmux) + if (!pinmux) { + of_node_put(np); return -ENOMEM; + } for (j = 0; j < group.num_pins; j++) { if (of_property_read_u32_index(np, "pins", j, &pin_id)) { dev_err(dev, "Group %s: Read intel pins id failed\n", group.name); + of_node_put(np); return -EINVAL; } if (pin_id >= drvdata->pctl_desc.npins) { dev_err(dev, "Group %s: Invalid pin ID, idx: %d, pin %u\n", group.name, j, pin_id); + of_node_put(np); return -EINVAL; } group.pins[j] = pin_id; if (of_property_read_u32_index(np, "pinmux", j, &pinmux_id)) { dev_err(dev, "Group %s: Read intel pinmux id failed\n", group.name); + of_node_put(np); return -EINVAL; } pinmux[j] = pinmux_id; @@ -745,6 +754,7 @@ static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata) pinmux); if (err < 0) { dev_err(dev, "Failed to register group %s\n", group.name); + of_node_put(np); return err; } memset(&group, 0, sizeof(group)); diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index f2746125b077..651a36b9dcc0 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -3,8 +3,8 @@ * Ingenic SoCs pinctrl driver * * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net> - * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk> + * Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> */ #include <linux/compiler.h> @@ -26,47 +26,83 @@ #include "pinconf.h" #include "pinmux.h" -#define GPIO_PIN 0x00 -#define GPIO_MSK 0x20 +#define GPIO_PIN 0x00 +#define GPIO_MSK 0x20 + +#define JZ4730_GPIO_DATA 0x00 +#define JZ4730_GPIO_GPDIR 0x04 +#define JZ4730_GPIO_GPPUR 0x0c +#define JZ4730_GPIO_GPALR 0x10 +#define JZ4730_GPIO_GPAUR 0x14 +#define JZ4730_GPIO_GPIDLR 0x18 +#define JZ4730_GPIO_GPIDUR 0x1c +#define JZ4730_GPIO_GPIER 0x20 +#define JZ4730_GPIO_GPIMR 0x24 +#define JZ4730_GPIO_GPFR 0x28 + +#define JZ4740_GPIO_DATA 0x10 +#define JZ4740_GPIO_PULL_DIS 0x30 +#define JZ4740_GPIO_FUNC 0x40 +#define JZ4740_GPIO_SELECT 0x50 +#define JZ4740_GPIO_DIR 0x60 +#define JZ4740_GPIO_TRIG 0x70 +#define JZ4740_GPIO_FLAG 0x80 + +#define JZ4770_GPIO_INT 0x10 +#define JZ4770_GPIO_PAT1 0x30 +#define JZ4770_GPIO_PAT0 0x40 +#define JZ4770_GPIO_FLAG 0x50 +#define JZ4770_GPIO_PEN 0x70 + +#define X1830_GPIO_PEL 0x110 +#define X1830_GPIO_PEH 0x120 +#define X1830_GPIO_SR 0x150 +#define X1830_GPIO_SMT 0x160 + +#define X2000_GPIO_EDG 0x70 +#define X2000_GPIO_PEPU 0x80 +#define X2000_GPIO_PEPD 0x90 +#define X2000_GPIO_SR 0xd0 +#define X2000_GPIO_SMT 0xe0 + +#define REG_SET(x) ((x) + 0x4) +#define REG_CLEAR(x) ((x) + 0x8) + +#define REG_PZ_BASE(x) ((x) * 7) +#define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0) + +#define GPIO_PULL_DIS 0 +#define GPIO_PULL_UP 1 +#define GPIO_PULL_DOWN 2 + +#define PINS_PER_GPIO_CHIP 32 +#define JZ4730_PINS_PER_PAIRED_REG 16 -#define JZ4740_GPIO_DATA 0x10 -#define JZ4740_GPIO_PULL_DIS 0x30 -#define JZ4740_GPIO_FUNC 0x40 -#define JZ4740_GPIO_SELECT 0x50 -#define JZ4740_GPIO_DIR 0x60 -#define JZ4740_GPIO_TRIG 0x70 -#define JZ4740_GPIO_FLAG 0x80 - -#define JZ4770_GPIO_INT 0x10 -#define JZ4770_GPIO_PAT1 0x30 -#define JZ4770_GPIO_PAT0 0x40 -#define JZ4770_GPIO_FLAG 0x50 -#define JZ4770_GPIO_PEN 0x70 - -#define X1830_GPIO_PEL 0x110 -#define X1830_GPIO_PEH 0x120 - -#define REG_SET(x) ((x) + 0x4) -#define REG_CLEAR(x) ((x) + 0x8) - -#define REG_PZ_BASE(x) ((x) * 7) -#define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0) - -#define GPIO_PULL_DIS 0 -#define GPIO_PULL_UP 1 -#define GPIO_PULL_DOWN 2 +#define INGENIC_PIN_GROUP_FUNCS(name, id, funcs) \ + { \ + name, \ + id##_pins, \ + ARRAY_SIZE(id##_pins), \ + funcs, \ + } -#define PINS_PER_GPIO_CHIP 32 +#define INGENIC_PIN_GROUP(name, id, func) \ + INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func)) enum jz_version { + ID_JZ4730, ID_JZ4740, ID_JZ4725B, + ID_JZ4750, + ID_JZ4755, ID_JZ4760, ID_JZ4770, + ID_JZ4775, ID_JZ4780, ID_X1000, ID_X1500, ID_X1830, + ID_X2000, }; struct ingenic_chip_info { @@ -99,6 +135,99 @@ struct ingenic_gpio_chip { unsigned int irq, reg_base; }; +static const u32 jz4730_pull_ups[4] = { + 0x3fa3320f, 0xf200ffff, 0xffffffff, 0xffffffff, +}; + +static const u32 jz4730_pull_downs[4] = { + 0x00000df0, 0x0dff0000, 0x00000000, 0x00000000, +}; + +static int jz4730_mmc_1bit_pins[] = { 0x27, 0x26, 0x22, }; +static int jz4730_mmc_4bit_pins[] = { 0x23, 0x24, 0x25, }; +static int jz4730_uart0_data_pins[] = { 0x7e, 0x7f, }; +static int jz4730_uart1_data_pins[] = { 0x18, 0x19, }; +static int jz4730_uart2_data_pins[] = { 0x6f, 0x7d, }; +static int jz4730_uart3_data_pins[] = { 0x10, 0x15, }; +static int jz4730_uart3_hwflow_pins[] = { 0x11, 0x17, }; +static int jz4730_lcd_8bit_pins[] = { + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, + 0x3a, 0x39, 0x38, +}; +static int jz4730_lcd_16bit_pins[] = { + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, +}; +static int jz4730_lcd_special_pins[] = { 0x3d, 0x3c, 0x3e, 0x3f, }; +static int jz4730_lcd_generic_pins[] = { 0x3b, }; +static int jz4730_nand_cs1_pins[] = { 0x53, }; +static int jz4730_nand_cs2_pins[] = { 0x54, }; +static int jz4730_nand_cs3_pins[] = { 0x55, }; +static int jz4730_nand_cs4_pins[] = { 0x56, }; +static int jz4730_nand_cs5_pins[] = { 0x57, }; +static int jz4730_pwm_pwm0_pins[] = { 0x5e, }; +static int jz4730_pwm_pwm1_pins[] = { 0x5f, }; + +static u8 jz4730_lcd_8bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, }; + +static const struct group_desc jz4730_groups[] = { + INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1), + INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1), + INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1), + INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1), + INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1), + INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1), + INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1), + INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, jz4730_lcd_8bit_funcs), + INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1), + INGENIC_PIN_GROUP("lcd-special", jz4730_lcd_special, 1), + INGENIC_PIN_GROUP("lcd-generic", jz4730_lcd_generic, 1), + INGENIC_PIN_GROUP("nand-cs1", jz4730_nand_cs1, 1), + INGENIC_PIN_GROUP("nand-cs2", jz4730_nand_cs2, 1), + INGENIC_PIN_GROUP("nand-cs3", jz4730_nand_cs3, 1), + INGENIC_PIN_GROUP("nand-cs4", jz4730_nand_cs4, 1), + INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1), + INGENIC_PIN_GROUP("pwm0", jz4730_pwm_pwm0, 1), + INGENIC_PIN_GROUP("pwm1", jz4730_pwm_pwm1, 1), +}; + +static const char *jz4730_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; +static const char *jz4730_uart0_groups[] = { "uart0-data", }; +static const char *jz4730_uart1_groups[] = { "uart1-data", }; +static const char *jz4730_uart2_groups[] = { "uart2-data", }; +static const char *jz4730_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; +static const char *jz4730_lcd_groups[] = { + "lcd-8bit", "lcd-16bit", "lcd-special", "lcd-generic", +}; +static const char *jz4730_nand_groups[] = { + "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-cs5", +}; +static const char *jz4730_pwm0_groups[] = { "pwm0", }; +static const char *jz4730_pwm1_groups[] = { "pwm1", }; + +static const struct function_desc jz4730_functions[] = { + { "mmc", jz4730_mmc_groups, ARRAY_SIZE(jz4730_mmc_groups), }, + { "uart0", jz4730_uart0_groups, ARRAY_SIZE(jz4730_uart0_groups), }, + { "uart1", jz4730_uart1_groups, ARRAY_SIZE(jz4730_uart1_groups), }, + { "uart2", jz4730_uart2_groups, ARRAY_SIZE(jz4730_uart2_groups), }, + { "uart3", jz4730_uart3_groups, ARRAY_SIZE(jz4730_uart3_groups), }, + { "lcd", jz4730_lcd_groups, ARRAY_SIZE(jz4730_lcd_groups), }, + { "nand", jz4730_nand_groups, ARRAY_SIZE(jz4730_nand_groups), }, + { "pwm0", jz4730_pwm0_groups, ARRAY_SIZE(jz4730_pwm0_groups), }, + { "pwm1", jz4730_pwm1_groups, ARRAY_SIZE(jz4730_pwm1_groups), }, +}; + +static const struct ingenic_chip_info jz4730_chip_info = { + .num_chips = 4, + .reg_offset = 0x30, + .version = ID_JZ4730, + .groups = jz4730_groups, + .num_groups = ARRAY_SIZE(jz4730_groups), + .functions = jz4730_functions, + .num_functions = ARRAY_SIZE(jz4730_functions), + .pull_ups = jz4730_pull_ups, + .pull_downs = jz4730_pull_downs, +}; + static const u32 jz4740_pull_ups[4] = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, }; @@ -113,13 +242,15 @@ static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, }; static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, }; static int jz4740_lcd_8bit_pins[] = { - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x52, 0x53, 0x54, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, + 0x52, 0x53, 0x54, }; static int jz4740_lcd_16bit_pins[] = { - 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x55, + 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, }; static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, }; -static int jz4740_lcd_18bit_tft_pins[] = { 0x56, 0x57, 0x31, 0x32, }; +static int jz4740_lcd_special_pins[] = { 0x31, 0x32, 0x56, 0x57, }; +static int jz4740_lcd_generic_pins[] = { 0x55, }; static int jz4740_nand_cs1_pins[] = { 0x39, }; static int jz4740_nand_cs2_pins[] = { 0x3a, }; static int jz4740_nand_cs3_pins[] = { 0x3b, }; @@ -134,18 +265,6 @@ static int jz4740_pwm_pwm5_pins[] = { 0x7c, }; static int jz4740_pwm_pwm6_pins[] = { 0x7e, }; static int jz4740_pwm_pwm7_pins[] = { 0x7f, }; - -#define INGENIC_PIN_GROUP_FUNCS(name, id, funcs) \ - { \ - name, \ - id##_pins, \ - ARRAY_SIZE(id##_pins), \ - funcs, \ - } - -#define INGENIC_PIN_GROUP(name, id, func) \ - INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func)) - static const struct group_desc jz4740_groups[] = { INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0), INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0), @@ -155,8 +274,8 @@ static const struct group_desc jz4740_groups[] = { INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0), INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0), INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0), - INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft, 0), - { "lcd-no-pins", }, + INGENIC_PIN_GROUP("lcd-special", jz4740_lcd_special, 0), + INGENIC_PIN_GROUP("lcd-generic", jz4740_lcd_generic, 0), INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0), INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0), INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0), @@ -176,7 +295,7 @@ static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; static const char *jz4740_uart1_groups[] = { "uart1-data", }; static const char *jz4740_lcd_groups[] = { - "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins", + "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic", }; static const char *jz4740_nand_groups[] = { "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", @@ -223,6 +342,17 @@ static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, }; static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, }; static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, }; static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, }; +static int jz4725b_lcd_8bit_pins[] = { + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x72, 0x73, 0x74, +}; +static int jz4725b_lcd_16bit_pins[] = { + 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, +}; +static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, }; +static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, }; +static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; +static int jz4725b_lcd_generic_pins[] = { 0x75, }; static int jz4725b_nand_cs1_pins[] = { 0x55, }; static int jz4725b_nand_cs2_pins[] = { 0x56, }; static int jz4725b_nand_cs3_pins[] = { 0x57, }; @@ -235,19 +365,6 @@ static int jz4725b_pwm_pwm2_pins[] = { 0x4c, }; static int jz4725b_pwm_pwm3_pins[] = { 0x4d, }; static int jz4725b_pwm_pwm4_pins[] = { 0x4e, }; static int jz4725b_pwm_pwm5_pins[] = { 0x4f, }; -static int jz4725b_lcd_8bit_pins[] = { - 0x72, 0x73, 0x74, - 0x60, 0x61, 0x62, 0x63, - 0x64, 0x65, 0x66, 0x67, -}; -static int jz4725b_lcd_16bit_pins[] = { - 0x68, 0x69, 0x6a, 0x6b, - 0x6c, 0x6d, 0x6e, 0x6f, -}; -static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, }; -static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, }; -static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; -static int jz4725b_lcd_generic_pins[] = { 0x75, }; static u8 jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, }; @@ -258,6 +375,12 @@ static const struct group_desc jz4725b_groups[] = { INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0), INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0), INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1), + INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0), + INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0), + INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0), + INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1), + INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0), + INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0), INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0), INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0), INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0), @@ -270,17 +393,15 @@ static const struct group_desc jz4725b_groups[] = { INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3, 0), INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4, 0), INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5, 0), - INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0), - INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0), - INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0), - INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1), - INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0), - INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0), }; static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; static const char *jz4725b_uart_groups[] = { "uart-data", }; +static const char *jz4725b_lcd_groups[] = { + "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", + "lcd-special", "lcd-generic", +}; static const char *jz4725b_nand_groups[] = { "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-cle-ale", "nand-fre-fwe", @@ -291,10 +412,6 @@ static const char *jz4725b_pwm2_groups[] = { "pwm2", }; static const char *jz4725b_pwm3_groups[] = { "pwm3", }; static const char *jz4725b_pwm4_groups[] = { "pwm4", }; static const char *jz4725b_pwm5_groups[] = { "pwm5", }; -static const char *jz4725b_lcd_groups[] = { - "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", - "lcd-special", "lcd-generic", -}; static const struct function_desc jz4725b_functions[] = { { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), }, @@ -322,6 +439,275 @@ static const struct ingenic_chip_info jz4725b_chip_info = { .pull_downs = jz4740_pull_downs, }; +static const u32 jz4750_pull_ups[6] = { + 0xffffffff, 0xffffffff, 0x3fffffff, 0x7fffffff, 0x1fff3fff, 0x00ffffff, +}; + +static const u32 jz4750_pull_downs[6] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static int jz4750_uart0_data_pins[] = { 0xa4, 0xa5, }; +static int jz4750_uart0_hwflow_pins[] = { 0xa6, 0xa7, }; +static int jz4750_uart1_data_pins[] = { 0x90, 0x91, }; +static int jz4750_uart1_hwflow_pins[] = { 0x92, 0x93, }; +static int jz4750_uart2_data_pins[] = { 0x9b, 0x9a, }; +static int jz4750_uart3_data_pins[] = { 0xb0, 0xb1, }; +static int jz4750_uart3_hwflow_pins[] = { 0xb2, 0xb3, }; +static int jz4750_mmc0_1bit_pins[] = { 0xa8, 0xa9, 0xa0, }; +static int jz4750_mmc0_4bit_pins[] = { 0xa1, 0xa2, 0xa3, }; +static int jz4750_mmc0_8bit_pins[] = { 0xa4, 0xa5, 0xa6, 0xa7, }; +static int jz4750_mmc1_1bit_pins[] = { 0xae, 0xaf, 0xaa, }; +static int jz4750_mmc1_4bit_pins[] = { 0xab, 0xac, 0xad, }; +static int jz4750_i2c_pins[] = { 0x8c, 0x8d, }; +static int jz4750_cim_pins[] = { + 0x89, 0x8b, 0x8a, 0x88, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, +}; +static int jz4750_lcd_8bit_pins[] = { + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x72, 0x73, 0x74, +}; +static int jz4750_lcd_16bit_pins[] = { + 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, +}; +static int jz4750_lcd_18bit_pins[] = { 0x70, 0x71, }; +static int jz4750_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0xb2, 0xb3, }; +static int jz4750_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; +static int jz4750_lcd_generic_pins[] = { 0x75, }; +static int jz4750_nand_cs1_pins[] = { 0x55, }; +static int jz4750_nand_cs2_pins[] = { 0x56, }; +static int jz4750_nand_cs3_pins[] = { 0x57, }; +static int jz4750_nand_cs4_pins[] = { 0x58, }; +static int jz4750_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; +static int jz4750_pwm_pwm0_pins[] = { 0x94, }; +static int jz4750_pwm_pwm1_pins[] = { 0x95, }; +static int jz4750_pwm_pwm2_pins[] = { 0x96, }; +static int jz4750_pwm_pwm3_pins[] = { 0x97, }; +static int jz4750_pwm_pwm4_pins[] = { 0x98, }; +static int jz4750_pwm_pwm5_pins[] = { 0x99, }; + +static const struct group_desc jz4750_groups[] = { + INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1), + INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1), + INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0), + INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0), + INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1), + INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0), + INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0), + INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0), + INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0), + INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0), + INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0), + INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0), + INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0), + INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0), + INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0), + INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0), + INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0), + INGENIC_PIN_GROUP("lcd-24bit", jz4750_lcd_24bit, 1), + INGENIC_PIN_GROUP("lcd-special", jz4750_lcd_special, 0), + INGENIC_PIN_GROUP("lcd-generic", jz4750_lcd_generic, 0), + INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0), + INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0), + INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0), + INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0), + INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0), + INGENIC_PIN_GROUP("pwm0", jz4750_pwm_pwm0, 0), + INGENIC_PIN_GROUP("pwm1", jz4750_pwm_pwm1, 0), + INGENIC_PIN_GROUP("pwm2", jz4750_pwm_pwm2, 0), + INGENIC_PIN_GROUP("pwm3", jz4750_pwm_pwm3, 0), + INGENIC_PIN_GROUP("pwm4", jz4750_pwm_pwm4, 0), + INGENIC_PIN_GROUP("pwm5", jz4750_pwm_pwm5, 0), +}; + +static const char *jz4750_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; +static const char *jz4750_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; +static const char *jz4750_uart2_groups[] = { "uart2-data", }; +static const char *jz4750_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; +static const char *jz4750_mmc0_groups[] = { + "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", +}; +static const char *jz4750_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", }; +static const char *jz4750_i2c_groups[] = { "i2c-data", }; +static const char *jz4750_cim_groups[] = { "cim-data", }; +static const char *jz4750_lcd_groups[] = { + "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", + "lcd-special", "lcd-generic", +}; +static const char *jz4750_nand_groups[] = { + "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", +}; +static const char *jz4750_pwm0_groups[] = { "pwm0", }; +static const char *jz4750_pwm1_groups[] = { "pwm1", }; +static const char *jz4750_pwm2_groups[] = { "pwm2", }; +static const char *jz4750_pwm3_groups[] = { "pwm3", }; +static const char *jz4750_pwm4_groups[] = { "pwm4", }; +static const char *jz4750_pwm5_groups[] = { "pwm5", }; + +static const struct function_desc jz4750_functions[] = { + { "uart0", jz4750_uart0_groups, ARRAY_SIZE(jz4750_uart0_groups), }, + { "uart1", jz4750_uart1_groups, ARRAY_SIZE(jz4750_uart1_groups), }, + { "uart2", jz4750_uart2_groups, ARRAY_SIZE(jz4750_uart2_groups), }, + { "uart3", jz4750_uart3_groups, ARRAY_SIZE(jz4750_uart3_groups), }, + { "mmc0", jz4750_mmc0_groups, ARRAY_SIZE(jz4750_mmc0_groups), }, + { "mmc1", jz4750_mmc1_groups, ARRAY_SIZE(jz4750_mmc1_groups), }, + { "i2c", jz4750_i2c_groups, ARRAY_SIZE(jz4750_i2c_groups), }, + { "cim", jz4750_cim_groups, ARRAY_SIZE(jz4750_cim_groups), }, + { "lcd", jz4750_lcd_groups, ARRAY_SIZE(jz4750_lcd_groups), }, + { "nand", jz4750_nand_groups, ARRAY_SIZE(jz4750_nand_groups), }, + { "pwm0", jz4750_pwm0_groups, ARRAY_SIZE(jz4750_pwm0_groups), }, + { "pwm1", jz4750_pwm1_groups, ARRAY_SIZE(jz4750_pwm1_groups), }, + { "pwm2", jz4750_pwm2_groups, ARRAY_SIZE(jz4750_pwm2_groups), }, + { "pwm3", jz4750_pwm3_groups, ARRAY_SIZE(jz4750_pwm3_groups), }, + { "pwm4", jz4750_pwm4_groups, ARRAY_SIZE(jz4750_pwm4_groups), }, + { "pwm5", jz4750_pwm5_groups, ARRAY_SIZE(jz4750_pwm5_groups), }, +}; + +static const struct ingenic_chip_info jz4750_chip_info = { + .num_chips = 6, + .reg_offset = 0x100, + .version = ID_JZ4750, + .groups = jz4750_groups, + .num_groups = ARRAY_SIZE(jz4750_groups), + .functions = jz4750_functions, + .num_functions = ARRAY_SIZE(jz4750_functions), + .pull_ups = jz4750_pull_ups, + .pull_downs = jz4750_pull_downs, +}; + +static const u32 jz4755_pull_ups[6] = { + 0xffffffff, 0xffffffff, 0x0fffffff, 0xffffffff, 0x33dc3fff, 0x0000fc00, +}; + +static const u32 jz4755_pull_downs[6] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, }; +static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; +static int jz4755_uart1_data_pins[] = { 0x97, 0x99, }; +static int jz4755_uart2_data_pins[] = { 0x9f, }; +static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, }; +static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, }; +static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, }; +static int jz4755_mmc1_4bit_pins[] = { 0x3b, 0x3e, 0x3f, }; +static int jz4755_i2c_pins[] = { 0x8c, 0x8d, }; +static int jz4755_cim_pins[] = { + 0x89, 0x8b, 0x8a, 0x88, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, +}; +static int jz4755_lcd_8bit_pins[] = { + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x72, 0x73, 0x74, +}; +static int jz4755_lcd_16bit_pins[] = { + 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, +}; +static int jz4755_lcd_18bit_pins[] = { 0x70, 0x71, }; +static int jz4755_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, }; +static int jz4755_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; +static int jz4755_lcd_generic_pins[] = { 0x75, }; +static int jz4755_nand_cs1_pins[] = { 0x55, }; +static int jz4755_nand_cs2_pins[] = { 0x56, }; +static int jz4755_nand_cs3_pins[] = { 0x57, }; +static int jz4755_nand_cs4_pins[] = { 0x58, }; +static int jz4755_nand_fre_fwe_pins[] = { 0x5c, 0x5d, }; +static int jz4755_pwm_pwm0_pins[] = { 0x94, }; +static int jz4755_pwm_pwm1_pins[] = { 0xab, }; +static int jz4755_pwm_pwm2_pins[] = { 0x96, }; +static int jz4755_pwm_pwm3_pins[] = { 0x97, }; +static int jz4755_pwm_pwm4_pins[] = { 0x98, }; +static int jz4755_pwm_pwm5_pins[] = { 0x99, }; + +static u8 jz4755_mmc0_1bit_funcs[] = { 2, 2, 1, }; +static u8 jz4755_mmc0_4bit_funcs[] = { 1, 0, 1, }; +static u8 jz4755_lcd_24bit_funcs[] = { 1, 1, 1, 1, 0, 0, }; + +static const struct group_desc jz4755_groups[] = { + INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0), + INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0), + INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 0), + INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1), + INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit, + jz4755_mmc0_1bit_funcs), + INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit, + jz4755_mmc0_4bit_funcs), + INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1), + INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1), + INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0), + INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0), + INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0), + INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0), + INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0), + INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit, + jz4755_lcd_24bit_funcs), + INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0), + INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0), + INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0), + INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0), + INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0), + INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0), + INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0), + INGENIC_PIN_GROUP("pwm0", jz4755_pwm_pwm0, 0), + INGENIC_PIN_GROUP("pwm1", jz4755_pwm_pwm1, 1), + INGENIC_PIN_GROUP("pwm2", jz4755_pwm_pwm2, 0), + INGENIC_PIN_GROUP("pwm3", jz4755_pwm_pwm3, 0), + INGENIC_PIN_GROUP("pwm4", jz4755_pwm_pwm4, 0), + INGENIC_PIN_GROUP("pwm5", jz4755_pwm_pwm5, 0), +}; + +static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; +static const char *jz4755_uart1_groups[] = { "uart1-data", }; +static const char *jz4755_uart2_groups[] = { "uart2-data", }; +static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; +static const char *jz4755_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", }; +static const char *jz4755_i2c_groups[] = { "i2c-data", }; +static const char *jz4755_cim_groups[] = { "cim-data", }; +static const char *jz4755_lcd_groups[] = { + "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", + "lcd-special", "lcd-generic", +}; +static const char *jz4755_nand_groups[] = { + "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe", +}; +static const char *jz4755_pwm0_groups[] = { "pwm0", }; +static const char *jz4755_pwm1_groups[] = { "pwm1", }; +static const char *jz4755_pwm2_groups[] = { "pwm2", }; +static const char *jz4755_pwm3_groups[] = { "pwm3", }; +static const char *jz4755_pwm4_groups[] = { "pwm4", }; +static const char *jz4755_pwm5_groups[] = { "pwm5", }; + +static const struct function_desc jz4755_functions[] = { + { "uart0", jz4755_uart0_groups, ARRAY_SIZE(jz4755_uart0_groups), }, + { "uart1", jz4755_uart1_groups, ARRAY_SIZE(jz4755_uart1_groups), }, + { "uart2", jz4755_uart2_groups, ARRAY_SIZE(jz4755_uart2_groups), }, + { "mmc0", jz4755_mmc0_groups, ARRAY_SIZE(jz4755_mmc0_groups), }, + { "mmc1", jz4755_mmc1_groups, ARRAY_SIZE(jz4755_mmc1_groups), }, + { "i2c", jz4755_i2c_groups, ARRAY_SIZE(jz4755_i2c_groups), }, + { "cim", jz4755_cim_groups, ARRAY_SIZE(jz4755_cim_groups), }, + { "lcd", jz4755_lcd_groups, ARRAY_SIZE(jz4755_lcd_groups), }, + { "nand", jz4755_nand_groups, ARRAY_SIZE(jz4755_nand_groups), }, + { "pwm0", jz4755_pwm0_groups, ARRAY_SIZE(jz4755_pwm0_groups), }, + { "pwm1", jz4755_pwm1_groups, ARRAY_SIZE(jz4755_pwm1_groups), }, + { "pwm2", jz4755_pwm2_groups, ARRAY_SIZE(jz4755_pwm2_groups), }, + { "pwm3", jz4755_pwm3_groups, ARRAY_SIZE(jz4755_pwm3_groups), }, + { "pwm4", jz4755_pwm4_groups, ARRAY_SIZE(jz4755_pwm4_groups), }, + { "pwm5", jz4755_pwm5_groups, ARRAY_SIZE(jz4755_pwm5_groups), }, +}; + +static const struct ingenic_chip_info jz4755_chip_info = { + .num_chips = 6, + .reg_offset = 0x100, + .version = ID_JZ4755, + .groups = jz4755_groups, + .num_groups = ARRAY_SIZE(jz4755_groups), + .functions = jz4755_functions, + .num_functions = ARRAY_SIZE(jz4755_functions), + .pull_ups = jz4755_pull_ups, + .pull_downs = jz4755_pull_downs, +}; + static const u32 jz4760_pull_ups[6] = { 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f, }; @@ -389,7 +775,7 @@ static int jz4760_lcd_18bit_pins[] = { static int jz4760_lcd_24bit_pins[] = { 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55, }; -static int jz4760_lcd_special_pins[] = { 0x40, 0x41, 0x4a, 0x54 }; +static int jz4760_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; static int jz4760_lcd_generic_pins[] = { 0x49, }; static int jz4760_pwm_pwm0_pins[] = { 0x80, }; static int jz4760_pwm_pwm1_pins[] = { 0x81, }; @@ -450,8 +836,8 @@ static const struct group_desc jz4760_groups[] = { INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0), INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0), INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0), - INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0), INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1), + INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0), INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0), INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0), INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0), @@ -648,7 +1034,13 @@ static int jz4770_cim_12bit_pins[] = { }; static int jz4770_lcd_8bit_pins[] = { 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d, - 0x48, 0x49, 0x52, 0x53, + 0x48, 0x52, 0x53, +}; +static int jz4770_lcd_16bit_pins[] = { + 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, +}; +static int jz4770_lcd_18bit_pins[] = { + 0x5a, 0x5b, }; static int jz4770_lcd_24bit_pins[] = { 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, @@ -656,6 +1048,8 @@ static int jz4770_lcd_24bit_pins[] = { 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, }; +static int jz4770_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; +static int jz4770_lcd_generic_pins[] = { 0x49, }; static int jz4770_pwm_pwm0_pins[] = { 0x80, }; static int jz4770_pwm_pwm1_pins[] = { 0x81, }; static int jz4770_pwm_pwm2_pins[] = { 0x82, }; @@ -667,7 +1061,9 @@ static int jz4770_pwm_pwm7_pins[] = { 0x6b, }; static int jz4770_mac_rmii_pins[] = { 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, }; -static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, }; +static int jz4770_mac_mii_pins[] = { + 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf, +}; static const struct group_desc jz4770_groups[] = { INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), @@ -754,8 +1150,11 @@ static const struct group_desc jz4770_groups[] = { INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0), INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0), INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0), + INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0), + INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0), INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0), - { "lcd-no-pins", }, + INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1), + INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0), INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0), INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0), INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0), @@ -816,7 +1215,8 @@ static const char *jz4770_i2c1_groups[] = { "i2c1-data", }; static const char *jz4770_i2c2_groups[] = { "i2c2-data", }; static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; static const char *jz4770_lcd_groups[] = { - "lcd-8bit", "lcd-24bit", "lcd-no-pins", + "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", + "lcd-special", "lcd-generic", }; static const char *jz4770_pwm0_groups[] = { "pwm0", }; static const char *jz4770_pwm1_groups[] = { "pwm1", }; @@ -874,6 +1274,279 @@ static const struct ingenic_chip_info jz4770_chip_info = { .pull_downs = jz4770_pull_downs, }; +static const u32 jz4775_pull_ups[7] = { + 0x28ff00ff, 0xf030f3fc, 0x0fffffff, 0xfffe4000, 0xf0f0000c, 0x0000f00f, 0x0000f3c0, +}; + +static const u32 jz4775_pull_downs[7] = { + 0x00000000, 0x00030c03, 0x00000000, 0x00008000, 0x00000403, 0x00000ff0, 0x00030c00, +}; + +static int jz4775_uart0_data_pins[] = { 0xa0, 0xa3, }; +static int jz4775_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; +static int jz4775_uart1_data_pins[] = { 0x7a, 0x7c, }; +static int jz4775_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; +static int jz4775_uart2_data_c_pins[] = { 0x54, 0x4a, }; +static int jz4775_uart2_data_f_pins[] = { 0xa5, 0xa4, }; +static int jz4775_uart3_data_pins[] = { 0x1e, 0x1f, }; +static int jz4775_ssi_dt_a_pins[] = { 0x13, }; +static int jz4775_ssi_dt_d_pins[] = { 0x75, }; +static int jz4775_ssi_dr_a_pins[] = { 0x14, }; +static int jz4775_ssi_dr_d_pins[] = { 0x74, }; +static int jz4775_ssi_clk_a_pins[] = { 0x12, }; +static int jz4775_ssi_clk_d_pins[] = { 0x78, }; +static int jz4775_ssi_gpc_pins[] = { 0x76, }; +static int jz4775_ssi_ce0_a_pins[] = { 0x17, }; +static int jz4775_ssi_ce0_d_pins[] = { 0x79, }; +static int jz4775_ssi_ce1_pins[] = { 0x77, }; +static int jz4775_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; +static int jz4775_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; +static int jz4775_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, }; +static int jz4775_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; +static int jz4775_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; +static int jz4775_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; +static int jz4775_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; +static int jz4775_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; +static int jz4775_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; +static int jz4775_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; +static int jz4775_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; +static int jz4775_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; +static int jz4775_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; +static int jz4775_nemc_8bit_data_pins[] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, +}; +static int jz4775_nemc_16bit_data_pins[] = { + 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1, +}; +static int jz4775_nemc_cle_ale_pins[] = { 0x20, 0x21, }; +static int jz4775_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; +static int jz4775_nemc_rd_we_pins[] = { 0x10, 0x11, }; +static int jz4775_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; +static int jz4775_nemc_wait_pins[] = { 0x1b, }; +static int jz4775_nemc_cs1_pins[] = { 0x15, }; +static int jz4775_nemc_cs2_pins[] = { 0x16, }; +static int jz4775_nemc_cs3_pins[] = { 0x17, }; +static int jz4775_i2c0_pins[] = { 0x7e, 0x7f, }; +static int jz4775_i2c1_pins[] = { 0x9e, 0x9f, }; +static int jz4775_i2c2_pins[] = { 0x80, 0x83, }; +static int jz4775_i2s_data_tx_pins[] = { 0xa3, }; +static int jz4775_i2s_data_rx_pins[] = { 0xa2, }; +static int jz4775_i2s_clk_txrx_pins[] = { 0xa0, 0xa1, }; +static int jz4775_i2s_sysclk_pins[] = { 0x83, }; +static int jz4775_dmic_pins[] = { 0xaa, 0xab, }; +static int jz4775_cim_pins[] = { + 0x26, 0x27, 0x28, 0x29, + 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, +}; +static int jz4775_lcd_8bit_pins[] = { + 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d, + 0x48, 0x52, 0x53, +}; +static int jz4775_lcd_16bit_pins[] = { + 0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59, +}; +static int jz4775_lcd_18bit_pins[] = { + 0x5a, 0x5b, +}; +static int jz4775_lcd_24bit_pins[] = { + 0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55, +}; +static int jz4775_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, }; +static int jz4775_lcd_generic_pins[] = { 0x49, }; +static int jz4775_pwm_pwm0_pins[] = { 0x80, }; +static int jz4775_pwm_pwm1_pins[] = { 0x81, }; +static int jz4775_pwm_pwm2_pins[] = { 0x82, }; +static int jz4775_pwm_pwm3_pins[] = { 0x83, }; +static int jz4775_mac_rmii_pins[] = { + 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, +}; +static int jz4775_mac_mii_pins[] = { + 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf, +}; +static int jz4775_mac_rgmii_pins[] = { + 0xa9, 0x7b, 0x7a, 0xab, 0xaa, 0xac, 0x7d, 0x7c, 0xa5, 0xa4, + 0xad, 0xae, 0xa7, 0xa6, +}; +static int jz4775_mac_gmii_pins[] = { + 0x31, 0x30, 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, + 0xa8, 0x28, 0x24, 0xaf, +}; +static int jz4775_otg_pins[] = { 0x8a, }; + +static u8 jz4775_uart3_data_funcs[] = { 0, 1, }; +static u8 jz4775_mac_mii_funcs[] = { 1, 1, 1, 1, 0, 1, 0, }; +static u8 jz4775_mac_rgmii_funcs[] = { + 0, 1, 1, 0, 0, 0, 1, 1, 0, 0, + 0, 0, 0, 0, +}; +static u8 jz4775_mac_gmii_funcs[] = { + 1, 1, 1, 1, 1, 1, 1, 1, + 0, 1, 1, 0, +}; + +static const struct group_desc jz4775_groups[] = { + INGENIC_PIN_GROUP("uart0-data", jz4775_uart0_data, 0), + INGENIC_PIN_GROUP("uart0-hwflow", jz4775_uart0_hwflow, 0), + INGENIC_PIN_GROUP("uart1-data", jz4775_uart1_data, 0), + INGENIC_PIN_GROUP("uart1-hwflow", jz4775_uart1_hwflow, 0), + INGENIC_PIN_GROUP("uart2-data-c", jz4775_uart2_data_c, 2), + INGENIC_PIN_GROUP("uart2-data-f", jz4775_uart2_data_f, 1), + INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4775_uart3_data, + jz4775_uart3_data_funcs), + INGENIC_PIN_GROUP("ssi-dt-a", jz4775_ssi_dt_a, 2), + INGENIC_PIN_GROUP("ssi-dt-d", jz4775_ssi_dt_d, 1), + INGENIC_PIN_GROUP("ssi-dr-a", jz4775_ssi_dr_a, 2), + INGENIC_PIN_GROUP("ssi-dr-d", jz4775_ssi_dr_d, 1), + INGENIC_PIN_GROUP("ssi-clk-a", jz4775_ssi_clk_a, 2), + INGENIC_PIN_GROUP("ssi-clk-d", jz4775_ssi_clk_d, 1), + INGENIC_PIN_GROUP("ssi-gpc", jz4775_ssi_gpc, 1), + INGENIC_PIN_GROUP("ssi-ce0-a", jz4775_ssi_ce0_a, 2), + INGENIC_PIN_GROUP("ssi-ce0-d", jz4775_ssi_ce0_d, 1), + INGENIC_PIN_GROUP("ssi-ce1", jz4775_ssi_ce1, 1), + INGENIC_PIN_GROUP("mmc0-1bit-a", jz4775_mmc0_1bit_a, 1), + INGENIC_PIN_GROUP("mmc0-4bit-a", jz4775_mmc0_4bit_a, 1), + INGENIC_PIN_GROUP("mmc0-8bit-a", jz4775_mmc0_8bit_a, 1), + INGENIC_PIN_GROUP("mmc0-1bit-e", jz4775_mmc0_1bit_e, 0), + INGENIC_PIN_GROUP("mmc0-4bit-e", jz4775_mmc0_4bit_e, 0), + INGENIC_PIN_GROUP("mmc1-1bit-d", jz4775_mmc1_1bit_d, 0), + INGENIC_PIN_GROUP("mmc1-4bit-d", jz4775_mmc1_4bit_d, 0), + INGENIC_PIN_GROUP("mmc1-1bit-e", jz4775_mmc1_1bit_e, 1), + INGENIC_PIN_GROUP("mmc1-4bit-e", jz4775_mmc1_4bit_e, 1), + INGENIC_PIN_GROUP("mmc2-1bit-b", jz4775_mmc2_1bit_b, 0), + INGENIC_PIN_GROUP("mmc2-4bit-b", jz4775_mmc2_4bit_b, 0), + INGENIC_PIN_GROUP("mmc2-1bit-e", jz4775_mmc2_1bit_e, 2), + INGENIC_PIN_GROUP("mmc2-4bit-e", jz4775_mmc2_4bit_e, 2), + INGENIC_PIN_GROUP("nemc-8bit-data", jz4775_nemc_8bit_data, 0), + INGENIC_PIN_GROUP("nemc-16bit-data", jz4775_nemc_16bit_data, 1), + INGENIC_PIN_GROUP("nemc-cle-ale", jz4775_nemc_cle_ale, 0), + INGENIC_PIN_GROUP("nemc-addr", jz4775_nemc_addr, 0), + INGENIC_PIN_GROUP("nemc-rd-we", jz4775_nemc_rd_we, 0), + INGENIC_PIN_GROUP("nemc-frd-fwe", jz4775_nemc_frd_fwe, 0), + INGENIC_PIN_GROUP("nemc-wait", jz4775_nemc_wait, 0), + INGENIC_PIN_GROUP("nemc-cs1", jz4775_nemc_cs1, 0), + INGENIC_PIN_GROUP("nemc-cs2", jz4775_nemc_cs2, 0), + INGENIC_PIN_GROUP("nemc-cs3", jz4775_nemc_cs3, 0), + INGENIC_PIN_GROUP("i2c0-data", jz4775_i2c0, 0), + INGENIC_PIN_GROUP("i2c1-data", jz4775_i2c1, 0), + INGENIC_PIN_GROUP("i2c2-data", jz4775_i2c2, 1), + INGENIC_PIN_GROUP("i2s-data-tx", jz4775_i2s_data_tx, 1), + INGENIC_PIN_GROUP("i2s-data-rx", jz4775_i2s_data_rx, 1), + INGENIC_PIN_GROUP("i2s-clk-txrx", jz4775_i2s_clk_txrx, 1), + INGENIC_PIN_GROUP("i2s-sysclk", jz4775_i2s_sysclk, 2), + INGENIC_PIN_GROUP("dmic", jz4775_dmic, 1), + INGENIC_PIN_GROUP("cim-data", jz4775_cim, 0), + INGENIC_PIN_GROUP("lcd-8bit", jz4775_lcd_8bit, 0), + INGENIC_PIN_GROUP("lcd-16bit", jz4775_lcd_16bit, 0), + INGENIC_PIN_GROUP("lcd-18bit", jz4775_lcd_18bit, 0), + INGENIC_PIN_GROUP("lcd-24bit", jz4775_lcd_24bit, 0), + INGENIC_PIN_GROUP("lcd-generic", jz4775_lcd_generic, 0), + INGENIC_PIN_GROUP("lcd-special", jz4775_lcd_special, 1), + INGENIC_PIN_GROUP("pwm0", jz4775_pwm_pwm0, 0), + INGENIC_PIN_GROUP("pwm1", jz4775_pwm_pwm1, 0), + INGENIC_PIN_GROUP("pwm2", jz4775_pwm_pwm2, 0), + INGENIC_PIN_GROUP("pwm3", jz4775_pwm_pwm3, 0), + INGENIC_PIN_GROUP("mac-rmii", jz4775_mac_rmii, 0), + INGENIC_PIN_GROUP_FUNCS("mac-mii", jz4775_mac_mii, + jz4775_mac_mii_funcs), + INGENIC_PIN_GROUP_FUNCS("mac-rgmii", jz4775_mac_rgmii, + jz4775_mac_rgmii_funcs), + INGENIC_PIN_GROUP_FUNCS("mac-gmii", jz4775_mac_gmii, + jz4775_mac_gmii_funcs), + INGENIC_PIN_GROUP("otg-vbus", jz4775_otg, 0), +}; + +static const char *jz4775_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; +static const char *jz4775_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; +static const char *jz4775_uart2_groups[] = { "uart2-data-c", "uart2-data-f", }; +static const char *jz4775_uart3_groups[] = { "uart3-data", }; +static const char *jz4775_ssi_groups[] = { + "ssi-dt-a", "ssi-dt-d", + "ssi-dr-a", "ssi-dr-d", + "ssi-clk-a", "ssi-clk-d", + "ssi-gpc", + "ssi-ce0-a", "ssi-ce0-d", + "ssi-ce1", +}; +static const char *jz4775_mmc0_groups[] = { + "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", + "mmc0-1bit-e", "mmc0-4bit-e", +}; +static const char *jz4775_mmc1_groups[] = { + "mmc1-1bit-d", "mmc1-4bit-d", + "mmc1-1bit-e", "mmc1-4bit-e", +}; +static const char *jz4775_mmc2_groups[] = { + "mmc2-1bit-b", "mmc2-4bit-b", + "mmc2-1bit-e", "mmc2-4bit-e", +}; +static const char *jz4775_nemc_groups[] = { + "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", + "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", +}; +static const char *jz4775_cs1_groups[] = { "nemc-cs1", }; +static const char *jz4775_cs2_groups[] = { "nemc-cs2", }; +static const char *jz4775_cs3_groups[] = { "nemc-cs3", }; +static const char *jz4775_i2c0_groups[] = { "i2c0-data", }; +static const char *jz4775_i2c1_groups[] = { "i2c1-data", }; +static const char *jz4775_i2c2_groups[] = { "i2c2-data", }; +static const char *jz4775_i2s_groups[] = { + "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", +}; +static const char *jz4775_dmic_groups[] = { "dmic", }; +static const char *jz4775_cim_groups[] = { "cim-data", }; +static const char *jz4775_lcd_groups[] = { + "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", + "lcd-special", "lcd-generic", +}; +static const char *jz4775_pwm0_groups[] = { "pwm0", }; +static const char *jz4775_pwm1_groups[] = { "pwm1", }; +static const char *jz4775_pwm2_groups[] = { "pwm2", }; +static const char *jz4775_pwm3_groups[] = { "pwm3", }; +static const char *jz4775_mac_groups[] = { + "mac-rmii", "mac-mii", "mac-rgmii", "mac-gmii", +}; +static const char *jz4775_otg_groups[] = { "otg-vbus", }; + +static const struct function_desc jz4775_functions[] = { + { "uart0", jz4775_uart0_groups, ARRAY_SIZE(jz4775_uart0_groups), }, + { "uart1", jz4775_uart1_groups, ARRAY_SIZE(jz4775_uart1_groups), }, + { "uart2", jz4775_uart2_groups, ARRAY_SIZE(jz4775_uart2_groups), }, + { "uart3", jz4775_uart3_groups, ARRAY_SIZE(jz4775_uart3_groups), }, + { "ssi", jz4775_ssi_groups, ARRAY_SIZE(jz4775_ssi_groups), }, + { "mmc0", jz4775_mmc0_groups, ARRAY_SIZE(jz4775_mmc0_groups), }, + { "mmc1", jz4775_mmc1_groups, ARRAY_SIZE(jz4775_mmc1_groups), }, + { "mmc2", jz4775_mmc2_groups, ARRAY_SIZE(jz4775_mmc2_groups), }, + { "nemc", jz4775_nemc_groups, ARRAY_SIZE(jz4775_nemc_groups), }, + { "nemc-cs1", jz4775_cs1_groups, ARRAY_SIZE(jz4775_cs1_groups), }, + { "nemc-cs2", jz4775_cs2_groups, ARRAY_SIZE(jz4775_cs2_groups), }, + { "nemc-cs3", jz4775_cs3_groups, ARRAY_SIZE(jz4775_cs3_groups), }, + { "i2c0", jz4775_i2c0_groups, ARRAY_SIZE(jz4775_i2c0_groups), }, + { "i2c1", jz4775_i2c1_groups, ARRAY_SIZE(jz4775_i2c1_groups), }, + { "i2c2", jz4775_i2c2_groups, ARRAY_SIZE(jz4775_i2c2_groups), }, + { "i2s", jz4775_i2s_groups, ARRAY_SIZE(jz4775_i2s_groups), }, + { "dmic", jz4775_dmic_groups, ARRAY_SIZE(jz4775_dmic_groups), }, + { "cim", jz4775_cim_groups, ARRAY_SIZE(jz4775_cim_groups), }, + { "lcd", jz4775_lcd_groups, ARRAY_SIZE(jz4775_lcd_groups), }, + { "pwm0", jz4775_pwm0_groups, ARRAY_SIZE(jz4775_pwm0_groups), }, + { "pwm1", jz4775_pwm1_groups, ARRAY_SIZE(jz4775_pwm1_groups), }, + { "pwm2", jz4775_pwm2_groups, ARRAY_SIZE(jz4775_pwm2_groups), }, + { "pwm3", jz4775_pwm3_groups, ARRAY_SIZE(jz4775_pwm3_groups), }, + { "mac", jz4775_mac_groups, ARRAY_SIZE(jz4775_mac_groups), }, + { "otg", jz4775_otg_groups, ARRAY_SIZE(jz4775_otg_groups), }, +}; + +static const struct ingenic_chip_info jz4775_chip_info = { + .num_chips = 7, + .reg_offset = 0x100, + .version = ID_JZ4775, + .groups = jz4775_groups, + .num_groups = ARRAY_SIZE(jz4775_groups), + .functions = jz4775_functions, + .num_functions = ARRAY_SIZE(jz4775_functions), + .pull_ups = jz4775_pull_ups, + .pull_downs = jz4775_pull_downs, +}; + static const u32 jz4780_pull_ups[6] = { 0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f, }; @@ -927,6 +1600,7 @@ static int jz4780_i2s_data_rx_pins[] = { 0x86, }; static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, }; static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, }; static int jz4780_i2s_sysclk_pins[] = { 0x85, }; +static int jz4780_dmic_pins[] = { 0x32, 0x33, }; static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, }; static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, }; @@ -1025,11 +1699,16 @@ static const struct group_desc jz4780_groups[] = { jz4780_i2s_clk_txrx_funcs), INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1), INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2), + INGENIC_PIN_GROUP("dmic", jz4780_dmic, 1), INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0), INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0), INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0), + INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0), + INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0), + INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0), INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0), - { "lcd-no-pins", }, + INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1), + INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0), INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0), INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0), INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0), @@ -1077,6 +1756,7 @@ static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", }; static const char *jz4780_i2s_groups[] = { "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", }; +static const char *jz4780_dmic_groups[] = { "dmic", }; static const char *jz4780_cim_groups[] = { "cim-data", }; static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", }; @@ -1104,6 +1784,7 @@ static const struct function_desc jz4780_functions[] = { { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), }, { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), }, { "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), }, + { "dmic", jz4780_dmic_groups, ARRAY_SIZE(jz4780_dmic_groups), }, { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), }, { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, @@ -1189,6 +1870,8 @@ static int x1000_i2s_data_tx_pins[] = { 0x24, }; static int x1000_i2s_data_rx_pins[] = { 0x23, }; static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; static int x1000_i2s_sysclk_pins[] = { 0x20, }; +static int x1000_dmic0_pins[] = { 0x35, 0x36, }; +static int x1000_dmic1_pins[] = { 0x25, }; static int x1000_cim_pins[] = { 0x08, 0x09, 0x0a, 0x0b, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, @@ -1254,10 +1937,11 @@ static const struct group_desc x1000_groups[] = { INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1), INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1), INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1), + INGENIC_PIN_GROUP("dmic0", x1000_dmic0, 0), + INGENIC_PIN_GROUP("dmic1", x1000_dmic1, 1), INGENIC_PIN_GROUP("cim-data", x1000_cim, 2), INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1), INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1), - { "lcd-no-pins", }, INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0, 0), INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1, 1), INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2, 1), @@ -1298,10 +1982,9 @@ static const char *x1000_i2c2_groups[] = { "i2c2-data", }; static const char *x1000_i2s_groups[] = { "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", }; +static const char *x1000_dmic_groups[] = { "dmic0", "dmic1", }; static const char *x1000_cim_groups[] = { "cim-data", }; -static const char *x1000_lcd_groups[] = { - "lcd-8bit", "lcd-16bit", "lcd-no-pins", -}; +static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", }; static const char *x1000_pwm0_groups[] = { "pwm0", }; static const char *x1000_pwm1_groups[] = { "pwm1", }; static const char *x1000_pwm2_groups[] = { "pwm2", }; @@ -1324,6 +2007,7 @@ static const struct function_desc x1000_functions[] = { { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), }, { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), }, { "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), }, + { "dmic", x1000_dmic_groups, ARRAY_SIZE(x1000_dmic_groups), }, { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), }, { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), }, { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), }, @@ -1363,6 +2047,8 @@ static int x1500_i2s_data_tx_pins[] = { 0x24, }; static int x1500_i2s_data_rx_pins[] = { 0x23, }; static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; static int x1500_i2s_sysclk_pins[] = { 0x20, }; +static int x1500_dmic0_pins[] = { 0x35, 0x36, }; +static int x1500_dmic1_pins[] = { 0x25, }; static int x1500_cim_pins[] = { 0x08, 0x09, 0x0a, 0x0b, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, @@ -1392,8 +2078,9 @@ static const struct group_desc x1500_groups[] = { INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1), INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1), INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1), + INGENIC_PIN_GROUP("dmic0", x1500_dmic0, 0), + INGENIC_PIN_GROUP("dmic1", x1500_dmic1, 1), INGENIC_PIN_GROUP("cim-data", x1500_cim, 2), - { "lcd-no-pins", }, INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0), INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1), INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2, 1), @@ -1413,8 +2100,8 @@ static const char *x1500_i2c2_groups[] = { "i2c2-data", }; static const char *x1500_i2s_groups[] = { "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", }; +static const char *x1500_dmic_groups[] = { "dmic0", "dmic1", }; static const char *x1500_cim_groups[] = { "cim-data", }; -static const char *x1500_lcd_groups[] = { "lcd-no-pins", }; static const char *x1500_pwm0_groups[] = { "pwm0", }; static const char *x1500_pwm1_groups[] = { "pwm1", }; static const char *x1500_pwm2_groups[] = { "pwm2", }; @@ -1431,8 +2118,8 @@ static const struct function_desc x1500_functions[] = { { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), }, { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), }, { "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), }, + { "dmic", x1500_dmic_groups, ARRAY_SIZE(x1500_dmic_groups), }, { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), }, - { "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), }, { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), }, { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), }, { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), }, @@ -1471,16 +2158,16 @@ static int x1830_ssi0_gpc_pins[] = { 0x4d, }; static int x1830_ssi0_ce0_pins[] = { 0x50, }; static int x1830_ssi0_ce1_pins[] = { 0x4e, }; static int x1830_ssi1_dt_c_pins[] = { 0x53, }; -static int x1830_ssi1_dr_c_pins[] = { 0x54, }; -static int x1830_ssi1_clk_c_pins[] = { 0x57, }; -static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; -static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; -static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; static int x1830_ssi1_dt_d_pins[] = { 0x62, }; +static int x1830_ssi1_dr_c_pins[] = { 0x54, }; static int x1830_ssi1_dr_d_pins[] = { 0x63, }; +static int x1830_ssi1_clk_c_pins[] = { 0x57, }; static int x1830_ssi1_clk_d_pins[] = { 0x66, }; +static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; static int x1830_ssi1_gpc_d_pins[] = { 0x64, }; +static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; static int x1830_ssi1_ce0_d_pins[] = { 0x67, }; +static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; static int x1830_ssi1_ce1_d_pins[] = { 0x65, }; static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, }; static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, }; @@ -1494,11 +2181,15 @@ static int x1830_i2s_data_rx_pins[] = { 0x54, }; static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, }; static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, }; static int x1830_i2s_sysclk_pins[] = { 0x57, }; -static int x1830_lcd_rgb_18bit_pins[] = { +static int x1830_dmic0_pins[] = { 0x48, 0x59, }; +static int x1830_dmic1_pins[] = { 0x5a, }; +static int x1830_lcd_tft_8bit_pins[] = { 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, - 0x68, 0x69, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x76, 0x77, - 0x78, 0x79, 0x7a, 0x7b, + 0x68, 0x73, 0x72, 0x69, +}; +static int x1830_lcd_tft_24bit_pins[] = { + 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, + 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, }; static int x1830_lcd_slcd_8bit_pins[] = { 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d, @@ -1562,10 +2253,12 @@ static const struct group_desc x1830_groups[] = { INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0), INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0), INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0), - INGENIC_PIN_GROUP("lcd-rgb-18bit", x1830_lcd_rgb_18bit, 0), + INGENIC_PIN_GROUP("dmic0", x1830_dmic0, 2), + INGENIC_PIN_GROUP("dmic1", x1830_dmic1, 2), + INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0), + INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0), INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1), INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1), - { "lcd-no-pins", }, INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0), INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1), INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0), @@ -1607,8 +2300,9 @@ static const char *x1830_i2c2_groups[] = { "i2c2-data", }; static const char *x1830_i2s_groups[] = { "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", }; +static const char *x1830_dmic_groups[] = { "dmic0", "dmic1", }; static const char *x1830_lcd_groups[] = { - "lcd-rgb-18bit", "lcd-slcd-8bit", "lcd-slcd-16bit", "lcd-no-pins", + "lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit", }; static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", }; static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", }; @@ -1632,6 +2326,7 @@ static const struct function_desc x1830_functions[] = { { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), }, { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), }, { "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), }, + { "dmic", x1830_dmic_groups, ARRAY_SIZE(x1830_dmic_groups), }, { "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), }, { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), }, { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), }, @@ -1656,6 +2351,456 @@ static const struct ingenic_chip_info x1830_chip_info = { .pull_downs = x1830_pull_downs, }; +static const u32 x2000_pull_ups[5] = { + 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x8fff003f, +}; + +static const u32 x2000_pull_downs[5] = { + 0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x8fff003f, +}; + +static int x2000_uart0_data_pins[] = { 0x77, 0x78, }; +static int x2000_uart0_hwflow_pins[] = { 0x79, 0x7a, }; +static int x2000_uart1_data_pins[] = { 0x57, 0x58, }; +static int x2000_uart1_hwflow_pins[] = { 0x55, 0x56, }; +static int x2000_uart2_data_pins[] = { 0x7e, 0x7f, }; +static int x2000_uart3_data_c_pins[] = { 0x59, 0x5a, }; +static int x2000_uart3_data_d_pins[] = { 0x62, 0x63, }; +static int x2000_uart3_hwflow_c_pins[] = { 0x5b, 0x5c, }; +static int x2000_uart3_hwflow_d_pins[] = { 0x60, 0x61, }; +static int x2000_uart4_data_a_pins[] = { 0x02, 0x03, }; +static int x2000_uart4_data_c_pins[] = { 0x4b, 0x4c, }; +static int x2000_uart4_hwflow_a_pins[] = { 0x00, 0x01, }; +static int x2000_uart4_hwflow_c_pins[] = { 0x49, 0x4a, }; +static int x2000_uart5_data_a_pins[] = { 0x04, 0x05, }; +static int x2000_uart5_data_c_pins[] = { 0x45, 0x46, }; +static int x2000_uart6_data_a_pins[] = { 0x06, 0x07, }; +static int x2000_uart6_data_c_pins[] = { 0x47, 0x48, }; +static int x2000_uart7_data_a_pins[] = { 0x08, 0x09, }; +static int x2000_uart7_data_c_pins[] = { 0x41, 0x42, }; +static int x2000_uart8_data_pins[] = { 0x3c, 0x3d, }; +static int x2000_uart9_data_pins[] = { 0x3e, 0x3f, }; +static int x2000_sfc0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, 0x71, 0x72, }; +static int x2000_sfc0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, 0x90, 0x91, }; +static int x2000_sfc1_pins[] = { 0x77, 0x78, 0x79, 0x7a, }; +static int x2000_ssi0_dt_b_pins[] = { 0x3e, }; +static int x2000_ssi0_dt_d_pins[] = { 0x69, }; +static int x2000_ssi0_dr_b_pins[] = { 0x3d, }; +static int x2000_ssi0_dr_d_pins[] = { 0x6a, }; +static int x2000_ssi0_clk_b_pins[] = { 0x3f, }; +static int x2000_ssi0_clk_d_pins[] = { 0x68, }; +static int x2000_ssi0_ce0_b_pins[] = { 0x3c, }; +static int x2000_ssi0_ce0_d_pins[] = { 0x6d, }; +static int x2000_ssi1_dt_c_pins[] = { 0x4b, }; +static int x2000_ssi1_dt_d_pins[] = { 0x72, }; +static int x2000_ssi1_dt_e_pins[] = { 0x91, }; +static int x2000_ssi1_dr_c_pins[] = { 0x4a, }; +static int x2000_ssi1_dr_d_pins[] = { 0x73, }; +static int x2000_ssi1_dr_e_pins[] = { 0x92, }; +static int x2000_ssi1_clk_c_pins[] = { 0x4c, }; +static int x2000_ssi1_clk_d_pins[] = { 0x71, }; +static int x2000_ssi1_clk_e_pins[] = { 0x90, }; +static int x2000_ssi1_ce0_c_pins[] = { 0x49, }; +static int x2000_ssi1_ce0_d_pins[] = { 0x76, }; +static int x2000_ssi1_ce0_e_pins[] = { 0x95, }; +static int x2000_mmc0_1bit_pins[] = { 0x71, 0x72, 0x73, }; +static int x2000_mmc0_4bit_pins[] = { 0x74, 0x75, 0x75, }; +static int x2000_mmc0_8bit_pins[] = { 0x77, 0x78, 0x79, 0x7a, }; +static int x2000_mmc1_1bit_pins[] = { 0x68, 0x69, 0x6a, }; +static int x2000_mmc1_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; +static int x2000_mmc2_1bit_pins[] = { 0x80, 0x81, 0x82, }; +static int x2000_mmc2_4bit_pins[] = { 0x83, 0x84, 0x85, }; +static int x2000_emc_8bit_data_pins[] = { + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, +}; +static int x2000_emc_16bit_data_pins[] = { + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, +}; +static int x2000_emc_addr_pins[] = { + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x28, 0x29, 0x2a, 0x2b, 0x2c, +}; +static int x2000_emc_rd_we_pins[] = { 0x2d, 0x2e, }; +static int x2000_emc_wait_pins[] = { 0x2f, }; +static int x2000_emc_cs1_pins[] = { 0x57, }; +static int x2000_emc_cs2_pins[] = { 0x58, }; +static int x2000_i2c0_pins[] = { 0x4e, 0x4d, }; +static int x2000_i2c1_c_pins[] = { 0x58, 0x57, }; +static int x2000_i2c1_d_pins[] = { 0x6c, 0x6b, }; +static int x2000_i2c2_b_pins[] = { 0x37, 0x36, }; +static int x2000_i2c2_d_pins[] = { 0x75, 0x74, }; +static int x2000_i2c2_e_pins[] = { 0x94, 0x93, }; +static int x2000_i2c3_a_pins[] = { 0x11, 0x10, }; +static int x2000_i2c3_d_pins[] = { 0x7f, 0x7e, }; +static int x2000_i2c4_c_pins[] = { 0x5a, 0x59, }; +static int x2000_i2c4_d_pins[] = { 0x61, 0x60, }; +static int x2000_i2c5_c_pins[] = { 0x5c, 0x5b, }; +static int x2000_i2c5_d_pins[] = { 0x65, 0x64, }; +static int x2000_i2s1_data_tx_pins[] = { 0x47, }; +static int x2000_i2s1_data_rx_pins[] = { 0x44, }; +static int x2000_i2s1_clk_tx_pins[] = { 0x45, 0x46, }; +static int x2000_i2s1_clk_rx_pins[] = { 0x42, 0x43, }; +static int x2000_i2s1_sysclk_tx_pins[] = { 0x48, }; +static int x2000_i2s1_sysclk_rx_pins[] = { 0x41, }; +static int x2000_i2s2_data_rx0_pins[] = { 0x0a, }; +static int x2000_i2s2_data_rx1_pins[] = { 0x0b, }; +static int x2000_i2s2_data_rx2_pins[] = { 0x0c, }; +static int x2000_i2s2_data_rx3_pins[] = { 0x0d, }; +static int x2000_i2s2_clk_rx_pins[] = { 0x11, 0x09, }; +static int x2000_i2s2_sysclk_rx_pins[] = { 0x07, }; +static int x2000_i2s3_data_tx0_pins[] = { 0x03, }; +static int x2000_i2s3_data_tx1_pins[] = { 0x04, }; +static int x2000_i2s3_data_tx2_pins[] = { 0x05, }; +static int x2000_i2s3_data_tx3_pins[] = { 0x06, }; +static int x2000_i2s3_clk_tx_pins[] = { 0x10, 0x02, }; +static int x2000_i2s3_sysclk_tx_pins[] = { 0x00, }; +static int x2000_dmic0_pins[] = { 0x54, 0x55, }; +static int x2000_dmic1_pins[] = { 0x56, }; +static int x2000_dmic2_pins[] = { 0x57, }; +static int x2000_dmic3_pins[] = { 0x58, }; +static int x2000_cim_8bit_pins[] = { + 0x0e, 0x0c, 0x0d, 0x4f, + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, +}; +static int x2000_cim_12bit_pins[] = { 0x08, 0x09, 0x0a, 0x0b, }; +static int x2000_lcd_tft_8bit_pins[] = { + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x38, 0x3a, 0x39, 0x3b, +}; +static int x2000_lcd_tft_16bit_pins[] = { + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, +}; +static int x2000_lcd_tft_18bit_pins[] = { + 0x30, 0x31, +}; +static int x2000_lcd_tft_24bit_pins[] = { + 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, +}; +static int x2000_lcd_slcd_8bit_pins[] = { + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x3a, 0x38, 0x3b, 0x30, 0x39, +}; +static int x2000_pwm_pwm0_c_pins[] = { 0x40, }; +static int x2000_pwm_pwm0_d_pins[] = { 0x7e, }; +static int x2000_pwm_pwm1_c_pins[] = { 0x41, }; +static int x2000_pwm_pwm1_d_pins[] = { 0x7f, }; +static int x2000_pwm_pwm2_c_pins[] = { 0x42, }; +static int x2000_pwm_pwm2_e_pins[] = { 0x80, }; +static int x2000_pwm_pwm3_c_pins[] = { 0x43, }; +static int x2000_pwm_pwm3_e_pins[] = { 0x81, }; +static int x2000_pwm_pwm4_c_pins[] = { 0x44, }; +static int x2000_pwm_pwm4_e_pins[] = { 0x82, }; +static int x2000_pwm_pwm5_c_pins[] = { 0x45, }; +static int x2000_pwm_pwm5_e_pins[] = { 0x83, }; +static int x2000_pwm_pwm6_c_pins[] = { 0x46, }; +static int x2000_pwm_pwm6_e_pins[] = { 0x84, }; +static int x2000_pwm_pwm7_c_pins[] = { 0x47, }; +static int x2000_pwm_pwm7_e_pins[] = { 0x85, }; +static int x2000_pwm_pwm8_pins[] = { 0x48, }; +static int x2000_pwm_pwm9_pins[] = { 0x49, }; +static int x2000_pwm_pwm10_pins[] = { 0x4a, }; +static int x2000_pwm_pwm11_pins[] = { 0x4b, }; +static int x2000_pwm_pwm12_pins[] = { 0x4c, }; +static int x2000_pwm_pwm13_pins[] = { 0x4d, }; +static int x2000_pwm_pwm14_pins[] = { 0x4e, }; +static int x2000_pwm_pwm15_pins[] = { 0x4f, }; +static int x2000_mac0_rmii_pins[] = { + 0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4e, 0x41, +}; +static int x2000_mac0_rgmii_pins[] = { + 0x4b, 0x49, 0x48, 0x47, 0x46, 0x4a, 0x45, 0x44, 0x43, 0x42, + 0x4c, 0x4d, 0x4f, 0x4e, 0x41, +}; +static int x2000_mac1_rmii_pins[] = { + 0x32, 0x2d, 0x2c, 0x31, 0x29, 0x28, 0x33, 0x34, 0x35, 0x37, +}; +static int x2000_mac1_rgmii_pins[] = { + 0x32, 0x2f, 0x2e, 0x2d, 0x2c, 0x31, 0x2b, 0x2a, 0x29, 0x28, + 0x33, 0x34, 0x36, 0x35, 0x37, +}; +static int x2000_otg_pins[] = { 0x96, }; + +static u8 x2000_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, }; + +static const struct group_desc x2000_groups[] = { + INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2), + INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2), + INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1), + INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1), + INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0), + INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0), + INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1), + INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0), + INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1), + INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1), + INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3), + INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1), + INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3), + INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1), + INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3), + INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1), + INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3), + INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1), + INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3), + INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3), + INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3), + INGENIC_PIN_GROUP("sfc0-d", x2000_sfc0_d, 1), + INGENIC_PIN_GROUP("sfc0-e", x2000_sfc0_e, 0), + INGENIC_PIN_GROUP("sfc1", x2000_sfc1, 1), + INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1), + INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1), + INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1), + INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1), + INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1), + INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1), + INGENIC_PIN_GROUP("ssi0-ce0-b", x2000_ssi0_ce0_b, 1), + INGENIC_PIN_GROUP("ssi0-ce0-d", x2000_ssi0_ce0_d, 1), + INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2), + INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2), + INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1), + INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2), + INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2), + INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1), + INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2), + INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2), + INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1), + INGENIC_PIN_GROUP("ssi1-ce0-c", x2000_ssi1_ce0_c, 2), + INGENIC_PIN_GROUP("ssi1-ce0-d", x2000_ssi1_ce0_d, 2), + INGENIC_PIN_GROUP("ssi1-ce0-e", x2000_ssi1_ce0_e, 1), + INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0), + INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0), + INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0), + INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0), + INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0), + INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0), + INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0), + INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0), + INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0), + INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0), + INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0), + INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0), + INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3), + INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3), + INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3), + INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2), + INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1), + INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2), + INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2), + INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1), + INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0), + INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1), + INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1), + INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2), + INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1), + INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1), + INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2), + INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2), + INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2), + INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2), + INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2), + INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2), + INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2), + INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2), + INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2), + INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2), + INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2), + INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2), + INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2), + INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2), + INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2), + INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2), + INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2), + INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2), + INGENIC_PIN_GROUP("dmic0", x2000_dmic0, 0), + INGENIC_PIN_GROUP("dmic1", x2000_dmic1, 0), + INGENIC_PIN_GROUP("dmic2", x2000_dmic2, 0), + INGENIC_PIN_GROUP("dmic3", x2000_dmic3, 0), + INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit, + x2000_cim_8bit_funcs), + INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0), + INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1), + INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1), + INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1), + INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1), + INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2), + INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2), + INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0), + INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2), + INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0), + INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2), + INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0), + INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1), + INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0), + INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1), + INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0), + INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1), + INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0), + INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1), + INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0), + INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1), + INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0), + INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1), + INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0), + INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0), + INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0), + INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0), + INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0), + INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0), + INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0), + INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0), + INGENIC_PIN_GROUP("mac0-rmii", x2000_mac0_rmii, 1), + INGENIC_PIN_GROUP("mac0-rgmii", x2000_mac0_rgmii, 1), + INGENIC_PIN_GROUP("mac1-rmii", x2000_mac1_rmii, 3), + INGENIC_PIN_GROUP("mac1-rgmii", x2000_mac1_rgmii, 3), + INGENIC_PIN_GROUP("otg-vbus", x2000_otg, 0), +}; + +static const char *x2000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; +static const char *x2000_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; +static const char *x2000_uart2_groups[] = { "uart2-data", }; +static const char *x2000_uart3_groups[] = { + "uart3-data-c", "uart3-data-d", "uart3-hwflow-c", "uart3-hwflow-d", +}; +static const char *x2000_uart4_groups[] = { + "uart4-data-a", "uart4-data-c", "uart4-hwflow-a", "uart4-hwflow-c", +}; +static const char *x2000_uart5_groups[] = { "uart5-data-a", "uart5-data-c", }; +static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", }; +static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", }; +static const char *x2000_uart8_groups[] = { "uart8-data", }; +static const char *x2000_uart9_groups[] = { "uart9-data", }; +static const char *x2000_sfc_groups[] = { "sfc0-d", "sfc0-e", "sfc1", }; +static const char *x2000_ssi0_groups[] = { + "ssi0-dt-b", "ssi0-dt-d", + "ssi0-dr-b", "ssi0-dr-d", + "ssi0-clk-b", "ssi0-clk-d", + "ssi0-ce0-b", "ssi0-ce0-d", +}; +static const char *x2000_ssi1_groups[] = { + "ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e", + "ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e", + "ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e", + "ssi1-ce0-c", "ssi1-ce0-d", "ssi1-ce0-e", +}; +static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", }; +static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; +static const char *x2000_mmc2_groups[] = { "mmc2-1bit", "mmc2-4bit", }; +static const char *x2000_emc_groups[] = { + "emc-8bit-data", "emc-16bit-data", + "emc-addr", "emc-rd-we", "emc-wait", +}; +static const char *x2000_cs1_groups[] = { "emc-cs1", }; +static const char *x2000_cs2_groups[] = { "emc-cs2", }; +static const char *x2000_i2c0_groups[] = { "i2c0-data", }; +static const char *x2000_i2c1_groups[] = { "i2c1-data-c", "i2c1-data-d", }; +static const char *x2000_i2c2_groups[] = { "i2c2-data-b", "i2c2-data-d", }; +static const char *x2000_i2c3_groups[] = { "i2c3-data-a", "i2c3-data-d", }; +static const char *x2000_i2c4_groups[] = { "i2c4-data-c", "i2c4-data-d", }; +static const char *x2000_i2c5_groups[] = { "i2c5-data-c", "i2c5-data-d", }; +static const char *x2000_i2s1_groups[] = { + "i2s1-data-tx", "i2s1-data-rx", + "i2s1-clk-tx", "i2s1-clk-rx", + "i2s1-sysclk-tx", "i2s1-sysclk-rx", +}; +static const char *x2000_i2s2_groups[] = { + "i2s2-data-rx0", "i2s2-data-rx1", "i2s2-data-rx2", "i2s2-data-rx3", + "i2s2-clk-rx", "i2s2-sysclk-rx", +}; +static const char *x2000_i2s3_groups[] = { + "i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3", + "i2s3-clk-tx", "i2s3-sysclk-tx", +}; +static const char *x2000_dmic_groups[] = { "dmic0", "dmic1", "dmic2", "dmic3", }; +static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; +static const char *x2000_lcd_groups[] = { + "lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit", + "lcd-slcd-8bit", "lcd-slcd-16bit", +}; +static const char *x2000_pwm0_groups[] = { "pwm0-c", "pwm0-d", }; +static const char *x2000_pwm1_groups[] = { "pwm1-c", "pwm1-d", }; +static const char *x2000_pwm2_groups[] = { "pwm2-c", "pwm2-e", }; +static const char *x2000_pwm3_groups[] = { "pwm3-c", "pwm3-r", }; +static const char *x2000_pwm4_groups[] = { "pwm4-c", "pwm4-e", }; +static const char *x2000_pwm5_groups[] = { "pwm5-c", "pwm5-e", }; +static const char *x2000_pwm6_groups[] = { "pwm6-c", "pwm6-e", }; +static const char *x2000_pwm7_groups[] = { "pwm7-c", "pwm7-e", }; +static const char *x2000_pwm8_groups[] = { "pwm8", }; +static const char *x2000_pwm9_groups[] = { "pwm9", }; +static const char *x2000_pwm10_groups[] = { "pwm10", }; +static const char *x2000_pwm11_groups[] = { "pwm11", }; +static const char *x2000_pwm12_groups[] = { "pwm12", }; +static const char *x2000_pwm13_groups[] = { "pwm13", }; +static const char *x2000_pwm14_groups[] = { "pwm14", }; +static const char *x2000_pwm15_groups[] = { "pwm15", }; +static const char *x2000_mac0_groups[] = { "mac0-rmii", "mac0-rgmii", }; +static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", }; +static const char *x2000_otg_groups[] = { "otg-vbus", }; + +static const struct function_desc x2000_functions[] = { + { "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), }, + { "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), }, + { "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), }, + { "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), }, + { "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), }, + { "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), }, + { "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), }, + { "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), }, + { "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), }, + { "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), }, + { "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), }, + { "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), }, + { "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), }, + { "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), }, + { "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), }, + { "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), }, + { "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), }, + { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), }, + { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), }, + { "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), }, + { "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), }, + { "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), }, + { "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), }, + { "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), }, + { "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), }, + { "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), }, + { "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), }, + { "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), }, + { "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), }, + { "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), }, + { "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), }, + { "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), }, + { "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), }, + { "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), }, + { "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), }, + { "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), }, + { "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), }, + { "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), }, + { "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), }, + { "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), }, + { "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), }, + { "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), }, + { "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), }, + { "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), }, + { "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), }, + { "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), }, + { "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), }, + { "mac0", x2000_mac0_groups, ARRAY_SIZE(x2000_mac0_groups), }, + { "mac1", x2000_mac1_groups, ARRAY_SIZE(x2000_mac1_groups), }, + { "otg", x2000_otg_groups, ARRAY_SIZE(x2000_otg_groups), }, +}; + +static const struct ingenic_chip_info x2000_chip_info = { + .num_chips = 5, + .reg_offset = 0x100, + .version = ID_X2000, + .groups = x2000_groups, + .num_groups = ARRAY_SIZE(x2000_groups), + .functions = x2000_functions, + .num_functions = ARRAY_SIZE(x2000_functions), + .pull_ups = x2000_pull_ups, + .pull_downs = x2000_pull_downs, +}; + static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) { unsigned int val; @@ -1668,6 +2813,12 @@ static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc, u8 reg, u8 offset, bool set) { + if (jzgc->jzpc->info->version == ID_JZ4730) { + regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, + BIT(offset), set ? BIT(offset) : 0); + return; + } + if (set) reg = REG_SET(reg); else @@ -1695,6 +2846,20 @@ static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc) jzgc->gc.base / PINS_PER_GPIO_CHIP); } +static void jz4730_gpio_set_bits(struct ingenic_gpio_chip *jzgc, + u8 reg_upper, u8 reg_lower, u8 offset, u8 value) +{ + /* + * JZ4730 function and IRQ registers support two-bits-per-pin + * definitions, split into two groups of 16. + */ + u8 reg = offset < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper; + unsigned int idx = offset % JZ4730_PINS_PER_PAIRED_REG; + unsigned int mask = GENMASK(1, 0) << idx * 2; + + regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2)); +} + static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, u8 offset) { @@ -1708,43 +2873,60 @@ static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc, { if (jzgc->jzpc->info->version >= ID_JZ4770) ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value); - else + else if (jzgc->jzpc->info->version >= ID_JZ4740) ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); + else + ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_DATA, offset, !!value); } static void irq_set_type(struct ingenic_gpio_chip *jzgc, u8 offset, unsigned int type) { u8 reg1, reg2; - bool val1, val2; + bool val1, val2, val3; switch (type) { + case IRQ_TYPE_EDGE_BOTH: + val1 = val2 = false; + val3 = true; + break; case IRQ_TYPE_EDGE_RISING: val1 = val2 = true; + val3 = false; break; case IRQ_TYPE_EDGE_FALLING: - val1 = false; + val1 = val3 = false; val2 = true; break; case IRQ_TYPE_LEVEL_HIGH: val1 = true; - val2 = false; + val2 = val3 = false; break; case IRQ_TYPE_LEVEL_LOW: default: - val1 = val2 = false; + val1 = val2 = val3 = false; break; } if (jzgc->jzpc->info->version >= ID_JZ4770) { reg1 = JZ4770_GPIO_PAT1; reg2 = JZ4770_GPIO_PAT0; - } else { + } else if (jzgc->jzpc->info->version >= ID_JZ4740) { reg1 = JZ4740_GPIO_TRIG; reg2 = JZ4740_GPIO_DIR; + } else { + ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPDIR, offset, false); + jz4730_gpio_set_bits(jzgc, JZ4730_GPIO_GPIDUR, + JZ4730_GPIO_GPIDLR, offset, (val2 << 1) | val1); + return; } - if (jzgc->jzpc->info->version >= ID_X1000) { + if (jzgc->jzpc->info->version >= ID_X2000) { + ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); + ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); + ingenic_gpio_shadow_set_bit_load(jzgc); + ingenic_gpio_set_bit(jzgc, X2000_GPIO_EDG, offset, val3); + } else if (jzgc->jzpc->info->version >= ID_X1000) { ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); ingenic_gpio_shadow_set_bit_load(jzgc); @@ -1758,16 +2940,24 @@ static void ingenic_gpio_irq_mask(struct irq_data *irqd) { struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); + int irq = irqd->hwirq; - ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true); + if (jzgc->jzpc->info->version >= ID_JZ4740) + ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, true); + else + ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, true); } static void ingenic_gpio_irq_unmask(struct irq_data *irqd) { struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); + int irq = irqd->hwirq; - ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false); + if (jzgc->jzpc->info->version >= ID_JZ4740) + ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, false); + else + ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, false); } static void ingenic_gpio_irq_enable(struct irq_data *irqd) @@ -1778,8 +2968,10 @@ static void ingenic_gpio_irq_enable(struct irq_data *irqd) if (jzgc->jzpc->info->version >= ID_JZ4770) ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true); - else + else if (jzgc->jzpc->info->version >= ID_JZ4740) ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); + else + ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, true); ingenic_gpio_irq_unmask(irqd); } @@ -1794,8 +2986,10 @@ static void ingenic_gpio_irq_disable(struct irq_data *irqd) if (jzgc->jzpc->info->version >= ID_JZ4770) ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false); - else + else if (jzgc->jzpc->info->version >= ID_JZ4740) ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); + else + ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, false); } static void ingenic_gpio_irq_ack(struct irq_data *irqd) @@ -1805,7 +2999,8 @@ static void ingenic_gpio_irq_ack(struct irq_data *irqd) int irq = irqd->hwirq; bool high; - if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) { + if ((irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) && + (jzgc->jzpc->info->version < ID_X2000)) { /* * Switch to an interrupt for the opposite edge to the one that * triggered the interrupt being ACKed. @@ -1819,8 +3014,10 @@ static void ingenic_gpio_irq_ack(struct irq_data *irqd) if (jzgc->jzpc->info->version >= ID_JZ4770) ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false); - else + else if (jzgc->jzpc->info->version >= ID_JZ4740) ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); + else + ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPFR, irq, false); } static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) @@ -1842,7 +3039,7 @@ static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) irq_set_handler_locked(irqd, handle_bad_irq); } - if (type == IRQ_TYPE_EDGE_BOTH) { + if ((type == IRQ_TYPE_EDGE_BOTH) && (jzgc->jzpc->info->version < ID_X2000)) { /* * The hardware does not support interrupts on both edges. The * best we can do is to set up a single-edge interrupt and then @@ -1876,8 +3073,10 @@ static void ingenic_gpio_irq_handler(struct irq_desc *desc) if (jzgc->jzpc->info->version >= ID_JZ4770) flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG); - else + else if (jzgc->jzpc->info->version >= ID_JZ4740) flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG); + else + flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR); for_each_set_bit(i, &flag, 32) generic_handle_irq(irq_linear_revmap(gc->irq.domain, i)); @@ -1913,13 +3112,26 @@ static int ingenic_gpio_direction_output(struct gpio_chip *gc, } static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc, - unsigned int pin, u8 reg, bool set) + unsigned int pin, unsigned int reg, bool set) { unsigned int idx = pin % PINS_PER_GPIO_CHIP; unsigned int offt = pin / PINS_PER_GPIO_CHIP; - regmap_write(jzpc->map, offt * jzpc->info->reg_offset + - (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); + if (set) { + if (jzpc->info->version >= ID_JZ4740) + regmap_write(jzpc->map, offt * jzpc->info->reg_offset + + REG_SET(reg), BIT(idx)); + else + regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset + + reg, BIT(idx)); + } else { + if (jzpc->info->version >= ID_JZ4740) + regmap_write(jzpc->map, offt * jzpc->info->reg_offset + + REG_CLEAR(reg), BIT(idx)); + else + regmap_clear_bits(jzpc->map, offt * jzpc->info->reg_offset + + reg, BIT(idx)); + } } static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, @@ -1938,8 +3150,24 @@ static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc, pin / PINS_PER_GPIO_CHIP); } +static inline void jz4730_config_pin_function(struct ingenic_pinctrl *jzpc, + unsigned int pin, u8 reg_upper, u8 reg_lower, u8 value) +{ + /* + * JZ4730 function and IRQ registers support two-bits-per-pin + * definitions, split into two groups of 16. + */ + unsigned int idx = pin % JZ4730_PINS_PER_PAIRED_REG; + unsigned int mask = GENMASK(1, 0) << idx * 2; + unsigned int offt = pin / PINS_PER_GPIO_CHIP; + u8 reg = (pin % PINS_PER_GPIO_CHIP) < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper; + + regmap_update_bits(jzpc->map, offt * jzpc->info->reg_offset + reg, + mask, value << (idx * 2)); +} + static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, - unsigned int pin, u8 reg) + unsigned int pin, unsigned int reg) { unsigned int idx = pin % PINS_PER_GPIO_CHIP; unsigned int offt = pin / PINS_PER_GPIO_CHIP; @@ -1961,6 +3189,10 @@ static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1)) return GPIO_LINE_DIRECTION_IN; return GPIO_LINE_DIRECTION_OUT; + } else if (jzpc->info->version == ID_JZ4730) { + if (!ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPDIR)) + return GPIO_LINE_DIRECTION_IN; + return GPIO_LINE_DIRECTION_OUT; } if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT)) @@ -2019,10 +3251,13 @@ static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, ingenic_config_pin(jzpc, pin, GPIO_MSK, false); ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2); ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1); - } else { + } else if (jzpc->info->version >= ID_JZ4740) { ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true); ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2); ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1); + } else { + ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false); + jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, func); } return 0; @@ -2083,10 +3318,14 @@ static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); ingenic_config_pin(jzpc, pin, GPIO_MSK, true); ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input); - } else { + } else if (jzpc->info->version >= ID_JZ4740) { ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false); ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input); ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false); + } else { + ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false); + ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPDIR, !input); + jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, 0); } return 0; @@ -2107,44 +3346,120 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, enum pin_config_param param = pinconf_to_config_param(*config); unsigned int idx = pin % PINS_PER_GPIO_CHIP; unsigned int offt = pin / PINS_PER_GPIO_CHIP; - bool pull; + unsigned int arg = 1; + unsigned int bias, reg; + bool pull, pullup, pulldown; + + if (jzpc->info->version >= ID_X2000) { + pullup = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) && + !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) && + (jzpc->info->pull_ups[offt] & BIT(idx)); + pulldown = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) && + !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) && + (jzpc->info->pull_downs[offt] & BIT(idx)); + + } else if (jzpc->info->version >= ID_X1830) { + unsigned int half = PINS_PER_GPIO_CHIP / 2; + unsigned int idxh = (pin % half) * 2; - if (jzpc->info->version >= ID_JZ4770) - pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN); - else - pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); + if (idx < half) + regmap_read(jzpc->map, offt * jzpc->info->reg_offset + + X1830_GPIO_PEL, &bias); + else + regmap_read(jzpc->map, offt * jzpc->info->reg_offset + + X1830_GPIO_PEH, &bias); + + bias = (bias >> idxh) & (GPIO_PULL_UP | GPIO_PULL_DOWN); + + pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] & BIT(idx)); + pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx)); + + } else { + if (jzpc->info->version >= ID_JZ4770) + pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN); + else if (jzpc->info->version >= ID_JZ4740) + pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); + else + pull = ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPPUR); + + pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx)); + pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx)); + } switch (param) { case PIN_CONFIG_BIAS_DISABLE: - if (pull) + if (pullup || pulldown) return -EINVAL; + break; case PIN_CONFIG_BIAS_PULL_UP: - if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx))) + if (!pullup) return -EINVAL; + break; case PIN_CONFIG_BIAS_PULL_DOWN: - if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx))) + if (!pulldown) return -EINVAL; + + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (jzpc->info->version >= ID_X2000) + reg = X2000_GPIO_SMT; + else if (jzpc->info->version >= ID_X1830) + reg = X1830_GPIO_SMT; + else + return -EINVAL; + + arg = !!ingenic_get_pin_config(jzpc, pin, reg); + break; + + case PIN_CONFIG_SLEW_RATE: + if (jzpc->info->version >= ID_X2000) + reg = X2000_GPIO_SR; + else if (jzpc->info->version >= ID_X1830) + reg = X1830_GPIO_SR; + else + return -EINVAL; + + arg = !!ingenic_get_pin_config(jzpc, pin, reg); break; default: return -ENOTSUPP; } - *config = pinconf_to_config_packed(param, 1); + *config = pinconf_to_config_packed(param, arg); return 0; } static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, unsigned int pin, unsigned int bias) { - if (jzpc->info->version >= ID_X1830) { + if (jzpc->info->version >= ID_X2000) { + switch (bias) { + case PIN_CONFIG_BIAS_PULL_UP: + ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false); + ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, true); + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false); + ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, true); + break; + + case PIN_CONFIG_BIAS_DISABLE: + default: + ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false); + ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false); + } + + } else if (jzpc->info->version >= ID_X1830) { unsigned int idx = pin % PINS_PER_GPIO_CHIP; unsigned int half = PINS_PER_GPIO_CHIP / 2; - unsigned int idxh = pin % half * 2; + unsigned int idxh = (pin % half) * 2; unsigned int offt = pin / PINS_PER_GPIO_CHIP; if (idx < half) { @@ -2161,18 +3476,40 @@ static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, } else if (jzpc->info->version >= ID_JZ4770) { ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !bias); - } else { + } else if (jzpc->info->version >= ID_JZ4740) { ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias); + } else { + ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPPUR, bias); } } +static void ingenic_set_schmitt_trigger(struct ingenic_pinctrl *jzpc, + unsigned int pin, bool enable) +{ + if (jzpc->info->version >= ID_X2000) + ingenic_config_pin(jzpc, pin, X2000_GPIO_SMT, enable); + else + ingenic_config_pin(jzpc, pin, X1830_GPIO_SMT, enable); +} + static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc, unsigned int pin, bool high) { if (jzpc->info->version >= ID_JZ4770) ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, high); - else + else if (jzpc->info->version >= ID_JZ4740) ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high); + else + ingenic_config_pin(jzpc, pin, JZ4730_GPIO_DATA, high); +} + +static void ingenic_set_slew_rate(struct ingenic_pinctrl *jzpc, + unsigned int pin, unsigned int slew) +{ + if (jzpc->info->version >= ID_X2000) + ingenic_config_pin(jzpc, pin, X2000_GPIO_SR, slew); + else + ingenic_config_pin(jzpc, pin, X1830_GPIO_SR, slew); } static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, @@ -2189,7 +3526,9 @@ static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, case PIN_CONFIG_BIAS_DISABLE: case PIN_CONFIG_BIAS_PULL_UP: case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_SLEW_RATE: continue; default: return -ENOTSUPP; @@ -2222,6 +3561,13 @@ static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN); break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (jzpc->info->version < ID_X1830) + return -EINVAL; + + ingenic_set_schmitt_trigger(jzpc, pin, arg); + break; + case PIN_CONFIG_OUTPUT: ret = pinctrl_gpio_direction_output(pin); if (ret) @@ -2230,6 +3576,13 @@ static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, ingenic_set_output_level(jzpc, pin, arg); break; + case PIN_CONFIG_SLEW_RATE: + if (jzpc->info->version < ID_X1830) + return -EINVAL; + + ingenic_set_slew_rate(jzpc, pin, arg); + break; + default: /* unreachable */ break; @@ -2301,13 +3654,18 @@ static const struct regmap_config ingenic_pinctrl_regmap_config = { }; static const struct of_device_id ingenic_gpio_of_match[] __initconst = { + { .compatible = "ingenic,jz4730-gpio", }, { .compatible = "ingenic,jz4740-gpio", }, { .compatible = "ingenic,jz4725b-gpio", }, + { .compatible = "ingenic,jz4750-gpio", }, + { .compatible = "ingenic,jz4755-gpio", }, { .compatible = "ingenic,jz4760-gpio", }, { .compatible = "ingenic,jz4770-gpio", }, + { .compatible = "ingenic,jz4775-gpio", }, { .compatible = "ingenic,jz4780-gpio", }, { .compatible = "ingenic,x1000-gpio", }, { .compatible = "ingenic,x1830-gpio", }, + { .compatible = "ingenic,x2000-gpio", }, {}, }; @@ -2380,6 +3738,7 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, GFP_KERNEL); if (!girq->parents) return -ENOMEM; + girq->parents[0] = jzgc->irq; girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_level_irq; @@ -2485,8 +3844,10 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) for_each_child_of_node(dev->of_node, node) { if (of_match_node(ingenic_gpio_of_match, node)) { err = ingenic_gpio_probe(jzpc, node); - if (err) + if (err) { + of_node_put(node); return err; + } } } @@ -2495,6 +3856,10 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id ingenic_pinctrl_of_match[] = { { + .compatible = "ingenic,jz4730-pinctrl", + .data = IF_ENABLED(CONFIG_MACH_JZ4730, &jz4730_chip_info) + }, + { .compatible = "ingenic,jz4740-pinctrl", .data = IF_ENABLED(CONFIG_MACH_JZ4740, &jz4740_chip_info) }, @@ -2503,6 +3868,14 @@ static const struct of_device_id ingenic_pinctrl_of_match[] = { .data = IF_ENABLED(CONFIG_MACH_JZ4725B, &jz4725b_chip_info) }, { + .compatible = "ingenic,jz4750-pinctrl", + .data = IF_ENABLED(CONFIG_MACH_JZ4750, &jz4750_chip_info) + }, + { + .compatible = "ingenic,jz4755-pinctrl", + .data = IF_ENABLED(CONFIG_MACH_JZ4755, &jz4755_chip_info) + }, + { .compatible = "ingenic,jz4760-pinctrl", .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info) }, @@ -2515,6 +3888,10 @@ static const struct of_device_id ingenic_pinctrl_of_match[] = { .data = IF_ENABLED(CONFIG_MACH_JZ4770, &jz4770_chip_info) }, { + .compatible = "ingenic,jz4775-pinctrl", + .data = IF_ENABLED(CONFIG_MACH_JZ4775, &jz4775_chip_info) + }, + { .compatible = "ingenic,jz4780-pinctrl", .data = IF_ENABLED(CONFIG_MACH_JZ4780, &jz4780_chip_info) }, @@ -2534,6 +3911,14 @@ static const struct of_device_id ingenic_pinctrl_of_match[] = { .compatible = "ingenic,x1830-pinctrl", .data = IF_ENABLED(CONFIG_MACH_X1830, &x1830_chip_info) }, + { + .compatible = "ingenic,x2000-pinctrl", + .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info) + }, + { + .compatible = "ingenic,x2000e-pinctrl", + .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info) + }, { /* sentinel */ }, }; diff --git a/drivers/pinctrl/pinctrl-k210.c b/drivers/pinctrl/pinctrl-k210.c index 8a733cf77ba0..f831526d06ff 100644 --- a/drivers/pinctrl/pinctrl-k210.c +++ b/drivers/pinctrl/pinctrl-k210.c @@ -15,7 +15,6 @@ #include <linux/pinctrl/pinmux.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> -#include <linux/io.h> #include <dt-bindings/pinctrl/k210-fpioa.h> diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c index 7b2f885e68bd..ed9bf2c89998 100644 --- a/drivers/pinctrl/pinctrl-lpc18xx.c +++ b/drivers/pinctrl/pinctrl-lpc18xx.c @@ -646,7 +646,7 @@ static const struct pin_config_item lpc18xx_conf_items[ARRAY_SIZE(lpc18xx_params static int lpc18xx_pconf_get_usb1(enum pin_config_param param, int *arg, u32 reg) { switch (param) { - case PIN_CONFIG_LOW_POWER_MODE: + case PIN_CONFIG_MODE_LOW_POWER: if (reg & LPC18XX_SCU_USB1_EPWR) *arg = 0; else @@ -904,7 +904,7 @@ static int lpc18xx_pconf_set_usb1(struct pinctrl_dev *pctldev, u32 param_val, u32 *reg) { switch (param) { - case PIN_CONFIG_LOW_POWER_MODE: + case PIN_CONFIG_MODE_LOW_POWER: if (param_val) *reg &= ~LPC18XX_SCU_USB1_EPWR; else diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 53a0badc6b03..067fc4208de4 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -16,10 +16,12 @@ */ #include <linux/init.h> +#include <linux/module.h> #include <linux/platform_device.h> #include <linux/io.h> #include <linux/bitops.h> #include <linux/gpio/driver.h> +#include <linux/of_device.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/pinctrl/machine.h> @@ -61,8 +63,17 @@ enum rockchip_pinctrl_type { RK3308, RK3368, RK3399, + RK3568, }; + +/** + * Generate a bitmask for setting a value (v) with a write mask bit in hiword + * register 31:16 area. + */ +#define WRITE_MASK_VAL(h, l, v) \ + (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) + /* * Encode variants of iomux registers into a type variable */ @@ -290,6 +301,25 @@ struct rockchip_pin_bank { .pull_type[3] = pull3, \ } +#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ + { \ + .bank_num = ID, \ + .pin = PIN, \ + .func = FUNC, \ + .route_offset = REG, \ + .route_val = VAL, \ + .route_location = FLAG, \ + } + +#define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \ + PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME) + +#define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \ + PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF) + +#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \ + PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU) + /** * struct rockchip_mux_recalced_data: represent a pin iomux data. * @num: bank number. @@ -801,597 +831,203 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, } static struct rockchip_mux_route_data px30_mux_route_data[] = { - { - /* cif-d2m0 */ - .bank_num = 2, - .pin = 0, - .func = 1, - .route_offset = 0x184, - .route_val = BIT(16 + 7), - }, { - /* cif-d2m1 */ - .bank_num = 3, - .pin = 3, - .func = 3, - .route_offset = 0x184, - .route_val = BIT(16 + 7) | BIT(7), - }, { - /* pdm-m0 */ - .bank_num = 3, - .pin = 22, - .func = 2, - .route_offset = 0x184, - .route_val = BIT(16 + 8), - }, { - /* pdm-m1 */ - .bank_num = 2, - .pin = 22, - .func = 1, - .route_offset = 0x184, - .route_val = BIT(16 + 8) | BIT(8), - }, { - /* uart2-rxm0 */ - .bank_num = 1, - .pin = 27, - .func = 2, - .route_offset = 0x184, - .route_val = BIT(16 + 10), - }, { - /* uart2-rxm1 */ - .bank_num = 2, - .pin = 14, - .func = 2, - .route_offset = 0x184, - .route_val = BIT(16 + 10) | BIT(10), - }, { - /* uart3-rxm0 */ - .bank_num = 0, - .pin = 17, - .func = 2, - .route_offset = 0x184, - .route_val = BIT(16 + 9), - }, { - /* uart3-rxm1 */ - .bank_num = 1, - .pin = 15, - .func = 2, - .route_offset = 0x184, - .route_val = BIT(16 + 9) | BIT(9), - }, + RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */ + RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */ + RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */ + RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */ + RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */ + RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */ + RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */ + RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */ }; static struct rockchip_mux_route_data rk3128_mux_route_data[] = { - { - /* spi-0 */ - .bank_num = 1, - .pin = 10, - .func = 1, - .route_offset = 0x144, - .route_val = BIT(16 + 3) | BIT(16 + 4), - }, { - /* spi-1 */ - .bank_num = 1, - .pin = 27, - .func = 3, - .route_offset = 0x144, - .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), - }, { - /* spi-2 */ - .bank_num = 0, - .pin = 13, - .func = 2, - .route_offset = 0x144, - .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), - }, { - /* i2s-0 */ - .bank_num = 1, - .pin = 5, - .func = 1, - .route_offset = 0x144, - .route_val = BIT(16 + 5), - }, { - /* i2s-1 */ - .bank_num = 0, - .pin = 14, - .func = 1, - .route_offset = 0x144, - .route_val = BIT(16 + 5) | BIT(5), - }, { - /* emmc-0 */ - .bank_num = 1, - .pin = 22, - .func = 2, - .route_offset = 0x144, - .route_val = BIT(16 + 6), - }, { - /* emmc-1 */ - .bank_num = 2, - .pin = 4, - .func = 2, - .route_offset = 0x144, - .route_val = BIT(16 + 6) | BIT(6), - }, + RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */ + RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */ + RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */ + RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */ + RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */ + RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */ + RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */ }; static struct rockchip_mux_route_data rk3188_mux_route_data[] = { - { - /* non-iomuxed emmc/flash pins on flash-dqs */ - .bank_num = 0, - .pin = 24, - .func = 1, - .route_location = ROCKCHIP_ROUTE_GRF, - .route_offset = 0xa0, - .route_val = BIT(16 + 11), - }, { - /* non-iomuxed emmc/flash pins on emmc-clk */ - .bank_num = 0, - .pin = 24, - .func = 2, - .route_location = ROCKCHIP_ROUTE_GRF, - .route_offset = 0xa0, - .route_val = BIT(16 + 11) | BIT(11), - }, + RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */ + RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */ }; static struct rockchip_mux_route_data rk3228_mux_route_data[] = { - { - /* pwm0-0 */ - .bank_num = 0, - .pin = 26, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16), - }, { - /* pwm0-1 */ - .bank_num = 3, - .pin = 21, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16) | BIT(0), - }, { - /* pwm1-0 */ - .bank_num = 0, - .pin = 27, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16 + 1), - }, { - /* pwm1-1 */ - .bank_num = 0, - .pin = 30, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 1) | BIT(1), - }, { - /* pwm2-0 */ - .bank_num = 0, - .pin = 28, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16 + 2), - }, { - /* pwm2-1 */ - .bank_num = 1, - .pin = 12, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 2) | BIT(2), - }, { - /* pwm3-0 */ - .bank_num = 3, - .pin = 26, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16 + 3), - }, { - /* pwm3-1 */ - .bank_num = 1, - .pin = 11, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 3) | BIT(3), - }, { - /* sdio-0_d0 */ - .bank_num = 1, - .pin = 1, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16 + 4), - }, { - /* sdio-1_d0 */ - .bank_num = 3, - .pin = 2, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16 + 4) | BIT(4), - }, { - /* spi-0_rx */ - .bank_num = 0, - .pin = 13, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 5), - }, { - /* spi-1_rx */ - .bank_num = 2, - .pin = 0, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 5) | BIT(5), - }, { - /* emmc-0_cmd */ - .bank_num = 1, - .pin = 22, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 7), - }, { - /* emmc-1_cmd */ - .bank_num = 2, - .pin = 4, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 7) | BIT(7), - }, { - /* uart2-0_rx */ - .bank_num = 1, - .pin = 19, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 8), - }, { - /* uart2-1_rx */ - .bank_num = 1, - .pin = 10, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 8) | BIT(8), - }, { - /* uart1-0_rx */ - .bank_num = 1, - .pin = 10, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16 + 11), - }, { - /* uart1-1_rx */ - .bank_num = 3, - .pin = 13, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16 + 11) | BIT(11), - }, + RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */ + RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */ + RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */ + RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */ + RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */ + RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */ + RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */ + RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */ + RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */ + RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */ + RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */ + RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */ + RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */ + RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */ + RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */ + RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */ + RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */ + RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */ }; static struct rockchip_mux_route_data rk3288_mux_route_data[] = { - { - /* edphdmi_cecinoutt1 */ - .bank_num = 7, - .pin = 16, - .func = 2, - .route_offset = 0x264, - .route_val = BIT(16 + 12) | BIT(12), - }, { - /* edphdmi_cecinout */ - .bank_num = 7, - .pin = 23, - .func = 4, - .route_offset = 0x264, - .route_val = BIT(16 + 12), - }, + RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */ + RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */ }; static struct rockchip_mux_route_data rk3308_mux_route_data[] = { - { - /* rtc_clk */ - .bank_num = 0, - .pin = 19, - .func = 1, - .route_offset = 0x314, - .route_val = BIT(16 + 0) | BIT(0), - }, { - /* uart2_rxm0 */ - .bank_num = 1, - .pin = 22, - .func = 2, - .route_offset = 0x314, - .route_val = BIT(16 + 2) | BIT(16 + 3), - }, { - /* uart2_rxm1 */ - .bank_num = 4, - .pin = 26, - .func = 2, - .route_offset = 0x314, - .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), - }, { - /* i2c3_sdam0 */ - .bank_num = 0, - .pin = 15, - .func = 2, - .route_offset = 0x608, - .route_val = BIT(16 + 8) | BIT(16 + 9), - }, { - /* i2c3_sdam1 */ - .bank_num = 3, - .pin = 12, - .func = 2, - .route_offset = 0x608, - .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8), - }, { - /* i2c3_sdam2 */ - .bank_num = 2, - .pin = 0, - .func = 3, - .route_offset = 0x608, - .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9), - }, { - /* i2s-8ch-1-sclktxm0 */ - .bank_num = 1, - .pin = 3, - .func = 2, - .route_offset = 0x308, - .route_val = BIT(16 + 3), - }, { - /* i2s-8ch-1-sclkrxm0 */ - .bank_num = 1, - .pin = 4, - .func = 2, - .route_offset = 0x308, - .route_val = BIT(16 + 3), - }, { - /* i2s-8ch-1-sclktxm1 */ - .bank_num = 1, - .pin = 13, - .func = 2, - .route_offset = 0x308, - .route_val = BIT(16 + 3) | BIT(3), - }, { - /* i2s-8ch-1-sclkrxm1 */ - .bank_num = 1, - .pin = 14, - .func = 2, - .route_offset = 0x308, - .route_val = BIT(16 + 3) | BIT(3), - }, { - /* pdm-clkm0 */ - .bank_num = 1, - .pin = 4, - .func = 3, - .route_offset = 0x308, - .route_val = BIT(16 + 12) | BIT(16 + 13), - }, { - /* pdm-clkm1 */ - .bank_num = 1, - .pin = 14, - .func = 4, - .route_offset = 0x308, - .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), - }, { - /* pdm-clkm2 */ - .bank_num = 2, - .pin = 6, - .func = 2, - .route_offset = 0x308, - .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), - }, { - /* pdm-clkm-m2 */ - .bank_num = 2, - .pin = 4, - .func = 3, - .route_offset = 0x600, - .route_val = BIT(16 + 2) | BIT(2), - }, { - /* spi1_miso */ - .bank_num = 3, - .pin = 10, - .func = 3, - .route_offset = 0x314, - .route_val = BIT(16 + 9), - }, { - /* spi1_miso_m1 */ - .bank_num = 2, - .pin = 4, - .func = 2, - .route_offset = 0x314, - .route_val = BIT(16 + 9) | BIT(9), - }, { - /* owire_m0 */ - .bank_num = 0, - .pin = 11, - .func = 3, - .route_offset = 0x314, - .route_val = BIT(16 + 10) | BIT(16 + 11), - }, { - /* owire_m1 */ - .bank_num = 1, - .pin = 22, - .func = 7, - .route_offset = 0x314, - .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), - }, { - /* owire_m2 */ - .bank_num = 2, - .pin = 2, - .func = 5, - .route_offset = 0x314, - .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), - }, { - /* can_rxd_m0 */ - .bank_num = 0, - .pin = 11, - .func = 2, - .route_offset = 0x314, - .route_val = BIT(16 + 12) | BIT(16 + 13), - }, { - /* can_rxd_m1 */ - .bank_num = 1, - .pin = 22, - .func = 5, - .route_offset = 0x314, - .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), - }, { - /* can_rxd_m2 */ - .bank_num = 2, - .pin = 2, - .func = 4, - .route_offset = 0x314, - .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), - }, { - /* mac_rxd0_m0 */ - .bank_num = 1, - .pin = 20, - .func = 3, - .route_offset = 0x314, - .route_val = BIT(16 + 14), - }, { - /* mac_rxd0_m1 */ - .bank_num = 4, - .pin = 2, - .func = 2, - .route_offset = 0x314, - .route_val = BIT(16 + 14) | BIT(14), - }, { - /* uart3_rx */ - .bank_num = 3, - .pin = 12, - .func = 4, - .route_offset = 0x314, - .route_val = BIT(16 + 15), - }, { - /* uart3_rx_m1 */ - .bank_num = 0, - .pin = 17, - .func = 3, - .route_offset = 0x314, - .route_val = BIT(16 + 15) | BIT(15), - }, + RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */ + RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */ + RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */ + RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */ + RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */ + RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */ + RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */ + RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */ + RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */ + RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */ + RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */ + RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */ + RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */ + RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ + RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */ + RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */ + RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */ + RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */ + RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */ + RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */ + RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */ + RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */ + RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */ + RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */ + RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */ + RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */ }; static struct rockchip_mux_route_data rk3328_mux_route_data[] = { - { - /* uart2dbg_rxm0 */ - .bank_num = 1, - .pin = 1, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16) | BIT(16 + 1), - }, { - /* uart2dbg_rxm1 */ - .bank_num = 2, - .pin = 1, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16) | BIT(16 + 1) | BIT(0), - }, { - /* gmac-m1_rxd0 */ - .bank_num = 1, - .pin = 11, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 2) | BIT(2), - }, { - /* gmac-m1-optimized_rxd3 */ - .bank_num = 1, - .pin = 14, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 10) | BIT(10), - }, { - /* pdm_sdi0m0 */ - .bank_num = 2, - .pin = 19, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 3), - }, { - /* pdm_sdi0m1 */ - .bank_num = 1, - .pin = 23, - .func = 3, - .route_offset = 0x50, - .route_val = BIT(16 + 3) | BIT(3), - }, { - /* spi_rxdm2 */ - .bank_num = 3, - .pin = 2, - .func = 4, - .route_offset = 0x50, - .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), - }, { - /* i2s2_sdim0 */ - .bank_num = 1, - .pin = 24, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16 + 6), - }, { - /* i2s2_sdim1 */ - .bank_num = 3, - .pin = 2, - .func = 6, - .route_offset = 0x50, - .route_val = BIT(16 + 6) | BIT(6), - }, { - /* card_iom1 */ - .bank_num = 2, - .pin = 22, - .func = 3, - .route_offset = 0x50, - .route_val = BIT(16 + 7) | BIT(7), - }, { - /* tsp_d5m1 */ - .bank_num = 2, - .pin = 16, - .func = 3, - .route_offset = 0x50, - .route_val = BIT(16 + 8) | BIT(8), - }, { - /* cif_data5m1 */ - .bank_num = 2, - .pin = 16, - .func = 4, - .route_offset = 0x50, - .route_val = BIT(16 + 9) | BIT(9), - }, + RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */ + RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */ + RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */ + RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */ + RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */ + RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */ + RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */ + RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */ + RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */ + RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */ + RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */ + RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */ }; static struct rockchip_mux_route_data rk3399_mux_route_data[] = { - { - /* uart2dbga_rx */ - .bank_num = 4, - .pin = 8, - .func = 2, - .route_offset = 0xe21c, - .route_val = BIT(16 + 10) | BIT(16 + 11), - }, { - /* uart2dbgb_rx */ - .bank_num = 4, - .pin = 16, - .func = 2, - .route_offset = 0xe21c, - .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), - }, { - /* uart2dbgc_rx */ - .bank_num = 4, - .pin = 19, - .func = 1, - .route_offset = 0xe21c, - .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), - }, { - /* pcie_clkreqn */ - .bank_num = 2, - .pin = 26, - .func = 2, - .route_offset = 0xe21c, - .route_val = BIT(16 + 14), - }, { - /* pcie_clkreqnb */ - .bank_num = 4, - .pin = 24, - .func = 1, - .route_offset = 0xe21c, - .route_val = BIT(16 + 14) | BIT(14), - }, + RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */ + RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */ + RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */ + RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */ + RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */ +}; + +static struct rockchip_mux_route_data rk3568_mux_route_data[] = { + RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */ + RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */ + RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */ + RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */ + RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */ + RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */ + RK_MUXROUTE_PMU(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */ + RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */ + RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */ + RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */ + RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */ + RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */ + RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */ + RK_MUXROUTE_PMU(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */ + RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */ + RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */ + RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */ + RK_MUXROUTE_PMU(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */ + RK_MUXROUTE_PMU(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */ + RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */ + RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */ + RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */ + RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */ + RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */ + RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */ + RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */ + RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */ + RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */ + RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */ + RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */ + RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */ + RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */ + RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */ + RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */ + RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */ + RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */ + RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */ + RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */ + RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */ + RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */ + RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */ + RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */ + RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */ + RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */ + RK_MUXROUTE_PMU(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */ + RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */ + RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */ + RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */ + RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */ + RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */ + RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */ + RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */ + RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */ + RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */ + RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */ + RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */ + RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */ + RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */ + RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */ + RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */ + RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */ + RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */ + RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */ + RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */ + RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */ + RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */ + RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */ + RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */ + RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */ + RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */ + RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */ + RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */ + RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */ + RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */ + RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */ + RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */ + RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */ + RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */ + RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */ + RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ + RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ + RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ + RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ + RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */ + RK_MUXROUTE_PMU(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */ + RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */ + RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */ + RK_MUXROUTE_PMU(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */ + RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */ + RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */ + RK_MUXROUTE_PMU(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */ + RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */ + RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */ }; static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, @@ -2102,6 +1738,68 @@ static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, *bit = (pin_num % 8) * 2; } +#define RK3568_PULL_PMU_OFFSET 0x20 +#define RK3568_PULL_GRF_OFFSET 0x80 +#define RK3568_PULL_BITS_PER_PIN 2 +#define RK3568_PULL_PINS_PER_REG 8 +#define RK3568_PULL_BANK_STRIDE 0x10 + +static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + if (bank->bank_num == 0) { + *regmap = info->regmap_pmu; + *reg = RK3568_PULL_PMU_OFFSET; + *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); + + *bit = pin_num % RK3568_PULL_PINS_PER_REG; + *bit *= RK3568_PULL_BITS_PER_PIN; + } else { + *regmap = info->regmap_base; + *reg = RK3568_PULL_GRF_OFFSET; + *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % RK3568_PULL_PINS_PER_REG); + *bit *= RK3568_PULL_BITS_PER_PIN; + } +} + +#define RK3568_DRV_PMU_OFFSET 0x70 +#define RK3568_DRV_GRF_OFFSET 0x200 +#define RK3568_DRV_BITS_PER_PIN 8 +#define RK3568_DRV_PINS_PER_REG 2 +#define RK3568_DRV_BANK_STRIDE 0x40 + +static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + /* The first 32 pins of the first bank are located in PMU */ + if (bank->bank_num == 0) { + *regmap = info->regmap_pmu; + *reg = RK3568_DRV_PMU_OFFSET; + *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); + + *bit = pin_num % RK3568_DRV_PINS_PER_REG; + *bit *= RK3568_DRV_BITS_PER_PIN; + } else { + *regmap = info->regmap_base; + *reg = RK3568_DRV_GRF_OFFSET; + *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; + *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); + + *bit = (pin_num % RK3568_DRV_PINS_PER_REG); + *bit *= RK3568_DRV_BITS_PER_PIN; + } +} + static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { { 2, 4, 8, 12, -1, -1, -1, -1 }, { 3, 6, 9, 12, -1, -1, -1, -1 }, @@ -2202,6 +1900,11 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, bank->bank_num, pin_num, strength); ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); + if (ctrl->type == RK3568) { + rmask_bits = RK3568_DRV_BITS_PER_PIN; + ret = (1 << (strength + 1)) - 1; + goto config; + } ret = -EINVAL; for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { @@ -2271,6 +1974,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, return -EINVAL; } +config: /* enable the write to the equivalent lower bits */ data = ((1 << rmask_bits) - 1) << (bit + 16); rmask = data | (data >> 16); @@ -2373,6 +2077,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, case RK3308: case RK3368: case RK3399: + case RK3568: pull_type = bank->pull_type[pin_num / 8]; ret = -EINVAL; for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); @@ -2382,6 +2087,14 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, break; } } + /* + * In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6, + * where that pull up value becomes 3. + */ + if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { + if (ret == 1) + ret = 3; + } if (ret < 0) { dev_err(info->dev, "unsupported pull setting %d\n", @@ -2426,6 +2139,35 @@ static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, return 0; } +#define RK3568_SCHMITT_BITS_PER_PIN 2 +#define RK3568_SCHMITT_PINS_PER_REG 8 +#define RK3568_SCHMITT_BANK_STRIDE 0x10 +#define RK3568_SCHMITT_GRF_OFFSET 0xc0 +#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30 + +static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + if (bank->bank_num == 0) { + *regmap = info->regmap_pmu; + *reg = RK3568_SCHMITT_PMUGRF_OFFSET; + } else { + *regmap = info->regmap_base; + *reg = RK3568_SCHMITT_GRF_OFFSET; + *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; + } + + *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4); + *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG; + *bit *= RK3568_SCHMITT_BITS_PER_PIN; + + return 0; +} + static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) { struct rockchip_pinctrl *info = bank->drvdata; @@ -2444,6 +2186,13 @@ static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) return ret; data >>= bit; + switch (ctrl->type) { + case RK3568: + return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1); + default: + break; + } + return data & 0x1; } @@ -2465,8 +2214,17 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, return ret; /* enable the write to the equivalent lower bits */ - data = BIT(bit + 16) | (enable << bit); - rmask = BIT(bit + 16) | BIT(bit); + switch (ctrl->type) { + case RK3568: + data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); + rmask = data | (data >> 16); + data |= ((enable ? 0x2 : 0x1) << bit); + break; + default: + data = BIT(bit + 16) | (enable << bit); + rmask = BIT(bit + 16) | BIT(bit); + break; + } return regmap_update_bits(regmap, reg, rmask, data); } @@ -2640,6 +2398,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, case RK3308: case RK3368: case RK3399: + case RK3568: return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); } @@ -3433,6 +3192,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev, * things enabled, so for us that's all masked and all enabled. */ writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); + writel_relaxed(0xffffffff, bank->reg_base + GPIO_PORTS_EOI); writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); gc->mask_cache = 0xffffffff; @@ -4213,6 +3973,45 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = { .drv_calc_reg = rk3399_calc_drv_reg_and_bit, }; +static struct rockchip_pin_bank rk3568_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT), + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT), + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT), + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT), + PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT), +}; + +static struct rockchip_pin_ctrl rk3568_pin_ctrl = { + .pin_banks = rk3568_pin_banks, + .nr_banks = ARRAY_SIZE(rk3568_pin_banks), + .label = "RK3568-GPIO", + .type = RK3568, + .grf_mux_offset = 0x0, + .pmu_mux_offset = 0x0, + .grf_drv_offset = 0x0200, + .pmu_drv_offset = 0x0070, + .iomux_routes = rk3568_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data), + .pull_calc_reg = rk3568_calc_pull_reg_and_bit, + .drv_calc_reg = rk3568_calc_drv_reg_and_bit, + .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit, +}; + static const struct of_device_id rockchip_pinctrl_dt_match[] = { { .compatible = "rockchip,px30-pinctrl", .data = &px30_pin_ctrl }, @@ -4242,6 +4041,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { .data = &rk3368_pin_ctrl }, { .compatible = "rockchip,rk3399-pinctrl", .data = &rk3399_pin_ctrl }, + { .compatible = "rockchip,rk3568-pinctrl", + .data = &rk3568_pin_ctrl }, {}, }; @@ -4259,3 +4060,14 @@ static int __init rockchip_pinctrl_drv_register(void) return platform_driver_register(&rockchip_pinctrl_driver); } postcore_initcall(rockchip_pinctrl_drv_register); + +static void __exit rockchip_pinctrl_drv_unregister(void) +{ + platform_driver_unregister(&rockchip_pinctrl_driver); +} +module_exit(rockchip_pinctrl_drv_unregister); + +MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:pinctrl-rockchip"); +MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 7771316dfffa..2c9c9835f375 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -270,20 +270,44 @@ static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg) writel(val, reg); } +static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs, + unsigned int pin) +{ + unsigned int mux_bytes = pcs->width / BITS_PER_BYTE; + + if (pcs->bits_per_mux) { + unsigned int pin_offset_bytes; + + pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE; + return (pin_offset_bytes / mux_bytes) * mux_bytes; + } + + return pin * mux_bytes; +} + +static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs, + unsigned int pin) +{ + return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin; +} + static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned pin) { struct pcs_device *pcs; - unsigned val, mux_bytes; + unsigned int val; unsigned long offset; size_t pa; pcs = pinctrl_dev_get_drvdata(pctldev); - mux_bytes = pcs->width / BITS_PER_BYTE; - offset = pin * mux_bytes; + offset = pcs_pin_reg_offset_get(pcs, pin); val = pcs->read(pcs->base + offset); + + if (pcs->bits_per_mux) + val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin); + pa = pcs->res->start + offset; seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME); @@ -384,7 +408,6 @@ static int pcs_request_gpio(struct pinctrl_dev *pctldev, struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); struct pcs_gpiofunc_range *frange = NULL; struct list_head *pos, *tmp; - int mux_bytes = 0; unsigned data; /* If function mask is null, return directly. */ @@ -392,29 +415,27 @@ static int pcs_request_gpio(struct pinctrl_dev *pctldev, return -ENOTSUPP; list_for_each_safe(pos, tmp, &pcs->gpiofuncs) { + u32 offset; + frange = list_entry(pos, struct pcs_gpiofunc_range, node); if (pin >= frange->offset + frange->npins || pin < frange->offset) continue; - mux_bytes = pcs->width / BITS_PER_BYTE; - if (pcs->bits_per_mux) { - int byte_num, offset, pin_shift; + offset = pcs_pin_reg_offset_get(pcs, pin); - byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE; - offset = (byte_num / mux_bytes) * mux_bytes; - pin_shift = pin % (pcs->width / pcs->bits_per_pin) * - pcs->bits_per_pin; + if (pcs->bits_per_mux) { + int pin_shift = pcs_pin_shift_reg_get(pcs, pin); data = pcs->read(pcs->base + offset); data &= ~(pcs->fmask << pin_shift); data |= frange->gpiofunc << pin_shift; pcs->write(data, pcs->base + offset); } else { - data = pcs->read(pcs->base + pin * mux_bytes); + data = pcs->read(pcs->base + offset); data &= ~pcs->fmask; data |= frange->gpiofunc; - pcs->write(data, pcs->base + pin * mux_bytes); + pcs->write(data, pcs->base + offset); } break; } @@ -512,7 +533,7 @@ static int pcs_pinconf_get(struct pinctrl_dev *pctldev, break; case PIN_CONFIG_DRIVE_STRENGTH: case PIN_CONFIG_SLEW_RATE: - case PIN_CONFIG_LOW_POWER_MODE: + case PIN_CONFIG_MODE_LOW_POWER: default: *config = data; break; @@ -550,7 +571,7 @@ static int pcs_pinconf_set(struct pinctrl_dev *pctldev, case PIN_CONFIG_INPUT_SCHMITT: case PIN_CONFIG_DRIVE_STRENGTH: case PIN_CONFIG_SLEW_RATE: - case PIN_CONFIG_LOW_POWER_MODE: + case PIN_CONFIG_MODE_LOW_POWER: shift = ffs(func->conf[i].mask) - 1; data &= ~func->conf[i].mask; data |= (arg << shift) & func->conf[i].mask; @@ -656,10 +677,8 @@ static const struct pinconf_ops pcs_pinconf_ops = { * pcs_add_pin() - add a pin to the static per controller pin array * @pcs: pcs driver instance * @offset: register offset from base - * @pin_pos: unused */ -static int pcs_add_pin(struct pcs_device *pcs, unsigned offset, - unsigned pin_pos) +static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset) { struct pcs_soc_data *pcs_soc = &pcs->socdata; struct pinctrl_pin_desc *pin; @@ -703,14 +722,12 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset, static int pcs_allocate_pin_table(struct pcs_device *pcs) { int mux_bytes, nr_pins, i; - int num_pins_in_register = 0; mux_bytes = pcs->width / BITS_PER_BYTE; if (pcs->bits_per_mux) { pcs->bits_per_pin = fls(pcs->fmask); nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; - num_pins_in_register = pcs->width / pcs->bits_per_pin; } else { nr_pins = pcs->size / mux_bytes; } @@ -728,17 +745,9 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs) for (i = 0; i < pcs->desc.npins; i++) { unsigned offset; int res; - int byte_num; - int pin_pos = 0; - if (pcs->bits_per_mux) { - byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE; - offset = (byte_num / mux_bytes) * mux_bytes; - pin_pos = i % num_pins_in_register; - } else { - offset = i * mux_bytes; - } - res = pcs_add_pin(pcs, offset, pin_pos); + offset = pcs_pin_reg_offset_get(pcs, i); + res = pcs_add_pin(pcs, offset); if (res < 0) { dev_err(pcs->dev, "error adding pins: %i\n", res); return res; @@ -910,7 +919,7 @@ static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np, { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, - { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, }, + { "pinctrl-single,low-power-mode", PIN_CONFIG_MODE_LOW_POWER, }, }; static const struct pcs_conf_type prop4[] = { { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index c6052a0e827a..5fb924a2eedd 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -1016,7 +1016,7 @@ static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_SLEW_RATE: arg = !!(reg & ZYNQ_PINCONF_SPEED); break; - case PIN_CONFIG_LOW_POWER_MODE: + case PIN_CONFIG_MODE_LOW_POWER: { enum zynq_io_standards iostd = zynq_pinconf_iostd_get(reg); @@ -1087,7 +1087,7 @@ static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev, reg &= ~ZYNQ_PINCONF_IOTYPE_MASK; reg |= arg << ZYNQ_PINCONF_IOTYPE_SHIFT; break; - case PIN_CONFIG_LOW_POWER_MODE: + case PIN_CONFIG_MODE_LOW_POWER: if (arg) reg |= ZYNQ_PINCONF_DISABLE_RECVR; else diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c new file mode 100644 index 000000000000..d5497003ce71 --- /dev/null +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -0,0 +1,906 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ZynqMP pin controller + * + * Copyright (C) 2020 Xilinx, Inc. + * + * Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> + * Rajan Vaja <rajan.vaja@xilinx.com> + */ + +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/firmware/xlnx-zynqmp.h> + +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf-generic.h> + +#include "core.h" +#include "pinctrl-utils.h" + +#define ZYNQMP_PIN_PREFIX "MIO" +#define PINCTRL_GET_FUNC_NAME_RESP_LEN 16 +#define MAX_FUNC_NAME_LEN 16 +#define MAX_GROUP_PIN 50 +#define MAX_PIN_GROUPS 50 +#define END_OF_FUNCTIONS "END_OF_FUNCTIONS" +#define NUM_GROUPS_PER_RESP 6 + +#define PINCTRL_GET_FUNC_GROUPS_RESP_LEN 12 +#define PINCTRL_GET_PIN_GROUPS_RESP_LEN 12 +#define NA_GROUP 0xFFFF +#define RESERVED_GROUP 0xFFFE + +#define DRIVE_STRENGTH_2MA 2 +#define DRIVE_STRENGTH_4MA 4 +#define DRIVE_STRENGTH_8MA 8 +#define DRIVE_STRENGTH_12MA 12 + +/** + * struct zynqmp_pmux_function - a pinmux function + * @name: Name of the pin mux function + * @groups: List of pin groups for this function + * @ngroups: Number of entries in @groups + * @node: Firmware node matching with the function + * + * This structure holds information about pin control function + * and function group names supporting that function. + */ +struct zynqmp_pmux_function { + char name[MAX_FUNC_NAME_LEN]; + const char * const *groups; + unsigned int ngroups; +}; + +/** + * struct zynqmp_pinctrl - driver data + * @pctrl: Pin control device + * @groups: Pin groups + * @ngroups: Number of @groups + * @funcs: Pin mux functions + * @nfuncs: Number of @funcs + * + * This struct is stored as driver data and used to retrieve + * information regarding pin control functions, groups and + * group pins. + */ +struct zynqmp_pinctrl { + struct pinctrl_dev *pctrl; + const struct zynqmp_pctrl_group *groups; + unsigned int ngroups; + const struct zynqmp_pmux_function *funcs; + unsigned int nfuncs; +}; + +/** + * struct zynqmp_pctrl_group - Pin control group info + * @name: Group name + * @pins: Group pin numbers + * @npins: Number of pins in the group + */ +struct zynqmp_pctrl_group { + const char *name; + unsigned int pins[MAX_GROUP_PIN]; + unsigned int npins; +}; + +static struct pinctrl_desc zynqmp_desc; + +static int zynqmp_pctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->ngroups; +} + +static const char *zynqmp_pctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->groups[selector].name; +} + +static int zynqmp_pctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *npins) +{ + struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *pins = pctrl->groups[selector].pins; + *npins = pctrl->groups[selector].npins; + + return 0; +} + +static const struct pinctrl_ops zynqmp_pctrl_ops = { + .get_groups_count = zynqmp_pctrl_get_groups_count, + .get_group_name = zynqmp_pctrl_get_group_name, + .get_group_pins = zynqmp_pctrl_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinctrl_utils_free_map, +}; + +static int zynqmp_pinmux_request_pin(struct pinctrl_dev *pctldev, + unsigned int pin) +{ + int ret; + + ret = zynqmp_pm_pinctrl_request(pin); + if (ret) { + dev_err(pctldev->dev, "request failed for pin %u\n", pin); + return ret; + } + + return 0; +} + +static int zynqmp_pmux_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->nfuncs; +} + +static const char *zynqmp_pmux_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->funcs[selector].name; +} + +/** + * zynqmp_pmux_get_function_groups() - Get groups for the function + * @pctldev: Pincontrol device pointer. + * @selector: Function ID + * @groups: Group names. + * @num_groups: Number of function groups. + * + * Get function's group count and group names. + */ +static int zynqmp_pmux_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned * const num_groups) +{ + struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctrl->funcs[selector].groups; + *num_groups = pctrl->funcs[selector].ngroups; + + return 0; +} + +/** + * zynqmp_pinmux_set_mux() - Set requested function for the group + * @pctldev: Pincontrol device pointer. + * @function: Function ID. + * @group: Group ID. + * + * Loop through all pins of the group and call firmware API + * to set requested function for all pins in the group. + * + * Return: 0 on success else error code. + */ +static int zynqmp_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, + unsigned int group) +{ + struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct zynqmp_pctrl_group *pgrp = &pctrl->groups[group]; + int ret, i; + + for (i = 0; i < pgrp->npins; i++) { + unsigned int pin = pgrp->pins[i]; + + ret = zynqmp_pm_pinctrl_set_function(pin, function); + if (ret) { + dev_err(pctldev->dev, "set mux failed for pin %u\n", + pin); + return ret; + } + } + + return 0; +} + +static int zynqmp_pinmux_release_pin(struct pinctrl_dev *pctldev, + unsigned int pin) +{ + int ret; + + ret = zynqmp_pm_pinctrl_release(pin); + if (ret) { + dev_err(pctldev->dev, "free pin failed for pin %u\n", + pin); + return ret; + } + + return 0; +} + +static const struct pinmux_ops zynqmp_pinmux_ops = { + .request = zynqmp_pinmux_request_pin, + .get_functions_count = zynqmp_pmux_get_functions_count, + .get_function_name = zynqmp_pmux_get_function_name, + .get_function_groups = zynqmp_pmux_get_function_groups, + .set_mux = zynqmp_pinmux_set_mux, + .free = zynqmp_pinmux_release_pin, +}; + +/** + * zynqmp_pinconf_cfg_get() - get config value for the pin + * @pctldev: Pin control device pointer. + * @pin: Pin number. + * @config: Value of config param. + * + * Get value of the requested configuration parameter for the + * given pin. + * + * Return: 0 on success else error code. + */ +static int zynqmp_pinconf_cfg_get(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *config) +{ + unsigned int arg, param = pinconf_to_config_param(*config); + int ret; + + if (pin >= zynqmp_desc.npins) + return -EOPNOTSUPP; + + switch (param) { + case PIN_CONFIG_SLEW_RATE: + param = PM_PINCTRL_CONFIG_SLEW_RATE; + ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg); + break; + case PIN_CONFIG_BIAS_PULL_UP: + param = PM_PINCTRL_CONFIG_PULL_CTRL; + ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg); + if (arg != PM_PINCTRL_BIAS_PULL_UP) + return -EINVAL; + + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + param = PM_PINCTRL_CONFIG_PULL_CTRL; + ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg); + if (arg != PM_PINCTRL_BIAS_PULL_DOWN) + return -EINVAL; + + arg = 1; + break; + case PIN_CONFIG_BIAS_DISABLE: + param = PM_PINCTRL_CONFIG_BIAS_STATUS; + ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg); + if (arg != PM_PINCTRL_BIAS_DISABLE) + return -EINVAL; + + arg = 1; + break; + case PIN_CONFIG_POWER_SOURCE: + param = PM_PINCTRL_CONFIG_VOLTAGE_STATUS; + ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg); + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + param = PM_PINCTRL_CONFIG_SCHMITT_CMOS; + ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg); + break; + case PIN_CONFIG_DRIVE_STRENGTH: + param = PM_PINCTRL_CONFIG_DRIVE_STRENGTH; + ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg); + switch (arg) { + case PM_PINCTRL_DRIVE_STRENGTH_2MA: + arg = DRIVE_STRENGTH_2MA; + break; + case PM_PINCTRL_DRIVE_STRENGTH_4MA: + arg = DRIVE_STRENGTH_4MA; + break; + case PM_PINCTRL_DRIVE_STRENGTH_8MA: + arg = DRIVE_STRENGTH_8MA; + break; + case PM_PINCTRL_DRIVE_STRENGTH_12MA: + arg = DRIVE_STRENGTH_12MA; + break; + default: + /* Invalid drive strength */ + dev_warn(pctldev->dev, + "Invalid drive strength for pin %d\n", + pin); + return -EINVAL; + } + break; + default: + ret = -EOPNOTSUPP; + break; + } + + if (ret) + return ret; + + param = pinconf_to_config_param(*config); + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +/** + * zynqmp_pinconf_cfg_set() - Set requested config for the pin + * @pctldev: Pincontrol device pointer. + * @pin: Pin number. + * @configs: Configuration to set. + * @num_configs: Number of configurations. + * + * Loop through all configurations and call firmware API + * to set requested configurations for the pin. + * + * Return: 0 on success else error code. + */ +static int zynqmp_pinconf_cfg_set(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *configs, + unsigned int num_configs) +{ + int i, ret; + + if (pin >= zynqmp_desc.npins) + return -EOPNOTSUPP; + + for (i = 0; i < num_configs; i++) { + unsigned int param = pinconf_to_config_param(configs[i]); + unsigned int arg = pinconf_to_config_argument(configs[i]); + unsigned int value; + + switch (param) { + case PIN_CONFIG_SLEW_RATE: + param = PM_PINCTRL_CONFIG_SLEW_RATE; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; + case PIN_CONFIG_BIAS_PULL_UP: + param = PM_PINCTRL_CONFIG_PULL_CTRL; + arg = PM_PINCTRL_BIAS_PULL_UP; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + param = PM_PINCTRL_CONFIG_PULL_CTRL; + arg = PM_PINCTRL_BIAS_PULL_DOWN; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; + case PIN_CONFIG_BIAS_DISABLE: + param = PM_PINCTRL_CONFIG_BIAS_STATUS; + arg = PM_PINCTRL_BIAS_DISABLE; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + param = PM_PINCTRL_CONFIG_SCHMITT_CMOS; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; + case PIN_CONFIG_DRIVE_STRENGTH: + switch (arg) { + case DRIVE_STRENGTH_2MA: + value = PM_PINCTRL_DRIVE_STRENGTH_2MA; + break; + case DRIVE_STRENGTH_4MA: + value = PM_PINCTRL_DRIVE_STRENGTH_4MA; + break; + case DRIVE_STRENGTH_8MA: + value = PM_PINCTRL_DRIVE_STRENGTH_8MA; + break; + case DRIVE_STRENGTH_12MA: + value = PM_PINCTRL_DRIVE_STRENGTH_12MA; + break; + default: + /* Invalid drive strength */ + dev_warn(pctldev->dev, + "Invalid drive strength for pin %d\n", + pin); + return -EINVAL; + } + + param = PM_PINCTRL_CONFIG_DRIVE_STRENGTH; + ret = zynqmp_pm_pinctrl_set_config(pin, param, value); + break; + case PIN_CONFIG_POWER_SOURCE: + param = PM_PINCTRL_CONFIG_VOLTAGE_STATUS; + ret = zynqmp_pm_pinctrl_get_config(pin, param, &value); + + if (arg != value) + dev_warn(pctldev->dev, + "Invalid IO Standard requested for pin %d\n", + pin); + + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + case PIN_CONFIG_MODE_LOW_POWER: + /* + * These cases are mentioned in dts but configurable + * registers are unknown. So falling through to ignore + * boot time warnings as of now. + */ + ret = 0; + break; + default: + dev_warn(pctldev->dev, + "unsupported configuration parameter '%u'\n", + param); + ret = -EOPNOTSUPP; + break; + } + + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + if (ret) + dev_warn(pctldev->dev, + "failed to set: pin %u param %u value %u\n", + pin, param, arg); + } + + return 0; +} + +/** + * zynqmp_pinconf_group_set() - Set requested config for the group + * @pctldev: Pincontrol device pointer. + * @selector: Group ID. + * @configs: Configuration to set. + * @num_configs: Number of configurations. + * + * Call function to set configs for each pin in the group. + * + * Return: 0 on success else error code. + */ +static int zynqmp_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *configs, + unsigned int num_configs) +{ + int i, ret; + struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct zynqmp_pctrl_group *pgrp = &pctrl->groups[selector]; + + for (i = 0; i < pgrp->npins; i++) { + ret = zynqmp_pinconf_cfg_set(pctldev, pgrp->pins[i], configs, + num_configs); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinconf_ops zynqmp_pinconf_ops = { + .is_generic = true, + .pin_config_get = zynqmp_pinconf_cfg_get, + .pin_config_set = zynqmp_pinconf_cfg_set, + .pin_config_group_set = zynqmp_pinconf_group_set, +}; + +static struct pinctrl_desc zynqmp_desc = { + .name = "zynqmp_pinctrl", + .owner = THIS_MODULE, + .pctlops = &zynqmp_pctrl_ops, + .pmxops = &zynqmp_pinmux_ops, + .confops = &zynqmp_pinconf_ops, +}; + +static int zynqmp_pinctrl_get_function_groups(u32 fid, u32 index, u16 *groups) +{ + struct zynqmp_pm_query_data qdata = {0}; + u32 payload[PAYLOAD_ARG_CNT]; + int ret; + + qdata.qid = PM_QID_PINCTRL_GET_FUNCTION_GROUPS; + qdata.arg1 = fid; + qdata.arg2 = index; + + ret = zynqmp_pm_query_data(qdata, payload); + if (ret) + return ret; + + memcpy(groups, &payload[1], PINCTRL_GET_FUNC_GROUPS_RESP_LEN); + + return ret; +} + +static int zynqmp_pinctrl_get_func_num_groups(u32 fid, unsigned int *ngroups) +{ + struct zynqmp_pm_query_data qdata = {0}; + u32 payload[PAYLOAD_ARG_CNT]; + int ret; + + qdata.qid = PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS; + qdata.arg1 = fid; + + ret = zynqmp_pm_query_data(qdata, payload); + if (ret) + return ret; + + *ngroups = payload[1]; + + return ret; +} + +/** + * zynqmp_pinctrl_prepare_func_groups() - prepare function and groups data + * @dev: Device pointer. + * @fid: Function ID. + * @func: Function data. + * @groups: Groups data. + * + * Query firmware to get group IDs for each function. Firmware returns + * group IDs. Based on group index for the function, group names in + * the function are stored. For example, the first group in "eth0" function + * is named as "eth0_0" and second group as "eth0_1" and so on. + * + * Based on the group ID received from the firmware, function stores name of + * the group for that group ID. For example, if "eth0" first group ID + * is x, groups[x] name will be stored as "eth0_0". + * + * Once done for each function, each function would have its group names + * and each groups would also have their names. + * + * Return: 0 on success else error code. + */ +static int zynqmp_pinctrl_prepare_func_groups(struct device *dev, u32 fid, + struct zynqmp_pmux_function *func, + struct zynqmp_pctrl_group *groups) +{ + u16 resp[NUM_GROUPS_PER_RESP] = {0}; + const char **fgroups; + int ret = 0, index, i; + + fgroups = devm_kzalloc(dev, sizeof(*fgroups) * func->ngroups, GFP_KERNEL); + if (!fgroups) + return -ENOMEM; + + for (index = 0; index < func->ngroups; index += NUM_GROUPS_PER_RESP) { + ret = zynqmp_pinctrl_get_function_groups(fid, index, resp); + if (ret) + return ret; + + for (i = 0; i < NUM_GROUPS_PER_RESP; i++) { + if (resp[i] == NA_GROUP) + goto done; + + if (resp[i] == RESERVED_GROUP) + continue; + + fgroups[index + i] = devm_kasprintf(dev, GFP_KERNEL, + "%s_%d_grp", + func->name, + index + i); + if (!fgroups[index + i]) + return -ENOMEM; + + groups[resp[i]].name = devm_kasprintf(dev, GFP_KERNEL, + "%s_%d_grp", + func->name, + index + i); + if (!groups[resp[i]].name) + return -ENOMEM; + } + } +done: + func->groups = fgroups; + + return ret; +} + +static void zynqmp_pinctrl_get_function_name(u32 fid, char *name) +{ + struct zynqmp_pm_query_data qdata = {0}; + u32 payload[PAYLOAD_ARG_CNT]; + + qdata.qid = PM_QID_PINCTRL_GET_FUNCTION_NAME; + qdata.arg1 = fid; + + /* + * Name of the function is maximum 16 bytes and cannot + * accommodate the return value in SMC buffers, hence ignoring + * the return value for this specific qid. + */ + zynqmp_pm_query_data(qdata, payload); + memcpy(name, payload, PINCTRL_GET_FUNC_NAME_RESP_LEN); +} + +static int zynqmp_pinctrl_get_num_functions(unsigned int *nfuncs) +{ + struct zynqmp_pm_query_data qdata = {0}; + u32 payload[PAYLOAD_ARG_CNT]; + int ret; + + qdata.qid = PM_QID_PINCTRL_GET_NUM_FUNCTIONS; + + ret = zynqmp_pm_query_data(qdata, payload); + if (ret) + return ret; + + *nfuncs = payload[1]; + + return ret; +} + +static int zynqmp_pinctrl_get_pin_groups(u32 pin, u32 index, u16 *groups) +{ + struct zynqmp_pm_query_data qdata = {0}; + u32 payload[PAYLOAD_ARG_CNT]; + int ret; + + qdata.qid = PM_QID_PINCTRL_GET_PIN_GROUPS; + qdata.arg1 = pin; + qdata.arg2 = index; + + ret = zynqmp_pm_query_data(qdata, payload); + if (ret) + return ret; + + memcpy(groups, &payload[1], PINCTRL_GET_PIN_GROUPS_RESP_LEN); + + return ret; +} + +static void zynqmp_pinctrl_group_add_pin(struct zynqmp_pctrl_group *group, + unsigned int pin) +{ + group->pins[group->npins++] = pin; +} + +/** + * zynqmp_pinctrl_create_pin_groups() - assign pins to respective groups + * @dev: Device pointer. + * @groups: Groups data. + * @pin: Pin number. + * + * Query firmware to get groups available for the given pin. + * Based on the firmware response(group IDs for the pin), add + * pin number to the respective group's pin array. + * + * Once all pins are queries, each groups would have its number + * of pins and pin numbers data. + * + * Return: 0 on success else error code. + */ +static int zynqmp_pinctrl_create_pin_groups(struct device *dev, + struct zynqmp_pctrl_group *groups, + unsigned int pin) +{ + u16 resp[NUM_GROUPS_PER_RESP] = {0}; + int ret, i, index = 0; + + do { + ret = zynqmp_pinctrl_get_pin_groups(pin, index, resp); + if (ret) + return ret; + + for (i = 0; i < NUM_GROUPS_PER_RESP; i++) { + if (resp[i] == NA_GROUP) + return ret; + + if (resp[i] == RESERVED_GROUP) + continue; + + zynqmp_pinctrl_group_add_pin(&groups[resp[i]], pin); + } + index += NUM_GROUPS_PER_RESP; + } while (index <= MAX_PIN_GROUPS); + + return ret; +} + +/** + * zynqmp_pinctrl_prepare_group_pins() - prepare each group's pin data + * @dev: Device pointer. + * @groups: Groups data. + * @ngroups: Number of groups. + * + * Prepare pin number and number of pins data for each pins. + * + * Return: 0 on success else error code. + */ +static int zynqmp_pinctrl_prepare_group_pins(struct device *dev, + struct zynqmp_pctrl_group *groups, + unsigned int ngroups) +{ + unsigned int pin; + int ret; + + for (pin = 0; pin < zynqmp_desc.npins; pin++) { + ret = zynqmp_pinctrl_create_pin_groups(dev, groups, pin); + if (ret) + return ret; + } + + return 0; +} + +/** + * zynqmp_pinctrl_prepare_function_info() - prepare function info + * @dev: Device pointer. + * @pctrl: Pin control driver data. + * + * Query firmware for functions, groups and pin information and + * prepare pin control driver data. + * + * Query number of functions and number of function groups (number + * of groups in given function) to allocate required memory buffers + * for functions and groups. Once buffers are allocated to store + * functions and groups data, query and store required information + * (number of groups and group names for each function, number of + * pins and pin numbers for each group). + * + * Return: 0 on success else error code. + */ +static int zynqmp_pinctrl_prepare_function_info(struct device *dev, + struct zynqmp_pinctrl *pctrl) +{ + struct zynqmp_pmux_function *funcs; + struct zynqmp_pctrl_group *groups; + int ret, i; + + ret = zynqmp_pinctrl_get_num_functions(&pctrl->nfuncs); + if (ret) + return ret; + + funcs = devm_kzalloc(dev, sizeof(*funcs) * pctrl->nfuncs, GFP_KERNEL); + if (!funcs) + return -ENOMEM; + + for (i = 0; i < pctrl->nfuncs; i++) { + zynqmp_pinctrl_get_function_name(i, funcs[i].name); + + ret = zynqmp_pinctrl_get_func_num_groups(i, &funcs[i].ngroups); + if (ret) + return ret; + + pctrl->ngroups += funcs[i].ngroups; + } + + groups = devm_kzalloc(dev, sizeof(*groups) * pctrl->ngroups, GFP_KERNEL); + if (!groups) + return -ENOMEM; + + for (i = 0; i < pctrl->nfuncs; i++) { + ret = zynqmp_pinctrl_prepare_func_groups(dev, i, &funcs[i], + groups); + if (ret) + return ret; + } + + ret = zynqmp_pinctrl_prepare_group_pins(dev, groups, pctrl->ngroups); + if (ret) + return ret; + + pctrl->funcs = funcs; + pctrl->groups = groups; + + return ret; +} + +static int zynqmp_pinctrl_get_num_pins(unsigned int *npins) +{ + struct zynqmp_pm_query_data qdata = {0}; + u32 payload[PAYLOAD_ARG_CNT]; + int ret; + + qdata.qid = PM_QID_PINCTRL_GET_NUM_PINS; + + ret = zynqmp_pm_query_data(qdata, payload); + if (ret) + return ret; + + *npins = payload[1]; + + return ret; +} + +/** + * zynqmp_pinctrl_prepare_pin_desc() - prepare pin description info + * @dev: Device pointer. + * @zynqmp_pins: Pin information. + * @npins: Number of pins. + * + * Query number of pins information from firmware and prepare pin + * description containing pin number and pin name. + * + * Return: 0 on success else error code. + */ +static int zynqmp_pinctrl_prepare_pin_desc(struct device *dev, + const struct pinctrl_pin_desc + **zynqmp_pins, + unsigned int *npins) +{ + struct pinctrl_pin_desc *pins, *pin; + int ret; + int i; + + ret = zynqmp_pinctrl_get_num_pins(npins); + if (ret) + return ret; + + pins = devm_kzalloc(dev, sizeof(*pins) * *npins, GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (i = 0; i < *npins; i++) { + pin = &pins[i]; + pin->number = i; + pin->name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", + ZYNQMP_PIN_PREFIX, i); + if (!pin->name) + return -ENOMEM; + } + + *zynqmp_pins = pins; + + return 0; +} + +static int zynqmp_pinctrl_probe(struct platform_device *pdev) +{ + struct zynqmp_pinctrl *pctrl; + int ret; + + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + ret = zynqmp_pinctrl_prepare_pin_desc(&pdev->dev, + &zynqmp_desc.pins, + &zynqmp_desc.npins); + if (ret) { + dev_err(&pdev->dev, "pin desc prepare fail with %d\n", + ret); + return ret; + } + + ret = zynqmp_pinctrl_prepare_function_info(&pdev->dev, pctrl); + if (ret) { + dev_err(&pdev->dev, "function info prepare fail with %d\n", + ret); + return ret; + } + + pctrl->pctrl = pinctrl_register(&zynqmp_desc, &pdev->dev, pctrl); + if (IS_ERR(pctrl->pctrl)) + return PTR_ERR(pctrl->pctrl); + + platform_set_drvdata(pdev, pctrl); + + return ret; +} + +static int zynqmp_pinctrl_remove(struct platform_device *pdev) +{ + struct zynqmp_pinctrl *pctrl = platform_get_drvdata(pdev); + + pinctrl_unregister(pctrl->pctrl); + + return 0; +} + +static const struct of_device_id zynqmp_pinctrl_of_match[] = { + { .compatible = "xlnx,zynqmp-pinctrl" }, + { } +}; + +MODULE_DEVICE_TABLE(of, zynqmp_pinctrl_of_match); + +static struct platform_driver zynqmp_pinctrl_driver = { + .driver = { + .name = "zynqmp-pinctrl", + .of_match_table = zynqmp_pinctrl_of_match, + }, + .probe = zynqmp_pinctrl_probe, + .remove = zynqmp_pinctrl_remove, +}; + +module_platform_driver(zynqmp_pinctrl_driver); + +MODULE_AUTHOR("Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>"); +MODULE_DESCRIPTION("ZynqMP Pin Controller Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 36a11c9e893a..6cdbd9ccf2f0 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -12,6 +12,7 @@ */ #define pr_fmt(fmt) "pinmux core: " fmt +#include <linux/ctype.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/init.h> @@ -673,13 +674,114 @@ void pinmux_show_setting(struct seq_file *s, DEFINE_SHOW_ATTRIBUTE(pinmux_functions); DEFINE_SHOW_ATTRIBUTE(pinmux_pins); +#define PINMUX_SELECT_MAX 128 +static ssize_t pinmux_select(struct file *file, const char __user *user_buf, + size_t len, loff_t *ppos) +{ + struct seq_file *sfile = file->private_data; + struct pinctrl_dev *pctldev = sfile->private; + const struct pinmux_ops *pmxops = pctldev->desc->pmxops; + const char *const *groups; + char *buf, *gname, *fname; + unsigned int num_groups; + int fsel, gsel, ret; + + if (len > PINMUX_SELECT_MAX) + return -ENOMEM; + + buf = kzalloc(PINMUX_SELECT_MAX, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + ret = strncpy_from_user(buf, user_buf, PINMUX_SELECT_MAX); + if (ret < 0) + goto exit_free_buf; + buf[len-1] = '\0'; + + /* remove leading and trailing spaces of input buffer */ + gname = strstrip(buf); + if (*gname == '\0') { + ret = -EINVAL; + goto exit_free_buf; + } + + /* find a separator which is a spacelike character */ + for (fname = gname; !isspace(*fname); fname++) { + if (*fname == '\0') { + ret = -EINVAL; + goto exit_free_buf; + } + } + *fname = '\0'; + + /* drop extra spaces between function and group names */ + fname = skip_spaces(fname + 1); + if (*fname == '\0') { + ret = -EINVAL; + goto exit_free_buf; + } + + ret = pinmux_func_name_to_selector(pctldev, fname); + if (ret < 0) { + dev_err(pctldev->dev, "invalid function %s in map table\n", fname); + goto exit_free_buf; + } + fsel = ret; + + ret = pmxops->get_function_groups(pctldev, fsel, &groups, &num_groups); + if (ret) { + dev_err(pctldev->dev, "no groups for function %d (%s)", fsel, fname); + goto exit_free_buf; + } + + ret = match_string(groups, num_groups, gname); + if (ret < 0) { + dev_err(pctldev->dev, "invalid group %s", gname); + goto exit_free_buf; + } + + ret = pinctrl_get_group_selector(pctldev, gname); + if (ret < 0) { + dev_err(pctldev->dev, "failed to get group selector for %s", gname); + goto exit_free_buf; + } + gsel = ret; + + ret = pmxops->set_mux(pctldev, fsel, gsel); + if (ret) { + dev_err(pctldev->dev, "set_mux() failed: %d", ret); + goto exit_free_buf; + } + ret = len; + +exit_free_buf: + kfree(buf); + + return ret; +} + +static int pinmux_select_open(struct inode *inode, struct file *file) +{ + return single_open(file, NULL, inode->i_private); +} + +static const struct file_operations pinmux_select_ops = { + .owner = THIS_MODULE, + .open = pinmux_select_open, + .write = pinmux_select, + .llseek = no_llseek, + .release = single_release, +}; + void pinmux_init_device_debugfs(struct dentry *devroot, struct pinctrl_dev *pctldev) { - debugfs_create_file("pinmux-functions", S_IFREG | S_IRUGO, + debugfs_create_file("pinmux-functions", 0444, devroot, pctldev, &pinmux_functions_fops); - debugfs_create_file("pinmux-pins", S_IFREG | S_IRUGO, + debugfs_create_file("pinmux-pins", 0444, devroot, pctldev, &pinmux_pins_fops); + debugfs_create_file("pinmux-select", 0200, + devroot, pctldev, &pinmux_select_ops); } #endif /* CONFIG_DEBUG_FS */ diff --git a/drivers/pinctrl/pxa/pinctrl-pxa2xx.c b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c index eab029a21643..d2568dab8c78 100644 --- a/drivers/pinctrl/pxa/pinctrl-pxa2xx.c +++ b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c @@ -194,7 +194,7 @@ static int pxa2xx_pconf_group_get(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pctl->lock, flags); val = readl_relaxed(pgsr) & BIT(pin % 32); - *config = val ? PIN_CONFIG_LOW_POWER_MODE : 0; + *config = val ? PIN_CONFIG_MODE_LOW_POWER : 0; spin_unlock_irqrestore(&pctl->lock, flags); dev_dbg(pctl->dev, "get sleep gpio state(pin=%d) %d\n", @@ -217,7 +217,7 @@ static int pxa2xx_pconf_group_set(struct pinctrl_dev *pctldev, for (i = 0; i < num_configs; i++) { switch (pinconf_to_config_param(configs[i])) { - case PIN_CONFIG_LOW_POWER_MODE: + case PIN_CONFIG_MODE_LOW_POWER: is_set = pinconf_to_config_argument(configs[i]); break; default: diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 6853a896c476..25d2f7f7f3b6 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -3,7 +3,7 @@ if (ARCH_QCOM || COMPILE_TEST) config PINCTRL_MSM tristate "Qualcomm core pin controller driver" - depends on QCOM_SCM || !QCOM_SCM #if QCOM_SCM=m this can't be =y + depends on GPIOLIB && (QCOM_SCM || !QCOM_SCM) #if QCOM_SCM=m this can't be =y select PINMUX select PINCONF select GENERIC_PINCONF @@ -222,7 +222,7 @@ config PINCTRL_SC7280 config PINCTRL_SC8180X tristate "Qualcomm Technologies Inc SC8180x pin controller driver" - depends on GPIOLIB && OF + depends on GPIOLIB && (OF || ACPI) select PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c b/drivers/pinctrl/qcom/pinctrl-sc7280.c index 9d41abfca37e..afddf6d60dbe 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c @@ -1449,6 +1449,28 @@ static const struct msm_pingroup sc7280_groups[] = { [182] = SDC_QDSD_PINGROUP(sdc2_data, 0xb4000, 9, 0), }; +static const struct msm_gpio_wakeirq_map sc7280_pdc_map[] = { + { 0, 134 }, { 3, 131 }, { 4, 121 }, { 7, 103 }, { 8, 155 }, + { 11, 93 }, { 12, 78 }, { 15, 79 }, { 16, 80 }, { 18, 81 }, + { 19, 107 }, { 20, 82 }, { 21, 83 }, { 23, 99 }, { 24, 86 }, + { 25, 95 }, { 27, 158 }, { 28, 159 }, { 31, 90 }, { 32, 144 }, + { 34, 77 }, { 35, 92 }, { 36, 157 }, { 39, 73 }, { 40, 97 }, + { 41, 98 }, { 43, 85 }, { 44, 100 }, { 45, 101 }, { 47, 102 }, + { 48, 74 }, { 51, 112 }, { 52, 156 }, { 54, 117 }, { 55, 84 }, + { 56, 108 }, { 59, 110 }, { 60, 111 }, { 61, 123 }, { 63, 104 }, + { 68, 127 }, { 72, 150 }, { 75, 133 }, { 77, 125 }, { 78, 105 }, + { 79, 106 }, { 80, 118 }, { 81, 119 }, { 82, 162 }, { 83, 122 }, + { 86, 75 }, { 88, 154 }, { 89, 124 }, { 90, 149 }, { 91, 76 }, + { 93, 128 }, { 95, 160 }, { 101, 126 }, { 102, 96 }, { 103, 116 }, + { 104, 114 }, { 112, 72 }, { 116, 135 }, { 117, 163 }, { 119, 137 }, + { 121, 138 }, { 123, 139 }, { 125, 140 }, { 127, 141 }, { 128, 165 }, + { 129, 143 }, { 130, 94 }, { 131, 145 }, { 133, 146 }, { 136, 147 }, + { 140, 148 }, { 141, 115 }, { 142, 113 }, { 145, 130 }, { 148, 132 }, + { 150, 87 }, { 151, 88 }, { 153, 89 }, { 155, 164 }, { 156, 129 }, + { 157, 161 }, { 158, 120 }, { 161, 136 }, { 163, 142 }, { 172, 166 }, + { 174, 167 }, +}; + static const struct msm_pinctrl_soc_data sc7280_pinctrl = { .pins = sc7280_pins, .npins = ARRAY_SIZE(sc7280_pins), @@ -1457,6 +1479,8 @@ static const struct msm_pinctrl_soc_data sc7280_pinctrl = { .groups = sc7280_groups, .ngroups = ARRAY_SIZE(sc7280_groups), .ngpios = 176, + .wakeirq_map = sc7280_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sc7280_pdc_map), }; static int sc7280_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/qcom/pinctrl-sc8180x.c b/drivers/pinctrl/qcom/pinctrl-sc8180x.c index b765bf667574..0d9654b4ab60 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8180x.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8180x.c @@ -23,6 +23,21 @@ enum { WEST }; +/* + * ACPI DSDT has one single memory resource for TLMM. The offsets below are + * used to locate different tiles for ACPI probe. + */ +struct tile_info { + u32 offset; + u32 size; +}; + +static const struct tile_info sc8180x_tile_info[] = { + { 0x00d00000, 0x00300000, }, + { 0x00500000, 0x00700000, }, + { 0x00100000, 0x00300000, }, +}; + #define FUNCTION(fname) \ [msm_mux_##fname] = { \ .name = #fname, \ @@ -1557,6 +1572,13 @@ static const struct msm_pingroup sc8180x_groups[] = { [193] = SDC_QDSD_PINGROUP(sdc2_data, 0x4b2000, 9, 0), }; +static const int sc8180x_acpi_reserved_gpios[] = { + 0, 1, 2, 3, + 47, 48, 49, 50, + 126, 127, 128, 129, + -1 /* terminator */ +}; + static const struct msm_gpio_wakeirq_map sc8180x_pdc_map[] = { { 3, 31 }, { 5, 32 }, { 8, 33 }, { 9, 34 }, { 10, 100 }, { 12, 104 }, { 24, 37 }, { 26, 38 }, { 27, 41 }, { 28, 42 }, { 30, 39 }, { 36, 43 }, @@ -1588,13 +1610,109 @@ static struct msm_pinctrl_soc_data sc8180x_pinctrl = { .nwakeirq_map = ARRAY_SIZE(sc8180x_pdc_map), }; +static const struct msm_pinctrl_soc_data sc8180x_acpi_pinctrl = { + .tiles = sc8180x_tiles, + .ntiles = ARRAY_SIZE(sc8180x_tiles), + .pins = sc8180x_pins, + .npins = ARRAY_SIZE(sc8180x_pins), + .groups = sc8180x_groups, + .ngroups = ARRAY_SIZE(sc8180x_groups), + .reserved_gpios = sc8180x_acpi_reserved_gpios, + .ngpios = 190, +}; + +/* + * ACPI DSDT has one single memory resource for TLMM, which voilates the + * hardware layout of 3 sepearte tiles. Let's split the memory resource into + * 3 named ones, so that msm_pinctrl_probe() can map memory for ACPI in the + * same way as for DT probe. + */ +static int sc8180x_pinctrl_add_tile_resources(struct platform_device *pdev) +{ + int nres_num = pdev->num_resources + ARRAY_SIZE(sc8180x_tiles) - 1; + struct resource *mres, *nres, *res; + int i, ret; + + /* + * DT already has tiles defined properly, so nothing needs to be done + * for DT probe. + */ + if (pdev->dev.of_node) + return 0; + + /* Allocate for new resources */ + nres = devm_kzalloc(&pdev->dev, sizeof(*nres) * nres_num, GFP_KERNEL); + if (!nres) + return -ENOMEM; + + res = nres; + + for (i = 0; i < pdev->num_resources; i++) { + struct resource *r = &pdev->resource[i]; + + /* Save memory resource and copy others */ + if (resource_type(r) == IORESOURCE_MEM) + mres = r; + else + *res++ = *r; + } + + /* Append tile memory resources */ + for (i = 0; i < ARRAY_SIZE(sc8180x_tiles); i++, res++) { + const struct tile_info *info = &sc8180x_tile_info[i]; + + res->start = mres->start + info->offset; + res->end = mres->start + info->offset + info->size - 1; + res->flags = mres->flags; + res->name = sc8180x_tiles[i]; + + /* Add new MEM to resource tree */ + insert_resource(mres->parent, res); + } + + /* Remove old MEM from resource tree */ + remove_resource(mres); + + /* Free old resources and install new ones */ + ret = platform_device_add_resources(pdev, nres, nres_num); + if (ret) { + dev_err(&pdev->dev, "failed to add new resources: %d\n", ret); + return ret; + } + + return 0; +} + static int sc8180x_pinctrl_probe(struct platform_device *pdev) { - return msm_pinctrl_probe(pdev, &sc8180x_pinctrl); + const struct msm_pinctrl_soc_data *soc_data; + int ret; + + soc_data = device_get_match_data(&pdev->dev); + if (!soc_data) + return -EINVAL; + + ret = sc8180x_pinctrl_add_tile_resources(pdev); + if (ret) + return ret; + + return msm_pinctrl_probe(pdev, soc_data); } +static const struct acpi_device_id sc8180x_pinctrl_acpi_match[] = { + { + .id = "QCOM040D", + .driver_data = (kernel_ulong_t) &sc8180x_acpi_pinctrl, + }, + { } +}; +MODULE_DEVICE_TABLE(acpi, sc8180x_pinctrl_acpi_match); + static const struct of_device_id sc8180x_pinctrl_of_match[] = { - { .compatible = "qcom,sc8180x-tlmm", }, + { + .compatible = "qcom,sc8180x-tlmm", + .data = &sc8180x_pinctrl, + }, { }, }; MODULE_DEVICE_TABLE(of, sc8180x_pinctrl_of_match); @@ -1603,6 +1721,7 @@ static struct platform_driver sc8180x_pinctrl_driver = { .driver = { .name = "sc8180x-pinctrl", .of_match_table = sc8180x_pinctrl_of_match, + .acpi_match_table = sc8180x_pinctrl_acpi_match, }, .probe = sc8180x_pinctrl_probe, .remove = msm_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350.c b/drivers/pinctrl/qcom/pinctrl-sm8350.c index a406ed0ec7d3..4d8f8636c2b3 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8350.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8350.c @@ -1603,6 +1603,25 @@ static const struct msm_pingroup sm8350_groups[] = { [206] = SDC_PINGROUP(sdc2_data, 0x1cf000, 9, 0), }; +static const struct msm_gpio_wakeirq_map sm8350_pdc_map[] = { + { 2, 117 }, { 7, 82 }, { 11, 83 }, { 14, 80 }, { 15, 146 }, + { 19, 121 }, { 23, 84 }, { 26, 86 }, { 27, 75 }, { 31, 85 }, + { 32, 97 }, { 34, 98 }, { 35, 131 }, { 36, 79 }, { 38, 99 }, + { 39, 92 }, { 40, 101 }, { 43, 137 }, { 44, 102 }, { 46, 96 }, + { 47, 93 }, { 50, 108 }, { 51, 127 }, { 55, 128 }, { 56, 81 }, + { 59, 112 }, { 60, 119 }, { 63, 73 }, { 67, 74 }, { 71, 134 }, + { 75, 103 }, { 79, 104 }, { 80, 126 }, { 81, 139 }, { 82, 140 }, + { 83, 141 }, { 84, 124 }, { 85, 109 }, { 86, 143 }, { 87, 138 }, + { 88, 122 }, { 89, 113 }, { 90, 114 }, { 91, 115 }, { 92, 76 }, + { 95, 147 }, { 96, 148 }, { 98, 149 }, { 99, 150 }, { 115, 125 }, + { 116, 106 }, { 117, 105 }, { 118, 116 }, { 119, 123 }, { 130, 145 }, + { 136, 72 }, { 140, 100 }, { 151, 110 }, { 153, 95 }, { 155, 107 }, + { 156, 94 }, { 157, 111 }, { 159, 118 }, { 162, 77 }, { 165, 78 }, + { 169, 70 }, { 172, 132 }, { 174, 87 }, { 175, 88 }, { 177, 89 }, + { 179, 120 }, { 180, 129 }, { 183, 90 }, { 185, 136 }, { 187, 142 }, + { 190, 144 }, { 198, 91 }, { 200, 133 }, { 202, 135 }, +}; + static const struct msm_pinctrl_soc_data sm8350_tlmm = { .pins = sm8350_pins, .npins = ARRAY_SIZE(sm8350_pins), @@ -1611,6 +1630,8 @@ static const struct msm_pinctrl_soc_data sm8350_tlmm = { .groups = sm8350_groups, .ngroups = ARRAY_SIZE(sm8350_groups), .ngpios = 204, + .wakeirq_map = sm8350_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sm8350_pdc_map), }; static int sm8350_tlmm_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 9801c717e311..00870da0c94e 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1127,8 +1127,15 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 }, /* pm8150l has 12 GPIOs with holes on 7 */ { .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 }, + { .compatible = "qcom,pm8350-gpio", .data = (void *) 10 }, + { .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 }, + { .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 }, + { .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 }, { .compatible = "qcom,pm6150-gpio", .data = (void *) 10 }, { .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 }, + { .compatible = "qcom,pm8008-gpio", .data = (void *) 2 }, /* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */ { .compatible = "qcom,pmx55-gpio", .data = (void *) 11 }, { }, diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index 2bfd3006f6fd..5ccc49b387f1 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -394,26 +394,6 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) return 0; } -const struct pinmux_bias_reg * -sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, - unsigned int *bit) -{ - unsigned int i, j; - - for (i = 0; pfc->info->bias_regs[i].puen; i++) { - for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) { - if (pfc->info->bias_regs[i].pins[j] == pin) { - *bit = j; - return &pfc->info->bias_regs[i]; - } - } - } - - WARN_ONCE(1, "Pin %u is not in bias info list\n", pin); - - return NULL; -} - static int sh_pfc_init_ranges(struct sh_pfc *pfc) { struct sh_pfc_pin_range *range; diff --git a/drivers/pinctrl/renesas/core.h b/drivers/pinctrl/renesas/core.h index 5ca7e0830ae9..51f391e9713a 100644 --- a/drivers/pinctrl/renesas/core.h +++ b/drivers/pinctrl/renesas/core.h @@ -29,12 +29,4 @@ void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data); int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin); int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); -const struct pinmux_bias_reg * -sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, - unsigned int *bit); - -unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin); -void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias); - #endif /* __SH_PFC_CORE_H__ */ diff --git a/drivers/pinctrl/renesas/pfc-r8a73a4.c b/drivers/pinctrl/renesas/pfc-r8a73a4.c index b21f5afe610f..b26ff9d6ead4 100644 --- a/drivers/pinctrl/renesas/pfc-r8a73a4.c +++ b/drivers/pinctrl/renesas/pfc-r8a73a4.c @@ -2649,59 +2649,21 @@ static const struct pinmux_irq pinmux_irqs[] = { PINMUX_IRQ(329), /* IRQ57 */ }; -#define PORTCR_PULMD_OFF (0 << 6) -#define PORTCR_PULMD_DOWN (2 << 6) -#define PORTCR_PULMD_UP (3 << 6) -#define PORTCR_PULMD_MASK (3 << 6) - static const unsigned int r8a73a4_portcr_offsets[] = { 0x00000000, 0x00001000, 0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000, 0x00002000, 0x00002000, 0x00003000, 0x00003000, }; -static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) -{ - void __iomem *addr; - - addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin; - - switch (ioread8(addr) & PORTCR_PULMD_MASK) { - case PORTCR_PULMD_UP: - return PIN_CONFIG_BIAS_PULL_UP; - case PORTCR_PULMD_DOWN: - return PIN_CONFIG_BIAS_PULL_DOWN; - case PORTCR_PULMD_OFF: - default: - return PIN_CONFIG_BIAS_DISABLE; - } -} - -static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) +static void __iomem *r8a73a4_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin) { - void __iomem *addr; - u32 value; - - addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin; - value = ioread8(addr) & ~PORTCR_PULMD_MASK; - - switch (bias) { - case PIN_CONFIG_BIAS_PULL_UP: - value |= PORTCR_PULMD_UP; - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - value |= PORTCR_PULMD_DOWN; - break; - } - - iowrite8(value, addr); + return pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin; } static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = { - .get_bias = r8a73a4_pinmux_get_bias, - .set_bias = r8a73a4_pinmux_set_bias, + .get_bias = rmobile_pinmux_get_bias, + .set_bias = rmobile_pinmux_set_bias, + .pin_to_portcr = r8a73a4_pin_to_portcr, }; const struct sh_pfc_soc_info r8a73a4_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pfc-r8a7740.c b/drivers/pinctrl/renesas/pfc-r8a7740.c index fdf1b0f09f57..4eac3899d69b 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7740.c +++ b/drivers/pinctrl/renesas/pfc-r8a7740.c @@ -3672,11 +3672,6 @@ static const struct pinmux_irq pinmux_irqs[] = { PINMUX_IRQ(41, 167), /* IRQ31A */ }; -#define PORTnCR_PULMD_OFF (0 << 6) -#define PORTnCR_PULMD_DOWN (2 << 6) -#define PORTnCR_PULMD_UP (3 << 6) -#define PORTnCR_PULMD_MASK (3 << 6) - struct r8a7740_portcr_group { unsigned int end_pin; unsigned int offset; @@ -3686,7 +3681,7 @@ static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = { { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 }, }; -static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin) +static void __iomem *r8a7740_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin) { unsigned int i; @@ -3701,43 +3696,10 @@ static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin) return NULL; } -static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) -{ - void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin); - u32 value = ioread8(addr) & PORTnCR_PULMD_MASK; - - switch (value) { - case PORTnCR_PULMD_UP: - return PIN_CONFIG_BIAS_PULL_UP; - case PORTnCR_PULMD_DOWN: - return PIN_CONFIG_BIAS_PULL_DOWN; - case PORTnCR_PULMD_OFF: - default: - return PIN_CONFIG_BIAS_DISABLE; - } -} - -static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin); - u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK; - - switch (bias) { - case PIN_CONFIG_BIAS_PULL_UP: - value |= PORTnCR_PULMD_UP; - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - value |= PORTnCR_PULMD_DOWN; - break; - } - - iowrite8(value, addr); -} - static const struct sh_pfc_soc_operations r8a7740_pfc_ops = { - .get_bias = r8a7740_pinmux_get_bias, - .set_bias = r8a7740_pinmux_set_bias, + .get_bias = rmobile_pinmux_get_bias, + .set_bias = rmobile_pinmux_set_bias, + .pin_to_portcr = r8a7740_pin_to_portcr, }; const struct sh_pfc_soc_info r8a7740_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pfc-r8a7778.c b/drivers/pinctrl/renesas/pfc-r8a7778.c index 75f52b1798c3..6185af9c4990 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7778.c +++ b/drivers/pinctrl/renesas/pfc-r8a7778.c @@ -16,7 +16,6 @@ #include <linux/kernel.h> #include <linux/pinctrl/pinconf-generic.h> -#include "core.h" #include "sh_pfc.h" #define PORT_GP_PUP_1(bank, pin, fn, sfx) \ diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c index 6fce9fe2e98f..fe4ccab6b0b8 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7791.c +++ b/drivers/pinctrl/renesas/pfc-r8a7791.c @@ -16,22 +16,50 @@ * which case they support both 3.3V and 1.8V signalling. */ #define CPU_ALL_GP(fn, sfx) \ - PORT_GP_32(0, fn, sfx), \ - PORT_GP_26(1, fn, sfx), \ - PORT_GP_32(2, fn, sfx), \ - PORT_GP_32(3, fn, sfx), \ - PORT_GP_32(4, fn, sfx), \ - PORT_GP_32(5, fn, sfx), \ - PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_1(6, 24, fn, sfx), \ - PORT_GP_1(6, 25, fn, sfx), \ - PORT_GP_1(6, 26, fn, sfx), \ - PORT_GP_1(6, 27, fn, sfx), \ - PORT_GP_1(6, 28, fn, sfx), \ - PORT_GP_1(6, 29, fn, sfx), \ - PORT_GP_1(6, 30, fn, sfx), \ - PORT_GP_1(6, 31, fn, sfx), \ - PORT_GP_26(7, fn, sfx) + PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 26, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 27, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 30, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 31, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_7(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_1(7, 7, fn, sfx), \ + PORT_GP_1(7, 8, fn, sfx), \ + PORT_GP_1(7, 9, fn, sfx), \ + PORT_GP_CFG_1(7, 10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 13, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 14, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 15, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 16, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 17, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 18, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 19, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ + PIN_NOGP_CFG(AVS1, "AVS1", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(AVS2, "AVS2", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) enum { PINMUX_RESERVED = 0, @@ -1696,8 +1724,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1), }; +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; + static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), + PINMUX_NOGP_ALL(), }; #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) @@ -6645,8 +6682,322 @@ static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc return 31 - (pin & 0x1f); } +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) { + [ 0] = RCAR_GP_PIN(1, 4), /* A20 */ + [ 1] = RCAR_GP_PIN(1, 5), /* A21 */ + [ 2] = RCAR_GP_PIN(1, 6), /* A22 */ + [ 3] = RCAR_GP_PIN(1, 7), /* A23 */ + [ 4] = RCAR_GP_PIN(1, 8), /* A24 */ + [ 5] = RCAR_GP_PIN(6, 31), /* DU0_DOTCLKIN */ + [ 6] = RCAR_GP_PIN(0, 0), /* D0 */ + [ 7] = RCAR_GP_PIN(0, 1), /* D1 */ + [ 8] = RCAR_GP_PIN(0, 2), /* D2 */ + [ 9] = RCAR_GP_PIN(0, 3), /* D3 */ + [10] = RCAR_GP_PIN(0, 4), /* D4 */ + [11] = RCAR_GP_PIN(0, 5), /* D5 */ + [12] = RCAR_GP_PIN(0, 6), /* D6 */ + [13] = RCAR_GP_PIN(0, 7), /* D7 */ + [14] = RCAR_GP_PIN(0, 8), /* D8 */ + [15] = RCAR_GP_PIN(0, 9), /* D9 */ + [16] = RCAR_GP_PIN(0, 10), /* D10 */ + [17] = RCAR_GP_PIN(0, 11), /* D11 */ + [18] = RCAR_GP_PIN(0, 12), /* D12 */ + [19] = RCAR_GP_PIN(0, 13), /* D13 */ + [20] = RCAR_GP_PIN(0, 14), /* D14 */ + [21] = RCAR_GP_PIN(0, 15), /* D15 */ + [22] = RCAR_GP_PIN(0, 16), /* A0 */ + [23] = RCAR_GP_PIN(0, 17), /* A1 */ + [24] = RCAR_GP_PIN(0, 18), /* A2 */ + [25] = RCAR_GP_PIN(0, 19), /* A3 */ + [26] = RCAR_GP_PIN(0, 20), /* A4 */ + [27] = RCAR_GP_PIN(0, 21), /* A5 */ + [28] = RCAR_GP_PIN(0, 22), /* A6 */ + [29] = RCAR_GP_PIN(0, 23), /* A7 */ + [30] = RCAR_GP_PIN(0, 24), /* A8 */ + [31] = RCAR_GP_PIN(0, 25), /* A9 */ + } }, + { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) { + [ 0] = RCAR_GP_PIN(0, 26), /* A10 */ + [ 1] = RCAR_GP_PIN(0, 27), /* A11 */ + [ 2] = RCAR_GP_PIN(0, 28), /* A12 */ + [ 3] = RCAR_GP_PIN(0, 29), /* A13 */ + [ 4] = RCAR_GP_PIN(0, 30), /* A14 */ + [ 5] = RCAR_GP_PIN(0, 31), /* A15 */ + [ 6] = RCAR_GP_PIN(1, 0), /* A16 */ + [ 7] = RCAR_GP_PIN(1, 1), /* A17 */ + [ 8] = RCAR_GP_PIN(1, 2), /* A18 */ + [ 9] = RCAR_GP_PIN(1, 3), /* A19 */ + [10] = PIN_TRST_N, /* TRST# */ + [11] = PIN_TCK, /* TCK */ + [12] = PIN_TMS, /* TMS */ + [13] = PIN_TDI, /* TDI */ + [14] = RCAR_GP_PIN(1, 11), /* CS1#/A26 */ + [15] = RCAR_GP_PIN(1, 12), /* EX_CS0# */ + [16] = RCAR_GP_PIN(1, 13), /* EX_CS1# */ + [17] = RCAR_GP_PIN(1, 14), /* EX_CS2# */ + [18] = RCAR_GP_PIN(1, 15), /* EX_CS3# */ + [19] = RCAR_GP_PIN(1, 16), /* EX_CS4# */ + [20] = RCAR_GP_PIN(1, 17), /* EX_CS5# */ + [21] = RCAR_GP_PIN(1, 18), /* BS# */ + [22] = RCAR_GP_PIN(1, 19), /* RD# */ + [23] = RCAR_GP_PIN(1, 20), /* RD/WR# */ + [24] = RCAR_GP_PIN(1, 21), /* WE0# */ + [25] = RCAR_GP_PIN(1, 22), /* WE1# */ + [26] = RCAR_GP_PIN(1, 23), /* EX_WAIT0 */ + [27] = RCAR_GP_PIN(1, 24), /* DREQ0 */ + [28] = RCAR_GP_PIN(1, 25), /* DACK0 */ + [29] = RCAR_GP_PIN(5, 31), /* SPEEDIN */ + [30] = RCAR_GP_PIN(2, 0), /* SSI_SCK0129 */ + [31] = RCAR_GP_PIN(2, 1), /* SSI_WS0129 */ + } }, + { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) { + [ 0] = RCAR_GP_PIN(2, 2), /* SSI_SDATA0 */ + [ 1] = RCAR_GP_PIN(2, 3), /* SSI_SCK1 */ + [ 2] = RCAR_GP_PIN(2, 4), /* SSI_WS1 */ + [ 3] = RCAR_GP_PIN(2, 5), /* SSI_SDATA1 */ + [ 4] = RCAR_GP_PIN(2, 6), /* SSI_SCK2 */ + [ 5] = RCAR_GP_PIN(2, 7), /* SSI_WS2 */ + [ 6] = RCAR_GP_PIN(2, 8), /* SSI_SDATA2 */ + [ 7] = RCAR_GP_PIN(2, 9), /* SSI_SCK34 */ + [ 8] = RCAR_GP_PIN(2, 10), /* SSI_WS34 */ + [ 9] = RCAR_GP_PIN(2, 11), /* SSI_SDATA3 */ + [10] = RCAR_GP_PIN(2, 12), /* SSI_SCK4 */ + [11] = RCAR_GP_PIN(2, 13), /* SSI_WS4 */ + [12] = RCAR_GP_PIN(2, 14), /* SSI_SDATA4 */ + [13] = RCAR_GP_PIN(2, 15), /* SSI_SCK5 */ + [14] = RCAR_GP_PIN(2, 16), /* SSI_WS5 */ + [15] = RCAR_GP_PIN(2, 17), /* SSI_SDATA5 */ + [16] = RCAR_GP_PIN(2, 18), /* SSI_SCK6 */ + [17] = RCAR_GP_PIN(2, 19), /* SSI_WS6 */ + [18] = RCAR_GP_PIN(2, 20), /* SSI_SDATA6 */ + [19] = RCAR_GP_PIN(2, 21), /* SSI_SCK78 */ + [20] = RCAR_GP_PIN(2, 22), /* SSI_WS78 */ + [21] = RCAR_GP_PIN(2, 23), /* SSI_SDATA7 */ + [22] = RCAR_GP_PIN(2, 24), /* SSI_SDATA8 */ + [23] = RCAR_GP_PIN(2, 25), /* SSI_SCK9 */ + [24] = RCAR_GP_PIN(2, 26), /* SSI_WS9 */ + [25] = RCAR_GP_PIN(2, 27), /* SSI_SDATA9 */ + [26] = RCAR_GP_PIN(2, 28), /* AUDIO_CLKA */ + [27] = RCAR_GP_PIN(2, 29), /* AUDIO_CLKB */ + [28] = RCAR_GP_PIN(2, 30), /* AUDIO_CLKC */ + [29] = RCAR_GP_PIN(2, 31), /* AUDIO_CLKOUT */ + [30] = RCAR_GP_PIN(7, 10), /* IRQ0 */ + [31] = RCAR_GP_PIN(7, 11), /* IRQ1 */ + } }, + { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) { + [ 0] = RCAR_GP_PIN(7, 12), /* IRQ2 */ + [ 1] = RCAR_GP_PIN(7, 13), /* IRQ3 */ + [ 2] = RCAR_GP_PIN(7, 14), /* IRQ4 */ + [ 3] = RCAR_GP_PIN(7, 15), /* IRQ5 */ + [ 4] = RCAR_GP_PIN(7, 16), /* IRQ6 */ + [ 5] = RCAR_GP_PIN(7, 17), /* IRQ7 */ + [ 6] = RCAR_GP_PIN(7, 18), /* IRQ8 */ + [ 7] = RCAR_GP_PIN(7, 19), /* IRQ9 */ + [ 8] = RCAR_GP_PIN(3, 0), /* DU1_DR0 */ + [ 9] = RCAR_GP_PIN(3, 1), /* DU1_DR1 */ + [10] = RCAR_GP_PIN(3, 2), /* DU1_DR2 */ + [11] = RCAR_GP_PIN(3, 3), /* DU1_DR3 */ + [12] = RCAR_GP_PIN(3, 4), /* DU1_DR4 */ + [13] = RCAR_GP_PIN(3, 5), /* DU1_DR5 */ + [14] = RCAR_GP_PIN(3, 6), /* DU1_DR6 */ + [15] = RCAR_GP_PIN(3, 7), /* DU1_DR7 */ + [16] = RCAR_GP_PIN(3, 8), /* DU1_DG0 */ + [17] = RCAR_GP_PIN(3, 9), /* DU1_DG1 */ + [18] = RCAR_GP_PIN(3, 10), /* DU1_DG2 */ + [19] = RCAR_GP_PIN(3, 11), /* DU1_DG3 */ + [20] = RCAR_GP_PIN(3, 12), /* DU1_DG4 */ + [21] = RCAR_GP_PIN(3, 13), /* DU1_DG5 */ + [22] = RCAR_GP_PIN(3, 14), /* DU1_DG6 */ + [23] = RCAR_GP_PIN(3, 15), /* DU1_DG7 */ + [24] = RCAR_GP_PIN(3, 16), /* DU1_DB0 */ + [25] = RCAR_GP_PIN(3, 17), /* DU1_DB1 */ + [26] = RCAR_GP_PIN(3, 18), /* DU1_DB2 */ + [27] = RCAR_GP_PIN(3, 19), /* DU1_DB3 */ + [28] = RCAR_GP_PIN(3, 20), /* DU1_DB4 */ + [29] = RCAR_GP_PIN(3, 21), /* DU1_DB5 */ + [30] = RCAR_GP_PIN(3, 22), /* DU1_DB6 */ + [31] = RCAR_GP_PIN(3, 23), /* DU1_DB7 */ + } }, + { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) { + [ 0] = RCAR_GP_PIN(3, 24), /* DU1_DOTCLKIN */ + [ 1] = RCAR_GP_PIN(3, 25), /* DU1_DOTCLKOUT0 */ + [ 2] = RCAR_GP_PIN(3, 26), /* DU1_DOTCLKOUT1 */ + [ 3] = RCAR_GP_PIN(3, 27), /* DU1_EXHSYNC_DU1_HSYNC */ + [ 4] = RCAR_GP_PIN(3, 28), /* DU1_EXVSYNC_DU1_VSYNC */ + [ 5] = RCAR_GP_PIN(3, 29), /* DU1_EXODDF_DU1_ODDF_DISP_CDE */ + [ 6] = RCAR_GP_PIN(3, 30), /* DU1_DISP */ + [ 7] = RCAR_GP_PIN(3, 31), /* DU1_CDE */ + [ 8] = RCAR_GP_PIN(4, 0), /* VI0_CLK */ + [ 9] = RCAR_GP_PIN(4, 1), /* VI0_CLKENB */ + [10] = RCAR_GP_PIN(4, 2), /* VI0_FIELD */ + [11] = RCAR_GP_PIN(4, 3), /* VI0_HSYNC# */ + [12] = RCAR_GP_PIN(4, 4), /* VI0_VSYNC# */ + [13] = RCAR_GP_PIN(4, 5), /* VI0_DATA0_VI0_B0 */ + [14] = RCAR_GP_PIN(4, 6), /* VI0_DATA1_VI0_B1 */ + [15] = RCAR_GP_PIN(4, 7), /* VI0_DATA2_VI0_B2 */ + [16] = RCAR_GP_PIN(4, 8), /* VI0_DATA3_VI0_B3 */ + [17] = RCAR_GP_PIN(4, 9), /* VI0_DATA4_VI0_B4 */ + [18] = RCAR_GP_PIN(4, 10), /* VI0_DATA5_VI0_B5 */ + [19] = RCAR_GP_PIN(4, 11), /* VI0_DATA6_VI0_B6 */ + [20] = RCAR_GP_PIN(4, 12), /* VI0_DATA7_VI0_B7 */ + [21] = RCAR_GP_PIN(4, 13), /* VI0_G0 */ + [22] = RCAR_GP_PIN(4, 14), /* VI0_G1 */ + [23] = RCAR_GP_PIN(4, 15), /* VI0_G2 */ + [24] = RCAR_GP_PIN(4, 16), /* VI0_G3 */ + [25] = RCAR_GP_PIN(4, 17), /* VI0_G4 */ + [26] = RCAR_GP_PIN(4, 18), /* VI0_G5 */ + [27] = RCAR_GP_PIN(4, 19), /* VI0_G6 */ + [28] = RCAR_GP_PIN(4, 20), /* VI0_G7 */ + [29] = RCAR_GP_PIN(4, 21), /* VI0_R0 */ + [30] = RCAR_GP_PIN(4, 22), /* VI0_R1 */ + [31] = RCAR_GP_PIN(4, 23), /* VI0_R2 */ + } }, + { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) { + [ 0] = RCAR_GP_PIN(4, 24), /* VI0_R3 */ + [ 1] = RCAR_GP_PIN(4, 25), /* VI0_R4 */ + [ 2] = RCAR_GP_PIN(4, 26), /* VI0_R5 */ + [ 3] = RCAR_GP_PIN(4, 27), /* VI0_R6 */ + [ 4] = RCAR_GP_PIN(4, 28), /* VI0_R7 */ + [ 5] = RCAR_GP_PIN(5, 0), /* VI1_HSYNC# */ + [ 6] = RCAR_GP_PIN(5, 1), /* VI1_VSYNC# */ + [ 7] = RCAR_GP_PIN(5, 2), /* VI1_CLKENB */ + [ 8] = RCAR_GP_PIN(5, 3), /* VI1_FIELD */ + [ 9] = RCAR_GP_PIN(5, 4), /* VI1_CLK */ + [10] = RCAR_GP_PIN(5, 5), /* VI1_DATA0 */ + [11] = RCAR_GP_PIN(5, 6), /* VI1_DATA1 */ + [12] = RCAR_GP_PIN(5, 7), /* VI1_DATA2 */ + [13] = RCAR_GP_PIN(5, 8), /* VI1_DATA3 */ + [14] = RCAR_GP_PIN(5, 9), /* VI1_DATA4 */ + [15] = RCAR_GP_PIN(5, 10), /* VI1_DATA5 */ + [16] = RCAR_GP_PIN(5, 11), /* VI1_DATA6 */ + [17] = RCAR_GP_PIN(5, 12), /* VI1_DATA7 */ + [18] = RCAR_GP_PIN(5, 13), /* ETH_MDIO */ + [19] = RCAR_GP_PIN(5, 14), /* ETH_CRS_DV */ + [20] = RCAR_GP_PIN(5, 15), /* ETH_RX_ER */ + [21] = RCAR_GP_PIN(5, 16), /* ETH_RXD0 */ + [22] = RCAR_GP_PIN(5, 17), /* ETH_RXD1 */ + [23] = RCAR_GP_PIN(5, 18), /* ETH_LINK */ + [24] = RCAR_GP_PIN(5, 19), /* ETH_REFCLK */ + [25] = RCAR_GP_PIN(5, 20), /* ETH_TXD1 */ + [26] = RCAR_GP_PIN(5, 21), /* ETH_TX_EN */ + [27] = RCAR_GP_PIN(5, 22), /* ETH_MAGIC */ + [28] = RCAR_GP_PIN(5, 23), /* ETH_TXD0 */ + [29] = RCAR_GP_PIN(5, 24), /* ETH_MDC */ + [30] = RCAR_GP_PIN(5, 25), /* STP_IVCXO27_0 */ + [31] = RCAR_GP_PIN(5, 26), /* STP_ISCLK_0 */ + } }, + { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) { + [ 0] = RCAR_GP_PIN(5, 27), /* STP_ISD_0 */ + [ 1] = RCAR_GP_PIN(5, 28), /* STP_ISEN_0 */ + [ 2] = RCAR_GP_PIN(5, 29), /* STP_ISSYNC_0 */ + [ 3] = RCAR_GP_PIN(5, 30), /* STP_OPWM_0 */ + [ 4] = RCAR_GP_PIN(6, 0), /* SD0_CLK */ + [ 5] = RCAR_GP_PIN(6, 1), /* SD0_CMD */ + [ 6] = RCAR_GP_PIN(6, 2), /* SD0_DATA0 */ + [ 7] = RCAR_GP_PIN(6, 3), /* SD0_DATA1 */ + [ 8] = RCAR_GP_PIN(6, 4), /* SD0_DATA2 */ + [ 9] = RCAR_GP_PIN(6, 5), /* SD0_DATA3 */ + [10] = RCAR_GP_PIN(6, 6), /* SD0_CD */ + [11] = RCAR_GP_PIN(6, 7), /* SD0_WP */ + [12] = RCAR_GP_PIN(6, 8), /* SD2_CLK */ + [13] = RCAR_GP_PIN(6, 9), /* SD2_CMD */ + [14] = RCAR_GP_PIN(6, 10), /* SD2_DATA0 */ + [15] = RCAR_GP_PIN(6, 11), /* SD2_DATA1 */ + [16] = RCAR_GP_PIN(6, 12), /* SD2_DATA2 */ + [17] = RCAR_GP_PIN(6, 13), /* SD2_DATA3 */ + [18] = RCAR_GP_PIN(6, 14), /* SD2_CD */ + [19] = RCAR_GP_PIN(6, 15), /* SD2_WP */ + [20] = RCAR_GP_PIN(6, 16), /* SD3_CLK */ + [21] = RCAR_GP_PIN(6, 17), /* SD3_CMD */ + [22] = RCAR_GP_PIN(6, 18), /* SD3_DATA0 */ + [23] = RCAR_GP_PIN(6, 19), /* SD3_DATA1 */ + [24] = RCAR_GP_PIN(6, 20), /* SD3_DATA2 */ + [25] = RCAR_GP_PIN(6, 21), /* SD3_DATA3 */ + [26] = RCAR_GP_PIN(6, 22), /* SD3_CD */ + [27] = RCAR_GP_PIN(6, 23), /* SD3_WP */ + [28] = RCAR_GP_PIN(6, 24), /* MSIOF0_SCK */ + [29] = RCAR_GP_PIN(6, 25), /* MSIOF0_SYNC */ + [30] = RCAR_GP_PIN(6, 26), /* MSIOF0_TXD */ + [31] = RCAR_GP_PIN(6, 27), /* MSIOF0_RXD */ + } }, + { PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) { + /* PUPR7 pull-up pins */ + [ 0] = RCAR_GP_PIN(6, 28), /* MSIOF0_SS1 */ + [ 1] = RCAR_GP_PIN(6, 29), /* MSIOF0_SS2 */ + [ 2] = RCAR_GP_PIN(4, 29), /* SIM0_RST */ + [ 3] = RCAR_GP_PIN(4, 30), /* SIM0_CLK */ + [ 4] = RCAR_GP_PIN(4, 31), /* SIM0_D */ + [ 5] = RCAR_GP_PIN(7, 20), /* GPS_CLK */ + [ 6] = RCAR_GP_PIN(7, 21), /* GPS_SIGN */ + [ 7] = RCAR_GP_PIN(7, 22), /* GPS_MAG */ + [ 8] = RCAR_GP_PIN(7, 0), /* HCTS0# */ + [ 9] = RCAR_GP_PIN(7, 1), /* HRTS0# */ + [10] = RCAR_GP_PIN(7, 2), /* HSCK0 */ + [11] = RCAR_GP_PIN(7, 3), /* HRX0 */ + [12] = RCAR_GP_PIN(7, 4), /* HTX0 */ + [13] = RCAR_GP_PIN(7, 5), /* HRX1 */ + [14] = RCAR_GP_PIN(7, 6), /* HTX1 */ + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = RCAR_GP_PIN(1, 9), /* A25 */ + [19] = SH_PFC_PIN_NONE, + [20] = RCAR_GP_PIN(1, 10), /* CS0# */ + [21] = RCAR_GP_PIN(7, 23), /* USB0_PWEN */ + [22] = RCAR_GP_PIN(7, 24), /* USB0_OVC */ + [23] = RCAR_GP_PIN(7, 25), /* USB1_PWEN */ + [24] = RCAR_GP_PIN(6, 30), /* USB1_OVC */ + [25] = PIN_AVS1, /* AVS1 */ + [26] = PIN_AVS2, /* AVS2 */ + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("N/A", 0, "PUPR7", 0xe606011c) { + /* PUPR7 pull-down pins */ + [ 0] = SH_PFC_PIN_NONE, + [ 1] = SH_PFC_PIN_NONE, + [ 2] = SH_PFC_PIN_NONE, + [ 3] = SH_PFC_PIN_NONE, + [ 4] = SH_PFC_PIN_NONE, + [ 5] = SH_PFC_PIN_NONE, + [ 6] = SH_PFC_PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */ + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { /* sentinel */ }, +}; + static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = { .pin_to_pocctrl = r8a7791_pin_to_pocctrl, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; #ifdef CONFIG_PINCTRL_PFC_R8A7743 @@ -6665,6 +7016,7 @@ const struct sh_pfc_soc_info r8a7743_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions.common), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), @@ -6687,6 +7039,7 @@ const struct sh_pfc_soc_info r8a7744_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions.common), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), @@ -6711,6 +7064,7 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = { ARRAY_SIZE(pinmux_functions.automotive), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), @@ -6735,6 +7089,7 @@ const struct sh_pfc_soc_info r8a7793_pinmux_info = { ARRAY_SIZE(pinmux_functions.automotive), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c index 258f82fb31c0..f54a7c81005d 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7792.c +++ b/drivers/pinctrl/renesas/pfc-r8a7792.c @@ -8,7 +8,6 @@ #include <linux/kernel.h> -#include "core.h" #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx) \ diff --git a/drivers/pinctrl/renesas/pfc-r8a77950.c b/drivers/pinctrl/renesas/pfc-r8a77950.c index 32fe8caca70a..ee4ce9349aae 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77950.c +++ b/drivers/pinctrl/renesas/pfc-r8a77950.c @@ -8,7 +8,6 @@ #include <linux/errno.h> #include <linux/kernel.h> -#include "core.h" #include "sh_pfc.h" #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c index bdd605e41303..be4eee070842 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77951.c +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c @@ -9,7 +9,6 @@ #include <linux/kernel.h> #include <linux/sys_soc.h> -#include "core.h" #include "sh_pfc.h" #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) @@ -4126,6 +4125,18 @@ static const union vin_data vin4_data_b_mux = { VI4_DATA22_MARK, VI4_DATA23_MARK, }, }; +static const unsigned int vin4_g8_pins[] = { + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +}; +static const unsigned int vin4_g8_mux[] = { + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, +}; static const unsigned int vin4_sync_pins[] = { /* HSYNC#, VSYNC# */ RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17), @@ -4180,6 +4191,18 @@ static const union vin_data16 vin5_data_mux = { VI5_DATA14_MARK, VI5_DATA15_MARK, }, }; +static const unsigned int vin5_high8_pins[] = { + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +}; +static const unsigned int vin5_high8_mux[] = { + VI5_DATA8_MARK, VI5_DATA9_MARK, + VI5_DATA10_MARK, VI5_DATA11_MARK, + VI5_DATA12_MARK, VI5_DATA13_MARK, + VI5_DATA14_MARK, VI5_DATA15_MARK, +}; static const unsigned int vin5_sync_pins[] = { /* HSYNC#, VSYNC# */ RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), @@ -4210,7 +4233,7 @@ static const unsigned int vin5_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[326]; + struct sh_pfc_pin_group common[328]; #ifdef CONFIG_PINCTRL_PFC_R8A77951 struct sh_pfc_pin_group automotive[30]; #endif @@ -4530,6 +4553,7 @@ static const struct { SH_PFC_PIN_GROUP(vin4_data18_b), VIN_DATA_PIN_GROUP(vin4_data, 20, _b), VIN_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP(vin4_g8), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), @@ -4538,6 +4562,7 @@ static const struct { VIN_DATA_PIN_GROUP(vin5_data, 10), VIN_DATA_PIN_GROUP(vin5_data, 12), VIN_DATA_PIN_GROUP(vin5_data, 16), + SH_PFC_PIN_GROUP(vin5_high8), SH_PFC_PIN_GROUP(vin5_sync), SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), @@ -5097,6 +5122,7 @@ static const char * const vin4_groups[] = { "vin4_data18_b", "vin4_data20_b", "vin4_data24_b", + "vin4_g8", "vin4_sync", "vin4_field", "vin4_clkenb", @@ -5108,6 +5134,7 @@ static const char * const vin5_groups[] = { "vin5_data10", "vin5_data12", "vin5_data16", + "vin5_high8", "vin5_sync", "vin5_field", "vin5_clkenb", diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index 96b5b1509bb7..44e9d2eea484 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -14,7 +14,6 @@ #include <linux/errno.h> #include <linux/kernel.h> -#include "core.h" #include "sh_pfc.h" #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) @@ -4100,6 +4099,18 @@ static const union vin_data vin4_data_b_mux = { VI4_DATA22_MARK, VI4_DATA23_MARK, }, }; +static const unsigned int vin4_g8_pins[] = { + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +}; +static const unsigned int vin4_g8_mux[] = { + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, +}; static const unsigned int vin4_sync_pins[] = { /* HSYNC#, VSYNC# */ RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17), @@ -4154,6 +4165,18 @@ static const union vin_data16 vin5_data_mux = { VI5_DATA14_MARK, VI5_DATA15_MARK, }, }; +static const unsigned int vin5_high8_pins[] = { + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +}; +static const unsigned int vin5_high8_mux[] = { + VI5_DATA8_MARK, VI5_DATA9_MARK, + VI5_DATA10_MARK, VI5_DATA11_MARK, + VI5_DATA12_MARK, VI5_DATA13_MARK, + VI5_DATA14_MARK, VI5_DATA15_MARK, +}; static const unsigned int vin5_sync_pins[] = { /* HSYNC#, VSYNC# */ RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), @@ -4184,7 +4207,7 @@ static const unsigned int vin5_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[322]; + struct sh_pfc_pin_group common[324]; #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) struct sh_pfc_pin_group automotive[30]; #endif @@ -4500,6 +4523,7 @@ static const struct { SH_PFC_PIN_GROUP(vin4_data18_b), VIN_DATA_PIN_GROUP(vin4_data, 20, _b), VIN_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP(vin4_g8), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), @@ -4508,6 +4532,7 @@ static const struct { VIN_DATA_PIN_GROUP(vin5_data, 10), VIN_DATA_PIN_GROUP(vin5_data, 12), VIN_DATA_PIN_GROUP(vin5_data, 16), + SH_PFC_PIN_GROUP(vin5_high8), SH_PFC_PIN_GROUP(vin5_sync), SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), @@ -5054,6 +5079,7 @@ static const char * const vin4_groups[] = { "vin4_data18_b", "vin4_data20_b", "vin4_data24_b", + "vin4_g8", "vin4_sync", "vin4_field", "vin4_clkenb", @@ -5065,6 +5091,7 @@ static const char * const vin5_groups[] = { "vin5_data10", "vin5_data12", "vin5_data16", + "vin5_high8", "vin5_sync", "vin5_field", "vin5_clkenb", diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index f15e29383d9b..e69210cc6148 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -15,7 +15,6 @@ #include <linux/errno.h> #include <linux/kernel.h> -#include "core.h" #include "sh_pfc.h" #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) @@ -4337,6 +4336,20 @@ static const union vin_data vin4_data_b_mux = { }, }; +static const unsigned int vin4_g8_pins[] = { + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +}; + +static const unsigned int vin4_g8_mux[] = { + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, +}; + static const unsigned int vin4_sync_pins[] = { /* VSYNC_N, HSYNC_N */ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), @@ -4397,6 +4410,20 @@ static const union vin_data16 vin5_data_mux = { }, }; +static const unsigned int vin5_high8_pins[] = { + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +}; + +static const unsigned int vin5_high8_mux[] = { + VI5_DATA8_MARK, VI5_DATA9_MARK, + VI5_DATA10_MARK, VI5_DATA11_MARK, + VI5_DATA12_MARK, VI5_DATA13_MARK, + VI5_DATA14_MARK, VI5_DATA15_MARK, +}; + static const unsigned int vin5_sync_pins[] = { /* VSYNC_N, HSYNC_N */ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10), @@ -4431,7 +4458,7 @@ static const unsigned int vin5_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[324]; + struct sh_pfc_pin_group common[326]; #ifdef CONFIG_PINCTRL_PFC_R8A77965 struct sh_pfc_pin_group automotive[30]; #endif @@ -4749,6 +4776,7 @@ static const struct { SH_PFC_PIN_GROUP(vin4_data18_b), VIN_DATA_PIN_GROUP(vin4_data, 20, _b), VIN_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP(vin4_g8), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), @@ -4757,6 +4785,7 @@ static const struct { VIN_DATA_PIN_GROUP(vin5_data, 10), VIN_DATA_PIN_GROUP(vin5_data, 12), VIN_DATA_PIN_GROUP(vin5_data, 16), + SH_PFC_PIN_GROUP(vin5_high8), SH_PFC_PIN_GROUP(vin5_sync), SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), @@ -5307,6 +5336,7 @@ static const char * const vin4_groups[] = { "vin4_data18_b", "vin4_data20_b", "vin4_data24_b", + "vin4_g8", "vin4_sync", "vin4_field", "vin4_clkenb", @@ -5318,6 +5348,7 @@ static const char * const vin5_groups[] = { "vin5_data10", "vin5_data12", "vin5_data16", + "vin5_high8", "vin5_sync", "vin5_field", "vin5_clkenb", diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c index e8a0fc468eb2..7935826cfae7 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77970.c +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c @@ -16,7 +16,6 @@ #include <linux/io.h> #include <linux/kernel.h> -#include "core.h" #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx) \ diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c index ebd07bebaeeb..20cff93a2a13 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77980.c +++ b/drivers/pinctrl/renesas/pfc-r8a77980.c @@ -16,7 +16,6 @@ #include <linux/io.h> #include <linux/kernel.h> -#include "core.h" #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx) \ diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index 0a32e3c317c1..d040eb3e305d 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -14,7 +14,6 @@ #include <linux/errno.h> #include <linux/kernel.h> -#include "core.h" #include "sh_pfc.h" #define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN) @@ -3697,6 +3696,20 @@ static const union vin_data vin4_data_b_mux = { }, }; +static const unsigned int vin4_g8_pins[] = { + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), +}; + +static const unsigned int vin4_g8_mux[] = { + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, +}; + static const unsigned int vin4_sync_pins[] = { /* HSYNC, VSYNC */ RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24), @@ -3771,6 +3784,20 @@ static const unsigned int vin5_data8_b_mux[] = { VI5_DATA6_B_MARK, VI5_DATA7_B_MARK, }; +static const unsigned int vin5_high8_pins[] = { + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), +}; + +static const unsigned int vin5_high8_mux[] = { + VI5_DATA8_A_MARK, VI5_DATA9_A_MARK, + VI5_DATA10_A_MARK, VI5_DATA11_A_MARK, + VI5_DATA12_A_MARK, VI5_DATA13_A_MARK, + VI5_DATA14_A_MARK, VI5_DATA15_A_MARK, +}; + static const unsigned int vin5_sync_a_pins[] = { /* HSYNC_N, VSYNC_N */ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9), @@ -3813,7 +3840,7 @@ static const unsigned int vin5_clk_b_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[253]; + struct sh_pfc_pin_group common[255]; #ifdef CONFIG_PINCTRL_PFC_R8A77990 struct sh_pfc_pin_group automotive[21]; #endif @@ -4058,6 +4085,7 @@ static const struct { SH_PFC_PIN_GROUP(vin4_data18_b), VIN_DATA_PIN_GROUP(vin4_data, 20, _b), VIN_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP(vin4_g8), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), @@ -4067,6 +4095,7 @@ static const struct { VIN_DATA_PIN_GROUP(vin5_data, 12, _a), VIN_DATA_PIN_GROUP(vin5_data, 16, _a), SH_PFC_PIN_GROUP(vin5_data8_b), + SH_PFC_PIN_GROUP(vin5_high8), SH_PFC_PIN_GROUP(vin5_sync_a), SH_PFC_PIN_GROUP(vin5_field_a), SH_PFC_PIN_GROUP(vin5_clkenb_a), @@ -4516,6 +4545,7 @@ static const char * const vin4_groups[] = { "vin4_data18_b", "vin4_data20_b", "vin4_data24_b", + "vin4_g8", "vin4_sync", "vin4_field", "vin4_clkenb", @@ -4528,6 +4558,7 @@ static const char * const vin5_groups[] = { "vin5_data12_a", "vin5_data16_a", "vin5_data8_b", + "vin5_high8", "vin5_sync_a", "vin5_field_a", "vin5_clkenb_a", diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c index 672251d86c2d..b479f87a3b23 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77995.c +++ b/drivers/pinctrl/renesas/pfc-r8a77995.c @@ -14,7 +14,6 @@ #include <linux/errno.h> #include <linux/kernel.h> -#include "core.h" #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx) \ diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c index 2250ccd0470a..ad6532443a78 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779a0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c @@ -11,7 +11,6 @@ #include <linux/io.h> #include <linux/kernel.h> -#include "core.h" #include "sh_pfc.h" #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) diff --git a/drivers/pinctrl/renesas/pfc-sh73a0.c b/drivers/pinctrl/renesas/pfc-sh73a0.c index 96b91e95b1e1..ed6db809e80d 100644 --- a/drivers/pinctrl/renesas/pfc-sh73a0.c +++ b/drivers/pinctrl/renesas/pfc-sh73a0.c @@ -13,7 +13,6 @@ #include <linux/regulator/machine.h> #include <linux/slab.h> -#include "core.h" #include "sh_pfc.h" #define CPU_ALL_PORT(fn, pfx, sfx) \ @@ -4310,50 +4309,14 @@ static const struct regulator_init_data sh73a0_vccq_mc0_init_data = { * Pin bias */ -#define PORTnCR_PULMD_OFF (0 << 6) -#define PORTnCR_PULMD_DOWN (2 << 6) -#define PORTnCR_PULMD_UP (3 << 6) -#define PORTnCR_PULMD_MASK (3 << 6) - static const unsigned int sh73a0_portcr_offsets[] = { 0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000, 0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000, }; -static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) +static void __iomem *sh73a0_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin) { - void __iomem *addr = pfc->windows->virt - + sh73a0_portcr_offsets[pin >> 5] + pin; - u32 value = ioread8(addr) & PORTnCR_PULMD_MASK; - - switch (value) { - case PORTnCR_PULMD_UP: - return PIN_CONFIG_BIAS_PULL_UP; - case PORTnCR_PULMD_DOWN: - return PIN_CONFIG_BIAS_PULL_DOWN; - case PORTnCR_PULMD_OFF: - default: - return PIN_CONFIG_BIAS_DISABLE; - } -} - -static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - void __iomem *addr = pfc->windows->virt - + sh73a0_portcr_offsets[pin >> 5] + pin; - u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK; - - switch (bias) { - case PIN_CONFIG_BIAS_PULL_UP: - value |= PORTnCR_PULMD_UP; - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - value |= PORTnCR_PULMD_DOWN; - break; - } - - iowrite8(value, addr); + return pfc->windows->virt + sh73a0_portcr_offsets[pin >> 5] + pin; } /* ----------------------------------------------------------------------------- @@ -4383,8 +4346,9 @@ static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc) static const struct sh_pfc_soc_operations sh73a0_pfc_ops = { .init = sh73a0_pinmux_soc_init, - .get_bias = sh73a0_pinmux_get_bias, - .set_bias = sh73a0_pinmux_set_bias, + .get_bias = rmobile_pinmux_get_bias, + .set_bias = rmobile_pinmux_set_bias, + .pin_to_portcr = sh73a0_pin_to_portcr, }; const struct sh_pfc_soc_info sh73a0_pinmux_info = { diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index a49f74730272..bb488af29862 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -10,6 +10,7 @@ #include <linux/device.h> #include <linux/err.h> #include <linux/init.h> +#include <linux/io.h> #include <linux/module.h> #include <linux/of.h> #include <linux/pinctrl/consumer.h> @@ -840,21 +841,48 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc) return pinctrl_enable(pmx->pctl); } +static const struct pinmux_bias_reg * +rcar_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, + unsigned int *bit) +{ + unsigned int i, j; + + for (i = 0; pfc->info->bias_regs[i].puen || pfc->info->bias_regs[i].pud; i++) { + for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) { + if (pfc->info->bias_regs[i].pins[j] == pin) { + *bit = j; + return &pfc->info->bias_regs[i]; + } + } + } + + WARN_ONCE(1, "Pin %u is not in bias info list\n", pin); + + return NULL; +} + unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) { const struct pinmux_bias_reg *reg; unsigned int bit; - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + reg = rcar_pin_to_bias_reg(pfc, pin, &bit); if (!reg) return PIN_CONFIG_BIAS_DISABLE; - if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) - return PIN_CONFIG_BIAS_DISABLE; - else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit))) - return PIN_CONFIG_BIAS_PULL_UP; - else - return PIN_CONFIG_BIAS_PULL_DOWN; + if (reg->puen) { + if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) + return PIN_CONFIG_BIAS_DISABLE; + else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit))) + return PIN_CONFIG_BIAS_PULL_UP; + else + return PIN_CONFIG_BIAS_PULL_DOWN; + } else { + if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) + return PIN_CONFIG_BIAS_PULL_DOWN; + else + return PIN_CONFIG_BIAS_DISABLE; + } } void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, @@ -864,21 +892,68 @@ void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, u32 enable, updown; unsigned int bit; - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + reg = rcar_pin_to_bias_reg(pfc, pin, &bit); if (!reg) return; - enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); - if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= BIT(bit); + if (reg->puen) { + enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); + if (bias != PIN_CONFIG_BIAS_DISABLE) + enable |= BIT(bit); - if (reg->pud) { - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= BIT(bit); + if (reg->pud) { + updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); + if (bias == PIN_CONFIG_BIAS_PULL_UP) + updown |= BIT(bit); - sh_pfc_write(pfc, reg->pud, updown); + sh_pfc_write(pfc, reg->pud, updown); + } + + sh_pfc_write(pfc, reg->puen, enable); + } else { + enable = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); + if (bias == PIN_CONFIG_BIAS_PULL_DOWN) + enable |= BIT(bit); + + sh_pfc_write(pfc, reg->pud, enable); + } +} + +#define PORTnCR_PULMD_OFF (0 << 6) +#define PORTnCR_PULMD_DOWN (2 << 6) +#define PORTnCR_PULMD_UP (3 << 6) +#define PORTnCR_PULMD_MASK (3 << 6) + +unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) +{ + void __iomem *reg = pfc->info->ops->pin_to_portcr(pfc, pin); + u32 value = ioread8(reg) & PORTnCR_PULMD_MASK; + + switch (value) { + case PORTnCR_PULMD_UP: + return PIN_CONFIG_BIAS_PULL_UP; + case PORTnCR_PULMD_DOWN: + return PIN_CONFIG_BIAS_PULL_DOWN; + case PORTnCR_PULMD_OFF: + default: + return PIN_CONFIG_BIAS_DISABLE; + } +} + +void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + void __iomem *reg = pfc->info->ops->pin_to_portcr(pfc, pin); + u32 value = ioread8(reg) & ~PORTnCR_PULMD_MASK; + + switch (bias) { + case PIN_CONFIG_BIAS_PULL_UP: + value |= PORTnCR_PULMD_UP; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + value |= PORTnCR_PULMD_DOWN; + break; } - sh_pfc_write(pfc, reg->puen, enable); + iowrite8(value, reg); } diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 5934faeb23d7..320898861c4b 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -188,9 +188,9 @@ struct pinmux_drive_reg { .reg = r, \ .fields = -struct pinmux_bias_reg { +struct pinmux_bias_reg { /* At least one of puen/pud must exist */ u32 puen; /* Pull-enable or pull-up control register */ - u32 pud; /* Pull-up/down control register (optional) */ + u32 pud; /* Pull-up/down or pull-down control register */ const u16 pins[32]; }; @@ -273,6 +273,7 @@ struct sh_pfc_soc_operations { void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, unsigned int bias); int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl); + void __iomem * (*pin_to_portcr)(struct sh_pfc *pfc, unsigned int pin); }; struct sh_pfc_soc_info { @@ -478,9 +479,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; PORT_GP_CFG_1(bank, 5, fn, sfx, cfg) #define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0) -#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_7(bank, fn, sfx, cfg) \ PORT_GP_CFG_6(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 6, fn, sfx, cfg) +#define PORT_GP_7(bank, fn, sfx) PORT_GP_CFG_7(bank, fn, sfx, 0) + +#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ + PORT_GP_CFG_7(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 7, fn, sfx, cfg) #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0) @@ -773,4 +778,15 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; */ #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin)) +/* + * Bias helpers + */ +unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin); +void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias); + +unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin); +void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias); + #endif /* __SH_PFC_H */ diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 0cd7f33cdf25..2b99f4130e1e 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -55,7 +55,7 @@ static void exynos_irq_mask(struct irq_data *irqd) struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; - unsigned long mask; + unsigned int mask; unsigned long flags; raw_spin_lock_irqsave(&bank->slock, flags); @@ -83,7 +83,7 @@ static void exynos_irq_unmask(struct irq_data *irqd) struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; - unsigned long mask; + unsigned int mask; unsigned long flags; /* @@ -483,7 +483,7 @@ static void exynos_irq_eint0_15(struct irq_desc *desc) chained_irq_exit(chip, desc); } -static inline void exynos_irq_demux_eint(unsigned long pend, +static inline void exynos_irq_demux_eint(unsigned int pend, struct irq_domain *domain) { unsigned int irq; @@ -500,8 +500,8 @@ static void exynos_irq_demux_eint16_31(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc); - unsigned long pend; - unsigned long mask; + unsigned int pend; + unsigned int mask; int i; chained_irq_enter(chip, desc); diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 7d9bdedcd71b..ad9eb5ed8e81 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -531,6 +531,8 @@ static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, break; } + dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num); + return false; } @@ -545,11 +547,8 @@ static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; (*map)[*num_maps].data.mux.group = grp->name; - if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) { - dev_err(pctl->dev, "invalid function %d on pin %d .\n", - fnum, pin); + if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) return -EINVAL; - } (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; (*num_maps)++; @@ -620,7 +619,6 @@ static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, func = STM32_GET_PIN_FUNC(pinfunc); if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { - dev_err(pctl->dev, "invalid function.\n"); err = -EINVAL; goto exit; } @@ -821,11 +819,8 @@ static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, int pin; ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); - if (!ret) { - dev_err(pctl->dev, "invalid function %d on group %d .\n", - function, group); + if (!ret) return -EINVAL; - } range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); if (!range) { @@ -1542,8 +1537,10 @@ int stm32_pctl_probe(struct platform_device *pdev) if (of_property_read_bool(child, "gpio-controller")) { bank->rstc = of_reset_control_get_exclusive(child, NULL); - if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) + if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) { + of_node_put(child); return -EPROBE_DEFER; + } bank->clk = of_clk_get_by_name(child, NULL); if (IS_ERR(bank->clk)) { @@ -1551,6 +1548,7 @@ int stm32_pctl_probe(struct platform_device *pdev) dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk)); + of_node_put(child); return PTR_ERR(bank->clk); } i++; diff --git a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c index 60a67139ff0a..4e2382778d38 100644 --- a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c +++ b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c @@ -511,8 +511,10 @@ static int ti_iodelay_dt_node_to_map(struct pinctrl_dev *pctldev, } pins = devm_kcalloc(iod->dev, rows, sizeof(*pins), GFP_KERNEL); - if (!pins) + if (!pins) { + error = -ENOMEM; goto free_group; + } cfg = devm_kcalloc(iod->dev, rows, sizeof(*cfg), GFP_KERNEL); if (!cfg) { @@ -867,7 +869,8 @@ static int ti_iodelay_probe(struct platform_device *pdev) goto exit_out; } - if (ti_iodelay_pinconf_init_dev(iod)) + ret = ti_iodelay_pinconf_init_dev(iod); + if (ret) goto exit_out; ret = ti_iodelay_alloc_pins(dev, iod, res->start); diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 6bd22359d411..8e3b78bb2ac2 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -1904,7 +1904,7 @@ static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev, arg = ret; break; - case PIN_CONFIG_LOW_POWER_MODE: + case PIN_CONFIG_MODE_LOW_POWER: ret = tegra_io_pad_is_powered(pmc, pad->id); if (ret < 0) return ret; @@ -1941,7 +1941,7 @@ static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev, arg = pinconf_to_config_argument(configs[i]); switch (param) { - case PIN_CONFIG_LOW_POWER_MODE: + case PIN_CONFIG_MODE_LOW_POWER: if (arg) err = tegra_io_pad_power_disable(pad->id); else |