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Diffstat (limited to 'drivers/video/omap2/dss')
-rw-r--r--drivers/video/omap2/dss/dispc.c16
-rw-r--r--drivers/video/omap2/dss/display.c4
-rw-r--r--drivers/video/omap2/dss/dsi.c463
-rw-r--r--drivers/video/omap2/dss/dss.c6
-rw-r--r--drivers/video/omap2/dss/dss.h11
-rw-r--r--drivers/video/omap2/dss/manager.c204
-rw-r--r--drivers/video/omap2/dss/overlay.c2
-rw-r--r--drivers/video/omap2/dss/rfbi.c2
8 files changed, 372 insertions, 336 deletions
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index e777e352dbcd..5ecdc0004094 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -31,6 +31,7 @@
#include <linux/seq_file.h>
#include <linux/delay.h>
#include <linux/workqueue.h>
+#include <linux/hardirq.h>
#include <plat/sram.h>
#include <plat/clock.h>
@@ -335,7 +336,7 @@ void dispc_save_context(void)
void dispc_restore_context(void)
{
RR(SYSCONFIG);
- RR(IRQENABLE);
+ /*RR(IRQENABLE);*/
/*RR(CONTROL);*/
RR(CONFIG);
RR(DEFAULT_COLOR0);
@@ -472,6 +473,15 @@ void dispc_restore_context(void)
/* enable last, because LCD & DIGIT enable are here */
RR(CONTROL);
+
+ /* clear spurious SYNC_LOST_DIGIT interrupts */
+ dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
+
+ /*
+ * enable last so IRQs won't trigger before
+ * the context is fully restored
+ */
+ RR(IRQENABLE);
}
#undef SR
@@ -3019,7 +3029,7 @@ void dispc_fake_vsync_irq(void)
u32 irqstatus = DISPC_IRQ_VSYNC;
int i;
- local_irq_disable();
+ WARN_ON(!in_interrupt());
for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
struct omap_dispc_isr_data *isr_data;
@@ -3031,8 +3041,6 @@ void dispc_fake_vsync_irq(void)
if (isr_data->mask & irqstatus)
isr_data->isr(isr_data->arg, irqstatus);
}
-
- local_irq_enable();
}
#endif
diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c
index ef8c8529dda2..22dd7a474f79 100644
--- a/drivers/video/omap2/dss/display.c
+++ b/drivers/video/omap2/dss/display.c
@@ -82,6 +82,9 @@ static ssize_t display_upd_mode_store(struct device *dev,
int val, r;
enum omap_dss_update_mode mode;
+ if (!dssdev->driver->set_update_mode)
+ return -EINVAL;
+
val = simple_strtoul(buf, NULL, 10);
switch (val) {
@@ -343,7 +346,6 @@ int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev)
case OMAP_DISPLAY_TYPE_VENC:
case OMAP_DISPLAY_TYPE_SDI:
return 24;
- return 24;
default:
BUG();
}
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index 3af207b2bde3..b3fa3a7db911 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -165,6 +165,14 @@ struct dsi_reg { u16 idx; };
#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
+#define DSI_CIO_IRQ_ERROR_MASK \
+ (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
+ DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
+ DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRCONTROL1 | \
+ DSI_CIO_IRQ_ERRCONTROL2 | DSI_CIO_IRQ_ERRCONTROL3 | \
+ DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
+ DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
+ DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3)
#define DSI_DT_DCS_SHORT_WRITE_0 0x05
#define DSI_DT_DCS_SHORT_WRITE_1 0x15
@@ -232,13 +240,15 @@ static struct
unsigned pll_locked;
struct completion bta_completion;
+ void (*bta_callback)(void);
int update_channel;
struct dsi_update_region update_region;
bool te_enabled;
- struct work_struct framedone_work;
+ struct workqueue_struct *workqueue;
+
void (*framedone_callback)(int, void *);
void *framedone_data;
@@ -509,9 +519,13 @@ void dsi_irq_handler(void)
dss_collect_irq_stats(vcstatus, dsi.irq_stats.vc_irqs[i]);
#endif
- if (vcstatus & DSI_VC_IRQ_BTA)
+ if (vcstatus & DSI_VC_IRQ_BTA) {
complete(&dsi.bta_completion);
+ if (dsi.bta_callback)
+ dsi.bta_callback();
+ }
+
if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
i, vcstatus);
@@ -536,8 +550,12 @@ void dsi_irq_handler(void)
/* flush posted write */
dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
- DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
- print_irq_status_cio(ciostatus);
+ if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
+ DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
+ print_irq_status_cio(ciostatus);
+ } else if (debug_irq) {
+ print_irq_status_cio(ciostatus);
+ }
}
dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
@@ -584,11 +602,8 @@ static void _dsi_initialize_irq(void)
for (i = 0; i < 4; ++i)
dsi_write_reg(DSI_VC_IRQENABLE(i), l);
- /* XXX zonda responds incorrectly, causing control error:
- Exit from LP-ESC mode to LP11 uses wrong transition states on the
- data lines LP0 and LN0. */
- dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,
- -1 & (~DSI_CIO_IRQ_ERRCONTROL2));
+ l = DSI_CIO_IRQ_ERROR_MASK;
+ dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, l);
}
static u32 dsi_get_errors(void)
@@ -1098,6 +1113,7 @@ int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
DSSERR("PLL not coming out of reset.\n");
r = -ENODEV;
+ dispc_pck_free_enable(0);
goto err1;
}
@@ -1740,42 +1756,52 @@ static void dsi_vc_initial_config(int channel)
dsi.vc[channel].mode = DSI_VC_MODE_L4;
}
-static void dsi_vc_config_l4(int channel)
+static int dsi_vc_config_l4(int channel)
{
if (dsi.vc[channel].mode == DSI_VC_MODE_L4)
- return;
+ return 0;
DSSDBGF("%d", channel);
dsi_vc_enable(channel, 0);
- if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
+ /* VC_BUSY */
+ if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
DSSERR("vc(%d) busy when trying to config for L4\n", channel);
+ return -EIO;
+ }
REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
dsi_vc_enable(channel, 1);
dsi.vc[channel].mode = DSI_VC_MODE_L4;
+
+ return 0;
}
-static void dsi_vc_config_vp(int channel)
+static int dsi_vc_config_vp(int channel)
{
if (dsi.vc[channel].mode == DSI_VC_MODE_VP)
- return;
+ return 0;
DSSDBGF("%d", channel);
dsi_vc_enable(channel, 0);
- if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
+ /* VC_BUSY */
+ if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
DSSERR("vc(%d) busy when trying to config for VP\n", channel);
+ return -EIO;
+ }
REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
dsi_vc_enable(channel, 1);
dsi.vc[channel].mode = DSI_VC_MODE_VP;
+
+ return 0;
}
@@ -1854,19 +1880,19 @@ static u16 dsi_vc_flush_receive_data(int channel)
u32 val;
u8 dt;
val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
- DSSDBG("\trawval %#08x\n", val);
+ DSSERR("\trawval %#08x\n", val);
dt = FLD_GET(val, 5, 0);
if (dt == DSI_DT_RX_ACK_WITH_ERR) {
u16 err = FLD_GET(val, 23, 8);
dsi_show_rx_ack_with_err(err);
} else if (dt == DSI_DT_RX_SHORT_READ_1) {
- DSSDBG("\tDCS short response, 1 byte: %#x\n",
+ DSSERR("\tDCS short response, 1 byte: %#x\n",
FLD_GET(val, 23, 8));
} else if (dt == DSI_DT_RX_SHORT_READ_2) {
- DSSDBG("\tDCS short response, 2 byte: %#x\n",
+ DSSERR("\tDCS short response, 2 byte: %#x\n",
FLD_GET(val, 23, 8));
} else if (dt == DSI_DT_RX_DCS_LONG_READ) {
- DSSDBG("\tDCS long response, len %d\n",
+ DSSERR("\tDCS long response, len %d\n",
FLD_GET(val, 23, 8));
dsi_vc_flush_long_data(channel);
} else {
@@ -2087,6 +2113,13 @@ int dsi_vc_dcs_write(int channel, u8 *data, int len)
if (r)
goto err;
+ if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
+ DSSERR("rx fifo not empty after write, dumping data:\n");
+ dsi_vc_flush_receive_data(channel);
+ r = -EIO;
+ goto err;
+ }
+
return 0;
err:
DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n",
@@ -2233,11 +2266,12 @@ int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data)
}
EXPORT_SYMBOL(dsi_vc_dcs_read_1);
-int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u16 *data)
+int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2)
{
+ u8 buf[2];
int r;
- r = dsi_vc_dcs_read(channel, dcs_cmd, (u8 *)data, 2);
+ r = dsi_vc_dcs_read(channel, dcs_cmd, buf, 2);
if (r < 0)
return r;
@@ -2245,231 +2279,122 @@ int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u16 *data)
if (r != 2)
return -EIO;
+ *data1 = buf[0];
+ *data2 = buf[1];
+
return 0;
}
EXPORT_SYMBOL(dsi_vc_dcs_read_2);
int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
{
- int r;
- r = dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
+ return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
len, 0);
-
- if (r)
- return r;
-
- r = dsi_vc_send_bta_sync(channel);
-
- return r;
}
EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
-static void dsi_set_lp_rx_timeout(unsigned long ns)
+static void dsi_set_lp_rx_timeout(unsigned ticks, bool x4, bool x16)
{
- u32 r;
- unsigned x4, x16;
unsigned long fck;
- unsigned long ticks;
+ unsigned long total_ticks;
+ u32 r;
- /* ticks in DSI_FCK */
+ BUG_ON(ticks > 0x1fff);
+ /* ticks in DSI_FCK */
fck = dsi_fclk_rate();
- ticks = (fck / 1000 / 1000) * ns / 1000;
- x4 = 0;
- x16 = 0;
-
- if (ticks > 0x1fff) {
- ticks = (fck / 1000 / 1000) * ns / 1000 / 4;
- x4 = 1;
- x16 = 0;
- }
-
- if (ticks > 0x1fff) {
- ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
- x4 = 0;
- x16 = 1;
- }
-
- if (ticks > 0x1fff) {
- ticks = (fck / 1000 / 1000) * ns / 1000 / (4 * 16);
- x4 = 1;
- x16 = 1;
- }
-
- if (ticks > 0x1fff) {
- DSSWARN("LP_TX_TO over limit, setting it to max\n");
- ticks = 0x1fff;
- x4 = 1;
- x16 = 1;
- }
r = dsi_read_reg(DSI_TIMING2);
r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
- r = FLD_MOD(r, x16, 14, 14); /* LP_RX_TO_X16 */
- r = FLD_MOD(r, x4, 13, 13); /* LP_RX_TO_X4 */
+ r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
+ r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
dsi_write_reg(DSI_TIMING2, r);
- DSSDBG("LP_RX_TO %lu ns (%#lx ticks%s%s)\n",
- (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
- (fck / 1000 / 1000),
- ticks, x4 ? " x4" : "", x16 ? " x16" : "");
+ total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
+
+ DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
+ total_ticks,
+ ticks, x4 ? " x4" : "", x16 ? " x16" : "",
+ (total_ticks * 1000) / (fck / 1000 / 1000));
}
-static void dsi_set_ta_timeout(unsigned long ns)
+static void dsi_set_ta_timeout(unsigned ticks, bool x8, bool x16)
{
- u32 r;
- unsigned x8, x16;
unsigned long fck;
- unsigned long ticks;
+ unsigned long total_ticks;
+ u32 r;
+
+ BUG_ON(ticks > 0x1fff);
/* ticks in DSI_FCK */
fck = dsi_fclk_rate();
- ticks = (fck / 1000 / 1000) * ns / 1000;
- x8 = 0;
- x16 = 0;
-
- if (ticks > 0x1fff) {
- ticks = (fck / 1000 / 1000) * ns / 1000 / 8;
- x8 = 1;
- x16 = 0;
- }
-
- if (ticks > 0x1fff) {
- ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
- x8 = 0;
- x16 = 1;
- }
-
- if (ticks > 0x1fff) {
- ticks = (fck / 1000 / 1000) * ns / 1000 / (8 * 16);
- x8 = 1;
- x16 = 1;
- }
-
- if (ticks > 0x1fff) {
- DSSWARN("TA_TO over limit, setting it to max\n");
- ticks = 0x1fff;
- x8 = 1;
- x16 = 1;
- }
r = dsi_read_reg(DSI_TIMING1);
r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
- r = FLD_MOD(r, x16, 30, 30); /* TA_TO_X16 */
- r = FLD_MOD(r, x8, 29, 29); /* TA_TO_X8 */
+ r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
+ r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
dsi_write_reg(DSI_TIMING1, r);
- DSSDBG("TA_TO %lu ns (%#lx ticks%s%s)\n",
- (ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1) * 1000) /
- (fck / 1000 / 1000),
- ticks, x8 ? " x8" : "", x16 ? " x16" : "");
+ total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
+
+ DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
+ total_ticks,
+ ticks, x8 ? " x8" : "", x16 ? " x16" : "",
+ (total_ticks * 1000) / (fck / 1000 / 1000));
}
-static void dsi_set_stop_state_counter(unsigned long ns)
+static void dsi_set_stop_state_counter(unsigned ticks, bool x4, bool x16)
{
- u32 r;
- unsigned x4, x16;
unsigned long fck;
- unsigned long ticks;
+ unsigned long total_ticks;
+ u32 r;
- /* ticks in DSI_FCK */
+ BUG_ON(ticks > 0x1fff);
+ /* ticks in DSI_FCK */
fck = dsi_fclk_rate();
- ticks = (fck / 1000 / 1000) * ns / 1000;
- x4 = 0;
- x16 = 0;
-
- if (ticks > 0x1fff) {
- ticks = (fck / 1000 / 1000) * ns / 1000 / 4;
- x4 = 1;
- x16 = 0;
- }
-
- if (ticks > 0x1fff) {
- ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
- x4 = 0;
- x16 = 1;
- }
-
- if (ticks > 0x1fff) {
- ticks = (fck / 1000 / 1000) * ns / 1000 / (4 * 16);
- x4 = 1;
- x16 = 1;
- }
-
- if (ticks > 0x1fff) {
- DSSWARN("STOP_STATE_COUNTER_IO over limit, "
- "setting it to max\n");
- ticks = 0x1fff;
- x4 = 1;
- x16 = 1;
- }
r = dsi_read_reg(DSI_TIMING1);
r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
- r = FLD_MOD(r, x16, 14, 14); /* STOP_STATE_X16_IO */
- r = FLD_MOD(r, x4, 13, 13); /* STOP_STATE_X4_IO */
+ r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
+ r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
dsi_write_reg(DSI_TIMING1, r);
- DSSDBG("STOP_STATE_COUNTER %lu ns (%#lx ticks%s%s)\n",
- (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
- (fck / 1000 / 1000),
- ticks, x4 ? " x4" : "", x16 ? " x16" : "");
+ total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
+
+ DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
+ total_ticks,
+ ticks, x4 ? " x4" : "", x16 ? " x16" : "",
+ (total_ticks * 1000) / (fck / 1000 / 1000));
}
-static void dsi_set_hs_tx_timeout(unsigned long ns)
+static void dsi_set_hs_tx_timeout(unsigned ticks, bool x4, bool x16)
{
- u32 r;
- unsigned x4, x16;
unsigned long fck;
- unsigned long ticks;
+ unsigned long total_ticks;
+ u32 r;
- /* ticks in TxByteClkHS */
+ BUG_ON(ticks > 0x1fff);
+ /* ticks in TxByteClkHS */
fck = dsi_get_txbyteclkhs();
- ticks = (fck / 1000 / 1000) * ns / 1000;
- x4 = 0;
- x16 = 0;
-
- if (ticks > 0x1fff) {
- ticks = (fck / 1000 / 1000) * ns / 1000 / 4;
- x4 = 1;
- x16 = 0;
- }
-
- if (ticks > 0x1fff) {
- ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
- x4 = 0;
- x16 = 1;
- }
-
- if (ticks > 0x1fff) {
- ticks = (fck / 1000 / 1000) * ns / 1000 / (4 * 16);
- x4 = 1;
- x16 = 1;
- }
-
- if (ticks > 0x1fff) {
- DSSWARN("HS_TX_TO over limit, setting it to max\n");
- ticks = 0x1fff;
- x4 = 1;
- x16 = 1;
- }
r = dsi_read_reg(DSI_TIMING2);
r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
- r = FLD_MOD(r, x16, 30, 30); /* HS_TX_TO_X16 */
- r = FLD_MOD(r, x4, 29, 29); /* HS_TX_TO_X8 (4 really) */
+ r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
+ r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
dsi_write_reg(DSI_TIMING2, r);
- DSSDBG("HS_TX_TO %lu ns (%#lx ticks%s%s)\n",
- (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
- (fck / 1000 / 1000),
- ticks, x4 ? " x4" : "", x16 ? " x16" : "");
+ total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
+
+ DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
+ total_ticks,
+ ticks, x4 ? " x4" : "", x16 ? " x16" : "",
+ (total_ticks * 1000) / (fck / 1000 / 1000));
}
static int dsi_proto_config(struct omap_dss_device *dssdev)
{
@@ -2487,10 +2412,10 @@ static int dsi_proto_config(struct omap_dss_device *dssdev)
DSI_FIFO_SIZE_32);
/* XXX what values for the timeouts? */
- dsi_set_stop_state_counter(1000);
- dsi_set_ta_timeout(6400000);
- dsi_set_lp_rx_timeout(48000);
- dsi_set_hs_tx_timeout(1000000);
+ dsi_set_stop_state_counter(0x1000, false, false);
+ dsi_set_ta_timeout(0x1fff, true, true);
+ dsi_set_lp_rx_timeout(0x1fff, true, true);
+ dsi_set_hs_tx_timeout(0x1fff, true, true);
switch (dssdev->ctrl.pixel_size) {
case 16:
@@ -2759,6 +2684,7 @@ static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
unsigned packet_payload;
unsigned packet_len;
u32 l;
+ int r;
const unsigned channel = dsi.update_channel;
/* line buffer is 1024 x 24bits */
/* XXX: for some reason using full buffer size causes considerable TX
@@ -2809,8 +2735,9 @@ static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
dsi_perf_mark_start();
- schedule_delayed_work(&dsi.framedone_timeout_work,
+ r = queue_delayed_work(dsi.workqueue, &dsi.framedone_timeout_work,
msecs_to_jiffies(250));
+ BUG_ON(r == 0);
dss_start_update(dssdev);
@@ -2834,62 +2761,70 @@ static void dsi_te_timeout(unsigned long arg)
}
#endif
-static void dsi_framedone_timeout_work_callback(struct work_struct *work)
+static void dsi_handle_framedone(int error)
{
- int r;
const int channel = dsi.update_channel;
- DSSERR("Framedone not received for 250ms!\n");
+ cancel_delayed_work(&dsi.framedone_timeout_work);
+
+ dsi_vc_disable_bta_irq(channel);
/* SIDLEMODE back to smart-idle */
dispc_enable_sidle();
+ dsi.bta_callback = NULL;
+
if (dsi.te_enabled) {
/* enable LP_RX_TO again after the TE */
REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
}
- /* Send BTA after the frame. We need this for the TE to work, as TE
- * trigger is only sent for BTAs without preceding packet. Thus we need
- * to BTA after the pixel packets so that next BTA will cause TE
- * trigger.
- *
- * This is not needed when TE is not in use, but we do it anyway to
- * make sure that the transfer has been completed. It would be more
- * optimal, but more complex, to wait only just before starting next
- * transfer. */
- r = dsi_vc_send_bta_sync(channel);
- if (r)
- DSSERR("BTA after framedone failed\n");
-
/* RX_FIFO_NOT_EMPTY */
if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
DSSERR("Received error during frame transfer:\n");
dsi_vc_flush_receive_data(channel);
+ if (!error)
+ error = -EIO;
}
- dsi.framedone_callback(-ETIMEDOUT, dsi.framedone_data);
+ dsi.framedone_callback(error, dsi.framedone_data);
+
+ if (!error)
+ dsi_perf_show("DISPC");
}
-static void dsi_framedone_irq_callback(void *data, u32 mask)
+static void dsi_framedone_timeout_work_callback(struct work_struct *work)
{
- /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
- * turns itself off. However, DSI still has the pixels in its buffers,
- * and is sending the data.
- */
+ /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
+ * 250ms which would conflict with this timeout work. What should be
+ * done is first cancel the transfer on the HW, and then cancel the
+ * possibly scheduled framedone work. However, cancelling the transfer
+ * on the HW is buggy, and would probably require resetting the whole
+ * DSI */
- /* SIDLEMODE back to smart-idle */
- dispc_enable_sidle();
+ DSSERR("Framedone not received for 250ms!\n");
- schedule_work(&dsi.framedone_work);
+ dsi_handle_framedone(-ETIMEDOUT);
}
-static void dsi_handle_framedone(void)
+static void dsi_framedone_bta_callback(void)
+{
+ dsi_handle_framedone(0);
+
+#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
+ dispc_fake_vsync_irq();
+#endif
+}
+
+static void dsi_framedone_irq_callback(void *data, u32 mask)
{
- int r;
const int channel = dsi.update_channel;
+ int r;
- DSSDBG("FRAMEDONE\n");
+ /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
+ * turns itself off. However, DSI still has the pixels in its buffers,
+ * and is sending the data.
+ */
if (dsi.te_enabled) {
/* enable LP_RX_TO again after the TE */
@@ -2904,37 +2839,30 @@ static void dsi_handle_framedone(void)
* This is not needed when TE is not in use, but we do it anyway to
* make sure that the transfer has been completed. It would be more
* optimal, but more complex, to wait only just before starting next
- * transfer. */
- r = dsi_vc_send_bta_sync(channel);
- if (r)
- DSSERR("BTA after framedone failed\n");
-
- /* RX_FIFO_NOT_EMPTY */
- if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
- DSSERR("Received error during frame transfer:\n");
- dsi_vc_flush_receive_data(channel);
- }
-
-#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
- dispc_fake_vsync_irq();
-#endif
-}
-
-static void dsi_framedone_work_callback(struct work_struct *work)
-{
- DSSDBGF();
+ * transfer.
+ *
+ * Also, as there's no interrupt telling when the transfer has been
+ * done and the channel could be reconfigured, the only way is to
+ * busyloop until TE_SIZE is zero. With BTA we can do this
+ * asynchronously.
+ * */
- cancel_delayed_work_sync(&dsi.framedone_timeout_work);
+ dsi.bta_callback = dsi_framedone_bta_callback;
- dsi_handle_framedone();
+ barrier();
- dsi_perf_show("DISPC");
+ dsi_vc_enable_bta_irq(channel);
- dsi.framedone_callback(0, dsi.framedone_data);
+ r = dsi_vc_send_bta(channel);
+ if (r) {
+ DSSERR("BTA after framedone failed\n");
+ dsi_handle_framedone(-EIO);
+ }
}
int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
- u16 *x, u16 *y, u16 *w, u16 *h)
+ u16 *x, u16 *y, u16 *w, u16 *h,
+ bool enlarge_update_area)
{
u16 dw, dh;
@@ -2958,7 +2886,8 @@ int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
dsi_perf_mark_setup();
if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
- dss_setup_partial_planes(dssdev, x, y, w, h);
+ dss_setup_partial_planes(dssdev, x, y, w, h,
+ enlarge_update_area);
dispc_set_lcd_size(*w, *h);
}
@@ -2973,6 +2902,12 @@ int omap_dsi_update(struct omap_dss_device *dssdev,
{
dsi.update_channel = channel;
+ /* OMAP DSS cannot send updates of odd widths.
+ * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
+ * here to make sure we catch erroneous updates. Otherwise we'll only
+ * see rather obscure HW error happening, as DSS halts. */
+ BUG_ON(x % 2 == 1);
+
if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
dsi.framedone_callback = callback;
dsi.framedone_data = data;
@@ -2985,7 +2920,12 @@ int omap_dsi_update(struct omap_dss_device *dssdev,
dsi_update_screen_dispc(dssdev, x, y, w, h);
} else {
- dsi_update_screen_l4(dssdev, x, y, w, h);
+ int r;
+
+ r = dsi_update_screen_l4(dssdev, x, y, w, h);
+ if (r)
+ return r;
+
dsi_perf_show("L4");
callback(0, data);
}
@@ -3048,8 +2988,10 @@ static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
cinfo.regm3 = dssdev->phy.dsi.div.regm3;
cinfo.regm4 = dssdev->phy.dsi.div.regm4;
r = dsi_calc_clock_rates(&cinfo);
- if (r)
+ if (r) {
+ DSSERR("Failed to calc dsi clocks\n");
return r;
+ }
r = dsi_pll_set_clock_div(&cinfo);
if (r) {
@@ -3147,6 +3089,13 @@ err0:
static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
{
+ /* disable interface */
+ dsi_if_enable(0);
+ dsi_vc_enable(0, 0);
+ dsi_vc_enable(1, 0);
+ dsi_vc_enable(2, 0);
+ dsi_vc_enable(3, 0);
+
dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
dsi_complexio_uninit();
@@ -3257,7 +3206,7 @@ void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
burst_size_bytes = 16 * 32 / 8;
*fifo_high = fifo_size - burst_size_bytes;
- *fifo_low = fifo_size - burst_size_bytes * 8;
+ *fifo_low = fifo_size - burst_size_bytes * 2;
}
int dsi_init_display(struct omap_dss_device *dssdev)
@@ -3274,6 +3223,18 @@ int dsi_init_display(struct omap_dss_device *dssdev)
return 0;
}
+void dsi_wait_dsi1_pll_active(void)
+{
+ if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1)
+ DSSERR("DSI1 PLL clock not active\n");
+}
+
+void dsi_wait_dsi2_pll_active(void)
+{
+ if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1)
+ DSSERR("DSI2 PLL clock not active\n");
+}
+
int dsi_init(struct platform_device *pdev)
{
u32 rev;
@@ -3292,7 +3253,10 @@ int dsi_init(struct platform_device *pdev)
mutex_init(&dsi.lock);
sema_init(&dsi.bus_lock, 1);
- INIT_WORK(&dsi.framedone_work, dsi_framedone_work_callback);
+ dsi.workqueue = create_singlethread_workqueue("dsi");
+ if (dsi.workqueue == NULL)
+ return -ENOMEM;
+
INIT_DELAYED_WORK_DEFERRABLE(&dsi.framedone_timeout_work,
dsi_framedone_timeout_work_callback);
@@ -3328,6 +3292,7 @@ int dsi_init(struct platform_device *pdev)
err2:
iounmap(dsi.base);
err1:
+ destroy_workqueue(dsi.workqueue);
return r;
}
@@ -3335,6 +3300,8 @@ void dsi_exit(void)
{
iounmap(dsi.base);
+ destroy_workqueue(dsi.workqueue);
+
DSSDBG("omap_dsi_exit\n");
}
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 24b18258654f..77c3621c9171 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -265,6 +265,9 @@ void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
+ if (clk_src == DSS_SRC_DSI1_PLL_FCLK)
+ dsi_wait_dsi1_pll_active();
+
REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */
dss.dispc_clk_source = clk_src;
@@ -279,6 +282,9 @@ void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1;
+ if (clk_src == DSS_SRC_DSI2_PLL_FCLK)
+ dsi_wait_dsi2_pll_active();
+
REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */
dss.dsi_clk_source = clk_src;
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index 786f433fd571..5c7940d5f282 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -199,7 +199,8 @@ int dss_init_overlay_managers(struct platform_device *pdev);
void dss_uninit_overlay_managers(struct platform_device *pdev);
int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl);
void dss_setup_partial_planes(struct omap_dss_device *dssdev,
- u16 *x, u16 *y, u16 *w, u16 *h);
+ u16 *x, u16 *y, u16 *w, u16 *h,
+ bool enlarge_update_area);
void dss_start_update(struct omap_dss_device *dssdev);
/* overlay */
@@ -281,6 +282,8 @@ void dsi_pll_uninit(void);
void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
u32 fifo_size, enum omap_burst_size *burst_size,
u32 *fifo_low, u32 *fifo_high);
+void dsi_wait_dsi1_pll_active(void);
+void dsi_wait_dsi2_pll_active(void);
#else
static inline int dsi_init(struct platform_device *pdev)
{
@@ -289,6 +292,12 @@ static inline int dsi_init(struct platform_device *pdev)
static inline void dsi_exit(void)
{
}
+static inline void dsi_wait_dsi1_pll_active(void)
+{
+}
+static inline void dsi_wait_dsi2_pll_active(void)
+{
+}
#endif
/* DPI */
diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
index 9e1fbe531bf0..6a649ab5539e 100644
--- a/drivers/video/omap2/dss/manager.c
+++ b/drivers/video/omap2/dss/manager.c
@@ -440,6 +440,10 @@ struct manager_cache_data {
/* manual update region */
u16 x, y, w, h;
+
+ /* enlarge the update area if the update area contains scaled
+ * overlays */
+ bool enlarge_update_area;
};
static struct {
@@ -525,7 +529,7 @@ static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr)
int i;
struct omap_dss_device *dssdev = mgr->device;
- if (!dssdev)
+ if (!dssdev || dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
return 0;
if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) {
@@ -596,11 +600,14 @@ int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl)
int r;
int i;
- if (!ovl->manager || !ovl->manager->device)
+ if (!ovl->manager)
return 0;
dssdev = ovl->manager->device;
+ if (!dssdev || dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
+ return 0;
+
if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) {
irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
channel = OMAP_DSS_CHANNEL_DIGIT;
@@ -718,6 +725,7 @@ static int configure_overlay(enum omap_plane plane)
u16 x, y, w, h;
u32 paddr;
int r;
+ u16 orig_w, orig_h, orig_outw, orig_outh;
DSSDBGF("%d", plane);
@@ -738,8 +746,16 @@ static int configure_overlay(enum omap_plane plane)
outh = c->out_height == 0 ? c->height : c->out_height;
paddr = c->paddr;
+ orig_w = w;
+ orig_h = h;
+ orig_outw = outw;
+ orig_outh = outh;
+
if (c->manual_update && mc->do_manual_update) {
unsigned bpp;
+ unsigned scale_x_m = w, scale_x_d = outw;
+ unsigned scale_y_m = h, scale_y_d = outh;
+
/* If the overlay is outside the update region, disable it */
if (!rectangle_intersects(mc->x, mc->y, mc->w, mc->h,
x, y, outw, outh)) {
@@ -770,38 +786,47 @@ static int configure_overlay(enum omap_plane plane)
BUG();
}
- if (dispc_is_overlay_scaled(c)) {
- /* If the overlay is scaled, the update area has
- * already been enlarged to cover the whole overlay. We
- * only need to adjust x/y here */
- x = c->pos_x - mc->x;
- y = c->pos_y - mc->y;
+ if (mc->x > c->pos_x) {
+ x = 0;
+ outw -= (mc->x - c->pos_x);
+ paddr += (mc->x - c->pos_x) *
+ scale_x_m / scale_x_d * bpp / 8;
} else {
- if (mc->x > c->pos_x) {
- x = 0;
- w -= (mc->x - c->pos_x);
- paddr += (mc->x - c->pos_x) * bpp / 8;
- } else {
- x = c->pos_x - mc->x;
- }
-
- if (mc->y > c->pos_y) {
- y = 0;
- h -= (mc->y - c->pos_y);
- paddr += (mc->y - c->pos_y) * c->screen_width *
- bpp / 8;
- } else {
- y = c->pos_y - mc->y;
- }
-
- if (mc->w < (x+w))
- w -= (x+w) - (mc->w);
+ x = c->pos_x - mc->x;
+ }
- if (mc->h < (y+h))
- h -= (y+h) - (mc->h);
+ if (mc->y > c->pos_y) {
+ y = 0;
+ outh -= (mc->y - c->pos_y);
+ paddr += (mc->y - c->pos_y) *
+ scale_y_m / scale_y_d *
+ c->screen_width * bpp / 8;
+ } else {
+ y = c->pos_y - mc->y;
+ }
- outw = w;
- outh = h;
+ if (mc->w < (x + outw))
+ outw -= (x + outw) - (mc->w);
+
+ if (mc->h < (y + outh))
+ outh -= (y + outh) - (mc->h);
+
+ w = w * outw / orig_outw;
+ h = h * outh / orig_outh;
+
+ /* YUV mode overlay's input width has to be even and the
+ * algorithm above may adjust the width to be odd.
+ *
+ * Here we adjust the width if needed, preferring to increase
+ * the width if the original width was bigger.
+ */
+ if ((w & 1) &&
+ (c->color_mode == OMAP_DSS_COLOR_YUV2 ||
+ c->color_mode == OMAP_DSS_COLOR_UYVY)) {
+ if (orig_w > w)
+ w += 1;
+ else
+ w -= 1;
}
}
@@ -960,7 +985,7 @@ static void make_even(u16 *x, u16 *w)
/* Configure dispc for partial update. Return possibly modified update
* area */
void dss_setup_partial_planes(struct omap_dss_device *dssdev,
- u16 *xi, u16 *yi, u16 *wi, u16 *hi)
+ u16 *xi, u16 *yi, u16 *wi, u16 *hi, bool enlarge_update_area)
{
struct overlay_cache_data *oc;
struct manager_cache_data *mc;
@@ -969,6 +994,7 @@ void dss_setup_partial_planes(struct omap_dss_device *dssdev,
int i;
u16 x, y, w, h;
unsigned long flags;
+ bool area_changed;
x = *xi;
y = *yi;
@@ -989,73 +1015,91 @@ void dss_setup_partial_planes(struct omap_dss_device *dssdev,
spin_lock_irqsave(&dss_cache.lock, flags);
- /* We need to show the whole overlay if it is scaled. So look for
- * those, and make the update area larger if found.
- * Also mark the overlay cache dirty */
- for (i = 0; i < num_ovls; ++i) {
- unsigned x1, y1, x2, y2;
- unsigned outw, outh;
+ /*
+ * Execute the outer loop until the inner loop has completed
+ * once without increasing the update area. This will ensure that
+ * all scaled overlays end up completely within the update area.
+ */
+ do {
+ area_changed = false;
- oc = &dss_cache.overlay_cache[i];
+ /* We need to show the whole overlay if it is scaled. So look
+ * for those, and make the update area larger if found.
+ * Also mark the overlay cache dirty */
+ for (i = 0; i < num_ovls; ++i) {
+ unsigned x1, y1, x2, y2;
+ unsigned outw, outh;
- if (oc->channel != mgr->id)
- continue;
+ oc = &dss_cache.overlay_cache[i];
- oc->dirty = true;
+ if (oc->channel != mgr->id)
+ continue;
- if (!oc->enabled)
- continue;
+ oc->dirty = true;
- if (!dispc_is_overlay_scaled(oc))
- continue;
+ if (!enlarge_update_area)
+ continue;
- outw = oc->out_width == 0 ? oc->width : oc->out_width;
- outh = oc->out_height == 0 ? oc->height : oc->out_height;
+ if (!oc->enabled)
+ continue;
- /* is the overlay outside the update region? */
- if (!rectangle_intersects(x, y, w, h,
- oc->pos_x, oc->pos_y,
- outw, outh))
- continue;
+ if (!dispc_is_overlay_scaled(oc))
+ continue;
- /* if the overlay totally inside the update region? */
- if (rectangle_subset(oc->pos_x, oc->pos_y, outw, outh,
- x, y, w, h))
- continue;
+ outw = oc->out_width == 0 ?
+ oc->width : oc->out_width;
+ outh = oc->out_height == 0 ?
+ oc->height : oc->out_height;
+
+ /* is the overlay outside the update region? */
+ if (!rectangle_intersects(x, y, w, h,
+ oc->pos_x, oc->pos_y,
+ outw, outh))
+ continue;
- if (x > oc->pos_x)
- x1 = oc->pos_x;
- else
- x1 = x;
+ /* if the overlay totally inside the update region? */
+ if (rectangle_subset(oc->pos_x, oc->pos_y, outw, outh,
+ x, y, w, h))
+ continue;
- if (y > oc->pos_y)
- y1 = oc->pos_y;
- else
- y1 = y;
+ if (x > oc->pos_x)
+ x1 = oc->pos_x;
+ else
+ x1 = x;
- if ((x + w) < (oc->pos_x + outw))
- x2 = oc->pos_x + outw;
- else
- x2 = x + w;
+ if (y > oc->pos_y)
+ y1 = oc->pos_y;
+ else
+ y1 = y;
- if ((y + h) < (oc->pos_y + outh))
- y2 = oc->pos_y + outh;
- else
- y2 = y + h;
+ if ((x + w) < (oc->pos_x + outw))
+ x2 = oc->pos_x + outw;
+ else
+ x2 = x + w;
- x = x1;
- y = y1;
- w = x2 - x1;
- h = y2 - y1;
+ if ((y + h) < (oc->pos_y + outh))
+ y2 = oc->pos_y + outh;
+ else
+ y2 = y + h;
- make_even(&x, &w);
+ x = x1;
+ y = y1;
+ w = x2 - x1;
+ h = y2 - y1;
- DSSDBG("changing upd area due to ovl(%d) scaling %d,%d %dx%d\n",
+ make_even(&x, &w);
+
+ DSSDBG("changing upd area due to ovl(%d) "
+ "scaling %d,%d %dx%d\n",
i, x, y, w, h);
- }
+
+ area_changed = true;
+ }
+ } while (area_changed);
mc = &dss_cache.manager_cache[mgr->id];
mc->do_manual_update = true;
+ mc->enlarge_update_area = enlarge_update_area;
mc->x = x;
mc->y = y;
mc->w = w;
diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
index 82336583adef..244dca81a399 100644
--- a/drivers/video/omap2/dss/overlay.c
+++ b/drivers/video/omap2/dss/overlay.c
@@ -65,7 +65,7 @@ static ssize_t overlay_manager_store(struct omap_overlay *ovl, const char *buf,
for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
mgr = omap_dss_get_overlay_manager(i);
- if (strncmp(buf, mgr->name, len) == 0)
+ if (sysfs_streq(buf, mgr->name))
break;
mgr = NULL;
diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c
index cc23f53cc62d..bbe62464e92d 100644
--- a/drivers/video/omap2/dss/rfbi.c
+++ b/drivers/video/omap2/dss/rfbi.c
@@ -886,7 +886,7 @@ int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
return -EINVAL;
if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
- dss_setup_partial_planes(dssdev, x, y, w, h);
+ dss_setup_partial_planes(dssdev, x, y, w, h, true);
dispc_set_lcd_size(*w, *h);
}
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-23 23:01:48 +0300