diff options
Diffstat (limited to 'drivers/spi')
32 files changed, 823 insertions, 492 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index d2815eb361c0..cca92a81fff7 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -419,10 +419,10 @@ config SPI_IMX This enables support for the Freescale i.MX SPI controllers. config SPI_INGENIC - tristate "Ingenic JZ47xx SoCs SPI controller" + tristate "Ingenic SoCs SPI controller" depends on MACH_INGENIC || COMPILE_TEST help - This enables support for the Ingenic JZ47xx SoCs SPI controller. + This enables support for the Ingenic SoCs SPI controller. To compile this driver as a module, choose M here: the module will be called spi-ingenic. diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 92d9610df1fd..480c0c8c18e4 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -277,6 +277,9 @@ static int atmel_qspi_find_mode(const struct spi_mem_op *op) static bool atmel_qspi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { + if (!spi_mem_default_supports_op(mem, op)) + return false; + if (atmel_qspi_find_mode(op) < 0) return false; @@ -285,12 +288,6 @@ static bool atmel_qspi_supports_op(struct spi_mem *mem, op->dummy.nbytes == 0) return false; - /* DTR ops not supported. */ - if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) - return false; - if (op->cmd.nbytes != 1) - return false; - return true; } diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index 86c76211b3d3..cad2d55dcd3d 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -1205,7 +1205,7 @@ static int bcm_qspi_exec_mem_op(struct spi_mem *mem, addr = op->addr.val; len = op->data.nbytes; - if (bcm_qspi_bspi_ver_three(qspi) == true) { + if (has_bspi(qspi) && bcm_qspi_bspi_ver_three(qspi) == true) { /* * The address coming into this function is a raw flash offset. * But for BSPI <= V3, we need to convert it to a remapped BSPI @@ -1224,7 +1224,7 @@ static int bcm_qspi_exec_mem_op(struct spi_mem *mem, len < 4) mspi_read = true; - if (mspi_read) + if (!has_bspi(qspi) || mspi_read) return bcm_qspi_mspi_exec_mem_op(spi, op); ret = bcm_qspi_bspi_set_mode(qspi, op, 0); diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index b0c9f62ccefb..41922a5ea1f4 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -19,6 +19,7 @@ #include <linux/iopoll.h> #include <linux/jiffies.h> #include <linux/kernel.h> +#include <linux/log2.h> #include <linux/module.h> #include <linux/of_device.h> #include <linux/of.h> @@ -42,6 +43,8 @@ /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) +#define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) + struct cqspi_st; struct cqspi_flash_pdata { @@ -52,10 +55,6 @@ struct cqspi_flash_pdata { u32 tsd2d_ns; u32 tchsh_ns; u32 tslch_ns; - u8 inst_width; - u8 addr_width; - u8 data_width; - bool dtr; u8 cs; }; @@ -102,12 +101,6 @@ struct cqspi_driver_platdata { #define CQSPI_TIMEOUT_MS 500 #define CQSPI_READ_TIMEOUT_MS 10 -/* Instruction type */ -#define CQSPI_INST_TYPE_SINGLE 0 -#define CQSPI_INST_TYPE_DUAL 1 -#define CQSPI_INST_TYPE_QUAD 2 -#define CQSPI_INST_TYPE_OCTAL 3 - #define CQSPI_DUMMY_CLKS_PER_BYTE 8 #define CQSPI_DUMMY_BYTES_MAX 4 #define CQSPI_DUMMY_CLKS_MAX 31 @@ -348,18 +341,18 @@ static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) return IRQ_HANDLED; } -static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata) +static unsigned int cqspi_calc_rdreg(const struct spi_mem_op *op) { u32 rdreg = 0; - rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; - rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; - rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; + rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; + rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; + rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; return rdreg; } -static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr) +static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op) { unsigned int dummy_clk; @@ -367,83 +360,12 @@ static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr) return 0; dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); - if (dtr) + if (op->cmd.dtr) dummy_clk /= 2; return dummy_clk; } -static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata, - const struct spi_mem_op *op) -{ - f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE; - f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE; - f_pdata->data_width = CQSPI_INST_TYPE_SINGLE; - - /* - * For an op to be DTR, cmd phase along with every other non-empty - * phase should have dtr field set to 1. If an op phase has zero - * nbytes, ignore its dtr field; otherwise, check its dtr field. - */ - f_pdata->dtr = op->cmd.dtr && - (!op->addr.nbytes || op->addr.dtr) && - (!op->data.nbytes || op->data.dtr); - - switch (op->data.buswidth) { - case 0: - break; - case 1: - f_pdata->data_width = CQSPI_INST_TYPE_SINGLE; - break; - case 2: - f_pdata->data_width = CQSPI_INST_TYPE_DUAL; - break; - case 4: - f_pdata->data_width = CQSPI_INST_TYPE_QUAD; - break; - case 8: - f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; - break; - default: - return -EINVAL; - } - - /* Right now we only support 8-8-8 DTR mode. */ - if (f_pdata->dtr) { - switch (op->cmd.buswidth) { - case 0: - break; - case 8: - f_pdata->inst_width = CQSPI_INST_TYPE_OCTAL; - break; - default: - return -EINVAL; - } - - switch (op->addr.buswidth) { - case 0: - break; - case 8: - f_pdata->addr_width = CQSPI_INST_TYPE_OCTAL; - break; - default: - return -EINVAL; - } - - switch (op->data.buswidth) { - case 0: - break; - case 8: - f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; - break; - default: - return -EINVAL; - } - } - - return 0; -} - static int cqspi_wait_idle(struct cqspi_st *cqspi) { const unsigned int poll_idle_retry = 3; @@ -525,8 +447,7 @@ static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata, } static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, - const struct spi_mem_op *op, unsigned int shift, - bool enable) + const struct spi_mem_op *op, unsigned int shift) { struct cqspi_st *cqspi = f_pdata->cqspi; void __iomem *reg_base = cqspi->iobase; @@ -539,7 +460,7 @@ static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, * We enable dual byte opcode here. The callers have to set up the * extension opcode based on which type of operation it is. */ - if (enable) { + if (op->cmd.dtr) { reg |= CQSPI_REG_CONFIG_DTR_PROTO; reg |= CQSPI_REG_CONFIG_DUAL_OPCODE; @@ -571,12 +492,7 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, size_t read_len; int status; - status = cqspi_set_protocol(f_pdata, op); - if (status) - return status; - - status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB, - f_pdata->dtr); + status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); if (status) return status; @@ -587,17 +503,17 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, return -EINVAL; } - if (f_pdata->dtr) + if (op->cmd.dtr) opcode = op->cmd.opcode >> 8; else opcode = op->cmd.opcode; reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; - rdreg = cqspi_calc_rdreg(f_pdata); + rdreg = cqspi_calc_rdreg(op); writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); - dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr); + dummy_clk = cqspi_calc_dummy(op); if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) return -EOPNOTSUPP; @@ -644,12 +560,7 @@ static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, size_t write_len; int ret; - ret = cqspi_set_protocol(f_pdata, op); - if (ret) - return ret; - - ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB, - f_pdata->dtr); + ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); if (ret) return ret; @@ -660,10 +571,10 @@ static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, return -EINVAL; } - reg = cqspi_calc_rdreg(f_pdata); + reg = cqspi_calc_rdreg(op); writel(reg, reg_base + CQSPI_REG_RD_INSTR); - if (f_pdata->dtr) + if (op->cmd.dtr) opcode = op->cmd.opcode >> 8; else opcode = op->cmd.opcode; @@ -710,21 +621,20 @@ static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, int ret; u8 opcode; - ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB, - f_pdata->dtr); + ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB); if (ret) return ret; - if (f_pdata->dtr) + if (op->cmd.dtr) opcode = op->cmd.opcode >> 8; else opcode = op->cmd.opcode; reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; - reg |= cqspi_calc_rdreg(f_pdata); + reg |= cqspi_calc_rdreg(op); /* Setup dummy clock cycles */ - dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr); + dummy_clk = cqspi_calc_dummy(op); if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) return -EOPNOTSUPP; @@ -969,22 +879,21 @@ static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, void __iomem *reg_base = cqspi->iobase; u8 opcode; - ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB, - f_pdata->dtr); + ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB); if (ret) return ret; - if (f_pdata->dtr) + if (op->cmd.dtr) opcode = op->cmd.opcode >> 8; else opcode = op->cmd.opcode; /* Set opcode. */ reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; - reg |= f_pdata->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; - reg |= f_pdata->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; + reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; + reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; writel(reg, reg_base + CQSPI_REG_WR_INSTR); - reg = cqspi_calc_rdreg(f_pdata); + reg = cqspi_calc_rdreg(op); writel(reg, reg_base + CQSPI_REG_RD_INSTR); /* @@ -1266,10 +1175,6 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, const u_char *buf = op->data.buf.out; int ret; - ret = cqspi_set_protocol(f_pdata, op); - if (ret) - return ret; - ret = cqspi_write_setup(f_pdata, op); if (ret) return ret; @@ -1282,7 +1187,7 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, * mode. So, we can not use direct mode when in DTR mode for writing * data. */ - if (!f_pdata->dtr && cqspi->use_direct_mode && + if (!op->cmd.dtr && cqspi->use_direct_mode && ((to + len) <= cqspi->ahb_size)) { memcpy_toio(cqspi->ahb_base + to, buf, len); return cqspi_wait_idle(cqspi); @@ -1370,9 +1275,6 @@ static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, int ret; ddata = of_device_get_match_data(dev); - ret = cqspi_set_protocol(f_pdata, op); - if (ret) - return ret; ret = cqspi_read_setup(f_pdata, op); if (ret) @@ -1437,9 +1339,18 @@ static bool cqspi_supports_mem_op(struct spi_mem *mem, all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && !op->data.dtr; - /* Mixed DTR modes not supported. */ - if (!(all_true || all_false)) + if (all_true) { + /* Right now we only support 8-8-8 DTR mode. */ + if (op->cmd.nbytes && op->cmd.buswidth != 8) + return false; + if (op->addr.nbytes && op->addr.buswidth != 8) + return false; + if (op->data.nbytes && op->data.buswidth != 8) + return false; + } else if (!all_false) { + /* Mixed DTR modes are not supported. */ return false; + } return spi_mem_default_supports_op(mem, op); } @@ -1707,11 +1618,9 @@ static int cqspi_probe(struct platform_device *pdev) } pm_runtime_enable(dev); - ret = pm_runtime_get_sync(dev); - if (ret < 0) { - pm_runtime_put_noidle(dev); + ret = pm_runtime_resume_and_get(dev); + if (ret < 0) goto probe_master_put; - } ret = clk_prepare_enable(cqspi->clk); if (ret) { diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c index ceb16e70d235..b509eefe16a8 100644 --- a/drivers/spi/spi-cadence.c +++ b/drivers/spi/spi-cadence.c @@ -657,7 +657,7 @@ static int __maybe_unused cdns_spi_resume(struct device *dev) * * Return: 0 on success and error value on error */ -static int __maybe_unused cnds_runtime_resume(struct device *dev) +static int __maybe_unused cdns_spi_runtime_resume(struct device *dev) { struct spi_master *master = dev_get_drvdata(dev); struct cdns_spi *xspi = spi_master_get_devdata(master); @@ -686,7 +686,7 @@ static int __maybe_unused cnds_runtime_resume(struct device *dev) * * Return: Always 0 */ -static int __maybe_unused cnds_runtime_suspend(struct device *dev) +static int __maybe_unused cdns_spi_runtime_suspend(struct device *dev) { struct spi_master *master = dev_get_drvdata(dev); struct cdns_spi *xspi = spi_master_get_devdata(master); @@ -698,8 +698,8 @@ static int __maybe_unused cnds_runtime_suspend(struct device *dev) } static const struct dev_pm_ops cdns_spi_dev_pm_ops = { - SET_RUNTIME_PM_OPS(cnds_runtime_suspend, - cnds_runtime_resume, NULL) + SET_RUNTIME_PM_OPS(cdns_spi_runtime_suspend, + cdns_spi_runtime_resume, NULL) SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume) }; diff --git a/drivers/spi/spi-clps711x.c b/drivers/spi/spi-clps711x.c index 0bef5ce08094..c005ed26a3e1 100644 --- a/drivers/spi/spi-clps711x.c +++ b/drivers/spi/spi-clps711x.c @@ -9,6 +9,7 @@ #include <linux/clk.h> #include <linux/gpio/consumer.h> #include <linux/module.h> +#include <linux/of.h> #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/regmap.h> @@ -89,6 +90,7 @@ static irqreturn_t spi_clps711x_isr(int irq, void *dev_id) static int spi_clps711x_probe(struct platform_device *pdev) { + struct device_node *np = pdev->dev.of_node; struct spi_clps711x_data *hw; struct spi_master *master; int irq, ret; @@ -117,8 +119,7 @@ static int spi_clps711x_probe(struct platform_device *pdev) goto err_out; } - hw->syscon = - syscon_regmap_lookup_by_compatible("cirrus,ep7209-syscon3"); + hw->syscon = syscon_regmap_lookup_by_phandle(np, "syscon"); if (IS_ERR(hw->syscon)) { ret = PTR_ERR(hw->syscon); goto err_out; diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c index 5f05d519fbbd..71376b6df89d 100644 --- a/drivers/spi/spi-img-spfi.c +++ b/drivers/spi/spi-img-spfi.c @@ -731,7 +731,7 @@ static int img_spfi_resume(struct device *dev) int ret; ret = pm_runtime_get_sync(dev); - if (ret) { + if (ret < 0) { pm_runtime_put_noidle(dev); return ret; } diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index b2dd0a4d2446..733e40e71ee6 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -108,6 +108,7 @@ struct spi_imx_data { const void *tx_buf; unsigned int txfifo; /* number of words pushed in tx FIFO */ unsigned int dynamic_burst; + bool rx_only; /* Slave mode */ bool slave_mode; @@ -554,11 +555,6 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, else cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); - if (spi->mode & SPI_CPHA) - cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); - else - cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); - if (spi->mode & SPI_CPOL) { cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); @@ -606,6 +602,24 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, return 0; } +static void mx51_configure_cpha(struct spi_imx_data *spi_imx, + struct spi_device *spi) +{ + bool cpha = (spi->mode & SPI_CPHA); + bool flip_cpha = (spi->mode & SPI_RX_CPHA_FLIP) && spi_imx->rx_only; + u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); + + /* Flip cpha logical value iff flip_cpha */ + cpha ^= flip_cpha; + + if (cpha) + cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); + else + cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); + + writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); +} + static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx, struct spi_device *spi) { @@ -627,6 +641,8 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx, ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk); spi_imx->spi_bus_clk = clk; + mx51_configure_cpha(spi_imx, spi); + /* * ERR009165: work in XHC mode instead of SMC as PIO on the chips * before i.mx6ul. @@ -1251,6 +1267,9 @@ static int spi_imx_setupxfer(struct spi_device *spi, else spi_imx->usedma = false; + spi_imx->rx_only = ((t->tx_buf == NULL) + || (t->tx_buf == spi->controller->dummy_tx)); + if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) { spi_imx->rx = mx53_ecspi_rx_slave; spi_imx->tx = mx53_ecspi_tx_slave; @@ -1553,9 +1572,8 @@ spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg) struct spi_imx_data *spi_imx = spi_master_get_devdata(master); int ret; - ret = pm_runtime_get_sync(spi_imx->dev); + ret = pm_runtime_resume_and_get(spi_imx->dev); if (ret < 0) { - pm_runtime_put_noidle(spi_imx->dev); dev_err(spi_imx->dev, "failed to enable clock\n"); return ret; } @@ -1655,6 +1673,9 @@ static int spi_imx_probe(struct platform_device *pdev) is_imx53_ecspi(spi_imx)) spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY; + if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) + spi_imx->bitbang.master->mode_bits |= SPI_RX_CPHA_FLIP; + if (is_imx51_ecspi(spi_imx) && device_property_read_u32(&pdev->dev, "cs-gpios", NULL)) /* @@ -1771,9 +1792,8 @@ static int spi_imx_remove(struct platform_device *pdev) spi_bitbang_stop(&spi_imx->bitbang); - ret = pm_runtime_get_sync(spi_imx->dev); + ret = pm_runtime_resume_and_get(spi_imx->dev); if (ret < 0) { - pm_runtime_put_noidle(spi_imx->dev); dev_err(spi_imx->dev, "failed to enable clock\n"); return ret; } diff --git a/drivers/spi/spi-ingenic.c b/drivers/spi/spi-ingenic.c index 03077a7e11c8..713a238bee63 100644 --- a/drivers/spi/spi-ingenic.c +++ b/drivers/spi/spi-ingenic.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * SPI bus driver for the Ingenic JZ47xx SoCs + * SPI bus driver for the Ingenic SoCs * Copyright (c) 2017-2021 Artur Rojek <contact@artur-rojek.eu> * Copyright (c) 2017-2021 Paul Cercueil <paul@crapouillou.net> + * Copyright (c) 2022 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> */ #include <linux/clk.h> @@ -52,6 +53,9 @@ struct jz_soc_info { u32 bits_per_word_mask; struct reg_field flen_field; bool has_trendian; + + unsigned int max_speed_hz; + unsigned int max_native_cs; }; struct ingenic_spi { @@ -380,7 +384,7 @@ static int spi_ingenic_probe(struct platform_device *pdev) struct spi_controller *ctlr; struct ingenic_spi *priv; void __iomem *base; - int ret; + int num_cs, ret; pdata = of_device_get_match_data(dev); if (!pdata) { @@ -416,6 +420,9 @@ static int spi_ingenic_probe(struct platform_device *pdev) if (IS_ERR(priv->flen_field)) return PTR_ERR(priv->flen_field); + if (device_property_read_u32(dev, "num-cs", &num_cs)) + num_cs = pdata->max_native_cs; + platform_set_drvdata(pdev, ctlr); ctlr->prepare_transfer_hardware = spi_ingenic_prepare_hardware; @@ -428,8 +435,10 @@ static int spi_ingenic_probe(struct platform_device *pdev) ctlr->max_dma_len = SPI_INGENIC_FIFO_SIZE; ctlr->bits_per_word_mask = pdata->bits_per_word_mask; ctlr->min_speed_hz = 7200; - ctlr->max_speed_hz = 54000000; - ctlr->num_chipselect = 2; + ctlr->max_speed_hz = pdata->max_speed_hz; + ctlr->use_gpio_descriptors = true; + ctlr->max_native_cs = pdata->max_native_cs; + ctlr->num_chipselect = num_cs; ctlr->dev.of_node = pdev->dev.of_node; if (spi_ingenic_request_dma(ctlr, dev)) @@ -452,17 +461,44 @@ static const struct jz_soc_info jz4750_soc_info = { .bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 17), .flen_field = REG_FIELD(REG_SSICR1, 4, 7), .has_trendian = false, + + .max_speed_hz = 54000000, + .max_native_cs = 2, }; static const struct jz_soc_info jz4780_soc_info = { .bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 32), .flen_field = REG_FIELD(REG_SSICR1, 3, 7), .has_trendian = true, + + .max_speed_hz = 54000000, + .max_native_cs = 2, +}; + +static const struct jz_soc_info x1000_soc_info = { + .bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 32), + .flen_field = REG_FIELD(REG_SSICR1, 3, 7), + .has_trendian = true, + + .max_speed_hz = 50000000, + .max_native_cs = 2, +}; + +static const struct jz_soc_info x2000_soc_info = { + .bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 32), + .flen_field = REG_FIELD(REG_SSICR1, 3, 7), + .has_trendian = true, + + .max_speed_hz = 50000000, + .max_native_cs = 1, }; static const struct of_device_id spi_ingenic_of_match[] = { { .compatible = "ingenic,jz4750-spi", .data = &jz4750_soc_info }, + { .compatible = "ingenic,jz4775-spi", .data = &jz4780_soc_info }, { .compatible = "ingenic,jz4780-spi", .data = &jz4780_soc_info }, + { .compatible = "ingenic,x1000-spi", .data = &x1000_soc_info }, + { .compatible = "ingenic,x2000-spi", .data = &x2000_soc_info }, {} }; MODULE_DEVICE_TABLE(of, spi_ingenic_of_match); @@ -476,7 +512,8 @@ static struct platform_driver spi_ingenic_driver = { }; module_platform_driver(spi_ingenic_driver); -MODULE_DESCRIPTION("SPI bus driver for the Ingenic JZ47xx SoCs"); +MODULE_DESCRIPTION("SPI bus driver for the Ingenic SoCs"); MODULE_AUTHOR("Artur Rojek <contact@artur-rojek.eu>"); MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>"); +MODULE_AUTHOR("周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>"); MODULE_LICENSE("GPL"); diff --git a/drivers/spi/spi-intel-pci.c b/drivers/spi/spi-intel-pci.c index a5ef7a526a7f..f6eec7a869b6 100644 --- a/drivers/spi/spi-intel-pci.c +++ b/drivers/spi/spi-intel-pci.c @@ -72,6 +72,7 @@ static const struct pci_device_id intel_spi_pci_ids[] = { { PCI_VDEVICE(INTEL, 0x4da4), (unsigned long)&bxt_info }, { PCI_VDEVICE(INTEL, 0x51a4), (unsigned long)&cnl_info }, { PCI_VDEVICE(INTEL, 0x54a4), (unsigned long)&cnl_info }, + { PCI_VDEVICE(INTEL, 0x7a24), (unsigned long)&cnl_info }, { PCI_VDEVICE(INTEL, 0x7aa4), (unsigned long)&cnl_info }, { PCI_VDEVICE(INTEL, 0xa0a4), (unsigned long)&bxt_info }, { PCI_VDEVICE(INTEL, 0xa1a4), (unsigned long)&bxt_info }, diff --git a/drivers/spi/spi-intel.c b/drivers/spi/spi-intel.c index e937cfe85559..50f42983b950 100644 --- a/drivers/spi/spi-intel.c +++ b/drivers/spi/spi-intel.c @@ -779,10 +779,59 @@ static const char *intel_spi_get_name(struct spi_mem *mem) return dev_name(ispi->dev); } +static int intel_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) +{ + struct intel_spi *ispi = spi_master_get_devdata(desc->mem->spi->master); + const struct intel_spi_mem_op *iop; + + iop = intel_spi_match_mem_op(ispi, &desc->info.op_tmpl); + if (!iop) + return -EOPNOTSUPP; + + desc->priv = (void *)iop; + return 0; +} + +static ssize_t intel_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, u64 offs, + size_t len, void *buf) +{ + struct intel_spi *ispi = spi_master_get_devdata(desc->mem->spi->master); + const struct intel_spi_mem_op *iop = desc->priv; + struct spi_mem_op op = desc->info.op_tmpl; + int ret; + + /* Fill in the gaps */ + op.addr.val = offs; + op.data.nbytes = len; + op.data.buf.in = buf; + + ret = iop->exec_op(ispi, iop, &op); + return ret ? ret : len; +} + +static ssize_t intel_spi_dirmap_write(struct spi_mem_dirmap_desc *desc, u64 offs, + size_t len, const void *buf) +{ + struct intel_spi *ispi = spi_master_get_devdata(desc->mem->spi->master); + const struct intel_spi_mem_op *iop = desc->priv; + struct spi_mem_op op = desc->info.op_tmpl; + int ret; + + op.addr.val = offs; + op.data.nbytes = len; + op.data.buf.out = buf; + + ret = iop->exec_op(ispi, iop, &op); + return ret ? ret : len; +} + static const struct spi_controller_mem_ops intel_spi_mem_ops = { .supports_op = intel_spi_supports_mem_op, .exec_op = intel_spi_exec_mem_op, .get_name = intel_spi_get_name, + .dirmap_create = intel_spi_dirmap_create, + .dirmap_read = intel_spi_dirmap_read, + .dirmap_write = intel_spi_dirmap_write, }; #define INTEL_SPI_OP_ADDR(__nbytes) \ @@ -1205,7 +1254,7 @@ static int intel_spi_populate_chip(struct intel_spi *ispi) * intel_spi_probe() - Probe the Intel SPI flash controller * @dev: Pointer to the parent device * @mem: MMIO resource - * @info: Platform spefific information + * @info: Platform specific information * * Probes Intel SPI flash controller and creates the flash chip device. * Returns %0 on success and negative errno in case of failure. diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 0e8dafc62d94..7d7091aa0c22 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -262,9 +262,8 @@ static int spi_mem_access_start(struct spi_mem *mem) if (ctlr->auto_runtime_pm) { int ret; - ret = pm_runtime_get_sync(ctlr->dev.parent); + ret = pm_runtime_resume_and_get(ctlr->dev.parent); if (ret < 0) { - pm_runtime_put_noidle(ctlr->dev.parent); dev_err(&ctlr->dev, "Failed to power device: %d\n", ret); return ret; diff --git a/drivers/spi/spi-mpc52xx-psc.c b/drivers/spi/spi-mpc52xx-psc.c index 21ef5d481faf..7654736c2c0e 100644 --- a/drivers/spi/spi-mpc52xx-psc.c +++ b/drivers/spi/spi-mpc52xx-psc.c @@ -20,6 +20,7 @@ #include <linux/spi/spi.h> #include <linux/fsl_devices.h> #include <linux/slab.h> +#include <linux/of_irq.h> #include <asm/mpc52xx.h> #include <asm/mpc52xx_psc.h> diff --git a/drivers/spi/spi-mpc52xx.c b/drivers/spi/spi-mpc52xx.c index 51041526546d..3ebdce804b90 100644 --- a/drivers/spi/spi-mpc52xx.c +++ b/drivers/spi/spi-mpc52xx.c @@ -19,6 +19,9 @@ #include <linux/io.h> #include <linux/of_gpio.h> #include <linux/slab.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> + #include <asm/time.h> #include <asm/mpc52xx.h> diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index 1a0b3208dfca..0a3b9f7eed30 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -17,105 +17,148 @@ #include <linux/platform_data/spi-mt65xx.h> #include <linux/pm_runtime.h> #include <linux/spi/spi.h> +#include <linux/spi/spi-mem.h> #include <linux/dma-mapping.h> -#define SPI_CFG0_REG 0x0000 -#define SPI_CFG1_REG 0x0004 -#define SPI_TX_SRC_REG 0x0008 -#define SPI_RX_DST_REG 0x000c -#define SPI_TX_DATA_REG 0x0010 -#define SPI_RX_DATA_REG 0x0014 -#define SPI_CMD_REG 0x0018 -#define SPI_STATUS0_REG 0x001c -#define SPI_PAD_SEL_REG 0x0024 -#define SPI_CFG2_REG 0x0028 -#define SPI_TX_SRC_REG_64 0x002c -#define SPI_RX_DST_REG_64 0x0030 -#define SPI_CFG3_IPM_REG 0x0040 - -#define SPI_CFG0_SCK_HIGH_OFFSET 0 -#define SPI_CFG0_SCK_LOW_OFFSET 8 -#define SPI_CFG0_CS_HOLD_OFFSET 16 -#define SPI_CFG0_CS_SETUP_OFFSET 24 -#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0 -#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16 - -#define SPI_CFG1_CS_IDLE_OFFSET 0 -#define SPI_CFG1_PACKET_LOOP_OFFSET 8 -#define SPI_CFG1_PACKET_LENGTH_OFFSET 16 -#define SPI_CFG1_GET_TICK_DLY_OFFSET 29 -#define SPI_CFG1_GET_TICK_DLY_OFFSET_V1 30 - -#define SPI_CFG1_GET_TICK_DLY_MASK 0xe0000000 -#define SPI_CFG1_GET_TICK_DLY_MASK_V1 0xc0000000 - -#define SPI_CFG1_CS_IDLE_MASK 0xff -#define SPI_CFG1_PACKET_LOOP_MASK 0xff00 -#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 -#define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16) -#define SPI_CFG2_SCK_HIGH_OFFSET 0 -#define SPI_CFG2_SCK_LOW_OFFSET 16 - -#define SPI_CMD_ACT BIT(0) -#define SPI_CMD_RESUME BIT(1) -#define SPI_CMD_RST BIT(2) -#define SPI_CMD_PAUSE_EN BIT(4) -#define SPI_CMD_DEASSERT BIT(5) -#define SPI_CMD_SAMPLE_SEL BIT(6) -#define SPI_CMD_CS_POL BIT(7) -#define SPI_CMD_CPHA BIT(8) -#define SPI_CMD_CPOL BIT(9) -#define SPI_CMD_RX_DMA BIT(10) -#define SPI_CMD_TX_DMA BIT(11) -#define SPI_CMD_TXMSBF BIT(12) -#define SPI_CMD_RXMSBF BIT(13) -#define SPI_CMD_RX_ENDIAN BIT(14) -#define SPI_CMD_TX_ENDIAN BIT(15) -#define SPI_CMD_FINISH_IE BIT(16) -#define SPI_CMD_PAUSE_IE BIT(17) -#define SPI_CMD_IPM_NONIDLE_MODE BIT(19) -#define SPI_CMD_IPM_SPIM_LOOP BIT(21) -#define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22 +#define SPI_CFG0_REG 0x0000 +#define SPI_CFG1_REG 0x0004 +#define SPI_TX_SRC_REG 0x0008 +#define SPI_RX_DST_REG 0x000c +#define SPI_TX_DATA_REG 0x0010 +#define SPI_RX_DATA_REG 0x0014 +#define SPI_CMD_REG 0x0018 +#define SPI_STATUS0_REG 0x001c +#define SPI_PAD_SEL_REG 0x0024 +#define SPI_CFG2_REG 0x0028 +#define SPI_TX_SRC_REG_64 0x002c +#define SPI_RX_DST_REG_64 0x0030 +#define SPI_CFG3_IPM_REG 0x0040 + +#define SPI_CFG0_SCK_HIGH_OFFSET 0 +#define SPI_CFG0_SCK_LOW_OFFSET 8 +#define SPI_CFG0_CS_HOLD_OFFSET 16 +#define SPI_CFG0_CS_SETUP_OFFSET 24 +#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0 +#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16 + +#define SPI_CFG1_CS_IDLE_OFFSET 0 +#define SPI_CFG1_PACKET_LOOP_OFFSET 8 +#define SPI_CFG1_PACKET_LENGTH_OFFSET 16 +#define SPI_CFG1_GET_TICK_DLY_OFFSET 29 +#define SPI_CFG1_GET_TICK_DLY_OFFSET_V1 30 + +#define SPI_CFG1_GET_TICK_DLY_MASK 0xe0000000 +#define SPI_CFG1_GET_TICK_DLY_MASK_V1 0xc0000000 + +#define SPI_CFG1_CS_IDLE_MASK 0xff +#define SPI_CFG1_PACKET_LOOP_MASK 0xff00 +#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 +#define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16) +#define SPI_CFG2_SCK_HIGH_OFFSET 0 +#define SPI_CFG2_SCK_LOW_OFFSET 16 + +#define SPI_CMD_ACT BIT(0) +#define SPI_CMD_RESUME BIT(1) +#define SPI_CMD_RST BIT(2) +#define SPI_CMD_PAUSE_EN BIT(4) +#define SPI_CMD_DEASSERT BIT(5) +#define SPI_CMD_SAMPLE_SEL BIT(6) +#define SPI_CMD_CS_POL BIT(7) +#define SPI_CMD_CPHA BIT(8) +#define SPI_CMD_CPOL BIT(9) +#define SPI_CMD_RX_DMA BIT(10) +#define SPI_CMD_TX_DMA BIT(11) +#define SPI_CMD_TXMSBF BIT(12) +#define SPI_CMD_RXMSBF BIT(13) +#define SPI_CMD_RX_ENDIAN BIT(14) +#define SPI_CMD_TX_ENDIAN BIT(15) +#define SPI_CMD_FINISH_IE BIT(16) +#define SPI_CMD_PAUSE_IE BIT(17) +#define SPI_CMD_IPM_NONIDLE_MODE BIT(19) +#define SPI_CMD_IPM_SPIM_LOOP BIT(21) +#define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22 #define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22) -#define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2) -#define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3) -#define MT8173_SPI_MAX_PAD_SEL 3 -#define MTK_SPI_PAUSE_INT_STATUS 0x2 +#define PIN_MODE_CFG(x) ((x) / 2) -#define MTK_SPI_IDLE 0 -#define MTK_SPI_PAUSED 1 +#define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2) +#define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3) +#define SPI_CFG3_IPM_XMODE_EN BIT(4) +#define SPI_CFG3_IPM_NODATA_FLAG BIT(5) +#define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET 8 +#define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET 12 -#define MTK_SPI_MAX_FIFO_SIZE 32U -#define MTK_SPI_PACKET_SIZE 1024 -#define MTK_SPI_IPM_PACKET_SIZE SZ_64K -#define MTK_SPI_32BITS_MASK (0xffffffff) +#define SPI_CFG3_IPM_CMD_PIN_MODE_MASK GENMASK(1, 0) +#define SPI_CFG3_IPM_CMD_BYTELEN_MASK GENMASK(11, 8) +#define SPI_CFG3_IPM_ADDR_BYTELEN_MASK GENMASK(15, 12) -#define DMA_ADDR_EXT_BITS (36) -#define DMA_ADDR_DEF_BITS (32) +#define MT8173_SPI_MAX_PAD_SEL 3 +#define MTK_SPI_PAUSE_INT_STATUS 0x2 + +#define MTK_SPI_MAX_FIFO_SIZE 32U +#define MTK_SPI_PACKET_SIZE 1024 +#define MTK_SPI_IPM_PACKET_SIZE SZ_64K +#define MTK_SPI_IPM_PACKET_LOOP SZ_256 + +#define MTK_SPI_IDLE 0 +#define MTK_SPI_PAUSED 1 + +#define MTK_SPI_32BITS_MASK (0xffffffff) + +#define DMA_ADDR_EXT_BITS (36) +#define DMA_ADDR_DEF_BITS (32) + +/** + * struct mtk_spi_compatible - device data structure + * @need_pad_sel: Enable pad (pins) selection in SPI controller + * @must_tx: Must explicitly send dummy TX bytes to do RX only transfer + * @enhance_timing: Enable adjusting cfg register to enhance time accuracy + * @dma_ext: DMA address extension supported + * @no_need_unprepare: Don't unprepare the SPI clk during runtime + * @ipm_design: Adjust/extend registers to support IPM design IP features + */ struct mtk_spi_compatible { bool need_pad_sel; - /* Must explicitly send dummy Tx bytes to do Rx only transfer */ bool must_tx; - /* some IC design adjust cfg register to enhance time accuracy */ bool enhance_timing; - /* some IC support DMA addr extension */ bool dma_ext; - /* some IC no need unprepare SPI clk */ bool no_need_unprepare; - /* IPM design adjust and extend register to support more features */ bool ipm_design; - }; +/** + * struct mtk_spi - SPI driver instance + * @base: Start address of the SPI controller registers + * @state: SPI controller state + * @pad_num: Number of pad_sel entries + * @pad_sel: Groups of pins to select + * @parent_clk: Parent of sel_clk + * @sel_clk: SPI master mux clock + * @spi_clk: Peripheral clock + * @spi_hclk: AHB bus clock + * @cur_transfer: Currently processed SPI transfer + * @xfer_len: Number of bytes to transfer + * @num_xfered: Number of transferred bytes + * @tx_sgl: TX transfer scatterlist + * @rx_sgl: RX transfer scatterlist + * @tx_sgl_len: Size of TX DMA transfer + * @rx_sgl_len: Size of RX DMA transfer + * @dev_comp: Device data structure + * @spi_clk_hz: Current SPI clock in Hz + * @spimem_done: SPI-MEM operation completion + * @use_spimem: Enables SPI-MEM + * @dev: Device pointer + * @tx_dma: DMA start for SPI-MEM TX + * @rx_dma: DMA start for SPI-MEM RX + */ struct mtk_spi { void __iomem *base; u32 state; int pad_num; u32 *pad_sel; - struct clk *parent_clk, *sel_clk, *spi_clk; + struct clk *parent_clk, *sel_clk, *spi_clk, *spi_hclk; struct spi_transfer *cur_transfer; u32 xfer_len; u32 num_xfered; @@ -123,6 +166,11 @@ struct mtk_spi { u32 tx_sgl_len, rx_sgl_len; const struct mtk_spi_compatible *dev_comp; u32 spi_clk_hz; + struct completion spimem_done; + bool use_spimem; + struct device *dev; + dma_addr_t tx_dma; + dma_addr_t rx_dma; }; static const struct mtk_spi_compatible mtk_common_compat; @@ -704,6 +752,12 @@ static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) else mdata->state = MTK_SPI_IDLE; + /* SPI-MEM ops */ + if (mdata->use_spimem) { + complete(&mdata->spimem_done); + return IRQ_HANDLED; + } + if (!master->can_dma(master, NULL, trans)) { if (trans->rx_buf) { cnt = mdata->xfer_len / 4; @@ -787,21 +841,287 @@ static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } +static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem, + struct spi_mem_op *op) +{ + int opcode_len; + + if (op->data.dir != SPI_MEM_NO_DATA) { + opcode_len = 1 + op->addr.nbytes + op->dummy.nbytes; + if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { + op->data.nbytes = MTK_SPI_IPM_PACKET_SIZE - opcode_len; + /* force data buffer dma-aligned. */ + op->data.nbytes -= op->data.nbytes % 4; + } + } + + return 0; +} + +static bool mtk_spi_mem_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + if (!spi_mem_default_supports_op(mem, op)) + return false; + + if (op->addr.nbytes && op->dummy.nbytes && + op->addr.buswidth != op->dummy.buswidth) + return false; + + if (op->addr.nbytes + op->dummy.nbytes > 16) + return false; + + if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { + if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE > + MTK_SPI_IPM_PACKET_LOOP || + op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE != 0) + return false; + } + + return true; +} + +static void mtk_spi_mem_setup_dma_xfer(struct spi_master *master, + const struct spi_mem_op *op) +{ + struct mtk_spi *mdata = spi_master_get_devdata(master); + + writel((u32)(mdata->tx_dma & MTK_SPI_32BITS_MASK), + mdata->base + SPI_TX_SRC_REG); +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + if (mdata->dev_comp->dma_ext) + writel((u32)(mdata->tx_dma >> 32), + mdata->base + SPI_TX_SRC_REG_64); +#endif + + if (op->data.dir == SPI_MEM_DATA_IN) { + writel((u32)(mdata->rx_dma & MTK_SPI_32BITS_MASK), + mdata->base + SPI_RX_DST_REG); +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + if (mdata->dev_comp->dma_ext) + writel((u32)(mdata->rx_dma >> 32), + mdata->base + SPI_RX_DST_REG_64); +#endif + } +} + +static int mtk_spi_transfer_wait(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master); + /* + * For each byte we wait for 8 cycles of the SPI clock. + * Since speed is defined in Hz and we want milliseconds, + * so it should be 8 * 1000. + */ + u64 ms = 8000LL; + + if (op->data.dir == SPI_MEM_NO_DATA) + ms *= 32; /* prevent we may get 0 for short transfers. */ + else + ms *= op->data.nbytes; + ms = div_u64(ms, mem->spi->max_speed_hz); + ms += ms + 1000; /* 1s tolerance */ + + if (ms > UINT_MAX) + ms = UINT_MAX; + + if (!wait_for_completion_timeout(&mdata->spimem_done, + msecs_to_jiffies(ms))) { + dev_err(mdata->dev, "spi-mem transfer timeout\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int mtk_spi_mem_exec_op(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master); + u32 reg_val, nio, tx_size; + char *tx_tmp_buf, *rx_tmp_buf; + int ret = 0; + + mdata->use_spimem = true; + reinit_completion(&mdata->spimem_done); + + mtk_spi_reset(mdata); + mtk_spi_hw_init(mem->spi->master, mem->spi); + mtk_spi_prepare_transfer(mem->spi->master, mem->spi->max_speed_hz); + + reg_val = readl(mdata->base + SPI_CFG3_IPM_REG); + /* opcode byte len */ + reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK; + reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET; + + /* addr & dummy byte len */ + reg_val &= ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK; + if (op->addr.nbytes || op->dummy.nbytes) + reg_val |= (op->addr.nbytes + op->dummy.nbytes) << + SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET; + + /* data byte len */ + if (op->data.dir == SPI_MEM_NO_DATA) { + reg_val |= SPI_CFG3_IPM_NODATA_FLAG; + writel(0, mdata->base + SPI_CFG1_REG); + } else { + reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG; + mdata->xfer_len = op->data.nbytes; + mtk_spi_setup_packet(mem->spi->master); + } + + if (op->addr.nbytes || op->dummy.nbytes) { + if (op->addr.buswidth == 1 || op->dummy.buswidth == 1) + reg_val |= SPI_CFG3_IPM_XMODE_EN; + else + reg_val &= ~SPI_CFG3_IPM_XMODE_EN; + } + + if (op->addr.buswidth == 2 || + op->dummy.buswidth == 2 || + op->data.buswidth == 2) + nio = 2; + else if (op->addr.buswidth == 4 || + op->dummy.buswidth == 4 || + op->data.buswidth == 4) + nio = 4; + else + nio = 1; + + reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK; + reg_val |= PIN_MODE_CFG(nio); + + reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; + if (op->data.dir == SPI_MEM_DATA_IN) + reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; + else + reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR; + writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); + + tx_size = 1 + op->addr.nbytes + op->dummy.nbytes; + if (op->data.dir == SPI_MEM_DATA_OUT) + tx_size += op->data.nbytes; + + tx_size = max_t(u32, tx_size, 32); + + tx_tmp_buf = kzalloc(tx_size, GFP_KERNEL | GFP_DMA); + if (!tx_tmp_buf) { + mdata->use_spimem = false; + return -ENOMEM; + } + + tx_tmp_buf[0] = op->cmd.opcode; + + if (op->addr.nbytes) { + int i; + + for (i = 0; i < op->addr.nbytes; i++) + tx_tmp_buf[i + 1] = op->addr.val >> + (8 * (op->addr.nbytes - i - 1)); + } + + if (op->dummy.nbytes) + memset(tx_tmp_buf + op->addr.nbytes + 1, + 0xff, + op->dummy.nbytes); + + if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) + memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1, + op->data.buf.out, + op->data.nbytes); + + mdata->tx_dma = dma_map_single(mdata->dev, tx_tmp_buf, + tx_size, DMA_TO_DEVICE); + if (dma_mapping_error(mdata->dev, mdata->tx_dma)) { + ret = -ENOMEM; + goto err_exit; + } + + if (op->data.dir == SPI_MEM_DATA_IN) { + if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) { + rx_tmp_buf = kzalloc(op->data.nbytes, + GFP_KERNEL | GFP_DMA); + if (!rx_tmp_buf) { + ret = -ENOMEM; + goto unmap_tx_dma; + } + } else { + rx_tmp_buf = op->data.buf.in; + } + + mdata->rx_dma = dma_map_single(mdata->dev, + rx_tmp_buf, + op->data.nbytes, + DMA_FROM_DEVICE); + if (dma_mapping_error(mdata->dev, mdata->rx_dma)) { + ret = -ENOMEM; + goto kfree_rx_tmp_buf; + } + } + + reg_val = readl(mdata->base + SPI_CMD_REG); + reg_val |= SPI_CMD_TX_DMA; + if (op->data.dir == SPI_MEM_DATA_IN) + reg_val |= SPI_CMD_RX_DMA; + writel(reg_val, mdata->base + SPI_CMD_REG); + + mtk_spi_mem_setup_dma_xfer(mem->spi->master, op); + + mtk_spi_enable_transfer(mem->spi->master); + + /* Wait for the interrupt. */ + ret = mtk_spi_transfer_wait(mem, op); + if (ret) + goto unmap_rx_dma; + + /* spi disable dma */ + reg_val = readl(mdata->base + SPI_CMD_REG); + reg_val &= ~SPI_CMD_TX_DMA; + if (op->data.dir == SPI_MEM_DATA_IN) + reg_val &= ~SPI_CMD_RX_DMA; + writel(reg_val, mdata->base + SPI_CMD_REG); + +unmap_rx_dma: + if (op->data.dir == SPI_MEM_DATA_IN) { + dma_unmap_single(mdata->dev, mdata->rx_dma, + op->data.nbytes, DMA_FROM_DEVICE); + if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) + memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes); + } +kfree_rx_tmp_buf: + if (op->data.dir == SPI_MEM_DATA_IN && + !IS_ALIGNED((size_t)op->data.buf.in, 4)) + kfree(rx_tmp_buf); +unmap_tx_dma: + dma_unmap_single(mdata->dev, mdata->tx_dma, + tx_size, DMA_TO_DEVICE); +err_exit: + kfree(tx_tmp_buf); + mdata->use_spimem = false; + + return ret; +} + +static const struct spi_controller_mem_ops mtk_spi_mem_ops = { + .adjust_op_size = mtk_spi_mem_adjust_op_size, + .supports_op = mtk_spi_mem_supports_op, + .exec_op = mtk_spi_mem_exec_op, +}; + static int mtk_spi_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct spi_master *master; struct mtk_spi *mdata; - const struct of_device_id *of_id; int i, irq, ret, addr_bits; - master = spi_alloc_master(&pdev->dev, sizeof(*mdata)); - if (!master) { - dev_err(&pdev->dev, "failed to alloc spi master\n"); - return -ENOMEM; - } + master = devm_spi_alloc_master(dev, sizeof(*mdata)); + if (!master) + return dev_err_probe(dev, -ENOMEM, "failed to alloc spi master\n"); master->auto_runtime_pm = true; - master->dev.of_node = pdev->dev.of_node; + master->dev.of_node = dev->of_node; master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; master->set_cs = mtk_spi_set_cs; @@ -812,15 +1132,8 @@ static int mtk_spi_probe(struct platform_device *pdev) master->set_cs_timing = mtk_spi_set_hw_cs_timing; master->use_gpio_descriptors = true; - of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node); - if (!of_id) { - dev_err(&pdev->dev, "failed to probe of_node\n"); - ret = -EINVAL; - goto err_put_master; - } - mdata = spi_master_get_devdata(master); - mdata->dev_comp = of_id->data; + mdata->dev_comp = device_get_match_data(dev); if (mdata->dev_comp->enhance_timing) master->mode_bits |= SPI_CS_HIGH; @@ -830,143 +1143,122 @@ static int mtk_spi_probe(struct platform_device *pdev) if (mdata->dev_comp->ipm_design) master->mode_bits |= SPI_LOOP; + if (mdata->dev_comp->ipm_design) { + mdata->dev = dev; + master->mem_ops = &mtk_spi_mem_ops; + init_completion(&mdata->spimem_done); + } + if (mdata->dev_comp->need_pad_sel) { - mdata->pad_num = of_property_count_u32_elems( - pdev->dev.of_node, + mdata->pad_num = of_property_count_u32_elems(dev->of_node, "mediatek,pad-select"); - if (mdata->pad_num < 0) { - dev_err(&pdev->dev, + if (mdata->pad_num < 0) + return dev_err_probe(dev, -EINVAL, "No 'mediatek,pad-select' property\n"); - ret = -EINVAL; - goto err_put_master; - } - mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num, + mdata->pad_sel = devm_kmalloc_array(dev, mdata->pad_num, sizeof(u32), GFP_KERNEL); - if (!mdata->pad_sel) { - ret = -ENOMEM; - goto err_put_master; - } + if (!mdata->pad_sel) + return -ENOMEM; for (i = 0; i < mdata->pad_num; i++) { - of_property_read_u32_index(pdev->dev.of_node, + of_property_read_u32_index(dev->of_node, "mediatek,pad-select", i, &mdata->pad_sel[i]); - if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) { - dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n", - i, mdata->pad_sel[i]); - ret = -EINVAL; - goto err_put_master; - } + if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) + return dev_err_probe(dev, -EINVAL, + "wrong pad-sel[%d]: %u\n", + i, mdata->pad_sel[i]); } } platform_set_drvdata(pdev, master); mdata->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(mdata->base)) { - ret = PTR_ERR(mdata->base); - goto err_put_master; - } + if (IS_ERR(mdata->base)) + return PTR_ERR(mdata->base); irq = platform_get_irq(pdev, 0); - if (irq < 0) { - ret = irq; - goto err_put_master; - } + if (irq < 0) + return irq; - if (!pdev->dev.dma_mask) - pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; + if (!dev->dma_mask) + dev->dma_mask = &dev->coherent_dma_mask; - ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt, - IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master); - if (ret) { - dev_err(&pdev->dev, "failed to register irq (%d)\n", ret); - goto err_put_master; - } + ret = devm_request_irq(dev, irq, mtk_spi_interrupt, + IRQF_TRIGGER_NONE, dev_name(dev), master); + if (ret) + return dev_err_probe(dev, ret, "failed to register irq\n"); - mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk"); - if (IS_ERR(mdata->parent_clk)) { - ret = PTR_ERR(mdata->parent_clk); - dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret); - goto err_put_master; - } + mdata->parent_clk = devm_clk_get(dev, "parent-clk"); + if (IS_ERR(mdata->parent_clk)) + return dev_err_probe(dev, PTR_ERR(mdata->parent_clk), + "failed to get parent-clk\n"); - mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk"); - if (IS_ERR(mdata->sel_clk)) { - ret = PTR_ERR(mdata->sel_clk); - dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret); - goto err_put_master; - } + mdata->sel_clk = devm_clk_get(dev, "sel-clk"); + if (IS_ERR(mdata->sel_clk)) + return dev_err_probe(dev, PTR_ERR(mdata->sel_clk), "failed to get sel-clk\n"); - mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk"); - if (IS_ERR(mdata->spi_clk)) { - ret = PTR_ERR(mdata->spi_clk); - dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret); - goto err_put_master; - } + mdata->spi_clk = devm_clk_get(dev, "spi-clk"); + if (IS_ERR(mdata->spi_clk)) + return dev_err_probe(dev, PTR_ERR(mdata->spi_clk), "failed to get spi-clk\n"); - ret = clk_prepare_enable(mdata->spi_clk); - if (ret < 0) { - dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret); - goto err_put_master; - } + mdata->spi_hclk = devm_clk_get_optional(dev, "hclk"); + if (IS_ERR(mdata->spi_hclk)) + return dev_err_probe(dev, PTR_ERR(mdata->spi_hclk), "failed to get hclk\n"); ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to clk_set_parent\n"); + + ret = clk_prepare_enable(mdata->spi_hclk); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to enable hclk\n"); + + ret = clk_prepare_enable(mdata->spi_clk); if (ret < 0) { - dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret); - clk_disable_unprepare(mdata->spi_clk); - goto err_put_master; + clk_disable_unprepare(mdata->spi_hclk); + return dev_err_probe(dev, ret, "failed to enable spi_clk\n"); } mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk); - if (mdata->dev_comp->no_need_unprepare) + if (mdata->dev_comp->no_need_unprepare) { clk_disable(mdata->spi_clk); - else + clk_disable(mdata->spi_hclk); + } else { clk_disable_unprepare(mdata->spi_clk); - - pm_runtime_enable(&pdev->dev); + clk_disable_unprepare(mdata->spi_hclk); + } if (mdata->dev_comp->need_pad_sel) { - if (mdata->pad_num != master->num_chipselect) { - dev_err(&pdev->dev, + if (mdata->pad_num != master->num_chipselect) + return dev_err_probe(dev, -EINVAL, "pad_num does not match num_chipselect(%d != %d)\n", mdata->pad_num, master->num_chipselect); - ret = -EINVAL; - goto err_disable_runtime_pm; - } - if (!master->cs_gpiods && master->num_chipselect > 1) { - dev_err(&pdev->dev, + if (!master->cs_gpiods && master->num_chipselect > 1) + return dev_err_probe(dev, -EINVAL, "cs_gpios not specified and num_chipselect > 1\n"); - ret = -EINVAL; - goto err_disable_runtime_pm; - } } if (mdata->dev_comp->dma_ext) addr_bits = DMA_ADDR_EXT_BITS; else addr_bits = DMA_ADDR_DEF_BITS; - ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits)); + ret = dma_set_mask(dev, DMA_BIT_MASK(addr_bits)); if (ret) - dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n", + dev_notice(dev, "SPI dma_set_mask(%d) failed, ret:%d\n", addr_bits, ret); - ret = devm_spi_register_master(&pdev->dev, master); + pm_runtime_enable(dev); + + ret = devm_spi_register_master(dev, master); if (ret) { - dev_err(&pdev->dev, "failed to register master (%d)\n", ret); - goto err_disable_runtime_pm; + pm_runtime_disable(dev); + return dev_err_probe(dev, ret, "failed to register master\n"); } return 0; - -err_disable_runtime_pm: - pm_runtime_disable(&pdev->dev); -err_put_master: - spi_master_put(master); - - return ret; } static int mtk_spi_remove(struct platform_device *pdev) @@ -978,8 +1270,10 @@ static int mtk_spi_remove(struct platform_device *pdev) mtk_spi_reset(mdata); - if (mdata->dev_comp->no_need_unprepare) + if (mdata->dev_comp->no_need_unprepare) { clk_unprepare(mdata->spi_clk); + clk_unprepare(mdata->spi_hclk); + } return 0; } @@ -995,8 +1289,10 @@ static int mtk_spi_suspend(struct device *dev) if (ret) return ret; - if (!pm_runtime_suspended(dev)) + if (!pm_runtime_suspended(dev)) { clk_disable_unprepare(mdata->spi_clk); + clk_disable_unprepare(mdata->spi_hclk); + } return ret; } @@ -1013,11 +1309,20 @@ static int mtk_spi_resume(struct device *dev) dev_err(dev, "failed to enable spi_clk (%d)\n", ret); return ret; } + + ret = clk_prepare_enable(mdata->spi_hclk); + if (ret < 0) { + dev_err(dev, "failed to enable spi_hclk (%d)\n", ret); + clk_disable_unprepare(mdata->spi_clk); + return ret; + } } ret = spi_master_resume(master); - if (ret < 0) + if (ret < 0) { clk_disable_unprepare(mdata->spi_clk); + clk_disable_unprepare(mdata->spi_hclk); + } return ret; } @@ -1029,10 +1334,13 @@ static int mtk_spi_runtime_suspend(struct device *dev) struct spi_master *master = dev_get_drvdata(dev); struct mtk_spi *mdata = spi_master_get_devdata(master); - if (mdata->dev_comp->no_need_unprepare) + if (mdata->dev_comp->no_need_unprepare) { clk_disable(mdata->spi_clk); - else + clk_disable(mdata->spi_hclk); + } else { clk_disable_unprepare(mdata->spi_clk); + clk_disable_unprepare(mdata->spi_hclk); + } return 0; } @@ -1043,13 +1351,31 @@ static int mtk_spi_runtime_resume(struct device *dev) struct mtk_spi *mdata = spi_master_get_devdata(master); int ret; - if (mdata->dev_comp->no_need_unprepare) + if (mdata->dev_comp->no_need_unprepare) { ret = clk_enable(mdata->spi_clk); - else + if (ret < 0) { + dev_err(dev, "failed to enable spi_clk (%d)\n", ret); + return ret; + } + ret = clk_enable(mdata->spi_hclk); + if (ret < 0) { + dev_err(dev, "failed to enable spi_hclk (%d)\n", ret); + clk_disable(mdata->spi_clk); + return ret; + } + } else { ret = clk_prepare_enable(mdata->spi_clk); - if (ret < 0) { - dev_err(dev, "failed to enable spi_clk (%d)\n", ret); - return ret; + if (ret < 0) { + dev_err(dev, "failed to prepare_enable spi_clk (%d)\n", ret); + return ret; + } + + ret = clk_prepare_enable(mdata->spi_hclk); + if (ret < 0) { + dev_err(dev, "failed to prepare_enable spi_hclk (%d)\n", ret); + clk_disable_unprepare(mdata->spi_clk); + return ret; + } } return 0; diff --git a/drivers/spi/spi-mtk-nor.c b/drivers/spi/spi-mtk-nor.c index 94fb09696677..d167699a1a96 100644 --- a/drivers/spi/spi-mtk-nor.c +++ b/drivers/spi/spi-mtk-nor.c @@ -960,7 +960,17 @@ static int __maybe_unused mtk_nor_suspend(struct device *dev) static int __maybe_unused mtk_nor_resume(struct device *dev) { - return pm_runtime_force_resume(dev); + struct spi_controller *ctlr = dev_get_drvdata(dev); + struct mtk_nor *sp = spi_controller_get_devdata(ctlr); + int ret; + + ret = pm_runtime_force_resume(dev); + if (ret) + return ret; + + mtk_nor_init(sp); + + return 0; } static const struct dev_pm_ops mtk_nor_pm_ops = { diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index 55c092069301..65be8e085ab8 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -813,6 +813,7 @@ static int mxic_spi_probe(struct platform_device *pdev) if (ret) { dev_err(&pdev->dev, "spi_register_master failed\n"); pm_runtime_disable(&pdev->dev); + mxic_spi_mem_ecc_remove(mxic); } return ret; diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c index 435309b09227..55178579f3c6 100644 --- a/drivers/spi/spi-mxs.c +++ b/drivers/spi/spi-mxs.c @@ -605,9 +605,8 @@ static int mxs_spi_probe(struct platform_device *pdev) } } - ret = pm_runtime_get_sync(ssp->dev); + ret = pm_runtime_resume_and_get(ssp->dev); if (ret < 0) { - pm_runtime_put_noidle(ssp->dev); dev_err(ssp->dev, "runtime_get_sync failed\n"); goto out_pm_runtime_disable; } diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c index 60c9cdf1c94b..6c7ca588437f 100644 --- a/drivers/spi/spi-omap2-mcspi.c +++ b/drivers/spi/spi-omap2-mcspi.c @@ -246,9 +246,8 @@ static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable) enable = !enable; if (spi->controller_state) { - int err = pm_runtime_get_sync(mcspi->dev); + int err = pm_runtime_resume_and_get(mcspi->dev); if (err < 0) { - pm_runtime_put_noidle(mcspi->dev); dev_err(mcspi->dev, "failed to get sync: %d\n", err); return; } @@ -1068,9 +1067,8 @@ static int omap2_mcspi_setup(struct spi_device *spi) initial_setup = true; } - ret = pm_runtime_get_sync(mcspi->dev); + ret = pm_runtime_resume_and_get(mcspi->dev); if (ret < 0) { - pm_runtime_put_noidle(mcspi->dev); if (initial_setup) omap2_mcspi_cleanup(spi); @@ -1317,12 +1315,9 @@ static int omap2_mcspi_controller_setup(struct omap2_mcspi *mcspi) struct omap2_mcspi_regs *ctx = &mcspi->ctx; int ret = 0; - ret = pm_runtime_get_sync(mcspi->dev); - if (ret < 0) { - pm_runtime_put_noidle(mcspi->dev); - + ret = pm_runtime_resume_and_get(mcspi->dev); + if (ret < 0) return ret; - } mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, OMAP2_MCSPI_WAKEUPENABLE_WKEN); diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index cdc16eecaf6b..a08215eb9e14 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -196,6 +196,8 @@ struct rockchip_spi { bool slave_abort; bool cs_inactive; /* spi slave tansmition stop when cs inactive */ + bool cs_high_supported; /* native CS supports active-high polarity */ + struct spi_transfer *xfer; /* Store xfer temporarily */ }; @@ -719,6 +721,11 @@ static int rockchip_spi_setup(struct spi_device *spi) struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller); u32 cr0; + if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) { + dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n"); + return -EINVAL; + } + pm_runtime_get_sync(rs->dev); cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0); @@ -899,6 +906,7 @@ static int rockchip_spi_probe(struct platform_device *pdev) switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) { case ROCKCHIP_SPI_VER2_TYPE2: + rs->cs_high_supported = true; ctlr->mode_bits |= SPI_CS_HIGH; if (ctlr->can_dma && slave_mode) rs->cs_inactive = true; diff --git a/drivers/spi/spi-rpc-if.c b/drivers/spi/spi-rpc-if.c index fe82f3575df4..24ec1c83f379 100644 --- a/drivers/spi/spi-rpc-if.c +++ b/drivers/spi/spi-rpc-if.c @@ -158,14 +158,18 @@ static int rpcif_spi_probe(struct platform_device *pdev) error = rpcif_hw_init(rpc, false); if (error) - return error; + goto out_disable_rpm; error = spi_register_controller(ctlr); if (error) { dev_err(&pdev->dev, "spi_register_controller failed\n"); - rpcif_disable_rpm(rpc); + goto out_disable_rpm; } + return 0; + +out_disable_rpm: + rpcif_disable_rpm(rpc); return error; } diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c index bd5708d7e5a1..7a014eeec2d0 100644 --- a/drivers/spi/spi-rspi.c +++ b/drivers/spi/spi-rspi.c @@ -1108,14 +1108,11 @@ static struct dma_chan *rspi_request_dma_chan(struct device *dev, } memset(&cfg, 0, sizeof(cfg)); + cfg.dst_addr = port_addr + RSPI_SPDR; + cfg.src_addr = port_addr + RSPI_SPDR; + cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; + cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; cfg.direction = dir; - if (dir == DMA_MEM_TO_DEV) { - cfg.dst_addr = port_addr; - cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; - } else { - cfg.src_addr = port_addr; - cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; - } ret = dmaengine_slave_config(chan, &cfg); if (ret) { @@ -1146,12 +1143,12 @@ static int rspi_request_dma(struct device *dev, struct spi_controller *ctlr, } ctlr->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id, - res->start + RSPI_SPDR); + res->start); if (!ctlr->dma_tx) return -ENODEV; ctlr->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id, - res->start + RSPI_SPDR); + res->start); if (!ctlr->dma_rx) { dma_release_channel(ctlr->dma_tx); ctlr->dma_tx = NULL; diff --git a/drivers/spi/spi-sprd.c b/drivers/spi/spi-sprd.c index 28e70db9bbba..65b8075da4eb 100644 --- a/drivers/spi/spi-sprd.c +++ b/drivers/spi/spi-sprd.c @@ -1008,9 +1008,8 @@ static int sprd_spi_remove(struct platform_device *pdev) struct sprd_spi *ss = spi_controller_get_devdata(sctlr); int ret; - ret = pm_runtime_get_sync(ss->dev); + ret = pm_runtime_resume_and_get(ss->dev); if (ret < 0) { - pm_runtime_put_noidle(ss->dev); dev_err(ss->dev, "failed to resume SPI controller\n"); return ret; } diff --git a/drivers/spi/spi-stm32-qspi.c b/drivers/spi/spi-stm32-qspi.c index ffdc55f87e82..bf47a1452001 100644 --- a/drivers/spi/spi-stm32-qspi.c +++ b/drivers/spi/spi-stm32-qspi.c @@ -463,11 +463,9 @@ static int stm32_qspi_poll_status(struct spi_mem *mem, const struct spi_mem_op * if (!spi_mem_supports_op(mem, op)) return -EOPNOTSUPP; - ret = pm_runtime_get_sync(qspi->dev); - if (ret < 0) { - pm_runtime_put_noidle(qspi->dev); + ret = pm_runtime_resume_and_get(qspi->dev); + if (ret < 0) return ret; - } mutex_lock(&qspi->lock); @@ -490,11 +488,9 @@ static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master); int ret; - ret = pm_runtime_get_sync(qspi->dev); - if (ret < 0) { - pm_runtime_put_noidle(qspi->dev); + ret = pm_runtime_resume_and_get(qspi->dev); + if (ret < 0) return ret; - } mutex_lock(&qspi->lock); if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) @@ -536,11 +532,9 @@ static ssize_t stm32_qspi_dirmap_read(struct spi_mem_dirmap_desc *desc, u32 addr_max; int ret; - ret = pm_runtime_get_sync(qspi->dev); - if (ret < 0) { - pm_runtime_put_noidle(qspi->dev); + ret = pm_runtime_resume_and_get(qspi->dev); + if (ret < 0) return ret; - } mutex_lock(&qspi->lock); /* make a local copy of desc op_tmpl and complete dirmap rdesc @@ -583,11 +577,9 @@ static int stm32_qspi_setup(struct spi_device *spi) if (!spi->max_speed_hz) return -EINVAL; - ret = pm_runtime_get_sync(qspi->dev); - if (ret < 0) { - pm_runtime_put_noidle(qspi->dev); + ret = pm_runtime_resume_and_get(qspi->dev); + if (ret < 0) return ret; - } presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1; @@ -851,11 +843,9 @@ static int __maybe_unused stm32_qspi_resume(struct device *dev) pinctrl_pm_select_default_state(dev); - ret = pm_runtime_get_sync(dev); - if (ret < 0) { - pm_runtime_put_noidle(dev); + ret = pm_runtime_resume_and_get(dev); + if (ret < 0) return ret; - } writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR); writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR); diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c index a6adc20f6862..6fe617b445a5 100644 --- a/drivers/spi/spi-stm32.c +++ b/drivers/spi/spi-stm32.c @@ -2000,9 +2000,8 @@ static int __maybe_unused stm32_spi_resume(struct device *dev) return ret; } - ret = pm_runtime_get_sync(dev); + ret = pm_runtime_resume_and_get(dev); if (ret < 0) { - pm_runtime_put_noidle(dev); dev_err(dev, "Unable to power device:%d\n", ret); return ret; } diff --git a/drivers/spi/spi-sunplus-sp7021.c b/drivers/spi/spi-sunplus-sp7021.c index f989f7b99296..f1fa88777575 100644 --- a/drivers/spi/spi-sunplus-sp7021.c +++ b/drivers/spi/spi-sunplus-sp7021.c @@ -85,8 +85,6 @@ struct sp7021_spi_ctlr { int s_irq; struct clk *spi_clk; struct reset_control *rstc; - // irq spin lock - spinlock_t lock; // data xfer lock struct mutex buf_lock; struct completion isr_done; @@ -199,8 +197,6 @@ static irqreturn_t sp7021_spi_master_irq(int irq, void *dev) if (tx_len == 0 && total_len == 0) return IRQ_NONE; - spin_lock_irq(&pspim->lock); - rx_cnt = FIELD_GET(SP7021_RX_CNT_MASK, fd_status); if (fd_status & SP7021_RX_FULL_FLAG) rx_cnt = pspim->data_unit; @@ -239,7 +235,6 @@ static irqreturn_t sp7021_spi_master_irq(int irq, void *dev) if (isrdone) complete(&pspim->isr_done); - spin_unlock_irq(&pspim->lock); return IRQ_HANDLED; } @@ -446,7 +441,6 @@ static int sp7021_spi_controller_probe(struct platform_device *pdev) pspim->mode = mode; pspim->ctlr = ctlr; pspim->dev = dev; - spin_lock_init(&pspim->lock); mutex_init(&pspim->buf_lock); init_completion(&pspim->isr_done); init_completion(&pspim->slave_isr); diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 8f345247a8c3..d9be80e3e1bc 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -964,9 +964,8 @@ static int tegra_spi_setup(struct spi_device *spi) spi->controller_data = cdata; } - ret = pm_runtime_get_sync(tspi->dev); + ret = pm_runtime_resume_and_get(tspi->dev); if (ret < 0) { - pm_runtime_put_noidle(tspi->dev); dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); if (cdata) tegra_spi_cleanup(spi); @@ -1394,10 +1393,9 @@ static int tegra_spi_probe(struct platform_device *pdev) goto exit_pm_disable; } - ret = pm_runtime_get_sync(&pdev->dev); + ret = pm_runtime_resume_and_get(&pdev->dev); if (ret < 0) { dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret); - pm_runtime_put_noidle(&pdev->dev); goto exit_pm_disable; } @@ -1476,9 +1474,8 @@ static int tegra_spi_resume(struct device *dev) struct tegra_spi_data *tspi = spi_master_get_devdata(master); int ret; - ret = pm_runtime_get_sync(dev); + ret = pm_runtime_resume_and_get(dev); if (ret < 0) { - pm_runtime_put_noidle(dev); dev_err(dev, "pm runtime failed, e = %d\n", ret); return ret; } diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c index 2888d8a8dc6d..220ee08c4a06 100644 --- a/drivers/spi/spi-tegra20-sflash.c +++ b/drivers/spi/spi-tegra20-sflash.c @@ -486,10 +486,9 @@ static int tegra_sflash_probe(struct platform_device *pdev) goto exit_pm_disable; } - ret = pm_runtime_get_sync(&pdev->dev); + ret = pm_runtime_resume_and_get(&pdev->dev); if (ret < 0) { dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret); - pm_runtime_put_noidle(&pdev->dev); goto exit_pm_disable; } @@ -549,9 +548,8 @@ static int tegra_sflash_resume(struct device *dev) struct tegra_sflash_data *tsd = spi_master_get_devdata(master); int ret; - ret = pm_runtime_get_sync(dev); + ret = pm_runtime_resume_and_get(dev); if (ret < 0) { - pm_runtime_put_noidle(dev); dev_err(dev, "pm runtime failed, e = %d\n", ret); return ret; } diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c index 80c3787deea9..38360434d6e9 100644 --- a/drivers/spi/spi-tegra20-slink.c +++ b/drivers/spi/spi-tegra20-slink.c @@ -749,9 +749,8 @@ static int tegra_slink_setup(struct spi_device *spi) spi->mode & SPI_CPHA ? "" : "~", spi->max_speed_hz); - ret = pm_runtime_get_sync(tspi->dev); + ret = pm_runtime_resume_and_get(tspi->dev); if (ret < 0) { - pm_runtime_put_noidle(tspi->dev); dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); return ret; } @@ -1169,9 +1168,8 @@ static int tegra_slink_resume(struct device *dev) struct tegra_slink_data *tspi = spi_master_get_devdata(master); int ret; - ret = pm_runtime_get_sync(dev); + ret = pm_runtime_resume_and_get(dev); if (ret < 0) { - pm_runtime_put_noidle(dev); dev_err(dev, "pm runtime failed, e = %d\n", ret); return ret; } diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c index e06aafe169e0..b5b65d882d7a 100644 --- a/drivers/spi/spi-ti-qspi.c +++ b/drivers/spi/spi-ti-qspi.c @@ -172,9 +172,8 @@ static int ti_qspi_setup(struct spi_device *spi) dev_dbg(qspi->dev, "hz: %d, clock divider %d\n", qspi->spi_max_frequency, clk_div); - ret = pm_runtime_get_sync(qspi->dev); + ret = pm_runtime_resume_and_get(qspi->dev); if (ret < 0) { - pm_runtime_put_noidle(qspi->dev); dev_err(qspi->dev, "pm_runtime_get_sync() failed\n"); return ret; } @@ -448,6 +447,7 @@ static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst, enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; struct dma_async_tx_descriptor *tx; int ret; + unsigned long time_left; tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags); if (!tx) { @@ -467,9 +467,9 @@ static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst, } dma_async_issue_pending(chan); - ret = wait_for_completion_timeout(&qspi->transfer_complete, + time_left = wait_for_completion_timeout(&qspi->transfer_complete, msecs_to_jiffies(len)); - if (ret <= 0) { + if (time_left == 0) { dmaengine_terminate_sync(chan); dev_err(qspi->dev, "DMA wait_for_completion_timeout\n"); return -ETIMEDOUT; diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index c4dd1200fe99..136bd0e51ada 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -1130,11 +1130,15 @@ static int __spi_unmap_msg(struct spi_controller *ctlr, struct spi_message *msg) if (ctlr->dma_tx) tx_dev = ctlr->dma_tx->device->dev; + else if (ctlr->dma_map_dev) + tx_dev = ctlr->dma_map_dev; else tx_dev = ctlr->dev.parent; if (ctlr->dma_rx) rx_dev = ctlr->dma_rx->device->dev; + else if (ctlr->dma_map_dev) + rx_dev = ctlr->dma_map_dev; else rx_dev = ctlr->dev.parent; @@ -1607,9 +1611,8 @@ static void __spi_pump_messages(struct spi_controller *ctlr, bool in_kthread) mutex_lock(&ctlr->io_mutex); if (!was_busy && ctlr->auto_runtime_pm) { - ret = pm_runtime_get_sync(ctlr->dev.parent); + ret = pm_runtime_resume_and_get(ctlr->dev.parent); if (ret < 0) { - pm_runtime_put_noidle(ctlr->dev.parent); dev_err(&ctlr->dev, "Failed to power device: %d\n", ret); mutex_unlock(&ctlr->io_mutex); @@ -3470,7 +3473,7 @@ static int __spi_validate_bits_per_word(struct spi_controller *ctlr, int spi_setup(struct spi_device *spi) { unsigned bad_bits, ugly_bits; - int status; + int status = 0; /* * Check mode to prevent that any two of DUAL, QUAD and NO_MOSI/MISO @@ -3513,13 +3516,18 @@ int spi_setup(struct spi_device *spi) return -EINVAL; } - if (!spi->bits_per_word) + if (!spi->bits_per_word) { spi->bits_per_word = 8; - - status = __spi_validate_bits_per_word(spi->controller, - spi->bits_per_word); - if (status) - return status; + } else { + /* + * Some controllers may not support the default 8 bits-per-word + * so only perform the check when this is explicitly provided. + */ + status = __spi_validate_bits_per_word(spi->controller, + spi->bits_per_word); + if (status) + return status; + } if (spi->controller->max_speed_hz && (!spi->max_speed_hz || @@ -3539,10 +3547,9 @@ int spi_setup(struct spi_device *spi) } if (spi->controller->auto_runtime_pm && spi->controller->set_cs) { - status = pm_runtime_get_sync(spi->controller->dev.parent); + status = pm_runtime_resume_and_get(spi->controller->dev.parent); if (status < 0) { mutex_unlock(&spi->controller->io_mutex); - pm_runtime_put_noidle(spi->controller->dev.parent); dev_err(&spi->controller->dev, "Failed to power device: %d\n", status); return status; diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index 53a551714265..b2775d82d2d7 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -8,19 +8,18 @@ */ #include <linux/init.h> -#include <linux/module.h> #include <linux/ioctl.h> #include <linux/fs.h> #include <linux/device.h> #include <linux/err.h> #include <linux/list.h> #include <linux/errno.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> #include <linux/mutex.h> +#include <linux/property.h> #include <linux/slab.h> #include <linux/compat.h> -#include <linux/of.h> -#include <linux/of_device.h> -#include <linux/acpi.h> #include <linux/spi/spi.h> #include <linux/spi/spidev.h> @@ -46,6 +45,7 @@ static DECLARE_BITMAP(minors, N_SPI_MINORS); +static_assert(N_SPI_MINORS > 0 && N_SPI_MINORS <= 256); /* Bit masks for spi_device.mode management. Note that incorrect * settings for some settings can cause *lots* of trouble for other @@ -63,7 +63,8 @@ static DECLARE_BITMAP(minors, N_SPI_MINORS); | SPI_LSB_FIRST | SPI_3WIRE | SPI_LOOP \ | SPI_NO_CS | SPI_READY | SPI_TX_DUAL \ | SPI_TX_QUAD | SPI_TX_OCTAL | SPI_RX_DUAL \ - | SPI_RX_QUAD | SPI_RX_OCTAL) + | SPI_RX_QUAD | SPI_RX_OCTAL \ + | SPI_RX_CPHA_FLIP) struct spidev_data { dev_t devt; @@ -568,19 +569,20 @@ spidev_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) static int spidev_open(struct inode *inode, struct file *filp) { - struct spidev_data *spidev; + struct spidev_data *spidev = NULL, *iter; int status = -ENXIO; mutex_lock(&device_list_lock); - list_for_each_entry(spidev, &device_list, device_entry) { - if (spidev->devt == inode->i_rdev) { + list_for_each_entry(iter, &device_list, device_entry) { + if (iter->devt == inode->i_rdev) { status = 0; + spidev = iter; break; } } - if (status) { + if (!spidev) { pr_debug("spidev: nothing for minor %d\n", iminor(inode)); goto err_find_dev; } @@ -693,25 +695,38 @@ static const struct spi_device_id spidev_spi_ids[] = { }; MODULE_DEVICE_TABLE(spi, spidev_spi_ids); -#ifdef CONFIG_OF +/* + * spidev should never be referenced in DT without a specific compatible string, + * it is a Linux implementation thing rather than a description of the hardware. + */ +static int spidev_of_check(struct device *dev) +{ + if (device_property_match_string(dev, "compatible", "spidev") < 0) + return 0; + + dev_err(dev, "spidev listed directly in DT is not supported\n"); + return -EINVAL; +} + static const struct of_device_id spidev_dt_ids[] = { - { .compatible = "rohm,dh2228fv" }, - { .compatible = "lineartechnology,ltc2488" }, - { .compatible = "semtech,sx1301" }, - { .compatible = "lwn,bk4" }, - { .compatible = "dh,dhcom-board" }, - { .compatible = "menlo,m53cpld" }, - { .compatible = "cisco,spi-petra" }, - { .compatible = "micron,spi-authenta" }, + { .compatible = "rohm,dh2228fv", .data = &spidev_of_check }, + { .compatible = "lineartechnology,ltc2488", .data = &spidev_of_check }, + { .compatible = "semtech,sx1301", .data = &spidev_of_check }, + { .compatible = "lwn,bk4", .data = &spidev_of_check }, + { .compatible = "dh,dhcom-board", .data = &spidev_of_check }, + { .compatible = "menlo,m53cpld", .data = &spidev_of_check }, + { .compatible = "cisco,spi-petra", .data = &spidev_of_check }, + { .compatible = "micron,spi-authenta", .data = &spidev_of_check }, {}, }; MODULE_DEVICE_TABLE(of, spidev_dt_ids); -#endif - -#ifdef CONFIG_ACPI /* Dummy SPI devices not to be used in production systems */ -#define SPIDEV_ACPI_DUMMY 1 +static int spidev_acpi_check(struct device *dev) +{ + dev_warn(dev, "do not use this driver in production systems!\n"); + return 0; +} static const struct acpi_device_id spidev_acpi_ids[] = { /* @@ -720,51 +735,29 @@ static const struct acpi_device_id spidev_acpi_ids[] = { * description of the connected peripheral and they should also use * a proper driver instead of poking directly to the SPI bus. */ - { "SPT0001", SPIDEV_ACPI_DUMMY }, - { "SPT0002", SPIDEV_ACPI_DUMMY }, - { "SPT0003", SPIDEV_ACPI_DUMMY }, + { "SPT0001", (kernel_ulong_t)&spidev_acpi_check }, + { "SPT0002", (kernel_ulong_t)&spidev_acpi_check }, + { "SPT0003", (kernel_ulong_t)&spidev_acpi_check }, {}, }; MODULE_DEVICE_TABLE(acpi, spidev_acpi_ids); -static void spidev_probe_acpi(struct spi_device *spi) -{ - const struct acpi_device_id *id; - - if (!has_acpi_companion(&spi->dev)) - return; - - id = acpi_match_device(spidev_acpi_ids, &spi->dev); - if (WARN_ON(!id)) - return; - - if (id->driver_data == SPIDEV_ACPI_DUMMY) - dev_warn(&spi->dev, "do not use this driver in production systems!\n"); -} -#else -static inline void spidev_probe_acpi(struct spi_device *spi) {} -#endif - /*-------------------------------------------------------------------------*/ static int spidev_probe(struct spi_device *spi) { + int (*match)(struct device *dev); struct spidev_data *spidev; int status; unsigned long minor; - /* - * spidev should never be referenced in DT without a specific - * compatible string, it is a Linux implementation thing - * rather than a description of the hardware. - */ - if (spi->dev.of_node && of_device_is_compatible(spi->dev.of_node, "spidev")) { - dev_err(&spi->dev, "spidev listed directly in DT is not supported\n"); - return -EINVAL; + match = device_get_match_data(&spi->dev); + if (match) { + status = match(&spi->dev); + if (status) + return status; } - spidev_probe_acpi(spi); - /* Allocate driver data */ spidev = kzalloc(sizeof(*spidev), GFP_KERNEL); if (!spidev) @@ -832,8 +825,8 @@ static void spidev_remove(struct spi_device *spi) static struct spi_driver spidev_spi_driver = { .driver = { .name = "spidev", - .of_match_table = of_match_ptr(spidev_dt_ids), - .acpi_match_table = ACPI_PTR(spidev_acpi_ids), + .of_match_table = spidev_dt_ids, + .acpi_match_table = spidev_acpi_ids, }, .probe = spidev_probe, .remove = spidev_remove, @@ -856,7 +849,6 @@ static int __init spidev_init(void) * that will key udev/mdev to add/remove /dev nodes. Last, register * the driver which manages those device numbers. */ - BUILD_BUG_ON(N_SPI_MINORS > 256); status = register_chrdev(SPIDEV_MAJOR, "spi", &spidev_fops); if (status < 0) return status; |