diff options
Diffstat (limited to 'drivers/pinctrl')
60 files changed, 2564 insertions, 1455 deletions
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index 187abd7693cf..0c89647f166f 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -577,6 +577,8 @@ SS_PIN_DECL(N3, GPIOJ2, SGPMO); SIG_EXPR_LIST_DECL_SINGLE(SGPMI, SGPM, SIG_DESC_SET(SCU84, 11)); SS_PIN_DECL(N4, GPIOJ3, SGPMI); +FUNC_GROUP_DECL(SGPM, R2, L2, N3, N4); + #define N5 76 SIG_EXPR_LIST_DECL_SINGLE(VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12)); SIG_EXPR_LIST_DECL_SINGLE(DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8)); @@ -2127,6 +2129,7 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = { ASPEED_PINCTRL_GROUP(SD2), ASPEED_PINCTRL_GROUP(SDA1), ASPEED_PINCTRL_GROUP(SDA2), + ASPEED_PINCTRL_GROUP(SGPM), ASPEED_PINCTRL_GROUP(SGPS1), ASPEED_PINCTRL_GROUP(SGPS2), ASPEED_PINCTRL_GROUP(SIOONCTRL), @@ -2296,6 +2299,7 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = { ASPEED_PINCTRL_FUNC(SD2), ASPEED_PINCTRL_FUNC(SDA1), ASPEED_PINCTRL_FUNC(SDA2), + ASPEED_PINCTRL_FUNC(SGPM), ASPEED_PINCTRL_FUNC(SGPS1), ASPEED_PINCTRL_FUNC(SGPS2), ASPEED_PINCTRL_FUNC(SIOONCTRL), diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig index c8575399d6f7..331106274509 100644 --- a/drivers/pinctrl/bcm/Kconfig +++ b/drivers/pinctrl/bcm/Kconfig @@ -17,11 +17,15 @@ config PINCTRL_BCM281XX framework. GPIO is provided by a separate GPIO driver. config PINCTRL_BCM2835 - bool + bool "Broadcom BCM2835 GPIO (with PINCONF) driver" + depends on OF && (ARCH_BCM2835 || ARCH_BRCMSTB || COMPILE_TEST) select PINMUX select PINCONF select GENERIC_PINCONF select GPIOLIB_IRQCHIP + default ARCH_BCM2835 || ARCH_BRCMSTB + help + Say Y here to enable the Broadcom BCM2835 GPIO driver. config PINCTRL_IPROC_GPIO bool "Broadcom iProc GPIO (with PINCONF) driver" diff --git a/drivers/pinctrl/bcm/pinctrl-ns2-mux.c b/drivers/pinctrl/bcm/pinctrl-ns2-mux.c index 4b5cf0e0f16e..2bf6af7df7d9 100644 --- a/drivers/pinctrl/bcm/pinctrl-ns2-mux.c +++ b/drivers/pinctrl/bcm/pinctrl-ns2-mux.c @@ -1048,6 +1048,8 @@ static int ns2_pinmux_probe(struct platform_device *pdev) return PTR_ERR(pinctrl->base0); res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) + return -EINVAL; pinctrl->base1 = devm_ioremap_nocache(&pdev->dev, res->start, resource_size(res)); if (!pinctrl->base1) { diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index c6ff4d5fa482..e745788fa36f 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -99,7 +99,7 @@ EXPORT_SYMBOL_GPL(pinctrl_dev_get_drvdata); */ struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *devname) { - struct pinctrl_dev *pctldev = NULL; + struct pinctrl_dev *pctldev; if (!devname) return NULL; @@ -178,29 +178,6 @@ const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin) return desc->name; } -/** - * pin_is_valid() - check if pin exists on controller - * @pctldev: the pin control device to check the pin on - * @pin: pin to check, use the local pin controller index number - * - * This tells us whether a certain pin exist on a certain pin controller or - * not. Pin lists may be sparse, so some pins may not exist. - */ -bool pin_is_valid(struct pinctrl_dev *pctldev, int pin) -{ - struct pin_desc *pindesc; - - if (pin < 0) - return false; - - mutex_lock(&pctldev->mutex); - pindesc = pin_desc_get(pctldev, pin); - mutex_unlock(&pctldev->mutex); - - return pindesc != NULL; -} -EXPORT_SYMBOL_GPL(pin_is_valid); - /* Deletes a range of pin descriptors */ static void pinctrl_free_pindescs(struct pinctrl_dev *pctldev, const struct pinctrl_pin_desc *pins, @@ -312,7 +289,7 @@ static inline int gpio_to_pin(struct pinctrl_gpio_range *range, static struct pinctrl_gpio_range * pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio) { - struct pinctrl_gpio_range *range = NULL; + struct pinctrl_gpio_range *range; mutex_lock(&pctldev->mutex); /* Loop over the ranges */ @@ -392,7 +369,7 @@ static int pinctrl_get_device_gpio_range(unsigned gpio, struct pinctrl_dev **outdev, struct pinctrl_gpio_range **outrange) { - struct pinctrl_dev *pctldev = NULL; + struct pinctrl_dev *pctldev; mutex_lock(&pinctrldev_list_mutex); @@ -1216,6 +1193,15 @@ struct pinctrl_state *pinctrl_lookup_state(struct pinctrl *p, } EXPORT_SYMBOL_GPL(pinctrl_lookup_state); +static void pinctrl_link_add(struct pinctrl_dev *pctldev, + struct device *consumer) +{ + if (pctldev->desc->link_consumers) + device_link_add(consumer, pctldev->dev, + DL_FLAG_PM_RUNTIME | + DL_FLAG_AUTOREMOVE_CONSUMER); +} + /** * pinctrl_commit_state() - select/activate/program a pinctrl state to HW * @p: the pinctrl handle for the device that requests configuration @@ -1261,6 +1247,10 @@ static int pinctrl_commit_state(struct pinctrl *p, struct pinctrl_state *state) if (ret < 0) { goto unapply_new_state; } + + /* Do not link hogs (circular dependency) */ + if (p != setting->pctldev->p) + pinctrl_link_add(setting->pctldev, p->dev); } p->state = state; @@ -1666,7 +1656,7 @@ DEFINE_SHOW_ATTRIBUTE(pinctrl_groups); static int pinctrl_gpioranges_show(struct seq_file *s, void *what) { struct pinctrl_dev *pctldev = s->private; - struct pinctrl_gpio_range *range = NULL; + struct pinctrl_gpio_range *range; seq_puts(s, "GPIO ranges handled:\n"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8183.c b/drivers/pinctrl/mediatek/pinctrl-mt8183.c index 2c7409ed16fa..9a74d5025be6 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8183.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c @@ -583,6 +583,7 @@ static struct platform_driver mt8183_pinctrl_driver = { .driver = { .name = "mt8183-pinctrl", .of_match_table = mt8183_pinctrl_of_match, + .pm = &mtk_paris_pinctrl_pm_ops, }, .probe = mt8183_pinctrl_probe, }; diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index d3b34e9a7507..923264d0e9ef 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -926,3 +926,22 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, return 0; } + +static int mtk_paris_pinctrl_suspend(struct device *device) +{ + struct mtk_pinctrl *pctl = dev_get_drvdata(device); + + return mtk_eint_do_suspend(pctl->eint); +} + +static int mtk_paris_pinctrl_resume(struct device *device) +{ + struct mtk_pinctrl *pctl = dev_get_drvdata(device); + + return mtk_eint_do_resume(pctl->eint); +} + +const struct dev_pm_ops mtk_paris_pinctrl_pm_ops = { + .suspend_noirq = mtk_paris_pinctrl_suspend, + .resume_noirq = mtk_paris_pinctrl_resume, +}; diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.h b/drivers/pinctrl/mediatek/pinctrl-paris.h index 37146caa667d..3d43771074e6 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.h +++ b/drivers/pinctrl/mediatek/pinctrl-paris.h @@ -60,4 +60,6 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, const struct mtk_pin_soc *soc); +extern const struct dev_pm_ops mtk_paris_pinctrl_pm_ops; + #endif /* __PINCTRL_PARIS_H */ diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c index d494492e98e9..3475cd7bd2af 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c @@ -1304,28 +1304,28 @@ static struct meson_pmx_func meson_g12a_aobus_functions[] = { }; static struct meson_bank meson_g12a_periphs_banks[] = { - /* name first last irq pullen pull dir out in */ - BANK("Z", GPIOZ_0, GPIOZ_15, 12, 27, - 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), - BANK("H", GPIOH_0, GPIOH_8, 28, 36, - 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), - BANK("BOOT", BOOT_0, BOOT_15, 37, 52, - 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), - BANK("C", GPIOC_0, GPIOC_7, 53, 60, - 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), - BANK("A", GPIOA_0, GPIOA_15, 61, 76, - 5, 0, 5, 0, 16, 0, 17, 0, 18, 0), - BANK("X", GPIOX_0, GPIOX_19, 77, 96, - 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), + /* name first last irq pullen pull dir out in ds */ + BANK_DS("Z", GPIOZ_0, GPIOZ_15, 12, 27, + 4, 0, 4, 0, 12, 0, 13, 0, 14, 0, 5, 0), + BANK_DS("H", GPIOH_0, GPIOH_8, 28, 36, + 3, 0, 3, 0, 9, 0, 10, 0, 11, 0, 4, 0), + BANK_DS("BOOT", BOOT_0, BOOT_15, 37, 52, + 0, 0, 0, 0, 0, 0, 1, 0, 2, 0, 0, 0), + BANK_DS("C", GPIOC_0, GPIOC_7, 53, 60, + 1, 0, 1, 0, 3, 0, 4, 0, 5, 0, 1, 0), + BANK_DS("A", GPIOA_0, GPIOA_15, 61, 76, + 5, 0, 5, 0, 16, 0, 17, 0, 18, 0, 6, 0), + BANK_DS("X", GPIOX_0, GPIOX_19, 77, 96, + 2, 0, 2, 0, 6, 0, 7, 0, 8, 0, 2, 0), }; static struct meson_bank meson_g12a_aobus_banks[] = { - /* name first last irq pullen pull dir out in */ - BANK("AO", GPIOAO_0, GPIOAO_11, 0, 11, - 3, 0, 2, 0, 0, 0, 4, 0, 1, 0), + /* name first last irq pullen pull dir out in ds */ + BANK_DS("AO", GPIOAO_0, GPIOAO_11, 0, 11, 3, 0, 2, 0, 0, 0, 4, 0, 1, 0, + 0, 0), /* GPIOE actually located in the AO bank */ - BANK("E", GPIOE_0, GPIOE_2, 97, 99, - 3, 16, 2, 16, 0, 16, 4, 16, 1, 16), + BANK_DS("E", GPIOE_0, GPIOE_2, 97, 99, 3, 16, 2, 16, 0, 16, 4, 16, 1, + 16, 1, 0), }; static struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = { diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index 4edeb4cae72a..83c0b1753e70 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -1,15 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Pin controller and GPIO driver for Amlogic Meson GXBB. * * Copyright (C) 2016 Endless Mobile, Inc. * Author: Carlo Caione <carlo@endlessm.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <dt-bindings/gpio/meson-gxbb-gpio.h> diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c index 0c0a5018102b..813f2bdd90a5 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c @@ -1,15 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Pin controller and GPIO driver for Amlogic Meson GXL. * * Copyright (C) 2016 Endless Mobile, Inc. * Author: Carlo Caione <carlo@endlessm.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <dt-bindings/gpio/meson-gxl-gpio.h> diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 96a4a72708e4..df77a3e86a77 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -1,14 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Pin controller and GPIO driver for Amlogic Meson SoCs * * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ /* @@ -174,68 +168,223 @@ int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, return 0; } -static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, - unsigned long *configs, unsigned num_configs) +static int meson_pinconf_set_gpio_bit(struct meson_pinctrl *pc, + unsigned int pin, + unsigned int reg_type, + bool arg) { - struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); struct meson_bank *bank; - enum pin_config_param param; unsigned int reg, bit; - int i, ret; + int ret; + + ret = meson_get_bank(pc, pin, &bank); + if (ret) + return ret; + + meson_calc_reg_and_bit(bank, pin, reg_type, ®, &bit); + return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), + arg ? BIT(bit) : 0); +} + +static int meson_pinconf_get_gpio_bit(struct meson_pinctrl *pc, + unsigned int pin, + unsigned int reg_type) +{ + struct meson_bank *bank; + unsigned int reg, bit, val; + int ret; + + ret = meson_get_bank(pc, pin, &bank); + if (ret) + return ret; + + meson_calc_reg_and_bit(bank, pin, reg_type, ®, &bit); + ret = regmap_read(pc->reg_gpio, reg, &val); + if (ret) + return ret; + + return BIT(bit) & val ? 1 : 0; +} + +static int meson_pinconf_set_output(struct meson_pinctrl *pc, + unsigned int pin, + bool out) +{ + return meson_pinconf_set_gpio_bit(pc, pin, REG_DIR, !out); +} + +static int meson_pinconf_get_output(struct meson_pinctrl *pc, + unsigned int pin) +{ + int ret = meson_pinconf_get_gpio_bit(pc, pin, REG_DIR); + + if (ret < 0) + return ret; + + return !ret; +} + +static int meson_pinconf_set_drive(struct meson_pinctrl *pc, + unsigned int pin, + bool high) +{ + return meson_pinconf_set_gpio_bit(pc, pin, REG_OUT, high); +} + +static int meson_pinconf_get_drive(struct meson_pinctrl *pc, + unsigned int pin) +{ + return meson_pinconf_get_gpio_bit(pc, pin, REG_OUT); +} + +static int meson_pinconf_set_output_drive(struct meson_pinctrl *pc, + unsigned int pin, + bool high) +{ + int ret; + + ret = meson_pinconf_set_output(pc, pin, true); + if (ret) + return ret; + + return meson_pinconf_set_drive(pc, pin, high); +} + +static int meson_pinconf_disable_bias(struct meson_pinctrl *pc, + unsigned int pin) +{ + struct meson_bank *bank; + unsigned int reg, bit = 0; + int ret; + + ret = meson_get_bank(pc, pin, &bank); + if (ret) + return ret; + + meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); + ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), 0); + if (ret) + return ret; + + return 0; +} + +static int meson_pinconf_enable_bias(struct meson_pinctrl *pc, unsigned int pin, + bool pull_up) +{ + struct meson_bank *bank; + unsigned int reg, bit, val = 0; + int ret; + + ret = meson_get_bank(pc, pin, &bank); + if (ret) + return ret; + + meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); + if (pull_up) + val = BIT(bit); + + ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), val); + if (ret) + return ret; + + meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); + ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), BIT(bit)); + if (ret) + return ret; + + return 0; +} + +static int meson_pinconf_set_drive_strength(struct meson_pinctrl *pc, + unsigned int pin, + u16 drive_strength_ua) +{ + struct meson_bank *bank; + unsigned int reg, bit, ds_val; + int ret; + + if (!pc->reg_ds) { + dev_err(pc->dev, "drive-strength not supported\n"); + return -ENOTSUPP; + } ret = meson_get_bank(pc, pin, &bank); if (ret) return ret; + meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit); + bit = bit << 1; + + if (drive_strength_ua <= 500) { + ds_val = MESON_PINCONF_DRV_500UA; + } else if (drive_strength_ua <= 2500) { + ds_val = MESON_PINCONF_DRV_2500UA; + } else if (drive_strength_ua <= 3000) { + ds_val = MESON_PINCONF_DRV_3000UA; + } else if (drive_strength_ua <= 4000) { + ds_val = MESON_PINCONF_DRV_4000UA; + } else { + dev_warn_once(pc->dev, + "pin %u: invalid drive-strength : %d , default to 4mA\n", + pin, drive_strength_ua); + ds_val = MESON_PINCONF_DRV_4000UA; + } + + ret = regmap_update_bits(pc->reg_ds, reg, 0x3 << bit, ds_val << bit); + if (ret) + return ret; + + return 0; +} + +static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, + unsigned long *configs, unsigned num_configs) +{ + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); + enum pin_config_param param; + unsigned int arg = 0; + int i, ret; + for (i = 0; i < num_configs; i++) { param = pinconf_to_config_param(configs[i]); switch (param) { + case PIN_CONFIG_DRIVE_STRENGTH_UA: + case PIN_CONFIG_OUTPUT_ENABLE: + case PIN_CONFIG_OUTPUT: + arg = pinconf_to_config_argument(configs[i]); + break; + + default: + break; + } + + switch (param) { case PIN_CONFIG_BIAS_DISABLE: - dev_dbg(pc->dev, "pin %u: disable bias\n", pin); - - meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, - &bit); - ret = regmap_update_bits(pc->reg_pullen, reg, - BIT(bit), 0); - if (ret) - return ret; + ret = meson_pinconf_disable_bias(pc, pin); break; case PIN_CONFIG_BIAS_PULL_UP: - dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin); - - meson_calc_reg_and_bit(bank, pin, REG_PULLEN, - ®, &bit); - ret = regmap_update_bits(pc->reg_pullen, reg, - BIT(bit), BIT(bit)); - if (ret) - return ret; - - meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); - ret = regmap_update_bits(pc->reg_pull, reg, - BIT(bit), BIT(bit)); - if (ret) - return ret; + ret = meson_pinconf_enable_bias(pc, pin, true); break; case PIN_CONFIG_BIAS_PULL_DOWN: - dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin); - - meson_calc_reg_and_bit(bank, pin, REG_PULLEN, - ®, &bit); - ret = regmap_update_bits(pc->reg_pullen, reg, - BIT(bit), BIT(bit)); - if (ret) - return ret; - - meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); - ret = regmap_update_bits(pc->reg_pull, reg, - BIT(bit), 0); - if (ret) - return ret; + ret = meson_pinconf_enable_bias(pc, pin, false); + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + ret = meson_pinconf_set_drive_strength(pc, pin, arg); + break; + case PIN_CONFIG_OUTPUT_ENABLE: + ret = meson_pinconf_set_output(pc, pin, arg); + break; + case PIN_CONFIG_OUTPUT: + ret = meson_pinconf_set_output_drive(pc, pin, arg); break; default: - return -ENOTSUPP; + ret = -ENOTSUPP; } + + if (ret) + return ret; } return 0; @@ -275,12 +424,55 @@ static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) return conf; } +static int meson_pinconf_get_drive_strength(struct meson_pinctrl *pc, + unsigned int pin, + u16 *drive_strength_ua) +{ + struct meson_bank *bank; + unsigned int reg, bit; + unsigned int val; + int ret; + + if (!pc->reg_ds) + return -ENOTSUPP; + + ret = meson_get_bank(pc, pin, &bank); + if (ret) + return ret; + + meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit); + + ret = regmap_read(pc->reg_ds, reg, &val); + if (ret) + return ret; + + switch ((val >> bit) & 0x3) { + case MESON_PINCONF_DRV_500UA: + *drive_strength_ua = 500; + break; + case MESON_PINCONF_DRV_2500UA: + *drive_strength_ua = 2500; + break; + case MESON_PINCONF_DRV_3000UA: + *drive_strength_ua = 3000; + break; + case MESON_PINCONF_DRV_4000UA: + *drive_strength_ua = 4000; + break; + default: + return -EINVAL; + } + + return 0; +} + static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, unsigned long *config) { struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); enum pin_config_param param = pinconf_to_config_param(*config); u16 arg; + int ret; switch (param) { case PIN_CONFIG_BIAS_DISABLE: @@ -291,6 +483,29 @@ static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, else return -EINVAL; break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + ret = meson_pinconf_get_drive_strength(pc, pin, &arg); + if (ret) + return ret; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + ret = meson_pinconf_get_output(pc, pin); + if (ret <= 0) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_OUTPUT: + ret = meson_pinconf_get_output(pc, pin); + if (ret <= 0) + return -EINVAL; + + ret = meson_pinconf_get_drive(pc, pin); + if (ret < 0) + return -EINVAL; + + arg = ret; + break; + default: return -ENOTSUPP; } @@ -335,56 +550,19 @@ static const struct pinconf_ops meson_pinconf_ops = { static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) { - struct meson_pinctrl *pc = gpiochip_get_data(chip); - unsigned int reg, bit; - struct meson_bank *bank; - int ret; - - ret = meson_get_bank(pc, gpio, &bank); - if (ret) - return ret; - - meson_calc_reg_and_bit(bank, gpio, REG_DIR, ®, &bit); - - return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), BIT(bit)); + return meson_pinconf_set_output(gpiochip_get_data(chip), gpio, false); } static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) { - struct meson_pinctrl *pc = gpiochip_get_data(chip); - unsigned int reg, bit; - struct meson_bank *bank; - int ret; - - ret = meson_get_bank(pc, gpio, &bank); - if (ret) - return ret; - - meson_calc_reg_and_bit(bank, gpio, REG_DIR, ®, &bit); - ret = regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 0); - if (ret) - return ret; - - meson_calc_reg_and_bit(bank, gpio, REG_OUT, ®, &bit); - return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), - value ? BIT(bit) : 0); + return meson_pinconf_set_output_drive(gpiochip_get_data(chip), + gpio, value); } static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) { - struct meson_pinctrl *pc = gpiochip_get_data(chip); - unsigned int reg, bit; - struct meson_bank *bank; - int ret; - - ret = meson_get_bank(pc, gpio, &bank); - if (ret) - return; - - meson_calc_reg_and_bit(bank, gpio, REG_OUT, ®, &bit); - regmap_update_bits(pc->reg_gpio, reg, BIT(bit), - value ? BIT(bit) : 0); + meson_pinconf_set_drive(gpiochip_get_data(chip), gpio, value); } static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h index 5eaab925f427..b9abb493a6d9 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.h +++ b/drivers/pinctrl/meson/pinctrl-meson.h @@ -1,14 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Pin controller and GPIO driver for Amlogic Meson SoCs * * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <linux/gpio/driver.h> @@ -71,10 +65,21 @@ enum meson_reg_type { REG_DIR, REG_OUT, REG_IN, + REG_DS, NUM_REG, }; /** + * enum meson_pinconf_drv - value of drive-strength supported + */ +enum meson_pinconf_drv { + MESON_PINCONF_DRV_500UA, + MESON_PINCONF_DRV_2500UA, + MESON_PINCONF_DRV_3000UA, + MESON_PINCONF_DRV_4000UA, +}; + +/** * struct meson bank * * @name: bank name @@ -132,7 +137,8 @@ struct meson_pinctrl { .num_groups = ARRAY_SIZE(fn ## _groups), \ } -#define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ +#define BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, \ + dsr, dsb) \ { \ .name = n, \ .first = f, \ @@ -145,9 +151,13 @@ struct meson_pinctrl { [REG_DIR] = { dr, db }, \ [REG_OUT] = { or, ob }, \ [REG_IN] = { ir, ib }, \ + [REG_DS] = { dsr, dsb }, \ }, \ } +#define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ + BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, 0, 0) + #define MESON_PIN(x) PINCTRL_PIN(x, #x) /* Common pmx functions */ diff --git a/drivers/pinctrl/meson/pinctrl-meson8-pmx.c b/drivers/pinctrl/meson/pinctrl-meson8-pmx.c index b93b058c8a07..3810b066df16 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8-pmx.c +++ b/drivers/pinctrl/meson/pinctrl-meson8-pmx.c @@ -1,15 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * First generation of pinmux driver for Amlogic Meson SoCs * * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> * Copyright (C) 2017 Jerome Brunet <jbrunet@baylibre.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ /* For this first generation of pinctrl driver every pinmux group can be diff --git a/drivers/pinctrl/meson/pinctrl-meson8-pmx.h b/drivers/pinctrl/meson/pinctrl-meson8-pmx.h index 47293c28f913..47c0c28bb8fe 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8-pmx.h +++ b/drivers/pinctrl/meson/pinctrl-meson8-pmx.h @@ -1,15 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * First generation of pinmux driver for Amlogic Meson SoCs * * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> * Copyright (C) 2017 Jerome Brunet <jbrunet@baylibre.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ struct meson8_pmx_data { diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c index 785e29e74a56..2070e3c61a34 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8.c +++ b/drivers/pinctrl/meson/pinctrl-meson8.c @@ -1,14 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Pin controller and GPIO driver for Amlogic Meson8 and Meson8m2. * * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <dt-bindings/gpio/meson8-gpio.h> diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c index 7f76000cc12e..8d2d430ea02d 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8b.c +++ b/drivers/pinctrl/meson/pinctrl-meson8b.c @@ -1,15 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Pin controller and GPIO driver for Amlogic Meson8b. * * Copyright (C) 2015 Endless Mobile, Inc. * Author: Carlo Caione <carlo@endlessm.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <dt-bindings/gpio/meson8b-gpio.h> diff --git a/drivers/pinctrl/nomadik/Kconfig b/drivers/pinctrl/nomadik/Kconfig index c3efe7d7e91f..49c49fd6b853 100644 --- a/drivers/pinctrl/nomadik/Kconfig +++ b/drivers/pinctrl/nomadik/Kconfig @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + if ARCH_U8500 config PINCTRL_ABX500 diff --git a/drivers/pinctrl/nomadik/pinctrl-ab8500.c b/drivers/pinctrl/nomadik/pinctrl-ab8500.c index 0723627c7bc2..3106a21cd277 100644 --- a/drivers/pinctrl/nomadik/pinctrl-ab8500.c +++ b/drivers/pinctrl/nomadik/pinctrl-ab8500.c @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) ST-Ericsson SA 2012 * * Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <linux/kernel.h> diff --git a/drivers/pinctrl/nomadik/pinctrl-ab8505.c b/drivers/pinctrl/nomadik/pinctrl-ab8505.c index 2683509c1410..5e6e7d28390a 100644 --- a/drivers/pinctrl/nomadik/pinctrl-ab8505.c +++ b/drivers/pinctrl/nomadik/pinctrl-ab8505.c @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) ST-Ericsson SA 2012 * * Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <linux/kernel.h> diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c index 3d630a0544e1..c3595200e1e6 100644 --- a/drivers/pinctrl/nomadik/pinctrl-abx500.c +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c @@ -1,14 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) ST-Ericsson SA 2013 * * Author: Patrice Chotard <patrice.chotard@st.com> - * License terms: GNU General Public License (GPL) version 2 * * Driver allows to use AxB5xx unused pins to be used as GPIO - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <linux/kernel.h> #include <linux/types.h> diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index ec02739bd21b..ddd1f466d302 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Generic GPIO driver for logic cells found in the Nomadik SoC * @@ -5,10 +6,6 @@ * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <linux/kernel.h> #include <linux/init.h> diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index b4f7f8a458ea..d0cbdb1ad76a 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -39,6 +39,7 @@ static const struct pin_config_item conf_items[] = { PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL, false), PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL, false), PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH, "output drive strength", "mA", true), + PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH_UA, "output drive strength", "uA", true), PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec", true), PCONFDUMP(PIN_CONFIG_INPUT_ENABLE, "input enabled", NULL, false), PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL, false), @@ -167,6 +168,7 @@ static const struct pinconf_generic_params dt_params[] = { { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 }, { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 }, { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, + { "drive-strength-microamp", PIN_CONFIG_DRIVE_STRENGTH_UA, 0 }, { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, diff --git a/drivers/pinctrl/pinctrl-bm1880.c b/drivers/pinctrl/pinctrl-bm1880.c index 446b07d8fbfc..63b130cb1ffb 100644 --- a/drivers/pinctrl/pinctrl-bm1880.c +++ b/drivers/pinctrl/pinctrl-bm1880.c @@ -27,6 +27,7 @@ * @ngroups: Number of @groups * @funcs: Pinmux functions * @nfuncs: Number of @funcs + * @pconf: Pinconf data */ struct bm1880_pinctrl { void __iomem *base; @@ -35,6 +36,7 @@ struct bm1880_pinctrl { unsigned int ngroups; const struct bm1880_pinmux_function *funcs; unsigned int nfuncs; + const struct bm1880_pinconf_data *pinconf; }; /** @@ -55,7 +57,6 @@ struct bm1880_pctrl_group { * @groups: List of pingroups for this function. * @ngroups: Number of entries in @groups. * @mux_val: Selector for this function - * @mux_mask: Mask for function specific selector * @mux: Offset of function specific mux * @mux_shift: Shift for function specific selector */ @@ -64,11 +65,18 @@ struct bm1880_pinmux_function { const char * const *groups; unsigned int ngroups; u32 mux_val; - u32 mux_mask; u32 mux; u8 mux_shift; }; +/** + * struct bm1880_pinconf_data - pinconf data + * @drv_bits: Drive strength bit width + */ +struct bm1880_pinconf_data { + u32 drv_bits; +}; + static const struct pinctrl_pin_desc bm1880_pins[] = { PINCTRL_PIN(0, "MIO0"), PINCTRL_PIN(1, "MIO1"), @@ -636,165 +644,273 @@ static const char * const i2s1_group[] = { "i2s1_grp" }; static const char * const i2s1_mclkin_group[] = { "i2s1_mclkin_grp" }; static const char * const spi0_group[] = { "spi0_grp" }; -#define BM1880_PINMUX_FUNCTION(fname, mval, mask) \ +#define BM1880_PINMUX_FUNCTION(fname, mval) \ [F_##fname] = { \ .name = #fname, \ .groups = fname##_group, \ .ngroups = ARRAY_SIZE(fname##_group), \ .mux_val = mval, \ - .mux_mask = mask, \ } -#define BM1880_PINMUX_FUNCTION_MUX(fname, mval, mask, offset, shift)\ - [F_##fname] = { \ - .name = #fname, \ - .groups = fname##_group, \ - .ngroups = ARRAY_SIZE(fname##_group), \ - .mux_val = mval, \ - .mux_mask = mask, \ - .mux = offset, \ - .mux_shift = shift, \ +static const struct bm1880_pinmux_function bm1880_pmux_functions[] = { + BM1880_PINMUX_FUNCTION(nand, 2), + BM1880_PINMUX_FUNCTION(spi, 0), + BM1880_PINMUX_FUNCTION(emmc, 1), + BM1880_PINMUX_FUNCTION(sdio, 0), + BM1880_PINMUX_FUNCTION(eth0, 0), + BM1880_PINMUX_FUNCTION(pwm0, 2), + BM1880_PINMUX_FUNCTION(pwm1, 2), + BM1880_PINMUX_FUNCTION(pwm2, 2), + BM1880_PINMUX_FUNCTION(pwm3, 2), + BM1880_PINMUX_FUNCTION(pwm4, 2), + BM1880_PINMUX_FUNCTION(pwm5, 2), + BM1880_PINMUX_FUNCTION(pwm6, 2), + BM1880_PINMUX_FUNCTION(pwm7, 2), + BM1880_PINMUX_FUNCTION(pwm8, 2), + BM1880_PINMUX_FUNCTION(pwm9, 2), + BM1880_PINMUX_FUNCTION(pwm10, 2), + BM1880_PINMUX_FUNCTION(pwm11, 2), + BM1880_PINMUX_FUNCTION(pwm12, 2), + BM1880_PINMUX_FUNCTION(pwm13, 2), + BM1880_PINMUX_FUNCTION(pwm14, 2), + BM1880_PINMUX_FUNCTION(pwm15, 2), + BM1880_PINMUX_FUNCTION(pwm16, 2), + BM1880_PINMUX_FUNCTION(pwm17, 2), + BM1880_PINMUX_FUNCTION(pwm18, 2), + BM1880_PINMUX_FUNCTION(pwm19, 2), + BM1880_PINMUX_FUNCTION(pwm20, 2), + BM1880_PINMUX_FUNCTION(pwm21, 2), + BM1880_PINMUX_FUNCTION(pwm22, 2), + BM1880_PINMUX_FUNCTION(pwm23, 2), + BM1880_PINMUX_FUNCTION(pwm24, 2), + BM1880_PINMUX_FUNCTION(pwm25, 2), + BM1880_PINMUX_FUNCTION(pwm26, 2), + BM1880_PINMUX_FUNCTION(pwm27, 2), + BM1880_PINMUX_FUNCTION(pwm28, 2), + BM1880_PINMUX_FUNCTION(pwm29, 2), + BM1880_PINMUX_FUNCTION(pwm30, 2), + BM1880_PINMUX_FUNCTION(pwm31, 2), + BM1880_PINMUX_FUNCTION(pwm32, 2), + BM1880_PINMUX_FUNCTION(pwm33, 2), + BM1880_PINMUX_FUNCTION(pwm34, 2), + BM1880_PINMUX_FUNCTION(pwm35, 2), + BM1880_PINMUX_FUNCTION(pwm36, 2), + BM1880_PINMUX_FUNCTION(pwm37, 2), + BM1880_PINMUX_FUNCTION(i2c0, 1), + BM1880_PINMUX_FUNCTION(i2c1, 1), + BM1880_PINMUX_FUNCTION(i2c2, 1), + BM1880_PINMUX_FUNCTION(i2c3, 1), + BM1880_PINMUX_FUNCTION(i2c4, 1), + BM1880_PINMUX_FUNCTION(uart0, 3), + BM1880_PINMUX_FUNCTION(uart1, 3), + BM1880_PINMUX_FUNCTION(uart2, 3), + BM1880_PINMUX_FUNCTION(uart3, 3), + BM1880_PINMUX_FUNCTION(uart4, 1), + BM1880_PINMUX_FUNCTION(uart5, 1), + BM1880_PINMUX_FUNCTION(uart6, 1), + BM1880_PINMUX_FUNCTION(uart7, 1), + BM1880_PINMUX_FUNCTION(uart8, 1), + BM1880_PINMUX_FUNCTION(uart9, 1), + BM1880_PINMUX_FUNCTION(uart10, 1), + BM1880_PINMUX_FUNCTION(uart11, 1), + BM1880_PINMUX_FUNCTION(uart12, 3), + BM1880_PINMUX_FUNCTION(uart13, 3), + BM1880_PINMUX_FUNCTION(uart14, 3), + BM1880_PINMUX_FUNCTION(uart15, 3), + BM1880_PINMUX_FUNCTION(gpio0, 0), + BM1880_PINMUX_FUNCTION(gpio1, 0), + BM1880_PINMUX_FUNCTION(gpio2, 0), + BM1880_PINMUX_FUNCTION(gpio3, 0), + BM1880_PINMUX_FUNCTION(gpio4, 0), + BM1880_PINMUX_FUNCTION(gpio5, 0), + BM1880_PINMUX_FUNCTION(gpio6, 0), + BM1880_PINMUX_FUNCTION(gpio7, 0), + BM1880_PINMUX_FUNCTION(gpio8, 0), + BM1880_PINMUX_FUNCTION(gpio9, 0), + BM1880_PINMUX_FUNCTION(gpio10, 0), + BM1880_PINMUX_FUNCTION(gpio11, 0), + BM1880_PINMUX_FUNCTION(gpio12, 1), + BM1880_PINMUX_FUNCTION(gpio13, 1), + BM1880_PINMUX_FUNCTION(gpio14, 0), + BM1880_PINMUX_FUNCTION(gpio15, 0), + BM1880_PINMUX_FUNCTION(gpio16, 0), + BM1880_PINMUX_FUNCTION(gpio17, 0), + BM1880_PINMUX_FUNCTION(gpio18, 0), + BM1880_PINMUX_FUNCTION(gpio19, 0), + BM1880_PINMUX_FUNCTION(gpio20, 0), + BM1880_PINMUX_FUNCTION(gpio21, 0), + BM1880_PINMUX_FUNCTION(gpio22, 0), + BM1880_PINMUX_FUNCTION(gpio23, 0), + BM1880_PINMUX_FUNCTION(gpio24, 0), + BM1880_PINMUX_FUNCTION(gpio25, 0), + BM1880_PINMUX_FUNCTION(gpio26, 0), + BM1880_PINMUX_FUNCTION(gpio27, 0), + BM1880_PINMUX_FUNCTION(gpio28, 0), + BM1880_PINMUX_FUNCTION(gpio29, 0), + BM1880_PINMUX_FUNCTION(gpio30, 0), + BM1880_PINMUX_FUNCTION(gpio31, 0), + BM1880_PINMUX_FUNCTION(gpio32, 0), + BM1880_PINMUX_FUNCTION(gpio33, 0), + BM1880_PINMUX_FUNCTION(gpio34, 0), + BM1880_PINMUX_FUNCTION(gpio35, 0), + BM1880_PINMUX_FUNCTION(gpio36, 0), + BM1880_PINMUX_FUNCTION(gpio37, 0), + BM1880_PINMUX_FUNCTION(gpio38, 0), + BM1880_PINMUX_FUNCTION(gpio39, 0), + BM1880_PINMUX_FUNCTION(gpio40, 0), + BM1880_PINMUX_FUNCTION(gpio41, 0), + BM1880_PINMUX_FUNCTION(gpio42, 0), + BM1880_PINMUX_FUNCTION(gpio43, 0), + BM1880_PINMUX_FUNCTION(gpio44, 0), + BM1880_PINMUX_FUNCTION(gpio45, 0), + BM1880_PINMUX_FUNCTION(gpio46, 0), + BM1880_PINMUX_FUNCTION(gpio47, 0), + BM1880_PINMUX_FUNCTION(gpio48, 0), + BM1880_PINMUX_FUNCTION(gpio49, 0), + BM1880_PINMUX_FUNCTION(gpio50, 0), + BM1880_PINMUX_FUNCTION(gpio51, 0), + BM1880_PINMUX_FUNCTION(gpio52, 0), + BM1880_PINMUX_FUNCTION(gpio53, 0), + BM1880_PINMUX_FUNCTION(gpio54, 0), + BM1880_PINMUX_FUNCTION(gpio55, 0), + BM1880_PINMUX_FUNCTION(gpio56, 0), + BM1880_PINMUX_FUNCTION(gpio57, 0), + BM1880_PINMUX_FUNCTION(gpio58, 0), + BM1880_PINMUX_FUNCTION(gpio59, 0), + BM1880_PINMUX_FUNCTION(gpio60, 0), + BM1880_PINMUX_FUNCTION(gpio61, 0), + BM1880_PINMUX_FUNCTION(gpio62, 0), + BM1880_PINMUX_FUNCTION(gpio63, 0), + BM1880_PINMUX_FUNCTION(gpio64, 0), + BM1880_PINMUX_FUNCTION(gpio65, 0), + BM1880_PINMUX_FUNCTION(gpio66, 0), + BM1880_PINMUX_FUNCTION(gpio67, 0), + BM1880_PINMUX_FUNCTION(eth1, 1), + BM1880_PINMUX_FUNCTION(i2s0, 2), + BM1880_PINMUX_FUNCTION(i2s0_mclkin, 1), + BM1880_PINMUX_FUNCTION(i2s1, 2), + BM1880_PINMUX_FUNCTION(i2s1_mclkin, 1), + BM1880_PINMUX_FUNCTION(spi0, 1), +}; + +#define BM1880_PINCONF_DAT(_width) \ + { \ + .drv_bits = _width, \ } -static const struct bm1880_pinmux_function bm1880_pmux_functions[] = { - BM1880_PINMUX_FUNCTION(nand, 2, 0x03), - BM1880_PINMUX_FUNCTION(spi, 0, 0x03), - BM1880_PINMUX_FUNCTION(emmc, 1, 0x03), - BM1880_PINMUX_FUNCTION(sdio, 0, 0x03), - BM1880_PINMUX_FUNCTION(eth0, 0, 0x03), - BM1880_PINMUX_FUNCTION_MUX(pwm0, 2, 0x0F, 0x50, 0x00), - BM1880_PINMUX_FUNCTION_MUX(pwm1, 2, 0x0F, 0x50, 0x04), - BM1880_PINMUX_FUNCTION_MUX(pwm2, 2, 0x0F, 0x50, 0x08), - BM1880_PINMUX_FUNCTION_MUX(pwm3, 2, 0x0F, 0x50, 0x0C), - BM1880_PINMUX_FUNCTION_MUX(pwm4, 2, 0x0F, 0x50, 0x10), - BM1880_PINMUX_FUNCTION_MUX(pwm5, 2, 0x0F, 0x50, 0x14), - BM1880_PINMUX_FUNCTION_MUX(pwm6, 2, 0x0F, 0x50, 0x18), - BM1880_PINMUX_FUNCTION_MUX(pwm7, 2, 0x0F, 0x50, 0x1C), - BM1880_PINMUX_FUNCTION_MUX(pwm8, 2, 0x0F, 0x54, 0x00), - BM1880_PINMUX_FUNCTION_MUX(pwm9, 2, 0x0F, 0x54, 0x04), - BM1880_PINMUX_FUNCTION_MUX(pwm10, 2, 0x0F, 0x54, 0x08), - BM1880_PINMUX_FUNCTION_MUX(pwm11, 2, 0x0F, 0x54, 0x0C), - BM1880_PINMUX_FUNCTION_MUX(pwm12, 2, 0x0F, 0x54, 0x10), - BM1880_PINMUX_FUNCTION_MUX(pwm13, 2, 0x0F, 0x54, 0x14), - BM1880_PINMUX_FUNCTION_MUX(pwm14, 2, 0x0F, 0x54, 0x18), - BM1880_PINMUX_FUNCTION_MUX(pwm15, 2, 0x0F, 0x54, 0x1C), - BM1880_PINMUX_FUNCTION_MUX(pwm16, 2, 0x0F, 0x58, 0x00), - BM1880_PINMUX_FUNCTION_MUX(pwm17, 2, 0x0F, 0x58, 0x04), - BM1880_PINMUX_FUNCTION_MUX(pwm18, 2, 0x0F, 0x58, 0x08), - BM1880_PINMUX_FUNCTION_MUX(pwm19, 2, 0x0F, 0x58, 0x0C), - BM1880_PINMUX_FUNCTION_MUX(pwm20, 2, 0x0F, 0x58, 0x10), - BM1880_PINMUX_FUNCTION_MUX(pwm21, 2, 0x0F, 0x58, 0x14), - BM1880_PINMUX_FUNCTION_MUX(pwm22, 2, 0x0F, 0x58, 0x18), - BM1880_PINMUX_FUNCTION_MUX(pwm23, 2, 0x0F, 0x58, 0x1C), - BM1880_PINMUX_FUNCTION_MUX(pwm24, 2, 0x0F, 0x5C, 0x00), - BM1880_PINMUX_FUNCTION_MUX(pwm25, 2, 0x0F, 0x5C, 0x04), - BM1880_PINMUX_FUNCTION_MUX(pwm26, 2, 0x0F, 0x5C, 0x08), - BM1880_PINMUX_FUNCTION_MUX(pwm27, 2, 0x0F, 0x5C, 0x0C), - BM1880_PINMUX_FUNCTION_MUX(pwm28, 2, 0x0F, 0x5C, 0x10), - BM1880_PINMUX_FUNCTION_MUX(pwm29, 2, 0x0F, 0x5C, 0x14), - BM1880_PINMUX_FUNCTION_MUX(pwm30, 2, 0x0F, 0x5C, 0x18), - BM1880_PINMUX_FUNCTION_MUX(pwm31, 2, 0x0F, 0x5C, 0x1C), - BM1880_PINMUX_FUNCTION_MUX(pwm32, 2, 0x0F, 0x60, 0x00), - BM1880_PINMUX_FUNCTION_MUX(pwm33, 2, 0x0F, 0x60, 0x04), - BM1880_PINMUX_FUNCTION_MUX(pwm34, 2, 0x0F, 0x60, 0x08), - BM1880_PINMUX_FUNCTION_MUX(pwm35, 2, 0x0F, 0x60, 0x0C), - BM1880_PINMUX_FUNCTION_MUX(pwm36, 2, 0x0F, 0x60, 0x10), - BM1880_PINMUX_FUNCTION_MUX(pwm37, 2, 0x0F, 0x60, 0x1C), - BM1880_PINMUX_FUNCTION(i2c0, 1, 0x03), - BM1880_PINMUX_FUNCTION(i2c1, 1, 0x03), - BM1880_PINMUX_FUNCTION(i2c2, 1, 0x03), - BM1880_PINMUX_FUNCTION(i2c3, 1, 0x03), - BM1880_PINMUX_FUNCTION(i2c4, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart0, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart1, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart2, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart3, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart4, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart5, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart6, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart7, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart8, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart9, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart10, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart11, 1, 0x03), - BM1880_PINMUX_FUNCTION(uart12, 3, 0x03), - BM1880_PINMUX_FUNCTION(uart13, 3, 0x03), - BM1880_PINMUX_FUNCTION(uart14, 3, 0x03), - BM1880_PINMUX_FUNCTION(uart15, 3, 0x03), - BM1880_PINMUX_FUNCTION_MUX(gpio0, 0, 0x03, 0x4E0, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio1, 0, 0x03, 0x4E4, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio2, 0, 0x03, 0x4E4, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio3, 0, 0x03, 0x4E8, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio4, 0, 0x03, 0x4E8, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio5, 0, 0x03, 0x4EC, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio6, 0, 0x03, 0x4EC, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio7, 0, 0x03, 0x4F0, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio8, 0, 0x03, 0x4F0, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio9, 0, 0x03, 0x4F4, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio10, 0, 0x03, 0x4F4, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio11, 0, 0x03, 0x4F8, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio12, 1, 0x03, 0x4F8, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio13, 1, 0x03, 0x4FC, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio14, 0, 0x03, 0x474, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio15, 0, 0x03, 0x478, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio16, 0, 0x03, 0x478, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio17, 0, 0x03, 0x47C, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio18, 0, 0x03, 0x47C, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio19, 0, 0x03, 0x480, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio20, 0, 0x03, 0x480, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio21, 0, 0x03, 0x484, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio22, 0, 0x03, 0x484, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio23, 0, 0x03, 0x488, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio24, 0, 0x03, 0x488, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio25, 0, 0x03, 0x48C, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio26, 0, 0x03, 0x48C, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio27, 0, 0x03, 0x490, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio28, 0, 0x03, 0x490, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio29, 0, 0x03, 0x494, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio30, 0, 0x03, 0x494, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio31, 0, 0x03, 0x498, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio32, 0, 0x03, 0x498, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio33, 0, 0x03, 0x49C, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio34, 0, 0x03, 0x49C, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio35, 0, 0x03, 0x4A0, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio36, 0, 0x03, 0x4A0, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio37, 0, 0x03, 0x4A4, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio38, 0, 0x03, 0x4A4, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio39, 0, 0x03, 0x4A8, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio40, 0, 0x03, 0x4A8, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio41, 0, 0x03, 0x4AC, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio42, 0, 0x03, 0x4AC, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio43, 0, 0x03, 0x4B0, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio44, 0, 0x03, 0x4B0, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio45, 0, 0x03, 0x4B4, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio46, 0, 0x03, 0x4B4, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio47, 0, 0x03, 0x4B8, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio48, 0, 0x03, 0x4B8, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio49, 0, 0x03, 0x4BC, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio50, 0, 0x03, 0x4BC, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio51, 0, 0x03, 0x4C0, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio52, 0, 0x03, 0x4C0, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio53, 0, 0x03, 0x4C4, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio54, 0, 0x03, 0x4C4, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio55, 0, 0x03, 0x4C8, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio56, 0, 0x03, 0x4C8, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio57, 0, 0x03, 0x4CC, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio58, 0, 0x03, 0x4CC, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio59, 0, 0x03, 0x4D0, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio60, 0, 0x03, 0x4D0, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio61, 0, 0x03, 0x4D4, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio62, 0, 0x03, 0x4D4, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio63, 0, 0x03, 0x4D8, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio64, 0, 0x03, 0x4D8, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio65, 0, 0x03, 0x4DC, 0x04), - BM1880_PINMUX_FUNCTION_MUX(gpio66, 0, 0x03, 0x4DC, 0x14), - BM1880_PINMUX_FUNCTION_MUX(gpio67, 0, 0x03, 0x4E0, 0x04), - BM1880_PINMUX_FUNCTION(eth1, 1, 0x03), - BM1880_PINMUX_FUNCTION(i2s0, 2, 0x03), - BM1880_PINMUX_FUNCTION(i2s0_mclkin, 1, 0x03), - BM1880_PINMUX_FUNCTION(i2s1, 2, 0x03), - BM1880_PINMUX_FUNCTION(i2s1_mclkin, 1, 0x03), - BM1880_PINMUX_FUNCTION(spi0, 1, 0x03), +static const struct bm1880_pinconf_data bm1880_pinconf[] = { + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), }; static int bm1880_pctrl_get_groups_count(struct pinctrl_dev *pctldev) @@ -870,33 +986,308 @@ static int bm1880_pinmux_set_mux(struct pinctrl_dev *pctldev, const struct bm1880_pinmux_function *func = &pctrl->funcs[function]; int i; - if (func->mux) { + for (i = 0; i < pgrp->npins; i++) { + unsigned int pin = pgrp->pins[i]; + u32 offset = (pin >> 1) << 2; + u32 mux_offset = ((!((pin + 1) & 1) << 4) + 4); u32 regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + - func->mux); + offset); + + regval &= ~(0x03 << mux_offset); + regval |= func->mux_val << mux_offset; + + writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset); + } + + return 0; +} + +#define BM1880_PINCONF(pin, idx) ((!((pin + 1) & 1) << 4) + idx) +#define BM1880_PINCONF_PULLCTRL(pin) BM1880_PINCONF(pin, 0) +#define BM1880_PINCONF_PULLUP(pin) BM1880_PINCONF(pin, 1) +#define BM1880_PINCONF_PULLDOWN(pin) BM1880_PINCONF(pin, 2) +#define BM1880_PINCONF_DRV(pin) BM1880_PINCONF(pin, 6) +#define BM1880_PINCONF_SCHMITT(pin) BM1880_PINCONF(pin, 9) +#define BM1880_PINCONF_SLEW(pin) BM1880_PINCONF(pin, 10) + +static int bm1880_pinconf_drv_set(unsigned int mA, u32 width, + u32 *regval, u32 bit_offset) +{ + u32 _regval; + + _regval = *regval; + + /* + * There are two sets of drive strength bit width exposed by the + * SoC at 4mA step, hence we need to handle them separately. + */ + if (width == 0x03) { + switch (mA) { + case 4: + _regval &= ~(width << bit_offset); + _regval |= (0 << bit_offset); + break; + case 8: + _regval &= ~(width << bit_offset); + _regval |= (1 << bit_offset); + break; + case 12: + _regval &= ~(width << bit_offset); + _regval |= (2 << bit_offset); + break; + case 16: + _regval &= ~(width << bit_offset); + _regval |= (3 << bit_offset); + break; + case 20: + _regval &= ~(width << bit_offset); + _regval |= (4 << bit_offset); + break; + case 24: + _regval &= ~(width << bit_offset); + _regval |= (5 << bit_offset); + break; + case 28: + _regval &= ~(width << bit_offset); + _regval |= (6 << bit_offset); + break; + case 32: + _regval &= ~(width << bit_offset); + _regval |= (7 << bit_offset); + break; + default: + return -EINVAL; + } + } else { + switch (mA) { + case 4: + _regval &= ~(width << bit_offset); + _regval |= (0 << bit_offset); + break; + case 8: + _regval &= ~(width << bit_offset); + _regval |= (1 << bit_offset); + break; + case 12: + _regval &= ~(width << bit_offset); + _regval |= (2 << bit_offset); + break; + case 16: + _regval &= ~(width << bit_offset); + _regval |= (3 << bit_offset); + break; + default: + return -EINVAL; + } + } + + *regval = _regval; + + return 0; +} + +static int bm1880_pinconf_drv_get(u32 width, u32 drv) +{ + int ret = -ENOTSUPP; - regval &= ~(func->mux_mask << func->mux_shift); - regval |= func->mux_val << func->mux_shift; - writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + - func->mux); + /* + * There are two sets of drive strength bit width exposed by the + * SoC at 4mA step, hence we need to handle them separately. + */ + if (width == 0x03) { + switch (drv) { + case 0: + ret = 4; + break; + case 1: + ret = 8; + break; + case 2: + ret = 12; + break; + case 3: + ret = 16; + break; + case 4: + ret = 20; + break; + case 5: + ret = 24; + break; + case 6: + ret = 28; + break; + case 7: + ret = 32; + break; + default: + break; + } } else { - for (i = 0; i < pgrp->npins; i++) { - unsigned int pin = pgrp->pins[i]; - u32 offset = (pin >> 1) << 2; - u32 mux_offset = ((!((pin + 1) & 1) << 4) + 4); - u32 regval = readl_relaxed(pctrl->base + - BM1880_REG_MUX + offset); - - regval &= ~(func->mux_mask << mux_offset); - regval |= func->mux_val << mux_offset; - - writel_relaxed(regval, pctrl->base + - BM1880_REG_MUX + offset); + switch (drv) { + case 0: + ret = 4; + break; + case 1: + ret = 8; + break; + case 2: + ret = 12; + break; + case 3: + ret = 16; + break; + default: + break; + } + } + + return ret; +} + +static int bm1880_pinconf_cfg_get(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *config) +{ + struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned int param = pinconf_to_config_param(*config); + unsigned int arg = 0; + u32 regval, offset, bit_offset; + int ret; + + offset = (pin >> 1) << 2; + regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + bit_offset = BM1880_PINCONF_PULLUP(pin); + arg = !!(regval & BIT(bit_offset)); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + bit_offset = BM1880_PINCONF_PULLDOWN(pin); + arg = !!(regval & BIT(bit_offset)); + break; + case PIN_CONFIG_BIAS_DISABLE: + bit_offset = BM1880_PINCONF_PULLCTRL(pin); + arg = !!(regval & BIT(bit_offset)); + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + bit_offset = BM1880_PINCONF_SCHMITT(pin); + arg = !!(regval & BIT(bit_offset)); + break; + case PIN_CONFIG_SLEW_RATE: + bit_offset = BM1880_PINCONF_SLEW(pin); + arg = !!(regval & BIT(bit_offset)); + break; + case PIN_CONFIG_DRIVE_STRENGTH: + bit_offset = BM1880_PINCONF_DRV(pin); + ret = bm1880_pinconf_drv_get(pctrl->pinconf[pin].drv_bits, + !!(regval & BIT(bit_offset))); + if (ret < 0) + return ret; + + arg = ret; + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int bm1880_pinconf_cfg_set(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *configs, + unsigned int num_configs) +{ + struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + u32 regval, offset, bit_offset; + int i, ret; + + offset = (pin >> 1) << 2; + regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset); + + for (i = 0; i < num_configs; i++) { + unsigned int param = pinconf_to_config_param(configs[i]); + unsigned int arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + bit_offset = BM1880_PINCONF_PULLUP(pin); + regval |= BIT(bit_offset); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + bit_offset = BM1880_PINCONF_PULLDOWN(pin); + regval |= BIT(bit_offset); + break; + case PIN_CONFIG_BIAS_DISABLE: + bit_offset = BM1880_PINCONF_PULLCTRL(pin); + regval |= BIT(bit_offset); + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + bit_offset = BM1880_PINCONF_SCHMITT(pin); + if (arg) + regval |= BIT(bit_offset); + else + regval &= ~BIT(bit_offset); + break; + case PIN_CONFIG_SLEW_RATE: + bit_offset = BM1880_PINCONF_SLEW(pin); + if (arg) + regval |= BIT(bit_offset); + else + regval &= ~BIT(bit_offset); + break; + case PIN_CONFIG_DRIVE_STRENGTH: + bit_offset = BM1880_PINCONF_DRV(pin); + ret = bm1880_pinconf_drv_set(arg, + pctrl->pinconf[pin].drv_bits, + ®val, bit_offset); + if (ret < 0) + return ret; + + break; + default: + dev_warn(pctldev->dev, + "unsupported configuration parameter '%u'\n", + param); + continue; } + + writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset); } return 0; } +static int bm1880_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *configs, + unsigned int num_configs) +{ + int i, ret; + struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct bm1880_pctrl_group *pgrp = &pctrl->groups[selector]; + + for (i = 0; i < pgrp->npins; i++) { + ret = bm1880_pinconf_cfg_set(pctldev, pgrp->pins[i], configs, + num_configs); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinconf_ops bm1880_pinconf_ops = { + .is_generic = true, + .pin_config_get = bm1880_pinconf_cfg_get, + .pin_config_set = bm1880_pinconf_cfg_set, + .pin_config_group_set = bm1880_pinconf_group_set, +}; + static const struct pinmux_ops bm1880_pinmux_ops = { .get_functions_count = bm1880_pmux_get_functions_count, .get_function_name = bm1880_pmux_get_function_name, @@ -910,6 +1301,7 @@ static struct pinctrl_desc bm1880_desc = { .npins = ARRAY_SIZE(bm1880_pins), .pctlops = &bm1880_pctrl_ops, .pmxops = &bm1880_pinmux_ops, + .confops = &bm1880_pinconf_ops, .owner = THIS_MODULE, }; @@ -932,6 +1324,7 @@ static int bm1880_pinctrl_probe(struct platform_device *pdev) pctrl->ngroups = ARRAY_SIZE(bm1880_pctrl_groups); pctrl->funcs = bm1880_pmux_functions; pctrl->nfuncs = ARRAY_SIZE(bm1880_pmux_functions); + pctrl->pinconf = bm1880_pinconf; pctrl->pctrldev = devm_pinctrl_register(&pdev->dev, &bm1880_desc, pctrl); diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c index 63035181dfde..d10704cc9318 100644 --- a/drivers/pinctrl/pinctrl-coh901.c +++ b/drivers/pinctrl/pinctrl-coh901.c @@ -1,8 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * U300 GPIO module. * * Copyright (C) 2007-2012 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0) * Author: Linus Walleij <linus.walleij@linaro.org> * Author: Jonas Aaberg <jonas.aberg@stericsson.com> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 16bf21bf69a2..64363363fe27 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -3212,6 +3212,7 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, base, &rockchip_regmap_config); } + of_node_put(node); } bank->irq = irq_of_parse_and_map(bank->of_node, 0); diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index eba872ce4a7c..d3332da35637 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -622,6 +622,7 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev) pctl->pctl_desc.pins = stmfx_pins; pctl->pctl_desc.npins = ARRAY_SIZE(stmfx_pins); pctl->pctl_desc.owner = THIS_MODULE; + pctl->pctl_desc.link_consumers = true; ret = devm_pinctrl_register_and_init(pctl->dev, &pctl->pctl_desc, pctl, &pctl->pctl_dev); diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c index 2e90a6d8fb3b..a32badf3f118 100644 --- a/drivers/pinctrl/pinctrl-tb10x.c +++ b/drivers/pinctrl/pinctrl-tb10x.c @@ -483,22 +483,22 @@ struct tb10x_port { * @base: register set base address. * @pingroups: pointer to an array of the pin groups this driver manages. * @pinfuncgrpcnt: number of pingroups in @pingroups. - * @pinfuncs: pointer to an array of pin functions this driver manages. * @pinfuncnt: number of pin functions in @pinfuncs. * @mutex: mutex for exclusive access to a pin controller's state. * @ports: current state of each port. * @gpios: Indicates if a given pin is currently used as GPIO (1) or not (0). + * @pinfuncs: flexible array of pin functions this driver manages. */ struct tb10x_pinctrl { struct pinctrl_dev *pctl; void *base; const struct tb10x_pinfuncgrp *pingroups; unsigned int pinfuncgrpcnt; - struct tb10x_of_pinfunc *pinfuncs; unsigned int pinfuncnt; struct mutex mutex; struct tb10x_port ports[TB10X_PORTS]; DECLARE_BITMAP(gpios, MAX_PIN + 1); + struct tb10x_of_pinfunc pinfuncs[]; }; static inline void tb10x_pinctrl_set_config(struct tb10x_pinctrl *state, @@ -771,15 +771,13 @@ static int tb10x_pinctrl_probe(struct platform_device *pdev) return -EINVAL; } - state = devm_kzalloc(dev, sizeof(struct tb10x_pinctrl) + - of_get_child_count(of_node) - * sizeof(struct tb10x_of_pinfunc), - GFP_KERNEL); + state = devm_kzalloc(dev, struct_size(state, pinfuncs, + of_get_child_count(of_node)), + GFP_KERNEL); if (!state) return -ENOMEM; platform_set_drvdata(pdev, state); - state->pinfuncs = (struct tb10x_of_pinfunc *)(state + 1); mutex_init(&state->mutex); mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c index 2b1a61dba224..6d59e3f836df 100644 --- a/drivers/pinctrl/pinctrl-u300.c +++ b/drivers/pinctrl/pinctrl-u300.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Driver for the U300 pin controller * diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 98a438dba711..06790e5ece6c 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -421,10 +421,10 @@ DECLARE_MSM_GPIO_PINS(147); DECLARE_MSM_GPIO_PINS(148); DECLARE_MSM_GPIO_PINS(149); -static const unsigned int sdc2_clk_pins[] = { 150 }; -static const unsigned int sdc2_cmd_pins[] = { 151 }; -static const unsigned int sdc2_data_pins[] = { 152 }; -static const unsigned int ufs_reset_pins[] = { 153 }; +static const unsigned int ufs_reset_pins[] = { 150 }; +static const unsigned int sdc2_clk_pins[] = { 151 }; +static const unsigned int sdc2_cmd_pins[] = { 152 }; +static const unsigned int sdc2_data_pins[] = { 153 }; enum sdm845_functions { msm_mux_gpio, @@ -1272,10 +1272,10 @@ static const struct msm_pingroup sdm845_groups[] = { PINGROUP(147, NORTH, _, _, _, _, _, _, _, _, _, _), PINGROUP(148, NORTH, _, _, _, _, _, _, _, _, _, _), PINGROUP(149, NORTH, _, _, _, _, _, _, _, _, _, _), + UFS_RESET(ufs_reset, 0x99f000), SDC_QDSD_PINGROUP(sdc2_clk, 0x99a000, 14, 6), SDC_QDSD_PINGROUP(sdc2_cmd, 0x99a000, 11, 3), SDC_QDSD_PINGROUP(sdc2_data, 0x99a000, 9, 0), - UFS_RESET(ufs_reset, 0x99f000), }; static const int sdm845_acpi_reserved_gpios[] = { @@ -1289,7 +1289,7 @@ static const struct msm_pinctrl_soc_data sdm845_pinctrl = { .nfunctions = ARRAY_SIZE(sdm845_functions), .groups = sdm845_groups, .ngroups = ARRAY_SIZE(sdm845_groups), - .ngpios = 150, + .ngpios = 151, }; static const struct msm_pinctrl_soc_data sdm845_acpi_pinctrl = { diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 3f989f5cb021..b8640ad41bef 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -717,7 +717,7 @@ static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; } #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */ #ifdef DEBUG -static bool is0s(const u16 *enum_ids, unsigned int n) +static bool __init is0s(const u16 *enum_ids, unsigned int n) { unsigned int i; @@ -728,11 +728,11 @@ static bool is0s(const u16 *enum_ids, unsigned int n) return true; } -static unsigned int sh_pfc_errors; -static unsigned int sh_pfc_warnings; +static unsigned int sh_pfc_errors __initdata = 0; +static unsigned int sh_pfc_warnings __initdata = 0; -static void sh_pfc_check_cfg_reg(const char *drvname, - const struct pinmux_cfg_reg *cfg_reg) +static void __init sh_pfc_check_cfg_reg(const char *drvname, + const struct pinmux_cfg_reg *cfg_reg) { unsigned int i, n, rw, fw; @@ -764,7 +764,7 @@ static void sh_pfc_check_cfg_reg(const char *drvname, } } -static void sh_pfc_check_info(const struct sh_pfc_soc_info *info) +static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) { const struct sh_pfc_function *func; const char *drvname = info->name; @@ -773,6 +773,35 @@ static void sh_pfc_check_info(const struct sh_pfc_soc_info *info) pr_info("Checking %s\n", drvname); + /* Check pins */ + for (i = 0; i < info->nr_pins; i++) { + for (j = 0; j < i; j++) { + if (!strcmp(info->pins[i].name, info->pins[j].name)) { + pr_err("%s: pin %s/%s: name conflict\n", + drvname, info->pins[i].name, + info->pins[j].name); + sh_pfc_errors++; + } + + if (info->pins[i].pin != (u16)-1 && + info->pins[i].pin == info->pins[j].pin) { + pr_err("%s: pin %s/%s: pin %u conflict\n", + drvname, info->pins[i].name, + info->pins[j].name, info->pins[i].pin); + sh_pfc_errors++; + } + + if (info->pins[i].enum_id && + info->pins[i].enum_id == info->pins[j].enum_id) { + pr_err("%s: pin %s/%s: enum_id %u conflict\n", + drvname, info->pins[i].name, + info->pins[j].name, + info->pins[i].enum_id); + sh_pfc_errors++; + } + } + } + /* Check groups and functions */ refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL); if (!refcnts) @@ -780,9 +809,15 @@ static void sh_pfc_check_info(const struct sh_pfc_soc_info *info) for (i = 0; i < info->nr_functions; i++) { func = &info->functions[i]; + if (!func->name) { + pr_err("%s: empty function %u\n", drvname, i); + sh_pfc_errors++; + continue; + } for (j = 0; j < func->nr_groups; j++) { for (k = 0; k < info->nr_groups; k++) { - if (!strcmp(func->groups[j], + if (info->groups[k].name && + !strcmp(func->groups[j], info->groups[k].name)) { refcnts[k]++; break; @@ -798,13 +833,18 @@ static void sh_pfc_check_info(const struct sh_pfc_soc_info *info) } for (i = 0; i < info->nr_groups; i++) { + if (!info->groups[i].name) { + pr_err("%s: empty group %u\n", drvname, i); + sh_pfc_errors++; + continue; + } if (!refcnts[i]) { pr_err("%s: orphan group %s\n", drvname, info->groups[i].name); sh_pfc_errors++; } else if (refcnts[i] > 1) { - pr_err("%s: group %s referred by %u functions\n", - drvname, info->groups[i].name, refcnts[i]); + pr_warn("%s: group %s referenced by %u functions\n", + drvname, info->groups[i].name, refcnts[i]); sh_pfc_warnings++; } } @@ -816,7 +856,7 @@ static void sh_pfc_check_info(const struct sh_pfc_soc_info *info) sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]); } -static void sh_pfc_check_driver(const struct platform_driver *pdrv) +static void __init sh_pfc_check_driver(const struct platform_driver *pdrv) { unsigned int i; diff --git a/drivers/pinctrl/sh-pfc/pfc-emev2.c b/drivers/pinctrl/sh-pfc/pfc-emev2.c index 0af1ef82a1a8..6c66fc335d2f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-emev2.c +++ b/drivers/pinctrl/sh-pfc/pfc-emev2.c @@ -19,6 +19,20 @@ PORT_1(155, fn, pfx##155, sfx), PORT_1(156, fn, pfx##156, sfx), \ PORT_1(157, fn, pfx##157, sfx), PORT_1(158, fn, pfx##158, sfx) +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP(LCD3_B2, "B15", fn), \ + PIN_NOGP(LCD3_B3, "C15", fn), \ + PIN_NOGP(LCD3_B4, "D15", fn), \ + PIN_NOGP(LCD3_B5, "B14", fn), \ + PIN_NOGP(LCD3_B6, "C14", fn), \ + PIN_NOGP(LCD3_B7, "D14", fn), \ + PIN_NOGP(LCD3_G2, "B17", fn), \ + PIN_NOGP(LCD3_G3, "C17", fn), \ + PIN_NOGP(LCD3_G4, "D17", fn), \ + PIN_NOGP(LCD3_G5, "B16", fn), \ + PIN_NOGP(LCD3_G6, "C16", fn), \ + PIN_NOGP(LCD3_G7, "D16", fn) + enum { PINMUX_RESERVED = 0, @@ -218,10 +232,13 @@ enum { PINMUX_MARK_END, }; -/* Pin numbers for pins without a corresponding GPIO port number are computed - * from the row and column numbers with a 1000 offset to avoid collisions with - * GPIO port numbers. */ -#define PIN_NUMBER(row, col) (1000+((row)-1)*23+(col)-1) +/* + * Pins not associated with a GPIO port. + */ +enum { + PORT_ASSIGN_LAST(), + NOGP_ALL(), +}; /* Expand to a list of sh_pfc_pin entries (named PORT#). * NOTE: No config are recorded since the driver do not handle pinconf. */ @@ -230,20 +247,7 @@ enum { static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_EMEV_GPIO_ALL(), - - /* Pins not associated with a GPIO port */ - SH_PFC_PIN_NAMED(2, 14, B14), - SH_PFC_PIN_NAMED(2, 15, B15), - SH_PFC_PIN_NAMED(2, 16, B16), - SH_PFC_PIN_NAMED(2, 17, B17), - SH_PFC_PIN_NAMED(3, 14, C14), - SH_PFC_PIN_NAMED(3, 15, C15), - SH_PFC_PIN_NAMED(3, 16, C16), - SH_PFC_PIN_NAMED(3, 17, C17), - SH_PFC_PIN_NAMED(4, 14, D14), - SH_PFC_PIN_NAMED(4, 15, D15), - SH_PFC_PIN_NAMED(4, 16, D16), - SH_PFC_PIN_NAMED(4, 17, D17), + PINMUX_NOGP_ALL(), }; /* Expand to a list of name_DATA, name_FN marks */ @@ -829,12 +833,10 @@ static const unsigned int lcd3_rgb888_pins[] = { /* R[0:7], G[0:7], B[0:7] */ 32, 33, 34, 35, 36, 37, 38, 39, - 40, 41, PIN_NUMBER(2, 17), PIN_NUMBER(3, 17), - PIN_NUMBER(4, 17), PIN_NUMBER(2, 16), PIN_NUMBER(3, 16), - PIN_NUMBER(4, 16), - 42, 43, PIN_NUMBER(2, 15), PIN_NUMBER(3, 15), - PIN_NUMBER(4, 15), PIN_NUMBER(2, 14), PIN_NUMBER(3, 14), - PIN_NUMBER(4, 14) + 40, 41, PIN_LCD3_G2, PIN_LCD3_G3, + PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7, + 42, 43, PIN_LCD3_B2, PIN_LCD3_B3, + PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7 }; static const unsigned int lcd3_rgb888_mux[] = { LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK, @@ -850,12 +852,10 @@ static const unsigned int yuv3_pins[] = { /* CLK_O, HS, VS, DE */ 18, 21, 22, 23, /* YUV3_D[0:15] */ - 40, 41, PIN_NUMBER(2, 17), PIN_NUMBER(3, 17), - PIN_NUMBER(4, 17), PIN_NUMBER(2, 16), PIN_NUMBER(3, 16), - PIN_NUMBER(4, 16), - 42, 43, PIN_NUMBER(2, 15), PIN_NUMBER(3, 15), - PIN_NUMBER(4, 15), PIN_NUMBER(2, 14), PIN_NUMBER(3, 14), - PIN_NUMBER(4, 14), + 40, 41, PIN_LCD3_G2, PIN_LCD3_G3, + PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7, + 42, 43, PIN_LCD3_B2, PIN_LCD3_B3, + PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7, }; static const unsigned int yuv3_mux[] = { YUV3_CLK_O_MARK, YUV3_HS_MARK, YUV3_VS_MARK, YUV3_DE_MARK, @@ -972,12 +972,10 @@ static const unsigned int tp33_pins[] = { /* CLK, CTRL */ 38, 39, /* TP33_DATA[0:15] */ - 40, 41, PIN_NUMBER(2, 17), PIN_NUMBER(3, 17), - PIN_NUMBER(4, 17), PIN_NUMBER(2, 16), PIN_NUMBER(3, 16), - PIN_NUMBER(4, 16), - 42, 43, PIN_NUMBER(2, 15), PIN_NUMBER(3, 15), - PIN_NUMBER(4, 15), PIN_NUMBER(2, 14), PIN_NUMBER(3, 14), - PIN_NUMBER(4, 14), + 40, 41, PIN_LCD3_G2, PIN_LCD3_G3, + PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7, + 42, 43, PIN_LCD3_B2, PIN_LCD3_B3, + PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7, }; static const unsigned int tp33_mux[] = { TP33_CLK_MARK, TP33_CTRL_MARK, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index bf12849defdb..b21f5afe610f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -1252,7 +1252,7 @@ static const u16 pinmux_data[] = { #define __O (SH_PFC_PIN_CFG_OUTPUT) #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) -#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) +#define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN) #define R8A73A4_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD) #define R8A73A4_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index 696a0f6fc1da..fdf1b0f09f57 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -1515,7 +1515,7 @@ static const u16 pinmux_data[] = { #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) #define __PD (SH_PFC_PIN_CFG_PULL_DOWN) #define __PU (SH_PFC_PIN_CFG_PULL_UP) -#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) +#define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN) #define R8A7740_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD) #define R8A7740_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index c05dc1490486..b3b116da1bb0 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -10,7 +10,7 @@ #include "sh_pfc.h" -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_4(0, fn, sfx), \ PORT_GP_1(0, 4, fn, sfx), \ PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c index 49fe52d35f30..24866a5958ae 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c @@ -22,28 +22,17 @@ #define PORT_GP_PUP_1(bank, pin, fn, sfx) \ PORT_GP_CFG_1(bank, pin, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) -#define PORT_GP_PUP_27(bank, fn, sfx) \ - PORT_GP_PUP_1(bank, 0, fn, sfx), PORT_GP_PUP_1(bank, 1, fn, sfx), \ - PORT_GP_PUP_1(bank, 2, fn, sfx), PORT_GP_PUP_1(bank, 3, fn, sfx), \ - PORT_GP_PUP_1(bank, 4, fn, sfx), PORT_GP_PUP_1(bank, 5, fn, sfx), \ - PORT_GP_PUP_1(bank, 6, fn, sfx), PORT_GP_PUP_1(bank, 7, fn, sfx), \ - PORT_GP_PUP_1(bank, 8, fn, sfx), PORT_GP_PUP_1(bank, 9, fn, sfx), \ - PORT_GP_PUP_1(bank, 10, fn, sfx), PORT_GP_PUP_1(bank, 11, fn, sfx), \ - PORT_GP_PUP_1(bank, 12, fn, sfx), PORT_GP_PUP_1(bank, 13, fn, sfx), \ - PORT_GP_PUP_1(bank, 14, fn, sfx), PORT_GP_PUP_1(bank, 15, fn, sfx), \ - PORT_GP_PUP_1(bank, 16, fn, sfx), PORT_GP_PUP_1(bank, 17, fn, sfx), \ - PORT_GP_PUP_1(bank, 18, fn, sfx), PORT_GP_PUP_1(bank, 19, fn, sfx), \ - PORT_GP_PUP_1(bank, 20, fn, sfx), PORT_GP_PUP_1(bank, 21, fn, sfx), \ - PORT_GP_PUP_1(bank, 22, fn, sfx), PORT_GP_PUP_1(bank, 23, fn, sfx), \ - PORT_GP_PUP_1(bank, 24, fn, sfx), PORT_GP_PUP_1(bank, 25, fn, sfx), \ - PORT_GP_PUP_1(bank, 26, fn, sfx) - -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_PUP_27(4, fn, sfx) + PORT_GP_CFG_27(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP(CLKOUT, "B25", fn), \ + PIN_NOGP(CS0, "A20", fn), \ + PIN_NOGP(CS1_A26, "C20", fn) enum { PINMUX_RESERVED = 0, @@ -1253,19 +1242,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP10_24_22, CAN_CLK_C, SEL_CANCLK_C), }; -/* Pin numbers for pins without a corresponding GPIO port number are computed - * from the row and column numbers with a 1000 offset to avoid collisions with - * GPIO port numbers. +/* + * Pins not associated with a GPIO port. */ -#define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1) +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), - - /* Pins not associated with a GPIO port */ - SH_PFC_PIN_NAMED(3, 20, C20), - SH_PFC_PIN_NAMED(1, 20, A20), - SH_PFC_PIN_NAMED(2, 25, B25), + PINMUX_NOGP_ALL(), }; /* - macro */ @@ -1400,7 +1387,7 @@ HSPI_PFC_DAT(hspi1_a, HSPI_CLK1_A, HSPI_CS1_A, HSPI_RX1_A, HSPI_TX1_A); HSPI_PFC_PIN(hspi1_b, RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 26), - PIN_NUMBER(1, 20), PIN_NUMBER(2, 25)); + PIN_CS0, PIN_CLKOUT); HSPI_PFC_DAT(hspi1_b, HSPI_CLK1_B, HSPI_CS1_B, HSPI_RX1_B, HSPI_TX1_B); @@ -1426,7 +1413,7 @@ I2C_PFC_PIN(i2c1_b, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); I2C_PFC_MUX(i2c1_b, SDA1_B, SCL1_B); /* - I2C2 ------------------------------------------------------------------ */ -I2C_PFC_PIN(i2c2_a, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3)); +I2C_PFC_PIN(i2c2_a, PIN_CS1_A26, RCAR_GP_PIN(1, 3)); I2C_PFC_MUX(i2c2_a, SDA2_A, SCL2_A); I2C_PFC_PIN(i2c2_b, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4)); I2C_PFC_MUX(i2c2_b, SDA2_B, SCL2_B); @@ -1516,7 +1503,7 @@ SCIF_PFC_PIN(scif2_data_e, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4)); SCIF_PFC_DAT(scif2_data_e, TX2_E, RX2_E); SCIF_PFC_PIN(scif2_clk_a, RCAR_GP_PIN(3, 9)); SCIF_PFC_CLK(scif2_clk_a, SCK2_A); -SCIF_PFC_PIN(scif2_clk_b, PIN_NUMBER(3, 20)); +SCIF_PFC_PIN(scif2_clk_b, PIN_CS1_A26); SCIF_PFC_CLK(scif2_clk_b, SCK2_B); SCIF_PFC_PIN(scif2_clk_c, RCAR_GP_PIN(4, 12)); SCIF_PFC_CLK(scif2_clk_c, SCK2_C); @@ -1631,7 +1618,7 @@ SSI_PFC_PINS(ssi0_data, RCAR_GP_PIN(3, 10)); SSI_PFC_DATA(ssi0_data, SSI_SDATA0); SSI_PFC_PINS(ssi1_a_ctrl, RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21)); SSI_PFC_CTRL(ssi1_a_ctrl, SSI_SCK1_A, SSI_WS1_A); -SSI_PFC_PINS(ssi1_b_ctrl, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3)); +SSI_PFC_PINS(ssi1_b_ctrl, PIN_CS1_A26, RCAR_GP_PIN(1, 3)); SSI_PFC_CTRL(ssi1_b_ctrl, SSI_SCK1_B, SSI_WS1_B); SSI_PFC_PINS(ssi1_data, RCAR_GP_PIN(3, 9)); SSI_PFC_DATA(ssi1_data, SSI_SDATA1); @@ -2921,8 +2908,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -#define PIN_NONE U16_MAX - static const struct pinmux_bias_reg pinmux_bias_regs[] = { { PINMUX_BIAS_REG("PUPR0", 0x100, "N/A", 0) { [ 0] = RCAR_GP_PIN(0, 6), /* A0 */ @@ -2969,28 +2954,28 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 7] = RCAR_GP_PIN(1, 10), /* DACK0 */ [ 8] = RCAR_GP_PIN(1, 12), /* IRQ0 */ [ 9] = RCAR_GP_PIN(1, 13), /* IRQ1 */ - [10] = PIN_NONE, - [11] = PIN_NONE, - [12] = PIN_NONE, - [13] = PIN_NONE, - [14] = PIN_NONE, - [15] = PIN_NONE, - [16] = PIN_NONE, - [17] = PIN_NONE, - [18] = PIN_NONE, - [19] = PIN_NONE, - [20] = PIN_NONE, - [21] = PIN_NONE, - [22] = PIN_NONE, - [23] = PIN_NONE, - [24] = PIN_NONE, - [25] = PIN_NONE, - [26] = PIN_NONE, - [27] = PIN_NONE, - [28] = PIN_NONE, - [29] = PIN_NONE, - [30] = PIN_NONE, - [31] = PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, } }, { PINMUX_BIAS_REG("PUPR2", 0x108, "N/A", 0) { [ 0] = RCAR_GP_PIN(1, 22), /* DU0_DR0 */ @@ -3112,21 +3097,21 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [14] = RCAR_GP_PIN(4, 20), /* ETH_MAGIC */ [15] = RCAR_GP_PIN(4, 25), /* AVS1 */ [16] = RCAR_GP_PIN(4, 26), /* AVS2 */ - [17] = PIN_NONE, - [18] = PIN_NONE, - [19] = PIN_NONE, - [20] = PIN_NONE, - [21] = PIN_NONE, - [22] = PIN_NONE, - [23] = PIN_NONE, - [24] = PIN_NONE, - [25] = PIN_NONE, - [26] = PIN_NONE, - [27] = PIN_NONE, - [28] = PIN_NONE, - [29] = PIN_NONE, - [30] = PIN_NONE, - [31] = PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, } }, { /* sentinel */ }, }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 0c121b28ec3f..3e47cdc1411d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -11,7 +11,7 @@ #include "sh_pfc.h" -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ PORT_GP_32(1, fn, sfx), \ PORT_GP_32(2, fn, sfx), \ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index c41a6761cf9d..3366ed561cce 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -20,7 +20,7 @@ * All pins assigned to GPIO bank 3 can be used for SD interfaces in * which case they support both 3.3V and 1.8V signalling. */ -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ PORT_GP_30(1, fn, sfx), \ PORT_GP_30(2, fn, sfx), \ @@ -28,6 +28,12 @@ PORT_GP_32(4, fn, sfx), \ PORT_GP_32(5, fn, sfx) +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP(IIC0_SDA, "AF15", fn), \ + PIN_NOGP(IIC0_SCL, "AG15", fn), \ + PIN_NOGP(IIC3_SDA, "AH15", fn), \ + PIN_NOGP(IIC3_SCL, "AJ15", fn) + enum { PINMUX_RESERVED = 0, @@ -1727,19 +1733,17 @@ static const u16 pinmux_data[] = { PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1), }; -/* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */ -#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) -#define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200) -#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), - - /* Pins not associated with a GPIO port */ - SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15), - SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15), - SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15), - SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15), + PINMUX_NOGP_ALL(), }; /* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -2135,7 +2139,7 @@ static const unsigned int hscif1_ctrl_b_mux[] = { /* - I2C0 ------------------------------------------------------------------- */ static const unsigned int i2c0_pins[] = { /* SCL, SDA */ - PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15), + PIN_IIC0_SCL, PIN_IIC0_SDA, }; static const unsigned int i2c0_mux[] = { I2C0_SCL_MARK, I2C0_SDA_MARK, @@ -2201,7 +2205,7 @@ static const unsigned int i2c2_e_mux[] = { /* - I2C3 ------------------------------------------------------------------- */ static const unsigned int i2c3_pins[] = { /* SCL, SDA */ - PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15), + PIN_IIC3_SCL, PIN_IIC3_SDA, }; static const unsigned int i2c3_mux[] = { I2C3_SCL_MARK, I2C3_SDA_MARK, @@ -2209,7 +2213,7 @@ static const unsigned int i2c3_mux[] = { /* - IIC0 (I2C4) ------------------------------------------------------------ */ static const unsigned int iic0_pins[] = { /* SCL, SDA */ - PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15), + PIN_IIC0_SCL, PIN_IIC0_SDA, }; static const unsigned int iic0_mux[] = { IIC0_SCL_MARK, IIC0_SDA_MARK, @@ -2274,8 +2278,8 @@ static const unsigned int iic2_e_mux[] = { }; /* - IIC3 (I2C7) ------------------------------------------------------------ */ static const unsigned int iic3_pins[] = { -/* SCL, SDA */ - PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15), + /* SCL, SDA */ + PIN_IIC3_SCL, PIN_IIC3_SDA, }; static const unsigned int iic3_mux[] = { IIC3_SCL_MARK, IIC3_SDA_MARK, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 1292ec8d268f..bc9caf812fc1 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -15,7 +15,7 @@ * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in * which case they support both 3.3V and 1.8V signalling. */ -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ PORT_GP_26(1, fn, sfx), \ PORT_GP_32(2, fn, sfx), \ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c index bbace1478613..258f82fb31c0 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c @@ -11,7 +11,7 @@ #include "core.h" #include "sh_pfc.h" -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_29(0, fn, sfx), \ PORT_GP_23(1, fn, sfx), \ PORT_GP_32(2, fn, sfx), \ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c index 1ff4969d8381..34481b6c4328 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -14,7 +14,7 @@ #include "core.h" #include "sh_pfc.h" -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ PORT_GP_26(1, fn, sfx), \ PORT_GP_32(2, fn, sfx), \ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c index f16dfbad3f17..95f9aae3bfba 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c @@ -11,11 +11,9 @@ #include "core.h" #include "sh_pfc.h" -#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \ - SH_PFC_PIN_CFG_PULL_UP | \ - SH_PFC_PIN_CFG_PULL_DOWN) +#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ @@ -28,6 +26,53 @@ PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(CLKOUT, "CLKOUT", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ + PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ + PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) + /* * F_() : just information * FM() : macro for FN_xxx / xxx_MARK @@ -1447,69 +1492,16 @@ static const u16 pinmux_data[] = { }; /* - * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs. - * Physical layout rows: A - AW, cols: 1 - 39. + * Pins not associated with a GPIO port. */ -#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) -#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) -#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) -#define PIN_NONE U16_MAX +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), - - /* - * Pins not associated with a GPIO port. - * - * The pin positions are different between different r8a7795 - * packages, all that is needed for the pfc driver is a unique - * number for each pin. To this end use the pin layout from - * R-Car H3SiP to calculate a unique number for each pin. - */ - SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), + PINMUX_NOGP_ALL(), }; /* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -1658,7 +1650,7 @@ static const unsigned int avb_phy_int_mux[] = { }; static const unsigned int avb_mdio_pins[] = { /* AVB_MDC, AVB_MDIO */ - RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9), + RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, }; static const unsigned int avb_mdio_mux[] = { AVB_MDC_MARK, AVB_MDIO_MARK, @@ -1671,11 +1663,11 @@ static const unsigned int avb_mii_pins[] = { * AVB_RD1, AVB_RD2, AVB_RD3, * AVB_TXCREFCLK */ - PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18), - PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17), - PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13), - PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14), - PIN_NUMBER('A', 12), + PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, + PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, + PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, + PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, + PIN_AVB_TXCREFCLK, }; static const unsigned int avb_mii_mux[] = { @@ -3137,22 +3129,21 @@ static const unsigned int pwm6_b_mux[] = { /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { /* QSPI0_SPCLK, QSPI0_SSL */ - PIN_NUMBER('W', 3), PIN_NUMBER('Y', 3), + PIN_QSPI0_SPCLK, PIN_QSPI0_SSL, }; static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; static const unsigned int qspi0_data2_pins[] = { /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ - PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4), + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, }; static const unsigned int qspi0_data2_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, }; static const unsigned int qspi0_data4_pins[] = { /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */ - PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4), - PIN_NUMBER('Y', 6), PIN_A_NUMBER('B', 6), + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, PIN_QSPI0_IO2, PIN_QSPI0_IO3, }; static const unsigned int qspi0_data4_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, @@ -3161,22 +3152,21 @@ static const unsigned int qspi0_data4_mux[] = { /* - QSPI1 ------------------------------------------------------------------ */ static const unsigned int qspi1_ctrl_pins[] = { /* QSPI1_SPCLK, QSPI1_SSL */ - PIN_NUMBER('V', 3), PIN_NUMBER('V', 5), + PIN_QSPI1_SPCLK, PIN_QSPI1_SSL, }; static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; static const unsigned int qspi1_data2_pins[] = { /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ - PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5), + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, }; static const unsigned int qspi1_data2_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, }; static const unsigned int qspi1_data4_pins[] = { /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */ - PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5), - PIN_A_NUMBER('E', 4), PIN_A_NUMBER('C', 3), + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, PIN_QSPI1_IO2, PIN_QSPI1_IO3, }; static const unsigned int qspi1_data4_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, @@ -3812,6 +3802,36 @@ static const unsigned int tmu_tclk2_b_mux[] = { TCLK2_B_MARK, }; +/* - TPU ------------------------------------------------------------------- */ +static const unsigned int tpu_to0_pins[] = { + /* TPU0TO0 */ + RCAR_GP_PIN(6, 28), +}; +static const unsigned int tpu_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu_to1_pins[] = { + /* TPU0TO1 */ + RCAR_GP_PIN(6, 29), +}; +static const unsigned int tpu_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu_to2_pins[] = { + /* TPU0TO2 */ + RCAR_GP_PIN(6, 30), +}; +static const unsigned int tpu_to2_mux[] = { + TPU0TO2_MARK, +}; +static const unsigned int tpu_to3_pins[] = { + /* TPU0TO3 */ + RCAR_GP_PIN(6, 31), +}; +static const unsigned int tpu_to3_mux[] = { + TPU0TO3_MARK, +}; + /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { /* PWEN, OVC */ @@ -4165,6 +4185,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), SH_PFC_PIN_GROUP(tmu_tclk2_b), + SH_PFC_PIN_GROUP(tpu_to0), + SH_PFC_PIN_GROUP(tpu_to1), + SH_PFC_PIN_GROUP(tpu_to2), + SH_PFC_PIN_GROUP(tpu_to3), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb2), @@ -4635,6 +4659,13 @@ static const char * const tmu_groups[] = { "tmu_tclk2_b", }; +static const char * const tpu_groups[] = { + "tpu_to0", + "tpu_to1", + "tpu_to2", + "tpu_to3", +}; + static const char * const usb0_groups[] = { "usb0", }; @@ -4707,6 +4738,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(ssi), SH_PFC_FUNCTION(tmu), + SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb2), @@ -5272,44 +5304,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { static const struct pinmux_drive_reg pinmux_drive_regs[] = { { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { - { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */ - { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */ - { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */ - { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */ - { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */ - { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */ - { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */ - { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */ + { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ + { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ + { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ + { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ + { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ + { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ + { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ + { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { - { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */ - { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */ - { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */ - { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */ - { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */ - { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */ - { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */ - { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */ + { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ + { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ + { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ + { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ + { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ + { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ + { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ + { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ } }, { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { - { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */ - { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */ - { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */ - { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */ - { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */ - { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */ - { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */ - { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */ + { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ + { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ + { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ + { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ + { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ + { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ + { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ + { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { - { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */ - { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */ - { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */ - { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */ - { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */ - { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ - { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ - { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ + { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ + { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ + { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ + { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ + { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ + { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ + { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ + { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ } }, { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ @@ -5352,7 +5384,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ } }, { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { - { PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */ + { PIN_CLKOUT, 28, 3 }, /* CLKOUT */ { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ @@ -5363,7 +5395,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { } }, { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ - { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */ + { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ @@ -5382,30 +5414,30 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ } }, { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { - { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ - { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ - { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ - { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ - { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ - { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ - { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ + { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ + { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ + { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ + { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ + { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ + { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ + { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ } }, { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { - { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */ - { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */ - { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */ - { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */ + { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ + { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ + { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */ + { PIN_TMS, 4, 2 }, /* TMS */ } }, { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { - { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */ - { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */ - { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ - { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ + { PIN_TDO, 28, 2 }, /* TDO */ + { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ + { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ + { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ + { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ + { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ + { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ + { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ } }, { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ @@ -5474,7 +5506,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ - { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */ + { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ } }, { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { @@ -5548,35 +5580,35 @@ static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, static const struct pinmux_bias_reg pinmux_bias_regs[] = { { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { - [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */ - [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */ - [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */ - [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */ - [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */ - [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */ - [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */ - [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */ - [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */ - [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */ - [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */ - [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */ - [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */ - [13] = PIN_NUMBER('V', 6), /* RPC_WP# */ - [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */ - [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */ - [16] = PIN_NUMBER('B', 19), /* AVB_RXC */ - [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */ - [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */ - [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */ - [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */ - [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */ - [22] = PIN_NUMBER('A', 19), /* AVB_TXC */ - [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */ - [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */ - [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */ - [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */ - [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */ - [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */ + [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ + [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ + [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ + [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ + [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ + [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ + [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ + [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ + [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ + [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ + [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ + [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ + [12] = PIN_RPC_INT_N, /* RPC_INT# */ + [13] = PIN_RPC_WP_N, /* RPC_WP# */ + [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ + [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ + [16] = PIN_AVB_RXC, /* AVB_RXC */ + [17] = PIN_AVB_RD0, /* AVB_RD0 */ + [18] = PIN_AVB_RD1, /* AVB_RD1 */ + [19] = PIN_AVB_RD2, /* AVB_RD2 */ + [20] = PIN_AVB_RD3, /* AVB_RD3 */ + [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ + [22] = PIN_AVB_TXC, /* AVB_TXC */ + [23] = PIN_AVB_TD0, /* AVB_TD0 */ + [24] = PIN_AVB_TD1, /* AVB_TD1 */ + [25] = PIN_AVB_TD2, /* AVB_TD2 */ + [26] = PIN_AVB_TD3, /* AVB_TD3 */ + [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ + [28] = PIN_AVB_MDIO, /* AVB_MDIO */ [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ @@ -5616,7 +5648,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [31] = RCAR_GP_PIN(1, 19), /* A19 */ } }, { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { - [ 0] = PIN_NUMBER('F', 1), /* CLKOUT */ + [ 0] = PIN_CLKOUT, /* CLKOUT */ [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N_A26 */ [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ @@ -5625,7 +5657,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ - [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */ + [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ [10] = RCAR_GP_PIN(0, 0), /* D0 */ [11] = RCAR_GP_PIN(0, 1), /* D1 */ [12] = RCAR_GP_PIN(0, 2), /* D2 */ @@ -5646,20 +5678,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ - [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ - [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ + [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ + [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ } }, { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { - [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */ - [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */ - [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */ - [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/ - [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */ - [ 5] = PIN_A_NUMBER('T', 27), /* TCK */ - [ 6] = PIN_A_NUMBER('R', 30), /* TMS */ - [ 7] = PIN_A_NUMBER('R', 29), /* TDI */ - [ 8] = PIN_NONE, - [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */ + [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */ + [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ + [ 2] = PIN_FSCLKST_N, /* FSCLKST# */ + [ 3] = PIN_EXTALR, /* EXTALR*/ + [ 4] = PIN_TRST_N, /* TRST# */ + [ 5] = PIN_TCK, /* TCK */ + [ 6] = PIN_TMS, /* TMS */ + [ 7] = PIN_TDI, /* TDI */ + [ 8] = SH_PFC_PIN_NONE, + [ 9] = PIN_ASEBRK, /* ASEBRK */ [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ @@ -5724,7 +5756,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ - [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */ + [ 6] = PIN_MLB_REF, /* MLB_REF */ [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ @@ -5759,31 +5791,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ [ 5] = RCAR_GP_PIN(6, 30), /* USB31_PWEN */ [ 6] = RCAR_GP_PIN(6, 31), /* USB31_OVC */ - [ 7] = PIN_NONE, - [ 8] = PIN_NONE, - [ 9] = PIN_NONE, - [10] = PIN_NONE, - [11] = PIN_NONE, - [12] = PIN_NONE, - [13] = PIN_NONE, - [14] = PIN_NONE, - [15] = PIN_NONE, - [16] = PIN_NONE, - [17] = PIN_NONE, - [18] = PIN_NONE, - [19] = PIN_NONE, - [20] = PIN_NONE, - [21] = PIN_NONE, - [22] = PIN_NONE, - [23] = PIN_NONE, - [24] = PIN_NONE, - [25] = PIN_NONE, - [26] = PIN_NONE, - [27] = PIN_NONE, - [28] = PIN_NONE, - [29] = PIN_NONE, - [30] = PIN_NONE, - [31] = PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, } }, { /* sentinel */ }, }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 68bcb8980b16..7df010f757b1 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -12,11 +12,9 @@ #include "core.h" #include "sh_pfc.h" -#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \ - SH_PFC_PIN_CFG_PULL_UP | \ - SH_PFC_PIN_CFG_PULL_DOWN) +#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ @@ -29,6 +27,52 @@ PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ + PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ + PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) + /* * F_() : just information * FM() : macro for FN_xxx / xxx_MARK @@ -1508,68 +1552,16 @@ static const u16 pinmux_data[] = { }; /* - * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs. - * Physical layout rows: A - AW, cols: 1 - 39. + * Pins not associated with a GPIO port. */ -#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) -#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) -#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) -#define PIN_NONE U16_MAX +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), - - /* - * Pins not associated with a GPIO port. - * - * The pin positions are different between different r8a7795 - * packages, all that is needed for the pfc driver is a unique - * number for each pin. To this end use the pin layout from - * R-Car H3SiP to calculate a unique number for each pin. - */ - SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), + PINMUX_NOGP_ALL(), }; /* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -1717,7 +1709,7 @@ static const unsigned int avb_phy_int_mux[] = { }; static const unsigned int avb_mdio_pins[] = { /* AVB_MDC, AVB_MDIO */ - RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9), + RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, }; static const unsigned int avb_mdio_mux[] = { AVB_MDC_MARK, AVB_MDIO_MARK, @@ -1730,11 +1722,11 @@ static const unsigned int avb_mii_pins[] = { * AVB_RD1, AVB_RD2, AVB_RD3, * AVB_TXCREFCLK */ - PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18), - PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17), - PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13), - PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14), - PIN_NUMBER('A', 12), + PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, + PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, + PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, + PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, + PIN_AVB_TXCREFCLK, }; static const unsigned int avb_mii_mux[] = { @@ -3901,6 +3893,36 @@ static const unsigned int tmu_tclk2_b_mux[] = { TCLK2_B_MARK, }; +/* - TPU ------------------------------------------------------------------- */ +static const unsigned int tpu_to0_pins[] = { + /* TPU0TO0 */ + RCAR_GP_PIN(6, 28), +}; +static const unsigned int tpu_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu_to1_pins[] = { + /* TPU0TO1 */ + RCAR_GP_PIN(6, 29), +}; +static const unsigned int tpu_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu_to2_pins[] = { + /* TPU0TO2 */ + RCAR_GP_PIN(6, 30), +}; +static const unsigned int tpu_to2_mux[] = { + TPU0TO2_MARK, +}; +static const unsigned int tpu_to3_pins[] = { + /* TPU0TO3 */ + RCAR_GP_PIN(6, 31), +}; +static const unsigned int tpu_to3_mux[] = { + TPU0TO3_MARK, +}; + /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { /* PWEN, OVC */ @@ -4451,6 +4473,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), SH_PFC_PIN_GROUP(tmu_tclk2_b), + SH_PFC_PIN_GROUP(tpu_to0), + SH_PFC_PIN_GROUP(tpu_to1), + SH_PFC_PIN_GROUP(tpu_to2), + SH_PFC_PIN_GROUP(tpu_to3), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb2), @@ -4946,6 +4972,13 @@ static const char * const tmu_groups[] = { "tmu_tclk2_b", }; +static const char * const tpu_groups[] = { + "tpu_to0", + "tpu_to1", + "tpu_to2", + "tpu_to3", +}; + static const char * const usb0_groups[] = { "usb0", }; @@ -5048,6 +5081,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(ssi), SH_PFC_FUNCTION(tmu), + SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb2), @@ -5623,44 +5657,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { static const struct pinmux_drive_reg pinmux_drive_regs[] = { { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { - { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */ - { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */ - { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */ - { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */ - { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */ - { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */ - { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */ - { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */ + { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ + { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ + { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ + { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ + { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ + { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ + { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ + { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { - { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */ - { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */ - { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */ - { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */ - { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */ - { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */ - { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */ - { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */ + { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ + { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ + { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ + { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ + { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ + { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ + { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ + { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ } }, { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { - { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */ - { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */ - { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */ - { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */ - { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */ - { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */ - { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */ - { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */ + { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ + { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ + { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ + { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ + { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ + { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ + { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ + { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { - { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */ - { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */ - { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */ - { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */ - { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */ - { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ - { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ - { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ + { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ + { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ + { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ + { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ + { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ + { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ + { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ + { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ } }, { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ @@ -5714,7 +5748,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { } }, { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ - { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */ + { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ @@ -5733,30 +5767,30 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ } }, { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { - { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ - { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ - { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ - { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ - { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ - { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ - { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ + { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ + { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ + { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ + { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ + { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ + { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ + { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ } }, { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { - { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */ - { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */ - { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */ - { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */ + { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ + { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ + { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */ + { PIN_TMS, 4, 2 }, /* TMS */ } }, { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { - { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */ - { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */ - { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ - { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ + { PIN_TDO, 28, 2 }, /* TDO */ + { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ + { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ + { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ + { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ + { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ + { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ + { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ } }, { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ @@ -5825,7 +5859,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ - { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */ + { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ } }, { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { @@ -5898,35 +5932,35 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc static const struct pinmux_bias_reg pinmux_bias_regs[] = { { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { - [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */ - [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */ - [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */ - [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */ - [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */ - [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */ - [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */ - [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */ - [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */ - [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */ - [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */ - [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */ - [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */ - [13] = PIN_NUMBER('V', 6), /* RPC_WP# */ - [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */ - [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */ - [16] = PIN_NUMBER('B', 19), /* AVB_RXC */ - [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */ - [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */ - [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */ - [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */ - [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */ - [22] = PIN_NUMBER('A', 19), /* AVB_TXC */ - [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */ - [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */ - [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */ - [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */ - [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */ - [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */ + [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ + [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ + [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ + [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ + [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ + [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ + [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ + [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ + [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ + [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ + [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ + [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ + [12] = PIN_RPC_INT_N, /* RPC_INT# */ + [13] = PIN_RPC_WP_N, /* RPC_WP# */ + [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ + [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ + [16] = PIN_AVB_RXC, /* AVB_RXC */ + [17] = PIN_AVB_RD0, /* AVB_RD0 */ + [18] = PIN_AVB_RD1, /* AVB_RD1 */ + [19] = PIN_AVB_RD2, /* AVB_RD2 */ + [20] = PIN_AVB_RD3, /* AVB_RD3 */ + [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ + [22] = PIN_AVB_TXC, /* AVB_TXC */ + [23] = PIN_AVB_TD0, /* AVB_TD0 */ + [24] = PIN_AVB_TD1, /* AVB_TD1 */ + [25] = PIN_AVB_TD2, /* AVB_TD2 */ + [26] = PIN_AVB_TD3, /* AVB_TD3 */ + [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ + [28] = PIN_AVB_MDIO, /* AVB_MDIO */ [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ @@ -5975,7 +6009,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ - [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */ + [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ [10] = RCAR_GP_PIN(0, 0), /* D0 */ [11] = RCAR_GP_PIN(0, 1), /* D1 */ [12] = RCAR_GP_PIN(0, 2), /* D2 */ @@ -5996,20 +6030,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ - [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ - [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ + [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ + [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ } }, { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { - [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */ - [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */ - [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */ - [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/ - [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */ - [ 5] = PIN_A_NUMBER('T', 27), /* TCK */ - [ 6] = PIN_A_NUMBER('R', 30), /* TMS */ - [ 7] = PIN_A_NUMBER('R', 29), /* TDI */ - [ 8] = PIN_NONE, - [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */ + [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */ + [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ + [ 2] = PIN_FSCLKST_N, /* FSCLKST# */ + [ 3] = PIN_EXTALR, /* EXTALR*/ + [ 4] = PIN_TRST_N, /* TRST# */ + [ 5] = PIN_TCK, /* TCK */ + [ 6] = PIN_TMS, /* TMS */ + [ 7] = PIN_TDI, /* TDI */ + [ 8] = SH_PFC_PIN_NONE, + [ 9] = PIN_ASEBRK, /* ASEBRK */ [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ @@ -6074,7 +6108,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ - [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */ + [ 6] = PIN_MLB_REF, /* MLB_REF */ [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ @@ -6109,31 +6143,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */ [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */ - [ 7] = PIN_NONE, - [ 8] = PIN_NONE, - [ 9] = PIN_NONE, - [10] = PIN_NONE, - [11] = PIN_NONE, - [12] = PIN_NONE, - [13] = PIN_NONE, - [14] = PIN_NONE, - [15] = PIN_NONE, - [16] = PIN_NONE, - [17] = PIN_NONE, - [18] = PIN_NONE, - [19] = PIN_NONE, - [20] = PIN_NONE, - [21] = PIN_NONE, - [22] = PIN_NONE, - [23] = PIN_NONE, - [24] = PIN_NONE, - [25] = PIN_NONE, - [26] = PIN_NONE, - [27] = PIN_NONE, - [28] = PIN_NONE, - [29] = PIN_NONE, - [30] = PIN_NONE, - [31] = PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, } }, { /* sentinel */ }, }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c index 38cce690db70..61db7c7a35ec 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c @@ -17,11 +17,9 @@ #include "core.h" #include "sh_pfc.h" -#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \ - SH_PFC_PIN_CFG_PULL_UP | \ - SH_PFC_PIN_CFG_PULL_DOWN) +#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ @@ -34,6 +32,51 @@ PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ + PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ + PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) + /* * F_() : just information * FM() : macro for FN_xxx / xxx_MARK @@ -1512,67 +1555,16 @@ static const u16 pinmux_data[] = { }; /* - * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs. - * Physical layout rows: A - AW, cols: 1 - 39. + * Pins not associated with a GPIO port. */ -#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) -#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) -#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) -#define PIN_NONE U16_MAX +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), - - /* - * Pins not associated with a GPIO port. - * - * The pin positions are different between different r8a7796 - * packages, all that is needed for the pfc driver is a unique - * number for each pin. To this end use the pin layout from - * R-Car M3SiP to calculate a unique number for each pin. - */ - SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), + PINMUX_NOGP_ALL(), }; /* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -1721,7 +1713,7 @@ static const unsigned int avb_phy_int_mux[] = { }; static const unsigned int avb_mdio_pins[] = { /* AVB_MDC, AVB_MDIO */ - RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9), + RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, }; static const unsigned int avb_mdio_mux[] = { AVB_MDC_MARK, AVB_MDIO_MARK, @@ -1734,11 +1726,11 @@ static const unsigned int avb_mii_pins[] = { * AVB_RD1, AVB_RD2, AVB_RD3, * AVB_TXCREFCLK */ - PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18), - PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17), - PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13), - PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14), - PIN_NUMBER('A', 12), + PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, + PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, + PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, + PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, + PIN_AVB_TXCREFCLK, }; static const unsigned int avb_mii_mux[] = { @@ -3891,6 +3883,36 @@ static const unsigned int tmu_tclk2_b_mux[] = { TCLK2_B_MARK, }; +/* - TPU ------------------------------------------------------------------- */ +static const unsigned int tpu_to0_pins[] = { + /* TPU0TO0 */ + RCAR_GP_PIN(6, 28), +}; +static const unsigned int tpu_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu_to1_pins[] = { + /* TPU0TO1 */ + RCAR_GP_PIN(6, 29), +}; +static const unsigned int tpu_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu_to2_pins[] = { + /* TPU0TO2 */ + RCAR_GP_PIN(6, 30), +}; +static const unsigned int tpu_to2_mux[] = { + TPU0TO2_MARK, +}; +static const unsigned int tpu_to3_pins[] = { + /* TPU0TO3 */ + RCAR_GP_PIN(6, 31), +}; +static const unsigned int tpu_to3_mux[] = { + TPU0TO3_MARK, +}; + /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { /* PWEN, OVC */ @@ -4110,7 +4132,7 @@ static const unsigned int vin5_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[312]; + struct sh_pfc_pin_group common[316]; struct sh_pfc_pin_group automotive[30]; } pinmux_groups = { .common = { @@ -4397,6 +4419,10 @@ static const struct { SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), SH_PFC_PIN_GROUP(tmu_tclk2_b), + SH_PFC_PIN_GROUP(tpu_to0), + SH_PFC_PIN_GROUP(tpu_to1), + SH_PFC_PIN_GROUP(tpu_to2), + SH_PFC_PIN_GROUP(tpu_to3), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb30), @@ -4918,6 +4944,13 @@ static const char * const tmu_groups[] = { "tmu_tclk2_b", }; +static const char * const tpu_groups[] = { + "tpu_to0", + "tpu_to1", + "tpu_to2", + "tpu_to3", +}; + static const char * const usb0_groups[] = { "usb0", }; @@ -4963,7 +4996,7 @@ static const char * const vin5_groups[] = { }; static const struct { - struct sh_pfc_function common[49]; + struct sh_pfc_function common[50]; struct sh_pfc_function automotive[4]; } pinmux_functions = { .common = { @@ -5011,6 +5044,7 @@ static const struct { SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(ssi), SH_PFC_FUNCTION(tmu), + SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb30), @@ -5590,44 +5624,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { static const struct pinmux_drive_reg pinmux_drive_regs[] = { { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { - { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */ - { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */ - { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */ - { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */ - { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */ - { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */ - { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */ - { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */ + { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ + { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ + { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ + { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ + { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ + { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ + { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ + { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { - { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */ - { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */ - { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */ - { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */ - { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */ - { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */ - { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */ - { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */ + { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ + { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ + { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ + { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ + { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ + { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ + { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ + { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ } }, { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { - { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */ - { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */ - { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */ - { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */ - { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */ - { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */ - { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */ - { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */ + { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ + { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ + { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ + { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ + { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ + { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ + { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ + { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { - { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */ - { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */ - { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */ - { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */ - { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */ - { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ - { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ - { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ + { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ + { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ + { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ + { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ + { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ + { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ + { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ + { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ } }, { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ @@ -5681,7 +5715,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { } }, { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ - { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */ + { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ @@ -5700,29 +5734,29 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ } }, { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { - { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ - { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ - { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ - { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ - { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ - { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ - { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ + { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ + { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ + { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ + { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ + { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ + { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ + { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ } }, { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { - { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */ - { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */ - { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */ + { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ + { PIN_FSCLKST, 20, 2 }, /* FSCLKST */ + { PIN_TMS, 4, 2 }, /* TMS */ } }, { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { - { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */ - { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */ - { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ - { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ + { PIN_TDO, 28, 2 }, /* TDO */ + { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ + { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ + { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ + { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ + { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ + { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ + { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ } }, { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ @@ -5791,7 +5825,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ - { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */ + { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ } }, { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { @@ -5864,35 +5898,35 @@ static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc static const struct pinmux_bias_reg pinmux_bias_regs[] = { { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { - [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */ - [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */ - [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */ - [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */ - [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */ - [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */ - [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */ - [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */ - [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */ - [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */ - [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */ - [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */ - [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */ - [13] = PIN_NUMBER('V', 6), /* RPC_WP# */ - [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */ - [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */ - [16] = PIN_NUMBER('B', 19), /* AVB_RXC */ - [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */ - [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */ - [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */ - [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */ - [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */ - [22] = PIN_NUMBER('A', 19), /* AVB_TXC */ - [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */ - [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */ - [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */ - [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */ - [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */ - [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */ + [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ + [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ + [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ + [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ + [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ + [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ + [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ + [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ + [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ + [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ + [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ + [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ + [12] = PIN_RPC_INT_N, /* RPC_INT# */ + [13] = PIN_RPC_WP_N, /* RPC_WP# */ + [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ + [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ + [16] = PIN_AVB_RXC, /* AVB_RXC */ + [17] = PIN_AVB_RD0, /* AVB_RD0 */ + [18] = PIN_AVB_RD1, /* AVB_RD1 */ + [19] = PIN_AVB_RD2, /* AVB_RD2 */ + [20] = PIN_AVB_RD3, /* AVB_RD3 */ + [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ + [22] = PIN_AVB_TXC, /* AVB_TXC */ + [23] = PIN_AVB_TD0, /* AVB_TD0 */ + [24] = PIN_AVB_TD1, /* AVB_TD1 */ + [25] = PIN_AVB_TD2, /* AVB_TD2 */ + [26] = PIN_AVB_TD3, /* AVB_TD3 */ + [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ + [28] = PIN_AVB_MDIO, /* AVB_MDIO */ [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ @@ -5941,7 +5975,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ - [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */ + [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ [10] = RCAR_GP_PIN(0, 0), /* D0 */ [11] = RCAR_GP_PIN(0, 1), /* D1 */ [12] = RCAR_GP_PIN(0, 2), /* D2 */ @@ -5962,20 +5996,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ - [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ - [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ + [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ + [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ } }, { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { - [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */ - [ 1] = PIN_NONE, - [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */ - [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/ - [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */ - [ 5] = PIN_A_NUMBER('T', 27), /* TCK */ - [ 6] = PIN_A_NUMBER('R', 30), /* TMS */ - [ 7] = PIN_A_NUMBER('R', 29), /* TDI */ - [ 8] = PIN_NONE, - [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */ + [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */ + [ 1] = SH_PFC_PIN_NONE, + [ 2] = PIN_FSCLKST, /* FSCLKST */ + [ 3] = PIN_EXTALR, /* EXTALR*/ + [ 4] = PIN_TRST_N, /* TRST# */ + [ 5] = PIN_TCK, /* TCK */ + [ 6] = PIN_TMS, /* TMS */ + [ 7] = PIN_TDI, /* TDI */ + [ 8] = SH_PFC_PIN_NONE, + [ 9] = PIN_ASEBRK, /* ASEBRK */ [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ @@ -6040,7 +6074,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ - [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */ + [ 6] = PIN_MLB_REF, /* MLB_REF */ [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ @@ -6075,31 +6109,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */ [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */ - [ 7] = PIN_NONE, - [ 8] = PIN_NONE, - [ 9] = PIN_NONE, - [10] = PIN_NONE, - [11] = PIN_NONE, - [12] = PIN_NONE, - [13] = PIN_NONE, - [14] = PIN_NONE, - [15] = PIN_NONE, - [16] = PIN_NONE, - [17] = PIN_NONE, - [18] = PIN_NONE, - [19] = PIN_NONE, - [20] = PIN_NONE, - [21] = PIN_NONE, - [22] = PIN_NONE, - [23] = PIN_NONE, - [24] = PIN_NONE, - [25] = PIN_NONE, - [26] = PIN_NONE, - [27] = PIN_NONE, - [28] = PIN_NONE, - [29] = PIN_NONE, - [30] = PIN_NONE, - [31] = PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, } }, { /* sentinel */ }, }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c index 090024355eba..697c77a4ea95 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c @@ -18,11 +18,9 @@ #include "core.h" #include "sh_pfc.h" -#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \ - SH_PFC_PIN_CFG_PULL_UP | \ - SH_PFC_PIN_CFG_PULL_DOWN) +#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ @@ -35,6 +33,51 @@ PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ + PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ + PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) + /* * F_() : just information * FM() : macro for FN_xxx / xxx_MARK @@ -1517,67 +1560,16 @@ static const u16 pinmux_data[] = { }; /* - * R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs. - * Physical layout rows: A - AW, cols: 1 - 39. + * Pins not associated with a GPIO port. */ -#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) -#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) -#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) -#define PIN_NONE U16_MAX +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), - - /* - * Pins not associated with a GPIO port. - * - * The pin positions are different between different r8a77965 - * packages, all that is needed for the pfc driver is a unique - * number for each pin. To this end use the pin layout from - * R-Car M3SiP to calculate a unique number for each pin. - */ - SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), + PINMUX_NOGP_ALL(), }; /* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -1726,7 +1718,7 @@ static const unsigned int avb_phy_int_mux[] = { }; static const unsigned int avb_mdio_pins[] = { /* AVB_MDC, AVB_MDIO */ - RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9), + RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, }; static const unsigned int avb_mdio_mux[] = { AVB_MDC_MARK, AVB_MDIO_MARK, @@ -1739,11 +1731,11 @@ static const unsigned int avb_mii_pins[] = { * AVB_RD1, AVB_RD2, AVB_RD3, * AVB_TXCREFCLK */ - PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18), - PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17), - PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13), - PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14), - PIN_NUMBER('A', 12), + PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, + PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, + PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, + PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, + PIN_AVB_TXCREFCLK, }; static const unsigned int avb_mii_mux[] = { @@ -4116,6 +4108,36 @@ static const unsigned int tmu_tclk2_b_mux[] = { TCLK2_B_MARK, }; +/* - TPU ------------------------------------------------------------------- */ +static const unsigned int tpu_to0_pins[] = { + /* TPU0TO0 */ + RCAR_GP_PIN(6, 28), +}; +static const unsigned int tpu_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu_to1_pins[] = { + /* TPU0TO1 */ + RCAR_GP_PIN(6, 29), +}; +static const unsigned int tpu_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu_to2_pins[] = { + /* TPU0TO2 */ + RCAR_GP_PIN(6, 30), +}; +static const unsigned int tpu_to2_mux[] = { + TPU0TO2_MARK, +}; +static const unsigned int tpu_to3_pins[] = { + /* TPU0TO3 */ + RCAR_GP_PIN(6, 31), +}; +static const unsigned int tpu_to3_mux[] = { + TPU0TO3_MARK, +}; + /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { /* PWEN, OVC */ @@ -4672,6 +4694,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), SH_PFC_PIN_GROUP(tmu_tclk2_b), + SH_PFC_PIN_GROUP(tpu_to0), + SH_PFC_PIN_GROUP(tpu_to1), + SH_PFC_PIN_GROUP(tpu_to2), + SH_PFC_PIN_GROUP(tpu_to3), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb30), @@ -5164,6 +5190,13 @@ static const char * const tmu_groups[] = { "tmu_tclk2_b", }; +static const char * const tpu_groups[] = { + "tpu_to0", + "tpu_to1", + "tpu_to2", + "tpu_to3", +}; + static const char * const usb0_groups[] = { "usb0", }; @@ -5258,6 +5291,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(ssi), SH_PFC_FUNCTION(tmu), + SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb30), @@ -5830,44 +5864,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { static const struct pinmux_drive_reg pinmux_drive_regs[] = { { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { - { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */ - { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */ - { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */ - { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */ - { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */ - { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */ - { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */ - { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */ + { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ + { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ + { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ + { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ + { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ + { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ + { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ + { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { - { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */ - { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */ - { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */ - { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */ - { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */ - { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */ - { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */ - { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */ + { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ + { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ + { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ + { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ + { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ + { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ + { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ + { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ } }, { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { - { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */ - { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */ - { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */ - { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */ - { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */ - { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */ - { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */ - { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */ + { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ + { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ + { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ + { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ + { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ + { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ + { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ + { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { - { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */ - { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */ - { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */ - { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */ - { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */ - { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ - { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ - { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ + { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ + { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ + { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ + { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ + { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ + { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ + { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ + { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ } }, { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ @@ -5921,7 +5955,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { } }, { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ - { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */ + { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ @@ -5940,29 +5974,29 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ } }, { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { - { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ - { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ - { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ - { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ - { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ - { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ - { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ + { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ + { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ + { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ + { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ + { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ + { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ + { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ } }, { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { - { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN3 */ - { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */ - { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */ + { PIN_DU_DOTCLKIN3, 28, 2 }, /* DU_DOTCLKIN3 */ + { PIN_FSCLKST, 20, 2 }, /* FSCLKST */ + { PIN_TMS, 4, 2 }, /* TMS */ } }, { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { - { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */ - { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */ - { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ - { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ + { PIN_TDO, 28, 2 }, /* TDO */ + { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ + { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ + { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ + { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ + { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ + { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ + { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ } }, { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ @@ -6031,7 +6065,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ - { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */ + { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ } }, { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { @@ -6104,35 +6138,35 @@ static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po static const struct pinmux_bias_reg pinmux_bias_regs[] = { { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { - [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */ - [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */ - [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */ - [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */ - [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */ - [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */ - [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */ - [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */ - [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */ - [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */ - [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */ - [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */ - [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */ - [13] = PIN_NUMBER('V', 6), /* RPC_WP# */ - [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */ - [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */ - [16] = PIN_NUMBER('B', 19), /* AVB_RXC */ - [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */ - [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */ - [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */ - [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */ - [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */ - [22] = PIN_NUMBER('A', 19), /* AVB_TXC */ - [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */ - [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */ - [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */ - [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */ - [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */ - [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */ + [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ + [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ + [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ + [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ + [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ + [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ + [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ + [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ + [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ + [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ + [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ + [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ + [12] = PIN_RPC_INT_N, /* RPC_INT# */ + [13] = PIN_RPC_WP_N, /* RPC_WP# */ + [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ + [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ + [16] = PIN_AVB_RXC, /* AVB_RXC */ + [17] = PIN_AVB_RD0, /* AVB_RD0 */ + [18] = PIN_AVB_RD1, /* AVB_RD1 */ + [19] = PIN_AVB_RD2, /* AVB_RD2 */ + [20] = PIN_AVB_RD3, /* AVB_RD3 */ + [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ + [22] = PIN_AVB_TXC, /* AVB_TXC */ + [23] = PIN_AVB_TD0, /* AVB_TD0 */ + [24] = PIN_AVB_TD1, /* AVB_TD1 */ + [25] = PIN_AVB_TD2, /* AVB_TD2 */ + [26] = PIN_AVB_TD3, /* AVB_TD3 */ + [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ + [28] = PIN_AVB_MDIO, /* AVB_MDIO */ [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ @@ -6181,7 +6215,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ - [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */ + [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ [10] = RCAR_GP_PIN(0, 0), /* D0 */ [11] = RCAR_GP_PIN(0, 1), /* D1 */ [12] = RCAR_GP_PIN(0, 2), /* D2 */ @@ -6202,20 +6236,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ - [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ - [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ + [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ + [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ } }, { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { - [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */ - [ 1] = PIN_NONE, - [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */ - [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/ - [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */ - [ 5] = PIN_A_NUMBER('T', 27), /* TCK */ - [ 6] = PIN_A_NUMBER('R', 30), /* TMS */ - [ 7] = PIN_A_NUMBER('R', 29), /* TDI */ - [ 8] = PIN_NONE, - [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */ + [ 0] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ + [ 1] = SH_PFC_PIN_NONE, + [ 2] = PIN_FSCLKST, /* FSCLKST */ + [ 3] = PIN_EXTALR, /* EXTALR*/ + [ 4] = PIN_TRST_N, /* TRST# */ + [ 5] = PIN_TCK, /* TCK */ + [ 6] = PIN_TMS, /* TMS */ + [ 7] = PIN_TDI, /* TDI */ + [ 8] = SH_PFC_PIN_NONE, + [ 9] = PIN_ASEBRK, /* ASEBRK */ [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ @@ -6280,7 +6314,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ - [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */ + [ 6] = PIN_MLB_REF, /* MLB_REF */ [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ @@ -6315,31 +6349,31 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */ [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */ - [ 7] = PIN_NONE, - [ 8] = PIN_NONE, - [ 9] = PIN_NONE, - [10] = PIN_NONE, - [11] = PIN_NONE, - [12] = PIN_NONE, - [13] = PIN_NONE, - [14] = PIN_NONE, - [15] = PIN_NONE, - [16] = PIN_NONE, - [17] = PIN_NONE, - [18] = PIN_NONE, - [19] = PIN_NONE, - [20] = PIN_NONE, - [21] = PIN_NONE, - [22] = PIN_NONE, - [23] = PIN_NONE, - [24] = PIN_NONE, - [25] = PIN_NONE, - [26] = PIN_NONE, - [27] = PIN_NONE, - [28] = PIN_NONE, - [29] = PIN_NONE, - [30] = PIN_NONE, - [31] = PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, } }, { /* sentinel */ }, }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c index 2d76b548b942..25e27b6bee89 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c @@ -19,7 +19,7 @@ #include "core.h" #include "sh_pfc.h" -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ PORT_GP_28(1, fn, sfx), \ PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ @@ -205,8 +205,8 @@ #define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -631,14 +631,12 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP6_31_28, SCL4), PINMUX_IPSR_GPSR(IP6_31_28, IRQ4), PINMUX_IPSR_GPSR(IP6_31_28, D14), - PINMUX_IPSR_GPSR(IP6_31_28, MMC_WP), /* IPSR7 */ PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD), PINMUX_IPSR_GPSR(IP7_3_0, SDA4), PINMUX_IPSR_GPSR(IP7_3_0, IRQ5), PINMUX_IPSR_GPSR(IP7_3_0, D15), - PINMUX_IPSR_GPSR(IP7_3_0, MMC_CD), PINMUX_IPSR_GPSR(IP7_7_4, SCL0), PINMUX_IPSR_GPSR(IP7_7_4, DU_DR0), @@ -1121,20 +1119,6 @@ static const unsigned int mmc_ctrl_pins[] = { static const unsigned int mmc_ctrl_mux[] = { MMC_CLK_MARK, MMC_CMD_MARK, }; -static const unsigned int mmc_cd_pins[] = { - /* CD */ - RCAR_GP_PIN(3, 16), -}; -static const unsigned int mmc_cd_mux[] = { - MMC_CD_MARK, -}; -static const unsigned int mmc_wp_pins[] = { - /* WP */ - RCAR_GP_PIN(3, 15), -}; -static const unsigned int mmc_wp_mux[] = { - MMC_WP_MARK, -}; /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { @@ -1726,8 +1710,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc_data4), SH_PFC_PIN_GROUP(mmc_data8), SH_PFC_PIN_GROUP(mmc_ctrl), - SH_PFC_PIN_GROUP(mmc_cd), - SH_PFC_PIN_GROUP(mmc_wp), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -1897,8 +1879,6 @@ static const char * const mmc_groups[] = { "mmc_data4", "mmc_data8", "mmc_ctrl", - "mmc_cd", - "mmc_wp", }; static const char * const msiof0_groups[] = { diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c index 473da65890a7..9d7eb6aca0f4 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c @@ -19,7 +19,7 @@ #include "core.h" #include "sh_pfc.h" -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ PORT_GP_28(1, fn, sfx), \ PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c index 91a837b02a36..2dfb8d9cfda1 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c @@ -17,10 +17,9 @@ #include "core.h" #include "sh_pfc.h" -#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP | \ - SH_PFC_PIN_CFG_PULL_DOWN) +#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN) -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \ @@ -41,6 +40,25 @@ PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_MDC, "AVB_MDC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TCK, "TCK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TDI, "TDI", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TRST_N, "TRST_N", fn, CFG_FLAGS) + /* * F_() : just information * FM() : macro for FN_xxx / xxx_MARK @@ -1277,41 +1295,16 @@ static const u16 pinmux_data[] = { }; /* - * R8A77990 has 7 banks with 32 GPIOs in each => 224 GPIOs. - * Physical layout rows: A - AE, cols: 1 - 25. + * Pins not associated with a GPIO port. */ -#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) -#define PIN_NUMBER(r, c) (((r) - 'A') * 25 + (c) + 300) -#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) -#define PIN_NONE U16_MAX +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), - - /* - * Pins not associated with a GPIO port. - * - * The pin positions are different between different R8A77990 - * packages, all that is needed for the pfc driver is a unique - * number for each pin. To this end use the pin layout from - * R8A77990 to calculate a unique number for each pin. - */ - SH_PFC_PIN_NAMED_CFG('F', 1, TRST_N, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('F', 3, TMS, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('F', 4, TCK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('G', 2, TDI, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('G', 3, FSCLKST_N, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('H', 1, ASEBRK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('N', 1, AVB_TXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('N', 2, AVB_TD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('N', 3, AVB_TD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('N', 5, AVB_TD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('N', 6, AVB_TD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('P', 3, AVB_TX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('P', 4, AVB_MDIO, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('P', 5, AVB_MDC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('T', 21, MLB_REF, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS), + PINMUX_NOGP_ALL(), }; /* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -5026,15 +5019,15 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [0] = RCAR_GP_PIN(2, 23), /* RD# */ [1] = RCAR_GP_PIN(2, 22), /* BS# */ [2] = RCAR_GP_PIN(2, 21), /* AVB_PHY_INT */ - [3] = PIN_NUMBER('P', 5), /* AVB_MDC */ - [4] = PIN_NUMBER('P', 4), /* AVB_MDIO */ + [3] = PIN_AVB_MDC, /* AVB_MDC */ + [4] = PIN_AVB_MDIO, /* AVB_MDIO */ [5] = RCAR_GP_PIN(2, 20), /* AVB_TXCREFCLK */ - [6] = PIN_NUMBER('N', 6), /* AVB_TD3 */ - [7] = PIN_NUMBER('N', 5), /* AVB_TD2 */ - [8] = PIN_NUMBER('N', 3), /* AVB_TD1 */ - [9] = PIN_NUMBER('N', 2), /* AVB_TD0 */ - [10] = PIN_NUMBER('N', 1), /* AVB_TXC */ - [11] = PIN_NUMBER('P', 3), /* AVB_TX_CTL */ + [6] = PIN_AVB_TD3, /* AVB_TD3 */ + [7] = PIN_AVB_TD2, /* AVB_TD2 */ + [8] = PIN_AVB_TD1, /* AVB_TD1 */ + [9] = PIN_AVB_TD0, /* AVB_TD0 */ + [10] = PIN_AVB_TXC, /* AVB_TXC */ + [11] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ [12] = RCAR_GP_PIN(2, 19), /* AVB_RD3 */ [13] = RCAR_GP_PIN(2, 18), /* AVB_RD2 */ [14] = RCAR_GP_PIN(2, 17), /* AVB_RD1 */ @@ -5085,33 +5078,33 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [25] = RCAR_GP_PIN(1, 2), /* A2 */ [26] = RCAR_GP_PIN(1, 1), /* A1 */ [27] = RCAR_GP_PIN(1, 0), /* A0 */ - [28] = PIN_NONE, - [29] = PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, [30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */ [31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */ } }, { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { [0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ [1] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ - [2] = PIN_NUMBER('H', 1), /* ASEBRK */ - [3] = PIN_NONE, - [4] = PIN_NUMBER('G', 2), /* TDI */ - [5] = PIN_NUMBER('F', 3), /* TMS */ - [6] = PIN_NUMBER('F', 4), /* TCK */ - [7] = PIN_NUMBER('F', 1), /* TRST# */ - [8] = PIN_NONE, - [9] = PIN_NONE, - [10] = PIN_NONE, - [11] = PIN_NONE, - [12] = PIN_NONE, - [13] = PIN_NONE, - [14] = PIN_NONE, - [15] = PIN_NUMBER('G', 3), /* FSCLKST# */ + [2] = PIN_ASEBRK, /* ASEBRK */ + [3] = SH_PFC_PIN_NONE, + [4] = PIN_TDI, /* TDI */ + [5] = PIN_TMS, /* TMS */ + [6] = PIN_TCK, /* TCK */ + [7] = PIN_TRST_N, /* TRST# */ + [8] = SH_PFC_PIN_NONE, + [9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = PIN_FSCLKST_N, /* FSCLKST# */ [16] = RCAR_GP_PIN(0, 17), /* SDA4 */ [17] = RCAR_GP_PIN(0, 16), /* SCL4 */ - [18] = PIN_NONE, - [19] = PIN_NONE, - [20] = PIN_A_NUMBER('D', 3), /* PRESETOUT# */ + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = PIN_PRESETOUT_N, /* PRESETOUT# */ [21] = RCAR_GP_PIN(0, 15), /* D15 */ [22] = RCAR_GP_PIN(0, 14), /* D14 */ [23] = RCAR_GP_PIN(0, 13), /* D13 */ @@ -5130,8 +5123,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */ [3] = RCAR_GP_PIN(5, 2), /* TX0_A */ [4] = RCAR_GP_PIN(5, 1), /* RX0_A */ - [5] = PIN_NONE, - [6] = PIN_NONE, + [5] = SH_PFC_PIN_NONE, + [6] = SH_PFC_PIN_NONE, [7] = RCAR_GP_PIN(3, 15), /* SD1_WP */ [8] = RCAR_GP_PIN(3, 14), /* SD1_CD */ [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ @@ -5175,7 +5168,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [13] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ [14] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ [15] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ - [16] = PIN_NUMBER('T', 21), /* MLB_REF */ + [16] = PIN_MLB_REF, /* MLB_REF */ [17] = RCAR_GP_PIN(5, 19), /* MLB_DAT */ [18] = RCAR_GP_PIN(5, 18), /* MLB_SIG */ [19] = RCAR_GP_PIN(5, 17), /* MLB_CLK */ @@ -5193,36 +5186,36 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [31] = RCAR_GP_PIN(5, 5), /* RX1 */ } }, { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { - [0] = PIN_NONE, - [1] = PIN_NONE, - [2] = PIN_NONE, - [3] = PIN_NONE, - [4] = PIN_NONE, - [5] = PIN_NONE, - [6] = PIN_NONE, - [7] = PIN_NONE, - [8] = PIN_NONE, - [9] = PIN_NONE, - [10] = PIN_NONE, - [11] = PIN_NONE, - [12] = PIN_NONE, - [13] = PIN_NONE, - [14] = PIN_NONE, - [15] = PIN_NONE, - [16] = PIN_NONE, - [17] = PIN_NONE, - [18] = PIN_NONE, - [19] = PIN_NONE, - [20] = PIN_NONE, - [21] = PIN_NONE, - [22] = PIN_NONE, - [23] = PIN_NONE, - [24] = PIN_NONE, - [25] = PIN_NONE, - [26] = PIN_NONE, - [27] = PIN_NONE, - [28] = PIN_NONE, - [29] = PIN_NONE, + [0] = SH_PFC_PIN_NONE, + [1] = SH_PFC_PIN_NONE, + [2] = SH_PFC_PIN_NONE, + [3] = SH_PFC_PIN_NONE, + [4] = SH_PFC_PIN_NONE, + [5] = SH_PFC_PIN_NONE, + [6] = SH_PFC_PIN_NONE, + [7] = SH_PFC_PIN_NONE, + [8] = SH_PFC_PIN_NONE, + [9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, [30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */ [31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */ } }, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c index dd87085d48cb..c10b756476b1 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c @@ -17,7 +17,7 @@ #include "core.h" #include "sh_pfc.h" -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_9(0, fn, sfx), \ PORT_GP_32(1, fn, sfx), \ PORT_GP_32(2, fn, sfx), \ diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index e1276d143117..afabd95105d5 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -43,6 +43,9 @@ PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \ PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx) +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP(A11, "F26", fn) + enum { PINMUX_RESERVED = 0, @@ -1147,7 +1150,7 @@ static const u16 pinmux_data[] = { #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) #define __PD (SH_PFC_PIN_CFG_PULL_DOWN) #define __PU (SH_PFC_PIN_CFG_PULL_UP) -#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) +#define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN) #define SH73A0_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD) #define SH73A0_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU) @@ -1158,11 +1161,13 @@ static const u16 pinmux_data[] = { #define SH73A0_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD) #define SH73A0_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) -/* Pin numbers for pins without a corresponding GPIO port number are computed - * from the row and column numbers with a 1000 offset to avoid collisions with - * GPIO port numbers. +/* + * Pins not associated with a GPIO port. */ -#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1) +enum { + PORT_ASSIGN_LAST(), + NOGP_ALL(), +}; static const struct sh_pfc_pin pinmux_pins[] = { /* Table 25-1 (I/O and Pull U/D) */ @@ -1437,7 +1442,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { SH73A0_PIN_O(309), /* Pins not associated with a GPIO port */ - SH_PFC_PIN_NAMED(6, 26, F26), + PINMUX_NOGP_ALL(), }; /* - BSC -------------------------------------------------------------------- */ @@ -1863,7 +1868,7 @@ static const unsigned int keysc_out7_2_mux[] = { }; static const unsigned int keysc_out8_0_pins[] = { /* KEYOUT8 */ - PIN_NUMBER(6, 26), + PIN_A11, }; static const unsigned int keysc_out8_0_mux[] = { KEYOUT8_MARK, @@ -3073,7 +3078,7 @@ static const unsigned int tpu4_to2_mux[] = { }; static const unsigned int tpu4_to3_pins[] = { /* TO */ - PIN_NUMBER(6, 26), + PIN_A11, }; static const unsigned int tpu4_to3_mux[] = { TPU4TO3_MARK, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c index fac7b4699121..5dfd991ffdaa 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c @@ -11,7 +11,7 @@ #include "sh_pfc.h" -#define CPU_ALL_PORT(fn, sfx) \ +#define CPU_ALL_GP(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ PORT_GP_32(1, fn, sfx), \ PORT_GP_32(2, fn, sfx), \ diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index c97d2ba7677c..2824be4eb887 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -569,8 +569,7 @@ static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, switch (param) { case PIN_CONFIG_BIAS_DISABLE: - return pin->configs & - (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN); + return pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN; case PIN_CONFIG_BIAS_PULL_UP: return pin->configs & SH_PFC_PIN_CFG_PULL_UP; diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 7db5819eea7e..835148fc0f28 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -21,10 +21,14 @@ enum { PINMUX_TYPE_INPUT, }; +#define SH_PFC_PIN_NONE U16_MAX + #define SH_PFC_PIN_CFG_INPUT (1 << 0) #define SH_PFC_PIN_CFG_OUTPUT (1 << 1) #define SH_PFC_PIN_CFG_PULL_UP (1 << 2) #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) +#define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \ + SH_PFC_PIN_CFG_PULL_DOWN) #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4) #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5) #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) @@ -542,9 +546,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; PORT_GP_CFG_1(bank, 25, fn, sfx, cfg) #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0) -#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_27(bank, fn, sfx, cfg) \ PORT_GP_CFG_26(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 26, fn, sfx, cfg) +#define PORT_GP_27(bank, fn, sfx) PORT_GP_CFG_27(bank, fn, sfx, 0) + +#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \ + PORT_GP_CFG_27(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 27, fn, sfx, cfg) #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0) @@ -584,7 +592,7 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */ #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx -#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str) +#define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str) /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ #define _GP_GPIO(bank, _pin, _name, sfx, cfg) \ @@ -594,11 +602,29 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; .enum_id = _name##_DATA, \ .configs = cfg, \ } -#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused) /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN) -#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_GP(_GP_DATA, unused) + +/* + * GP_ASSIGN_LAST() - Expand to an enum definition for the last GP pin + * + * The largest GP pin index is obtained by taking the size of a union, + * containing one array per GP pin, sized by the corresponding pin index. + * As the fields in the CPU_ALL_GP() macro definition are separated by commas, + * while the members of a union must be terminated by semicolons, the commas + * are absorbed by wrapping them inside dummy attributes. + */ +#define _GP_ENTRY(bank, pin, name, sfx, cfg) \ + deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated +#define GP_ASSIGN_LAST() \ + GP_LAST = sizeof(union { \ + char dummy[0] __attribute__((deprecated, \ + CPU_ALL_GP(_GP_ENTRY, unused), \ + deprecated)); \ + }) /* * PORT style (linear pin space) @@ -641,22 +667,6 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; .configs = cfgs, \ } -/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */ -#define SH_PFC_PIN_NAMED(row, col, _name) \ - { \ - .pin = PIN_NUMBER(row, col), \ - .name = __stringify(PIN_##_name), \ - .configs = SH_PFC_PIN_CFG_NO_GPIO, \ - } - -/* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */ -#define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \ - { \ - .pin = PIN_NUMBER(row, col), \ - .name = __stringify(PIN_##_name), \ - .configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \ - } - /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, * PORT_name_OUT, PORT_name_IN marks */ @@ -665,6 +675,24 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; PORT##pfx##_OUT, PORT##pfx##_IN) #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) +/* + * PORT_ASSIGN_LAST() - Expand to an enum definition for the last PORT pin + * + * The largest PORT pin index is obtained by taking the size of a union, + * containing one array per PORT pin, sized by the corresponding pin index. + * As the fields in the CPU_ALL_PORT() macro definition are separated by + * commas, while the members of a union must be terminated by semicolons, the + * commas are absorbed by wrapping them inside dummy attributes. + */ +#define _PORT_ENTRY(pn, pfx, sfx) \ + deprecated)); char pfx[pn] __attribute__((deprecated +#define PORT_ASSIGN_LAST() \ + PORT_LAST = sizeof(union { \ + char dummy[0] __attribute__((deprecated, \ + CPU_ALL_PORT(_PORT_ENTRY, PORT, unused), \ + deprecated)); \ + }) + /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */ #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ [gpio - (base)] = { \ @@ -675,6 +703,26 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) /* + * Pins not associated with a GPIO port + */ + +#define PIN_NOGP_CFG(pin, name, fn, cfg) fn(pin, name, cfg) +#define PIN_NOGP(pin, name, fn) fn(pin, name, 0) + +/* NOGP_ALL - Expand to a list of PIN_id */ +#define _NOGP_ALL(pin, name, cfg) PIN_##pin +#define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL) + +/* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */ +#define _NOGP_PINMUX(_pin, _name, cfg) \ + { \ + .pin = PIN_##_pin, \ + .name = "PIN_" _name, \ + .configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \ + } +#define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX) + +/* * PORTnCR helper macro for SH-Mobile/R-Mobile */ #define PORTCR(nr, reg) \ diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 2317ccf63321..b453aed1bbeb 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -44,6 +44,18 @@ #define STM32_GPIO_AFRL 0x20 #define STM32_GPIO_AFRH 0x24 +/* custom bitfield to backup pin status */ +#define STM32_GPIO_BKP_MODE_SHIFT 0 +#define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0) +#define STM32_GPIO_BKP_ALT_SHIFT 2 +#define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2) +#define STM32_GPIO_BKP_SPEED_SHIFT 6 +#define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6) +#define STM32_GPIO_BKP_PUPD_SHIFT 8 +#define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8) +#define STM32_GPIO_BKP_TYPE 10 +#define STM32_GPIO_BKP_VAL 11 + #define STM32_GPIO_PINS_PER_BANK 16 #define STM32_GPIO_IRQ_LINE 16 @@ -79,6 +91,7 @@ struct stm32_gpio_bank { struct irq_domain *domain; u32 bank_nr; u32 bank_ioport_nr; + u32 pin_backup[STM32_GPIO_PINS_PER_BANK]; }; struct stm32_pinctrl { @@ -98,6 +111,8 @@ struct stm32_pinctrl { struct stm32_desc_pin *pins; u32 npins; u32 pkg; + u16 irqmux_map; + spinlock_t irqmux_lock; }; static inline int stm32_gpio_pin(int gpio) @@ -133,11 +148,50 @@ static inline u32 stm32_gpio_get_alt(u32 function) return 0; } +static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, + u32 offset, u32 value) +{ + bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); + bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; +} + +static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, + u32 mode, u32 alt) +{ + bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | + STM32_GPIO_BKP_ALT_MASK); + bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; + bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; +} + +static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, + u32 drive) +{ + bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); + bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; +} + +static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset, + u32 speed) +{ + bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; + bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; +} + +static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset, + u32 bias) +{ + bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; + bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; +} + /* GPIO functions */ static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, unsigned offset, int value) { + stm32_gpio_backup_value(bank, offset, value); + if (!value) offset += STM32_GPIO_PINS_PER_BANK; @@ -307,9 +361,53 @@ static int stm32_gpio_domain_activate(struct irq_domain *d, { struct stm32_gpio_bank *bank = d->host_data; struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); + unsigned long flags; + int ret = 0; + + /* + * gpio irq mux is shared between several banks, a lock has to be done + * to avoid overriding. + */ + spin_lock_irqsave(&pctl->irqmux_lock, flags); + if (pctl->hwlock) + ret = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT); + + if (ret) { + dev_err(pctl->dev, "Can't get hwspinlock\n"); + goto unlock; + } + + if (pctl->irqmux_map & BIT(irq_data->hwirq)) { + dev_err(pctl->dev, "irq line %ld already requested.\n", + irq_data->hwirq); + ret = -EBUSY; + if (pctl->hwlock) + hwspin_unlock(pctl->hwlock); + goto unlock; + } else { + pctl->irqmux_map |= BIT(irq_data->hwirq); + } regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); - return 0; + + if (pctl->hwlock) + hwspin_unlock(pctl->hwlock); + +unlock: + spin_unlock_irqrestore(&pctl->irqmux_lock, flags); + return ret; +} + +static void stm32_gpio_domain_deactivate(struct irq_domain *d, + struct irq_data *irq_data) +{ + struct stm32_gpio_bank *bank = d->host_data; + struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); + unsigned long flags; + + spin_lock_irqsave(&pctl->irqmux_lock, flags); + pctl->irqmux_map &= ~BIT(irq_data->hwirq); + spin_unlock_irqrestore(&pctl->irqmux_lock, flags); } static int stm32_gpio_domain_alloc(struct irq_domain *d, @@ -338,6 +436,7 @@ static const struct irq_domain_ops stm32_gpio_domain_ops = { .alloc = stm32_gpio_domain_alloc, .free = irq_domain_free_irqs_common, .activate = stm32_gpio_domain_activate, + .deactivate = stm32_gpio_domain_deactivate, }; /* Pinctrl functions */ @@ -620,6 +719,8 @@ static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, if (pctl->hwlock) hwspin_unlock(pctl->hwlock); + stm32_gpio_backup_mode(bank, pin, mode, alt); + unlock: spin_unlock_irqrestore(&bank->lock, flags); clk_disable(bank->clk); @@ -732,6 +833,8 @@ static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, if (pctl->hwlock) hwspin_unlock(pctl->hwlock); + stm32_gpio_backup_driving(bank, offset, drive); + unlock: spin_unlock_irqrestore(&bank->lock, flags); clk_disable(bank->clk); @@ -784,6 +887,8 @@ static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, if (pctl->hwlock) hwspin_unlock(pctl->hwlock); + stm32_gpio_backup_speed(bank, offset, speed); + unlock: spin_unlock_irqrestore(&bank->lock, flags); clk_disable(bank->clk); @@ -836,6 +941,8 @@ static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, if (pctl->hwlock) hwspin_unlock(pctl->hwlock); + stm32_gpio_backup_bias(bank, offset, bias); + unlock: spin_unlock_irqrestore(&bank->lock, flags); clk_disable(bank->clk); @@ -1290,6 +1397,8 @@ int stm32_pctl_probe(struct platform_device *pdev) pctl->hwlock = hwspin_lock_request_specific(hwlock_id); } + spin_lock_init(&pctl->irqmux_lock); + pctl->dev = dev; pctl->match_data = match->data; @@ -1329,6 +1438,7 @@ int stm32_pctl_probe(struct platform_device *pdev) pctl->pctl_desc.owner = THIS_MODULE; pctl->pctl_desc.pins = pins; pctl->pctl_desc.npins = pctl->npins; + pctl->pctl_desc.link_consumers = true; pctl->pctl_desc.confops = &stm32_pconf_ops; pctl->pctl_desc.pctlops = &stm32_pctrl_ops; pctl->pctl_desc.pmxops = &stm32_pmx_ops; @@ -1369,3 +1479,75 @@ int stm32_pctl_probe(struct platform_device *pdev) return 0; } + +static int __maybe_unused stm32_pinctrl_restore_gpio_regs( + struct stm32_pinctrl *pctl, u32 pin) +{ + const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin); + u32 val, alt, mode, offset = stm32_gpio_pin(pin); + struct pinctrl_gpio_range *range; + struct stm32_gpio_bank *bank; + bool pin_is_irq; + int ret; + + range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin); + if (!range) + return 0; + + pin_is_irq = gpiochip_line_is_irq(range->gc, offset); + + if (!desc || (!pin_is_irq && !desc->gpio_owner)) + return 0; + + bank = gpiochip_get_data(range->gc); + + alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; + alt >>= STM32_GPIO_BKP_ALT_SHIFT; + mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; + mode >>= STM32_GPIO_BKP_MODE_SHIFT; + + ret = stm32_pmx_set_mode(bank, offset, mode, alt); + if (ret) + return ret; + + if (mode == 1) { + val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); + val = val >> STM32_GPIO_BKP_VAL; + __stm32_gpio_set(bank, offset, val); + } + + val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); + val >>= STM32_GPIO_BKP_TYPE; + ret = stm32_pconf_set_driving(bank, offset, val); + if (ret) + return ret; + + val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; + val >>= STM32_GPIO_BKP_SPEED_SHIFT; + ret = stm32_pconf_set_speed(bank, offset, val); + if (ret) + return ret; + + val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; + val >>= STM32_GPIO_BKP_PUPD_SHIFT; + ret = stm32_pconf_set_bias(bank, offset, val); + if (ret) + return ret; + + if (pin_is_irq) + regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); + + return 0; +} + +int __maybe_unused stm32_pinctrl_resume(struct device *dev) +{ + struct stm32_pinctrl *pctl = dev_get_drvdata(dev); + struct stm32_pinctrl_group *g = pctl->groups; + int i; + + for (i = g->pin; i < g->pin + pctl->ngroups; i++) + stm32_pinctrl_restore_gpio_regs(pctl, i); + + return 0; +} diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h index de5e7012ca03..ec0d34c33903 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.h +++ b/drivers/pinctrl/stm32/pinctrl-stm32.h @@ -65,5 +65,7 @@ struct stm32_gpio_bank; int stm32_pctl_probe(struct platform_device *pdev); void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, u32 *alt); +int stm32_pinctrl_resume(struct device *dev); + #endif /* __PINCTRL_STM32_H */ diff --git a/drivers/pinctrl/stm32/pinctrl-stm32mp157.c b/drivers/pinctrl/stm32/pinctrl-stm32mp157.c index 320544f69e57..2ccb99d64df8 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32mp157.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32mp157.c @@ -2342,11 +2342,16 @@ static const struct of_device_id stm32mp157_pctrl_match[] = { { } }; +static const struct dev_pm_ops stm32_pinctrl_dev_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, stm32_pinctrl_resume) +}; + static struct platform_driver stm32mp157_pinctrl_driver = { .probe = stm32_pctl_probe, .driver = { .name = "stm32mp157-pinctrl", .of_match_table = stm32mp157_pctrl_match, + .pm = &stm32_pinctrl_dev_pm_ops, }, }; diff --git a/drivers/pinctrl/tegra/Kconfig b/drivers/pinctrl/tegra/Kconfig index 24e20cc08d5b..6f79f1f392c1 100644 --- a/drivers/pinctrl/tegra/Kconfig +++ b/drivers/pinctrl/tegra/Kconfig @@ -23,6 +23,10 @@ config PINCTRL_TEGRA210 bool select PINCTRL_TEGRA +config PINCTRL_TEGRA194 + bool + select PINCTRL_TEGRA + config PINCTRL_TEGRA_XUSB def_bool y if ARCH_TEGRA select GENERIC_PHY diff --git a/drivers/pinctrl/tegra/Makefile b/drivers/pinctrl/tegra/Makefile index bbcb043c34a2..ead4e10097d0 100644 --- a/drivers/pinctrl/tegra/Makefile +++ b/drivers/pinctrl/tegra/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o obj-$(CONFIG_PINCTRL_TEGRA210) += pinctrl-tegra210.o +obj-$(CONFIG_PINCTRL_TEGRA194) += pinctrl-tegra194.o obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index a5008c066bac..76e88c4470d3 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -292,7 +292,7 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, const struct tegra_pingroup *g, enum tegra_pinconf_param param, bool report_err, - s8 *bank, s16 *reg, s8 *bit, s8 *width) + s8 *bank, s32 *reg, s8 *bit, s8 *width) { switch (param) { case TEGRA_PINCONF_PARAM_PULL: @@ -451,7 +451,7 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev, const struct tegra_pingroup *g; int ret; s8 bank, bit, width; - s16 reg; + s32 reg; u32 val, mask; g = &pmx->soc->groups[group]; @@ -480,7 +480,7 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, const struct tegra_pingroup *g; int ret, i; s8 bank, bit, width; - s16 reg; + s32 reg; u32 val, mask; g = &pmx->soc->groups[group]; @@ -548,7 +548,7 @@ static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, const struct tegra_pingroup *g; int i, ret; s8 bank, bit, width; - s16 reg; + s32 reg; u32 val; g = &pmx->soc->groups[group]; diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index 44c71941b5f8..82cd947e5171 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -143,10 +143,10 @@ struct tegra_pingroup { const unsigned *pins; u8 npins; u8 funcs[4]; - s16 mux_reg; - s16 pupd_reg; - s16 tri_reg; - s16 drv_reg; + s32 mux_reg; + s32 pupd_reg; + s32 tri_reg; + s32 drv_reg; u32 mux_bank:2; u32 pupd_bank:2; u32 tri_bank:2; diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c new file mode 100644 index 000000000000..957ef198850a --- /dev/null +++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Pinctrl data for the NVIDIA Tegra194 pinmux + * + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <linux/init.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include "pinctrl-tegra.h" + +/* Define unique ID for each pins */ +enum pin_id { + TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0 = 256, + TEGRA_PIN_PEX_L5_RST_N_PGG1 = 257, + TEGRA_PIN_NUM_GPIOS = 258, +}; + +/* Table for pin descriptor */ +static const struct pinctrl_pin_desc tegra194_pins[] = { + PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, + "TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0"), + PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, + "TEGRA_PIN_PEX_L5_RST_N_PGG1"), +}; + +static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = { + TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, +}; + +static const unsigned int pex_l5_rst_n_pgg1_pins[] = { + TEGRA_PIN_PEX_L5_RST_N_PGG1, +}; + +/* Define unique ID for each function */ +enum tegra_mux_dt { + TEGRA_MUX_RSVD0, + TEGRA_MUX_RSVD1, + TEGRA_MUX_RSVD2, + TEGRA_MUX_RSVD3, + TEGRA_MUX_PE5, +}; + +/* Make list of each function name */ +#define TEGRA_PIN_FUNCTION(lid) \ + { \ + .name = #lid, \ + } +static struct tegra_function tegra194_functions[] = { + TEGRA_PIN_FUNCTION(rsvd0), + TEGRA_PIN_FUNCTION(rsvd1), + TEGRA_PIN_FUNCTION(rsvd2), + TEGRA_PIN_FUNCTION(rsvd3), + TEGRA_PIN_FUNCTION(pe5), +}; + +#define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \ + drvup_w, slwr_b, slwr_w, slwf_b, \ + slwf_w, bank) \ + .drv_reg = ((r)), \ + .drv_bank = bank, \ + .drvdn_bit = drvdn_b, \ + .drvdn_width = drvdn_w, \ + .drvup_bit = drvup_b, \ + .drvup_width = drvup_w, \ + .slwr_bit = slwr_b, \ + .slwr_width = slwr_w, \ + .slwf_bit = slwf_b, \ + .slwf_width = slwf_w + +#define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk, e_input, \ + e_od, schmitt_b, drvtype) \ + .mux_reg = ((r)), \ + .lpmd_bit = -1, \ + .lock_bit = -1, \ + .hsm_bit = -1, \ + .parked_bit = -1, \ + .mux_bank = bank, \ + .mux_bit = 0, \ + .pupd_reg = ((r)), \ + .pupd_bank = bank, \ + .pupd_bit = 2, \ + .tri_reg = ((r)), \ + .tri_bank = bank, \ + .tri_bit = 4, \ + .einput_bit = e_input, \ + .odrain_bit = e_od, \ + .schmitt_bit = schmitt_b, \ + .drvtype_bit = 13, \ + .drv_reg = -1 + +#define drive_pex_l5_clkreq_n_pgg0 \ + DRV_PINGROUP_ENTRY_Y(0x14004, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pex_l5_rst_n_pgg1 \ + DRV_PINGROUP_ENTRY_Y(0x1400c, 12, 5, 20, 5, -1, -1, -1, -1, 0) + +#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_lpbk, \ + e_input, e_lpdr, e_od, schmitt_b, drvtype, io_rail) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .funcs = { \ + TEGRA_MUX_##f0, \ + TEGRA_MUX_##f1, \ + TEGRA_MUX_##f2, \ + TEGRA_MUX_##f3, \ + }, \ + PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk, \ + e_input, e_od, \ + schmitt_b, drvtype), \ + drive_##pg_name, \ + } + +static const struct tegra_pingroup tegra194_groups[] = { + PINGROUP(pex_l5_clkreq_n_pgg0, PE5, RSVD1, RSVD2, RSVD3, 0x14000, 0, + Y, -1, 6, 8, 11, 12, N, "vddio_pex_ctl_2"), + PINGROUP(pex_l5_rst_n_pgg1, PE5, RSVD1, RSVD2, RSVD3, 0x14008, 0, + Y, -1, 6, 8, 11, 12, N, "vddio_pex_ctl_2"), +}; + +static const struct tegra_pinctrl_soc_data tegra194_pinctrl = { + .ngpios = TEGRA_PIN_NUM_GPIOS, + .pins = tegra194_pins, + .npins = ARRAY_SIZE(tegra194_pins), + .functions = tegra194_functions, + .nfunctions = ARRAY_SIZE(tegra194_functions), + .groups = tegra194_groups, + .ngroups = ARRAY_SIZE(tegra194_groups), + .hsm_in_mux = true, + .schmitt_in_mux = true, + .drvtype_in_mux = true, +}; + +static int tegra194_pinctrl_probe(struct platform_device *pdev) +{ + return tegra_pinctrl_probe(pdev, &tegra194_pinctrl); +} + +static const struct of_device_id tegra194_pinctrl_of_match[] = { + { .compatible = "nvidia,tegra194-pinmux", }, + { }, +}; + +static struct platform_driver tegra194_pinctrl_driver = { + .driver = { + .name = "tegra194-pinctrl", + .of_match_table = tegra194_pinctrl_of_match, + }, + .probe = tegra194_pinctrl_probe, +}; + +static int __init tegra194_pinctrl_init(void) +{ + return platform_driver_register(&tegra194_pinctrl_driver); +} +arch_initcall(tegra194_pinctrl_init); |