diff options
Diffstat (limited to 'drivers/pinctrl')
56 files changed, 4077 insertions, 459 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 84dd2ed47a92..b422e4ed73f4 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -67,6 +67,19 @@ config PINCTRL_AT91 help Say Y here to enable the at91 pinctrl driver +config PINCTRL_AT91PIO4 + bool "AT91 PIO4 pinctrl driver" + depends on OF + depends on ARCH_AT91 + select PINMUX + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP + select OF_GPIO + help + Say Y here to enable the at91 pinctrl/gpio driver for Atmel PIO4 + controller available on sama5d2 SoC. + config PINCTRL_AMD bool "AMD GPIO pin control" depends on GPIOLIB diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index cad077c43fb7..8bed0c2222df 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o +obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c index 7d9482bf8252..1ca783098e47 100644 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c @@ -143,7 +143,7 @@ static inline bool cygnus_get_bit(struct cygnus_gpio *chip, unsigned int reg, return !!(readl(chip->base + offset) & BIT(shift)); } -static void cygnus_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +static void cygnus_gpio_irq_handler(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct cygnus_gpio *chip = to_cygnus_gpio(gc); diff --git a/drivers/pinctrl/berlin/Kconfig b/drivers/pinctrl/berlin/Kconfig index b18322bc7bf9..8fe6ad7795dc 100644 --- a/drivers/pinctrl/berlin/Kconfig +++ b/drivers/pinctrl/berlin/Kconfig @@ -1,4 +1,4 @@ -if ARCH_BERLIN +if (ARCH_BERLIN || COMPILE_TEST) config PINCTRL_BERLIN bool @@ -6,15 +6,23 @@ config PINCTRL_BERLIN select REGMAP_MMIO config PINCTRL_BERLIN_BG2 - bool + def_bool MACH_BERLIN_BG2 + depends on OF select PINCTRL_BERLIN config PINCTRL_BERLIN_BG2CD - bool + def_bool MACH_BERLIN_BG2CD + depends on OF select PINCTRL_BERLIN config PINCTRL_BERLIN_BG2Q - bool + def_bool MACH_BERLIN_BG2Q + depends on OF + select PINCTRL_BERLIN + +config PINCTRL_BERLIN_BG4CT + bool "Marvell berlin4ct pin controller driver" + depends on OF select PINCTRL_BERLIN endif diff --git a/drivers/pinctrl/berlin/Makefile b/drivers/pinctrl/berlin/Makefile index deb0c6baf316..06f94029ad66 100644 --- a/drivers/pinctrl/berlin/Makefile +++ b/drivers/pinctrl/berlin/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_PINCTRL_BERLIN) += berlin.o obj-$(CONFIG_PINCTRL_BERLIN_BG2) += berlin-bg2.o obj-$(CONFIG_PINCTRL_BERLIN_BG2CD) += berlin-bg2cd.o obj-$(CONFIG_PINCTRL_BERLIN_BG2Q) += berlin-bg2q.o +obj-$(CONFIG_PINCTRL_BERLIN_BG4CT) += berlin-bg4ct.o diff --git a/drivers/pinctrl/berlin/berlin-bg2.c b/drivers/pinctrl/berlin/berlin-bg2.c index 274c5535b531..fabe728ae268 100644 --- a/drivers/pinctrl/berlin/berlin-bg2.c +++ b/drivers/pinctrl/berlin/berlin-bg2.c @@ -3,7 +3,7 @@ * * Copyright (C) 2014 Marvell Technology Group Ltd. * - * Antoine Ténart <antoine.tenart@free-electrons.com> + * Antoine Ténart <antoine.tenart@free-electrons.com> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -246,6 +246,6 @@ static struct platform_driver berlin2_pinctrl_driver = { }; module_platform_driver(berlin2_pinctrl_driver); -MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>"); +MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>"); MODULE_DESCRIPTION("Marvell Berlin BG2 pinctrl driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/berlin/berlin-bg2cd.c b/drivers/pinctrl/berlin/berlin-bg2cd.c index 0cb793a3552a..ad8c75861373 100644 --- a/drivers/pinctrl/berlin/berlin-bg2cd.c +++ b/drivers/pinctrl/berlin/berlin-bg2cd.c @@ -3,7 +3,7 @@ * * Copyright (C) 2014 Marvell Technology Group Ltd. * - * Antoine Ténart <antoine.tenart@free-electrons.com> + * Antoine Ténart <antoine.tenart@free-electrons.com> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -19,24 +19,24 @@ static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = { /* G */ - BERLIN_PINCTRL_GROUP("G0", 0x00, 0x1, 0x00, + BERLIN_PINCTRL_GROUP("G0", 0x00, 0x3, 0x00, BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), BERLIN_PINCTRL_FUNCTION(0x2, "led"), BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), - BERLIN_PINCTRL_GROUP("G1", 0x00, 0x2, 0x01, + BERLIN_PINCTRL_GROUP("G1", 0x00, 0x3, 0x03, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), - BERLIN_PINCTRL_GROUP("G2", 0x00, 0x2, 0x02, + BERLIN_PINCTRL_GROUP("G2", 0x00, 0x3, 0x06, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), BERLIN_PINCTRL_FUNCTION(0x2, "fe"), BERLIN_PINCTRL_FUNCTION(0x3, "pll"), BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), - BERLIN_PINCTRL_GROUP("G3", 0x00, 0x2, 0x04, + BERLIN_PINCTRL_GROUP("G3", 0x00, 0x3, 0x09, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), BERLIN_PINCTRL_FUNCTION(0x2, "twsi2"), @@ -44,7 +44,7 @@ static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = { BERLIN_PINCTRL_FUNCTION(0x4, "fe"), BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), - BERLIN_PINCTRL_GROUP("G4", 0x00, 0x2, 0x06, + BERLIN_PINCTRL_GROUP("G4", 0x00, 0x3, 0x0c, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), BERLIN_PINCTRL_FUNCTION(0x2, "twsi3"), @@ -52,7 +52,7 @@ static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = { BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), - BERLIN_PINCTRL_GROUP("G5", 0x00, 0x3, 0x08, + BERLIN_PINCTRL_GROUP("G5", 0x00, 0x3, 0x0f, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), BERLIN_PINCTRL_FUNCTION(0x2, "twsi3"), @@ -60,64 +60,66 @@ static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = { BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), - BERLIN_PINCTRL_GROUP("G6", 0x00, 0x2, 0x0b, + BERLIN_PINCTRL_GROUP("G6", 0x00, 0x3, 0x12, BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RX/TX */ BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), - BERLIN_PINCTRL_GROUP("G7", 0x00, 0x3, 0x0d, + BERLIN_PINCTRL_GROUP("G7", 0x00, 0x3, 0x15, BERLIN_PINCTRL_FUNCTION(0x0, "eddc"), BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"), BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), - BERLIN_PINCTRL_GROUP("G8", 0x00, 0x3, 0x10, + BERLIN_PINCTRL_GROUP("G8", 0x00, 0x3, 0x18, BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n */ BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), - BERLIN_PINCTRL_GROUP("G9", 0x00, 0x3, 0x13, + BERLIN_PINCTRL_GROUP("G9", 0x00, 0x3, 0x1b, BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS1n/SS2n */ - BERLIN_PINCTRL_FUNCTION(0x2, "twsi0")), - BERLIN_PINCTRL_GROUP("G10", 0x00, 0x2, 0x16, + BERLIN_PINCTRL_FUNCTION(0x3, "twsi0")), + BERLIN_PINCTRL_GROUP("G10", 0x00, 0x2, 0x1e, BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* CLK */ BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), - BERLIN_PINCTRL_GROUP("G11", 0x00, 0x2, 0x18, + BERLIN_PINCTRL_GROUP("G11", 0x04, 0x2, 0x00, BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDI/SDO */ BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), - BERLIN_PINCTRL_GROUP("G12", 0x00, 0x3, 0x1a, + BERLIN_PINCTRL_GROUP("G12", 0x04, 0x3, 0x02, BERLIN_PINCTRL_FUNCTION(0x0, "usb1"), BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), - BERLIN_PINCTRL_GROUP("G13", 0x04, 0x3, 0x00, + BERLIN_PINCTRL_GROUP("G13", 0x04, 0x3, 0x05, BERLIN_PINCTRL_FUNCTION(0x0, "nand"), BERLIN_PINCTRL_FUNCTION(0x1, "usb0_dbg"), BERLIN_PINCTRL_FUNCTION(0x2, "usb1_dbg")), - BERLIN_PINCTRL_GROUP("G14", 0x04, 0x1, 0x03, + BERLIN_PINCTRL_GROUP("G14", 0x04, 0x1, 0x08, BERLIN_PINCTRL_FUNCTION(0x0, "nand"), BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), - BERLIN_PINCTRL_GROUP("G15", 0x04, 0x2, 0x04, + BERLIN_PINCTRL_GROUP("G15", 0x04, 0x3, 0x09, BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), - BERLIN_PINCTRL_GROUP("G16", 0x04, 0x3, 0x06, + BERLIN_PINCTRL_GROUP("G16", 0x04, 0x3, 0x0c, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G17", 0x04, 0x3, 0x09, + BERLIN_PINCTRL_GROUP("G17", 0x04, 0x3, 0x0f, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G18", 0x04, 0x1, 0x0c, + BERLIN_PINCTRL_GROUP("G18", 0x04, 0x2, 0x12, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G19", 0x04, 0x1, 0x0d, + BERLIN_PINCTRL_GROUP("G19", 0x04, 0x2, 0x14, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G20", 0x04, 0x1, 0x0e, + BERLIN_PINCTRL_GROUP("G20", 0x04, 0x2, 0x16, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G21", 0x04, 0x3, 0x0f, + BERLIN_PINCTRL_GROUP("G21", 0x04, 0x3, 0x18, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G22", 0x04, 0x3, 0x12, + BERLIN_PINCTRL_GROUP("G22", 0x04, 0x3, 0x1b, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G23", 0x04, 0x3, 0x15, + BERLIN_PINCTRL_GROUP("G23", 0x08, 0x3, 0x00, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G24", 0x04, 0x2, 0x18, + BERLIN_PINCTRL_GROUP("G24", 0x08, 0x2, 0x03, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G25", 0x04, 0x2, 0x1a, + BERLIN_PINCTRL_GROUP("G25", 0x08, 0x2, 0x05, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G26", 0x04, 0x1, 0x1c, + BERLIN_PINCTRL_GROUP("G26", 0x08, 0x1, 0x07, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G27", 0x04, 0x1, 0x1d, + BERLIN_PINCTRL_GROUP("G27", 0x08, 0x2, 0x08, BERLIN_PINCTRL_FUNCTION_UNKNOWN), - BERLIN_PINCTRL_GROUP("G28", 0x04, 0x2, 0x1e, + BERLIN_PINCTRL_GROUP("G28", 0x08, 0x3, 0x0a, + BERLIN_PINCTRL_FUNCTION_UNKNOWN), + BERLIN_PINCTRL_GROUP("G29", 0x08, 0x3, 0x0d, BERLIN_PINCTRL_FUNCTION_UNKNOWN), }; @@ -189,6 +191,6 @@ static struct platform_driver berlin2cd_pinctrl_driver = { }; module_platform_driver(berlin2cd_pinctrl_driver); -MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>"); +MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>"); MODULE_DESCRIPTION("Marvell Berlin BG2CD pinctrl driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/berlin/berlin-bg2q.c b/drivers/pinctrl/berlin/berlin-bg2q.c index a466054a8206..cd171aea8ca8 100644 --- a/drivers/pinctrl/berlin/berlin-bg2q.c +++ b/drivers/pinctrl/berlin/berlin-bg2q.c @@ -3,7 +3,7 @@ * * Copyright (C) 2014 Marvell Technology Group Ltd. * - * Antoine Ténart <antoine.tenart@free-electrons.com> + * Antoine Ténart <antoine.tenart@free-electrons.com> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -408,6 +408,6 @@ static struct platform_driver berlin2q_pinctrl_driver = { }; module_platform_driver(berlin2q_pinctrl_driver); -MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>"); +MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>"); MODULE_DESCRIPTION("Marvell Berlin BG2Q pinctrl driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/berlin/berlin-bg4ct.c b/drivers/pinctrl/berlin/berlin-bg4ct.c new file mode 100644 index 000000000000..09172043d589 --- /dev/null +++ b/drivers/pinctrl/berlin/berlin-bg4ct.c @@ -0,0 +1,503 @@ +/* + * Marvell berlin4ct pinctrl driver + * + * Copyright (C) 2015 Marvell Technology Group Ltd. + * + * Author: Jisheng Zhang <jszhang@marvell.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include "berlin.h" + +static const struct berlin_desc_group berlin4ct_soc_pinctrl_groups[] = { + BERLIN_PINCTRL_GROUP("EMMC_RSTn", 0x0, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "emmc"), /* RSTn */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* GPIO47 */ + BERLIN_PINCTRL_GROUP("NAND_IO0", 0x0, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO0 */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXD0 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* CLK */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO0 */ + BERLIN_PINCTRL_GROUP("NAND_IO1", 0x0, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO1 */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXD1 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* CDn */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO1 */ + BERLIN_PINCTRL_GROUP("NAND_IO2", 0x0, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO2 */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXD2 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT0 */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO2 */ + BERLIN_PINCTRL_GROUP("NAND_IO3", 0x0, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO3 */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXD3 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT1 */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO3 */ + BERLIN_PINCTRL_GROUP("NAND_IO4", 0x0, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO4 */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXC */ + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT2 */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO4 */ + BERLIN_PINCTRL_GROUP("NAND_IO5", 0x0, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO5 */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXCTL */ + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT3 */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO5 */ + BERLIN_PINCTRL_GROUP("NAND_IO6", 0x0, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO6 */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* MDC */ + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* CMD */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO6 */ + BERLIN_PINCTRL_GROUP("NAND_IO7", 0x0, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO7 */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* MDIO */ + BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* WP */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO7 */ + BERLIN_PINCTRL_GROUP("NAND_ALE", 0x0, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* ALE */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXD0 */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO8 */ + BERLIN_PINCTRL_GROUP("NAND_CLE", 0x4, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* CLE */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXD1 */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO9 */ + BERLIN_PINCTRL_GROUP("NAND_WEn", 0x4, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* WEn */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXD2 */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO10 */ + BERLIN_PINCTRL_GROUP("NAND_REn", 0x4, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* REn */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXD3 */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO11 */ + BERLIN_PINCTRL_GROUP("NAND_WPn", 0x4, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* WPn */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO12 */ + BERLIN_PINCTRL_GROUP("NAND_CEn", 0x4, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* CEn */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXC */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO13 */ + BERLIN_PINCTRL_GROUP("NAND_RDY", 0x4, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* RDY */ + BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXCTL */ + BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO14 */ + BERLIN_PINCTRL_GROUP("SD0_CLK", 0x4, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO29 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* CLK*/ + BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* CLK */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG8 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG8 */ + BERLIN_PINCTRL_GROUP("SD0_DAT0", 0x4, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO30 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT0 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* SOP */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG9 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG9 */ + BERLIN_PINCTRL_GROUP("SD0_DAT1", 0x4, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO31 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT1 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* SD */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG10 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG10 */ + BERLIN_PINCTRL_GROUP("SD0_DAT2", 0x4, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO32 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT2 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* VALD */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG11 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG11 */ + BERLIN_PINCTRL_GROUP("SD0_DAT3", 0x8, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO33 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT3 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* CLK */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG12 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG12 */ + BERLIN_PINCTRL_GROUP("SD0_CDn", 0x8, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO34 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* CDn */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* SOP */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG13 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG13 */ + BERLIN_PINCTRL_GROUP("SD0_CMD", 0x8, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO35 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* CMD */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* SD */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG14 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG14 */ + BERLIN_PINCTRL_GROUP("SD0_WP", 0x8, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO36 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* WP */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* VALD */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG15 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG15 */ + BERLIN_PINCTRL_GROUP("STS0_CLK", 0x8, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO21 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), /* CLK */ + BERLIN_PINCTRL_FUNCTION(0x2, "cpupll"), /* CLKO */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG0 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG0 */ + BERLIN_PINCTRL_GROUP("STS0_SOP", 0x8, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO22 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), /* SOP */ + BERLIN_PINCTRL_FUNCTION(0x2, "syspll"), /* CLKO */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG1 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG1 */ + BERLIN_PINCTRL_GROUP("STS0_SD", 0x8, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO23 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), /* SD */ + BERLIN_PINCTRL_FUNCTION(0x2, "mempll"), /* CLKO */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG2 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG2 */ + BERLIN_PINCTRL_GROUP("STS0_VALD", 0x8, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO24 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), /* VALD */ + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG3 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG3 */ + BERLIN_PINCTRL_GROUP("STS1_CLK", 0x8, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO25 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), /* CLK */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm0"), + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG4 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG4 */ + BERLIN_PINCTRL_GROUP("STS1_SOP", 0x8, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO26 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), /* SOP */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm1"), + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG5 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG5 */ + BERLIN_PINCTRL_GROUP("STS1_SD", 0xc, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO27 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), /* SD */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm2"), + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG6 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG6 */ + BERLIN_PINCTRL_GROUP("STS1_VALD", 0xc, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO28 */ + BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), /* VALD */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm3"), + BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG7 */ + BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG7 */ + BERLIN_PINCTRL_GROUP("SCRD0_RST", 0xc, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO15 */ + BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* RST */ + BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* CLK */ + BERLIN_PINCTRL_GROUP("SCRD0_DCLK", 0xc, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO16 */ + BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* DCLK */ + BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* CMD */ + BERLIN_PINCTRL_GROUP("SCRD0_GPIO0", 0xc, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO17 */ + BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* SCRD0 GPIO0 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sif"), /* DIO */ + BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* DAT0 */ + BERLIN_PINCTRL_GROUP("SCRD0_GPIO1", 0xc, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO18 */ + BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* SCRD0 GPIO1 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sif"), /* CLK */ + BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* DAT1 */ + BERLIN_PINCTRL_GROUP("SCRD0_DIO", 0xc, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO19 */ + BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* DIO */ + BERLIN_PINCTRL_FUNCTION(0x2, "sif"), /* DEN */ + BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* DAT2 */ + BERLIN_PINCTRL_GROUP("SCRD0_CRD_PRES", 0xc, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO20 */ + BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* crd pres */ + BERLIN_PINCTRL_FUNCTION(0x1, "sd1a")), /* DAT3 */ + BERLIN_PINCTRL_GROUP("SPI1_SS0n", 0xc, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO37 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts2")), /* CLK */ + BERLIN_PINCTRL_GROUP("SPI1_SS1n", 0xc, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS1n */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO38 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts2"), /* SOP */ + BERLIN_PINCTRL_FUNCTION(0x4, "pwm1")), + BERLIN_PINCTRL_GROUP("SPI1_SS2n", 0x10, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS2n */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO39 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts2"), /* SD */ + BERLIN_PINCTRL_FUNCTION(0x4, "pwm0")), + BERLIN_PINCTRL_GROUP("SPI1_SS3n", 0x10, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS3n */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO40 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts2")), /* VALD */ + BERLIN_PINCTRL_GROUP("SPI1_SCLK", 0x10, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SCLK */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO41 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* CLK */ + BERLIN_PINCTRL_GROUP("SPI1_SDO", 0x10, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDO */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO42 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* SOP */ + BERLIN_PINCTRL_GROUP("SPI1_SDI", 0x10, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDI */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO43 */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* SD */ + BERLIN_PINCTRL_GROUP("USB0_DRV_VBUS", 0x10, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO44 */ + BERLIN_PINCTRL_FUNCTION(0x1, "usb0"), /* VBUS */ + BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* VALD */ + BERLIN_PINCTRL_GROUP("TW0_SCL", 0x10, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO45 */ + BERLIN_PINCTRL_FUNCTION(0x1, "tw0")), /* SCL */ + BERLIN_PINCTRL_GROUP("TW0_SDA", 0x10, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO46 */ + BERLIN_PINCTRL_FUNCTION(0x1, "tw0")), /* SDA */ +}; + +static const struct berlin_desc_group berlin4ct_avio_pinctrl_groups[] = { + BERLIN_PINCTRL_GROUP("TX_EDDC_SCL", 0x0, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO0 */ + BERLIN_PINCTRL_FUNCTION(0x1, "tx_eddc"), /* SCL */ + BERLIN_PINCTRL_FUNCTION(0x2, "tw1")), /* SCL */ + BERLIN_PINCTRL_GROUP("TX_EDDC_SDA", 0x0, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO1 */ + BERLIN_PINCTRL_FUNCTION(0x1, "tx_eddc"), /* SDA */ + BERLIN_PINCTRL_FUNCTION(0x2, "tw1")), /* SDA */ + BERLIN_PINCTRL_GROUP("I2S1_LRCKO", 0x0, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO2 */ + BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* LRCKO */ + BERLIN_PINCTRL_FUNCTION(0x3, "sts6"), /* CLK */ + BERLIN_PINCTRL_FUNCTION(0x4, "adac"), /* DBG0 */ + BERLIN_PINCTRL_FUNCTION(0x6, "sd1b"), /* CLK */ + BERLIN_PINCTRL_FUNCTION(0x7, "avio")), /* DBG0 */ + BERLIN_PINCTRL_GROUP("I2S1_BCLKO", 0x0, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO3 */ + BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* BCLKO */ + BERLIN_PINCTRL_FUNCTION(0x3, "sts6"), /* SOP */ + BERLIN_PINCTRL_FUNCTION(0x4, "adac"), /* DBG1 */ + BERLIN_PINCTRL_FUNCTION(0x6, "sd1b"), /* CMD */ + BERLIN_PINCTRL_FUNCTION(0x7, "avio")), /* DBG1 */ + BERLIN_PINCTRL_GROUP("I2S1_DO", 0x0, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO4 */ + BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* DO */ + BERLIN_PINCTRL_FUNCTION(0x3, "sts6"), /* SD */ + BERLIN_PINCTRL_FUNCTION(0x4, "adac"), /* DBG2 */ + BERLIN_PINCTRL_FUNCTION(0x6, "sd1b"), /* DAT0 */ + BERLIN_PINCTRL_FUNCTION(0x7, "avio")), /* DBG2 */ + BERLIN_PINCTRL_GROUP("I2S1_MCLK", 0x0, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO5 */ + BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* MCLK */ + BERLIN_PINCTRL_FUNCTION(0x3, "sts6"), /* VALD */ + BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* MCLK */ + BERLIN_PINCTRL_FUNCTION(0x6, "sd1b"), /* DAT1 */ + BERLIN_PINCTRL_FUNCTION(0x7, "avio")), /* DBG3 */ + BERLIN_PINCTRL_GROUP("SPDIFO", 0x0, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO6 */ + BERLIN_PINCTRL_FUNCTION(0x1, "spdifo"), + BERLIN_PINCTRL_FUNCTION(0x2, "avpll"), /* CLKO */ + BERLIN_PINCTRL_FUNCTION(0x4, "adac")), /* DBG3 */ + BERLIN_PINCTRL_GROUP("I2S2_MCLK", 0x0, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO7 */ + BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* MCLK */ + BERLIN_PINCTRL_FUNCTION(0x4, "hdmi"), /* FBCLK */ + BERLIN_PINCTRL_FUNCTION(0x5, "pdm")), /* CLKO */ + BERLIN_PINCTRL_GROUP("I2S2_LRCKI", 0x0, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO8 */ + BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* LRCKI */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm0"), + BERLIN_PINCTRL_FUNCTION(0x3, "sts7"), /* CLK */ + BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* LRCK */ + BERLIN_PINCTRL_FUNCTION(0x6, "sd1b")), /* DAT2 */ + BERLIN_PINCTRL_GROUP("I2S2_BCLKI", 0x0, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO9 */ + BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* BCLKI */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm1"), + BERLIN_PINCTRL_FUNCTION(0x3, "sts7"), /* SOP */ + BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* BCLK */ + BERLIN_PINCTRL_FUNCTION(0x6, "sd1b")), /* DAT3 */ + BERLIN_PINCTRL_GROUP("I2S2_DI0", 0x4, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO10 */ + BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI0 */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm2"), + BERLIN_PINCTRL_FUNCTION(0x3, "sts7"), /* SD */ + BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* SDIN */ + BERLIN_PINCTRL_FUNCTION(0x5, "pdm"), /* DI0 */ + BERLIN_PINCTRL_FUNCTION(0x6, "sd1b")), /* CDn */ + BERLIN_PINCTRL_GROUP("I2S2_DI1", 0x4, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO11 */ + BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI1 */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm3"), + BERLIN_PINCTRL_FUNCTION(0x3, "sts7"), /* VALD */ + BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* PWMCLK */ + BERLIN_PINCTRL_FUNCTION(0x5, "pdm"), /* DI1 */ + BERLIN_PINCTRL_FUNCTION(0x6, "sd1b")), /* WP */ +}; + +static const struct berlin_desc_group berlin4ct_sysmgr_pinctrl_groups[] = { + BERLIN_PINCTRL_GROUP("SM_TW2_SCL", 0x0, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO19 */ + BERLIN_PINCTRL_FUNCTION(0x1, "tw2")), /* SCL */ + BERLIN_PINCTRL_GROUP("SM_TW2_SDA", 0x0, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO20 */ + BERLIN_PINCTRL_FUNCTION(0x1, "tw2")), /* SDA */ + BERLIN_PINCTRL_GROUP("SM_TW3_SCL", 0x0, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO21 */ + BERLIN_PINCTRL_FUNCTION(0x1, "tw3")), /* SCL */ + BERLIN_PINCTRL_GROUP("SM_TW3_SDA", 0x0, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO22 */ + BERLIN_PINCTRL_FUNCTION(0x1, "tw3")), /* SDA */ + BERLIN_PINCTRL_GROUP("SM_TMS", 0x0, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TMS */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* SM GPIO0 */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm0")), + BERLIN_PINCTRL_GROUP("SM_TDI", 0x0, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TDI */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* SM GPIO1 */ + BERLIN_PINCTRL_FUNCTION(0x2, "pwm1")), + BERLIN_PINCTRL_GROUP("SM_TDO", 0x0, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TDO */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO2 */ + BERLIN_PINCTRL_GROUP("SM_URT0_TXD", 0x0, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* TXD */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO3 */ + BERLIN_PINCTRL_GROUP("SM_URT0_RXD", 0x0, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RXD */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO4 */ + BERLIN_PINCTRL_GROUP("SM_URT1_TXD", 0x0, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO5 */ + BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* TXD */ + BERLIN_PINCTRL_FUNCTION(0x2, "eth1"), /* RXCLK */ + BERLIN_PINCTRL_FUNCTION(0x3, "pwm2"), + BERLIN_PINCTRL_FUNCTION(0x4, "timer0"), + BERLIN_PINCTRL_FUNCTION(0x5, "clk_25m")), + BERLIN_PINCTRL_GROUP("SM_URT1_RXD", 0x4, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO6 */ + BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* RXD */ + BERLIN_PINCTRL_FUNCTION(0x3, "pwm3"), + BERLIN_PINCTRL_FUNCTION(0x4, "timer1")), + BERLIN_PINCTRL_GROUP("SM_SPI2_SS0n", 0x4, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "spi2"), /* SS0 n*/ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO7 */ + BERLIN_PINCTRL_GROUP("SM_SPI2_SS1n", 0x4, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO8 */ + BERLIN_PINCTRL_FUNCTION(0x1, "spi2")), /* SS1n */ + BERLIN_PINCTRL_GROUP("SM_SPI2_SS2n", 0x4, 0x3, 0x09, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO9 */ + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS2n */ + BERLIN_PINCTRL_FUNCTION(0x2, "eth1"), /* MDC */ + BERLIN_PINCTRL_FUNCTION(0x3, "pwm0"), + BERLIN_PINCTRL_FUNCTION(0x4, "timer0"), + BERLIN_PINCTRL_FUNCTION(0x5, "clk_25m")), + BERLIN_PINCTRL_GROUP("SM_SPI2_SS3n", 0x4, 0x3, 0x0c, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO10 */ + BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS3n */ + BERLIN_PINCTRL_FUNCTION(0x2, "eth1"), /* MDIO */ + BERLIN_PINCTRL_FUNCTION(0x3, "pwm1"), + BERLIN_PINCTRL_FUNCTION(0x4, "timer1")), + BERLIN_PINCTRL_GROUP("SM_SPI2_SDO", 0x4, 0x3, 0x0f, + BERLIN_PINCTRL_FUNCTION(0x0, "spi2"), /* SDO */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO11 */ + BERLIN_PINCTRL_GROUP("SM_SPI2_SDI", 0x4, 0x3, 0x12, + BERLIN_PINCTRL_FUNCTION(0x0, "spi2"), /* SDI */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO12 */ + BERLIN_PINCTRL_GROUP("SM_SPI2_SCLK", 0x4, 0x3, 0x15, + BERLIN_PINCTRL_FUNCTION(0x0, "spi2"), /* SCLK */ + BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO13 */ + BERLIN_PINCTRL_GROUP("SM_FE_LED0", 0x4, 0x3, 0x18, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO14 */ + BERLIN_PINCTRL_FUNCTION(0x2, "led")), /* LED0 */ + BERLIN_PINCTRL_GROUP("SM_FE_LED1", 0x4, 0x3, 0x1b, + BERLIN_PINCTRL_FUNCTION(0x0, "pwr"), + BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* SM GPIO 15 */ + BERLIN_PINCTRL_FUNCTION(0x2, "led")), /* LED1 */ + BERLIN_PINCTRL_GROUP("SM_FE_LED2", 0x8, 0x3, 0x00, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO16 */ + BERLIN_PINCTRL_FUNCTION(0x2, "led")), /* LED2 */ + BERLIN_PINCTRL_GROUP("SM_HDMI_HPD", 0x8, 0x3, 0x03, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO17 */ + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), /* HPD */ + BERLIN_PINCTRL_GROUP("SM_HDMI_CEC", 0x8, 0x3, 0x06, + BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO18 */ + BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), /* CEC */ +}; + +static const struct berlin_pinctrl_desc berlin4ct_soc_pinctrl_data = { + .groups = berlin4ct_soc_pinctrl_groups, + .ngroups = ARRAY_SIZE(berlin4ct_soc_pinctrl_groups), +}; + +static const struct berlin_pinctrl_desc berlin4ct_avio_pinctrl_data = { + .groups = berlin4ct_avio_pinctrl_groups, + .ngroups = ARRAY_SIZE(berlin4ct_avio_pinctrl_groups), +}; + +static const struct berlin_pinctrl_desc berlin4ct_sysmgr_pinctrl_data = { + .groups = berlin4ct_sysmgr_pinctrl_groups, + .ngroups = ARRAY_SIZE(berlin4ct_sysmgr_pinctrl_groups), +}; + +static const struct of_device_id berlin4ct_pinctrl_match[] = { + { + .compatible = "marvell,berlin4ct-soc-pinctrl", + .data = &berlin4ct_soc_pinctrl_data, + }, + { + .compatible = "marvell,berlin4ct-avio-pinctrl", + .data = &berlin4ct_avio_pinctrl_data, + }, + { + .compatible = "marvell,berlin4ct-system-pinctrl", + .data = &berlin4ct_sysmgr_pinctrl_data, + }, + {} +}; +MODULE_DEVICE_TABLE(of, berlin4ct_pinctrl_match); + +static int berlin4ct_pinctrl_probe(struct platform_device *pdev) +{ + const struct of_device_id *match = + of_match_device(berlin4ct_pinctrl_match, &pdev->dev); + struct regmap_config *rmconfig; + struct regmap *regmap; + struct resource *res; + void __iomem *base; + + rmconfig = devm_kzalloc(&pdev->dev, sizeof(*rmconfig), GFP_KERNEL); + if (!rmconfig) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + rmconfig->reg_bits = 32, + rmconfig->val_bits = 32, + rmconfig->reg_stride = 4, + rmconfig->max_register = resource_size(res); + + regmap = devm_regmap_init_mmio(&pdev->dev, base, rmconfig); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return berlin_pinctrl_probe_regmap(pdev, match->data, regmap); +} + +static struct platform_driver berlin4ct_pinctrl_driver = { + .probe = berlin4ct_pinctrl_probe, + .driver = { + .name = "berlin4ct-pinctrl", + .of_match_table = berlin4ct_pinctrl_match, + }, +}; +module_platform_driver(berlin4ct_pinctrl_driver); + +MODULE_AUTHOR("Jisheng Zhang <jszhang@marvell.com>"); +MODULE_DESCRIPTION("Marvell berlin4ct pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c index f49580617055..46f2b4818da3 100644 --- a/drivers/pinctrl/berlin/berlin.c +++ b/drivers/pinctrl/berlin/berlin.c @@ -3,7 +3,7 @@ * * Copyright (C) 2014 Marvell Technology Group Ltd. * - * Antoine Ténart <antoine.tenart@free-electrons.com> + * Antoine Ténart <antoine.tenart@free-electrons.com> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -292,20 +292,14 @@ static struct pinctrl_desc berlin_pctrl_desc = { .owner = THIS_MODULE, }; -int berlin_pinctrl_probe(struct platform_device *pdev, - const struct berlin_pinctrl_desc *desc) +int berlin_pinctrl_probe_regmap(struct platform_device *pdev, + const struct berlin_pinctrl_desc *desc, + struct regmap *regmap) { struct device *dev = &pdev->dev; - struct device_node *parent_np = of_get_parent(dev->of_node); struct berlin_pinctrl *pctrl; - struct regmap *regmap; int ret; - regmap = syscon_node_to_regmap(parent_np); - of_node_put(parent_np); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); if (!pctrl) return -ENOMEM; @@ -330,3 +324,17 @@ int berlin_pinctrl_probe(struct platform_device *pdev, return 0; } + +int berlin_pinctrl_probe(struct platform_device *pdev, + const struct berlin_pinctrl_desc *desc) +{ + struct device *dev = &pdev->dev; + struct device_node *parent_np = of_get_parent(dev->of_node); + struct regmap *regmap = syscon_node_to_regmap(parent_np); + + of_node_put(parent_np); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return berlin_pinctrl_probe_regmap(pdev, desc, regmap); +} diff --git a/drivers/pinctrl/berlin/berlin.h b/drivers/pinctrl/berlin/berlin.h index e1aa84145194..e9b30f95b03e 100644 --- a/drivers/pinctrl/berlin/berlin.h +++ b/drivers/pinctrl/berlin/berlin.h @@ -3,7 +3,7 @@ * * Copyright (C) 2014 Marvell Technology Group Ltd. * - * Antoine Ténart <antoine.tenart@free-electrons.com> + * Antoine Ténart <antoine.tenart@free-electrons.com> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -58,4 +58,8 @@ struct berlin_pinctrl_function { int berlin_pinctrl_probe(struct platform_device *pdev, const struct berlin_pinctrl_desc *desc); +int berlin_pinctrl_probe_regmap(struct platform_device *pdev, + const struct berlin_pinctrl_desc *desc, + struct regmap *regmap); + #endif /* __PINCTRL_BERLIN_H */ diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 69723e07036b..9638a00c67c2 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -349,6 +349,9 @@ static bool pinctrl_ready_for_gpio_range(unsigned gpio) struct pinctrl_gpio_range *range = NULL; struct gpio_chip *chip = gpio_to_chip(gpio); + if (WARN(!chip, "no gpio_chip for gpio%i?", gpio)) + return false; + mutex_lock(&pinctrldev_list_mutex); /* Loop over the pin controllers */ diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index d7b98ba36825..a5bb93987378 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -18,6 +18,7 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/of_device.h> +#include <linux/of_address.h> #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> @@ -39,6 +40,7 @@ struct imx_pinctrl { struct device *dev; struct pinctrl_dev *pctl; void __iomem *base; + void __iomem *input_sel_base; const struct imx_pinctrl_soc_info *info; }; @@ -254,7 +256,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, * Regular select input register can never be at offset * 0, and we only print register value for regular case. */ - writel(pin->input_val, ipctl->base + pin->input_reg); + if (ipctl->input_sel_base) + writel(pin->input_val, ipctl->input_sel_base + + pin->input_reg); + else + writel(pin->input_val, ipctl->base + + pin->input_reg); dev_dbg(ipctl->dev, "==>select_input: offset 0x%x val 0x%x\n", pin->input_reg, pin->input_val); @@ -542,6 +549,9 @@ static int imx_pinctrl_parse_groups(struct device_node *np, struct imx_pin_reg *pin_reg; struct imx_pin *pin = &grp->pins[i]; + if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) + mux_reg = -1; + if (info->flags & SHARE_MUX_CONF_REG) { conf_reg = mux_reg; } else { @@ -550,7 +560,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np, conf_reg = -1; } - pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4; + pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; pin_reg = &info->pin_regs[pin_id]; pin->pin = pin_id; grp->pin_ids[i] = pin_id; @@ -580,7 +590,6 @@ static int imx_pinctrl_parse_functions(struct device_node *np, struct device_node *child; struct imx_pmx_func *func; struct imx_pin_group *grp; - static u32 grp_index; u32 i = 0; dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); @@ -599,7 +608,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np, for_each_child_of_node(np, child) { func->groups[i] = child->name; - grp = &info->groups[grp_index++]; + grp = &info->groups[info->group_index++]; imx_pinctrl_parse_groups(child, grp, info, i++); } @@ -683,6 +692,8 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev, int imx_pinctrl_probe(struct platform_device *pdev, struct imx_pinctrl_soc_info *info) { + struct device_node *dev_np = pdev->dev.of_node; + struct device_node *np; struct imx_pinctrl *ipctl; struct resource *res; int ret, i; @@ -713,6 +724,23 @@ int imx_pinctrl_probe(struct platform_device *pdev, if (IS_ERR(ipctl->base)) return PTR_ERR(ipctl->base); + if (of_property_read_bool(dev_np, "fsl,input-sel")) { + np = of_parse_phandle(dev_np, "fsl,input-sel", 0); + if (np) { + ipctl->input_sel_base = of_iomap(np, 0); + if (IS_ERR(ipctl->input_sel_base)) { + of_node_put(np); + dev_err(&pdev->dev, + "iomuxc input select base address not found\n"); + return PTR_ERR(ipctl->input_sel_base); + } + } else { + dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); + return -EINVAL; + } + of_node_put(np); + } + imx_pinctrl_desc.name = dev_name(&pdev->dev); imx_pinctrl_desc.pins = info->pins; imx_pinctrl_desc.npins = info->npins; diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h index 49e55d39f7c8..2a592f657c18 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -78,12 +78,14 @@ struct imx_pinctrl_soc_info { struct imx_pin_reg *pin_regs; struct imx_pin_group *groups; unsigned int ngroups; + unsigned int group_index; struct imx_pmx_func *functions; unsigned int nfunctions; unsigned int flags; }; #define SHARE_MUX_CONF_REG 0x1 +#define ZERO_OFFSET_VALID 0x2 #define NO_MUX 0x0 #define NO_PAD 0x0 diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c b/drivers/pinctrl/freescale/pinctrl-imx7d.c index 1fa7530530dd..16dc925117de 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx7d.c +++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c @@ -174,6 +174,17 @@ enum imx7d_pads { MX7D_PAD_ENET1_COL = 154, }; +enum imx7d_lpsr_pads { + MX7D_PAD_GPIO1_IO00 = 0, + MX7D_PAD_GPIO1_IO01 = 1, + MX7D_PAD_GPIO1_IO02 = 2, + MX7D_PAD_GPIO1_IO03 = 3, + MX7D_PAD_GPIO1_IO04 = 4, + MX7D_PAD_GPIO1_IO05 = 5, + MX7D_PAD_GPIO1_IO06 = 6, + MX7D_PAD_GPIO1_IO07 = 7, +}; + /* Pad names for the pinmux subsystem */ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0), @@ -333,13 +344,32 @@ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL), }; +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07), +}; + static struct imx_pinctrl_soc_info imx7d_pinctrl_info = { .pins = imx7d_pinctrl_pads, .npins = ARRAY_SIZE(imx7d_pinctrl_pads), }; +static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = { + .pins = imx7d_lpsr_pinctrl_pads, + .npins = ARRAY_SIZE(imx7d_lpsr_pinctrl_pads), + .flags = ZERO_OFFSET_VALID, +}; + static struct of_device_id imx7d_pinctrl_of_match[] = { { .compatible = "fsl,imx7d-iomuxc", .data = &imx7d_pinctrl_info, }, + { .compatible = "fsl,imx7d-iomuxc-lpsr", .data = &imx7d_lpsr_pinctrl_info }, { /* sentinel */ } }; diff --git a/drivers/pinctrl/freescale/pinctrl-mxs.c b/drivers/pinctrl/freescale/pinctrl-mxs.c index f64eecb24755..6bbda6b4ab50 100644 --- a/drivers/pinctrl/freescale/pinctrl-mxs.c +++ b/drivers/pinctrl/freescale/pinctrl-mxs.c @@ -474,7 +474,7 @@ static int mxs_pinctrl_probe_dt(struct platform_device *pdev, f->name = fn = child->name; } f->ngroups++; - }; + } /* Get groups for each function */ idxf = 0; diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index dac4865f3203..b59ce75b1947 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -425,7 +425,7 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) } } -static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc) +static void byt_gpio_irq_handler(struct irq_desc *desc) { struct irq_data *data = irq_desc_get_irq_data(desc); struct byt_gpio *vg = to_byt_gpio(irq_desc_get_handler_data(desc)); @@ -696,6 +696,7 @@ static int byt_gpio_resume(struct device *dev) } #endif +#ifdef CONFIG_PM static int byt_gpio_runtime_suspend(struct device *dev) { return 0; @@ -705,6 +706,7 @@ static int byt_gpio_runtime_resume(struct device *dev) { return 0; } +#endif static const struct dev_pm_ops byt_gpio_pm_ops = { SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 2d5d3ddc36e5..270c127e03ea 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1414,7 +1414,7 @@ static struct irq_chip chv_gpio_irqchip = { .flags = IRQCHIP_SKIP_SET_WAKE, }; -static void chv_gpio_irq_handler(unsigned irq, struct irq_desc *desc) +static void chv_gpio_irq_handler(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index bb377c110541..613ba1b1e0b7 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -836,7 +836,7 @@ static void intel_gpio_community_irq_handler(struct gpio_chip *gc, } } -static void intel_gpio_irq_handler(unsigned irq, struct irq_desc *desc) +static void intel_gpio_irq_handler(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc); @@ -861,26 +861,6 @@ static struct irq_chip intel_gpio_irqchip = { .irq_set_wake = intel_gpio_irq_wake, }; -static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) -{ - size_t i; - - for (i = 0; i < pctrl->ncommunities; i++) { - const struct intel_community *community; - void __iomem *base; - unsigned gpp; - - community = &pctrl->communities[i]; - base = community->regs; - - for (gpp = 0; gpp < community->ngpps; gpp++) { - /* Mask and clear all interrupts */ - writel(0, base + community->ie_offset + gpp * 4); - writel(0xffff, base + GPI_IS + gpp * 4); - } - } -} - static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) { int ret; @@ -1087,6 +1067,26 @@ int intel_pinctrl_suspend(struct device *dev) } EXPORT_SYMBOL_GPL(intel_pinctrl_suspend); +static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) +{ + size_t i; + + for (i = 0; i < pctrl->ncommunities; i++) { + const struct intel_community *community; + void __iomem *base; + unsigned gpp; + + community = &pctrl->communities[i]; + base = community->regs; + + for (gpp = 0; gpp < community->ngpps; gpp++) { + /* Mask and clear all interrupts */ + writel(0, base + community->ie_offset + gpp * 4); + writel(0xffff, base + GPI_IS + gpp * 4); + } + } +} + int intel_pinctrl_resume(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 7726c6caaf83..5279e230e1b5 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -899,7 +899,7 @@ static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq) int start_level, curr_level; unsigned int reg_offset; const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets); - u32 mask = 1 << (hwirq & 0x1f); + u32 mask = BIT(hwirq & 0x1f); u32 port = (hwirq >> 5) & eint_offsets->port_mask; void __iomem *reg = pctl->eint_reg_base + (port << 2); const struct mtk_desc_pin *pin; @@ -1190,7 +1190,7 @@ mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index) } } -static void mtk_eint_irq_handler(unsigned irq, struct irq_desc *desc) +static void mtk_eint_irq_handler(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); struct mtk_pinctrl *pctl = irq_desc_get_handler_data(desc); @@ -1436,7 +1436,7 @@ int mtk_pctrl_init(struct platform_device *pdev, irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip, handle_level_irq); irq_set_chip_data(virq, pctl); - }; + } irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl); return 0; diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index 352ede13a9e9..96cf03908e93 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -860,7 +860,7 @@ static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status) chained_irq_exit(host_chip, desc); } -static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +static void nmk_gpio_irq_handler(struct irq_desc *desc) { struct gpio_chip *chip = irq_desc_get_handler_data(desc); struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); @@ -873,7 +873,7 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) __nmk_gpio_irq_handler(desc, status); } -static void nmk_gpio_latent_irq_handler(unsigned int irq, struct irq_desc *desc) +static void nmk_gpio_latent_irq_handler(struct irq_desc *desc) { struct gpio_chip *chip = irq_desc_get_handler_data(desc); struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index e63ad9fbd388..099a3442ff42 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -28,25 +28,25 @@ #ifdef CONFIG_DEBUG_FS static const struct pin_config_item conf_items[] = { + PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL, false), PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL, false), PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL, false), - PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL, false), - PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL, false), PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL, false), PCONFDUMP(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, "input bias pull to pin specific state", NULL, false), - PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL, false), + PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL, false), PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL, false), PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL, false), + PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL, false), PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH, "output drive strength", "mA", true), + PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec", true), PCONFDUMP(PIN_CONFIG_INPUT_ENABLE, "input enabled", NULL, false), - PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL, false), PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL, false), - PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec", true), - PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true), - PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true), + PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL, false), PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, "pin low power", "mode", true), PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true), + PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true), + PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true), }; static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev, @@ -150,27 +150,28 @@ EXPORT_SYMBOL_GPL(pinconf_generic_dump_config); #ifdef CONFIG_OF static const struct pinconf_generic_params dt_params[] = { + { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, { "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 }, - { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, - { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 }, - { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 }, + { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 }, { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, - { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, - { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "input-schmitt", PIN_CONFIG_INPUT_SCHMITT, 0 }, { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, - { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, - { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, - { "low-power-enable", PIN_CONFIG_LOW_POWER_MODE, 1 }, + { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, { "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 }, - { "output-low", PIN_CONFIG_OUTPUT, 0, }, + { "low-power-enable", PIN_CONFIG_LOW_POWER_MODE, 1 }, { "output-high", PIN_CONFIG_OUTPUT, 1, }, - { "slew-rate", PIN_CONFIG_SLEW_RATE, 0}, + { "output-low", PIN_CONFIG_OUTPUT, 0, }, + { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, + { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, }; /** diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c index a5976ebc4482..f6be68518c87 100644 --- a/drivers/pinctrl/pinctrl-adi2.c +++ b/drivers/pinctrl/pinctrl-adi2.c @@ -530,8 +530,7 @@ static inline void preflow_handler(struct irq_desc *desc) static inline void preflow_handler(struct irq_desc *desc) { } #endif -static void adi_gpio_handle_pint_irq(unsigned int inta_irq, - struct irq_desc *desc) +static void adi_gpio_handle_pint_irq(struct irq_desc *desc) { u32 request; u32 level_mask, hwirq; diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 5e86bb8ca80e..3318f1d6193c 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -492,15 +492,15 @@ static struct irq_chip amd_gpio_irqchip = { .irq_set_type = amd_gpio_irq_set_type, }; -static void amd_gpio_irq_handler(unsigned int __irq, struct irq_desc *desc) +static void amd_gpio_irq_handler(struct irq_desc *desc) { - unsigned int irq = irq_desc_get_irq(desc); u32 i; u32 off; u32 reg; u32 pin_reg; u64 reg64; int handled = 0; + unsigned int irq; unsigned long flags; struct irq_chip *chip = irq_desc_get_chip(desc); struct gpio_chip *gc = irq_desc_get_handler_data(desc); @@ -541,7 +541,7 @@ static void amd_gpio_irq_handler(unsigned int __irq, struct irq_desc *desc) } if (handled == 0) - handle_bad_irq(irq, desc); + handle_bad_irq(desc); spin_lock_irqsave(&gpio_dev->lock, flags); reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c new file mode 100644 index 000000000000..33edd07d9149 --- /dev/null +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -0,0 +1,1094 @@ +/* + * Driver for the Atmel PIO4 controller + * + * Copyright (C) 2015 Atmel, + * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/slab.h> +#include "core.h" +#include "pinconf.h" +#include "pinctrl-utils.h" + +/* + * Warning: + * In order to not introduce confusion between Atmel PIO groups and pinctrl + * framework groups, Atmel PIO groups will be called banks, line is kept to + * designed the pin id into this bank. + */ + +#define ATMEL_PIO_MSKR 0x0000 +#define ATMEL_PIO_CFGR 0x0004 +#define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0) +#define ATMEL_PIO_DIR_MASK BIT(8) +#define ATMEL_PIO_PUEN_MASK BIT(9) +#define ATMEL_PIO_PDEN_MASK BIT(10) +#define ATMEL_PIO_IFEN_MASK BIT(12) +#define ATMEL_PIO_IFSCEN_MASK BIT(13) +#define ATMEL_PIO_OPD_MASK BIT(14) +#define ATMEL_PIO_SCHMITT_MASK BIT(15) +#define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24) +#define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24) +#define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24) +#define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24) +#define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24) +#define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24) +#define ATMEL_PIO_PDSR 0x0008 +#define ATMEL_PIO_LOCKSR 0x000C +#define ATMEL_PIO_SODR 0x0010 +#define ATMEL_PIO_CODR 0x0014 +#define ATMEL_PIO_ODSR 0x0018 +#define ATMEL_PIO_IER 0x0020 +#define ATMEL_PIO_IDR 0x0024 +#define ATMEL_PIO_IMR 0x0028 +#define ATMEL_PIO_ISR 0x002C +#define ATMEL_PIO_IOFR 0x003C + +#define ATMEL_PIO_NPINS_PER_BANK 32 +#define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK) +#define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK) +#define ATMEL_PIO_BANK_OFFSET 0x40 + +#define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff) +#define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf) +#define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf) + +struct atmel_pioctrl_data { + unsigned nbanks; +}; + +struct atmel_group { + const char *name; + u32 pin; +}; + +struct atmel_pin { + unsigned pin_id; + unsigned mux; + unsigned ioset; + unsigned bank; + unsigned line; + const char *device; +}; + +/** + * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio) + * @reg_base: base address of the controller. + * @clk: clock of the controller. + * @nbanks: number of PIO groups, it can vary depending on the SoC. + * @pinctrl_dev: pinctrl device registered. + * @groups: groups table to provide group name and pin in the group to pinctrl. + * @group_names: group names table to provide all the group/pin names to + * pinctrl or gpio. + * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line + * fields are set at probe time. Other ones are set when parsing dt + * pinctrl. + * @npins: number of pins. + * @gpio_chip: gpio chip registered. + * @irq_domain: irq domain for the gpio controller. + * @irqs: table containing the hw irq number of the bank. The index of the + * table is the bank id. + * @dev: device entry for the Atmel PIO controller. + * @node: node of the Atmel PIO controller. + */ +struct atmel_pioctrl { + void __iomem *reg_base; + struct clk *clk; + unsigned nbanks; + struct pinctrl_dev *pinctrl_dev; + struct atmel_group *groups; + const char * const *group_names; + struct atmel_pin **pins; + unsigned npins; + struct gpio_chip *gpio_chip; + struct irq_domain *irq_domain; + int *irqs; + unsigned *pm_wakeup_sources; + unsigned *pm_suspend_backup; + struct device *dev; + struct device_node *node; +}; + +static const char * const atmel_functions[] = { + "GPIO", "A", "B", "C", "D", "E", "F", "G" +}; + +/* --- GPIO --- */ +static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl, + unsigned int bank, unsigned int reg) +{ + return readl_relaxed(atmel_pioctrl->reg_base + + ATMEL_PIO_BANK_OFFSET * bank + reg); +} + +static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl, + unsigned int bank, unsigned int reg, + unsigned int val) +{ + writel_relaxed(val, atmel_pioctrl->reg_base + + ATMEL_PIO_BANK_OFFSET * bank + reg); +} + +static void atmel_gpio_irq_ack(struct irq_data *d) +{ + /* + * Nothing to do, interrupt is cleared when reading the status + * register. + */ +} + +static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type) +{ + struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); + struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; + unsigned reg; + + atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, + BIT(pin->line)); + reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); + reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK); + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + irq_set_handler_locked(d, handle_edge_irq); + reg |= ATMEL_PIO_CFGR_EVTSEL_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + irq_set_handler_locked(d, handle_edge_irq); + reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + irq_set_handler_locked(d, handle_edge_irq); + reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH; + break; + case IRQ_TYPE_LEVEL_LOW: + irq_set_handler_locked(d, handle_level_irq); + reg |= ATMEL_PIO_CFGR_EVTSEL_LOW; + break; + case IRQ_TYPE_LEVEL_HIGH: + irq_set_handler_locked(d, handle_level_irq); + reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH; + break; + case IRQ_TYPE_NONE: + default: + return -EINVAL; + } + + atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); + + return 0; +} + +static void atmel_gpio_irq_mask(struct irq_data *d) +{ + struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); + struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; + + atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR, + BIT(pin->line)); +} + +static void atmel_gpio_irq_unmask(struct irq_data *d) +{ + struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); + struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; + + atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER, + BIT(pin->line)); +} + +#ifdef CONFIG_PM_SLEEP + +static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on) +{ + struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); + int bank = ATMEL_PIO_BANK(d->hwirq); + int line = ATMEL_PIO_LINE(d->hwirq); + + /* The gpio controller has one interrupt line per bank. */ + irq_set_irq_wake(atmel_pioctrl->irqs[bank], on); + + if (on) + atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line); + else + atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line)); + + return 0; +} +#else +#define atmel_gpio_irq_set_wake NULL +#endif /* CONFIG_PM_SLEEP */ + +static struct irq_chip atmel_gpio_irq_chip = { + .name = "GPIO", + .irq_ack = atmel_gpio_irq_ack, + .irq_mask = atmel_gpio_irq_mask, + .irq_unmask = atmel_gpio_irq_unmask, + .irq_set_type = atmel_gpio_irq_set_type, + .irq_set_wake = atmel_gpio_irq_set_wake, +}; + +static void atmel_gpio_irq_handler(struct irq_desc *desc) +{ + unsigned int irq = irq_desc_get_irq(desc); + struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned long isr; + int n, bank = -1; + + /* Find from which bank is the irq received. */ + for (n = 0; n < atmel_pioctrl->nbanks; n++) { + if (atmel_pioctrl->irqs[n] == irq) { + bank = n; + break; + } + } + + if (bank < 0) { + dev_err(atmel_pioctrl->dev, + "no bank associated to irq %u\n", irq); + return; + } + + chained_irq_enter(chip, desc); + + for (;;) { + isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, + ATMEL_PIO_ISR); + isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank, + ATMEL_PIO_IMR); + if (!isr) + break; + + for_each_set_bit(n, &isr, BITS_PER_LONG) + generic_handle_irq(gpio_to_irq(bank * + ATMEL_PIO_NPINS_PER_BANK + n)); + } + + chained_irq_exit(chip, desc); +} + +static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev); + struct atmel_pin *pin = atmel_pioctrl->pins[offset]; + unsigned reg; + + atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, + BIT(pin->line)); + reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); + reg &= ~ATMEL_PIO_DIR_MASK; + atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); + + return 0; +} + +static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev); + struct atmel_pin *pin = atmel_pioctrl->pins[offset]; + unsigned reg; + + reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR); + + return !!(reg & BIT(pin->line)); +} + +static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, + int value) +{ + struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev); + struct atmel_pin *pin = atmel_pioctrl->pins[offset]; + unsigned reg; + + atmel_gpio_write(atmel_pioctrl, pin->bank, + value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, + BIT(pin->line)); + + atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, + BIT(pin->line)); + reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); + reg |= ATMEL_PIO_DIR_MASK; + atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); + + return 0; +} + +static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val) +{ + struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev); + struct atmel_pin *pin = atmel_pioctrl->pins[offset]; + + atmel_gpio_write(atmel_pioctrl, pin->bank, + val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, + BIT(pin->line)); +} + +static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev); + + return irq_find_mapping(atmel_pioctrl->irq_domain, offset); +} + +static struct gpio_chip atmel_gpio_chip = { + .direction_input = atmel_gpio_direction_input, + .get = atmel_gpio_get, + .direction_output = atmel_gpio_direction_output, + .set = atmel_gpio_set, + .to_irq = atmel_gpio_to_irq, + .base = 0, +}; + +/* --- PINCTRL --- */ +static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev, + unsigned pin_id) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned bank = atmel_pioctrl->pins[pin_id]->bank; + unsigned line = atmel_pioctrl->pins[pin_id]->line; + void __iomem *addr = atmel_pioctrl->reg_base + + bank * ATMEL_PIO_BANK_OFFSET; + + writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); + /* Have to set MSKR first, to access the right pin CFGR. */ + wmb(); + + return readl_relaxed(addr + ATMEL_PIO_CFGR); +} + +static void atmel_pin_config_write(struct pinctrl_dev *pctldev, + unsigned pin_id, u32 conf) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned bank = atmel_pioctrl->pins[pin_id]->bank; + unsigned line = atmel_pioctrl->pins[pin_id]->line; + void __iomem *addr = atmel_pioctrl->reg_base + + bank * ATMEL_PIO_BANK_OFFSET; + + writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR); + /* Have to set MSKR first, to access the right pin CFGR. */ + wmb(); + writel_relaxed(conf, addr + ATMEL_PIO_CFGR); +} + +static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + + return atmel_pioctrl->npins; +} + +static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + + return atmel_pioctrl->groups[selector].name; +} + +static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned selector, const unsigned **pins, + unsigned *num_pins) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + + *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin; + *num_pins = 1; + + return 0; +} + +struct atmel_group *atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, + unsigned pin) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + int i; + + for (i = 0; i < atmel_pioctrl->npins; i++) { + struct atmel_group *grp = atmel_pioctrl->groups + i; + + if (grp->pin == pin) + return grp; + } + + return NULL; +} + +static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev, + struct device_node *np, + u32 pinfunc, const char **grp_name, + const char **func_name) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned pin_id, func_id; + struct atmel_group *grp; + + pin_id = ATMEL_GET_PIN_NO(pinfunc); + func_id = ATMEL_GET_PIN_FUNC(pinfunc); + + if (func_id >= ARRAY_SIZE(atmel_functions)) + return -EINVAL; + + *func_name = atmel_functions[func_id]; + + grp = atmel_pctl_find_group_by_pin(pctldev, pin_id); + if (!grp) + return -EINVAL; + *grp_name = grp->name; + + atmel_pioctrl->pins[pin_id]->mux = func_id; + atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc); + /* Want the device name not the group one. */ + if (np->parent == atmel_pioctrl->node) + atmel_pioctrl->pins[pin_id]->device = np->name; + else + atmel_pioctrl->pins[pin_id]->device = np->parent->name; + + return 0; +} + +static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps) +{ + unsigned num_pins, num_configs, reserve; + unsigned long *configs; + struct property *pins; + bool has_config; + u32 pinfunc; + int ret, i; + + pins = of_find_property(np, "pinmux", NULL); + if (!pins) + return -EINVAL; + + ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, + &num_configs); + if (ret < 0) { + dev_err(pctldev->dev, "%s: could not parse node property\n", + of_node_full_name(np)); + return ret; + } + + if (num_configs) + has_config = true; + + num_pins = pins->length / sizeof(u32); + if (!num_pins) { + dev_err(pctldev->dev, "no pins found in node %s\n", + of_node_full_name(np)); + return -EINVAL; + } + + /* + * Reserve maps, at least there is a mux map and an optional conf + * map for each pin. + */ + reserve = 1; + if (has_config && num_pins >= 1) + reserve++; + reserve *= num_pins; + ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, + reserve); + if (ret < 0) + return ret; + + for (i = 0; i < num_pins; i++) { + const char *group, *func; + + ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc); + if (ret) + return ret; + + ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group, + &func); + if (ret) + return ret; + + pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps, + group, func); + + if (has_config) { + ret = pinctrl_utils_add_map_configs(pctldev, map, + reserved_maps, num_maps, group, + configs, num_configs, + PIN_MAP_TYPE_CONFIGS_GROUP); + if (ret < 0) + return ret; + } + } + + return 0; +} + +static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + unsigned *num_maps) +{ + struct device_node *np; + unsigned reserved_maps; + int ret; + + *map = NULL; + *num_maps = 0; + reserved_maps = 0; + + /* + * If all the pins of a device have the same configuration (or no one), + * it is useless to add a subnode, so directly parse node referenced by + * phandle. + */ + ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map, + &reserved_maps, num_maps); + if (ret) { + for_each_child_of_node(np_config, np) { + ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map, + &reserved_maps, num_maps); + if (ret < 0) + break; + } + } + + if (ret < 0) { + pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); + dev_err(pctldev->dev, "can't create maps for node %s\n", + np_config->full_name); + } + + return ret; +} + +static const struct pinctrl_ops atmel_pctlops = { + .get_groups_count = atmel_pctl_get_groups_count, + .get_group_name = atmel_pctl_get_group_name, + .get_group_pins = atmel_pctl_get_group_pins, + .dt_node_to_map = atmel_pctl_dt_node_to_map, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(atmel_functions); +} + +static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return atmel_functions[selector]; +} + +static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev, + unsigned selector, + const char * const **groups, + unsigned * const num_groups) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + + *groups = atmel_pioctrl->group_names; + *num_groups = atmel_pioctrl->npins; + + return 0; +} + +static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned pin; + u32 conf; + + dev_dbg(pctldev->dev, "enable function %s group %s\n", + atmel_functions[function], atmel_pioctrl->groups[group].name); + + pin = atmel_pioctrl->groups[group].pin; + conf = atmel_pin_config_read(pctldev, pin); + conf &= (~ATMEL_PIO_CFGR_FUNC_MASK); + conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK); + dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf); + atmel_pin_config_write(pctldev, pin, conf); + + return 0; +} + +static const struct pinmux_ops atmel_pmxops = { + .get_functions_count = atmel_pmx_get_functions_count, + .get_function_name = atmel_pmx_get_function_name, + .get_function_groups = atmel_pmx_get_function_groups, + .set_mux = atmel_pmx_set_mux, +}; + +static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev, + unsigned group, + unsigned long *config) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned param = pinconf_to_config_param(*config), arg = 0; + struct atmel_group *grp = atmel_pioctrl->groups + group; + unsigned pin_id = grp->pin; + u32 res; + + res = atmel_pin_config_read(pctldev, pin_id); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + if (!(res & ATMEL_PIO_PUEN_MASK)) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if ((res & ATMEL_PIO_PUEN_MASK) || + (!(res & ATMEL_PIO_PDEN_MASK))) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_BIAS_DISABLE: + if ((res & ATMEL_PIO_PUEN_MASK) || + ((res & ATMEL_PIO_PDEN_MASK))) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!(res & ATMEL_PIO_OPD_MASK)) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (!(res & ATMEL_PIO_SCHMITT_MASK)) + return -EINVAL; + arg = 1; + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, + unsigned group, + unsigned long *configs, + unsigned num_configs) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + struct atmel_group *grp = atmel_pioctrl->groups + group; + unsigned bank, pin, pin_id = grp->pin; + u32 mask, conf = 0; + int i; + + conf = atmel_pin_config_read(pctldev, pin_id); + + for (i = 0; i < num_configs; i++) { + unsigned param = pinconf_to_config_param(configs[i]); + unsigned arg = pinconf_to_config_argument(configs[i]); + + dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", + __func__, pin_id, configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + conf &= (~ATMEL_PIO_PUEN_MASK); + conf &= (~ATMEL_PIO_PDEN_MASK); + break; + case PIN_CONFIG_BIAS_PULL_UP: + conf |= ATMEL_PIO_PUEN_MASK; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + conf |= ATMEL_PIO_PDEN_MASK; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (arg == 0) + conf &= (~ATMEL_PIO_OPD_MASK); + else + conf |= ATMEL_PIO_OPD_MASK; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (arg == 0) + conf |= ATMEL_PIO_SCHMITT_MASK; + else + conf &= (~ATMEL_PIO_SCHMITT_MASK); + break; + case PIN_CONFIG_INPUT_DEBOUNCE: + if (arg == 0) { + conf &= (~ATMEL_PIO_IFEN_MASK); + conf &= (~ATMEL_PIO_IFSCEN_MASK); + } else { + /* + * We don't care about the debounce value for several reasons: + * - can't have different debounce periods inside a same group, + * - the register to configure this period is a secure register. + * The debouncing filter can filter a pulse with a duration of less + * than 1/2 slow clock period. + */ + conf |= ATMEL_PIO_IFEN_MASK; + conf |= ATMEL_PIO_IFSCEN_MASK; + } + break; + case PIN_CONFIG_OUTPUT: + conf |= ATMEL_PIO_DIR_MASK; + bank = ATMEL_PIO_BANK(pin_id); + pin = ATMEL_PIO_LINE(pin_id); + mask = 1 << pin; + + if (arg == 0) { + writel_relaxed(mask, atmel_pioctrl->reg_base + + bank * ATMEL_PIO_BANK_OFFSET + + ATMEL_PIO_CODR); + } else { + writel_relaxed(mask, atmel_pioctrl->reg_base + + bank * ATMEL_PIO_BANK_OFFSET + + ATMEL_PIO_SODR); + } + break; + default: + dev_warn(pctldev->dev, + "unsupported configuration parameter: %u\n", + param); + continue; + } + } + + dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf); + atmel_pin_config_write(pctldev, pin_id, conf); + + return 0; +} + +static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned pin_id) +{ + struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); + u32 conf; + + if (!atmel_pioctrl->pins[pin_id]->device) + return; + + if (atmel_pioctrl->pins[pin_id]) + seq_printf(s, " (%s, ioset %u) ", + atmel_pioctrl->pins[pin_id]->device, + atmel_pioctrl->pins[pin_id]->ioset); + + conf = atmel_pin_config_read(pctldev, pin_id); + if (conf & ATMEL_PIO_PUEN_MASK) + seq_printf(s, "%s ", "pull-up"); + if (conf & ATMEL_PIO_PDEN_MASK) + seq_printf(s, "%s ", "pull-down"); + if (conf & ATMEL_PIO_IFEN_MASK) + seq_printf(s, "%s ", "debounce"); + if (conf & ATMEL_PIO_OPD_MASK) + seq_printf(s, "%s ", "open-drain"); + if (conf & ATMEL_PIO_SCHMITT_MASK) + seq_printf(s, "%s ", "schmitt"); +} + +static const struct pinconf_ops atmel_confops = { + .pin_config_group_get = atmel_conf_pin_config_group_get, + .pin_config_group_set = atmel_conf_pin_config_group_set, + .pin_config_dbg_show = atmel_conf_pin_config_dbg_show, +}; + +static struct pinctrl_desc atmel_pinctrl_desc = { + .name = "atmel_pinctrl", + .confops = &atmel_confops, + .pctlops = &atmel_pctlops, + .pmxops = &atmel_pmxops, +}; + +static int atmel_pctrl_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev); + int i; + + /* + * For each bank, save IMR to restore it later and disable all GPIO + * interrupts excepting the ones marked as wakeup sources. + */ + for (i = 0; i < atmel_pioctrl->nbanks; i++) { + atmel_pioctrl->pm_suspend_backup[i] = + atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR); + atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR, + ~atmel_pioctrl->pm_wakeup_sources[i]); + } + + return 0; +} + +static int atmel_pctrl_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < atmel_pioctrl->nbanks; i++) + atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER, + atmel_pioctrl->pm_suspend_backup[i]); + + return 0; +} + +static const struct dev_pm_ops atmel_pctrl_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume) +}; + +/* + * The number of banks can be different from a SoC to another one. + * We can have up to 16 banks. + */ +static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = { + .nbanks = 4, +}; + +static const struct of_device_id atmel_pctrl_of_match[] = { + { + .compatible = "atmel,sama5d2-pinctrl", + .data = &atmel_sama5d2_pioctrl_data, + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, atmel_pctrl_of_match); + +static int atmel_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct pinctrl_pin_desc *pin_desc; + const char **group_names; + const struct of_device_id *match; + int i, ret; + struct resource *res; + struct atmel_pioctrl *atmel_pioctrl; + struct atmel_pioctrl_data *atmel_pioctrl_data; + + atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL); + if (!atmel_pioctrl) + return -ENOMEM; + atmel_pioctrl->dev = dev; + atmel_pioctrl->node = dev->of_node; + platform_set_drvdata(pdev, atmel_pioctrl); + + match = of_match_node(atmel_pctrl_of_match, dev->of_node); + if (!match) { + dev_err(dev, "unknown compatible string\n"); + return -ENODEV; + } + atmel_pioctrl_data = (struct atmel_pioctrl_data *)match->data; + atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks; + atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "unable to get atmel pinctrl resource\n"); + return -EINVAL; + } + atmel_pioctrl->reg_base = devm_ioremap_resource(dev, res); + if (IS_ERR(atmel_pioctrl->reg_base)) + return -EINVAL; + + atmel_pioctrl->clk = devm_clk_get(dev, NULL); + if (IS_ERR(atmel_pioctrl->clk)) { + dev_err(dev, "failed to get clock\n"); + return PTR_ERR(atmel_pioctrl->clk); + } + + atmel_pioctrl->pins = devm_kzalloc(dev, sizeof(*atmel_pioctrl->pins) + * atmel_pioctrl->npins, GFP_KERNEL); + if (!atmel_pioctrl->pins) + return -ENOMEM; + + pin_desc = devm_kzalloc(dev, sizeof(*pin_desc) + * atmel_pioctrl->npins, GFP_KERNEL); + if (!pin_desc) + return -ENOMEM; + atmel_pinctrl_desc.pins = pin_desc; + atmel_pinctrl_desc.npins = atmel_pioctrl->npins; + + /* One pin is one group since a pin can achieve all functions. */ + group_names = devm_kzalloc(dev, sizeof(*group_names) + * atmel_pioctrl->npins, GFP_KERNEL); + if (!group_names) + return -ENOMEM; + atmel_pioctrl->group_names = group_names; + + atmel_pioctrl->groups = devm_kzalloc(&pdev->dev, + sizeof(*atmel_pioctrl->groups) * atmel_pioctrl->npins, + GFP_KERNEL); + if (!atmel_pioctrl->groups) + return -ENOMEM; + for (i = 0 ; i < atmel_pioctrl->npins; i++) { + struct atmel_group *group = atmel_pioctrl->groups + i; + unsigned bank = ATMEL_PIO_BANK(i); + unsigned line = ATMEL_PIO_LINE(i); + + atmel_pioctrl->pins[i] = devm_kzalloc(dev, + sizeof(**atmel_pioctrl->pins), GFP_KERNEL); + if (!atmel_pioctrl->pins[i]) + return -ENOMEM; + + atmel_pioctrl->pins[i]->pin_id = i; + atmel_pioctrl->pins[i]->bank = bank; + atmel_pioctrl->pins[i]->line = line; + + pin_desc[i].number = i; + /* Pin naming convention: P(bank_name)(bank_pin_number). */ + pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d", + bank + 'A', line); + + group->name = group_names[i] = pin_desc[i].name; + group->pin = pin_desc[i].number; + + dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line); + } + + atmel_pioctrl->gpio_chip = &atmel_gpio_chip; + atmel_pioctrl->gpio_chip->of_node = dev->of_node; + atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins; + atmel_pioctrl->gpio_chip->label = dev_name(dev); + atmel_pioctrl->gpio_chip->dev = dev; + atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names; + + atmel_pioctrl->pm_wakeup_sources = devm_kzalloc(dev, + sizeof(*atmel_pioctrl->pm_wakeup_sources) + * atmel_pioctrl->nbanks, GFP_KERNEL); + if (!atmel_pioctrl->pm_wakeup_sources) + return -ENOMEM; + + atmel_pioctrl->pm_suspend_backup = devm_kzalloc(dev, + sizeof(*atmel_pioctrl->pm_suspend_backup) + * atmel_pioctrl->nbanks, GFP_KERNEL); + if (!atmel_pioctrl->pm_suspend_backup) + return -ENOMEM; + + atmel_pioctrl->irqs = devm_kzalloc(dev, sizeof(*atmel_pioctrl->irqs) + * atmel_pioctrl->nbanks, GFP_KERNEL); + if (!atmel_pioctrl->irqs) + return -ENOMEM; + + /* There is one controller but each bank has its own irq line. */ + for (i = 0; i < atmel_pioctrl->nbanks; i++) { + res = platform_get_resource(pdev, IORESOURCE_IRQ, i); + if (!res) { + dev_err(dev, "missing irq resource for group %c\n", + 'A' + i); + return -EINVAL; + } + atmel_pioctrl->irqs[i] = res->start; + irq_set_chained_handler(res->start, atmel_gpio_irq_handler); + irq_set_handler_data(res->start, atmel_pioctrl); + dev_dbg(dev, "bank %i: hwirq=%u\n", i, res->start); + } + + atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node, + atmel_pioctrl->gpio_chip->ngpio, + &irq_domain_simple_ops, NULL); + if (!atmel_pioctrl->irq_domain) { + dev_err(dev, "can't add the irq domain\n"); + return -ENODEV; + } + atmel_pioctrl->irq_domain->name = "atmel gpio"; + + for (i = 0; i < atmel_pioctrl->npins; i++) { + int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i); + + irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip, + handle_simple_irq); + irq_set_chip_data(irq, atmel_pioctrl); + dev_dbg(dev, + "atmel gpio irq domain: hwirq: %d, linux irq: %d\n", + i, irq); + } + + ret = clk_prepare_enable(atmel_pioctrl->clk); + if (ret) { + dev_err(dev, "failed to prepare and enable clock\n"); + goto clk_prepare_enable_error; + } + + atmel_pioctrl->pinctrl_dev = pinctrl_register(&atmel_pinctrl_desc, + &pdev->dev, + atmel_pioctrl); + if (!atmel_pioctrl->pinctrl_dev) { + dev_err(dev, "pinctrl registration failed\n"); + goto pinctrl_register_error; + } + + ret = gpiochip_add(atmel_pioctrl->gpio_chip); + if (ret) { + dev_err(dev, "failed to add gpiochip\n"); + goto gpiochip_add_error; + } + + ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev), + 0, 0, atmel_pioctrl->gpio_chip->ngpio); + if (ret) { + dev_err(dev, "failed to add gpio pin range\n"); + goto gpiochip_add_pin_range_error; + } + + dev_info(&pdev->dev, "atmel pinctrl initialized\n"); + + return 0; + +clk_prepare_enable_error: + irq_domain_remove(atmel_pioctrl->irq_domain); +pinctrl_register_error: + clk_disable_unprepare(atmel_pioctrl->clk); +gpiochip_add_error: + pinctrl_unregister(atmel_pioctrl->pinctrl_dev); +gpiochip_add_pin_range_error: + gpiochip_remove(atmel_pioctrl->gpio_chip); + + return ret; +} + +int atmel_pinctrl_remove(struct platform_device *pdev) +{ + struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev); + + irq_domain_remove(atmel_pioctrl->irq_domain); + clk_disable_unprepare(atmel_pioctrl->clk); + pinctrl_unregister(atmel_pioctrl->pinctrl_dev); + gpiochip_remove(atmel_pioctrl->gpio_chip); + + return 0; +} + +static struct platform_driver atmel_pinctrl_driver = { + .driver = { + .name = "pinctrl-at91-pio4", + .of_match_table = atmel_pctrl_of_match, + .pm = &atmel_pctrl_pm_ops, + }, + .probe = atmel_pinctrl_probe, + .remove = atmel_pinctrl_remove, +}; +module_platform_driver(atmel_pinctrl_driver); + +MODULE_AUTHOR(Ludovic Desroches <ludovic.desroches@atmel.com>); +MODULE_DESCRIPTION("Atmel PIO4 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index bae0012ee356..b0fde0f385e6 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1585,7 +1585,7 @@ static struct irq_chip gpio_irqchip = { .irq_set_wake = gpio_irq_set_wake, }; -static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) +static void gpio_irq_handler(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc); diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c index 3731cc67a88b..9c9b88934bcc 100644 --- a/drivers/pinctrl/pinctrl-coh901.c +++ b/drivers/pinctrl/pinctrl-coh901.c @@ -519,7 +519,7 @@ static struct irq_chip u300_gpio_irqchip = { .irq_set_type = u300_gpio_irq_type, }; -static void u300_gpio_irq_handler(unsigned __irq, struct irq_desc *desc) +static void u300_gpio_irq_handler(struct irq_desc *desc) { unsigned int irq = irq_desc_get_irq(desc); struct irq_chip *parent_chip = irq_desc_get_chip(desc); diff --git a/drivers/pinctrl/pinctrl-digicolor.c b/drivers/pinctrl/pinctrl-digicolor.c index 461fffc4c62a..11f8b835d3b6 100644 --- a/drivers/pinctrl/pinctrl-digicolor.c +++ b/drivers/pinctrl/pinctrl-digicolor.c @@ -337,9 +337,9 @@ static int dc_pinctrl_probe(struct platform_device *pdev) pmap->dev = &pdev->dev; pmap->pctl = pinctrl_register(pctl_desc, &pdev->dev, pmap); - if (!pmap->pctl) { + if (IS_ERR(pmap->pctl)) { dev_err(&pdev->dev, "pinctrl driver registration failed\n"); - return -EINVAL; + return PTR_ERR(pmap->pctl); } ret = dc_gpiochip_add(pmap, pdev->dev.of_node); diff --git a/drivers/pinctrl/pinctrl-pistachio.c b/drivers/pinctrl/pinctrl-pistachio.c index 3dc2ae15f3a1..952b1c623887 100644 --- a/drivers/pinctrl/pinctrl-pistachio.c +++ b/drivers/pinctrl/pinctrl-pistachio.c @@ -1303,20 +1303,18 @@ static int pistachio_gpio_irq_set_type(struct irq_data *data, unsigned int type) } if (type & IRQ_TYPE_LEVEL_MASK) - __irq_set_handler_locked(data->irq, handle_level_irq); + irq_set_handler_locked(data, handle_level_irq); else - __irq_set_handler_locked(data->irq, handle_edge_irq); + irq_set_handler_locked(data, handle_edge_irq); return 0; } -static void pistachio_gpio_irq_handler(unsigned int __irq, - struct irq_desc *desc) +static void pistachio_gpio_irq_handler(struct irq_desc *desc) { - unsigned int irq = irq_desc_get_irq(desc); struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct pistachio_gpio_bank *bank = gc_to_bank(gc); - struct irq_chip *chip = irq_get_chip(irq); + struct irq_chip *chip = irq_desc_get_chip(desc); unsigned long pending; unsigned int pin; diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index c5246c05f70c..3d020fdc7bb6 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1475,7 +1475,7 @@ static const struct gpio_chip rockchip_gpiolib_chip = { * Interrupt handling */ -static void rockchip_irq_demux(unsigned int __irq, struct irq_desc *desc) +static void rockchip_irq_demux(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); @@ -2089,6 +2089,21 @@ static struct rockchip_pin_ctrl rk2928_pin_ctrl = { .pull_calc_reg = rk2928_calc_pull_reg_and_bit, }; +static struct rockchip_pin_bank rk3036_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), +}; + +static struct rockchip_pin_ctrl rk3036_pin_ctrl = { + .pin_banks = rk3036_pin_banks, + .nr_banks = ARRAY_SIZE(rk3036_pin_banks), + .label = "RK3036-GPIO", + .type = RK2928, + .grf_mux_offset = 0xa8, + .pull_calc_reg = rk2928_calc_pull_reg_and_bit, +}; + static struct rockchip_pin_bank rk3066a_pin_banks[] = { PIN_BANK(0, 32, "gpio0"), PIN_BANK(1, 32, "gpio1"), @@ -2207,6 +2222,8 @@ static struct rockchip_pin_ctrl rk3368_pin_ctrl = { static const struct of_device_id rockchip_pinctrl_dt_match[] = { { .compatible = "rockchip,rk2928-pinctrl", .data = (void *)&rk2928_pin_ctrl }, + { .compatible = "rockchip,rk3036-pinctrl", + .data = (void *)&rk3036_pin_ctrl }, { .compatible = "rockchip,rk3066a-pinctrl", .data = (void *)&rk3066a_pin_ctrl }, { .compatible = "rockchip,rk3066b-pinctrl", diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index bf548c2a7a9d..ef04b962c3d5 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1679,7 +1679,7 @@ static irqreturn_t pcs_irq_handler(int irq, void *d) * Use this if you have a separate interrupt for each * pinctrl-single instance. */ -static void pcs_irq_chain_handler(unsigned int irq, struct irq_desc *desc) +static void pcs_irq_chain_handler(struct irq_desc *desc) { struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc); struct irq_chip *chip; diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index f8338d2e6b6b..389526e704fb 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1460,7 +1460,7 @@ static void __gpio_irq_handler(struct st_gpio_bank *bank) } } -static void st_gpio_irq_handler(unsigned irq, struct irq_desc *desc) +static void st_gpio_irq_handler(struct irq_desc *desc) { /* interrupt dedicated per bank */ struct irq_chip *chip = irq_desc_get_chip(desc); @@ -1472,7 +1472,7 @@ static void st_gpio_irq_handler(unsigned irq, struct irq_desc *desc) chained_irq_exit(chip, desc); } -static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc) +static void st_gpio_irqmux_handler(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); struct st_pinctrl *info = irq_desc_get_handler_data(desc); diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c index c349911708ef..b89ad3c0c731 100644 --- a/drivers/pinctrl/pinctrl-tz1090-pdc.c +++ b/drivers/pinctrl/pinctrl-tz1090-pdc.c @@ -668,7 +668,7 @@ static int tz1090_pdc_pinconf_reg(struct pinctrl_dev *pctldev, break; default: return -ENOTSUPP; - }; + } /* Only input bias parameters supported */ *reg = REG_GPIO_CONTROL2; @@ -801,7 +801,7 @@ static int tz1090_pdc_pinconf_group_reg(struct pinctrl_dev *pctldev, break; default: return -ENOTSUPP; - }; + } /* Calculate field information */ *mask = (BIT(*width) - 1) << *shift; diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c index 6d07a2f64d97..5425299d759d 100644 --- a/drivers/pinctrl/pinctrl-tz1090.c +++ b/drivers/pinctrl/pinctrl-tz1090.c @@ -1661,7 +1661,7 @@ static int tz1090_pinconf_reg(struct pinctrl_dev *pctldev, break; default: return -ENOTSUPP; - }; + } /* Only input bias parameters supported */ pu = &tz1090_pinconf_pullup[pin]; @@ -1790,7 +1790,7 @@ static int tz1090_pinconf_group_reg(struct pinctrl_dev *pctldev, break; default: return -ENOTSUPP; - }; + } /* Calculate field information */ *shift = g->slw_bit * *width; diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 67e08cb315c4..29984b36926a 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -313,8 +313,7 @@ static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev, /* See if this pctldev has this function */ while (selector < nfuncs) { - const char *fname = ops->get_function_name(pctldev, - selector); + const char *fname = ops->get_function_name(pctldev, selector); if (!strcmp(function, fname)) return selector; diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 492cdd51dc5c..a0c7407c1cac 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -765,9 +765,8 @@ static struct irq_chip msm_gpio_irq_chip = { .irq_set_wake = msm_gpio_irq_set_wake, }; -static void msm_gpio_irq_handler(unsigned int __irq, struct irq_desc *desc) +static void msm_gpio_irq_handler(struct irq_desc *desc) { - unsigned int irq = irq_desc_get_irq(desc); struct gpio_chip *gc = irq_desc_get_handler_data(desc); const struct msm_pingroup *g; struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); @@ -795,7 +794,7 @@ static void msm_gpio_irq_handler(unsigned int __irq, struct irq_desc *desc) /* No interrupts were flagged */ if (handled == 0) - handle_bad_irq(irq, desc); + handle_bad_irq(desc); chained_irq_exit(chip, desc); } diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index c978b311031b..d809c9eaa323 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -584,7 +584,7 @@ static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) } #else -#define msm_gpio_dbg_show NULL +#define pm8xxx_gpio_dbg_show NULL #endif static struct gpio_chip pm8xxx_gpio_template = { @@ -723,9 +723,9 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev) #endif pctrl->pctrl = pinctrl_register(&pctrl->desc, &pdev->dev, pctrl); - if (!pctrl->pctrl) { + if (IS_ERR(pctrl->pctrl)) { dev_err(&pdev->dev, "couldn't register pm8xxx gpio driver\n"); - return -ENODEV; + return PTR_ERR(pctrl->pctrl); } pctrl->chip = pm8xxx_gpio_template; diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index 2d1b69f171be..8982027de8e8 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -639,7 +639,7 @@ static void pm8xxx_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip) } #else -#define msm_mpp_dbg_show NULL +#define pm8xxx_mpp_dbg_show NULL #endif static struct gpio_chip pm8xxx_mpp_template = { @@ -814,9 +814,9 @@ static int pm8xxx_mpp_probe(struct platform_device *pdev) #endif pctrl->pctrl = pinctrl_register(&pctrl->desc, &pdev->dev, pctrl); - if (!pctrl->pctrl) { + if (IS_ERR(pctrl->pctrl)) { dev_err(&pdev->dev, "couldn't register pm8xxx mpp driver\n"); - return -ENODEV; + return PTR_ERR(pctrl->pctrl); } pctrl->chip = pm8xxx_mpp_template; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 5f45caaef46d..71ccf6a90b22 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -419,7 +419,7 @@ static const struct of_device_id exynos_wkup_irq_ids[] = { }; /* interrupt handler for wakeup interrupts 0..15 */ -static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc) +static void exynos_irq_eint0_15(struct irq_desc *desc) { struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc); struct samsung_pin_bank *bank = eintd->bank; @@ -451,7 +451,7 @@ static inline void exynos_irq_demux_eint(unsigned long pend, } /* interrupt handler for wakeup interrupt 16 */ -static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) +static void exynos_irq_demux_eint16_31(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc); diff --git a/drivers/pinctrl/samsung/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c index 9ce0b8619d4c..82dc109f7ed4 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos5440.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos5440.c @@ -284,7 +284,7 @@ static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev, if (!idx) kfree(map[idx].data.configs.group_or_pin); } - }; + } kfree(map); } diff --git a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c index 019844d479bb..3d92f827da7a 100644 --- a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c +++ b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c @@ -240,7 +240,7 @@ static struct irq_chip s3c2410_eint0_3_chip = { .irq_set_type = s3c24xx_eint_type, }; -static void s3c2410_demux_eint0_3(unsigned int irq, struct irq_desc *desc) +static void s3c2410_demux_eint0_3(struct irq_desc *desc) { struct irq_data *data = irq_desc_get_irq_data(desc); struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc); @@ -295,7 +295,7 @@ static struct irq_chip s3c2412_eint0_3_chip = { .irq_set_type = s3c24xx_eint_type, }; -static void s3c2412_demux_eint0_3(unsigned int irq, struct irq_desc *desc) +static void s3c2412_demux_eint0_3(struct irq_desc *desc) { struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc); struct irq_data *data = irq_desc_get_irq_data(desc); @@ -361,7 +361,7 @@ static inline void s3c24xx_demux_eint(struct irq_desc *desc, u32 offset, u32 range) { struct s3c24xx_eint_data *data = irq_desc_get_handler_data(desc); - struct irq_chip *chip = irq_desc_get_irq_chip(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); struct samsung_pinctrl_drv_data *d = data->drvdata; unsigned int pend, mask; @@ -388,12 +388,12 @@ static inline void s3c24xx_demux_eint(struct irq_desc *desc, chained_irq_exit(chip, desc); } -static void s3c24xx_demux_eint4_7(unsigned int irq, struct irq_desc *desc) +static void s3c24xx_demux_eint4_7(struct irq_desc *desc) { s3c24xx_demux_eint(desc, 0, 0xf0); } -static void s3c24xx_demux_eint8_23(unsigned int irq, struct irq_desc *desc) +static void s3c24xx_demux_eint8_23(struct irq_desc *desc) { s3c24xx_demux_eint(desc, 8, 0xffff00); } diff --git a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c index f5ea40a69711..43407ab248f5 100644 --- a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c +++ b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c @@ -407,7 +407,7 @@ static const struct irq_domain_ops s3c64xx_gpio_irqd_ops = { .xlate = irq_domain_xlate_twocell, }; -static void s3c64xx_eint_gpio_irq(unsigned int irq, struct irq_desc *desc) +static void s3c64xx_eint_gpio_irq(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); struct s3c64xx_eint_gpio_data *data = irq_desc_get_handler_data(desc); @@ -631,22 +631,22 @@ static inline void s3c64xx_irq_demux_eint(struct irq_desc *desc, u32 range) chained_irq_exit(chip, desc); } -static void s3c64xx_demux_eint0_3(unsigned int irq, struct irq_desc *desc) +static void s3c64xx_demux_eint0_3(struct irq_desc *desc) { s3c64xx_irq_demux_eint(desc, 0xf); } -static void s3c64xx_demux_eint4_11(unsigned int irq, struct irq_desc *desc) +static void s3c64xx_demux_eint4_11(struct irq_desc *desc) { s3c64xx_irq_demux_eint(desc, 0xff0); } -static void s3c64xx_demux_eint12_19(unsigned int irq, struct irq_desc *desc) +static void s3c64xx_demux_eint12_19(struct irq_desc *desc) { s3c64xx_irq_demux_eint(desc, 0xff000); } -static void s3c64xx_demux_eint20_27(unsigned int irq, struct irq_desc *desc) +static void s3c64xx_demux_eint20_27(struct irq_desc *desc) { s3c64xx_irq_demux_eint(desc, 0xff00000); } diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c index 9df0c5f25824..829018c812bd 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -544,6 +544,11 @@ static const struct pinctrl_pin_desc atlas7_ioc_pads[] = { PINCTRL_PIN(156, "lvds_tx0d1n"), PINCTRL_PIN(157, "lvds_tx0d0p"), PINCTRL_PIN(158, "lvds_tx0d0n"), + PINCTRL_PIN(159, "jtag_tdo"), + PINCTRL_PIN(160, "jtag_tms"), + PINCTRL_PIN(161, "jtag_tck"), + PINCTRL_PIN(162, "jtag_tdi"), + PINCTRL_PIN(163, "jtag_trstn"), }; struct atlas7_pad_config atlas7_ioc_pad_confs[] = { @@ -708,6 +713,11 @@ struct atlas7_pad_config atlas7_ioc_pad_confs[] = { PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7), PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8), PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9), + PADCONF(159, 5, 0x140, 0x280, 0x380, -1, 0, 0, 0, 0), + PADCONF(160, 6, 0x140, 0x280, 0x380, -1, 4, 2, 2, 0), + PADCONF(161, 5, 0x140, 0x280, 0x380, -1, 8, 4, 4, 0), + PADCONF(162, 6, 0x140, 0x280, 0x380, -1, 12, 6, 6, 0), + PADCONF(163, 6, 0x140, 0x280, 0x380, -1, 16, 8, 8, 0), }; /* pin list of each pin group */ @@ -724,12 +734,15 @@ static const unsigned int sp_rgmii_gpio_pins[] = { 97, 98, 99, 100, 101, 102, 141, 142, 143, 144, 145, 146, 147, 148, }; static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154, 151, 152, 149, 150, }; -static const unsigned int uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40, 39, - 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135, 136, - 137, 138, 139, 140, }; +static const unsigned int jtag_uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40, + 39, 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135, + 136, 137, 138, 139, 140, 159, 160, 161, 162, 163, }; static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13, - 14, 15, 16, 17, }; + 14, 15, 16, 17, 9, }; static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, }; +static const unsigned int audio_digmic_pins0[] = { 51, }; +static const unsigned int audio_digmic_pins1[] = { 122, }; +static const unsigned int audio_digmic_pins2[] = { 161, }; static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41, 40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118, 115, 49, 50, 142, 143, 80, }; @@ -737,16 +750,49 @@ static const unsigned int audio_i2s_pins[] = { 118, 115, 116, 117, 112, 113, 114, }; static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, }; static const unsigned int audio_i2s_extclk_pins[] = { 112, }; -static const unsigned int audio_uart0_pins[] = { 143, 142, 141, 144, }; -static const unsigned int audio_uart1_pins[] = { 147, 146, 145, 148, }; -static const unsigned int audio_uart2_pins0[] = { 20, 21, 19, 18, }; -static const unsigned int audio_uart2_pins1[] = { 109, 110, 101, 111, }; -static const unsigned int c_can_trnsvr_pins[] = { 1, }; -static const unsigned int c0_can_pins0[] = { 11, 10, }; -static const unsigned int c0_can_pins1[] = { 2, 3, }; -static const unsigned int c1_can_pins0[] = { 138, 137, }; -static const unsigned int c1_can_pins1[] = { 147, 146, }; -static const unsigned int c1_can_pins2[] = { 2, 3, }; +static const unsigned int audio_spdif_out_pins0[] = { 112, }; +static const unsigned int audio_spdif_out_pins1[] = { 116, }; +static const unsigned int audio_spdif_out_pins2[] = { 142, }; +static const unsigned int audio_uart0_basic_pins[] = { 143, 142, 141, 144, }; +static const unsigned int audio_uart0_urfs_pins0[] = { 117, }; +static const unsigned int audio_uart0_urfs_pins1[] = { 139, }; +static const unsigned int audio_uart0_urfs_pins2[] = { 163, }; +static const unsigned int audio_uart0_urfs_pins3[] = { 162, }; +static const unsigned int audio_uart1_basic_pins[] = { 147, 146, 145, 148, }; +static const unsigned int audio_uart1_urfs_pins0[] = { 117, }; +static const unsigned int audio_uart1_urfs_pins1[] = { 140, }; +static const unsigned int audio_uart1_urfs_pins2[] = { 163, }; +static const unsigned int audio_uart2_urfs_pins0[] = { 139, }; +static const unsigned int audio_uart2_urfs_pins1[] = { 163, }; +static const unsigned int audio_uart2_urfs_pins2[] = { 96, }; +static const unsigned int audio_uart2_urxd_pins0[] = { 20, }; +static const unsigned int audio_uart2_urxd_pins1[] = { 109, }; +static const unsigned int audio_uart2_urxd_pins2[] = { 93, }; +static const unsigned int audio_uart2_usclk_pins0[] = { 19, }; +static const unsigned int audio_uart2_usclk_pins1[] = { 101, }; +static const unsigned int audio_uart2_usclk_pins2[] = { 91, }; +static const unsigned int audio_uart2_utfs_pins0[] = { 18, }; +static const unsigned int audio_uart2_utfs_pins1[] = { 111, }; +static const unsigned int audio_uart2_utfs_pins2[] = { 94, }; +static const unsigned int audio_uart2_utxd_pins0[] = { 21, }; +static const unsigned int audio_uart2_utxd_pins1[] = { 110, }; +static const unsigned int audio_uart2_utxd_pins2[] = { 92, }; +static const unsigned int c_can_trnsvr_en_pins0[] = { 2, }; +static const unsigned int c_can_trnsvr_en_pins1[] = { 0, }; +static const unsigned int c_can_trnsvr_intr_pins[] = { 1, }; +static const unsigned int c_can_trnsvr_stb_n_pins[] = { 3, }; +static const unsigned int c0_can_rxd_trnsv0_pins[] = { 11, }; +static const unsigned int c0_can_rxd_trnsv1_pins[] = { 2, }; +static const unsigned int c0_can_txd_trnsv0_pins[] = { 10, }; +static const unsigned int c0_can_txd_trnsv1_pins[] = { 3, }; +static const unsigned int c1_can_rxd_pins0[] = { 138, }; +static const unsigned int c1_can_rxd_pins1[] = { 147, }; +static const unsigned int c1_can_rxd_pins2[] = { 2, }; +static const unsigned int c1_can_rxd_pins3[] = { 162, }; +static const unsigned int c1_can_txd_pins0[] = { 137, }; +static const unsigned int c1_can_txd_pins1[] = { 146, }; +static const unsigned int c1_can_txd_pins2[] = { 3, }; +static const unsigned int c1_can_txd_pins3[] = { 161, }; static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, }; static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, }; @@ -804,7 +850,29 @@ static const unsigned int gn_trg_shutdown_pins2[] = { 117, }; static const unsigned int gn_trg_shutdown_pins3[] = { 123, }; static const unsigned int i2c0_pins[] = { 128, 127, }; static const unsigned int i2c1_pins[] = { 126, 125, }; -static const unsigned int jtag_pins0[] = { 125, 4, 2, 0, 1, 3, }; +static const unsigned int i2s0_pins[] = { 91, 93, 94, 92, }; +static const unsigned int i2s1_basic_pins[] = { 95, 96, }; +static const unsigned int i2s1_rxd0_pins0[] = { 61, }; +static const unsigned int i2s1_rxd0_pins1[] = { 131, }; +static const unsigned int i2s1_rxd0_pins2[] = { 129, }; +static const unsigned int i2s1_rxd0_pins3[] = { 117, }; +static const unsigned int i2s1_rxd0_pins4[] = { 83, }; +static const unsigned int i2s1_rxd1_pins0[] = { 72, }; +static const unsigned int i2s1_rxd1_pins1[] = { 132, }; +static const unsigned int i2s1_rxd1_pins2[] = { 130, }; +static const unsigned int i2s1_rxd1_pins3[] = { 118, }; +static const unsigned int i2s1_rxd1_pins4[] = { 84, }; +static const unsigned int jtag_jt_dbg_nsrst_pins[] = { 125, }; +static const unsigned int jtag_ntrst_pins0[] = { 4, }; +static const unsigned int jtag_ntrst_pins1[] = { 163, }; +static const unsigned int jtag_swdiotms_pins0[] = { 2, }; +static const unsigned int jtag_swdiotms_pins1[] = { 160, }; +static const unsigned int jtag_tck_pins0[] = { 0, }; +static const unsigned int jtag_tck_pins1[] = { 161, }; +static const unsigned int jtag_tdi_pins0[] = { 1, }; +static const unsigned int jtag_tdi_pins1[] = { 162, }; +static const unsigned int jtag_tdo_pins0[] = { 3, }; +static const unsigned int jtag_tdo_pins1[] = { 159, }; static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, }; static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80, @@ -821,7 +889,7 @@ static const unsigned int nd_df_pins[] = { 44, 43, 42, 41, 40, 39, 38, 37, 47, 46, 52, 51, 45, 49, 50, 48, 124, }; static const unsigned int nd_df_nowp_pins[] = { 44, 43, 42, 41, 40, 39, 38, 37, 47, 46, 52, 51, 45, 49, 50, 48, }; -static const unsigned int ps_pins[] = { 120, 119, }; +static const unsigned int ps_pins[] = { 120, 119, 121, }; static const unsigned int pwc_core_on_pins[] = { 8, }; static const unsigned int pwc_ext_on_pins[] = { 6, }; static const unsigned int pwc_gpio3_clk_pins[] = { 3, }; @@ -836,18 +904,26 @@ static const unsigned int pwc_wakeup_src3_pins[] = { 3, }; static const unsigned int pw_cko0_pins0[] = { 123, }; static const unsigned int pw_cko0_pins1[] = { 101, }; static const unsigned int pw_cko0_pins2[] = { 82, }; +static const unsigned int pw_cko0_pins3[] = { 162, }; static const unsigned int pw_cko1_pins0[] = { 124, }; static const unsigned int pw_cko1_pins1[] = { 110, }; +static const unsigned int pw_cko1_pins2[] = { 163, }; static const unsigned int pw_i2s01_clk_pins0[] = { 125, }; static const unsigned int pw_i2s01_clk_pins1[] = { 117, }; -static const unsigned int pw_pwm0_pins[] = { 119, }; -static const unsigned int pw_pwm1_pins[] = { 120, }; +static const unsigned int pw_i2s01_clk_pins2[] = { 132, }; +static const unsigned int pw_pwm0_pins0[] = { 119, }; +static const unsigned int pw_pwm0_pins1[] = { 159, }; +static const unsigned int pw_pwm1_pins0[] = { 120, }; +static const unsigned int pw_pwm1_pins1[] = { 160, }; +static const unsigned int pw_pwm1_pins2[] = { 131, }; static const unsigned int pw_pwm2_pins0[] = { 121, }; static const unsigned int pw_pwm2_pins1[] = { 98, }; +static const unsigned int pw_pwm2_pins2[] = { 161, }; static const unsigned int pw_pwm3_pins0[] = { 122, }; static const unsigned int pw_pwm3_pins1[] = { 73, }; static const unsigned int pw_pwm_cpu_vol_pins0[] = { 121, }; static const unsigned int pw_pwm_cpu_vol_pins1[] = { 98, }; +static const unsigned int pw_pwm_cpu_vol_pins2[] = { 161, }; static const unsigned int pw_backlight_pins0[] = { 122, }; static const unsigned int pw_backlight_pins1[] = { 73, }; static const unsigned int rg_eth_mac_pins[] = { 108, 103, 104, 105, 106, 107, @@ -863,8 +939,11 @@ static const unsigned int sd1_pins[] = { 48, 49, 44, 43, 42, 41, 40, 39, 38, 37, }; static const unsigned int sd1_4bit_pins0[] = { 48, 49, 44, 43, 42, 41, }; static const unsigned int sd1_4bit_pins1[] = { 48, 49, 40, 39, 38, 37, }; -static const unsigned int sd2_pins0[] = { 124, 31, 32, 33, 34, 35, 36, 123, }; -static const unsigned int sd2_no_cdb_pins0[] = { 31, 32, 33, 34, 35, 36, 123, }; +static const unsigned int sd2_basic_pins[] = { 31, 32, 33, 34, 35, 36, }; +static const unsigned int sd2_cdb_pins0[] = { 124, }; +static const unsigned int sd2_cdb_pins1[] = { 161, }; +static const unsigned int sd2_wpb_pins0[] = { 123, }; +static const unsigned int sd2_wpb_pins1[] = { 163, }; static const unsigned int sd3_pins[] = { 85, 86, 87, 88, 89, 90, }; static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, }; static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, }; @@ -877,19 +956,39 @@ static const unsigned int tpiu_trace_pins[] = { 53, 56, 57, 58, 59, 60, 61, static const unsigned int uart0_pins[] = { 121, 120, 134, 133, }; static const unsigned int uart0_nopause_pins[] = { 134, 133, }; static const unsigned int uart1_pins[] = { 136, 135, }; -static const unsigned int uart2_pins[] = { 11, 10, }; -static const unsigned int uart3_pins0[] = { 125, 126, 138, 137, }; -static const unsigned int uart3_pins1[] = { 111, 109, 84, 83, }; -static const unsigned int uart3_pins2[] = { 140, 139, 138, 137, }; -static const unsigned int uart3_pins3[] = { 139, 140, 84, 83, }; -static const unsigned int uart3_nopause_pins0[] = { 138, 137, }; -static const unsigned int uart3_nopause_pins1[] = { 84, 83, }; -static const unsigned int uart4_pins0[] = { 122, 123, 140, 139, }; -static const unsigned int uart4_pins1[] = { 100, 99, 140, 139, }; -static const unsigned int uart4_pins2[] = { 117, 116, 140, 139, }; -static const unsigned int uart4_nopause_pins[] = { 140, 139, }; -static const unsigned int usb0_drvvbus_pins[] = { 51, }; -static const unsigned int usb1_drvvbus_pins[] = { 134, }; +static const unsigned int uart2_cts_pins0[] = { 132, }; +static const unsigned int uart2_cts_pins1[] = { 162, }; +static const unsigned int uart2_rts_pins0[] = { 131, }; +static const unsigned int uart2_rts_pins1[] = { 161, }; +static const unsigned int uart2_rxd_pins0[] = { 11, }; +static const unsigned int uart2_rxd_pins1[] = { 160, }; +static const unsigned int uart2_rxd_pins2[] = { 130, }; +static const unsigned int uart2_txd_pins0[] = { 10, }; +static const unsigned int uart2_txd_pins1[] = { 159, }; +static const unsigned int uart2_txd_pins2[] = { 129, }; +static const unsigned int uart3_cts_pins0[] = { 125, }; +static const unsigned int uart3_cts_pins1[] = { 111, }; +static const unsigned int uart3_cts_pins2[] = { 140, }; +static const unsigned int uart3_rts_pins0[] = { 126, }; +static const unsigned int uart3_rts_pins1[] = { 109, }; +static const unsigned int uart3_rts_pins2[] = { 139, }; +static const unsigned int uart3_rxd_pins0[] = { 138, }; +static const unsigned int uart3_rxd_pins1[] = { 84, }; +static const unsigned int uart3_rxd_pins2[] = { 162, }; +static const unsigned int uart3_txd_pins0[] = { 137, }; +static const unsigned int uart3_txd_pins1[] = { 83, }; +static const unsigned int uart3_txd_pins2[] = { 161, }; +static const unsigned int uart4_basic_pins[] = { 140, 139, }; +static const unsigned int uart4_cts_pins0[] = { 122, }; +static const unsigned int uart4_cts_pins1[] = { 100, }; +static const unsigned int uart4_cts_pins2[] = { 117, }; +static const unsigned int uart4_rts_pins0[] = { 123, }; +static const unsigned int uart4_rts_pins1[] = { 99, }; +static const unsigned int uart4_rts_pins2[] = { 116, }; +static const unsigned int usb0_drvvbus_pins0[] = { 51, }; +static const unsigned int usb0_drvvbus_pins1[] = { 162, }; +static const unsigned int usb1_drvvbus_pins0[] = { 134, }; +static const unsigned int usb1_drvvbus_pins1[] = { 163, }; static const unsigned int visbus_dout_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 54, 55, 56, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, }; @@ -910,23 +1009,59 @@ struct atlas7_pin_group altas7_pin_groups[] = { GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins), GROUP("sp_rgmii_gpio_grp", sp_rgmii_gpio_pins), GROUP("lvds_gpio_grp", lvds_gpio_pins), - GROUP("uart_nand_gpio_grp", uart_nand_gpio_pins), + GROUP("jtag_uart_nand_gpio_grp", jtag_uart_nand_gpio_pins), GROUP("rtc_gpio_grp", rtc_gpio_pins), GROUP("audio_ac97_grp", audio_ac97_pins), + GROUP("audio_digmic_grp0", audio_digmic_pins0), + GROUP("audio_digmic_grp1", audio_digmic_pins1), + GROUP("audio_digmic_grp2", audio_digmic_pins2), GROUP("audio_func_dbg_grp", audio_func_dbg_pins), GROUP("audio_i2s_grp", audio_i2s_pins), GROUP("audio_i2s_2ch_grp", audio_i2s_2ch_pins), GROUP("audio_i2s_extclk_grp", audio_i2s_extclk_pins), - GROUP("audio_uart0_grp", audio_uart0_pins), - GROUP("audio_uart1_grp", audio_uart1_pins), - GROUP("audio_uart2_grp0", audio_uart2_pins0), - GROUP("audio_uart2_grp1", audio_uart2_pins1), - GROUP("c_can_trnsvr_grp", c_can_trnsvr_pins), - GROUP("c0_can_grp0", c0_can_pins0), - GROUP("c0_can_grp1", c0_can_pins1), - GROUP("c1_can_grp0", c1_can_pins0), - GROUP("c1_can_grp1", c1_can_pins1), - GROUP("c1_can_grp2", c1_can_pins2), + GROUP("audio_spdif_out_grp0", audio_spdif_out_pins0), + GROUP("audio_spdif_out_grp1", audio_spdif_out_pins1), + GROUP("audio_spdif_out_grp2", audio_spdif_out_pins2), + GROUP("audio_uart0_basic_grp", audio_uart0_basic_pins), + GROUP("audio_uart0_urfs_grp0", audio_uart0_urfs_pins0), + GROUP("audio_uart0_urfs_grp1", audio_uart0_urfs_pins1), + GROUP("audio_uart0_urfs_grp2", audio_uart0_urfs_pins2), + GROUP("audio_uart0_urfs_grp3", audio_uart0_urfs_pins3), + GROUP("audio_uart1_basic_grp", audio_uart1_basic_pins), + GROUP("audio_uart1_urfs_grp0", audio_uart1_urfs_pins0), + GROUP("audio_uart1_urfs_grp1", audio_uart1_urfs_pins1), + GROUP("audio_uart1_urfs_grp2", audio_uart1_urfs_pins2), + GROUP("audio_uart2_urfs_grp0", audio_uart2_urfs_pins0), + GROUP("audio_uart2_urfs_grp1", audio_uart2_urfs_pins1), + GROUP("audio_uart2_urfs_grp2", audio_uart2_urfs_pins2), + GROUP("audio_uart2_urxd_grp0", audio_uart2_urxd_pins0), + GROUP("audio_uart2_urxd_grp1", audio_uart2_urxd_pins1), + GROUP("audio_uart2_urxd_grp2", audio_uart2_urxd_pins2), + GROUP("audio_uart2_usclk_grp0", audio_uart2_usclk_pins0), + GROUP("audio_uart2_usclk_grp1", audio_uart2_usclk_pins1), + GROUP("audio_uart2_usclk_grp2", audio_uart2_usclk_pins2), + GROUP("audio_uart2_utfs_grp0", audio_uart2_utfs_pins0), + GROUP("audio_uart2_utfs_grp1", audio_uart2_utfs_pins1), + GROUP("audio_uart2_utfs_grp2", audio_uart2_utfs_pins2), + GROUP("audio_uart2_utxd_grp0", audio_uart2_utxd_pins0), + GROUP("audio_uart2_utxd_grp1", audio_uart2_utxd_pins1), + GROUP("audio_uart2_utxd_grp2", audio_uart2_utxd_pins2), + GROUP("c_can_trnsvr_en_grp0", c_can_trnsvr_en_pins0), + GROUP("c_can_trnsvr_en_grp1", c_can_trnsvr_en_pins1), + GROUP("c_can_trnsvr_intr_grp", c_can_trnsvr_intr_pins), + GROUP("c_can_trnsvr_stb_n_grp", c_can_trnsvr_stb_n_pins), + GROUP("c0_can_rxd_trnsv0_grp", c0_can_rxd_trnsv0_pins), + GROUP("c0_can_rxd_trnsv1_grp", c0_can_rxd_trnsv1_pins), + GROUP("c0_can_txd_trnsv0_grp", c0_can_txd_trnsv0_pins), + GROUP("c0_can_txd_trnsv1_grp", c0_can_txd_trnsv1_pins), + GROUP("c1_can_rxd_grp0", c1_can_rxd_pins0), + GROUP("c1_can_rxd_grp1", c1_can_rxd_pins1), + GROUP("c1_can_rxd_grp2", c1_can_rxd_pins2), + GROUP("c1_can_rxd_grp3", c1_can_rxd_pins3), + GROUP("c1_can_txd_grp0", c1_can_txd_pins0), + GROUP("c1_can_txd_grp1", c1_can_txd_pins1), + GROUP("c1_can_txd_grp2", c1_can_txd_pins2), + GROUP("c1_can_txd_grp3", c1_can_txd_pins3), GROUP("ca_audio_lpc_grp", ca_audio_lpc_pins), GROUP("ca_bt_lpc_grp", ca_bt_lpc_pins), GROUP("ca_coex_grp", ca_coex_pins), @@ -977,7 +1112,29 @@ struct atlas7_pin_group altas7_pin_groups[] = { GROUP("gn_trg_shutdown_grp3", gn_trg_shutdown_pins3), GROUP("i2c0_grp", i2c0_pins), GROUP("i2c1_grp", i2c1_pins), - GROUP("jtag_grp0", jtag_pins0), + GROUP("i2s0_grp", i2s0_pins), + GROUP("i2s1_basic_grp", i2s1_basic_pins), + GROUP("i2s1_rxd0_grp0", i2s1_rxd0_pins0), + GROUP("i2s1_rxd0_grp1", i2s1_rxd0_pins1), + GROUP("i2s1_rxd0_grp2", i2s1_rxd0_pins2), + GROUP("i2s1_rxd0_grp3", i2s1_rxd0_pins3), + GROUP("i2s1_rxd0_grp4", i2s1_rxd0_pins4), + GROUP("i2s1_rxd1_grp0", i2s1_rxd1_pins0), + GROUP("i2s1_rxd1_grp1", i2s1_rxd1_pins1), + GROUP("i2s1_rxd1_grp2", i2s1_rxd1_pins2), + GROUP("i2s1_rxd1_grp3", i2s1_rxd1_pins3), + GROUP("i2s1_rxd1_grp4", i2s1_rxd1_pins4), + GROUP("jtag_jt_dbg_nsrst_grp", jtag_jt_dbg_nsrst_pins), + GROUP("jtag_ntrst_grp0", jtag_ntrst_pins0), + GROUP("jtag_ntrst_grp1", jtag_ntrst_pins1), + GROUP("jtag_swdiotms_grp0", jtag_swdiotms_pins0), + GROUP("jtag_swdiotms_grp1", jtag_swdiotms_pins1), + GROUP("jtag_tck_grp0", jtag_tck_pins0), + GROUP("jtag_tck_grp1", jtag_tck_pins1), + GROUP("jtag_tdi_grp0", jtag_tdi_pins0), + GROUP("jtag_tdi_grp1", jtag_tdi_pins1), + GROUP("jtag_tdo_grp0", jtag_tdo_pins0), + GROUP("jtag_tdo_grp1", jtag_tdo_pins1), GROUP("ks_kas_spi_grp0", ks_kas_spi_pins0), GROUP("ld_ldd_grp", ld_ldd_pins), GROUP("ld_ldd_16bit_grp", ld_ldd_16bit_pins), @@ -1002,18 +1159,26 @@ struct atlas7_pin_group altas7_pin_groups[] = { GROUP("pw_cko0_grp0", pw_cko0_pins0), GROUP("pw_cko0_grp1", pw_cko0_pins1), GROUP("pw_cko0_grp2", pw_cko0_pins2), + GROUP("pw_cko0_grp3", pw_cko0_pins3), GROUP("pw_cko1_grp0", pw_cko1_pins0), GROUP("pw_cko1_grp1", pw_cko1_pins1), + GROUP("pw_cko1_grp2", pw_cko1_pins2), GROUP("pw_i2s01_clk_grp0", pw_i2s01_clk_pins0), GROUP("pw_i2s01_clk_grp1", pw_i2s01_clk_pins1), - GROUP("pw_pwm0_grp", pw_pwm0_pins), - GROUP("pw_pwm1_grp", pw_pwm1_pins), + GROUP("pw_i2s01_clk_grp2", pw_i2s01_clk_pins2), + GROUP("pw_pwm0_grp0", pw_pwm0_pins0), + GROUP("pw_pwm0_grp1", pw_pwm0_pins1), + GROUP("pw_pwm1_grp0", pw_pwm1_pins0), + GROUP("pw_pwm1_grp1", pw_pwm1_pins1), + GROUP("pw_pwm1_grp2", pw_pwm1_pins2), GROUP("pw_pwm2_grp0", pw_pwm2_pins0), GROUP("pw_pwm2_grp1", pw_pwm2_pins1), + GROUP("pw_pwm2_grp2", pw_pwm2_pins2), GROUP("pw_pwm3_grp0", pw_pwm3_pins0), GROUP("pw_pwm3_grp1", pw_pwm3_pins1), GROUP("pw_pwm_cpu_vol_grp0", pw_pwm_cpu_vol_pins0), GROUP("pw_pwm_cpu_vol_grp1", pw_pwm_cpu_vol_pins1), + GROUP("pw_pwm_cpu_vol_grp2", pw_pwm_cpu_vol_pins2), GROUP("pw_backlight_grp0", pw_backlight_pins0), GROUP("pw_backlight_grp1", pw_backlight_pins1), GROUP("rg_eth_mac_grp", rg_eth_mac_pins), @@ -1026,8 +1191,11 @@ struct atlas7_pin_group altas7_pin_groups[] = { GROUP("sd1_grp", sd1_pins), GROUP("sd1_4bit_grp0", sd1_4bit_pins0), GROUP("sd1_4bit_grp1", sd1_4bit_pins1), - GROUP("sd2_grp0", sd2_pins0), - GROUP("sd2_no_cdb_grp0", sd2_no_cdb_pins0), + GROUP("sd2_basic_grp", sd2_basic_pins), + GROUP("sd2_cdb_grp0", sd2_cdb_pins0), + GROUP("sd2_cdb_grp1", sd2_cdb_pins1), + GROUP("sd2_wpb_grp0", sd2_wpb_pins0), + GROUP("sd2_wpb_grp1", sd2_wpb_pins1), GROUP("sd3_grp", sd3_pins), GROUP("sd5_grp", sd5_pins), GROUP("sd6_grp0", sd6_pins0), @@ -1039,19 +1207,39 @@ struct atlas7_pin_group altas7_pin_groups[] = { GROUP("uart0_grp", uart0_pins), GROUP("uart0_nopause_grp", uart0_nopause_pins), GROUP("uart1_grp", uart1_pins), - GROUP("uart2_grp", uart2_pins), - GROUP("uart3_grp0", uart3_pins0), - GROUP("uart3_grp1", uart3_pins1), - GROUP("uart3_grp2", uart3_pins2), - GROUP("uart3_grp3", uart3_pins3), - GROUP("uart3_nopause_grp0", uart3_nopause_pins0), - GROUP("uart3_nopause_grp1", uart3_nopause_pins1), - GROUP("uart4_grp0", uart4_pins0), - GROUP("uart4_grp1", uart4_pins1), - GROUP("uart4_grp2", uart4_pins2), - GROUP("uart4_nopause_grp", uart4_nopause_pins), - GROUP("usb0_drvvbus_grp", usb0_drvvbus_pins), - GROUP("usb1_drvvbus_grp", usb1_drvvbus_pins), + GROUP("uart2_cts_grp0", uart2_cts_pins0), + GROUP("uart2_cts_grp1", uart2_cts_pins1), + GROUP("uart2_rts_grp0", uart2_rts_pins0), + GROUP("uart2_rts_grp1", uart2_rts_pins1), + GROUP("uart2_rxd_grp0", uart2_rxd_pins0), + GROUP("uart2_rxd_grp1", uart2_rxd_pins1), + GROUP("uart2_rxd_grp2", uart2_rxd_pins2), + GROUP("uart2_txd_grp0", uart2_txd_pins0), + GROUP("uart2_txd_grp1", uart2_txd_pins1), + GROUP("uart2_txd_grp2", uart2_txd_pins2), + GROUP("uart3_cts_grp0", uart3_cts_pins0), + GROUP("uart3_cts_grp1", uart3_cts_pins1), + GROUP("uart3_cts_grp2", uart3_cts_pins2), + GROUP("uart3_rts_grp0", uart3_rts_pins0), + GROUP("uart3_rts_grp1", uart3_rts_pins1), + GROUP("uart3_rts_grp2", uart3_rts_pins2), + GROUP("uart3_rxd_grp0", uart3_rxd_pins0), + GROUP("uart3_rxd_grp1", uart3_rxd_pins1), + GROUP("uart3_rxd_grp2", uart3_rxd_pins2), + GROUP("uart3_txd_grp0", uart3_txd_pins0), + GROUP("uart3_txd_grp1", uart3_txd_pins1), + GROUP("uart3_txd_grp2", uart3_txd_pins2), + GROUP("uart4_basic_grp", uart4_basic_pins), + GROUP("uart4_cts_grp0", uart4_cts_pins0), + GROUP("uart4_cts_grp1", uart4_cts_pins1), + GROUP("uart4_cts_grp2", uart4_cts_pins2), + GROUP("uart4_rts_grp0", uart4_rts_pins0), + GROUP("uart4_rts_grp1", uart4_rts_pins1), + GROUP("uart4_rts_grp2", uart4_rts_pins2), + GROUP("usb0_drvvbus_grp0", usb0_drvvbus_pins0), + GROUP("usb0_drvvbus_grp1", usb0_drvvbus_pins1), + GROUP("usb1_drvvbus_grp0", usb1_drvvbus_pins0), + GROUP("usb1_drvvbus_grp1", usb1_drvvbus_pins1), GROUP("visbus_dout_grp", visbus_dout_pins), GROUP("vi_vip1_grp", vi_vip1_pins), GROUP("vi_vip1_ext_grp", vi_vip1_ext_pins), @@ -1065,23 +1253,90 @@ static const char * const lcd_vip_gpio_grp[] = { "lcd_vip_gpio_grp", }; static const char * const sdio_i2s_gpio_grp[] = { "sdio_i2s_gpio_grp", }; static const char * const sp_rgmii_gpio_grp[] = { "sp_rgmii_gpio_grp", }; static const char * const lvds_gpio_grp[] = { "lvds_gpio_grp", }; -static const char * const uart_nand_gpio_grp[] = { "uart_nand_gpio_grp", }; +static const char * const jtag_uart_nand_gpio_grp[] = { + "jtag_uart_nand_gpio_grp", }; static const char * const rtc_gpio_grp[] = { "rtc_gpio_grp", }; static const char * const audio_ac97_grp[] = { "audio_ac97_grp", }; +static const char * const audio_digmic_grp0[] = { "audio_digmic_grp0", }; +static const char * const audio_digmic_grp1[] = { "audio_digmic_grp1", }; +static const char * const audio_digmic_grp2[] = { "audio_digmic_grp2", }; static const char * const audio_func_dbg_grp[] = { "audio_func_dbg_grp", }; static const char * const audio_i2s_grp[] = { "audio_i2s_grp", }; static const char * const audio_i2s_2ch_grp[] = { "audio_i2s_2ch_grp", }; static const char * const audio_i2s_extclk_grp[] = { "audio_i2s_extclk_grp", }; -static const char * const audio_uart0_grp[] = { "audio_uart0_grp", }; -static const char * const audio_uart1_grp[] = { "audio_uart1_grp", }; -static const char * const audio_uart2_grp0[] = { "audio_uart2_grp0", }; -static const char * const audio_uart2_grp1[] = { "audio_uart2_grp1", }; -static const char * const c_can_trnsvr_grp[] = { "c_can_trnsvr_grp", }; -static const char * const c0_can_grp0[] = { "c0_can_grp0", }; -static const char * const c0_can_grp1[] = { "c0_can_grp1", }; -static const char * const c1_can_grp0[] = { "c1_can_grp0", }; -static const char * const c1_can_grp1[] = { "c1_can_grp1", }; -static const char * const c1_can_grp2[] = { "c1_can_grp2", }; +static const char * const audio_spdif_out_grp0[] = { "audio_spdif_out_grp0", }; +static const char * const audio_spdif_out_grp1[] = { "audio_spdif_out_grp1", }; +static const char * const audio_spdif_out_grp2[] = { "audio_spdif_out_grp2", }; +static const char * const audio_uart0_basic_grp[] = { + "audio_uart0_basic_grp", }; +static const char * const audio_uart0_urfs_grp0[] = { + "audio_uart0_urfs_grp0", }; +static const char * const audio_uart0_urfs_grp1[] = { + "audio_uart0_urfs_grp1", }; +static const char * const audio_uart0_urfs_grp2[] = { + "audio_uart0_urfs_grp2", }; +static const char * const audio_uart0_urfs_grp3[] = { + "audio_uart0_urfs_grp3", }; +static const char * const audio_uart1_basic_grp[] = { + "audio_uart1_basic_grp", }; +static const char * const audio_uart1_urfs_grp0[] = { + "audio_uart1_urfs_grp0", }; +static const char * const audio_uart1_urfs_grp1[] = { + "audio_uart1_urfs_grp1", }; +static const char * const audio_uart1_urfs_grp2[] = { + "audio_uart1_urfs_grp2", }; +static const char * const audio_uart2_urfs_grp0[] = { + "audio_uart2_urfs_grp0", }; +static const char * const audio_uart2_urfs_grp1[] = { + "audio_uart2_urfs_grp1", }; +static const char * const audio_uart2_urfs_grp2[] = { + "audio_uart2_urfs_grp2", }; +static const char * const audio_uart2_urxd_grp0[] = { + "audio_uart2_urxd_grp0", }; +static const char * const audio_uart2_urxd_grp1[] = { + "audio_uart2_urxd_grp1", }; +static const char * const audio_uart2_urxd_grp2[] = { + "audio_uart2_urxd_grp2", }; +static const char * const audio_uart2_usclk_grp0[] = { + "audio_uart2_usclk_grp0", }; +static const char * const audio_uart2_usclk_grp1[] = { + "audio_uart2_usclk_grp1", }; +static const char * const audio_uart2_usclk_grp2[] = { + "audio_uart2_usclk_grp2", }; +static const char * const audio_uart2_utfs_grp0[] = { + "audio_uart2_utfs_grp0", }; +static const char * const audio_uart2_utfs_grp1[] = { + "audio_uart2_utfs_grp1", }; +static const char * const audio_uart2_utfs_grp2[] = { + "audio_uart2_utfs_grp2", }; +static const char * const audio_uart2_utxd_grp0[] = { + "audio_uart2_utxd_grp0", }; +static const char * const audio_uart2_utxd_grp1[] = { + "audio_uart2_utxd_grp1", }; +static const char * const audio_uart2_utxd_grp2[] = { + "audio_uart2_utxd_grp2", }; +static const char * const c_can_trnsvr_en_grp0[] = { "c_can_trnsvr_en_grp0", }; +static const char * const c_can_trnsvr_en_grp1[] = { "c_can_trnsvr_en_grp1", }; +static const char * const c_can_trnsvr_intr_grp[] = { + "c_can_trnsvr_intr_grp", }; +static const char * const c_can_trnsvr_stb_n_grp[] = { + "c_can_trnsvr_stb_n_grp", }; +static const char * const c0_can_rxd_trnsv0_grp[] = { + "c0_can_rxd_trnsv0_grp", }; +static const char * const c0_can_rxd_trnsv1_grp[] = { + "c0_can_rxd_trnsv1_grp", }; +static const char * const c0_can_txd_trnsv0_grp[] = { + "c0_can_txd_trnsv0_grp", }; +static const char * const c0_can_txd_trnsv1_grp[] = { + "c0_can_txd_trnsv1_grp", }; +static const char * const c1_can_rxd_grp0[] = { "c1_can_rxd_grp0", }; +static const char * const c1_can_rxd_grp1[] = { "c1_can_rxd_grp1", }; +static const char * const c1_can_rxd_grp2[] = { "c1_can_rxd_grp2", }; +static const char * const c1_can_rxd_grp3[] = { "c1_can_rxd_grp3", }; +static const char * const c1_can_txd_grp0[] = { "c1_can_txd_grp0", }; +static const char * const c1_can_txd_grp1[] = { "c1_can_txd_grp1", }; +static const char * const c1_can_txd_grp2[] = { "c1_can_txd_grp2", }; +static const char * const c1_can_txd_grp3[] = { "c1_can_txd_grp3", }; static const char * const ca_audio_lpc_grp[] = { "ca_audio_lpc_grp", }; static const char * const ca_bt_lpc_grp[] = { "ca_bt_lpc_grp", }; static const char * const ca_coex_grp[] = { "ca_coex_grp", }; @@ -1135,7 +1390,30 @@ static const char * const gn_trg_shutdown_grp2[] = { "gn_trg_shutdown_grp2", }; static const char * const gn_trg_shutdown_grp3[] = { "gn_trg_shutdown_grp3", }; static const char * const i2c0_grp[] = { "i2c0_grp", }; static const char * const i2c1_grp[] = { "i2c1_grp", }; -static const char * const jtag_grp0[] = { "jtag_grp0", }; +static const char * const i2s0_grp[] = { "i2s0_grp", }; +static const char * const i2s1_basic_grp[] = { "i2s1_basic_grp", }; +static const char * const i2s1_rxd0_grp0[] = { "i2s1_rxd0_grp0", }; +static const char * const i2s1_rxd0_grp1[] = { "i2s1_rxd0_grp1", }; +static const char * const i2s1_rxd0_grp2[] = { "i2s1_rxd0_grp2", }; +static const char * const i2s1_rxd0_grp3[] = { "i2s1_rxd0_grp3", }; +static const char * const i2s1_rxd0_grp4[] = { "i2s1_rxd0_grp4", }; +static const char * const i2s1_rxd1_grp0[] = { "i2s1_rxd1_grp0", }; +static const char * const i2s1_rxd1_grp1[] = { "i2s1_rxd1_grp1", }; +static const char * const i2s1_rxd1_grp2[] = { "i2s1_rxd1_grp2", }; +static const char * const i2s1_rxd1_grp3[] = { "i2s1_rxd1_grp3", }; +static const char * const i2s1_rxd1_grp4[] = { "i2s1_rxd1_grp4", }; +static const char * const jtag_jt_dbg_nsrst_grp[] = { + "jtag_jt_dbg_nsrst_grp", }; +static const char * const jtag_ntrst_grp0[] = { "jtag_ntrst_grp0", }; +static const char * const jtag_ntrst_grp1[] = { "jtag_ntrst_grp1", }; +static const char * const jtag_swdiotms_grp0[] = { "jtag_swdiotms_grp0", }; +static const char * const jtag_swdiotms_grp1[] = { "jtag_swdiotms_grp1", }; +static const char * const jtag_tck_grp0[] = { "jtag_tck_grp0", }; +static const char * const jtag_tck_grp1[] = { "jtag_tck_grp1", }; +static const char * const jtag_tdi_grp0[] = { "jtag_tdi_grp0", }; +static const char * const jtag_tdi_grp1[] = { "jtag_tdi_grp1", }; +static const char * const jtag_tdo_grp0[] = { "jtag_tdo_grp0", }; +static const char * const jtag_tdo_grp1[] = { "jtag_tdo_grp1", }; static const char * const ks_kas_spi_grp0[] = { "ks_kas_spi_grp0", }; static const char * const ld_ldd_grp[] = { "ld_ldd_grp", }; static const char * const ld_ldd_16bit_grp[] = { "ld_ldd_16bit_grp", }; @@ -1160,18 +1438,26 @@ static const char * const pwc_wakeup_src3_grp[] = { "pwc_wakeup_src3_grp", }; static const char * const pw_cko0_grp0[] = { "pw_cko0_grp0", }; static const char * const pw_cko0_grp1[] = { "pw_cko0_grp1", }; static const char * const pw_cko0_grp2[] = { "pw_cko0_grp2", }; +static const char * const pw_cko0_grp3[] = { "pw_cko0_grp3", }; static const char * const pw_cko1_grp0[] = { "pw_cko1_grp0", }; static const char * const pw_cko1_grp1[] = { "pw_cko1_grp1", }; +static const char * const pw_cko1_grp2[] = { "pw_cko1_grp2", }; static const char * const pw_i2s01_clk_grp0[] = { "pw_i2s01_clk_grp0", }; static const char * const pw_i2s01_clk_grp1[] = { "pw_i2s01_clk_grp1", }; -static const char * const pw_pwm0_grp[] = { "pw_pwm0_grp", }; -static const char * const pw_pwm1_grp[] = { "pw_pwm1_grp", }; +static const char * const pw_i2s01_clk_grp2[] = { "pw_i2s01_clk_grp2", }; +static const char * const pw_pwm0_grp0[] = { "pw_pwm0_grp0", }; +static const char * const pw_pwm0_grp1[] = { "pw_pwm0_grp1", }; +static const char * const pw_pwm1_grp0[] = { "pw_pwm1_grp0", }; +static const char * const pw_pwm1_grp1[] = { "pw_pwm1_grp1", }; +static const char * const pw_pwm1_grp2[] = { "pw_pwm1_grp2", }; static const char * const pw_pwm2_grp0[] = { "pw_pwm2_grp0", }; static const char * const pw_pwm2_grp1[] = { "pw_pwm2_grp1", }; +static const char * const pw_pwm2_grp2[] = { "pw_pwm2_grp2", }; static const char * const pw_pwm3_grp0[] = { "pw_pwm3_grp0", }; static const char * const pw_pwm3_grp1[] = { "pw_pwm3_grp1", }; static const char * const pw_pwm_cpu_vol_grp0[] = { "pw_pwm_cpu_vol_grp0", }; static const char * const pw_pwm_cpu_vol_grp1[] = { "pw_pwm_cpu_vol_grp1", }; +static const char * const pw_pwm_cpu_vol_grp2[] = { "pw_pwm_cpu_vol_grp2", }; static const char * const pw_backlight_grp0[] = { "pw_backlight_grp0", }; static const char * const pw_backlight_grp1[] = { "pw_backlight_grp1", }; static const char * const rg_eth_mac_grp[] = { "rg_eth_mac_grp", }; @@ -1187,8 +1473,11 @@ static const char * const sd0_4bit_grp[] = { "sd0_4bit_grp", }; static const char * const sd1_grp[] = { "sd1_grp", }; static const char * const sd1_4bit_grp0[] = { "sd1_4bit_grp0", }; static const char * const sd1_4bit_grp1[] = { "sd1_4bit_grp1", }; -static const char * const sd2_grp0[] = { "sd2_grp0", }; -static const char * const sd2_no_cdb_grp0[] = { "sd2_no_cdb_grp0", }; +static const char * const sd2_basic_grp[] = { "sd2_basic_grp", }; +static const char * const sd2_cdb_grp0[] = { "sd2_cdb_grp0", }; +static const char * const sd2_cdb_grp1[] = { "sd2_cdb_grp1", }; +static const char * const sd2_wpb_grp0[] = { "sd2_wpb_grp0", }; +static const char * const sd2_wpb_grp1[] = { "sd2_wpb_grp1", }; static const char * const sd3_grp[] = { "sd3_grp", }; static const char * const sd5_grp[] = { "sd5_grp", }; static const char * const sd6_grp0[] = { "sd6_grp0", }; @@ -1200,19 +1489,39 @@ static const char * const tpiu_trace_grp[] = { "tpiu_trace_grp", }; static const char * const uart0_grp[] = { "uart0_grp", }; static const char * const uart0_nopause_grp[] = { "uart0_nopause_grp", }; static const char * const uart1_grp[] = { "uart1_grp", }; -static const char * const uart2_grp[] = { "uart2_grp", }; -static const char * const uart3_grp0[] = { "uart3_grp0", }; -static const char * const uart3_grp1[] = { "uart3_grp1", }; -static const char * const uart3_grp2[] = { "uart3_grp2", }; -static const char * const uart3_grp3[] = { "uart3_grp3", }; -static const char * const uart3_nopause_grp0[] = { "uart3_nopause_grp0", }; -static const char * const uart3_nopause_grp1[] = { "uart3_nopause_grp1", }; -static const char * const uart4_grp0[] = { "uart4_grp0", }; -static const char * const uart4_grp1[] = { "uart4_grp1", }; -static const char * const uart4_grp2[] = { "uart4_grp2", }; -static const char * const uart4_nopause_grp[] = { "uart4_nopause_grp", }; -static const char * const usb0_drvvbus_grp[] = { "usb0_drvvbus_grp", }; -static const char * const usb1_drvvbus_grp[] = { "usb1_drvvbus_grp", }; +static const char * const uart2_cts_grp0[] = { "uart2_cts_grp0", }; +static const char * const uart2_cts_grp1[] = { "uart2_cts_grp1", }; +static const char * const uart2_rts_grp0[] = { "uart2_rts_grp0", }; +static const char * const uart2_rts_grp1[] = { "uart2_rts_grp1", }; +static const char * const uart2_rxd_grp0[] = { "uart2_rxd_grp0", }; +static const char * const uart2_rxd_grp1[] = { "uart2_rxd_grp1", }; +static const char * const uart2_rxd_grp2[] = { "uart2_rxd_grp2", }; +static const char * const uart2_txd_grp0[] = { "uart2_txd_grp0", }; +static const char * const uart2_txd_grp1[] = { "uart2_txd_grp1", }; +static const char * const uart2_txd_grp2[] = { "uart2_txd_grp2", }; +static const char * const uart3_cts_grp0[] = { "uart3_cts_grp0", }; +static const char * const uart3_cts_grp1[] = { "uart3_cts_grp1", }; +static const char * const uart3_cts_grp2[] = { "uart3_cts_grp2", }; +static const char * const uart3_rts_grp0[] = { "uart3_rts_grp0", }; +static const char * const uart3_rts_grp1[] = { "uart3_rts_grp1", }; +static const char * const uart3_rts_grp2[] = { "uart3_rts_grp2", }; +static const char * const uart3_rxd_grp0[] = { "uart3_rxd_grp0", }; +static const char * const uart3_rxd_grp1[] = { "uart3_rxd_grp1", }; +static const char * const uart3_rxd_grp2[] = { "uart3_rxd_grp2", }; +static const char * const uart3_txd_grp0[] = { "uart3_txd_grp0", }; +static const char * const uart3_txd_grp1[] = { "uart3_txd_grp1", }; +static const char * const uart3_txd_grp2[] = { "uart3_txd_grp2", }; +static const char * const uart4_basic_grp[] = { "uart4_basic_grp", }; +static const char * const uart4_cts_grp0[] = { "uart4_cts_grp0", }; +static const char * const uart4_cts_grp1[] = { "uart4_cts_grp1", }; +static const char * const uart4_cts_grp2[] = { "uart4_cts_grp2", }; +static const char * const uart4_rts_grp0[] = { "uart4_rts_grp0", }; +static const char * const uart4_rts_grp1[] = { "uart4_rts_grp1", }; +static const char * const uart4_rts_grp2[] = { "uart4_rts_grp2", }; +static const char * const usb0_drvvbus_grp0[] = { "usb0_drvvbus_grp0", }; +static const char * const usb0_drvvbus_grp1[] = { "usb0_drvvbus_grp1", }; +static const char * const usb1_drvvbus_grp0[] = { "usb1_drvvbus_grp0", }; +static const char * const usb1_drvvbus_grp1[] = { "usb1_drvvbus_grp1", }; static const char * const visbus_dout_grp[] = { "visbus_dout_grp", }; static const char * const vi_vip1_grp[] = { "vi_vip1_grp", }; static const char * const vi_vip1_ext_grp[] = { "vi_vip1_ext_grp", }; @@ -1376,7 +1685,7 @@ static struct atlas7_grp_mux lvds_gpio_grp_mux = { .pad_mux_list = lvds_gpio_grp_pad_mux, }; -static struct atlas7_pad_mux uart_nand_gpio_grp_pad_mux[] = { +static struct atlas7_pad_mux jtag_uart_nand_gpio_grp_pad_mux[] = { MUX(1, 44, 0, N, N, N, N), MUX(1, 43, 0, N, N, N, N), MUX(1, 42, 0, N, N, N, N), @@ -1401,11 +1710,16 @@ static struct atlas7_pad_mux uart_nand_gpio_grp_pad_mux[] = { MUX(1, 138, 0, N, N, N, N), MUX(1, 139, 0, N, N, N, N), MUX(1, 140, 0, N, N, N, N), + MUX(1, 159, 0, N, N, N, N), + MUX(1, 160, 0, N, N, N, N), + MUX(1, 161, 0, N, N, N, N), + MUX(1, 162, 0, N, N, N, N), + MUX(1, 163, 0, N, N, N, N), }; -static struct atlas7_grp_mux uart_nand_gpio_grp_mux = { - .pad_mux_count = ARRAY_SIZE(uart_nand_gpio_grp_pad_mux), - .pad_mux_list = uart_nand_gpio_grp_pad_mux, +static struct atlas7_grp_mux jtag_uart_nand_gpio_grp_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_uart_nand_gpio_grp_pad_mux), + .pad_mux_list = jtag_uart_nand_gpio_grp_pad_mux, }; static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = { @@ -1422,6 +1736,7 @@ static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = { MUX(0, 15, 0, N, N, N, N), MUX(0, 16, 0, N, N, N, N), MUX(0, 17, 0, N, N, N, N), + MUX(0, 9, 0, N, N, N, N), }; static struct atlas7_grp_mux rtc_gpio_grp_mux = { @@ -1441,6 +1756,33 @@ static struct atlas7_grp_mux audio_ac97_grp_mux = { .pad_mux_list = audio_ac97_grp_pad_mux, }; +static struct atlas7_pad_mux audio_digmic_grp0_pad_mux[] = { + MUX(1, 51, 3, 0xa10, 20, 0xa90, 20), +}; + +static struct atlas7_grp_mux audio_digmic_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_digmic_grp0_pad_mux), + .pad_mux_list = audio_digmic_grp0_pad_mux, +}; + +static struct atlas7_pad_mux audio_digmic_grp1_pad_mux[] = { + MUX(1, 122, 5, 0xa10, 20, 0xa90, 20), +}; + +static struct atlas7_grp_mux audio_digmic_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_digmic_grp1_pad_mux), + .pad_mux_list = audio_digmic_grp1_pad_mux, +}; + +static struct atlas7_pad_mux audio_digmic_grp2_pad_mux[] = { + MUX(1, 161, 7, 0xa10, 20, 0xa90, 20), +}; + +static struct atlas7_grp_mux audio_digmic_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(audio_digmic_grp2_pad_mux), + .pad_mux_list = audio_digmic_grp2_pad_mux, +}; + static struct atlas7_pad_mux audio_func_dbg_grp_pad_mux[] = { MUX(1, 141, 4, N, N, N, N), MUX(1, 144, 4, N, N, N, N), @@ -1512,111 +1854,397 @@ static struct atlas7_grp_mux audio_i2s_extclk_grp_mux = { .pad_mux_list = audio_i2s_extclk_grp_pad_mux, }; -static struct atlas7_pad_mux audio_uart0_grp_pad_mux[] = { +static struct atlas7_pad_mux audio_spdif_out_grp0_pad_mux[] = { + MUX(1, 112, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_spdif_out_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp0_pad_mux), + .pad_mux_list = audio_spdif_out_grp0_pad_mux, +}; + +static struct atlas7_pad_mux audio_spdif_out_grp1_pad_mux[] = { + MUX(1, 116, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_spdif_out_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp1_pad_mux), + .pad_mux_list = audio_spdif_out_grp1_pad_mux, +}; + +static struct atlas7_pad_mux audio_spdif_out_grp2_pad_mux[] = { + MUX(1, 142, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux audio_spdif_out_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp2_pad_mux), + .pad_mux_list = audio_spdif_out_grp2_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart0_basic_grp_pad_mux[] = { MUX(1, 143, 1, N, N, N, N), MUX(1, 142, 1, N, N, N, N), MUX(1, 141, 1, N, N, N, N), MUX(1, 144, 1, N, N, N, N), }; -static struct atlas7_grp_mux audio_uart0_grp_mux = { - .pad_mux_count = ARRAY_SIZE(audio_uart0_grp_pad_mux), - .pad_mux_list = audio_uart0_grp_pad_mux, +static struct atlas7_grp_mux audio_uart0_basic_grp_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart0_basic_grp_pad_mux), + .pad_mux_list = audio_uart0_basic_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart0_urfs_grp0_pad_mux[] = { + MUX(1, 117, 5, 0xa10, 28, 0xa90, 28), }; -static struct atlas7_pad_mux audio_uart1_grp_pad_mux[] = { - MUX(1, 147, 1, N, N, N, N), - MUX(1, 146, 1, N, N, N, N), - MUX(1, 145, 1, N, N, N, N), - MUX(1, 148, 1, N, N, N, N), +static struct atlas7_grp_mux audio_uart0_urfs_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp0_pad_mux), + .pad_mux_list = audio_uart0_urfs_grp0_pad_mux, }; -static struct atlas7_grp_mux audio_uart1_grp_mux = { - .pad_mux_count = ARRAY_SIZE(audio_uart1_grp_pad_mux), - .pad_mux_list = audio_uart1_grp_pad_mux, +static struct atlas7_pad_mux audio_uart0_urfs_grp1_pad_mux[] = { + MUX(1, 139, 3, 0xa10, 28, 0xa90, 28), }; -static struct atlas7_pad_mux audio_uart2_grp0_pad_mux[] = { +static struct atlas7_grp_mux audio_uart0_urfs_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp1_pad_mux), + .pad_mux_list = audio_uart0_urfs_grp1_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart0_urfs_grp2_pad_mux[] = { + MUX(1, 163, 3, 0xa10, 28, 0xa90, 28), +}; + +static struct atlas7_grp_mux audio_uart0_urfs_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp2_pad_mux), + .pad_mux_list = audio_uart0_urfs_grp2_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart0_urfs_grp3_pad_mux[] = { + MUX(1, 162, 6, 0xa10, 28, 0xa90, 28), +}; + +static struct atlas7_grp_mux audio_uart0_urfs_grp3_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp3_pad_mux), + .pad_mux_list = audio_uart0_urfs_grp3_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart1_basic_grp_pad_mux[] = { + MUX(1, 147, 1, 0xa10, 24, 0xa90, 24), + MUX(1, 146, 1, 0xa10, 25, 0xa90, 25), + MUX(1, 145, 1, 0xa10, 23, 0xa90, 23), + MUX(1, 148, 1, 0xa10, 22, 0xa90, 22), +}; + +static struct atlas7_grp_mux audio_uart1_basic_grp_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart1_basic_grp_pad_mux), + .pad_mux_list = audio_uart1_basic_grp_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart1_urfs_grp0_pad_mux[] = { + MUX(1, 117, 6, 0xa10, 29, 0xa90, 29), +}; + +static struct atlas7_grp_mux audio_uart1_urfs_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp0_pad_mux), + .pad_mux_list = audio_uart1_urfs_grp0_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart1_urfs_grp1_pad_mux[] = { + MUX(1, 140, 3, 0xa10, 29, 0xa90, 29), +}; + +static struct atlas7_grp_mux audio_uart1_urfs_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp1_pad_mux), + .pad_mux_list = audio_uart1_urfs_grp1_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart1_urfs_grp2_pad_mux[] = { + MUX(1, 163, 4, 0xa10, 29, 0xa90, 29), +}; + +static struct atlas7_grp_mux audio_uart1_urfs_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp2_pad_mux), + .pad_mux_list = audio_uart1_urfs_grp2_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_urfs_grp0_pad_mux[] = { + MUX(1, 139, 4, 0xa10, 30, 0xa90, 30), +}; + +static struct atlas7_grp_mux audio_uart2_urfs_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp0_pad_mux), + .pad_mux_list = audio_uart2_urfs_grp0_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_urfs_grp1_pad_mux[] = { + MUX(1, 163, 6, 0xa10, 30, 0xa90, 30), +}; + +static struct atlas7_grp_mux audio_uart2_urfs_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp1_pad_mux), + .pad_mux_list = audio_uart2_urfs_grp1_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_urfs_grp2_pad_mux[] = { + MUX(1, 96, 3, 0xa10, 30, 0xa90, 30), +}; + +static struct atlas7_grp_mux audio_uart2_urfs_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp2_pad_mux), + .pad_mux_list = audio_uart2_urfs_grp2_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_urxd_grp0_pad_mux[] = { MUX(1, 20, 2, 0xa00, 24, 0xa80, 24), - MUX(1, 21, 2, 0xa00, 25, 0xa80, 25), - MUX(1, 19, 2, 0xa00, 23, 0xa80, 23), - MUX(1, 18, 2, 0xa00, 22, 0xa80, 22), }; -static struct atlas7_grp_mux audio_uart2_grp0_mux = { - .pad_mux_count = ARRAY_SIZE(audio_uart2_grp0_pad_mux), - .pad_mux_list = audio_uart2_grp0_pad_mux, +static struct atlas7_grp_mux audio_uart2_urxd_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp0_pad_mux), + .pad_mux_list = audio_uart2_urxd_grp0_pad_mux, }; -static struct atlas7_pad_mux audio_uart2_grp1_pad_mux[] = { +static struct atlas7_pad_mux audio_uart2_urxd_grp1_pad_mux[] = { MUX(1, 109, 2, 0xa00, 24, 0xa80, 24), - MUX(1, 110, 2, 0xa00, 25, 0xa80, 25), +}; + +static struct atlas7_grp_mux audio_uart2_urxd_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp1_pad_mux), + .pad_mux_list = audio_uart2_urxd_grp1_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_urxd_grp2_pad_mux[] = { + MUX(1, 93, 3, 0xa00, 24, 0xa80, 24), +}; + +static struct atlas7_grp_mux audio_uart2_urxd_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp2_pad_mux), + .pad_mux_list = audio_uart2_urxd_grp2_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_usclk_grp0_pad_mux[] = { + MUX(1, 19, 2, 0xa00, 23, 0xa80, 23), +}; + +static struct atlas7_grp_mux audio_uart2_usclk_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp0_pad_mux), + .pad_mux_list = audio_uart2_usclk_grp0_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_usclk_grp1_pad_mux[] = { MUX(1, 101, 2, 0xa00, 23, 0xa80, 23), +}; + +static struct atlas7_grp_mux audio_uart2_usclk_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp1_pad_mux), + .pad_mux_list = audio_uart2_usclk_grp1_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_usclk_grp2_pad_mux[] = { + MUX(1, 91, 3, 0xa00, 23, 0xa80, 23), +}; + +static struct atlas7_grp_mux audio_uart2_usclk_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp2_pad_mux), + .pad_mux_list = audio_uart2_usclk_grp2_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_utfs_grp0_pad_mux[] = { + MUX(1, 18, 2, 0xa00, 22, 0xa80, 22), +}; + +static struct atlas7_grp_mux audio_uart2_utfs_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp0_pad_mux), + .pad_mux_list = audio_uart2_utfs_grp0_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_utfs_grp1_pad_mux[] = { MUX(1, 111, 2, 0xa00, 22, 0xa80, 22), }; -static struct atlas7_grp_mux audio_uart2_grp1_mux = { - .pad_mux_count = ARRAY_SIZE(audio_uart2_grp1_pad_mux), - .pad_mux_list = audio_uart2_grp1_pad_mux, +static struct atlas7_grp_mux audio_uart2_utfs_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp1_pad_mux), + .pad_mux_list = audio_uart2_utfs_grp1_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_utfs_grp2_pad_mux[] = { + MUX(1, 94, 3, 0xa00, 22, 0xa80, 22), +}; + +static struct atlas7_grp_mux audio_uart2_utfs_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp2_pad_mux), + .pad_mux_list = audio_uart2_utfs_grp2_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_utxd_grp0_pad_mux[] = { + MUX(1, 21, 2, 0xa00, 25, 0xa80, 25), +}; + +static struct atlas7_grp_mux audio_uart2_utxd_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp0_pad_mux), + .pad_mux_list = audio_uart2_utxd_grp0_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_utxd_grp1_pad_mux[] = { + MUX(1, 110, 2, 0xa00, 25, 0xa80, 25), +}; + +static struct atlas7_grp_mux audio_uart2_utxd_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp1_pad_mux), + .pad_mux_list = audio_uart2_utxd_grp1_pad_mux, +}; + +static struct atlas7_pad_mux audio_uart2_utxd_grp2_pad_mux[] = { + MUX(1, 92, 3, 0xa00, 25, 0xa80, 25), +}; + +static struct atlas7_grp_mux audio_uart2_utxd_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp2_pad_mux), + .pad_mux_list = audio_uart2_utxd_grp2_pad_mux, +}; + +static struct atlas7_pad_mux c_can_trnsvr_en_grp0_pad_mux[] = { + MUX(0, 2, 6, N, N, N, N), }; -static struct atlas7_pad_mux c_can_trnsvr_grp_pad_mux[] = { +static struct atlas7_grp_mux c_can_trnsvr_en_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp0_pad_mux), + .pad_mux_list = c_can_trnsvr_en_grp0_pad_mux, +}; + +static struct atlas7_pad_mux c_can_trnsvr_en_grp1_pad_mux[] = { + MUX(0, 0, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux c_can_trnsvr_en_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp1_pad_mux), + .pad_mux_list = c_can_trnsvr_en_grp1_pad_mux, +}; + +static struct atlas7_pad_mux c_can_trnsvr_intr_grp_pad_mux[] = { MUX(0, 1, 2, N, N, N, N), }; -static struct atlas7_grp_mux c_can_trnsvr_grp_mux = { - .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_grp_pad_mux), - .pad_mux_list = c_can_trnsvr_grp_pad_mux, +static struct atlas7_grp_mux c_can_trnsvr_intr_grp_mux = { + .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_intr_grp_pad_mux), + .pad_mux_list = c_can_trnsvr_intr_grp_pad_mux, }; -static struct atlas7_pad_mux c0_can_grp0_pad_mux[] = { +static struct atlas7_pad_mux c_can_trnsvr_stb_n_grp_pad_mux[] = { + MUX(0, 3, 6, N, N, N, N), +}; + +static struct atlas7_grp_mux c_can_trnsvr_stb_n_grp_mux = { + .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_stb_n_grp_pad_mux), + .pad_mux_list = c_can_trnsvr_stb_n_grp_pad_mux, +}; + +static struct atlas7_pad_mux c0_can_rxd_trnsv0_grp_pad_mux[] = { MUX(0, 11, 1, 0xa08, 9, 0xa88, 9), +}; + +static struct atlas7_grp_mux c0_can_rxd_trnsv0_grp_mux = { + .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv0_grp_pad_mux), + .pad_mux_list = c0_can_rxd_trnsv0_grp_pad_mux, +}; + +static struct atlas7_pad_mux c0_can_rxd_trnsv1_grp_pad_mux[] = { + MUX(0, 2, 5, 0xa10, 9, 0xa90, 9), +}; + +static struct atlas7_grp_mux c0_can_rxd_trnsv1_grp_mux = { + .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv1_grp_pad_mux), + .pad_mux_list = c0_can_rxd_trnsv1_grp_pad_mux, +}; + +static struct atlas7_pad_mux c0_can_txd_trnsv0_grp_pad_mux[] = { MUX(0, 10, 1, N, N, N, N), }; -static struct atlas7_grp_mux c0_can_grp0_mux = { - .pad_mux_count = ARRAY_SIZE(c0_can_grp0_pad_mux), - .pad_mux_list = c0_can_grp0_pad_mux, +static struct atlas7_grp_mux c0_can_txd_trnsv0_grp_mux = { + .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv0_grp_pad_mux), + .pad_mux_list = c0_can_txd_trnsv0_grp_pad_mux, }; -static struct atlas7_pad_mux c0_can_grp1_pad_mux[] = { - MUX(0, 2, 5, 0xa08, 9, 0xa88, 9), +static struct atlas7_pad_mux c0_can_txd_trnsv1_grp_pad_mux[] = { MUX(0, 3, 5, N, N, N, N), }; -static struct atlas7_grp_mux c0_can_grp1_mux = { - .pad_mux_count = ARRAY_SIZE(c0_can_grp1_pad_mux), - .pad_mux_list = c0_can_grp1_pad_mux, +static struct atlas7_grp_mux c0_can_txd_trnsv1_grp_mux = { + .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv1_grp_pad_mux), + .pad_mux_list = c0_can_txd_trnsv1_grp_pad_mux, }; -static struct atlas7_pad_mux c1_can_grp0_pad_mux[] = { +static struct atlas7_pad_mux c1_can_rxd_grp0_pad_mux[] = { MUX(1, 138, 2, 0xa00, 4, 0xa80, 4), - MUX(1, 137, 2, N, N, N, N), }; -static struct atlas7_grp_mux c1_can_grp0_mux = { - .pad_mux_count = ARRAY_SIZE(c1_can_grp0_pad_mux), - .pad_mux_list = c1_can_grp0_pad_mux, +static struct atlas7_grp_mux c1_can_rxd_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp0_pad_mux), + .pad_mux_list = c1_can_rxd_grp0_pad_mux, }; -static struct atlas7_pad_mux c1_can_grp1_pad_mux[] = { +static struct atlas7_pad_mux c1_can_rxd_grp1_pad_mux[] = { MUX(1, 147, 2, 0xa00, 4, 0xa80, 4), - MUX(1, 146, 2, N, N, N, N), }; -static struct atlas7_grp_mux c1_can_grp1_mux = { - .pad_mux_count = ARRAY_SIZE(c1_can_grp1_pad_mux), - .pad_mux_list = c1_can_grp1_pad_mux, +static struct atlas7_grp_mux c1_can_rxd_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp1_pad_mux), + .pad_mux_list = c1_can_rxd_grp1_pad_mux, }; -static struct atlas7_pad_mux c1_can_grp2_pad_mux[] = { +static struct atlas7_pad_mux c1_can_rxd_grp2_pad_mux[] = { MUX(0, 2, 2, 0xa00, 4, 0xa80, 4), +}; + +static struct atlas7_grp_mux c1_can_rxd_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp2_pad_mux), + .pad_mux_list = c1_can_rxd_grp2_pad_mux, +}; + +static struct atlas7_pad_mux c1_can_rxd_grp3_pad_mux[] = { + MUX(1, 162, 4, 0xa00, 4, 0xa80, 4), +}; + +static struct atlas7_grp_mux c1_can_rxd_grp3_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp3_pad_mux), + .pad_mux_list = c1_can_rxd_grp3_pad_mux, +}; + +static struct atlas7_pad_mux c1_can_txd_grp0_pad_mux[] = { + MUX(1, 137, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux c1_can_txd_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp0_pad_mux), + .pad_mux_list = c1_can_txd_grp0_pad_mux, +}; + +static struct atlas7_pad_mux c1_can_txd_grp1_pad_mux[] = { + MUX(1, 146, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux c1_can_txd_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp1_pad_mux), + .pad_mux_list = c1_can_txd_grp1_pad_mux, +}; + +static struct atlas7_pad_mux c1_can_txd_grp2_pad_mux[] = { MUX(0, 3, 2, N, N, N, N), }; -static struct atlas7_grp_mux c1_can_grp2_mux = { - .pad_mux_count = ARRAY_SIZE(c1_can_grp2_pad_mux), - .pad_mux_list = c1_can_grp2_pad_mux, +static struct atlas7_grp_mux c1_can_txd_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp2_pad_mux), + .pad_mux_list = c1_can_txd_grp2_pad_mux, +}; + +static struct atlas7_pad_mux c1_can_txd_grp3_pad_mux[] = { + MUX(1, 161, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux c1_can_txd_grp3_mux = { + .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp3_pad_mux), + .pad_mux_list = c1_can_txd_grp3_pad_mux, }; static struct atlas7_pad_mux ca_audio_lpc_grp_pad_mux[] = { @@ -2198,18 +2826,215 @@ static struct atlas7_grp_mux i2c1_grp_mux = { .pad_mux_list = i2c1_grp_pad_mux, }; -static struct atlas7_pad_mux jtag_grp0_pad_mux[] = { +static struct atlas7_pad_mux i2s0_grp_pad_mux[] = { + MUX(1, 91, 2, 0xa10, 12, 0xa90, 12), + MUX(1, 93, 2, 0xa10, 13, 0xa90, 13), + MUX(1, 94, 2, 0xa10, 14, 0xa90, 14), + MUX(1, 92, 2, 0xa10, 15, 0xa90, 15), +}; + +static struct atlas7_grp_mux i2s0_grp_mux = { + .pad_mux_count = ARRAY_SIZE(i2s0_grp_pad_mux), + .pad_mux_list = i2s0_grp_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_basic_grp_pad_mux[] = { + MUX(1, 95, 2, 0xa10, 16, 0xa90, 16), + MUX(1, 96, 2, 0xa10, 19, 0xa90, 19), +}; + +static struct atlas7_grp_mux i2s1_basic_grp_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_basic_grp_pad_mux), + .pad_mux_list = i2s1_basic_grp_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd0_grp0_pad_mux[] = { + MUX(1, 61, 4, 0xa10, 17, 0xa90, 17), +}; + +static struct atlas7_grp_mux i2s1_rxd0_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp0_pad_mux), + .pad_mux_list = i2s1_rxd0_grp0_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd0_grp1_pad_mux[] = { + MUX(1, 131, 4, 0xa10, 17, 0xa90, 17), +}; + +static struct atlas7_grp_mux i2s1_rxd0_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp1_pad_mux), + .pad_mux_list = i2s1_rxd0_grp1_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd0_grp2_pad_mux[] = { + MUX(1, 129, 2, 0xa10, 17, 0xa90, 17), +}; + +static struct atlas7_grp_mux i2s1_rxd0_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp2_pad_mux), + .pad_mux_list = i2s1_rxd0_grp2_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd0_grp3_pad_mux[] = { + MUX(1, 117, 7, 0xa10, 17, 0xa90, 17), +}; + +static struct atlas7_grp_mux i2s1_rxd0_grp3_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp3_pad_mux), + .pad_mux_list = i2s1_rxd0_grp3_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd0_grp4_pad_mux[] = { + MUX(1, 83, 4, 0xa10, 17, 0xa90, 17), +}; + +static struct atlas7_grp_mux i2s1_rxd0_grp4_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp4_pad_mux), + .pad_mux_list = i2s1_rxd0_grp4_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd1_grp0_pad_mux[] = { + MUX(1, 72, 4, 0xa10, 18, 0xa90, 18), +}; + +static struct atlas7_grp_mux i2s1_rxd1_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp0_pad_mux), + .pad_mux_list = i2s1_rxd1_grp0_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd1_grp1_pad_mux[] = { + MUX(1, 132, 4, 0xa10, 18, 0xa90, 18), +}; + +static struct atlas7_grp_mux i2s1_rxd1_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp1_pad_mux), + .pad_mux_list = i2s1_rxd1_grp1_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd1_grp2_pad_mux[] = { + MUX(1, 130, 2, 0xa10, 18, 0xa90, 18), +}; + +static struct atlas7_grp_mux i2s1_rxd1_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp2_pad_mux), + .pad_mux_list = i2s1_rxd1_grp2_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd1_grp3_pad_mux[] = { + MUX(1, 118, 7, 0xa10, 18, 0xa90, 18), +}; + +static struct atlas7_grp_mux i2s1_rxd1_grp3_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp3_pad_mux), + .pad_mux_list = i2s1_rxd1_grp3_pad_mux, +}; + +static struct atlas7_pad_mux i2s1_rxd1_grp4_pad_mux[] = { + MUX(1, 84, 4, 0xa10, 18, 0xa90, 18), +}; + +static struct atlas7_grp_mux i2s1_rxd1_grp4_mux = { + .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp4_pad_mux), + .pad_mux_list = i2s1_rxd1_grp4_pad_mux, +}; + +static struct atlas7_pad_mux jtag_jt_dbg_nsrst_grp_pad_mux[] = { MUX(1, 125, 5, 0xa08, 2, 0xa88, 2), +}; + +static struct atlas7_grp_mux jtag_jt_dbg_nsrst_grp_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_jt_dbg_nsrst_grp_pad_mux), + .pad_mux_list = jtag_jt_dbg_nsrst_grp_pad_mux, +}; + +static struct atlas7_pad_mux jtag_ntrst_grp0_pad_mux[] = { MUX(0, 4, 3, 0xa08, 3, 0xa88, 3), - MUX(0, 2, 3, N, N, N, N), - MUX(0, 0, 3, N, N, N, N), - MUX(0, 1, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux jtag_ntrst_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp0_pad_mux), + .pad_mux_list = jtag_ntrst_grp0_pad_mux, +}; + +static struct atlas7_pad_mux jtag_ntrst_grp1_pad_mux[] = { + MUX(1, 163, 1, 0xa08, 3, 0xa88, 3), +}; + +static struct atlas7_grp_mux jtag_ntrst_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp1_pad_mux), + .pad_mux_list = jtag_ntrst_grp1_pad_mux, +}; + +static struct atlas7_pad_mux jtag_swdiotms_grp0_pad_mux[] = { + MUX(0, 2, 3, 0xa10, 10, 0xa90, 10), +}; + +static struct atlas7_grp_mux jtag_swdiotms_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp0_pad_mux), + .pad_mux_list = jtag_swdiotms_grp0_pad_mux, +}; + +static struct atlas7_pad_mux jtag_swdiotms_grp1_pad_mux[] = { + MUX(1, 160, 1, 0xa10, 10, 0xa90, 10), +}; + +static struct atlas7_grp_mux jtag_swdiotms_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp1_pad_mux), + .pad_mux_list = jtag_swdiotms_grp1_pad_mux, +}; + +static struct atlas7_pad_mux jtag_tck_grp0_pad_mux[] = { + MUX(0, 0, 3, 0xa10, 11, 0xa90, 11), +}; + +static struct atlas7_grp_mux jtag_tck_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_tck_grp0_pad_mux), + .pad_mux_list = jtag_tck_grp0_pad_mux, +}; + +static struct atlas7_pad_mux jtag_tck_grp1_pad_mux[] = { + MUX(1, 161, 1, 0xa10, 11, 0xa90, 11), +}; + +static struct atlas7_grp_mux jtag_tck_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_tck_grp1_pad_mux), + .pad_mux_list = jtag_tck_grp1_pad_mux, +}; + +static struct atlas7_pad_mux jtag_tdi_grp0_pad_mux[] = { + MUX(0, 1, 3, 0xa10, 31, 0xa90, 31), +}; + +static struct atlas7_grp_mux jtag_tdi_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp0_pad_mux), + .pad_mux_list = jtag_tdi_grp0_pad_mux, +}; + +static struct atlas7_pad_mux jtag_tdi_grp1_pad_mux[] = { + MUX(1, 162, 1, 0xa10, 31, 0xa90, 31), +}; + +static struct atlas7_grp_mux jtag_tdi_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp1_pad_mux), + .pad_mux_list = jtag_tdi_grp1_pad_mux, +}; + +static struct atlas7_pad_mux jtag_tdo_grp0_pad_mux[] = { MUX(0, 3, 3, N, N, N, N), }; -static struct atlas7_grp_mux jtag_grp0_mux = { - .pad_mux_count = ARRAY_SIZE(jtag_grp0_pad_mux), - .pad_mux_list = jtag_grp0_pad_mux, +static struct atlas7_grp_mux jtag_tdo_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp0_pad_mux), + .pad_mux_list = jtag_tdo_grp0_pad_mux, +}; + +static struct atlas7_pad_mux jtag_tdo_grp1_pad_mux[] = { + MUX(1, 159, 1, N, N, N, N), +}; + +static struct atlas7_grp_mux jtag_tdo_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp1_pad_mux), + .pad_mux_list = jtag_tdo_grp1_pad_mux, }; static struct atlas7_pad_mux ks_kas_spi_grp0_pad_mux[] = { @@ -2401,6 +3226,7 @@ static struct atlas7_grp_mux nd_df_nowp_grp_mux = { static struct atlas7_pad_mux ps_grp_pad_mux[] = { MUX(1, 120, 2, N, N, N, N), MUX(1, 119, 2, N, N, N, N), + MUX(1, 121, 5, N, N, N, N), }; static struct atlas7_grp_mux ps_grp_mux = { @@ -2534,6 +3360,15 @@ static struct atlas7_grp_mux pw_cko0_grp2_mux = { .pad_mux_list = pw_cko0_grp2_pad_mux, }; +static struct atlas7_pad_mux pw_cko0_grp3_pad_mux[] = { + MUX(1, 162, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_cko0_grp3_mux = { + .pad_mux_count = ARRAY_SIZE(pw_cko0_grp3_pad_mux), + .pad_mux_list = pw_cko0_grp3_pad_mux, +}; + static struct atlas7_pad_mux pw_cko1_grp0_pad_mux[] = { MUX(1, 124, 3, N, N, N, N), }; @@ -2552,6 +3387,15 @@ static struct atlas7_grp_mux pw_cko1_grp1_mux = { .pad_mux_list = pw_cko1_grp1_pad_mux, }; +static struct atlas7_pad_mux pw_cko1_grp2_pad_mux[] = { + MUX(1, 163, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_cko1_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(pw_cko1_grp2_pad_mux), + .pad_mux_list = pw_cko1_grp2_pad_mux, +}; + static struct atlas7_pad_mux pw_i2s01_clk_grp0_pad_mux[] = { MUX(1, 125, 3, N, N, N, N), }; @@ -2570,22 +3414,58 @@ static struct atlas7_grp_mux pw_i2s01_clk_grp1_mux = { .pad_mux_list = pw_i2s01_clk_grp1_pad_mux, }; -static struct atlas7_pad_mux pw_pwm0_grp_pad_mux[] = { +static struct atlas7_pad_mux pw_i2s01_clk_grp2_pad_mux[] = { + MUX(1, 132, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_i2s01_clk_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp2_pad_mux), + .pad_mux_list = pw_i2s01_clk_grp2_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm0_grp0_pad_mux[] = { MUX(1, 119, 3, N, N, N, N), }; -static struct atlas7_grp_mux pw_pwm0_grp_mux = { - .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp_pad_mux), - .pad_mux_list = pw_pwm0_grp_pad_mux, +static struct atlas7_grp_mux pw_pwm0_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp0_pad_mux), + .pad_mux_list = pw_pwm0_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm0_grp1_pad_mux[] = { + MUX(1, 159, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm0_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp1_pad_mux), + .pad_mux_list = pw_pwm0_grp1_pad_mux, }; -static struct atlas7_pad_mux pw_pwm1_grp_pad_mux[] = { +static struct atlas7_pad_mux pw_pwm1_grp0_pad_mux[] = { MUX(1, 120, 3, N, N, N, N), }; -static struct atlas7_grp_mux pw_pwm1_grp_mux = { - .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp_pad_mux), - .pad_mux_list = pw_pwm1_grp_pad_mux, +static struct atlas7_grp_mux pw_pwm1_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp0_pad_mux), + .pad_mux_list = pw_pwm1_grp0_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm1_grp1_pad_mux[] = { + MUX(1, 160, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm1_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp1_pad_mux), + .pad_mux_list = pw_pwm1_grp1_pad_mux, +}; + +static struct atlas7_pad_mux pw_pwm1_grp2_pad_mux[] = { + MUX(1, 131, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm1_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp2_pad_mux), + .pad_mux_list = pw_pwm1_grp2_pad_mux, }; static struct atlas7_pad_mux pw_pwm2_grp0_pad_mux[] = { @@ -2606,6 +3486,15 @@ static struct atlas7_grp_mux pw_pwm2_grp1_mux = { .pad_mux_list = pw_pwm2_grp1_pad_mux, }; +static struct atlas7_pad_mux pw_pwm2_grp2_pad_mux[] = { + MUX(1, 161, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm2_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp2_pad_mux), + .pad_mux_list = pw_pwm2_grp2_pad_mux, +}; + static struct atlas7_pad_mux pw_pwm3_grp0_pad_mux[] = { MUX(1, 122, 3, N, N, N, N), }; @@ -2642,6 +3531,15 @@ static struct atlas7_grp_mux pw_pwm_cpu_vol_grp1_mux = { .pad_mux_list = pw_pwm_cpu_vol_grp1_pad_mux, }; +static struct atlas7_pad_mux pw_pwm_cpu_vol_grp2_pad_mux[] = { + MUX(1, 161, 5, N, N, N, N), +}; + +static struct atlas7_grp_mux pw_pwm_cpu_vol_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp2_pad_mux), + .pad_mux_list = pw_pwm_cpu_vol_grp2_pad_mux, +}; + static struct atlas7_pad_mux pw_backlight_grp0_pad_mux[] = { MUX(1, 122, 3, N, N, N, N), }; @@ -2795,35 +3693,54 @@ static struct atlas7_grp_mux sd1_4bit_grp1_mux = { .pad_mux_list = sd1_4bit_grp1_pad_mux, }; -static struct atlas7_pad_mux sd2_grp0_pad_mux[] = { - MUX(1, 124, 2, 0xa08, 7, 0xa88, 7), +static struct atlas7_pad_mux sd2_basic_grp_pad_mux[] = { MUX(1, 31, 1, N, N, N, N), MUX(1, 32, 1, N, N, N, N), MUX(1, 33, 1, N, N, N, N), MUX(1, 34, 1, N, N, N, N), MUX(1, 35, 1, N, N, N, N), MUX(1, 36, 1, N, N, N, N), - MUX(1, 123, 2, N, N, N, N), }; -static struct atlas7_grp_mux sd2_grp0_mux = { - .pad_mux_count = ARRAY_SIZE(sd2_grp0_pad_mux), - .pad_mux_list = sd2_grp0_pad_mux, +static struct atlas7_grp_mux sd2_basic_grp_mux = { + .pad_mux_count = ARRAY_SIZE(sd2_basic_grp_pad_mux), + .pad_mux_list = sd2_basic_grp_pad_mux, }; -static struct atlas7_pad_mux sd2_no_cdb_grp0_pad_mux[] = { - MUX(1, 31, 1, N, N, N, N), - MUX(1, 32, 1, N, N, N, N), - MUX(1, 33, 1, N, N, N, N), - MUX(1, 34, 1, N, N, N, N), - MUX(1, 35, 1, N, N, N, N), - MUX(1, 36, 1, N, N, N, N), - MUX(1, 123, 2, N, N, N, N), +static struct atlas7_pad_mux sd2_cdb_grp0_pad_mux[] = { + MUX(1, 124, 2, 0xa08, 7, 0xa88, 7), }; -static struct atlas7_grp_mux sd2_no_cdb_grp0_mux = { - .pad_mux_count = ARRAY_SIZE(sd2_no_cdb_grp0_pad_mux), - .pad_mux_list = sd2_no_cdb_grp0_pad_mux, +static struct atlas7_grp_mux sd2_cdb_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp0_pad_mux), + .pad_mux_list = sd2_cdb_grp0_pad_mux, +}; + +static struct atlas7_pad_mux sd2_cdb_grp1_pad_mux[] = { + MUX(1, 161, 6, 0xa08, 7, 0xa88, 7), +}; + +static struct atlas7_grp_mux sd2_cdb_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp1_pad_mux), + .pad_mux_list = sd2_cdb_grp1_pad_mux, +}; + +static struct atlas7_pad_mux sd2_wpb_grp0_pad_mux[] = { + MUX(1, 123, 2, 0xa10, 6, 0xa90, 6), +}; + +static struct atlas7_grp_mux sd2_wpb_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp0_pad_mux), + .pad_mux_list = sd2_wpb_grp0_pad_mux, +}; + +static struct atlas7_pad_mux sd2_wpb_grp1_pad_mux[] = { + MUX(1, 163, 7, 0xa10, 6, 0xa90, 6), +}; + +static struct atlas7_grp_mux sd2_wpb_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp1_pad_mux), + .pad_mux_list = sd2_wpb_grp1_pad_mux, }; static struct atlas7_pad_mux sd3_grp_pad_mux[] = { @@ -2975,146 +3892,302 @@ static struct atlas7_grp_mux uart1_grp_mux = { .pad_mux_list = uart1_grp_pad_mux, }; -static struct atlas7_pad_mux uart2_grp_pad_mux[] = { - MUX(0, 11, 2, N, N, N, N), +static struct atlas7_pad_mux uart2_cts_grp0_pad_mux[] = { + MUX(1, 132, 3, 0xa10, 2, 0xa90, 2), +}; + +static struct atlas7_grp_mux uart2_cts_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_cts_grp0_pad_mux), + .pad_mux_list = uart2_cts_grp0_pad_mux, +}; + +static struct atlas7_pad_mux uart2_cts_grp1_pad_mux[] = { + MUX(1, 162, 2, 0xa10, 2, 0xa90, 2), +}; + +static struct atlas7_grp_mux uart2_cts_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_cts_grp1_pad_mux), + .pad_mux_list = uart2_cts_grp1_pad_mux, +}; + +static struct atlas7_pad_mux uart2_rts_grp0_pad_mux[] = { + MUX(1, 131, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux uart2_rts_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_rts_grp0_pad_mux), + .pad_mux_list = uart2_rts_grp0_pad_mux, +}; + +static struct atlas7_pad_mux uart2_rts_grp1_pad_mux[] = { + MUX(1, 161, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux uart2_rts_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_rts_grp1_pad_mux), + .pad_mux_list = uart2_rts_grp1_pad_mux, +}; + +static struct atlas7_pad_mux uart2_rxd_grp0_pad_mux[] = { + MUX(0, 11, 2, 0xa10, 5, 0xa90, 5), +}; + +static struct atlas7_grp_mux uart2_rxd_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp0_pad_mux), + .pad_mux_list = uart2_rxd_grp0_pad_mux, +}; + +static struct atlas7_pad_mux uart2_rxd_grp1_pad_mux[] = { + MUX(1, 160, 2, 0xa10, 5, 0xa90, 5), +}; + +static struct atlas7_grp_mux uart2_rxd_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp1_pad_mux), + .pad_mux_list = uart2_rxd_grp1_pad_mux, +}; + +static struct atlas7_pad_mux uart2_rxd_grp2_pad_mux[] = { + MUX(1, 130, 3, 0xa10, 5, 0xa90, 5), +}; + +static struct atlas7_grp_mux uart2_rxd_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp2_pad_mux), + .pad_mux_list = uart2_rxd_grp2_pad_mux, +}; + +static struct atlas7_pad_mux uart2_txd_grp0_pad_mux[] = { MUX(0, 10, 2, N, N, N, N), }; -static struct atlas7_grp_mux uart2_grp_mux = { - .pad_mux_count = ARRAY_SIZE(uart2_grp_pad_mux), - .pad_mux_list = uart2_grp_pad_mux, +static struct atlas7_grp_mux uart2_txd_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_txd_grp0_pad_mux), + .pad_mux_list = uart2_txd_grp0_pad_mux, +}; + +static struct atlas7_pad_mux uart2_txd_grp1_pad_mux[] = { + MUX(1, 159, 2, N, N, N, N), }; -static struct atlas7_pad_mux uart3_grp0_pad_mux[] = { +static struct atlas7_grp_mux uart2_txd_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_txd_grp1_pad_mux), + .pad_mux_list = uart2_txd_grp1_pad_mux, +}; + +static struct atlas7_pad_mux uart2_txd_grp2_pad_mux[] = { + MUX(1, 129, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux uart2_txd_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart2_txd_grp2_pad_mux), + .pad_mux_list = uart2_txd_grp2_pad_mux, +}; + +static struct atlas7_pad_mux uart3_cts_grp0_pad_mux[] = { MUX(1, 125, 2, 0xa08, 0, 0xa88, 0), - MUX(1, 126, 2, N, N, N, N), - MUX(1, 138, 1, 0xa00, 5, 0xa80, 5), - MUX(1, 137, 1, N, N, N, N), }; -static struct atlas7_grp_mux uart3_grp0_mux = { - .pad_mux_count = ARRAY_SIZE(uart3_grp0_pad_mux), - .pad_mux_list = uart3_grp0_pad_mux, +static struct atlas7_grp_mux uart3_cts_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_cts_grp0_pad_mux), + .pad_mux_list = uart3_cts_grp0_pad_mux, }; -static struct atlas7_pad_mux uart3_grp1_pad_mux[] = { +static struct atlas7_pad_mux uart3_cts_grp1_pad_mux[] = { MUX(1, 111, 4, 0xa08, 0, 0xa88, 0), - MUX(1, 109, 4, N, N, N, N), - MUX(1, 84, 2, 0xa00, 5, 0xa80, 5), - MUX(1, 83, 2, N, N, N, N), }; -static struct atlas7_grp_mux uart3_grp1_mux = { - .pad_mux_count = ARRAY_SIZE(uart3_grp1_pad_mux), - .pad_mux_list = uart3_grp1_pad_mux, +static struct atlas7_grp_mux uart3_cts_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_cts_grp1_pad_mux), + .pad_mux_list = uart3_cts_grp1_pad_mux, }; -static struct atlas7_pad_mux uart3_grp2_pad_mux[] = { +static struct atlas7_pad_mux uart3_cts_grp2_pad_mux[] = { MUX(1, 140, 2, 0xa08, 0, 0xa88, 0), +}; + +static struct atlas7_grp_mux uart3_cts_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_cts_grp2_pad_mux), + .pad_mux_list = uart3_cts_grp2_pad_mux, +}; + +static struct atlas7_pad_mux uart3_rts_grp0_pad_mux[] = { + MUX(1, 126, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_rts_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_rts_grp0_pad_mux), + .pad_mux_list = uart3_rts_grp0_pad_mux, +}; + +static struct atlas7_pad_mux uart3_rts_grp1_pad_mux[] = { + MUX(1, 109, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_rts_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_rts_grp1_pad_mux), + .pad_mux_list = uart3_rts_grp1_pad_mux, +}; + +static struct atlas7_pad_mux uart3_rts_grp2_pad_mux[] = { MUX(1, 139, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_rts_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_rts_grp2_pad_mux), + .pad_mux_list = uart3_rts_grp2_pad_mux, +}; + +static struct atlas7_pad_mux uart3_rxd_grp0_pad_mux[] = { MUX(1, 138, 1, 0xa00, 5, 0xa80, 5), - MUX(1, 137, 1, N, N, N, N), }; -static struct atlas7_grp_mux uart3_grp2_mux = { - .pad_mux_count = ARRAY_SIZE(uart3_grp2_pad_mux), - .pad_mux_list = uart3_grp2_pad_mux, +static struct atlas7_grp_mux uart3_rxd_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp0_pad_mux), + .pad_mux_list = uart3_rxd_grp0_pad_mux, }; -static struct atlas7_pad_mux uart3_grp3_pad_mux[] = { - MUX(1, 139, 2, N, N, N, N), - MUX(1, 140, 2, 0xa08, 0, 0xa88, 0), +static struct atlas7_pad_mux uart3_rxd_grp1_pad_mux[] = { MUX(1, 84, 2, 0xa00, 5, 0xa80, 5), - MUX(1, 83, 2, N, N, N, N), }; -static struct atlas7_grp_mux uart3_grp3_mux = { - .pad_mux_count = ARRAY_SIZE(uart3_grp3_pad_mux), - .pad_mux_list = uart3_grp3_pad_mux, +static struct atlas7_grp_mux uart3_rxd_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp1_pad_mux), + .pad_mux_list = uart3_rxd_grp1_pad_mux, }; -static struct atlas7_pad_mux uart3_nopause_grp0_pad_mux[] = { - MUX(1, 138, 1, 0xa00, 5, 0xa80, 5), +static struct atlas7_pad_mux uart3_rxd_grp2_pad_mux[] = { + MUX(1, 162, 3, 0xa00, 5, 0xa80, 5), +}; + +static struct atlas7_grp_mux uart3_rxd_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp2_pad_mux), + .pad_mux_list = uart3_rxd_grp2_pad_mux, +}; + +static struct atlas7_pad_mux uart3_txd_grp0_pad_mux[] = { MUX(1, 137, 1, N, N, N, N), }; -static struct atlas7_grp_mux uart3_nopause_grp0_mux = { - .pad_mux_count = ARRAY_SIZE(uart3_nopause_grp0_pad_mux), - .pad_mux_list = uart3_nopause_grp0_pad_mux, +static struct atlas7_grp_mux uart3_txd_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_txd_grp0_pad_mux), + .pad_mux_list = uart3_txd_grp0_pad_mux, }; -static struct atlas7_pad_mux uart3_nopause_grp1_pad_mux[] = { - MUX(1, 84, 2, 0xa00, 5, 0xa80, 5), +static struct atlas7_pad_mux uart3_txd_grp1_pad_mux[] = { MUX(1, 83, 2, N, N, N, N), }; -static struct atlas7_grp_mux uart3_nopause_grp1_mux = { - .pad_mux_count = ARRAY_SIZE(uart3_nopause_grp1_pad_mux), - .pad_mux_list = uart3_nopause_grp1_pad_mux, +static struct atlas7_grp_mux uart3_txd_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_txd_grp1_pad_mux), + .pad_mux_list = uart3_txd_grp1_pad_mux, }; -static struct atlas7_pad_mux uart4_grp0_pad_mux[] = { - MUX(1, 122, 4, 0xa08, 1, 0xa88, 1), - MUX(1, 123, 4, N, N, N, N), +static struct atlas7_pad_mux uart3_txd_grp2_pad_mux[] = { + MUX(1, 161, 3, N, N, N, N), +}; + +static struct atlas7_grp_mux uart3_txd_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart3_txd_grp2_pad_mux), + .pad_mux_list = uart3_txd_grp2_pad_mux, +}; + +static struct atlas7_pad_mux uart4_basic_grp_pad_mux[] = { MUX(1, 140, 1, N, N, N, N), MUX(1, 139, 1, N, N, N, N), }; -static struct atlas7_grp_mux uart4_grp0_mux = { - .pad_mux_count = ARRAY_SIZE(uart4_grp0_pad_mux), - .pad_mux_list = uart4_grp0_pad_mux, +static struct atlas7_grp_mux uart4_basic_grp_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_basic_grp_pad_mux), + .pad_mux_list = uart4_basic_grp_pad_mux, +}; + +static struct atlas7_pad_mux uart4_cts_grp0_pad_mux[] = { + MUX(1, 122, 4, 0xa08, 1, 0xa88, 1), +}; + +static struct atlas7_grp_mux uart4_cts_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_cts_grp0_pad_mux), + .pad_mux_list = uart4_cts_grp0_pad_mux, }; -static struct atlas7_pad_mux uart4_grp1_pad_mux[] = { +static struct atlas7_pad_mux uart4_cts_grp1_pad_mux[] = { MUX(1, 100, 4, 0xa08, 1, 0xa88, 1), - MUX(1, 99, 4, N, N, N, N), - MUX(1, 140, 1, N, N, N, N), - MUX(1, 139, 1, N, N, N, N), }; -static struct atlas7_grp_mux uart4_grp1_mux = { - .pad_mux_count = ARRAY_SIZE(uart4_grp1_pad_mux), - .pad_mux_list = uart4_grp1_pad_mux, +static struct atlas7_grp_mux uart4_cts_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_cts_grp1_pad_mux), + .pad_mux_list = uart4_cts_grp1_pad_mux, }; -static struct atlas7_pad_mux uart4_grp2_pad_mux[] = { +static struct atlas7_pad_mux uart4_cts_grp2_pad_mux[] = { MUX(1, 117, 2, 0xa08, 1, 0xa88, 1), - MUX(1, 116, 2, N, N, N, N), - MUX(1, 140, 1, N, N, N, N), - MUX(1, 139, 1, N, N, N, N), }; -static struct atlas7_grp_mux uart4_grp2_mux = { - .pad_mux_count = ARRAY_SIZE(uart4_grp2_pad_mux), - .pad_mux_list = uart4_grp2_pad_mux, +static struct atlas7_grp_mux uart4_cts_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_cts_grp2_pad_mux), + .pad_mux_list = uart4_cts_grp2_pad_mux, }; -static struct atlas7_pad_mux uart4_nopause_grp_pad_mux[] = { - MUX(1, 140, 1, N, N, N, N), - MUX(1, 139, 1, N, N, N, N), +static struct atlas7_pad_mux uart4_rts_grp0_pad_mux[] = { + MUX(1, 123, 4, N, N, N, N), }; -static struct atlas7_grp_mux uart4_nopause_grp_mux = { - .pad_mux_count = ARRAY_SIZE(uart4_nopause_grp_pad_mux), - .pad_mux_list = uart4_nopause_grp_pad_mux, +static struct atlas7_grp_mux uart4_rts_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_rts_grp0_pad_mux), + .pad_mux_list = uart4_rts_grp0_pad_mux, }; -static struct atlas7_pad_mux usb0_drvvbus_grp_pad_mux[] = { +static struct atlas7_pad_mux uart4_rts_grp1_pad_mux[] = { + MUX(1, 99, 4, N, N, N, N), +}; + +static struct atlas7_grp_mux uart4_rts_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_rts_grp1_pad_mux), + .pad_mux_list = uart4_rts_grp1_pad_mux, +}; + +static struct atlas7_pad_mux uart4_rts_grp2_pad_mux[] = { + MUX(1, 116, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux uart4_rts_grp2_mux = { + .pad_mux_count = ARRAY_SIZE(uart4_rts_grp2_pad_mux), + .pad_mux_list = uart4_rts_grp2_pad_mux, +}; + +static struct atlas7_pad_mux usb0_drvvbus_grp0_pad_mux[] = { MUX(1, 51, 2, N, N, N, N), }; -static struct atlas7_grp_mux usb0_drvvbus_grp_mux = { - .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp_pad_mux), - .pad_mux_list = usb0_drvvbus_grp_pad_mux, +static struct atlas7_grp_mux usb0_drvvbus_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp0_pad_mux), + .pad_mux_list = usb0_drvvbus_grp0_pad_mux, +}; + +static struct atlas7_pad_mux usb0_drvvbus_grp1_pad_mux[] = { + MUX(1, 162, 7, N, N, N, N), }; -static struct atlas7_pad_mux usb1_drvvbus_grp_pad_mux[] = { +static struct atlas7_grp_mux usb0_drvvbus_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp1_pad_mux), + .pad_mux_list = usb0_drvvbus_grp1_pad_mux, +}; + +static struct atlas7_pad_mux usb1_drvvbus_grp0_pad_mux[] = { MUX(1, 134, 2, N, N, N, N), }; -static struct atlas7_grp_mux usb1_drvvbus_grp_mux = { - .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp_pad_mux), - .pad_mux_list = usb1_drvvbus_grp_pad_mux, +static struct atlas7_grp_mux usb1_drvvbus_grp0_mux = { + .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp0_pad_mux), + .pad_mux_list = usb1_drvvbus_grp0_pad_mux, +}; + +static struct atlas7_pad_mux usb1_drvvbus_grp1_pad_mux[] = { + MUX(1, 163, 2, N, N, N, N), +}; + +static struct atlas7_grp_mux usb1_drvvbus_grp1_mux = { + .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp1_pad_mux), + .pad_mux_list = usb1_drvvbus_grp1_pad_mux, }; static struct atlas7_pad_mux visbus_dout_grp_pad_mux[] = { @@ -3252,11 +4325,20 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = { FUNCTION("sdio_i2s_gpio", sdio_i2s_gpio_grp, &sdio_i2s_gpio_grp_mux), FUNCTION("sp_rgmii_gpio", sp_rgmii_gpio_grp, &sp_rgmii_gpio_grp_mux), FUNCTION("lvds_gpio", lvds_gpio_grp, &lvds_gpio_grp_mux), - FUNCTION("uart_nand_gpio", - uart_nand_gpio_grp, - &uart_nand_gpio_grp_mux), + FUNCTION("jtag_uart_nand_gpio", + jtag_uart_nand_gpio_grp, + &jtag_uart_nand_gpio_grp_mux), FUNCTION("rtc_gpio", rtc_gpio_grp, &rtc_gpio_grp_mux), FUNCTION("audio_ac97", audio_ac97_grp, &audio_ac97_grp_mux), + FUNCTION("audio_digmic_m0", + audio_digmic_grp0, + &audio_digmic_grp0_mux), + FUNCTION("audio_digmic_m1", + audio_digmic_grp1, + &audio_digmic_grp1_mux), + FUNCTION("audio_digmic_m2", + audio_digmic_grp2, + &audio_digmic_grp2_mux), FUNCTION("audio_func_dbg", audio_func_dbg_grp, &audio_func_dbg_grp_mux), @@ -3265,16 +4347,119 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = { FUNCTION("audio_i2s_extclk", audio_i2s_extclk_grp, &audio_i2s_extclk_grp_mux), - FUNCTION("audio_uart0", audio_uart0_grp, &audio_uart0_grp_mux), - FUNCTION("audio_uart1", audio_uart1_grp, &audio_uart1_grp_mux), - FUNCTION("audio_uart2_m0", audio_uart2_grp0, &audio_uart2_grp0_mux), - FUNCTION("audio_uart2_m1", audio_uart2_grp1, &audio_uart2_grp1_mux), - FUNCTION("c_can_trnsvr", c_can_trnsvr_grp, &c_can_trnsvr_grp_mux), - FUNCTION("c0_can_m0", c0_can_grp0, &c0_can_grp0_mux), - FUNCTION("c0_can_m1", c0_can_grp1, &c0_can_grp1_mux), - FUNCTION("c1_can_m0", c1_can_grp0, &c1_can_grp0_mux), - FUNCTION("c1_can_m1", c1_can_grp1, &c1_can_grp1_mux), - FUNCTION("c1_can_m2", c1_can_grp2, &c1_can_grp2_mux), + FUNCTION("audio_spdif_out_m0", + audio_spdif_out_grp0, + &audio_spdif_out_grp0_mux), + FUNCTION("audio_spdif_out_m1", + audio_spdif_out_grp1, + &audio_spdif_out_grp1_mux), + FUNCTION("audio_spdif_out_m2", + audio_spdif_out_grp2, + &audio_spdif_out_grp2_mux), + FUNCTION("audio_uart0_basic", + audio_uart0_basic_grp, + &audio_uart0_basic_grp_mux), + FUNCTION("audio_uart0_urfs_m0", + audio_uart0_urfs_grp0, + &audio_uart0_urfs_grp0_mux), + FUNCTION("audio_uart0_urfs_m1", + audio_uart0_urfs_grp1, + &audio_uart0_urfs_grp1_mux), + FUNCTION("audio_uart0_urfs_m2", + audio_uart0_urfs_grp2, + &audio_uart0_urfs_grp2_mux), + FUNCTION("audio_uart0_urfs_m3", + audio_uart0_urfs_grp3, + &audio_uart0_urfs_grp3_mux), + FUNCTION("audio_uart1_basic", + audio_uart1_basic_grp, + &audio_uart1_basic_grp_mux), + FUNCTION("audio_uart1_urfs_m0", + audio_uart1_urfs_grp0, + &audio_uart1_urfs_grp0_mux), + FUNCTION("audio_uart1_urfs_m1", + audio_uart1_urfs_grp1, + &audio_uart1_urfs_grp1_mux), + FUNCTION("audio_uart1_urfs_m2", + audio_uart1_urfs_grp2, + &audio_uart1_urfs_grp2_mux), + FUNCTION("audio_uart2_urfs_m0", + audio_uart2_urfs_grp0, + &audio_uart2_urfs_grp0_mux), + FUNCTION("audio_uart2_urfs_m1", + audio_uart2_urfs_grp1, + &audio_uart2_urfs_grp1_mux), + FUNCTION("audio_uart2_urfs_m2", + audio_uart2_urfs_grp2, + &audio_uart2_urfs_grp2_mux), + FUNCTION("audio_uart2_urxd_m0", + audio_uart2_urxd_grp0, + &audio_uart2_urxd_grp0_mux), + FUNCTION("audio_uart2_urxd_m1", + audio_uart2_urxd_grp1, + &audio_uart2_urxd_grp1_mux), + FUNCTION("audio_uart2_urxd_m2", + audio_uart2_urxd_grp2, + &audio_uart2_urxd_grp2_mux), + FUNCTION("audio_uart2_usclk_m0", + audio_uart2_usclk_grp0, + &audio_uart2_usclk_grp0_mux), + FUNCTION("audio_uart2_usclk_m1", + audio_uart2_usclk_grp1, + &audio_uart2_usclk_grp1_mux), + FUNCTION("audio_uart2_usclk_m2", + audio_uart2_usclk_grp2, + &audio_uart2_usclk_grp2_mux), + FUNCTION("audio_uart2_utfs_m0", + audio_uart2_utfs_grp0, + &audio_uart2_utfs_grp0_mux), + FUNCTION("audio_uart2_utfs_m1", + audio_uart2_utfs_grp1, + &audio_uart2_utfs_grp1_mux), + FUNCTION("audio_uart2_utfs_m2", + audio_uart2_utfs_grp2, + &audio_uart2_utfs_grp2_mux), + FUNCTION("audio_uart2_utxd_m0", + audio_uart2_utxd_grp0, + &audio_uart2_utxd_grp0_mux), + FUNCTION("audio_uart2_utxd_m1", + audio_uart2_utxd_grp1, + &audio_uart2_utxd_grp1_mux), + FUNCTION("audio_uart2_utxd_m2", + audio_uart2_utxd_grp2, + &audio_uart2_utxd_grp2_mux), + FUNCTION("c_can_trnsvr_en_m0", + c_can_trnsvr_en_grp0, + &c_can_trnsvr_en_grp0_mux), + FUNCTION("c_can_trnsvr_en_m1", + c_can_trnsvr_en_grp1, + &c_can_trnsvr_en_grp1_mux), + FUNCTION("c_can_trnsvr_intr", + c_can_trnsvr_intr_grp, + &c_can_trnsvr_intr_grp_mux), + FUNCTION("c_can_trnsvr_stb_n", + c_can_trnsvr_stb_n_grp, + &c_can_trnsvr_stb_n_grp_mux), + FUNCTION("c0_can_rxd_trnsv0", + c0_can_rxd_trnsv0_grp, + &c0_can_rxd_trnsv0_grp_mux), + FUNCTION("c0_can_rxd_trnsv1", + c0_can_rxd_trnsv1_grp, + &c0_can_rxd_trnsv1_grp_mux), + FUNCTION("c0_can_txd_trnsv0", + c0_can_txd_trnsv0_grp, + &c0_can_txd_trnsv0_grp_mux), + FUNCTION("c0_can_txd_trnsv1", + c0_can_txd_trnsv1_grp, + &c0_can_txd_trnsv1_grp_mux), + FUNCTION("c1_can_rxd_m0", c1_can_rxd_grp0, &c1_can_rxd_grp0_mux), + FUNCTION("c1_can_rxd_m1", c1_can_rxd_grp1, &c1_can_rxd_grp1_mux), + FUNCTION("c1_can_rxd_m2", c1_can_rxd_grp2, &c1_can_rxd_grp2_mux), + FUNCTION("c1_can_rxd_m3", c1_can_rxd_grp3, &c1_can_rxd_grp3_mux), + FUNCTION("c1_can_txd_m0", c1_can_txd_grp0, &c1_can_txd_grp0_mux), + FUNCTION("c1_can_txd_m1", c1_can_txd_grp1, &c1_can_txd_grp1_mux), + FUNCTION("c1_can_txd_m2", c1_can_txd_grp2, &c1_can_txd_grp2_mux), + FUNCTION("c1_can_txd_m3", c1_can_txd_grp3, &c1_can_txd_grp3_mux), FUNCTION("ca_audio_lpc", ca_audio_lpc_grp, &ca_audio_lpc_grp_mux), FUNCTION("ca_bt_lpc", ca_bt_lpc_grp, &ca_bt_lpc_grp_mux), FUNCTION("ca_coex", ca_coex_grp, &ca_coex_grp_mux), @@ -3377,7 +4562,35 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = { &gn_trg_shutdown_grp3_mux), FUNCTION("i2c0", i2c0_grp, &i2c0_grp_mux), FUNCTION("i2c1", i2c1_grp, &i2c1_grp_mux), - FUNCTION("jtag_m0", jtag_grp0, &jtag_grp0_mux), + FUNCTION("i2s0", i2s0_grp, &i2s0_grp_mux), + FUNCTION("i2s1_basic", i2s1_basic_grp, &i2s1_basic_grp_mux), + FUNCTION("i2s1_rxd0_m0", i2s1_rxd0_grp0, &i2s1_rxd0_grp0_mux), + FUNCTION("i2s1_rxd0_m1", i2s1_rxd0_grp1, &i2s1_rxd0_grp1_mux), + FUNCTION("i2s1_rxd0_m2", i2s1_rxd0_grp2, &i2s1_rxd0_grp2_mux), + FUNCTION("i2s1_rxd0_m3", i2s1_rxd0_grp3, &i2s1_rxd0_grp3_mux), + FUNCTION("i2s1_rxd0_m4", i2s1_rxd0_grp4, &i2s1_rxd0_grp4_mux), + FUNCTION("i2s1_rxd1_m0", i2s1_rxd1_grp0, &i2s1_rxd1_grp0_mux), + FUNCTION("i2s1_rxd1_m1", i2s1_rxd1_grp1, &i2s1_rxd1_grp1_mux), + FUNCTION("i2s1_rxd1_m2", i2s1_rxd1_grp2, &i2s1_rxd1_grp2_mux), + FUNCTION("i2s1_rxd1_m3", i2s1_rxd1_grp3, &i2s1_rxd1_grp3_mux), + FUNCTION("i2s1_rxd1_m4", i2s1_rxd1_grp4, &i2s1_rxd1_grp4_mux), + FUNCTION("jtag_jt_dbg_nsrst", + jtag_jt_dbg_nsrst_grp, + &jtag_jt_dbg_nsrst_grp_mux), + FUNCTION("jtag_ntrst_m0", jtag_ntrst_grp0, &jtag_ntrst_grp0_mux), + FUNCTION("jtag_ntrst_m1", jtag_ntrst_grp1, &jtag_ntrst_grp1_mux), + FUNCTION("jtag_swdiotms_m0", + jtag_swdiotms_grp0, + &jtag_swdiotms_grp0_mux), + FUNCTION("jtag_swdiotms_m1", + jtag_swdiotms_grp1, + &jtag_swdiotms_grp1_mux), + FUNCTION("jtag_tck_m0", jtag_tck_grp0, &jtag_tck_grp0_mux), + FUNCTION("jtag_tck_m1", jtag_tck_grp1, &jtag_tck_grp1_mux), + FUNCTION("jtag_tdi_m0", jtag_tdi_grp0, &jtag_tdi_grp0_mux), + FUNCTION("jtag_tdi_m1", jtag_tdi_grp1, &jtag_tdi_grp1_mux), + FUNCTION("jtag_tdo_m0", jtag_tdo_grp0, &jtag_tdo_grp0_mux), + FUNCTION("jtag_tdo_m1", jtag_tdo_grp1, &jtag_tdo_grp1_mux), FUNCTION("ks_kas_spi_m0", ks_kas_spi_grp0, &ks_kas_spi_grp0_mux), FUNCTION("ld_ldd", ld_ldd_grp, &ld_ldd_grp_mux), FUNCTION("ld_ldd_16bit", ld_ldd_16bit_grp, &ld_ldd_16bit_grp_mux), @@ -3414,18 +4627,27 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = { FUNCTION("pw_cko0_m0", pw_cko0_grp0, &pw_cko0_grp0_mux), FUNCTION("pw_cko0_m1", pw_cko0_grp1, &pw_cko0_grp1_mux), FUNCTION("pw_cko0_m2", pw_cko0_grp2, &pw_cko0_grp2_mux), + FUNCTION("pw_cko0_m3", pw_cko0_grp3, &pw_cko0_grp3_mux), FUNCTION("pw_cko1_m0", pw_cko1_grp0, &pw_cko1_grp0_mux), FUNCTION("pw_cko1_m1", pw_cko1_grp1, &pw_cko1_grp1_mux), + FUNCTION("pw_cko1_m2", pw_cko1_grp2, &pw_cko1_grp2_mux), FUNCTION("pw_i2s01_clk_m0", pw_i2s01_clk_grp0, &pw_i2s01_clk_grp0_mux), FUNCTION("pw_i2s01_clk_m1", pw_i2s01_clk_grp1, &pw_i2s01_clk_grp1_mux), - FUNCTION("pw_pwm0", pw_pwm0_grp, &pw_pwm0_grp_mux), - FUNCTION("pw_pwm1", pw_pwm1_grp, &pw_pwm1_grp_mux), + FUNCTION("pw_i2s01_clk_m2", + pw_i2s01_clk_grp2, + &pw_i2s01_clk_grp2_mux), + FUNCTION("pw_pwm0_m0", pw_pwm0_grp0, &pw_pwm0_grp0_mux), + FUNCTION("pw_pwm0_m1", pw_pwm0_grp1, &pw_pwm0_grp1_mux), + FUNCTION("pw_pwm1_m0", pw_pwm1_grp0, &pw_pwm1_grp0_mux), + FUNCTION("pw_pwm1_m1", pw_pwm1_grp1, &pw_pwm1_grp1_mux), + FUNCTION("pw_pwm1_m2", pw_pwm1_grp2, &pw_pwm1_grp2_mux), FUNCTION("pw_pwm2_m0", pw_pwm2_grp0, &pw_pwm2_grp0_mux), FUNCTION("pw_pwm2_m1", pw_pwm2_grp1, &pw_pwm2_grp1_mux), + FUNCTION("pw_pwm2_m2", pw_pwm2_grp2, &pw_pwm2_grp2_mux), FUNCTION("pw_pwm3_m0", pw_pwm3_grp0, &pw_pwm3_grp0_mux), FUNCTION("pw_pwm3_m1", pw_pwm3_grp1, &pw_pwm3_grp1_mux), FUNCTION("pw_pwm_cpu_vol_m0", @@ -3434,6 +4656,9 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = { FUNCTION("pw_pwm_cpu_vol_m1", pw_pwm_cpu_vol_grp1, &pw_pwm_cpu_vol_grp1_mux), + FUNCTION("pw_pwm_cpu_vol_m2", + pw_pwm_cpu_vol_grp2, + &pw_pwm_cpu_vol_grp2_mux), FUNCTION("pw_backlight_m0", pw_backlight_grp0, &pw_backlight_grp0_mux), @@ -3456,8 +4681,11 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = { FUNCTION("sd1", sd1_grp, &sd1_grp_mux), FUNCTION("sd1_4bit_m0", sd1_4bit_grp0, &sd1_4bit_grp0_mux), FUNCTION("sd1_4bit_m1", sd1_4bit_grp1, &sd1_4bit_grp1_mux), - FUNCTION("sd2_m0", sd2_grp0, &sd2_grp0_mux), - FUNCTION("sd2_no_cdb_m0", sd2_no_cdb_grp0, &sd2_no_cdb_grp0_mux), + FUNCTION("sd2_basic", sd2_basic_grp, &sd2_basic_grp_mux), + FUNCTION("sd2_cdb_m0", sd2_cdb_grp0, &sd2_cdb_grp0_mux), + FUNCTION("sd2_cdb_m1", sd2_cdb_grp1, &sd2_cdb_grp1_mux), + FUNCTION("sd2_wpb_m0", sd2_wpb_grp0, &sd2_wpb_grp0_mux), + FUNCTION("sd2_wpb_m1", sd2_wpb_grp1, &sd2_wpb_grp1_mux), FUNCTION("sd3", sd3_grp, &sd3_grp_mux), FUNCTION("sd5", sd5_grp, &sd5_grp_mux), FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux), @@ -3471,23 +4699,47 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = { FUNCTION("uart0", uart0_grp, &uart0_grp_mux), FUNCTION("uart0_nopause", uart0_nopause_grp, &uart0_nopause_grp_mux), FUNCTION("uart1", uart1_grp, &uart1_grp_mux), - FUNCTION("uart2", uart2_grp, &uart2_grp_mux), - FUNCTION("uart3_m0", uart3_grp0, &uart3_grp0_mux), - FUNCTION("uart3_m1", uart3_grp1, &uart3_grp1_mux), - FUNCTION("uart3_m2", uart3_grp2, &uart3_grp2_mux), - FUNCTION("uart3_m3", uart3_grp3, &uart3_grp3_mux), - FUNCTION("uart3_nopause_m0", - uart3_nopause_grp0, - &uart3_nopause_grp0_mux), - FUNCTION("uart3_nopause_m1", - uart3_nopause_grp1, - &uart3_nopause_grp1_mux), - FUNCTION("uart4_m0", uart4_grp0, &uart4_grp0_mux), - FUNCTION("uart4_m1", uart4_grp1, &uart4_grp1_mux), - FUNCTION("uart4_m2", uart4_grp2, &uart4_grp2_mux), - FUNCTION("uart4_nopause", uart4_nopause_grp, &uart4_nopause_grp_mux), - FUNCTION("usb0_drvvbus", usb0_drvvbus_grp, &usb0_drvvbus_grp_mux), - FUNCTION("usb1_drvvbus", usb1_drvvbus_grp, &usb1_drvvbus_grp_mux), + FUNCTION("uart2_cts_m0", uart2_cts_grp0, &uart2_cts_grp0_mux), + FUNCTION("uart2_cts_m1", uart2_cts_grp1, &uart2_cts_grp1_mux), + FUNCTION("uart2_rts_m0", uart2_rts_grp0, &uart2_rts_grp0_mux), + FUNCTION("uart2_rts_m1", uart2_rts_grp1, &uart2_rts_grp1_mux), + FUNCTION("uart2_rxd_m0", uart2_rxd_grp0, &uart2_rxd_grp0_mux), + FUNCTION("uart2_rxd_m1", uart2_rxd_grp1, &uart2_rxd_grp1_mux), + FUNCTION("uart2_rxd_m2", uart2_rxd_grp2, &uart2_rxd_grp2_mux), + FUNCTION("uart2_txd_m0", uart2_txd_grp0, &uart2_txd_grp0_mux), + FUNCTION("uart2_txd_m1", uart2_txd_grp1, &uart2_txd_grp1_mux), + FUNCTION("uart2_txd_m2", uart2_txd_grp2, &uart2_txd_grp2_mux), + FUNCTION("uart3_cts_m0", uart3_cts_grp0, &uart3_cts_grp0_mux), + FUNCTION("uart3_cts_m1", uart3_cts_grp1, &uart3_cts_grp1_mux), + FUNCTION("uart3_cts_m2", uart3_cts_grp2, &uart3_cts_grp2_mux), + FUNCTION("uart3_rts_m0", uart3_rts_grp0, &uart3_rts_grp0_mux), + FUNCTION("uart3_rts_m1", uart3_rts_grp1, &uart3_rts_grp1_mux), + FUNCTION("uart3_rts_m2", uart3_rts_grp2, &uart3_rts_grp2_mux), + FUNCTION("uart3_rxd_m0", uart3_rxd_grp0, &uart3_rxd_grp0_mux), + FUNCTION("uart3_rxd_m1", uart3_rxd_grp1, &uart3_rxd_grp1_mux), + FUNCTION("uart3_rxd_m2", uart3_rxd_grp2, &uart3_rxd_grp2_mux), + FUNCTION("uart3_txd_m0", uart3_txd_grp0, &uart3_txd_grp0_mux), + FUNCTION("uart3_txd_m1", uart3_txd_grp1, &uart3_txd_grp1_mux), + FUNCTION("uart3_txd_m2", uart3_txd_grp2, &uart3_txd_grp2_mux), + FUNCTION("uart4_basic", uart4_basic_grp, &uart4_basic_grp_mux), + FUNCTION("uart4_cts_m0", uart4_cts_grp0, &uart4_cts_grp0_mux), + FUNCTION("uart4_cts_m1", uart4_cts_grp1, &uart4_cts_grp1_mux), + FUNCTION("uart4_cts_m2", uart4_cts_grp2, &uart4_cts_grp2_mux), + FUNCTION("uart4_rts_m0", uart4_rts_grp0, &uart4_rts_grp0_mux), + FUNCTION("uart4_rts_m1", uart4_rts_grp1, &uart4_rts_grp1_mux), + FUNCTION("uart4_rts_m2", uart4_rts_grp2, &uart4_rts_grp2_mux), + FUNCTION("usb0_drvvbus_m0", + usb0_drvvbus_grp0, + &usb0_drvvbus_grp0_mux), + FUNCTION("usb0_drvvbus_m1", + usb0_drvvbus_grp1, + &usb0_drvvbus_grp1_mux), + FUNCTION("usb1_drvvbus_m0", + usb1_drvvbus_grp0, + &usb1_drvvbus_grp0_mux), + FUNCTION("usb1_drvvbus_m1", + usb1_drvvbus_grp1, + &usb1_drvvbus_grp1_mux), FUNCTION("visbus_dout", visbus_dout_grp, &visbus_dout_grp_mux), FUNCTION("vi_vip1", vi_vip1_grp, &vi_vip1_grp_mux), FUNCTION("vi_vip1_ext", vi_vip1_ext_grp, &vi_vip1_ext_grp_mux), @@ -4489,7 +5741,7 @@ static struct irq_chip atlas7_gpio_irq_chip = { .irq_set_type = atlas7_gpio_irq_type, }; -static void atlas7_gpio_handle_irq(unsigned int __irq, struct irq_desc *desc) +static void atlas7_gpio_handle_irq(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc); @@ -4512,7 +5764,7 @@ static void atlas7_gpio_handle_irq(unsigned int __irq, struct irq_desc *desc) if (!status) { pr_warn("%s: gpio [%s] status %#x no interrupt is flaged\n", __func__, gc->label, status); - handle_bad_irq(irq, desc); + handle_bad_irq(desc); return; } diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index f8bd9fb52033..2a8d69725de8 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -545,7 +545,7 @@ static struct irq_chip sirfsoc_irq_chip = { .irq_set_type = sirfsoc_gpio_irq_type, }; -static void sirfsoc_gpio_handle_irq(unsigned int __irq, struct irq_desc *desc) +static void sirfsoc_gpio_handle_irq(struct irq_desc *desc) { unsigned int irq = irq_desc_get_irq(desc); struct gpio_chip *gc = irq_desc_get_handler_data(desc); @@ -570,7 +570,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int __irq, struct irq_desc *desc) printk(KERN_WARNING "%s: gpio id %d status %#x no interrupt is flagged\n", __func__, bank->id, status); - handle_bad_irq(irq, desc); + handle_bad_irq(desc); return; } diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c index ae8f29fb5536..1f0af250dbb5 100644 --- a/drivers/pinctrl/spear/pinctrl-plgpio.c +++ b/drivers/pinctrl/spear/pinctrl-plgpio.c @@ -356,7 +356,7 @@ static struct irq_chip plgpio_irqchip = { .irq_set_type = plgpio_irq_set_type, }; -static void plgpio_irq_handler(unsigned irq, struct irq_desc *desc) +static void plgpio_irq_handler(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct plgpio *plgpio = container_of(gc, struct plgpio, chip); diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index ae27872ff3a6..e68fd951129a 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -42,6 +42,10 @@ config PINCTRL_SUN8I_A33 def_bool MACH_SUN8I select PINCTRL_SUNXI_COMMON +config PINCTRL_SUN8I_A83T + def_bool MACH_SUN8I + select PINCTRL_SUNXI_COMMON + config PINCTRL_SUN8I_A23_R def_bool MACH_SUN8I depends on RESET_CONTROLLER diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 227a1213947c..e08029034510 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -12,4 +12,5 @@ obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o +obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c index 9596b0a3df6b..d4bc4f0e8be0 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c @@ -47,45 +47,57 @@ static const struct sunxi_desc_pin sun6i_a31_r_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 0), /* PL_EINT0 */ SUNXI_FUNCTION(0x3, "s_jtag")), /* MS */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 1), /* PL_EINT1 */ SUNXI_FUNCTION(0x3, "s_jtag")), /* CK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 2), /* PL_EINT2 */ SUNXI_FUNCTION(0x3, "s_jtag")), /* DO */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 3), /* PL_EINT3 */ SUNXI_FUNCTION(0x3, "s_jtag")), /* DI */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 0)), /* PM_EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 1)), /* PM_EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 2), /* PM_EINT2 */ SUNXI_FUNCTION(0x3, "1wire")), SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 3)), /* PM_EINT3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 4)), /* PM_EINT4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 5)), /* PM_EINT5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 6), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 6)), /* PM_EINT6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 7), /* PM_EINT7 */ SUNXI_FUNCTION(0x3, "rtc")), /* CLKO */ }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c new file mode 100644 index 000000000000..90b973e15982 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c @@ -0,0 +1,603 @@ +/* + * Allwinner a83t SoCs pinctrl driver. + * + * Copyright (C) 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> + * + * Based on pinctrl-sun8i-a23.c, which is: + * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org> + * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun8i_a83t_pins[] = { + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PB_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PB_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ + SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PB_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */ + SUNXI_FUNCTION(0x3, "tdm"), /* LRCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PB_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ + SUNXI_FUNCTION(0x3, "tdm"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PB_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */ + SUNXI_FUNCTION(0x3, "tdm"), /* DOUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PB_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */ + SUNXI_FUNCTION(0x3, "tdm"), /* DIN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PB_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */ + SUNXI_FUNCTION(0x3, "tdm"), /* MCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PB_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PB_EINT10 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* WE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */ + SUNXI_FUNCTION(0x3, "spi0")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RE */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand"), /* DQS */ + SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand")), /* CE2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand")), /* CE3 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXDV */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ + SUNXI_FUNCTION(0x4, "gmac")), /* RGMII-NULL / MII-CRS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */ + SUNXI_FUNCTION(0x4, "gmac")), /* GTXCK / ETXCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */ + SUNXI_FUNCTION(0x4, "gmac")), /* GTXCTL / ETXEL */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */ + SUNXI_FUNCTION(0x4, "gmac")), /* GNULL / ETXERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */ + SUNXI_FUNCTION(0x4, "gmac")), /* GCLKIN / ECOL */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */ + SUNXI_FUNCTION(0x4, "gmac")), /* GMDC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */ + SUNXI_FUNCTION(0x4, "gmac")), /* GMDIO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm")), /* PWM */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 29), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ + SUNXI_FUNCTION(0x4, "ccir")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ + SUNXI_FUNCTION(0x4, "ccir")), /* DE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ + SUNXI_FUNCTION(0x4, "ccir")), /* HSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ + SUNXI_FUNCTION(0x4, "ccir")), /* VSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D2 */ + SUNXI_FUNCTION(0x4, "ccir")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D3 */ + SUNXI_FUNCTION(0x4, "ccir")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D4 */ + SUNXI_FUNCTION(0x4, "ccir")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D5 */ + SUNXI_FUNCTION(0x4, "ccir")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D6 */ + SUNXI_FUNCTION(0x3, "uart4"), /* TX */ + SUNXI_FUNCTION(0x4, "ccir")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D7 */ + SUNXI_FUNCTION(0x3, "uart4"), /* RX */ + SUNXI_FUNCTION(0x4, "ccir")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D8 */ + SUNXI_FUNCTION(0x3, "uart4"), /* RTS */ + SUNXI_FUNCTION(0x4, "ccir")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D9 */ + SUNXI_FUNCTION(0x3, "uart4"), /* CTS */ + SUNXI_FUNCTION(0x4, "ccir")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SCK */ + SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SDA */ + SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "owa")), /* DOUT */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ + SUNXI_FUNCTION(0x3, "spi1"), /* CS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ + SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ + SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* BCLK */ + SUNXI_FUNCTION(0x3, "uart3"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* LRCK */ + SUNXI_FUNCTION(0x3, "uart3"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */ + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */ + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PH_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PH_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PH_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PH_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PH_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PH_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "hdmi"), /* HSCL */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PH_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "hdmi"), /* HSDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PH_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "hdmi"), /* HCEC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PH_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PH_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PH_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PH_EINT11 */ +}; + +static const struct sunxi_pinctrl_desc sun8i_a83t_pinctrl_data = { + .pins = sun8i_a83t_pins, + .npins = ARRAY_SIZE(sun8i_a83t_pins), + .irq_banks = 3, +}; + +static int sun8i_a83t_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun8i_a83t_pinctrl_data); +} + +static const struct of_device_id sun8i_a83t_pinctrl_match[] = { + { .compatible = "allwinner,sun8i-a83t-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, sun8i_a83t_pinctrl_match); + +static struct platform_driver sun8i_a83t_pinctrl_driver = { + .probe = sun8i_a83t_pinctrl_probe, + .driver = { + .name = "sun8i-a83t-pinctrl", + .of_match_table = sun8i_a83t_pinctrl_match, + }, +}; +module_platform_driver(sun8i_a83t_pinctrl_driver); + +MODULE_AUTHOR("Vishnu Patekar <vishnupatekar0510@gmail.com>"); +MODULE_DESCRIPTION("Allwinner a83t pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index fb4669c0ce0e..21fd638171f9 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -617,13 +617,11 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) spin_lock_irqsave(&pctl->lock, flags); if (type & IRQ_TYPE_LEVEL_MASK) - __irq_set_chip_handler_name_locked(d->irq, - &sunxi_pinctrl_level_irq_chip, - handle_fasteoi_irq, NULL); + irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip, + handle_fasteoi_irq, NULL); else - __irq_set_chip_handler_name_locked(d->irq, - &sunxi_pinctrl_edge_irq_chip, - handle_edge_irq, NULL); + irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip, + handle_edge_irq, NULL); regval = readl(pctl->membase + reg); regval &= ~(IRQ_CFG_IRQ_MASK << index); @@ -718,6 +716,7 @@ static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d, unsigned long *out_hwirq, unsigned int *out_type) { + struct sunxi_pinctrl *pctl = d->host_data; struct sunxi_desc_function *desc; int pin, base; @@ -725,10 +724,9 @@ static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d, return -EINVAL; base = PINS_PER_BANK * intspec[0]; - pin = base + intspec[1]; + pin = pctl->desc->pin_base + base + intspec[1]; - desc = sunxi_pinctrl_desc_find_function_by_pin(d->host_data, - pin, "irq"); + desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq"); if (!desc) return -EINVAL; @@ -742,7 +740,7 @@ static struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = { .xlate = sunxi_pinctrl_irq_of_xlate, }; -static void sunxi_pinctrl_irq_handler(unsigned __irq, struct irq_desc *desc) +static void sunxi_pinctrl_irq_handler(struct irq_desc *desc) { unsigned int irq = irq_desc_get_irq(desc); struct irq_chip *chip = irq_desc_get_chip(desc); @@ -1031,7 +1029,7 @@ int sunxi_pinctrl_init(struct platform_device *pdev, irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip, handle_edge_irq); irq_set_chip_data(irqno, pctl); - }; + } for (i = 0; i < pctl->desc->irq_banks; i++) { /* Mask and clear all IRQs before registering a handler */ diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c b/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c index 7beb87e8f499..a7056dccfa53 100644 --- a/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c @@ -537,6 +537,8 @@ static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned nand_cs1_pins[] = {22, 23}; static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned sd_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, 52}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned uart0_pins[] = {85, 88}; static const unsigned uart0_muxvals[] = {1, 1}; static const unsigned uart1_pins[] = {155, 156}; @@ -619,6 +621,7 @@ static const struct uniphier_pinctrl_group ph1_ld4_groups[] = { UNIPHIER_PINCTRL_GROUP(i2c3), UNIPHIER_PINCTRL_GROUP(nand), UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), UNIPHIER_PINCTRL_GROUP(uart0), UNIPHIER_PINCTRL_GROUP(uart1), UNIPHIER_PINCTRL_GROUP(uart1b), @@ -776,6 +779,7 @@ static const char * const i2c1_groups[] = {"i2c1"}; static const char * const i2c2_groups[] = {"i2c2"}; static const char * const i2c3_groups[] = {"i2c3"}; static const char * const nand_groups[] = {"nand", "nand_cs1"}; +static const char * const sd_groups[] = {"sd"}; static const char * const uart0_groups[] = {"uart0"}; static const char * const uart1_groups[] = {"uart1", "uart1b"}; static const char * const uart2_groups[] = {"uart2"}; @@ -831,6 +835,7 @@ static const struct uniphier_pinmux_function ph1_ld4_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c2), UNIPHIER_PINMUX_FUNCTION(i2c3), UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(sd), UNIPHIER_PINMUX_FUNCTION(uart0), UNIPHIER_PINMUX_FUNCTION(uart1), UNIPHIER_PINMUX_FUNCTION(uart2), diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c index 9720e697fbc1..1824831bb4da 100644 --- a/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c @@ -761,6 +761,8 @@ static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned nand_cs1_pins[] = {37, 38}; static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned uart0_pins[] = {135, 136}; static const unsigned uart0_muxvals[] = {3, 3}; static const unsigned uart0b_pins[] = {11, 12}; @@ -866,6 +868,7 @@ static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = { UNIPHIER_PINCTRL_GROUP(i2c3), UNIPHIER_PINCTRL_GROUP(nand), UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), UNIPHIER_PINCTRL_GROUP(uart0), UNIPHIER_PINCTRL_GROUP(uart0b), UNIPHIER_PINCTRL_GROUP(uart1), @@ -1136,6 +1139,7 @@ static const char * const i2c1_groups[] = {"i2c1"}; static const char * const i2c2_groups[] = {"i2c2"}; static const char * const i2c3_groups[] = {"i2c3"}; static const char * const nand_groups[] = {"nand", "nand_cs1"}; +static const char * const sd_groups[] = {"sd"}; static const char * const uart0_groups[] = {"uart0", "uart0b"}; static const char * const uart1_groups[] = {"uart1", "uart1b"}; static const char * const uart2_groups[] = {"uart2", "uart2b"}; @@ -1219,6 +1223,7 @@ static const struct uniphier_pinmux_function ph1_ld6b_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c2), UNIPHIER_PINMUX_FUNCTION(i2c3), UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(sd), UNIPHIER_PINMUX_FUNCTION(uart0), UNIPHIER_PINMUX_FUNCTION(uart1), UNIPHIER_PINMUX_FUNCTION(uart2), diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c b/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c index 96921e40da5f..ec8e92dfaf8c 100644 --- a/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c @@ -1031,6 +1031,11 @@ static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned nand_cs1_pins[] = {131, 132}; static const unsigned nand_cs1_muxvals[] = {1, 1}; +static const unsigned sd_pins[] = {150, 151, 152, 153, 154, 155, 156, 157, 158}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned sd1_pins[] = {319, 320, 321, 322, 323, 324, 325, 326, + 327}; +static const unsigned sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned uart0_pins[] = {127, 128}; static const unsigned uart0_muxvals[] = {0, 0}; static const unsigned uart1_pins[] = {129, 130}; @@ -1140,6 +1145,8 @@ static const struct uniphier_pinctrl_group ph1_pro4_groups[] = { UNIPHIER_PINCTRL_GROUP(i2c6), UNIPHIER_PINCTRL_GROUP(nand), UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(sd1), UNIPHIER_PINCTRL_GROUP(uart0), UNIPHIER_PINCTRL_GROUP(uart1), UNIPHIER_PINCTRL_GROUP(uart2), @@ -1412,6 +1419,8 @@ static const char * const i2c2_groups[] = {"i2c2"}; static const char * const i2c3_groups[] = {"i2c3"}; static const char * const i2c6_groups[] = {"i2c6"}; static const char * const nand_groups[] = {"nand", "nand_cs1"}; +static const char * const sd_groups[] = {"sd"}; +static const char * const sd1_groups[] = {"sd1"}; static const char * const uart0_groups[] = {"uart0"}; static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; @@ -1498,6 +1507,8 @@ static const struct uniphier_pinmux_function ph1_pro4_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c3), UNIPHIER_PINMUX_FUNCTION(i2c6), UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(sd), + UNIPHIER_PINMUX_FUNCTION(sd1), UNIPHIER_PINMUX_FUNCTION(uart0), UNIPHIER_PINMUX_FUNCTION(uart1), UNIPHIER_PINMUX_FUNCTION(uart2), diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c b/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c index 9af455978058..e3d648eae85a 100644 --- a/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c @@ -818,6 +818,8 @@ static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned nand_cs1_pins[] = {26, 27}; static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 258}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned uart0_pins[] = {47, 48}; static const unsigned uart0_muxvals[] = {0, 0}; static const unsigned uart0b_pins[] = {227, 228}; @@ -930,6 +932,7 @@ static const struct uniphier_pinctrl_group ph1_pro5_groups[] = { UNIPHIER_PINCTRL_GROUP(i2c5b), UNIPHIER_PINCTRL_GROUP(i2c5c), UNIPHIER_PINCTRL_GROUP(i2c6), + UNIPHIER_PINCTRL_GROUP(sd), UNIPHIER_PINCTRL_GROUP(uart0), UNIPHIER_PINCTRL_GROUP(uart0b), UNIPHIER_PINCTRL_GROUP(uart1), @@ -1209,6 +1212,7 @@ static const char * const i2c3_groups[] = {"i2c3"}; static const char * const i2c5_groups[] = {"i2c5", "i2c5b", "i2c5c"}; static const char * const i2c6_groups[] = {"i2c6"}; static const char * const nand_groups[] = {"nand", "nand_cs1"}; +static const char * const sd_groups[] = {"sd"}; static const char * const uart0_groups[] = {"uart0", "uart0b"}; static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; @@ -1296,6 +1300,7 @@ static const struct uniphier_pinmux_function ph1_pro5_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c5), UNIPHIER_PINMUX_FUNCTION(i2c6), UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(sd), UNIPHIER_PINMUX_FUNCTION(uart0), UNIPHIER_PINMUX_FUNCTION(uart1), UNIPHIER_PINMUX_FUNCTION(uart2), diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c b/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c index 7e9dae54fcb2..37bfd3f6c729 100644 --- a/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c +++ b/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c @@ -450,6 +450,8 @@ static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned nand_cs1_pins[] = {22, 23}; static const unsigned nand_cs1_muxvals[] = {0, 0}; +static const unsigned sd_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40}; +static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned uart0_pins[] = {70, 71}; static const unsigned uart0_muxvals[] = {3, 3}; static const unsigned uart1_pins[] = {114, 115}; @@ -536,6 +538,7 @@ static const struct uniphier_pinctrl_group ph1_sld8_groups[] = { UNIPHIER_PINCTRL_GROUP(i2c3), UNIPHIER_PINCTRL_GROUP(nand), UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), UNIPHIER_PINCTRL_GROUP(uart0), UNIPHIER_PINCTRL_GROUP(uart1), UNIPHIER_PINCTRL_GROUP(uart2), @@ -684,6 +687,7 @@ static const char * const i2c1_groups[] = {"i2c1"}; static const char * const i2c2_groups[] = {"i2c2"}; static const char * const i2c3_groups[] = {"i2c3"}; static const char * const nand_groups[] = {"nand", "nand_cs1"}; +static const char * const sd_groups[] = {"sd"}; static const char * const uart0_groups[] = {"uart0"}; static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; @@ -739,6 +743,7 @@ static const struct uniphier_pinmux_function ph1_sld8_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c2), UNIPHIER_PINMUX_FUNCTION(i2c3), UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(sd), UNIPHIER_PINMUX_FUNCTION(uart0), UNIPHIER_PINMUX_FUNCTION(uart1), UNIPHIER_PINMUX_FUNCTION(uart2), diff --git a/drivers/pinctrl/uniphier/pinctrl-proxstream2.c b/drivers/pinctrl/uniphier/pinctrl-proxstream2.c index 3f036e236ad9..bc00d7591c59 100644 --- a/drivers/pinctrl/uniphier/pinctrl-proxstream2.c +++ b/drivers/pinctrl/uniphier/pinctrl-proxstream2.c @@ -751,6 +751,8 @@ static const unsigned nand_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; static const unsigned nand_cs1_pins[] = {37, 38}; static const unsigned nand_cs1_muxvals[] = {8, 8}; +static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55}; +static const unsigned sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8}; static const unsigned uart0_pins[] = {217, 218}; static const unsigned uart0_muxvals[] = {8, 8}; static const unsigned uart0b_pins[] = {179, 180}; @@ -857,6 +859,7 @@ static const struct uniphier_pinctrl_group proxstream2_groups[] = { UNIPHIER_PINCTRL_GROUP(i2c6), UNIPHIER_PINCTRL_GROUP(nand), UNIPHIER_PINCTRL_GROUP(nand_cs1), + UNIPHIER_PINCTRL_GROUP(sd), UNIPHIER_PINCTRL_GROUP(uart0), UNIPHIER_PINCTRL_GROUP(uart0b), UNIPHIER_PINCTRL_GROUP(uart1), @@ -1128,6 +1131,7 @@ static const char * const i2c3_groups[] = {"i2c3"}; static const char * const i2c5_groups[] = {"i2c5"}; static const char * const i2c6_groups[] = {"i2c6"}; static const char * const nand_groups[] = {"nand", "nand_cs1"}; +static const char * const sd_groups[] = {"sd"}; static const char * const uart0_groups[] = {"uart0", "uart0b"}; static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; @@ -1213,6 +1217,7 @@ static const struct uniphier_pinmux_function proxstream2_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c5), UNIPHIER_PINMUX_FUNCTION(i2c6), UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(sd), UNIPHIER_PINMUX_FUNCTION(uart0), UNIPHIER_PINMUX_FUNCTION(uart1), UNIPHIER_PINMUX_FUNCTION(uart2), |