diff options
Diffstat (limited to 'drivers/pinctrl')
181 files changed, 16720 insertions, 1877 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 95a8e2b9a614..33db9104df17 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -49,6 +49,20 @@ config PINCTRL_AMD Requires ACPI/FDT device enumeration code to set up a platform device. +config PINCTRL_AMDISP + tristate "AMDISP GPIO pin control" + depends on DRM_AMD_ISP || COMPILE_TEST + depends on HAS_IOMEM + select GPIOLIB + select PINCONF + select GENERIC_PINCONF + help + The driver for memory mapped GPIO functionality on AMD platforms + with ISP support. All the pins are output controlled only + + Requires AMDGPU to MFD add device for enumeration to set up as + platform device. + config PINCTRL_APPLE_GPIO tristate "Apple SoC GPIO pin controller driver" depends on ARCH_APPLE @@ -89,12 +103,10 @@ config PINCTRL_AS3722 config PINCTRL_AT91 bool "AT91 pinctrl driver" - depends on OF - depends on ARCH_AT91 + depends on (OF && ARCH_AT91) || COMPILE_TEST select PINMUX select PINCONF select GPIOLIB - select OF_GPIO select GPIOLIB_IRQCHIP help Say Y here to enable the at91 pinctrl driver diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index fba1c56624c0..ac27e88677d1 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o obj-$(CONFIG_OF) += devicetree.o obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o +obj-$(CONFIG_PINCTRL_AMDISP) += pinctrl-amdisp.o obj-$(CONFIG_PINCTRL_APPLE_GPIO) += pinctrl-apple-gpio.o obj-$(CONFIG_PINCTRL_ARTPEC6) += pinctrl-artpec6.o obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o diff --git a/drivers/pinctrl/actions/pinctrl-owl.c b/drivers/pinctrl/actions/pinctrl-owl.c index d49b77dcfcff..86f3d5c69e36 100644 --- a/drivers/pinctrl/actions/pinctrl-owl.c +++ b/drivers/pinctrl/actions/pinctrl-owl.c @@ -598,7 +598,7 @@ static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset) return !!(val & BIT(offset)); } -static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +static int owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { struct owl_pinctrl *pctrl = gpiochip_get_data(chip); const struct owl_gpio_port *port; @@ -607,13 +607,15 @@ static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) port = owl_gpio_get_port(pctrl, &offset); if (WARN_ON(port == NULL)) - return; + return -ENODEV; gpio_base = pctrl->base + port->offset; raw_spin_lock_irqsave(&pctrl->lock, flags); owl_gpio_update_reg(gpio_base + port->dat, offset, value); raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; } static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) @@ -960,7 +962,7 @@ int owl_pinctrl_probe(struct platform_device *pdev, pctrl->chip.direction_input = owl_gpio_direction_input; pctrl->chip.direction_output = owl_gpio_direction_output; pctrl->chip.get = owl_gpio_get; - pctrl->chip.set = owl_gpio_set; + pctrl->chip.set_rv = owl_gpio_set; pctrl->chip.request = owl_gpio_request; pctrl->chip.free = owl_gpio_free; diff --git a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c index cf6efa9c0364..9ea20fde3a24 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c @@ -52,6 +52,12 @@ #define BCM281XX_HDMI_PIN_REG_MODE_MASK 0x0010 #define BCM281XX_HDMI_PIN_REG_MODE_SHIFT 4 +/* BCM21664 access lock registers */ +#define BCM21664_WR_ACCESS_OFFSET 0x07F0 +#define BCM21664_WR_ACCESS_PASSWORD 0xA5A501 +#define BCM21664_ACCESS_LOCK_OFFSET(lock) (0x0780 + (lock * 4)) +#define BCM21664_ACCESS_LOCK_COUNT 5 + /* * bcm281xx_pin_type - types of pin register */ @@ -72,24 +78,45 @@ static enum bcm281xx_pin_type hdmi_pin = BCM281XX_PIN_TYPE_HDMI; struct bcm281xx_pin_function { const char *name; const char * const *groups; - const unsigned ngroups; + const unsigned int ngroups; }; /* - * bcm281xx_pinctrl_data - Broadcom-specific pinctrl data - * @reg_base - base of pinctrl registers + * Device types (used in bcm281xx_pinctrl_desc to differentiate + * the two device types from each other) */ -struct bcm281xx_pinctrl_data { - void __iomem *reg_base; +enum bcm281xx_pinctrl_type { + BCM281XX_PINCTRL_TYPE, + BCM21664_PINCTRL_TYPE, +}; + +/* + * bcm281xx_pinctrl_info - description of a pinctrl device supported + * by this driver, intended to be used as a provider of OF match data. + */ +struct bcm281xx_pinctrl_info { + enum bcm281xx_pinctrl_type device_type; /* List of all pins */ const struct pinctrl_pin_desc *pins; - const unsigned npins; + unsigned int npins; const struct bcm281xx_pin_function *functions; - const unsigned nfunctions; + unsigned int nfunctions; + + const struct regmap_config *regmap_config; +}; + +/* + * bcm281xx_pinctrl_data - Broadcom-specific pinctrl data + * @reg_base - base of pinctrl registers + */ +struct bcm281xx_pinctrl_data { + struct device *dev; + void __iomem *reg_base; struct regmap *regmap; + const struct bcm281xx_pinctrl_info *info; }; /* @@ -933,22 +960,598 @@ static const struct bcm281xx_pin_function bcm281xx_functions[] = { BCM281XX_PIN_FUNCTION(alt4), }; -static struct bcm281xx_pinctrl_data bcm281xx_pinctrl = { +static const struct regmap_config bcm281xx_pinctrl_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = BCM281XX_PIN_VC_CAM3_SDA * 4, +}; + +static const struct bcm281xx_pinctrl_info bcm281xx_pinctrl = { + .device_type = BCM281XX_PINCTRL_TYPE, + .pins = bcm281xx_pinctrl_pins, .npins = ARRAY_SIZE(bcm281xx_pinctrl_pins), .functions = bcm281xx_functions, .nfunctions = ARRAY_SIZE(bcm281xx_functions), + + .regmap_config = &bcm281xx_pinctrl_regmap_config, +}; + +/* BCM21664 data */ +#define BCM21664_PIN_ADCSYN 0 +#define BCM21664_PIN_BATRM 1 +#define BCM21664_PIN_BSC1CLK 2 +#define BCM21664_PIN_BSC1DAT 3 +#define BCM21664_PIN_CAMCS0 4 +#define BCM21664_PIN_CAMCS1 5 +#define BCM21664_PIN_CLK32K 6 +#define BCM21664_PIN_CLK_CX8 7 +#define BCM21664_PIN_DCLK1 8 +#define BCM21664_PIN_DCLK4 9 +#define BCM21664_PIN_DCLKREQ1 10 +#define BCM21664_PIN_DCLKREQ4 11 +#define BCM21664_PIN_DMIC0CLK 12 +#define BCM21664_PIN_DMIC0DQ 13 +#define BCM21664_PIN_DSI0TE 14 +#define BCM21664_PIN_GPIO00 15 +#define BCM21664_PIN_GPIO01 16 +#define BCM21664_PIN_GPIO02 17 +#define BCM21664_PIN_GPIO03 18 +#define BCM21664_PIN_GPIO04 19 +#define BCM21664_PIN_GPIO05 20 +#define BCM21664_PIN_GPIO06 21 +#define BCM21664_PIN_GPIO07 22 +#define BCM21664_PIN_GPIO08 23 +#define BCM21664_PIN_GPIO09 24 +#define BCM21664_PIN_GPIO10 25 +#define BCM21664_PIN_GPIO11 26 +#define BCM21664_PIN_GPIO12 27 +#define BCM21664_PIN_GPIO13 28 +#define BCM21664_PIN_GPIO14 29 +#define BCM21664_PIN_GPIO15 30 +#define BCM21664_PIN_GPIO16 31 +#define BCM21664_PIN_GPIO17 32 +#define BCM21664_PIN_GPIO18 33 +#define BCM21664_PIN_GPIO19 34 +#define BCM21664_PIN_GPIO20 35 +#define BCM21664_PIN_GPIO21 36 +#define BCM21664_PIN_GPIO22 37 +#define BCM21664_PIN_GPIO23 38 +#define BCM21664_PIN_GPIO24 39 +#define BCM21664_PIN_GPIO25 40 +#define BCM21664_PIN_GPIO26 41 +#define BCM21664_PIN_GPIO27 42 +#define BCM21664_PIN_GPIO28 43 +#define BCM21664_PIN_GPIO32 44 +#define BCM21664_PIN_GPIO33 45 +#define BCM21664_PIN_GPIO34 46 +#define BCM21664_PIN_GPS_CALREQ 47 +#define BCM21664_PIN_GPS_HOSTREQ 48 +#define BCM21664_PIN_GPS_PABLANK 49 +#define BCM21664_PIN_GPS_TMARK 50 +#define BCM21664_PIN_ICUSBDM 51 +#define BCM21664_PIN_ICUSBDP 52 +#define BCM21664_PIN_LCDCS0 53 +#define BCM21664_PIN_LCDRES 54 +#define BCM21664_PIN_LCDSCL 55 +#define BCM21664_PIN_LCDSDA 56 +#define BCM21664_PIN_LCDTE 57 +#define BCM21664_PIN_MDMGPIO00 58 +#define BCM21664_PIN_MDMGPIO01 59 +#define BCM21664_PIN_MDMGPIO02 60 +#define BCM21664_PIN_MDMGPIO03 61 +#define BCM21664_PIN_MDMGPIO04 62 +#define BCM21664_PIN_MDMGPIO05 63 +#define BCM21664_PIN_MDMGPIO06 64 +#define BCM21664_PIN_MDMGPIO07 65 +#define BCM21664_PIN_MDMGPIO08 66 +#define BCM21664_PIN_MMC0CK 67 +#define BCM21664_PIN_MMC0CMD 68 +#define BCM21664_PIN_MMC0DAT0 69 +#define BCM21664_PIN_MMC0DAT1 70 +#define BCM21664_PIN_MMC0DAT2 71 +#define BCM21664_PIN_MMC0DAT3 72 +#define BCM21664_PIN_MMC0DAT4 73 +#define BCM21664_PIN_MMC0DAT5 74 +#define BCM21664_PIN_MMC0DAT6 75 +#define BCM21664_PIN_MMC0DAT7 76 +#define BCM21664_PIN_MMC0RST 77 +#define BCM21664_PIN_MMC1CK 78 +#define BCM21664_PIN_MMC1CMD 79 +#define BCM21664_PIN_MMC1DAT0 80 +#define BCM21664_PIN_MMC1DAT1 81 +#define BCM21664_PIN_MMC1DAT2 82 +#define BCM21664_PIN_MMC1DAT3 83 +#define BCM21664_PIN_MMC1DAT4 84 +#define BCM21664_PIN_MMC1DAT5 85 +#define BCM21664_PIN_MMC1DAT6 86 +#define BCM21664_PIN_MMC1DAT7 87 +#define BCM21664_PIN_MMC1RST 88 +#define BCM21664_PIN_PC1 89 +#define BCM21664_PIN_PC2 90 +#define BCM21664_PIN_PMBSCCLK 91 +#define BCM21664_PIN_PMBSCDAT 92 +#define BCM21664_PIN_PMUINT 93 +#define BCM21664_PIN_RESETN 94 +#define BCM21664_PIN_RFST2G_MTSLOTEN3G 95 +#define BCM21664_PIN_RTXDATA2G_TXDATA3G1 96 +#define BCM21664_PIN_RTXEN2G_TXDATA3G2 97 +#define BCM21664_PIN_RXDATA3G0 98 +#define BCM21664_PIN_RXDATA3G1 99 +#define BCM21664_PIN_RXDATA3G2 100 +#define BCM21664_PIN_SDCK 101 +#define BCM21664_PIN_SDCMD 102 +#define BCM21664_PIN_SDDAT0 103 +#define BCM21664_PIN_SDDAT1 104 +#define BCM21664_PIN_SDDAT2 105 +#define BCM21664_PIN_SDDAT3 106 +#define BCM21664_PIN_SIMCLK 107 +#define BCM21664_PIN_SIMDAT 108 +#define BCM21664_PIN_SIMDET 109 +#define BCM21664_PIN_SIMRST 110 +#define BCM21664_PIN_GPIO93 111 +#define BCM21664_PIN_GPIO94 112 +#define BCM21664_PIN_SPI0CLK 113 +#define BCM21664_PIN_SPI0FSS 114 +#define BCM21664_PIN_SPI0RXD 115 +#define BCM21664_PIN_SPI0TXD 116 +#define BCM21664_PIN_SRI_C 117 +#define BCM21664_PIN_SRI_D 118 +#define BCM21664_PIN_SRI_E 119 +#define BCM21664_PIN_SSPCK 120 +#define BCM21664_PIN_SSPDI 121 +#define BCM21664_PIN_SSPDO 122 +#define BCM21664_PIN_SSPSYN 123 +#define BCM21664_PIN_STAT1 124 +#define BCM21664_PIN_STAT2 125 +#define BCM21664_PIN_SWCLKTCK 126 +#define BCM21664_PIN_SWDIOTMS 127 +#define BCM21664_PIN_SYSCLKEN 128 +#define BCM21664_PIN_TDI 129 +#define BCM21664_PIN_TDO 130 +#define BCM21664_PIN_TESTMODE 131 +#define BCM21664_PIN_TRACECLK 132 +#define BCM21664_PIN_TRACEDT00 133 +#define BCM21664_PIN_TRACEDT01 134 +#define BCM21664_PIN_TRACEDT02 135 +#define BCM21664_PIN_TRACEDT03 136 +#define BCM21664_PIN_TRACEDT04 137 +#define BCM21664_PIN_TRACEDT05 138 +#define BCM21664_PIN_TRACEDT06 139 +#define BCM21664_PIN_TRACEDT07 140 +#define BCM21664_PIN_TRSTB 141 +#define BCM21664_PIN_TXDATA3G0 142 +#define BCM21664_PIN_UBCTSN 143 +#define BCM21664_PIN_UBRTSN 144 +#define BCM21664_PIN_UBRX 145 +#define BCM21664_PIN_UBTX 146 +#define BCM21664_PIN_TRACEDT08 147 +#define BCM21664_PIN_TRACEDT09 148 +#define BCM21664_PIN_TRACEDT10 149 +#define BCM21664_PIN_TRACEDT11 150 +#define BCM21664_PIN_TRACEDT12 151 +#define BCM21664_PIN_TRACEDT13 152 +#define BCM21664_PIN_TRACEDT14 153 +#define BCM21664_PIN_TRACEDT15 154 + +static const struct pinctrl_pin_desc bcm21664_pinctrl_pins[] = { + BCM281XX_PIN_DESC(BCM21664_PIN_ADCSYN, "adcsyn", std), + BCM281XX_PIN_DESC(BCM21664_PIN_BATRM, "batrm", std), + BCM281XX_PIN_DESC(BCM21664_PIN_BSC1CLK, "bsc1clk", i2c), + BCM281XX_PIN_DESC(BCM21664_PIN_BSC1DAT, "bsc1dat", i2c), + BCM281XX_PIN_DESC(BCM21664_PIN_CAMCS0, "camcs0", std), + BCM281XX_PIN_DESC(BCM21664_PIN_CAMCS1, "camcs1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_CLK32K, "clk32k", std), + BCM281XX_PIN_DESC(BCM21664_PIN_CLK_CX8, "clk_cx8", std), + BCM281XX_PIN_DESC(BCM21664_PIN_DCLK1, "dclk1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_DCLK4, "dclk4", std), + BCM281XX_PIN_DESC(BCM21664_PIN_DCLKREQ1, "dclkreq1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_DCLKREQ4, "dclkreq4", std), + BCM281XX_PIN_DESC(BCM21664_PIN_DMIC0CLK, "dmic0clk", std), + BCM281XX_PIN_DESC(BCM21664_PIN_DMIC0DQ, "dmic0dq", std), + BCM281XX_PIN_DESC(BCM21664_PIN_DSI0TE, "dsi0te", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO00, "gpio00", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO01, "gpio01", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO02, "gpio02", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO03, "gpio03", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO04, "gpio04", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO05, "gpio05", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO06, "gpio06", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO07, "gpio07", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO08, "gpio08", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO09, "gpio09", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO10, "gpio10", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO11, "gpio11", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO12, "gpio12", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO13, "gpio13", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO14, "gpio14", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO15, "gpio15", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO16, "gpio16", i2c), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO17, "gpio17", i2c), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO18, "gpio18", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO19, "gpio19", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO20, "gpio20", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO21, "gpio21", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO22, "gpio22", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO23, "gpio23", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO24, "gpio24", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO25, "gpio25", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO26, "gpio26", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO27, "gpio27", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO28, "gpio28", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO32, "gpio32", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO33, "gpio33", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO34, "gpio34", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPS_CALREQ, "gps_calreq", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPS_HOSTREQ, "gps_hostreq", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPS_PABLANK, "gps_pablank", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPS_TMARK, "gps_tmark", std), + BCM281XX_PIN_DESC(BCM21664_PIN_ICUSBDM, "icusbdm", std), + BCM281XX_PIN_DESC(BCM21664_PIN_ICUSBDP, "icusbdp", std), + BCM281XX_PIN_DESC(BCM21664_PIN_LCDCS0, "lcdcs0", std), + BCM281XX_PIN_DESC(BCM21664_PIN_LCDRES, "lcdres", std), + BCM281XX_PIN_DESC(BCM21664_PIN_LCDSCL, "lcdscl", std), + BCM281XX_PIN_DESC(BCM21664_PIN_LCDSDA, "lcdsda", std), + BCM281XX_PIN_DESC(BCM21664_PIN_LCDTE, "lcdte", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO00, "mdmgpio00", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO01, "mdmgpio01", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO02, "mdmgpio02", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO03, "mdmgpio03", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO04, "mdmgpio04", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO05, "mdmgpio05", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO06, "mdmgpio06", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO07, "mdmgpio07", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MDMGPIO08, "mdmgpio08", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0CK, "mmc0ck", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0CMD, "mmc0cmd", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT0, "mmc0dat0", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT1, "mmc0dat1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT2, "mmc0dat2", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT3, "mmc0dat3", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT4, "mmc0dat4", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT5, "mmc0dat5", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT6, "mmc0dat6", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0DAT7, "mmc0dat7", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC0RST, "mmc0rst", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1CK, "mmc1ck", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1CMD, "mmc1cmd", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT0, "mmc1dat0", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT1, "mmc1dat1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT2, "mmc1dat2", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT3, "mmc1dat3", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT4, "mmc1dat4", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT5, "mmc1dat5", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT6, "mmc1dat6", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1DAT7, "mmc1dat7", std), + BCM281XX_PIN_DESC(BCM21664_PIN_MMC1RST, "mmc1rst", std), + BCM281XX_PIN_DESC(BCM21664_PIN_PC1, "pc1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_PC2, "pc2", std), + BCM281XX_PIN_DESC(BCM21664_PIN_PMBSCCLK, "pmbscclk", i2c), + BCM281XX_PIN_DESC(BCM21664_PIN_PMBSCDAT, "pmbscdat", i2c), + BCM281XX_PIN_DESC(BCM21664_PIN_PMUINT, "pmuint", std), + BCM281XX_PIN_DESC(BCM21664_PIN_RESETN, "resetn", std), + BCM281XX_PIN_DESC(BCM21664_PIN_RFST2G_MTSLOTEN3G, "rfst2g_mtsloten3g", std), + BCM281XX_PIN_DESC(BCM21664_PIN_RTXDATA2G_TXDATA3G1, "rtxdata2g_txdata3g1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_RTXEN2G_TXDATA3G2, "rtxen2g_txdata3g2", std), + BCM281XX_PIN_DESC(BCM21664_PIN_RXDATA3G0, "rxdata3g0", std), + BCM281XX_PIN_DESC(BCM21664_PIN_RXDATA3G1, "rxdata3g1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_RXDATA3G2, "rxdata3g2", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SDCK, "sdck", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SDCMD, "sdcmd", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SDDAT0, "sddat0", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SDDAT1, "sddat1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SDDAT2, "sddat2", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SDDAT3, "sddat3", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SIMCLK, "simclk", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SIMDAT, "simdat", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SIMDET, "simdet", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SIMRST, "simrst", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO93, "gpio93", std), + BCM281XX_PIN_DESC(BCM21664_PIN_GPIO94, "gpio94", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SPI0CLK, "spi0clk", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SPI0FSS, "spi0fss", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SPI0RXD, "spi0rxd", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SPI0TXD, "spi0txd", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SRI_C, "sri_c", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SRI_D, "sri_d", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SRI_E, "sri_e", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SSPCK, "sspck", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SSPDI, "sspdi", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SSPDO, "sspdo", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SSPSYN, "sspsyn", std), + BCM281XX_PIN_DESC(BCM21664_PIN_STAT1, "stat1", std), + BCM281XX_PIN_DESC(BCM21664_PIN_STAT2, "stat2", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SWCLKTCK, "swclktck", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SWDIOTMS, "swdiotms", std), + BCM281XX_PIN_DESC(BCM21664_PIN_SYSCLKEN, "sysclken", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TDI, "tdi", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TDO, "tdo", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TESTMODE, "testmode", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACECLK, "traceclk", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT00, "tracedt00", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT01, "tracedt01", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT02, "tracedt02", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT03, "tracedt03", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT04, "tracedt04", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT05, "tracedt05", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT06, "tracedt06", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT07, "tracedt07", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRSTB, "trstb", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TXDATA3G0, "txdata3g0", std), + BCM281XX_PIN_DESC(BCM21664_PIN_UBCTSN, "ubctsn", std), + BCM281XX_PIN_DESC(BCM21664_PIN_UBRTSN, "ubrtsn", std), + BCM281XX_PIN_DESC(BCM21664_PIN_UBRX, "ubrx", std), + BCM281XX_PIN_DESC(BCM21664_PIN_UBTX, "ubtx", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT08, "tracedt08", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT09, "tracedt09", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT10, "tracedt10", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT11, "tracedt11", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT12, "tracedt12", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT13, "tracedt13", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT14, "tracedt14", std), + BCM281XX_PIN_DESC(BCM21664_PIN_TRACEDT15, "tracedt15", std), +}; + +static const char * const bcm21664_alt_groups[] = { + "adcsyn", + "batrm", + "bsc1clk", + "bsc1dat", + "camcs0", + "camcs1", + "clk32k", + "clk_cx8", + "dclk1", + "dclk4", + "dclkreq1", + "dclkreq4", + "dmic0clk", + "dmic0dq", + "dsi0te", + "gpio00", + "gpio01", + "gpio02", + "gpio03", + "gpio04", + "gpio05", + "gpio06", + "gpio07", + "gpio08", + "gpio09", + "gpio10", + "gpio11", + "gpio12", + "gpio13", + "gpio14", + "gpio15", + "gpio16", + "gpio17", + "gpio18", + "gpio19", + "gpio20", + "gpio21", + "gpio22", + "gpio23", + "gpio24", + "gpio25", + "gpio26", + "gpio27", + "gpio28", + "gpio32", + "gpio33", + "gpio34", + "gps_calreq", + "gps_hostreq", + "gps_pablank", + "gps_tmark", + "icusbdm", + "icusbdp", + "lcdcs0", + "lcdres", + "lcdscl", + "lcdsda", + "lcdte", + "mdmgpio00", + "mdmgpio01", + "mdmgpio02", + "mdmgpio03", + "mdmgpio04", + "mdmgpio05", + "mdmgpio06", + "mdmgpio07", + "mdmgpio08", + "mmc0ck", + "mmc0cmd", + "mmc0dat0", + "mmc0dat1", + "mmc0dat2", + "mmc0dat3", + "mmc0dat4", + "mmc0dat5", + "mmc0dat6", + "mmc0dat7", + "mmc0rst", + "mmc1ck", + "mmc1cmd", + "mmc1dat0", + "mmc1dat1", + "mmc1dat2", + "mmc1dat3", + "mmc1dat4", + "mmc1dat5", + "mmc1dat6", + "mmc1dat7", + "mmc1rst", + "pc1", + "pc2", + "pmbscclk", + "pmbscdat", + "pmuint", + "resetn", + "rfst2g_mtsloten3g", + "rtxdata2g_txdata3g1", + "rtxen2g_txdata3g2", + "rxdata3g0", + "rxdata3g1", + "rxdata3g2", + "sdck", + "sdcmd", + "sddat0", + "sddat1", + "sddat2", + "sddat3", + "simclk", + "simdat", + "simdet", + "simrst", + "gpio93", + "gpio94", + "spi0clk", + "spi0fss", + "spi0rxd", + "spi0txd", + "sri_c", + "sri_d", + "sri_e", + "sspck", + "sspdi", + "sspdo", + "sspsyn", + "stat1", + "stat2", + "swclktck", + "swdiotms", + "sysclken", + "tdi", + "tdo", + "testmode", + "traceclk", + "tracedt00", + "tracedt01", + "tracedt02", + "tracedt03", + "tracedt04", + "tracedt05", + "tracedt06", + "tracedt07", + "trstb", + "txdata3g0", + "ubctsn", + "ubrtsn", + "ubrx", + "ubtx", + "tracedt08", + "tracedt09", + "tracedt10", + "tracedt11", + "tracedt12", + "tracedt13", + "tracedt14", + "tracedt15", +}; + +#define BCM21664_PIN_FUNCTION(fcn_name) \ +{ \ + .name = #fcn_name, \ + .groups = bcm21664_alt_groups, \ + .ngroups = ARRAY_SIZE(bcm21664_alt_groups), \ +} + +static const struct bcm281xx_pin_function bcm21664_functions[] = { + BCM21664_PIN_FUNCTION(alt1), + BCM21664_PIN_FUNCTION(alt2), + BCM21664_PIN_FUNCTION(alt3), + BCM21664_PIN_FUNCTION(alt4), + BCM21664_PIN_FUNCTION(alt5), + BCM21664_PIN_FUNCTION(alt6), +}; + +static const struct regmap_config bcm21664_pinctrl_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = BCM21664_WR_ACCESS_OFFSET, }; +static const struct bcm281xx_pinctrl_info bcm21664_pinctrl = { + .device_type = BCM21664_PINCTRL_TYPE, + + .pins = bcm21664_pinctrl_pins, + .npins = ARRAY_SIZE(bcm21664_pinctrl_pins), + .functions = bcm21664_functions, + .nfunctions = ARRAY_SIZE(bcm21664_functions), + + .regmap_config = &bcm21664_pinctrl_regmap_config, +}; + +/* BCM21664 pinctrl access lock handlers */ +static int bcm21664_pinctrl_lock_all(struct bcm281xx_pinctrl_data *pdata) +{ + int i, rc; + + for (i = 0; i < BCM21664_ACCESS_LOCK_COUNT; i++) { + rc = regmap_write(pdata->regmap, BCM21664_WR_ACCESS_OFFSET, + BCM21664_WR_ACCESS_PASSWORD); + if (rc) { + dev_err(pdata->dev, "Failed to enable write access: %d\n", + rc); + return rc; + } + rc = regmap_write(pdata->regmap, BCM21664_ACCESS_LOCK_OFFSET(i), + 0xffffffff); + if (rc) { + dev_err(pdata->dev, "Failed to write access lock: %d\n", + rc); + return rc; + } + } + + return 0; +} + +static int bcm21664_pinctrl_set_pin_lock(struct bcm281xx_pinctrl_data *pdata, + unsigned int pin, bool lock) +{ + unsigned int access_lock = pin / 32; + int rc; + + dev_dbg(pdata->dev, + "%s(): %s pin %s (%d)\n", + __func__, lock ? "Lock" : "Unlock", pdata->info->pins[pin].name, + pin); + + rc = regmap_write(pdata->regmap, BCM21664_WR_ACCESS_OFFSET, + BCM21664_WR_ACCESS_PASSWORD); + if (rc) { + dev_err(pdata->dev, "Failed to enable write access: %d\n", + rc); + return rc; + } + + rc = regmap_update_bits(pdata->regmap, + BCM21664_ACCESS_LOCK_OFFSET(access_lock), + BIT(pin % 32), + (int)lock << (pin % 32)); + + if (rc) { + dev_err(pdata->dev, "Failed to %s pin: %d\n", + lock ? "lock" : "unlock", rc); + return rc; + } + + return 0; +} + static inline enum bcm281xx_pin_type pin_type_get(struct pinctrl_dev *pctldev, - unsigned pin) + unsigned int pin) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); - if (pin >= pdata->npins) + if (pin >= pdata->info->npins) return BCM281XX_PIN_TYPE_UNKNOWN; - return *(enum bcm281xx_pin_type *)(pdata->pins[pin].drv_data); + return *(enum bcm281xx_pin_type *)(pdata->info->pins[pin].drv_data); } #define BCM281XX_PIN_SHIFT(type, param) \ @@ -970,36 +1573,29 @@ static inline void bcm281xx_pin_update(u32 *reg_val, u32 *reg_mask, *reg_mask |= param_mask; } -static const struct regmap_config bcm281xx_pinctrl_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = BCM281XX_PIN_VC_CAM3_SDA * 4, -}; - static int bcm281xx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); - return pdata->npins; + return pdata->info->npins; } static const char *bcm281xx_pinctrl_get_group_name(struct pinctrl_dev *pctldev, - unsigned group) + unsigned int group) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); - return pdata->pins[group].name; + return pdata->info->pins[group].name; } static int bcm281xx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, - unsigned group, + unsigned int group, const unsigned **pins, - unsigned *num_pins) + unsigned int *num_pins) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); - *pins = &pdata->pins[group].number; + *pins = &pdata->info->pins[group].number; *num_pins = 1; return 0; @@ -1007,7 +1603,7 @@ static int bcm281xx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, static void bcm281xx_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned offset) + unsigned int offset) { seq_printf(s, " %s", dev_name(pctldev->dev)); } @@ -1025,43 +1621,53 @@ static int bcm281xx_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); - return pdata->nfunctions; + return pdata->info->nfunctions; } static const char *bcm281xx_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev, - unsigned function) + unsigned int function) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); - return pdata->functions[function].name; + return pdata->info->functions[function].name; } static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev, - unsigned function, + unsigned int function, const char * const **groups, - unsigned * const num_groups) + unsigned int * const num_groups) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); - *groups = pdata->functions[function].groups; - *num_groups = pdata->functions[function].ngroups; + *groups = pdata->info->functions[function].groups; + *num_groups = pdata->info->functions[function].ngroups; return 0; } static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev, - unsigned function, - unsigned group) + unsigned int function, + unsigned int group) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); - const struct bcm281xx_pin_function *f = &pdata->functions[function]; - u32 offset = 4 * pdata->pins[group].number; + const struct bcm281xx_pin_function *f = &pdata->info->functions[function]; + enum bcm281xx_pinctrl_type device_type = pdata->info->device_type; + unsigned int pin = pdata->info->pins[group].number; + u32 offset = 4 * pin; int rc = 0; dev_dbg(pctldev->dev, "%s(): Enable function %s (%d) of pin %s (%d) @offset 0x%x.\n", - __func__, f->name, function, pdata->pins[group].name, - pdata->pins[group].number, offset); + __func__, f->name, function, pdata->info->pins[group].name, + pin, offset); + + if (device_type == BCM21664_PINCTRL_TYPE) { + rc = bcm21664_pinctrl_set_pin_lock(pdata, pin, false); + if (rc) { + /* Error is printed in bcm21664_pinctrl_set_pin_lock */ + return rc; + } + } rc = regmap_update_bits(pdata->regmap, offset, BCM281XX_PIN_REG_F_SEL_MASK, @@ -1069,7 +1675,15 @@ static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev, if (rc) dev_err(pctldev->dev, "Error updating register for pin %s (%d).\n", - pdata->pins[group].name, pdata->pins[group].number); + pdata->info->pins[group].name, pin); + + if (device_type == BCM21664_PINCTRL_TYPE) { + rc = bcm21664_pinctrl_set_pin_lock(pdata, pin, true); + if (rc) { + /* Error is printed in bcm21664_pinctrl_set_pin_lock */ + return rc; + } + } return rc; } @@ -1082,7 +1696,7 @@ static const struct pinmux_ops bcm281xx_pinctrl_pinmux_ops = { }; static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev, - unsigned pin, + unsigned int pin, unsigned long *config) { return -ENOTSUPP; @@ -1091,9 +1705,9 @@ static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev, /* Goes through the configs and update register val/mask */ static int bcm281xx_std_pin_update(struct pinctrl_dev *pctldev, - unsigned pin, + unsigned int pin, unsigned long *configs, - unsigned num_configs, + unsigned int num_configs, u32 *val, u32 *mask) { @@ -1168,7 +1782,7 @@ static int bcm281xx_std_pin_update(struct pinctrl_dev *pctldev, "Invalid Drive Strength value (%d) for " "pin %s (%d). Valid values are " "(2..16) mA, even numbers only.\n", - arg, pdata->pins[pin].name, pin); + arg, pdata->info->pins[pin].name, pin); return -EINVAL; } bcm281xx_pin_update(val, mask, (arg/2)-1, @@ -1179,7 +1793,7 @@ static int bcm281xx_std_pin_update(struct pinctrl_dev *pctldev, default: dev_err(pctldev->dev, "Unrecognized pin config %d for pin %s (%d).\n", - param, pdata->pins[pin].name, pin); + param, pdata->info->pins[pin].name, pin); return -EINVAL; } /* switch config */ @@ -1207,9 +1821,9 @@ static const u16 bcm281xx_pullup_map[] = { /* Goes through the configs and update register val/mask */ static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev, - unsigned pin, + unsigned int pin, unsigned long *configs, - unsigned num_configs, + unsigned int num_configs, u32 *val, u32 *mask) { @@ -1233,7 +1847,7 @@ static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev, "Invalid pull-up value (%d) for pin %s " "(%d). Valid values are 568, 720, 831, " "1080, 1200, 1800, 2700 Ohms.\n", - arg, pdata->pins[pin].name, pin); + arg, pdata->info->pins[pin].name, pin); return -EINVAL; } @@ -1266,7 +1880,69 @@ static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev, default: dev_err(pctldev->dev, "Unrecognized pin config %d for pin %s (%d).\n", - param, pdata->pins[pin].name, pin); + param, pdata->info->pins[pin].name, pin); + return -EINVAL; + + } /* switch config */ + } /* for each config */ + + return 0; +} + +/* Goes through the configs and update register val/mask */ +static int bcm21664_i2c_pin_update(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *configs, + unsigned int num_configs, + u32 *val, + u32 *mask) +{ + struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + int i; + enum pin_config_param param; + u32 arg; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + /* + * BCM21664 I2C pins use the same config bits as standard pins, + * but only pull up/none, slew rate and input enable/disable + * options are supported. + */ + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + bcm281xx_pin_update(val, mask, 1, + BCM281XX_PIN_SHIFT(STD, PULL_UP), + BCM281XX_PIN_MASK(STD, PULL_UP)); + break; + + case PIN_CONFIG_BIAS_DISABLE: + bcm281xx_pin_update(val, mask, 0, + BCM281XX_PIN_SHIFT(STD, PULL_UP), + BCM281XX_PIN_MASK(STD, PULL_UP)); + break; + + case PIN_CONFIG_SLEW_RATE: + arg = (arg >= 1 ? 1 : 0); + bcm281xx_pin_update(val, mask, arg, + BCM281XX_PIN_SHIFT(STD, SLEW), + BCM281XX_PIN_MASK(STD, SLEW)); + break; + + case PIN_CONFIG_INPUT_ENABLE: + /* inversed since register is for input _disable_ */ + arg = (arg >= 1 ? 0 : 1); + bcm281xx_pin_update(val, mask, arg, + BCM281XX_PIN_SHIFT(STD, INPUT_DIS), + BCM281XX_PIN_MASK(STD, INPUT_DIS)); + break; + + default: + dev_err(pctldev->dev, + "Unrecognized pin config %d for pin %s (%d).\n", + param, pdata->info->pins[pin].name, pin); return -EINVAL; } /* switch config */ @@ -1277,9 +1953,9 @@ static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev, /* Goes through the configs and update register val/mask */ static int bcm281xx_hdmi_pin_update(struct pinctrl_dev *pctldev, - unsigned pin, + unsigned int pin, unsigned long *configs, - unsigned num_configs, + unsigned int num_configs, u32 *val, u32 *mask) { @@ -1311,7 +1987,7 @@ static int bcm281xx_hdmi_pin_update(struct pinctrl_dev *pctldev, default: dev_err(pctldev->dev, "Unrecognized pin config %d for pin %s (%d).\n", - param, pdata->pins[pin].name, pin); + param, pdata->info->pins[pin].name, pin); return -EINVAL; } /* switch config */ @@ -1321,11 +1997,12 @@ static int bcm281xx_hdmi_pin_update(struct pinctrl_dev *pctldev, } static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev, - unsigned pin, + unsigned int pin, unsigned long *configs, - unsigned num_configs) + unsigned int num_configs) { struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); + enum bcm281xx_pinctrl_type device_type = pdata->info->device_type; enum bcm281xx_pin_type pin_type; u32 offset = 4 * pin; u32 cfg_val, cfg_mask; @@ -1343,8 +2020,12 @@ static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev, break; case BCM281XX_PIN_TYPE_I2C: - rc = bcm281xx_i2c_pin_update(pctldev, pin, configs, - num_configs, &cfg_val, &cfg_mask); + if (device_type == BCM21664_PINCTRL_TYPE) + rc = bcm21664_i2c_pin_update(pctldev, pin, configs, + num_configs, &cfg_val, &cfg_mask); + else + rc = bcm281xx_i2c_pin_update(pctldev, pin, configs, + num_configs, &cfg_val, &cfg_mask); break; case BCM281XX_PIN_TYPE_HDMI: @@ -1354,7 +2035,7 @@ static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev, default: dev_err(pctldev->dev, "Unknown pin type for pin %s (%d).\n", - pdata->pins[pin].name, pin); + pdata->info->pins[pin].name, pin); return -EINVAL; } /* switch pin type */ @@ -1364,16 +2045,32 @@ static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev, dev_dbg(pctldev->dev, "%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n", - __func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask); + __func__, pdata->info->pins[pin].name, pin, cfg_val, cfg_mask); + + if (device_type == BCM21664_PINCTRL_TYPE) { + rc = bcm21664_pinctrl_set_pin_lock(pdata, pin, false); + if (rc) { + /* Error is printed in bcm21664_pinctrl_set_pin_lock */ + return rc; + } + } rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val); if (rc) { dev_err(pctldev->dev, "Error updating register for pin %s (%d).\n", - pdata->pins[pin].name, pin); + pdata->info->pins[pin].name, pin); return rc; } + if (device_type == BCM21664_PINCTRL_TYPE) { + rc = bcm21664_pinctrl_set_pin_lock(pdata, pin, true); + if (rc) { + /* Error is printed in bcm21664_pinctrl_set_pin_lock */ + return rc; + } + } + return 0; } @@ -1390,10 +2087,23 @@ static struct pinctrl_desc bcm281xx_pinctrl_desc = { .owner = THIS_MODULE, }; +static struct bcm281xx_pinctrl_data bcm281xx_pinctrl_pdata; + static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev) { - struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl; + struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl_pdata; struct pinctrl_dev *pctl; + int rc; + + /* Set device pointer in platform data */ + pdata->dev = &pdev->dev; + + /* Get the data to use from OF match */ + pdata->info = of_device_get_match_data(&pdev->dev); + if (!pdata->info) { + dev_err(&pdev->dev, "Failed to get data from OF match\n"); + return -ENODEV; + } /* So far We can assume there is only 1 bank of registers */ pdata->reg_base = devm_platform_ioremap_resource(pdev, 0); @@ -1404,15 +2114,27 @@ static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev) /* Initialize the dynamic part of pinctrl_desc */ pdata->regmap = devm_regmap_init_mmio(&pdev->dev, pdata->reg_base, - &bcm281xx_pinctrl_regmap_config); + pdata->info->regmap_config); if (IS_ERR(pdata->regmap)) { dev_err(&pdev->dev, "Regmap MMIO init failed.\n"); return -ENODEV; } bcm281xx_pinctrl_desc.name = dev_name(&pdev->dev); - bcm281xx_pinctrl_desc.pins = bcm281xx_pinctrl.pins; - bcm281xx_pinctrl_desc.npins = bcm281xx_pinctrl.npins; + bcm281xx_pinctrl_desc.pins = pdata->info->pins; + bcm281xx_pinctrl_desc.npins = pdata->info->npins; + + /* + * For BCM21664, lock all pins by default; they will be unlocked + * as needed + */ + if (pdata->info->device_type == BCM21664_PINCTRL_TYPE) { + rc = bcm21664_pinctrl_lock_all(pdata); + if (rc) { + dev_err(&pdev->dev, "Failed to lock all pins\n"); + return rc; + } + } pctl = devm_pinctrl_register(&pdev->dev, &bcm281xx_pinctrl_desc, pdata); if (IS_ERR(pctl)) { @@ -1426,7 +2148,8 @@ static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev) } static const struct of_device_id bcm281xx_pinctrl_of_match[] = { - { .compatible = "brcm,bcm11351-pinctrl", }, + { .compatible = "brcm,bcm11351-pinctrl", .data = &bcm281xx_pinctrl }, + { .compatible = "brcm,bcm21664-pinctrl", .data = &bcm21664_pinctrl }, { }, }; diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index eaeec096bc9a..826827800474 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -356,11 +356,14 @@ static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offse return GPIO_LINE_DIRECTION_IN; } -static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +static int bcm2835_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) { struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); + + return 0; } static int bcm2835_gpio_direction_output(struct gpio_chip *chip, @@ -394,7 +397,7 @@ static const struct gpio_chip bcm2835_gpio_chip = { .direction_output = bcm2835_gpio_direction_output, .get_direction = bcm2835_gpio_get_direction, .get = bcm2835_gpio_get, - .set = bcm2835_gpio_set, + .set_rv = bcm2835_gpio_set, .set_config = gpiochip_generic_config, .base = -1, .ngpio = BCM2835_NUM_GPIOS, @@ -411,7 +414,7 @@ static const struct gpio_chip bcm2711_gpio_chip = { .direction_output = bcm2835_gpio_direction_output, .get_direction = bcm2835_gpio_get_direction, .get = bcm2835_gpio_get, - .set = bcm2835_gpio_set, + .set_rv = bcm2835_gpio_set, .set_config = gpiochip_generic_config, .base = -1, .ngpio = BCM2711_NUM_GPIOS, diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c index c9a3d3aa8c10..1d08b8d4cdd7 100644 --- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c @@ -390,7 +390,7 @@ static int iproc_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio) return GPIO_LINE_DIRECTION_IN; } -static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) +static int iproc_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) { struct iproc_gpio *chip = gpiochip_get_data(gc); unsigned long flags; @@ -400,6 +400,8 @@ static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) raw_spin_unlock_irqrestore(&chip->lock, flags); dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val); + + return 0; } static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio) @@ -863,7 +865,7 @@ static int iproc_gpio_probe(struct platform_device *pdev) gc->direction_input = iproc_gpio_direction_input; gc->direction_output = iproc_gpio_direction_output; gc->get_direction = iproc_gpio_get_direction; - gc->set = iproc_gpio_set; + gc->set_rv = iproc_gpio_set; gc->get = iproc_gpio_get; chip->pinmux_is_supported = of_property_read_bool(dev->of_node, diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c index a96be8f244e0..b08f8480ddc6 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c @@ -310,7 +310,7 @@ static int nsp_gpio_get_direction(struct gpio_chip *gc, unsigned gpio) return !val; } -static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) +static int nsp_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) { struct nsp_gpio *chip = gpiochip_get_data(gc); unsigned long flags; @@ -320,6 +320,8 @@ static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) raw_spin_unlock_irqrestore(&chip->lock, flags); dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val); + + return 0; } static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio) @@ -654,7 +656,7 @@ static int nsp_gpio_probe(struct platform_device *pdev) gc->direction_input = nsp_gpio_direction_input; gc->direction_output = nsp_gpio_direction_output; gc->get_direction = nsp_gpio_get_direction; - gc->set = nsp_gpio_set; + gc->set_rv = nsp_gpio_set; gc->get = nsp_gpio_get; /* optional GPIO interrupt support */ diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c index c372a2a24be4..9dc2da8056b7 100644 --- a/drivers/pinctrl/berlin/berlin.c +++ b/drivers/pinctrl/berlin/berlin.c @@ -204,6 +204,7 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev) const struct berlin_desc_group *desc_group; const struct berlin_desc_function *desc_function; int i, max_functions = 0; + struct pinfunction *new_functions; pctrl->nfunctions = 0; @@ -229,12 +230,15 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev) } } - pctrl->functions = krealloc(pctrl->functions, + new_functions = krealloc(pctrl->functions, pctrl->nfunctions * sizeof(*pctrl->functions), GFP_KERNEL); - if (!pctrl->functions) + if (!new_functions) { + kfree(pctrl->functions); return -ENOMEM; + } + pctrl->functions = new_functions; /* map functions to theirs groups */ for (i = 0; i < pctrl->desc->ngroups; i++) { desc_group = pctrl->desc->groups + i; diff --git a/drivers/pinctrl/cirrus/pinctrl-madera-core.c b/drivers/pinctrl/cirrus/pinctrl-madera-core.c index 73ec5b9beb49..d19ef13224cc 100644 --- a/drivers/pinctrl/cirrus/pinctrl-madera-core.c +++ b/drivers/pinctrl/cirrus/pinctrl-madera-core.c @@ -1061,8 +1061,9 @@ static int madera_pin_probe(struct platform_device *pdev) /* if the configuration is provided through pdata, apply it */ if (pdata->gpio_configs) { - ret = pinctrl_register_mappings(pdata->gpio_configs, - pdata->n_gpio_configs); + ret = devm_pinctrl_register_mappings(priv->dev, + pdata->gpio_configs, + pdata->n_gpio_configs); if (ret) return dev_err_probe(priv->dev, ret, "Failed to register pdata mappings\n"); @@ -1081,17 +1082,8 @@ static int madera_pin_probe(struct platform_device *pdev) return 0; } -static void madera_pin_remove(struct platform_device *pdev) -{ - struct madera_pin_private *priv = platform_get_drvdata(pdev); - - if (priv->madera->pdata.gpio_configs) - pinctrl_unregister_mappings(priv->madera->pdata.gpio_configs); -} - static struct platform_driver madera_pin_driver = { .probe = madera_pin_probe, - .remove = madera_pin_remove, .driver = { .name = "madera-pinctrl", }, diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 4bdbf6bb26e2..9046292d1360 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -1530,6 +1530,35 @@ void pinctrl_unregister_mappings(const struct pinctrl_map *map) } EXPORT_SYMBOL_GPL(pinctrl_unregister_mappings); +static void devm_pinctrl_unregister_mappings(void *maps) +{ + pinctrl_unregister_mappings(maps); +} + +/** + * devm_pinctrl_register_mappings() - Resource managed pinctrl_register_mappings() + * @dev: device for which mappings are registered + * @maps: the pincontrol mappings table to register. Note the pinctrl-core + * keeps a reference to the passed in maps, so they should _not_ be + * marked with __initdata. + * @num_maps: the number of maps in the mapping table + * + * Returns: 0 on success, or negative errno on failure. + */ +int devm_pinctrl_register_mappings(struct device *dev, + const struct pinctrl_map *maps, + unsigned int num_maps) +{ + int ret; + + ret = pinctrl_register_mappings(maps, num_maps); + if (ret) + return ret; + + return devm_add_action_or_reset(dev, devm_pinctrl_unregister_mappings, (void *)maps); +} +EXPORT_SYMBOL_GPL(devm_pinctrl_register_mappings); + /** * pinctrl_force_sleep() - turn a given controller device into sleep state * @pctldev: pin controller device diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c index 6a94ecd6a8de..0b7f74beb6a6 100644 --- a/drivers/pinctrl/devicetree.c +++ b/drivers/pinctrl/devicetree.c @@ -143,10 +143,14 @@ static int dt_to_map_one_config(struct pinctrl *p, pctldev = get_pinctrl_dev_from_of_node(np_pctldev); if (pctldev) break; - /* Do not defer probing of hogs (circular loop) */ + /* + * Do not defer probing of hogs (circular loop) + * + * Return 1 to let the caller catch the case. + */ if (np_pctldev == p->dev->of_node) { of_node_put(np_pctldev); - return -ENODEV; + return 1; } } of_node_put(np_pctldev); @@ -265,6 +269,8 @@ int pinctrl_dt_to_map(struct pinctrl *p, struct pinctrl_dev *pctldev) ret = dt_to_map_one_config(p, pctldev, statename, np_config); of_node_put(np_config); + if (ret == 1) + continue; if (ret < 0) goto err; } diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index 4c420b21b804..8d24decd3f07 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -20,7 +20,9 @@ config PINCTRL_IMX_SCMI config PINCTRL_IMX_SCU tristate + depends on OF depends on IMX_SCU || COMPILE_TEST + default IMX_SCU select PINCTRL_IMX config PINCTRL_IMX1_CORE @@ -159,6 +161,7 @@ config PINCTRL_IMX8MM tristate "IMX8MM pinctrl driver" depends on OF depends on SOC_IMX8M || COMPILE_TEST + default SOC_IMX8M select PINCTRL_IMX help Say Y here to enable the imx8mm pinctrl driver @@ -167,6 +170,7 @@ config PINCTRL_IMX8MN tristate "IMX8MN pinctrl driver" depends on OF depends on SOC_IMX8M || COMPILE_TEST + default SOC_IMX8M select PINCTRL_IMX help Say Y here to enable the imx8mn pinctrl driver @@ -175,6 +179,7 @@ config PINCTRL_IMX8MP tristate "IMX8MP pinctrl driver" depends on OF depends on SOC_IMX8M || COMPILE_TEST + default SOC_IMX8M select PINCTRL_IMX help Say Y here to enable the imx8mp pinctrl driver @@ -183,6 +188,7 @@ config PINCTRL_IMX8MQ tristate "IMX8MQ pinctrl driver" depends on OF depends on SOC_IMX8M || COMPILE_TEST + default SOC_IMX8M select PINCTRL_IMX help Say Y here to enable the imx8mq pinctrl driver @@ -191,6 +197,7 @@ config PINCTRL_IMX8QM tristate "IMX8QM pinctrl driver" depends on OF depends on (IMX_SCU && ARCH_MXC && ARM64) || COMPILE_TEST + default ARCH_MXC select PINCTRL_IMX_SCU help Say Y here to enable the imx8qm pinctrl driver @@ -199,6 +206,7 @@ config PINCTRL_IMX8QXP tristate "IMX8QXP pinctrl driver" depends on OF depends on (IMX_SCU && ARCH_MXC && ARM64) || COMPILE_TEST + default ARCH_MXC select PINCTRL_IMX_SCU help Say Y here to enable the imx8qxp pinctrl driver @@ -207,6 +215,7 @@ config PINCTRL_IMX8DXL tristate "IMX8DXL pinctrl driver" depends on OF depends on (IMX_SCU && ARCH_MXC && ARM64) || COMPILE_TEST + default ARCH_MXC select PINCTRL_IMX_SCU help Say Y here to enable the imx8dxl pinctrl driver @@ -215,6 +224,7 @@ config PINCTRL_IMX8ULP tristate "IMX8ULP pinctrl driver" depends on OF depends on ARCH_MXC || COMPILE_TEST + default ARCH_MXC select PINCTRL_IMX help Say Y here to enable the imx8ulp pinctrl driver @@ -239,6 +249,7 @@ config PINCTRL_IMX93 tristate "IMX93 pinctrl driver" depends on OF depends on ARCH_MXC || COMPILE_TEST + default SOC_IMX9 select PINCTRL_IMX help Say Y here to enable the imx93 pinctrl driver diff --git a/drivers/pinctrl/freescale/pinctrl-imx-scmi.c b/drivers/pinctrl/freescale/pinctrl-imx-scmi.c index 8f15c4c4dc44..4e8ab919b334 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx-scmi.c +++ b/drivers/pinctrl/freescale/pinctrl-imx-scmi.c @@ -51,6 +51,7 @@ struct scmi_pinctrl_imx { #define IMX_SCMI_PIN_SIZE 24 #define IMX95_DAISY_OFF 0x408 +#define IMX94_DAISY_OFF 0x608 static int pinctrl_scmi_imx_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np, @@ -70,6 +71,8 @@ static int pinctrl_scmi_imx_dt_node_to_map(struct pinctrl_dev *pctldev, if (!daisy_off) { if (of_machine_is_compatible("fsl,imx95")) { daisy_off = IMX95_DAISY_OFF; + } else if (of_machine_is_compatible("fsl,imx94")) { + daisy_off = IMX94_DAISY_OFF; } else { dev_err(pctldev->dev, "platform not support scmi pinctrl\n"); return -EINVAL; @@ -289,6 +292,7 @@ scmi_pinctrl_imx_get_pins(struct scmi_pinctrl_imx *pmx, struct pinctrl_desc *des static const char * const scmi_pinctrl_imx_allowlist[] = { "fsl,imx95", + "fsl,imx94", NULL }; diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 842a1e6cbfc4..18de31328540 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -37,16 +37,16 @@ static inline const struct group_desc *imx_pinctrl_find_group_by_name( struct pinctrl_dev *pctldev, const char *name) { - const struct group_desc *grp = NULL; + const struct group_desc *grp; int i; for (i = 0; i < pctldev->num_groups; i++) { grp = pinctrl_generic_get_group(pctldev, i); if (grp && !strcmp(grp->grp.name, name)) - break; + return grp; } - return grp; + return NULL; } static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index 14c26c023590..248c2e558ff3 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -39,7 +39,6 @@ config PINCTRL_INTEL config PINCTRL_INTEL_PLATFORM tristate "Intel pinctrl and GPIO platform driver" - depends on ACPI select PINCTRL_INTEL help This pinctrl driver provides an interface that allows configuring @@ -141,7 +140,6 @@ config PINCTRL_METEORLAKE config PINCTRL_METEORPOINT tristate "Intel Meteor Point pinctrl and GPIO driver" - depends on ACPI select PINCTRL_INTEL help Meteor Point is the PCH of Intel Meteor Lake. This pinctrl driver diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 7340dc20349c..969137c4cb06 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -1355,6 +1355,8 @@ static void byt_gpio_irq_handler(struct irq_desc *desc) void __iomem *reg; unsigned long pending; + chained_irq_enter(chip, desc); + /* check from GPIO controller which pin triggered the interrupt */ for (base = 0; base < vg->chip.ngpio; base += 32) { reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); @@ -1369,7 +1371,8 @@ static void byt_gpio_irq_handler(struct irq_desc *desc) for_each_set_bit(pin, &pending, 32) generic_handle_domain_irq(vg->chip.irq.domain, base + pin); } - chip->irq_eoi(data); + + chained_irq_exit(chip, desc); } static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0) @@ -1557,16 +1560,14 @@ static int byt_set_soc_data(struct intel_pinctrl *vg, vg->soc = soc; vg->ncommunities = vg->soc->ncommunities; - vg->communities = devm_kcalloc(vg->dev, vg->ncommunities, - sizeof(*vg->communities), GFP_KERNEL); + vg->communities = devm_kmemdup_array(vg->dev, vg->soc->communities, vg->ncommunities, + sizeof(*vg->soc->communities), GFP_KERNEL); if (!vg->communities) return -ENOMEM; for (i = 0; i < vg->soc->ncommunities; i++) { struct intel_community *comm = vg->communities + i; - *comm = vg->soc->communities[i]; - comm->pad_regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(comm->pad_regs)) return PTR_ERR(comm->pad_regs); diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index c673e262e1db..69b18ce0f685 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1631,9 +1631,8 @@ static int chv_pinctrl_probe(struct platform_device *pdev) pctrl->soc = soc_data; pctrl->ncommunities = pctrl->soc->ncommunities; - pctrl->communities = devm_kmemdup(dev, pctrl->soc->communities, - pctrl->ncommunities * sizeof(*pctrl->communities), - GFP_KERNEL); + pctrl->communities = devm_kmemdup_array(dev, pctrl->soc->communities, pctrl->ncommunities, + sizeof(*pctrl->soc->communities), GFP_KERNEL); if (!pctrl->communities) return -ENOMEM; diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index f8b0221055e4..d889c7c878e2 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1576,8 +1576,8 @@ int intel_pinctrl_probe(struct platform_device *pdev, * to the registers. */ pctrl->ncommunities = pctrl->soc->ncommunities; - pctrl->communities = devm_kcalloc(dev, pctrl->ncommunities, - sizeof(*pctrl->communities), GFP_KERNEL); + pctrl->communities = devm_kmemdup_array(dev, pctrl->soc->communities, pctrl->ncommunities, + sizeof(*pctrl->soc->communities), GFP_KERNEL); if (!pctrl->communities) return -ENOMEM; @@ -1587,8 +1587,6 @@ int intel_pinctrl_probe(struct platform_device *pdev, u32 offset; u32 value; - *community = pctrl->soc->communities[i]; - regs = devm_platform_ioremap_resource(pdev, community->barno); if (IS_ERR(regs)) return PTR_ERR(regs); @@ -1940,3 +1938,4 @@ MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("PWM_LPSS"); diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index cc5ede17c383..ac5459a4c63e 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -549,6 +549,8 @@ static void lp_gpio_irq_handler(struct irq_desc *desc) unsigned long pending; u32 base, pin; + chained_irq_enter(chip, desc); + /* check from GPIO controller which pin triggered the interrupt */ for (base = 0; base < lg->chip.ngpio; base += 32) { reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); @@ -560,7 +562,8 @@ static void lp_gpio_irq_handler(struct irq_desc *desc) for_each_set_bit(pin, &pending, 32) generic_handle_domain_irq(lg->chip.irq.domain, base + pin); } - chip->irq_eoi(data); + + chained_irq_exit(chip, desc); } static void lp_irq_ack(struct irq_data *d) diff --git a/drivers/pinctrl/intel/pinctrl-tangier.c b/drivers/pinctrl/intel/pinctrl-tangier.c index d3baf0f4eea0..ac61e632b487 100644 --- a/drivers/pinctrl/intel/pinctrl-tangier.c +++ b/drivers/pinctrl/intel/pinctrl-tangier.c @@ -524,7 +524,6 @@ static int tng_pinctrl_probe(struct platform_device *pdev, struct device *dev = &pdev->dev; struct tng_family *families; struct tng_pinctrl *tp; - size_t families_len; void __iomem *regs; unsigned int i; @@ -543,8 +542,8 @@ static int tng_pinctrl_probe(struct platform_device *pdev, * Make a copy of the families which we can use to hold pointers * to the registers. */ - families_len = size_mul(sizeof(*families), tp->nfamilies); - families = devm_kmemdup(dev, tp->families, families_len, GFP_KERNEL); + families = devm_kmemdup_array(dev, tp->families, tp->nfamilies, + sizeof(*tp->families), GFP_KERNEL); if (!families) return -ENOMEM; diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 58f32818a0e6..2d15af6be276 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -181,6 +181,16 @@ config PINCTRL_MT6797 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS +config PINCTRL_MT6893 + bool "MediaTek Dimensity MT6893 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_PARIS + help + Say yes here to support pin controller and gpio driver + on the MediaTek Dimensity 1200 MT6893 Smartphone SoC. + config PINCTRL_MT7622 bool "MediaTek MT7622 pin control" depends on OF @@ -263,6 +273,18 @@ config PINCTRL_MT8195 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS +config PINCTRL_MT8196 + bool "MediaTek MT8196 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_PARIS + help + Say yes here to support pin controller and gpio driver + on MediaTek MT8196 SoC. + In MTK platform, we support virtual gpio and use it to + map specific eint which doesn't have real gpio pin. + config PINCTRL_MT8365 bool "MediaTek MT8365 pin control" depends on OF diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 721ae83476d0..7518980fba59 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o obj-$(CONFIG_PINCTRL_MT6795) += pinctrl-mt6795.o obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o +obj-$(CONFIG_PINCTRL_MT6893) += pinctrl-mt6893.o obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o @@ -36,6 +37,7 @@ obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o obj-$(CONFIG_PINCTRL_MT8188) += pinctrl-mt8188.o obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o +obj-$(CONFIG_PINCTRL_MT8196) += pinctrl-mt8196.o obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c index 27f0a54e12bf..d906a5e4101f 100644 --- a/drivers/pinctrl/mediatek/mtk-eint.c +++ b/drivers/pinctrl/mediatek/mtk-eint.c @@ -1,11 +1,13 @@ // SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2014-2018 MediaTek Inc. +// Copyright (c) 2014-2025 MediaTek Inc. /* * Library for MediaTek External Interrupt Support * * Author: Maoguang Meng <maoguang.meng@mediatek.com> * Sean Wang <sean.wang@mediatek.com> + * Hao Chang <ot_chhao.chang@mediatek.com> + * Qingliang Li <qingliang.li@mediatek.com> * */ @@ -68,13 +70,11 @@ static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint, unsigned int eint_num, unsigned int offset) { - unsigned int eint_base = 0; + unsigned int idx = eint->pins[eint_num].index; + unsigned int inst = eint->pins[eint_num].instance; void __iomem *reg; - if (eint_num >= eint->hw->ap_num) - eint_base = eint->hw->ap_num; - - reg = eint->base + offset + ((eint_num - eint_base) / 32) * 4; + reg = eint->base[inst] + offset + (idx / 32 * 4); return reg; } @@ -83,7 +83,7 @@ static unsigned int mtk_eint_can_en_debounce(struct mtk_eint *eint, unsigned int eint_num) { unsigned int sens; - unsigned int bit = BIT(eint_num % 32); + unsigned int bit = BIT(eint->pins[eint_num].index % 32); void __iomem *reg = mtk_eint_get_offset(eint, eint_num, eint->regs->sens); @@ -92,7 +92,7 @@ static unsigned int mtk_eint_can_en_debounce(struct mtk_eint *eint, else sens = MTK_EINT_EDGE_SENSITIVE; - if (eint_num < eint->hw->db_cnt && sens != MTK_EINT_EDGE_SENSITIVE) + if (eint->pins[eint_num].debounce && sens != MTK_EINT_EDGE_SENSITIVE) return 1; else return 0; @@ -102,9 +102,9 @@ static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq) { int start_level, curr_level; unsigned int reg_offset; - u32 mask = BIT(hwirq & 0x1f); - u32 port = (hwirq >> 5) & eint->hw->port_mask; - void __iomem *reg = eint->base + (port << 2); + unsigned int mask = BIT(eint->pins[hwirq].index & 0x1f); + unsigned int port = (eint->pins[hwirq].index >> 5) & eint->hw->port_mask; + void __iomem *reg = eint->base[eint->pins[hwirq].instance] + (port << 2); curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq); @@ -126,11 +126,13 @@ static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq) static void mtk_eint_mask(struct irq_data *d) { struct mtk_eint *eint = irq_data_get_irq_chip_data(d); - u32 mask = BIT(d->hwirq & 0x1f); + unsigned int idx = eint->pins[d->hwirq].index; + unsigned int inst = eint->pins[d->hwirq].instance; + unsigned int mask = BIT(idx & 0x1f); void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->mask_set); - eint->cur_mask[d->hwirq >> 5] &= ~mask; + eint->cur_mask[inst][idx >> 5] &= ~mask; writel(mask, reg); } @@ -138,22 +140,24 @@ static void mtk_eint_mask(struct irq_data *d) static void mtk_eint_unmask(struct irq_data *d) { struct mtk_eint *eint = irq_data_get_irq_chip_data(d); - u32 mask = BIT(d->hwirq & 0x1f); + unsigned int idx = eint->pins[d->hwirq].index; + unsigned int inst = eint->pins[d->hwirq].instance; + unsigned int mask = BIT(idx & 0x1f); void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->mask_clr); - eint->cur_mask[d->hwirq >> 5] |= mask; + eint->cur_mask[inst][idx >> 5] |= mask; writel(mask, reg); - if (eint->dual_edge[d->hwirq]) + if (eint->pins[d->hwirq].dual_edge) mtk_eint_flip_edge(eint, d->hwirq); } static unsigned int mtk_eint_get_mask(struct mtk_eint *eint, unsigned int eint_num) { - unsigned int bit = BIT(eint_num % 32); + unsigned int bit = BIT(eint->pins[eint_num].index % 32); void __iomem *reg = mtk_eint_get_offset(eint, eint_num, eint->regs->mask); @@ -163,7 +167,7 @@ static unsigned int mtk_eint_get_mask(struct mtk_eint *eint, static void mtk_eint_ack(struct irq_data *d) { struct mtk_eint *eint = irq_data_get_irq_chip_data(d); - u32 mask = BIT(d->hwirq & 0x1f); + unsigned int mask = BIT(eint->pins[d->hwirq].index & 0x1f); void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->ack); @@ -174,7 +178,7 @@ static int mtk_eint_set_type(struct irq_data *d, unsigned int type) { struct mtk_eint *eint = irq_data_get_irq_chip_data(d); bool masked; - u32 mask = BIT(d->hwirq & 0x1f); + unsigned int mask = BIT(eint->pins[d->hwirq].index & 0x1f); void __iomem *reg; if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) || @@ -186,9 +190,9 @@ static int mtk_eint_set_type(struct irq_data *d, unsigned int type) } if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) - eint->dual_edge[d->hwirq] = 1; + eint->pins[d->hwirq].dual_edge = 1; else - eint->dual_edge[d->hwirq] = 0; + eint->pins[d->hwirq].dual_edge = 0; if (!mtk_eint_get_mask(eint, d->hwirq)) { mtk_eint_mask(d); @@ -223,27 +227,32 @@ static int mtk_eint_set_type(struct irq_data *d, unsigned int type) static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on) { struct mtk_eint *eint = irq_data_get_irq_chip_data(d); - int shift = d->hwirq & 0x1f; - int reg = d->hwirq >> 5; + unsigned int idx = eint->pins[d->hwirq].index; + unsigned int inst = eint->pins[d->hwirq].instance; + unsigned int shift = idx & 0x1f; + unsigned int port = idx >> 5; if (on) - eint->wake_mask[reg] |= BIT(shift); + eint->wake_mask[inst][port] |= BIT(shift); else - eint->wake_mask[reg] &= ~BIT(shift); + eint->wake_mask[inst][port] &= ~BIT(shift); return 0; } static void mtk_eint_chip_write_mask(const struct mtk_eint *eint, - void __iomem *base, u32 *buf) + void __iomem *base, unsigned int **buf) { - int port; + int inst, port, port_num; void __iomem *reg; - for (port = 0; port < eint->hw->ports; port++) { - reg = base + (port << 2); - writel_relaxed(~buf[port], reg + eint->regs->mask_set); - writel_relaxed(buf[port], reg + eint->regs->mask_clr); + for (inst = 0; inst < eint->nbase; inst++) { + port_num = DIV_ROUND_UP(eint->base_pin_num[inst], 32); + for (port = 0; port < port_num; port++) { + reg = eint->base[inst] + (port << 2); + writel_relaxed(~buf[inst][port], reg + eint->regs->mask_set); + writel_relaxed(buf[inst][port], reg + eint->regs->mask_clr); + } } } @@ -303,15 +312,18 @@ static struct irq_chip mtk_eint_irq_chip = { static unsigned int mtk_eint_hw_init(struct mtk_eint *eint) { - void __iomem *dom_en = eint->base + eint->regs->dom_en; - void __iomem *mask_set = eint->base + eint->regs->mask_set; - unsigned int i; - - for (i = 0; i < eint->hw->ap_num; i += 32) { - writel(0xffffffff, dom_en); - writel(0xffffffff, mask_set); - dom_en += 4; - mask_set += 4; + void __iomem *dom_reg, *mask_reg; + unsigned int i, j; + + for (i = 0; i < eint->nbase; i++) { + dom_reg = eint->base[i] + eint->regs->dom_en; + mask_reg = eint->base[i] + eint->regs->mask_set; + for (j = 0; j < eint->base_pin_num[i]; j += 32) { + writel(0xffffffff, dom_reg); + writel(0xffffffff, mask_reg); + dom_reg += 4; + mask_reg += 4; + } } return 0; @@ -322,14 +334,16 @@ mtk_eint_debounce_process(struct mtk_eint *eint, int index) { unsigned int rst, ctrl_offset; unsigned int bit, dbnc; + unsigned int inst = eint->pins[index].instance; + unsigned int idx = eint->pins[index].index; - ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_ctrl; - dbnc = readl(eint->base + ctrl_offset); - bit = MTK_EINT_DBNC_SET_EN << ((index % 4) * 8); + ctrl_offset = (idx / 4) * 4 + eint->regs->dbnc_ctrl; + dbnc = readl(eint->base[inst] + ctrl_offset); + bit = MTK_EINT_DBNC_SET_EN << ((idx % 4) * 8); if ((bit & dbnc) > 0) { - ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_set; - rst = MTK_EINT_DBNC_RST_BIT << ((index % 4) * 8); - writel(rst, eint->base + ctrl_offset); + ctrl_offset = (idx / 4) * 4 + eint->regs->dbnc_set; + rst = MTK_EINT_DBNC_RST_BIT << ((idx % 4) * 8); + writel(rst, eint->base[inst] + ctrl_offset); } } @@ -337,65 +351,68 @@ static void mtk_eint_irq_handler(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); struct mtk_eint *eint = irq_desc_get_handler_data(desc); - unsigned int status, eint_num; - int offset, mask_offset, index; - void __iomem *reg = mtk_eint_get_offset(eint, 0, eint->regs->stat); + unsigned int i, j, port, status, shift, mask, eint_num; + void __iomem *reg; int dual_edge, start_level, curr_level; chained_irq_enter(chip, desc); - for (eint_num = 0; eint_num < eint->hw->ap_num; eint_num += 32, - reg += 4) { - status = readl(reg); - while (status) { - offset = __ffs(status); - mask_offset = eint_num >> 5; - index = eint_num + offset; - status &= ~BIT(offset); - - /* - * If we get an interrupt on pin that was only required - * for wake (but no real interrupt requested), mask the - * interrupt (as would mtk_eint_resume do anyway later - * in the resume sequence). - */ - if (eint->wake_mask[mask_offset] & BIT(offset) && - !(eint->cur_mask[mask_offset] & BIT(offset))) { - writel_relaxed(BIT(offset), reg - - eint->regs->stat + - eint->regs->mask_set); - } + for (i = 0; i < eint->nbase; i++) { + for (j = 0; j < eint->base_pin_num[i]; j += 32) { + port = j >> 5; + status = readl(eint->base[i] + port * 4 + eint->regs->stat); + while (status) { + shift = __ffs(status); + status &= ~BIT(shift); + mask = BIT(shift); + eint_num = eint->pin_list[i][shift + j]; - dual_edge = eint->dual_edge[index]; - if (dual_edge) { /* - * Clear soft-irq in case we raised it last - * time. + * If we get an interrupt on pin that was only required + * for wake (but no real interrupt requested), mask the + * interrupt (as would mtk_eint_resume do anyway later + * in the resume sequence). */ - writel(BIT(offset), reg - eint->regs->stat + - eint->regs->soft_clr); - - start_level = - eint->gpio_xlate->get_gpio_state(eint->pctl, - index); + if (eint->wake_mask[i][port] & mask && + !(eint->cur_mask[i][port] & mask)) { + reg = mtk_eint_get_offset(eint, eint_num, + eint->regs->mask_set); + writel_relaxed(mask, reg); + } + + dual_edge = eint->pins[eint_num].dual_edge; + if (dual_edge) { + /* + * Clear soft-irq in case we raised it last + * time. + */ + reg = mtk_eint_get_offset(eint, eint_num, + eint->regs->soft_clr); + writel(mask, reg); + + start_level = + eint->gpio_xlate->get_gpio_state(eint->pctl, + eint_num); + } + + generic_handle_domain_irq(eint->domain, eint_num); + + if (dual_edge) { + curr_level = mtk_eint_flip_edge(eint, eint_num); + + /* + * If level changed, we might lost one edge + * interrupt, raised it through soft-irq. + */ + if (start_level != curr_level) { + reg = mtk_eint_get_offset(eint, eint_num, + eint->regs->soft_set); + writel(mask, reg); + } + } + + if (eint->pins[eint_num].debounce) + mtk_eint_debounce_process(eint, eint_num); } - - generic_handle_domain_irq(eint->domain, index); - - if (dual_edge) { - curr_level = mtk_eint_flip_edge(eint, index); - - /* - * If level changed, we might lost one edge - * interrupt, raised it through soft-irq. - */ - if (start_level != curr_level) - writel(BIT(offset), reg - - eint->regs->stat + - eint->regs->soft_set); - } - - if (index < eint->hw->db_cnt) - mtk_eint_debounce_process(eint, index); } } chained_irq_exit(chip, desc); @@ -423,17 +440,19 @@ int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num, int virq, eint_offset; unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc; + unsigned int inst = eint->pins[eint_num].instance; + unsigned int idx = eint->pins[eint_num].index; struct irq_data *d; if (!eint->hw->db_time) return -EOPNOTSUPP; virq = irq_find_mapping(eint->domain, eint_num); - eint_offset = (eint_num % 4) * 8; + eint_offset = (idx % 4) * 8; d = irq_get_irq_data(virq); - set_offset = (eint_num / 4) * 4 + eint->regs->dbnc_set; - clr_offset = (eint_num / 4) * 4 + eint->regs->dbnc_clr; + set_offset = (idx / 4) * 4 + eint->regs->dbnc_set; + clr_offset = (idx / 4) * 4 + eint->regs->dbnc_clr; if (!mtk_eint_can_en_debounce(eint, eint_num)) return -EINVAL; @@ -454,12 +473,12 @@ int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num, } clr_bit = 0xff << eint_offset; - writel(clr_bit, eint->base + clr_offset); + writel(clr_bit, eint->base[inst] + clr_offset); bit = ((dbnc << MTK_EINT_DBNC_SET_DBNC_BITS) | MTK_EINT_DBNC_SET_EN) << eint_offset; rst = MTK_EINT_DBNC_RST_BIT << eint_offset; - writel(rst | bit, eint->base + set_offset); + writel(rst | bit, eint->base[inst] + set_offset); /* * Delay a while (more than 2T) to wait for hw debounce counter reset @@ -485,34 +504,67 @@ int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n) } EXPORT_SYMBOL_GPL(mtk_eint_find_irq); -int mtk_eint_do_init(struct mtk_eint *eint) +int mtk_eint_do_init(struct mtk_eint *eint, struct mtk_eint_pin *eint_pin) { - int i; + unsigned int size, i, port, virq, inst = 0; /* If clients don't assign a specific regs, let's use generic one */ if (!eint->regs) eint->regs = &mtk_generic_eint_regs; - eint->wake_mask = devm_kcalloc(eint->dev, eint->hw->ports, - sizeof(*eint->wake_mask), GFP_KERNEL); - if (!eint->wake_mask) + eint->base_pin_num = devm_kmalloc_array(eint->dev, eint->nbase, sizeof(u16), + GFP_KERNEL | __GFP_ZERO); + if (!eint->base_pin_num) return -ENOMEM; - eint->cur_mask = devm_kcalloc(eint->dev, eint->hw->ports, - sizeof(*eint->cur_mask), GFP_KERNEL); - if (!eint->cur_mask) - return -ENOMEM; + if (eint_pin) { + eint->pins = eint_pin; + for (i = 0; i < eint->hw->ap_num; i++) { + inst = eint->pins[i].instance; + if (inst >= eint->nbase) + continue; + eint->base_pin_num[inst]++; + } + } else { + size = eint->hw->ap_num * sizeof(struct mtk_eint_pin); + eint->pins = devm_kmalloc(eint->dev, size, GFP_KERNEL); + if (!eint->pins) + goto err_pins; + + eint->base_pin_num[inst] = eint->hw->ap_num; + for (i = 0; i < eint->hw->ap_num; i++) { + eint->pins[i].instance = inst; + eint->pins[i].index = i; + eint->pins[i].debounce = (i < eint->hw->db_cnt) ? 1 : 0; + } + } - eint->dual_edge = devm_kcalloc(eint->dev, eint->hw->ap_num, - sizeof(int), GFP_KERNEL); - if (!eint->dual_edge) - return -ENOMEM; + eint->pin_list = devm_kmalloc(eint->dev, eint->nbase * sizeof(u16 *), GFP_KERNEL); + if (!eint->pin_list) + goto err_pin_list; + + eint->wake_mask = devm_kmalloc(eint->dev, eint->nbase * sizeof(u32 *), GFP_KERNEL); + if (!eint->wake_mask) + goto err_wake_mask; - eint->domain = irq_domain_add_linear(eint->dev->of_node, - eint->hw->ap_num, - &irq_domain_simple_ops, NULL); + eint->cur_mask = devm_kmalloc(eint->dev, eint->nbase * sizeof(u32 *), GFP_KERNEL); + if (!eint->cur_mask) + goto err_cur_mask; + + for (i = 0; i < eint->nbase; i++) { + eint->pin_list[i] = devm_kzalloc(eint->dev, eint->base_pin_num[i] * sizeof(u16), + GFP_KERNEL); + port = DIV_ROUND_UP(eint->base_pin_num[i], 32); + eint->wake_mask[i] = devm_kzalloc(eint->dev, port * sizeof(u32), GFP_KERNEL); + eint->cur_mask[i] = devm_kzalloc(eint->dev, port * sizeof(u32), GFP_KERNEL); + if (!eint->pin_list[i] || !eint->wake_mask[i] || !eint->cur_mask[i]) + goto err_eint; + } + + eint->domain = irq_domain_create_linear(of_fwnode_handle(eint->dev->of_node), + eint->hw->ap_num, &irq_domain_simple_ops, NULL); if (!eint->domain) - return -ENOMEM; + goto err_eint; if (eint->hw->db_time) { for (i = 0; i < MTK_EINT_DBNC_MAX; i++) @@ -523,8 +575,11 @@ int mtk_eint_do_init(struct mtk_eint *eint) mtk_eint_hw_init(eint); for (i = 0; i < eint->hw->ap_num; i++) { - int virq = irq_create_mapping(eint->domain, i); - + inst = eint->pins[i].instance; + if (inst >= eint->nbase) + continue; + eint->pin_list[inst][eint->pins[i].index] = i; + virq = irq_create_mapping(eint->domain, i); irq_set_chip_and_handler(virq, &mtk_eint_irq_chip, handle_level_irq); irq_set_chip_data(virq, eint); @@ -534,6 +589,27 @@ int mtk_eint_do_init(struct mtk_eint *eint) eint); return 0; + +err_eint: + for (i = 0; i < eint->nbase; i++) { + if (eint->cur_mask[i]) + devm_kfree(eint->dev, eint->cur_mask[i]); + if (eint->wake_mask[i]) + devm_kfree(eint->dev, eint->wake_mask[i]); + if (eint->pin_list[i]) + devm_kfree(eint->dev, eint->pin_list[i]); + } + devm_kfree(eint->dev, eint->cur_mask); +err_cur_mask: + devm_kfree(eint->dev, eint->wake_mask); +err_wake_mask: + devm_kfree(eint->dev, eint->pin_list); +err_pin_list: + if (!eint_pin) + devm_kfree(eint->dev, eint->pins); +err_pins: + devm_kfree(eint->dev, eint->base_pin_num); + return -ENOMEM; } EXPORT_SYMBOL_GPL(mtk_eint_do_init); diff --git a/drivers/pinctrl/mediatek/mtk-eint.h b/drivers/pinctrl/mediatek/mtk-eint.h index 6139b16cd225..fc31a4c0c77b 100644 --- a/drivers/pinctrl/mediatek/mtk-eint.h +++ b/drivers/pinctrl/mediatek/mtk-eint.h @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2014-2018 MediaTek Inc. + * Copyright (C) 2014-2025 MediaTek Inc. * * Author: Maoguang Meng <maoguang.meng@mediatek.com> * Sean Wang <sean.wang@mediatek.com> - * + * Hao Chang <ot_chhao.chang@mediatek.com> + * Qingliang Li <qingliang.li@mediatek.com> */ #ifndef __MTK_EINT_H #define __MTK_EINT_H @@ -40,6 +41,14 @@ struct mtk_eint_hw { const unsigned int *db_time; }; +struct mtk_eint_pin { + u16 number; + u8 instance; + u8 index; + bool debounce; + bool dual_edge; +}; + extern const unsigned int debounce_time_mt2701[]; extern const unsigned int debounce_time_mt6765[]; extern const unsigned int debounce_time_mt6795[]; @@ -56,17 +65,21 @@ struct mtk_eint_xt { struct mtk_eint { struct device *dev; - void __iomem *base; + void __iomem **base; + int nbase; + u16 *base_pin_num; struct irq_domain *domain; int irq; int *dual_edge; - u32 *wake_mask; - u32 *cur_mask; + u16 **pin_list; + u32 **wake_mask; + u32 **cur_mask; /* Used to fit into various EINT device */ const struct mtk_eint_hw *hw; const struct mtk_eint_regs *regs; + struct mtk_eint_pin *pins; u16 num_db_time; /* Used to fit into various pinctrl device */ @@ -75,7 +88,7 @@ struct mtk_eint { }; #if IS_ENABLED(CONFIG_EINT_MTK) -int mtk_eint_do_init(struct mtk_eint *eint); +int mtk_eint_do_init(struct mtk_eint *eint, struct mtk_eint_pin *eint_pin); int mtk_eint_do_suspend(struct mtk_eint *eint); int mtk_eint_do_resume(struct mtk_eint *eint); int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_n, @@ -83,7 +96,8 @@ int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_n, int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n); #else -static inline int mtk_eint_do_init(struct mtk_eint *eint) +static inline int mtk_eint_do_init(struct mtk_eint *eint, + struct mtk_eint_pin *eint_pin) { return -EOPNOTSUPP; } diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c index 547a798b71c8..b97b28ebb37a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c @@ -6,6 +6,7 @@ */ #include <dt-bindings/pinctrl/mt65xx.h> +#include <linux/bitfield.h> #include <linux/bits.h> #include <linux/cleanup.h> #include <linux/gpio/driver.h> @@ -112,39 +113,19 @@ #define REG_LAN_LED1_MAPPING 0x0280 #define LAN4_LED_MAPPING_MASK GENMASK(18, 16) -#define LAN4_PHY4_LED_MAP BIT(18) -#define LAN4_PHY2_LED_MAP BIT(17) -#define LAN4_PHY1_LED_MAP BIT(16) -#define LAN4_PHY0_LED_MAP 0 -#define LAN4_PHY3_LED_MAP GENMASK(17, 16) +#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n)) #define LAN3_LED_MAPPING_MASK GENMASK(14, 12) -#define LAN3_PHY4_LED_MAP BIT(14) -#define LAN3_PHY2_LED_MAP BIT(13) -#define LAN3_PHY1_LED_MAP BIT(12) -#define LAN3_PHY0_LED_MAP 0 -#define LAN3_PHY3_LED_MAP GENMASK(13, 12) +#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) #define LAN2_LED_MAPPING_MASK GENMASK(10, 8) -#define LAN2_PHY4_LED_MAP BIT(12) -#define LAN2_PHY2_LED_MAP BIT(11) -#define LAN2_PHY1_LED_MAP BIT(10) -#define LAN2_PHY0_LED_MAP 0 -#define LAN2_PHY3_LED_MAP GENMASK(11, 10) +#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) #define LAN1_LED_MAPPING_MASK GENMASK(6, 4) -#define LAN1_PHY4_LED_MAP BIT(6) -#define LAN1_PHY2_LED_MAP BIT(5) -#define LAN1_PHY1_LED_MAP BIT(4) -#define LAN1_PHY0_LED_MAP 0 -#define LAN1_PHY3_LED_MAP GENMASK(5, 4) +#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) #define LAN0_LED_MAPPING_MASK GENMASK(2, 0) -#define LAN0_PHY4_LED_MAP BIT(3) -#define LAN0_PHY2_LED_MAP BIT(2) -#define LAN0_PHY1_LED_MAP BIT(1) -#define LAN0_PHY0_LED_MAP 0 -#define LAN0_PHY3_LED_MAP GENMASK(2, 1) +#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) /* CONF */ #define REG_I2C_SDA_E2 0x001c @@ -1476,8 +1457,8 @@ static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED0_MAPPING, - LAN1_LED_MAPPING_MASK, - LAN1_PHY1_LED_MAP + LAN0_LED_MAPPING_MASK, + LAN0_PHY_LED_MAP(0) }, .regmap_size = 2, }, { @@ -1491,8 +1472,8 @@ static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED0_MAPPING, - LAN2_LED_MAPPING_MASK, - LAN2_PHY1_LED_MAP + LAN1_LED_MAPPING_MASK, + LAN1_PHY_LED_MAP(0) }, .regmap_size = 2, }, { @@ -1506,8 +1487,8 @@ static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED0_MAPPING, - LAN3_LED_MAPPING_MASK, - LAN3_PHY1_LED_MAP + LAN2_LED_MAPPING_MASK, + LAN2_PHY_LED_MAP(0) }, .regmap_size = 2, }, { @@ -1521,8 +1502,8 @@ static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED0_MAPPING, - LAN4_LED_MAPPING_MASK, - LAN4_PHY1_LED_MAP + LAN3_LED_MAPPING_MASK, + LAN3_PHY_LED_MAP(0) }, .regmap_size = 2, }, @@ -1540,8 +1521,8 @@ static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED0_MAPPING, - LAN1_LED_MAPPING_MASK, - LAN1_PHY2_LED_MAP + LAN0_LED_MAPPING_MASK, + LAN0_PHY_LED_MAP(1) }, .regmap_size = 2, }, { @@ -1555,8 +1536,8 @@ static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED0_MAPPING, - LAN2_LED_MAPPING_MASK, - LAN2_PHY2_LED_MAP + LAN1_LED_MAPPING_MASK, + LAN1_PHY_LED_MAP(1) }, .regmap_size = 2, }, { @@ -1570,8 +1551,8 @@ static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED0_MAPPING, - LAN3_LED_MAPPING_MASK, - LAN3_PHY2_LED_MAP + LAN2_LED_MAPPING_MASK, + LAN2_PHY_LED_MAP(1) }, .regmap_size = 2, }, { @@ -1585,8 +1566,8 @@ static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED0_MAPPING, - LAN4_LED_MAPPING_MASK, - LAN4_PHY2_LED_MAP + LAN3_LED_MAPPING_MASK, + LAN3_PHY_LED_MAP(1) }, .regmap_size = 2, }, @@ -1604,8 +1585,8 @@ static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED0_MAPPING, - LAN1_LED_MAPPING_MASK, - LAN1_PHY3_LED_MAP + LAN0_LED_MAPPING_MASK, + LAN0_PHY_LED_MAP(2) }, .regmap_size = 2, }, { @@ -1619,8 +1600,8 @@ static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED0_MAPPING, - LAN2_LED_MAPPING_MASK, - LAN2_PHY3_LED_MAP + LAN1_LED_MAPPING_MASK, + LAN1_PHY_LED_MAP(2) }, .regmap_size = 2, }, { @@ -1634,8 +1615,8 @@ static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED0_MAPPING, - LAN3_LED_MAPPING_MASK, - LAN3_PHY3_LED_MAP + LAN2_LED_MAPPING_MASK, + LAN2_PHY_LED_MAP(2) }, .regmap_size = 2, }, { @@ -1649,8 +1630,8 @@ static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED0_MAPPING, - LAN4_LED_MAPPING_MASK, - LAN4_PHY3_LED_MAP + LAN3_LED_MAPPING_MASK, + LAN3_PHY_LED_MAP(2) }, .regmap_size = 2, }, @@ -1668,8 +1649,8 @@ static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED0_MAPPING, - LAN1_LED_MAPPING_MASK, - LAN1_PHY4_LED_MAP + LAN0_LED_MAPPING_MASK, + LAN0_PHY_LED_MAP(3) }, .regmap_size = 2, }, { @@ -1683,8 +1664,8 @@ static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED0_MAPPING, - LAN2_LED_MAPPING_MASK, - LAN2_PHY4_LED_MAP + LAN1_LED_MAPPING_MASK, + LAN1_PHY_LED_MAP(3) }, .regmap_size = 2, }, { @@ -1698,8 +1679,8 @@ static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED0_MAPPING, - LAN3_LED_MAPPING_MASK, - LAN3_PHY4_LED_MAP + LAN2_LED_MAPPING_MASK, + LAN2_PHY_LED_MAP(3) }, .regmap_size = 2, }, { @@ -1713,8 +1694,8 @@ static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED0_MAPPING, - LAN4_LED_MAPPING_MASK, - LAN4_PHY4_LED_MAP + LAN3_LED_MAPPING_MASK, + LAN3_PHY_LED_MAP(3) }, .regmap_size = 2, }, @@ -1732,8 +1713,8 @@ static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED1_MAPPING, - LAN1_LED_MAPPING_MASK, - LAN1_PHY1_LED_MAP + LAN0_LED_MAPPING_MASK, + LAN0_PHY_LED_MAP(0) }, .regmap_size = 2, }, { @@ -1747,8 +1728,8 @@ static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED1_MAPPING, - LAN2_LED_MAPPING_MASK, - LAN2_PHY1_LED_MAP + LAN1_LED_MAPPING_MASK, + LAN1_PHY_LED_MAP(0) }, .regmap_size = 2, }, { @@ -1762,8 +1743,8 @@ static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED1_MAPPING, - LAN3_LED_MAPPING_MASK, - LAN3_PHY1_LED_MAP + LAN2_LED_MAPPING_MASK, + LAN2_PHY_LED_MAP(0) }, .regmap_size = 2, }, { @@ -1777,8 +1758,8 @@ static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED1_MAPPING, - LAN4_LED_MAPPING_MASK, - LAN4_PHY1_LED_MAP + LAN3_LED_MAPPING_MASK, + LAN3_PHY_LED_MAP(0) }, .regmap_size = 2, }, @@ -1796,8 +1777,8 @@ static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED1_MAPPING, - LAN1_LED_MAPPING_MASK, - LAN1_PHY2_LED_MAP + LAN0_LED_MAPPING_MASK, + LAN0_PHY_LED_MAP(1) }, .regmap_size = 2, }, { @@ -1811,8 +1792,8 @@ static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED1_MAPPING, - LAN2_LED_MAPPING_MASK, - LAN2_PHY2_LED_MAP + LAN1_LED_MAPPING_MASK, + LAN1_PHY_LED_MAP(1) }, .regmap_size = 2, }, { @@ -1826,8 +1807,8 @@ static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED1_MAPPING, - LAN3_LED_MAPPING_MASK, - LAN3_PHY2_LED_MAP + LAN2_LED_MAPPING_MASK, + LAN2_PHY_LED_MAP(1) }, .regmap_size = 2, }, { @@ -1841,8 +1822,8 @@ static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED1_MAPPING, - LAN4_LED_MAPPING_MASK, - LAN4_PHY2_LED_MAP + LAN3_LED_MAPPING_MASK, + LAN3_PHY_LED_MAP(1) }, .regmap_size = 2, }, @@ -1860,8 +1841,8 @@ static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED1_MAPPING, - LAN1_LED_MAPPING_MASK, - LAN1_PHY3_LED_MAP + LAN0_LED_MAPPING_MASK, + LAN0_PHY_LED_MAP(2) }, .regmap_size = 2, }, { @@ -1875,8 +1856,8 @@ static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED1_MAPPING, - LAN2_LED_MAPPING_MASK, - LAN2_PHY3_LED_MAP + LAN1_LED_MAPPING_MASK, + LAN1_PHY_LED_MAP(2) }, .regmap_size = 2, }, { @@ -1890,8 +1871,8 @@ static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED1_MAPPING, - LAN3_LED_MAPPING_MASK, - LAN3_PHY3_LED_MAP + LAN2_LED_MAPPING_MASK, + LAN2_PHY_LED_MAP(2) }, .regmap_size = 2, }, { @@ -1905,8 +1886,8 @@ static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED1_MAPPING, - LAN4_LED_MAPPING_MASK, - LAN4_PHY3_LED_MAP + LAN3_LED_MAPPING_MASK, + LAN3_PHY_LED_MAP(2) }, .regmap_size = 2, }, @@ -1924,8 +1905,8 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED1_MAPPING, - LAN1_LED_MAPPING_MASK, - LAN1_PHY4_LED_MAP + LAN0_LED_MAPPING_MASK, + LAN0_PHY_LED_MAP(3) }, .regmap_size = 2, }, { @@ -1939,8 +1920,8 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED1_MAPPING, - LAN2_LED_MAPPING_MASK, - LAN2_PHY4_LED_MAP + LAN1_LED_MAPPING_MASK, + LAN1_PHY_LED_MAP(3) }, .regmap_size = 2, }, { @@ -1954,8 +1935,8 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED1_MAPPING, - LAN3_LED_MAPPING_MASK, - LAN3_PHY4_LED_MAP + LAN2_LED_MAPPING_MASK, + LAN2_PHY_LED_MAP(3) }, .regmap_size = 2, }, { @@ -1969,8 +1950,8 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { .regmap[1] = { AIROHA_FUNC_MUX, REG_LAN_LED1_MAPPING, - LAN4_LED_MAPPING_MASK, - LAN4_PHY4_LED_MAP + LAN3_LED_MAPPING_MASK, + LAN3_PHY_LED_MAP(3) }, .regmap_size = 2, }, @@ -2266,15 +2247,16 @@ static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev, } /* gpio callbacks */ -static void airoha_gpio_set(struct gpio_chip *chip, unsigned int gpio, - int value) +static int airoha_gpio_set(struct gpio_chip *chip, unsigned int gpio, + int value) { struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip); u32 offset = gpio % AIROHA_PIN_BANK_SIZE; u8 index = gpio / AIROHA_PIN_BANK_SIZE; - regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.data[index], - BIT(offset), value ? BIT(offset) : 0); + return regmap_update_bits(pinctrl->regmap, + pinctrl->gpiochip.data[index], + BIT(offset), value ? BIT(offset) : 0); } static int airoha_gpio_get(struct gpio_chip *chip, unsigned int gpio) @@ -2299,9 +2281,7 @@ static int airoha_gpio_direction_output(struct gpio_chip *chip, if (err) return err; - airoha_gpio_set(chip, gpio, value); - - return 0; + return airoha_gpio_set(chip, gpio, value); } /* irq callbacks */ @@ -2438,7 +2418,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl, gc->free = gpiochip_generic_free; gc->direction_input = pinctrl_gpio_direction_input; gc->direction_output = airoha_gpio_direction_output; - gc->set = airoha_gpio_set; + gc->set_rv = airoha_gpio_set; gc->get = airoha_gpio_get; gc->base = -1; gc->ngpio = AIROHA_NUM_PINS; @@ -2734,9 +2714,7 @@ static int airoha_pinconf_set_pin_value(struct pinctrl_dev *pctrl_dev, if (pin < 0) return pin; - airoha_gpio_set(&pinctrl->gpiochip.chip, pin, value); - - return 0; + return airoha_gpio_set(&pinctrl->gpiochip.chip, pin, value); } static int airoha_pinconf_set(struct pinctrl_dev *pctrl_dev, diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index aad4891223d3..827d0f191031 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -496,24 +496,26 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio) return !!value; } -static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) +static int mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) { struct mtk_pinctrl *hw = gpiochip_get_data(chip); const struct mtk_pin_desc *desc; desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; - if (!desc->name) { - dev_err(hw->dev, "Failed to set gpio %d\n", gpio); - return; - } + if (!desc->name) + return -ENOTSUPP; - mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value); + return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value); } static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, int value) { - mtk_gpio_set(chip, gpio, value); + int ret; + + ret = mtk_gpio_set(chip, gpio, value); + if (ret) + return ret; return pinctrl_gpio_direction_output(chip, gpio); } @@ -567,7 +569,7 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw) chip->direction_input = pinctrl_gpio_direction_input; chip->direction_output = mtk_gpio_direction_output; chip->get = mtk_gpio_get; - chip->set = mtk_gpio_set; + chip->set_rv = mtk_gpio_set; chip->to_irq = mtk_gpio_to_irq; chip->set_config = mtk_gpio_set_config; chip->base = -1; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6893.c b/drivers/pinctrl/mediatek/pinctrl-mt6893.c new file mode 100644 index 000000000000..468ce0109b07 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt6893.c @@ -0,0 +1,879 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. + * Copyright (C) 2024 Collabora Ltd. + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ + +#include <linux/module.h> +#include "pinctrl-mtk-mt6893.h" +#include "pinctrl-paris.h" + +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ + 32, 0) + +#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ + 32, 1) + +static const struct mtk_pin_field_calc mt6893_pin_mode_range[] = { + PIN_FIELD(0, 219, 0x0300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt6893_pin_dir_range[] = { + PIN_FIELD(0, 219, 0x0000, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6893_pin_di_range[] = { + PIN_FIELD(0, 219, 0x0200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6893_pin_do_range[] = { + PIN_FIELD(0, 219, 0x0100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6893_pin_smt_range[] = { + PINS_FIELD_BASE(0, 9, 2, 0x00f0, 0x10, 7, 1), + PINS_FIELD_BASE(10, 15, 1, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(16, 17, 5, 0x00c0, 0x10, 8, 1), + PINS_FIELD_BASE(18, 25, 7, 0x00f0, 0x10, 1, 1), + PINS_FIELD_BASE(26, 30, 6, 0x00e0, 0x10, 6, 1), + PINS_FIELD_BASE(31, 35, 6, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(36, 36, 6, 0x00e0, 0x10, 16, 1), + PINS_FIELD_BASE(37, 39, 6, 0x00e0, 0x10, 15, 1), + PIN_FIELD_BASE(40, 41, 6, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 6, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(43, 44, 6, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(45, 45, 6, 0x00e0, 0x10, 12, 1), + PIN_FIELD_BASE(46, 46, 6, 0x00e0, 0x10, 14, 1), + PIN_FIELD_BASE(47, 47, 6, 0x00e0, 0x10, 13, 1), + PIN_FIELD_BASE(48, 49, 6, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(50, 50, 6, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(51, 52, 3, 0x0090, 0x10, 6, 1), + PINS_FIELD_BASE(53, 56, 3, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(57, 60, 3, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(62, 62, 4, 0x0050, 0x10, 1, 1), + PINS_FIELD_BASE(63, 73, 3, 0x0090, 0x10, 0, 1), + PINS_FIELD_BASE(74, 84, 4, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(85, 86, 4, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(87, 88, 4, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(89, 90, 2, 0x00f0, 0x10, 26, 1), + PIN_FIELD_BASE(91, 91, 2, 0x00f0, 0x10, 0, 1), + PINS_FIELD_BASE(92, 95, 2, 0x0100, 0x10, 0, 1), + PIN_FIELD_BASE(96, 96, 2, 0x00f0, 0x10, 30, 1), + PIN_FIELD_BASE(97, 97, 2, 0x00f0, 0x10, 28, 1), + PIN_FIELD_BASE(98, 98, 2, 0x00f0, 0x10, 31, 1), + PINS_FIELD_BASE(99, 102, 2, 0x00f0, 0x10, 29, 1), + PINS_FIELD_BASE(103, 105, 2, 0x00f0, 0x10, 24, 1), + PIN_FIELD_BASE(106, 106, 2, 0x00f0, 0x10, 25, 1), + PIN_FIELD_BASE(107, 108, 2, 0x00f0, 0x10, 5, 1), + PINS_FIELD_BASE(109, 113, 2, 0x00f0, 0x10, 8, 1), + PINS_FIELD_BASE(114, 116, 2, 0x00f0, 0x10, 16, 1), + PIN_FIELD_BASE(117, 117, 2, 0x00f0, 0x10, 17, 1), + PIN_FIELD_BASE(118, 118, 2, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(119, 119, 2, 0x00f0, 0x10, 18, 1), + PIN_FIELD_BASE(120, 120, 2, 0x00f0, 0x10, 15, 1), + PIN_FIELD_BASE(121, 121, 2, 0x00f0, 0x10, 23, 1), + PIN_FIELD_BASE(122, 122, 2, 0x00f0, 0x10, 14, 1), + PIN_FIELD_BASE(123, 123, 2, 0x00f0, 0x10, 22, 1), + PIN_FIELD_BASE(124, 124, 2, 0x00f0, 0x10, 13, 1), + PIN_FIELD_BASE(125, 125, 2, 0x00f0, 0x10, 21, 1), + PINS_FIELD_BASE(126, 129, 2, 0x00f0, 0x10, 9, 1), + PINS_FIELD_BASE(130, 135, 2, 0x00f0, 0x10, 4, 1), + PIN_FIELD_BASE(136, 138, 2, 0x00f0, 0x10, 1, 1), + PIN_FIELD_BASE(139, 139, 2, 0x00f0, 0x10, 12, 1), + PIN_FIELD_BASE(140, 140, 2, 0x00f0, 0x10, 20, 1), + PIN_FIELD_BASE(141, 141, 2, 0x00f0, 0x10, 11, 1), + PIN_FIELD_BASE(142, 142, 2, 0x00f0, 0x10, 19, 1), + PINS_FIELD_BASE(143, 148, 1, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(149, 151, 1, 0x0090, 0x10, 0, 1), + PINS_FIELD_BASE(152, 155, 5, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(156, 156, 5, 0x00c0, 0x10, 14, 1), + PINS_FIELD_BASE(157, 159, 5, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(160, 161, 5, 0x00c0, 0x10, 11, 1), + PINS_FIELD_BASE(162, 171, 5, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(172, 173, 5, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(174, 174, 5, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(175, 175, 5, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(176, 177, 5, 0x00c0, 0x10, 1, 1), + PINS_FIELD_BASE(178, 182, 5, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(183, 183, 7, 0x00f0, 0x10, 3, 1), + PINS_FIELD_BASE(184, 190, 7, 0x00f0, 0x10, 4, 1), + PIN_FIELD_BASE(191, 191, 7, 0x00f0, 0x10, 5, 1), + PIN_FIELD_BASE(192, 192, 7, 0x00f0, 0x10, 2, 1), + PIN_FIELD_BASE(193, 193, 7, 0x00f0, 0x10, 4, 1), + PIN_FIELD_BASE(194, 194, 7, 0x00f0, 0x10, 6, 1), + PIN_FIELD_BASE(195, 195, 7, 0x00f0, 0x10, 12, 1), + PINS_FIELD_BASE(196, 199, 7, 0x00f0, 0x10, 0, 1), + PIN_FIELD_BASE(200, 200, 7, 0x00f0, 0x10, 11, 1), + PIN_FIELD_BASE(201, 201, 7, 0x00f0, 0x10, 14, 1), + PIN_FIELD_BASE(202, 202, 7, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(203, 203, 7, 0x00f0, 0x10, 13, 1), + PIN_FIELD_BASE(204, 205, 6, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(206, 208, 7, 0x00f0, 0x10, 15, 1), + PINS_FIELD_BASE(209, 211, 7, 0x00f0, 0x10, 7, 1), + PIN_FIELD_BASE(212, 213, 7, 0x00f0, 0x10, 8, 1), + PINS_FIELD_BASE(214, 219, 7, 0x00f0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6893_pin_ies_range[] = { + PIN_FIELD_BASE(0, 9, 2, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(10, 15, 1, 0x0020, 0x10, 9, 1), + PIN_FIELD_BASE(16, 17, 5, 0x0030, 0x10, 21, 1), + PIN_FIELD_BASE(18, 25, 7, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(26, 30, 6, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, 6, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(32, 32, 6, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(33, 33, 6, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(34, 34, 6, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(35, 35, 6, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(36, 39, 6, 0x0040, 0x10, 23, 1), + PIN_FIELD_BASE(40, 41, 6, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 6, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(43, 44, 6, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(45, 45, 6, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(46, 46, 6, 0x0040, 0x10, 22, 1), + PIN_FIELD_BASE(47, 47, 6, 0x0040, 0x10, 21, 1), + PIN_FIELD_BASE(48, 49, 6, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(50, 50, 6, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(51, 52, 3, 0x0020, 0x10, 16, 1), + PIN_FIELD_BASE(53, 53, 3, 0x0020, 0x10, 21, 1), + PIN_FIELD_BASE(54, 54, 3, 0x0020, 0x10, 18, 1), + PIN_FIELD_BASE(55, 55, 3, 0x0020, 0x10, 20, 1), + PIN_FIELD_BASE(56, 56, 3, 0x0020, 0x10, 19, 1), + PIN_FIELD_BASE(57, 60, 3, 0x0020, 0x10, 12, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0020, 0x10, 11, 1), + PIN_FIELD_BASE(62, 62, 4, 0x0010, 0x10, 11, 1), + PIN_FIELD_BASE(63, 64, 3, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(65, 72, 3, 0x0020, 0x10, 3, 1), + PIN_FIELD_BASE(73, 73, 3, 0x0020, 0x10, 2, 1), + PIN_FIELD_BASE(74, 84, 4, 0x0010, 0x10, 0, 1), + PIN_FIELD_BASE(85, 86, 4, 0x0010, 0x10, 14, 1), + PIN_FIELD_BASE(87, 88, 4, 0x0010, 0x10, 12, 1), + PIN_FIELD_BASE(89, 90, 2, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(91, 91, 2, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(92, 92, 2, 0x0070, 0x10, 28, 1), + PIN_FIELD_BASE(93, 93, 2, 0x0070, 0x10, 30, 1), + PIN_FIELD_BASE(94, 94, 2, 0x0070, 0x10, 29, 1), + PIN_FIELD_BASE(95, 95, 2, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(96, 96, 2, 0x0070, 0x10, 26, 1), + PIN_FIELD_BASE(97, 97, 2, 0x0070, 0x10, 21, 1), + PIN_FIELD_BASE(98, 98, 2, 0x0070, 0x10, 27, 1), + PIN_FIELD_BASE(99, 102, 2, 0x0070, 0x10, 22, 1), + PIN_FIELD_BASE(103, 103, 2, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(104, 104, 2, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(105, 105, 2, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(106, 106, 2, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(107, 108, 2, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(109, 109, 2, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(110, 110, 2, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(111, 111, 2, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(112, 112, 2, 0x0060, 0x10, 26, 1), + PIN_FIELD_BASE(113, 113, 2, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(114, 114, 2, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(115, 115, 2, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(116, 116, 2, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(117, 117, 2, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(118, 118, 2, 0x0060, 0x10, 31, 1), + PIN_FIELD_BASE(119, 119, 2, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(120, 120, 2, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(121, 121, 2, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(122, 122, 2, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(123, 123, 2, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(124, 124, 2, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(125, 125, 2, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(126, 129, 2, 0x0060, 0x10, 27, 1), + PIN_FIELD_BASE(130, 132, 2, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(133, 135, 2, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(136, 138, 2, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(139, 139, 2, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(140, 140, 2, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(141, 141, 2, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(142, 142, 2, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(143, 145, 1, 0x0020, 0x10, 6, 1), + PIN_FIELD_BASE(146, 148, 1, 0x0020, 0x10, 3, 1), + PIN_FIELD_BASE(149, 151, 1, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(152, 152, 5, 0x0030, 0x10, 26, 1), + PIN_FIELD_BASE(153, 153, 5, 0x0030, 0x10, 25, 1), + PIN_FIELD_BASE(154, 155, 5, 0x0030, 0x10, 23, 1), + PIN_FIELD_BASE(156, 158, 5, 0x0030, 0x10, 29, 1), + PIN_FIELD_BASE(159, 159, 5, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(160, 161, 5, 0x0030, 0x10, 27, 1), + PIN_FIELD_BASE(162, 171, 5, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(172, 173, 5, 0x0030, 0x10, 13, 1), + PIN_FIELD_BASE(174, 174, 5, 0x0030, 0x10, 12, 1), + PIN_FIELD_BASE(175, 175, 5, 0x0030, 0x10, 15, 1), + PIN_FIELD_BASE(176, 177, 5, 0x0030, 0x10, 10, 1), + PIN_FIELD_BASE(178, 182, 5, 0x0030, 0x10, 16, 1), + PIN_FIELD_BASE(183, 184, 7, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(185, 185, 7, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(186, 186, 7, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(187, 187, 7, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(188, 188, 7, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(189, 189, 7, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(190, 191, 7, 0x0050, 0x10, 27, 1), + PIN_FIELD_BASE(192, 192, 7, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(193, 193, 7, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(194, 194, 7, 0x0050, 0x10, 29, 1), + PIN_FIELD_BASE(195, 195, 7, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(196, 196, 7, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(197, 197, 7, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(198, 198, 7, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(199, 199, 7, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(200, 200, 7, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(201, 201, 7, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(202, 202, 7, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(203, 203, 7, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(204, 205, 6, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(206, 208, 7, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(209, 209, 7, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(210, 210, 7, 0x0050, 0x10, 31, 1), + PIN_FIELD_BASE(211, 211, 7, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(212, 212, 7, 0x0050, 0x10, 30, 1), + PIN_FIELD_BASE(213, 213, 7, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(214, 214, 7, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(215, 215, 7, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(216, 217, 7, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(218, 219, 7, 0x0050, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt6893_pin_pu_range[] = { + PIN_FIELD_BASE(0, 9, 2, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(16, 17, 5, 0x0070, 0x10, 21, 1), + PIN_FIELD_BASE(18, 25, 7, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(26, 30, 6, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, 6, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(32, 32, 6, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(33, 33, 6, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(34, 34, 6, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(35, 35, 6, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(36, 39, 6, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(40, 41, 6, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 6, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(43, 44, 6, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(57, 60, 3, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(62, 62, 4, 0x0030, 0x10, 11, 1), + PIN_FIELD_BASE(63, 64, 3, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(65, 72, 3, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(73, 73, 3, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(74, 84, 4, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(85, 86, 4, 0x0030, 0x10, 14, 1), + PIN_FIELD_BASE(87, 88, 4, 0x0030, 0x10, 12, 1), + PIN_FIELD_BASE(89, 90, 2, 0x00b0, 0x10, 19, 1), + PIN_FIELD_BASE(91, 91, 2, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(92, 92, 2, 0x00b0, 0x10, 28, 1), + PIN_FIELD_BASE(93, 93, 2, 0x00b0, 0x10, 30, 1), + PIN_FIELD_BASE(94, 94, 2, 0x00b0, 0x10, 29, 1), + PIN_FIELD_BASE(95, 95, 2, 0x00b0, 0x10, 31, 1), + PIN_FIELD_BASE(96, 96, 2, 0x00b0, 0x10, 26, 1), + PIN_FIELD_BASE(97, 97, 2, 0x00b0, 0x10, 21, 1), + PIN_FIELD_BASE(98, 98, 2, 0x00b0, 0x10, 27, 1), + PIN_FIELD_BASE(99, 102, 2, 0x00b0, 0x10, 22, 1), + PIN_FIELD_BASE(103, 103, 2, 0x00b0, 0x10, 17, 1), + PIN_FIELD_BASE(104, 104, 2, 0x00b0, 0x10, 16, 1), + PIN_FIELD_BASE(105, 105, 2, 0x00b0, 0x10, 18, 1), + PIN_FIELD_BASE(106, 106, 2, 0x00b0, 0x10, 15, 1), + PIN_FIELD_BASE(107, 108, 2, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(109, 109, 2, 0x00a0, 0x10, 25, 1), + PIN_FIELD_BASE(110, 110, 2, 0x00a0, 0x10, 22, 1), + PIN_FIELD_BASE(111, 111, 2, 0x00a0, 0x10, 24, 1), + PIN_FIELD_BASE(112, 112, 2, 0x00a0, 0x10, 26, 1), + PIN_FIELD_BASE(113, 113, 2, 0x00a0, 0x10, 23, 1), + PIN_FIELD_BASE(114, 114, 2, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(115, 115, 2, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(116, 116, 2, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(117, 117, 2, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(118, 118, 2, 0x00a0, 0x10, 31, 1), + PIN_FIELD_BASE(119, 119, 2, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(120, 120, 2, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(121, 121, 2, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(122, 122, 2, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(123, 123, 2, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(124, 124, 2, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(125, 125, 2, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(126, 129, 2, 0x00a0, 0x10, 27, 1), + PIN_FIELD_BASE(130, 132, 2, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(133, 135, 2, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(136, 138, 2, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(139, 139, 2, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(140, 140, 2, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(141, 141, 2, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(142, 142, 2, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(143, 145, 1, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(146, 148, 1, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(149, 151, 1, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(156, 159, 5, 0x0070, 0x10, 25, 1), + PIN_FIELD_BASE(160, 161, 5, 0x0070, 0x10, 23, 1), + PIN_FIELD_BASE(162, 171, 5, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(172, 173, 5, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(174, 174, 5, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(175, 175, 5, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(176, 177, 5, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(178, 182, 5, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(195, 195, 7, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(196, 196, 7, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(197, 197, 7, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(198, 198, 7, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(199, 199, 7, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(200, 200, 7, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(201, 201, 7, 0x0090, 0x10, 27, 1), + PIN_FIELD_BASE(202, 202, 7, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(203, 203, 7, 0x0090, 0x10, 26, 1), + PIN_FIELD_BASE(204, 205, 6, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(206, 208, 7, 0x0090, 0x10, 28, 1), + PIN_FIELD_BASE(209, 209, 7, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(210, 210, 7, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(211, 211, 7, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(212, 212, 7, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(213, 213, 7, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(214, 214, 7, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(215, 215, 7, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(216, 217, 7, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(218, 219, 7, 0x0090, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt6893_pin_pd_range[] = { + PIN_FIELD_BASE(0, 9, 2, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(16, 17, 5, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(18, 25, 7, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(26, 30, 6, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, 6, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(32, 32, 6, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(33, 33, 6, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(34, 34, 6, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(35, 35, 6, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(36, 39, 6, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(40, 41, 6, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 6, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(43, 44, 6, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(57, 60, 3, 0x0030, 0x10, 12, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0030, 0x10, 11, 1), + PIN_FIELD_BASE(62, 62, 4, 0x0020, 0x10, 11, 1), + PIN_FIELD_BASE(63, 64, 3, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(65, 72, 3, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(73, 73, 3, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(74, 84, 4, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(85, 86, 4, 0x0020, 0x10, 14, 1), + PIN_FIELD_BASE(87, 88, 4, 0x0020, 0x10, 12, 1), + PIN_FIELD_BASE(89, 90, 2, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(91, 91, 2, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(92, 92, 2, 0x0090, 0x10, 28, 1), + PIN_FIELD_BASE(93, 93, 2, 0x0090, 0x10, 30, 1), + PIN_FIELD_BASE(94, 94, 2, 0x0090, 0x10, 29, 1), + PIN_FIELD_BASE(95, 95, 2, 0x0090, 0x10, 31, 1), + PIN_FIELD_BASE(96, 96, 2, 0x0090, 0x10, 26, 1), + PIN_FIELD_BASE(97, 97, 2, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(98, 98, 2, 0x0090, 0x10, 27, 1), + PIN_FIELD_BASE(99, 102, 2, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(103, 103, 2, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(104, 104, 2, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(105, 105, 2, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(106, 106, 2, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(107, 108, 2, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(109, 109, 2, 0x0080, 0x10, 25, 1), + PIN_FIELD_BASE(110, 110, 2, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(111, 111, 2, 0x0080, 0x10, 24, 1), + PIN_FIELD_BASE(112, 112, 2, 0x0080, 0x10, 26, 1), + PIN_FIELD_BASE(113, 113, 2, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(114, 114, 2, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(115, 115, 2, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(116, 116, 2, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(117, 117, 2, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(118, 118, 2, 0x0080, 0x10, 31, 1), + PIN_FIELD_BASE(119, 119, 2, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(120, 120, 2, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(121, 121, 2, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(122, 122, 2, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(123, 123, 2, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(124, 124, 2, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(125, 125, 2, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(126, 129, 2, 0x0080, 0x10, 27, 1), + PIN_FIELD_BASE(130, 132, 2, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(133, 135, 2, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(136, 138, 2, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(139, 139, 2, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(140, 140, 2, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(141, 141, 2, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(142, 142, 2, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(143, 145, 1, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(146, 148, 1, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(149, 151, 1, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(156, 159, 5, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(160, 161, 5, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(162, 171, 5, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(172, 173, 5, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(174, 174, 5, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(175, 175, 5, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(176, 177, 5, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(178, 182, 5, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(195, 195, 7, 0x0070, 0x10, 25, 1), + PIN_FIELD_BASE(196, 196, 7, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(197, 197, 7, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(198, 198, 7, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(199, 199, 7, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(200, 200, 7, 0x0070, 0x10, 24, 1), + PIN_FIELD_BASE(201, 201, 7, 0x0070, 0x10, 27, 1), + PIN_FIELD_BASE(202, 202, 7, 0x0070, 0x10, 23, 1), + PIN_FIELD_BASE(203, 203, 7, 0x0070, 0x10, 26, 1), + PIN_FIELD_BASE(204, 205, 6, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(206, 208, 7, 0x0070, 0x10, 28, 1), + PIN_FIELD_BASE(209, 209, 7, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(210, 210, 7, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(211, 211, 7, 0x0070, 0x10, 21, 1), + PIN_FIELD_BASE(212, 212, 7, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(213, 213, 7, 0x0070, 0x10, 22, 1), + PIN_FIELD_BASE(214, 214, 7, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(215, 215, 7, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(216, 217, 7, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(218, 219, 7, 0x0070, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt6893_pin_drv_range[] = { + PINS_FIELD_BASE(0, 9, 2, 0x0000, 0x10, 21, 3), + PINS_FIELD_BASE(10, 15, 1, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(16, 17, 5, 0x0000, 0x10, 18, 3), + PINS_FIELD_BASE(18, 25, 7, 0x0000, 0x10, 3, 3), + PINS_FIELD_BASE(26, 30, 6, 0x0000, 0x10, 15, 3), + PINS_FIELD_BASE(31, 35, 6, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(36, 36, 6, 0x0010, 0x10, 7, 3), + PINS_FIELD_BASE(37, 39, 6, 0x0010, 0x10, 4, 3), + PIN_FIELD_BASE(40, 41, 6, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(42, 42, 6, 0x0000, 0x10, 12, 3), + PINS_FIELD_BASE(43, 44, 6, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(45, 45, 6, 0x0000, 0x10, 30, 2), + PIN_FIELD_BASE(46, 46, 6, 0x0010, 0x10, 2, 2), + PIN_FIELD_BASE(47, 47, 6, 0x0010, 0x10, 0, 2), + PIN_FIELD_BASE(48, 49, 6, 0x0000, 0x10, 26, 2), + PIN_FIELD_BASE(50, 50, 6, 0x0000, 0x10, 24, 2), + PIN_FIELD_BASE(51, 52, 3, 0x0000, 0x10, 18, 3), + PINS_FIELD_BASE(53, 56, 3, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(57, 60, 3, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(61, 61, 3, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(62, 62, 4, 0x0000, 0x10, 3, 3), + PINS_FIELD_BASE(63, 73, 3, 0x0000, 0x10, 0, 3), + PINS_FIELD_BASE(74, 84, 4, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(85, 86, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(87, 88, 4, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(89, 90, 2, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(91, 91, 2, 0x0000, 0x10, 0, 3), + PINS_FIELD_BASE(92, 95, 2, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(96, 96, 2, 0x0020, 0x10, 27, 3), + PIN_FIELD_BASE(97, 97, 2, 0x0020, 0x10, 21, 3), + PIN_FIELD_BASE(98, 98, 2, 0x0030, 0x10, 0, 3), + PINS_FIELD_BASE(99, 102, 2, 0x0020, 0x10, 24, 3), + PINS_FIELD_BASE(103, 105, 2, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(106, 106, 2, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(107, 108, 2, 0x0000, 0x10, 15, 3), + PINS_FIELD_BASE(109, 113, 2, 0x0000, 0x10, 24, 3), + PINS_FIELD_BASE(114, 117, 2, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(118, 118, 2, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(119, 119, 2, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(120, 120, 2, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(121, 121, 2, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(122, 122, 2, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(123, 123, 2, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(124, 124, 2, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(125, 125, 2, 0x0020, 0x10, 0, 3), + PINS_FIELD_BASE(126, 129, 2, 0x0000, 0x10, 27, 3), + PINS_FIELD_BASE(130, 135, 2, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(136, 138, 2, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(139, 139, 2, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(140, 140, 2, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(141, 141, 2, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(142, 142, 2, 0x0010, 0x10, 24, 3), + PINS_FIELD_BASE(143, 148, 1, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(149, 151, 1, 0x0000, 0x10, 0, 3), + PINS_FIELD_BASE(152, 155, 5, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(156, 156, 5, 0x0010, 0x10, 6, 3), + PINS_FIELD_BASE(157, 159, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(160, 160, 5, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(161, 161, 5, 0x0010, 0x10, 0, 3), + PINS_FIELD_BASE(162, 171, 5, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(172, 172, 5, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(173, 173, 5, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(174, 174, 5, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(175, 177, 5, 0x0000, 0x10, 3, 3), + PINS_FIELD_BASE(178, 182, 5, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(183, 183, 7, 0x0000, 0x10, 9, 3), + PINS_FIELD_BASE(184, 190, 7, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(191, 191, 7, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(192, 192, 7, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(193, 193, 7, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(194, 194, 7, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(195, 195, 7, 0x0010, 0x10, 3, 3), + PINS_FIELD_BASE(196, 199, 7, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(200, 200, 7, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(201, 201, 7, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(202, 202, 7, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(203, 203, 7, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(204, 205, 6, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(206, 208, 7, 0x0010, 0x10, 12, 3), + PINS_FIELD_BASE(209, 212, 7, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(213, 213, 7, 0x0000, 0x10, 24, 3), + PINS_FIELD_BASE(214, 219, 7, 0x0000, 0x10, 0, 3), +}; + +static const struct mtk_pin_field_calc mt6893_pin_pupd_range[] = { + PIN_FIELD_BASE(10, 15, 1, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(45, 45, 6, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(46, 46, 6, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(47, 47, 6, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(48, 49, 6, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(50, 50, 6, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(51, 52, 3, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(53, 53, 3, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(54, 54, 3, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(55, 55, 3, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(56, 56, 3, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(152, 152, 5, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(153, 153, 5, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(154, 155, 5, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(183, 184, 7, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(185, 185, 7, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(186, 186, 7, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(187, 187, 7, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(188, 188, 7, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(189, 189, 7, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(190, 191, 7, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(192, 192, 7, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 7, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(194, 194, 7, 0x0080, 0x10, 11, 1), +}; + +static const struct mtk_pin_field_calc mt6893_pin_r0_range[] = { + PIN_FIELD_BASE(10, 15, 1, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(24, 24, 7, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(25, 25, 7, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(45, 45, 6, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(46, 46, 6, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(47, 47, 6, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(48, 49, 6, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(50, 50, 6, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(51, 52, 3, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(53, 53, 3, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(54, 54, 3, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(55, 55, 3, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(56, 56, 3, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(118, 118, 2, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(119, 119, 2, 0x00e0, 0x10, 12, 1), + PIN_FIELD_BASE(120, 120, 2, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(121, 121, 2, 0x00e0, 0x10, 22, 1), + PIN_FIELD_BASE(122, 122, 2, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(123, 123, 2, 0x00e0, 0x10, 20, 1), + PIN_FIELD_BASE(124, 124, 2, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(125, 125, 2, 0x00e0, 0x10, 18, 1), + PIN_FIELD_BASE(139, 139, 2, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(140, 140, 2, 0x00e0, 0x10, 16, 1), + PIN_FIELD_BASE(141, 141, 2, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(142, 142, 2, 0x00e0, 0x10, 14, 1), + PIN_FIELD_BASE(152, 152, 5, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(153, 153, 5, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(154, 155, 5, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(160, 160, 5, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(161, 161, 5, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(183, 184, 7, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(185, 185, 7, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(186, 186, 7, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(187, 187, 7, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(188, 188, 7, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(189, 189, 7, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(190, 191, 7, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(192, 192, 7, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 7, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(194, 194, 7, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(200, 200, 7, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(201, 201, 7, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(202, 202, 7, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(203, 203, 7, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(204, 204, 6, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(205, 205, 6, 0x00d0, 0x10, 2, 1), +}; + +static const struct mtk_pin_field_calc mt6893_pin_r1_range[] = { + PIN_FIELD_BASE(10, 15, 1, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(24, 24, 7, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(25, 25, 7, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(45, 45, 6, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(46, 46, 6, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(47, 47, 6, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(48, 49, 6, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(50, 50, 6, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(51, 52, 3, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(53, 53, 3, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(54, 54, 3, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(55, 55, 3, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(56, 56, 3, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(118, 118, 2, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(119, 119, 2, 0x00e0, 0x10, 13, 1), + PIN_FIELD_BASE(120, 120, 2, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, 2, 0x00e0, 0x10, 23, 1), + PIN_FIELD_BASE(122, 122, 2, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(123, 123, 2, 0x00e0, 0x10, 21, 1), + PIN_FIELD_BASE(124, 124, 2, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(125, 125, 2, 0x00e0, 0x10, 19, 1), + PIN_FIELD_BASE(139, 139, 2, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(140, 140, 2, 0x00e0, 0x10, 17, 1), + PIN_FIELD_BASE(141, 141, 2, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(142, 142, 2, 0x00e0, 0x10, 15, 1), + PIN_FIELD_BASE(152, 152, 5, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(153, 153, 5, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(154, 155, 5, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(160, 160, 5, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(161, 161, 5, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(183, 184, 7, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(185, 185, 7, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(186, 186, 7, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(187, 187, 7, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(188, 188, 7, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(189, 189, 7, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(190, 191, 7, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(192, 192, 7, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 7, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(194, 194, 7, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(200, 200, 7, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(201, 201, 7, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(202, 202, 7, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(203, 203, 7, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(204, 204, 6, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(205, 205, 6, 0x00d0, 0x10, 3, 1), +}; + +static const struct mtk_pin_field_calc mt6893_pin_drv_adv_range[] = { + PIN_FIELD_BASE(24, 24, 7, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(25, 25, 7, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(89, 89, 2, 0x0050, 0x10, 6, 5), + PIN_FIELD_BASE(90, 90, 2, 0x0050, 0x10, 11, 5), + PIN_FIELD_BASE(118, 118, 2, 0x0040, 0x10, 0, 3), + PIN_FIELD_BASE(119, 119, 2, 0x0040, 0x10, 18, 3), + PIN_FIELD_BASE(120, 120, 2, 0x0040, 0x10, 15, 3), + PIN_FIELD_BASE(121, 121, 2, 0x0050, 0x10, 3, 3), + PIN_FIELD_BASE(122, 122, 2, 0x0040, 0x10, 12, 3), + PIN_FIELD_BASE(123, 123, 2, 0x0050, 0x10, 0, 3), + PIN_FIELD_BASE(124, 124, 2, 0x0040, 0x10, 9, 3), + PIN_FIELD_BASE(125, 125, 2, 0x0040, 0x10, 27, 3), + PIN_FIELD_BASE(139, 139, 2, 0x0040, 0x10, 6, 3), + PIN_FIELD_BASE(140, 140, 2, 0x0040, 0x10, 24, 3), + PIN_FIELD_BASE(141, 141, 2, 0x0040, 0x10, 3, 3), + PIN_FIELD_BASE(142, 142, 2, 0x0040, 0x10, 21, 3), + PIN_FIELD_BASE(160, 160, 5, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(161, 161, 5, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(200, 200, 7, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(201, 201, 7, 0x0030, 0x10, 15, 3), + PIN_FIELD_BASE(202, 202, 7, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(203, 203, 7, 0x0030, 0x10, 12, 3), + PIN_FIELD_BASE(204, 204, 6, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(205, 205, 6, 0x0020, 0x10, 3, 3), +}; + +static const struct mtk_pin_field_calc mt6893_pin_rsel_range[] = { + PIN_FIELD_BASE(24, 24, 7, 0x00e0, 0x10, 0, 2), + PIN_FIELD_BASE(25, 25, 7, 0x00e0, 0x10, 2, 2), + PIN_FIELD_BASE(118, 118, 2, 0x00e0, 0x10, 0, 2), + PIN_FIELD_BASE(119, 119, 2, 0x00e0, 0x10, 12, 2), + PIN_FIELD_BASE(120, 120, 2, 0x00e0, 0x10, 10, 2), + PIN_FIELD_BASE(121, 121, 2, 0x00e0, 0x10, 22, 2), + PIN_FIELD_BASE(122, 122, 2, 0x00e0, 0x10, 8, 2), + PIN_FIELD_BASE(123, 123, 2, 0x00e0, 0x10, 20, 2), + PIN_FIELD_BASE(124, 124, 2, 0x00e0, 0x10, 6, 2), + PIN_FIELD_BASE(125, 125, 2, 0x00e0, 0x10, 18, 2), + PIN_FIELD_BASE(139, 139, 2, 0x00e0, 0x10, 4, 2), + PIN_FIELD_BASE(140, 140, 2, 0x00e0, 0x10, 16, 2), + PIN_FIELD_BASE(141, 141, 2, 0x00e0, 0x10, 2, 2), + PIN_FIELD_BASE(142, 142, 2, 0x00e0, 0x10, 14, 2), + PIN_FIELD_BASE(160, 160, 5, 0x00b0, 0x10, 0, 2), + PIN_FIELD_BASE(161, 161, 5, 0x00b0, 0x10, 2, 2), + PIN_FIELD_BASE(200, 200, 7, 0x00e0, 0x10, 6, 2), + PIN_FIELD_BASE(201, 201, 7, 0x00e0, 0x10, 10, 2), + PIN_FIELD_BASE(202, 202, 7, 0x00e0, 0x10, 4, 2), + PIN_FIELD_BASE(203, 203, 7, 0x00e0, 0x10, 8, 2), + PIN_FIELD_BASE(204, 204, 6, 0x00d0, 0x10, 0, 2), + PIN_FIELD_BASE(205, 205, 6, 0x00d0, 0x10, 2, 2), +}; + +static const unsigned int mt6893_pull_type[] = { + MTK_PULL_PU_PD_TYPE, /* 0 */ MTK_PULL_PU_PD_TYPE, /* 1 */ + MTK_PULL_PU_PD_TYPE, /* 2 */ MTK_PULL_PU_PD_TYPE, /* 3 */ + MTK_PULL_PU_PD_TYPE, /* 4 */ MTK_PULL_PU_PD_TYPE, /* 5 */ + MTK_PULL_PU_PD_TYPE, /* 6 */ MTK_PULL_PU_PD_TYPE, /* 7 */ + MTK_PULL_PU_PD_TYPE, /* 8 */ MTK_PULL_PU_PD_TYPE, /* 9 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 10 */ MTK_PULL_PUPD_R1R0_TYPE, /* 11 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 12 */ MTK_PULL_PUPD_R1R0_TYPE, /* 13 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 14 */ MTK_PULL_PUPD_R1R0_TYPE, /* 15 */ + MTK_PULL_PU_PD_TYPE, /* 16 */ MTK_PULL_PU_PD_TYPE, /* 17 */ + MTK_PULL_PU_PD_TYPE, /* 18 */ MTK_PULL_PU_PD_TYPE, /* 19 */ + MTK_PULL_PU_PD_TYPE, /* 20 */ MTK_PULL_PU_PD_TYPE, /* 21 */ + MTK_PULL_PU_PD_TYPE, /* 22 */ MTK_PULL_PU_PD_TYPE, /* 23 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 24 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 25 */ + MTK_PULL_PU_PD_TYPE, /* 26 */ MTK_PULL_PU_PD_TYPE, /* 27 */ + MTK_PULL_PU_PD_TYPE, /* 28 */ MTK_PULL_PU_PD_TYPE, /* 29 */ + MTK_PULL_PU_PD_TYPE, /* 30 */ MTK_PULL_PU_PD_TYPE, /* 31 */ + MTK_PULL_PU_PD_TYPE, /* 32 */ MTK_PULL_PU_PD_TYPE, /* 33 */ + MTK_PULL_PU_PD_TYPE, /* 34 */ MTK_PULL_PU_PD_TYPE, /* 35 */ + MTK_PULL_PU_PD_TYPE, /* 36 */ MTK_PULL_PU_PD_TYPE, /* 37 */ + MTK_PULL_PU_PD_TYPE, /* 38 */ MTK_PULL_PU_PD_TYPE, /* 39 */ + MTK_PULL_PU_PD_TYPE, /* 40 */ MTK_PULL_PU_PD_TYPE, /* 41 */ + MTK_PULL_PU_PD_TYPE, /* 42 */ MTK_PULL_PU_PD_TYPE, /* 43 */ + MTK_PULL_PU_PD_TYPE, /* 44 */ MTK_PULL_PUPD_R1R0_TYPE, /* 45 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 46 */ MTK_PULL_PUPD_R1R0_TYPE, /* 47 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 48 */ MTK_PULL_PUPD_R1R0_TYPE, /* 49 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 50 */ MTK_PULL_PUPD_R1R0_TYPE, /* 51 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 52 */ MTK_PULL_PUPD_R1R0_TYPE, /* 53 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 54 */ MTK_PULL_PUPD_R1R0_TYPE, /* 55 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 56 */ MTK_PULL_PU_PD_TYPE, /* 57 */ + MTK_PULL_PU_PD_TYPE, /* 58 */ MTK_PULL_PU_PD_TYPE, /* 59 */ + MTK_PULL_PU_PD_TYPE, /* 60 */ MTK_PULL_PU_PD_TYPE, /* 61 */ + MTK_PULL_PU_PD_TYPE, /* 62 */ MTK_PULL_PU_PD_TYPE, /* 63 */ + MTK_PULL_PU_PD_TYPE, /* 64 */ MTK_PULL_PU_PD_TYPE, /* 65 */ + MTK_PULL_PU_PD_TYPE, /* 66 */ MTK_PULL_PU_PD_TYPE, /* 67 */ + MTK_PULL_PU_PD_TYPE, /* 68 */ MTK_PULL_PU_PD_TYPE, /* 69 */ + MTK_PULL_PU_PD_TYPE, /* 70 */ MTK_PULL_PU_PD_TYPE, /* 71 */ + MTK_PULL_PU_PD_TYPE, /* 72 */ MTK_PULL_PU_PD_TYPE, /* 73 */ + MTK_PULL_PU_PD_TYPE, /* 74 */ MTK_PULL_PU_PD_TYPE, /* 75 */ + MTK_PULL_PU_PD_TYPE, /* 76 */ MTK_PULL_PU_PD_TYPE, /* 77 */ + MTK_PULL_PU_PD_TYPE, /* 78 */ MTK_PULL_PU_PD_TYPE, /* 79 */ + MTK_PULL_PU_PD_TYPE, /* 80 */ MTK_PULL_PU_PD_TYPE, /* 81 */ + MTK_PULL_PU_PD_TYPE, /* 82 */ MTK_PULL_PU_PD_TYPE, /* 83 */ + MTK_PULL_PU_PD_TYPE, /* 84 */ MTK_PULL_PU_PD_TYPE, /* 85 */ + MTK_PULL_PU_PD_TYPE, /* 86 */ MTK_PULL_PU_PD_TYPE, /* 87 */ + MTK_PULL_PU_PD_TYPE, /* 88 */ MTK_PULL_PU_PD_TYPE, /* 89 */ + MTK_PULL_PU_PD_TYPE, /* 90 */ MTK_PULL_PU_PD_TYPE, /* 91 */ + MTK_PULL_PU_PD_TYPE, /* 92 */ MTK_PULL_PU_PD_TYPE, /* 93 */ + MTK_PULL_PU_PD_TYPE, /* 94 */ MTK_PULL_PU_PD_TYPE, /* 95 */ + MTK_PULL_PU_PD_TYPE, /* 96 */ MTK_PULL_PU_PD_TYPE, /* 97 */ + MTK_PULL_PU_PD_TYPE, /* 98 */ MTK_PULL_PU_PD_TYPE, /* 99 */ + MTK_PULL_PU_PD_TYPE, /* 100 */ MTK_PULL_PU_PD_TYPE, /* 101 */ + MTK_PULL_PU_PD_TYPE, /* 102 */ MTK_PULL_PU_PD_TYPE, /* 103 */ + MTK_PULL_PU_PD_TYPE, /* 104 */ MTK_PULL_PU_PD_TYPE, /* 105 */ + MTK_PULL_PU_PD_TYPE, /* 106 */ MTK_PULL_PU_PD_TYPE, /* 107 */ + MTK_PULL_PU_PD_TYPE, /* 108 */ MTK_PULL_PU_PD_TYPE, /* 109 */ + MTK_PULL_PU_PD_TYPE, /* 110 */ MTK_PULL_PU_PD_TYPE, /* 111 */ + MTK_PULL_PU_PD_TYPE, /* 112 */ MTK_PULL_PU_PD_TYPE, /* 113 */ + MTK_PULL_PU_PD_TYPE, /* 114 */ MTK_PULL_PU_PD_TYPE, /* 115 */ + MTK_PULL_PU_PD_TYPE, /* 116 */ MTK_PULL_PU_PD_TYPE, /* 117 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 118 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 119 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 120 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 121 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 122 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 123 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 124 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 125 */ + MTK_PULL_PU_PD_TYPE, /* 126 */ MTK_PULL_PU_PD_TYPE, /* 127 */ + MTK_PULL_PU_PD_TYPE, /* 128 */ MTK_PULL_PU_PD_TYPE, /* 129 */ + MTK_PULL_PU_PD_TYPE, /* 130 */ MTK_PULL_PU_PD_TYPE, /* 131 */ + MTK_PULL_PU_PD_TYPE, /* 132 */ MTK_PULL_PU_PD_TYPE, /* 133 */ + MTK_PULL_PU_PD_TYPE, /* 134 */ MTK_PULL_PU_PD_TYPE, /* 135 */ + MTK_PULL_PU_PD_TYPE, /* 136 */ MTK_PULL_PU_PD_TYPE, /* 137 */ + MTK_PULL_PU_PD_TYPE, /* 138 */ MTK_PULL_PU_PD_TYPE, /* 139 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 140 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 141 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 142 */ MTK_PULL_PU_PD_TYPE, /* 143 */ + MTK_PULL_PU_PD_TYPE, /* 144 */ MTK_PULL_PU_PD_TYPE, /* 145 */ + MTK_PULL_PU_PD_TYPE, /* 146 */ MTK_PULL_PU_PD_TYPE, /* 147 */ + MTK_PULL_PU_PD_TYPE, /* 148 */ MTK_PULL_PU_PD_TYPE, /* 149 */ + MTK_PULL_PU_PD_TYPE, /* 150 */ MTK_PULL_PU_PD_TYPE, /* 151 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 152 */ MTK_PULL_PUPD_R1R0_TYPE, /* 153 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 154 */ MTK_PULL_PUPD_R1R0_TYPE, /* 155 */ + MTK_PULL_PU_PD_TYPE, /* 156 */ MTK_PULL_PU_PD_TYPE, /* 157 */ + MTK_PULL_PU_PD_TYPE, /* 158 */ MTK_PULL_PU_PD_TYPE, /* 159 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 160 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 161 */ + MTK_PULL_PU_PD_TYPE, /* 162 */ MTK_PULL_PU_PD_TYPE, /* 163 */ + MTK_PULL_PU_PD_TYPE, /* 164 */ MTK_PULL_PU_PD_TYPE, /* 165 */ + MTK_PULL_PU_PD_TYPE, /* 166 */ MTK_PULL_PU_PD_TYPE, /* 167 */ + MTK_PULL_PU_PD_TYPE, /* 168 */ MTK_PULL_PU_PD_TYPE, /* 169 */ + MTK_PULL_PU_PD_TYPE, /* 170 */ MTK_PULL_PU_PD_TYPE, /* 171 */ + MTK_PULL_PU_PD_TYPE, /* 172 */ MTK_PULL_PU_PD_TYPE, /* 173 */ + MTK_PULL_PU_PD_TYPE, /* 174 */ MTK_PULL_PU_PD_TYPE, /* 175 */ + MTK_PULL_PU_PD_TYPE, /* 176 */ MTK_PULL_PU_PD_TYPE, /* 177 */ + MTK_PULL_PU_PD_TYPE, /* 178 */ MTK_PULL_PU_PD_TYPE, /* 179 */ + MTK_PULL_PU_PD_TYPE, /* 180 */ MTK_PULL_PU_PD_TYPE, /* 181 */ + MTK_PULL_PU_PD_TYPE, /* 182 */ MTK_PULL_PUPD_R1R0_TYPE, /* 183 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 184 */ MTK_PULL_PUPD_R1R0_TYPE, /* 185 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 186 */ MTK_PULL_PUPD_R1R0_TYPE, /* 187 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 188 */ MTK_PULL_PUPD_R1R0_TYPE, /* 189 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 190 */ MTK_PULL_PUPD_R1R0_TYPE, /* 191 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 192 */ MTK_PULL_PUPD_R1R0_TYPE, /* 193 */ + MTK_PULL_PUPD_R1R0_TYPE, /* 194 */ MTK_PULL_PU_PD_TYPE, /* 195 */ + MTK_PULL_PU_PD_TYPE, /* 196 */ MTK_PULL_PU_PD_TYPE, /* 197 */ + MTK_PULL_PU_PD_TYPE, /* 198 */ MTK_PULL_PU_PD_TYPE, /* 199 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 200 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 201 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 202 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 203 */ + MTK_PULL_PU_PD_RSEL_TYPE, /* 204 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 205 */ + MTK_PULL_PU_PD_TYPE, /* 206 */ MTK_PULL_PU_PD_TYPE, /* 207 */ + MTK_PULL_PU_PD_TYPE, /* 208 */ MTK_PULL_PU_PD_TYPE, /* 209 */ + MTK_PULL_PU_PD_TYPE, /* 210 */ MTK_PULL_PU_PD_TYPE, /* 211 */ + MTK_PULL_PU_PD_TYPE, /* 212 */ MTK_PULL_PU_PD_TYPE, /* 213 */ + MTK_PULL_PU_PD_TYPE, /* 214 */ MTK_PULL_PU_PD_TYPE, /* 215 */ + MTK_PULL_PU_PD_TYPE, /* 216 */ MTK_PULL_PU_PD_TYPE, /* 217 */ + MTK_PULL_PU_PD_TYPE, /* 218 */ MTK_PULL_PU_PD_TYPE, /* 219 */ +}; + +static const char * const mt6893_pinctrl_register_base_name[] = { + "base", "rm", "bm", "bl", "br", "lm", "lb", "rt", "lt", "tl", +}; + +static const struct mtk_pin_reg_calc mt6893_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6893_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6893_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6893_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6893_pin_do_range), + [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt6893_pin_dir_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6893_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6893_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt6893_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt6893_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6893_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6893_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6893_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6893_pin_r1_range), + [PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt6893_pin_drv_adv_range), + [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt6893_pin_rsel_range), +}; + +static const struct mtk_eint_hw mt6893_eint_hw = { + .port_mask = 7, + .ports = 7, + .ap_num = 224, + .db_cnt = 32, + .db_time = debounce_time_mt6765, +}; + +static const struct mtk_pin_soc mt6893_data = { + .reg_cal = mt6893_reg_cals, + .pins = mtk_pins_mt6893, + .npins = ARRAY_SIZE(mtk_pins_mt6893), + .ngrps = ARRAY_SIZE(mtk_pins_mt6893), + .eint_hw = &mt6893_eint_hw, + .nfuncs = 8, + .gpio_m = 0, + .base_names = mt6893_pinctrl_register_base_name, + .nbase_names = ARRAY_SIZE(mt6893_pinctrl_register_base_name), + .pull_type = mt6893_pull_type, + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_drive_set = mtk_pinconf_adv_drive_set_raw, + .adv_drive_get = mtk_pinconf_adv_drive_get_raw, +}; + +static const struct of_device_id mt6893_pinctrl_of_match[] = { + { .compatible = "mediatek,mt6893-pinctrl", .data = &mt6893_data }, + { /* sentinel */ } +}; + +static struct platform_driver mt6893_pinctrl_driver = { + .driver = { + .name = "mt6893-pinctrl", + .of_match_table = mt6893_pinctrl_of_match, + .pm = pm_sleep_ptr(&mtk_paris_pinctrl_pm_ops) + }, + .probe = mtk_paris_pinctrl_probe, +}; + +static int __init mt6893_pinctrl_init(void) +{ + return platform_driver_register(&mt6893_pinctrl_driver); +} + +arch_initcall(mt6893_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT6893 Pinctrl Driver"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8196.c b/drivers/pinctrl/mediatek/pinctrl-mt8196.c new file mode 100644 index 000000000000..82a73929c7a0 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8196.c @@ -0,0 +1,1860 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Guodong Liu <Guodong.Liu@mediatek.com> + * Lei Xue <lei.xue@mediatek.com> + * Cathy Xu <ot_cathy.xu@mediatek.com> + */ + +#include <linux/module.h> +#include "pinctrl-mtk-mt8196.h" +#include "pinctrl-paris.h" + +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ + 32, 0) + +#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ + 32, 1) + +static const struct mtk_pin_field_calc mt8196_pin_mode_range[] = { + PIN_FIELD(0, 270, 0x0300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt8196_pin_dir_range[] = { + PIN_FIELD(0, 270, 0x0000, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_di_range[] = { + PIN_FIELD(0, 270, 0x0200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_do_range[] = { + PIN_FIELD(0, 270, 0x0100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 8, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, 11, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(3, 3, 11, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(4, 4, 11, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(5, 5, 11, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(6, 6, 11, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(7, 7, 11, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(8, 8, 11, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(9, 9, 9, 0x0120, 0x10, 13, 1), + PIN_FIELD_BASE(10, 10, 9, 0x0120, 0x10, 12, 1), + PIN_FIELD_BASE(11, 11, 8, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(12, 12, 9, 0x0120, 0x10, 15, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0120, 0x10, 3, 1), + PIN_FIELD_BASE(14, 14, 3, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0120, 0x10, 0, 1), + PIN_FIELD_BASE(16, 16, 6, 0x0120, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 6, 0x0120, 0x10, 3, 1), + PIN_FIELD_BASE(18, 18, 6, 0x0120, 0x10, 1, 1), + PIN_FIELD_BASE(19, 19, 6, 0x0120, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, 3, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(21, 21, 2, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(22, 22, 2, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(23, 23, 2, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(24, 24, 2, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(25, 25, 2, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(26, 26, 2, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(27, 27, 2, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(28, 28, 2, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, 2, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(30, 30, 2, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(31, 31, 2, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(32, 32, 1, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(33, 33, 1, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(34, 34, 1, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(35, 35, 1, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(36, 36, 1, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(37, 37, 1, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(38, 38, 1, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(39, 39, 8, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(40, 40, 8, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(41, 41, 8, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(42, 42, 8, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(43, 43, 8, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(44, 44, 8, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, 8, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(46, 46, 8, 0x00d0, 0x10, 6, 1), + PIN_FIELD_BASE(47, 47, 8, 0x00d0, 0x10, 9, 1), + PIN_FIELD_BASE(48, 48, 8, 0x00d0, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, 8, 0x00d0, 0x10, 10, 1), + PIN_FIELD_BASE(50, 50, 8, 0x00d0, 0x10, 8, 1), + PIN_FIELD_BASE(51, 51, 8, 0x00d0, 0x10, 11, 1), + PIN_FIELD_BASE(52, 52, 9, 0x0120, 0x10, 7, 1), + PIN_FIELD_BASE(53, 53, 9, 0x0120, 0x10, 8, 1), + PIN_FIELD_BASE(54, 54, 9, 0x0120, 0x10, 2, 1), + PIN_FIELD_BASE(55, 55, 9, 0x0120, 0x10, 1, 1), + PIN_FIELD_BASE(56, 56, 9, 0x0120, 0x10, 5, 1), + PIN_FIELD_BASE(57, 57, 9, 0x0120, 0x10, 6, 1), + PIN_FIELD_BASE(58, 58, 9, 0x0120, 0x10, 3, 1), + PIN_FIELD_BASE(59, 59, 9, 0x0120, 0x10, 4, 1), + PIN_FIELD_BASE(60, 60, 9, 0x0120, 0x10, 19, 1), + PIN_FIELD_BASE(61, 61, 9, 0x0120, 0x10, 10, 1), + PIN_FIELD_BASE(62, 62, 9, 0x0120, 0x10, 9, 1), + PIN_FIELD_BASE(63, 63, 9, 0x0120, 0x10, 14, 1), + PIN_FIELD_BASE(64, 64, 9, 0x0120, 0x10, 0, 1), + PIN_FIELD_BASE(65, 65, 9, 0x0120, 0x10, 11, 1), + PIN_FIELD_BASE(66, 66, 9, 0x0120, 0x10, 16, 1), + PIN_FIELD_BASE(67, 67, 9, 0x0120, 0x10, 18, 1), + PIN_FIELD_BASE(68, 68, 9, 0x0120, 0x10, 18, 1), + PIN_FIELD_BASE(69, 69, 9, 0x0120, 0x10, 18, 1), + PIN_FIELD_BASE(70, 70, 9, 0x0120, 0x10, 17, 1), + PIN_FIELD_BASE(71, 71, 9, 0x0120, 0x10, 17, 1), + PIN_FIELD_BASE(72, 72, 9, 0x0120, 0x10, 18, 1), + PIN_FIELD_BASE(73, 73, 9, 0x0120, 0x10, 17, 1), + PIN_FIELD_BASE(74, 74, 9, 0x0120, 0x10, 17, 1), + PIN_FIELD_BASE(75, 75, 10, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(76, 76, 10, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(77, 77, 10, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(78, 78, 10, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(79, 79, 10, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(80, 80, 10, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(81, 81, 11, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(82, 82, 11, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(83, 83, 11, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(84, 84, 11, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(85, 85, 11, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(86, 86, 11, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(87, 87, 11, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(88, 88, 11, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(89, 89, 11, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(90, 90, 11, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(91, 91, 12, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(92, 92, 12, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, 12, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(94, 94, 12, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(95, 95, 12, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(96, 96, 12, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(97, 97, 12, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(98, 98, 12, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(99, 99, 12, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(100, 100, 12, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(101, 101, 12, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(102, 102, 12, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(103, 103, 12, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(104, 104, 12, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(105, 105, 12, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(106, 106, 5, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 5, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(108, 108, 5, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(109, 109, 5, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(110, 110, 5, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, 5, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(112, 112, 5, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(113, 113, 5, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(114, 114, 5, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(115, 115, 5, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(116, 116, 5, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(117, 117, 5, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(118, 118, 6, 0x0120, 0x10, 6, 1), + PIN_FIELD_BASE(119, 119, 6, 0x0120, 0x10, 7, 1), + PIN_FIELD_BASE(120, 120, 6, 0x0120, 0x10, 9, 1), + PIN_FIELD_BASE(121, 121, 6, 0x0120, 0x10, 8, 1), + PIN_FIELD_BASE(122, 122, 6, 0x0120, 0x10, 3, 1), + PIN_FIELD_BASE(123, 123, 6, 0x0120, 0x10, 4, 1), + PIN_FIELD_BASE(124, 124, 6, 0x0120, 0x10, 5, 1), + PIN_FIELD_BASE(125, 125, 7, 0x00f0, 0x10, 0, 1), + PIN_FIELD_BASE(126, 126, 7, 0x00f0, 0x10, 1, 1), + PIN_FIELD_BASE(127, 127, 7, 0x00f0, 0x10, 2, 1), + PIN_FIELD_BASE(128, 128, 7, 0x00f0, 0x10, 3, 1), + PIN_FIELD_BASE(129, 129, 7, 0x00f0, 0x10, 4, 1), + PIN_FIELD_BASE(130, 130, 7, 0x00f0, 0x10, 5, 1), + PIN_FIELD_BASE(131, 131, 7, 0x00f0, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 7, 0x00f0, 0x10, 11, 1), + PIN_FIELD_BASE(133, 133, 7, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(134, 134, 7, 0x00f0, 0x10, 6, 1), + PIN_FIELD_BASE(135, 135, 7, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(136, 136, 7, 0x00f0, 0x10, 7, 1), + PIN_FIELD_BASE(137, 137, 4, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(138, 138, 4, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(139, 139, 4, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(140, 140, 4, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(141, 141, 4, 0x00d0, 0x10, 6, 1), + PIN_FIELD_BASE(142, 142, 4, 0x00d0, 0x10, 7, 1), + PIN_FIELD_BASE(143, 143, 4, 0x00d0, 0x10, 8, 1), + PIN_FIELD_BASE(144, 144, 4, 0x00d0, 0x10, 9, 1), + PIN_FIELD_BASE(145, 145, 4, 0x00d0, 0x10, 10, 1), + PIN_FIELD_BASE(146, 146, 4, 0x00d0, 0x10, 10, 1), + PIN_FIELD_BASE(147, 147, 4, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(148, 148, 4, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(149, 149, 4, 0x00d0, 0x10, 11, 1), + PIN_FIELD_BASE(150, 150, 4, 0x00d0, 0x10, 11, 1), + PIN_FIELD_BASE(151, 151, 4, 0x00d0, 0x10, 11, 1), + PIN_FIELD_BASE(152, 152, 4, 0x00d0, 0x10, 11, 1), + PIN_FIELD_BASE(153, 153, 4, 0x00d0, 0x10, 13, 1), + PIN_FIELD_BASE(154, 154, 4, 0x00d0, 0x10, 13, 1), + PIN_FIELD_BASE(155, 155, 4, 0x00d0, 0x10, 12, 1), + PIN_FIELD_BASE(156, 156, 4, 0x00d0, 0x10, 12, 1), + PIN_FIELD_BASE(157, 157, 2, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(158, 158, 2, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(159, 159, 2, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(160, 160, 3, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(161, 161, 3, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(162, 162, 3, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(163, 163, 3, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(164, 164, 3, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(165, 165, 3, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(166, 166, 3, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(167, 167, 3, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(168, 168, 3, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(169, 169, 3, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(170, 170, 3, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(171, 171, 3, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(172, 172, 3, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(173, 173, 3, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(174, 174, 1, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(175, 175, 1, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(176, 176, 1, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(177, 177, 1, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(178, 178, 1, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(179, 179, 1, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(180, 180, 1, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(181, 181, 1, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(182, 182, 1, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(183, 183, 1, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(184, 184, 1, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(185, 185, 1, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(186, 186, 13, 0x0110, 0x10, 14, 1), + PIN_FIELD_BASE(187, 187, 13, 0x0110, 0x10, 14, 1), + PIN_FIELD_BASE(188, 188, 13, 0x0110, 0x10, 4, 1), + PIN_FIELD_BASE(189, 189, 13, 0x0110, 0x10, 9, 1), + PIN_FIELD_BASE(190, 190, 13, 0x0110, 0x10, 5, 1), + PIN_FIELD_BASE(191, 191, 13, 0x0110, 0x10, 10, 1), + PIN_FIELD_BASE(192, 192, 13, 0x0110, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 13, 0x0110, 0x10, 15, 1), + PIN_FIELD_BASE(194, 194, 13, 0x0110, 0x10, 6, 1), + PIN_FIELD_BASE(195, 195, 13, 0x0110, 0x10, 11, 1), + PIN_FIELD_BASE(196, 196, 13, 0x0110, 0x10, 1, 1), + PIN_FIELD_BASE(197, 197, 13, 0x0110, 0x10, 16, 1), + PIN_FIELD_BASE(198, 198, 13, 0x0110, 0x10, 7, 1), + PIN_FIELD_BASE(199, 199, 13, 0x0110, 0x10, 12, 1), + PIN_FIELD_BASE(200, 200, 13, 0x0110, 0x10, 19, 1), + PIN_FIELD_BASE(201, 201, 13, 0x0110, 0x10, 22, 1), + PIN_FIELD_BASE(202, 202, 13, 0x0110, 0x10, 8, 1), + PIN_FIELD_BASE(203, 203, 13, 0x0110, 0x10, 13, 1), + PIN_FIELD_BASE(204, 204, 13, 0x0110, 0x10, 2, 1), + PIN_FIELD_BASE(205, 205, 13, 0x0110, 0x10, 3, 1), + PIN_FIELD_BASE(206, 206, 13, 0x0110, 0x10, 18, 1), + PIN_FIELD_BASE(207, 207, 13, 0x0110, 0x10, 17, 1), + PIN_FIELD_BASE(208, 208, 13, 0x0110, 0x10, 17, 1), + PIN_FIELD_BASE(209, 209, 13, 0x0110, 0x10, 17, 1), + PIN_FIELD_BASE(210, 210, 14, 0x0130, 0x10, 0, 1), + PIN_FIELD_BASE(211, 211, 14, 0x0130, 0x10, 1, 1), + PIN_FIELD_BASE(212, 212, 14, 0x0130, 0x10, 2, 1), + PIN_FIELD_BASE(213, 213, 14, 0x0130, 0x10, 3, 1), + PIN_FIELD_BASE(214, 214, 13, 0x0110, 0x10, 20, 1), + PIN_FIELD_BASE(215, 215, 13, 0x0110, 0x10, 21, 1), + PIN_FIELD_BASE(216, 216, 14, 0x0130, 0x10, 11, 1), + PIN_FIELD_BASE(217, 217, 14, 0x0130, 0x10, 11, 1), + PIN_FIELD_BASE(218, 218, 14, 0x0130, 0x10, 11, 1), + PIN_FIELD_BASE(219, 219, 14, 0x0130, 0x10, 4, 1), + PIN_FIELD_BASE(220, 220, 14, 0x0130, 0x10, 11, 1), + PIN_FIELD_BASE(221, 221, 14, 0x0130, 0x10, 12, 1), + PIN_FIELD_BASE(222, 222, 14, 0x0130, 0x10, 22, 1), + PIN_FIELD_BASE(223, 223, 14, 0x0130, 0x10, 21, 1), + PIN_FIELD_BASE(224, 224, 14, 0x0130, 0x10, 5, 1), + PIN_FIELD_BASE(225, 225, 14, 0x0130, 0x10, 6, 1), + PIN_FIELD_BASE(226, 226, 14, 0x0130, 0x10, 7, 1), + PIN_FIELD_BASE(227, 227, 14, 0x0130, 0x10, 8, 1), + PIN_FIELD_BASE(228, 228, 14, 0x0130, 0x10, 9, 1), + PIN_FIELD_BASE(229, 229, 14, 0x0130, 0x10, 10, 1), + PIN_FIELD_BASE(230, 230, 15, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(231, 231, 15, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(232, 232, 15, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(233, 233, 15, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(234, 234, 15, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(235, 235, 15, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(236, 236, 15, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(237, 237, 15, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(238, 238, 15, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(239, 239, 15, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(240, 240, 15, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(241, 241, 15, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(242, 242, 15, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(243, 243, 15, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(244, 244, 15, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(245, 245, 15, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(246, 246, 15, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(247, 247, 15, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(248, 248, 15, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(249, 249, 15, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(250, 250, 15, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(251, 251, 3, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(252, 252, 3, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(253, 253, 3, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(254, 254, 3, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(255, 255, 3, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(256, 256, 3, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(257, 257, 3, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(258, 258, 3, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(259, 259, 14, 0x0130, 0x10, 13, 1), + PIN_FIELD_BASE(260, 260, 14, 0x0130, 0x10, 14, 1), + PIN_FIELD_BASE(261, 261, 14, 0x0130, 0x10, 15, 1), + PIN_FIELD_BASE(262, 262, 14, 0x0130, 0x10, 16, 1), + PIN_FIELD_BASE(263, 263, 14, 0x0130, 0x10, 17, 1), + PIN_FIELD_BASE(264, 264, 14, 0x0130, 0x10, 18, 1), + PIN_FIELD_BASE(265, 265, 14, 0x0130, 0x10, 19, 1), + PIN_FIELD_BASE(266, 266, 14, 0x0130, 0x10, 20, 1), + PIN_FIELD_BASE(267, 267, 15, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(268, 268, 15, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(269, 269, 15, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(270, 270, 15, 0x00e0, 0x10, 7, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 8, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, 11, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(3, 3, 11, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, 11, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(5, 5, 11, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(6, 6, 11, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(7, 7, 11, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(8, 8, 11, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(9, 9, 9, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(10, 10, 9, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(11, 11, 8, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(12, 12, 9, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(14, 14, 3, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 6, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 6, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, 6, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, 6, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, 3, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 2, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(22, 22, 2, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(23, 23, 2, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(24, 24, 2, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(26, 26, 2, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(27, 27, 2, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, 2, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(29, 29, 2, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(30, 30, 2, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(31, 31, 2, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, 1, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(33, 33, 1, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(34, 34, 1, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(35, 35, 1, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(36, 36, 1, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(37, 37, 1, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(38, 38, 1, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(39, 39, 8, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(40, 40, 8, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(41, 41, 8, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(42, 42, 8, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(43, 43, 8, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(44, 44, 8, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(45, 45, 8, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(46, 46, 8, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(47, 47, 8, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(48, 48, 8, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(49, 49, 8, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(50, 50, 8, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(51, 51, 8, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(52, 52, 9, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(53, 53, 9, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(54, 54, 9, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(55, 55, 9, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(56, 56, 9, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(57, 57, 9, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(58, 58, 9, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(59, 59, 9, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(60, 60, 9, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(61, 61, 9, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(62, 62, 9, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(63, 63, 9, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(64, 64, 9, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(65, 65, 9, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(66, 66, 9, 0x0070, 0x10, 24, 1), + PIN_FIELD_BASE(67, 67, 9, 0x0070, 0x10, 22, 1), + PIN_FIELD_BASE(68, 68, 9, 0x0070, 0x10, 21, 1), + PIN_FIELD_BASE(69, 69, 9, 0x0070, 0x10, 25, 1), + PIN_FIELD_BASE(70, 70, 9, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(71, 71, 9, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(72, 72, 9, 0x0070, 0x10, 23, 1), + PIN_FIELD_BASE(73, 73, 9, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(74, 74, 9, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(75, 75, 10, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(76, 76, 10, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(77, 77, 10, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(78, 78, 10, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(79, 79, 10, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(80, 80, 10, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(81, 81, 11, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(82, 82, 11, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(83, 83, 11, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(84, 84, 11, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(85, 85, 11, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(86, 86, 11, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(87, 87, 11, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(88, 88, 11, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(89, 89, 11, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(90, 90, 11, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(91, 91, 12, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(92, 92, 12, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(93, 93, 12, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(94, 94, 12, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(95, 95, 12, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(96, 96, 12, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(97, 97, 12, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(98, 98, 12, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(99, 99, 12, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(100, 100, 12, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(101, 101, 12, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(102, 102, 12, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(103, 103, 12, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, 12, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(105, 105, 12, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(106, 106, 5, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 5, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(108, 108, 5, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(109, 109, 5, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(110, 110, 5, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(111, 111, 5, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(112, 112, 5, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(113, 113, 5, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(114, 114, 5, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(115, 115, 5, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(116, 116, 5, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(117, 117, 5, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(118, 118, 6, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(119, 119, 6, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(120, 120, 6, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(121, 121, 6, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(122, 122, 6, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, 6, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(124, 124, 6, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(125, 125, 7, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(126, 126, 7, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(127, 127, 7, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(128, 128, 7, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(129, 129, 7, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(130, 130, 7, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(131, 131, 7, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 7, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(133, 133, 7, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(134, 134, 7, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(135, 135, 7, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(136, 136, 7, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(137, 137, 4, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(138, 138, 4, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(143, 143, 4, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(144, 144, 4, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(145, 145, 4, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(146, 146, 4, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(147, 147, 4, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(148, 148, 4, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(149, 149, 4, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(150, 150, 4, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(151, 151, 4, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(152, 152, 4, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(153, 153, 4, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 4, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(155, 155, 4, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(156, 156, 4, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(157, 157, 2, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(158, 158, 2, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(159, 159, 2, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(160, 160, 3, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(161, 161, 3, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(162, 162, 3, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(163, 163, 3, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(164, 164, 3, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(165, 165, 3, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(166, 166, 3, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(167, 167, 3, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(168, 168, 3, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(169, 169, 3, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(170, 170, 3, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(171, 171, 3, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(172, 172, 3, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(173, 173, 3, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(174, 174, 1, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(175, 175, 1, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(176, 176, 1, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(177, 177, 1, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(178, 178, 1, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 1, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(180, 180, 1, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(181, 181, 1, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(182, 182, 1, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(183, 183, 1, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(184, 184, 1, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(185, 185, 1, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(186, 186, 13, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(187, 187, 13, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(188, 188, 13, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(189, 189, 13, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(190, 190, 13, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(191, 191, 13, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(192, 192, 13, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 13, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(194, 194, 13, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(195, 195, 13, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(196, 196, 13, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(197, 197, 13, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(198, 198, 13, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(199, 199, 13, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(200, 200, 13, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(201, 201, 13, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(202, 202, 13, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(203, 203, 13, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(204, 204, 13, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(205, 205, 13, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(206, 206, 13, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(207, 207, 13, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(208, 208, 13, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(209, 209, 13, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(210, 210, 14, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(211, 211, 14, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(212, 212, 14, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(213, 213, 14, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(214, 214, 13, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(215, 215, 13, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(216, 216, 14, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(217, 217, 14, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(218, 218, 14, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(219, 219, 14, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(220, 220, 14, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(221, 221, 14, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(222, 222, 14, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(223, 223, 14, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(224, 224, 14, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(225, 225, 14, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(226, 226, 14, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(227, 227, 14, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(228, 228, 14, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(229, 229, 14, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(230, 230, 15, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(231, 231, 15, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(232, 232, 15, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(233, 233, 15, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(234, 234, 15, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(235, 235, 15, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(236, 236, 15, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(237, 237, 15, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(238, 238, 15, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(239, 239, 15, 0x0040, 0x10, 23, 1), + PIN_FIELD_BASE(240, 240, 15, 0x0040, 0x10, 22, 1), + PIN_FIELD_BASE(241, 241, 15, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(242, 242, 15, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(243, 243, 15, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(244, 244, 15, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(245, 245, 15, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(246, 246, 15, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(247, 247, 15, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(248, 248, 15, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(249, 249, 15, 0x0040, 0x10, 24, 1), + PIN_FIELD_BASE(250, 250, 15, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(251, 251, 3, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(252, 252, 3, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(253, 253, 3, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(254, 254, 3, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(255, 255, 3, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(256, 256, 3, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(257, 257, 3, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(258, 258, 3, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(259, 259, 14, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(260, 260, 14, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(261, 261, 14, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(262, 262, 14, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(263, 263, 14, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(264, 264, 14, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(265, 265, 14, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(266, 266, 14, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(267, 267, 15, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(268, 268, 15, 0x0040, 0x10, 21, 1), + PIN_FIELD_BASE(269, 269, 15, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(270, 270, 15, 0x0040, 0x10, 19, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_pupd_range[] = { + PIN_FIELD_BASE(60, 60, 9, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(125, 125, 7, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(126, 126, 7, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(127, 127, 7, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(128, 128, 7, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(129, 129, 7, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(130, 130, 7, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(131, 131, 7, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 7, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(133, 133, 7, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(134, 134, 7, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(135, 135, 7, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(136, 136, 7, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(137, 137, 4, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(138, 138, 4, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(139, 139, 4, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(140, 140, 4, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(141, 141, 4, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 4, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(143, 143, 4, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(144, 144, 4, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(145, 145, 4, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(146, 146, 4, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(147, 147, 4, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(148, 148, 4, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(149, 149, 4, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(150, 150, 4, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(151, 151, 4, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(152, 152, 4, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(153, 153, 4, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 4, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(155, 155, 4, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(156, 156, 4, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(217, 217, 14, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(218, 218, 14, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(219, 219, 14, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(224, 224, 14, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(225, 225, 14, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(226, 226, 14, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(227, 227, 14, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(228, 228, 14, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(229, 229, 14, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(259, 259, 14, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(260, 260, 14, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(261, 261, 14, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(262, 262, 14, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(263, 263, 14, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(264, 264, 14, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(265, 265, 14, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(266, 266, 14, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(267, 267, 15, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(268, 268, 15, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(269, 269, 15, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(270, 270, 15, 0x0080, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_r0_range[] = { + PIN_FIELD_BASE(60, 60, 9, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(125, 125, 7, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(126, 126, 7, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(127, 127, 7, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(128, 128, 7, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(129, 129, 7, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(130, 130, 7, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(131, 131, 7, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 7, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(133, 133, 7, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(134, 134, 7, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(135, 135, 7, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(136, 136, 7, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(137, 137, 4, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(138, 138, 4, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(139, 139, 4, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(140, 140, 4, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(141, 141, 4, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 4, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(143, 143, 4, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(144, 144, 4, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(145, 145, 4, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(146, 146, 4, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(147, 147, 4, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(148, 148, 4, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(149, 149, 4, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(150, 150, 4, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(151, 151, 4, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(152, 152, 4, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(153, 153, 4, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 4, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(155, 155, 4, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(156, 156, 4, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(217, 217, 14, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(218, 218, 14, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(219, 219, 14, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(224, 224, 14, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(225, 225, 14, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(226, 226, 14, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(227, 227, 14, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(228, 228, 14, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(229, 229, 14, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(259, 259, 14, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(260, 260, 14, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(261, 261, 14, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(262, 262, 14, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(263, 263, 14, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(264, 264, 14, 0x00c0, 0x10, 14, 1), + PIN_FIELD_BASE(265, 265, 14, 0x00c0, 0x10, 15, 1), + PIN_FIELD_BASE(266, 266, 14, 0x00c0, 0x10, 16, 1), + PIN_FIELD_BASE(267, 267, 15, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(268, 268, 15, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(269, 269, 15, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(270, 270, 15, 0x00a0, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_r1_range[] = { + PIN_FIELD_BASE(60, 60, 9, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(125, 125, 7, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(126, 126, 7, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(127, 127, 7, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(128, 128, 7, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(129, 129, 7, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(130, 130, 7, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(131, 131, 7, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 7, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(133, 133, 7, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(134, 134, 7, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(135, 135, 7, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(136, 136, 7, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(137, 137, 4, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(138, 138, 4, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(139, 139, 4, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(140, 140, 4, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(141, 141, 4, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 4, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(143, 143, 4, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(144, 144, 4, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(145, 145, 4, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(146, 146, 4, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(147, 147, 4, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(148, 148, 4, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(149, 149, 4, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(150, 150, 4, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(151, 151, 4, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(152, 152, 4, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(153, 153, 4, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 4, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(155, 155, 4, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(156, 156, 4, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(217, 217, 14, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(218, 218, 14, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(219, 219, 14, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(224, 224, 14, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(225, 225, 14, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(226, 226, 14, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(227, 227, 14, 0x00d0, 0x10, 6, 1), + PIN_FIELD_BASE(228, 228, 14, 0x00d0, 0x10, 7, 1), + PIN_FIELD_BASE(229, 229, 14, 0x00d0, 0x10, 8, 1), + PIN_FIELD_BASE(259, 259, 14, 0x00d0, 0x10, 9, 1), + PIN_FIELD_BASE(260, 260, 14, 0x00d0, 0x10, 10, 1), + PIN_FIELD_BASE(261, 261, 14, 0x00d0, 0x10, 11, 1), + PIN_FIELD_BASE(262, 262, 14, 0x00d0, 0x10, 12, 1), + PIN_FIELD_BASE(263, 263, 14, 0x00d0, 0x10, 13, 1), + PIN_FIELD_BASE(264, 264, 14, 0x00d0, 0x10, 14, 1), + PIN_FIELD_BASE(265, 265, 14, 0x00d0, 0x10, 15, 1), + PIN_FIELD_BASE(266, 266, 14, 0x00d0, 0x10, 16, 1), + PIN_FIELD_BASE(267, 267, 15, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(268, 268, 15, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(269, 269, 15, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(270, 270, 15, 0x00b0, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_pu_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 8, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, 11, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(3, 3, 11, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, 11, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(5, 5, 11, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(6, 6, 11, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(7, 7, 11, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(8, 8, 11, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(9, 9, 9, 0x00c0, 0x10, 14, 1), + PIN_FIELD_BASE(10, 10, 9, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(11, 11, 8, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(12, 12, 9, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(13, 13, 6, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(14, 14, 3, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(15, 15, 6, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 6, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 6, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, 6, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, 6, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, 3, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 2, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(22, 22, 2, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(23, 23, 2, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(24, 24, 2, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(26, 26, 2, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(27, 27, 2, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, 2, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(29, 29, 2, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(30, 30, 2, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(31, 31, 2, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, 1, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(33, 33, 1, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(34, 34, 1, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(35, 35, 1, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(36, 36, 1, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(37, 37, 1, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(38, 38, 1, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(39, 39, 8, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(40, 40, 8, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(41, 41, 8, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(42, 42, 8, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(43, 43, 8, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(44, 44, 8, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(45, 45, 8, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(46, 46, 8, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(47, 47, 8, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(48, 48, 8, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(49, 49, 8, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(50, 50, 8, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(51, 51, 8, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(52, 52, 9, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(53, 53, 9, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(54, 54, 9, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(55, 55, 9, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(56, 56, 9, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(57, 57, 9, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(58, 58, 9, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(59, 59, 9, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(61, 61, 9, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(62, 62, 9, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(63, 63, 9, 0x00c0, 0x10, 18, 1), + PIN_FIELD_BASE(64, 64, 9, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(65, 65, 9, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(66, 66, 9, 0x00c0, 0x10, 24, 1), + PIN_FIELD_BASE(67, 67, 9, 0x00c0, 0x10, 21, 1), + PIN_FIELD_BASE(68, 68, 9, 0x00c0, 0x10, 20, 1), + PIN_FIELD_BASE(69, 69, 9, 0x00c0, 0x10, 25, 1), + PIN_FIELD_BASE(70, 70, 9, 0x00c0, 0x10, 16, 1), + PIN_FIELD_BASE(71, 71, 9, 0x00c0, 0x10, 15, 1), + PIN_FIELD_BASE(72, 72, 9, 0x00c0, 0x10, 23, 1), + PIN_FIELD_BASE(73, 73, 9, 0x00c0, 0x10, 19, 1), + PIN_FIELD_BASE(74, 74, 9, 0x00c0, 0x10, 17, 1), + PIN_FIELD_BASE(75, 75, 10, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(76, 76, 10, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(77, 77, 10, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(78, 78, 10, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(79, 79, 10, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(80, 80, 10, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(81, 81, 11, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(82, 82, 11, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(83, 83, 11, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(84, 84, 11, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(85, 85, 11, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(86, 86, 11, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(87, 87, 11, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(88, 88, 11, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(89, 89, 11, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(90, 90, 11, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(91, 91, 12, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(92, 92, 12, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(93, 93, 12, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(94, 94, 12, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(95, 95, 12, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(96, 96, 12, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(97, 97, 12, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(98, 98, 12, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(99, 99, 12, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(100, 100, 12, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(101, 101, 12, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(102, 102, 12, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(103, 103, 12, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, 12, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(105, 105, 12, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(106, 106, 5, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 5, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(108, 108, 5, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(109, 109, 5, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(110, 110, 5, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(111, 111, 5, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(112, 112, 5, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(113, 113, 5, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(114, 114, 5, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(115, 115, 5, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(116, 116, 5, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(117, 117, 5, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(118, 118, 6, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(119, 119, 6, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(120, 120, 6, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(121, 121, 6, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(122, 122, 6, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, 6, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(124, 124, 6, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(157, 157, 2, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(158, 158, 2, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(159, 159, 2, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(160, 160, 3, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(161, 161, 3, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(162, 162, 3, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(163, 163, 3, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(164, 164, 3, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(165, 165, 3, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(166, 166, 3, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(167, 167, 3, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(168, 168, 3, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(169, 169, 3, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(170, 170, 3, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(171, 171, 3, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(172, 172, 3, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(173, 173, 3, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(174, 174, 1, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(175, 175, 1, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(176, 176, 1, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(177, 177, 1, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(178, 178, 1, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 1, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(180, 180, 1, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(181, 181, 1, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(182, 182, 1, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(183, 183, 1, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(184, 184, 1, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(185, 185, 1, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(186, 186, 13, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(187, 187, 13, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(188, 188, 13, 0x00d0, 0x10, 12, 1), + PIN_FIELD_BASE(189, 189, 13, 0x00d0, 0x10, 17, 1), + PIN_FIELD_BASE(190, 190, 13, 0x00d0, 0x10, 13, 1), + PIN_FIELD_BASE(191, 191, 13, 0x00d0, 0x10, 18, 1), + PIN_FIELD_BASE(192, 192, 13, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 13, 0x00d0, 0x10, 6, 1), + PIN_FIELD_BASE(194, 194, 13, 0x00d0, 0x10, 14, 1), + PIN_FIELD_BASE(195, 195, 13, 0x00d0, 0x10, 19, 1), + PIN_FIELD_BASE(196, 196, 13, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(197, 197, 13, 0x00d0, 0x10, 7, 1), + PIN_FIELD_BASE(198, 198, 13, 0x00d0, 0x10, 15, 1), + PIN_FIELD_BASE(199, 199, 13, 0x00d0, 0x10, 20, 1), + PIN_FIELD_BASE(200, 200, 13, 0x00d0, 0x10, 22, 1), + PIN_FIELD_BASE(201, 201, 13, 0x00d0, 0x10, 25, 1), + PIN_FIELD_BASE(202, 202, 13, 0x00d0, 0x10, 16, 1), + PIN_FIELD_BASE(203, 203, 13, 0x00d0, 0x10, 21, 1), + PIN_FIELD_BASE(204, 204, 13, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(205, 205, 13, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(206, 206, 13, 0x00d0, 0x10, 8, 1), + PIN_FIELD_BASE(207, 207, 13, 0x00d0, 0x10, 9, 1), + PIN_FIELD_BASE(208, 208, 13, 0x00d0, 0x10, 10, 1), + PIN_FIELD_BASE(209, 209, 13, 0x00d0, 0x10, 11, 1), + PIN_FIELD_BASE(210, 210, 14, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(211, 211, 14, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(212, 212, 14, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(213, 213, 14, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(214, 214, 13, 0x00d0, 0x10, 23, 1), + PIN_FIELD_BASE(215, 215, 13, 0x00d0, 0x10, 24, 1), + PIN_FIELD_BASE(216, 216, 14, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(220, 220, 14, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(221, 221, 14, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(222, 222, 14, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(223, 223, 14, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(230, 230, 15, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(231, 231, 15, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(232, 232, 15, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(233, 233, 15, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(234, 234, 15, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(235, 235, 15, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(236, 236, 15, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(237, 237, 15, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(238, 238, 15, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(239, 239, 15, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(240, 240, 15, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(241, 241, 15, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(242, 242, 15, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(243, 243, 15, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(244, 244, 15, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(245, 245, 15, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(246, 246, 15, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(247, 247, 15, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(248, 248, 15, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(249, 249, 15, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(250, 250, 15, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(251, 251, 3, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(252, 252, 3, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(253, 253, 3, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(254, 254, 3, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(255, 255, 3, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(256, 256, 3, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(257, 257, 3, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(258, 258, 3, 0x0090, 0x10, 9, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_pd_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 8, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, 11, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(3, 3, 11, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, 11, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(5, 5, 11, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(6, 6, 11, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(7, 7, 11, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(8, 8, 11, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(9, 9, 9, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(10, 10, 9, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(11, 11, 8, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(12, 12, 9, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(14, 14, 3, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 6, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 6, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, 6, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, 6, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, 3, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 2, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(22, 22, 2, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(23, 23, 2, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(24, 24, 2, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(26, 26, 2, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(27, 27, 2, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, 2, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(29, 29, 2, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(30, 30, 2, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(31, 31, 2, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, 1, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(33, 33, 1, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(34, 34, 1, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(35, 35, 1, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(36, 36, 1, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(37, 37, 1, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(38, 38, 1, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(39, 39, 8, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(40, 40, 8, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(41, 41, 8, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(42, 42, 8, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(43, 43, 8, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(44, 44, 8, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(45, 45, 8, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(46, 46, 8, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(47, 47, 8, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(48, 48, 8, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(49, 49, 8, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(50, 50, 8, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(51, 51, 8, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(52, 52, 9, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(53, 53, 9, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(54, 54, 9, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(55, 55, 9, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(56, 56, 9, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(57, 57, 9, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(58, 58, 9, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(59, 59, 9, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(61, 61, 9, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(62, 62, 9, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(63, 63, 9, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(64, 64, 9, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(65, 65, 9, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(66, 66, 9, 0x00a0, 0x10, 24, 1), + PIN_FIELD_BASE(67, 67, 9, 0x00a0, 0x10, 21, 1), + PIN_FIELD_BASE(68, 68, 9, 0x00a0, 0x10, 20, 1), + PIN_FIELD_BASE(69, 69, 9, 0x00a0, 0x10, 25, 1), + PIN_FIELD_BASE(70, 70, 9, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(71, 71, 9, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(72, 72, 9, 0x00a0, 0x10, 23, 1), + PIN_FIELD_BASE(73, 73, 9, 0x00a0, 0x10, 19, 1), + PIN_FIELD_BASE(74, 74, 9, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(75, 75, 10, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(76, 76, 10, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(77, 77, 10, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(78, 78, 10, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(79, 79, 10, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(80, 80, 10, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(81, 81, 11, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(82, 82, 11, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(83, 83, 11, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(84, 84, 11, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(85, 85, 11, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(86, 86, 11, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(87, 87, 11, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(88, 88, 11, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(89, 89, 11, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(90, 90, 11, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(91, 91, 12, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(92, 92, 12, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(93, 93, 12, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(94, 94, 12, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(95, 95, 12, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(96, 96, 12, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(97, 97, 12, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(98, 98, 12, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(99, 99, 12, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(100, 100, 12, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(101, 101, 12, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(102, 102, 12, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(103, 103, 12, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, 12, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(105, 105, 12, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(106, 106, 5, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 5, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(108, 108, 5, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(109, 109, 5, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(110, 110, 5, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(111, 111, 5, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(112, 112, 5, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(113, 113, 5, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(114, 114, 5, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(115, 115, 5, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(116, 116, 5, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(117, 117, 5, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(118, 118, 6, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(119, 119, 6, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(120, 120, 6, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(121, 121, 6, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(122, 122, 6, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, 6, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(124, 124, 6, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(157, 157, 2, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(158, 158, 2, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(159, 159, 2, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(160, 160, 3, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(161, 161, 3, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(162, 162, 3, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(163, 163, 3, 0x0080, 0x10, 21, 1), + PIN_FIELD_BASE(164, 164, 3, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(165, 165, 3, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(166, 166, 3, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(167, 167, 3, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(168, 168, 3, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(169, 169, 3, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(170, 170, 3, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(171, 171, 3, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(172, 172, 3, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(173, 173, 3, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(174, 174, 1, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(175, 175, 1, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(176, 176, 1, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(177, 177, 1, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(178, 178, 1, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 1, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(180, 180, 1, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(181, 181, 1, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(182, 182, 1, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(183, 183, 1, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(184, 184, 1, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(185, 185, 1, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(186, 186, 13, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(187, 187, 13, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(188, 188, 13, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(189, 189, 13, 0x00c0, 0x10, 17, 1), + PIN_FIELD_BASE(190, 190, 13, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(191, 191, 13, 0x00c0, 0x10, 18, 1), + PIN_FIELD_BASE(192, 192, 13, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 13, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(194, 194, 13, 0x00c0, 0x10, 14, 1), + PIN_FIELD_BASE(195, 195, 13, 0x00c0, 0x10, 19, 1), + PIN_FIELD_BASE(196, 196, 13, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(197, 197, 13, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(198, 198, 13, 0x00c0, 0x10, 15, 1), + PIN_FIELD_BASE(199, 199, 13, 0x00c0, 0x10, 20, 1), + PIN_FIELD_BASE(200, 200, 13, 0x00c0, 0x10, 22, 1), + PIN_FIELD_BASE(201, 201, 13, 0x00c0, 0x10, 25, 1), + PIN_FIELD_BASE(202, 202, 13, 0x00c0, 0x10, 16, 1), + PIN_FIELD_BASE(203, 203, 13, 0x00c0, 0x10, 21, 1), + PIN_FIELD_BASE(204, 204, 13, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(205, 205, 13, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(206, 206, 13, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(207, 207, 13, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(208, 208, 13, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(209, 209, 13, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(210, 210, 14, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(211, 211, 14, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(212, 212, 14, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(213, 213, 14, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(214, 214, 13, 0x00c0, 0x10, 23, 1), + PIN_FIELD_BASE(215, 215, 13, 0x00c0, 0x10, 24, 1), + PIN_FIELD_BASE(216, 216, 14, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(220, 220, 14, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(221, 221, 14, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(222, 222, 14, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(223, 223, 14, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(230, 230, 15, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(231, 231, 15, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(232, 232, 15, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(233, 233, 15, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(234, 234, 15, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(235, 235, 15, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(236, 236, 15, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(237, 237, 15, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(238, 238, 15, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(239, 239, 15, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(240, 240, 15, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(241, 241, 15, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(242, 242, 15, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(243, 243, 15, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(244, 244, 15, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(245, 245, 15, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(246, 246, 15, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(247, 247, 15, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(248, 248, 15, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(249, 249, 15, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(250, 250, 15, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(251, 251, 3, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(252, 252, 3, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(253, 253, 3, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(254, 254, 3, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(255, 255, 3, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(256, 256, 3, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(257, 257, 3, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(258, 258, 3, 0x0080, 0x10, 9, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(1, 1, 8, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(2, 2, 11, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(3, 3, 11, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(4, 4, 11, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(5, 5, 11, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(6, 6, 11, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(7, 7, 11, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(8, 8, 11, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(9, 9, 9, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(10, 10, 9, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(11, 11, 8, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(12, 12, 9, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(13, 13, 6, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(14, 14, 3, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(15, 15, 6, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(16, 16, 6, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(17, 17, 6, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(18, 18, 6, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(19, 19, 6, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(20, 20, 3, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(21, 21, 2, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(22, 22, 2, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(23, 23, 2, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(24, 24, 2, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(25, 25, 2, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(26, 26, 2, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(27, 27, 2, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(28, 28, 2, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(29, 29, 2, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(30, 30, 2, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(31, 31, 2, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(32, 32, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(33, 33, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(34, 34, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(35, 35, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(36, 36, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(37, 37, 1, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(38, 38, 1, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(39, 39, 8, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(40, 40, 8, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(41, 41, 8, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(42, 42, 8, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(43, 43, 8, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(44, 44, 8, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(45, 45, 8, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(46, 46, 8, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(47, 47, 8, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(48, 48, 8, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(49, 49, 8, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(50, 50, 8, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(51, 51, 8, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(52, 52, 9, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(53, 53, 9, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(54, 54, 9, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(55, 55, 9, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(56, 56, 9, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(57, 57, 9, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(58, 58, 9, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(59, 59, 9, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(60, 60, 9, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(61, 61, 9, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(62, 62, 9, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(63, 63, 9, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(64, 64, 9, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(65, 65, 9, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(66, 66, 9, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(67, 67, 9, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(68, 68, 9, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(69, 69, 9, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(70, 70, 9, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(71, 71, 9, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(72, 72, 9, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(73, 73, 9, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(74, 74, 9, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(75, 75, 10, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(76, 76, 10, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(77, 77, 10, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(78, 78, 10, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(79, 79, 10, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(80, 80, 10, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(81, 81, 11, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(82, 82, 11, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(83, 83, 11, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(84, 84, 11, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(85, 85, 11, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(86, 86, 11, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(87, 87, 11, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(88, 88, 11, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(89, 89, 11, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(90, 90, 11, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(91, 91, 12, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(92, 92, 12, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(93, 93, 12, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(94, 94, 12, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(95, 95, 12, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(96, 96, 12, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(97, 97, 12, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(98, 98, 12, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(99, 99, 12, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(100, 100, 12, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(101, 101, 12, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(102, 102, 12, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(103, 103, 12, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(104, 104, 12, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(105, 105, 12, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(106, 106, 5, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(107, 107, 5, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(108, 108, 5, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(109, 109, 5, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(110, 110, 5, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(111, 111, 5, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(112, 112, 5, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(113, 113, 5, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(114, 114, 5, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(115, 115, 5, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(116, 116, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(117, 117, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(118, 118, 6, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(119, 119, 6, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(120, 120, 6, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(121, 121, 6, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(122, 122, 6, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(123, 123, 6, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(124, 124, 6, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(125, 125, 7, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(126, 126, 7, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(127, 127, 7, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(128, 128, 7, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(129, 129, 7, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(130, 130, 7, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(131, 131, 7, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(132, 132, 7, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(133, 133, 7, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(134, 134, 7, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(135, 135, 7, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(136, 136, 7, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(137, 137, 4, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(138, 138, 4, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(139, 139, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(140, 140, 4, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(141, 141, 4, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(142, 142, 4, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(143, 143, 4, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(144, 144, 4, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(145, 145, 4, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(146, 146, 4, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(147, 147, 4, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(148, 148, 4, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(149, 149, 4, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(150, 150, 4, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(151, 151, 4, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(152, 152, 4, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(153, 153, 4, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(154, 154, 4, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(155, 155, 4, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(156, 156, 4, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(157, 157, 2, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(158, 158, 2, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(159, 159, 2, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(160, 160, 3, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(161, 161, 3, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(162, 162, 3, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(163, 163, 3, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(164, 164, 3, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(165, 165, 3, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(166, 166, 3, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(167, 167, 3, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(168, 168, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(169, 169, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(170, 170, 3, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(171, 171, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(172, 172, 3, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(173, 173, 3, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(174, 174, 1, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(175, 175, 1, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(176, 176, 1, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(177, 177, 1, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(178, 178, 1, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(179, 179, 1, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(180, 180, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(181, 181, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(182, 182, 1, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(183, 183, 1, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(184, 184, 1, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(185, 185, 1, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(186, 186, 13, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(187, 187, 13, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(188, 188, 13, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(189, 189, 13, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(190, 190, 13, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(191, 191, 13, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(192, 192, 13, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(193, 193, 13, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(194, 194, 13, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(195, 195, 13, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(196, 196, 13, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(197, 197, 13, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(198, 198, 13, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(199, 199, 13, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(200, 200, 13, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(201, 201, 13, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(202, 202, 13, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(203, 203, 13, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(204, 204, 13, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(205, 205, 13, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(206, 206, 13, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(207, 207, 13, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(208, 208, 13, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(209, 209, 13, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(210, 210, 14, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(211, 211, 14, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(212, 212, 14, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(213, 213, 14, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(214, 214, 13, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(215, 215, 13, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(216, 216, 14, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(217, 217, 14, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(218, 218, 14, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(219, 219, 14, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(220, 220, 14, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(221, 221, 14, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(222, 222, 14, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(223, 223, 14, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(224, 224, 14, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(225, 225, 14, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(226, 226, 14, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(227, 227, 14, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(228, 228, 14, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(229, 229, 14, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(230, 230, 15, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(231, 231, 15, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(232, 232, 15, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(233, 233, 15, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(234, 234, 15, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(235, 235, 15, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(236, 236, 15, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(237, 237, 15, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(238, 238, 15, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(239, 239, 15, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(240, 240, 15, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(241, 241, 15, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(242, 242, 15, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(243, 243, 15, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(244, 244, 15, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(245, 245, 15, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(246, 246, 15, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(247, 247, 15, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(248, 248, 15, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(249, 249, 15, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(250, 250, 15, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(251, 251, 3, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(252, 252, 3, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(253, 253, 3, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(254, 254, 3, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(255, 255, 3, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(256, 256, 3, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(257, 257, 3, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(258, 258, 3, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(259, 259, 14, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(260, 260, 14, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(261, 261, 14, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(262, 262, 14, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(263, 263, 14, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(264, 264, 14, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(265, 265, 14, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(266, 266, 14, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(267, 267, 15, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(268, 268, 15, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(269, 269, 15, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(270, 270, 15, 0x0000, 0x10, 21, 3), +}; + +static const struct mtk_pin_field_calc mt8196_pin_drv_adv_range[] = { + PIN_FIELD_BASE(46, 46, 8, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(47, 47, 8, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(48, 48, 8, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(49, 49, 8, 0x0030, 0x10, 12, 3), + PIN_FIELD_BASE(50, 50, 8, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(51, 51, 8, 0x0030, 0x10, 15, 3), + PIN_FIELD_BASE(52, 52, 9, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(53, 53, 9, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(75, 75, 10, 0x0020, 0x10, 0, 5), + PIN_FIELD_BASE(76, 76, 10, 0x0020, 0x10, 5, 5), + PIN_FIELD_BASE(77, 77, 10, 0x0020, 0x10, 10, 5), + PIN_FIELD_BASE(78, 78, 10, 0x0020, 0x10, 15, 5), + PIN_FIELD_BASE(99, 99, 12, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(100, 100, 12, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(101, 101, 12, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(102, 102, 12, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(104, 104, 12, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(105, 105, 12, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(123, 123, 6, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(124, 124, 6, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(164, 164, 3, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(165, 165, 3, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(166, 166, 3, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(167, 167, 3, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(168, 168, 3, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(170, 170, 3, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(176, 176, 1, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(177, 177, 1, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(188, 188, 13, 0x0040, 0x10, 0, 3), + PIN_FIELD_BASE(189, 189, 13, 0x0040, 0x10, 15, 3), + PIN_FIELD_BASE(190, 190, 13, 0x0040, 0x10, 3, 3), + PIN_FIELD_BASE(191, 191, 13, 0x0040, 0x10, 18, 3), + PIN_FIELD_BASE(194, 194, 13, 0x0040, 0x10, 6, 3), + PIN_FIELD_BASE(195, 195, 13, 0x0040, 0x10, 21, 3), + PIN_FIELD_BASE(198, 198, 13, 0x0040, 0x10, 9, 3), + PIN_FIELD_BASE(199, 199, 13, 0x0040, 0x10, 24, 3), + PIN_FIELD_BASE(200, 200, 13, 0x0050, 0x10, 0, 3), + PIN_FIELD_BASE(201, 201, 13, 0x0050, 0x10, 9, 3), + PIN_FIELD_BASE(202, 202, 13, 0x0040, 0x10, 12, 3), + PIN_FIELD_BASE(203, 203, 13, 0x0040, 0x10, 27, 3), + PIN_FIELD_BASE(214, 214, 13, 0x0050, 0x10, 3, 3), + PIN_FIELD_BASE(215, 215, 13, 0x0050, 0x10, 6, 3), +}; + +static const struct mtk_pin_field_calc mt8196_pin_rsel_range[] = { + PIN_FIELD_BASE(46, 46, 8, 0x00c0, 0x10, 0, 3), + PIN_FIELD_BASE(47, 47, 8, 0x00c0, 0x10, 9, 3), + PIN_FIELD_BASE(48, 48, 8, 0x00c0, 0x10, 3, 3), + PIN_FIELD_BASE(49, 49, 8, 0x00c0, 0x10, 12, 3), + PIN_FIELD_BASE(50, 50, 8, 0x00c0, 0x10, 6, 3), + PIN_FIELD_BASE(51, 51, 8, 0x00c0, 0x10, 15, 3), + PIN_FIELD_BASE(52, 52, 9, 0x0110, 0x10, 0, 3), + PIN_FIELD_BASE(53, 53, 9, 0x0110, 0x10, 3, 3), + PIN_FIELD_BASE(99, 99, 12, 0x00b0, 0x10, 0, 3), + PIN_FIELD_BASE(100, 100, 12, 0x00b0, 0x10, 9, 3), + PIN_FIELD_BASE(101, 101, 12, 0x00b0, 0x10, 3, 3), + PIN_FIELD_BASE(102, 102, 12, 0x00b0, 0x10, 12, 3), + PIN_FIELD_BASE(104, 104, 12, 0x00b0, 0x10, 6, 3), + PIN_FIELD_BASE(105, 105, 12, 0x00b0, 0x10, 15, 3), + PIN_FIELD_BASE(123, 123, 6, 0x0100, 0x10, 0, 3), + PIN_FIELD_BASE(124, 124, 6, 0x0100, 0x10, 3, 3), + PIN_FIELD_BASE(164, 164, 3, 0x00b0, 0x10, 0, 3), + PIN_FIELD_BASE(165, 165, 3, 0x00b0, 0x10, 6, 3), + PIN_FIELD_BASE(166, 166, 3, 0x00b0, 0x10, 3, 3), + PIN_FIELD_BASE(167, 167, 3, 0x00b0, 0x10, 9, 3), + PIN_FIELD_BASE(168, 168, 3, 0x00b0, 0x10, 12, 3), + PIN_FIELD_BASE(170, 170, 3, 0x00b0, 0x10, 15, 3), + PIN_FIELD_BASE(176, 176, 1, 0x00b0, 0x10, 0, 3), + PIN_FIELD_BASE(177, 177, 1, 0x00b0, 0x10, 3, 3), + PIN_FIELD_BASE(188, 188, 13, 0x00f0, 0x10, 0, 3), + PIN_FIELD_BASE(189, 189, 13, 0x00f0, 0x10, 15, 3), + PIN_FIELD_BASE(190, 190, 13, 0x00f0, 0x10, 3, 3), + PIN_FIELD_BASE(191, 191, 13, 0x00f0, 0x10, 18, 3), + PIN_FIELD_BASE(194, 194, 13, 0x00f0, 0x10, 6, 3), + PIN_FIELD_BASE(195, 195, 13, 0x00f0, 0x10, 21, 3), + PIN_FIELD_BASE(198, 198, 13, 0x00f0, 0x10, 9, 3), + PIN_FIELD_BASE(199, 199, 13, 0x00f0, 0x10, 24, 3), + PIN_FIELD_BASE(200, 200, 13, 0x0100, 0x10, 0, 3), + PIN_FIELD_BASE(201, 201, 13, 0x0100, 0x10, 9, 3), + PIN_FIELD_BASE(202, 202, 13, 0x00f0, 0x10, 12, 3), + PIN_FIELD_BASE(203, 203, 13, 0x00f0, 0x10, 27, 3), + PIN_FIELD_BASE(214, 214, 13, 0x0100, 0x10, 3, 3), + PIN_FIELD_BASE(215, 215, 13, 0x0100, 0x10, 6, 3), +}; + +static const struct mtk_pin_rsel mt8196_pin_rsel_val_range[] = { + PIN_RSEL(46, 53, 0x0, 75000, 75000), + PIN_RSEL(46, 53, 0x1, 10000, 5000), + PIN_RSEL(46, 53, 0x2, 5000, 75000), + PIN_RSEL(46, 53, 0x3, 4000, 5000), + PIN_RSEL(46, 53, 0x4, 3000, 75000), + PIN_RSEL(46, 53, 0x5, 2000, 5000), + PIN_RSEL(46, 53, 0x6, 1500, 75000), + PIN_RSEL(46, 53, 0x7, 1000, 5000), + PIN_RSEL(99, 102, 0x0, 75000, 75000), + PIN_RSEL(99, 102, 0x1, 10000, 5000), + PIN_RSEL(99, 102, 0x2, 5000, 75000), + PIN_RSEL(99, 102, 0x3, 4000, 5000), + PIN_RSEL(99, 102, 0x4, 3000, 75000), + PIN_RSEL(99, 102, 0x5, 2000, 5000), + PIN_RSEL(99, 102, 0x6, 1500, 75000), + PIN_RSEL(99, 102, 0x7, 1000, 5000), + PIN_RSEL(104, 105, 0x0, 75000, 75000), + PIN_RSEL(104, 105, 0x1, 10000, 5000), + PIN_RSEL(104, 105, 0x2, 5000, 75000), + PIN_RSEL(104, 105, 0x3, 4000, 5000), + PIN_RSEL(104, 105, 0x4, 3000, 75000), + PIN_RSEL(104, 105, 0x5, 2000, 5000), + PIN_RSEL(104, 105, 0x6, 1500, 75000), + PIN_RSEL(104, 105, 0x7, 1000, 5000), + PIN_RSEL(123, 124, 0x0, 75000, 75000), + PIN_RSEL(123, 124, 0x1, 10000, 5000), + PIN_RSEL(123, 124, 0x2, 5000, 75000), + PIN_RSEL(123, 124, 0x3, 4000, 5000), + PIN_RSEL(123, 124, 0x4, 3000, 75000), + PIN_RSEL(123, 124, 0x5, 2000, 5000), + PIN_RSEL(123, 124, 0x6, 1500, 75000), + PIN_RSEL(123, 124, 0x7, 1000, 5000), + PIN_RSEL(164, 168, 0x0, 75000, 75000), + PIN_RSEL(164, 168, 0x1, 10000, 5000), + PIN_RSEL(164, 168, 0x2, 5000, 75000), + PIN_RSEL(164, 168, 0x3, 4000, 5000), + PIN_RSEL(164, 168, 0x4, 3000, 75000), + PIN_RSEL(164, 168, 0x5, 2000, 5000), + PIN_RSEL(164, 168, 0x6, 1500, 75000), + PIN_RSEL(164, 168, 0x7, 1000, 5000), + PIN_RSEL(170, 170, 0x0, 75000, 75000), + PIN_RSEL(170, 170, 0x1, 10000, 5000), + PIN_RSEL(170, 170, 0x2, 5000, 75000), + PIN_RSEL(170, 170, 0x3, 4000, 5000), + PIN_RSEL(170, 170, 0x4, 3000, 75000), + PIN_RSEL(170, 170, 0x5, 2000, 5000), + PIN_RSEL(170, 170, 0x6, 1500, 75000), + PIN_RSEL(170, 170, 0x7, 1000, 5000), + PIN_RSEL(176, 177, 0x0, 75000, 75000), + PIN_RSEL(176, 177, 0x1, 10000, 5000), + PIN_RSEL(176, 177, 0x2, 5000, 75000), + PIN_RSEL(176, 177, 0x3, 4000, 5000), + PIN_RSEL(176, 177, 0x4, 3000, 75000), + PIN_RSEL(176, 177, 0x5, 2000, 5000), + PIN_RSEL(176, 177, 0x6, 1500, 75000), + PIN_RSEL(176, 177, 0x7, 1000, 5000), + PIN_RSEL(188, 191, 0x0, 75000, 75000), + PIN_RSEL(188, 191, 0x1, 10000, 5000), + PIN_RSEL(188, 191, 0x2, 5000, 75000), + PIN_RSEL(188, 191, 0x3, 4000, 5000), + PIN_RSEL(188, 191, 0x4, 3000, 75000), + PIN_RSEL(188, 191, 0x5, 2000, 5000), + PIN_RSEL(188, 191, 0x6, 1500, 75000), + PIN_RSEL(188, 191, 0x7, 1000, 5000), + PIN_RSEL(194, 195, 0x0, 75000, 75000), + PIN_RSEL(194, 195, 0x1, 10000, 5000), + PIN_RSEL(194, 195, 0x2, 5000, 75000), + PIN_RSEL(194, 195, 0x3, 4000, 5000), + PIN_RSEL(194, 195, 0x4, 3000, 75000), + PIN_RSEL(194, 195, 0x5, 2000, 5000), + PIN_RSEL(194, 195, 0x6, 1500, 75000), + PIN_RSEL(194, 195, 0x7, 1000, 5000), + PIN_RSEL(198, 203, 0x0, 75000, 75000), + PIN_RSEL(198, 203, 0x1, 10000, 5000), + PIN_RSEL(198, 203, 0x2, 5000, 75000), + PIN_RSEL(198, 203, 0x3, 4000, 5000), + PIN_RSEL(198, 203, 0x4, 3000, 75000), + PIN_RSEL(198, 203, 0x5, 2000, 5000), + PIN_RSEL(198, 203, 0x6, 1500, 75000), + PIN_RSEL(198, 203, 0x7, 1000, 5000), + PIN_RSEL(214, 215, 0x0, 75000, 75000), + PIN_RSEL(214, 215, 0x1, 10000, 5000), + PIN_RSEL(214, 215, 0x2, 5000, 75000), + PIN_RSEL(214, 215, 0x3, 4000, 5000), + PIN_RSEL(214, 215, 0x4, 3000, 75000), + PIN_RSEL(214, 215, 0x5, 2000, 5000), + PIN_RSEL(214, 215, 0x6, 1500, 75000), + PIN_RSEL(214, 215, 0x7, 1000, 5000), +}; + +static const unsigned int mt8196_pull_type[] = { + MTK_PULL_PU_PD_TYPE,/*0*/ MTK_PULL_PU_PD_TYPE,/*1*/ + MTK_PULL_PU_PD_TYPE,/*2*/ MTK_PULL_PU_PD_TYPE,/*3*/ + MTK_PULL_PU_PD_TYPE,/*4*/ MTK_PULL_PU_PD_TYPE,/*5*/ + MTK_PULL_PU_PD_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE,/*7*/ + MTK_PULL_PU_PD_TYPE,/*8*/ MTK_PULL_PU_PD_TYPE,/*9*/ + MTK_PULL_PU_PD_TYPE,/*10*/ MTK_PULL_PU_PD_TYPE,/*11*/ + MTK_PULL_PU_PD_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE,/*13*/ + MTK_PULL_PU_PD_TYPE,/*14*/ MTK_PULL_PU_PD_TYPE,/*15*/ + MTK_PULL_PU_PD_TYPE,/*16*/ MTK_PULL_PU_PD_TYPE,/*17*/ + MTK_PULL_PU_PD_TYPE,/*18*/ MTK_PULL_PU_PD_TYPE,/*19*/ + MTK_PULL_PU_PD_TYPE,/*20*/ MTK_PULL_PU_PD_TYPE,/*21*/ + MTK_PULL_PU_PD_TYPE,/*22*/ MTK_PULL_PU_PD_TYPE,/*23*/ + MTK_PULL_PU_PD_TYPE,/*24*/ MTK_PULL_PU_PD_TYPE,/*25*/ + MTK_PULL_PU_PD_TYPE,/*26*/ MTK_PULL_PU_PD_TYPE,/*27*/ + MTK_PULL_PU_PD_TYPE,/*28*/ MTK_PULL_PU_PD_TYPE,/*29*/ + MTK_PULL_PU_PD_TYPE,/*30*/ MTK_PULL_PU_PD_TYPE,/*31*/ + MTK_PULL_PU_PD_TYPE,/*32*/ MTK_PULL_PU_PD_TYPE,/*33*/ + MTK_PULL_PU_PD_TYPE,/*34*/ MTK_PULL_PU_PD_TYPE,/*35*/ + MTK_PULL_PU_PD_TYPE,/*36*/ MTK_PULL_PU_PD_TYPE,/*37*/ + MTK_PULL_PU_PD_TYPE,/*38*/ MTK_PULL_PU_PD_TYPE,/*39*/ + MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/ + MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/ + MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*46*/ MTK_PULL_PU_PD_RSEL_TYPE,/*47*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*48*/ MTK_PULL_PU_PD_RSEL_TYPE,/*49*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*50*/ MTK_PULL_PU_PD_RSEL_TYPE,/*51*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*52*/ MTK_PULL_PU_PD_RSEL_TYPE,/*53*/ + MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/ + MTK_PULL_PU_PD_TYPE,/*56*/ MTK_PULL_PU_PD_TYPE,/*57*/ + MTK_PULL_PU_PD_TYPE,/*58*/ MTK_PULL_PU_PD_TYPE,/*59*/ + MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PU_PD_TYPE,/*61*/ + MTK_PULL_PU_PD_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE,/*63*/ + MTK_PULL_PU_PD_TYPE,/*64*/ MTK_PULL_PU_PD_TYPE,/*65*/ + MTK_PULL_PU_PD_TYPE,/*66*/ MTK_PULL_PU_PD_TYPE,/*67*/ + MTK_PULL_PU_PD_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ + MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ + MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ + MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ + MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ + MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ + MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ + MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ + MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ + MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ + MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ + MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ + MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ + MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ + MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ + MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_RSEL_TYPE,/*99*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*100*/ MTK_PULL_PU_PD_RSEL_TYPE,/*101*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*102*/ MTK_PULL_PU_PD_TYPE,/*103*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*104*/ MTK_PULL_PU_PD_RSEL_TYPE,/*105*/ + MTK_PULL_PU_PD_TYPE,/*106*/ MTK_PULL_PU_PD_TYPE,/*107*/ + MTK_PULL_PU_PD_TYPE,/*108*/ MTK_PULL_PU_PD_TYPE,/*109*/ + MTK_PULL_PU_PD_TYPE,/*110*/ MTK_PULL_PU_PD_TYPE,/*111*/ + MTK_PULL_PU_PD_TYPE,/*112*/ MTK_PULL_PU_PD_TYPE,/*113*/ + MTK_PULL_PU_PD_TYPE,/*114*/ MTK_PULL_PU_PD_TYPE,/*115*/ + MTK_PULL_PU_PD_TYPE,/*116*/ MTK_PULL_PU_PD_TYPE,/*117*/ + MTK_PULL_PU_PD_TYPE,/*118*/ MTK_PULL_PU_PD_TYPE,/*119*/ + MTK_PULL_PU_PD_TYPE,/*120*/ MTK_PULL_PU_PD_TYPE,/*121*/ + MTK_PULL_PU_PD_TYPE,/*122*/ MTK_PULL_PU_PD_RSEL_TYPE,/*123*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*124*/ MTK_PULL_PUPD_R1R0_TYPE,/*125*/ + MTK_PULL_PUPD_R1R0_TYPE,/*126*/ MTK_PULL_PUPD_R1R0_TYPE,/*127*/ + MTK_PULL_PUPD_R1R0_TYPE,/*128*/ MTK_PULL_PUPD_R1R0_TYPE,/*129*/ + MTK_PULL_PUPD_R1R0_TYPE,/*130*/ MTK_PULL_PUPD_R1R0_TYPE,/*131*/ + MTK_PULL_PUPD_R1R0_TYPE,/*132*/ MTK_PULL_PUPD_R1R0_TYPE,/*133*/ + MTK_PULL_PUPD_R1R0_TYPE,/*134*/ MTK_PULL_PUPD_R1R0_TYPE,/*135*/ + MTK_PULL_PUPD_R1R0_TYPE,/*136*/ MTK_PULL_PUPD_R1R0_TYPE,/*137*/ + MTK_PULL_PUPD_R1R0_TYPE,/*138*/ MTK_PULL_PUPD_R1R0_TYPE,/*139*/ + MTK_PULL_PUPD_R1R0_TYPE,/*140*/ MTK_PULL_PUPD_R1R0_TYPE,/*141*/ + MTK_PULL_PUPD_R1R0_TYPE,/*142*/ MTK_PULL_PUPD_R1R0_TYPE,/*143*/ + MTK_PULL_PUPD_R1R0_TYPE,/*144*/ MTK_PULL_PUPD_R1R0_TYPE,/*145*/ + MTK_PULL_PUPD_R1R0_TYPE,/*146*/ MTK_PULL_PUPD_R1R0_TYPE,/*147*/ + MTK_PULL_PUPD_R1R0_TYPE,/*148*/ MTK_PULL_PUPD_R1R0_TYPE,/*149*/ + MTK_PULL_PUPD_R1R0_TYPE,/*150*/ MTK_PULL_PUPD_R1R0_TYPE,/*151*/ + MTK_PULL_PUPD_R1R0_TYPE,/*152*/ MTK_PULL_PUPD_R1R0_TYPE,/*153*/ + MTK_PULL_PUPD_R1R0_TYPE,/*154*/ MTK_PULL_PUPD_R1R0_TYPE,/*155*/ + MTK_PULL_PUPD_R1R0_TYPE,/*156*/ MTK_PULL_PU_PD_TYPE,/*157*/ + MTK_PULL_PU_PD_TYPE,/*158*/ MTK_PULL_PU_PD_TYPE,/*159*/ + MTK_PULL_PU_PD_TYPE,/*160*/ MTK_PULL_PU_PD_TYPE,/*161*/ + MTK_PULL_PU_PD_TYPE,/*162*/ MTK_PULL_PU_PD_TYPE,/*163*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*164*/ MTK_PULL_PU_PD_RSEL_TYPE,/*165*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*166*/ MTK_PULL_PU_PD_RSEL_TYPE,/*167*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*168*/ MTK_PULL_PU_PD_TYPE,/*169*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*170*/ MTK_PULL_PU_PD_TYPE,/*171*/ + MTK_PULL_PU_PD_TYPE,/*172*/ MTK_PULL_PU_PD_TYPE,/*173*/ + MTK_PULL_PU_PD_TYPE,/*174*/ MTK_PULL_PU_PD_TYPE,/*175*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*176*/ MTK_PULL_PU_PD_RSEL_TYPE,/*177*/ + MTK_PULL_PU_PD_TYPE,/*178*/ MTK_PULL_PU_PD_TYPE,/*179*/ + MTK_PULL_PU_PD_TYPE,/*180*/ MTK_PULL_PU_PD_TYPE,/*181*/ + MTK_PULL_PU_PD_TYPE,/*182*/ MTK_PULL_PU_PD_TYPE,/*183*/ + MTK_PULL_PU_PD_TYPE,/*184*/ MTK_PULL_PU_PD_TYPE,/*185*/ + MTK_PULL_PU_PD_TYPE,/*186*/ MTK_PULL_PU_PD_TYPE,/*187*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*188*/ MTK_PULL_PU_PD_RSEL_TYPE,/*189*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*190*/ MTK_PULL_PU_PD_RSEL_TYPE,/*191*/ + MTK_PULL_PU_PD_TYPE,/*192*/ MTK_PULL_PU_PD_TYPE,/*193*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*194*/ MTK_PULL_PU_PD_RSEL_TYPE,/*195*/ + MTK_PULL_PU_PD_TYPE,/*196*/ MTK_PULL_PU_PD_TYPE,/*197*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*198*/ MTK_PULL_PU_PD_RSEL_TYPE,/*199*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*200*/ MTK_PULL_PU_PD_RSEL_TYPE,/*201*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*202*/ MTK_PULL_PU_PD_RSEL_TYPE,/*203*/ + MTK_PULL_PU_PD_TYPE,/*204*/ MTK_PULL_PU_PD_TYPE,/*205*/ + MTK_PULL_PU_PD_TYPE,/*206*/ MTK_PULL_PU_PD_TYPE,/*207*/ + MTK_PULL_PU_PD_TYPE,/*208*/ MTK_PULL_PU_PD_TYPE,/*209*/ + MTK_PULL_PU_PD_TYPE,/*210*/ MTK_PULL_PU_PD_TYPE,/*211*/ + MTK_PULL_PU_PD_TYPE,/*212*/ MTK_PULL_PU_PD_TYPE,/*213*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*214*/ MTK_PULL_PU_PD_RSEL_TYPE,/*215*/ + MTK_PULL_PU_PD_TYPE,/*216*/ MTK_PULL_PUPD_R1R0_TYPE,/*217*/ + MTK_PULL_PUPD_R1R0_TYPE,/*218*/ MTK_PULL_PUPD_R1R0_TYPE,/*219*/ + MTK_PULL_PU_PD_TYPE,/*220*/ MTK_PULL_PU_PD_TYPE,/*221*/ + MTK_PULL_PU_PD_TYPE,/*222*/ MTK_PULL_PU_PD_TYPE,/*223*/ + MTK_PULL_PUPD_R1R0_TYPE,/*224*/ MTK_PULL_PUPD_R1R0_TYPE,/*225*/ + MTK_PULL_PUPD_R1R0_TYPE,/*226*/ MTK_PULL_PUPD_R1R0_TYPE,/*227*/ + MTK_PULL_PUPD_R1R0_TYPE,/*228*/ MTK_PULL_PUPD_R1R0_TYPE,/*229*/ + MTK_PULL_PU_PD_TYPE,/*230*/ MTK_PULL_PU_PD_TYPE,/*231*/ + MTK_PULL_PU_PD_TYPE,/*232*/ MTK_PULL_PU_PD_TYPE,/*233*/ + MTK_PULL_PU_PD_TYPE,/*234*/ MTK_PULL_PU_PD_TYPE,/*235*/ + MTK_PULL_PU_PD_TYPE,/*236*/ MTK_PULL_PU_PD_TYPE,/*237*/ + MTK_PULL_PU_PD_TYPE,/*238*/ MTK_PULL_PU_PD_TYPE,/*239*/ + MTK_PULL_PU_PD_TYPE,/*240*/ MTK_PULL_PU_PD_TYPE,/*241*/ + MTK_PULL_PU_PD_TYPE,/*242*/ MTK_PULL_PU_PD_TYPE,/*243*/ + MTK_PULL_PU_PD_TYPE,/*244*/ MTK_PULL_PU_PD_TYPE,/*245*/ + MTK_PULL_PU_PD_TYPE,/*246*/ MTK_PULL_PU_PD_TYPE,/*247*/ + MTK_PULL_PU_PD_TYPE,/*248*/ MTK_PULL_PU_PD_TYPE,/*249*/ + MTK_PULL_PU_PD_TYPE,/*250*/ MTK_PULL_PU_PD_TYPE,/*251*/ + MTK_PULL_PU_PD_TYPE,/*252*/ MTK_PULL_PU_PD_TYPE,/*253*/ + MTK_PULL_PU_PD_TYPE,/*254*/ MTK_PULL_PU_PD_TYPE,/*255*/ + MTK_PULL_PU_PD_TYPE,/*256*/ MTK_PULL_PU_PD_TYPE,/*257*/ + MTK_PULL_PU_PD_TYPE,/*258*/ MTK_PULL_PUPD_R1R0_TYPE,/*259*/ + MTK_PULL_PUPD_R1R0_TYPE,/*260*/ MTK_PULL_PUPD_R1R0_TYPE,/*261*/ + MTK_PULL_PUPD_R1R0_TYPE,/*262*/ MTK_PULL_PUPD_R1R0_TYPE,/*263*/ + MTK_PULL_PUPD_R1R0_TYPE,/*264*/ MTK_PULL_PUPD_R1R0_TYPE,/*265*/ + MTK_PULL_PUPD_R1R0_TYPE,/*266*/ MTK_PULL_PUPD_R1R0_TYPE,/*267*/ + MTK_PULL_PUPD_R1R0_TYPE,/*268*/ MTK_PULL_PUPD_R1R0_TYPE,/*269*/ + MTK_PULL_PUPD_R1R0_TYPE,/*270*/ +}; + +static const struct mtk_pin_reg_calc mt8196_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8196_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8196_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8196_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8196_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8196_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8196_pin_ies_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8196_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8196_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8196_pin_r1_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8196_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8196_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8196_pin_drv_range), + [PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8196_pin_drv_adv_range), + [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8196_pin_rsel_range), +}; + +static const char * const mt8196_pinctrl_register_base_names[] = { + "iocfg0", "iocfg_rt", "iocfg_rm1", "iocfg_rm2", + "iocfg_rb", "iocfg_bm1", "iocfg_bm2", "iocfg_bm3", + "iocfg_lt", "iocfg_lm1", "iocfg_lm2", "iocfg_lb1", + "iocfg_lb2", "iocfg_tm1", "iocfg_tm2", "iocfg_tm3", +}; + +static const struct mtk_eint_hw mt8196_eint_hw = { + .port_mask = 0xf, + .ports = 3, + .ap_num = 293, + .db_cnt = 32, + .db_time = debounce_time_mt6765, +}; + +static const struct mtk_pin_soc mt8196_data = { + .reg_cal = mt8196_reg_cals, + .pins = mtk_pins_mt8196, + .npins = ARRAY_SIZE(mtk_pins_mt8196), + .ngrps = ARRAY_SIZE(mtk_pins_mt8196), + .eint_hw = &mt8196_eint_hw, + .eint_pin = eint_pins_mt8196, + .nfuncs = 8, + .gpio_m = 0, + .base_names = mt8196_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt8196_pinctrl_register_base_names), + .pull_type = mt8196_pull_type, + .pin_rsel = mt8196_pin_rsel_val_range, + .npin_rsel = ARRAY_SIZE(mt8196_pin_rsel_val_range), + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_drive_get = mtk_pinconf_adv_drive_get_raw, + .adv_drive_set = mtk_pinconf_adv_drive_set_raw, +}; + +static const struct of_device_id mt8196_pinctrl_of_match[] = { + { .compatible = "mediatek,mt8196-pinctrl", .data = &mt8196_data }, + { /* sentinel */ } +}; + +static struct platform_driver mt8196_pinctrl_driver = { + .driver = { + .name = "mt8196-pinctrl", + .of_match_table = mt8196_pinctrl_of_match, + .pm = pm_sleep_ptr(&mtk_paris_pinctrl_pm_ops), + }, + .probe = mtk_paris_pinctrl_probe, +}; + +static int __init mt8196_pinctrl_init(void) +{ + return platform_driver_register(&mt8196_pinctrl_driver); +} +arch_initcall(mt8196_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8196 Pinctrl Driver"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index 00e95682b9f8..4918d38abfc2 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -13,6 +13,7 @@ #include <linux/platform_device.h> #include <linux/io.h> #include <linux/module.h> +#include <linux/of_address.h> #include <linux/of_irq.h> #include "mtk-eint.h" @@ -367,7 +368,7 @@ static const struct mtk_eint_xt mtk_eint_xt = { int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; - int ret; + int ret, i, j, count_reg_names; if (!IS_ENABLED(CONFIG_EINT_MTK)) return 0; @@ -379,10 +380,27 @@ int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) if (!hw->eint) return -ENOMEM; - hw->eint->base = devm_platform_ioremap_resource_byname(pdev, "eint"); - if (IS_ERR(hw->eint->base)) { - ret = PTR_ERR(hw->eint->base); - goto err_free_eint; + count_reg_names = of_property_count_strings(np, "reg-names"); + if (count_reg_names < 0) + return -EINVAL; + + hw->eint->nbase = count_reg_names - (int)hw->soc->nbase_names; + if (hw->eint->nbase <= 0) + return -EINVAL; + + hw->eint->base = devm_kmalloc_array(&pdev->dev, hw->eint->nbase, + sizeof(*hw->eint->base), GFP_KERNEL | __GFP_ZERO); + if (!hw->eint->base) { + ret = -ENOMEM; + goto err_free_base; + } + + for (i = hw->soc->nbase_names, j = 0; i < count_reg_names; i++, j++) { + hw->eint->base[j] = of_iomap(np, i); + if (IS_ERR(hw->eint->base[j])) { + ret = PTR_ERR(hw->eint->base[j]); + goto err_free_eint; + } } hw->eint->irq = irq_of_parse_and_map(np, 0); @@ -401,9 +419,19 @@ int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) hw->eint->pctl = hw; hw->eint->gpio_xlate = &mtk_eint_xt; - return mtk_eint_do_init(hw->eint); + ret = mtk_eint_do_init(hw->eint, hw->soc->eint_pin); + if (ret) + goto err_free_eint; + + return 0; err_free_eint: + for (j = 0; j < hw->eint->nbase; j++) { + if (hw->eint->base[j]) + iounmap(hw->eint->base[j]); + } + devm_kfree(hw->dev, hw->eint->base); +err_free_base: devm_kfree(hw->dev, hw->eint); hw->eint = NULL; return ret; diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h index 9c271dc2b521..36d2898037dd 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h @@ -242,6 +242,7 @@ struct mtk_pin_soc { unsigned int nfuncs; const struct mtk_eint_regs *eint_regs; const struct mtk_eint_hw *eint_hw; + struct mtk_eint_pin *eint_pin; /* Specific parameters per SoC */ u8 gpio_m; diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 91edb539925a..a4cb6d511fcd 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -86,7 +86,7 @@ static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, return 0; } -static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +static int mtk_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { unsigned int reg_addr; unsigned int bit; @@ -100,7 +100,7 @@ static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value) else reg_addr = CLR_ADDR(reg_addr, pctl); - regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); + return regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); } static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, @@ -809,7 +809,12 @@ static const struct pinmux_ops mtk_pmx_ops = { static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) { - mtk_gpio_set(chip, offset, value); + int ret; + + ret = mtk_gpio_set(chip, offset, value); + if (ret) + return ret; + return pinctrl_gpio_direction_output(chip, offset); } @@ -893,7 +898,7 @@ static const struct gpio_chip mtk_gpio_chip = { .direction_input = pinctrl_gpio_direction_input, .direction_output = mtk_gpio_direction_output, .get = mtk_gpio_get, - .set = mtk_gpio_set, + .set_rv = mtk_gpio_set, .to_irq = mtk_gpio_to_irq, .set_config = mtk_gpio_set_config, }; @@ -1015,9 +1020,15 @@ static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev) if (!pctl->eint) return -ENOMEM; - pctl->eint->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(pctl->eint->base)) - return PTR_ERR(pctl->eint->base); + pctl->eint->nbase = 1; + /* mtk-eint expects an array */ + pctl->eint->base = devm_kzalloc(pctl->dev, sizeof(pctl->eint->base), GFP_KERNEL); + if (!pctl->eint->base) + return -ENOMEM; + + pctl->eint->base[0] = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pctl->eint->base[0])) + return PTR_ERR(pctl->eint->base[0]); pctl->eint->irq = irq_of_parse_and_map(np, 0); if (!pctl->eint->irq) @@ -1033,7 +1044,7 @@ static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev) pctl->eint->pctl = pctl; pctl->eint->gpio_xlate = &mtk_eint_xt; - return mtk_eint_do_init(pctl->eint); + return mtk_eint_do_init(pctl->eint, NULL); } /* This is used as a common probe function */ diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6893.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6893.h new file mode 100644 index 000000000000..0d3bb16411f8 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6893.h @@ -0,0 +1,2283 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * Copyright (C) 2024 Collabora Ltd. + * + * Author: Andy Teng <andy.teng@mediatek.com> + */ + +#ifndef __PINCTRL_MTK_MT6893_H +#define __PINCTRL_MTK_MT6893_H + +#include "pinctrl-paris.h" + +static const struct mtk_pin_desc mtk_pins_mt6893[] = { + MTK_PIN( + 0, "GPIO0", + MTK_EINT_FUNCTION(0, 0), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "SPI6_CLK"), + MTK_FUNCTION(2, "I2S5_MCK"), + MTK_FUNCTION(3, "PWM_0"), + MTK_FUNCTION(4, "MD_INT0"), + MTK_FUNCTION(5, "TP_GPIO0_AO") + ), + MTK_PIN( + 1, "GPIO1", + MTK_EINT_FUNCTION(0, 1), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "SPI6_CSB"), + MTK_FUNCTION(2, "I2S5_BCK"), + MTK_FUNCTION(3, "PWM_1"), + MTK_FUNCTION(4, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(5, "TP_GPIO1_AO") + ), + MTK_PIN( + 2, "GPIO2", + MTK_EINT_FUNCTION(0, 2), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "SPI6_MI"), + MTK_FUNCTION(2, "I2S5_LRCK"), + MTK_FUNCTION(3, "PWM_2"), + MTK_FUNCTION(4, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(5, "TP_GPIO2_AO") + ), + MTK_PIN( + 3, "GPIO3", + MTK_EINT_FUNCTION(0, 3), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "SPI6_MO"), + MTK_FUNCTION(2, "I2S5_DO"), + MTK_FUNCTION(3, "PWM_3"), + MTK_FUNCTION(4, "CLKM0"), + MTK_FUNCTION(5, "TP_GPIO3_AO") + ), + MTK_PIN( + 4, "GPIO4", + MTK_EINT_FUNCTION(0, 4), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "SPI7_A_CLK"), + MTK_FUNCTION(2, "I2S2_MCK"), + MTK_FUNCTION(3, "DMIC1_CLK"), + MTK_FUNCTION(4, "PCM1_DI"), + MTK_FUNCTION(5, "TP_GPIO4_AO") + ), + MTK_PIN( + 5, "GPIO5", + MTK_EINT_FUNCTION(0, 5), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "SPI7_A_CSB"), + MTK_FUNCTION(2, "I2S2_BCK"), + MTK_FUNCTION(3, "DMIC1_DAT"), + MTK_FUNCTION(4, "PCM1_CLK"), + MTK_FUNCTION(5, "TP_GPIO5_AO") + ), + MTK_PIN( + 6, "GPIO6", + MTK_EINT_FUNCTION(0, 6), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "SPI7_A_MI"), + MTK_FUNCTION(2, "I2S2_LRCK"), + MTK_FUNCTION(3, "DMIC_CLK"), + MTK_FUNCTION(4, "PCM1_SYNC"), + MTK_FUNCTION(5, "TP_GPIO6_AO"), + MTK_FUNCTION(6, "CONN_TCXOENA_REQ") + ), + MTK_PIN( + 7, "GPIO7", + MTK_EINT_FUNCTION(0, 7), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "SPI7_A_MO"), + MTK_FUNCTION(2, "I2S2_DI"), + MTK_FUNCTION(3, "DMIC_DAT"), + MTK_FUNCTION(4, "PCM1_DO0"), + MTK_FUNCTION(5, "TP_GPIO7_AO"), + MTK_FUNCTION(6, "WIFI_TXD") + ), + MTK_PIN( + 8, "GPIO8", + MTK_EINT_FUNCTION(0, 8), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "SRCLKENAI1"), + MTK_FUNCTION(2, "I2S2_DI2"), + MTK_FUNCTION(3, "KPCOL2"), + MTK_FUNCTION(4, "PCM1_DO1"), + MTK_FUNCTION(5, "CLKM1"), + MTK_FUNCTION(6, "CONN_BT_TXD") + ), + MTK_PIN( + 9, "GPIO9", + MTK_EINT_FUNCTION(0, 9), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "DVFSRC_EXT_REQ"), + MTK_FUNCTION(3, "KPROW2"), + MTK_FUNCTION(4, "PCM1_DO2"), + MTK_FUNCTION(5, "CLKM3"), + MTK_FUNCTION(6, "CMMCLK4") + ), + MTK_PIN( + 10, "GPIO10", + MTK_EINT_FUNCTION(0, 10), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "MSDC1_CLK_A"), + MTK_FUNCTION(2, "SPI4_B_CLK"), + MTK_FUNCTION(3, "I2S8_MCK"), + MTK_FUNCTION(4, "DSI1_TE"), + MTK_FUNCTION(5, "MD_INT0"), + MTK_FUNCTION(6, "TP_GPIO0_AO") + ), + MTK_PIN( + 11, "GPIO11", + MTK_EINT_FUNCTION(0, 11), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "MSDC1_CMD_A"), + MTK_FUNCTION(2, "SPI4_B_CSB"), + MTK_FUNCTION(3, "I2S8_BCK"), + MTK_FUNCTION(4, "LCM1_RST"), + MTK_FUNCTION(5, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(6, "TP_GPIO1_AO") + ), + MTK_PIN( + 12, "GPIO12", + MTK_EINT_FUNCTION(0, 12), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "MSDC1_DAT3_A"), + MTK_FUNCTION(2, "SPI4_B_MI"), + MTK_FUNCTION(3, "I2S8_LRCK"), + MTK_FUNCTION(4, "DMIC1_CLK"), + MTK_FUNCTION(5, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(6, "TP_GPIO2_AO") + ), + MTK_PIN( + 13, "GPIO13", + MTK_EINT_FUNCTION(0, 13), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "MSDC1_DAT0_A"), + MTK_FUNCTION(2, "SPI4_B_MO"), + MTK_FUNCTION(3, "I2S8_DI"), + MTK_FUNCTION(4, "DMIC1_DAT"), + MTK_FUNCTION(5, "ANT_SEL10"), + MTK_FUNCTION(6, "TP_GPIO3_AO") + ), + MTK_PIN( + 14, "GPIO14", + MTK_EINT_FUNCTION(0, 14), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "MSDC1_DAT2_A"), + MTK_FUNCTION(2, "SPI5_C_CLK"), + MTK_FUNCTION(3, "I2S9_MCK"), + MTK_FUNCTION(4, "IDDIG"), + MTK_FUNCTION(5, "ANT_SEL11"), + MTK_FUNCTION(6, "TP_GPIO4_AO") + ), + MTK_PIN( + 15, "GPIO15", + MTK_EINT_FUNCTION(0, 15), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "MSDC1_DAT1_A"), + MTK_FUNCTION(2, "SPI5_C_CSB"), + MTK_FUNCTION(3, "I2S9_BCK"), + MTK_FUNCTION(4, "USB_DRVVBUS"), + MTK_FUNCTION(5, "ANT_SEL12"), + MTK_FUNCTION(6, "TP_GPIO5_AO") + ), + MTK_PIN( + 16, "GPIO16", + MTK_EINT_FUNCTION(0, 16), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "SRCLKENAI1"), + MTK_FUNCTION(2, "SPI5_C_MI"), + MTK_FUNCTION(3, "I2S9_LRCK"), + MTK_FUNCTION(4, "KPCOL2"), + MTK_FUNCTION(5, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(6, "TP_GPIO6_AO"), + MTK_FUNCTION(7, "DBG_MON_A30") + ), + MTK_PIN( + 17, "GPIO17", + MTK_EINT_FUNCTION(0, 17), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "SPI5_C_MO"), + MTK_FUNCTION(3, "I2S9_DO"), + MTK_FUNCTION(4, "KPROW2"), + MTK_FUNCTION(5, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(6, "TP_GPIO7_AO"), + MTK_FUNCTION(7, "DBG_MON_A31") + ), + MTK_PIN( + 18, "GPIO18", + MTK_EINT_FUNCTION(0, 18), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "DP_TX_HPD"), + MTK_FUNCTION(2, "SPI4_C_MI"), + MTK_FUNCTION(3, "SPI1_B_MI"), + MTK_FUNCTION(4, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(5, "ANT_SEL10"), + MTK_FUNCTION(6, "MD_INT0") + ), + MTK_PIN( + 19, "GPIO19", + MTK_EINT_FUNCTION(0, 19), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "SRCLKENAI1"), + MTK_FUNCTION(2, "SPI4_C_MO"), + MTK_FUNCTION(3, "SPI1_B_MO"), + MTK_FUNCTION(4, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(5, "ANT_SEL11"), + MTK_FUNCTION(6, "MD_INT1_C2K_UIM0_HOT_PLUG") + ), + MTK_PIN( + 20, "GPIO20", + MTK_EINT_FUNCTION(0, 20), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "SPI4_C_CLK"), + MTK_FUNCTION(3, "SPI1_B_CLK"), + MTK_FUNCTION(4, "PWM_3"), + MTK_FUNCTION(5, "ANT_SEL12"), + MTK_FUNCTION(6, "MD_INT2_C2K_UIM1_HOT_PLUG") + ), + MTK_PIN( + 21, "GPIO21", + MTK_EINT_FUNCTION(0, 21), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "DP_TX_HPD"), + MTK_FUNCTION(2, "SPI4_C_CSB"), + MTK_FUNCTION(3, "SPI1_B_CSB"), + MTK_FUNCTION(4, "I2S7_MCK"), + MTK_FUNCTION(5, "I2S9_MCK"), + MTK_FUNCTION(6, "IDDIG") + ), + MTK_PIN( + 22, "GPIO22", + MTK_EINT_FUNCTION(0, 22), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "LCM1_RST"), + MTK_FUNCTION(2, "SPI0_C_CLK"), + MTK_FUNCTION(3, "SPI7_B_CLK"), + MTK_FUNCTION(4, "I2S7_BCK"), + MTK_FUNCTION(5, "I2S9_BCK"), + MTK_FUNCTION(6, "SCL13") + ), + MTK_PIN( + 23, "GPIO23", + MTK_EINT_FUNCTION(0, 23), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "DSI1_TE"), + MTK_FUNCTION(2, "SPI0_C_CSB"), + MTK_FUNCTION(3, "SPI7_B_CSB"), + MTK_FUNCTION(4, "I2S7_LRCK"), + MTK_FUNCTION(5, "I2S9_LRCK"), + MTK_FUNCTION(6, "SDA13") + ), + MTK_PIN( + 24, "GPIO24", + MTK_EINT_FUNCTION(0, 24), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "SRCLKENAI1"), + MTK_FUNCTION(2, "SPI0_C_MI"), + MTK_FUNCTION(3, "SPI7_B_MI"), + MTK_FUNCTION(4, "I2S6_DI"), + MTK_FUNCTION(5, "I2S8_DI"), + MTK_FUNCTION(6, "SCL_6306") + ), + MTK_PIN( + 25, "GPIO25", + MTK_EINT_FUNCTION(0, 25), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "SPI0_C_MO"), + MTK_FUNCTION(3, "SPI7_B_MO"), + MTK_FUNCTION(4, "I2S7_DO"), + MTK_FUNCTION(5, "I2S9_DO"), + MTK_FUNCTION(6, "SDA_6306") + ), + MTK_PIN( + 26, "GPIO26", + MTK_EINT_FUNCTION(0, 26), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "PWM_2"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "USB_DRVVBUS") + ), + MTK_PIN( + 27, "GPIO27", + MTK_EINT_FUNCTION(0, 27), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "PWM_3"), + MTK_FUNCTION(2, "CLKM1") + ), + MTK_PIN( + 28, "GPIO28", + MTK_EINT_FUNCTION(0, 28), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "PWM_0"), + MTK_FUNCTION(2, "CLKM2") + ), + MTK_PIN( + 29, "GPIO29", + MTK_EINT_FUNCTION(0, 29), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "PWM_1"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "DSI1_TE") + ), + MTK_PIN( + 30, "GPIO30", + MTK_EINT_FUNCTION(0, 30), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "PWM_2"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "LCM1_RST") + ), + MTK_PIN( + 31, "GPIO31", + MTK_EINT_FUNCTION(0, 31), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "I2S3_MCK"), + MTK_FUNCTION(2, "I2S1_MCK"), + MTK_FUNCTION(3, "I2S5_MCK"), + MTK_FUNCTION(4, "SRCLKENAI0"), + MTK_FUNCTION(5, "I2S0_MCK") + ), + MTK_PIN( + 32, "GPIO32", + MTK_EINT_FUNCTION(0, 32), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "I2S3_BCK"), + MTK_FUNCTION(2, "I2S1_BCK"), + MTK_FUNCTION(3, "I2S5_BCK"), + MTK_FUNCTION(4, "PCM0_CLK"), + MTK_FUNCTION(5, "I2S0_BCK") + ), + MTK_PIN( + 33, "GPIO33", + MTK_EINT_FUNCTION(0, 33), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "I2S3_LRCK"), + MTK_FUNCTION(2, "I2S1_LRCK"), + MTK_FUNCTION(3, "I2S5_LRCK"), + MTK_FUNCTION(4, "PCM0_SYNC"), + MTK_FUNCTION(5, "I2S0_LRCK") + ), + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(0, 34), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "I2S0_DI"), + MTK_FUNCTION(2, "I2S2_DI"), + MTK_FUNCTION(3, "I2S2_DI2"), + MTK_FUNCTION(4, "PCM0_DI"), + MTK_FUNCTION(5, "I2S0_DI") + ), + MTK_PIN( + 35, "GPIO35", + MTK_EINT_FUNCTION(0, 35), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "I2S3_DO"), + MTK_FUNCTION(2, "I2S1_DO"), + MTK_FUNCTION(3, "I2S5_DO"), + MTK_FUNCTION(4, "PCM0_DO") + ), + MTK_PIN( + 36, "GPIO36", + MTK_EINT_FUNCTION(0, 36), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "SPI5_A_CLK"), + MTK_FUNCTION(2, "DMIC1_CLK"), + MTK_FUNCTION(3, "IDDIG"), + MTK_FUNCTION(4, "MD_URXD0"), + MTK_FUNCTION(5, "UCTS0"), + MTK_FUNCTION(6, "URXD1"), + MTK_FUNCTION(7, "DBG_MON_A0") + ), + MTK_PIN( + 37, "GPIO37", + MTK_EINT_FUNCTION(0, 37), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "SPI5_A_CSB"), + MTK_FUNCTION(2, "DMIC1_DAT"), + MTK_FUNCTION(3, "USB_DRVVBUS"), + MTK_FUNCTION(4, "MD_UTXD0"), + MTK_FUNCTION(5, "URTS0"), + MTK_FUNCTION(6, "UTXD1"), + MTK_FUNCTION(7, "DBG_MON_A1") + ), + MTK_PIN( + 38, "GPIO38", + MTK_EINT_FUNCTION(0, 38), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "SPI5_A_MI"), + MTK_FUNCTION(2, "DMIC_CLK"), + MTK_FUNCTION(3, "DSI1_TE"), + MTK_FUNCTION(4, "MD_URXD1"), + MTK_FUNCTION(5, "URXD0"), + MTK_FUNCTION(6, "UCTS1"), + MTK_FUNCTION(7, "DBG_MON_A2") + ), + MTK_PIN( + 39, "GPIO39", + MTK_EINT_FUNCTION(0, 39), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "SPI5_A_MO"), + MTK_FUNCTION(2, "DMIC_DAT"), + MTK_FUNCTION(3, "LCM1_RST"), + MTK_FUNCTION(4, "MD_UTXD1"), + MTK_FUNCTION(5, "UTXD0"), + MTK_FUNCTION(6, "URTS1"), + MTK_FUNCTION(7, "DBG_MON_A3") + ), + MTK_PIN( + 40, "GPIO40", + MTK_EINT_FUNCTION(0, 40), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(7, "DBG_MON_A6") + ), + MTK_PIN( + 41, "GPIO41", + MTK_EINT_FUNCTION(0, 41), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "DSI_TE") + ), + MTK_PIN( + 42, "GPIO42", + MTK_EINT_FUNCTION(0, 42), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "LCM_RST") + ), + MTK_PIN( + 43, "GPIO43", + MTK_EINT_FUNCTION(0, 43), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(2, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(3, "SCL_6306"), + MTK_FUNCTION(4, "ADSP_URXD0"), + MTK_FUNCTION(5, "PTA_RXD"), + MTK_FUNCTION(6, "SSPM_URXD_AO"), + MTK_FUNCTION(7, "DBG_MON_A4") + ), + MTK_PIN( + 44, "GPIO44", + MTK_EINT_FUNCTION(0, 44), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(2, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(3, "SDA_6306"), + MTK_FUNCTION(4, "ADSP_UTXD0"), + MTK_FUNCTION(5, "PTA_TXD"), + MTK_FUNCTION(6, "SSPM_UTXD_AO"), + MTK_FUNCTION(7, "DBG_MON_A5") + ), + MTK_PIN( + 45, "GPIO45", + MTK_EINT_FUNCTION(0, 45), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "MD1_SIM2_SCLK"), + MTK_FUNCTION(2, "MD1_SIM1_SCLK"), + MTK_FUNCTION(3, "MCUPM_JTAG_TDI"), + MTK_FUNCTION(4, "APU_JTAG_TDI"), + MTK_FUNCTION(5, "CCU_JTAG_TDI"), + MTK_FUNCTION(6, "LVTS_SCK") + ), + MTK_PIN( + 46, "GPIO46", + MTK_EINT_FUNCTION(0, 46), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "MD1_SIM2_SRST"), + MTK_FUNCTION(2, "MD1_SIM1_SRST"), + MTK_FUNCTION(3, "MCUPM_JTAG_TMS"), + MTK_FUNCTION(4, "APU_JTAG_TMS"), + MTK_FUNCTION(5, "CCU_JTAG_TMS"), + MTK_FUNCTION(6, "LVTS_SDI") + ), + MTK_PIN( + 47, "GPIO47", + MTK_EINT_FUNCTION(0, 47), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "MD1_SIM2_SIO"), + MTK_FUNCTION(2, "MD1_SIM1_SIO"), + MTK_FUNCTION(3, "MCUPM_JTAG_TDO"), + MTK_FUNCTION(4, "APU_JTAG_TDO"), + MTK_FUNCTION(5, "CCU_JTAG_TDO"), + MTK_FUNCTION(6, "LVTS_SCF") + ), + MTK_PIN( + 48, "GPIO48", + MTK_EINT_FUNCTION(0, 48), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "MD1_SIM1_SIO"), + MTK_FUNCTION(2, "MD1_SIM2_SIO"), + MTK_FUNCTION(3, "MCUPM_JTAG_TRSTN"), + MTK_FUNCTION(4, "APU_JTAG_TRST"), + MTK_FUNCTION(5, "CCU_JTAG_TRST"), + MTK_FUNCTION(6, "LVTS_FOUT") + ), + MTK_PIN( + 49, "GPIO49", + MTK_EINT_FUNCTION(0, 49), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "MD1_SIM1_SRST"), + MTK_FUNCTION(2, "MD1_SIM2_SRST"), + MTK_FUNCTION(3, "MCUPM_JTAG_TCK"), + MTK_FUNCTION(4, "APU_JTAG_TCK"), + MTK_FUNCTION(5, "CCU_JTAG_TCK"), + MTK_FUNCTION(6, "LVTS_SDO") + ), + MTK_PIN( + 50, "GPIO50", + MTK_EINT_FUNCTION(0, 50), + DRV_GRP2, + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "MD1_SIM1_SCLK"), + MTK_FUNCTION(2, "MD1_SIM2_SCLK"), + MTK_FUNCTION(6, "LVTS_26M") + ), + MTK_PIN( + 51, "GPIO51", + MTK_EINT_FUNCTION(0, 51), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "PCM1_CLK"), + MTK_FUNCTION(3, "VPU_UDI_TCK"), + MTK_FUNCTION(4, "UDI_TCK"), + MTK_FUNCTION(5, "IPU_JTAG_TCK"), + MTK_FUNCTION(6, "SSPM_JTAG_TCK"), + MTK_FUNCTION(7, "JTCK_SEL3") + ), + MTK_PIN( + 52, "GPIO52", + MTK_EINT_FUNCTION(0, 52), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(2, "PCM1_SYNC"), + MTK_FUNCTION(3, "VPU_UDI_TMS"), + MTK_FUNCTION(4, "UDI_TMS"), + MTK_FUNCTION(5, "IPU_JTAG_TMS"), + MTK_FUNCTION(6, "SSPM_JTAG_TMS"), + MTK_FUNCTION(7, "JTMS_SEL3") + ), + MTK_PIN( + 53, "GPIO53", + MTK_EINT_FUNCTION(0, 53), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(2, "PCM1_DI") + ), + MTK_PIN( + 54, "GPIO54", + MTK_EINT_FUNCTION(0, 54), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "PCM1_DO0"), + MTK_FUNCTION(3, "VPU_UDI_TDI"), + MTK_FUNCTION(4, "UDI_TDI"), + MTK_FUNCTION(5, "IPU_JTAG_TDI"), + MTK_FUNCTION(6, "SSPM_JTAG_TDI"), + MTK_FUNCTION(7, "JTDI_SEL3") + ), + MTK_PIN( + 55, "GPIO55", + MTK_EINT_FUNCTION(0, 55), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "PCM1_DO2"), + MTK_FUNCTION(3, "VPU_UDI_NTRST"), + MTK_FUNCTION(4, "UDI_NTRST"), + MTK_FUNCTION(5, "IPU_JTAG_TRST"), + MTK_FUNCTION(6, "SSPM_JTAG_TRSTN"), + MTK_FUNCTION(7, "JTRSTN_SEL3") + ), + MTK_PIN( + 56, "GPIO56", + MTK_EINT_FUNCTION(0, 56), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "PCM1_DO1"), + MTK_FUNCTION(3, "VPU_UDI_TDO"), + MTK_FUNCTION(4, "UDI_TDO"), + MTK_FUNCTION(5, "IPU_JTAG_TDO"), + MTK_FUNCTION(6, "SSPM_JTAG_TDO"), + MTK_FUNCTION(7, "JTDO_SEL3") + ), + MTK_PIN( + 57, "GPIO57", + MTK_EINT_FUNCTION(0, 57), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "MIPI2_D_SCLK"), + MTK_FUNCTION(7, "DBG_MON_A14") + ), + MTK_PIN( + 58, "GPIO58", + MTK_EINT_FUNCTION(0, 58), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "MIPI2_D_SDATA"), + MTK_FUNCTION(7, "DBG_MON_A15") + ), + MTK_PIN( + 59, "GPIO59", + MTK_EINT_FUNCTION(0, 59), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "MIPI_M_SCLK"), + MTK_FUNCTION(7, "DBG_MON_A17") + ), + MTK_PIN( + 60, "GPIO60", + MTK_EINT_FUNCTION(0, 60), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "MIPI_M_SDATA"), + MTK_FUNCTION(7, "DBG_MON_A18") + ), + MTK_PIN( + 61, "GPIO61", + MTK_EINT_FUNCTION(0, 61), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "MD_UCNT_A_TGL"), + MTK_FUNCTION(7, "DBG_MON_A16") + ), + MTK_PIN( + 62, "GPIO62", + MTK_EINT_FUNCTION(0, 62), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "DIGRF_IRQ") + ), + MTK_PIN( + 63, "GPIO63", + MTK_EINT_FUNCTION(0, 63), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "BPI_BUS0"), + MTK_FUNCTION(7, "DBG_MON_A19") + ), + MTK_PIN( + 64, "GPIO64", + MTK_EINT_FUNCTION(0, 64), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "BPI_BUS1"), + MTK_FUNCTION(7, "DBG_MON_A20") + ), + MTK_PIN( + 65, "GPIO65", + MTK_EINT_FUNCTION(0, 65), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "BPI_BUS2"), + MTK_FUNCTION(7, "DBG_MON_A21") + ), + MTK_PIN( + 66, "GPIO66", + MTK_EINT_FUNCTION(0, 66), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "BPI_BUS3"), + MTK_FUNCTION(7, "DBG_MON_A22") + ), + MTK_PIN( + 67, "GPIO67", + MTK_EINT_FUNCTION(0, 67), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "BPI_BUS4") + ), + MTK_PIN( + 68, "GPIO68", + MTK_EINT_FUNCTION(0, 68), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "BPI_BUS5") + ), + MTK_PIN( + 69, "GPIO69", + MTK_EINT_FUNCTION(0, 69), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "BPI_BUS6"), + MTK_FUNCTION(2, "CONN_BPI_BUS6") + ), + MTK_PIN( + 70, "GPIO70", + MTK_EINT_FUNCTION(0, 70), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "BPI_BUS7"), + MTK_FUNCTION(2, "CONN_BPI_BUS7") + ), + MTK_PIN( + 71, "GPIO71", + MTK_EINT_FUNCTION(0, 71), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "BPI_BUS8"), + MTK_FUNCTION(2, "CONN_BPI_BUS8") + ), + MTK_PIN( + 72, "GPIO72", + MTK_EINT_FUNCTION(0, 72), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "BPI_BUS9"), + MTK_FUNCTION(2, "CONN_BPI_BUS9") + ), + MTK_PIN( + 73, "GPIO73", + MTK_EINT_FUNCTION(0, 73), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "BPI_BUS10"), + MTK_FUNCTION(2, "CONN_BPI_BUS10") + ), + MTK_PIN( + 74, "GPIO74", + MTK_EINT_FUNCTION(0, 74), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "BPI_BUS11_OLAT0"), + MTK_FUNCTION(2, "CONN_BPI_BUS11_OLAT0") + ), + MTK_PIN( + 75, "GPIO75", + MTK_EINT_FUNCTION(0, 75), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "BPI_BUS12_OLAT1"), + MTK_FUNCTION(2, "CONN_BPI_BUS12_OLAT1") + ), + MTK_PIN( + 76, "GPIO76", + MTK_EINT_FUNCTION(0, 76), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "BPI_BUS13_OLAT2"), + MTK_FUNCTION(2, "CONN_BPI_BUS13_OLAT2") + ), + MTK_PIN( + 77, "GPIO77", + MTK_EINT_FUNCTION(0, 77), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "BPI_BUS14_OLAT3"), + MTK_FUNCTION(2, "CONN_BPI_BUS14_OLAT3") + ), + MTK_PIN( + 78, "GPIO78", + MTK_EINT_FUNCTION(0, 78), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "BPI_BUS15_OLAT4"), + MTK_FUNCTION(2, "CONN_BPI_BUS15_OLAT4"), + MTK_FUNCTION(7, "DBG_MON_A7") + ), + MTK_PIN( + 79, "GPIO79", + MTK_EINT_FUNCTION(0, 79), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "BPI_BUS16_OLAT5"), + MTK_FUNCTION(2, "CONN_BPI_BUS16_OLAT5"), + MTK_FUNCTION(7, "DBG_MON_A8") + ), + MTK_PIN( + 80, "GPIO80", + MTK_EINT_FUNCTION(0, 80), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "BPI_BUS17_ANT0"), + MTK_FUNCTION(2, "CONN_BPI_BUS17_ANT0"), + MTK_FUNCTION(7, "DBG_MON_A9") + ), + MTK_PIN( + 81, "GPIO81", + MTK_EINT_FUNCTION(0, 81), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "BPI_BUS18_ANT1"), + MTK_FUNCTION(2, "CONN_BPI_BUS18_ANT1"), + MTK_FUNCTION(7, "DBG_MON_A10") + ), + MTK_PIN( + 82, "GPIO82", + MTK_EINT_FUNCTION(0, 82), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "BPI_BUS19_ANT2"), + MTK_FUNCTION(2, "CONN_BPI_BUS19_ANT2"), + MTK_FUNCTION(7, "DBG_MON_A11") + ), + MTK_PIN( + 83, "GPIO83", + MTK_EINT_FUNCTION(0, 83), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "BPI_BUS20_ANT3"), + MTK_FUNCTION(2, "CONN_BPI_BUS20_ANT3"), + MTK_FUNCTION(7, "DBG_MON_A12") + ), + MTK_PIN( + 84, "GPIO84", + MTK_EINT_FUNCTION(0, 84), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "BPI_BUS21_ANT4"), + MTK_FUNCTION(2, "CONN_BPI_BUS21_ANT4"), + MTK_FUNCTION(7, "DBG_MON_A13") + ), + MTK_PIN( + 85, "GPIO85", + MTK_EINT_FUNCTION(0, 85), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "MIPI1_D_SCLK"), + MTK_FUNCTION(2, "CONN_MIPI1_SCLK") + ), + MTK_PIN( + 86, "GPIO86", + MTK_EINT_FUNCTION(0, 86), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "MIPI1_D_SDATA"), + MTK_FUNCTION(2, "CONN_MIPI1_SDATA") + ), + MTK_PIN( + 87, "GPIO87", + MTK_EINT_FUNCTION(0, 87), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "MIPI0_D_SCLK"), + MTK_FUNCTION(2, "CONN_MIPI0_SCLK") + ), + MTK_PIN( + 88, "GPIO88", + MTK_EINT_FUNCTION(0, 88), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "MIPI0_D_SDATA"), + MTK_FUNCTION(2, "CONN_MIPI0_SDATA") + ), + MTK_PIN( + 89, "GPIO89", + MTK_EINT_FUNCTION(0, 89), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "SPMI_SCL"), + MTK_FUNCTION(2, "SCL10") + ), + MTK_PIN( + 90, "GPIO90", + MTK_EINT_FUNCTION(0, 90), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "SPMI_SDA"), + MTK_FUNCTION(2, "SDA10") + ), + MTK_PIN( + 91, "GPIO91", + MTK_EINT_FUNCTION(0, 91), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "AP_GOOD") + ), + MTK_PIN( + 92, "GPIO92", + MTK_EINT_FUNCTION(0, 92), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "MD_URXD0"), + MTK_FUNCTION(3, "MD_URXD1"), + MTK_FUNCTION(4, "SSPM_URXD_AO"), + MTK_FUNCTION(5, "CONN_BGF_UART0_RXD") + ), + MTK_PIN( + 93, "GPIO93", + MTK_EINT_FUNCTION(0, 93), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "MD_UTXD0"), + MTK_FUNCTION(3, "MD_UTXD1"), + MTK_FUNCTION(4, "SSPM_UTXD_AO"), + MTK_FUNCTION(5, "CONN_BGF_UART0_TXD"), + MTK_FUNCTION(6, "WIFI_TXD") + ), + MTK_PIN( + 94, "GPIO94", + MTK_EINT_FUNCTION(0, 94), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "ADSP_URXD0"), + MTK_FUNCTION(3, "MD32_0_RXD"), + MTK_FUNCTION(4, "SSPM_URXD_AO"), + MTK_FUNCTION(5, "TP_URXD1_AO"), + MTK_FUNCTION(6, "TP_URXD2_AO"), + MTK_FUNCTION(7, "MBISTREADEN_TRIGGER") + ), + MTK_PIN( + 95, "GPIO95", + MTK_EINT_FUNCTION(0, 95), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "ADSP_UTXD0"), + MTK_FUNCTION(3, "MD32_0_TXD"), + MTK_FUNCTION(4, "SSPM_UTXD_AO"), + MTK_FUNCTION(5, "TP_UTXD1_AO"), + MTK_FUNCTION(6, "TP_UTXD2_AO"), + MTK_FUNCTION(7, "MBISTWRITEEN_TRIGGER") + ), + MTK_PIN( + 96, "GPIO96", + MTK_EINT_FUNCTION(0, 96), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "TDM_LRCK"), + MTK_FUNCTION(2, "I2S7_LRCK"), + MTK_FUNCTION(3, "I2S9_LRCK"), + MTK_FUNCTION(4, "SPI4_A_CLK"), + MTK_FUNCTION(5, "ADSP_JTAG0_TDI"), + MTK_FUNCTION(6, "CONN_BGF_DSP_L1_JDI"), + MTK_FUNCTION(7, "IO_JTAG_TDI") + ), + MTK_PIN( + 97, "GPIO97", + MTK_EINT_FUNCTION(0, 97), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "TDM_BCK"), + MTK_FUNCTION(2, "I2S7_BCK"), + MTK_FUNCTION(3, "I2S9_BCK"), + MTK_FUNCTION(4, "SPI4_A_CSB"), + MTK_FUNCTION(5, "ADSP_JTAG0_TRSTN"), + MTK_FUNCTION(6, "CONN_BGF_DSP_L1_JINTP"), + MTK_FUNCTION(7, "IO_JTAG_TRSTN") + ), + MTK_PIN( + 98, "GPIO98", + MTK_EINT_FUNCTION(0, 98), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "TDM_MCK"), + MTK_FUNCTION(2, "I2S7_MCK"), + MTK_FUNCTION(3, "I2S9_MCK"), + MTK_FUNCTION(4, "SPI4_A_MI"), + MTK_FUNCTION(5, "ADSP_JTAG0_TCK"), + MTK_FUNCTION(6, "CONN_BGF_DSP_L1_JCK"), + MTK_FUNCTION(7, "IO_JTAG_TCK") + ), + MTK_PIN( + 99, "GPIO99", + MTK_EINT_FUNCTION(0, 99), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "TDM_DATA0"), + MTK_FUNCTION(2, "I2S6_DI"), + MTK_FUNCTION(3, "I2S8_DI"), + MTK_FUNCTION(4, "SPI4_A_MO"), + MTK_FUNCTION(5, "ADSP_JTAG0_TDO"), + MTK_FUNCTION(6, "CONN_BGF_DSP_L1_JDO"), + MTK_FUNCTION(7, "IO_JTAG_TDO") + ), + MTK_PIN( + 100, "GPIO100", + MTK_EINT_FUNCTION(0, 100), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "TDM_DATA1"), + MTK_FUNCTION(2, "I2S7_DO"), + MTK_FUNCTION(3, "I2S9_DO"), + MTK_FUNCTION(4, "DP_TX_HPD"), + MTK_FUNCTION(5, "ADSP_JTAG0_TMS"), + MTK_FUNCTION(6, "CONN_BGF_DSP_L1_JMS"), + MTK_FUNCTION(7, "IO_JTAG_TMS") + ), + MTK_PIN( + 101, "GPIO101", + MTK_EINT_FUNCTION(0, 101), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "TDM_DATA2"), + MTK_FUNCTION(2, "DMIC1_CLK"), + MTK_FUNCTION(3, "SRCLKENAI0"), + MTK_FUNCTION(4, "SPI5_B_CLK"), + MTK_FUNCTION(5, "CLKM0"), + MTK_FUNCTION(7, "DAP_MD32_SWD") + ), + MTK_PIN( + 102, "GPIO102", + MTK_EINT_FUNCTION(0, 102), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "TDM_DATA3"), + MTK_FUNCTION(2, "DMIC1_DAT"), + MTK_FUNCTION(3, "SRCLKENAI1"), + MTK_FUNCTION(4, "SPI5_B_CSB"), + MTK_FUNCTION(5, "DP_TX_HPD"), + MTK_FUNCTION(6, "DVFSRC_EXT_REQ"), + MTK_FUNCTION(7, "DAP_MD32_SWCK") + ), + MTK_PIN( + 103, "GPIO103", + MTK_EINT_FUNCTION(0, 103), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "SPI0_A_MI"), + MTK_FUNCTION(2, "SCP_SPI0_MI"), + MTK_FUNCTION(5, "DFD_TDO"), + MTK_FUNCTION(6, "SPM_JTAG_TDO"), + MTK_FUNCTION(7, "JTDO_SEL1") + ), + MTK_PIN( + 104, "GPIO104", + MTK_EINT_FUNCTION(0, 104), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "SPI0_A_CSB"), + MTK_FUNCTION(2, "SCP_SPI0_CS"), + MTK_FUNCTION(5, "DFD_TMS"), + MTK_FUNCTION(6, "SPM_JTAG_TMS"), + MTK_FUNCTION(7, "JTMS_SEL1") + ), + MTK_PIN( + 105, "GPIO105", + MTK_EINT_FUNCTION(0, 105), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "SPI0_A_MO"), + MTK_FUNCTION(2, "SCP_SPI0_MO"), + MTK_FUNCTION(3, "SCP_SDA0"), + MTK_FUNCTION(5, "DFD_TDI"), + MTK_FUNCTION(6, "SPM_JTAG_TDI"), + MTK_FUNCTION(7, "JTDI_SEL1") + ), + MTK_PIN( + 106, "GPIO106", + MTK_EINT_FUNCTION(0, 106), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "SPI0_A_CLK"), + MTK_FUNCTION(2, "SCP_SPI0_CK"), + MTK_FUNCTION(3, "SCP_SCL0"), + MTK_FUNCTION(5, "DFD_TCK_XI"), + MTK_FUNCTION(6, "SPM_JTAG_TCK"), + MTK_FUNCTION(7, "JTCK_SEL1") + ), + MTK_PIN( + 107, "GPIO107", + MTK_EINT_FUNCTION(0, 107), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "DMIC_CLK"), + MTK_FUNCTION(2, "PWM_0"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(4, "SPI5_B_MI"), + MTK_FUNCTION(6, "SPM_JTAG_TRSTN"), + MTK_FUNCTION(7, "JTRSTN_SEL1") + ), + MTK_PIN( + 108, "GPIO108", + MTK_EINT_FUNCTION(0, 108), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "DMIC_DAT"), + MTK_FUNCTION(2, "PWM_1"), + MTK_FUNCTION(3, "CLKM3"), + MTK_FUNCTION(4, "SPI5_B_MO"), + MTK_FUNCTION(7, "DAP_SONIC_SWD") + ), + MTK_PIN( + 109, "GPIO109", + MTK_EINT_FUNCTION(0, 109), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "I2S1_MCK"), + MTK_FUNCTION(2, "I2S3_MCK"), + MTK_FUNCTION(3, "I2S2_MCK"), + MTK_FUNCTION(4, "DP_TX_HPD"), + MTK_FUNCTION(5, "I2S2_MCK"), + MTK_FUNCTION(6, "SRCLKENAI0"), + MTK_FUNCTION(7, "DAP_SONIC_SWCK") + ), + MTK_PIN( + 110, "GPIO110", + MTK_EINT_FUNCTION(0, 110), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "I2S1_BCK"), + MTK_FUNCTION(2, "I2S3_BCK"), + MTK_FUNCTION(3, "I2S2_BCK"), + MTK_FUNCTION(4, "PCM0_CLK"), + MTK_FUNCTION(5, "I2S2_BCK"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TDO") + ), + MTK_PIN( + 111, "GPIO111", + MTK_EINT_FUNCTION(0, 111), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "I2S1_LRCK"), + MTK_FUNCTION(2, "I2S3_LRCK"), + MTK_FUNCTION(3, "I2S2_LRCK"), + MTK_FUNCTION(4, "PCM0_SYNC"), + MTK_FUNCTION(5, "I2S2_LRCK"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TDI") + ), + MTK_PIN( + 112, "GPIO112", + MTK_EINT_FUNCTION(0, 112), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "I2S2_DI"), + MTK_FUNCTION(2, "I2S0_DI"), + MTK_FUNCTION(3, "I2S2_DI2"), + MTK_FUNCTION(4, "PCM0_DI"), + MTK_FUNCTION(5, "I2S2_DI"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TMS") + ), + MTK_PIN( + 113, "GPIO113", + MTK_EINT_FUNCTION(0, 113), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "I2S1_DO"), + MTK_FUNCTION(2, "I2S3_DO"), + MTK_FUNCTION(3, "I2S5_DO"), + MTK_FUNCTION(4, "PCM0_DO"), + MTK_FUNCTION(5, "I2S2_DI2"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TCK") + ), + MTK_PIN( + 114, "GPIO114", + MTK_EINT_FUNCTION(0, 114), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "SPI2_MI"), + MTK_FUNCTION(2, "SCP_SPI2_MI"), + MTK_FUNCTION(6, "CONN_BGF_MCU_TRST_B") + ), + MTK_PIN( + 115, "GPIO115", + MTK_EINT_FUNCTION(0, 115), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "SPI2_CSB"), + MTK_FUNCTION(2, "SCP_SPI2_CS"), + MTK_FUNCTION(6, "CONN_BGF_MCU_DBGI_N") + ), + MTK_PIN( + 116, "GPIO116", + MTK_EINT_FUNCTION(0, 116), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "SPI2_MO"), + MTK_FUNCTION(2, "SCP_SPI2_MO"), + MTK_FUNCTION(3, "SCP_SDA1"), + MTK_FUNCTION(6, "CONN_BGF_MCU_DBGACK_N") + ), + MTK_PIN( + 117, "GPIO117", + MTK_EINT_FUNCTION(0, 117), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "SPI2_CLK"), + MTK_FUNCTION(2, "SCP_SPI2_CK"), + MTK_FUNCTION(3, "SCP_SCL1") + ), + MTK_PIN( + 118, "GPIO118", + MTK_EINT_FUNCTION(0, 118), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "SCL1"), + MTK_FUNCTION(2, "SCP_SCL0"), + MTK_FUNCTION(3, "SCP_SCL1") + ), + MTK_PIN( + 119, "GPIO119", + MTK_EINT_FUNCTION(0, 119), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "SDA1"), + MTK_FUNCTION(2, "SCP_SDA0"), + MTK_FUNCTION(3, "SCP_SDA1") + ), + MTK_PIN( + 120, "GPIO120", + MTK_EINT_FUNCTION(0, 120), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "SCL9") + ), + MTK_PIN( + 121, "GPIO121", + MTK_EINT_FUNCTION(0, 121), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "SDA9") + ), + MTK_PIN( + 122, "GPIO122", + MTK_EINT_FUNCTION(0, 122), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "SCL8") + ), + MTK_PIN( + 123, "GPIO123", + MTK_EINT_FUNCTION(0, 123), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "SDA8") + ), + MTK_PIN( + 124, "GPIO124", + MTK_EINT_FUNCTION(0, 124), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "SCL7"), + MTK_FUNCTION(2, "DMIC1_CLK") + ), + MTK_PIN( + 125, "GPIO125", + MTK_EINT_FUNCTION(0, 125), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "SDA7"), + MTK_FUNCTION(2, "DMIC1_DAT") + ), + MTK_PIN( + 126, "GPIO126", + MTK_EINT_FUNCTION(0, 126), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "CMFLASH0"), + MTK_FUNCTION(2, "PWM_2"), + MTK_FUNCTION(3, "TP_UCTS1_AO"), + MTK_FUNCTION(4, "UCTS0"), + MTK_FUNCTION(5, "SCL11"), + MTK_FUNCTION(6, "MD32_1_GPIO0") + ), + MTK_PIN( + 127, "GPIO127", + MTK_EINT_FUNCTION(0, 127), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "CMFLASH1"), + MTK_FUNCTION(2, "PWM_3"), + MTK_FUNCTION(3, "TP_URTS1_AO"), + MTK_FUNCTION(4, "URTS0"), + MTK_FUNCTION(5, "SDA11"), + MTK_FUNCTION(6, "MD32_1_GPIO1") + ), + MTK_PIN( + 128, "GPIO128", + MTK_EINT_FUNCTION(0, 128), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "CMFLASH2"), + MTK_FUNCTION(2, "PWM_0"), + MTK_FUNCTION(3, "TP_UCTS2_AO"), + MTK_FUNCTION(4, "UCTS1"), + MTK_FUNCTION(5, "SCL12"), + MTK_FUNCTION(6, "MD32_1_GPIO2") + ), + MTK_PIN( + 129, "GPIO129", + MTK_EINT_FUNCTION(0, 129), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "CMFLASH3"), + MTK_FUNCTION(2, "PWM_1"), + MTK_FUNCTION(3, "TP_URTS2_AO"), + MTK_FUNCTION(4, "URTS1"), + MTK_FUNCTION(5, "SDA12") + ), + MTK_PIN( + 130, "GPIO130", + MTK_EINT_FUNCTION(0, 130), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "CMVREF0"), + MTK_FUNCTION(2, "ANT_SEL10"), + MTK_FUNCTION(3, "SCP_JTAG0_TDO"), + MTK_FUNCTION(4, "MD32_0_JTAG_TDO"), + MTK_FUNCTION(5, "SCL11"), + MTK_FUNCTION(6, "CONN_WF_MCU_TDO"), + MTK_FUNCTION(7, "DBG_MON_A23") + ), + MTK_PIN( + 131, "GPIO131", + MTK_EINT_FUNCTION(0, 131), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "CMVREF1"), + MTK_FUNCTION(2, "ANT_SEL11"), + MTK_FUNCTION(3, "SCP_JTAG0_TDI"), + MTK_FUNCTION(4, "MD32_0_JTAG_TDI"), + MTK_FUNCTION(5, "SDA11"), + MTK_FUNCTION(6, "CONN_WF_MCU_TDI"), + MTK_FUNCTION(7, "DBG_MON_A26") + ), + MTK_PIN( + 132, "GPIO132", + MTK_EINT_FUNCTION(0, 132), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "CMVREF2"), + MTK_FUNCTION(2, "ANT_SEL12"), + MTK_FUNCTION(3, "SCP_JTAG0_TMS"), + MTK_FUNCTION(4, "MD32_0_JTAG_TMS"), + MTK_FUNCTION(6, "CONN_WF_MCU_TMS"), + MTK_FUNCTION(7, "DBG_MON_A28") + ), + MTK_PIN( + 133, "GPIO133", + MTK_EINT_FUNCTION(0, 133), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "CMVREF3"), + MTK_FUNCTION(2, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(3, "SCP_JTAG0_TCK"), + MTK_FUNCTION(4, "MD32_0_JTAG_TCK"), + MTK_FUNCTION(6, "CONN_WF_MCU_TCK"), + MTK_FUNCTION(7, "DBG_MON_A24") + ), + MTK_PIN( + 134, "GPIO134", + MTK_EINT_FUNCTION(0, 134), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "CMVREF4"), + MTK_FUNCTION(2, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(3, "SCP_JTAG0_TRSTN"), + MTK_FUNCTION(4, "MD32_0_JTAG_TRST"), + MTK_FUNCTION(6, "CONN_WF_MCU_TRST_B"), + MTK_FUNCTION(7, "DBG_MON_A27") + ), + MTK_PIN( + 135, "GPIO135", + MTK_EINT_FUNCTION(0, 135), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "PWM_0"), + MTK_FUNCTION(2, "SRCLKENAI1"), + MTK_FUNCTION(3, "MD_URXD0"), + MTK_FUNCTION(4, "MD32_0_RXD"), + MTK_FUNCTION(5, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(6, "CONN_WF_MCU_DBGI_N"), + MTK_FUNCTION(7, "DBG_MON_A29") + ), + MTK_PIN( + 136, "GPIO136", + MTK_EINT_FUNCTION(0, 136), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "CMMCLK3"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "MD_UTXD0"), + MTK_FUNCTION(4, "MD32_0_TXD"), + MTK_FUNCTION(5, "CONN_BT_TXD"), + MTK_FUNCTION(6, "CONN_WF_MCU_DBGACK_N"), + MTK_FUNCTION(7, "DBG_MON_A25") + ), + MTK_PIN( + 137, "GPIO137", + MTK_EINT_FUNCTION(0, 137), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "CMMCLK4"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "MD_URXD1"), + MTK_FUNCTION(4, "MD32_1_RXD"), + MTK_FUNCTION(5, "ILDO_DOUT0"), + MTK_FUNCTION(6, "CONN_BGF_UART0_RXD") + ), + MTK_PIN( + 138, "GPIO138", + MTK_EINT_FUNCTION(0, 138), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "CMMCLK5"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "MD_UTXD1"), + MTK_FUNCTION(4, "MD32_1_TXD"), + MTK_FUNCTION(5, "ILDO_DOUT1"), + MTK_FUNCTION(6, "CONN_BGF_UART0_TXD") + ), + MTK_PIN( + 139, "GPIO139", + MTK_EINT_FUNCTION(0, 139), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "SCL4") + ), + MTK_PIN( + 140, "GPIO140", + MTK_EINT_FUNCTION(0, 140), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "SDA4") + ), + MTK_PIN( + 141, "GPIO141", + MTK_EINT_FUNCTION(0, 141), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "SCL2") + ), + MTK_PIN( + 142, "GPIO142", + MTK_EINT_FUNCTION(0, 142), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "SDA2") + ), + MTK_PIN( + 143, "GPIO143", + MTK_EINT_FUNCTION(0, 143), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "CMVREF0"), + MTK_FUNCTION(2, "SPI3_CLK"), + MTK_FUNCTION(3, "ADSP_JTAG1_TDO"), + MTK_FUNCTION(4, "SCP_JTAG1_TDO"), + MTK_FUNCTION(5, "MD32_1_JTAG_TDO"), + MTK_FUNCTION(6, "CONN_BGF_DSP_L5_JDO") + ), + MTK_PIN( + 144, "GPIO144", + MTK_EINT_FUNCTION(0, 144), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "CMVREF1"), + MTK_FUNCTION(2, "SPI3_CSB"), + MTK_FUNCTION(3, "ADSP_JTAG1_TDI"), + MTK_FUNCTION(4, "SCP_JTAG1_TDI"), + MTK_FUNCTION(5, "MD32_1_JTAG_TDI"), + MTK_FUNCTION(6, "CONN_BGF_DSP_L5_JDI") + ), + MTK_PIN( + 145, "GPIO145", + MTK_EINT_FUNCTION(0, 145), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "CMVREF2"), + MTK_FUNCTION(2, "SPI3_MI"), + MTK_FUNCTION(3, "ADSP_JTAG1_TMS"), + MTK_FUNCTION(4, "SCP_JTAG1_TMS"), + MTK_FUNCTION(5, "MD32_1_JTAG_TMS"), + MTK_FUNCTION(6, "CONN_BGF_DSP_L5_JMS") + ), + MTK_PIN( + 146, "GPIO146", + MTK_EINT_FUNCTION(0, 146), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "CMVREF3"), + MTK_FUNCTION(2, "SPI3_MO"), + MTK_FUNCTION(3, "ADSP_JTAG1_TCK"), + MTK_FUNCTION(4, "SCP_JTAG1_TCK"), + MTK_FUNCTION(5, "MD32_1_JTAG_TCK"), + MTK_FUNCTION(6, "CONN_BGF_DSP_L5_JCK") + ), + MTK_PIN( + 147, "GPIO147", + MTK_EINT_FUNCTION(0, 147), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "CMVREF4"), + MTK_FUNCTION(2, "EXT_FRAME_SYNC"), + MTK_FUNCTION(3, "ADSP_JTAG1_TRSTN"), + MTK_FUNCTION(4, "SCP_JTAG1_TRSTN"), + MTK_FUNCTION(5, "MD32_1_JTAG_TRST"), + MTK_FUNCTION(6, "CONN_BGF_DSP_L5_JINTP") + ), + MTK_PIN( + 148, "GPIO148", + MTK_EINT_FUNCTION(0, 148), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "PWM_1"), + MTK_FUNCTION(2, "AGPS_SYNC"), + MTK_FUNCTION(3, "CMMCLK5"), + MTK_FUNCTION(6, "CONN_WF_MCU_AICE_TMSC") + ), + MTK_PIN( + 149, "GPIO149", + MTK_EINT_FUNCTION(0, 149), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(1, "CMMCLK0"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "MD32_0_GPIO0"), + MTK_FUNCTION(6, "CONN_WF_MCU_AICE_TCKC") + ), + MTK_PIN( + 150, "GPIO150", + MTK_EINT_FUNCTION(0, 150), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(1, "CMMCLK1"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "MD32_0_GPIO1"), + MTK_FUNCTION(6, "CONN_BGF_MCU_AICE_TMSC") + ), + MTK_PIN( + 151, "GPIO151", + MTK_EINT_FUNCTION(0, 151), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(1, "CMMCLK2"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "MD32_0_GPIO2"), + MTK_FUNCTION(6, "CONN_BGF_MCU_AICE_TCKC") + ), + MTK_PIN( + 152, "GPIO152", + MTK_EINT_FUNCTION(0, 152), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(1, "KPROW1"), + MTK_FUNCTION(2, "PWM_2"), + MTK_FUNCTION(3, "IDDIG"), + MTK_FUNCTION(4, "DP_TX_HPD"), + MTK_FUNCTION(5, "DSI1_TE"), + MTK_FUNCTION(6, "MBISTREADEN_TRIGGER"), + MTK_FUNCTION(7, "DBG_MON_B2") + ), + MTK_PIN( + 153, "GPIO153", + MTK_EINT_FUNCTION(0, 153), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(1, "KPROW0"), + MTK_FUNCTION(7, "DBG_MON_B1") + ), + MTK_PIN( + 154, "GPIO154", + MTK_EINT_FUNCTION(0, 154), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO154"), + MTK_FUNCTION(1, "KPCOL0"), + MTK_FUNCTION(7, "DBG_MON_A32") + ), + MTK_PIN( + 155, "GPIO155", + MTK_EINT_FUNCTION(0, 155), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO155"), + MTK_FUNCTION(1, "KPCOL1"), + MTK_FUNCTION(2, "PWM_3"), + MTK_FUNCTION(3, "USB_DRVVBUS"), + MTK_FUNCTION(4, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(5, "LCM1_RST"), + MTK_FUNCTION(6, "MBISTWRITEEN_TRIGGER"), + MTK_FUNCTION(7, "DBG_MON_B0") + ), + MTK_PIN( + 156, "GPIO156", + MTK_EINT_FUNCTION(0, 156), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO156"), + MTK_FUNCTION(1, "SPI1_A_CLK"), + MTK_FUNCTION(2, "SCP_SPI1_A_CK"), + MTK_FUNCTION(3, "MRG_CLK"), + MTK_FUNCTION(4, "AGPS_SYNC"), + MTK_FUNCTION(5, "SCL12"), + MTK_FUNCTION(7, "DBG_MON_B3") + ), + MTK_PIN( + 157, "GPIO157", + MTK_EINT_FUNCTION(0, 157), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO157"), + MTK_FUNCTION(1, "SPI1_A_CSB"), + MTK_FUNCTION(2, "SCP_SPI1_A_CS"), + MTK_FUNCTION(3, "MRG_SYNC"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(5, "SDA12"), + MTK_FUNCTION(7, "DBG_MON_B4") + ), + MTK_PIN( + 158, "GPIO158", + MTK_EINT_FUNCTION(0, 158), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO158"), + MTK_FUNCTION(1, "SPI1_A_MI"), + MTK_FUNCTION(2, "SCP_SPI1_A_MI"), + MTK_FUNCTION(3, "MRG_DI"), + MTK_FUNCTION(4, "PTA_RXD"), + MTK_FUNCTION(5, "SCL13"), + MTK_FUNCTION(7, "DBG_MON_B5") + ), + MTK_PIN( + 159, "GPIO159", + MTK_EINT_FUNCTION(0, 159), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO159"), + MTK_FUNCTION(1, "SPI1_A_MO"), + MTK_FUNCTION(2, "SCP_SPI1_A_MO"), + MTK_FUNCTION(3, "MRG_DO"), + MTK_FUNCTION(4, "PTA_TXD"), + MTK_FUNCTION(5, "SDA13"), + MTK_FUNCTION(7, "DBG_MON_B6") + ), + MTK_PIN( + 160, "GPIO160", + MTK_EINT_FUNCTION(0, 160), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO160"), + MTK_FUNCTION(1, "SCL3"), + MTK_FUNCTION(2, "SCP_SCL0"), + MTK_FUNCTION(3, "SCP_SCL1") + ), + MTK_PIN( + 161, "GPIO161", + MTK_EINT_FUNCTION(0, 161), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO161"), + MTK_FUNCTION(1, "SDA3"), + MTK_FUNCTION(2, "SCP_SDA0"), + MTK_FUNCTION(3, "SCP_SDA1") + ), + MTK_PIN( + 162, "GPIO162", + MTK_EINT_FUNCTION(0, 162), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO162"), + MTK_FUNCTION(1, "ANT_SEL0"), + MTK_FUNCTION(2, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(7, "DBG_MON_B7") + ), + MTK_PIN( + 163, "GPIO163", + MTK_EINT_FUNCTION(0, 163), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO163"), + MTK_FUNCTION(1, "ANT_SEL1"), + MTK_FUNCTION(2, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(7, "DBG_MON_B8") + ), + MTK_PIN( + 164, "GPIO164", + MTK_EINT_FUNCTION(0, 164), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO164"), + MTK_FUNCTION(1, "ANT_SEL2"), + MTK_FUNCTION(2, "SCP_SPI1_B_CK"), + MTK_FUNCTION(3, "TP_URXD1_AO"), + MTK_FUNCTION(5, "UCTS0"), + MTK_FUNCTION(7, "DBG_MON_B9") + ), + MTK_PIN( + 165, "GPIO165", + MTK_EINT_FUNCTION(0, 165), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO165"), + MTK_FUNCTION(1, "ANT_SEL3"), + MTK_FUNCTION(2, "SCP_SPI1_B_CS"), + MTK_FUNCTION(3, "TP_UTXD1_AO"), + MTK_FUNCTION(4, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(5, "URTS0"), + MTK_FUNCTION(7, "DBG_MON_B10") + ), + MTK_PIN( + 166, "GPIO166", + MTK_EINT_FUNCTION(0, 166), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO166"), + MTK_FUNCTION(1, "ANT_SEL4"), + MTK_FUNCTION(2, "SCP_SPI1_B_MI"), + MTK_FUNCTION(3, "TP_URXD2_AO"), + MTK_FUNCTION(4, "SRCLKENAI1"), + MTK_FUNCTION(5, "UCTS1"), + MTK_FUNCTION(7, "DBG_MON_B11") + ), + MTK_PIN( + 167, "GPIO167", + MTK_EINT_FUNCTION(0, 167), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO167"), + MTK_FUNCTION(1, "ANT_SEL5"), + MTK_FUNCTION(2, "SCP_SPI1_B_MO"), + MTK_FUNCTION(3, "TP_UTXD2_AO"), + MTK_FUNCTION(4, "SRCLKENAI0"), + MTK_FUNCTION(5, "URTS1"), + MTK_FUNCTION(7, "DBG_MON_B12") + ), + MTK_PIN( + 168, "GPIO168", + MTK_EINT_FUNCTION(0, 168), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO168"), + MTK_FUNCTION(1, "ANT_SEL6"), + MTK_FUNCTION(2, "SPI0_B_CLK"), + MTK_FUNCTION(3, "TP_UCTS1_AO"), + MTK_FUNCTION(4, "KPCOL2"), + MTK_FUNCTION(5, "MD_UCTS0"), + MTK_FUNCTION(6, "SCL12"), + MTK_FUNCTION(7, "DBG_MON_B13") + ), + MTK_PIN( + 169, "GPIO169", + MTK_EINT_FUNCTION(0, 169), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO169"), + MTK_FUNCTION(1, "ANT_SEL7"), + MTK_FUNCTION(2, "SPI0_B_CSB"), + MTK_FUNCTION(3, "TP_URTS1_AO"), + MTK_FUNCTION(4, "KPROW2"), + MTK_FUNCTION(5, "MD_URTS0"), + MTK_FUNCTION(6, "SDA12"), + MTK_FUNCTION(7, "DBG_MON_B14") + ), + MTK_PIN( + 170, "GPIO170", + MTK_EINT_FUNCTION(0, 170), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO170"), + MTK_FUNCTION(1, "ANT_SEL8"), + MTK_FUNCTION(2, "SPI0_B_MI"), + MTK_FUNCTION(3, "TP_UCTS2_AO"), + MTK_FUNCTION(4, "SRCLKENAI1"), + MTK_FUNCTION(5, "MD_UCTS1"), + MTK_FUNCTION(6, "SCL13") + ), + MTK_PIN( + 171, "GPIO171", + MTK_EINT_FUNCTION(0, 171), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO171"), + MTK_FUNCTION(1, "ANT_SEL9"), + MTK_FUNCTION(2, "SPI0_B_MO"), + MTK_FUNCTION(3, "TP_URTS2_AO"), + MTK_FUNCTION(4, "SRCLKENAI0"), + MTK_FUNCTION(5, "MD_URTS1"), + MTK_FUNCTION(6, "SDA13") + ), + MTK_PIN( + 172, "GPIO172", + MTK_EINT_FUNCTION(0, 172), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO172"), + MTK_FUNCTION(1, "CONN_TOP_CLK"), + MTK_FUNCTION(2, "AUXIF_CLK0"), + MTK_FUNCTION(7, "DBG_MON_B18") + ), + MTK_PIN( + 173, "GPIO173", + MTK_EINT_FUNCTION(0, 173), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO173"), + MTK_FUNCTION(1, "CONN_TOP_DATA"), + MTK_FUNCTION(2, "AUXIF_ST0"), + MTK_FUNCTION(7, "DBG_MON_B19") + ), + MTK_PIN( + 174, "GPIO174", + MTK_EINT_FUNCTION(0, 174), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO174"), + MTK_FUNCTION(1, "CONN_HRST_B"), + MTK_FUNCTION(7, "DBG_MON_B17") + ), + MTK_PIN( + 175, "GPIO175", + MTK_EINT_FUNCTION(0, 175), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO175"), + MTK_FUNCTION(1, "CONN_WB_PTA"), + MTK_FUNCTION(7, "DBG_MON_B20") + ), + MTK_PIN( + 176, "GPIO176", + MTK_EINT_FUNCTION(0, 176), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO176"), + MTK_FUNCTION(1, "CONN_BT_CLK"), + MTK_FUNCTION(2, "AUXIF_CLK1"), + MTK_FUNCTION(7, "DBG_MON_B15") + ), + MTK_PIN( + 177, "GPIO177", + MTK_EINT_FUNCTION(0, 177), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO177"), + MTK_FUNCTION(1, "CONN_BT_DATA"), + MTK_FUNCTION(2, "AUXIF_ST1"), + MTK_FUNCTION(7, "DBG_MON_B16") + ), + MTK_PIN( + 178, "GPIO178", + MTK_EINT_FUNCTION(0, 178), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO178"), + MTK_FUNCTION(1, "CONN_WF_CTRL0"), + MTK_FUNCTION(7, "DBG_MON_B21") + ), + MTK_PIN( + 179, "GPIO179", + MTK_EINT_FUNCTION(0, 179), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO179"), + MTK_FUNCTION(1, "CONN_WF_CTRL1"), + MTK_FUNCTION(2, "UFS_MPHY_SCL"), + MTK_FUNCTION(7, "DBG_MON_B22") + ), + MTK_PIN( + 180, "GPIO180", + MTK_EINT_FUNCTION(0, 180), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO180"), + MTK_FUNCTION(1, "CONN_WF_CTRL2"), + MTK_FUNCTION(2, "UFS_MPHY_SDA"), + MTK_FUNCTION(7, "DBG_MON_B23") + ), + MTK_PIN( + 181, "GPIO181", + MTK_EINT_FUNCTION(0, 181), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO181"), + MTK_FUNCTION(1, "CONN_WF_CTRL3"), + MTK_FUNCTION(2, "UFS_UNIPRO_SDA") + ), + MTK_PIN( + 182, "GPIO182", + MTK_EINT_FUNCTION(0, 182), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO182"), + MTK_FUNCTION(1, "CONN_WF_CTRL4"), + MTK_FUNCTION(2, "UFS_UNIPRO_SCL") + ), + MTK_PIN( + 183, "GPIO183", + MTK_EINT_FUNCTION(0, 183), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO183"), + MTK_FUNCTION(1, "MSDC0_CMD") + ), + MTK_PIN( + 184, "GPIO184", + MTK_EINT_FUNCTION(0, 184), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO184"), + MTK_FUNCTION(1, "MSDC0_DAT0") + ), + MTK_PIN( + 185, "GPIO185", + MTK_EINT_FUNCTION(0, 185), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO185"), + MTK_FUNCTION(1, "MSDC0_DAT2") + ), + MTK_PIN( + 186, "GPIO186", + MTK_EINT_FUNCTION(0, 186), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO186"), + MTK_FUNCTION(1, "MSDC0_DAT4") + ), + MTK_PIN( + 187, "GPIO187", + MTK_EINT_FUNCTION(0, 187), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO187"), + MTK_FUNCTION(1, "MSDC0_DAT6") + ), + MTK_PIN( + 188, "GPIO188", + MTK_EINT_FUNCTION(0, 188), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO188"), + MTK_FUNCTION(1, "MSDC0_DAT1") + ), + MTK_PIN( + 189, "GPIO189", + MTK_EINT_FUNCTION(0, 189), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO189"), + MTK_FUNCTION(1, "MSDC0_DAT5") + ), + MTK_PIN( + 190, "GPIO190", + MTK_EINT_FUNCTION(0, 190), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO190"), + MTK_FUNCTION(1, "MSDC0_DAT7") + ), + MTK_PIN( + 191, "GPIO191", + MTK_EINT_FUNCTION(0, 191), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO191"), + MTK_FUNCTION(1, "MSDC0_DSL"), + MTK_FUNCTION(2, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(3, "IDDIG"), + MTK_FUNCTION(4, "DMIC_CLK"), + MTK_FUNCTION(5, "DSI1_TE") + ), + MTK_PIN( + 192, "GPIO192", + MTK_EINT_FUNCTION(0, 192), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO192"), + MTK_FUNCTION(1, "MSDC0_CLK"), + MTK_FUNCTION(2, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(3, "USB_DRVVBUS"), + MTK_FUNCTION(4, "DMIC_DAT"), + MTK_FUNCTION(5, "LCM1_RST") + ), + MTK_PIN( + 193, "GPIO193", + MTK_EINT_FUNCTION(0, 193), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO193"), + MTK_FUNCTION(1, "MSDC0_DAT3") + ), + MTK_PIN( + 194, "GPIO194", + MTK_EINT_FUNCTION(0, 194), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO194"), + MTK_FUNCTION(1, "MSDC0_RSTB") + ), + MTK_PIN( + 195, "GPIO195", + MTK_EINT_FUNCTION(0, 195), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO195"), + MTK_FUNCTION(1, "SCP_VREQ_VAO"), + MTK_FUNCTION(2, "DVFSRC_EXT_REQ") + ), + MTK_PIN( + 196, "GPIO196", + MTK_EINT_FUNCTION(0, 196), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO196"), + MTK_FUNCTION(1, "AUD_DAT_MOSI2"), + MTK_FUNCTION(7, "DBG_MON_B27") + ), + MTK_PIN( + 197, "GPIO197", + MTK_EINT_FUNCTION(0, 197), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO197"), + MTK_FUNCTION(1, "AUD_NLE_MOSI1"), + MTK_FUNCTION(2, "AUD_CLK_MISO"), + MTK_FUNCTION(3, "I2S2_MCK"), + MTK_FUNCTION(4, "I2S6_MCK"), + MTK_FUNCTION(5, "I2S8_MCK"), + MTK_FUNCTION(6, "UFS_UNIPRO_SDA"), + MTK_FUNCTION(7, "DBG_MON_B28") + ), + MTK_PIN( + 198, "GPIO198", + MTK_EINT_FUNCTION(0, 198), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO198"), + MTK_FUNCTION(1, "AUD_NLE_MOSI0"), + MTK_FUNCTION(2, "AUD_SYNC_MISO"), + MTK_FUNCTION(3, "I2S2_BCK"), + MTK_FUNCTION(4, "I2S6_BCK"), + MTK_FUNCTION(5, "I2S8_BCK"), + MTK_FUNCTION(7, "DBG_MON_B29") + ), + MTK_PIN( + 199, "GPIO199", + MTK_EINT_FUNCTION(0, 199), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO199"), + MTK_FUNCTION(1, "AUD_DAT_MISO2"), + MTK_FUNCTION(3, "I2S2_DI2"), + MTK_FUNCTION(7, "DBG_MON_B32") + ), + MTK_PIN( + 200, "GPIO200", + MTK_EINT_FUNCTION(0, 200), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO200"), + MTK_FUNCTION(1, "SCL6"), + MTK_FUNCTION(2, "SCP_SCL0"), + MTK_FUNCTION(3, "SCP_SCL1"), + MTK_FUNCTION(4, "SCL_6306") + ), + MTK_PIN( + 201, "GPIO201", + MTK_EINT_FUNCTION(0, 201), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO201"), + MTK_FUNCTION(1, "SDA6"), + MTK_FUNCTION(2, "SCP_SDA0"), + MTK_FUNCTION(3, "SCP_SDA1"), + MTK_FUNCTION(4, "SDA_6306") + ), + MTK_PIN( + 202, "GPIO202", + MTK_EINT_FUNCTION(0, 202), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO202"), + MTK_FUNCTION(1, "SCL5") + ), + MTK_PIN( + 203, "GPIO203", + MTK_EINT_FUNCTION(0, 203), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO203"), + MTK_FUNCTION(1, "SDA5") + ), + MTK_PIN( + 204, "GPIO204", + MTK_EINT_FUNCTION(0, 204), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO204"), + MTK_FUNCTION(1, "SCL0"), + MTK_FUNCTION(2, "SPI4_C_CLK"), + MTK_FUNCTION(3, "SPI7_B_CLK") + ), + MTK_PIN( + 205, "GPIO205", + MTK_EINT_FUNCTION(0, 205), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO205"), + MTK_FUNCTION(1, "SDA0"), + MTK_FUNCTION(2, "SPI4_C_CSB"), + MTK_FUNCTION(3, "SPI7_B_CSB") + ), + MTK_PIN( + 206, "GPIO206", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO206"), + MTK_FUNCTION(1, "SRCLKENA0") + ), + MTK_PIN( + 207, "GPIO207", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO207"), + MTK_FUNCTION(1, "SRCLKENA1") + ), + MTK_PIN( + 208, "GPIO208", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO208"), + MTK_FUNCTION(1, "WATCHDOG") + ), + MTK_PIN( + 209, "GPIO209", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO209"), + MTK_FUNCTION(1, "PWRAP_SPI0_MI"), + MTK_FUNCTION(2, "PWRAP_SPI0_MO") + ), + MTK_PIN( + 210, "GPIO210", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO210"), + MTK_FUNCTION(1, "PWRAP_SPI0_CSN") + ), + MTK_PIN( + 211, "GPIO211", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO211"), + MTK_FUNCTION(1, "PWRAP_SPI0_MO"), + MTK_FUNCTION(2, "PWRAP_SPI0_MI") + ), + MTK_PIN( + 212, "GPIO212", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO212"), + MTK_FUNCTION(1, "PWRAP_SPI0_CK") + ), + MTK_PIN( + 213, "GPIO213", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO213"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + MTK_PIN( + 214, "GPIO214", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO214"), + MTK_FUNCTION(1, "AUD_CLK_MOSI"), + MTK_FUNCTION(3, "I2S1_MCK"), + MTK_FUNCTION(4, "I2S7_MCK"), + MTK_FUNCTION(5, "I2S9_MCK"), + MTK_FUNCTION(6, "UFS_UNIPRO_SCL") + ), + MTK_PIN( + 215, "GPIO215", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO215"), + MTK_FUNCTION(1, "AUD_SYNC_MOSI"), + MTK_FUNCTION(3, "I2S1_BCK"), + MTK_FUNCTION(4, "I2S7_BCK"), + MTK_FUNCTION(5, "I2S9_BCK"), + MTK_FUNCTION(7, "DBG_MON_B24") + ), + MTK_PIN( + 216, "GPIO216", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO216"), + MTK_FUNCTION(1, "AUD_DAT_MOSI0"), + MTK_FUNCTION(3, "I2S1_LRCK"), + MTK_FUNCTION(4, "I2S7_LRCK"), + MTK_FUNCTION(5, "I2S9_LRCK"), + MTK_FUNCTION(7, "DBG_MON_B25") + ), + MTK_PIN( + 217, "GPIO217", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO217"), + MTK_FUNCTION(1, "AUD_DAT_MOSI1"), + MTK_FUNCTION(3, "I2S1_DO"), + MTK_FUNCTION(4, "I2S7_DO"), + MTK_FUNCTION(5, "I2S9_DO"), + MTK_FUNCTION(6, "UFS_MPHY_SDA"), + MTK_FUNCTION(7, "DBG_MON_B26") + ), + MTK_PIN( + 218, "GPIO218", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO218"), + MTK_FUNCTION(1, "AUD_DAT_MISO0"), + MTK_FUNCTION(2, "VOW_DAT_MISO"), + MTK_FUNCTION(3, "I2S2_LRCK"), + MTK_FUNCTION(4, "I2S6_LRCK"), + MTK_FUNCTION(5, "I2S8_LRCK"), + MTK_FUNCTION(7, "DBG_MON_B30") + ), + MTK_PIN( + 219, "GPIO219", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO219"), + MTK_FUNCTION(1, "AUD_DAT_MISO1"), + MTK_FUNCTION(2, "VOW_CLK_MISO"), + MTK_FUNCTION(3, "I2S2_DI"), + MTK_FUNCTION(4, "I2S6_DI"), + MTK_FUNCTION(5, "I2S8_DI"), + MTK_FUNCTION(6, "UFS_MPHY_SCL"), + MTK_FUNCTION(7, "DBG_MON_B31") + ), + MTK_PIN( + 220, "GPIO220", + MTK_EINT_FUNCTION(0, 216), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 221, "GPIO221", + MTK_EINT_FUNCTION(0, 217), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 222, "GPIO222", + MTK_EINT_FUNCTION(0, 218), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 223, "GPIO223", + MTK_EINT_FUNCTION(0, 219), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 224, "GPIO224", + MTK_EINT_FUNCTION(0, 220), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 225, "GPIO225", + MTK_EINT_FUNCTION(0, 222), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 226, "GPIO226", + MTK_EINT_FUNCTION(0, 223), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), +}; + +#endif /* __PINCTRL_MTK_MT6893_H */ diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8196.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8196.h new file mode 100644 index 000000000000..c2a7e239a234 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8196.h @@ -0,0 +1,3085 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Guodong Liu <Guodong.Liu@mediatek.com> + */ + +#ifndef __PINCTRL_MTK_MT8196_H +#define __PINCTRL_MTK_MT8196_H + +#include "pinctrl-paris.h" +#define EINT_INVALID_BASE 0xff + +static const struct mtk_pin_desc mtk_pins_mt8196[] = { + MTK_PIN( + 0, "GPIO0", + MTK_EINT_FUNCTION(0, 0), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "DMIC1_CLK"), + MTK_FUNCTION(3, "SPI3_A_MO"), + MTK_FUNCTION(4, "FMI2S_B_LRCK"), + MTK_FUNCTION(5, "SCP_DMIC1_CLK"), + MTK_FUNCTION(6, "TP_GPIO14_AO") + ), + MTK_PIN( + 1, "GPIO1", + MTK_EINT_FUNCTION(0, 1), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "DMIC1_DAT"), + MTK_FUNCTION(2, "SRCLKENAI1"), + MTK_FUNCTION(3, "SPI3_A_MI"), + MTK_FUNCTION(4, "FMI2S_B_DI"), + MTK_FUNCTION(5, "SCP_DMIC1_DAT"), + MTK_FUNCTION(6, "TP_GPIO15_AO") + ), + MTK_PIN( + 2, "GPIO2", + MTK_EINT_FUNCTION(0, 2), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "PWM_VLP"), + MTK_FUNCTION(2, "DSI_HSYNC"), + MTK_FUNCTION(5, "RG_TSFDC_LDO_EN"), + MTK_FUNCTION(6, "TP_GPIO8_AO") + ), + MTK_PIN( + 3, "GPIO3", + MTK_EINT_FUNCTION(0, 3), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "MD_INT0"), + MTK_FUNCTION(2, "DSI1_HSYNC"), + MTK_FUNCTION(5, "DA_TSFDC_LDO_MODE"), + MTK_FUNCTION(6, "TP_GPIO9_AO") + ), + MTK_PIN( + 4, "GPIO4", + MTK_EINT_FUNCTION(0, 4), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "DISP_PWM1"), + MTK_FUNCTION(2, "MD32_0_GPIO0") + ), + MTK_PIN( + 5, "GPIO5", + MTK_EINT_FUNCTION(0, 5), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "LCM1_RST"), + MTK_FUNCTION(2, "SPI7_A_CLK") + ), + MTK_PIN( + 6, "GPIO6", + MTK_EINT_FUNCTION(0, 6), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "DSI1_TE"), + MTK_FUNCTION(2, "SPI7_A_CSB") + ), + MTK_PIN( + 7, "GPIO7", + MTK_EINT_FUNCTION(0, 7), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(2, "SPI7_A_MO"), + MTK_FUNCTION(3, "GPS_PPS0") + ), + MTK_PIN( + 8, "GPIO8", + MTK_EINT_FUNCTION(0, 8), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(2, "SPI7_A_MI"), + MTK_FUNCTION(3, "EDP_TX_HPD") + ), + MTK_PIN( + 9, "GPIO9", + MTK_EINT_FUNCTION(0, 9), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(3, "I2SIN1_LRCK"), + MTK_FUNCTION(7, "RG_TSFDC_LDO_REFSEL0") + ), + MTK_PIN( + 10, "GPIO10", + MTK_EINT_FUNCTION(0, 10), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(3, "I2SOUT1_DO"), + MTK_FUNCTION(7, "RG_TSFDC_LDO_REFSEL1") + ), + MTK_PIN( + 11, "GPIO11", + MTK_EINT_FUNCTION(0, 11), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(4, "FMI2S_B_BCK"), + MTK_FUNCTION(7, "DBG_MON_A30") + ), + MTK_PIN( + 12, "GPIO12", + MTK_EINT_FUNCTION(0, 12), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(3, "I2SIN1_DI_B") + ), + MTK_PIN( + 13, "GPIO13", + MTK_EINT_FUNCTION(0, 13), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "EDP_TX_HPD"), + MTK_FUNCTION(2, "GPS_PPS1") + ), + MTK_PIN( + 14, "GPIO14", + MTK_EINT_FUNCTION(0, 14), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "SRCLKENA2"), + MTK_FUNCTION(2, "DSI2_TE"), + MTK_FUNCTION(3, "SPMI_P_TRIG_FLAG"), + MTK_FUNCTION(5, "MD_INT3"), + MTK_FUNCTION(6, "TP_GPIO8_AO") + ), + MTK_PIN( + 15, "GPIO15", + MTK_EINT_FUNCTION(0, 15), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "SPMI_M_TRIG_FLAG"), + MTK_FUNCTION(3, "UCTS0"), + MTK_FUNCTION(4, "MD_INT4"), + MTK_FUNCTION(5, "I2SOUT2_DO"), + MTK_FUNCTION(6, "TP_GPIO9_AO") + ), + MTK_PIN( + 16, "GPIO16", + MTK_EINT_FUNCTION(0, 16), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "SRCLKENAI1"), + MTK_FUNCTION(2, "DP_TX_HPD"), + MTK_FUNCTION(3, "URTS0"), + MTK_FUNCTION(4, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(5, "KPROW2"), + MTK_FUNCTION(6, "TP_GPIO10_AO") + ), + MTK_PIN( + 17, "GPIO17", + MTK_EINT_FUNCTION(0, 17), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "MD_INT0"), + MTK_FUNCTION(2, "DP_OC_EN"), + MTK_FUNCTION(3, "UCTS1"), + MTK_FUNCTION(4, "MD_NTN_URXD1"), + MTK_FUNCTION(5, "KPCOL2"), + MTK_FUNCTION(6, "TP_GPIO11_AO") + ), + MTK_PIN( + 18, "GPIO18", + MTK_EINT_FUNCTION(0, 18), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "DMIC1_CLK"), + MTK_FUNCTION(2, "DP_RAUX_SBU1"), + MTK_FUNCTION(3, "URTS1"), + MTK_FUNCTION(4, "MD_NTN_UTXD1"), + MTK_FUNCTION(5, "I2SIN2_DI"), + MTK_FUNCTION(6, "TP_UTXD_GNSS_VLP") + ), + MTK_PIN( + 19, "GPIO19", + MTK_EINT_FUNCTION(0, 19), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "DMIC1_DAT"), + MTK_FUNCTION(2, "DP_RAUX_SBU2"), + MTK_FUNCTION(3, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(4, "CLKM3_A"), + MTK_FUNCTION(5, "I2SIN2_BCK"), + MTK_FUNCTION(6, "TP_URXD_GNSS_VLP") + ), + MTK_PIN( + 20, "GPIO20", + MTK_EINT_FUNCTION(0, 20), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "IDDIG"), + MTK_FUNCTION(2, "LCM2_RST"), + MTK_FUNCTION(3, "GPS_PPS1"), + MTK_FUNCTION(4, "CLKM2_A") + ), + MTK_PIN( + 21, "GPIO21", + MTK_EINT_FUNCTION(0, 21), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "BPI_BUS11"), + MTK_FUNCTION(2, "PCIE_PERSTN_1P"), + MTK_FUNCTION(3, "DSI1_TE"), + MTK_FUNCTION(4, "DMIC_CLK"), + MTK_FUNCTION(5, "SCP_DMIC_CLK") + ), + MTK_PIN( + 22, "GPIO22", + MTK_EINT_FUNCTION(0, 22), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "BPI_BUS12"), + MTK_FUNCTION(2, "PCIE_CLKREQN_1P"), + MTK_FUNCTION(3, "DSI2_TE"), + MTK_FUNCTION(4, "DMIC_DAT"), + MTK_FUNCTION(5, "SCP_DMIC_DAT") + ), + MTK_PIN( + 23, "GPIO23", + MTK_EINT_FUNCTION(0, 23), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "BPI_BUS13"), + MTK_FUNCTION(2, "PCIE_WAKEN_1P"), + MTK_FUNCTION(3, "DSI3_TE"), + MTK_FUNCTION(4, "DMIC1_CLK"), + MTK_FUNCTION(5, "SCP_DMIC1_CLK") + ), + MTK_PIN( + 24, "GPIO24", + MTK_EINT_FUNCTION(0, 24), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "BPI_BUS14"), + MTK_FUNCTION(2, "LCM1_RST"), + MTK_FUNCTION(3, "AGPS_SYNC"), + MTK_FUNCTION(4, "DMIC1_DAT"), + MTK_FUNCTION(5, "SCP_DMIC1_DAT"), + MTK_FUNCTION(6, "DISP_PWM1") + ), + MTK_PIN( + 25, "GPIO25", + MTK_EINT_FUNCTION(0, 25), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "BPI_BUS15"), + MTK_FUNCTION(2, "LCM2_RST"), + MTK_FUNCTION(3, "SRCLKENAI1"), + MTK_FUNCTION(4, "DMIC2_CLK"), + MTK_FUNCTION(6, "DISP_PWM2") + ), + MTK_PIN( + 26, "GPIO26", + MTK_EINT_FUNCTION(0, 26), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "BPI_BUS16"), + MTK_FUNCTION(2, "LCM3_RST"), + MTK_FUNCTION(4, "DMIC2_DAT"), + MTK_FUNCTION(6, "DISP_PWM3") + ), + MTK_PIN( + 27, "GPIO27", + MTK_EINT_FUNCTION(0, 27), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "BPI_BUS17"), + MTK_FUNCTION(2, "UTXD4"), + MTK_FUNCTION(6, "DISP_PWM4"), + MTK_FUNCTION(7, "DBG_MON_A20") + ), + MTK_PIN( + 28, "GPIO28", + MTK_EINT_FUNCTION(0, 28), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "BPI_BUS18"), + MTK_FUNCTION(2, "URXD4"), + MTK_FUNCTION(3, "SPI2_A_MI"), + MTK_FUNCTION(4, "CLKM0_A"), + MTK_FUNCTION(7, "DBG_MON_A21") + ), + MTK_PIN( + 29, "GPIO29", + MTK_EINT_FUNCTION(0, 29), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "BPI_BUS19"), + MTK_FUNCTION(2, "MD_NTN_UTXD1"), + MTK_FUNCTION(3, "SPI2_A_MO"), + MTK_FUNCTION(4, "CLKM1_A"), + MTK_FUNCTION(6, "UCTS4"), + MTK_FUNCTION(7, "DBG_MON_A17") + ), + MTK_PIN( + 30, "GPIO30", + MTK_EINT_FUNCTION(0, 30), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "BPI_BUS20"), + MTK_FUNCTION(2, "MD_NTN_URXD1"), + MTK_FUNCTION(3, "SPI2_A_CLK"), + MTK_FUNCTION(4, "CLKM2_A"), + MTK_FUNCTION(5, "DSI3_HSYNC"), + MTK_FUNCTION(6, "URTS4"), + MTK_FUNCTION(7, "DBG_MON_A18") + ), + MTK_PIN( + 31, "GPIO31", + MTK_EINT_FUNCTION(0, 31), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "BPI_BUS21"), + MTK_FUNCTION(3, "SPI2_A_CSB"), + MTK_FUNCTION(4, "CLKM3_A"), + MTK_FUNCTION(6, "EDP_TX_HPD"), + MTK_FUNCTION(7, "DBG_MON_A19") + ), + MTK_PIN( + 32, "GPIO32", + MTK_EINT_FUNCTION(0, 32), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "LCM4_RST"), + MTK_FUNCTION(2, "DP_TX_HPD"), + MTK_FUNCTION(3, "SSPM_JTAG_TCK_VLP"), + MTK_FUNCTION(4, "ADSP_JTAG0_TCK"), + MTK_FUNCTION(5, "SCP_JTAG0_TCK_VLP"), + MTK_FUNCTION(6, "SPU0_TCK"), + MTK_FUNCTION(7, "IO_JTAG_TCK") + ), + MTK_PIN( + 33, "GPIO33", + MTK_EINT_FUNCTION(0, 33), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "DSI4_TE"), + MTK_FUNCTION(2, "DP_OC_EN"), + MTK_FUNCTION(3, "SSPM_JTAG_TRSTN_VLP"), + MTK_FUNCTION(4, "ADSP_JTAG0_TRSTN"), + MTK_FUNCTION(5, "SCP_JTAG0_TRSTN_VLP"), + MTK_FUNCTION(6, "SPU0_NTRST"), + MTK_FUNCTION(7, "IO_JTAG_TRSTN") + ), + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(0, 34), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "UCTS5"), + MTK_FUNCTION(2, "DP_RAUX_SBU1"), + MTK_FUNCTION(3, "SSPM_JTAG_TDI_VLP"), + MTK_FUNCTION(4, "ADSP_JTAG0_TDI"), + MTK_FUNCTION(5, "SCP_JTAG0_TDI_VLP"), + MTK_FUNCTION(6, "SPU0_TDI"), + MTK_FUNCTION(7, "IO_JTAG_TDI") + ), + MTK_PIN( + 35, "GPIO35", + MTK_EINT_FUNCTION(0, 35), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "URTS5"), + MTK_FUNCTION(2, "DP_RAUX_SBU2"), + MTK_FUNCTION(3, "SSPM_JTAG_TDO_VLP"), + MTK_FUNCTION(4, "ADSP_JTAG0_TDO"), + MTK_FUNCTION(5, "SCP_JTAG0_TDO_VLP"), + MTK_FUNCTION(6, "SPU0_TDO"), + MTK_FUNCTION(7, "IO_JTAG_TDO") + ), + MTK_PIN( + 36, "GPIO36", + MTK_EINT_FUNCTION(0, 36), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "UTXD5"), + MTK_FUNCTION(3, "SSPM_JTAG_TMS_VLP"), + MTK_FUNCTION(4, "ADSP_JTAG0_TMS"), + MTK_FUNCTION(5, "SCP_JTAG0_TMS_VLP"), + MTK_FUNCTION(6, "SPU0_TMS"), + MTK_FUNCTION(7, "IO_JTAG_TMS") + ), + MTK_PIN( + 37, "GPIO37", + MTK_EINT_FUNCTION(0, 37), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "URXD5"), + MTK_FUNCTION(3, "MD_INT3"), + MTK_FUNCTION(4, "CLKM0_B"), + MTK_FUNCTION(5, "TP_GPIO5_AO"), + MTK_FUNCTION(6, "SPU0_UTX"), + MTK_FUNCTION(7, "DAP_MD32_SWCK") + ), + MTK_PIN( + 38, "GPIO38", + MTK_EINT_FUNCTION(0, 38), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(2, "SPMI_P_TRIG_FLAG"), + MTK_FUNCTION(3, "MD_INT4"), + MTK_FUNCTION(4, "CLKM1_B"), + MTK_FUNCTION(5, "TP_GPIO6_AO"), + MTK_FUNCTION(6, "SPU0_URX"), + MTK_FUNCTION(7, "DAP_MD32_SWD") + ), + MTK_PIN( + 39, "GPIO39", + MTK_EINT_FUNCTION(0, 39), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "I2S_MCK0"), + MTK_FUNCTION(3, "GPS_PPS0"), + MTK_FUNCTION(4, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(7, "DBG_MON_B12") + ), + MTK_PIN( + 40, "GPIO40", + MTK_EINT_FUNCTION(0, 40), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "I2SIN6_0_BCK"), + MTK_FUNCTION(3, "SPI4_B_CLK"), + MTK_FUNCTION(4, "UCTS2"), + MTK_FUNCTION(5, "CCU1_UTXD"), + MTK_FUNCTION(7, "DBG_MON_B13") + ), + MTK_PIN( + 41, "GPIO41", + MTK_EINT_FUNCTION(0, 41), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "I2SIN6_0_LRCK"), + MTK_FUNCTION(3, "SPI4_B_CSB"), + MTK_FUNCTION(4, "URTS2"), + MTK_FUNCTION(5, "CCU1_URXD"), + MTK_FUNCTION(7, "DBG_MON_B14") + ), + MTK_PIN( + 42, "GPIO42", + MTK_EINT_FUNCTION(0, 42), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "I2SIN6_0_DI"), + MTK_FUNCTION(3, "SPI4_B_MI"), + MTK_FUNCTION(4, "URXD2"), + MTK_FUNCTION(5, "CCU1_URTS"), + MTK_FUNCTION(6, "MD32_0_RXD"), + MTK_FUNCTION(7, "DBG_MON_B15") + ), + MTK_PIN( + 43, "GPIO43", + MTK_EINT_FUNCTION(0, 43), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "I2SOUT6_0_DO"), + MTK_FUNCTION(3, "SPI4_B_MO"), + MTK_FUNCTION(4, "UTXD2"), + MTK_FUNCTION(5, "CCU1_UCTS"), + MTK_FUNCTION(6, "MD32_0_TXD"), + MTK_FUNCTION(7, "DBG_MON_B16") + ), + MTK_PIN( + 44, "GPIO44", + MTK_EINT_FUNCTION(0, 44), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(3, "SPI3_A_CLK"), + MTK_FUNCTION(6, "TP_GPIO10_AO") + ), + MTK_PIN( + 45, "GPIO45", + MTK_EINT_FUNCTION(0, 45), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(2, "DSI2_HSYNC"), + MTK_FUNCTION(3, "SPI3_A_CSB"), + MTK_FUNCTION(4, "PWM_VLP"), + MTK_FUNCTION(6, "TP_GPIO11_AO") + ), + MTK_PIN( + 46, "GPIO46", + MTK_EINT_FUNCTION(0, 46), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "SCP_SCL4"), + MTK_FUNCTION(2, "PWM_VLP"), + MTK_FUNCTION(4, "SCP_ILDO_DTEST1_VLP"), + MTK_FUNCTION(5, "UFS_MPHY_SCL"), + MTK_FUNCTION(6, "TP_GPIO0_AO") + ), + MTK_PIN( + 47, "GPIO47", + MTK_EINT_FUNCTION(0, 47), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "SCP_SDA4"), + MTK_FUNCTION(4, "SCP_ILDO_DTEST2_VLP"), + MTK_FUNCTION(5, "UFS_MPHY_SDA"), + MTK_FUNCTION(6, "TP_GPIO1_AO") + ), + MTK_PIN( + 48, "GPIO48", + MTK_EINT_FUNCTION(0, 48), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "SCP_SCL5"), + MTK_FUNCTION(2, "PWM_VLP"), + MTK_FUNCTION(3, "CCU0_UTXD"), + MTK_FUNCTION(4, "SCP_ILDO_DTEST3_VLP"), + MTK_FUNCTION(6, "TP_GPIO2_AO") + ), + MTK_PIN( + 49, "GPIO49", + MTK_EINT_FUNCTION(0, 49), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "SCP_SDA5"), + MTK_FUNCTION(3, "CCU0_URXD"), + MTK_FUNCTION(4, "SCP_ILDO_DTEST4_VLP"), + MTK_FUNCTION(6, "TP_GPIO3_AO") + ), + MTK_PIN( + 50, "GPIO50", + MTK_EINT_FUNCTION(0, 50), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "SCP_SCL6"), + MTK_FUNCTION(2, "PWM_VLP"), + MTK_FUNCTION(3, "CCU0_URTS"), + MTK_FUNCTION(4, "DSI_HSYNC"), + MTK_FUNCTION(6, "TP_GPIO4_AO") + ), + MTK_PIN( + 51, "GPIO51", + MTK_EINT_FUNCTION(0, 51), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "SCP_SDA6"), + MTK_FUNCTION(3, "CCU0_UCTS"), + MTK_FUNCTION(4, "DSI1_HSYNC"), + MTK_FUNCTION(6, "TP_GPIO5_AO") + ), + MTK_PIN( + 52, "GPIO52", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "SCP_SCL1"), + MTK_FUNCTION(3, "TDM_DATA2") + ), + MTK_PIN( + 53, "GPIO53", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "SCP_SDA1"), + MTK_FUNCTION(3, "TDM_DATA3") + ), + MTK_PIN( + 54, "GPIO54", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "AUD_CLK_MOSI"), + MTK_FUNCTION(3, "TDM_MCK") + ), + MTK_PIN( + 55, "GPIO55", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "AUD_CLK_MISO"), + MTK_FUNCTION(2, "I2SOUT2_BCK"), + MTK_FUNCTION(3, "TDM_BCK") + ), + MTK_PIN( + 56, "GPIO56", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "AUD_DAT_MOSI0"), + MTK_FUNCTION(2, "I2SOUT2_LRCK"), + MTK_FUNCTION(3, "TDM_LRCK") + ), + MTK_PIN( + 57, "GPIO57", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "AUD_DAT_MOSI1"), + MTK_FUNCTION(2, "I2SOUT2_DO"), + MTK_FUNCTION(3, "TDM_DATA0") + ), + MTK_PIN( + 58, "GPIO58", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "AUD_DAT_MISO0"), + MTK_FUNCTION(3, "TDM_DATA1") + ), + MTK_PIN( + 59, "GPIO59", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "AUD_DAT_MISO1"), + MTK_FUNCTION(3, "I2SIN1_BCK") + ), + MTK_PIN( + 60, "GPIO60", + MTK_EINT_FUNCTION(0, 60), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "KPCOL0"), + MTK_FUNCTION(6, "TP_GPIO13_AO") + ), + MTK_PIN( + 61, "GPIO61", + MTK_EINT_FUNCTION(0, 61), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "MCU_M_PMIC_POC_I") + ), + MTK_PIN( + 62, "GPIO62", + MTK_EINT_FUNCTION(0, 62), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "MCU_B_PMIC_POC_I") + ), + MTK_PIN( + 63, "GPIO63", + MTK_EINT_FUNCTION(0, 63), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "MFG_PMIC_POC_I") + ), + MTK_PIN( + 64, "GPIO64", + MTK_EINT_FUNCTION(0, 64), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "PRE_UVLO") + ), + MTK_PIN( + 65, "GPIO65", + MTK_EINT_FUNCTION(0, 65), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "DPM2PMIC"), + MTK_FUNCTION(2, "SRCLKENA1") + ), + MTK_PIN( + 66, "GPIO66", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "WATCHDOG") + ), + MTK_PIN( + 67, "GPIO67", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "SRCLKENA0") + ), + MTK_PIN( + 68, "GPIO68", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "SCP_VREQ_VAO") + ), + MTK_PIN( + 69, "GPIO69", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + MTK_PIN( + 70, "GPIO70", + MTK_EINT_FUNCTION(0, 70), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "CMFLASH0") + ), + MTK_PIN( + 71, "GPIO71", + MTK_EINT_FUNCTION(0, 71), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO71") + ), + MTK_PIN( + 72, "GPIO72", + MTK_EINT_FUNCTION(0, 72), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO72") + ), + MTK_PIN( + 73, "GPIO73", + MTK_EINT_FUNCTION(0, 73), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO73") + ), + MTK_PIN( + 74, "GPIO74", + MTK_EINT_FUNCTION(0, 74), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "DCXO_FPM_LPM") + ), + MTK_PIN( + 75, "GPIO75", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "SPMI_M_SCL") + ), + MTK_PIN( + 76, "GPIO76", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "SPMI_M_SDA") + ), + MTK_PIN( + 77, "GPIO77", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "SPMI_P_SCL") + ), + MTK_PIN( + 78, "GPIO78", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "SPMI_P_SDA") + ), + MTK_PIN( + 79, "GPIO79", + MTK_EINT_FUNCTION(0, 79), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "CMMCLK0"), + MTK_FUNCTION(2, "MD_INT4") + ), + MTK_PIN( + 80, "GPIO80", + MTK_EINT_FUNCTION(0, 80), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "CMMCLK1") + ), + MTK_PIN( + 81, "GPIO81", + MTK_EINT_FUNCTION(0, 81), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "SCP_SPI0_CK"), + MTK_FUNCTION(2, "SPI6_B_CLK"), + MTK_FUNCTION(3, "PWM_VLP"), + MTK_FUNCTION(4, "I2SOUT5_BCK"), + MTK_FUNCTION(6, "TP_GPIO0_AO") + ), + MTK_PIN( + 82, "GPIO82", + MTK_EINT_FUNCTION(0, 82), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "SCP_SPI0_CS"), + MTK_FUNCTION(2, "SPI6_B_CSB"), + MTK_FUNCTION(4, "I2SOUT5_LRCK"), + MTK_FUNCTION(6, "TP_GPIO1_AO") + ), + MTK_PIN( + 83, "GPIO83", + MTK_EINT_FUNCTION(0, 83), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "SCP_SPI0_MO"), + MTK_FUNCTION(2, "SPI6_B_MO"), + MTK_FUNCTION(4, "I2SOUT5_DATA0"), + MTK_FUNCTION(6, "TP_GPIO2_AO") + ), + MTK_PIN( + 84, "GPIO84", + MTK_EINT_FUNCTION(0, 84), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "SCP_SPI0_MI"), + MTK_FUNCTION(2, "SPI6_B_MI"), + MTK_FUNCTION(4, "I2SOUT5_DATA1"), + MTK_FUNCTION(6, "TP_GPIO3_AO") + ), + MTK_PIN( + 85, "GPIO85", + MTK_EINT_FUNCTION(0, 85), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "SCP_SPI1_CK"), + MTK_FUNCTION(2, "SPI7_B_CLK"), + MTK_FUNCTION(4, "I2SIN5_DATA0"), + MTK_FUNCTION(5, "PWM_VLP"), + MTK_FUNCTION(6, "TP_GPIO4_AO") + ), + MTK_PIN( + 86, "GPIO86", + MTK_EINT_FUNCTION(0, 86), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "SCP_SPI1_CS"), + MTK_FUNCTION(2, "SPI7_B_CSB"), + MTK_FUNCTION(4, "I2SIN5_DATA1"), + MTK_FUNCTION(6, "TP_GPIO5_AO") + ), + MTK_PIN( + 87, "GPIO87", + MTK_EINT_FUNCTION(0, 87), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "SCP_SPI1_MO"), + MTK_FUNCTION(2, "SPI7_B_MO"), + MTK_FUNCTION(4, "I2SIN5_BCK"), + MTK_FUNCTION(6, "TP_GPIO6_AO") + ), + MTK_PIN( + 88, "GPIO88", + MTK_EINT_FUNCTION(0, 88), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "SCP_SPI1_MI"), + MTK_FUNCTION(2, "SPI7_B_MI"), + MTK_FUNCTION(4, "I2SIN5_LRCK"), + MTK_FUNCTION(6, "TP_GPIO7_AO") + ), + MTK_PIN( + 89, "GPIO89", + MTK_EINT_FUNCTION(0, 89), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "DSI_TE"), + MTK_FUNCTION(2, "DSI1_TE"), + MTK_FUNCTION(7, "DBG_MON_B30") + ), + MTK_PIN( + 90, "GPIO90", + MTK_EINT_FUNCTION(0, 90), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "LCM_RST"), + MTK_FUNCTION(2, "LCM1_RST"), + MTK_FUNCTION(7, "DBG_MON_B31") + ), + MTK_PIN( + 91, "GPIO91", + MTK_EINT_FUNCTION(0, 91), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "CMFLASH2"), + MTK_FUNCTION(2, "SF_D0"), + MTK_FUNCTION(3, "SRCLKENAI1"), + MTK_FUNCTION(5, "KPCOL2"), + MTK_FUNCTION(6, "TP_GPIO11_AO") + ), + MTK_PIN( + 92, "GPIO92", + MTK_EINT_FUNCTION(0, 92), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "CMFLASH3"), + MTK_FUNCTION(2, "SF_D1"), + MTK_FUNCTION(4, "DISP_PWM1"), + MTK_FUNCTION(6, "TP_GPIO12_AO") + ), + MTK_PIN( + 93, "GPIO93", + MTK_EINT_FUNCTION(0, 93), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "CMFLASH1"), + MTK_FUNCTION(2, "SF_D2"), + MTK_FUNCTION(3, "SRCLKENAI0"), + MTK_FUNCTION(5, "KPROW2"), + MTK_FUNCTION(6, "TP_GPIO13_AO") + ), + MTK_PIN( + 94, "GPIO94", + MTK_EINT_FUNCTION(0, 94), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "I2S_MCK1"), + MTK_FUNCTION(2, "SF_D3"), + MTK_FUNCTION(4, "MD32_0_GPIO0"), + MTK_FUNCTION(5, "CLKM0_A"), + MTK_FUNCTION(6, "TP_GPIO14_AO"), + MTK_FUNCTION(7, "DBG_MON_B18") + ), + MTK_PIN( + 95, "GPIO95", + MTK_EINT_FUNCTION(0, 95), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "I2SIN1_BCK"), + MTK_FUNCTION(2, "I2SIN4_BCK"), + MTK_FUNCTION(3, "SPI6_A_CLK"), + MTK_FUNCTION(4, "MD32_1_GPIO0"), + MTK_FUNCTION(5, "CLKM1_A"), + MTK_FUNCTION(6, "TP_GPIO15_AO"), + MTK_FUNCTION(7, "DBG_MON_B19") + ), + MTK_PIN( + 96, "GPIO96", + MTK_EINT_FUNCTION(0, 96), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "I2SIN1_LRCK"), + MTK_FUNCTION(2, "I2SIN4_LRCK"), + MTK_FUNCTION(3, "SPI6_A_CSB"), + MTK_FUNCTION(4, "MD32_2_GPIO0"), + MTK_FUNCTION(5, "CLKM2_A"), + MTK_FUNCTION(7, "DBG_MON_B20") + ), + MTK_PIN( + 97, "GPIO97", + MTK_EINT_FUNCTION(0, 97), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "I2SIN1_DI_A"), + MTK_FUNCTION(2, "I2SIN4_DATA0"), + MTK_FUNCTION(3, "SPI6_A_MO"), + MTK_FUNCTION(4, "MD32_3_GPIO0"), + MTK_FUNCTION(5, "CLKM3_A"), + MTK_FUNCTION(7, "DBG_MON_B21") + ), + MTK_PIN( + 98, "GPIO98", + MTK_EINT_FUNCTION(0, 98), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "I2SOUT1_DO"), + MTK_FUNCTION(2, "I2SOUT4_DATA0"), + MTK_FUNCTION(3, "SPI6_A_MI"), + MTK_FUNCTION(7, "DBG_MON_B22") + ), + MTK_PIN( + 99, "GPIO99", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "SCL0"), + MTK_FUNCTION(2, "LCM2_RST"), + MTK_FUNCTION(3, "AUD_DAC_26M_CLK"), + MTK_FUNCTION(4, "SPU0_SCL"), + MTK_FUNCTION(7, "DBG_MON_B24") + ), + MTK_PIN( + 100, "GPIO100", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "SDA0"), + MTK_FUNCTION(2, "DSI2_TE"), + MTK_FUNCTION(4, "SPU0_SDA"), + MTK_FUNCTION(7, "DBG_MON_B25") + ), + MTK_PIN( + 101, "GPIO101", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "SCL10"), + MTK_FUNCTION(2, "SF_CS"), + MTK_FUNCTION(3, "SCP_DMIC1_CLK"), + MTK_FUNCTION(4, "I2SIN5_DATA2"), + MTK_FUNCTION(5, "SCP_SCL_OIS"), + MTK_FUNCTION(6, "TP_GPIO10_AO"), + MTK_FUNCTION(7, "DBG_MON_B28") + ), + MTK_PIN( + 102, "GPIO102", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "SDA10"), + MTK_FUNCTION(2, "SF_CK"), + MTK_FUNCTION(3, "SCP_DMIC1_DAT"), + MTK_FUNCTION(4, "I2SIN5_DATA3"), + MTK_FUNCTION(5, "SCP_SDA_OIS"), + MTK_FUNCTION(6, "TP_GPIO11_AO"), + MTK_FUNCTION(7, "DBG_MON_B29") + ), + MTK_PIN( + 103, "GPIO103", + MTK_EINT_FUNCTION(0, 103), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(2, "DSI1_TE"), + MTK_FUNCTION(5, "I2S_MCK0"), + MTK_FUNCTION(7, "DBG_MON_B23") + ), + MTK_PIN( + 104, "GPIO104", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "SCL6"), + MTK_FUNCTION(2, "SPU1_SCL"), + MTK_FUNCTION(3, "AUD_DAC_26M_CLK"), + MTK_FUNCTION(4, "USB_DRVVBUS_2P"), + MTK_FUNCTION(5, "I2S_MCK1"), + MTK_FUNCTION(6, "IDDIG_2P"), + MTK_FUNCTION(7, "DBG_MON_B26") + ), + MTK_PIN( + 105, "GPIO105", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "SDA6"), + MTK_FUNCTION(2, "SPU1_SDA"), + MTK_FUNCTION(3, "DISP_PWM2"), + MTK_FUNCTION(4, "VBUSVALID_2P"), + MTK_FUNCTION(5, "I2S_MCK2"), + MTK_FUNCTION(6, "VBUSVALID_3P"), + MTK_FUNCTION(7, "DBG_MON_B27") + ), + MTK_PIN( + 106, "GPIO106", + MTK_EINT_FUNCTION(0, 106), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "SCP_SPI3_CK"), + MTK_FUNCTION(2, "SPI3_B_CLK"), + MTK_FUNCTION(3, "MD_UTXD0"), + MTK_FUNCTION(4, "TP_UTXD1_VLP"), + MTK_FUNCTION(5, "CONN_BG_GPS_MCU_UART0_TXD"), + MTK_FUNCTION(6, "TP_GPIO6_AO"), + MTK_FUNCTION(7, "DBG_MON_B0") + ), + MTK_PIN( + 107, "GPIO107", + MTK_EINT_FUNCTION(0, 107), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "SCP_SPI3_CS"), + MTK_FUNCTION(2, "SPI3_B_CSB"), + MTK_FUNCTION(3, "MD_URXD0"), + MTK_FUNCTION(4, "TP_URXD1_VLP"), + MTK_FUNCTION(5, "CONN_BG_GPS_MCU_UART0_RXD"), + MTK_FUNCTION(6, "TP_GPIO7_AO"), + MTK_FUNCTION(7, "DBG_MON_B1") + ), + MTK_PIN( + 108, "GPIO108", + MTK_EINT_FUNCTION(0, 108), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "SCP_SPI3_MO"), + MTK_FUNCTION(2, "SPI3_B_MO"), + MTK_FUNCTION(3, "MD_UTXD1"), + MTK_FUNCTION(4, "MD32PCM_UTXD_AO_VLP"), + MTK_FUNCTION(5, "CONN_BG_GPS_MCU_UART1_TXD"), + MTK_FUNCTION(6, "TP_GPIO8_AO"), + MTK_FUNCTION(7, "DBG_MON_B2") + ), + MTK_PIN( + 109, "GPIO109", + MTK_EINT_FUNCTION(0, 109), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "SCP_SPI3_MI"), + MTK_FUNCTION(2, "SPI3_B_MI"), + MTK_FUNCTION(3, "MD_URXD1"), + MTK_FUNCTION(4, "MD32PCM_URXD_AO_VLP"), + MTK_FUNCTION(5, "CONN_BG_GPS_MCU_UART1_RXD"), + MTK_FUNCTION(6, "TP_GPIO9_AO"), + MTK_FUNCTION(7, "DBG_MON_B3") + ), + MTK_PIN( + 110, "GPIO110", + MTK_EINT_FUNCTION(0, 110), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "SPI1_CLK"), + MTK_FUNCTION(2, "PWM_0"), + MTK_FUNCTION(3, "MD_UCTS0"), + MTK_FUNCTION(4, "TP_UCTS1_VLP"), + MTK_FUNCTION(6, "SPU0_GPIO_O"), + MTK_FUNCTION(7, "DBG_MON_B4") + ), + MTK_PIN( + 111, "GPIO111", + MTK_EINT_FUNCTION(0, 111), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "SPI1_CSB"), + MTK_FUNCTION(2, "PWM_1"), + MTK_FUNCTION(3, "MD_URTS0"), + MTK_FUNCTION(4, "TP_URTS1_VLP"), + MTK_FUNCTION(6, "SPU0_GPIO_I"), + MTK_FUNCTION(7, "DBG_MON_B5") + ), + MTK_PIN( + 112, "GPIO112", + MTK_EINT_FUNCTION(0, 112), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "SPI1_MO"), + MTK_FUNCTION(2, "PWM_2"), + MTK_FUNCTION(3, "MD_UCTS1"), + MTK_FUNCTION(6, "SPU1_GPIO_O"), + MTK_FUNCTION(7, "DBG_MON_B6") + ), + MTK_PIN( + 113, "GPIO113", + MTK_EINT_FUNCTION(0, 113), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "SPI1_MI"), + MTK_FUNCTION(2, "PWM_3"), + MTK_FUNCTION(3, "MD_URTS1"), + MTK_FUNCTION(6, "SPU1_GPIO_I"), + MTK_FUNCTION(7, "DBG_MON_B7") + ), + MTK_PIN( + 114, "GPIO114", + MTK_EINT_FUNCTION(0, 114), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "SPI0_SPU_CLK"), + MTK_FUNCTION(2, "SPI4_A_CLK"), + MTK_FUNCTION(5, "CONN_BG_GPS_MCU_DBG_UART_TX"), + MTK_FUNCTION(7, "DBG_MON_B8") + ), + MTK_PIN( + 115, "GPIO115", + MTK_EINT_FUNCTION(0, 115), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "SPI0_SPU_CSB"), + MTK_FUNCTION(2, "SPI4_A_CSB"), + MTK_FUNCTION(7, "DBG_MON_B9") + ), + MTK_PIN( + 116, "GPIO116", + MTK_EINT_FUNCTION(0, 116), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "SPI0_SPU_MO"), + MTK_FUNCTION(2, "SPI4_A_MO"), + MTK_FUNCTION(3, "LCM1_RST"), + MTK_FUNCTION(7, "DBG_MON_B10") + ), + MTK_PIN( + 117, "GPIO117", + MTK_EINT_FUNCTION(0, 117), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "SPI0_SPU_MI"), + MTK_FUNCTION(2, "SPI4_A_MI"), + MTK_FUNCTION(3, "DSI1_TE"), + MTK_FUNCTION(7, "DBG_MON_B11") + ), + MTK_PIN( + 118, "GPIO118", + MTK_EINT_FUNCTION(0, 118), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "SPI5_CLK"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(3, "DP_TX_HPD"), + MTK_FUNCTION(4, "AD_ILDO_DTEST0") + ), + MTK_PIN( + 119, "GPIO119", + MTK_EINT_FUNCTION(0, 119), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "SPI5_CSB"), + MTK_FUNCTION(2, "VBUSVALID"), + MTK_FUNCTION(3, "DP_OC_EN"), + MTK_FUNCTION(4, "AD_ILDO_DTEST1") + ), + MTK_PIN( + 120, "GPIO120", + MTK_EINT_FUNCTION(0, 120), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "SPI5_MO"), + MTK_FUNCTION(2, "LCM2_RST"), + MTK_FUNCTION(3, "DP_RAUX_SBU1"), + MTK_FUNCTION(4, "AD_ILDO_DTEST2"), + MTK_FUNCTION(6, "IDDIG_3P") + ), + MTK_PIN( + 121, "GPIO121", + MTK_EINT_FUNCTION(0, 121), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "SPI5_MI"), + MTK_FUNCTION(2, "DSI2_TE"), + MTK_FUNCTION(3, "DP_RAUX_SBU2"), + MTK_FUNCTION(4, "AD_ILDO_DTEST3"), + MTK_FUNCTION(6, "USB_DRVVBUS_3P"), + MTK_FUNCTION(7, "DBG_MON_B17") + ), + MTK_PIN( + 122, "GPIO122", + MTK_EINT_FUNCTION(0, 122), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "AP_GOOD"), + MTK_FUNCTION(2, "CONN_TCXOENA_REQ") + ), + MTK_PIN( + 123, "GPIO123", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "SCL3"), + MTK_FUNCTION(5, "I2SIN2_LRCK"), + MTK_FUNCTION(6, "TP_UTXD_MD_VCORE") + ), + MTK_PIN( + 124, "GPIO124", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "SDA3"), + MTK_FUNCTION(6, "TP_URXD_MD_VCORE") + ), + MTK_PIN( + 125, "GPIO125", + MTK_EINT_FUNCTION(0, 125), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "MD1_SIM2_SCLK"), + MTK_FUNCTION(3, "HFRP_JTAG0_TCK"), + MTK_FUNCTION(4, "UDI_TCK"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L1_JCK"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TCK_VLP"), + MTK_FUNCTION(7, "JTCK2_SEL1") + ), + MTK_PIN( + 126, "GPIO126", + MTK_EINT_FUNCTION(0, 126), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(3, "HFRP_JTAG0_TMS"), + MTK_FUNCTION(4, "UDI_TMS"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L1_JMS"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TMS_VLP"), + MTK_FUNCTION(7, "JTMS2_SEL1") + ), + MTK_PIN( + 127, "GPIO127", + MTK_EINT_FUNCTION(0, 127), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "MD1_SIM2_SRST"), + MTK_FUNCTION(3, "HFRP_JTAG0_TDI"), + MTK_FUNCTION(4, "UDI_TDI_0"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L1_JDI"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TDI_VLP"), + MTK_FUNCTION(7, "JTDI2_SEL1") + ), + MTK_PIN( + 128, "GPIO128", + MTK_EINT_FUNCTION(0, 128), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "MD1_SIM2_SIO"), + MTK_FUNCTION(3, "HFRP_JTAG0_TDO"), + MTK_FUNCTION(4, "UDI_TDO_0"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L1_JDO"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TDO_VLP"), + MTK_FUNCTION(7, "JTDO2_SEL1") + ), + MTK_PIN( + 129, "GPIO129", + MTK_EINT_FUNCTION(0, 129), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "DSI2_HSYNC"), + MTK_FUNCTION(3, "HFRP_JTAG0_TRSTN"), + MTK_FUNCTION(4, "UDI_NTRST"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TRSTN_VLP"), + MTK_FUNCTION(7, "JTRSTN2_SEL1") + ), + MTK_PIN( + 130, "GPIO130", + MTK_EINT_FUNCTION(0, 130), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(2, "DSI3_HSYNC"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L1_JINTP") + ), + MTK_PIN( + 131, "GPIO131", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "MD1_SIM2_SCLK"), + MTK_FUNCTION(2, "MD1_SIM1_SCLK"), + MTK_FUNCTION(3, "MCUPM_JTAG_TDI"), + MTK_FUNCTION(4, "CLKM0_A"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L5_JDI"), + MTK_FUNCTION(6, "TSFDC_SCK"), + MTK_FUNCTION(7, "SCP_JTAG0_TDI_VCORE") + ), + MTK_PIN( + 132, "GPIO132", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "MD1_SIM2_SRST"), + MTK_FUNCTION(2, "MD1_SIM1_SRST"), + MTK_FUNCTION(3, "MCUPM_JTAG_TMS"), + MTK_FUNCTION(4, "CLKM1_B"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L5_JMS"), + MTK_FUNCTION(6, "TSFDC_SDI"), + MTK_FUNCTION(7, "SCP_JTAG0_TMS_VCORE") + ), + MTK_PIN( + 133, "GPIO133", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "MD1_SIM2_SIO"), + MTK_FUNCTION(2, "MD1_SIM1_SIO"), + MTK_FUNCTION(3, "MCUPM_JTAG_TDO"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L5_JDO"), + MTK_FUNCTION(6, "TSFDC_SCF"), + MTK_FUNCTION(7, "SCP_JTAG0_TDO_VCORE") + ), + MTK_PIN( + 134, "GPIO134", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "MD1_SIM1_SCLK"), + MTK_FUNCTION(2, "MD1_SIM2_SCLK"), + MTK_FUNCTION(6, "TSFDC_26M") + ), + MTK_PIN( + 135, "GPIO135", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "MD1_SIM1_SRST"), + MTK_FUNCTION(2, "MD1_SIM2_SRST"), + MTK_FUNCTION(3, "MCUPM_JTAG_TCK"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L5_JCK"), + MTK_FUNCTION(6, "TSFDC_SDO"), + MTK_FUNCTION(7, "SCP_JTAG0_TCK_VCORE") + ), + MTK_PIN( + 136, "GPIO136", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "MD1_SIM1_SIO"), + MTK_FUNCTION(2, "MD1_SIM2_SIO"), + MTK_FUNCTION(3, "MCUPM_JTAG_TRSTN"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L5_JINTP"), + MTK_FUNCTION(6, "TSFDC_FOUT"), + MTK_FUNCTION(7, "SCP_JTAG0_TRSTN_VCORE") + ), + MTK_PIN( + 137, "GPIO137", + MTK_EINT_FUNCTION(0, 137), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "MIPI0_D_SCLK"), + MTK_FUNCTION(2, "BPI_BUS16"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(6, "SPM_JTAG_TRSTN_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A0") + ), + MTK_PIN( + 138, "GPIO138", + MTK_EINT_FUNCTION(0, 138), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "MIPI0_D_SDATA"), + MTK_FUNCTION(2, "BPI_BUS17"), + MTK_FUNCTION(4, "PCM0_LRCK"), + MTK_FUNCTION(6, "SPM_JTAG_TCK_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A1") + ), + MTK_PIN( + 139, "GPIO139", + MTK_EINT_FUNCTION(0, 139), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "MIPI1_D_SCLK"), + MTK_FUNCTION(2, "BPI_BUS18"), + MTK_FUNCTION(4, "MD_GPS_BLANK"), + MTK_FUNCTION(6, "SPM_JTAG_TMS_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A2") + ), + MTK_PIN( + 140, "GPIO140", + MTK_EINT_FUNCTION(0, 140), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "MIPI1_D_SDATA"), + MTK_FUNCTION(2, "BPI_BUS19"), + MTK_FUNCTION(4, "MD_URXD1_CONN"), + MTK_FUNCTION(6, "SPM_JTAG_TDO_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A3") + ), + MTK_PIN( + 141, "GPIO141", + MTK_EINT_FUNCTION(0, 141), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "MIPI2_D_SCLK"), + MTK_FUNCTION(2, "BPI_BUS20"), + MTK_FUNCTION(4, "MD_UTXD1_CONN"), + MTK_FUNCTION(6, "SPM_JTAG_TDI_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A4") + ), + MTK_PIN( + 142, "GPIO142", + MTK_EINT_FUNCTION(0, 142), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "MIPI2_D_SDATA"), + MTK_FUNCTION(2, "BPI_BUS21"), + MTK_FUNCTION(6, "SSPM_JTAG_TRSTN_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A5") + ), + MTK_PIN( + 143, "GPIO143", + MTK_EINT_FUNCTION(0, 143), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "MIPI3_D_SCLK"), + MTK_FUNCTION(2, "BPI_BUS22"), + MTK_FUNCTION(4, "TP_UTXD_GNSS_VLP"), + MTK_FUNCTION(5, "MD_UTXD1_CONN"), + MTK_FUNCTION(6, "SSPM_JTAG_TCK_VCORE") + ), + MTK_PIN( + 144, "GPIO144", + MTK_EINT_FUNCTION(0, 144), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "MIPI3_D_SDATA"), + MTK_FUNCTION(2, "BPI_BUS23"), + MTK_FUNCTION(4, "TP_URXD_GNSS_VLP"), + MTK_FUNCTION(5, "MD_URXD1_CONN"), + MTK_FUNCTION(6, "SSPM_JTAG_TMS_VCORE") + ), + MTK_PIN( + 145, "GPIO145", + MTK_EINT_FUNCTION(0, 145), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "BPI_BUS0"), + MTK_FUNCTION(4, "PCIE_WAKEN_1P"), + MTK_FUNCTION(6, "SSPM_JTAG_TDO_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A10") + ), + MTK_PIN( + 146, "GPIO146", + MTK_EINT_FUNCTION(0, 146), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "BPI_BUS1"), + MTK_FUNCTION(4, "PCIE_PERSTN_1P"), + MTK_FUNCTION(6, "SSPM_JTAG_TDI_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A11") + ), + MTK_PIN( + 147, "GPIO147", + MTK_EINT_FUNCTION(0, 147), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "BPI_BUS2"), + MTK_FUNCTION(2, "AUD_DAC_26M_CLK"), + MTK_FUNCTION(4, "PCIE_CLKREQN_1P"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TRSTN_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A12") + ), + MTK_PIN( + 148, "GPIO148", + MTK_EINT_FUNCTION(0, 148), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "BPI_BUS3"), + MTK_FUNCTION(2, "AUD_DAC_26M_CLK"), + MTK_FUNCTION(4, "TP_UTXD_MD_VLP"), + MTK_FUNCTION(5, "TP_GPIO0_AO"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TCK_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A13") + ), + MTK_PIN( + 149, "GPIO149", + MTK_EINT_FUNCTION(0, 149), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(1, "BPI_BUS4"), + MTK_FUNCTION(2, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "TP_URXD_MD_VLP"), + MTK_FUNCTION(5, "TP_GPIO1_AO"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TMS_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A14") + ), + MTK_PIN( + 150, "GPIO150", + MTK_EINT_FUNCTION(0, 150), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(1, "BPI_BUS5"), + MTK_FUNCTION(2, "GPS_PPS0"), + MTK_FUNCTION(5, "TP_GPIO2_AO"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TDO_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A15") + ), + MTK_PIN( + 151, "GPIO151", + MTK_EINT_FUNCTION(0, 151), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(1, "BPI_BUS6"), + MTK_FUNCTION(2, "GPS_PPS1"), + MTK_FUNCTION(5, "TP_GPIO3_AO"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TDI_VCORE") + ), + MTK_PIN( + 152, "GPIO152", + MTK_EINT_FUNCTION(0, 152), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(1, "BPI_BUS7"), + MTK_FUNCTION(2, "EDP_TX_HPD"), + MTK_FUNCTION(5, "AGPS_SYNC"), + MTK_FUNCTION(6, "SSPM_UTXD_AO_VCORE") + ), + MTK_PIN( + 153, "GPIO153", + MTK_EINT_FUNCTION(0, 153), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(1, "MD_UCNT_A_TGL"), + MTK_FUNCTION(6, "TP_URTS1_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A8") + ), + MTK_PIN( + 154, "GPIO154", + MTK_EINT_FUNCTION(0, 154), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO154"), + MTK_FUNCTION(1, "DIGRF_IRQ"), + MTK_FUNCTION(6, "TP_UCTS1_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A9") + ), + MTK_PIN( + 155, "GPIO155", + MTK_EINT_FUNCTION(0, 155), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO155"), + MTK_FUNCTION(1, "MIPI_M_SCLK"), + MTK_FUNCTION(4, "UCTS2"), + MTK_FUNCTION(6, "TP_UTXD_CONSYS_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A6") + ), + MTK_PIN( + 156, "GPIO156", + MTK_EINT_FUNCTION(0, 156), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO156"), + MTK_FUNCTION(1, "MIPI_M_SDATA"), + MTK_FUNCTION(4, "URTS2"), + MTK_FUNCTION(6, "TP_URXD_CONSYS_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A7") + ), + MTK_PIN( + 157, "GPIO157", + MTK_EINT_FUNCTION(0, 157), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO157"), + MTK_FUNCTION(1, "BPI_BUS8"), + MTK_FUNCTION(4, "UTXD2"), + MTK_FUNCTION(5, "CLKM0_A"), + MTK_FUNCTION(6, "SSPM_URXD_AO_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A16") + ), + MTK_PIN( + 158, "GPIO158", + MTK_EINT_FUNCTION(0, 158), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO158"), + MTK_FUNCTION(1, "BPI_BUS9"), + MTK_FUNCTION(4, "URXD2"), + MTK_FUNCTION(5, "CLKM1_A"), + MTK_FUNCTION(6, "TP_UTXD1_VCORE") + ), + MTK_PIN( + 159, "GPIO159", + MTK_EINT_FUNCTION(0, 159), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO159"), + MTK_FUNCTION(1, "BPI_BUS10"), + MTK_FUNCTION(2, "MD_INT0"), + MTK_FUNCTION(3, "SRCLKENAI1"), + MTK_FUNCTION(5, "CLKM2_A"), + MTK_FUNCTION(6, "TP_URXD1_VCORE") + ), + MTK_PIN( + 160, "GPIO160", + MTK_EINT_FUNCTION(0, 160), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO160"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "MD_UTXD1"), + MTK_FUNCTION(5, "MBISTREADEN_TRIGGER"), + MTK_FUNCTION(6, "CONN_BG_GPS_MCU_DBG_UART_TX") + ), + MTK_PIN( + 161, "GPIO161", + MTK_EINT_FUNCTION(0, 161), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO161"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "MD_URXD1"), + MTK_FUNCTION(5, "MBISTWRITEEN_TRIGGER") + ), + MTK_PIN( + 162, "GPIO162", + MTK_EINT_FUNCTION(0, 162), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO162"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "MD_UTXD0"), + MTK_FUNCTION(3, "TP_UTXD1_VLP"), + MTK_FUNCTION(4, "ADSP_UTXD0"), + MTK_FUNCTION(5, "SSPM_UTXD_AO_VLP"), + MTK_FUNCTION(6, "HFRP_UTXD1") + ), + MTK_PIN( + 163, "GPIO163", + MTK_EINT_FUNCTION(0, 163), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO163"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "MD_URXD0"), + MTK_FUNCTION(3, "TP_URXD1_VLP"), + MTK_FUNCTION(4, "ADSP_URXD0"), + MTK_FUNCTION(5, "SSPM_URXD_AO_VLP"), + MTK_FUNCTION(6, "HFRP_URXD1") + ), + MTK_PIN( + 164, "GPIO164", + MTK_EINT_FUNCTION(0, 164), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO164"), + MTK_FUNCTION(1, "SCP_SCL0"), + MTK_FUNCTION(6, "TP_GPIO0_AO"), + MTK_FUNCTION(7, "DBG_MON_A22") + ), + MTK_PIN( + 165, "GPIO165", + MTK_EINT_FUNCTION(0, 165), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO165"), + MTK_FUNCTION(1, "SCP_SDA0"), + MTK_FUNCTION(6, "TP_GPIO1_AO"), + MTK_FUNCTION(7, "DBG_MON_A23") + ), + MTK_PIN( + 166, "GPIO166", + MTK_EINT_FUNCTION(0, 166), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO166"), + MTK_FUNCTION(1, "SCP_SCL2"), + MTK_FUNCTION(6, "TP_GPIO2_AO"), + MTK_FUNCTION(7, "DBG_MON_A24") + ), + MTK_PIN( + 167, "GPIO167", + MTK_EINT_FUNCTION(0, 167), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO167"), + MTK_FUNCTION(1, "SCP_SDA2"), + MTK_FUNCTION(6, "TP_GPIO3_AO"), + MTK_FUNCTION(7, "DBG_MON_A25") + ), + MTK_PIN( + 168, "GPIO168", + MTK_EINT_FUNCTION(0, 168), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO168"), + MTK_FUNCTION(1, "SCP_SPI2_CK"), + MTK_FUNCTION(2, "SPI2_B_CLK"), + MTK_FUNCTION(3, "PWM_VLP"), + MTK_FUNCTION(4, "SCP_SCL2"), + MTK_FUNCTION(7, "DBG_MON_A26") + ), + MTK_PIN( + 169, "GPIO169", + MTK_EINT_FUNCTION(0, 169), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO169"), + MTK_FUNCTION(1, "SCP_SPI2_CS"), + MTK_FUNCTION(2, "SPI2_B_CSB"), + MTK_FUNCTION(7, "DBG_MON_A27") + ), + MTK_PIN( + 170, "GPIO170", + MTK_EINT_FUNCTION(0, 170), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO170"), + MTK_FUNCTION(1, "SCP_SPI2_MO"), + MTK_FUNCTION(2, "SPI2_B_MO"), + MTK_FUNCTION(4, "SCP_SDA2"), + MTK_FUNCTION(7, "DBG_MON_A28") + ), + MTK_PIN( + 171, "GPIO171", + MTK_EINT_FUNCTION(0, 171), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO171"), + MTK_FUNCTION(1, "SCP_SPI2_MI"), + MTK_FUNCTION(2, "SPI2_B_MI"), + MTK_FUNCTION(7, "DBG_MON_A29") + ), + MTK_PIN( + 172, "GPIO172", + MTK_EINT_FUNCTION(0, 172), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO172"), + MTK_FUNCTION(1, "CONN_TCXOENA_REQ") + ), + MTK_PIN( + 173, "GPIO173", + MTK_EINT_FUNCTION(0, 173), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO173"), + MTK_FUNCTION(1, "CMFLASH3"), + MTK_FUNCTION(2, "PWM_3"), + MTK_FUNCTION(3, "MD_GPS_L5_BLANK"), + MTK_FUNCTION(4, "CLKM1_A"), + MTK_FUNCTION(7, "DBG_MON_A31") + ), + MTK_PIN( + 174, "GPIO174", + MTK_EINT_FUNCTION(0, 174), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO174"), + MTK_FUNCTION(1, "CMFLASH0"), + MTK_FUNCTION(2, "PWM_0"), + MTK_FUNCTION(3, "VBUSVALID_1P"), + MTK_FUNCTION(4, "MD32_2_RXD"), + MTK_FUNCTION(5, "DISP_PWM3") + ), + MTK_PIN( + 175, "GPIO175", + MTK_EINT_FUNCTION(0, 175), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO175"), + MTK_FUNCTION(1, "CMFLASH1"), + MTK_FUNCTION(2, "PWM_1"), + MTK_FUNCTION(3, "EDP_TX_HPD"), + MTK_FUNCTION(4, "MD32_2_TXD"), + MTK_FUNCTION(5, "DISP_PWM4") + ), + MTK_PIN( + 176, "GPIO176", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO176"), + MTK_FUNCTION(1, "SCL5"), + MTK_FUNCTION(2, "LCM3_RST"), + MTK_FUNCTION(4, "MD_URXD1_CONN"), + MTK_FUNCTION(6, "TP_UTXD_GNSS_VCORE") + ), + MTK_PIN( + 177, "GPIO177", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO177"), + MTK_FUNCTION(1, "SDA5"), + MTK_FUNCTION(2, "DSI3_TE"), + MTK_FUNCTION(4, "MD_UTXD1_CONN"), + MTK_FUNCTION(6, "TP_URXD_GNSS_VCORE") + ), + MTK_PIN( + 178, "GPIO178", + MTK_EINT_FUNCTION(0, 178), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO178"), + MTK_FUNCTION(1, "DMIC_CLK"), + MTK_FUNCTION(2, "SCP_DMIC_CLK"), + MTK_FUNCTION(3, "SRCLKENAI0"), + MTK_FUNCTION(4, "CLKM2_B"), + MTK_FUNCTION(5, "TP_GPIO7_AO"), + MTK_FUNCTION(6, "SPU1_UTX"), + MTK_FUNCTION(7, "DAP_SONIC_SWCK") + ), + MTK_PIN( + 179, "GPIO179", + MTK_EINT_FUNCTION(0, 179), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO179"), + MTK_FUNCTION(1, "DMIC_DAT"), + MTK_FUNCTION(2, "SCP_DMIC_DAT"), + MTK_FUNCTION(3, "SRCLKENAI1"), + MTK_FUNCTION(4, "CLKM3_B"), + MTK_FUNCTION(5, "TP_GPIO8_AO"), + MTK_FUNCTION(6, "SPU1_URX"), + MTK_FUNCTION(7, "DAP_SONIC_SWD") + ), + MTK_PIN( + 180, "GPIO180", + MTK_EINT_FUNCTION(0, 180), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO180"), + MTK_FUNCTION(1, "IDDIG_1P"), + MTK_FUNCTION(2, "CMVREF0"), + MTK_FUNCTION(3, "GPS_PPS1"), + MTK_FUNCTION(4, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(5, "DISP_PWM1") + ), + MTK_PIN( + 181, "GPIO181", + MTK_EINT_FUNCTION(0, 181), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO181"), + MTK_FUNCTION(1, "USB_DRVVBUS_1P"), + MTK_FUNCTION(2, "CMVREF1"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TRSTN"), + MTK_FUNCTION(4, "ADSP_JTAG1_TRSTN"), + MTK_FUNCTION(5, "HFRP_JTAG1_TRSTN"), + MTK_FUNCTION(6, "SPU1_NTRST"), + MTK_FUNCTION(7, "CONN_BG_GPS_MCU_TRST_B") + ), + MTK_PIN( + 182, "GPIO182", + MTK_EINT_FUNCTION(0, 182), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO182"), + MTK_FUNCTION(1, "SCL11"), + MTK_FUNCTION(2, "CMVREF2"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TCK"), + MTK_FUNCTION(4, "ADSP_JTAG1_TCK"), + MTK_FUNCTION(5, "HFRP_JTAG1_TCK"), + MTK_FUNCTION(6, "SPU1_TCK"), + MTK_FUNCTION(7, "CONN_BG_GPS_MCU_TCK") + ), + MTK_PIN( + 183, "GPIO183", + MTK_EINT_FUNCTION(0, 183), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO183"), + MTK_FUNCTION(1, "SDA11"), + MTK_FUNCTION(2, "CMVREF3"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TMS"), + MTK_FUNCTION(4, "ADSP_JTAG1_TMS"), + MTK_FUNCTION(5, "HFRP_JTAG1_TMS"), + MTK_FUNCTION(6, "SPU1_TMS"), + MTK_FUNCTION(7, "CONN_BG_GPS_MCU_TMS") + ), + MTK_PIN( + 184, "GPIO184", + MTK_EINT_FUNCTION(0, 184), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO184"), + MTK_FUNCTION(1, "SCL12"), + MTK_FUNCTION(2, "CMVREF4"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TDO"), + MTK_FUNCTION(4, "ADSP_JTAG1_TDO"), + MTK_FUNCTION(5, "HFRP_JTAG1_TDO"), + MTK_FUNCTION(6, "SPU1_TDO"), + MTK_FUNCTION(7, "CONN_BG_GPS_MCU_TDO") + ), + MTK_PIN( + 185, "GPIO185", + MTK_EINT_FUNCTION(0, 185), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO185"), + MTK_FUNCTION(1, "SDA12"), + MTK_FUNCTION(2, "CMVREF5"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TDI"), + MTK_FUNCTION(4, "ADSP_JTAG1_TDI"), + MTK_FUNCTION(5, "HFRP_JTAG1_TDI"), + MTK_FUNCTION(6, "SPU1_TDI"), + MTK_FUNCTION(7, "CONN_BG_GPS_MCU_TDI") + ), + MTK_PIN( + 186, "GPIO186", + MTK_EINT_FUNCTION(0, 186), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO186"), + MTK_FUNCTION(1, "MD_GPS_L1_BLANK"), + MTK_FUNCTION(2, "PMSR_SMAP"), + MTK_FUNCTION(3, "TP_GPIO2_AO") + ), + MTK_PIN( + 187, "GPIO187", + MTK_EINT_FUNCTION(0, 187), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO187"), + MTK_FUNCTION(1, "MD_GPS_L5_BLANK"), + MTK_FUNCTION(3, "TP_GPIO4_AO") + ), + MTK_PIN( + 188, "GPIO188", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO188"), + MTK_FUNCTION(1, "SCL2"), + MTK_FUNCTION(2, "SCP_SCL8") + ), + MTK_PIN( + 189, "GPIO189", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO189"), + MTK_FUNCTION(1, "SDA2"), + MTK_FUNCTION(2, "SCP_SDA8") + ), + MTK_PIN( + 190, "GPIO190", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO190"), + MTK_FUNCTION(1, "SCL4"), + MTK_FUNCTION(2, "SCP_SCL9"), + MTK_FUNCTION(6, "UDI_TDI_6") + ), + MTK_PIN( + 191, "GPIO191", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO191"), + MTK_FUNCTION(1, "SDA4"), + MTK_FUNCTION(2, "SCP_SDA9"), + MTK_FUNCTION(6, "UDI_TDI_7") + ), + MTK_PIN( + 192, "GPIO192", + MTK_EINT_FUNCTION(0, 192), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO192"), + MTK_FUNCTION(1, "CMMCLK2"), + MTK_FUNCTION(4, "MD32_3_RXD") + ), + MTK_PIN( + 193, "GPIO193", + MTK_EINT_FUNCTION(0, 193), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO193"), + MTK_FUNCTION(3, "CLKM0_B"), + MTK_FUNCTION(4, "MD32_3_TXD"), + MTK_FUNCTION(6, "UDI_TDO_7") + ), + MTK_PIN( + 194, "GPIO194", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO194"), + MTK_FUNCTION(1, "SCL7"), + MTK_FUNCTION(2, "MD32_3_GPIO0"), + MTK_FUNCTION(3, "CLKM2_B"), + MTK_FUNCTION(6, "UDI_TDI_2") + ), + MTK_PIN( + 195, "GPIO195", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO195"), + MTK_FUNCTION(1, "SDA7"), + MTK_FUNCTION(3, "CLKM3_B"), + MTK_FUNCTION(6, "UDI_TDI_3") + ), + MTK_PIN( + 196, "GPIO196", + MTK_EINT_FUNCTION(0, 196), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO196"), + MTK_FUNCTION(1, "CMMCLK3") + ), + MTK_PIN( + 197, "GPIO197", + MTK_EINT_FUNCTION(0, 197), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO197"), + MTK_FUNCTION(3, "CLKM1_B"), + MTK_FUNCTION(6, "UDI_TDI_1") + ), + MTK_PIN( + 198, "GPIO198", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO198"), + MTK_FUNCTION(1, "SCL8"), + MTK_FUNCTION(6, "UDI_TDI_4") + ), + MTK_PIN( + 199, "GPIO199", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO199"), + MTK_FUNCTION(1, "SDA8"), + MTK_FUNCTION(6, "UDI_TDI_5") + ), + MTK_PIN( + 200, "GPIO200", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO200"), + MTK_FUNCTION(1, "SCL1") + ), + MTK_PIN( + 201, "GPIO201", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO201"), + MTK_FUNCTION(1, "SDA1"), + MTK_FUNCTION(7, "TSFDC_BG_COMP") + ), + MTK_PIN( + 202, "GPIO202", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO202"), + MTK_FUNCTION(1, "SCL9"), + MTK_FUNCTION(2, "SCP_SCL7"), + MTK_FUNCTION(6, "TP_GPIO15_AO") + ), + MTK_PIN( + 203, "GPIO203", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO203"), + MTK_FUNCTION(1, "SDA9"), + MTK_FUNCTION(2, "SCP_SDA7"), + MTK_FUNCTION(6, "TP_GPIO9_AO") + ), + MTK_PIN( + 204, "GPIO204", + MTK_EINT_FUNCTION(0, 204), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO204"), + MTK_FUNCTION(1, "SCL13"), + MTK_FUNCTION(2, "CMVREF6"), + MTK_FUNCTION(3, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(5, "CLKM2_B"), + MTK_FUNCTION(6, "TP_GPIO12_AO") + ), + MTK_PIN( + 205, "GPIO205", + MTK_EINT_FUNCTION(0, 205), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO205"), + MTK_FUNCTION(1, "SDA13"), + MTK_FUNCTION(2, "CMVREF7"), + MTK_FUNCTION(3, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(5, "CLKM3_B"), + MTK_FUNCTION(6, "TP_GPIO13_AO") + ), + MTK_PIN( + 206, "GPIO206", + MTK_EINT_FUNCTION(0, 206), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO206"), + MTK_FUNCTION(2, "MD32_2_GPIO0"), + MTK_FUNCTION(5, "VBUSVALID"), + MTK_FUNCTION(6, "UDI_TDO_3") + ), + MTK_PIN( + 207, "GPIO207", + MTK_EINT_FUNCTION(0, 207), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO207"), + MTK_FUNCTION(1, "PCIE_WAKEN_2P"), + MTK_FUNCTION(2, "PMSR_SMAP_MAX"), + MTK_FUNCTION(4, "FMI2S_A_BCK"), + MTK_FUNCTION(6, "UDI_TDO_4") + ), + MTK_PIN( + 208, "GPIO208", + MTK_EINT_FUNCTION(0, 208), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO208"), + MTK_FUNCTION(1, "PCIE_CLKREQN_2P"), + MTK_FUNCTION(2, "PMSR_SMAP_MAX_W"), + MTK_FUNCTION(4, "FMI2S_A_LRCK"), + MTK_FUNCTION(5, "CLKM0_B"), + MTK_FUNCTION(6, "UDI_TDO_5") + ), + MTK_PIN( + 209, "GPIO209", + MTK_EINT_FUNCTION(0, 209), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO209"), + MTK_FUNCTION(1, "PCIE_PERSTN_2P"), + MTK_FUNCTION(2, "PMSR_SMAP"), + MTK_FUNCTION(4, "FMI2S_A_DI"), + MTK_FUNCTION(5, "CLKM1_B"), + MTK_FUNCTION(6, "UDI_TDO_6") + ), + MTK_PIN( + 210, "GPIO210", + MTK_EINT_FUNCTION(0, 210), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO210"), + MTK_FUNCTION(1, "CMMCLK4") + ), + MTK_PIN( + 211, "GPIO211", + MTK_EINT_FUNCTION(0, 211), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO211"), + MTK_FUNCTION(1, "CMMCLK5"), + MTK_FUNCTION(2, "CONN_TCXOENA_REQ") + ), + MTK_PIN( + 212, "GPIO212", + MTK_EINT_FUNCTION(0, 212), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO212"), + MTK_FUNCTION(1, "CMMCLK6"), + MTK_FUNCTION(2, "TP_GPIO10_AO"), + MTK_FUNCTION(5, "IDDIG"), + MTK_FUNCTION(6, "UDI_TDO_1") + ), + MTK_PIN( + 213, "GPIO213", + MTK_EINT_FUNCTION(0, 213), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO213"), + MTK_FUNCTION(1, "CMMCLK7"), + MTK_FUNCTION(2, "TP_GPIO11_AO"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(6, "UDI_TDO_2") + ), + MTK_PIN( + 214, "GPIO214", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO214"), + MTK_FUNCTION(1, "SCP_SCL3"), + MTK_FUNCTION(2, "SDA14_E1_SCL14_E2"), + MTK_FUNCTION(6, "GBE1_MDC"), + MTK_FUNCTION(7, "GBE0_MDC") + ), + MTK_PIN( + 215, "GPIO215", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO215"), + MTK_FUNCTION(1, "SCP_SDA3"), + MTK_FUNCTION(2, "SCL14_E1_SDA14_E2"), + MTK_FUNCTION(6, "GBE1_MDIO"), + MTK_FUNCTION(7, "GBE0_MDIO") + ), + MTK_PIN( + 216, "GPIO216", + MTK_EINT_FUNCTION(0, 216), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO216"), + MTK_FUNCTION(1, "GPS_PPS0") + ), + MTK_PIN( + 217, "GPIO217", + MTK_EINT_FUNCTION(0, 217), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO217"), + MTK_FUNCTION(1, "KPROW0"), + MTK_FUNCTION(6, "TP_GPIO12_AO") + ), + MTK_PIN( + 218, "GPIO218", + MTK_EINT_FUNCTION(0, 218), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO218"), + MTK_FUNCTION(1, "KPROW1"), + MTK_FUNCTION(2, "SPI0_WP"), + MTK_FUNCTION(3, "MBISTREADEN_TRIGGER"), + MTK_FUNCTION(5, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(6, "TP_GPIO14_AO") + ), + MTK_PIN( + 219, "GPIO219", + MTK_EINT_FUNCTION(0, 219), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO219"), + MTK_FUNCTION(1, "KPCOL1"), + MTK_FUNCTION(2, "SPI0_HOLD"), + MTK_FUNCTION(3, "MBISTWRITEEN_TRIGGER"), + MTK_FUNCTION(4, "SPMI_M_TRIG_FLAG"), + MTK_FUNCTION(5, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(6, "SPM_JTAG_TRSTN_VLP"), + MTK_FUNCTION(7, "JTRSTN_SEL1") + ), + MTK_PIN( + 220, "GPIO220", + MTK_EINT_FUNCTION(0, 220), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO220"), + MTK_FUNCTION(1, "SPI0_CLK"), + MTK_FUNCTION(6, "SPM_JTAG_TCK_VLP"), + MTK_FUNCTION(7, "JTCK_SEL1") + ), + MTK_PIN( + 221, "GPIO221", + MTK_EINT_FUNCTION(0, 221), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO221"), + MTK_FUNCTION(1, "SPI0_CSB"), + MTK_FUNCTION(6, "SPM_JTAG_TMS_VLP"), + MTK_FUNCTION(7, "JTMS_SEL1") + ), + MTK_PIN( + 222, "GPIO222", + MTK_EINT_FUNCTION(0, 222), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO222"), + MTK_FUNCTION(1, "SPI0_MO"), + MTK_FUNCTION(2, "SCP_SCL7"), + MTK_FUNCTION(6, "SPM_JTAG_TDO_VLP"), + MTK_FUNCTION(7, "JTDO_SEL1") + ), + MTK_PIN( + 223, "GPIO223", + MTK_EINT_FUNCTION(0, 223), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO223"), + MTK_FUNCTION(1, "SPI0_MI"), + MTK_FUNCTION(2, "SCP_SDA7"), + MTK_FUNCTION(6, "SPM_JTAG_TDI_VLP"), + MTK_FUNCTION(7, "JTDI_SEL1") + ), + MTK_PIN( + 224, "GPIO224", + MTK_EINT_FUNCTION(0, 224), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO224"), + MTK_FUNCTION(1, "MSDC2_CLK"), + MTK_FUNCTION(2, "DMIC2_CLK"), + MTK_FUNCTION(3, "GBE0_AUX_PPS0"), + MTK_FUNCTION(4, "GBE0_TXER"), + MTK_FUNCTION(5, "GBE1_TXER"), + MTK_FUNCTION(6, "GBE1_AUX_PPS0"), + MTK_FUNCTION(7, "MD32_1_TXD") + ), + MTK_PIN( + 225, "GPIO225", + MTK_EINT_FUNCTION(0, 225), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO225"), + MTK_FUNCTION(1, "MSDC2_CMD"), + MTK_FUNCTION(2, "DMIC2_DAT"), + MTK_FUNCTION(3, "GBE0_AUX_PPS1"), + MTK_FUNCTION(4, "GBE0_RXER"), + MTK_FUNCTION(5, "GBE1_RXER"), + MTK_FUNCTION(6, "GBE1_AUX_PPS1"), + MTK_FUNCTION(7, "MD32_1_RXD") + ), + MTK_PIN( + 226, "GPIO226", + MTK_EINT_FUNCTION(0, 226), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO226"), + MTK_FUNCTION(1, "MSDC2_DAT0"), + MTK_FUNCTION(2, "I2SIN3_BCK"), + MTK_FUNCTION(3, "GBE0_AUX_PPS2"), + MTK_FUNCTION(4, "GBE0_COL"), + MTK_FUNCTION(5, "GBE1_COL"), + MTK_FUNCTION(6, "GBE1_AUX_PPS2"), + MTK_FUNCTION(7, "GBE1_MDC") + ), + MTK_PIN( + 227, "GPIO227", + MTK_EINT_FUNCTION(0, 227), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO227"), + MTK_FUNCTION(1, "MSDC2_DAT1"), + MTK_FUNCTION(2, "I2SIN3_LRCK"), + MTK_FUNCTION(3, "GBE0_AUX_PPS3"), + MTK_FUNCTION(4, "GBE0_INTR"), + MTK_FUNCTION(5, "GBE1_INTR"), + MTK_FUNCTION(6, "GBE1_AUX_PPS3"), + MTK_FUNCTION(7, "GBE1_MDIO") + ), + MTK_PIN( + 228, "GPIO228", + MTK_EINT_FUNCTION(0, 228), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO228"), + MTK_FUNCTION(1, "MSDC2_DAT2"), + MTK_FUNCTION(2, "I2SIN3_DI"), + MTK_FUNCTION(3, "GBE0_MDC"), + MTK_FUNCTION(4, "GBE1_MDC"), + MTK_FUNCTION(5, "CONN_BG_GPS_MCU_AICE_TCKC") + ), + MTK_PIN( + 229, "GPIO229", + MTK_EINT_FUNCTION(0, 229), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO229"), + MTK_FUNCTION(1, "MSDC2_DAT3"), + MTK_FUNCTION(2, "I2SOUT3_DO"), + MTK_FUNCTION(3, "GBE0_MDIO"), + MTK_FUNCTION(4, "GBE1_MDIO"), + MTK_FUNCTION(5, "CONN_BG_GPS_MCU_AICE_TMSC"), + MTK_FUNCTION(7, "AVB_CLK2") + ), + MTK_PIN( + 230, "GPIO230", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO230"), + MTK_FUNCTION(1, "CONN_TOP_CLK") + ), + MTK_PIN( + 231, "GPIO231", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO231"), + MTK_FUNCTION(1, "CONN_TOP_DATA") + ), + MTK_PIN( + 232, "GPIO232", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO232"), + MTK_FUNCTION(1, "CONN_HRST_B") + ), + MTK_PIN( + 233, "GPIO233", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO233"), + MTK_FUNCTION(1, "I2SIN0_BCK") + ), + MTK_PIN( + 234, "GPIO234", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO234"), + MTK_FUNCTION(1, "I2SIN0_LRCK") + ), + MTK_PIN( + 235, "GPIO235", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO235"), + MTK_FUNCTION(1, "I2SIN0_DI") + ), + MTK_PIN( + 236, "GPIO236", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO236"), + MTK_FUNCTION(1, "I2SOUT0_DO") + ), + MTK_PIN( + 237, "GPIO237", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO237"), + MTK_FUNCTION(1, "CONN_UARTHUB_UART_TX"), + MTK_FUNCTION(3, "UTXD3") + ), + MTK_PIN( + 238, "GPIO238", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO238"), + MTK_FUNCTION(1, "CONN_UARTHUB_UART_RX"), + MTK_FUNCTION(3, "URXD3") + ), + MTK_PIN( + 239, "GPIO239", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO239"), + MTK_FUNCTION(1, "TP_UTXD_CONSYS_VLP"), + MTK_FUNCTION(2, "TP_URXD_CONSYS_VLP") + ), + MTK_PIN( + 240, "GPIO240", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO240"), + MTK_FUNCTION(1, "TP_URXD_CONSYS_VLP"), + MTK_FUNCTION(2, "TP_UTXD_CONSYS_VLP") + ), + MTK_PIN( + 241, "GPIO241", + MTK_EINT_FUNCTION(0, 241), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO241"), + MTK_FUNCTION(1, "PCIE_PERSTN") + ), + MTK_PIN( + 242, "GPIO242", + MTK_EINT_FUNCTION(0, 242), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO242"), + MTK_FUNCTION(1, "PCIE_WAKEN") + ), + MTK_PIN( + 243, "GPIO243", + MTK_EINT_FUNCTION(0, 243), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO243"), + MTK_FUNCTION(1, "PCIE_CLKREQN") + ), + MTK_PIN( + 244, "GPIO244", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO244"), + MTK_FUNCTION(1, "CONN_RST") + ), + MTK_PIN( + 245, "GPIO245", + MTK_EINT_FUNCTION(0, 245), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO245") + ), + MTK_PIN( + 246, "GPIO246", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO246"), + MTK_FUNCTION(1, "CONN_PTA_TXD0") + ), + MTK_PIN( + 247, "GPIO247", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO247"), + MTK_FUNCTION(1, "CONN_PTA_RXD0") + ), + MTK_PIN( + 248, "GPIO248", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO248"), + MTK_FUNCTION(3, "UCTS3") + ), + MTK_PIN( + 249, "GPIO249", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO249"), + MTK_FUNCTION(3, "URTS3") + ), + MTK_PIN( + 250, "GPIO250", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO250") + ), + MTK_PIN( + 251, "GPIO251", + MTK_EINT_FUNCTION(0, 251), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO251"), + MTK_FUNCTION(1, "IDDIG_1P") + ), + MTK_PIN( + 252, "GPIO252", + MTK_EINT_FUNCTION(0, 252), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO252"), + MTK_FUNCTION(1, "USB_DRVVBUS_1P") + ), + MTK_PIN( + 253, "GPIO253", + MTK_EINT_FUNCTION(0, 253), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO253"), + MTK_FUNCTION(1, "VBUSVALID_1P") + ), + MTK_PIN( + 254, "GPIO254", + MTK_EINT_FUNCTION(0, 254), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO254"), + MTK_FUNCTION(1, "IDDIG_2P") + ), + MTK_PIN( + 255, "GPIO255", + MTK_EINT_FUNCTION(0, 255), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO255"), + MTK_FUNCTION(1, "USB_DRVVBUS_2P") + ), + MTK_PIN( + 256, "GPIO256", + MTK_EINT_FUNCTION(0, 256), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO256"), + MTK_FUNCTION(1, "VBUSVALID_2P") + ), + MTK_PIN( + 257, "GPIO257", + MTK_EINT_FUNCTION(0, 257), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO257"), + MTK_FUNCTION(1, "VBUSVALID_3P") + ), + MTK_PIN( + 258, "GPIO258", + MTK_EINT_FUNCTION(0, 258), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO258"), + MTK_FUNCTION(7, "AVB_CLK1") + ), + MTK_PIN( + 259, "GPIO259", + MTK_EINT_FUNCTION(0, 259), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO259"), + MTK_FUNCTION(1, "GBE0_TXD0"), + MTK_FUNCTION(2, "GBE1_TXD0") + ), + MTK_PIN( + 260, "GPIO260", + MTK_EINT_FUNCTION(0, 260), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO260"), + MTK_FUNCTION(1, "GBE0_TXD1"), + MTK_FUNCTION(2, "GBE1_TXD1") + ), + MTK_PIN( + 261, "GPIO261", + MTK_EINT_FUNCTION(0, 261), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO261"), + MTK_FUNCTION(1, "GBE0_TXC"), + MTK_FUNCTION(2, "GBE1_TXC") + ), + MTK_PIN( + 262, "GPIO262", + MTK_EINT_FUNCTION(0, 262), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO262"), + MTK_FUNCTION(1, "GBE0_TXEN"), + MTK_FUNCTION(2, "GBE1_TXEN") + ), + MTK_PIN( + 263, "GPIO263", + MTK_EINT_FUNCTION(0, 263), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO263"), + MTK_FUNCTION(1, "GBE0_RXD0"), + MTK_FUNCTION(2, "GBE1_RXD0"), + MTK_FUNCTION(3, "GBE0_AUX_PPS0") + ), + MTK_PIN( + 264, "GPIO264", + MTK_EINT_FUNCTION(0, 264), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO264"), + MTK_FUNCTION(1, "GBE0_RXD1"), + MTK_FUNCTION(2, "GBE1_RXD1"), + MTK_FUNCTION(3, "GBE0_AUX_PPS1") + ), + MTK_PIN( + 265, "GPIO265", + MTK_EINT_FUNCTION(0, 265), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO265"), + MTK_FUNCTION(1, "GBE0_RXC"), + MTK_FUNCTION(2, "GBE1_RXC"), + MTK_FUNCTION(3, "GBE0_AUX_PPS2") + ), + MTK_PIN( + 266, "GPIO266", + MTK_EINT_FUNCTION(0, 266), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO266"), + MTK_FUNCTION(1, "GBE0_RXDV"), + MTK_FUNCTION(2, "GBE1_RXDV"), + MTK_FUNCTION(3, "GBE0_AUX_PPS3") + ), + MTK_PIN( + 267, "GPIO267", + MTK_EINT_FUNCTION(0, 267), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO267"), + MTK_FUNCTION(1, "GBE0_TXD2"), + MTK_FUNCTION(2, "GBE1_TXD2"), + MTK_FUNCTION(3, "GBE0_RXER"), + MTK_FUNCTION(4, "GBE1_RXER") + ), + MTK_PIN( + 268, "GPIO268", + MTK_EINT_FUNCTION(0, 268), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO268"), + MTK_FUNCTION(1, "GBE0_TXD3"), + MTK_FUNCTION(2, "GBE1_TXD3") + ), + MTK_PIN( + 269, "GPIO269", + MTK_EINT_FUNCTION(0, 269), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO269"), + MTK_FUNCTION(1, "GBE0_RXD2"), + MTK_FUNCTION(2, "GBE1_RXD2"), + MTK_FUNCTION(3, "GBE0_MDC") + ), + MTK_PIN( + 270, "GPIO270", + MTK_EINT_FUNCTION(0, 270), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO270"), + MTK_FUNCTION(1, "GBE0_RXD3"), + MTK_FUNCTION(2, "GBE1_RXD3"), + MTK_FUNCTION(3, "GBE0_MDIO") + ), + MTK_PIN( + 271, "veint271", + MTK_EINT_FUNCTION(0, 271), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 272, "veint272", + MTK_EINT_FUNCTION(0, 272), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 273, "veint273", + MTK_EINT_FUNCTION(0, 273), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 274, "veint274", + MTK_EINT_FUNCTION(0, 274), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 275, "veint275", + MTK_EINT_FUNCTION(0, 275), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 276, "veint276", + MTK_EINT_FUNCTION(0, 276), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 277, "veint277", + MTK_EINT_FUNCTION(0, 277), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 278, "veint278", + MTK_EINT_FUNCTION(0, 278), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 279, "veint279", + MTK_EINT_FUNCTION(0, 279), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 280, "veint280", + MTK_EINT_FUNCTION(0, 280), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 281, "veint281", + MTK_EINT_FUNCTION(0, 281), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 282, "veint282", + MTK_EINT_FUNCTION(0, 282), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 283, "veint283", + MTK_EINT_FUNCTION(0, 283), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 284, "veint284", + MTK_EINT_FUNCTION(0, 284), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 285, "veint285", + MTK_EINT_FUNCTION(0, 285), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 286, "veint286", + MTK_EINT_FUNCTION(0, 286), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 287, "veint287", + MTK_EINT_FUNCTION(0, 287), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 288, "veint288", + MTK_EINT_FUNCTION(0, 288), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 289, "veint289", + MTK_EINT_FUNCTION(0, 289), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 290, "veint290", + MTK_EINT_FUNCTION(0, 290), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 291, "veint291", + MTK_EINT_FUNCTION(0, 291), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 292, "veint292", + MTK_EINT_FUNCTION(0, 292), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ) +}; + +static struct mtk_eint_pin eint_pins_mt8196[] = { + MTK_EINT_PIN(0, 2, 0, 1), + MTK_EINT_PIN(1, 2, 1, 1), + MTK_EINT_PIN(2, 2, 16, 0), + MTK_EINT_PIN(3, 2, 17, 0), + MTK_EINT_PIN(4, 2, 2, 1), + MTK_EINT_PIN(5, 2, 3, 1), + MTK_EINT_PIN(6, 2, 4, 1), + MTK_EINT_PIN(7, 2, 5, 1), + MTK_EINT_PIN(8, 2, 6, 1), + MTK_EINT_PIN(9, 2, 18, 0), + MTK_EINT_PIN(10, 2, 7, 1), + MTK_EINT_PIN(11, 2, 8, 1), + MTK_EINT_PIN(12, 2, 9, 1), + MTK_EINT_PIN(13, 1, 4, 0), + MTK_EINT_PIN(14, 0, 0, 1), + MTK_EINT_PIN(15, 1, 5, 0), + MTK_EINT_PIN(16, 1, 6, 0), + MTK_EINT_PIN(17, 1, 7, 0), + MTK_EINT_PIN(18, 1, 8, 0), + MTK_EINT_PIN(19, 1, 9, 0), + MTK_EINT_PIN(20, 0, 1, 1), + MTK_EINT_PIN(21, 0, 10, 0), + MTK_EINT_PIN(22, 0, 11, 0), + MTK_EINT_PIN(23, 0, 12, 0), + MTK_EINT_PIN(24, 0, 13, 0), + MTK_EINT_PIN(25, 0, 14, 0), + MTK_EINT_PIN(26, 0, 15, 0), + MTK_EINT_PIN(27, 0, 2, 1), + MTK_EINT_PIN(28, 0, 16, 0), + MTK_EINT_PIN(29, 0, 17, 0), + MTK_EINT_PIN(30, 0, 18, 0), + MTK_EINT_PIN(31, 0, 3, 1), + MTK_EINT_PIN(32, 0, 19, 0), + MTK_EINT_PIN(33, 0, 20, 0), + MTK_EINT_PIN(34, 0, 21, 0), + MTK_EINT_PIN(35, 0, 22, 0), + MTK_EINT_PIN(36, 0, 23, 0), + MTK_EINT_PIN(37, 0, 24, 0), + MTK_EINT_PIN(38, 0, 25, 0), + MTK_EINT_PIN(39, 2, 10, 1), + MTK_EINT_PIN(40, 2, 11, 1), + MTK_EINT_PIN(41, 2, 12, 1), + MTK_EINT_PIN(42, 2, 13, 1), + MTK_EINT_PIN(43, 2, 14, 1), + MTK_EINT_PIN(44, 2, 19, 0), + MTK_EINT_PIN(45, 2, 20, 0), + MTK_EINT_PIN(46, 2, 21, 0), + MTK_EINT_PIN(47, 2, 22, 0), + MTK_EINT_PIN(48, 2, 23, 0), + MTK_EINT_PIN(49, 2, 24, 0), + MTK_EINT_PIN(50, 2, 25, 0), + MTK_EINT_PIN(51, 2, 26, 0), + MTK_EINT_PIN(52, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(53, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(54, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(55, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(56, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(57, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(58, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(59, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(60, 2, 27, 0), + MTK_EINT_PIN(61, 2, 28, 0), + MTK_EINT_PIN(62, 2, 29, 0), + MTK_EINT_PIN(63, 2, 30, 0), + MTK_EINT_PIN(64, 2, 31, 0), + MTK_EINT_PIN(65, 2, 32, 0), + MTK_EINT_PIN(66, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(67, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(68, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(69, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(70, 2, 33, 0), + MTK_EINT_PIN(71, 2, 34, 0), + MTK_EINT_PIN(72, 2, 35, 0), + MTK_EINT_PIN(73, 2, 36, 0), + MTK_EINT_PIN(74, 2, 37, 0), + MTK_EINT_PIN(75, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(76, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(77, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(78, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(79, 2, 38, 0), + MTK_EINT_PIN(80, 2, 39, 0), + MTK_EINT_PIN(81, 2, 40, 0), + MTK_EINT_PIN(82, 2, 41, 0), + MTK_EINT_PIN(83, 2, 42, 0), + MTK_EINT_PIN(84, 2, 43, 0), + MTK_EINT_PIN(85, 2, 44, 0), + MTK_EINT_PIN(86, 2, 45, 0), + MTK_EINT_PIN(87, 2, 46, 0), + MTK_EINT_PIN(88, 2, 47, 0), + MTK_EINT_PIN(89, 2, 48, 0), + MTK_EINT_PIN(90, 2, 49, 0), + MTK_EINT_PIN(91, 2, 50, 0), + MTK_EINT_PIN(92, 2, 15, 1), + MTK_EINT_PIN(93, 2, 51, 0), + MTK_EINT_PIN(94, 2, 52, 0), + MTK_EINT_PIN(95, 2, 53, 0), + MTK_EINT_PIN(96, 2, 54, 0), + MTK_EINT_PIN(97, 2, 55, 0), + MTK_EINT_PIN(98, 2, 56, 0), + MTK_EINT_PIN(99, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(100, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(101, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(102, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(103, 2, 57, 0), + MTK_EINT_PIN(104, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(105, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(106, 1, 10, 0), + MTK_EINT_PIN(107, 1, 11, 0), + MTK_EINT_PIN(108, 1, 12, 0), + MTK_EINT_PIN(109, 1, 13, 0), + MTK_EINT_PIN(110, 1, 0, 1), + MTK_EINT_PIN(111, 1, 1, 1), + MTK_EINT_PIN(112, 1, 2, 1), + MTK_EINT_PIN(113, 1, 3, 1), + MTK_EINT_PIN(114, 1, 14, 0), + MTK_EINT_PIN(115, 1, 15, 0), + MTK_EINT_PIN(116, 1, 16, 0), + MTK_EINT_PIN(117, 1, 17, 0), + MTK_EINT_PIN(118, 1, 18, 0), + MTK_EINT_PIN(119, 1, 19, 0), + MTK_EINT_PIN(120, 1, 20, 0), + MTK_EINT_PIN(121, 1, 21, 0), + MTK_EINT_PIN(122, 1, 22, 0), + MTK_EINT_PIN(123, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(124, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(125, 1, 23, 0), + MTK_EINT_PIN(126, 1, 24, 0), + MTK_EINT_PIN(127, 1, 25, 0), + MTK_EINT_PIN(128, 1, 26, 0), + MTK_EINT_PIN(129, 1, 27, 0), + MTK_EINT_PIN(130, 1, 28, 0), + MTK_EINT_PIN(131, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(132, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(133, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(134, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(135, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(136, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(137, 0, 26, 0), + MTK_EINT_PIN(138, 0, 27, 0), + MTK_EINT_PIN(139, 0, 28, 0), + MTK_EINT_PIN(140, 0, 29, 0), + MTK_EINT_PIN(141, 0, 30, 0), + MTK_EINT_PIN(142, 0, 31, 0), + MTK_EINT_PIN(143, 0, 32, 0), + MTK_EINT_PIN(144, 0, 33, 0), + MTK_EINT_PIN(145, 0, 34, 0), + MTK_EINT_PIN(146, 0, 35, 0), + MTK_EINT_PIN(147, 0, 36, 0), + MTK_EINT_PIN(148, 0, 4, 1), + MTK_EINT_PIN(149, 0, 37, 0), + MTK_EINT_PIN(150, 0, 5, 1), + MTK_EINT_PIN(151, 0, 38, 0), + MTK_EINT_PIN(152, 0, 39, 0), + MTK_EINT_PIN(153, 0, 40, 0), + MTK_EINT_PIN(154, 0, 41, 0), + MTK_EINT_PIN(155, 0, 42, 0), + MTK_EINT_PIN(156, 0, 43, 0), + MTK_EINT_PIN(157, 0, 44, 0), + MTK_EINT_PIN(158, 0, 45, 0), + MTK_EINT_PIN(159, 0, 46, 0), + MTK_EINT_PIN(160, 0, 47, 0), + MTK_EINT_PIN(161, 0, 48, 0), + MTK_EINT_PIN(162, 0, 49, 0), + MTK_EINT_PIN(163, 0, 50, 0), + MTK_EINT_PIN(164, 0, 51, 0), + MTK_EINT_PIN(165, 0, 52, 0), + MTK_EINT_PIN(166, 0, 53, 0), + MTK_EINT_PIN(167, 0, 54, 0), + MTK_EINT_PIN(168, 0, 55, 0), + MTK_EINT_PIN(169, 0, 56, 0), + MTK_EINT_PIN(170, 0, 57, 0), + MTK_EINT_PIN(171, 0, 58, 0), + MTK_EINT_PIN(172, 0, 6, 1), + MTK_EINT_PIN(173, 0, 7, 1), + MTK_EINT_PIN(174, 0, 8, 1), + MTK_EINT_PIN(175, 0, 9, 1), + MTK_EINT_PIN(176, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(177, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(178, 0, 59, 0), + MTK_EINT_PIN(179, 0, 60, 0), + MTK_EINT_PIN(180, 0, 61, 0), + MTK_EINT_PIN(181, 0, 62, 0), + MTK_EINT_PIN(182, 0, 63, 0), + MTK_EINT_PIN(183, 0, 64, 0), + MTK_EINT_PIN(184, 0, 65, 0), + MTK_EINT_PIN(185, 0, 66, 0), + MTK_EINT_PIN(186, 3, 6, 0), + MTK_EINT_PIN(187, 3, 7, 0), + MTK_EINT_PIN(188, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(189, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(190, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(191, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(192, 3, 8, 0), + MTK_EINT_PIN(193, 3, 9, 0), + MTK_EINT_PIN(194, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(195, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(196, 3, 10, 0), + MTK_EINT_PIN(197, 3, 11, 0), + MTK_EINT_PIN(198, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(199, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(200, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(201, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(202, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(203, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(204, 3, 12, 0), + MTK_EINT_PIN(205, 3, 13, 0), + MTK_EINT_PIN(206, 3, 14, 0), + MTK_EINT_PIN(207, 3, 0, 1), + MTK_EINT_PIN(208, 3, 1, 1), + MTK_EINT_PIN(209, 3, 2, 1), + MTK_EINT_PIN(210, 3, 15, 0), + MTK_EINT_PIN(211, 3, 3, 1), + MTK_EINT_PIN(212, 3, 4, 1), + MTK_EINT_PIN(213, 3, 5, 1), + MTK_EINT_PIN(214, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(215, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(216, 3, 16, 0), + MTK_EINT_PIN(217, 3, 17, 0), + MTK_EINT_PIN(218, 3, 18, 0), + MTK_EINT_PIN(219, 3, 19, 0), + MTK_EINT_PIN(220, 3, 20, 0), + MTK_EINT_PIN(221, 3, 21, 0), + MTK_EINT_PIN(222, 3, 22, 0), + MTK_EINT_PIN(223, 3, 23, 0), + MTK_EINT_PIN(224, 3, 24, 0), + MTK_EINT_PIN(225, 3, 25, 0), + MTK_EINT_PIN(226, 3, 26, 0), + MTK_EINT_PIN(227, 3, 27, 0), + MTK_EINT_PIN(228, 3, 28, 0), + MTK_EINT_PIN(229, 3, 29, 0), + MTK_EINT_PIN(230, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(231, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(232, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(233, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(234, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(235, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(236, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(237, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(238, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(239, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(240, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(241, 3, 30, 0), + MTK_EINT_PIN(242, 3, 31, 0), + MTK_EINT_PIN(243, 3, 32, 0), + MTK_EINT_PIN(244, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(245, 3, 45, 0), + MTK_EINT_PIN(246, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(247, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(248, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(249, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(250, EINT_INVALID_BASE, 0, 0), + MTK_EINT_PIN(251, 0, 67, 0), + MTK_EINT_PIN(252, 0, 68, 0), + MTK_EINT_PIN(253, 0, 69, 0), + MTK_EINT_PIN(254, 0, 70, 0), + MTK_EINT_PIN(255, 0, 71, 0), + MTK_EINT_PIN(256, 0, 72, 0), + MTK_EINT_PIN(257, 0, 73, 0), + MTK_EINT_PIN(258, 0, 74, 0), + MTK_EINT_PIN(259, 3, 33, 0), + MTK_EINT_PIN(260, 3, 34, 0), + MTK_EINT_PIN(261, 3, 35, 0), + MTK_EINT_PIN(262, 3, 36, 0), + MTK_EINT_PIN(263, 3, 37, 0), + MTK_EINT_PIN(264, 3, 38, 0), + MTK_EINT_PIN(265, 3, 39, 0), + MTK_EINT_PIN(266, 3, 40, 0), + MTK_EINT_PIN(267, 3, 41, 0), + MTK_EINT_PIN(268, 3, 42, 0), + MTK_EINT_PIN(269, 3, 43, 0), + MTK_EINT_PIN(270, 3, 44, 0), + MTK_EINT_PIN(271, 4, 0, 0), + MTK_EINT_PIN(272, 4, 1, 0), + MTK_EINT_PIN(273, 4, 2, 0), + MTK_EINT_PIN(274, 4, 3, 0), + MTK_EINT_PIN(275, 4, 4, 0), + MTK_EINT_PIN(276, 4, 5, 0), + MTK_EINT_PIN(277, 4, 6, 0), + MTK_EINT_PIN(278, 4, 7, 0), + MTK_EINT_PIN(279, 4, 8, 0), + MTK_EINT_PIN(280, 4, 9, 0), + MTK_EINT_PIN(281, 4, 10, 0), + MTK_EINT_PIN(282, 4, 11, 0), + MTK_EINT_PIN(283, 4, 12, 0), + MTK_EINT_PIN(284, 4, 13, 0), + MTK_EINT_PIN(285, 4, 14, 0), + MTK_EINT_PIN(286, 4, 15, 0), + MTK_EINT_PIN(287, 4, 16, 0), + MTK_EINT_PIN(288, 4, 17, 0), + MTK_EINT_PIN(289, 4, 18, 0), + MTK_EINT_PIN(290, 4, 19, 0), + MTK_EINT_PIN(291, 4, 20, 0), + MTK_EINT_PIN(292, 4, 21, 0), +}; +#endif /* __PINCTRL_MTK_MT8196_H */ diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index 87e958d827bf..89ef4e530fcc 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -840,9 +840,6 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) const struct mtk_pin_desc *desc; int value, err; - if (gpio >= hw->soc->npins) - return -EINVAL; - /* * "Virtual" GPIOs are always and only used for interrupts * Since they are only used for interrupts, they are always inputs @@ -868,9 +865,6 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio) const struct mtk_pin_desc *desc; int value, err; - if (gpio >= hw->soc->npins) - return -EINVAL; - desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value); @@ -880,38 +874,29 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio) return !!value; } -static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) +static int mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) { struct mtk_pinctrl *hw = gpiochip_get_data(chip); const struct mtk_pin_desc *desc; - if (gpio >= hw->soc->npins) - return; - desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; - mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value); + return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value); } static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) { - struct mtk_pinctrl *hw = gpiochip_get_data(chip); - - if (gpio >= hw->soc->npins) - return -EINVAL; - return pinctrl_gpio_direction_input(chip, gpio); } static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, int value) { - struct mtk_pinctrl *hw = gpiochip_get_data(chip); - - if (gpio >= hw->soc->npins) - return -EINVAL; + int ret; - mtk_gpio_set(chip, gpio, value); + ret = mtk_gpio_set(chip, gpio, value); + if (ret) + return ret; return pinctrl_gpio_direction_output(chip, gpio); } @@ -964,7 +949,7 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw) chip->direction_input = mtk_gpio_direction_input; chip->direction_output = mtk_gpio_direction_output; chip->get = mtk_gpio_get; - chip->set = mtk_gpio_set; + chip->set_rv = mtk_gpio_set; chip->to_irq = mtk_gpio_to_irq; chip->set_config = mtk_gpio_set_config; chip->base = -1; diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.h b/drivers/pinctrl/mediatek/pinctrl-paris.h index 948ce126aa0c..d8c1822662fc 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.h +++ b/drivers/pinctrl/mediatek/pinctrl-paris.h @@ -49,6 +49,13 @@ __VA_ARGS__, { } }, \ } +#define MTK_EINT_PIN(_number, _instance, _index, _debounce) { \ + .number = _number, \ + .instance = _instance, \ + .index = _index, \ + .debounce = _debounce, \ + } + #define PINCTRL_PIN_GROUP(_name_, id) \ { \ .grp = PINCTRL_PINGROUP(_name_,id##_pins, ARRAY_SIZE(id##_pins)), \ diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig index cc397896762c..0315e224bce6 100644 --- a/drivers/pinctrl/meson/Kconfig +++ b/drivers/pinctrl/meson/Kconfig @@ -3,7 +3,7 @@ menuconfig PINCTRL_MESON tristate "Amlogic SoC pinctrl drivers" depends on ARCH_MESON || COMPILE_TEST depends on OF - default y + default ARCH_MESON select PINMUX select PINCONF select GENERIC_PINCONF @@ -17,25 +17,25 @@ config PINCTRL_MESON8 bool "Meson 8 SoC pinctrl driver" depends on ARM select PINCTRL_MESON8_PMX - default y + default ARCH_MESON config PINCTRL_MESON8B bool "Meson 8b SoC pinctrl driver" depends on ARM select PINCTRL_MESON8_PMX - default y + default ARCH_MESON config PINCTRL_MESON_GXBB tristate "Meson gxbb SoC pinctrl driver" depends on ARM64 select PINCTRL_MESON8_PMX - default y + default ARCH_MESON config PINCTRL_MESON_GXL tristate "Meson gxl SoC pinctrl driver" depends on ARM64 select PINCTRL_MESON8_PMX - default y + default ARCH_MESON config PINCTRL_MESON8_PMX tristate @@ -44,7 +44,7 @@ config PINCTRL_MESON_AXG tristate "Meson axg Soc pinctrl driver" depends on ARM64 select PINCTRL_MESON_AXG_PMX - default y + default ARCH_MESON config PINCTRL_MESON_AXG_PMX tristate @@ -53,30 +53,41 @@ config PINCTRL_MESON_G12A tristate "Meson g12a Soc pinctrl driver" depends on ARM64 select PINCTRL_MESON_AXG_PMX - default y + default ARCH_MESON config PINCTRL_MESON_A1 tristate "Meson a1 Soc pinctrl driver" depends on ARM64 select PINCTRL_MESON_AXG_PMX - default y + default ARCH_MESON config PINCTRL_MESON_S4 tristate "Meson s4 Soc pinctrl driver" depends on ARM64 select PINCTRL_MESON_AXG_PMX - default y + default ARCH_MESON + +config PINCTRL_AMLOGIC_A4 + bool "AMLOGIC pincontrol" + depends on ARM64 + default ARCH_MESON + help + This is the driver for the pin controller found on Amlogic SoCs. + + This driver is simplify subsequent support for new amlogic SoCs, + to support new Amlogic SoCs, only need to add the corresponding dts file, + no additional binding header files or C file are added. config PINCTRL_AMLOGIC_C3 tristate "Amlogic C3 SoC pinctrl driver" depends on ARM64 select PINCTRL_MESON_AXG_PMX - default y + default ARCH_MESON config PINCTRL_AMLOGIC_T7 tristate "Amlogic T7 SoC pinctrl driver" depends on ARM64 select PINCTRL_MESON_AXG_PMX - default y + default ARCH_MESON endif diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile index 9e538b9ffb9b..c92a65a83344 100644 --- a/drivers/pinctrl/meson/Makefile +++ b/drivers/pinctrl/meson/Makefile @@ -10,5 +10,6 @@ obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o obj-$(CONFIG_PINCTRL_MESON_S4) += pinctrl-meson-s4.o +obj-$(CONFIG_PINCTRL_AMLOGIC_A4) += pinctrl-amlogic-a4.o obj-$(CONFIG_PINCTRL_AMLOGIC_C3) += pinctrl-amlogic-c3.o obj-$(CONFIG_PINCTRL_AMLOGIC_T7) += pinctrl-amlogic-t7.o diff --git a/drivers/pinctrl/meson/pinctrl-amlogic-a4.c b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c new file mode 100644 index 000000000000..385cc619df13 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-amlogic-a4.c @@ -0,0 +1,1039 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Xianwei Zhao <xianwei.zhao@amlogic.com> + */ + +#include <linux/err.h> +#include <linux/gpio/driver.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/seq_file.h> +#include <linux/slab.h> +#include <linux/string_helpers.h> + +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <dt-bindings/pinctrl/amlogic,pinctrl.h> + +#include "../core.h" +#include "../pinconf.h" + +#define gpio_chip_to_bank(chip) \ + container_of(chip, struct aml_gpio_bank, gpio_chip) + +#define AML_REG_PULLEN 0 +#define AML_REG_PULL 1 +#define AML_REG_DIR 2 +#define AML_REG_OUT 3 +#define AML_REG_IN 4 +#define AML_REG_DS 5 +#define AML_NUM_REG 6 + +enum aml_pinconf_drv { + PINCONF_DRV_500UA, + PINCONF_DRV_2500UA, + PINCONF_DRV_3000UA, + PINCONF_DRV_4000UA, +}; + +struct aml_pio_control { + u32 gpio_offset; + u32 reg_offset[AML_NUM_REG]; + u32 bit_offset[AML_NUM_REG]; +}; + +struct aml_reg_bit { + u32 bank_id; + u32 reg_offs[AML_NUM_REG]; + u32 bit_offs[AML_NUM_REG]; +}; + +struct aml_pctl_data { + unsigned int number; + struct aml_reg_bit rb_offs[]; +}; + +struct aml_pmx_func { + const char *name; + const char **groups; + unsigned int ngroups; +}; + +struct aml_pctl_group { + const char *name; + unsigned int npins; + unsigned int *pins; + unsigned int *func; +}; + +struct aml_gpio_bank { + struct gpio_chip gpio_chip; + struct aml_pio_control pc; + u32 bank_id; + unsigned int pin_base; + struct regmap *reg_mux; + struct regmap *reg_gpio; + struct regmap *reg_ds; +}; + +struct aml_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl; + struct aml_gpio_bank *banks; + int nbanks; + struct aml_pmx_func *functions; + int nfunctions; + struct aml_pctl_group *groups; + int ngroups; + + const struct aml_pctl_data *data; +}; + +static const unsigned int aml_bit_strides[AML_NUM_REG] = { + 1, 1, 1, 1, 1, 2 +}; + +static const unsigned int aml_def_regoffs[AML_NUM_REG] = { + 3, 4, 2, 1, 0, 7 +}; + +static const char *aml_bank_name[31] = { +"GPIOA", "GPIOB", "GPIOC", "GPIOD", "GPIOE", "GPIOF", "GPIOG", +"GPIOH", "GPIOI", "GPIOJ", "GPIOK", "GPIOL", "GPIOM", "GPION", +"GPIOO", "GPIOP", "GPIOQ", "GPIOR", "GPIOS", "GPIOT", "GPIOU", +"GPIOV", "GPIOW", "GPIOX", "GPIOY", "GPIOZ", "GPIODV", "GPIOAO", +"GPIOCC", "TEST_N", "ANALOG" +}; + +static int aml_pmx_calc_reg_and_offset(struct pinctrl_gpio_range *range, + unsigned int pin, unsigned int *reg, + unsigned int *offset) +{ + unsigned int shift; + + shift = (pin - range->pin_base) << 2; + *reg = (shift / 32) * 4; + *offset = shift % 32; + + return 0; +} + +static int aml_pctl_set_function(struct aml_pinctrl *info, + struct pinctrl_gpio_range *range, + int pin_id, int func) +{ + struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); + int reg; + int offset; + + if (!bank->reg_mux) + return 0; + + aml_pmx_calc_reg_and_offset(range, pin_id, ®, &offset); + return regmap_update_bits(bank->reg_mux, reg, + 0xf << offset, (func & 0xf) << offset); +} + +static int aml_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->nfunctions; +} + +static const char *aml_pmx_get_fname(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->functions[selector].name; +} + +static int aml_pmx_get_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **grps, + unsigned * const ngrps) +{ + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + *grps = info->functions[selector].groups; + *ngrps = info->functions[selector].ngroups; + + return 0; +} + +static int aml_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned int fselector, + unsigned int group_id) +{ + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct aml_pctl_group *group = &info->groups[group_id]; + struct pinctrl_gpio_range *range; + int i; + + for (i = 0; i < group->npins; i++) { + range = pinctrl_find_gpio_range_from_pin(pctldev, group->pins[i]); + aml_pctl_set_function(info, range, group->pins[i], group->func[i]); + } + + return 0; +} + +static int aml_pmx_request_gpio(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return aml_pctl_set_function(info, range, pin, 0); +} + +static const struct pinmux_ops aml_pmx_ops = { + .set_mux = aml_pmx_set_mux, + .get_functions_count = aml_pmx_get_funcs_count, + .get_function_name = aml_pmx_get_fname, + .get_function_groups = aml_pmx_get_groups, + .gpio_request_enable = aml_pmx_request_gpio, +}; + +static int aml_calc_reg_and_bit(struct pinctrl_gpio_range *range, + unsigned int pin, + unsigned int reg_type, + unsigned int *reg, unsigned int *bit) +{ + struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); + + *bit = (pin - range->pin_base) * aml_bit_strides[reg_type] + + bank->pc.bit_offset[reg_type]; + *reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4; + *bit &= 0x1f; + + return 0; +} + +static int aml_pinconf_get_pull(struct aml_pinctrl *info, unsigned int pin) +{ + struct pinctrl_gpio_range *range = + pinctrl_find_gpio_range_from_pin(info->pctl, pin); + struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); + unsigned int reg, bit, val; + int ret, conf; + + aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); + + ret = regmap_read(bank->reg_gpio, reg, &val); + if (ret) + return ret; + + if (!(val & BIT(bit))) { + conf = PIN_CONFIG_BIAS_DISABLE; + } else { + aml_calc_reg_and_bit(range, pin, AML_REG_PULL, ®, &bit); + + ret = regmap_read(bank->reg_gpio, reg, &val); + if (ret) + return ret; + + if (val & BIT(bit)) + conf = PIN_CONFIG_BIAS_PULL_UP; + else + conf = PIN_CONFIG_BIAS_PULL_DOWN; + } + + return conf; +} + +static int aml_pinconf_get_drive_strength(struct aml_pinctrl *info, + unsigned int pin, + u16 *drive_strength_ua) +{ + struct pinctrl_gpio_range *range = + pinctrl_find_gpio_range_from_pin(info->pctl, pin); + struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); + unsigned int reg, bit; + unsigned int val; + int ret; + + if (!bank->reg_ds) + return -EOPNOTSUPP; + + aml_calc_reg_and_bit(range, pin, AML_REG_DS, ®, &bit); + ret = regmap_read(bank->reg_ds, reg, &val); + if (ret) + return ret; + + switch ((val >> bit) & 0x3) { + case PINCONF_DRV_500UA: + *drive_strength_ua = 500; + break; + case PINCONF_DRV_2500UA: + *drive_strength_ua = 2500; + break; + case PINCONF_DRV_3000UA: + *drive_strength_ua = 3000; + break; + case PINCONF_DRV_4000UA: + *drive_strength_ua = 4000; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int aml_pinconf_get_gpio_bit(struct aml_pinctrl *info, + unsigned int pin, + unsigned int reg_type) +{ + struct pinctrl_gpio_range *range = + pinctrl_find_gpio_range_from_pin(info->pctl, pin); + struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); + unsigned int reg, bit, val; + int ret; + + aml_calc_reg_and_bit(range, pin, reg_type, ®, &bit); + ret = regmap_read(bank->reg_gpio, reg, &val); + if (ret) + return ret; + + return BIT(bit) & val ? 1 : 0; +} + +static int aml_pinconf_get_output(struct aml_pinctrl *info, + unsigned int pin) +{ + int ret = aml_pinconf_get_gpio_bit(info, pin, AML_REG_DIR); + + if (ret < 0) + return ret; + + return !ret; +} + +static int aml_pinconf_get_drive(struct aml_pinctrl *info, + unsigned int pin) +{ + return aml_pinconf_get_gpio_bit(info, pin, AML_REG_OUT); +} + +static int aml_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, + unsigned long *config) +{ + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); + enum pin_config_param param = pinconf_to_config_param(*config); + u16 arg; + int ret; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_UP: + if (aml_pinconf_get_pull(info, pin) == param) + arg = 1; + else + return -EINVAL; + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + ret = aml_pinconf_get_drive_strength(info, pin, &arg); + if (ret) + return ret; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + ret = aml_pinconf_get_output(info, pin); + if (ret <= 0) + return -EINVAL; + arg = 1; + break; + case PIN_CONFIG_OUTPUT: + ret = aml_pinconf_get_output(info, pin); + if (ret <= 0) + return -EINVAL; + + ret = aml_pinconf_get_drive(info, pin); + if (ret < 0) + return -EINVAL; + + arg = ret; + break; + + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + dev_dbg(info->dev, "pinconf for pin %u is %lu\n", pin, *config); + + return 0; +} + +static int aml_pinconf_disable_bias(struct aml_pinctrl *info, + unsigned int pin) +{ + struct pinctrl_gpio_range *range = + pinctrl_find_gpio_range_from_pin(info->pctl, pin); + struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); + unsigned int reg, bit = 0; + + aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); + + return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0); +} + +static int aml_pinconf_enable_bias(struct aml_pinctrl *info, unsigned int pin, + bool pull_up) +{ + struct pinctrl_gpio_range *range = + pinctrl_find_gpio_range_from_pin(info->pctl, pin); + struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); + unsigned int reg, bit, val = 0; + int ret; + + aml_calc_reg_and_bit(range, pin, AML_REG_PULL, ®, &bit); + if (pull_up) + val = BIT(bit); + + ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), val); + if (ret) + return ret; + + aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, ®, &bit); + return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), BIT(bit)); +} + +static int aml_pinconf_set_drive_strength(struct aml_pinctrl *info, + unsigned int pin, + u16 drive_strength_ua) +{ + struct pinctrl_gpio_range *range = + pinctrl_find_gpio_range_from_pin(info->pctl, pin); + struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); + unsigned int reg, bit, ds_val; + + if (!bank->reg_ds) { + dev_err(info->dev, "drive-strength not supported\n"); + return -EOPNOTSUPP; + } + + aml_calc_reg_and_bit(range, pin, AML_REG_DS, ®, &bit); + + if (drive_strength_ua <= 500) { + ds_val = PINCONF_DRV_500UA; + } else if (drive_strength_ua <= 2500) { + ds_val = PINCONF_DRV_2500UA; + } else if (drive_strength_ua <= 3000) { + ds_val = PINCONF_DRV_3000UA; + } else if (drive_strength_ua <= 4000) { + ds_val = PINCONF_DRV_4000UA; + } else { + dev_warn_once(info->dev, + "pin %u: invalid drive-strength : %d , default to 4mA\n", + pin, drive_strength_ua); + ds_val = PINCONF_DRV_4000UA; + } + + return regmap_update_bits(bank->reg_ds, reg, 0x3 << bit, ds_val << bit); +} + +static int aml_pinconf_set_gpio_bit(struct aml_pinctrl *info, + unsigned int pin, + unsigned int reg_type, + bool arg) +{ + struct pinctrl_gpio_range *range = + pinctrl_find_gpio_range_from_pin(info->pctl, pin); + struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); + unsigned int reg, bit; + + aml_calc_reg_and_bit(range, pin, reg_type, ®, &bit); + return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), + arg ? BIT(bit) : 0); +} + +static int aml_pinconf_set_output(struct aml_pinctrl *info, + unsigned int pin, + bool out) +{ + return aml_pinconf_set_gpio_bit(info, pin, AML_REG_DIR, !out); +} + +static int aml_pinconf_set_drive(struct aml_pinctrl *info, + unsigned int pin, + bool high) +{ + return aml_pinconf_set_gpio_bit(info, pin, AML_REG_OUT, high); +} + +static int aml_pinconf_set_output_drive(struct aml_pinctrl *info, + unsigned int pin, + bool high) +{ + int ret; + + ret = aml_pinconf_set_output(info, pin, true); + if (ret) + return ret; + + return aml_pinconf_set_drive(info, pin, high); +} + +static int aml_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); + enum pin_config_param param; + unsigned int arg = 0; + int i, ret; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + + switch (param) { + case PIN_CONFIG_DRIVE_STRENGTH_UA: + case PIN_CONFIG_OUTPUT_ENABLE: + case PIN_CONFIG_OUTPUT: + arg = pinconf_to_config_argument(configs[i]); + break; + + default: + break; + } + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + ret = aml_pinconf_disable_bias(info, pin); + break; + case PIN_CONFIG_BIAS_PULL_UP: + ret = aml_pinconf_enable_bias(info, pin, true); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = aml_pinconf_enable_bias(info, pin, false); + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + ret = aml_pinconf_set_drive_strength(info, pin, arg); + break; + case PIN_CONFIG_OUTPUT_ENABLE: + ret = aml_pinconf_set_output(info, pin, arg); + break; + case PIN_CONFIG_OUTPUT: + ret = aml_pinconf_set_output_drive(info, pin, arg); + break; + default: + ret = -ENOTSUPP; + } + + if (ret) + return ret; + } + + return 0; +} + +static int aml_pinconf_group_set(struct pinctrl_dev *pcdev, + unsigned int num_group, + unsigned long *configs, + unsigned int num_configs) +{ + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev); + int i; + + for (i = 0; i < info->groups[num_group].npins; i++) { + aml_pinconf_set(pcdev, info->groups[num_group].pins[i], configs, + num_configs); + } + + return 0; +} + +static int aml_pinconf_group_get(struct pinctrl_dev *pcdev, + unsigned int group, unsigned long *config) +{ + return -EOPNOTSUPP; +} + +static const struct pinconf_ops aml_pinconf_ops = { + .pin_config_get = aml_pinconf_get, + .pin_config_set = aml_pinconf_set, + .pin_config_group_get = aml_pinconf_group_get, + .pin_config_group_set = aml_pinconf_group_set, + .is_generic = true, +}; + +static int aml_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->ngroups; +} + +static const char *aml_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + return info->groups[selector].name; +} + +static int aml_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, const unsigned int **pins, + unsigned int *npins) +{ + struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + + if (selector >= info->ngroups) + return -EINVAL; + + *pins = info->groups[selector].pins; + *npins = info->groups[selector].npins; + + return 0; +} + +static void aml_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, + unsigned int offset) +{ + seq_printf(s, " %s", dev_name(pcdev->dev)); +} + +static const struct pinctrl_ops aml_pctrl_ops = { + .get_groups_count = aml_get_groups_count, + .get_group_name = aml_get_group_name, + .get_group_pins = aml_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pinmux, + .dt_free_map = pinconf_generic_dt_free_map, + .pin_dbg_show = aml_pin_dbg_show, +}; + +static int aml_pctl_parse_functions(struct device_node *np, + struct aml_pinctrl *info, u32 index, + int *grp_index) +{ + struct device *dev = info->dev; + struct aml_pmx_func *func; + struct aml_pctl_group *grp; + int ret, i; + + func = &info->functions[index]; + func->name = np->name; + func->ngroups = of_get_child_count(np); + if (func->ngroups == 0) + return dev_err_probe(dev, -EINVAL, "No groups defined\n"); + + func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); + if (!func->groups) + return -ENOMEM; + + i = 0; + for_each_child_of_node_scoped(np, child) { + func->groups[i++] = child->name; + grp = &info->groups[*grp_index]; + grp->name = child->name; + *grp_index += 1; + ret = pinconf_generic_parse_dt_pinmux(child, dev, &grp->pins, + &grp->func, &grp->npins); + if (ret) { + dev_err(dev, "function :%s, groups:%s fail\n", func->name, child->name); + return ret; + } + } + dev_dbg(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups); + + return 0; +} + +static u32 aml_bank_pins(struct device_node *np) +{ + struct of_phandle_args of_args; + + if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, + 0, &of_args)) + return 0; + else + return of_args.args[2]; +} + +static int aml_bank_number(struct device_node *np) +{ + struct of_phandle_args of_args; + + if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, + 0, &of_args)) + return -EINVAL; + else + return of_args.args[1] >> 8; +} + +static unsigned int aml_count_pins(struct device_node *np) +{ + struct device_node *child; + unsigned int pins = 0; + + for_each_child_of_node(np, child) { + if (of_property_read_bool(child, "gpio-controller")) + pins += aml_bank_pins(child); + } + + return pins; +} + +/* + * A pinctrl device contains two types of nodes. The one named GPIO + * bank which includes gpio-controller property. The other one named + * function which includes one or more pin groups. The pin group + * include pinmux property(global index in pinctrl dev, and mux vlaue + * in mux reg) and pin configuration properties. + */ +static void aml_pctl_dt_child_count(struct aml_pinctrl *info, + struct device_node *np) +{ + struct device_node *child; + + for_each_child_of_node(np, child) { + if (of_property_read_bool(child, "gpio-controller")) { + info->nbanks++; + } else { + info->nfunctions++; + info->ngroups += of_get_child_count(child); + } + } +} + +static struct regmap *aml_map_resource(struct device *dev, unsigned int id, + struct device_node *node, char *name) +{ + struct resource res; + void __iomem *base; + int i; + + struct regmap_config aml_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + }; + + i = of_property_match_string(node, "reg-names", name); + if (i < 0) + return NULL; + if (of_address_to_resource(node, i, &res)) + return NULL; + base = devm_ioremap_resource(dev, &res); + if (IS_ERR(base)) + return ERR_CAST(base); + + aml_regmap_config.max_register = resource_size(&res) - 4; + aml_regmap_config.name = devm_kasprintf(dev, GFP_KERNEL, + "%s-%s", aml_bank_name[id], name); + if (!aml_regmap_config.name) + return ERR_PTR(-ENOMEM); + + return devm_regmap_init_mmio(dev, base, &aml_regmap_config); +} + +static inline int aml_gpio_calc_reg_and_bit(struct aml_gpio_bank *bank, + unsigned int reg_type, + unsigned int gpio, + unsigned int *reg, + unsigned int *bit) +{ + *bit = gpio * aml_bit_strides[reg_type] + bank->pc.bit_offset[reg_type]; + *reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4; + *bit &= 0x1f; + + return 0; +} + +static int aml_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) +{ + struct aml_gpio_bank *bank = gpiochip_get_data(chip); + unsigned int bit, reg, val; + int ret; + + aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); + + ret = regmap_read(bank->reg_gpio, reg, &val); + if (ret) + return ret; + + return BIT(bit) & val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; +} + +static int aml_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) +{ + struct aml_gpio_bank *bank = gpiochip_get_data(chip); + unsigned int bit, reg; + + aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); + + return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), BIT(bit)); +} + +static int aml_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, + int value) +{ + struct aml_gpio_bank *bank = gpiochip_get_data(chip); + unsigned int bit, reg; + int ret; + + aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, ®, &bit); + ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0); + if (ret < 0) + return ret; + + aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, ®, &bit); + + return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), + value ? BIT(bit) : 0); +} + +static int aml_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) +{ + struct aml_gpio_bank *bank = gpiochip_get_data(chip); + unsigned int bit, reg; + + aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, ®, &bit); + + return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), + value ? BIT(bit) : 0); +} + +static int aml_gpio_get(struct gpio_chip *chip, unsigned int gpio) +{ + struct aml_gpio_bank *bank = gpiochip_get_data(chip); + unsigned int reg, bit, val; + + aml_gpio_calc_reg_and_bit(bank, AML_REG_IN, gpio, ®, &bit); + regmap_read(bank->reg_gpio, reg, &val); + + return !!(val & BIT(bit)); +} + +static const struct gpio_chip aml_gpio_template = { + .request = gpiochip_generic_request, + .free = gpiochip_generic_free, + .set_config = gpiochip_generic_config, + .set_rv = aml_gpio_set, + .get = aml_gpio_get, + .direction_input = aml_gpio_direction_input, + .direction_output = aml_gpio_direction_output, + .get_direction = aml_gpio_get_direction, + .can_sleep = false, +}; + +static void init_bank_register_bit(struct aml_pinctrl *info, + struct aml_gpio_bank *bank) +{ + const struct aml_pctl_data *data = info->data; + const struct aml_reg_bit *aml_rb; + bool def_offs = true; + int i; + + if (data) { + for (i = 0; i < data->number; i++) { + aml_rb = &data->rb_offs[i]; + if (bank->bank_id == aml_rb->bank_id) { + def_offs = false; + break; + } + } + } + + if (def_offs) { + for (i = 0; i < AML_NUM_REG; i++) { + bank->pc.reg_offset[i] = aml_def_regoffs[i]; + bank->pc.bit_offset[i] = 0; + } + } else { + for (i = 0; i < AML_NUM_REG; i++) { + bank->pc.reg_offset[i] = aml_rb->reg_offs[i]; + bank->pc.bit_offset[i] = aml_rb->bit_offs[i]; + } + } +} + +static int aml_gpiolib_register_bank(struct aml_pinctrl *info, + int bank_nr, struct device_node *np) +{ + struct aml_gpio_bank *bank = &info->banks[bank_nr]; + struct device *dev = info->dev; + int ret = 0; + + ret = aml_bank_number(np); + if (ret < 0) { + dev_err(dev, "get num=%d bank identity fail\n", bank_nr); + return -EINVAL; + } + bank->bank_id = ret; + + bank->reg_mux = aml_map_resource(dev, bank->bank_id, np, "mux"); + if (IS_ERR_OR_NULL(bank->reg_mux)) { + if (bank->bank_id == AMLOGIC_GPIO_TEST_N || + bank->bank_id == AMLOGIC_GPIO_ANALOG) + bank->reg_mux = NULL; + else + return dev_err_probe(dev, bank->reg_mux ? PTR_ERR(bank->reg_mux) : -ENOENT, + "mux registers not found\n"); + } + + bank->reg_gpio = aml_map_resource(dev, bank->bank_id, np, "gpio"); + if (IS_ERR_OR_NULL(bank->reg_gpio)) + return dev_err_probe(dev, bank->reg_gpio ? PTR_ERR(bank->reg_gpio) : -ENOENT, + "gpio registers not found\n"); + + bank->reg_ds = aml_map_resource(dev, bank->bank_id, np, "ds"); + if (IS_ERR_OR_NULL(bank->reg_ds)) { + dev_dbg(info->dev, "ds registers not found - skipping\n"); + bank->reg_ds = bank->reg_gpio; + } + + bank->gpio_chip = aml_gpio_template; + bank->gpio_chip.base = -1; + bank->gpio_chip.ngpio = aml_bank_pins(np); + bank->gpio_chip.fwnode = of_fwnode_handle(np); + bank->gpio_chip.parent = dev; + + init_bank_register_bit(info, bank); + bank->gpio_chip.label = aml_bank_name[bank->bank_id]; + + bank->pin_base = bank->bank_id << 8; + + return 0; +} + +static int aml_pctl_probe_dt(struct platform_device *pdev, + struct pinctrl_desc *pctl_desc, + struct aml_pinctrl *info) +{ + struct device *dev = &pdev->dev; + struct pinctrl_pin_desc *pdesc; + struct device_node *np = dev->of_node; + int grp_index = 0; + int i = 0, j = 0, k = 0, bank; + int ret = 0; + + aml_pctl_dt_child_count(info, np); + if (!info->nbanks) + return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n"); + + dev_dbg(dev, "nbanks = %d\n", info->nbanks); + dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); + dev_dbg(dev, "ngroups = %d\n", info->ngroups); + + info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); + + info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); + + info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL); + + if (!info->functions || !info->groups || !info->banks) + return -ENOMEM; + + info->data = (struct aml_pctl_data *)of_device_get_match_data(dev); + + pctl_desc->npins = aml_count_pins(np); + + pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); + if (!pdesc) + return -ENOMEM; + + pctl_desc->pins = pdesc; + + bank = 0; + for_each_child_of_node_scoped(np, child) { + if (of_property_read_bool(child, "gpio-controller")) { + const char *bank_name = NULL; + char **pin_names; + + ret = aml_gpiolib_register_bank(info, bank, child); + if (ret) + return ret; + + k = info->banks[bank].pin_base; + bank_name = info->banks[bank].gpio_chip.label; + + pin_names = devm_kasprintf_strarray(dev, bank_name, + info->banks[bank].gpio_chip.ngpio); + if (IS_ERR(pin_names)) + return PTR_ERR(pin_names); + + for (j = 0; j < info->banks[bank].gpio_chip.ngpio; j++, k++) { + pdesc->number = k; + pdesc->name = pin_names[j]; + pdesc++; + } + bank++; + } else { + ret = aml_pctl_parse_functions(child, info, + i++, &grp_index); + if (ret) + return ret; + } + } + + return 0; +} + +static int aml_pctl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct aml_pinctrl *info; + struct pinctrl_desc *pctl_desc; + int ret, i; + + pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL); + if (!pctl_desc) + return -ENOMEM; + + info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + info->dev = dev; + platform_set_drvdata(pdev, info); + ret = aml_pctl_probe_dt(pdev, pctl_desc, info); + if (ret) + return ret; + + pctl_desc->owner = THIS_MODULE; + pctl_desc->pctlops = &aml_pctrl_ops; + pctl_desc->pmxops = &aml_pmx_ops; + pctl_desc->confops = &aml_pinconf_ops; + pctl_desc->name = dev_name(dev); + + info->pctl = devm_pinctrl_register(dev, pctl_desc, info); + if (IS_ERR(info->pctl)) + return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n"); + + for (i = 0; i < info->nbanks; i++) { + ret = gpiochip_add_data(&info->banks[i].gpio_chip, &info->banks[i]); + if (ret) + return dev_err_probe(dev, ret, "Failed to add gpiochip(%d)!\n", i); + } + + return 0; +} + +static const struct of_device_id aml_pctl_of_match[] = { + { .compatible = "amlogic,pinctrl-a4", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, aml_pctl_dt_match); + +static struct platform_driver aml_pctl_driver = { + .driver = { + .name = "amlogic-pinctrl", + .of_match_table = aml_pctl_of_match, + }, + .probe = aml_pctl_probe, +}; +module_platform_driver(aml_pctl_driver); + +MODULE_AUTHOR("Xianwei Zhao <xianwei.zhao@amlogic.com>"); +MODULE_DESCRIPTION("Pin controller and GPIO driver for Amlogic SoC"); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 253a0cc57e39..f5be61f2ede4 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -487,7 +487,7 @@ static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, case PIN_CONFIG_BIAS_PULL_DOWN: case PIN_CONFIG_BIAS_PULL_UP: if (meson_pinconf_get_pull(pc, pin) == param) - arg = 1; + arg = 60000; else return -EINVAL; break; @@ -580,9 +580,9 @@ static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, gpio, value); } -static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) +static int meson_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) { - meson_pinconf_set_drive(gpiochip_get_data(chip), gpio, value); + return meson_pinconf_set_drive(gpiochip_get_data(chip), gpio, value); } static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) @@ -616,7 +616,7 @@ static int meson_gpiolib_register(struct meson_pinctrl *pc) pc->chip.direction_input = meson_gpio_direction_input; pc->chip.direction_output = meson_gpio_direction_output; pc->chip.get = meson_gpio_get; - pc->chip.set = meson_gpio_set; + pc->chip.set_rv = meson_gpio_set; pc->chip.base = -1; pc->chip.ngpio = pc->data->num_pins; pc->chip.can_sleep = false; diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 335744ac8310..a6b106984e12 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -358,9 +358,7 @@ static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev, val = grp->val[func]; - regmap_update_bits(info->regmap, reg, mask, val); - - return 0; + return regmap_update_bits(info->regmap, reg, mask, val); } static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev, @@ -402,10 +400,13 @@ static int armada_37xx_gpio_get_direction(struct gpio_chip *chip, struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); unsigned int reg = OUTPUT_EN; unsigned int val, mask; + int ret; armada_37xx_update_reg(®, &offset); mask = BIT(offset); - regmap_read(info->regmap, reg, &val); + ret = regmap_read(info->regmap, reg, &val); + if (ret) + return ret; if (val & mask) return GPIO_LINE_DIRECTION_OUT; @@ -417,22 +418,22 @@ static int armada_37xx_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) { struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); - unsigned int reg = OUTPUT_EN; + unsigned int en_offset = offset; + unsigned int reg = OUTPUT_VAL; unsigned int mask, val, ret; armada_37xx_update_reg(®, &offset); mask = BIT(offset); + val = value ? mask : 0; - ret = regmap_update_bits(info->regmap, reg, mask, mask); - + ret = regmap_update_bits(info->regmap, reg, mask, val); if (ret) return ret; - reg = OUTPUT_VAL; - val = value ? mask : 0; - regmap_update_bits(info->regmap, reg, mask, val); + reg = OUTPUT_EN; + armada_37xx_update_reg(®, &en_offset); - return 0; + return regmap_update_bits(info->regmap, reg, mask, mask); } static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset) @@ -440,17 +441,20 @@ static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset) struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); unsigned int reg = INPUT_VAL; unsigned int val, mask; + int ret; armada_37xx_update_reg(®, &offset); mask = BIT(offset); - regmap_read(info->regmap, reg, &val); + ret = regmap_read(info->regmap, reg, &val); + if (ret) + return ret; return (val & mask) != 0; } -static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset, - int value) +static int armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) { struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); unsigned int reg = OUTPUT_VAL; @@ -460,7 +464,7 @@ static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset, mask = BIT(offset); val = value ? mask : 0; - regmap_update_bits(info->regmap, reg, mask, val); + return regmap_update_bits(info->regmap, reg, mask, val); } static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, @@ -469,16 +473,17 @@ static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, { struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); struct gpio_chip *chip = range->gc; + int ret; dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", offset, range->name, offset, input ? "input" : "output"); if (input) - armada_37xx_gpio_direction_input(chip, offset); + ret = armada_37xx_gpio_direction_input(chip, offset); else - armada_37xx_gpio_direction_output(chip, offset, 0); + ret = armada_37xx_gpio_direction_output(chip, offset, 0); - return 0; + return ret; } static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev, @@ -513,7 +518,7 @@ static const struct pinmux_ops armada_37xx_pmx_ops = { static const struct gpio_chip armada_37xx_gpiolib_chip = { .request = gpiochip_generic_request, .free = gpiochip_generic_free, - .set = armada_37xx_gpio_set, + .set_rv = armada_37xx_gpio_set, .get = armada_37xx_gpio_get, .get_direction = armada_37xx_gpio_get_direction, .direction_input = armada_37xx_gpio_direction_input, diff --git a/drivers/pinctrl/nomadik/Kconfig b/drivers/pinctrl/nomadik/Kconfig index aafecf348670..1b4fe2a4c302 100644 --- a/drivers/pinctrl/nomadik/Kconfig +++ b/drivers/pinctrl/nomadik/Kconfig @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -if ARCH_U8500 +if (ARCH_U8500 || COMPILE_TEST) config PINCTRL_ABX500 bool "ST-Ericsson ABx500 family Mixed Signal Circuit gpio functions" @@ -10,11 +10,11 @@ config PINCTRL_ABX500 config PINCTRL_AB8500 bool "AB8500 pin controller driver" - depends on PINCTRL_ABX500 && ARCH_U8500 + depends on PINCTRL_ABX500 && (ARCH_U8500 || COMPILE_TEST) config PINCTRL_AB8505 bool "AB8505 pin controller driver" - depends on PINCTRL_ABX500 && ARCH_U8500 + depends on PINCTRL_ABX500 && (ARCH_U8500 || COMPILE_TEST) endif diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c index 8cd4ba5cf0bd..2f55f83127cf 100644 --- a/drivers/pinctrl/nomadik/pinctrl-abx500.c +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c @@ -167,14 +167,10 @@ out: return bit; } -static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val) +static int abx500_gpio_set(struct gpio_chip *chip, unsigned int offset, + int val) { - struct abx500_pinctrl *pct = gpiochip_get_data(chip); - int ret; - - ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); - if (ret < 0) - dev_err(pct->dev, "%s write failed (%d)\n", __func__, ret); + return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); } static int abx500_gpio_direction_output(struct gpio_chip *chip, @@ -540,7 +536,7 @@ static const struct gpio_chip abx500gpio_chip = { .direction_input = abx500_gpio_direction_input, .get = abx500_gpio_get, .direction_output = abx500_gpio_direction_output, - .set = abx500_gpio_set, + .set_rv = abx500_gpio_set, .to_irq = abx500_gpio_to_irq, .dbg_show = abx500_gpio_dbg_show, }; diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35.c b/drivers/pinctrl/nuvoton/pinctrl-ma35.c index 59c4e7c6cdde..b51704bafd81 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-ma35.c +++ b/drivers/pinctrl/nuvoton/pinctrl-ma35.c @@ -98,12 +98,6 @@ static const u32 ds_3300mv_tbl[] = { 17100, 25600, 34100, 42800, 48000, 56000, 77000, 82000, }; -struct ma35_pin_func { - const char *name; - const char **groups; - u32 ngroups; -}; - struct ma35_pin_setting { u32 offset; u32 shift; @@ -112,13 +106,6 @@ struct ma35_pin_setting { unsigned int nconfigs; }; -struct ma35_pin_group { - const char *name; - unsigned int npins; - unsigned int *pins; - struct ma35_pin_setting *settings; -}; - struct ma35_pin_bank { void __iomem *reg_base; struct clk *clk; @@ -147,9 +134,9 @@ struct ma35_pinctrl { struct pinctrl_dev *pctl; const struct ma35_pinctrl_soc_info *info; struct regmap *regmap; - struct ma35_pin_group *groups; + struct group_desc *groups; unsigned int ngroups; - struct ma35_pin_func *functions; + struct pinfunction *functions; unsigned int nfunctions; }; @@ -166,7 +153,7 @@ static const char *ma35_get_group_name(struct pinctrl_dev *pctldev, unsigned int { struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev); - return npctl->groups[selector].name; + return npctl->groups[selector].grp.name; } static int ma35_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, @@ -177,19 +164,19 @@ static int ma35_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selecto if (selector >= npctl->ngroups) return -EINVAL; - *pins = npctl->groups[selector].pins; - *npins = npctl->groups[selector].npins; + *pins = npctl->groups[selector].grp.pins; + *npins = npctl->groups[selector].grp.npins; return 0; } -static struct ma35_pin_group *ma35_pinctrl_find_group_by_name( - const struct ma35_pinctrl *npctl, const char *name) +static struct group_desc * +ma35_pinctrl_find_group_by_name(const struct ma35_pinctrl *npctl, const char *name) { int i; for (i = 0; i < npctl->ngroups; i++) { - if (!strcmp(npctl->groups[i].name, name)) + if (!strcmp(npctl->groups[i].grp.name, name)) return &npctl->groups[i]; } return NULL; @@ -201,9 +188,10 @@ static int ma35_pinctrl_dt_node_to_map_func(struct pinctrl_dev *pctldev, unsigned int *num_maps) { struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev); - struct ma35_pin_group *grp; + struct ma35_pin_setting *setting; struct pinctrl_map *new_map; struct device_node *parent; + struct group_desc *grp; int map_num = 1; int i; @@ -217,7 +205,7 @@ static int ma35_pinctrl_dt_node_to_map_func(struct pinctrl_dev *pctldev, return -EINVAL; } - map_num += grp->npins; + map_num += grp->grp.npins; new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL); if (!new_map) return -ENOMEM; @@ -229,17 +217,19 @@ static int ma35_pinctrl_dt_node_to_map_func(struct pinctrl_dev *pctldev, if (!parent) return -EINVAL; + setting = grp->data; + new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; new_map[0].data.mux.function = parent->name; new_map[0].data.mux.group = np->name; of_node_put(parent); new_map++; - for (i = 0; i < grp->npins; i++) { + for (i = 0; i < grp->grp.npins; i++) { new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; - new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, grp->pins[i]); - new_map[i].data.configs.configs = grp->settings[i].configs; - new_map[i].data.configs.num_configs = grp->settings[i].nconfigs; + new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, grp->grp.pins[i]); + new_map[i].data.configs.configs = setting[i].configs; + new_map[i].data.configs.num_configs = setting[i].nconfigs; } dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", (*map)->data.mux.function, (*map)->data.mux.group, map_num); @@ -287,14 +277,14 @@ static int ma35_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int selecto unsigned int group) { struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev); - struct ma35_pin_group *grp = &npctl->groups[group]; - struct ma35_pin_setting *setting = grp->settings; + struct group_desc *grp = &npctl->groups[group]; + struct ma35_pin_setting *setting = grp->data; u32 i, regval; dev_dbg(npctl->dev, "enable function %s group %s\n", - npctl->functions[selector].name, npctl->groups[group].name); + npctl->functions[selector].name, grp->grp.name); - for (i = 0; i < grp->npins; i++) { + for (i = 0; i < grp->grp.npins; i++) { regmap_read(npctl->regmap, setting->offset, ®val); regval &= ~GENMASK(setting->shift + MA35_MFP_BITS_PER_PORT - 1, setting->shift); @@ -529,7 +519,6 @@ static int ma35_gpiolib_register(struct platform_device *pdev, struct ma35_pinct bank->irqtype = 0; bank->irqinten = 0; bank->chip.label = bank->name; - bank->chip.of_gpio_n_cells = 2; bank->chip.parent = &pdev->dev; bank->chip.request = ma35_gpio_core_to_request; bank->chip.direction_input = ma35_gpio_core_direction_in; @@ -986,22 +975,22 @@ static const struct pinconf_ops ma35_pinconf_ops = { .is_generic = true, }; -static int ma35_pinctrl_parse_groups(struct device_node *np, struct ma35_pin_group *grp, +static int ma35_pinctrl_parse_groups(struct fwnode_handle *fwnode, struct group_desc *grp, struct ma35_pinctrl *npctl, u32 index) { + struct device_node *np = to_of_node(fwnode); struct ma35_pin_setting *pin; unsigned long *configs; unsigned int nconfigs; + unsigned int *pins; int i, j, count, ret; u32 *elems; - grp->name = np->name; - ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &nconfigs); if (ret) return ret; - count = of_property_count_elems_of_size(np, "nuvoton,pins", sizeof(u32)); + count = fwnode_property_count_u32(fwnode, "nuvoton,pins"); if (!count || count % 3) return -EINVAL; @@ -1009,21 +998,22 @@ static int ma35_pinctrl_parse_groups(struct device_node *np, struct ma35_pin_gro if (!elems) return -ENOMEM; - ret = of_property_read_u32_array(np, "nuvoton,pins", elems, count); + grp->grp.name = np->name; + + ret = fwnode_property_read_u32_array(fwnode, "nuvoton,pins", elems, count); if (ret) return -EINVAL; + grp->grp.npins = count / 3; - grp->npins = count / 3; - - grp->pins = devm_kcalloc(npctl->dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL); - if (!grp->pins) + pins = devm_kcalloc(npctl->dev, grp->grp.npins, sizeof(*pins), GFP_KERNEL); + if (!pins) return -ENOMEM; + grp->grp.pins = pins; - grp->settings = devm_kcalloc(npctl->dev, grp->npins, sizeof(*grp->settings), GFP_KERNEL); - if (!grp->settings) + pin = devm_kcalloc(npctl->dev, grp->grp.npins, sizeof(*pin), GFP_KERNEL); + if (!pin) return -ENOMEM; - - pin = grp->settings; + grp->data = pin; for (i = 0, j = 0; i < count; i += 3, j++) { pin->offset = elems[i] * MA35_MFP_REG_SZ_PER_BANK + MA35_MFP_REG_BASE; @@ -1031,19 +1021,21 @@ static int ma35_pinctrl_parse_groups(struct device_node *np, struct ma35_pin_gro pin->muxval = elems[i + 2]; pin->configs = configs; pin->nconfigs = nconfigs; - grp->pins[j] = npctl->info->get_pin_num(pin->offset, pin->shift); + pins[j] = npctl->info->get_pin_num(pin->offset, pin->shift); pin++; } return 0; } -static int ma35_pinctrl_parse_functions(struct device_node *np, struct ma35_pinctrl *npctl, +static int ma35_pinctrl_parse_functions(struct fwnode_handle *fwnode, struct ma35_pinctrl *npctl, u32 index) { - struct device_node *child; - struct ma35_pin_func *func; - struct ma35_pin_group *grp; + struct device_node *np = to_of_node(fwnode); + struct fwnode_handle *child; + struct pinfunction *func; + struct group_desc *grp; static u32 grp_index; + const char **groups; u32 ret, i = 0; dev_dbg(npctl->dev, "parse function(%d): %s\n", index, np->name); @@ -1055,31 +1047,37 @@ static int ma35_pinctrl_parse_functions(struct device_node *np, struct ma35_pinc if (func->ngroups <= 0) return 0; - func->groups = devm_kcalloc(npctl->dev, func->ngroups, sizeof(char *), GFP_KERNEL); - if (!func->groups) + groups = devm_kcalloc(npctl->dev, func->ngroups, sizeof(*groups), GFP_KERNEL); + if (!groups) return -ENOMEM; - for_each_child_of_node(np, child) { - func->groups[i] = child->name; + fwnode_for_each_child_node(fwnode, child) { + struct device_node *node = to_of_node(child); + + groups[i] = node->name; grp = &npctl->groups[grp_index++]; ret = ma35_pinctrl_parse_groups(child, grp, npctl, i++); if (ret) { - of_node_put(child); + fwnode_handle_put(child); return ret; } } + + func->groups = groups; return 0; } static int ma35_pinctrl_probe_dt(struct platform_device *pdev, struct ma35_pinctrl *npctl) { + struct device *dev = &pdev->dev; struct fwnode_handle *child; u32 idx = 0; int ret; - device_for_each_child_node(&pdev->dev, child) { + device_for_each_child_node(dev, child) { if (fwnode_property_present(child, "gpio-controller")) continue; + npctl->nfunctions++; npctl->ngroups += of_get_child_count(to_of_node(child)); } @@ -1097,11 +1095,11 @@ static int ma35_pinctrl_probe_dt(struct platform_device *pdev, struct ma35_pinct if (!npctl->groups) return -ENOMEM; - device_for_each_child_node(&pdev->dev, child) { + device_for_each_child_node(dev, child) { if (fwnode_property_present(child, "gpio-controller")) continue; - ret = ma35_pinctrl_parse_functions(to_of_node(child), npctl, idx++); + ret = ma35_pinctrl_parse_functions(child, npctl, idx++); if (ret) { fwnode_handle_put(child); dev_err(&pdev->dev, "failed to parse function\n"); @@ -1146,7 +1144,7 @@ int ma35_pinctrl_probe(struct platform_device *pdev, const struct ma35_pinctrl_s npctl->info = info; npctl->dev = &pdev->dev; - npctl->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "nuvoton,sys"); + npctl->regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev), "nuvoton,sys"); if (IS_ERR(npctl->regmap)) return dev_err_probe(&pdev->dev, PTR_ERR(npctl->regmap), "No syscfg phandle specified\n"); diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35d1.c b/drivers/pinctrl/nuvoton/pinctrl-ma35d1.c index 8bb9a5a35954..eafa06ca0879 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-ma35d1.c +++ b/drivers/pinctrl/nuvoton/pinctrl-ma35d1.c @@ -9,7 +9,6 @@ #include <linux/io.h> #include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm.h> diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c index 62a46d824b46..dfd32feb3428 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -7,10 +7,8 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/mfd/syscon.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/property.h> #include <linux/regmap.h> @@ -504,17 +502,6 @@ static const int lkgpo2_pins[] = { 9 }; static const int nprd_smi_pins[] = { 190 }; -/* - * pin: name, number - * group: name, npins, pins - * function: name, ngroups, groups - */ -struct npcm7xx_group { - const char *name; - const unsigned int *pins; - int npins; -}; - #define NPCM7XX_GRPS \ NPCM7XX_GRP(smb0), \ NPCM7XX_GRP(smb0b), \ @@ -642,22 +629,14 @@ enum { #undef NPCM7XX_GRP }; -static struct npcm7xx_group npcm7xx_groups[] = { -#define NPCM7XX_GRP(x) { .name = #x, .pins = x ## _pins, \ - .npins = ARRAY_SIZE(x ## _pins) } +static struct pingroup npcm7xx_groups[] = { +#define NPCM7XX_GRP(x) PINCTRL_PINGROUP(#x, x ## _pins, ARRAY_SIZE(x ## _pins)) NPCM7XX_GRPS #undef NPCM7XX_GRP }; #define NPCM7XX_SFUNC(a) NPCM7XX_FUNC(a, #a) #define NPCM7XX_FUNC(a, b...) static const char *a ## _grp[] = { b } -#define NPCM7XX_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \ - .groups = nm ## _grp } -struct npcm7xx_func { - const char *name; - const unsigned int ngroups; - const char *const *groups; -}; NPCM7XX_SFUNC(smb0); NPCM7XX_SFUNC(smb0b); @@ -776,7 +755,8 @@ NPCM7XX_SFUNC(lkgpo2); NPCM7XX_SFUNC(nprd_smi); /* Function names */ -static struct npcm7xx_func npcm7xx_funcs[] = { +static struct pinfunction npcm7xx_funcs[] = { +#define NPCM7XX_MKFUNC(nm) PINCTRL_PINFUNCTION(#nm, nm ## _grp, ARRAY_SIZE(nm ## _grp)) NPCM7XX_MKFUNC(smb0), NPCM7XX_MKFUNC(smb0b), NPCM7XX_MKFUNC(smb0c), @@ -892,6 +872,7 @@ static struct npcm7xx_func npcm7xx_funcs[] = { NPCM7XX_MKFUNC(lkgpo1), NPCM7XX_MKFUNC(lkgpo2), NPCM7XX_MKFUNC(nprd_smi), +#undef NPCM7XX_MKFUNC }; #define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \ @@ -1849,22 +1830,13 @@ static struct pinctrl_desc npcm7xx_pinctrl_desc = { static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pctrl) { int ret = -ENXIO; - struct resource res; struct device *dev = pctrl->dev; struct fwnode_reference_args args; struct fwnode_handle *child; int id = 0; for_each_gpiochip_node(dev, child) { - struct device_node *np = to_of_node(child); - - ret = of_address_to_resource(np, 0, &res); - if (ret < 0) { - dev_err(dev, "Resource fail for GPIO bank %u\n", id); - return ret; - } - - pctrl->gpio_bank[id].base = ioremap(res.start, resource_size(&res)); + pctrl->gpio_bank[id].base = fwnode_iomap(child, 0); if (!pctrl->gpio_bank[id].base) return -EINVAL; @@ -1886,7 +1858,7 @@ static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pctrl) return ret; } - ret = irq_of_parse_and_map(np, 0); + ret = fwnode_irq_get(child, 0); if (!ret) { dev_err(dev, "No IRQ for GPIO bank %u\n", id); return -EINVAL; diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index f6a1e684a386..be3db8ab406c 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -587,17 +587,6 @@ static const int hgpio5_pins[] = { 25 }; static const int hgpio6_pins[] = { 59 }; static const int hgpio7_pins[] = { 60 }; -/* - * pin: name, number - * group: name, npins, pins - * function: name, ngroups, groups - */ -struct npcm8xx_pingroup { - const char *name; - const unsigned int *pins; - int npins; -}; - #define NPCM8XX_GRPS \ NPCM8XX_GRP(gpi36), \ NPCM8XX_GRP(gpi35), \ @@ -829,22 +818,14 @@ enum { #undef NPCM8XX_GRP }; -static struct npcm8xx_pingroup npcm8xx_pingroups[] = { -#define NPCM8XX_GRP(x) { .name = #x, .pins = x ## _pins, \ - .npins = ARRAY_SIZE(x ## _pins) } +static struct pingroup npcm8xx_pingroups[] = { +#define NPCM8XX_GRP(x) PINCTRL_PINGROUP(#x, x ## _pins, ARRAY_SIZE(x ## _pins)) NPCM8XX_GRPS #undef NPCM8XX_GRP }; #define NPCM8XX_SFUNC(a) NPCM8XX_FUNC(a, #a) #define NPCM8XX_FUNC(a, b...) static const char *a ## _grp[] = { b } -#define NPCM8XX_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \ - .groups = nm ## _grp } -struct npcm8xx_func { - const char *name; - const unsigned int ngroups; - const char *const *groups; -}; NPCM8XX_SFUNC(gpi36); NPCM8XX_SFUNC(gpi35); @@ -1067,7 +1048,8 @@ NPCM8XX_SFUNC(hgpio6); NPCM8XX_SFUNC(hgpio7); /* Function names */ -static struct npcm8xx_func npcm8xx_funcs[] = { +static struct pinfunction npcm8xx_funcs[] = { +#define NPCM8XX_MKFUNC(nm) PINCTRL_PINFUNCTION(#nm, nm ## _grp, ARRAY_SIZE(nm ## _grp)) NPCM8XX_MKFUNC(gpi36), NPCM8XX_MKFUNC(gpi35), NPCM8XX_MKFUNC(tp_jtag3), @@ -1287,6 +1269,7 @@ static struct npcm8xx_func npcm8xx_funcs[] = { NPCM8XX_MKFUNC(hgpio5), NPCM8XX_MKFUNC(hgpio6), NPCM8XX_MKFUNC(hgpio7), +#undef NPCM8XX_MKFUNC }; #define NPCM8XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q) \ @@ -2441,7 +2424,7 @@ static int npcm8xx_pinctrl_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pctrl); pctrl->gcr_regmap = - syscon_regmap_lookup_by_phandle(dev->of_node, "nuvoton,sysgcr"); + syscon_regmap_lookup_by_phandle(dev_of_node(dev), "nuvoton,sysgcr"); if (IS_ERR(pctrl->gcr_regmap)) return dev_err_probe(dev, PTR_ERR(pctrl->gcr_regmap), "Failed to find nuvoton,sysgcr property\n"); diff --git a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c index cdad4ef11a2f..4264ca749175 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c +++ b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c @@ -10,7 +10,6 @@ // block, shared between all GPIO banks #include <linux/device.h> -#include <linux/fwnode.h> #include <linux/gpio/driver.h> #include <linux/interrupt.h> #include <linux/irq.h> @@ -18,6 +17,7 @@ #include <linux/module.h> #include <linux/mod_devicetable.h> #include <linux/platform_device.h> +#include <linux/property.h> #include <linux/regmap.h> #include <linux/pinctrl/pinconf.h> @@ -482,13 +482,6 @@ static const struct pingroup wpcm450_groups[] = { #define WPCM450_SFUNC(a) WPCM450_FUNC(a, #a) #define WPCM450_FUNC(a, b...) static const char *a ## _grp[] = { b } -#define WPCM450_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \ - .groups = nm ## _grp } -struct wpcm450_func { - const char *name; - const unsigned int ngroups; - const char *const *groups; -}; WPCM450_SFUNC(smb3); WPCM450_SFUNC(smb4); @@ -555,7 +548,8 @@ WPCM450_FUNC(gpio, WPCM450_GRPS); #undef WPCM450_GRP /* Function names */ -static struct wpcm450_func wpcm450_funcs[] = { +static struct pinfunction wpcm450_funcs[] = { +#define WPCM450_MKFUNC(nm) PINCTRL_PINFUNCTION(#nm, nm ## _grp, ARRAY_SIZE(nm ## _grp)) WPCM450_MKFUNC(smb3), WPCM450_MKFUNC(smb4), WPCM450_MKFUNC(smb5), @@ -616,6 +610,7 @@ static struct wpcm450_func wpcm450_funcs[] = { WPCM450_MKFUNC(hg6), WPCM450_MKFUNC(hg7), WPCM450_MKFUNC(gpio), +#undef WPCM450_MKFUNC }; #define WPCM450_PINCFG(a, b, c, d, e, f, g) \ @@ -1033,7 +1028,7 @@ static int wpcm450_gpio_register(struct platform_device *pdev, return dev_err_probe(dev, PTR_ERR(pctrl->gpio_base), "Resource fail for GPIO controller\n"); - device_for_each_child_node(dev, child) { + for_each_gpiochip_node(dev, child) { void __iomem *dat = NULL; void __iomem *set = NULL; void __iomem *dirout = NULL; @@ -1044,9 +1039,6 @@ static int wpcm450_gpio_register(struct platform_device *pdev, u32 reg; int i; - if (!fwnode_property_read_bool(child, "gpio-controller")) - continue; - ret = fwnode_property_read_u32(child, "reg", ®); if (ret < 0) return ret; diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 42547f64453e..d67838afb085 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -234,6 +234,67 @@ static void parse_dt_cfg(struct device_node *np, } /** + * pinconf_generic_parse_dt_pinmux() + * parse the pinmux properties into generic pin mux values. + * @np: node containing the pinmux properties + * @dev: pincontrol core device + * @pid: array with pin identity entries + * @pmux: array with pin mux value entries + * @npins: number of pins + * + * pinmux propertity: mux value [0,7]bits and pin identity [8,31]bits. + */ +int pinconf_generic_parse_dt_pinmux(struct device_node *np, struct device *dev, + unsigned int **pid, unsigned int **pmux, + unsigned int *npins) +{ + unsigned int *pid_t; + unsigned int *pmux_t; + struct property *prop; + unsigned int npins_t, i; + u32 value; + int ret; + + prop = of_find_property(np, "pinmux", NULL); + if (!prop) { + dev_info(dev, "Missing pinmux property\n"); + return -ENOENT; + } + + if (!pid || !pmux || !npins) { + dev_err(dev, "parameters error\n"); + return -EINVAL; + } + + npins_t = prop->length / sizeof(u32); + pid_t = devm_kcalloc(dev, npins_t, sizeof(*pid_t), GFP_KERNEL); + pmux_t = devm_kcalloc(dev, npins_t, sizeof(*pmux_t), GFP_KERNEL); + if (!pid_t || !pmux_t) { + dev_err(dev, "kalloc memory fail\n"); + return -ENOMEM; + } + for (i = 0; i < npins_t; i++) { + ret = of_property_read_u32_index(np, "pinmux", i, &value); + if (ret) { + dev_err(dev, "get pinmux value fail\n"); + goto exit; + } + pmux_t[i] = value & 0xff; + pid_t[i] = (value >> 8) & 0xffffff; + } + *pid = pid_t; + *pmux = pmux_t; + *npins = npins_t; + + return 0; +exit: + devm_kfree(dev, pid_t); + devm_kfree(dev, pmux_t); + return ret; +} +EXPORT_SYMBOL_GPL(pinconf_generic_parse_dt_pinmux); + +/** * pinconf_generic_parse_dt_config() * parse the config properties into generic pinconfig values. * @np: node containing the pinconfig properties @@ -295,6 +356,75 @@ out: } EXPORT_SYMBOL_GPL(pinconf_generic_parse_dt_config); +int pinconf_generic_dt_node_to_map_pinmux(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + struct device *dev = pctldev->dev; + struct device_node *pnode; + unsigned long *configs = NULL; + unsigned int num_configs = 0; + struct property *prop; + unsigned int reserved_maps; + int reserve; + int ret; + + prop = of_find_property(np, "pinmux", NULL); + if (!prop) { + dev_info(dev, "Missing pinmux property\n"); + return -ENOENT; + } + + pnode = of_get_parent(np); + if (!pnode) { + dev_info(dev, "Missing function node\n"); + return -EINVAL; + } + + reserved_maps = 0; + *map = NULL; + *num_maps = 0; + + ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, + &num_configs); + if (ret < 0) { + dev_err(dev, "%pOF: could not parse node property\n", np); + return ret; + } + + reserve = 1; + if (num_configs) + reserve++; + + ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, + num_maps, reserve); + if (ret < 0) + goto exit; + + ret = pinctrl_utils_add_map_mux(pctldev, map, + &reserved_maps, num_maps, np->name, + pnode->name); + if (ret < 0) + goto exit; + + if (num_configs) { + ret = pinctrl_utils_add_map_configs(pctldev, map, &reserved_maps, + num_maps, np->name, configs, + num_configs, PIN_MAP_TYPE_CONFIGS_GROUP); + if (ret < 0) + goto exit; + } + +exit: + kfree(configs); + if (ret) + pinctrl_utils_free_map(pctldev, *map, *num_maps); + + return ret; +} +EXPORT_SYMBOL_GPL(pinconf_generic_dt_node_to_map_pinmux); + int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **map, unsigned int *reserved_maps, unsigned int *num_maps, diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h index a14c950bc700..e1ae71610526 100644 --- a/drivers/pinctrl/pinconf.h +++ b/drivers/pinctrl/pinconf.h @@ -138,4 +138,25 @@ int pinconf_generic_parse_dt_config(struct device_node *np, struct pinctrl_dev *pctldev, unsigned long **configs, unsigned int *nconfigs); + +int pinconf_generic_parse_dt_pinmux(struct device_node *np, struct device *dev, + unsigned int **pid, unsigned int **pmux, + unsigned int *npins); +#else +static inline int +pinconf_generic_parse_dt_config(struct device_node *np, + struct pinctrl_dev *pctldev, + unsigned long **configs, + unsigned int *nconfigs) +{ + return -ENOTSUPP; +} + +static inline int +pinconf_generic_parse_dt_pinmux(struct device_node *np, struct device *dev, + unsigned int **pid, unsigned int **pmux, + unsigned int *npins) +{ + return -ENOTSUPP; +} #endif diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 1d7fdcdec4c8..b3f0d02aeeb3 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -37,6 +37,10 @@ #include "pinctrl-utils.h" #include "pinctrl-amd.h" +#ifdef CONFIG_SUSPEND +static struct amd_gpio *pinctrl_dev; +#endif + static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) { unsigned long flags; @@ -101,7 +105,8 @@ static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) return !!(pin_reg & BIT(PIN_STS_OFF)); } -static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) +static int amd_gpio_set_value(struct gpio_chip *gc, unsigned int offset, + int value) { u32 pin_reg; unsigned long flags; @@ -115,6 +120,8 @@ static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) pin_reg &= ~BIT(OUTPUT_VALUE_OFF); writel(pin_reg, gpio_dev->base + offset * 4); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); + + return 0; } static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset, @@ -890,6 +897,44 @@ static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) } } +#if defined(CONFIG_SUSPEND) && defined(CONFIG_ACPI) +static void amd_gpio_check_pending(void) +{ + struct amd_gpio *gpio_dev = pinctrl_dev; + struct pinctrl_desc *desc = gpio_dev->pctrl->desc; + int i; + + if (!pm_debug_messages_on) + return; + + for (i = 0; i < desc->npins; i++) { + int pin = desc->pins[i].number; + u32 tmp; + + tmp = readl(gpio_dev->base + pin * 4); + if (tmp & PIN_IRQ_PENDING) + pm_pr_dbg("%s: GPIO %d is active: 0x%x.\n", __func__, pin, tmp); + } +} + +static struct acpi_s2idle_dev_ops pinctrl_amd_s2idle_dev_ops = { + .check = amd_gpio_check_pending, +}; + +static void amd_gpio_register_s2idle_ops(void) +{ + acpi_register_lps0_dev(&pinctrl_amd_s2idle_dev_ops); +} + +static void amd_gpio_unregister_s2idle_ops(void) +{ + acpi_unregister_lps0_dev(&pinctrl_amd_s2idle_dev_ops); +} +#else +static inline void amd_gpio_register_s2idle_ops(void) {} +static inline void amd_gpio_unregister_s2idle_ops(void) {} +#endif + #ifdef CONFIG_PM_SLEEP static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) { @@ -934,6 +979,17 @@ static int amd_gpio_suspend_hibernate_common(struct device *dev, bool is_suspend pin, is_suspend ? "suspend" : "hibernate"); } + /* + * debounce enabled over suspend has shown issues with a GPIO + * being unable to wake the system, as we're only interested in + * the actual wakeup event, clear it. + */ + if (gpio_dev->saved_regs[i] & (DB_CNTRl_MASK << DB_CNTRL_OFF)) { + amd_gpio_set_debounce(gpio_dev, pin, 0); + pm_pr_dbg("Clearing debounce for GPIO #%d during %s.\n", + pin, is_suspend ? "suspend" : "hibernate"); + } + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); } @@ -942,6 +998,9 @@ static int amd_gpio_suspend_hibernate_common(struct device *dev, bool is_suspend static int amd_gpio_suspend(struct device *dev) { +#ifdef CONFIG_SUSPEND + pinctrl_dev = dev_get_drvdata(dev); +#endif return amd_gpio_suspend_hibernate_common(dev, true); } @@ -1115,7 +1174,7 @@ static int amd_gpio_probe(struct platform_device *pdev) if (gpio_dev->irq < 0) return gpio_dev->irq; -#ifdef CONFIG_PM_SLEEP +#ifdef CONFIG_SUSPEND gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, sizeof(*gpio_dev->saved_regs), GFP_KERNEL); @@ -1128,7 +1187,7 @@ static int amd_gpio_probe(struct platform_device *pdev) gpio_dev->gc.direction_input = amd_gpio_direction_input; gpio_dev->gc.direction_output = amd_gpio_direction_output; gpio_dev->gc.get = amd_gpio_get_value; - gpio_dev->gc.set = amd_gpio_set_value; + gpio_dev->gc.set_rv = amd_gpio_set_value; gpio_dev->gc.set_config = amd_gpio_set_config; gpio_dev->gc.dbg_show = amd_gpio_dbg_show; @@ -1181,6 +1240,7 @@ static int amd_gpio_probe(struct platform_device *pdev) platform_set_drvdata(pdev, gpio_dev); acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev); + amd_gpio_register_s2idle_ops(); dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); return ret; @@ -1199,6 +1259,7 @@ static void amd_gpio_remove(struct platform_device *pdev) gpiochip_remove(&gpio_dev->gc); acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev); + amd_gpio_unregister_s2idle_ops(); } #ifdef CONFIG_ACPI diff --git a/drivers/pinctrl/pinctrl-amdisp.c b/drivers/pinctrl/pinctrl-amdisp.c new file mode 100644 index 000000000000..9256ed67bb20 --- /dev/null +++ b/drivers/pinctrl/pinctrl-amdisp.c @@ -0,0 +1,231 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * AMD ISP Pinctrl Driver + * + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + */ + +#include <linux/gpio/driver.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +#include "pinctrl-amdisp.h" + +#define DRV_NAME "amdisp-pinctrl" +#define GPIO_CONTROL_PIN 4 +#define GPIO_OFFSET_0 0x0 +#define GPIO_OFFSET_1 0x4 +#define GPIO_OFFSET_2 0x50 + +static const u32 gpio_offset[] = { + GPIO_OFFSET_0, + GPIO_OFFSET_1, + GPIO_OFFSET_2 +}; + +struct amdisp_pinctrl_data { + const struct pinctrl_pin_desc *pins; + unsigned int npins; + const struct amdisp_function *functions; + unsigned int nfunctions; + const struct amdisp_pingroup *groups; + unsigned int ngroups; +}; + +static const struct amdisp_pinctrl_data amdisp_pinctrl_data = { + .pins = amdisp_pins, + .npins = ARRAY_SIZE(amdisp_pins), + .functions = amdisp_functions, + .nfunctions = ARRAY_SIZE(amdisp_functions), + .groups = amdisp_groups, + .ngroups = ARRAY_SIZE(amdisp_groups), +}; + +struct amdisp_pinctrl { + struct device *dev; + struct pinctrl_dev *pctrl; + struct pinctrl_desc desc; + struct pinctrl_gpio_range gpio_range; + struct gpio_chip gc; + const struct amdisp_pinctrl_data *data; + void __iomem *gpiobase; + raw_spinlock_t lock; +}; + +static int amdisp_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct amdisp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->ngroups; +} + +static const char *amdisp_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group) +{ + struct amdisp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->groups[group].name; +} + +static int amdisp_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct amdisp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *pins = pctrl->data->groups[group].pins; + *num_pins = pctrl->data->groups[group].npins; + return 0; +} + +const struct pinctrl_ops amdisp_pinctrl_ops = { + .get_groups_count = amdisp_get_groups_count, + .get_group_name = amdisp_get_group_name, + .get_group_pins = amdisp_get_group_pins, +}; + +static int amdisp_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio) +{ + /* amdisp gpio only has output mode */ + return GPIO_LINE_DIRECTION_OUT; +} + +static int amdisp_gpio_direction_input(struct gpio_chip *gc, unsigned int gpio) +{ + return -EOPNOTSUPP; +} + +static int amdisp_gpio_direction_output(struct gpio_chip *gc, unsigned int gpio, + int value) +{ + /* Nothing to do, amdisp gpio only has output mode */ + return 0; +} + +static int amdisp_gpio_get(struct gpio_chip *gc, unsigned int gpio) +{ + unsigned long flags; + u32 pin_reg; + struct amdisp_pinctrl *pctrl = gpiochip_get_data(gc); + + raw_spin_lock_irqsave(&pctrl->lock, flags); + pin_reg = readl(pctrl->gpiobase + gpio_offset[gpio]); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + return !!(pin_reg & BIT(GPIO_CONTROL_PIN)); +} + +static void amdisp_gpio_set(struct gpio_chip *gc, unsigned int gpio, int value) +{ + unsigned long flags; + u32 pin_reg; + struct amdisp_pinctrl *pctrl = gpiochip_get_data(gc); + + raw_spin_lock_irqsave(&pctrl->lock, flags); + pin_reg = readl(pctrl->gpiobase + gpio_offset[gpio]); + if (value) + pin_reg |= BIT(GPIO_CONTROL_PIN); + else + pin_reg &= ~BIT(GPIO_CONTROL_PIN); + writel(pin_reg, pctrl->gpiobase + gpio_offset[gpio]); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static int amdisp_gpiochip_add(struct platform_device *pdev, + struct amdisp_pinctrl *pctrl) +{ + struct gpio_chip *gc = &pctrl->gc; + struct pinctrl_gpio_range *grange = &pctrl->gpio_range; + int ret; + + gc->label = dev_name(pctrl->dev); + gc->parent = &pdev->dev; + gc->names = amdisp_range_pins_name; + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; + gc->get_direction = amdisp_gpio_get_direction; + gc->direction_input = amdisp_gpio_direction_input; + gc->direction_output = amdisp_gpio_direction_output; + gc->get = amdisp_gpio_get; + gc->set = amdisp_gpio_set; + gc->base = -1; + gc->ngpio = ARRAY_SIZE(amdisp_range_pins); + + grange->id = 0; + grange->pin_base = 0; + grange->base = 0; + grange->pins = amdisp_range_pins; + grange->npins = ARRAY_SIZE(amdisp_range_pins); + grange->name = gc->label; + grange->gc = gc; + + ret = devm_gpiochip_add_data(&pdev->dev, gc, pctrl); + if (ret) + return ret; + + pinctrl_add_gpio_range(pctrl->pctrl, grange); + + return 0; +} + +static int amdisp_pinctrl_probe(struct platform_device *pdev) +{ + struct amdisp_pinctrl *pctrl; + struct resource *res; + int ret; + + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pdev->dev.init_name = DRV_NAME; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + pctrl->gpiobase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pctrl->gpiobase)) + return PTR_ERR(pctrl->gpiobase); + + platform_set_drvdata(pdev, pctrl); + + pctrl->dev = &pdev->dev; + pctrl->data = &amdisp_pinctrl_data; + pctrl->desc.owner = THIS_MODULE; + pctrl->desc.pctlops = &amdisp_pinctrl_ops; + pctrl->desc.pmxops = NULL; + pctrl->desc.name = dev_name(&pdev->dev); + pctrl->desc.pins = pctrl->data->pins; + pctrl->desc.npins = pctrl->data->npins; + ret = devm_pinctrl_register_and_init(&pdev->dev, &pctrl->desc, + pctrl, &pctrl->pctrl); + if (ret) + return ret; + + ret = pinctrl_enable(pctrl->pctrl); + if (ret) + return ret; + + ret = amdisp_gpiochip_add(pdev, pctrl); + if (ret) + return ret; + + return 0; +} + +static struct platform_driver amdisp_pinctrl_driver = { + .driver = { + .name = DRV_NAME, + }, + .probe = amdisp_pinctrl_probe, +}; +module_platform_driver(amdisp_pinctrl_driver); + +MODULE_AUTHOR("Benjamin Chan <benjamin.chan@amd.com>"); +MODULE_AUTHOR("Pratap Nirujogi <pratap.nirujogi@amd.com>"); +MODULE_DESCRIPTION("AMDISP pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRV_NAME); diff --git a/drivers/pinctrl/pinctrl-amdisp.h b/drivers/pinctrl/pinctrl-amdisp.h new file mode 100644 index 000000000000..9e3597a03227 --- /dev/null +++ b/drivers/pinctrl/pinctrl-amdisp.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * AMD ISP Pinctrl Driver + * + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + */ + +static const struct pinctrl_pin_desc amdisp_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), /* sensor0 control */ + PINCTRL_PIN(1, "GPIO_1"), /* sensor1 control */ + PINCTRL_PIN(2, "GPIO_2"), /* sensor2 control */ +}; + +#define AMDISP_GPIO_PINS(pin) \ +static const unsigned int gpio##pin##_pins[] = { pin } +AMDISP_GPIO_PINS(0); +AMDISP_GPIO_PINS(1); +AMDISP_GPIO_PINS(2); + +static const unsigned int amdisp_range_pins[] = { + 0, 1, 2 +}; + +static const char * const amdisp_range_pins_name[] = { + "gpio0", "gpio1", "gpio2" +}; + +enum amdisp_functions { + mux_gpio, + mux_NA +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2" +}; + +/** + * struct amdisp_function - a pinmux function + * @name: Name of the pinmux function. + * @groups: List of pingroups for this function. + * @ngroups: Number of entries in @groups. + */ +struct amdisp_function { + const char *name; + const char * const *groups; + unsigned int ngroups; +}; + +#define FUNCTION(fname) \ + [mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +static const struct amdisp_function amdisp_functions[] = { + FUNCTION(gpio), +}; + +/** + * struct amdisp_pingroup - a pinmux group + * @name: Name of the pinmux group. + * @pins: List of pins for this group. + * @npins: Number of entries in @pins. + * @funcs: List of functions belongs to this group. + * @nfuncs: Number of entries in @funcs. + * @offset: Group offset in amdisp pinmux groups. + */ +struct amdisp_pingroup { + const char *name; + const unsigned int *pins; + unsigned int npins; + unsigned int *funcs; + unsigned int nfuncs; + unsigned int offset; +}; + +#define PINGROUP(id, f0) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + mux_##f0, \ + }, \ + .nfuncs = 1, \ + .offset = id, \ + } + +static const struct amdisp_pingroup amdisp_groups[] = { + PINGROUP(0, gpio), + PINGROUP(1, gpio), + PINGROUP(2, gpio), +}; diff --git a/drivers/pinctrl/pinctrl-apple-gpio.c b/drivers/pinctrl/pinctrl-apple-gpio.c index f861e63f4115..0f551d67d482 100644 --- a/drivers/pinctrl/pinctrl-apple-gpio.c +++ b/drivers/pinctrl/pinctrl-apple-gpio.c @@ -66,7 +66,7 @@ struct apple_gpio_pinctrl { #define REG_GPIOx_DRIVE_STRENGTH1 GENMASK(23, 22) #define REG_IRQ(g, x) (0x800 + 0x40 * (g) + 4 * ((x) >> 5)) -struct regmap_config regmap_config = { +static const struct regmap_config regmap_config = { .reg_bits = 32, .val_bits = 32, .reg_stride = 4, @@ -79,13 +79,13 @@ struct regmap_config regmap_config = { /* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */ static void apple_gpio_set_reg(struct apple_gpio_pinctrl *pctl, - unsigned int pin, u32 mask, u32 value) + unsigned int pin, u32 mask, u32 value) { regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value); } static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl, - unsigned int pin) + unsigned int pin) { int ret; u32 val; @@ -100,9 +100,9 @@ static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl, /* Pin controller functions */ static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *node, - struct pinctrl_map **map, - unsigned *num_maps) + struct device_node *node, + struct pinctrl_map **map, + unsigned *num_maps) { unsigned reserved_maps; struct apple_gpio_pinctrl *pctl; @@ -147,8 +147,8 @@ static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev, group_name = pinctrl_generic_get_group_name(pctldev, pin); function_name = pinmux_generic_get_function_name(pctl->pctldev, func); ret = pinctrl_utils_add_map_mux(pctl->pctldev, map, - &reserved_maps, num_maps, - group_name, function_name); + &reserved_maps, num_maps, + group_name, function_name); if (ret) goto free_map; } @@ -171,7 +171,7 @@ static const struct pinctrl_ops apple_gpio_pinctrl_ops = { /* Pin multiplexer functions */ static int apple_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned func, - unsigned group) + unsigned group) { struct apple_gpio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); @@ -237,7 +237,7 @@ static int apple_gpio_direction_input(struct gpio_chip *chip, unsigned int offse } static int apple_gpio_direction_output(struct gpio_chip *chip, - unsigned int offset, int value) + unsigned int offset, int value) { struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); @@ -282,7 +282,7 @@ static void apple_gpio_irq_mask(struct irq_data *data) struct apple_gpio_pinctrl *pctl = gpiochip_get_data(gc); apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE, - FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF)); + FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF)); gpiochip_disable_irq(gc, data->hwirq); } @@ -294,7 +294,7 @@ static void apple_gpio_irq_unmask(struct irq_data *data) gpiochip_enable_irq(gc, data->hwirq); apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE, - FIELD_PREP(REG_GPIOx_MODE, irqtype)); + FIELD_PREP(REG_GPIOx_MODE, irqtype)); } static unsigned int apple_gpio_irq_startup(struct irq_data *data) @@ -303,7 +303,7 @@ static unsigned int apple_gpio_irq_startup(struct irq_data *data) struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip); apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_GRP, - FIELD_PREP(REG_GPIOx_GRP, 0)); + FIELD_PREP(REG_GPIOx_GRP, 0)); apple_gpio_direction_input(chip, data->hwirq); apple_gpio_irq_unmask(data); @@ -320,7 +320,7 @@ static int apple_gpio_irq_set_type(struct irq_data *data, unsigned int type) return -EINVAL; apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE, - FIELD_PREP(REG_GPIOx_MODE, irqtype)); + FIELD_PREP(REG_GPIOx_MODE, irqtype)); if (type & IRQ_TYPE_LEVEL_MASK) irq_set_handler_locked(data, handle_level_irq); @@ -429,7 +429,7 @@ static int apple_gpio_pinctrl_probe(struct platform_device *pdev) unsigned int npins; const char **pin_names; unsigned int *pin_nums; - static const char* pinmux_functions[] = { + static const char *pinmux_functions[] = { "gpio", "periph1", "periph2", "periph3" }; unsigned int i, nirqs = 0; diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 8b01d312305a..ca8a54a43ff5 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -390,7 +390,7 @@ static int atmel_gpio_direction_output(struct gpio_chip *chip, return 0; } -static void atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) +static int atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) { struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); struct atmel_pin *pin = atmel_pioctrl->pins[offset]; @@ -398,10 +398,12 @@ static void atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) atmel_gpio_write(atmel_pioctrl, pin->bank, val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, BIT(pin->line)); + + return 0; } -static void atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, - unsigned long *bits) +static int atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, + unsigned long *bits) { struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); unsigned int bank; @@ -431,6 +433,8 @@ static void atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, bits[word] >>= ATMEL_PIO_NPINS_PER_BANK; #endif } + + return 0; } static struct gpio_chip atmel_gpio_chip = { @@ -438,8 +442,8 @@ static struct gpio_chip atmel_gpio_chip = { .get = atmel_gpio_get, .get_multiple = atmel_gpio_get_multiple, .direction_output = atmel_gpio_direction_output, - .set = atmel_gpio_set, - .set_multiple = atmel_gpio_set_multiple, + .set_rv = atmel_gpio_set, + .set_multiple_rv = atmel_gpio_set_multiple, .to_irq = atmel_gpio_to_irq, .base = 0, }; @@ -609,8 +613,10 @@ static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, if (ret) goto exit; - pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps, + ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps, group, func); + if (ret) + goto exit; if (num_configs) { ret = pinctrl_utils_add_map_configs(pctldev, map, @@ -1206,7 +1212,7 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) dev_dbg(dev, "bank %i: irq=%d\n", i, ret); } - atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node, + atmel_pioctrl->irq_domain = irq_domain_create_linear(of_fwnode_handle(dev->of_node), atmel_pioctrl->gpio_chip->ngpio, &irq_domain_simple_ops, NULL); if (!atmel_pioctrl->irq_domain) diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 93ab277d9943..6c2727bd55bc 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1449,18 +1449,19 @@ static int at91_gpio_get(struct gpio_chip *chip, unsigned offset) return (pdsr & mask) != 0; } -static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, - int val) +static int at91_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) { struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); void __iomem *pio = at91_gpio->regbase; unsigned mask = 1 << offset; writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); + + return 0; } -static void at91_gpio_set_multiple(struct gpio_chip *chip, - unsigned long *mask, unsigned long *bits) +static int at91_gpio_set_multiple(struct gpio_chip *chip, + unsigned long *mask, unsigned long *bits) { struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); void __iomem *pio = at91_gpio->regbase; @@ -1472,6 +1473,8 @@ static void at91_gpio_set_multiple(struct gpio_chip *chip, writel_relaxed(set_mask, pio + PIO_SODR); writel_relaxed(clear_mask, pio + PIO_CODR); + + return 0; } static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, @@ -1798,8 +1801,8 @@ static const struct gpio_chip at91_gpio_template = { .direction_input = at91_gpio_direction_input, .get = at91_gpio_get, .direction_output = at91_gpio_direction_output, - .set = at91_gpio_set, - .set_multiple = at91_gpio_set_multiple, + .set_rv = at91_gpio_set, + .set_multiple_rv = at91_gpio_set_multiple, .dbg_show = at91_gpio_dbg_show, .can_sleep = false, .ngpio = MAX_NB_GPIO_PER_BANK, @@ -1819,12 +1822,16 @@ static int at91_gpio_probe(struct platform_device *pdev) struct at91_gpio_chip *at91_chip = NULL; struct gpio_chip *chip; struct pinctrl_gpio_range *range; + int alias_idx; int ret = 0; int irq, i; - int alias_idx = of_alias_get_id(np, "gpio"); uint32_t ngpio; char **names; + alias_idx = of_alias_get_id(np, "gpio"); + if (alias_idx < 0) + return alias_idx; + BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); if (gpio_chips[alias_idx]) return dev_err_probe(dev, -EBUSY, "%d slot is occupied.\n", alias_idx); diff --git a/drivers/pinctrl/pinctrl-aw9523.c b/drivers/pinctrl/pinctrl-aw9523.c index 9bf53de20be8..04afb344e9e5 100644 --- a/drivers/pinctrl/pinctrl-aw9523.c +++ b/drivers/pinctrl/pinctrl-aw9523.c @@ -784,7 +784,7 @@ static int aw9523_init_gpiochip(struct aw9523 *awi, unsigned int npins) gc->set_config = gpiochip_generic_config; gc->parent = dev; gc->owner = THIS_MODULE; - gc->can_sleep = false; + gc->can_sleep = true; return 0; } diff --git a/drivers/pinctrl/pinctrl-axp209.c b/drivers/pinctrl/pinctrl-axp209.c index 2b4805e74eed..fff408b60c4a 100644 --- a/drivers/pinctrl/pinctrl-axp209.c +++ b/drivers/pinctrl/pinctrl-axp209.c @@ -192,34 +192,30 @@ static int axp20x_gpio_get_direction(struct gpio_chip *chip, static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset, int value) { - chip->set(chip, offset, value); - - return 0; + return chip->set_rv(chip, offset, value); } -static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset, - int value) +static int axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) { struct axp20x_pctl *pctl = gpiochip_get_data(chip); int reg; /* AXP209 has GPIO3 status sharing the settings register */ - if (offset == 3) { - regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL, - AXP20X_GPIO3_FUNCTIONS, - value ? AXP20X_GPIO3_FUNCTION_OUT_HIGH : - AXP20X_GPIO3_FUNCTION_OUT_LOW); - return; - } + if (offset == 3) + return regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL, + AXP20X_GPIO3_FUNCTIONS, + value ? + AXP20X_GPIO3_FUNCTION_OUT_HIGH : + AXP20X_GPIO3_FUNCTION_OUT_LOW); reg = axp20x_gpio_get_reg(offset); if (reg < 0) - return; + return reg; - regmap_update_bits(pctl->regmap, reg, - AXP20X_GPIO_FUNCTIONS, - value ? AXP20X_GPIO_FUNCTION_OUT_HIGH : - AXP20X_GPIO_FUNCTION_OUT_LOW); + return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS, + value ? AXP20X_GPIO_FUNCTION_OUT_HIGH : + AXP20X_GPIO_FUNCTION_OUT_LOW); } static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset, @@ -229,12 +225,11 @@ static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset, int reg; /* AXP209 GPIO3 settings have a different layout */ - if (offset == 3) { + if (offset == 3) return regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL, AXP20X_GPIO3_FUNCTIONS, config == AXP20X_MUX_GPIO_OUT ? AXP20X_GPIO3_FUNCTION_OUT_LOW : AXP20X_GPIO3_FUNCTION_INPUT); - } reg = axp20x_gpio_get_reg(offset); if (reg < 0) @@ -468,7 +463,7 @@ static int axp20x_pctl_probe(struct platform_device *pdev) pctl->chip.owner = THIS_MODULE; pctl->chip.get = axp20x_gpio_get; pctl->chip.get_direction = axp20x_gpio_get_direction; - pctl->chip.set = axp20x_gpio_set; + pctl->chip.set_rv = axp20x_gpio_set; pctl->chip.direction_input = pinctrl_gpio_direction_input; pctl->chip.direction_output = axp20x_gpio_output; diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index d73004b4a45e..8a2fd632bdd4 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -40,6 +40,7 @@ /* Port Select configures the port */ #define CY8C95X0_PORTSEL 0x18 + /* Port settings, write PORTSEL first */ #define CY8C95X0_INTMASK 0x19 #define CY8C95X0_SELPWM 0x1A @@ -53,6 +54,9 @@ #define CY8C95X0_DRV_PP_FAST 0x21 #define CY8C95X0_DRV_PP_SLOW 0x22 #define CY8C95X0_DRV_HIZ 0x23 + +/* Internal device configuration */ +#define CY8C95X0_ENABLE_WDE 0x2D #define CY8C95X0_DEVID 0x2E #define CY8C95X0_WATCHDOG 0x2F #define CY8C95X0_COMMAND 0x30 @@ -137,7 +141,7 @@ static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = { * @irq_trig_low: I/O bits affected by a low voltage level * @irq_trig_high: I/O bits affected by a high voltage level * @push_pull: I/O bits configured as push pull driver - * @shiftmask: Mask used to compensate for Gport2 width + * @map: Mask used to compensate for Gport2 width * @nport: Number of Gports in this chip * @gpio_chip: gpiolib chip * @driver_data: private driver data @@ -158,7 +162,7 @@ struct cy8c95x0_pinctrl { DECLARE_BITMAP(irq_trig_low, MAX_LINE); DECLARE_BITMAP(irq_trig_high, MAX_LINE); DECLARE_BITMAP(push_pull, MAX_LINE); - DECLARE_BITMAP(shiftmask, MAX_LINE); + DECLARE_BITMAP(map, MAX_LINE); unsigned int nport; struct gpio_chip gpio_chip; unsigned long driver_data; @@ -310,9 +314,6 @@ static const char * const cy8c95x0_groups[] = { "gp77", }; -static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, - unsigned int pin, bool input); - static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin) { /* Account for GPORT2 which only has 4 bits */ @@ -477,20 +478,14 @@ static const struct regmap_config cy8c9520_i2c_regmap = { #endif }; -static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip, - unsigned int reg, - unsigned int port, - unsigned int mask, - unsigned int val, - bool *change, bool async, - bool force) +/* Caller should never modify PORTSEL directly */ +static int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip, + unsigned int reg, unsigned int port, + unsigned int mask, unsigned int val, + bool *change, bool async, bool force) { int ret, off, i; - /* Caller should never modify PORTSEL directly */ - if (reg == CY8C95X0_PORTSEL) - return -EINVAL; - /* Registers behind the PORTSEL mux have their own range in regmap */ if (cy8c95x0_muxed_register(reg)) { off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port); @@ -507,7 +502,8 @@ static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip if (ret < 0) return ret; - /* Mimic what hardware does and update the cache when a WC bit is written. + /* + * Mimic what hardware does and update the cache when a WC bit is written. * Allows to mark the registers as non-volatile and reduces I/O cycles. */ if (cy8c95x0_wc_register(reg) && (mask & val)) { @@ -523,7 +519,7 @@ static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip regcache_cache_only(chip->regmap, false); } - return ret; + return 0; } /** @@ -575,12 +571,13 @@ static int cy8c95x0_regmap_update_bits(struct cy8c95x0_pinctrl *chip, unsigned i } /** - * cy8c95x0_regmap_read() - reads a register using the regmap cache + * cy8c95x0_regmap_read_bits() - reads a register using the regmap cache * @chip: The pinctrl to work on * @reg: The register to read from. Can be direct access or muxed register. * @port: The port to be used for muxed registers or quick path direct access * registers. Otherwise unused. - * @read_val: Value read from hardware or cache + * @mask: Bitmask to apply + * @val: Value read from hardware or cache * * This function handles the register reads from the direct access registers and * the muxed registers while caching all register accesses, internally handling @@ -590,10 +587,12 @@ static int cy8c95x0_regmap_update_bits(struct cy8c95x0_pinctrl *chip, unsigned i * * Return: 0 for successful request, else a corresponding error value */ -static int cy8c95x0_regmap_read(struct cy8c95x0_pinctrl *chip, unsigned int reg, - unsigned int port, unsigned int *read_val) +static int cy8c95x0_regmap_read_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg, + unsigned int port, unsigned int mask, unsigned int *val) { - int off, ret; + unsigned int off; + unsigned int tmp; + int ret; /* Registers behind the PORTSEL mux have their own range in regmap */ if (cy8c95x0_muxed_register(reg)) { @@ -605,11 +604,14 @@ static int cy8c95x0_regmap_read(struct cy8c95x0_pinctrl *chip, unsigned int reg, else off = reg; } - guard(mutex)(&chip->i2c_lock); - ret = regmap_read(chip->regmap, off, read_val); + scoped_guard(mutex, &chip->i2c_lock) + ret = regmap_read(chip->regmap, off, &tmp); + if (ret) + return ret; - return ret; + *val = tmp & mask; + return 0; } static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, @@ -617,26 +619,18 @@ static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, { DECLARE_BITMAP(tmask, MAX_LINE); DECLARE_BITMAP(tval, MAX_LINE); + unsigned long bits, offset; int write_val; - u8 bits; int ret; /* Add the 4 bit gap of Gport2 */ - bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE); - bitmap_shift_left(tmask, tmask, 4, MAX_LINE); - bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3); - - bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE); - bitmap_shift_left(tval, tval, 4, MAX_LINE); - bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3); - - for (unsigned int i = 0; i < chip->nport; i++) { - /* Skip over unused banks */ - bits = bitmap_get_value8(tmask, i * BANK_SZ); - if (!bits) - continue; + bitmap_scatter(tmask, mask, chip->map, MAX_LINE); + bitmap_scatter(tval, val, chip->map, MAX_LINE); + + for_each_set_clump8(offset, bits, tmask, chip->tpin) { + unsigned int i = offset / 8; - write_val = bitmap_get_value8(tval, i * BANK_SZ); + write_val = bitmap_get_value8(tval, offset); ret = cy8c95x0_regmap_update_bits(chip, reg, i, bits, write_val); if (ret < 0) { @@ -653,40 +647,54 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, { DECLARE_BITMAP(tmask, MAX_LINE); DECLARE_BITMAP(tval, MAX_LINE); - DECLARE_BITMAP(tmp, MAX_LINE); - int read_val; - u8 bits; + unsigned long bits, offset; + unsigned int read_val; int ret; /* Add the 4 bit gap of Gport2 */ - bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE); - bitmap_shift_left(tmask, tmask, 4, MAX_LINE); - bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3); - - bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE); - bitmap_shift_left(tval, tval, 4, MAX_LINE); - bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3); - - for (unsigned int i = 0; i < chip->nport; i++) { - /* Skip over unused banks */ - bits = bitmap_get_value8(tmask, i * BANK_SZ); - if (!bits) - continue; + bitmap_scatter(tmask, mask, chip->map, MAX_LINE); + bitmap_scatter(tval, val, chip->map, MAX_LINE); + + for_each_set_clump8(offset, bits, tmask, chip->tpin) { + unsigned int i = offset / 8; - ret = cy8c95x0_regmap_read(chip, reg, i, &read_val); + ret = cy8c95x0_regmap_read_bits(chip, reg, i, bits, &read_val); if (ret < 0) { dev_err(chip->dev, "failed reading register %d, port %u: err %d\n", reg, i, ret); return ret; } - read_val &= bits; - read_val |= bitmap_get_value8(tval, i * BANK_SZ) & ~bits; - bitmap_set_value8(tval, read_val, i * BANK_SZ); + read_val |= bitmap_get_value8(tval, offset) & ~bits; + bitmap_set_value8(tval, read_val, offset); } /* Fill the 4 bit gap of Gport2 */ - bitmap_shift_right(tmp, tval, 4, MAX_LINE); - bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE); + bitmap_gather(val, tval, chip->map, MAX_LINE); + + return 0; +} + +static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, unsigned int pin, bool input) +{ + u8 port = cypress_get_port(chip, pin); + u8 bit = cypress_get_pin_mask(chip, pin); + int ret; + + ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, input ? bit : 0); + if (ret) + return ret; + + /* + * Disable driving the pin by forcing it to HighZ. Only setting + * the direction register isn't sufficient in Push-Pull mode. + */ + if (input && test_bit(pin, chip->push_pull)) { + ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DRV_HIZ, port, bit, bit); + if (ret) + return ret; + + __clear_bit(pin, chip->push_pull); + } return 0; } @@ -717,10 +725,10 @@ static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off) struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); u8 port = cypress_get_port(chip, off); u8 bit = cypress_get_pin_mask(chip, off); - u32 reg_val; + unsigned int reg_val; int ret; - ret = cy8c95x0_regmap_read(chip, CY8C95X0_INPUT, port, ®_val); + ret = cy8c95x0_regmap_read_bits(chip, CY8C95X0_INPUT, port, bit, ®_val); if (ret < 0) { /* * NOTE: @@ -731,17 +739,18 @@ static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off) return 0; } - return !!(reg_val & bit); + return reg_val ? 1 : 0; } -static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off, - int val) +static int cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off, + int val) { struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); u8 port = cypress_get_port(chip, off); u8 bit = cypress_get_pin_mask(chip, off); - cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0); + return cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, + val ? bit : 0); } static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off) @@ -749,14 +758,14 @@ static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off) struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); u8 port = cypress_get_port(chip, off); u8 bit = cypress_get_pin_mask(chip, off); - u32 reg_val; + unsigned int reg_val; int ret; - ret = cy8c95x0_regmap_read(chip, CY8C95X0_DIRECTION, port, ®_val); + ret = cy8c95x0_regmap_read_bits(chip, CY8C95X0_DIRECTION, port, bit, ®_val); if (ret < 0) return ret; - if (reg_val & bit) + if (reg_val) return GPIO_LINE_DIRECTION_IN; return GPIO_LINE_DIRECTION_OUT; @@ -769,8 +778,8 @@ static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip, enum pin_config_param param = pinconf_to_config_param(*config); u8 port = cypress_get_port(chip, off); u8 bit = cypress_get_pin_mask(chip, off); + unsigned int reg_val; unsigned int reg; - u32 reg_val; u16 arg = 0; int ret; @@ -827,16 +836,16 @@ static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip, * Writing 1 to one of the drive mode registers will automatically * clear conflicting set bits in the other drive mode registers. */ - ret = cy8c95x0_regmap_read(chip, reg, port, ®_val); + ret = cy8c95x0_regmap_read_bits(chip, reg, port, bit, ®_val); if (ret < 0) return ret; - if (reg_val & bit) + if (reg_val) arg = 1; if (param == PIN_CONFIG_OUTPUT_ENABLE) arg = !arg; - *config = pinconf_to_config_packed(param, (u16)arg); + *config = pinconf_to_config_packed(param, arg); return 0; } @@ -900,12 +909,12 @@ static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc, return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, bits, mask); } -static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc, - unsigned long *mask, unsigned long *bits) +static int cy8c95x0_gpio_set_multiple(struct gpio_chip *gc, + unsigned long *mask, unsigned long *bits) { struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); - cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask); + return cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask); } static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc) @@ -930,10 +939,10 @@ static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip) gc->direction_input = cy8c95x0_gpio_direction_input; gc->direction_output = cy8c95x0_gpio_direction_output; gc->get = cy8c95x0_gpio_get_value; - gc->set = cy8c95x0_gpio_set_value; + gc->set_rv = cy8c95x0_gpio_set_value; gc->get_direction = cy8c95x0_gpio_get_direction; gc->get_multiple = cy8c95x0_gpio_get_multiple; - gc->set_multiple = cy8c95x0_gpio_set_multiple; + gc->set_multiple_rv = cy8c95x0_gpio_set_multiple; gc->set_config = gpiochip_generic_config; gc->can_sleep = true; gc->add_pin_ranges = cy8c95x0_add_pin_ranges; @@ -1095,7 +1104,7 @@ static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid) if (!ret) return IRQ_RETVAL(0); - ret = 0; + ret = false; for_each_set_bit(level, pending, MAX_LINE) { /* Already accounted for 4bit gap in GPort2 */ nested_irq = irq_find_mapping(gc->irq.domain, level); @@ -1114,7 +1123,7 @@ static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid) else handle_nested_irq(nested_irq); - ret = 1; + ret = true; } return IRQ_RETVAL(ret); @@ -1248,32 +1257,6 @@ static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev, return cy8c95x0_set_mode(chip, pin, false); } -static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, - unsigned int pin, bool input) -{ - u8 port = cypress_get_port(chip, pin); - u8 bit = cypress_get_pin_mask(chip, pin); - int ret; - - ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, input ? bit : 0); - if (ret) - return ret; - - /* - * Disable driving the pin by forcing it to HighZ. Only setting - * the direction register isn't sufficient in Push-Pull mode. - */ - if (input && test_bit(pin, chip->push_pull)) { - ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DRV_HIZ, port, bit, bit); - if (ret) - return ret; - - __clear_bit(pin, chip->push_pull); - } - - return 0; -} - static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin, bool input) @@ -1305,7 +1288,7 @@ static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned int num_configs) { struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); - int ret = 0; + int ret; int i; for (i = 0; i < num_configs; i++) { @@ -1314,7 +1297,7 @@ static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, return ret; } - return ret; + return 0; } static const struct pinconf_ops cy8c95x0_pinconf_ops = { @@ -1486,8 +1469,11 @@ static int cy8c95x0_probe(struct i2c_client *client) return PTR_ERR(chip->regmap); bitmap_zero(chip->push_pull, MAX_LINE); - bitmap_zero(chip->shiftmask, MAX_LINE); - bitmap_set(chip->shiftmask, 0, 20); + + /* Setup HW pins mapping */ + bitmap_fill(chip->map, MAX_LINE); + bitmap_clear(chip->map, 20, 4); + mutex_init(&chip->i2c_lock); if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) { diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index bc7ee54e062b..3c660471ec69 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -3,7 +3,7 @@ * Ingenic SoCs pinctrl driver * * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net> - * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk> + * Copyright (c) 2017, 2019, 2020, 2023 Paul Boddie <paul@boddie.org.uk> * Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> */ @@ -58,6 +58,8 @@ #define JZ4770_GPIO_FLAG 0x50 #define JZ4770_GPIO_PEN 0x70 +#define X1600_GPIO_PU 0x80 + #define X1830_GPIO_PEL 0x110 #define X1830_GPIO_PEH 0x120 #define X1830_GPIO_SR 0x150 @@ -112,6 +114,7 @@ enum jz_version { ID_JZ4780, ID_X1000, ID_X1500, + ID_X1600, ID_X1830, ID_X2000, ID_X2100, @@ -162,6 +165,7 @@ static const unsigned long enabled_socs = IS_ENABLED(CONFIG_MACH_JZ4780) << ID_JZ4780 | IS_ENABLED(CONFIG_MACH_X1000) << ID_X1000 | IS_ENABLED(CONFIG_MACH_X1500) << ID_X1500 | + IS_ENABLED(CONFIG_MACH_X1600) << ID_X1600 | IS_ENABLED(CONFIG_MACH_X1830) << ID_X1830 | IS_ENABLED(CONFIG_MACH_X2000) << ID_X2000 | IS_ENABLED(CONFIG_MACH_X2100) << ID_X2100; @@ -206,6 +210,14 @@ static int jz4730_nand_cs5_pins[] = { 0x57, }; static int jz4730_pwm_pwm0_pins[] = { 0x5e, }; static int jz4730_pwm_pwm1_pins[] = { 0x5f, }; +static int jz4730_mii_pins[] = { 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, + 0x77, 0x78, 0x19, 0x7a, 0x1b, 0x7c, }; + +static int jz4730_i2s_mclk_pins[] = { 0x44, }; +static int jz4730_i2s_acreset_pins[] = { 0x45, }; +static int jz4730_i2s_data_pins[] = { 0x46, 0x47, }; +static int jz4730_i2s_clock_pins[] = { 0x4d, 0x4e, }; + static u8 jz4730_lcd_8bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, }; static const struct group_desc jz4730_groups[] = { @@ -227,6 +239,12 @@ static const struct group_desc jz4730_groups[] = { INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1), INGENIC_PIN_GROUP("pwm0", jz4730_pwm_pwm0, 1), INGENIC_PIN_GROUP("pwm1", jz4730_pwm_pwm1, 1), + INGENIC_PIN_GROUP("mii", jz4730_mii, 1), + INGENIC_PIN_GROUP("i2s-mclk-out", jz4730_i2s_mclk, 1), + INGENIC_PIN_GROUP("i2s-acreset", jz4730_i2s_acreset, 1), + INGENIC_PIN_GROUP("i2s-data", jz4730_i2s_data, 1), + INGENIC_PIN_GROUP("i2s-master", jz4730_i2s_clock, 1), + INGENIC_PIN_GROUP("i2s-slave", jz4730_i2s_clock, 2), }; static const char *jz4730_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; @@ -242,6 +260,8 @@ static const char *jz4730_nand_groups[] = { }; static const char *jz4730_pwm0_groups[] = { "pwm0", }; static const char *jz4730_pwm1_groups[] = { "pwm1", }; +static const char *jz4730_mii_groups[] = { "mii", }; +static const char *jz4730_i2s_groups[] = { "i2s-data", "i2s-master", "i2s-slave", }; static const struct function_desc jz4730_functions[] = { INGENIC_PIN_FUNCTION("mmc", jz4730_mmc), @@ -253,6 +273,8 @@ static const struct function_desc jz4730_functions[] = { INGENIC_PIN_FUNCTION("nand", jz4730_nand), INGENIC_PIN_FUNCTION("pwm0", jz4730_pwm0), INGENIC_PIN_FUNCTION("pwm1", jz4730_pwm1), + INGENIC_PIN_FUNCTION("mii", jz4730_mii), + INGENIC_PIN_FUNCTION("i2s", jz4730_i2s), }; static const struct ingenic_chip_info jz4730_chip_info = { @@ -2351,6 +2373,233 @@ static const struct ingenic_chip_info x1500_chip_info = { .access_table = &x1000_access_table, }; +static const u32 x1600_pull_ups[4] = { + 0xffffffff, 0xdffbf7bf, 0x987e0000, 0x0000003f, +}; + +static const u32 x1600_pull_downs[4] = { + 0x00000000, 0x00000000, 0x07000007, 0x00000000, +}; + +static int x1600_uart0_data_pins[] = { 0x27, 0x28, }; +static int x1600_uart0_hwflow_pins[] = { 0x29, 0x2a, }; +static int x1600_uart1_data_pins[] = { 0x23, 0x22, }; +static int x1600_uart1_hwflow_pins[] = { 0x25, 0x24, }; +static int x1600_uart2_data_a_pins[] = { 0x1f, 0x1e, }; +static int x1600_uart2_data_b_pins[] = { 0x21, 0x20, }; +static int x1600_uart3_data_b_pins[] = { 0x25, 0x24, }; +static int x1600_uart3_data_d_pins[] = { 0x65, 0x64, }; +static int x1600_sfc_pins[] = { 0x53, 0x54, 0x55, 0x56, 0x51, 0x52, 0x24, }; +static int x1600_ssi_dt_a_pins[] = { 0x1e, }; +static int x1600_ssi_dt_b_pins[] = { 0x2d, }; +static int x1600_ssi_dr_a_pins[] = { 0x1d, }; +static int x1600_ssi_dr_b_pins[] = { 0x2e, }; +static int x1600_ssi_clk_a_pins[] = { 0x1f, }; +static int x1600_ssi_clk_b_pins[] = { 0x2c, }; +static int x1600_ssi_ce0_a_pins[] = { 0x1c, }; +static int x1600_ssi_ce0_b_pins[] = { 0x31, }; +static int x1600_ssi_ce1_a_pins[] = { 0x22, }; +static int x1600_ssi_ce1_b_pins[] = { 0x30, }; +static int x1600_mmc0_1bit_b_pins[] = { 0x2c, 0x2d, 0x2e, }; +static int x1600_mmc0_4bit_b_pins[] = { 0x2f, 0x30, 0x31, }; +static int x1600_mmc0_1bit_c_pins[] = { 0x51, 0x53, 0x54, }; +static int x1600_mmc0_4bit_c_pins[] = { 0x56, 0x55, 0x52, }; +static int x1600_mmc1_1bit_pins[] = { 0x60, 0x61, 0x62, }; +static int x1600_mmc1_4bit_pins[] = { 0x63, 0x64, 0x65, }; +static int x1600_i2c0_a_pins[] = { 0x1d, 0x1c, }; +static int x1600_i2c0_b_pins[] = { 0x3f, 0x3e, }; +static int x1600_i2c1_b_15_pins[] = { 0x30, 0x2f, }; +static int x1600_i2c1_b_19_pins[] = { 0x34, 0x33, }; +static int x1600_i2s_data_tx_pins[] = { 0x39, }; +static int x1600_i2s_data_rx_pins[] = { 0x35, }; +static int x1600_i2s_clk_rx_pins[] = { 0x37, 0x38, }; +static int x1600_i2s_clk_tx_pins[] = { 0x3b, 0x3c, }; +static int x1600_i2s_sysclk_pins[] = { 0x36, 0x3a, }; + +static int x1600_cim_pins[] = { + 0x14, 0x16, 0x15, 0x18, 0x13, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, +}; + +static int x1600_slcd_8bit_pins[] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x17, 0x19, 0x1a, 0x1b, +}; + +static int x1600_slcd_16bit_pins[] = { + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, +}; + +static int x1600_lcd_16bit_pins[] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x18, 0x19, 0x1a, 0x1b, +}; + +static int x1600_lcd_18bit_pins[] = { + 0x10, 0x11, +}; + +static int x1600_lcd_24bit_pins[] = { + 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, +}; + +static int x1600_pwm_pwm0_pins[] = { 0x40, }; +static int x1600_pwm_pwm1_pins[] = { 0x41, }; +static int x1600_pwm_pwm2_pins[] = { 0x42, }; +static int x1600_pwm_pwm3_pins[] = { 0x58, }; +static int x1600_pwm_pwm4_pins[] = { 0x59, }; +static int x1600_pwm_pwm5_b_pins[] = { 0x33, }; +static int x1600_pwm_pwm5_c_pins[] = { 0x5a, }; +static int x1600_pwm_pwm6_b9_pins[] = { 0x29, }; +static int x1600_pwm_pwm6_b20_pins[] = { 0x34, }; +static int x1600_pwm_pwm7_b10_pins[] = { 0x2a, }; +static int x1600_pwm_pwm7_b21_pins[] = { 0x35, }; + +static int x1600_mac_pins[] = { + 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, +}; + +static int x1600_sfc_funcs[] = { 0, 0, 0, 0, 0, 0, 2, }; + +static const struct group_desc x1600_groups[] = { + INGENIC_PIN_GROUP("uart0-data", x1600_uart0_data, 0), + INGENIC_PIN_GROUP("uart0-hwflow", x1600_uart0_hwflow, 0), + INGENIC_PIN_GROUP("uart1-data", x1600_uart1_data, 1), + INGENIC_PIN_GROUP("uart1-hwflow", x1600_uart1_hwflow, 1), + INGENIC_PIN_GROUP("uart2-data-a", x1600_uart2_data_a, 2), + INGENIC_PIN_GROUP("uart2-data-b", x1600_uart2_data_b, 1), + INGENIC_PIN_GROUP("uart3-data-b", x1600_uart3_data_b, 0), + INGENIC_PIN_GROUP("uart3-data-d", x1600_uart3_data_d, 2), + INGENIC_PIN_GROUP_FUNCS("sfc", x1600_sfc, x1600_sfc_funcs), + INGENIC_PIN_GROUP("ssi-dt-a", x1600_ssi_dt_a, 0), + INGENIC_PIN_GROUP("ssi-dt-b", x1600_ssi_dt_b, 1), + INGENIC_PIN_GROUP("ssi-dr-a", x1600_ssi_dr_a, 0), + INGENIC_PIN_GROUP("ssi-dr-b", x1600_ssi_dr_b, 1), + INGENIC_PIN_GROUP("ssi-clk-a", x1600_ssi_clk_a, 0), + INGENIC_PIN_GROUP("ssi-clk-b", x1600_ssi_clk_b, 1), + INGENIC_PIN_GROUP("ssi-ce0-a", x1600_ssi_ce0_a, 0), + INGENIC_PIN_GROUP("ssi-ce0-b", x1600_ssi_ce0_b, 1), + INGENIC_PIN_GROUP("ssi-ce1-a", x1600_ssi_ce1_a, 2), + INGENIC_PIN_GROUP("ssi-ce1-b", x1600_ssi_ce1_b, 1), + INGENIC_PIN_GROUP("mmc0-1bit-b", x1600_mmc0_1bit_b, 0), + INGENIC_PIN_GROUP("mmc0-4bit-b", x1600_mmc0_4bit_b, 0), + INGENIC_PIN_GROUP("mmc0-1bit-c", x1600_mmc0_1bit_c, 1), + INGENIC_PIN_GROUP("mmc0-4bit-c", x1600_mmc0_4bit_c, 1), + INGENIC_PIN_GROUP("mmc1-1bit", x1600_mmc1_1bit, 0), + INGENIC_PIN_GROUP("mmc1-4bit", x1600_mmc1_4bit, 0), + INGENIC_PIN_GROUP("i2c0-data-a", x1600_i2c0_a, 2), + INGENIC_PIN_GROUP("i2c0-data-b", x1600_i2c0_b, 0), + INGENIC_PIN_GROUP("i2c1-data-b-15", x1600_i2c1_b_15, 2), + INGENIC_PIN_GROUP("i2c1-data-b-19", x1600_i2c1_b_19, 0), + INGENIC_PIN_GROUP("i2s-data-tx", x1600_i2s_data_tx, 0), + INGENIC_PIN_GROUP("i2s-data-rx", x1600_i2s_data_rx, 0), + INGENIC_PIN_GROUP("i2s-clk-rx", x1600_i2s_clk_rx, 0), + INGENIC_PIN_GROUP("i2s-clk-tx", x1600_i2s_clk_tx, 0), + INGENIC_PIN_GROUP("i2s-sysclk", x1600_i2s_sysclk, 0), + INGENIC_PIN_GROUP("cim-data", x1600_cim, 2), + INGENIC_PIN_GROUP("slcd-8bit", x1600_slcd_8bit, 1), + INGENIC_PIN_GROUP("slcd-16bit", x1600_slcd_16bit, 1), + INGENIC_PIN_GROUP("lcd-16bit", x1600_lcd_16bit, 0), + INGENIC_PIN_GROUP("lcd-18bit", x1600_lcd_18bit, 0), + INGENIC_PIN_GROUP("lcd-24bit", x1600_lcd_24bit, 0), + INGENIC_PIN_GROUP("pwm0", x1600_pwm_pwm0, 0), + INGENIC_PIN_GROUP("pwm1", x1600_pwm_pwm1, 0), + INGENIC_PIN_GROUP("pwm2", x1600_pwm_pwm2, 0), + INGENIC_PIN_GROUP("pwm3", x1600_pwm_pwm3, 1), + INGENIC_PIN_GROUP("pwm4", x1600_pwm_pwm4, 1), + INGENIC_PIN_GROUP("pwm5-b", x1600_pwm_pwm5_b, 2), + INGENIC_PIN_GROUP("pwm5-c", x1600_pwm_pwm5_c, 1), + INGENIC_PIN_GROUP("pwm6-b9", x1600_pwm_pwm6_b9, 1), + INGENIC_PIN_GROUP("pwm6-b20", x1600_pwm_pwm6_b20, 2), + INGENIC_PIN_GROUP("pwm7-b10", x1600_pwm_pwm7_b10, 1), + INGENIC_PIN_GROUP("pwm7-b21", x1600_pwm_pwm7_b21, 2), + INGENIC_PIN_GROUP("mac", x1600_mac, 1), +}; + +static const char * const x1600_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; +static const char * const x1600_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; +static const char * const x1600_uart2_groups[] = { "uart2-data-a", "uart2-data-b", }; +static const char * const x1600_uart3_groups[] = { "uart3-data-b", "uart3-data-d", }; + +static const char * const x1600_sfc_groups[] = { "sfc", }; + +static const char * const x1600_ssi_groups[] = { + "ssi-dt-a", "ssi-dt-b", + "ssi-dr-a", "ssi-dr-b", + "ssi-clk-a", "ssi-clk-b", + "ssi-ce0-a", "ssi-ce0-b", + "ssi-ce1-a", "ssi-ce1-b", +}; + +static const char * const x1600_mmc0_groups[] = { "mmc0-1bit-b", "mmc0-4bit-b", + "mmc0-1bit-c", "mmc0-4bit-c", +}; + +static const char * const x1600_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; + +static const char * const x1600_i2c0_groups[] = { "i2c0-data-a", "i2c0-data-b", }; +static const char * const x1600_i2c1_groups[] = { "i2c1-data-b-15", "i2c1-data-b-19", }; + +static const char * const x1600_i2s_groups[] = { + "i2s-data-tx", "i2s-data-rx", "i2s-clk-rx", "i2s-clk-tx", "i2s-sysclk", +}; + +static const char * const x1600_cim_groups[] = { "cim-data", }; + +static const char * const x1600_lcd_groups[] = { "slcd-8bit", "slcd-16bit", + "lcd-16bit", "lcd-18bit", "lcd-24bit", "lcd-no-pins", +}; + +static const char * const x1600_pwm0_groups[] = { "pwm0", }; +static const char * const x1600_pwm1_groups[] = { "pwm1", }; +static const char * const x1600_pwm2_groups[] = { "pwm2", }; +static const char * const x1600_pwm3_groups[] = { "pwm3", }; +static const char * const x1600_pwm4_groups[] = { "pwm4", }; +static const char * const x1600_pwm5_groups[] = { "pwm5-b", "pwm5-c", }; +static const char * const x1600_pwm6_groups[] = { "pwm6-b9", "pwm6-b20", }; +static const char * const x1600_pwm7_groups[] = { "pwm7-b10", "pwm7-b21", }; + +static const char * const x1600_mac_groups[] = { "mac", }; + +static const struct function_desc x1600_functions[] = { + INGENIC_PIN_FUNCTION("uart0", x1600_uart0), + INGENIC_PIN_FUNCTION("uart1", x1600_uart1), + INGENIC_PIN_FUNCTION("uart2", x1600_uart2), + INGENIC_PIN_FUNCTION("uart3", x1600_uart3), + INGENIC_PIN_FUNCTION("sfc", x1600_sfc), + INGENIC_PIN_FUNCTION("ssi", x1600_ssi), + INGENIC_PIN_FUNCTION("mmc0", x1600_mmc0), + INGENIC_PIN_FUNCTION("mmc1", x1600_mmc1), + INGENIC_PIN_FUNCTION("i2c0", x1600_i2c0), + INGENIC_PIN_FUNCTION("i2c1", x1600_i2c1), + INGENIC_PIN_FUNCTION("i2s", x1600_i2s), + INGENIC_PIN_FUNCTION("cim", x1600_cim), + INGENIC_PIN_FUNCTION("lcd", x1600_lcd), + INGENIC_PIN_FUNCTION("pwm0", x1600_pwm0), + INGENIC_PIN_FUNCTION("pwm1", x1600_pwm1), + INGENIC_PIN_FUNCTION("pwm2", x1600_pwm2), + INGENIC_PIN_FUNCTION("pwm3", x1600_pwm3), + INGENIC_PIN_FUNCTION("pwm4", x1600_pwm4), + INGENIC_PIN_FUNCTION("pwm5", x1600_pwm5), + INGENIC_PIN_FUNCTION("pwm6", x1600_pwm6), + INGENIC_PIN_FUNCTION("pwm7", x1600_pwm7), + INGENIC_PIN_FUNCTION("mac", x1600_mac), +}; + +static const struct ingenic_chip_info x1600_chip_info = { + .num_chips = 4, + .reg_offset = 0x100, + .version = ID_X1600, + .groups = x1600_groups, + .num_groups = ARRAY_SIZE(x1600_groups), + .functions = x1600_functions, + .num_functions = ARRAY_SIZE(x1600_functions), + .pull_ups = x1600_pull_ups, + .pull_downs = x1600_pull_downs, + .access_table = &x1000_access_table, +}; + static const u32 x1830_pull_ups[4] = { 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, }; @@ -3551,12 +3800,14 @@ static void ingenic_gpio_irq_handler(struct irq_desc *desc) chained_irq_exit(irq_chip, desc); } -static void ingenic_gpio_set(struct gpio_chip *gc, - unsigned int offset, int value) +static int ingenic_gpio_set(struct gpio_chip *gc, unsigned int offset, + int value) { struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); ingenic_gpio_set_value(jzgc, offset, value); + + return 0; } static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset) @@ -3860,7 +4111,9 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx)); } else { - if (is_soc_or_above(jzpc, ID_JZ4770)) + if (is_soc_or_above(jzpc, ID_X1600)) + pull = ingenic_get_pin_config(jzpc, pin, X1600_GPIO_PU); + else if (is_soc_or_above(jzpc, ID_JZ4770)) pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN); else if (is_soc_or_above(jzpc, ID_JZ4740)) pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); @@ -3959,6 +4212,8 @@ static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, REG_SET(X1830_GPIO_PEH), bias << idxh); } + } else if (is_soc_or_above(jzpc, ID_X1600)) { + ingenic_config_pin(jzpc, pin, X1600_GPIO_PU, bias); } else if (is_soc_or_above(jzpc, ID_JZ4770)) { ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !bias); } else if (is_soc_or_above(jzpc, ID_JZ4740)) { @@ -4150,6 +4405,7 @@ static const struct of_device_id ingenic_gpio_of_matches[] __initconst = { { .compatible = "ingenic,jz4775-gpio" }, { .compatible = "ingenic,jz4780-gpio" }, { .compatible = "ingenic,x1000-gpio" }, + { .compatible = "ingenic,x1600-gpio" }, { .compatible = "ingenic,x1830-gpio" }, { .compatible = "ingenic,x2000-gpio" }, { .compatible = "ingenic,x2100-gpio" }, @@ -4195,7 +4451,7 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, jzgc->gc.fwnode = fwnode; jzgc->gc.owner = THIS_MODULE; - jzgc->gc.set = ingenic_gpio_set; + jzgc->gc.set_rv = ingenic_gpio_set; jzgc->gc.get = ingenic_gpio_get; jzgc->gc.direction_input = pinctrl_gpio_direction_input; jzgc->gc.direction_output = ingenic_gpio_direction_output; @@ -4398,6 +4654,10 @@ static const struct of_device_id ingenic_pinctrl_of_matches[] = { .data = IF_ENABLED(CONFIG_MACH_X1500, &x1500_chip_info) }, { + .compatible = "ingenic,x1600-pinctrl", + .data = IF_ENABLED(CONFIG_MACH_X1600, &x1600_chip_info) + }, + { .compatible = "ingenic,x1830-pinctrl", .data = IF_ENABLED(CONFIG_MACH_X1830, &x1830_chip_info) }, diff --git a/drivers/pinctrl/pinctrl-k230.c b/drivers/pinctrl/pinctrl-k230.c index a9b4627b46b0..d716f23d837f 100644 --- a/drivers/pinctrl/pinctrl-k230.c +++ b/drivers/pinctrl/pinctrl-k230.c @@ -477,6 +477,10 @@ static int k230_pinctrl_parse_groups(struct device_node *np, grp->name = np->name; list = of_get_property(np, "pinmux", &size); + if (!list) { + dev_err(dev, "failed to get pinmux property\n"); + return -EINVAL; + } size /= sizeof(*list); grp->num_pins = size; @@ -586,6 +590,7 @@ static int k230_pinctrl_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct k230_pinctrl *info; struct pinctrl_desc *pctl; + int ret; info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); if (!info) @@ -611,19 +616,21 @@ static int k230_pinctrl_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(info->regmap_base), "failed to init regmap\n"); + ret = k230_pinctrl_parse_dt(pdev, info); + if (ret) + return ret; + info->pctl_dev = devm_pinctrl_register(dev, pctl, info); if (IS_ERR(info->pctl_dev)) return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "devm_pinctrl_register failed\n"); - k230_pinctrl_parse_dt(pdev, info); - return 0; } static const struct of_device_id k230_dt_ids[] = { { .compatible = "canaan,k230-pinctrl", }, - { /* sintenel */ } + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, k230_dt_ids); diff --git a/drivers/pinctrl/pinctrl-keembay.c b/drivers/pinctrl/pinctrl-keembay.c index b693f4787044..0d7cc8280ea2 100644 --- a/drivers/pinctrl/pinctrl-keembay.c +++ b/drivers/pinctrl/pinctrl-keembay.c @@ -1268,7 +1268,7 @@ static void keembay_gpio_irq_handler(struct irq_desc *desc) for_each_set_clump8(bit, clump, ®, BITS_PER_TYPE(typeof(reg))) { pin = clump & ~KEEMBAY_GPIO_IRQ_ENABLE; val = keembay_read_pin(kpc->base0 + KEEMBAY_GPIO_DATA_IN, pin); - kmb_irq = irq_linear_revmap(gc->irq.domain, pin); + kmb_irq = irq_find_mapping(gc->irq.domain, pin); /* Checks if the interrupt is enabled */ if (val && (clump & KEEMBAY_GPIO_IRQ_ENABLE)) diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index b96e6368a956..c2f4b16f42d2 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -382,6 +382,7 @@ static irqreturn_t mcp23s08_irq(int irq, void *data) { struct mcp23s08 *mcp = data; int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval, gpinten; + bool need_unmask = false; unsigned long int enabled_interrupts; unsigned int child_irq; bool intf_set, intcap_changed, gpio_bit_changed, @@ -396,9 +397,6 @@ static irqreturn_t mcp23s08_irq(int irq, void *data) goto unlock; } - if (mcp_read(mcp, MCP_INTCAP, &intcap)) - goto unlock; - if (mcp_read(mcp, MCP_INTCON, &intcon)) goto unlock; @@ -408,6 +406,16 @@ static irqreturn_t mcp23s08_irq(int irq, void *data) if (mcp_read(mcp, MCP_DEFVAL, &defval)) goto unlock; + /* Mask level interrupts to avoid their immediate reactivation after clearing */ + if (intcon) { + need_unmask = true; + if (mcp_write(mcp, MCP_GPINTEN, gpinten & ~intcon)) + goto unlock; + } + + if (mcp_read(mcp, MCP_INTCAP, &intcap)) + goto unlock; + /* This clears the interrupt(configurable on S18) */ if (mcp_read(mcp, MCP_GPIO, &gpio)) goto unlock; @@ -470,9 +478,18 @@ static irqreturn_t mcp23s08_irq(int irq, void *data) } } + if (need_unmask) { + mutex_lock(&mcp->lock); + goto unlock; + } + return IRQ_HANDLED; unlock: + if (need_unmask) + if (mcp_write(mcp, MCP_GPINTEN, gpinten)) + dev_err(mcp->chip.parent, "can't unmask GPINTEN\n"); + mutex_unlock(&mcp->lock); return IRQ_HANDLED; } @@ -619,6 +636,14 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, mcp->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); + /* + * Reset the chip - we don't really know what state it's in, so reset + * all pins to input first to prevent surprises. + */ + ret = mcp_write(mcp, MCP_IODIR, mcp->chip.ngpio == 16 ? 0xFFFF : 0xFF); + if (ret < 0) + return ret; + /* verify MCP_IOCON.SEQOP = 0, so sequential reads work, * and MCP_IOCON.HAEN = 1, so we work with all chips. */ diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c index a60db93b61b1..88c2f14cfc6b 100644 --- a/drivers/pinctrl/pinctrl-microchip-sgpio.c +++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c @@ -555,10 +555,10 @@ static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; } -static void microchip_sgpio_set_value(struct gpio_chip *gc, - unsigned int gpio, int value) +static int microchip_sgpio_set_value(struct gpio_chip *gc, unsigned int gpio, + int value) { - microchip_sgpio_direction_output(gc, gpio, value); + return microchip_sgpio_direction_output(gc, gpio, value); } static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio) @@ -858,7 +858,7 @@ static int microchip_sgpio_register_bank(struct device *dev, gc->direction_input = microchip_sgpio_direction_input; gc->direction_output = microchip_sgpio_direction_output; gc->get = microchip_sgpio_get_value; - gc->set = microchip_sgpio_set_value; + gc->set_rv = microchip_sgpio_set_value; gc->request = gpiochip_generic_request; gc->free = gpiochip_generic_free; gc->of_xlate = microchip_sgpio_of_xlate; diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 329d54b11529..fbb3d43746bb 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -1950,17 +1950,18 @@ static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset) return !!(val & BIT(offset % 32)); } -static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset, - int value) +static int ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) { struct ocelot_pinctrl *info = gpiochip_get_data(chip); if (value) - regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), - BIT(offset % 32)); - else - regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), - BIT(offset % 32)); + return regmap_write(info->map, + REG(OCELOT_GPIO_OUT_SET, info, offset), + BIT(offset % 32)); + + return regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), + BIT(offset % 32)); } static int ocelot_gpio_get_direction(struct gpio_chip *chip, @@ -1996,7 +1997,7 @@ static int ocelot_gpio_direction_output(struct gpio_chip *chip, static const struct gpio_chip ocelot_gpiolib_chip = { .request = gpiochip_generic_request, .free = gpiochip_generic_free, - .set = ocelot_gpio_set, + .set_rv = ocelot_gpio_set, .get = ocelot_gpio_get, .get_direction = ocelot_gpio_get_direction, .direction_input = pinctrl_gpio_direction_input, diff --git a/drivers/pinctrl/pinctrl-pistachio.c b/drivers/pinctrl/pinctrl-pistachio.c index 53408344927a..e7bf60960961 100644 --- a/drivers/pinctrl/pinctrl-pistachio.c +++ b/drivers/pinctrl/pinctrl-pistachio.c @@ -1186,12 +1186,14 @@ static int pistachio_gpio_get(struct gpio_chip *chip, unsigned offset) return !!(gpio_readl(bank, reg) & BIT(offset)); } -static void pistachio_gpio_set(struct gpio_chip *chip, unsigned offset, - int value) +static int pistachio_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) { struct pistachio_gpio_bank *bank = gpiochip_get_data(chip); gpio_mask_writel(bank, GPIO_OUTPUT, offset, !!value); + + return 0; } static int pistachio_gpio_direction_input(struct gpio_chip *chip, @@ -1326,7 +1328,7 @@ static void pistachio_gpio_irq_handler(struct irq_desc *desc) .direction_input = pistachio_gpio_direction_input, \ .direction_output = pistachio_gpio_direction_output, \ .get = pistachio_gpio_get, \ - .set = pistachio_gpio_set, \ + .set_rv = pistachio_gpio_set, \ .base = _pin_base, \ .ngpio = _npins, \ }, \ @@ -1393,12 +1395,6 @@ static int pistachio_gpio_register(struct pistachio_pinctrl *pctl) dev_err(pctl->dev, "Failed to retrieve IRQ for bank %u\n", i); goto err; } - if (!ret) { - fwnode_handle_put(child); - dev_err(pctl->dev, "No IRQ for bank %u\n", i); - ret = -EINVAL; - goto err; - } irq = ret; bank = &pctl->gpio_banks[i]; diff --git a/drivers/pinctrl/pinctrl-rk805.c b/drivers/pinctrl/pinctrl-rk805.c index c42f1bf93404..fc0e330b1d11 100644 --- a/drivers/pinctrl/pinctrl-rk805.c +++ b/drivers/pinctrl/pinctrl-rk805.c @@ -325,26 +325,26 @@ static int rk805_gpio_get(struct gpio_chip *chip, unsigned int offset) return !!(val & pci->pin_cfg[offset].val_msk); } -static void rk805_gpio_set(struct gpio_chip *chip, - unsigned int offset, - int value) +static int rk805_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) { struct rk805_pctrl_info *pci = gpiochip_get_data(chip); - int ret; - ret = regmap_update_bits(pci->rk808->regmap, - pci->pin_cfg[offset].reg, - pci->pin_cfg[offset].val_msk, - value ? pci->pin_cfg[offset].val_msk : 0); - if (ret) - dev_err(pci->dev, "set gpio%d value %d failed\n", - offset, value); + return regmap_update_bits(pci->rk808->regmap, + pci->pin_cfg[offset].reg, + pci->pin_cfg[offset].val_msk, + value ? pci->pin_cfg[offset].val_msk : 0); } static int rk805_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) { - rk805_gpio_set(chip, offset, value); + int ret; + + ret = rk805_gpio_set(chip, offset, value); + if (ret) + return ret; + return pinctrl_gpio_direction_output(chip, offset); } @@ -378,7 +378,7 @@ static const struct gpio_chip rk805_gpio_chip = { .free = gpiochip_generic_free, .get_direction = rk805_gpio_get_direction, .get = rk805_gpio_get, - .set = rk805_gpio_set, + .set_rv = rk805_gpio_set, .direction_input = pinctrl_gpio_direction_input, .direction_output = rk805_gpio_direction_output, .can_sleep = true, diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 15145882950f..930c454e0cec 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2003,6 +2003,115 @@ static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, return 0; } +#define RK3528_DRV_BITS_PER_PIN 8 +#define RK3528_DRV_PINS_PER_REG 2 +#define RK3528_DRV_GPIO0_OFFSET 0x100 +#define RK3528_DRV_GPIO1_OFFSET 0x20120 +#define RK3528_DRV_GPIO2_OFFSET 0x30160 +#define RK3528_DRV_GPIO3_OFFSET 0x20190 +#define RK3528_DRV_GPIO4_OFFSET 0x101C0 + +static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + + if (bank->bank_num == 0) + *reg = RK3528_DRV_GPIO0_OFFSET; + else if (bank->bank_num == 1) + *reg = RK3528_DRV_GPIO1_OFFSET; + else if (bank->bank_num == 2) + *reg = RK3528_DRV_GPIO2_OFFSET; + else if (bank->bank_num == 3) + *reg = RK3528_DRV_GPIO3_OFFSET; + else if (bank->bank_num == 4) + *reg = RK3528_DRV_GPIO4_OFFSET; + else + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + + *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RK3528_DRV_PINS_PER_REG; + *bit *= RK3528_DRV_BITS_PER_PIN; + + return 0; +} + +#define RK3528_PULL_BITS_PER_PIN 2 +#define RK3528_PULL_PINS_PER_REG 8 +#define RK3528_PULL_GPIO0_OFFSET 0x200 +#define RK3528_PULL_GPIO1_OFFSET 0x20210 +#define RK3528_PULL_GPIO2_OFFSET 0x30220 +#define RK3528_PULL_GPIO3_OFFSET 0x20230 +#define RK3528_PULL_GPIO4_OFFSET 0x10240 + +static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + + if (bank->bank_num == 0) + *reg = RK3528_PULL_GPIO0_OFFSET; + else if (bank->bank_num == 1) + *reg = RK3528_PULL_GPIO1_OFFSET; + else if (bank->bank_num == 2) + *reg = RK3528_PULL_GPIO2_OFFSET; + else if (bank->bank_num == 3) + *reg = RK3528_PULL_GPIO3_OFFSET; + else if (bank->bank_num == 4) + *reg = RK3528_PULL_GPIO4_OFFSET; + else + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + + *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3528_PULL_PINS_PER_REG; + *bit *= RK3528_PULL_BITS_PER_PIN; + + return 0; +} + +#define RK3528_SMT_BITS_PER_PIN 1 +#define RK3528_SMT_PINS_PER_REG 8 +#define RK3528_SMT_GPIO0_OFFSET 0x400 +#define RK3528_SMT_GPIO1_OFFSET 0x20410 +#define RK3528_SMT_GPIO2_OFFSET 0x30420 +#define RK3528_SMT_GPIO3_OFFSET 0x20430 +#define RK3528_SMT_GPIO4_OFFSET 0x10440 + +static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + + if (bank->bank_num == 0) + *reg = RK3528_SMT_GPIO0_OFFSET; + else if (bank->bank_num == 1) + *reg = RK3528_SMT_GPIO1_OFFSET; + else if (bank->bank_num == 2) + *reg = RK3528_SMT_GPIO2_OFFSET; + else if (bank->bank_num == 3) + *reg = RK3528_SMT_GPIO3_OFFSET; + else if (bank->bank_num == 4) + *reg = RK3528_SMT_GPIO4_OFFSET; + else + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + + *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4); + *bit = pin_num % RK3528_SMT_PINS_PER_REG; + *bit *= RK3528_SMT_BITS_PER_PIN; + + return 0; +} + #define RK3562_DRV_BITS_PER_PIN 8 #define RK3562_DRV_PINS_PER_REG 2 #define RK3562_DRV_GPIO0_OFFSET 0x20070 @@ -2640,7 +2749,8 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, rmask_bits = RK3588_DRV_BITS_PER_PIN; ret = strength; goto config; - } else if (ctrl->type == RK3562 || + } else if (ctrl->type == RK3528 || + ctrl->type == RK3562 || ctrl->type == RK3568) { rmask_bits = RK3568_DRV_BITS_PER_PIN; ret = (1 << (strength + 1)) - 1; @@ -2785,6 +2895,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) case RK3328: case RK3368: case RK3399: + case RK3528: case RK3562: case RK3568: case RK3576: @@ -2846,6 +2957,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, case RK3328: case RK3368: case RK3399: + case RK3528: case RK3562: case RK3568: case RK3576: @@ -3115,6 +3227,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, case RK3328: case RK3368: case RK3399: + case RK3528: case RK3562: case RK3568: case RK3576: @@ -4237,6 +4350,49 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = { .drv_calc_reg = rk3399_calc_drv_reg_and_bit, }; +static struct rockchip_pin_bank rk3528_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20020, 0x20028, 0x20030, 0x20038), + PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x30040, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20060, 0x20068, 0x20070, 0), + PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x10080, 0x10088, 0x10090, 0x10098), +}; + +static struct rockchip_pin_ctrl rk3528_pin_ctrl = { + .pin_banks = rk3528_pin_banks, + .nr_banks = ARRAY_SIZE(rk3528_pin_banks), + .label = "RK3528-GPIO", + .type = RK3528, + .pull_calc_reg = rk3528_calc_pull_reg_and_bit, + .drv_calc_reg = rk3528_calc_drv_reg_and_bit, + .schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit, +}; + static struct rockchip_pin_bank rk3562_pin_banks[] = { PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", IOMUX_WIDTH_4BIT, @@ -4404,6 +4560,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { .data = &rk3368_pin_ctrl }, { .compatible = "rockchip,rk3399-pinctrl", .data = &rk3399_pin_ctrl }, + { .compatible = "rockchip,rk3528-pinctrl", + .data = &rk3528_pin_ctrl }, { .compatible = "rockchip,rk3562-pinctrl", .data = &rk3562_pin_ctrl }, { .compatible = "rockchip,rk3568-pinctrl", diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index 87a20cec8e21..35cd38079d1e 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -196,6 +196,7 @@ enum rockchip_pinctrl_type { RK3328, RK3368, RK3399, + RK3528, RK3562, RK3568, RK3576, diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c index df4bbcd7d1d5..383681041e4c 100644 --- a/drivers/pinctrl/pinctrl-scmi.c +++ b/drivers/pinctrl/pinctrl-scmi.c @@ -507,6 +507,7 @@ static int pinctrl_scmi_get_pins(struct scmi_pinctrl *pmx, static const char * const scmi_pinctrl_blocklist[] = { "fsl,imx95", + "fsl,imx94", NULL }; diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 5be14dc979e2..5cda6201b60f 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1611,15 +1611,16 @@ static int pcs_irq_init_chained_handler(struct pcs_device *pcs, /* * We can use the register offset as the hardirq - * number as irq_domain_add_simple maps them lazily. + * number as irq_domain_create_simple maps them lazily. * This way we can easily support more than one * interrupt per function if needed. */ num_irqs = pcs->size; - pcs->domain = irq_domain_add_simple(np, num_irqs, 0, - &pcs_irqdomain_ops, - pcs_soc); + pcs->domain = irq_domain_create_simple(of_fwnode_handle(np), + num_irqs, 0, + &pcs_irqdomain_ops, + pcs_soc); if (!pcs->domain) { irq_set_chained_handler(pcs_soc->irq, NULL); return -EINVAL; diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index fe2d52e434db..8a2ef74862d3 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -374,11 +374,6 @@ static struct st_pio_control *st_get_pio_control( } /* Low level functions.. */ -static inline int st_gpio_bank(int gpio) -{ - return gpio/ST_GPIO_PINS_PER_BANK; -} - static inline int st_gpio_pin(int gpio) { return gpio%ST_GPIO_PINS_PER_BANK; diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index aae01120dc52..f4fdcaa043e6 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -115,14 +115,14 @@ static int stmfx_gpio_get(struct gpio_chip *gc, unsigned int offset) return ret ? ret : !!(value & mask); } -static void stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) +static int stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) { struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR; u32 mask = get_mask(offset); - regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset), - mask, mask); + return regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset), + mask, mask); } static int stmfx_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) @@ -161,8 +161,11 @@ static int stmfx_gpio_direction_output(struct gpio_chip *gc, struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); u32 mask = get_mask(offset); + int ret; - stmfx_gpio_set(gc, offset, value); + ret = stmfx_gpio_set(gc, offset, value); + if (ret) + return ret; return regmap_write_bits(pctl->stmfx->map, reg, mask, mask); } @@ -694,7 +697,7 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev) pctl->gpio_chip.direction_input = stmfx_gpio_direction_input; pctl->gpio_chip.direction_output = stmfx_gpio_direction_output; pctl->gpio_chip.get = stmfx_gpio_get; - pctl->gpio_chip.set = stmfx_gpio_set; + pctl->gpio_chip.set_rv = stmfx_gpio_set; pctl->gpio_chip.set_config = gpiochip_generic_config; pctl->gpio_chip.base = -1; pctl->gpio_chip.ngpio = pctl->pctl_desc.npins; diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index 98262b8ce43a..d3a12c1c0de2 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -432,24 +432,25 @@ static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl, (value ? 0x1f : 0x10)); } -static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset, - int value) +static int sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) { struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); if (sx150x_pin_is_oscio(pctl, offset)) - sx150x_gpio_oscio_set(pctl, value); - else - __sx150x_gpio_set(pctl, offset, value); + return sx150x_gpio_oscio_set(pctl, value); + + return __sx150x_gpio_set(pctl, offset, value); } -static void sx150x_gpio_set_multiple(struct gpio_chip *chip, - unsigned long *mask, - unsigned long *bits) +static int sx150x_gpio_set_multiple(struct gpio_chip *chip, + unsigned long *mask, + unsigned long *bits) { struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); - regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask, *bits); + return regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask, + *bits); } static int sx150x_gpio_direction_input(struct gpio_chip *chip, @@ -1175,7 +1176,7 @@ static int sx150x_probe(struct i2c_client *client) pctl->gpio.direction_input = sx150x_gpio_direction_input; pctl->gpio.direction_output = sx150x_gpio_direction_output; pctl->gpio.get = sx150x_gpio_get; - pctl->gpio.set = sx150x_gpio_set; + pctl->gpio.set_rv = sx150x_gpio_set; pctl->gpio.set_config = gpiochip_generic_config; pctl->gpio.parent = dev; pctl->gpio.can_sleep = true; @@ -1190,7 +1191,7 @@ static int sx150x_probe(struct i2c_client *client) * would require locking that is not in place at this time. */ if (pctl->data->model != SX150X_789) - pctl->gpio.set_multiple = sx150x_gpio_set_multiple; + pctl->gpio.set_multiple_rv = sx150x_gpio_set_multiple; /* Add Interrupt support if an irq is specified */ if (client->irq > 0) { diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c index d6bb8f58978d..4edb20e61951 100644 --- a/drivers/pinctrl/pinctrl-tb10x.c +++ b/drivers/pinctrl/pinctrl-tb10x.c @@ -823,7 +823,7 @@ static struct platform_driver tb10x_pinctrl_pdrv = { .remove = tb10x_pinctrl_remove, .driver = { .name = "tb10x_pinctrl", - .of_match_table = of_match_ptr(tb10x_pinctrl_dt_ids), + .of_match_table = tb10x_pinctrl_dt_ids, } }; diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 0743190da59e..2c31e7f2a27a 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -236,18 +236,7 @@ static const char *pin_free(struct pinctrl_dev *pctldev, int pin, if (desc->mux_usecount) return NULL; } - } - - /* - * If there is no kind of request function for the pin we just assume - * we got it by default and proceed. - */ - if (gpio_range && ops->gpio_disable_free) - ops->gpio_disable_free(pctldev, gpio_range, pin); - else if (ops->free) - ops->free(pctldev, pin); - scoped_guard(mutex, &desc->mux_lock) { if (gpio_range) { owner = desc->gpio_owner; desc->gpio_owner = NULL; @@ -258,6 +247,15 @@ static const char *pin_free(struct pinctrl_dev *pctldev, int pin, } } + /* + * If there is no kind of request function for the pin we just assume + * we got it by default and proceed. + */ + if (gpio_range && ops->gpio_disable_free) + ops->gpio_disable_free(pctldev, gpio_range, pin); + else if (ops->free) + ops->free(pctldev, pin); + module_put(pctldev->owner); return owner; diff --git a/drivers/pinctrl/pxa/pinctrl-pxa2xx.c b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c index 9e34b92ff5f2..9fd7a8fb2bc4 100644 --- a/drivers/pinctrl/pxa/pinctrl-pxa2xx.c +++ b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c @@ -281,9 +281,8 @@ static int pxa2xx_build_functions(struct pxa_pinctrl *pctl) for (df = pctl->ppins[i].functions; df->name; df++) if (!pxa2xx_find_function(pctl, df->name, functions)) (functions + pctl->nfuncs++)->name = df->name; - pctl->functions = devm_kmemdup(pctl->dev, functions, - pctl->nfuncs * sizeof(*functions), - GFP_KERNEL); + pctl->functions = devm_kmemdup_array(pctl->dev, functions, pctl->nfuncs, + sizeof(*functions), GFP_KERNEL); if (!pctl->functions) return -ENOMEM; @@ -314,7 +313,8 @@ static int pxa2xx_build_groups(struct pxa_pinctrl *pctl) pctl->ppins[j].pin.name; func = pctl->functions + i; func->ngroups = ngroups; - func->groups = devm_kmemdup(pctl->dev, gtmp, ngroups * sizeof(*gtmp), GFP_KERNEL); + func->groups = devm_kmemdup_array(pctl->dev, gtmp, ngroups, + sizeof(*gtmp), GFP_KERNEL); if (!func->groups) return -ENOMEM; } diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm index 35f47660a56b..0bb44c9a4c06 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -138,10 +138,10 @@ config PINCTRL_MSM8916 Qualcomm TLMM block found on the Qualcomm 8916 platform. config PINCTRL_MSM8917 - tristate "Qualcomm 8917 pin controller driver" + tristate "Qualcomm 8917/8937 pin controller driver" help This is the pinctrl, pinmux, pinconf and gpiolib driver for the - Qualcomm TLMM block found on the Qualcomm MSM8917 platform. + Qualcomm TLMM block found on the Qualcomm MSM8917, MSM8937 platform. config PINCTRL_MSM8953 tristate "Qualcomm 8953 pin controller driver" @@ -437,4 +437,14 @@ config PINCTRL_X1E80100 Say Y here to compile statically, or M here to compile it as a module. If unsure, say N. +config PINCTRL_TLMM_TEST + tristate "Qualcomm TLMM test driver" + depends on ARM64 || COMPILE_TEST + depends on KUNIT + help + This driver provides test cases for the interrupt capabilities of + TLMM driver (pinctrl-msm). Specify a floating gpio to use for testing + using the module parameter "gpio" and execute the kunit suite. + If unsure, say N. + endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 5c4100925cf9..954f5291cc37 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -71,3 +71,4 @@ obj-$(CONFIG_PINCTRL_SM8750) += pinctrl-sm8750.o obj-$(CONFIG_PINCTRL_SC8280XP_LPASS_LPI) += pinctrl-sc8280xp-lpass-lpi.o obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o obj-$(CONFIG_PINCTRL_X1E80100) += pinctrl-x1e80100.o +obj-$(CONFIG_PINCTRL_TLMM_TEST) += tlmm-test.o diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c index 20c3b9025044..3654913f1ae5 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8064.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c @@ -629,7 +629,6 @@ static struct platform_driver apq8064_pinctrl_driver = { .of_match_table = apq8064_pinctrl_of_match, }, .probe = apq8064_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init apq8064_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-apq8084.c b/drivers/pinctrl/qcom/pinctrl-apq8084.c index 3fc0a40762b6..27693cd64881 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8084.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c @@ -1207,7 +1207,6 @@ static struct platform_driver apq8084_pinctrl_driver = { .of_match_table = apq8084_pinctrl_of_match, }, .probe = apq8084_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init apq8084_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c index 1f7944dd829d..6ede3149b6e1 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -710,7 +710,6 @@ static struct platform_driver ipq4019_pinctrl_driver = { .of_match_table = ipq4019_pinctrl_of_match, }, .probe = ipq4019_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init ipq4019_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5018.c b/drivers/pinctrl/qcom/pinctrl-ipq5018.c index e2951f81c3ee..10b99d5d8a11 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq5018.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq5018.c @@ -754,7 +754,6 @@ static struct platform_driver ipq5018_pinctrl_driver = { .of_match_table = ipq5018_pinctrl_of_match, }, .probe = ipq5018_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init ipq5018_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5332.c b/drivers/pinctrl/qcom/pinctrl-ipq5332.c index 625f8014051f..1ac2fc09c119 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq5332.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq5332.c @@ -834,7 +834,6 @@ static struct platform_driver ipq5332_pinctrl_driver = { .of_match_table = ipq5332_pinctrl_of_match, }, .probe = ipq5332_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init ipq5332_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5424.c b/drivers/pinctrl/qcom/pinctrl-ipq5424.c index 0d610b076da3..7ff1f8acc1a3 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq5424.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq5424.c @@ -791,7 +791,6 @@ static struct platform_driver ipq5424_pinctrl_driver = { .of_match_table = ipq5424_pinctrl_of_match, }, .probe = ipq5424_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init ipq5424_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-ipq6018.c b/drivers/pinctrl/qcom/pinctrl-ipq6018.c index 0ad08647dbcd..a4ba980252e1 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq6018.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq6018.c @@ -1080,7 +1080,6 @@ static struct platform_driver ipq6018_pinctrl_driver = { .of_match_table = ipq6018_pinctrl_of_match, }, .probe = ipq6018_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init ipq6018_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8064.c b/drivers/pinctrl/qcom/pinctrl-ipq8064.c index e2bb94e86aef..0a9e357e64c6 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c @@ -631,7 +631,6 @@ static struct platform_driver ipq8064_pinctrl_driver = { .of_match_table = ipq8064_pinctrl_of_match, }, .probe = ipq8064_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init ipq8064_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c b/drivers/pinctrl/qcom/pinctrl-ipq8074.c index 337f3a1c92c1..482f13282fc2 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq8074.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq8074.c @@ -1041,7 +1041,6 @@ static struct platform_driver ipq8074_pinctrl_driver = { .of_match_table = ipq8074_pinctrl_of_match, }, .probe = ipq8074_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init ipq8074_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-ipq9574.c b/drivers/pinctrl/qcom/pinctrl-ipq9574.c index e2491617b236..89c05d8eb550 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq9574.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq9574.c @@ -799,7 +799,6 @@ static struct platform_driver ipq9574_pinctrl_driver = { .of_match_table = ipq9574_pinctrl_of_match, }, .probe = ipq9574_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init ipq9574_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 7366aba5a199..57fefeb603f0 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -327,14 +327,14 @@ static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin) LPI_GPIO_VALUE_IN_MASK; } -static void lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) +static int lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) { struct lpi_pinctrl *state = gpiochip_get_data(chip); unsigned long config; config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); - lpi_config_set(state->ctrl, pin, &config, 1); + return lpi_config_set(state->ctrl, pin, &config, 1); } #ifdef CONFIG_DEBUG_FS @@ -398,7 +398,7 @@ static const struct gpio_chip lpi_gpio_template = { .direction_input = lpi_gpio_direction_input, .direction_output = lpi_gpio_direction_output, .get = lpi_gpio_get, - .set = lpi_gpio_set, + .set_rv = lpi_gpio_set, .request = gpiochip_generic_request, .free = gpiochip_generic_free, .dbg_show = lpi_gpio_dbg_show, diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9607.c b/drivers/pinctrl/qcom/pinctrl-mdm9607.c index e7cd3ef1cf3e..3e18ba124fed 100644 --- a/drivers/pinctrl/qcom/pinctrl-mdm9607.c +++ b/drivers/pinctrl/qcom/pinctrl-mdm9607.c @@ -1059,7 +1059,6 @@ static struct platform_driver mdm9607_pinctrl_driver = { .of_match_table = mdm9607_pinctrl_of_match, }, .probe = mdm9607_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init mdm9607_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9615.c b/drivers/pinctrl/qcom/pinctrl-mdm9615.c index 0a2ae383d3d5..bea1ca3d1b7f 100644 --- a/drivers/pinctrl/qcom/pinctrl-mdm9615.c +++ b/drivers/pinctrl/qcom/pinctrl-mdm9615.c @@ -446,7 +446,6 @@ static struct platform_driver mdm9615_pinctrl_driver = { .of_match_table = mdm9615_pinctrl_of_match, }, .probe = mdm9615_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init mdm9615_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 82f0cc43bbf4..f713c80d7f3e 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -44,7 +44,6 @@ * @pctrl: pinctrl handle. * @chip: gpiochip handle. * @desc: pin controller descriptor - * @restart_nb: restart notifier block. * @irq: parent irq for the TLMM irq_chip. * @intr_target_use_scm: route irq to application cpu using scm calls * @lock: Spinlock to protect register resources as well @@ -64,7 +63,6 @@ struct msm_pinctrl { struct pinctrl_dev *pctrl; struct gpio_chip chip; struct pinctrl_desc desc; - struct notifier_block restart_nb; int irq; @@ -637,7 +635,7 @@ static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) return !!(val & BIT(g->in_bit)); } -static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +static int msm_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { const struct msm_pingroup *g; struct msm_pinctrl *pctrl = gpiochip_get_data(chip); @@ -656,6 +654,8 @@ static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) msm_writel_io(val, pctrl, g); raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; } #ifdef CONFIG_DEBUG_FS @@ -792,7 +792,7 @@ static const struct gpio_chip msm_gpio_template = { .direction_output = msm_gpio_direction_output, .get_direction = msm_gpio_get_direction, .get = msm_gpio_get, - .set = msm_gpio_set, + .set_rv = msm_gpio_set, .request = gpiochip_generic_request, .free = gpiochip_generic_free, .dbg_show = msm_gpio_dbg_show, @@ -1038,6 +1038,25 @@ static bool msm_gpio_needs_dual_edge_parent_workaround(struct irq_data *d, test_bit(d->hwirq, pctrl->skip_wake_irqs); } +static void msm_gpio_irq_init_valid_mask(struct gpio_chip *gc, + unsigned long *valid_mask, + unsigned int ngpios) +{ + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_pingroup *g; + int i; + + bitmap_fill(valid_mask, ngpios); + + for (i = 0; i < ngpios; i++) { + g = &pctrl->soc->groups[i]; + + if (g->intr_detection_width != 1 && + g->intr_detection_width != 2) + clear_bit(i, valid_mask); + } +} + static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); @@ -1441,8 +1460,9 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_bad_irq; girq->parents[0] = pctrl->irq; + girq->init_valid_mask = msm_gpio_irq_init_valid_mask; - ret = gpiochip_add_data(&pctrl->chip, pctrl); + ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); if (ret) { dev_err(pctrl->dev, "Failed register gpiochip\n"); return ret; @@ -1463,7 +1483,6 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) dev_name(pctrl->dev), 0, 0, chip->ngpio); if (ret) { dev_err(pctrl->dev, "Failed to add pin range\n"); - gpiochip_remove(&pctrl->chip); return ret; } } @@ -1471,10 +1490,9 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) return 0; } -static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, - void *data) +static int msm_ps_hold_restart(struct sys_off_data *data) { - struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); + struct msm_pinctrl *pctrl = data->cb_data; writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); mdelay(1000); @@ -1485,7 +1503,11 @@ static struct msm_pinctrl *poweroff_pctrl; static void msm_ps_hold_poweroff(void) { - msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); + struct sys_off_data data = { + .cb_data = poweroff_pctrl, + }; + + msm_ps_hold_restart(&data); } static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) @@ -1495,9 +1517,11 @@ static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) for (i = 0; i < pctrl->soc->nfunctions; i++) if (!strcmp(func[i].name, "ps_hold")) { - pctrl->restart_nb.notifier_call = msm_ps_hold_restart; - pctrl->restart_nb.priority = 128; - if (register_restart_handler(&pctrl->restart_nb)) + if (devm_register_sys_off_handler(pctrl->dev, + SYS_OFF_MODE_RESTART, + 128, + msm_ps_hold_restart, + pctrl)) dev_err(pctrl->dev, "failed to setup restart handler.\n"); poweroff_pctrl = pctrl; @@ -1594,15 +1618,5 @@ int msm_pinctrl_probe(struct platform_device *pdev, } EXPORT_SYMBOL(msm_pinctrl_probe); -void msm_pinctrl_remove(struct platform_device *pdev) -{ - struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); - - gpiochip_remove(&pctrl->chip); - - unregister_restart_handler(&pctrl->restart_nb); -} -EXPORT_SYMBOL(msm_pinctrl_remove); - MODULE_DESCRIPTION("Qualcomm Technologies, Inc. TLMM driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 63852ed70295..d7dc0947bb16 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -171,6 +171,5 @@ extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; int msm_pinctrl_probe(struct platform_device *pdev, const struct msm_pinctrl_soc_data *soc_data); -void msm_pinctrl_remove(struct platform_device *pdev); #endif diff --git a/drivers/pinctrl/qcom/pinctrl-msm8226.c b/drivers/pinctrl/qcom/pinctrl-msm8226.c index 64fee70f1772..f9a957347340 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8226.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8226.c @@ -654,7 +654,6 @@ static struct platform_driver msm8226_pinctrl_driver = { .of_match_table = msm8226_pinctrl_of_match, }, .probe = msm8226_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init msm8226_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8660.c b/drivers/pinctrl/qcom/pinctrl-msm8660.c index 999a5f867eb5..4dbc19ffd80e 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8660.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8660.c @@ -981,7 +981,6 @@ static struct platform_driver msm8660_pinctrl_driver = { .of_match_table = msm8660_pinctrl_of_match, }, .probe = msm8660_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init msm8660_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8909.c b/drivers/pinctrl/qcom/pinctrl-msm8909.c index 756856d20d6b..0aa4f77b774f 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8909.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8909.c @@ -929,7 +929,6 @@ static struct platform_driver msm8909_pinctrl_driver = { .of_match_table = msm8909_pinctrl_of_match, }, .probe = msm8909_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init msm8909_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8916.c b/drivers/pinctrl/qcom/pinctrl-msm8916.c index cea5c54f92fe..0dfc6dd33d58 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8916.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c @@ -969,7 +969,6 @@ static struct platform_driver msm8916_pinctrl_driver = { .of_match_table = msm8916_pinctrl_of_match, }, .probe = msm8916_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init msm8916_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8917.c b/drivers/pinctrl/qcom/pinctrl-msm8917.c index cff137bb3b23..2e1a94ab18b2 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8917.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8917.c @@ -539,6 +539,7 @@ enum msm8917_functions { msm_mux_webcam_standby, msm_mux_wsa_io, msm_mux_wsa_irq, + msm_mux_wsa_reset, msm_mux__, }; @@ -1123,6 +1124,10 @@ static const char * const wsa_io_groups[] = { "gpio94", "gpio95", }; +static const char * const wsa_reset_groups[] = { + "gpio96", +}; + static const char * const blsp_spi8_groups[] = { "gpio96", "gpio97", "gpio98", "gpio99", }; @@ -1378,6 +1383,7 @@ static const struct pinfunction msm8917_functions[] = { MSM_PIN_FUNCTION(webcam_standby), MSM_PIN_FUNCTION(wsa_io), MSM_PIN_FUNCTION(wsa_irq), + MSM_PIN_FUNCTION(wsa_reset), }; static const struct msm_pingroup msm8917_groups[] = { @@ -1601,7 +1607,6 @@ static struct platform_driver msm8917_pinctrl_driver = { .of_match_table = msm8917_pinctrl_of_match, }, .probe = msm8917_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init msm8917_pinctrl_init(void) @@ -1616,5 +1621,5 @@ static void __exit msm8917_pinctrl_exit(void) } module_exit(msm8917_pinctrl_exit); -MODULE_DESCRIPTION("Qualcomm msm8917 pinctrl driver"); +MODULE_DESCRIPTION("Qualcomm msm8917/msm8937 pinctrl driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8953.c b/drivers/pinctrl/qcom/pinctrl-msm8953.c index 998351bdfee1..956383341a7a 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8953.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8953.c @@ -1816,7 +1816,6 @@ static struct platform_driver msm8953_pinctrl_driver = { .of_match_table = msm8953_pinctrl_of_match, }, .probe = msm8953_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init msm8953_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8960.c b/drivers/pinctrl/qcom/pinctrl-msm8960.c index ebe230b3b437..a937ea867de7 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8960.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c @@ -1246,7 +1246,6 @@ static struct platform_driver msm8960_pinctrl_driver = { .of_match_table = msm8960_pinctrl_of_match, }, .probe = msm8960_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init msm8960_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8976.c b/drivers/pinctrl/qcom/pinctrl-msm8976.c index c30d80e4e98c..3bcb03387781 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8976.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8976.c @@ -1096,7 +1096,6 @@ static struct platform_driver msm8976_pinctrl_driver = { .of_match_table = msm8976_pinctrl_of_match, }, .probe = msm8976_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init msm8976_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8994.c b/drivers/pinctrl/qcom/pinctrl-msm8994.c index b1a6759ab4a5..7a3b6cbccb68 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8994.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8994.c @@ -1343,7 +1343,6 @@ static struct platform_driver msm8994_pinctrl_driver = { .of_match_table = msm8994_pinctrl_of_match, }, .probe = msm8994_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init msm8994_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8996.c b/drivers/pinctrl/qcom/pinctrl-msm8996.c index 1b5d80eaab83..d86d83106d3b 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8996.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8996.c @@ -1920,7 +1920,6 @@ static struct platform_driver msm8996_pinctrl_driver = { .of_match_table = msm8996_pinctrl_of_match, }, .probe = msm8996_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init msm8996_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8998.c b/drivers/pinctrl/qcom/pinctrl-msm8998.c index b7cbf32b3125..1daee815888f 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8998.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8998.c @@ -1535,7 +1535,6 @@ static struct platform_driver msm8998_pinctrl_driver = { .of_match_table = msm8998_pinctrl_of_match, }, .probe = msm8998_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init msm8998_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c index 238c83f6ec4f..8253aa25775b 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c @@ -1083,7 +1083,6 @@ static struct platform_driver msm8x74_pinctrl_driver = { .of_match_table = msm8x74_pinctrl_of_match, }, .probe = msm8x74_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init msm8x74_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c b/drivers/pinctrl/qcom/pinctrl-qcm2290.c index ba699eac9ee8..eeeec6434f6a 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcm2290.c +++ b/drivers/pinctrl/qcom/pinctrl-qcm2290.c @@ -37,6 +37,8 @@ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ .oe_bit = 9, \ .in_bit = 0, \ .out_bit = 1, \ @@ -165,6 +167,10 @@ static const struct pinctrl_pin_desc qcm2290_pins[] = { PINCTRL_PIN(62, "GPIO_62"), PINCTRL_PIN(63, "GPIO_63"), PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), PINCTRL_PIN(69, "GPIO_69"), PINCTRL_PIN(70, "GPIO_70"), PINCTRL_PIN(71, "GPIO_71"), @@ -179,12 +185,17 @@ static const struct pinctrl_pin_desc qcm2290_pins[] = { PINCTRL_PIN(80, "GPIO_80"), PINCTRL_PIN(81, "GPIO_81"), PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), PINCTRL_PIN(86, "GPIO_86"), PINCTRL_PIN(87, "GPIO_87"), PINCTRL_PIN(88, "GPIO_88"), PINCTRL_PIN(89, "GPIO_89"), PINCTRL_PIN(90, "GPIO_90"), PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), PINCTRL_PIN(94, "GPIO_94"), PINCTRL_PIN(95, "GPIO_95"), PINCTRL_PIN(96, "GPIO_96"), @@ -387,6 +398,7 @@ enum qcm2290_functions { msm_mux_ddr_pxi1, msm_mux_ddr_pxi2, msm_mux_ddr_pxi3, + msm_mux_egpio, msm_mux_gcc_gp1, msm_mux_gcc_gp2, msm_mux_gcc_gp3, @@ -816,6 +828,13 @@ static const char * const sd_write_groups[] = { static const char * const jitter_bist_groups[] = { "gpio96", "gpio97", }; +static const char * const egpio_groups[] = { + "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", + "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", + "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", + "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", +}; static const char * const ddr_pxi2_groups[] = { "gpio102", "gpio103", }; @@ -851,6 +870,7 @@ static const struct pinfunction qcm2290_functions[] = { MSM_PIN_FUNCTION(ddr_pxi1), MSM_PIN_FUNCTION(ddr_pxi2), MSM_PIN_FUNCTION(ddr_pxi3), + MSM_PIN_FUNCTION(egpio), MSM_PIN_FUNCTION(gcc_gp1), MSM_PIN_FUNCTION(gcc_gp2), MSM_PIN_FUNCTION(gcc_gp3), @@ -1037,35 +1057,35 @@ static const struct msm_pingroup qcm2290_groups[] = { [95] = PINGROUP(95, nav_gpio, gp_pdm0, qdss_gpio, wlan1_adc1, _, _, _, _, _), [96] = PINGROUP(96, qup4, nav_gpio, mdp_vsync, gp_pdm1, sd_write, jitter_bist, qdss_cti, qdss_cti, _), [97] = PINGROUP(97, qup4, nav_gpio, mdp_vsync, gp_pdm2, jitter_bist, qdss_cti, qdss_cti, _, _), - [98] = PINGROUP(98, _, _, _, _, _, _, _, _, _), - [99] = PINGROUP(99, _, _, _, _, _, _, _, _, _), - [100] = PINGROUP(100, atest, _, _, _, _, _, _, _, _), - [101] = PINGROUP(101, atest, _, _, _, _, _, _, _, _), - [102] = PINGROUP(102, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _), - [103] = PINGROUP(103, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _), - [104] = PINGROUP(104, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, pwm_8, _, _), - [105] = PINGROUP(105, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _), - [106] = PINGROUP(106, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, _), - [107] = PINGROUP(107, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, _), - [108] = PINGROUP(108, nav_gpio, _, _, _, _, _, _, _, _), - [109] = PINGROUP(109, _, qdss_gpio, _, _, _, _, _, _, _), - [110] = PINGROUP(110, _, qdss_gpio, _, _, _, _, _, _, _), - [111] = PINGROUP(111, _, _, _, _, _, _, _, _, _), - [112] = PINGROUP(112, _, _, _, _, _, _, _, _, _), - [113] = PINGROUP(113, _, _, _, _, _, _, _, _, _), - [114] = PINGROUP(114, _, _, _, _, _, _, _, _, _), - [115] = PINGROUP(115, _, pwm_9, _, _, _, _, _, _, _), - [116] = PINGROUP(116, _, _, _, _, _, _, _, _, _), - [117] = PINGROUP(117, _, _, _, _, _, _, _, _, _), - [118] = PINGROUP(118, _, _, _, _, _, _, _, _, _), - [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _), - [120] = PINGROUP(120, _, _, _, _, _, _, _, _, _), - [121] = PINGROUP(121, _, _, _, _, _, _, _, _, _), - [122] = PINGROUP(122, _, _, _, _, _, _, _, _, _), - [123] = PINGROUP(123, _, _, _, _, _, _, _, _, _), - [124] = PINGROUP(124, _, _, _, _, _, _, _, _, _), - [125] = PINGROUP(125, _, _, _, _, _, _, _, _, _), - [126] = PINGROUP(126, _, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, _, _, _, _, _, _, _, _, egpio), + [99] = PINGROUP(99, _, _, _, _, _, _, _, _, egpio), + [100] = PINGROUP(100, atest, _, _, _, _, _, _, _, egpio), + [101] = PINGROUP(101, atest, _, _, _, _, _, _, _, egpio), + [102] = PINGROUP(102, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, egpio), + [103] = PINGROUP(103, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, egpio), + [104] = PINGROUP(104, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, pwm_8, _, egpio), + [105] = PINGROUP(105, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, egpio), + [106] = PINGROUP(106, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, egpio), + [107] = PINGROUP(107, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, egpio), + [108] = PINGROUP(108, nav_gpio, _, _, _, _, _, _, _, egpio), + [109] = PINGROUP(109, _, qdss_gpio, _, _, _, _, _, _, egpio), + [110] = PINGROUP(110, _, qdss_gpio, _, _, _, _, _, _, egpio), + [111] = PINGROUP(111, _, _, _, _, _, _, _, _, egpio), + [112] = PINGROUP(112, _, _, _, _, _, _, _, _, egpio), + [113] = PINGROUP(113, _, _, _, _, _, _, _, _, egpio), + [114] = PINGROUP(114, _, _, _, _, _, _, _, _, egpio), + [115] = PINGROUP(115, _, pwm_9, _, _, _, _, _, _, egpio), + [116] = PINGROUP(116, _, _, _, _, _, _, _, _, egpio), + [117] = PINGROUP(117, _, _, _, _, _, _, _, _, egpio), + [118] = PINGROUP(118, _, _, _, _, _, _, _, _, egpio), + [119] = PINGROUP(119, _, _, _, _, _, _, _, _, egpio), + [120] = PINGROUP(120, _, _, _, _, _, _, _, _, egpio), + [121] = PINGROUP(121, _, _, _, _, _, _, _, _, egpio), + [122] = PINGROUP(122, _, _, _, _, _, _, _, _, egpio), + [123] = PINGROUP(123, _, _, _, _, _, _, _, _, egpio), + [124] = PINGROUP(124, _, _, _, _, _, _, _, _, egpio), + [125] = PINGROUP(125, _, _, _, _, _, _, _, _, egpio), + [126] = PINGROUP(126, _, _, _, _, _, _, _, _, egpio), [127] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x84004, 0, 0), [128] = SDC_QDSD_PINGROUP(sdc1_clk, 0x84000, 13, 6), [129] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x84000, 11, 3), @@ -1095,6 +1115,7 @@ static const struct msm_pinctrl_soc_data qcm2290_pinctrl = { .ngpios = 127, .wakeirq_map = qcm2290_mpm_map, .nwakeirq_map = ARRAY_SIZE(qcm2290_mpm_map), + .egpio_func = 9, }; static int qcm2290_pinctrl_probe(struct platform_device *pdev) @@ -1113,7 +1134,6 @@ static struct platform_driver qcm2290_pinctrl_driver = { .of_match_table = qcm2290_pinctrl_of_match, }, .probe = qcm2290_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init qcm2290_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c index ae7224012f8a..54e3b4435349 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -1644,7 +1644,6 @@ static struct platform_driver qcs404_pinctrl_driver = { .of_match_table = qcs404_pinctrl_of_match, }, .probe = qcs404_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init qcs404_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-qcs615.c b/drivers/pinctrl/qcom/pinctrl-qcs615.c index 23015b055f6a..2a943bc46a62 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs615.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs615.c @@ -1062,7 +1062,7 @@ static const struct msm_pinctrl_soc_data qcs615_tlmm = { .nfunctions = ARRAY_SIZE(qcs615_functions), .groups = qcs615_groups, .ngroups = ARRAY_SIZE(qcs615_groups), - .ngpios = 123, + .ngpios = 124, .tiles = qcs615_tiles, .ntiles = ARRAY_SIZE(qcs615_tiles), .wakeirq_map = qcs615_pdc_map, @@ -1087,7 +1087,6 @@ static struct platform_driver qcs615_tlmm_driver = { .of_match_table = qcs615_tlmm_of_match, }, .probe = qcs615_tlmm_probe, - .remove = msm_pinctrl_remove, }; static int __init qcs615_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-qcs8300.c b/drivers/pinctrl/qcom/pinctrl-qcs8300.c index ba6de944a859..d6437e26392b 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs8300.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs8300.c @@ -1204,7 +1204,7 @@ static const struct msm_pinctrl_soc_data qcs8300_pinctrl = { .nfunctions = ARRAY_SIZE(qcs8300_functions), .groups = qcs8300_groups, .ngroups = ARRAY_SIZE(qcs8300_groups), - .ngpios = 133, + .ngpios = 134, .wakeirq_map = qcs8300_pdc_map, .nwakeirq_map = ARRAY_SIZE(qcs8300_pdc_map), .egpio_func = 11, @@ -1227,7 +1227,6 @@ static struct platform_driver qcs8300_pinctrl_driver = { .of_match_table = qcs8300_pinctrl_of_match, }, .probe = qcs8300_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init qcs8300_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c index b5808fcfb13c..9ecc4d40e4dc 100644 --- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c +++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c @@ -145,7 +145,6 @@ static struct platform_driver qdf2xxx_pinctrl_driver = { .acpi_match_table = qdf2xxx_acpi_ids, }, .probe = qdf2xxx_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init qdf2xxx_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-qdu1000.c b/drivers/pinctrl/qcom/pinctrl-qdu1000.c index 47bc529ef550..eacb89fa3888 100644 --- a/drivers/pinctrl/qcom/pinctrl-qdu1000.c +++ b/drivers/pinctrl/qcom/pinctrl-qdu1000.c @@ -1248,7 +1248,6 @@ static struct platform_driver qdu1000_tlmm_driver = { .of_match_table = qdu1000_tlmm_of_match, }, .probe = qdu1000_tlmm_probe, - .remove = msm_pinctrl_remove, }; static int __init qdu1000_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p.c b/drivers/pinctrl/qcom/pinctrl-sa8775p.c index 8fdea25d8d67..1b62eb3e6620 100644 --- a/drivers/pinctrl/qcom/pinctrl-sa8775p.c +++ b/drivers/pinctrl/qcom/pinctrl-sa8775p.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022,2025, Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2023, Linaro Limited */ @@ -467,6 +467,7 @@ enum sa8775p_functions { msm_mux_edp2_lcd, msm_mux_edp3_hot, msm_mux_edp3_lcd, + msm_mux_egpio, msm_mux_emac0_mcg0, msm_mux_emac0_mcg1, msm_mux_emac0_mcg2, @@ -744,6 +745,13 @@ static const char * const edp3_lcd_groups[] = { "gpio49", }; +static const char *const egpio_groups[] = { + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", + "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", + "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", +}; + static const char * const emac0_mcg0_groups[] = { "gpio12", }; @@ -1209,6 +1217,7 @@ static const struct pinfunction sa8775p_functions[] = { MSM_PIN_FUNCTION(edp2_lcd), MSM_PIN_FUNCTION(edp3_hot), MSM_PIN_FUNCTION(edp3_lcd), + MSM_PIN_FUNCTION(egpio), MSM_PIN_FUNCTION(emac0_mcg0), MSM_PIN_FUNCTION(emac0_mcg1), MSM_PIN_FUNCTION(emac0_mcg2), @@ -1454,29 +1463,29 @@ static const struct msm_pingroup sa8775p_groups[] = { [123] = PINGROUP(123, hs2_mi2s, phase_flag, _, _, _, _, _, _, _), [124] = PINGROUP(124, hs2_mi2s, phase_flag, _, _, _, _, _, _, _), [125] = PINGROUP(125, hs2_mi2s, phase_flag, _, _, _, _, _, _, _), - [126] = PINGROUP(126, _, _, _, _, _, _, _, _, _), - [127] = PINGROUP(127, _, _, _, _, _, _, _, _, _), - [128] = PINGROUP(128, _, _, _, _, _, _, _, _, _), - [129] = PINGROUP(129, _, _, _, _, _, _, _, _, _), - [130] = PINGROUP(130, _, _, _, _, _, _, _, _, _), - [131] = PINGROUP(131, _, _, _, _, _, _, _, _, _), - [132] = PINGROUP(132, _, _, _, _, _, _, _, _, _), - [133] = PINGROUP(133, _, _, _, _, _, _, _, _, _), - [134] = PINGROUP(134, _, _, _, _, _, _, _, _, _), - [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _), - [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _), - [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _), - [138] = PINGROUP(138, _, _, _, _, _, _, _, _, _), - [139] = PINGROUP(139, _, _, _, _, _, _, _, _, _), - [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _), - [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _), - [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _), - [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _), - [144] = PINGROUP(144, dbg_out, _, _, _, _, _, _, _, _), - [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _), - [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), - [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), - [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, _, _, _, _, _, _, _, _, egpio), + [127] = PINGROUP(127, _, _, _, _, _, _, _, _, egpio), + [128] = PINGROUP(128, _, _, _, _, _, _, _, _, egpio), + [129] = PINGROUP(129, _, _, _, _, _, _, _, _, egpio), + [130] = PINGROUP(130, _, _, _, _, _, _, _, _, egpio), + [131] = PINGROUP(131, _, _, _, _, _, _, _, _, egpio), + [132] = PINGROUP(132, _, _, _, _, _, _, _, _, egpio), + [133] = PINGROUP(133, _, _, _, _, _, _, _, _, egpio), + [134] = PINGROUP(134, _, _, _, _, _, _, _, _, egpio), + [135] = PINGROUP(135, _, _, _, _, _, _, _, _, egpio), + [136] = PINGROUP(136, _, _, _, _, _, _, _, _, egpio), + [137] = PINGROUP(137, _, _, _, _, _, _, _, _, egpio), + [138] = PINGROUP(138, _, _, _, _, _, _, _, _, egpio), + [139] = PINGROUP(139, _, _, _, _, _, _, _, _, egpio), + [140] = PINGROUP(140, _, _, _, _, _, _, _, _, egpio), + [141] = PINGROUP(141, _, _, _, _, _, _, _, _, egpio), + [142] = PINGROUP(142, _, _, _, _, _, _, _, _, egpio), + [143] = PINGROUP(143, _, _, _, _, _, _, _, _, egpio), + [144] = PINGROUP(144, dbg_out, _, _, _, _, _, _, _, egpio), + [145] = PINGROUP(145, _, _, _, _, _, _, _, _, egpio), + [146] = PINGROUP(146, _, _, _, _, _, _, _, _, egpio), + [147] = PINGROUP(147, _, _, _, _, _, _, _, _, egpio), + [148] = PINGROUP(148, _, _, _, _, _, _, _, _, egpio), [149] = UFS_RESET(ufs_reset, 0x1a2000), [150] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x199000, 15, 0), [151] = SDC_QDSD_PINGROUP(sdc1_clk, 0x199000, 13, 6), @@ -1511,6 +1520,7 @@ static const struct msm_pinctrl_soc_data sa8775p_pinctrl = { .ngpios = 150, .wakeirq_map = sa8775p_pdc_map, .nwakeirq_map = ARRAY_SIZE(sa8775p_pdc_map), + .egpio_func = 9, }; static int sa8775p_pinctrl_probe(struct platform_device *pdev) @@ -1530,7 +1540,6 @@ static struct platform_driver sa8775p_pinctrl_driver = { .of_match_table = sa8775p_pinctrl_of_match, }, .probe = sa8775p_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init sa8775p_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sar2130p.c b/drivers/pinctrl/qcom/pinctrl-sar2130p.c index 19a2e37826c7..3dd1b5e5cfee 100644 --- a/drivers/pinctrl/qcom/pinctrl-sar2130p.c +++ b/drivers/pinctrl/qcom/pinctrl-sar2130p.c @@ -1486,7 +1486,6 @@ static struct platform_driver sar2130p_tlmm_driver = { .of_match_table = sar2130p_tlmm_of_match, }, .probe = sar2130p_tlmm_probe, - .remove = msm_pinctrl_remove, }; static int __init sar2130p_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sc7180.c b/drivers/pinctrl/qcom/pinctrl-sc7180.c index 6eb0c73791c0..c43fe10b71ad 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7180.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7180.c @@ -1159,7 +1159,6 @@ static struct platform_driver sc7180_pinctrl_driver = { .of_match_table = sc7180_pinctrl_of_match, }, .probe = sc7180_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init sc7180_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c b/drivers/pinctrl/qcom/pinctrl-sc7280.c index 0c10eeb60b55..1b070e9d41f5 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c @@ -1505,7 +1505,6 @@ static struct platform_driver sc7280_pinctrl_driver = { .of_match_table = sc7280_pinctrl_of_match, }, .probe = sc7280_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init sc7280_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sc8180x.c b/drivers/pinctrl/qcom/pinctrl-sc8180x.c index d6a79ad41a40..26dd165d1543 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8180x.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8180x.c @@ -1720,7 +1720,6 @@ static struct platform_driver sc8180x_pinctrl_driver = { .acpi_match_table = sc8180x_pinctrl_acpi_match, }, .probe = sc8180x_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init sc8180x_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp.c b/drivers/pinctrl/qcom/pinctrl-sc8280xp.c index 96f4fb5a5d29..6ccd7e5648d4 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8280xp.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp.c @@ -1926,7 +1926,6 @@ static struct platform_driver sc8280xp_pinctrl_driver = { .of_match_table = sc8280xp_pinctrl_of_match, }, .probe = sc8280xp_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init sc8280xp_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660.c b/drivers/pinctrl/qcom/pinctrl-sdm660.c index 907e4ffca5e7..1a78288f1bc8 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm660.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm660.c @@ -1442,7 +1442,6 @@ static struct platform_driver sdm660_pinctrl_driver = { .of_match_table = sdm660_pinctrl_of_match, }, .probe = sdm660_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init sdm660_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sdm670.c b/drivers/pinctrl/qcom/pinctrl-sdm670.c index c76183ba95e1..0fe1fa94cd6d 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm670.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm670.c @@ -1337,7 +1337,6 @@ static struct platform_driver sdm670_pinctrl_driver = { .of_match_table = sdm670_pinctrl_of_match, }, .probe = sdm670_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init sdm670_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index cc05c415ed15..0446e291aa48 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -1351,7 +1351,6 @@ static struct platform_driver sdm845_pinctrl_driver = { .acpi_match_table = ACPI_PTR(sdm845_pinctrl_acpi_match), }, .probe = sdm845_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init sdm845_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sdx55.c b/drivers/pinctrl/qcom/pinctrl-sdx55.c index 8826db9d21d0..2c17bf889146 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdx55.c +++ b/drivers/pinctrl/qcom/pinctrl-sdx55.c @@ -990,7 +990,6 @@ static struct platform_driver sdx55_pinctrl_driver = { .of_match_table = sdx55_pinctrl_of_match, }, .probe = sdx55_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init sdx55_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sdx65.c b/drivers/pinctrl/qcom/pinctrl-sdx65.c index f6f319c997fc..85b5c0206dbd 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdx65.c +++ b/drivers/pinctrl/qcom/pinctrl-sdx65.c @@ -939,7 +939,6 @@ static struct platform_driver sdx65_pinctrl_driver = { .of_match_table = sdx65_pinctrl_of_match, }, .probe = sdx65_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init sdx65_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sdx75.c b/drivers/pinctrl/qcom/pinctrl-sdx75.c index 3cfe8c7f04df..ab13a3a57a83 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdx75.c +++ b/drivers/pinctrl/qcom/pinctrl-sdx75.c @@ -1124,7 +1124,6 @@ static struct platform_driver sdx75_pinctrl_driver = { .of_match_table = sdx75_pinctrl_of_match, }, .probe = sdx75_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init sdx75_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm4450.c b/drivers/pinctrl/qcom/pinctrl-sm4450.c index 622f20e6f6f8..1ecdf1ab4f27 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm4450.c +++ b/drivers/pinctrl/qcom/pinctrl-sm4450.c @@ -994,7 +994,6 @@ static struct platform_driver sm4450_tlmm_driver = { .of_match_table = sm4450_tlmm_of_match, }, .probe = sm4450_tlmm_probe, - .remove = msm_pinctrl_remove, }; MODULE_DEVICE_TABLE(of, sm4450_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115.c b/drivers/pinctrl/qcom/pinctrl-sm6115.c index 4e91c75ad952..c273efa43996 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6115.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6115.c @@ -907,7 +907,6 @@ static struct platform_driver sm6115_tlmm_driver = { .of_match_table = sm6115_tlmm_of_match, }, .probe = sm6115_tlmm_probe, - .remove = msm_pinctrl_remove, }; static int __init sm6115_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm6125.c b/drivers/pinctrl/qcom/pinctrl-sm6125.c index c188842047aa..5092f20e0c1b 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6125.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6125.c @@ -1266,7 +1266,6 @@ static struct platform_driver sm6125_tlmm_driver = { .of_match_table = sm6125_tlmm_of_match, }, .probe = sm6125_tlmm_probe, - .remove = msm_pinctrl_remove, }; static int __init sm6125_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350.c b/drivers/pinctrl/qcom/pinctrl-sm6350.c index f3828c07b134..ba4686c86c54 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6350.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6350.c @@ -1373,7 +1373,6 @@ static struct platform_driver sm6350_tlmm_driver = { .of_match_table = sm6350_tlmm_of_match, }, .probe = sm6350_tlmm_probe, - .remove = msm_pinctrl_remove, }; static int __init sm6350_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm6375.c b/drivers/pinctrl/qcom/pinctrl-sm6375.c index c82c8516932e..49031571e65e 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6375.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6375.c @@ -1516,7 +1516,6 @@ static struct platform_driver sm6375_tlmm_driver = { .of_match_table = sm6375_tlmm_of_match, }, .probe = sm6375_tlmm_probe, - .remove = msm_pinctrl_remove, }; static int __init sm6375_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm7150.c b/drivers/pinctrl/qcom/pinctrl-sm7150.c index 3c7fd8af6635..6e89966cd70e 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm7150.c +++ b/drivers/pinctrl/qcom/pinctrl-sm7150.c @@ -1255,7 +1255,6 @@ static struct platform_driver sm7150_tlmm_driver = { .of_match_table = sm7150_tlmm_of_match, }, .probe = sm7150_tlmm_probe, - .remove = msm_pinctrl_remove, }; static int __init sm7150_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c index 01aea9c70b7a..794ed99463f7 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8150.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c @@ -1542,7 +1542,6 @@ static struct platform_driver sm8150_pinctrl_driver = { .of_match_table = sm8150_pinctrl_of_match, }, .probe = sm8150_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init sm8150_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c index e9961a49ff98..fb6f005d64f5 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8250.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c @@ -1351,7 +1351,6 @@ static struct platform_driver sm8250_pinctrl_driver = { .of_match_table = sm8250_pinctrl_of_match, }, .probe = sm8250_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init sm8250_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350.c b/drivers/pinctrl/qcom/pinctrl-sm8350.c index 9c69458bd910..c8a3f39ce6f1 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8350.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8350.c @@ -1642,7 +1642,6 @@ static struct platform_driver sm8350_tlmm_driver = { .of_match_table = sm8350_tlmm_of_match, }, .probe = sm8350_tlmm_probe, - .remove = msm_pinctrl_remove, }; static int __init sm8350_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450.c b/drivers/pinctrl/qcom/pinctrl-sm8450.c index d11bb1ee9e3d..f2e52d5a0f93 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450.c @@ -1677,7 +1677,6 @@ static struct platform_driver sm8450_tlmm_driver = { .of_match_table = sm8450_tlmm_of_match, }, .probe = sm8450_tlmm_probe, - .remove = msm_pinctrl_remove, }; static int __init sm8450_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c index 3c847d9cb5d9..1b4496cb39eb 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c @@ -1762,7 +1762,6 @@ static struct platform_driver sm8550_tlmm_driver = { .of_match_table = sm8550_tlmm_of_match, }, .probe = sm8550_tlmm_probe, - .remove = msm_pinctrl_remove, }; static int __init sm8550_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c b/drivers/pinctrl/qcom/pinctrl-sm8650.c index 104708252d12..449a0077f4b1 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8650.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c @@ -1742,7 +1742,6 @@ static struct platform_driver sm8650_tlmm_driver = { .of_match_table = sm8650_tlmm_of_match, }, .probe = sm8650_tlmm_probe, - .remove = msm_pinctrl_remove, }; static int __init sm8650_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-sm8750.c b/drivers/pinctrl/qcom/pinctrl-sm8750.c index 1af11cd95fb0..8516693d1db5 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8750.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8750.c @@ -46,7 +46,9 @@ .out_bit = 1, \ .intr_enable_bit = 0, \ .intr_status_bit = 0, \ - .intr_target_bit = 5, \ + .intr_wakeup_present_bit = 6, \ + .intr_wakeup_enable_bit = 7, \ + .intr_target_bit = 8, \ .intr_target_kpss_val = 3, \ .intr_raw_status_bit = 4, \ .intr_polarity_bit = 1, \ @@ -1709,7 +1711,6 @@ static struct platform_driver sm8750_tlmm_driver = { .of_match_table = sm8750_tlmm_of_match, }, .probe = sm8750_tlmm_probe, - .remove = msm_pinctrl_remove, }; static int __init sm8750_tlmm_init(void) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index c8ce61066070..bc082bfb52ef 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -764,14 +764,14 @@ static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin) return !!pad->out_value; } -static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value) +static int pmic_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) { struct pmic_gpio_state *state = gpiochip_get_data(chip); unsigned long config; config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); - pmic_gpio_config_set(state->ctrl, pin, &config, 1); + return pmic_gpio_config_set(state->ctrl, pin, &config, 1); } static int pmic_gpio_of_xlate(struct gpio_chip *chip, @@ -802,7 +802,7 @@ static const struct gpio_chip pmic_gpio_gpio_template = { .direction_input = pmic_gpio_direction_input, .direction_output = pmic_gpio_direction_output, .get = pmic_gpio_get, - .set = pmic_gpio_set, + .set_rv = pmic_gpio_set, .request = gpiochip_generic_request, .free = gpiochip_generic_free, .of_xlate = pmic_gpio_of_xlate, diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index 7b28c5fb2402..ba9084978f90 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -600,14 +600,14 @@ static int pmic_mpp_get(struct gpio_chip *chip, unsigned pin) return !!pad->out_value; } -static void pmic_mpp_set(struct gpio_chip *chip, unsigned pin, int value) +static int pmic_mpp_set(struct gpio_chip *chip, unsigned int pin, int value) { struct pmic_mpp_state *state = gpiochip_get_data(chip); unsigned long config; config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); - pmic_mpp_config_set(state->ctrl, pin, &config, 1); + return pmic_mpp_config_set(state->ctrl, pin, &config, 1); } static int pmic_mpp_of_xlate(struct gpio_chip *chip, @@ -638,7 +638,7 @@ static const struct gpio_chip pmic_mpp_gpio_template = { .direction_input = pmic_mpp_direction_input, .direction_output = pmic_mpp_direction_output, .get = pmic_mpp_get, - .set = pmic_mpp_set, + .set_rv = pmic_mpp_set, .request = gpiochip_generic_request, .free = gpiochip_generic_free, .of_xlate = pmic_mpp_of_xlate, diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index 82679417e25f..3a8014ebf064 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -507,7 +507,8 @@ static int pm8xxx_gpio_get(struct gpio_chip *chip, unsigned offset) return ret; } -static void pm8xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +static int pm8xxx_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) { struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip); struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; @@ -519,7 +520,7 @@ static void pm8xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value) val |= pin->open_drain << 1; val |= pin->output_value; - pm8xxx_write_bank(pctrl, pin, 1, val); + return pm8xxx_write_bank(pctrl, pin, 1, val); } static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip, @@ -596,7 +597,7 @@ static const struct gpio_chip pm8xxx_gpio_template = { .direction_input = pm8xxx_gpio_direction_input, .direction_output = pm8xxx_gpio_direction_output, .get = pm8xxx_gpio_get, - .set = pm8xxx_gpio_set, + .set_rv = pm8xxx_gpio_set, .of_xlate = pm8xxx_gpio_of_xlate, .dbg_show = pm8xxx_gpio_dbg_show, .owner = THIS_MODULE, diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index 4841bbfe4864..087c37d304fc 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -511,14 +511,15 @@ static int pm8xxx_mpp_get(struct gpio_chip *chip, unsigned offset) return ret; } -static void pm8xxx_mpp_set(struct gpio_chip *chip, unsigned offset, int value) +static int pm8xxx_mpp_set(struct gpio_chip *chip, unsigned int offset, + int value) { struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; pin->output_value = !!value; - pm8xxx_mpp_update(pctrl, pin); + return pm8xxx_mpp_update(pctrl, pin); } static int pm8xxx_mpp_of_xlate(struct gpio_chip *chip, @@ -633,7 +634,7 @@ static const struct gpio_chip pm8xxx_mpp_template = { .direction_input = pm8xxx_mpp_direction_input, .direction_output = pm8xxx_mpp_direction_output, .get = pm8xxx_mpp_get, - .set = pm8xxx_mpp_set, + .set_rv = pm8xxx_mpp_set, .of_xlate = pm8xxx_mpp_of_xlate, .dbg_show = pm8xxx_mpp_dbg_show, .owner = THIS_MODULE, diff --git a/drivers/pinctrl/qcom/pinctrl-x1e80100.c b/drivers/pinctrl/qcom/pinctrl-x1e80100.c index 419cb8facb2f..d4b215f34c39 100644 --- a/drivers/pinctrl/qcom/pinctrl-x1e80100.c +++ b/drivers/pinctrl/qcom/pinctrl-x1e80100.c @@ -1861,7 +1861,6 @@ static struct platform_driver x1e80100_pinctrl_driver = { .of_match_table = x1e80100_pinctrl_of_match, }, .probe = x1e80100_pinctrl_probe, - .remove = msm_pinctrl_remove, }; static int __init x1e80100_pinctrl_init(void) diff --git a/drivers/pinctrl/qcom/tlmm-test.c b/drivers/pinctrl/qcom/tlmm-test.c new file mode 100644 index 000000000000..7b99e89e0f67 --- /dev/null +++ b/drivers/pinctrl/qcom/tlmm-test.c @@ -0,0 +1,664 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#define pr_fmt(fmt) "tlmm-test: " fmt + +#include <kunit/test.h> +#include <linux/delay.h> +#include <linux/gpio/consumer.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/pinctrl/consumer.h> +#include <linux/platform_device.h> + +/* + * This TLMM test module serves the purpose of validating that the TLMM driver + * (pinctrl-msm) delivers expected number of interrupts in response to changing + * GPIO state. + * + * To achieve this without external equipment the test takes a module parameter + * "gpio", which the tester is expected to specify an unused and non-connected + * pin. The GPIO state is then driven by adjusting the bias of the pin, at + * suitable times through the different test cases. + * + * Upon execution, the test initialization will find the TLMM node (subject to + * tlmm_of_match[] allow listing) and create the necessary references + * dynamically, rather then relying on e.g. Devicetree and phandles. + */ + +#define MSM_PULL_MASK GENMASK(2, 0) +#define MSM_PULL_DOWN 1 +#define MSM_PULL_UP 3 +#define TLMM_REG_SIZE 0x1000 + +static int tlmm_test_gpio = -1; +module_param_named(gpio, tlmm_test_gpio, int, 0600); + +static struct { + void __iomem *base; + void __iomem *reg; + int irq; + + u32 low_val; + u32 high_val; +} tlmm_suite; + +/** + * struct tlmm_test_priv - Per-test context + * @intr_count: number of times hard handler was hit with TLMM_TEST_COUNT op set + * @thread_count: number of times thread handler was hit with TLMM_TEST_COUNT op set + * @intr_op: operations to be performed by the hard IRQ handler + * @intr_op_remain: number of times the TLMM_TEST_THEN_* operations should be + * performed by the hard IRQ handler + * @thread_op: operations to be performed by the threaded IRQ handler + * @thread_op_remain: number of times the TLMM_TEST_THEN_* operations should + * be performed by the threaded IRQ handler + */ +struct tlmm_test_priv { + atomic_t intr_count; + atomic_t thread_count; + + unsigned int intr_op; + atomic_t intr_op_remain; + + unsigned int thread_op; + atomic_t thread_op_remain; +}; + +/* Operation masks for @intr_op and @thread_op */ +#define TLMM_TEST_COUNT BIT(0) +#define TLMM_TEST_OUTPUT_LOW BIT(1) +#define TLMM_TEST_OUTPUT_HIGH BIT(2) +#define TLMM_TEST_THEN_HIGH BIT(3) +#define TLMM_TEST_THEN_LOW BIT(4) +#define TLMM_TEST_WAKE_THREAD BIT(5) + +static void tlmm_output_low(void) +{ + writel(tlmm_suite.low_val, tlmm_suite.reg); + readl(tlmm_suite.reg); +} + +static void tlmm_output_high(void) +{ + writel(tlmm_suite.high_val, tlmm_suite.reg); + readl(tlmm_suite.reg); +} + +static irqreturn_t tlmm_test_intr_fn(int irq, void *dev_id) +{ + struct tlmm_test_priv *priv = dev_id; + + if (priv->intr_op & TLMM_TEST_COUNT) + atomic_inc(&priv->intr_count); + + if (priv->intr_op & TLMM_TEST_OUTPUT_LOW) + tlmm_output_low(); + if (priv->intr_op & TLMM_TEST_OUTPUT_HIGH) + tlmm_output_high(); + + if (atomic_dec_if_positive(&priv->intr_op_remain) > 0) { + udelay(1); + + if (priv->intr_op & TLMM_TEST_THEN_LOW) + tlmm_output_low(); + if (priv->intr_op & TLMM_TEST_THEN_HIGH) + tlmm_output_high(); + } + + return priv->intr_op & TLMM_TEST_WAKE_THREAD ? IRQ_WAKE_THREAD : IRQ_HANDLED; +} + +static irqreturn_t tlmm_test_intr_thread_fn(int irq, void *dev_id) +{ + struct tlmm_test_priv *priv = dev_id; + + if (priv->thread_op & TLMM_TEST_COUNT) + atomic_inc(&priv->thread_count); + + if (priv->thread_op & TLMM_TEST_OUTPUT_LOW) + tlmm_output_low(); + if (priv->thread_op & TLMM_TEST_OUTPUT_HIGH) + tlmm_output_high(); + + if (atomic_dec_if_positive(&priv->thread_op_remain) > 0) { + udelay(1); + if (priv->thread_op & TLMM_TEST_THEN_LOW) + tlmm_output_low(); + if (priv->thread_op & TLMM_TEST_THEN_HIGH) + tlmm_output_high(); + } + + return IRQ_HANDLED; +} + +static void tlmm_test_request_hard_irq(struct kunit *test, unsigned long irqflags) +{ + struct tlmm_test_priv *priv = test->priv; + int ret; + + ret = request_irq(tlmm_suite.irq, tlmm_test_intr_fn, irqflags, test->name, priv); + KUNIT_EXPECT_EQ(test, ret, 0); +} + +static void tlmm_test_request_threaded_irq(struct kunit *test, unsigned long irqflags) +{ + struct tlmm_test_priv *priv = test->priv; + int ret; + + ret = request_threaded_irq(tlmm_suite.irq, + tlmm_test_intr_fn, tlmm_test_intr_thread_fn, + irqflags, test->name, priv); + + KUNIT_EXPECT_EQ(test, ret, 0); +} + +static void tlmm_test_silent(struct kunit *test, unsigned long irqflags) +{ + struct tlmm_test_priv *priv = test->priv; + + priv->intr_op = TLMM_TEST_COUNT; + + /* GPIO line at non-triggering level */ + if (irqflags == IRQF_TRIGGER_LOW || irqflags == IRQF_TRIGGER_FALLING) + tlmm_output_high(); + else + tlmm_output_low(); + + tlmm_test_request_hard_irq(test, irqflags); + msleep(100); + free_irq(tlmm_suite.irq, priv); + + KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 0); +} + +/* + * Test that no RISING interrupts are triggered on a silent pin + */ +static void tlmm_test_silent_rising(struct kunit *test) +{ + tlmm_test_silent(test, IRQF_TRIGGER_RISING); +} + +/* + * Test that no FALLING interrupts are triggered on a silent pin + */ +static void tlmm_test_silent_falling(struct kunit *test) +{ + tlmm_test_silent(test, IRQF_TRIGGER_FALLING); +} + +/* + * Test that no LOW interrupts are triggered on a silent pin + */ +static void tlmm_test_silent_low(struct kunit *test) +{ + tlmm_test_silent(test, IRQF_TRIGGER_LOW); +} + +/* + * Test that no HIGH interrupts are triggered on a silent pin + */ +static void tlmm_test_silent_high(struct kunit *test) +{ + tlmm_test_silent(test, IRQF_TRIGGER_HIGH); +} + +/* + * Square wave with 10 high pulses, assert that we get 10 rising interrupts + */ +static void tlmm_test_rising(struct kunit *test) +{ + struct tlmm_test_priv *priv = test->priv; + int i; + + priv->intr_op = TLMM_TEST_COUNT; + + tlmm_output_low(); + + tlmm_test_request_hard_irq(test, IRQF_TRIGGER_RISING); + for (i = 0; i < 10; i++) { + tlmm_output_low(); + msleep(20); + tlmm_output_high(); + msleep(20); + } + + free_irq(tlmm_suite.irq, priv); + + KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10); +} + +/* + * Square wave with 10 low pulses, assert that we get 10 falling interrupts + */ +static void tlmm_test_falling(struct kunit *test) +{ + struct tlmm_test_priv *priv = test->priv; + int i; + + priv->intr_op = TLMM_TEST_COUNT; + + tlmm_output_high(); + + tlmm_test_request_hard_irq(test, IRQF_TRIGGER_FALLING); + for (i = 0; i < 10; i++) { + tlmm_output_high(); + msleep(20); + tlmm_output_low(); + msleep(20); + } + free_irq(tlmm_suite.irq, priv); + + KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10); +} + +/* + * Drive line low 10 times, handler drives it high to "clear the interrupt + * source", assert we get 10 interrupts + */ +static void tlmm_test_low(struct kunit *test) +{ + struct tlmm_test_priv *priv = test->priv; + int i; + + priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_HIGH; + atomic_set(&priv->intr_op_remain, 9); + + tlmm_output_high(); + + tlmm_test_request_hard_irq(test, IRQF_TRIGGER_LOW); + for (i = 0; i < 10; i++) { + msleep(20); + tlmm_output_low(); + } + msleep(100); + free_irq(tlmm_suite.irq, priv); + + KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10); +} + +/* + * Drive line high 10 times, handler drives it low to "clear the interrupt + * source", assert we get 10 interrupts + */ +static void tlmm_test_high(struct kunit *test) +{ + struct tlmm_test_priv *priv = test->priv; + int i; + + priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_LOW; + atomic_set(&priv->intr_op_remain, 9); + + tlmm_output_low(); + + tlmm_test_request_hard_irq(test, IRQF_TRIGGER_HIGH); + for (i = 0; i < 10; i++) { + msleep(20); + tlmm_output_high(); + } + msleep(100); + free_irq(tlmm_suite.irq, priv); + + KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10); +} + +/* + * Handler drives GPIO high to "clear the interrupt source", then low to + * simulate a new interrupt, repeated 10 times, assert we get 10 interrupts + */ +static void tlmm_test_falling_in_handler(struct kunit *test) +{ + struct tlmm_test_priv *priv = test->priv; + + priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_HIGH | TLMM_TEST_THEN_LOW; + atomic_set(&priv->intr_op_remain, 10); + + tlmm_output_high(); + + tlmm_test_request_hard_irq(test, IRQF_TRIGGER_FALLING); + msleep(20); + tlmm_output_low(); + msleep(100); + free_irq(tlmm_suite.irq, priv); + + KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10); +} + +/* + * Handler drives GPIO low to "clear the interrupt source", then high to + * simulate a new interrupt, repeated 10 times, assert we get 10 interrupts + */ +static void tlmm_test_rising_in_handler(struct kunit *test) +{ + struct tlmm_test_priv *priv = test->priv; + + priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_LOW | TLMM_TEST_THEN_HIGH; + atomic_set(&priv->intr_op_remain, 10); + + tlmm_output_low(); + + tlmm_test_request_hard_irq(test, IRQF_TRIGGER_RISING); + msleep(20); + tlmm_output_high(); + msleep(100); + free_irq(tlmm_suite.irq, priv); + + KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10); +} + +/* + * Square wave with 10 high pulses, assert that we get 10 rising hard and + * 10 threaded interrupts + */ +static void tlmm_test_thread_rising(struct kunit *test) +{ + struct tlmm_test_priv *priv = test->priv; + int i; + + priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_WAKE_THREAD; + priv->thread_op = TLMM_TEST_COUNT; + + tlmm_output_low(); + + tlmm_test_request_threaded_irq(test, IRQF_TRIGGER_RISING); + for (i = 0; i < 10; i++) { + tlmm_output_low(); + msleep(20); + tlmm_output_high(); + msleep(20); + } + free_irq(tlmm_suite.irq, priv); + + KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10); + KUNIT_ASSERT_EQ(test, atomic_read(&priv->thread_count), 10); +} + +/* + * Square wave with 10 low pulses, assert that we get 10 falling interrupts + */ +static void tlmm_test_thread_falling(struct kunit *test) +{ + struct tlmm_test_priv *priv = test->priv; + int i; + + priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_WAKE_THREAD; + priv->thread_op = TLMM_TEST_COUNT; + + tlmm_output_high(); + + tlmm_test_request_threaded_irq(test, IRQF_TRIGGER_FALLING); + for (i = 0; i < 10; i++) { + tlmm_output_high(); + msleep(20); + tlmm_output_low(); + msleep(20); + } + free_irq(tlmm_suite.irq, priv); + + KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10); + KUNIT_ASSERT_EQ(test, atomic_read(&priv->thread_count), 10); +} + +/* + * Drive line high 10 times, threaded handler drives it low to "clear the + * interrupt source", assert we get 10 interrupts + */ +static void tlmm_test_thread_high(struct kunit *test) +{ + struct tlmm_test_priv *priv = test->priv; + int i; + + priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_WAKE_THREAD; + priv->thread_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_LOW; + + tlmm_output_low(); + + tlmm_test_request_threaded_irq(test, IRQF_TRIGGER_HIGH | IRQF_ONESHOT); + for (i = 0; i < 10; i++) { + tlmm_output_high(); + msleep(20); + } + free_irq(tlmm_suite.irq, priv); + + KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10); + KUNIT_ASSERT_EQ(test, atomic_read(&priv->thread_count), 10); +} + +/* + * Drive line low 10 times, threaded handler drives it high to "clear the + * interrupt source", assert we get 10 interrupts + */ +static void tlmm_test_thread_low(struct kunit *test) +{ + struct tlmm_test_priv *priv = test->priv; + int i; + + priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_WAKE_THREAD; + priv->thread_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_HIGH; + + tlmm_output_high(); + + tlmm_test_request_threaded_irq(test, IRQF_TRIGGER_LOW | IRQF_ONESHOT); + for (i = 0; i < 10; i++) { + tlmm_output_low(); + msleep(20); + } + free_irq(tlmm_suite.irq, priv); + + KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10); + KUNIT_ASSERT_EQ(test, atomic_read(&priv->thread_count), 10); +} + +/* + * Handler drives GPIO low to "clear the interrupt source", then high in the + * threaded handler to simulate a new interrupt, repeated 10 times, assert we + * get 10 interrupts + */ +static void tlmm_test_thread_rising_in_handler(struct kunit *test) +{ + struct tlmm_test_priv *priv = test->priv; + + priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_LOW | TLMM_TEST_WAKE_THREAD; + priv->thread_op = TLMM_TEST_COUNT | TLMM_TEST_THEN_HIGH; + atomic_set(&priv->thread_op_remain, 10); + + tlmm_output_low(); + + tlmm_test_request_threaded_irq(test, IRQF_TRIGGER_RISING); + msleep(20); + tlmm_output_high(); + msleep(100); + free_irq(tlmm_suite.irq, priv); + + KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10); + KUNIT_ASSERT_EQ(test, atomic_read(&priv->thread_count), 10); +} + +/* + * Handler drives GPIO high to "clear the interrupt source", then low in the + * threaded handler to simulate a new interrupt, repeated 10 times, assert we + * get 10 interrupts + */ +static void tlmm_test_thread_falling_in_handler(struct kunit *test) +{ + struct tlmm_test_priv *priv = test->priv; + + priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_HIGH | TLMM_TEST_WAKE_THREAD; + priv->thread_op = TLMM_TEST_COUNT | TLMM_TEST_THEN_LOW; + atomic_set(&priv->thread_op_remain, 10); + + tlmm_output_high(); + + tlmm_test_request_threaded_irq(test, IRQF_TRIGGER_FALLING); + msleep(20); + tlmm_output_low(); + msleep(100); + free_irq(tlmm_suite.irq, priv); + + KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10); + KUNIT_ASSERT_EQ(test, atomic_read(&priv->thread_count), 10); +} + +/* + * Validate that edge interrupts occurring while irq is disabled is delivered + * once the interrupt is reenabled. + */ +static void tlmm_test_rising_while_disabled(struct kunit *test) +{ + struct tlmm_test_priv *priv = test->priv; + unsigned int after_edge; + unsigned int before_edge; + + priv->intr_op = TLMM_TEST_COUNT; + atomic_set(&priv->thread_op_remain, 10); + + tlmm_output_low(); + + tlmm_test_request_hard_irq(test, IRQF_TRIGGER_RISING); + msleep(20); + + disable_irq(tlmm_suite.irq); + before_edge = atomic_read(&priv->intr_count); + + tlmm_output_high(); + msleep(20); + after_edge = atomic_read(&priv->intr_count); + + msleep(20); + enable_irq(tlmm_suite.irq); + msleep(20); + + free_irq(tlmm_suite.irq, priv); + + KUNIT_ASSERT_EQ(test, before_edge, 0); + KUNIT_ASSERT_EQ(test, after_edge, 0); + KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 1); +} + +static int tlmm_test_init(struct kunit *test) +{ + struct tlmm_test_priv *priv; + + priv = kunit_kzalloc(test, sizeof(*priv), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, priv); + + atomic_set(&priv->intr_count, 0); + atomic_set(&priv->thread_count, 0); + + atomic_set(&priv->intr_op_remain, 0); + atomic_set(&priv->thread_op_remain, 0); + + test->priv = priv; + + return 0; +} + +/* + * NOTE: When adding compatibles to this list, ensure that TLMM_REG_SIZE and + * pull configuration values are supported and correct. + */ +static const struct of_device_id tlmm_of_match[] = { + { .compatible = "qcom,sc8280xp-tlmm" }, + { .compatible = "qcom,x1e80100-tlmm" }, + {} +}; + +static int tlmm_test_init_suite(struct kunit_suite *suite) +{ + struct of_phandle_args args = {}; + struct resource res; + int ret; + u32 val; + + if (tlmm_test_gpio < 0) { + pr_err("use the tlmm-test.gpio module parameter to specify which GPIO to use\n"); + return -EINVAL; + } + + struct device_node *tlmm __free(device_node) = of_find_matching_node(NULL, tlmm_of_match); + if (!tlmm) { + pr_err("failed to find tlmm node\n"); + return -EINVAL; + } + + ret = of_address_to_resource(tlmm, 0, &res); + if (ret < 0) + return ret; + + tlmm_suite.base = ioremap(res.start, resource_size(&res)); + if (!tlmm_suite.base) + return -ENOMEM; + + args.np = tlmm; + args.args_count = 2; + args.args[0] = tlmm_test_gpio; + args.args[1] = 0; + + tlmm_suite.irq = irq_create_of_mapping(&args); + if (!tlmm_suite.irq) { + pr_err("failed to map TLMM irq %d\n", args.args[0]); + goto err_unmap; + } + + tlmm_suite.reg = tlmm_suite.base + tlmm_test_gpio * TLMM_REG_SIZE; + val = readl(tlmm_suite.reg) & ~MSM_PULL_MASK; + tlmm_suite.low_val = val | MSM_PULL_DOWN; + tlmm_suite.high_val = val | MSM_PULL_UP; + + return 0; + +err_unmap: + iounmap(tlmm_suite.base); + tlmm_suite.base = NULL; + return -EINVAL; +} + +static void tlmm_test_exit_suite(struct kunit_suite *suite) +{ + irq_dispose_mapping(tlmm_suite.irq); + iounmap(tlmm_suite.base); + + tlmm_suite.base = NULL; + tlmm_suite.irq = -1; +} + +static struct kunit_case tlmm_test_cases[] = { + KUNIT_CASE(tlmm_test_silent_rising), + KUNIT_CASE(tlmm_test_silent_falling), + KUNIT_CASE(tlmm_test_silent_low), + KUNIT_CASE(tlmm_test_silent_high), + KUNIT_CASE(tlmm_test_rising), + KUNIT_CASE(tlmm_test_falling), + KUNIT_CASE(tlmm_test_high), + KUNIT_CASE(tlmm_test_low), + KUNIT_CASE(tlmm_test_rising_in_handler), + KUNIT_CASE(tlmm_test_falling_in_handler), + KUNIT_CASE(tlmm_test_thread_rising), + KUNIT_CASE(tlmm_test_thread_falling), + KUNIT_CASE(tlmm_test_thread_high), + KUNIT_CASE(tlmm_test_thread_low), + KUNIT_CASE(tlmm_test_thread_rising_in_handler), + KUNIT_CASE(tlmm_test_thread_falling_in_handler), + KUNIT_CASE(tlmm_test_rising_while_disabled), + {} +}; + +static struct kunit_suite tlmm_test_suite = { + .name = "tlmm-test", + .init = tlmm_test_init, + .suite_init = tlmm_test_init_suite, + .suite_exit = tlmm_test_exit_suite, + .test_cases = tlmm_test_cases, +}; + +kunit_test_suites(&tlmm_test_suite); + +MODULE_DESCRIPTION("Qualcomm TLMM test"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 3c18d908b21e..e16034fc1bbf 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -42,6 +42,7 @@ config PINCTRL_RENESAS select PINCTRL_RZG2L if ARCH_RZG2L select PINCTRL_RZV2M if ARCH_R9A09G011 select PINCTRL_RZG2L if ARCH_R9A09G047 + select PINCTRL_RZG2L if ARCH_R9A09G056 select PINCTRL_RZG2L if ARCH_R9A09G057 select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203 select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264 diff --git a/drivers/pinctrl/renesas/pinctrl-rza2.c b/drivers/pinctrl/renesas/pinctrl-rza2.c index 8b36161c7c50..3b5812963850 100644 --- a/drivers/pinctrl/renesas/pinctrl-rza2.c +++ b/drivers/pinctrl/renesas/pinctrl-rza2.c @@ -246,6 +246,9 @@ static int rza2_gpio_register(struct rza2_pinctrl_priv *priv) int ret; chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np); + if (!chip.label) + return -ENOMEM; + chip.parent = priv->dev; chip.ngpio = priv->npins; diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index d1da7f53fc60..78fa08ff0faa 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -318,6 +318,7 @@ struct rzg2l_pinctrl_pin_settings { * @pmc: PMC registers cache * @pfc: PFC registers cache * @iolh: IOLH registers cache + * @pupd: PUPD registers cache * @ien: IEN registers cache * @sd_ch: SD_CH registers cache * @eth_poc: ET_POC registers cache @@ -331,6 +332,7 @@ struct rzg2l_pinctrl_reg_cache { u32 *pfc; u32 *iolh[2]; u32 *ien[2]; + u32 *pupd[2]; u8 sd_ch[2]; u8 eth_poc[2]; u8 eth_mode; @@ -2228,135 +2230,146 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = { PIN_CFG_IO_VMC_SD1)) }, }; -static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = { - { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) }, - { "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_IEN)) }, - { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, - { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD | PIN_CFG_NOD)) }, - { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD | PIN_CFG_NOD)) }, - { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD | PIN_CFG_OEN)) }, - { "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD | PIN_CFG_OEN)) }, - { "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD | PIN_CFG_OEN)) }, - { "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD | PIN_CFG_OEN)) }, - { "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) }, - { "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) }, - { "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) }, - { "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, - { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_IEN | PIN_CFG_PUPD)) }, - { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, - { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_IEN | PIN_CFG_PUPD)) }, - { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_IEN | PIN_CFG_PUPD)) }, - { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_IEN | PIN_CFG_PUPD)) }, - { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_IEN | PIN_CFG_PUPD)) }, - { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_IEN | PIN_CFG_PUPD)) }, - { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_IEN | PIN_CFG_PUPD)) }, - { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_IEN | PIN_CFG_PUPD)) }, - { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_IEN | PIN_CFG_PUPD)) }, - { "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, - { "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_IEN | PIN_CFG_PUPD)) }, - { "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_IEN | PIN_CFG_PUPD)) }, - { "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_IEN | PIN_CFG_PUPD)) }, - { "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_IEN | PIN_CFG_PUPD)) }, - { "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_IEN | PIN_CFG_PUPD)) }, - { "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, - { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, - { "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_IEN | PIN_CFG_PUPD)) }, - { "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) }, - { "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) }, - { "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) }, - { "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD | PIN_CFG_OEN)) }, - { "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) }, - { "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) }, - { "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) }, - { "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) }, - { "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) }, - { "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) }, - { "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_IEN | PIN_CFG_PUPD)) }, - { "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) }, - { "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | +static const struct { + struct rzg2l_dedicated_configs common[77]; + struct rzg2l_dedicated_configs pcie1[1]; +} rzv2h_dedicated_pins = { + .common = { + { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) }, + { "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_IEN)) }, + { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, + { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD | PIN_CFG_NOD)) }, + { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD | PIN_CFG_NOD)) }, + { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD | PIN_CFG_OEN)) }, + { "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD | PIN_CFG_OEN)) }, + { "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD | PIN_CFG_OEN)) }, + { "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD | PIN_CFG_OEN)) }, + { "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) }, + { "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) }, + { "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) }, + { "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, + { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, + { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, + { "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H | + PIN_CFG_SR)) }, + { "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) }, - { "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) }, - { "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) }, - { "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD | PIN_CFG_OEN)) }, - { "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) }, - { "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) }, - { "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | - PIN_CFG_PUPD)) }, - { "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) }, - { "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) }, - { "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) }, - { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) }, + { "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) }, + { "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H | + PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) }, + { "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) }, + { "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD | PIN_CFG_OEN)) }, + { "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) }, + { "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) }, + { "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) }, + { "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) }, + { "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) }, + { "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) }, + { "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) }, + { "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H | + PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) }, + { "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) }, + { "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD | PIN_CFG_OEN)) }, + { "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) }, + { "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) }, + { "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) }, + { "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) }, + { "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) }, + { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) }, + }, + .pcie1 = { + { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | + PIN_CFG_SR)) }, + }, }; static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = { @@ -2712,6 +2725,11 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) if (!cache->ien[i]) return -ENOMEM; + cache->pupd[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pupd[i]), + GFP_KERNEL); + if (!cache->pupd[i]) + return -ENOMEM; + /* Allocate dedicated cache. */ dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, sizeof(*dedicated_cache->iolh[i]), @@ -2955,7 +2973,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; for (u32 port = 0; port < nports; port++) { - bool has_iolh, has_ien; + bool has_iolh, has_ien, has_pupd; u32 off, caps; u8 pincnt; u64 cfg; @@ -2967,6 +2985,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen caps = FIELD_GET(PIN_CFG_MASK, cfg); has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); has_ien = !!(caps & PIN_CFG_IEN); + has_pupd = !!(caps & PIN_CFG_PUPD); if (suspend) RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]); @@ -2985,6 +3004,15 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen } } + if (has_pupd) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), + cache->pupd[0][port]); + if (pincnt >= 4) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), + cache->pupd[1][port]); + } + } + RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]); RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]); @@ -3332,13 +3360,37 @@ static struct rzg2l_pinctrl_data r9a09g047_data = { .bias_param_to_hw = &rzv2h_bias_param_to_hw, }; +static struct rzg2l_pinctrl_data r9a09g056_data = { + .port_pins = rzv2h_gpio_names, + .port_pin_configs = r9a09g057_gpio_configs, + .n_ports = ARRAY_SIZE(r9a09g057_gpio_configs), + .dedicated_pins = rzv2h_dedicated_pins.common, + .n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT, + .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins.common), + .hwcfg = &rzv2h_hwcfg, + .variable_pin_cfg = r9a09g057_variable_pin_cfg, + .n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg), + .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings), + .custom_params = renesas_rzv2h_custom_bindings, +#ifdef CONFIG_DEBUG_FS + .custom_conf_items = renesas_rzv2h_conf_items, +#endif + .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock, + .pmc_writeb = &rzv2h_pmc_writeb, + .oen_read = &rzv2h_oen_read, + .oen_write = &rzv2h_oen_write, + .hw_to_bias_param = &rzv2h_hw_to_bias_param, + .bias_param_to_hw = &rzv2h_bias_param_to_hw, +}; + static struct rzg2l_pinctrl_data r9a09g057_data = { .port_pins = rzv2h_gpio_names, .port_pin_configs = r9a09g057_gpio_configs, .n_ports = ARRAY_SIZE(r9a09g057_gpio_configs), - .dedicated_pins = rzv2h_dedicated_pins, + .dedicated_pins = rzv2h_dedicated_pins.common, .n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT, - .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins), + .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins.common) + + ARRAY_SIZE(rzv2h_dedicated_pins.pcie1), .hwcfg = &rzv2h_hwcfg, .variable_pin_cfg = r9a09g057_variable_pin_cfg, .n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg), @@ -3373,6 +3425,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = { .data = &r9a09g047_data, }, { + .compatible = "renesas,r9a09g056-pinctrl", + .data = &r9a09g056_data, + }, + { .compatible = "renesas,r9a09g057-pinctrl", .data = &r9a09g057_data, }, diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index e28fe8177646..9fd894729a7b 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -41,6 +41,15 @@ static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { }; /* + * Bank type for alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 2, DRV: 3 + */ +static const struct samsung_pin_bank_type exynos7870_bank_type_alive = { + .fld_width = { 4, 1, 2, 3, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + +/* * Bank type for non-alive type. Bit fields: * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4 */ @@ -70,6 +79,174 @@ static const struct samsung_pin_bank_type exynos8895_bank_type_off = { /* Pad retention control code for accessing PMU regmap */ static atomic_t exynos_shared_retention_refcnt; +/* pin banks of exynos2200 pin-controller - ALIVE */ +static const struct samsung_pin_bank_data exynos2200_pin_banks0[] __initconst = { + EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00), + EXYNOS850_PIN_BANK_EINTW(8, 0x20, "gpa1", 0x04), + EXYNOS850_PIN_BANK_EINTW(8, 0x40, "gpa2", 0x08), + EXYNOS850_PIN_BANK_EINTW(8, 0x60, "gpa3", 0x0c), + EXYNOS850_PIN_BANK_EINTW(2, 0x80, "gpa4", 0x10), + EXYNOS_PIN_BANK_EINTN(4, 0xa0, "gpq0"), + EXYNOS_PIN_BANK_EINTN(2, 0xc0, "gpq1"), + EXYNOS_PIN_BANK_EINTN(2, 0xe0, "gpq2"), +}; + +/* pin banks of exynos2200 pin-controller - CMGP */ +static const struct samsung_pin_bank_data exynos2200_pin_banks1[] __initconst = { + EXYNOS850_PIN_BANK_EINTW(2, 0x0, "gpm0", 0x00), + EXYNOS850_PIN_BANK_EINTW(2, 0x20, "gpm1", 0x04), + EXYNOS850_PIN_BANK_EINTW(2, 0x40, "gpm2", 0x08), + EXYNOS850_PIN_BANK_EINTW(2, 0x60, "gpm3", 0x0c), + EXYNOS850_PIN_BANK_EINTW(2, 0x80, "gpm4", 0x10), + EXYNOS850_PIN_BANK_EINTW(2, 0xa0, "gpm5", 0x14), + EXYNOS850_PIN_BANK_EINTW(2, 0xc0, "gpm6", 0x18), + EXYNOS850_PIN_BANK_EINTW(2, 0xe0, "gpm7", 0x1c), + EXYNOS850_PIN_BANK_EINTW(2, 0x100, "gpm8", 0x20), + EXYNOS850_PIN_BANK_EINTW(2, 0x120, "gpm9", 0x24), + EXYNOS850_PIN_BANK_EINTW(2, 0x140, "gpm10", 0x28), + EXYNOS850_PIN_BANK_EINTW(2, 0x160, "gpm11", 0x2c), + EXYNOS850_PIN_BANK_EINTW(2, 0x180, "gpm12", 0x30), + EXYNOS850_PIN_BANK_EINTW(2, 0x1a0, "gpm13", 0x34), + EXYNOS850_PIN_BANK_EINTW(1, 0x1c0, "gpm14", 0x38), + EXYNOS850_PIN_BANK_EINTW(1, 0x1e0, "gpm15", 0x3c), + EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40), + EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44), + EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm20", 0x48), + EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm21", 0x4c), + EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm22", 0x50), + EXYNOS850_PIN_BANK_EINTW(1, 0x2a0, "gpm23", 0x54), + EXYNOS850_PIN_BANK_EINTW(1, 0x2c0, "gpm24", 0x58), +}; + +/* pin banks of exynos2200 pin-controller - HSI1 */ +static const struct samsung_pin_bank_data exynos2200_pin_banks2[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpf0", 0x00), +}; + +/* pin banks of exynos2200 pin-controller - UFS */ +static const struct samsung_pin_bank_data exynos2200_pin_banks3[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(7, 0x0, "gpf1", 0x00), +}; + +/* pin banks of exynos2200 pin-controller - HSI1UFS */ +static const struct samsung_pin_bank_data exynos2200_pin_banks4[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gpf2", 0x00), +}; + +/* pin banks of exynos2200 pin-controller - PERIC0 */ +static const struct samsung_pin_bank_data exynos2200_pin_banks5[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpb0", 0x00), + EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpb1", 0x04), + EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpb2", 0x08), + EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpb3", 0x0c), + EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10), + EXYNOS850_PIN_BANK_EINTG(2, 0xa0, "gpc0", 0x14), + EXYNOS850_PIN_BANK_EINTG(2, 0xc0, "gpc1", 0x18), + EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpc2", 0x1c), + EXYNOS850_PIN_BANK_EINTG(7, 0x100, "gpg1", 0x20), + EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpg2", 0x24), +}; + +/* pin banks of exynos2200 pin-controller - PERIC1 */ +static const struct samsung_pin_bank_data exynos2200_pin_banks6[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpp7", 0x00), + EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp8", 0x04), + EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp9", 0x08), + EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpp10", 0x0c), +}; + +/* pin banks of exynos2200 pin-controller - PERIC2 */ +static const struct samsung_pin_bank_data exynos2200_pin_banks7[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpp0", 0x00), + EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04), + EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08), + EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpp3", 0x0c), + EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp5", 0x10), + EXYNOS850_PIN_BANK_EINTG(4, 0xa0, "gpp6", 0x14), + EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpp11", 0x18), + EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpc3", 0x1c), + EXYNOS850_PIN_BANK_EINTG(2, 0x100, "gpc4", 0x20), + EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpc5", 0x24), + EXYNOS850_PIN_BANK_EINTG(2, 0x140, "gpc6", 0x28), + EXYNOS850_PIN_BANK_EINTG(2, 0x160, "gpc7", 0x2c), + EXYNOS850_PIN_BANK_EINTG(2, 0x180, "gpc8", 0x30), + EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpc9", 0x34), + EXYNOS850_PIN_BANK_EINTG(5, 0x1c0, "gpg0", 0x38), +}; + +/* pin banks of exynos2200 pin-controller - VTS */ +static const struct samsung_pin_bank_data exynos2200_pin_banks8[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(7, 0x0, "gpv0", 0x00), +}; + +static const struct samsung_pin_ctrl exynos2200_pin_ctrl[] = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos2200_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos2200_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 CMGP data */ + .pin_banks = exynos2200_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos2200_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 HSI1 data */ + .pin_banks = exynos2200_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos2200_pin_banks2), + }, { + /* pin-controller instance 3 UFS data */ + .pin_banks = exynos2200_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos2200_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 4 HSI1UFS data */ + .pin_banks = exynos2200_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos2200_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 5 PERIC0 data */ + .pin_banks = exynos2200_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos2200_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 6 PERIC1 data */ + .pin_banks = exynos2200_pin_banks6, + .nr_banks = ARRAY_SIZE(exynos2200_pin_banks6), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 7 PERIC2 data */ + .pin_banks = exynos2200_pin_banks7, + .nr_banks = ARRAY_SIZE(exynos2200_pin_banks7), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 8 VTS data */ + .pin_banks = exynos2200_pin_banks8, + .nr_banks = ARRAY_SIZE(exynos2200_pin_banks8), + }, +}; + +const struct samsung_pinctrl_of_match_data exynos2200_of_data __initconst = { + .ctrl = exynos2200_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos2200_pin_ctrl), +}; + /* pin banks of exynos5433 pin-controller - ALIVE */ static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = { /* Must start with EINTG banks, ordered by EINT group number. */ @@ -450,6 +627,136 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl), }; +/* pin banks of exynos7870 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynos7870_pin_banks0[] __initconst = { + EXYNOS7870_PIN_BANK_EINTN(6, 0x000, "etc0"), + EXYNOS7870_PIN_BANK_EINTN(3, 0x020, "etc1"), + EXYNOS7870_PIN_BANK_EINTW(8, 0x040, "gpa0", 0x00), + EXYNOS7870_PIN_BANK_EINTW(8, 0x060, "gpa1", 0x04), + EXYNOS7870_PIN_BANK_EINTW(8, 0x080, "gpa2", 0x08), + EXYNOS7870_PIN_BANK_EINTN(2, 0x0c0, "gpq0"), +}; + +/* pin banks of exynos7870 pin-controller 1 (DISPAUD) */ +static const struct samsung_pin_bank_data exynos7870_pin_banks1[] __initconst = { + EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpz0", 0x00), + EXYNOS8895_PIN_BANK_EINTG(6, 0x020, "gpz1", 0x04), + EXYNOS8895_PIN_BANK_EINTG(4, 0x040, "gpz2", 0x08), +}; + +/* pin banks of exynos7870 pin-controller 2 (ESE) */ +static const struct samsung_pin_bank_data exynos7870_pin_banks2[] __initconst = { + EXYNOS8895_PIN_BANK_EINTG(5, 0x000, "gpc7", 0x00), +}; + +/* pin banks of exynos7870 pin-controller 3 (FSYS) */ +static const struct samsung_pin_bank_data exynos7870_pin_banks3[] __initconst = { + EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpr0", 0x00), + EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04), + EXYNOS8895_PIN_BANK_EINTG(2, 0x040, "gpr2", 0x08), + EXYNOS8895_PIN_BANK_EINTG(4, 0x060, "gpr3", 0x0c), + EXYNOS8895_PIN_BANK_EINTG(6, 0x080, "gpr4", 0x10), +}; + +/* pin banks of exynos7870 pin-controller 4 (MIF) */ +static const struct samsung_pin_bank_data exynos7870_pin_banks4[] __initconst = { + EXYNOS8895_PIN_BANK_EINTG(2, 0x000, "gpm0", 0x00), +}; + +/* pin banks of exynos7870 pin-controller 5 (NFC) */ +static const struct samsung_pin_bank_data exynos7870_pin_banks5[] __initconst = { + EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpc2", 0x00), +}; + +/* pin banks of exynos7870 pin-controller 6 (TOP) */ +static const struct samsung_pin_bank_data exynos7870_pin_banks6[] __initconst = { + EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpb0", 0x00), + EXYNOS8895_PIN_BANK_EINTG(3, 0x020, "gpc0", 0x04), + EXYNOS8895_PIN_BANK_EINTG(4, 0x040, "gpc1", 0x08), + EXYNOS8895_PIN_BANK_EINTG(4, 0x060, "gpc4", 0x0c), + EXYNOS8895_PIN_BANK_EINTG(2, 0x080, "gpc5", 0x10), + EXYNOS8895_PIN_BANK_EINTG(4, 0x0a0, "gpc6", 0x14), + EXYNOS8895_PIN_BANK_EINTG(2, 0x0c0, "gpc8", 0x18), + EXYNOS8895_PIN_BANK_EINTG(2, 0x0e0, "gpc9", 0x1c), + EXYNOS8895_PIN_BANK_EINTG(7, 0x100, "gpd1", 0x20), + EXYNOS8895_PIN_BANK_EINTG(6, 0x120, "gpd2", 0x24), + EXYNOS8895_PIN_BANK_EINTG(8, 0x140, "gpd3", 0x28), + EXYNOS8895_PIN_BANK_EINTG(7, 0x160, "gpd4", 0x2c), + EXYNOS8895_PIN_BANK_EINTG(3, 0x1a0, "gpe0", 0x34), + EXYNOS8895_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38), + EXYNOS8895_PIN_BANK_EINTG(2, 0x1e0, "gpf1", 0x3c), + EXYNOS8895_PIN_BANK_EINTG(2, 0x200, "gpf2", 0x40), + EXYNOS8895_PIN_BANK_EINTG(4, 0x220, "gpf3", 0x44), + EXYNOS8895_PIN_BANK_EINTG(5, 0x240, "gpf4", 0x48), +}; + +/* pin banks of exynos7870 pin-controller 7 (TOUCH) */ +static const struct samsung_pin_bank_data exynos7870_pin_banks7[] __initconst = { + EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpc3", 0x00), +}; + +static const struct samsung_pin_ctrl exynos7870_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 Alive data */ + .pin_banks = exynos7870_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos7870_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 DISPAUD data */ + .pin_banks = exynos7870_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos7870_pin_banks1), + }, { + /* pin-controller instance 2 ESE data */ + .pin_banks = exynos7870_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos7870_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 3 FSYS data */ + .pin_banks = exynos7870_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos7870_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 4 MIF data */ + .pin_banks = exynos7870_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos7870_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 5 NFC data */ + .pin_banks = exynos7870_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos7870_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 6 TOP data */ + .pin_banks = exynos7870_pin_banks6, + .nr_banks = ARRAY_SIZE(exynos7870_pin_banks6), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 7 TOUCH data */ + .pin_banks = exynos7870_pin_banks7, + .nr_banks = ARRAY_SIZE(exynos7870_pin_banks7), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos7870_of_data __initconst = { + .ctrl = exynos7870_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos7870_pin_ctrl), +}; + /* pin banks of exynos7885 pin-controller 0 (ALIVE) */ static const struct samsung_pin_bank_data exynos7885_pin_banks0[] __initconst = { EXYNOS_PIN_BANK_EINTN(3, 0x000, "etc0"), @@ -1112,8 +1419,8 @@ static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = { .pin_banks = exynosautov920_pin_banks0, .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks0), .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynosautov920_pinctrl_suspend, + .resume = exynosautov920_pinctrl_resume, .retention_data = &exynosautov920_retention_data, }, { /* pin-controller instance 1 AUD data */ @@ -1124,43 +1431,43 @@ static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = { .pin_banks = exynosautov920_pin_banks2, .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks2), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynosautov920_pinctrl_suspend, + .resume = exynosautov920_pinctrl_resume, }, { /* pin-controller instance 3 HSI1 data */ .pin_banks = exynosautov920_pin_banks3, .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks3), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynosautov920_pinctrl_suspend, + .resume = exynosautov920_pinctrl_resume, }, { /* pin-controller instance 4 HSI2 data */ .pin_banks = exynosautov920_pin_banks4, .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks4), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynosautov920_pinctrl_suspend, + .resume = exynosautov920_pinctrl_resume, }, { /* pin-controller instance 5 HSI2UFS data */ .pin_banks = exynosautov920_pin_banks5, .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks5), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynosautov920_pinctrl_suspend, + .resume = exynosautov920_pinctrl_resume, }, { /* pin-controller instance 6 PERIC0 data */ .pin_banks = exynosautov920_pin_banks6, .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks6), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynosautov920_pinctrl_suspend, + .resume = exynosautov920_pinctrl_resume, }, { /* pin-controller instance 7 PERIC1 data */ .pin_banks = exynosautov920_pin_banks7, .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks7), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = exynosautov920_pinctrl_suspend, + .resume = exynosautov920_pinctrl_resume, }, }; @@ -1455,15 +1762,15 @@ static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = { .pin_banks = gs101_pin_alive, .nr_banks = ARRAY_SIZE(gs101_pin_alive), .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = gs101_pinctrl_suspend, + .resume = gs101_pinctrl_resume, }, { /* pin banks of gs101 pin-controller (FAR_ALIVE) */ .pin_banks = gs101_pin_far_alive, .nr_banks = ARRAY_SIZE(gs101_pin_far_alive), .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = gs101_pinctrl_suspend, + .resume = gs101_pinctrl_resume, }, { /* pin banks of gs101 pin-controller (GSACORE) */ .pin_banks = gs101_pin_gsacore, @@ -1477,29 +1784,29 @@ static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = { .pin_banks = gs101_pin_peric0, .nr_banks = ARRAY_SIZE(gs101_pin_peric0), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = gs101_pinctrl_suspend, + .resume = gs101_pinctrl_resume, }, { /* pin banks of gs101 pin-controller (PERIC1) */ .pin_banks = gs101_pin_peric1, .nr_banks = ARRAY_SIZE(gs101_pin_peric1), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = gs101_pinctrl_suspend, + .resume = gs101_pinctrl_resume, }, { /* pin banks of gs101 pin-controller (HSI1) */ .pin_banks = gs101_pin_hsi1, .nr_banks = ARRAY_SIZE(gs101_pin_hsi1), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = gs101_pinctrl_suspend, + .resume = gs101_pinctrl_resume, }, { /* pin banks of gs101 pin-controller (HSI2) */ .pin_banks = gs101_pin_hsi2, .nr_banks = ARRAY_SIZE(gs101_pin_hsi2), .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, + .suspend = gs101_pinctrl_suspend, + .resume = gs101_pinctrl_resume, }, }; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 42093bae8bb7..f3e1c11abe55 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -370,6 +370,37 @@ struct exynos_eint_gpio_save { u32 eint_mask; }; +static void exynos_eint_update_flt_reg(void __iomem *reg, int cnt, int con) +{ + unsigned int val, shift; + int i; + + val = readl(reg); + for (i = 0; i < cnt; i++) { + shift = i * EXYNOS_FLTCON_LEN; + val &= ~(EXYNOS_FLTCON_DIGITAL << shift); + val |= con << shift; + } + writel(val, reg); +} + +/* + * Set the desired filter (digital or analog delay) and enable it to + * every pin in the bank. Note the filter selection bitfield is only + * found on alive banks. The filter determines to what extent signal + * fluctuations received through the pad are considered glitches. + */ +static void exynos_eint_set_filter(struct samsung_pin_bank *bank, int filter) +{ + unsigned int off = EXYNOS_GPIO_EFLTCON_OFFSET + bank->eint_fltcon_offset; + void __iomem *reg = bank->drvdata->virt_base + off; + unsigned int con = EXYNOS_FLTCON_EN | filter; + + for (int n = 0; n < bank->nr_pins; n += 4) + exynos_eint_update_flt_reg(reg + n, + min(bank->nr_pins - n, 4), con); +} + /* * exynos_eint_gpio_init() - setup handling of external gpio interrupts. * @d: driver data of samsung pinctrl driver. @@ -762,153 +793,190 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) return 0; } -static void exynos_pinctrl_suspend_bank( - struct samsung_pinctrl_drv_data *drvdata, - struct samsung_pin_bank *bank) +static void exynos_set_wakeup(struct samsung_pin_bank *bank) { - struct exynos_eint_gpio_save *save = bank->soc_priv; - const void __iomem *regs = bank->eint_base; + struct exynos_irq_chip *irq_chip; - if (clk_enable(bank->drvdata->pclk)) { - dev_err(bank->gpio_chip.parent, - "unable to enable clock for saving state\n"); - return; + if (bank->irq_chip) { + irq_chip = bank->irq_chip; + irq_chip->set_eint_wakeup_mask(bank->drvdata, irq_chip); } - - save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET - + bank->eint_offset); - save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset); - save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset + 4); - save->eint_mask = readl(regs + bank->irq_chip->eint_mask - + bank->eint_offset); - - clk_disable(bank->drvdata->pclk); - - pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); - pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); - pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); - pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); } -static void exynosauto_pinctrl_suspend_bank(struct samsung_pinctrl_drv_data *drvdata, - struct samsung_pin_bank *bank) +void exynos_pinctrl_suspend(struct samsung_pin_bank *bank) { struct exynos_eint_gpio_save *save = bank->soc_priv; const void __iomem *regs = bank->eint_base; - if (clk_enable(bank->drvdata->pclk)) { - dev_err(bank->gpio_chip.parent, - "unable to enable clock for saving state\n"); - return; + if (bank->eint_type == EINT_TYPE_GPIO) { + save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset); + save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset); + save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset + 4); + save->eint_mask = readl(regs + bank->irq_chip->eint_mask + + bank->eint_offset); + + pr_debug("%s: save con %#010x\n", + bank->name, save->eint_con); + pr_debug("%s: save fltcon0 %#010x\n", + bank->name, save->eint_fltcon0); + pr_debug("%s: save fltcon1 %#010x\n", + bank->name, save->eint_fltcon1); + pr_debug("%s: save mask %#010x\n", + bank->name, save->eint_mask); + } else if (bank->eint_type == EINT_TYPE_WKUP) { + exynos_set_wakeup(bank); } - - save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset); - save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset); - - clk_disable(bank->drvdata->pclk); - - pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); - pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); } -void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) +void gs101_pinctrl_suspend(struct samsung_pin_bank *bank) { - struct samsung_pin_bank *bank = drvdata->pin_banks; - struct exynos_irq_chip *irq_chip = NULL; - int i; + struct exynos_eint_gpio_save *save = bank->soc_priv; + const void __iomem *regs = bank->eint_base; - for (i = 0; i < drvdata->nr_banks; ++i, ++bank) { - if (bank->eint_type == EINT_TYPE_GPIO) { - if (bank->eint_con_offset) - exynosauto_pinctrl_suspend_bank(drvdata, bank); - else - exynos_pinctrl_suspend_bank(drvdata, bank); - } - else if (bank->eint_type == EINT_TYPE_WKUP) { - if (!irq_chip) { - irq_chip = bank->irq_chip; - irq_chip->set_eint_wakeup_mask(drvdata, - irq_chip); - } - } + if (bank->eint_type == EINT_TYPE_GPIO) { + save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset); + + save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + bank->eint_fltcon_offset); + + /* fltcon1 register only exists for pins 4-7 */ + if (bank->nr_pins > 4) + save->eint_fltcon1 = readl(regs + + EXYNOS_GPIO_EFLTCON_OFFSET + + bank->eint_fltcon_offset + 4); + + save->eint_mask = readl(regs + bank->irq_chip->eint_mask + + bank->eint_offset); + + pr_debug("%s: save con %#010x\n", + bank->name, save->eint_con); + pr_debug("%s: save fltcon0 %#010x\n", + bank->name, save->eint_fltcon0); + if (bank->nr_pins > 4) + pr_debug("%s: save fltcon1 %#010x\n", + bank->name, save->eint_fltcon1); + pr_debug("%s: save mask %#010x\n", + bank->name, save->eint_mask); + } else if (bank->eint_type == EINT_TYPE_WKUP) { + exynos_set_wakeup(bank); + exynos_eint_set_filter(bank, EXYNOS_FLTCON_ANALOG); } } -static void exynos_pinctrl_resume_bank( - struct samsung_pinctrl_drv_data *drvdata, - struct samsung_pin_bank *bank) +void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank) { struct exynos_eint_gpio_save *save = bank->soc_priv; - void __iomem *regs = bank->eint_base; + const void __iomem *regs = bank->eint_base; - if (clk_enable(bank->drvdata->pclk)) { - dev_err(bank->gpio_chip.parent, - "unable to enable clock for restoring state\n"); - return; + if (bank->eint_type == EINT_TYPE_GPIO) { + save->eint_con = readl(regs + bank->pctl_offset + + bank->eint_con_offset); + save->eint_mask = readl(regs + bank->pctl_offset + + bank->eint_mask_offset); + pr_debug("%s: save con %#010x\n", + bank->name, save->eint_con); + pr_debug("%s: save mask %#010x\n", + bank->name, save->eint_mask); + } else if (bank->eint_type == EINT_TYPE_WKUP) { + exynos_set_wakeup(bank); } +} - pr_debug("%s: con %#010x => %#010x\n", bank->name, - readl(regs + EXYNOS_GPIO_ECON_OFFSET - + bank->eint_offset), save->eint_con); - pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, - readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset), save->eint_fltcon0); - pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, - readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset + 4), save->eint_fltcon1); - pr_debug("%s: mask %#010x => %#010x\n", bank->name, - readl(regs + bank->irq_chip->eint_mask - + bank->eint_offset), save->eint_mask); - - writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET - + bank->eint_offset); - writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset); - writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset + 4); - writel(save->eint_mask, regs + bank->irq_chip->eint_mask - + bank->eint_offset); +void gs101_pinctrl_resume(struct samsung_pin_bank *bank) +{ + struct exynos_eint_gpio_save *save = bank->soc_priv; - clk_disable(bank->drvdata->pclk); + void __iomem *regs = bank->eint_base; + void __iomem *eint_fltcfg0 = regs + EXYNOS_GPIO_EFLTCON_OFFSET + + bank->eint_fltcon_offset; + + if (bank->eint_type == EINT_TYPE_GPIO) { + pr_debug("%s: con %#010x => %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset), save->eint_con); + + pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, + readl(eint_fltcfg0), save->eint_fltcon0); + + /* fltcon1 register only exists for pins 4-7 */ + if (bank->nr_pins > 4) + pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, + readl(eint_fltcfg0 + 4), save->eint_fltcon1); + + pr_debug("%s: mask %#010x => %#010x\n", bank->name, + readl(regs + bank->irq_chip->eint_mask + + bank->eint_offset), save->eint_mask); + + writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset); + writel(save->eint_fltcon0, eint_fltcfg0); + + if (bank->nr_pins > 4) + writel(save->eint_fltcon1, eint_fltcfg0 + 4); + writel(save->eint_mask, regs + bank->irq_chip->eint_mask + + bank->eint_offset); + } else if (bank->eint_type == EINT_TYPE_WKUP) { + exynos_eint_set_filter(bank, EXYNOS_FLTCON_DIGITAL); + } } -static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvdata, - struct samsung_pin_bank *bank) +void exynos_pinctrl_resume(struct samsung_pin_bank *bank) { struct exynos_eint_gpio_save *save = bank->soc_priv; void __iomem *regs = bank->eint_base; - if (clk_enable(bank->drvdata->pclk)) { - dev_err(bank->gpio_chip.parent, - "unable to enable clock for restoring state\n"); - return; + if (bank->eint_type == EINT_TYPE_GPIO) { + pr_debug("%s: con %#010x => %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset), save->eint_con); + pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset), save->eint_fltcon0); + pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset + 4), + save->eint_fltcon1); + pr_debug("%s: mask %#010x => %#010x\n", bank->name, + readl(regs + bank->irq_chip->eint_mask + + bank->eint_offset), save->eint_mask); + + writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset); + writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset); + writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset + 4); + writel(save->eint_mask, regs + bank->irq_chip->eint_mask + + bank->eint_offset); } - - pr_debug("%s: con %#010x => %#010x\n", bank->name, - readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con); - pr_debug("%s: mask %#010x => %#010x\n", bank->name, - readl(regs + bank->pctl_offset + bank->eint_mask_offset), save->eint_mask); - - writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset); - writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset); - - clk_disable(bank->drvdata->pclk); } -void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) +void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank) { - struct samsung_pin_bank *bank = drvdata->pin_banks; - int i; + struct exynos_eint_gpio_save *save = bank->soc_priv; + void __iomem *regs = bank->eint_base; - for (i = 0; i < drvdata->nr_banks; ++i, ++bank) - if (bank->eint_type == EINT_TYPE_GPIO) { - if (bank->eint_con_offset) - exynosauto_pinctrl_resume_bank(drvdata, bank); - else - exynos_pinctrl_resume_bank(drvdata, bank); - } + if (bank->eint_type == EINT_TYPE_GPIO) { + /* exynosautov920 has eint_con_offset for all but one bank */ + if (!bank->eint_con_offset) + exynos_pinctrl_resume(bank); + + pr_debug("%s: con %#010x => %#010x\n", bank->name, + readl(regs + bank->pctl_offset + bank->eint_con_offset), + save->eint_con); + pr_debug("%s: mask %#010x => %#010x\n", bank->name, + readl(regs + bank->pctl_offset + + bank->eint_mask_offset), save->eint_mask); + + writel(save->eint_con, + regs + bank->pctl_offset + bank->eint_con_offset); + writel(save->eint_mask, + regs + bank->pctl_offset + bank->eint_mask_offset); + } } static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index 33df21d5c9d6..362dc533186f 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -52,6 +52,26 @@ #define EXYNOS_EINT_MAX_PER_BANK 8 #define EXYNOS_EINT_NR_WKUP_EINT +/* + * EINT filter configuration register (on alive banks) has + * the following layout. + * + * BitfieldName[PinNum][Bit:Bit] + * FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24] + * FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16] + * FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8] + * FLT_EN[0][7] FLT_SEL[0][6] FLT_WIDTH[0][5:0] + * + * FLT_EN 0x0 = Disable, 0x1=Enable + * FLT_SEL 0x0 = Analog delay filter, 0x1 Digital filter (clock count) + * FLT_WIDTH Filtering width. Valid when FLT_SEL is 0x1 + */ + +#define EXYNOS_FLTCON_EN BIT(7) +#define EXYNOS_FLTCON_DIGITAL BIT(6) +#define EXYNOS_FLTCON_ANALOG (0 << 6) +#define EXYNOS_FLTCON_LEN 8 + #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ { \ .type = &bank_type_off, \ @@ -112,6 +132,25 @@ .pctl_res_idx = pctl_idx, \ } \ +#define EXYNOS7870_PIN_BANK_EINTN(pins, reg, id) \ + { \ + .type = &exynos7870_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define EXYNOS7870_PIN_BANK_EINTW(pins, reg, id, offs) \ + { \ + .type = &exynos7870_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = offs, \ + .name = id \ + } + #define EXYNOS850_PIN_BANK_EINTN(pins, reg, id) \ { \ .type = &exynos850_bank_type_alive, \ @@ -221,8 +260,12 @@ struct exynos_muxed_weint_data { int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d); int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d); -void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata); -void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata); +void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank); +void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank); +void exynos_pinctrl_suspend(struct samsung_pin_bank *bank); +void exynos_pinctrl_resume(struct samsung_pin_bank *bank); +void gs101_pinctrl_suspend(struct samsung_pin_bank *bank); +void gs101_pinctrl_resume(struct samsung_pin_bank *bank); struct samsung_retention_ctrl * exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, const struct samsung_retention_data *data); diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 963060920301..fe1ac82b9d79 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -570,15 +570,18 @@ static void samsung_gpio_set_value(struct gpio_chip *gc, } /* gpiolib gpio_set callback function */ -static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value) +static int samsung_gpio_set(struct gpio_chip *gc, unsigned int offset, + int value) { struct samsung_pin_bank *bank = gpiochip_get_data(gc); struct samsung_pinctrl_drv_data *drvdata = bank->drvdata; unsigned long flags; + int ret; - if (clk_enable(drvdata->pclk)) { + ret = clk_enable(drvdata->pclk); + if (ret) { dev_err(drvdata->dev, "failed to enable clock\n"); - return; + return ret; } raw_spin_lock_irqsave(&bank->slock, flags); @@ -586,6 +589,8 @@ static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value) raw_spin_unlock_irqrestore(&bank->slock, flags); clk_disable(drvdata->pclk); + + return 0; } /* gpiolib gpio_get callback function */ @@ -1062,7 +1067,7 @@ static int samsung_gpio_set_config(struct gpio_chip *gc, unsigned int offset, static const struct gpio_chip samsung_gpiolib_chip = { .request = gpiochip_generic_request, .free = gpiochip_generic_free, - .set = samsung_gpio_set, + .set_rv = samsung_gpio_set, .get = samsung_gpio_get, .direction_input = samsung_gpio_direction_input, .direction_output = samsung_gpio_direction_output, @@ -1333,6 +1338,7 @@ err_put_banks: static int __maybe_unused samsung_pinctrl_suspend(struct device *dev) { struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev); + struct samsung_pin_bank *bank; int i; i = clk_enable(drvdata->pclk); @@ -1343,7 +1349,7 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev) } for (i = 0; i < drvdata->nr_banks; i++) { - struct samsung_pin_bank *bank = &drvdata->pin_banks[i]; + bank = &drvdata->pin_banks[i]; const void __iomem *reg = bank->pctl_base + bank->pctl_offset; const u8 *offs = bank->type->reg_offset; const u8 *widths = bank->type->fld_width; @@ -1371,10 +1377,14 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev) } } + for (i = 0; i < drvdata->nr_banks; i++) { + bank = &drvdata->pin_banks[i]; + if (drvdata->suspend) + drvdata->suspend(bank); + } + clk_disable(drvdata->pclk); - if (drvdata->suspend) - drvdata->suspend(drvdata); if (drvdata->retention_ctrl && drvdata->retention_ctrl->enable) drvdata->retention_ctrl->enable(drvdata); @@ -1392,6 +1402,7 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev) static int __maybe_unused samsung_pinctrl_resume(struct device *dev) { struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev); + struct samsung_pin_bank *bank; int ret; int i; @@ -1406,11 +1417,14 @@ static int __maybe_unused samsung_pinctrl_resume(struct device *dev) return ret; } - if (drvdata->resume) - drvdata->resume(drvdata); + for (i = 0; i < drvdata->nr_banks; i++) { + bank = &drvdata->pin_banks[i]; + if (drvdata->resume) + drvdata->resume(bank); + } for (i = 0; i < drvdata->nr_banks; i++) { - struct samsung_pin_bank *bank = &drvdata->pin_banks[i]; + bank = &drvdata->pin_banks[i]; void __iomem *reg = bank->pctl_base + bank->pctl_offset; const u8 *offs = bank->type->reg_offset; const u8 *widths = bank->type->fld_width; @@ -1470,10 +1484,14 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { #ifdef CONFIG_PINCTRL_EXYNOS_ARM64 { .compatible = "google,gs101-pinctrl", .data = &gs101_of_data }, + { .compatible = "samsung,exynos2200-pinctrl", + .data = &exynos2200_of_data }, { .compatible = "samsung,exynos5433-pinctrl", .data = &exynos5433_of_data }, { .compatible = "samsung,exynos7-pinctrl", .data = &exynos7_of_data }, + { .compatible = "samsung,exynos7870-pinctrl", + .data = &exynos7870_of_data }, { .compatible = "samsung,exynos7885-pinctrl", .data = &exynos7885_of_data }, { .compatible = "samsung,exynos850-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 371e4f02bbfb..fcc57c244d16 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -285,8 +285,8 @@ struct samsung_pin_ctrl { int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *); void (*pud_value_init)(struct samsung_pinctrl_drv_data *drvdata); - void (*suspend)(struct samsung_pinctrl_drv_data *); - void (*resume)(struct samsung_pinctrl_drv_data *); + void (*suspend)(struct samsung_pin_bank *bank); + void (*resume)(struct samsung_pin_bank *bank); }; /** @@ -335,8 +335,8 @@ struct samsung_pinctrl_drv_data { struct samsung_retention_ctrl *retention_ctrl; - void (*suspend)(struct samsung_pinctrl_drv_data *); - void (*resume)(struct samsung_pinctrl_drv_data *); + void (*suspend)(struct samsung_pin_bank *bank); + void (*resume)(struct samsung_pin_bank *bank); }; /** @@ -377,6 +377,7 @@ struct samsung_pmx_func { }; /* list of all exported SoC specific data */ +extern const struct samsung_pinctrl_of_match_data exynos2200_of_data; extern const struct samsung_pinctrl_of_match_data exynos3250_of_data; extern const struct samsung_pinctrl_of_match_data exynos4210_of_data; extern const struct samsung_pinctrl_of_match_data exynos4x12_of_data; @@ -386,6 +387,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5410_of_data; extern const struct samsung_pinctrl_of_match_data exynos5420_of_data; extern const struct samsung_pinctrl_of_match_data exynos5433_of_data; extern const struct samsung_pinctrl_of_match_data exynos7_of_data; +extern const struct samsung_pinctrl_of_match_data exynos7870_of_data; extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data exynos8895_of_data; diff --git a/drivers/pinctrl/sophgo/Kconfig b/drivers/pinctrl/sophgo/Kconfig index c05f909a8838..9b0a3a4753b1 100644 --- a/drivers/pinctrl/sophgo/Kconfig +++ b/drivers/pinctrl/sophgo/Kconfig @@ -3,17 +3,21 @@ # Sophgo SoC PINCTRL drivers # -config PINCTRL_SOPHGO_CV18XX - bool +config PINCTRL_SOPHGO_COMMON + tristate select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF +config PINCTRL_SOPHGO_CV18XX_OPS + bool + config PINCTRL_SOPHGO_CV1800B tristate "Sophgo CV1800B SoC Pinctrl driver" depends on ARCH_SOPHGO || COMPILE_TEST depends on OF - select PINCTRL_SOPHGO_CV18XX + select PINCTRL_SOPHGO_COMMON + select PINCTRL_SOPHGO_CV18XX_OPS help Say Y to select the pinctrl driver for CV1800B SoC. This pin controller allows selecting the mux function for @@ -24,7 +28,8 @@ config PINCTRL_SOPHGO_CV1812H tristate "Sophgo CV1812H SoC Pinctrl driver" depends on ARCH_SOPHGO || COMPILE_TEST depends on OF - select PINCTRL_SOPHGO_CV18XX + select PINCTRL_SOPHGO_COMMON + select PINCTRL_SOPHGO_CV18XX_OPS help Say Y to select the pinctrl driver for CV1812H SoC. This pin controller allows selecting the mux function for @@ -35,7 +40,8 @@ config PINCTRL_SOPHGO_SG2000 tristate "Sophgo SG2000 SoC Pinctrl driver" depends on ARCH_SOPHGO || COMPILE_TEST depends on OF - select PINCTRL_SOPHGO_CV18XX + select PINCTRL_SOPHGO_COMMON + select PINCTRL_SOPHGO_CV18XX_OPS help Say Y to select the pinctrl driver for SG2000 SoC. This pin controller allows selecting the mux function for @@ -46,9 +52,37 @@ config PINCTRL_SOPHGO_SG2002 tristate "Sophgo SG2002 SoC Pinctrl driver" depends on ARCH_SOPHGO || COMPILE_TEST depends on OF - select PINCTRL_SOPHGO_CV18XX + select PINCTRL_SOPHGO_COMMON + select PINCTRL_SOPHGO_CV18XX_OPS help Say Y to select the pinctrl driver for SG2002 SoC. This pin controller allows selecting the mux function for each pin. This driver can also be built as a module called pinctrl-sg2002. + +config PINCTRL_SOPHGO_SG2042_OPS + bool + +config PINCTRL_SOPHGO_SG2042 + tristate "Sophgo SG2042 SoC Pinctrl driver" + depends on ARCH_SOPHGO || COMPILE_TEST + depends on OF + select PINCTRL_SOPHGO_COMMON + select PINCTRL_SOPHGO_SG2042_OPS + help + Say Y to select the pinctrl driver for SG2042 SoC. + This pin controller allows selecting the mux function for + each pin. This driver can also be built as a module called + pinctrl-sg2042. + +config PINCTRL_SOPHGO_SG2044 + tristate "Sophgo SG2044 SoC Pinctrl driver" + depends on ARCH_SOPHGO || COMPILE_TEST + depends on OF + select PINCTRL_SOPHGO_COMMON + select PINCTRL_SOPHGO_SG2042_OPS + help + Say Y to select the pinctrl driver for SG2044 SoC. + This pin controller allows selecting the mux function for + each pin. This driver can also be built as a module called + pinctrl-sg2044. diff --git a/drivers/pinctrl/sophgo/Makefile b/drivers/pinctrl/sophgo/Makefile index 4113a5c9191b..479c65e6dbc0 100644 --- a/drivers/pinctrl/sophgo/Makefile +++ b/drivers/pinctrl/sophgo/Makefile @@ -1,7 +1,13 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PINCTRL_SOPHGO_CV18XX) += pinctrl-cv18xx.o +obj-$(CONFIG_PINCTRL_SOPHGO_COMMON) += pinctrl-sophgo.o +pinctrl-sophgo-objs += pinctrl-sophgo-common.o +pinctrl-sophgo-$(CONFIG_PINCTRL_SOPHGO_CV18XX_OPS) += pinctrl-cv18xx.o +pinctrl-sophgo-$(CONFIG_PINCTRL_SOPHGO_SG2042_OPS) += pinctrl-sg2042-ops.o + obj-$(CONFIG_PINCTRL_SOPHGO_CV1800B) += pinctrl-cv1800b.o obj-$(CONFIG_PINCTRL_SOPHGO_CV1812H) += pinctrl-cv1812h.o obj-$(CONFIG_PINCTRL_SOPHGO_SG2000) += pinctrl-sg2000.o obj-$(CONFIG_PINCTRL_SOPHGO_SG2002) += pinctrl-sg2002.o +obj-$(CONFIG_PINCTRL_SOPHGO_SG2042) += pinctrl-sg2042.o +obj-$(CONFIG_PINCTRL_SOPHGO_SG2044) += pinctrl-sg2044.o diff --git a/drivers/pinctrl/sophgo/pinctrl-cv1800b.c b/drivers/pinctrl/sophgo/pinctrl-cv1800b.c index 3322906689e7..82db60212477 100644 --- a/drivers/pinctrl/sophgo/pinctrl-cv1800b.c +++ b/drivers/pinctrl/sophgo/pinctrl-cv1800b.c @@ -34,8 +34,9 @@ static const char *const cv1800b_power_domain_desc[] = { [VDDIO_SD0_SPI] = "VDDIO_SD0_SPI", }; -static int cv1800b_get_pull_up(struct cv1800_pin *pin, const u32 *psmap) +static int cv1800b_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); u32 pstate = psmap[pin->power_domain]; enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); @@ -54,8 +55,9 @@ static int cv1800b_get_pull_up(struct cv1800_pin *pin, const u32 *psmap) return -ENOTSUPP; } -static int cv1800b_get_pull_down(struct cv1800_pin *pin, const u32 *psmap) +static int cv1800b_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); u32 pstate = psmap[pin->power_domain]; enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); @@ -108,9 +110,10 @@ static const u32 cv1800b_eth_oc_map[] = { 17800 }; -static int cv1800b_get_oc_map(struct cv1800_pin *pin, const u32 *psmap, +static int cv1800b_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap, const u32 **map) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); u32 pstate = psmap[pin->power_domain]; @@ -153,9 +156,10 @@ static const u32 cv1800b_18od33_3v3_schmitt_map[] = { 1100000 }; -static int cv1800b_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap, +static int cv1800b_get_schmitt_map(const struct sophgo_pin *sp, const u32 *psmap, const u32 **map) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); u32 pstate = psmap[pin->power_domain]; @@ -177,11 +181,11 @@ static int cv1800b_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap, return -ENOTSUPP; } -static const struct cv1800_vddio_cfg_ops cv1800b_vddio_cfg_ops = { +static const struct sophgo_vddio_cfg_ops cv1800b_vddio_cfg_ops = { .get_pull_up = cv1800b_get_pull_up, .get_pull_down = cv1800b_get_pull_down, .get_oc_map = cv1800b_get_oc_map, - .get_schmitt_map = cv1800b_get_schmitt_map, + .get_schmitt_map = cv1800b_get_schmitt_map, }; static const struct pinctrl_pin_desc cv1800b_pins[] = { @@ -433,13 +437,18 @@ static const struct cv1800_pin cv1800b_pin_data[ARRAY_SIZE(cv1800b_pins)] = { CV1800_PINCONF_AREA_SYS, 0x120, 5), }; -static const struct cv1800_pinctrl_data cv1800b_pindata = { +static const struct sophgo_pinctrl_data cv1800b_pindata = { .pins = cv1800b_pins, .pindata = cv1800b_pin_data, .pdnames = cv1800b_power_domain_desc, .vddio_ops = &cv1800b_vddio_cfg_ops, + .cfg_ops = &cv1800_cfg_ops, + .pctl_ops = &cv1800_pctrl_ops, + .pmx_ops = &cv1800_pmx_ops, + .pconf_ops = &cv1800_pconf_ops, .npins = ARRAY_SIZE(cv1800b_pins), - .npd = ARRAY_SIZE(cv1800b_power_domain_desc), + .npds = ARRAY_SIZE(cv1800b_power_domain_desc), + .pinsize = sizeof(struct cv1800_pin), }; static const struct of_device_id cv1800b_pinctrl_ids[] = { @@ -449,7 +458,7 @@ static const struct of_device_id cv1800b_pinctrl_ids[] = { MODULE_DEVICE_TABLE(of, cv1800b_pinctrl_ids); static struct platform_driver cv1800b_pinctrl_driver = { - .probe = cv1800_pinctrl_probe, + .probe = sophgo_pinctrl_probe, .driver = { .name = "cv1800b-pinctrl", .suppress_bind_attrs = true, diff --git a/drivers/pinctrl/sophgo/pinctrl-cv1812h.c b/drivers/pinctrl/sophgo/pinctrl-cv1812h.c index 5632290b46fa..881a4d7ef589 100644 --- a/drivers/pinctrl/sophgo/pinctrl-cv1812h.c +++ b/drivers/pinctrl/sophgo/pinctrl-cv1812h.c @@ -40,8 +40,9 @@ static const char *const cv1812h_power_domain_desc[] = { [VDDIO_VIVO] = "VDDIO_VIVO", }; -static int cv1812h_get_pull_up(struct cv1800_pin *pin, const u32 *psmap) +static int cv1812h_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); u32 pstate = psmap[pin->power_domain]; enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); @@ -60,8 +61,9 @@ static int cv1812h_get_pull_up(struct cv1800_pin *pin, const u32 *psmap) return -ENOTSUPP; } -static int cv1812h_get_pull_down(struct cv1800_pin *pin, const u32 *psmap) +static int cv1812h_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); u32 pstate = psmap[pin->power_domain]; enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); @@ -114,9 +116,10 @@ static const u32 cv1812h_eth_oc_map[] = { 17800 }; -static int cv1812h_get_oc_map(struct cv1800_pin *pin, const u32 *psmap, +static int cv1812h_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap, const u32 **map) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); u32 pstate = psmap[pin->power_domain]; @@ -159,9 +162,10 @@ static const u32 cv1812h_18od33_3v3_schmitt_map[] = { 1100000 }; -static int cv1812h_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap, +static int cv1812h_get_schmitt_map(const struct sophgo_pin *sp, const u32 *psmap, const u32 **map) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); u32 pstate = psmap[pin->power_domain]; @@ -183,11 +187,11 @@ static int cv1812h_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap, return -ENOTSUPP; } -static const struct cv1800_vddio_cfg_ops cv1812h_vddio_cfg_ops = { +static const struct sophgo_vddio_cfg_ops cv1812h_vddio_cfg_ops = { .get_pull_up = cv1812h_get_pull_up, .get_pull_down = cv1812h_get_pull_down, .get_oc_map = cv1812h_get_oc_map, - .get_schmitt_map = cv1812h_get_schmitt_map, + .get_schmitt_map = cv1812h_get_schmitt_map, }; static const struct pinctrl_pin_desc cv1812h_pins[] = { @@ -742,13 +746,18 @@ static const struct cv1800_pin cv1812h_pin_data[ARRAY_SIZE(cv1812h_pins)] = { CV1800_PINCONF_AREA_RTC, 0x028), }; -static const struct cv1800_pinctrl_data cv1812h_pindata = { +static const struct sophgo_pinctrl_data cv1812h_pindata = { .pins = cv1812h_pins, .pindata = cv1812h_pin_data, .pdnames = cv1812h_power_domain_desc, .vddio_ops = &cv1812h_vddio_cfg_ops, + .cfg_ops = &cv1800_cfg_ops, + .pctl_ops = &cv1800_pctrl_ops, + .pmx_ops = &cv1800_pmx_ops, + .pconf_ops = &cv1800_pconf_ops, .npins = ARRAY_SIZE(cv1812h_pins), - .npd = ARRAY_SIZE(cv1812h_power_domain_desc), + .npds = ARRAY_SIZE(cv1812h_power_domain_desc), + .pinsize = sizeof(struct cv1800_pin), }; static const struct of_device_id cv1812h_pinctrl_ids[] = { @@ -758,7 +767,7 @@ static const struct of_device_id cv1812h_pinctrl_ids[] = { MODULE_DEVICE_TABLE(of, cv1812h_pinctrl_ids); static struct platform_driver cv1812h_pinctrl_driver = { - .probe = cv1800_pinctrl_probe, + .probe = sophgo_pinctrl_probe, .driver = { .name = "cv1812h-pinctrl", .suppress_bind_attrs = true, diff --git a/drivers/pinctrl/sophgo/pinctrl-cv18xx.c b/drivers/pinctrl/sophgo/pinctrl-cv18xx.c index 57f2674e75d6..c3a2dcf71f2a 100644 --- a/drivers/pinctrl/sophgo/pinctrl-cv18xx.c +++ b/drivers/pinctrl/sophgo/pinctrl-cv18xx.c @@ -15,8 +15,6 @@ #include <linux/seq_file.h> #include <linux/spinlock.h> -#include <linux/pinctrl/consumer.h> -#include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> @@ -24,35 +22,15 @@ #include <dt-bindings/pinctrl/pinctrl-cv18xx.h> -#include "../core.h" #include "../pinctrl-utils.h" -#include "../pinconf.h" #include "../pinmux.h" #include "pinctrl-cv18xx.h" -struct cv1800_pinctrl { - struct device *dev; - struct pinctrl_dev *pctl_dev; - const struct cv1800_pinctrl_data *data; - struct pinctrl_desc pdesc; +struct cv1800_priv { u32 *power_cfg; - - struct mutex mutex; - raw_spinlock_t lock; - void __iomem *regs[2]; }; -struct cv1800_pin_mux_config { - struct cv1800_pin *pin; - u32 config; -}; - -static unsigned int cv1800_dt_get_pin(u32 value) -{ - return value & GENMASK(15, 0); -} - static unsigned int cv1800_dt_get_pin_mux(u32 value) { return (value >> 16) & GENMASK(7, 0); @@ -66,40 +44,28 @@ static unsigned int cv1800_dt_get_pin_mux2(u32 value) #define cv1800_pinctrl_get_component_addr(pctrl, _comp) \ ((pctrl)->regs[(_comp)->area] + (_comp)->offset) -static int cv1800_cmp_pin(const void *key, const void *pivot) -{ - const struct cv1800_pin *pin = pivot; - int pin_id = (long)key; - int pivid = pin->pin; - - return pin_id - pivid; -} - -static int cv1800_set_power_cfg(struct cv1800_pinctrl *pctrl, +static int cv1800_set_power_cfg(struct sophgo_pinctrl *pctrl, u8 domain, u32 cfg) { - if (domain >= pctrl->data->npd) + struct cv1800_priv *priv = pctrl->priv_ctrl; + + if (domain >= pctrl->data->npds) return -ENOTSUPP; - if (pctrl->power_cfg[domain] && pctrl->power_cfg[domain] != cfg) + if (priv->power_cfg[domain] && priv->power_cfg[domain] != cfg) return -EINVAL; - pctrl->power_cfg[domain] = cfg; + priv->power_cfg[domain] = cfg; return 0; } -static int cv1800_get_power_cfg(struct cv1800_pinctrl *pctrl, +static int cv1800_get_power_cfg(struct sophgo_pinctrl *pctrl, u8 domain) { - return pctrl->power_cfg[domain]; -} + struct cv1800_priv *priv = pctrl->priv_ctrl; -static struct cv1800_pin *cv1800_get_pin(struct cv1800_pinctrl *pctrl, - unsigned long pin) -{ - return bsearch((void *)pin, pctrl->data->pindata, pctrl->data->npins, - sizeof(struct cv1800_pin), cv1800_cmp_pin); + return priv->power_cfg[domain]; } #define PIN_BGA_ID_OFFSET 8 @@ -112,7 +78,7 @@ static const char *const io_type_desc[] = { "ETH" }; -static const char *cv1800_get_power_cfg_desc(struct cv1800_pinctrl *pctrl, +static const char *cv1800_get_power_cfg_desc(struct sophgo_pinctrl *pctrl, u8 domain) { return pctrl->data->pdnames[domain]; @@ -121,53 +87,57 @@ static const char *cv1800_get_power_cfg_desc(struct cv1800_pinctrl *pctrl, static void cv1800_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *seq, unsigned int pin_id) { - struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id); + struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct cv1800_priv *priv = pctrl->priv_ctrl; + const struct sophgo_pin *sp = sophgo_get_pin(pctrl, pin_id); + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); + u32 pin_hwid = pin->pin.id; u32 value; void __iomem *reg; - if (pin->pin >> PIN_BGA_ID_OFFSET) + if (pin_hwid >> PIN_BGA_ID_OFFSET) seq_printf(seq, "pos: %c%u ", - 'A' + (pin->pin >> PIN_BGA_ID_OFFSET) - 1, - pin->pin & PIN_BGA_ID_MASK); + 'A' + (pin_hwid >> PIN_BGA_ID_OFFSET) - 1, + pin_hwid & PIN_BGA_ID_MASK); else - seq_printf(seq, "pos: %u ", pin->pin); + seq_printf(seq, "pos: %u ", pin_hwid); seq_printf(seq, "power-domain: %s ", cv1800_get_power_cfg_desc(pctrl, pin->power_domain)); seq_printf(seq, "type: %s ", io_type_desc[type]); - reg = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux); + reg = cv1800_pinctrl_get_component_addr(priv, &pin->mux); value = readl(reg); seq_printf(seq, "mux: 0x%08x ", value); - if (pin->flags & CV1800_PIN_HAVE_MUX2) { - reg = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux2); + if (pin->pin.flags & CV1800_PIN_HAVE_MUX2) { + reg = cv1800_pinctrl_get_component_addr(priv, &pin->mux2); value = readl(reg); seq_printf(seq, "mux2: 0x%08x ", value); } if (type == IO_TYPE_1V8_ONLY || type == IO_TYPE_1V8_OR_3V3) { - reg = cv1800_pinctrl_get_component_addr(pctrl, &pin->conf); + reg = cv1800_pinctrl_get_component_addr(priv, &pin->conf); value = readl(reg); seq_printf(seq, "conf: 0x%08x ", value); } } -static int cv1800_verify_pinmux_config(const struct cv1800_pin_mux_config *config) +static int cv1800_verify_pinmux_config(const struct sophgo_pin_mux_config *config) { + struct cv1800_pin *pin = sophgo_to_cv1800_pin(config->pin); unsigned int mux = cv1800_dt_get_pin_mux(config->config); unsigned int mux2 = cv1800_dt_get_pin_mux2(config->config); - if (mux > config->pin->mux.max) + if (mux > pin->mux.max) return -EINVAL; - if (config->pin->flags & CV1800_PIN_HAVE_MUX2) { - if (mux != config->pin->mux2.pfunc) + if (pin->pin.flags & CV1800_PIN_HAVE_MUX2) { + if (mux != pin->mux2.pfunc) return -EINVAL; - if (mux2 > config->pin->mux2.max) + if (mux2 > pin->mux2.max) return -EINVAL; } else { if (mux2 != PIN_MUX_INVALD) @@ -177,9 +147,10 @@ static int cv1800_verify_pinmux_config(const struct cv1800_pin_mux_config *confi return 0; } -static int cv1800_verify_pin_group(const struct cv1800_pin_mux_config *mux, - unsigned long npins) +static int cv1800_verify_pin_group(const struct sophgo_pin_mux_config *mux, + unsigned int npins) { + struct cv1800_pin *pin; enum cv1800_pin_io_type type; u8 power_domain; int i; @@ -187,232 +158,78 @@ static int cv1800_verify_pin_group(const struct cv1800_pin_mux_config *mux, if (npins == 1) return 0; - type = cv1800_pin_io_type(mux[0].pin); - power_domain = mux[0].pin->power_domain; + pin = sophgo_to_cv1800_pin(mux[0].pin); + type = cv1800_pin_io_type(pin); + power_domain = pin->power_domain; for (i = 0; i < npins; i++) { - if (type != cv1800_pin_io_type(mux[i].pin) || - power_domain != mux[i].pin->power_domain) + pin = sophgo_to_cv1800_pin(mux[i].pin); + + if (type != cv1800_pin_io_type(pin) || + power_domain != pin->power_domain) return -ENOTSUPP; } return 0; } -static int cv1800_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **maps, - unsigned int *num_maps) +static int cv1800_dt_node_to_map_post(struct device_node *cur, + struct sophgo_pinctrl *pctrl, + struct sophgo_pin_mux_config *pinmuxs, + unsigned int npins) { - struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - struct device *dev = pctrl->dev; - struct device_node *child; - struct pinctrl_map *map; - const char **grpnames; - const char *grpname; - int ngroups = 0; - int nmaps = 0; + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(pinmuxs[0].pin); + u32 power; int ret; - for_each_available_child_of_node(np, child) - ngroups += 1; - - grpnames = devm_kcalloc(dev, ngroups, sizeof(*grpnames), GFP_KERNEL); - if (!grpnames) - return -ENOMEM; - - map = kcalloc(ngroups * 2, sizeof(*map), GFP_KERNEL); - if (!map) - return -ENOMEM; - - ngroups = 0; - mutex_lock(&pctrl->mutex); - for_each_available_child_of_node(np, child) { - int npins = of_property_count_u32_elems(child, "pinmux"); - unsigned int *pins; - struct cv1800_pin_mux_config *pinmuxs; - u32 config, power; - int i; - - if (npins < 1) { - dev_err(dev, "invalid pinctrl group %pOFn.%pOFn\n", - np, child); - ret = -EINVAL; - goto dt_failed; - } - - grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", - np, child); - if (!grpname) { - ret = -ENOMEM; - goto dt_failed; - } - - grpnames[ngroups++] = grpname; - - pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); - if (!pins) { - ret = -ENOMEM; - goto dt_failed; - } - - pinmuxs = devm_kcalloc(dev, npins, sizeof(*pinmuxs), GFP_KERNEL); - if (!pinmuxs) { - ret = -ENOMEM; - goto dt_failed; - } - - for (i = 0; i < npins; i++) { - ret = of_property_read_u32_index(child, "pinmux", - i, &config); - if (ret) - goto dt_failed; - - pins[i] = cv1800_dt_get_pin(config); - pinmuxs[i].config = config; - pinmuxs[i].pin = cv1800_get_pin(pctrl, pins[i]); - - if (!pinmuxs[i].pin) { - dev_err(dev, "failed to get pin %d\n", pins[i]); - ret = -ENODEV; - goto dt_failed; - } - - ret = cv1800_verify_pinmux_config(&pinmuxs[i]); - if (ret) { - dev_err(dev, "group %s pin %d is invalid\n", - grpname, i); - goto dt_failed; - } - } - - ret = cv1800_verify_pin_group(pinmuxs, npins); - if (ret) { - dev_err(dev, "group %s is invalid\n", grpname); - goto dt_failed; - } - - ret = of_property_read_u32(child, "power-source", &power); - if (ret) - goto dt_failed; - - if (!(power == PIN_POWER_STATE_3V3 || power == PIN_POWER_STATE_1V8)) { - dev_err(dev, "group %s have unsupported power: %u\n", - grpname, power); - ret = -ENOTSUPP; - goto dt_failed; - } - - ret = cv1800_set_power_cfg(pctrl, pinmuxs[0].pin->power_domain, - power); - if (ret) - goto dt_failed; - - map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP; - map[nmaps].data.mux.function = np->name; - map[nmaps].data.mux.group = grpname; - nmaps += 1; - - ret = pinconf_generic_parse_dt_config(child, pctldev, - &map[nmaps].data.configs.configs, - &map[nmaps].data.configs.num_configs); - if (ret) { - dev_err(dev, "failed to parse pin config of group %s: %d\n", - grpname, ret); - goto dt_failed; - } - - ret = pinctrl_generic_add_group(pctldev, grpname, - pins, npins, pinmuxs); - if (ret < 0) { - dev_err(dev, "failed to add group %s: %d\n", grpname, ret); - goto dt_failed; - } - - /* don't create a map if there are no pinconf settings */ - if (map[nmaps].data.configs.num_configs == 0) - continue; - - map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; - map[nmaps].data.configs.group_or_pin = grpname; - nmaps += 1; - } - - ret = pinmux_generic_add_function(pctldev, np->name, - grpnames, ngroups, NULL); - if (ret < 0) { - dev_err(dev, "error adding function %s: %d\n", np->name, ret); - goto function_failed; - } - - *maps = map; - *num_maps = nmaps; - mutex_unlock(&pctrl->mutex); + ret = of_property_read_u32(cur, "power-source", &power); + if (ret) + return ret; - return 0; + if (!(power == PIN_POWER_STATE_3V3 || power == PIN_POWER_STATE_1V8)) + return -ENOTSUPP; -dt_failed: - of_node_put(child); -function_failed: - pinctrl_utils_free_map(pctldev, map, nmaps); - mutex_unlock(&pctrl->mutex); - return ret; + return cv1800_set_power_cfg(pctrl, pin->power_domain, power); } -static const struct pinctrl_ops cv1800_pctrl_ops = { +const struct pinctrl_ops cv1800_pctrl_ops = { .get_groups_count = pinctrl_generic_get_group_count, .get_group_name = pinctrl_generic_get_group_name, .get_group_pins = pinctrl_generic_get_group_pins, .pin_dbg_show = cv1800_pctrl_dbg_show, - .dt_node_to_map = cv1800_pctrl_dt_node_to_map, + .dt_node_to_map = sophgo_pctrl_dt_node_to_map, .dt_free_map = pinctrl_utils_free_map, }; +EXPORT_SYMBOL_GPL(cv1800_pctrl_ops); -static int cv1800_pmx_set_mux(struct pinctrl_dev *pctldev, - unsigned int fsel, unsigned int gsel) +static void cv1800_set_pinmux_config(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp, u32 config) { - struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - const struct group_desc *group; - const struct cv1800_pin_mux_config *configs; - unsigned int i; - - group = pinctrl_generic_get_group(pctldev, gsel); - if (!group) - return -EINVAL; - - configs = group->data; - - for (i = 0; i < group->grp.npins; i++) { - const struct cv1800_pin *pin = configs[i].pin; - u32 value = configs[i].config; - void __iomem *reg_mux; - void __iomem *reg_mux2; - unsigned long flags; - u32 mux; - u32 mux2; - - reg_mux = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux); - reg_mux2 = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux2); - mux = cv1800_dt_get_pin_mux(value); - mux2 = cv1800_dt_get_pin_mux2(value); - - raw_spin_lock_irqsave(&pctrl->lock, flags); - writel_relaxed(mux, reg_mux); - if (mux2 != PIN_MUX_INVALD) - writel_relaxed(mux2, reg_mux2); - raw_spin_unlock_irqrestore(&pctrl->lock, flags); - } - - return 0; + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); + struct cv1800_priv *priv = pctrl->priv_ctrl; + void __iomem *reg_mux; + void __iomem *reg_mux2; + u32 mux; + u32 mux2; + + reg_mux = cv1800_pinctrl_get_component_addr(priv, &pin->mux); + reg_mux2 = cv1800_pinctrl_get_component_addr(priv, &pin->mux2); + mux = cv1800_dt_get_pin_mux(config); + mux2 = cv1800_dt_get_pin_mux2(config); + + writel_relaxed(mux, reg_mux); + if (mux2 != PIN_MUX_INVALD) + writel_relaxed(mux2, reg_mux2); } -static const struct pinmux_ops cv1800_pmx_ops = { +const struct pinmux_ops cv1800_pmx_ops = { .get_functions_count = pinmux_generic_get_function_count, .get_function_name = pinmux_generic_get_function_name, .get_function_groups = pinmux_generic_get_function_groups, - .set_mux = cv1800_pmx_set_mux, + .set_mux = sophgo_pmx_set_mux, .strict = true, }; +EXPORT_SYMBOL_GPL(cv1800_pmx_ops); #define PIN_IO_PULLUP BIT(2) #define PIN_IO_PULLDOWN BIT(3) @@ -421,94 +238,14 @@ static const struct pinmux_ops cv1800_pmx_ops = { #define PIN_IO_BUS_HOLD BIT(10) #define PIN_IO_OUT_FAST_SLEW BIT(11) -static u32 cv1800_pull_down_typical_resistor(struct cv1800_pinctrl *pctrl, - struct cv1800_pin *pin) -{ - return pctrl->data->vddio_ops->get_pull_down(pin, pctrl->power_cfg); -} - -static u32 cv1800_pull_up_typical_resistor(struct cv1800_pinctrl *pctrl, - struct cv1800_pin *pin) -{ - return pctrl->data->vddio_ops->get_pull_up(pin, pctrl->power_cfg); -} - -static int cv1800_pinctrl_oc2reg(struct cv1800_pinctrl *pctrl, - struct cv1800_pin *pin, u32 target) -{ - const u32 *map; - int i, len; - - len = pctrl->data->vddio_ops->get_oc_map(pin, pctrl->power_cfg, &map); - if (len < 0) - return len; - - for (i = 0; i < len; i++) { - if (map[i] >= target) - return i; - } - - return -EINVAL; -} - -static int cv1800_pinctrl_reg2oc(struct cv1800_pinctrl *pctrl, - struct cv1800_pin *pin, u32 reg) -{ - const u32 *map; - int len; - - len = pctrl->data->vddio_ops->get_oc_map(pin, pctrl->power_cfg, &map); - if (len < 0) - return len; - - if (reg >= len) - return -EINVAL; - - return map[reg]; -} - -static int cv1800_pinctrl_schmitt2reg(struct cv1800_pinctrl *pctrl, - struct cv1800_pin *pin, u32 target) -{ - const u32 *map; - int i, len; - - len = pctrl->data->vddio_ops->get_schmitt_map(pin, pctrl->power_cfg, - &map); - if (len < 0) - return len; - - for (i = 0; i < len; i++) { - if (map[i] == target) - return i; - } - - return -EINVAL; -} - -static int cv1800_pinctrl_reg2schmitt(struct cv1800_pinctrl *pctrl, - struct cv1800_pin *pin, u32 reg) -{ - const u32 *map; - int len; - - len = pctrl->data->vddio_ops->get_schmitt_map(pin, pctrl->power_cfg, - &map); - if (len < 0) - return len; - - if (reg >= len) - return -EINVAL; - - return map[reg]; -} - static int cv1800_pconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id, unsigned long *config) { - struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct cv1800_priv *priv = pctrl->priv_ctrl; int param = pinconf_to_config_param(*config); - struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id); + const struct sophgo_pin *sp = sophgo_get_pin(pctrl, pin_id); + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type; u32 value; u32 arg; @@ -522,28 +259,28 @@ static int cv1800_pconf_get(struct pinctrl_dev *pctldev, if (type == IO_TYPE_ETH || type == IO_TYPE_AUDIO) return -ENOTSUPP; - value = readl(cv1800_pinctrl_get_component_addr(pctrl, &pin->conf)); + value = readl(cv1800_pinctrl_get_component_addr(priv, &pin->conf)); switch (param) { case PIN_CONFIG_BIAS_PULL_DOWN: enabled = FIELD_GET(PIN_IO_PULLDOWN, value); - arg = cv1800_pull_down_typical_resistor(pctrl, pin); + arg = sophgo_pinctrl_typical_pull_down(pctrl, sp, priv->power_cfg); break; case PIN_CONFIG_BIAS_PULL_UP: enabled = FIELD_GET(PIN_IO_PULLUP, value); - arg = cv1800_pull_up_typical_resistor(pctrl, pin); + arg = sophgo_pinctrl_typical_pull_up(pctrl, sp, priv->power_cfg); break; case PIN_CONFIG_DRIVE_STRENGTH_UA: enabled = true; arg = FIELD_GET(PIN_IO_DRIVE, value); - ret = cv1800_pinctrl_reg2oc(pctrl, pin, arg); + ret = sophgo_pinctrl_reg2oc(pctrl, sp, priv->power_cfg, arg); if (ret < 0) return ret; arg = ret; break; case PIN_CONFIG_INPUT_SCHMITT_UV: arg = FIELD_GET(PIN_IO_SCHMITT, value); - ret = cv1800_pinctrl_reg2schmitt(pctrl, pin, arg); + ret = sophgo_pinctrl_reg2schmitt(pctrl, sp, priv->power_cfg, arg); if (ret < 0) return ret; arg = ret; @@ -570,14 +307,16 @@ static int cv1800_pconf_get(struct pinctrl_dev *pctldev, return enabled ? 0 : -EINVAL; } -static int cv1800_pinconf_compute_config(struct cv1800_pinctrl *pctrl, - struct cv1800_pin *pin, +static int cv1800_pinconf_compute_config(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp, unsigned long *configs, unsigned int num_configs, - u32 *value) + u32 *value, u32 *mask) { + struct cv1800_priv *priv = pctrl->priv_ctrl; + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); int i; - u32 v = 0; + u32 v = 0, m = 0; enum cv1800_pin_io_type type; int ret; @@ -596,24 +335,30 @@ static int cv1800_pinconf_compute_config(struct cv1800_pinctrl *pctrl, case PIN_CONFIG_BIAS_PULL_DOWN: v &= ~PIN_IO_PULLDOWN; v |= FIELD_PREP(PIN_IO_PULLDOWN, arg); + m |= PIN_IO_PULLDOWN; break; case PIN_CONFIG_BIAS_PULL_UP: v &= ~PIN_IO_PULLUP; v |= FIELD_PREP(PIN_IO_PULLUP, arg); + m |= PIN_IO_PULLUP; break; case PIN_CONFIG_DRIVE_STRENGTH_UA: - ret = cv1800_pinctrl_oc2reg(pctrl, pin, arg); + ret = sophgo_pinctrl_oc2reg(pctrl, sp, + priv->power_cfg, arg); if (ret < 0) return ret; v &= ~PIN_IO_DRIVE; v |= FIELD_PREP(PIN_IO_DRIVE, ret); + m |= PIN_IO_DRIVE; break; case PIN_CONFIG_INPUT_SCHMITT_UV: - ret = cv1800_pinctrl_schmitt2reg(pctrl, pin, arg); + ret = sophgo_pinctrl_schmitt2reg(pctrl, sp, + priv->power_cfg, arg); if (ret < 0) return ret; v &= ~PIN_IO_SCHMITT; v |= FIELD_PREP(PIN_IO_SCHMITT, ret); + m |= PIN_IO_SCHMITT; break; case PIN_CONFIG_POWER_SOURCE: /* Ignore power source as it is always fixed */ @@ -621,10 +366,12 @@ static int cv1800_pinconf_compute_config(struct cv1800_pinctrl *pctrl, case PIN_CONFIG_SLEW_RATE: v &= ~PIN_IO_OUT_FAST_SLEW; v |= FIELD_PREP(PIN_IO_OUT_FAST_SLEW, arg); + m |= PIN_IO_OUT_FAST_SLEW; break; case PIN_CONFIG_BIAS_BUS_HOLD: v &= ~PIN_IO_BUS_HOLD; v |= FIELD_PREP(PIN_IO_BUS_HOLD, arg); + m |= PIN_IO_BUS_HOLD; break; default: return -ENOTSUPP; @@ -632,134 +379,73 @@ static int cv1800_pinconf_compute_config(struct cv1800_pinctrl *pctrl, } *value = v; + *mask = m; return 0; } -static int cv1800_pin_set_config(struct cv1800_pinctrl *pctrl, - unsigned int pin_id, - u32 value) +static int cv1800_set_pinconf_config(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp, + u32 value, u32 mask) { - struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id); - unsigned long flags; + struct cv1800_priv *priv = pctrl->priv_ctrl; + struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); void __iomem *addr; + u32 reg; - if (!pin) - return -EINVAL; - - addr = cv1800_pinctrl_get_component_addr(pctrl, &pin->conf); + addr = cv1800_pinctrl_get_component_addr(priv, &pin->conf); - raw_spin_lock_irqsave(&pctrl->lock, flags); - writel(value, addr); - raw_spin_unlock_irqrestore(&pctrl->lock, flags); + reg = readl(addr); + reg &= ~mask; + reg |= value; + writel(reg, addr); return 0; } -static int cv1800_pconf_set(struct pinctrl_dev *pctldev, - unsigned int pin_id, unsigned long *configs, - unsigned int num_configs) -{ - struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id); - u32 value; - - if (!pin) - return -ENODEV; - - if (cv1800_pinconf_compute_config(pctrl, pin, - configs, num_configs, &value)) - return -ENOTSUPP; - - return cv1800_pin_set_config(pctrl, pin_id, value); -} - -static int cv1800_pconf_group_set(struct pinctrl_dev *pctldev, - unsigned int gsel, - unsigned long *configs, - unsigned int num_configs) -{ - struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - const struct group_desc *group; - const struct cv1800_pin_mux_config *pinmuxs; - u32 value; - int i; - - group = pinctrl_generic_get_group(pctldev, gsel); - if (!group) - return -EINVAL; - - pinmuxs = group->data; - - if (cv1800_pinconf_compute_config(pctrl, pinmuxs[0].pin, - configs, num_configs, &value)) - return -ENOTSUPP; - - for (i = 0; i < group->grp.npins; i++) - cv1800_pin_set_config(pctrl, group->grp.pins[i], value); - - return 0; -} - -static const struct pinconf_ops cv1800_pconf_ops = { +const struct pinconf_ops cv1800_pconf_ops = { .pin_config_get = cv1800_pconf_get, - .pin_config_set = cv1800_pconf_set, - .pin_config_group_set = cv1800_pconf_group_set, + .pin_config_set = sophgo_pconf_set, + .pin_config_group_set = sophgo_pconf_group_set, .is_generic = true, }; +EXPORT_SYMBOL_GPL(cv1800_pconf_ops); -int cv1800_pinctrl_probe(struct platform_device *pdev) +static int cv1800_pinctrl_init(struct platform_device *pdev, + struct sophgo_pinctrl *pctrl) { - struct device *dev = &pdev->dev; - struct cv1800_pinctrl *pctrl; - const struct cv1800_pinctrl_data *pctrl_data; - int ret; - - pctrl_data = device_get_match_data(dev); - if (!pctrl_data) - return -ENODEV; + const struct sophgo_pinctrl_data *pctrl_data = pctrl->data; + struct cv1800_priv *priv; - if (pctrl_data->npins == 0 || pctrl_data->npd == 0) - return dev_err_probe(dev, -EINVAL, "invalid pin data\n"); - - pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); - if (!pctrl) + priv = devm_kzalloc(&pdev->dev, sizeof(struct cv1800_priv), GFP_KERNEL); + if (!priv) return -ENOMEM; - pctrl->power_cfg = devm_kcalloc(dev, pctrl_data->npd, - sizeof(u32), GFP_KERNEL); - if (!pctrl->power_cfg) + priv->power_cfg = devm_kcalloc(&pdev->dev, pctrl_data->npds, + sizeof(u32), GFP_KERNEL); + if (!priv->power_cfg) return -ENOMEM; - pctrl->regs[0] = devm_platform_ioremap_resource_byname(pdev, "sys"); - if (IS_ERR(pctrl->regs[0])) - return PTR_ERR(pctrl->regs[0]); - - pctrl->regs[1] = devm_platform_ioremap_resource_byname(pdev, "rtc"); - if (IS_ERR(pctrl->regs[1])) - return PTR_ERR(pctrl->regs[1]); - - pctrl->pdesc.name = dev_name(dev); - pctrl->pdesc.pins = pctrl_data->pins; - pctrl->pdesc.npins = pctrl_data->npins; - pctrl->pdesc.pctlops = &cv1800_pctrl_ops; - pctrl->pdesc.pmxops = &cv1800_pmx_ops; - pctrl->pdesc.confops = &cv1800_pconf_ops; - pctrl->pdesc.owner = THIS_MODULE; - - pctrl->data = pctrl_data; - pctrl->dev = dev; - raw_spin_lock_init(&pctrl->lock); - mutex_init(&pctrl->mutex); + priv->regs[0] = devm_platform_ioremap_resource_byname(pdev, "sys"); + if (IS_ERR(priv->regs[0])) + return PTR_ERR(priv->regs[0]); - platform_set_drvdata(pdev, pctrl); + priv->regs[1] = devm_platform_ioremap_resource_byname(pdev, "rtc"); + if (IS_ERR(priv->regs[1])) + return PTR_ERR(priv->regs[1]); - ret = devm_pinctrl_register_and_init(dev, &pctrl->pdesc, - pctrl, &pctrl->pctl_dev); - if (ret) - return dev_err_probe(dev, ret, - "fail to register pinctrl driver\n"); + pctrl->priv_ctrl = priv; - return pinctrl_enable(pctrl->pctl_dev); + return 0; } -EXPORT_SYMBOL_GPL(cv1800_pinctrl_probe); + +const struct sophgo_cfg_ops cv1800_cfg_ops = { + .pctrl_init = cv1800_pinctrl_init, + .verify_pinmux_config = cv1800_verify_pinmux_config, + .verify_pin_group = cv1800_verify_pin_group, + .dt_node_to_map_post = cv1800_dt_node_to_map_post, + .compute_pinconf_config = cv1800_pinconf_compute_config, + .set_pinconf_config = cv1800_set_pinconf_config, + .set_pinmux_config = cv1800_set_pinmux_config, +}; +EXPORT_SYMBOL_GPL(cv1800_cfg_ops); diff --git a/drivers/pinctrl/sophgo/pinctrl-cv18xx.h b/drivers/pinctrl/sophgo/pinctrl-cv18xx.h index 1a9998abb3b7..759c0e604acf 100644 --- a/drivers/pinctrl/sophgo/pinctrl-cv18xx.h +++ b/drivers/pinctrl/sophgo/pinctrl-cv18xx.h @@ -8,13 +8,14 @@ #include <linux/bits.h> #include <linux/bitfield.h> -#include <linux/device.h> #include <linux/mutex.h> #include <linux/spinlock.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinconf.h> +#include "pinctrl-sophgo.h" + enum cv1800_pin_io_type { IO_TYPE_1V8_ONLY = 0, IO_TYPE_1V8_OR_3V3 = 1, @@ -49,58 +50,37 @@ struct cv1800_pinconf { #define CV1800_PIN_FLAG_IO_TYPE(type) \ FIELD_PREP_CONST(CV1800_PIN_IO_TYPE, type) struct cv1800_pin { - u16 pin; - u16 flags; + struct sophgo_pin pin; u8 power_domain; struct cv1800_pinmux mux; struct cv1800_pinmux2 mux2; struct cv1800_pinconf conf; }; +#define sophgo_to_cv1800_pin(_pin) \ + container_of((_pin), struct cv1800_pin, pin) + #define PIN_POWER_STATE_1V8 1800 #define PIN_POWER_STATE_3V3 3300 -/** - * struct cv1800_vddio_cfg_ops - pin vddio operations - * - * @get_pull_up: get resistor for pull up; - * @get_pull_down: get resistor for pull down. - * @get_oc_map: get mapping for typical low level output current value to - * register value map. - * @get_schmitt_map: get mapping for register value to typical schmitt - * threshold. - */ -struct cv1800_vddio_cfg_ops { - int (*get_pull_up)(struct cv1800_pin *pin, const u32 *psmap); - int (*get_pull_down)(struct cv1800_pin *pin, const u32 *psmap); - int (*get_oc_map)(struct cv1800_pin *pin, const u32 *psmap, - const u32 **map); - int (*get_schmitt_map)(struct cv1800_pin *pin, const u32 *psmap, - const u32 **map); -}; - -struct cv1800_pinctrl_data { - const struct pinctrl_pin_desc *pins; - const struct cv1800_pin *pindata; - const char * const *pdnames; - const struct cv1800_vddio_cfg_ops *vddio_ops; - u16 npins; - u16 npd; -}; - -static inline enum cv1800_pin_io_type cv1800_pin_io_type(struct cv1800_pin *pin) +static inline enum cv1800_pin_io_type cv1800_pin_io_type(const struct cv1800_pin *pin) { - return FIELD_GET(CV1800_PIN_IO_TYPE, pin->flags); + return FIELD_GET(CV1800_PIN_IO_TYPE, pin->pin.flags); }; -int cv1800_pinctrl_probe(struct platform_device *pdev); +extern const struct pinctrl_ops cv1800_pctrl_ops; +extern const struct pinmux_ops cv1800_pmx_ops; +extern const struct pinconf_ops cv1800_pconf_ops; +extern const struct sophgo_cfg_ops cv1800_cfg_ops; #define CV1800_FUNC_PIN(_id, _power_domain, _type, \ _mux_area, _mux_offset, _mux_func_max) \ { \ - .pin = (_id), \ + .pin = { \ + .id = (_id), \ + .flags = CV1800_PIN_FLAG_IO_TYPE(_type), \ + }, \ .power_domain = (_power_domain), \ - .flags = CV1800_PIN_FLAG_IO_TYPE(_type), \ .mux = { \ .area = (_mux_area), \ .offset = (_mux_offset), \ @@ -112,9 +92,11 @@ int cv1800_pinctrl_probe(struct platform_device *pdev); _mux_area, _mux_offset, _mux_func_max, \ _conf_area, _conf_offset) \ { \ - .pin = (_id), \ + .pin = { \ + .id = (_id), \ + .flags = CV1800_PIN_FLAG_IO_TYPE(_type), \ + }, \ .power_domain = (_power_domain), \ - .flags = CV1800_PIN_FLAG_IO_TYPE(_type), \ .mux = { \ .area = (_mux_area), \ .offset = (_mux_offset), \ @@ -132,10 +114,12 @@ int cv1800_pinctrl_probe(struct platform_device *pdev); _mux2_func_max, \ _conf_area, _conf_offset) \ { \ - .pin = (_id), \ + .pin = { \ + .id = (_id), \ + .flags = CV1800_PIN_FLAG_IO_TYPE(_type) | \ + CV1800_PIN_HAVE_MUX2, \ + }, \ .power_domain = (_power_domain), \ - .flags = CV1800_PIN_FLAG_IO_TYPE(_type) | \ - CV1800_PIN_HAVE_MUX2, \ .mux = { \ .area = (_mux_area), \ .offset = (_mux_offset), \ diff --git a/drivers/pinctrl/sophgo/pinctrl-sg2000.c b/drivers/pinctrl/sophgo/pinctrl-sg2000.c index 63c05b4dd68f..0e303d2fa104 100644 --- a/drivers/pinctrl/sophgo/pinctrl-sg2000.c +++ b/drivers/pinctrl/sophgo/pinctrl-sg2000.c @@ -40,8 +40,9 @@ static const char *const sg2000_power_domain_desc[] = { [VDDIO_VIVO] = "VDDIO_VIVO", }; -static int sg2000_get_pull_up(struct cv1800_pin *pin, const u32 *psmap) +static int sg2000_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); u32 pstate = psmap[pin->power_domain]; enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); @@ -60,8 +61,9 @@ static int sg2000_get_pull_up(struct cv1800_pin *pin, const u32 *psmap) return -ENOTSUPP; } -static int sg2000_get_pull_down(struct cv1800_pin *pin, const u32 *psmap) +static int sg2000_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); u32 pstate = psmap[pin->power_domain]; enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); @@ -114,9 +116,10 @@ static const u32 sg2000_eth_oc_map[] = { 17800 }; -static int sg2000_get_oc_map(struct cv1800_pin *pin, const u32 *psmap, +static int sg2000_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap, const u32 **map) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); u32 pstate = psmap[pin->power_domain]; @@ -159,9 +162,10 @@ static const u32 sg2000_18od33_3v3_schmitt_map[] = { 1100000 }; -static int sg2000_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap, +static int sg2000_get_schmitt_map(const struct sophgo_pin *sp, const u32 *psmap, const u32 **map) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); u32 pstate = psmap[pin->power_domain]; @@ -183,11 +187,11 @@ static int sg2000_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap, return -ENOTSUPP; } -static const struct cv1800_vddio_cfg_ops sg2000_vddio_cfg_ops = { +static const struct sophgo_vddio_cfg_ops sg2000_vddio_cfg_ops = { .get_pull_up = sg2000_get_pull_up, .get_pull_down = sg2000_get_pull_down, .get_oc_map = sg2000_get_oc_map, - .get_schmitt_map = sg2000_get_schmitt_map, + .get_schmitt_map = sg2000_get_schmitt_map, }; static const struct pinctrl_pin_desc sg2000_pins[] = { @@ -742,13 +746,18 @@ static const struct cv1800_pin sg2000_pin_data[ARRAY_SIZE(sg2000_pins)] = { CV1800_PINCONF_AREA_RTC, 0x028), }; -static const struct cv1800_pinctrl_data sg2000_pindata = { +static const struct sophgo_pinctrl_data sg2000_pindata = { .pins = sg2000_pins, .pindata = sg2000_pin_data, .pdnames = sg2000_power_domain_desc, .vddio_ops = &sg2000_vddio_cfg_ops, + .cfg_ops = &cv1800_cfg_ops, + .pctl_ops = &cv1800_pctrl_ops, + .pmx_ops = &cv1800_pmx_ops, + .pconf_ops = &cv1800_pconf_ops, .npins = ARRAY_SIZE(sg2000_pins), - .npd = ARRAY_SIZE(sg2000_power_domain_desc), + .npds = ARRAY_SIZE(sg2000_power_domain_desc), + .pinsize = sizeof(struct cv1800_pin), }; static const struct of_device_id sg2000_pinctrl_ids[] = { @@ -758,7 +767,7 @@ static const struct of_device_id sg2000_pinctrl_ids[] = { MODULE_DEVICE_TABLE(of, sg2000_pinctrl_ids); static struct platform_driver sg2000_pinctrl_driver = { - .probe = cv1800_pinctrl_probe, + .probe = sophgo_pinctrl_probe, .driver = { .name = "sg2000-pinctrl", .suppress_bind_attrs = true, diff --git a/drivers/pinctrl/sophgo/pinctrl-sg2002.c b/drivers/pinctrl/sophgo/pinctrl-sg2002.c index 5c49208dcb59..2443fff1bc00 100644 --- a/drivers/pinctrl/sophgo/pinctrl-sg2002.c +++ b/drivers/pinctrl/sophgo/pinctrl-sg2002.c @@ -34,8 +34,9 @@ static const char *const sg2002_power_domain_desc[] = { [VDDIO_SD1] = "VDDIO_SD1", }; -static int sg2002_get_pull_up(struct cv1800_pin *pin, const u32 *psmap) +static int sg2002_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); u32 pstate = psmap[pin->power_domain]; enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); @@ -54,8 +55,9 @@ static int sg2002_get_pull_up(struct cv1800_pin *pin, const u32 *psmap) return -ENOTSUPP; } -static int sg2002_get_pull_down(struct cv1800_pin *pin, const u32 *psmap) +static int sg2002_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); u32 pstate = psmap[pin->power_domain]; enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); @@ -108,9 +110,10 @@ static const u32 sg2002_eth_oc_map[] = { 17800 }; -static int sg2002_get_oc_map(struct cv1800_pin *pin, const u32 *psmap, +static int sg2002_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap, const u32 **map) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); u32 pstate = psmap[pin->power_domain]; @@ -153,9 +156,10 @@ static const u32 sg2002_18od33_3v3_schmitt_map[] = { 1100000 }; -static int sg2002_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap, +static int sg2002_get_schmitt_map(const struct sophgo_pin *sp, const u32 *psmap, const u32 **map) { + const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp); enum cv1800_pin_io_type type = cv1800_pin_io_type(pin); u32 pstate = psmap[pin->power_domain]; @@ -177,11 +181,11 @@ static int sg2002_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap, return -ENOTSUPP; } -static const struct cv1800_vddio_cfg_ops sg2002_vddio_cfg_ops = { +static const struct sophgo_vddio_cfg_ops sg2002_vddio_cfg_ops = { .get_pull_up = sg2002_get_pull_up, .get_pull_down = sg2002_get_pull_down, .get_oc_map = sg2002_get_oc_map, - .get_schmitt_map = sg2002_get_schmitt_map, + .get_schmitt_map = sg2002_get_schmitt_map, }; static const struct pinctrl_pin_desc sg2002_pins[] = { @@ -513,13 +517,18 @@ static const struct cv1800_pin sg2002_pin_data[ARRAY_SIZE(sg2002_pins)] = { CV1800_PINCONF_AREA_SYS, 0xc84), }; -static const struct cv1800_pinctrl_data sg2002_pindata = { +static const struct sophgo_pinctrl_data sg2002_pindata = { .pins = sg2002_pins, .pindata = sg2002_pin_data, .pdnames = sg2002_power_domain_desc, .vddio_ops = &sg2002_vddio_cfg_ops, + .cfg_ops = &cv1800_cfg_ops, + .pctl_ops = &cv1800_pctrl_ops, + .pmx_ops = &cv1800_pmx_ops, + .pconf_ops = &cv1800_pconf_ops, .npins = ARRAY_SIZE(sg2002_pins), - .npd = ARRAY_SIZE(sg2002_power_domain_desc), + .npds = ARRAY_SIZE(sg2002_power_domain_desc), + .pinsize = sizeof(struct cv1800_pin), }; static const struct of_device_id sg2002_pinctrl_ids[] = { @@ -529,7 +538,7 @@ static const struct of_device_id sg2002_pinctrl_ids[] = { MODULE_DEVICE_TABLE(of, sg2002_pinctrl_ids); static struct platform_driver sg2002_pinctrl_driver = { - .probe = cv1800_pinctrl_probe, + .probe = sophgo_pinctrl_probe, .driver = { .name = "sg2002-pinctrl", .suppress_bind_attrs = true, diff --git a/drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c b/drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c new file mode 100644 index 000000000000..0526aa3f8438 --- /dev/null +++ b/drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sophgo sg2042 SoCs pinctrl driver. + * + * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com> + * + */ + +#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/cleanup.h> +#include <linux/export.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/spinlock.h> + +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include "../pinctrl-utils.h" +#include "../pinmux.h" + +#include "pinctrl-sg2042.h" + +#define PIN_IO_PULL_ONE_ENABLE BIT(0) +#define PIN_IO_PULL_DIR_UP (BIT(1) | PIN_IO_PULL_ONE_ENABLE) +#define PIN_IO_PULL_DIR_DOWN (0 | PIN_IO_PULL_ONE_ENABLE) +#define PIN_IO_PULL_ONE_MASK GENMASK(1, 0) + +#define PIN_IO_PULL_UP BIT(2) +#define PIN_IO_PULL_UP_DONW BIT(3) +#define PIN_IO_PULL_UP_MASK GENMASK(3, 2) + +#define PIN_IO_MUX GENMASK(5, 4) +#define PIN_IO_DRIVE GENMASK(9, 6) +#define PIN_IO_SCHMITT_ENABLE BIT(10) +#define PIN_IO_OUTPUT_ENABLE BIT(11) + +struct sg2042_priv { + void __iomem *regs; +}; + +static u8 sg2042_dt_get_pin_mux(u32 value) +{ + return value >> 16; +} + +static inline u32 sg2042_get_pin_reg(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp) +{ + struct sg2042_priv *priv = pctrl->priv_ctrl; + const struct sg2042_pin *pin = sophgo_to_sg2042_pin(sp); + void __iomem *reg = priv->regs + pin->offset; + + if (sp->flags & PIN_FLAG_WRITE_HIGH) + return readl(reg) >> 16; + else + return readl(reg) & 0xffff; +} + +static int sg2042_set_pin_reg(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp, + u32 value, u32 mask) +{ + struct sg2042_priv *priv = pctrl->priv_ctrl; + const struct sg2042_pin *pin = sophgo_to_sg2042_pin(sp); + void __iomem *reg = priv->regs + pin->offset; + u32 v = readl(reg); + + if (sp->flags & PIN_FLAG_WRITE_HIGH) { + v &= ~(mask << 16); + v |= value << 16; + } else { + v &= ~mask; + v |= value; + } + + writel(v, reg); + + return 0; +} + +static void sg2042_pctrl_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *seq, unsigned int pin_id) +{ + struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct sophgo_pin *sp = sophgo_get_pin(pctrl, pin_id); + u32 value, mux; + + value = sg2042_get_pin_reg(pctrl, sp); + mux = FIELD_GET(PIN_IO_MUX, value); + seq_printf(seq, "mux:%u reg:0x%04x ", mux, value); +} + +const struct pinctrl_ops sg2042_pctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .pin_dbg_show = sg2042_pctrl_dbg_show, + .dt_node_to_map = sophgo_pctrl_dt_node_to_map, + .dt_free_map = pinctrl_utils_free_map, +}; +EXPORT_SYMBOL_GPL(sg2042_pctrl_ops); + +static void sg2042_set_pinmux_config(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp, u32 config) +{ + u32 mux = sg2042_dt_get_pin_mux(config); + + if (!(sp->flags & PIN_FLAG_NO_PINMUX)) + sg2042_set_pin_reg(pctrl, sp, mux, PIN_IO_MUX); +} + +const struct pinmux_ops sg2042_pmx_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = sophgo_pmx_set_mux, + .strict = true, +}; +EXPORT_SYMBOL_GPL(sg2042_pmx_ops); + +static int sg2042_pconf_get(struct pinctrl_dev *pctldev, + unsigned int pin_id, unsigned long *config) +{ + struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + int param = pinconf_to_config_param(*config); + const struct sophgo_pin *sp = sophgo_get_pin(pctrl, pin_id); + u32 value; + u32 arg; + bool enabled; + int ret; + + if (!sp) + return -EINVAL; + + value = sg2042_get_pin_reg(pctrl, sp); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) + arg = FIELD_GET(PIN_IO_PULL_ONE_ENABLE, value); + else + arg = FIELD_GET(PIN_IO_PULL_UP_MASK, value); + enabled = arg == 0; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) { + arg = FIELD_GET(PIN_IO_PULL_ONE_MASK, value); + enabled = arg == PIN_IO_PULL_DIR_DOWN; + } else { + enabled = FIELD_GET(PIN_IO_PULL_UP_DONW, value) != 0; + } + arg = sophgo_pinctrl_typical_pull_down(pctrl, sp, NULL); + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) { + arg = FIELD_GET(PIN_IO_PULL_ONE_MASK, value); + enabled = arg == PIN_IO_PULL_DIR_UP; + } else { + enabled = FIELD_GET(PIN_IO_PULL_UP, value) != 0; + } + arg = sophgo_pinctrl_typical_pull_up(pctrl, sp, NULL); + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + enabled = FIELD_GET(PIN_IO_OUTPUT_ENABLE, value) != 0; + arg = FIELD_GET(PIN_IO_DRIVE, value); + ret = sophgo_pinctrl_reg2oc(pctrl, sp, NULL, arg); + if (ret < 0) + return ret; + arg = ret; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + arg = FIELD_GET(PIN_IO_SCHMITT_ENABLE, value); + enabled = arg != 0; + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + + return enabled ? 0 : -EINVAL; +} + +static int sg2042_pinconf_compute_config(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp, + unsigned long *configs, + unsigned int num_configs, + u32 *value, u32 *mask) +{ + int i; + u16 v = 0, m = 0; + int ret; + + if (!sp) + return -EINVAL; + + for (i = 0; i < num_configs; i++) { + int param = pinconf_to_config_param(configs[i]); + u32 arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) { + v &= ~PIN_IO_PULL_ONE_ENABLE; + m |= PIN_IO_PULL_ONE_ENABLE; + } else { + v &= ~PIN_IO_PULL_UP_MASK; + m |= PIN_IO_PULL_UP_MASK; + } + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) { + v &= ~PIN_IO_PULL_ONE_MASK; + v |= PIN_IO_PULL_DIR_DOWN; + m |= PIN_IO_PULL_ONE_MASK; + } else { + v |= PIN_IO_PULL_UP_DONW; + m |= PIN_IO_PULL_UP_DONW; + } + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) { + v &= ~PIN_IO_PULL_ONE_MASK; + v |= PIN_IO_PULL_DIR_UP; + m |= PIN_IO_PULL_ONE_MASK; + } else { + v |= PIN_IO_PULL_UP; + m |= PIN_IO_PULL_UP; + } + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + v &= ~(PIN_IO_DRIVE | PIN_IO_OUTPUT_ENABLE); + if (arg != 0) { + ret = sophgo_pinctrl_oc2reg(pctrl, sp, NULL, arg); + if (ret < 0) + return ret; + if (!(sp->flags & PIN_FLAG_NO_OEX_EN)) + v |= PIN_IO_OUTPUT_ENABLE; + v |= FIELD_PREP(PIN_IO_DRIVE, ret); + } + m |= PIN_IO_DRIVE | PIN_IO_OUTPUT_ENABLE; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + v |= PIN_IO_SCHMITT_ENABLE; + m |= PIN_IO_SCHMITT_ENABLE; + break; + default: + return -ENOTSUPP; + } + } + + *value = v; + *mask = m; + + return 0; +} + +const struct pinconf_ops sg2042_pconf_ops = { + .pin_config_get = sg2042_pconf_get, + .pin_config_set = sophgo_pconf_set, + .pin_config_group_set = sophgo_pconf_group_set, + .is_generic = true, +}; +EXPORT_SYMBOL_GPL(sg2042_pconf_ops); + +static int sophgo_pinctrl_init(struct platform_device *pdev, + struct sophgo_pinctrl *pctrl) +{ + struct sg2042_priv *priv; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); + + pctrl->priv_ctrl = priv; + + return 0; +} + +const struct sophgo_cfg_ops sg2042_cfg_ops = { + .pctrl_init = sophgo_pinctrl_init, + .compute_pinconf_config = sg2042_pinconf_compute_config, + .set_pinconf_config = sg2042_set_pin_reg, + .set_pinmux_config = sg2042_set_pinmux_config, +}; +EXPORT_SYMBOL_GPL(sg2042_cfg_ops); diff --git a/drivers/pinctrl/sophgo/pinctrl-sg2042.c b/drivers/pinctrl/sophgo/pinctrl-sg2042.c new file mode 100644 index 000000000000..185305ac897d --- /dev/null +++ b/drivers/pinctrl/sophgo/pinctrl-sg2042.c @@ -0,0 +1,655 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sophgo SG2042 SoC pinctrl driver. + * + * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com> + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> + +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include <dt-bindings/pinctrl/pinctrl-sg2042.h> + +#include "pinctrl-sg2042.h" + +static int sg2042_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap) +{ + return 35000; +} + +static int sg2042_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap) +{ + return 28000; +} + +static const u32 sg2042_oc_map[] = { + 5400, 8100, 10700, 13400, + 16100, 18800, 21400, 24100, + 26800, 29400, 32100, 34800, + 37400, 40100, 42800, 45400 +}; + +static int sg2042_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap, + const u32 **map) +{ + *map = sg2042_oc_map; + return ARRAY_SIZE(sg2042_oc_map); +} + +static const struct sophgo_vddio_cfg_ops sg2042_vddio_cfg_ops = { + .get_pull_up = sg2042_get_pull_up, + .get_pull_down = sg2042_get_pull_down, + .get_oc_map = sg2042_get_oc_map, +}; + +static const struct pinctrl_pin_desc sg2042_pins[] = { + PINCTRL_PIN(PIN_LPC_LCLK, "lpc_lclk"), + PINCTRL_PIN(PIN_LPC_LFRAME, "lpc_lframe"), + PINCTRL_PIN(PIN_LPC_LAD0, "lpc_lad0"), + PINCTRL_PIN(PIN_LPC_LAD1, "lpc_lad1"), + PINCTRL_PIN(PIN_LPC_LAD2, "lpc_lad2"), + PINCTRL_PIN(PIN_LPC_LAD3, "lpc_lad3"), + PINCTRL_PIN(PIN_LPC_LDRQ0, "lpc_ldrq0"), + PINCTRL_PIN(PIN_LPC_LDRQ1, "lpc_ldrq1"), + PINCTRL_PIN(PIN_LPC_SERIRQ, "lpc_serirq"), + PINCTRL_PIN(PIN_LPC_CLKRUN, "lpc_clkrun"), + PINCTRL_PIN(PIN_LPC_LPME, "lpc_lpme"), + PINCTRL_PIN(PIN_LPC_LPCPD, "lpc_lpcpd"), + PINCTRL_PIN(PIN_LPC_LSMI, "lpc_lsmi"), + PINCTRL_PIN(PIN_PCIE0_L0_RESET, "pcie0_l0_reset"), + PINCTRL_PIN(PIN_PCIE0_L1_RESET, "pcie0_l1_reset"), + PINCTRL_PIN(PIN_PCIE0_L0_WAKEUP, "pcie0_l0_wakeup"), + PINCTRL_PIN(PIN_PCIE0_L1_WAKEUP, "pcie0_l1_wakeup"), + PINCTRL_PIN(PIN_PCIE0_L0_CLKREQ_IN, "pcie0_l0_clkreq_in"), + PINCTRL_PIN(PIN_PCIE0_L1_CLKREQ_IN, "pcie0_l1_clkreq_in"), + PINCTRL_PIN(PIN_PCIE1_L0_RESET, "pcie1_l0_reset"), + PINCTRL_PIN(PIN_PCIE1_L1_RESET, "pcie1_l1_reset"), + PINCTRL_PIN(PIN_PCIE1_L0_WAKEUP, "pcie1_l0_wakeup"), + PINCTRL_PIN(PIN_PCIE1_L1_WAKEUP, "pcie1_l1_wakeup"), + PINCTRL_PIN(PIN_PCIE1_L0_CLKREQ_IN, "pcie1_l0_clkreq_in"), + PINCTRL_PIN(PIN_PCIE1_L1_CLKREQ_IN, "pcie1_l1_clkreq_in"), + PINCTRL_PIN(PIN_SPIF0_CLK_SEL1, "spif0_clk_sel1"), + PINCTRL_PIN(PIN_SPIF0_CLK_SEL0, "spif0_clk_sel0"), + PINCTRL_PIN(PIN_SPIF0_WP, "spif0_wp"), + PINCTRL_PIN(PIN_SPIF0_HOLD, "spif0_hold"), + PINCTRL_PIN(PIN_SPIF0_SDI, "spif0_sdi"), + PINCTRL_PIN(PIN_SPIF0_CS, "spif0_cs"), + PINCTRL_PIN(PIN_SPIF0_SCK, "spif0_sck"), + PINCTRL_PIN(PIN_SPIF0_SDO, "spif0_sdo"), + PINCTRL_PIN(PIN_SPIF1_CLK_SEL1, "spif1_clk_sel1"), + PINCTRL_PIN(PIN_SPIF1_CLK_SEL0, "spif1_clk_sel0"), + PINCTRL_PIN(PIN_SPIF1_WP, "spif1_wp"), + PINCTRL_PIN(PIN_SPIF1_HOLD, "spif1_hold"), + PINCTRL_PIN(PIN_SPIF1_SDI, "spif1_sdi"), + PINCTRL_PIN(PIN_SPIF1_CS, "spif1_cs"), + PINCTRL_PIN(PIN_SPIF1_SCK, "spif1_sck"), + PINCTRL_PIN(PIN_SPIF1_SDO, "spif1_sdo"), + PINCTRL_PIN(PIN_EMMC_WP, "emmc_wp"), + PINCTRL_PIN(PIN_EMMC_CD, "emmc_cd"), + PINCTRL_PIN(PIN_EMMC_RST, "emmc_rst"), + PINCTRL_PIN(PIN_EMMC_PWR_EN, "emmc_pwr_en"), + PINCTRL_PIN(PIN_SDIO_CD, "sdio_cd"), + PINCTRL_PIN(PIN_SDIO_WP, "sdio_wp"), + PINCTRL_PIN(PIN_SDIO_RST, "sdio_rst"), + PINCTRL_PIN(PIN_SDIO_PWR_EN, "sdio_pwr_en"), + PINCTRL_PIN(PIN_RGMII0_TXD0, "rgmii0_txd0"), + PINCTRL_PIN(PIN_RGMII0_TXD1, "rgmii0_txd1"), + PINCTRL_PIN(PIN_RGMII0_TXD2, "rgmii0_txd2"), + PINCTRL_PIN(PIN_RGMII0_TXD3, "rgmii0_txd3"), + PINCTRL_PIN(PIN_RGMII0_TXCTRL, "rgmii0_txctrl"), + PINCTRL_PIN(PIN_RGMII0_RXD0, "rgmii0_rxd0"), + PINCTRL_PIN(PIN_RGMII0_RXD1, "rgmii0_rxd1"), + PINCTRL_PIN(PIN_RGMII0_RXD2, "rgmii0_rxd2"), + PINCTRL_PIN(PIN_RGMII0_RXD3, "rgmii0_rxd3"), + PINCTRL_PIN(PIN_RGMII0_RXCTRL, "rgmii0_rxctrl"), + PINCTRL_PIN(PIN_RGMII0_TXC, "rgmii0_txc"), + PINCTRL_PIN(PIN_RGMII0_RXC, "rgmii0_rxc"), + PINCTRL_PIN(PIN_RGMII0_REFCLKO, "rgmii0_refclko"), + PINCTRL_PIN(PIN_RGMII0_IRQ, "rgmii0_irq"), + PINCTRL_PIN(PIN_RGMII0_MDC, "rgmii0_mdc"), + PINCTRL_PIN(PIN_RGMII0_MDIO, "rgmii0_mdio"), + PINCTRL_PIN(PIN_PWM0, "pwm0"), + PINCTRL_PIN(PIN_PWM1, "pwm1"), + PINCTRL_PIN(PIN_PWM2, "pwm2"), + PINCTRL_PIN(PIN_PWM3, "pwm3"), + PINCTRL_PIN(PIN_FAN0, "fan0"), + PINCTRL_PIN(PIN_FAN1, "fan1"), + PINCTRL_PIN(PIN_FAN2, "fan2"), + PINCTRL_PIN(PIN_FAN3, "fan3"), + PINCTRL_PIN(PIN_IIC0_SDA, "iic0_sda"), + PINCTRL_PIN(PIN_IIC0_SCL, "iic0_scl"), + PINCTRL_PIN(PIN_IIC1_SDA, "iic1_sda"), + PINCTRL_PIN(PIN_IIC1_SCL, "iic1_scl"), + PINCTRL_PIN(PIN_IIC2_SDA, "iic2_sda"), + PINCTRL_PIN(PIN_IIC2_SCL, "iic2_scl"), + PINCTRL_PIN(PIN_IIC3_SDA, "iic3_sda"), + PINCTRL_PIN(PIN_IIC3_SCL, "iic3_scl"), + PINCTRL_PIN(PIN_UART0_TX, "uart0_tx"), + PINCTRL_PIN(PIN_UART0_RX, "uart0_rx"), + PINCTRL_PIN(PIN_UART0_RTS, "uart0_rts"), + PINCTRL_PIN(PIN_UART0_CTS, "uart0_cts"), + PINCTRL_PIN(PIN_UART1_TX, "uart1_tx"), + PINCTRL_PIN(PIN_UART1_RX, "uart1_rx"), + PINCTRL_PIN(PIN_UART1_RTS, "uart1_rts"), + PINCTRL_PIN(PIN_UART1_CTS, "uart1_cts"), + PINCTRL_PIN(PIN_UART2_TX, "uart2_tx"), + PINCTRL_PIN(PIN_UART2_RX, "uart2_rx"), + PINCTRL_PIN(PIN_UART2_RTS, "uart2_rts"), + PINCTRL_PIN(PIN_UART2_CTS, "uart2_cts"), + PINCTRL_PIN(PIN_UART3_TX, "uart3_tx"), + PINCTRL_PIN(PIN_UART3_RX, "uart3_rx"), + PINCTRL_PIN(PIN_UART3_RTS, "uart3_rts"), + PINCTRL_PIN(PIN_UART3_CTS, "uart3_cts"), + PINCTRL_PIN(PIN_SPI0_CS0, "spi0_cs0"), + PINCTRL_PIN(PIN_SPI0_CS1, "spi0_cs1"), + PINCTRL_PIN(PIN_SPI0_SDI, "spi0_sdi"), + PINCTRL_PIN(PIN_SPI0_SDO, "spi0_sdo"), + PINCTRL_PIN(PIN_SPI0_SCK, "spi0_sck"), + PINCTRL_PIN(PIN_SPI1_CS0, "spi1_cs0"), + PINCTRL_PIN(PIN_SPI1_CS1, "spi1_cs1"), + PINCTRL_PIN(PIN_SPI1_SDI, "spi1_sdi"), + PINCTRL_PIN(PIN_SPI1_SDO, "spi1_sdo"), + PINCTRL_PIN(PIN_SPI1_SCK, "spi1_sck"), + PINCTRL_PIN(PIN_JTAG0_TDO, "jtag0_tdo"), + PINCTRL_PIN(PIN_JTAG0_TCK, "jtag0_tck"), + PINCTRL_PIN(PIN_JTAG0_TDI, "jtag0_tdi"), + PINCTRL_PIN(PIN_JTAG0_TMS, "jtag0_tms"), + PINCTRL_PIN(PIN_JTAG0_TRST, "jtag0_trst"), + PINCTRL_PIN(PIN_JTAG0_SRST, "jtag0_srst"), + PINCTRL_PIN(PIN_JTAG1_TDO, "jtag1_tdo"), + PINCTRL_PIN(PIN_JTAG1_TCK, "jtag1_tck"), + PINCTRL_PIN(PIN_JTAG1_TDI, "jtag1_tdi"), + PINCTRL_PIN(PIN_JTAG1_TMS, "jtag1_tms"), + PINCTRL_PIN(PIN_JTAG1_TRST, "jtag1_trst"), + PINCTRL_PIN(PIN_JTAG1_SRST, "jtag1_srst"), + PINCTRL_PIN(PIN_JTAG2_TDO, "jtag2_tdo"), + PINCTRL_PIN(PIN_JTAG2_TCK, "jtag2_tck"), + PINCTRL_PIN(PIN_JTAG2_TDI, "jtag2_tdi"), + PINCTRL_PIN(PIN_JTAG2_TMS, "jtag2_tms"), + PINCTRL_PIN(PIN_JTAG2_TRST, "jtag2_trst"), + PINCTRL_PIN(PIN_JTAG2_SRST, "jtag2_srst"), + PINCTRL_PIN(PIN_GPIO0, "gpio0"), + PINCTRL_PIN(PIN_GPIO1, "gpio1"), + PINCTRL_PIN(PIN_GPIO2, "gpio2"), + PINCTRL_PIN(PIN_GPIO3, "gpio3"), + PINCTRL_PIN(PIN_GPIO4, "gpio4"), + PINCTRL_PIN(PIN_GPIO5, "gpio5"), + PINCTRL_PIN(PIN_GPIO6, "gpio6"), + PINCTRL_PIN(PIN_GPIO7, "gpio7"), + PINCTRL_PIN(PIN_GPIO8, "gpio8"), + PINCTRL_PIN(PIN_GPIO9, "gpio9"), + PINCTRL_PIN(PIN_GPIO10, "gpio10"), + PINCTRL_PIN(PIN_GPIO11, "gpio11"), + PINCTRL_PIN(PIN_GPIO12, "gpio12"), + PINCTRL_PIN(PIN_GPIO13, "gpio13"), + PINCTRL_PIN(PIN_GPIO14, "gpio14"), + PINCTRL_PIN(PIN_GPIO15, "gpio15"), + PINCTRL_PIN(PIN_GPIO16, "gpio16"), + PINCTRL_PIN(PIN_GPIO17, "gpio17"), + PINCTRL_PIN(PIN_GPIO18, "gpio18"), + PINCTRL_PIN(PIN_GPIO19, "gpio19"), + PINCTRL_PIN(PIN_GPIO20, "gpio20"), + PINCTRL_PIN(PIN_GPIO21, "gpio21"), + PINCTRL_PIN(PIN_GPIO22, "gpio22"), + PINCTRL_PIN(PIN_GPIO23, "gpio23"), + PINCTRL_PIN(PIN_GPIO24, "gpio24"), + PINCTRL_PIN(PIN_GPIO25, "gpio25"), + PINCTRL_PIN(PIN_GPIO26, "gpio26"), + PINCTRL_PIN(PIN_GPIO27, "gpio27"), + PINCTRL_PIN(PIN_GPIO28, "gpio28"), + PINCTRL_PIN(PIN_GPIO29, "gpio29"), + PINCTRL_PIN(PIN_GPIO30, "gpio30"), + PINCTRL_PIN(PIN_GPIO31, "gpio31"), + PINCTRL_PIN(PIN_MODE_SEL0, "mode_sel0"), + PINCTRL_PIN(PIN_MODE_SEL1, "mode_sel1"), + PINCTRL_PIN(PIN_MODE_SEL2, "mode_sel2"), + PINCTRL_PIN(PIN_BOOT_SEL0, "boot_sel0"), + PINCTRL_PIN(PIN_BOOT_SEL1, "boot_sel1"), + PINCTRL_PIN(PIN_BOOT_SEL2, "boot_sel2"), + PINCTRL_PIN(PIN_BOOT_SEL3, "boot_sel3"), + PINCTRL_PIN(PIN_BOOT_SEL4, "boot_sel4"), + PINCTRL_PIN(PIN_BOOT_SEL5, "boot_sel5"), + PINCTRL_PIN(PIN_BOOT_SEL6, "boot_sel6"), + PINCTRL_PIN(PIN_BOOT_SEL7, "boot_sel7"), + PINCTRL_PIN(PIN_MULTI_SCKT, "multi_sckt"), + PINCTRL_PIN(PIN_SCKT_ID0, "sckt_id0"), + PINCTRL_PIN(PIN_SCKT_ID1, "sckt_id1"), + PINCTRL_PIN(PIN_PLL_CLK_IN_MAIN, "pll_clk_in_main"), + PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_L, "pll_clk_in_ddr_l"), + PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_R, "pll_clk_in_ddr_r"), + PINCTRL_PIN(PIN_XTAL_32K, "xtal_32k"), + PINCTRL_PIN(PIN_SYS_RST, "sys_rst"), + PINCTRL_PIN(PIN_PWR_BUTTON, "pwr_button"), + PINCTRL_PIN(PIN_TEST_EN, "test_en"), + PINCTRL_PIN(PIN_TEST_MODE_MBIST, "test_mode_mbist"), + PINCTRL_PIN(PIN_TEST_MODE_SCAN, "test_mode_scan"), + PINCTRL_PIN(PIN_TEST_MODE_BSD, "test_mode_bsd"), + PINCTRL_PIN(PIN_BISR_BYP, "bisr_byp"), +}; + +static const struct sg2042_pin sg2042_pin_data[ARRAY_SIZE(sg2042_pins)] = { + SG2042_GENERAL_PIN(PIN_LPC_LCLK, 0x000, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LFRAME, 0x000, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LAD0, 0x004, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LAD1, 0x004, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LAD2, 0x008, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LAD3, 0x008, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LDRQ0, 0x00c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LDRQ1, 0x00c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_SERIRQ, 0x010, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_CLKRUN, 0x010, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LPME, 0x014, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LPCPD, 0x014, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_LPC_LSMI, 0x018, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE0_L0_RESET, 0x018, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE0_L1_RESET, 0x01c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE0_L0_WAKEUP, 0x01c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE0_L1_WAKEUP, 0x020, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE0_L0_CLKREQ_IN, 0x020, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE0_L1_CLKREQ_IN, 0x024, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE1_L0_RESET, 0x024, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE1_L1_RESET, 0x028, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE1_L0_WAKEUP, 0x028, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE1_L1_WAKEUP, 0x02c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE1_L0_CLKREQ_IN, 0x02c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PCIE1_L1_CLKREQ_IN, 0x030, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF0_CLK_SEL1, 0x030, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF0_CLK_SEL0, 0x034, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF0_WP, 0x034, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF0_HOLD, 0x038, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF0_SDI, 0x038, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF0_CS, 0x03c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF0_SCK, 0x03c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF0_SDO, 0x040, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF1_CLK_SEL1, 0x040, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF1_CLK_SEL0, 0x044, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF1_WP, 0x044, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF1_HOLD, 0x048, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF1_SDI, 0x048, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF1_CS, 0x04c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF1_SCK, 0x04c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPIF1_SDO, 0x050, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_EMMC_WP, 0x050, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_EMMC_CD, 0x054, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_EMMC_RST, 0x054, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_EMMC_PWR_EN, 0x058, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SDIO_CD, 0x058, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SDIO_WP, 0x05c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SDIO_RST, 0x05c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SDIO_PWR_EN, 0x060, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_RGMII0_TXD0, 0x060, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_TXD1, 0x064, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_TXD2, 0x064, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_TXD3, 0x068, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_TXCTRL, 0x068, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_RXD0, 0x06c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_RXD1, 0x06c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_RXD2, 0x070, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_RXD3, 0x070, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_RXCTRL, 0x074, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_TXC, 0x074, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_RXC, 0x078, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_REFCLKO, 0x078, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_IRQ, 0x07c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_MDC, 0x07c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_MDIO, 0x080, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PWM0, 0x080, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PWM1, 0x084, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PWM2, 0x084, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_PWM3, 0x088, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_FAN0, 0x088, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_FAN1, 0x08c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_FAN2, 0x08c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_FAN3, 0x090, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_IIC0_SDA, 0x090, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC0_SCL, 0x094, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC1_SDA, 0x094, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC1_SCL, 0x098, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC2_SDA, 0x098, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC2_SCL, 0x09c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC3_SDA, 0x09c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC3_SCL, 0x0a0, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_UART0_TX, 0x0a0, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART0_RX, 0x0a4, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART0_RTS, 0x0a4, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART0_CTS, 0x0a8, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART1_TX, 0x0a8, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART1_RX, 0x0ac, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART1_RTS, 0x0ac, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART1_CTS, 0x0b0, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART2_TX, 0x0b0, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART2_RX, 0x0b4, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART2_RTS, 0x0b4, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART2_CTS, 0x0b8, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART3_TX, 0x0b8, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART3_RX, 0x0bc, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART3_RTS, 0x0bc, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_UART3_CTS, 0x0c0, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI0_CS0, 0x0c0, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI0_CS1, 0x0c4, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI0_SDI, 0x0c4, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI0_SDO, 0x0c8, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI0_SCK, 0x0c8, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI1_CS0, 0x0cc, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI1_CS1, 0x0cc, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI1_SDI, 0x0d0, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI1_SDO, 0x0d0, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_SPI1_SCK, 0x0d4, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG0_TDO, 0x0d4, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG0_TCK, 0x0d8, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG0_TDI, 0x0d8, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG0_TMS, 0x0dc, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG0_TRST, 0x0dc, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG0_SRST, 0x0e0, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG1_TDO, 0x0e0, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG1_TCK, 0x0e4, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG1_TDI, 0x0e4, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG1_TMS, 0x0e8, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG1_TRST, 0x0e8, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG1_SRST, 0x0ec, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG2_TDO, 0x0ec, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG2_TCK, 0x0f0, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG2_TDI, 0x0f0, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG2_TMS, 0x0f4, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG2_TRST, 0x0f4, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_JTAG2_SRST, 0x0f8, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO0, 0x0f8, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO1, 0x0fc, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO2, 0x0fc, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO3, 0x100, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO4, 0x100, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO5, 0x104, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO6, 0x104, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO7, 0x108, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO8, 0x108, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO9, 0x10c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO10, 0x10c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO11, 0x110, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO12, 0x110, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO13, 0x114, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO14, 0x114, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO15, 0x118, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO16, 0x118, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO17, 0x11c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO18, 0x11c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO19, 0x120, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO20, 0x120, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO21, 0x124, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO22, 0x124, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO23, 0x128, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO24, 0x128, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO25, 0x12c, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO26, 0x12c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO27, 0x130, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO28, 0x130, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO29, 0x134, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO30, 0x134, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_GPIO31, 0x138, + PIN_FLAG_ONLY_ONE_PULL), + SG2042_GENERAL_PIN(PIN_MODE_SEL0, 0x138, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_MODE_SEL1, 0x13c, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_MODE_SEL2, 0x13c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL0, 0x140, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL1, 0x140, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL2, 0x144, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL3, 0x144, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL4, 0x148, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL5, 0x148, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL6, 0x14c, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL7, 0x14c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_MULTI_SCKT, 0x150, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_SCKT_ID0, 0x150, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_SCKT_ID1, 0x154, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_MAIN, 0x154, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_L, 0x158, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_R, 0x158, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_XTAL_32K, 0x15c, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_SYS_RST, 0x15c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PWR_BUTTON, 0x160, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_TEST_EN, 0x160, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_TEST_MODE_MBIST, 0x164, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_TEST_MODE_SCAN, 0x164, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_TEST_MODE_BSD, 0x168, + PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BISR_BYP, 0x168, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL | + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), +}; + +static const struct sophgo_pinctrl_data sg2042_pindata = { + .pins = sg2042_pins, + .pindata = sg2042_pin_data, + .vddio_ops = &sg2042_vddio_cfg_ops, + .cfg_ops = &sg2042_cfg_ops, + .pctl_ops = &sg2042_pctrl_ops, + .pmx_ops = &sg2042_pmx_ops, + .pconf_ops = &sg2042_pconf_ops, + .npins = ARRAY_SIZE(sg2042_pins), + .pinsize = sizeof(struct sg2042_pin), +}; + +static const struct of_device_id sg2042_pinctrl_ids[] = { + { .compatible = "sophgo,sg2042-pinctrl", .data = &sg2042_pindata }, + { } +}; +MODULE_DEVICE_TABLE(of, sg2042_pinctrl_ids); + +static struct platform_driver sg2042_pinctrl_driver = { + .probe = sophgo_pinctrl_probe, + .driver = { + .name = "sg2042-pinctrl", + .suppress_bind_attrs = true, + .of_match_table = sg2042_pinctrl_ids, + }, +}; +module_platform_driver(sg2042_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for the SG2002 series SoC"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/sophgo/pinctrl-sg2042.h b/drivers/pinctrl/sophgo/pinctrl-sg2042.h new file mode 100644 index 000000000000..d481973fcf97 --- /dev/null +++ b/drivers/pinctrl/sophgo/pinctrl-sg2042.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com> + */ + +#ifndef _PINCTRL_SOPHGO_SG2042_H +#define _PINCTRL_SOPHGO_SG2042_H + +#include <linux/bits.h> +#include <linux/bitfield.h> +#include <linux/device.h> +#include <linux/mutex.h> +#include <linux/spinlock.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinconf.h> + +#include "pinctrl-sophgo.h" + +#define PIN_FLAG_DEFAULT 0 +#define PIN_FLAG_WRITE_HIGH BIT(0) +#define PIN_FLAG_ONLY_ONE_PULL BIT(1) +#define PIN_FLAG_NO_PINMUX BIT(2) +#define PIN_FLAG_NO_OEX_EN BIT(3) +#define PIN_FLAG_IS_ETH BIT(4) + +struct sg2042_pin { + struct sophgo_pin pin; + u16 offset; +}; + +#define sophgo_to_sg2042_pin(_pin) \ + container_of((_pin), struct sg2042_pin, pin) + +extern const struct pinctrl_ops sg2042_pctrl_ops; +extern const struct pinmux_ops sg2042_pmx_ops; +extern const struct pinconf_ops sg2042_pconf_ops; +extern const struct sophgo_cfg_ops sg2042_cfg_ops; + +#define SG2042_GENERAL_PIN(_id, _offset, _flag) \ + { \ + .pin = { \ + .id = (_id), \ + .flags = (_flag), \ + }, \ + .offset = (_offset), \ + } + +#endif diff --git a/drivers/pinctrl/sophgo/pinctrl-sg2044.c b/drivers/pinctrl/sophgo/pinctrl-sg2044.c new file mode 100644 index 000000000000..b0c46d8954ca --- /dev/null +++ b/drivers/pinctrl/sophgo/pinctrl-sg2044.c @@ -0,0 +1,718 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sophgo SG2042 SoC pinctrl driver. + * + * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com> + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> + +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include <dt-bindings/pinctrl/pinctrl-sg2044.h> + +#include "pinctrl-sg2042.h" + +static int sg2044_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap) +{ + return 19500; +} + +static int sg2044_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap) +{ + return 23200; +} + +static const u32 sg2044_oc_map[] = { + 3200, 6400, 9600, 12700, + 15900, 19100, 22200, 25300, + 29500, 32700, 35900, 39000, + 42000, 45200, 48300, 51400 +}; + +static int sg2044_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap, + const u32 **map) +{ + *map = sg2044_oc_map; + return ARRAY_SIZE(sg2044_oc_map); +} + +static const struct sophgo_vddio_cfg_ops sg2044_vddio_cfg_ops = { + .get_pull_up = sg2044_get_pull_up, + .get_pull_down = sg2044_get_pull_down, + .get_oc_map = sg2044_get_oc_map, +}; + +static const struct pinctrl_pin_desc sg2044_pins[] = { + PINCTRL_PIN(PIN_IIC0_SMBSUS_IN, "iic0_smbsus_in"), + PINCTRL_PIN(PIN_IIC0_SMBSUS_OUT, "iic0_smbsus_out"), + PINCTRL_PIN(PIN_IIC0_SMBALERT, "iic0_smbalert"), + PINCTRL_PIN(PIN_IIC1_SMBSUS_IN, "iic1_smbsus_in"), + PINCTRL_PIN(PIN_IIC1_SMBSUS_OUT, "iic1_smbsus_out"), + PINCTRL_PIN(PIN_IIC1_SMBALERT, "iic1_smbalert"), + PINCTRL_PIN(PIN_IIC2_SMBSUS_IN, "iic2_smbsus_in"), + PINCTRL_PIN(PIN_IIC2_SMBSUS_OUT, "iic2_smbsus_out"), + PINCTRL_PIN(PIN_IIC2_SMBALERT, "iic2_smbalert"), + PINCTRL_PIN(PIN_IIC3_SMBSUS_IN, "iic3_smbsus_in"), + PINCTRL_PIN(PIN_IIC3_SMBSUS_OUT, "iic3_smbsus_out"), + PINCTRL_PIN(PIN_IIC3_SMBALERT, "iic3_smbalert"), + PINCTRL_PIN(PIN_PCIE0_L0_RESET, "pcie0_l0_reset"), + PINCTRL_PIN(PIN_PCIE0_L1_RESET, "pcie0_l1_reset"), + PINCTRL_PIN(PIN_PCIE0_L0_WAKEUP, "pcie0_l0_wakeup"), + PINCTRL_PIN(PIN_PCIE0_L1_WAKEUP, "pcie0_l1_wakeup"), + PINCTRL_PIN(PIN_PCIE0_L0_CLKREQ_IN, "pcie0_l0_clkreq_in"), + PINCTRL_PIN(PIN_PCIE0_L1_CLKREQ_IN, "pcie0_l1_clkreq_in"), + PINCTRL_PIN(PIN_PCIE1_L0_RESET, "pcie1_l0_reset"), + PINCTRL_PIN(PIN_PCIE1_L1_RESET, "pcie1_l1_reset"), + PINCTRL_PIN(PIN_PCIE1_L0_WAKEUP, "pcie1_l0_wakeup"), + PINCTRL_PIN(PIN_PCIE1_L1_WAKEUP, "pcie1_l1_wakeup"), + PINCTRL_PIN(PIN_PCIE1_L0_CLKREQ_IN, "pcie1_l0_clkreq_in"), + PINCTRL_PIN(PIN_PCIE1_L1_CLKREQ_IN, "pcie1_l1_clkreq_in"), + PINCTRL_PIN(PIN_PCIE2_L0_RESET, "pcie2_l0_reset"), + PINCTRL_PIN(PIN_PCIE2_L1_RESET, "pcie2_l1_reset"), + PINCTRL_PIN(PIN_PCIE2_L0_WAKEUP, "pcie2_l0_wakeup"), + PINCTRL_PIN(PIN_PCIE2_L1_WAKEUP, "pcie2_l1_wakeup"), + PINCTRL_PIN(PIN_PCIE2_L0_CLKREQ_IN, "pcie2_l0_clkreq_in"), + PINCTRL_PIN(PIN_PCIE2_L1_CLKREQ_IN, "pcie2_l1_clkreq_in"), + PINCTRL_PIN(PIN_PCIE3_L0_RESET, "pcie3_l0_reset"), + PINCTRL_PIN(PIN_PCIE3_L1_RESET, "pcie3_l1_reset"), + PINCTRL_PIN(PIN_PCIE3_L0_WAKEUP, "pcie3_l0_wakeup"), + PINCTRL_PIN(PIN_PCIE3_L1_WAKEUP, "pcie3_l1_wakeup"), + PINCTRL_PIN(PIN_PCIE3_L0_CLKREQ_IN, "pcie3_l0_clkreq_in"), + PINCTRL_PIN(PIN_PCIE3_L1_CLKREQ_IN, "pcie3_l1_clkreq_in"), + PINCTRL_PIN(PIN_PCIE4_L0_RESET, "pcie4_l0_reset"), + PINCTRL_PIN(PIN_PCIE4_L1_RESET, "pcie4_l1_reset"), + PINCTRL_PIN(PIN_PCIE4_L0_WAKEUP, "pcie4_l0_wakeup"), + PINCTRL_PIN(PIN_PCIE4_L1_WAKEUP, "pcie4_l1_wakeup"), + PINCTRL_PIN(PIN_PCIE4_L0_CLKREQ_IN, "pcie4_l0_clkreq_in"), + PINCTRL_PIN(PIN_PCIE4_L1_CLKREQ_IN, "pcie4_l1_clkreq_in"), + PINCTRL_PIN(PIN_SPIF0_CLK_SEL1, "spif0_clk_sel1"), + PINCTRL_PIN(PIN_SPIF0_CLK_SEL0, "spif0_clk_sel0"), + PINCTRL_PIN(PIN_SPIF0_WP, "spif0_wp"), + PINCTRL_PIN(PIN_SPIF0_HOLD, "spif0_hold"), + PINCTRL_PIN(PIN_SPIF0_SDI, "spif0_sdi"), + PINCTRL_PIN(PIN_SPIF0_CS, "spif0_cs"), + PINCTRL_PIN(PIN_SPIF0_SCK, "spif0_sck"), + PINCTRL_PIN(PIN_SPIF0_SDO, "spif0_sdo"), + PINCTRL_PIN(PIN_SPIF1_CLK_SEL1, "spif1_clk_sel1"), + PINCTRL_PIN(PIN_SPIF1_CLK_SEL0, "spif1_clk_sel0"), + PINCTRL_PIN(PIN_SPIF1_WP, "spif1_wp"), + PINCTRL_PIN(PIN_SPIF1_HOLD, "spif1_hold"), + PINCTRL_PIN(PIN_SPIF1_SDI, "spif1_sdi"), + PINCTRL_PIN(PIN_SPIF1_CS, "spif1_cs"), + PINCTRL_PIN(PIN_SPIF1_SCK, "spif1_sck"), + PINCTRL_PIN(PIN_SPIF1_SDO, "spif1_sdo"), + PINCTRL_PIN(PIN_EMMC_WP, "emmc_wp"), + PINCTRL_PIN(PIN_EMMC_CD, "emmc_cd"), + PINCTRL_PIN(PIN_EMMC_RST, "emmc_rst"), + PINCTRL_PIN(PIN_EMMC_PWR_EN, "emmc_pwr_en"), + PINCTRL_PIN(PIN_SDIO_CD, "sdio_cd"), + PINCTRL_PIN(PIN_SDIO_WP, "sdio_wp"), + PINCTRL_PIN(PIN_SDIO_RST, "sdio_rst"), + PINCTRL_PIN(PIN_SDIO_PWR_EN, "sdio_pwr_en"), + PINCTRL_PIN(PIN_RGMII0_TXD0, "rgmii0_txd0"), + PINCTRL_PIN(PIN_RGMII0_TXD1, "rgmii0_txd1"), + PINCTRL_PIN(PIN_RGMII0_TXD2, "rgmii0_txd2"), + PINCTRL_PIN(PIN_RGMII0_TXD3, "rgmii0_txd3"), + PINCTRL_PIN(PIN_RGMII0_TXCTRL, "rgmii0_txctrl"), + PINCTRL_PIN(PIN_RGMII0_RXD0, "rgmii0_rxd0"), + PINCTRL_PIN(PIN_RGMII0_RXD1, "rgmii0_rxd1"), + PINCTRL_PIN(PIN_RGMII0_RXD2, "rgmii0_rxd2"), + PINCTRL_PIN(PIN_RGMII0_RXD3, "rgmii0_rxd3"), + PINCTRL_PIN(PIN_RGMII0_RXCTRL, "rgmii0_rxctrl"), + PINCTRL_PIN(PIN_RGMII0_TXC, "rgmii0_txc"), + PINCTRL_PIN(PIN_RGMII0_RXC, "rgmii0_rxc"), + PINCTRL_PIN(PIN_RGMII0_REFCLKO, "rgmii0_refclko"), + PINCTRL_PIN(PIN_RGMII0_IRQ, "rgmii0_irq"), + PINCTRL_PIN(PIN_RGMII0_MDC, "rgmii0_mdc"), + PINCTRL_PIN(PIN_RGMII0_MDIO, "rgmii0_mdio"), + PINCTRL_PIN(PIN_PWM0, "pwm0"), + PINCTRL_PIN(PIN_PWM1, "pwm1"), + PINCTRL_PIN(PIN_PWM2, "pwm2"), + PINCTRL_PIN(PIN_PWM3, "pwm3"), + PINCTRL_PIN(PIN_FAN0, "fan0"), + PINCTRL_PIN(PIN_FAN1, "fan1"), + PINCTRL_PIN(PIN_FAN2, "fan2"), + PINCTRL_PIN(PIN_FAN3, "fan3"), + PINCTRL_PIN(PIN_IIC0_SDA, "iic0_sda"), + PINCTRL_PIN(PIN_IIC0_SCL, "iic0_scl"), + PINCTRL_PIN(PIN_IIC1_SDA, "iic1_sda"), + PINCTRL_PIN(PIN_IIC1_SCL, "iic1_scl"), + PINCTRL_PIN(PIN_IIC2_SDA, "iic2_sda"), + PINCTRL_PIN(PIN_IIC2_SCL, "iic2_scl"), + PINCTRL_PIN(PIN_IIC3_SDA, "iic3_sda"), + PINCTRL_PIN(PIN_IIC3_SCL, "iic3_scl"), + PINCTRL_PIN(PIN_UART0_TX, "uart0_tx"), + PINCTRL_PIN(PIN_UART0_RX, "uart0_rx"), + PINCTRL_PIN(PIN_UART0_RTS, "uart0_rts"), + PINCTRL_PIN(PIN_UART0_CTS, "uart0_cts"), + PINCTRL_PIN(PIN_UART1_TX, "uart1_tx"), + PINCTRL_PIN(PIN_UART1_RX, "uart1_rx"), + PINCTRL_PIN(PIN_UART1_RTS, "uart1_rts"), + PINCTRL_PIN(PIN_UART1_CTS, "uart1_cts"), + PINCTRL_PIN(PIN_UART2_TX, "uart2_tx"), + PINCTRL_PIN(PIN_UART2_RX, "uart2_rx"), + PINCTRL_PIN(PIN_UART2_RTS, "uart2_rts"), + PINCTRL_PIN(PIN_UART2_CTS, "uart2_cts"), + PINCTRL_PIN(PIN_UART3_TX, "uart3_tx"), + PINCTRL_PIN(PIN_UART3_RX, "uart3_rx"), + PINCTRL_PIN(PIN_UART3_RTS, "uart3_rts"), + PINCTRL_PIN(PIN_UART3_CTS, "uart3_cts"), + PINCTRL_PIN(PIN_SPI0_CS0, "spi0_cs0"), + PINCTRL_PIN(PIN_SPI0_CS1, "spi0_cs1"), + PINCTRL_PIN(PIN_SPI0_SDI, "spi0_sdi"), + PINCTRL_PIN(PIN_SPI0_SDO, "spi0_sdo"), + PINCTRL_PIN(PIN_SPI0_SCK, "spi0_sck"), + PINCTRL_PIN(PIN_SPI1_CS0, "spi1_cs0"), + PINCTRL_PIN(PIN_SPI1_CS1, "spi1_cs1"), + PINCTRL_PIN(PIN_SPI1_SDI, "spi1_sdi"), + PINCTRL_PIN(PIN_SPI1_SDO, "spi1_sdo"), + PINCTRL_PIN(PIN_SPI1_SCK, "spi1_sck"), + PINCTRL_PIN(PIN_JTAG0_TDO, "jtag0_tdo"), + PINCTRL_PIN(PIN_JTAG0_TCK, "jtag0_tck"), + PINCTRL_PIN(PIN_JTAG0_TDI, "jtag0_tdi"), + PINCTRL_PIN(PIN_JTAG0_TMS, "jtag0_tms"), + PINCTRL_PIN(PIN_JTAG0_TRST, "jtag0_trst"), + PINCTRL_PIN(PIN_JTAG0_SRST, "jtag0_srst"), + PINCTRL_PIN(PIN_JTAG1_TDO, "jtag1_tdo"), + PINCTRL_PIN(PIN_JTAG1_TCK, "jtag1_tck"), + PINCTRL_PIN(PIN_JTAG1_TDI, "jtag1_tdi"), + PINCTRL_PIN(PIN_JTAG1_TMS, "jtag1_tms"), + PINCTRL_PIN(PIN_JTAG1_TRST, "jtag1_trst"), + PINCTRL_PIN(PIN_JTAG1_SRST, "jtag1_srst"), + PINCTRL_PIN(PIN_JTAG2_TDO, "jtag2_tdo"), + PINCTRL_PIN(PIN_JTAG2_TCK, "jtag2_tck"), + PINCTRL_PIN(PIN_JTAG2_TDI, "jtag2_tdi"), + PINCTRL_PIN(PIN_JTAG2_TMS, "jtag2_tms"), + PINCTRL_PIN(PIN_JTAG2_TRST, "jtag2_trst"), + PINCTRL_PIN(PIN_JTAG2_SRST, "jtag2_srst"), + PINCTRL_PIN(PIN_JTAG3_TDO, "jtag3_tdo"), + PINCTRL_PIN(PIN_JTAG3_TCK, "jtag3_tck"), + PINCTRL_PIN(PIN_JTAG3_TDI, "jtag3_tdi"), + PINCTRL_PIN(PIN_JTAG3_TMS, "jtag3_tms"), + PINCTRL_PIN(PIN_JTAG3_TRST, "jtag3_trst"), + PINCTRL_PIN(PIN_JTAG3_SRST, "jtag3_srst"), + PINCTRL_PIN(PIN_GPIO0, "gpio0"), + PINCTRL_PIN(PIN_GPIO1, "gpio1"), + PINCTRL_PIN(PIN_GPIO2, "gpio2"), + PINCTRL_PIN(PIN_GPIO3, "gpio3"), + PINCTRL_PIN(PIN_GPIO4, "gpio4"), + PINCTRL_PIN(PIN_GPIO5, "gpio5"), + PINCTRL_PIN(PIN_GPIO6, "gpio6"), + PINCTRL_PIN(PIN_GPIO7, "gpio7"), + PINCTRL_PIN(PIN_GPIO8, "gpio8"), + PINCTRL_PIN(PIN_GPIO9, "gpio9"), + PINCTRL_PIN(PIN_GPIO10, "gpio10"), + PINCTRL_PIN(PIN_GPIO11, "gpio11"), + PINCTRL_PIN(PIN_GPIO12, "gpio12"), + PINCTRL_PIN(PIN_GPIO13, "gpio13"), + PINCTRL_PIN(PIN_GPIO14, "gpio14"), + PINCTRL_PIN(PIN_GPIO15, "gpio15"), + PINCTRL_PIN(PIN_GPIO16, "gpio16"), + PINCTRL_PIN(PIN_GPIO17, "gpio17"), + PINCTRL_PIN(PIN_GPIO18, "gpio18"), + PINCTRL_PIN(PIN_GPIO19, "gpio19"), + PINCTRL_PIN(PIN_GPIO20, "gpio20"), + PINCTRL_PIN(PIN_GPIO21, "gpio21"), + PINCTRL_PIN(PIN_GPIO22, "gpio22"), + PINCTRL_PIN(PIN_GPIO23, "gpio23"), + PINCTRL_PIN(PIN_GPIO24, "gpio24"), + PINCTRL_PIN(PIN_GPIO25, "gpio25"), + PINCTRL_PIN(PIN_GPIO26, "gpio26"), + PINCTRL_PIN(PIN_GPIO27, "gpio27"), + PINCTRL_PIN(PIN_GPIO28, "gpio28"), + PINCTRL_PIN(PIN_GPIO29, "gpio29"), + PINCTRL_PIN(PIN_GPIO30, "gpio30"), + PINCTRL_PIN(PIN_GPIO31, "gpio31"), + PINCTRL_PIN(PIN_MODE_SEL0, "mode_sel0"), + PINCTRL_PIN(PIN_MODE_SEL1, "mode_sel1"), + PINCTRL_PIN(PIN_MODE_SEL2, "mode_sel2"), + PINCTRL_PIN(PIN_BOOT_SEL0, "boot_sel0"), + PINCTRL_PIN(PIN_BOOT_SEL1, "boot_sel1"), + PINCTRL_PIN(PIN_BOOT_SEL2, "boot_sel2"), + PINCTRL_PIN(PIN_BOOT_SEL3, "boot_sel3"), + PINCTRL_PIN(PIN_BOOT_SEL4, "boot_sel4"), + PINCTRL_PIN(PIN_BOOT_SEL5, "boot_sel5"), + PINCTRL_PIN(PIN_BOOT_SEL6, "boot_sel6"), + PINCTRL_PIN(PIN_BOOT_SEL7, "boot_sel7"), + PINCTRL_PIN(PIN_MULTI_SCKT, "multi_sckt"), + PINCTRL_PIN(PIN_SCKT_ID0, "sckt_id0"), + PINCTRL_PIN(PIN_SCKT_ID1, "sckt_id1"), + PINCTRL_PIN(PIN_PLL_CLK_IN_MAIN, "pll_clk_in_main"), + PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_0, "pll_clk_in_ddr_0"), + PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_1, "pll_clk_in_ddr_1"), + PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_2, "pll_clk_in_ddr_2"), + PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_3, "pll_clk_in_ddr_3"), + PINCTRL_PIN(PIN_XTAL_32K, "xtal_32k"), + PINCTRL_PIN(PIN_SYS_RST, "sys_rst"), + PINCTRL_PIN(PIN_PWR_BUTTON, "pwr_button"), + PINCTRL_PIN(PIN_TEST_EN, "test_en"), + PINCTRL_PIN(PIN_TEST_MODE_MBIST, "test_mode_mbist"), + PINCTRL_PIN(PIN_TEST_MODE_SCAN, "test_mode_scan"), + PINCTRL_PIN(PIN_TEST_MODE_BSD, "test_mode_bsd"), + PINCTRL_PIN(PIN_BISR_BYP, "bisr_byp"), +}; + +static const struct sg2042_pin sg2044_pin_data[ARRAY_SIZE(sg2044_pins)] = { + SG2042_GENERAL_PIN(PIN_IIC0_SMBSUS_IN, 0x000, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC0_SMBSUS_OUT, 0x000, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC0_SMBALERT, 0x004, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC1_SMBSUS_IN, 0x004, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC1_SMBSUS_OUT, 0x008, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC1_SMBALERT, 0x008, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC2_SMBSUS_IN, 0x00c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC2_SMBSUS_OUT, 0x00c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC2_SMBALERT, 0x010, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC3_SMBSUS_IN, 0x010, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC3_SMBSUS_OUT, 0x014, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC3_SMBALERT, 0x014, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE0_L0_RESET, 0x018, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE0_L1_RESET, 0x018, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE0_L0_WAKEUP, 0x01c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE0_L1_WAKEUP, 0x01c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE0_L0_CLKREQ_IN, 0x020, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE0_L1_CLKREQ_IN, 0x020, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE1_L0_RESET, 0x024, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE1_L1_RESET, 0x024, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE1_L0_WAKEUP, 0x028, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE1_L1_WAKEUP, 0x028, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE1_L0_CLKREQ_IN, 0x02c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE1_L1_CLKREQ_IN, 0x02c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE2_L0_RESET, 0x030, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE2_L1_RESET, 0x030, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE2_L0_WAKEUP, 0x034, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE2_L1_WAKEUP, 0x034, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE2_L0_CLKREQ_IN, 0x038, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE2_L1_CLKREQ_IN, 0x038, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE3_L0_RESET, 0x03c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE3_L1_RESET, 0x03c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE3_L0_WAKEUP, 0x040, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE3_L1_WAKEUP, 0x040, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE3_L0_CLKREQ_IN, 0x044, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE3_L1_CLKREQ_IN, 0x044, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE4_L0_RESET, 0x048, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE4_L1_RESET, 0x048, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE4_L0_WAKEUP, 0x04c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE4_L1_WAKEUP, 0x04c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PCIE4_L0_CLKREQ_IN, 0x050, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PCIE4_L1_CLKREQ_IN, 0x050, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPIF0_CLK_SEL1, 0x054, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPIF0_CLK_SEL0, 0x054, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPIF0_WP, 0x058, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPIF0_HOLD, 0x058, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPIF0_SDI, 0x05c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPIF0_CS, 0x05c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPIF0_SCK, 0x060, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPIF0_SDO, 0x060, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPIF1_CLK_SEL1, 0x064, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPIF1_CLK_SEL0, 0x064, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPIF1_WP, 0x068, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPIF1_HOLD, 0x068, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPIF1_SDI, 0x06c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPIF1_CS, 0x06c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPIF1_SCK, 0x070, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPIF1_SDO, 0x070, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_EMMC_WP, 0x074, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_EMMC_CD, 0x074, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_EMMC_RST, 0x078, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_EMMC_PWR_EN, 0x078, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SDIO_CD, 0x07c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SDIO_WP, 0x07c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SDIO_RST, 0x080, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SDIO_PWR_EN, 0x080, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_TXD0, 0x084, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_TXD1, 0x084, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_TXD2, 0x088, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_TXD3, 0x088, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_TXCTRL, 0x08c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_RXD0, 0x08c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_RXD1, 0x090, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_RXD2, 0x090, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_RXD3, 0x094, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_RXCTRL, 0x094, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_TXC, 0x098, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_RXC, 0x098, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_REFCLKO, 0x09c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_IRQ, 0x09c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_RGMII0_MDC, 0x0a0, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_RGMII0_MDIO, 0x0a0, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PWM0, 0x0a4, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PWM1, 0x0a4, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_PWM2, 0x0a8, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_PWM3, 0x0a8, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_FAN0, 0x0ac, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_FAN1, 0x0ac, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_FAN2, 0x0b0, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_FAN3, 0x0b0, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC0_SDA, 0x0b4, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC0_SCL, 0x0b4, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC1_SDA, 0x0b8, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC1_SCL, 0x0b8, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC2_SDA, 0x0bc, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC2_SCL, 0x0bc, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_IIC3_SDA, 0x0c0, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_IIC3_SCL, 0x0c0, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_UART0_TX, 0x0c4, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_UART0_RX, 0x0c4, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_UART0_RTS, 0x0c8, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_UART0_CTS, 0x0c8, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_UART1_TX, 0x0cc, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_UART1_RX, 0x0cc, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_UART1_RTS, 0x0d0, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_UART1_CTS, 0x0d0, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_UART2_TX, 0x0d4, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_UART2_RX, 0x0d4, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_UART2_RTS, 0x0d8, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_UART2_CTS, 0x0d8, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_UART3_TX, 0x0dc, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_UART3_RX, 0x0dc, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_UART3_RTS, 0x0e0, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_UART3_CTS, 0x0e0, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPI0_CS0, 0x0e4, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPI0_CS1, 0x0e4, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPI0_SDI, 0x0e8, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPI0_SDO, 0x0e8, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPI0_SCK, 0x0ec, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPI1_CS0, 0x0ec, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPI1_CS1, 0x0f0, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPI1_SDI, 0x0f0, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_SPI1_SDO, 0x0f4, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_SPI1_SCK, 0x0f4, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG0_TDO, 0x0f8, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG0_TCK, 0x0f8, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG0_TDI, 0x0fc, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG0_TMS, 0x0fc, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG0_TRST, 0x100, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG0_SRST, 0x100, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG1_TDO, 0x104, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG1_TCK, 0x104, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG1_TDI, 0x108, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG1_TMS, 0x108, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG1_TRST, 0x10c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG1_SRST, 0x10c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG2_TDO, 0x110, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG2_TCK, 0x110, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG2_TDI, 0x114, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG2_TMS, 0x114, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG2_TRST, 0x118, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG2_SRST, 0x118, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG3_TDO, 0x11c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG3_TCK, 0x11c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG3_TDI, 0x120, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG3_TMS, 0x120, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_JTAG3_TRST, 0x124, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_JTAG3_SRST, 0x124, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO0, 0x128, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO1, 0x128, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO2, 0x12c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO3, 0x12c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO4, 0x130, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO5, 0x130, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO6, 0x134, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO7, 0x134, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO8, 0x138, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO9, 0x138, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO10, 0x13c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO11, 0x13c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO12, 0x140, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO13, 0x140, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO14, 0x144, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO15, 0x144, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO16, 0x148, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO17, 0x148, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO18, 0x14c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO19, 0x14c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO20, 0x150, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO21, 0x150, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO22, 0x154, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO23, 0x154, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO24, 0x158, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO25, 0x158, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO26, 0x15c, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO27, 0x15c, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO28, 0x160, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO29, 0x160, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_GPIO30, 0x164, + PIN_FLAG_DEFAULT), + SG2042_GENERAL_PIN(PIN_GPIO31, 0x164, + PIN_FLAG_WRITE_HIGH), + SG2042_GENERAL_PIN(PIN_MODE_SEL0, 0x168, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_MODE_SEL1, 0x168, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_MODE_SEL2, 0x16c, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL0, 0x16c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL1, 0x170, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL2, 0x170, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL3, 0x174, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL4, 0x174, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL5, 0x178, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL6, 0x178, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BOOT_SEL7, 0x17c, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_MULTI_SCKT, 0x17c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_SCKT_ID0, 0x180, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_SCKT_ID1, 0x180, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_MAIN, 0x184, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_0, 0x184, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_1, 0x188, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_2, 0x188, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_3, 0x18c, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_XTAL_32K, 0x18c, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_SYS_RST, 0x190, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_PWR_BUTTON, 0x190, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_TEST_EN, 0x194, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_TEST_MODE_MBIST, 0x194, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_TEST_MODE_SCAN, 0x198, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_TEST_MODE_BSD, 0x198, + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | + PIN_FLAG_NO_OEX_EN), + SG2042_GENERAL_PIN(PIN_BISR_BYP, 0x19c, + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), +}; + +static const struct sophgo_pinctrl_data sg2044_pindata = { + .pins = sg2044_pins, + .pindata = sg2044_pin_data, + .vddio_ops = &sg2044_vddio_cfg_ops, + .cfg_ops = &sg2042_cfg_ops, + .pctl_ops = &sg2042_pctrl_ops, + .pmx_ops = &sg2042_pmx_ops, + .pconf_ops = &sg2042_pconf_ops, + .npins = ARRAY_SIZE(sg2044_pins), + .pinsize = sizeof(struct sg2042_pin), +}; + +static const struct of_device_id sg2044_pinctrl_ids[] = { + { .compatible = "sophgo,sg2044-pinctrl", .data = &sg2044_pindata }, + { } +}; +MODULE_DEVICE_TABLE(of, sg2044_pinctrl_ids); + +static struct platform_driver sg2044_pinctrl_driver = { + .probe = sophgo_pinctrl_probe, + .driver = { + .name = "sg2044-pinctrl", + .suppress_bind_attrs = true, + .of_match_table = sg2044_pinctrl_ids, + }, +}; +module_platform_driver(sg2044_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for the SG2002 series SoC"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/sophgo/pinctrl-sophgo-common.c b/drivers/pinctrl/sophgo/pinctrl-sophgo-common.c new file mode 100644 index 000000000000..7f1fd68db19e --- /dev/null +++ b/drivers/pinctrl/sophgo/pinctrl-sophgo-common.c @@ -0,0 +1,451 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sophgo SoCs pinctrl common ops. + * + * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com> + * + */ + +#include <linux/bsearch.h> +#include <linux/cleanup.h> +#include <linux/export.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/spinlock.h> + +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> + +#include "../pinctrl-utils.h" +#include "../pinconf.h" +#include "../pinmux.h" + +#include "pinctrl-sophgo.h" + +static u16 sophgo_dt_get_pin(u32 value) +{ + return value; +} + +static int sophgo_cmp_pin(const void *key, const void *pivot) +{ + const struct sophgo_pin *pin = pivot; + int pin_id = (long)key; + int pivid = pin->id; + + return pin_id - pivid; +} + +const struct sophgo_pin *sophgo_get_pin(struct sophgo_pinctrl *pctrl, + unsigned long pin_id) +{ + return bsearch((void *)pin_id, pctrl->data->pindata, pctrl->data->npins, + pctrl->data->pinsize, sophgo_cmp_pin); +} + +static int sophgo_verify_pinmux_config(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin_mux_config *config) +{ + if (pctrl->data->cfg_ops->verify_pinmux_config) + return pctrl->data->cfg_ops->verify_pinmux_config(config); + return 0; +} + +static int sophgo_verify_pin_group(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin_mux_config *config, + unsigned int npins) +{ + if (pctrl->data->cfg_ops->verify_pin_group) + return pctrl->data->cfg_ops->verify_pin_group(config, npins); + return 0; +} + +static int sophgo_dt_node_to_map_post(struct device_node *cur, + struct sophgo_pinctrl *pctrl, + struct sophgo_pin_mux_config *config, + unsigned int npins) +{ + if (pctrl->data->cfg_ops->dt_node_to_map_post) + return pctrl->data->cfg_ops->dt_node_to_map_post(cur, pctrl, + config, npins); + return 0; +} + +int sophgo_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np, + struct pinctrl_map **maps, unsigned int *num_maps) +{ + struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct device *dev = pctrl->dev; + struct device_node *child; + struct pinctrl_map *map; + const char **grpnames; + const char *grpname; + int ngroups = 0; + int nmaps = 0; + int ret; + + for_each_available_child_of_node(np, child) + ngroups += 1; + + grpnames = devm_kcalloc(dev, ngroups, sizeof(*grpnames), GFP_KERNEL); + if (!grpnames) + return -ENOMEM; + + map = kcalloc(ngroups * 2, sizeof(*map), GFP_KERNEL); + if (!map) + return -ENOMEM; + + ngroups = 0; + guard(mutex)(&pctrl->mutex); + for_each_available_child_of_node(np, child) { + int npins = of_property_count_u32_elems(child, "pinmux"); + unsigned int *pins; + struct sophgo_pin_mux_config *pinmuxs; + u32 config; + int i; + + if (npins < 1) { + dev_err(dev, "invalid pinctrl group %pOFn.%pOFn\n", + np, child); + ret = -EINVAL; + goto dt_failed; + } + + grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", + np, child); + if (!grpname) { + ret = -ENOMEM; + goto dt_failed; + } + + grpnames[ngroups++] = grpname; + + pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); + if (!pins) { + ret = -ENOMEM; + goto dt_failed; + } + + pinmuxs = devm_kcalloc(dev, npins, sizeof(*pinmuxs), GFP_KERNEL); + if (!pinmuxs) { + ret = -ENOMEM; + goto dt_failed; + } + + for (i = 0; i < npins; i++) { + ret = of_property_read_u32_index(child, "pinmux", + i, &config); + if (ret) + goto dt_failed; + + pins[i] = sophgo_dt_get_pin(config); + pinmuxs[i].config = config; + pinmuxs[i].pin = sophgo_get_pin(pctrl, pins[i]); + + if (!pinmuxs[i].pin) { + dev_err(dev, "failed to get pin %d\n", pins[i]); + ret = -ENODEV; + goto dt_failed; + } + + ret = sophgo_verify_pinmux_config(pctrl, &pinmuxs[i]); + if (ret) { + dev_err(dev, "group %s pin %d is invalid\n", + grpname, i); + goto dt_failed; + } + } + + ret = sophgo_verify_pin_group(pctrl, pinmuxs, npins); + if (ret) { + dev_err(dev, "group %s is invalid\n", grpname); + goto dt_failed; + } + + ret = sophgo_dt_node_to_map_post(child, pctrl, pinmuxs, npins); + if (ret) + goto dt_failed; + + map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP; + map[nmaps].data.mux.function = np->name; + map[nmaps].data.mux.group = grpname; + nmaps += 1; + + ret = pinconf_generic_parse_dt_config(child, pctldev, + &map[nmaps].data.configs.configs, + &map[nmaps].data.configs.num_configs); + if (ret) { + dev_err(dev, "failed to parse pin config of group %s: %d\n", + grpname, ret); + goto dt_failed; + } + + ret = pinctrl_generic_add_group(pctldev, grpname, + pins, npins, pinmuxs); + if (ret < 0) { + dev_err(dev, "failed to add group %s: %d\n", grpname, ret); + goto dt_failed; + } + + /* don't create a map if there are no pinconf settings */ + if (map[nmaps].data.configs.num_configs == 0) + continue; + + map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; + map[nmaps].data.configs.group_or_pin = grpname; + nmaps += 1; + } + + ret = pinmux_generic_add_function(pctldev, np->name, + grpnames, ngroups, NULL); + if (ret < 0) { + dev_err(dev, "error adding function %s: %d\n", np->name, ret); + goto function_failed; + } + + *maps = map; + *num_maps = nmaps; + + return 0; + +dt_failed: + of_node_put(child); +function_failed: + pinctrl_utils_free_map(pctldev, map, nmaps); + return ret; +} + +int sophgo_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned int fsel, unsigned int gsel) +{ + struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct group_desc *group; + const struct sophgo_pin_mux_config *configs; + unsigned int i; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + configs = group->data; + + for (i = 0; i < group->grp.npins; i++) { + const struct sophgo_pin *pin = configs[i].pin; + u32 value = configs[i].config; + + guard(raw_spinlock_irqsave)(&pctrl->lock); + + pctrl->data->cfg_ops->set_pinmux_config(pctrl, pin, value); + } + + return 0; +} + +static int sophgo_pin_set_config(struct sophgo_pinctrl *pctrl, + unsigned int pin_id, + u32 value, u32 mask) +{ + const struct sophgo_pin *pin = sophgo_get_pin(pctrl, pin_id); + + if (!pin) + return -EINVAL; + + guard(raw_spinlock_irqsave)(&pctrl->lock); + + return pctrl->data->cfg_ops->set_pinconf_config(pctrl, pin, value, mask); +} + +int sophgo_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id, + unsigned long *configs, unsigned int num_configs) +{ + struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct sophgo_pin *pin = sophgo_get_pin(pctrl, pin_id); + u32 value, mask; + + if (!pin) + return -ENODEV; + + if (pctrl->data->cfg_ops->compute_pinconf_config(pctrl, pin, + configs, num_configs, + &value, &mask)) + return -ENOTSUPP; + + return sophgo_pin_set_config(pctrl, pin_id, value, mask); +} + +int sophgo_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int gsel, + unsigned long *configs, unsigned int num_configs) +{ + struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct group_desc *group; + const struct sophgo_pin_mux_config *pinmuxs; + u32 value, mask; + int i; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + pinmuxs = group->data; + + if (pctrl->data->cfg_ops->compute_pinconf_config(pctrl, pinmuxs[0].pin, + configs, num_configs, + &value, &mask)) + return -ENOTSUPP; + + for (i = 0; i < group->grp.npins; i++) + sophgo_pin_set_config(pctrl, group->grp.pins[i], value, mask); + + return 0; +} + +u32 sophgo_pinctrl_typical_pull_down(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg) +{ + return pctrl->data->vddio_ops->get_pull_down(pin, power_cfg); +} + +u32 sophgo_pinctrl_typical_pull_up(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg) +{ + return pctrl->data->vddio_ops->get_pull_up(pin, power_cfg); +} + +int sophgo_pinctrl_oc2reg(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg, u32 target) +{ + const u32 *map; + int i, len; + + if (!pctrl->data->vddio_ops->get_oc_map) + return -ENOTSUPP; + + len = pctrl->data->vddio_ops->get_oc_map(pin, power_cfg, &map); + if (len < 0) + return len; + + for (i = 0; i < len; i++) { + if (map[i] >= target) + return i; + } + + return -EINVAL; +} + +int sophgo_pinctrl_reg2oc(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg, u32 reg) +{ + const u32 *map; + int len; + + if (!pctrl->data->vddio_ops->get_oc_map) + return -ENOTSUPP; + + len = pctrl->data->vddio_ops->get_oc_map(pin, power_cfg, &map); + if (len < 0) + return len; + + if (reg >= len) + return -EINVAL; + + return map[reg]; +} + +int sophgo_pinctrl_schmitt2reg(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg, u32 target) +{ + const u32 *map; + int i, len; + + if (!pctrl->data->vddio_ops->get_schmitt_map) + return -ENOTSUPP; + + len = pctrl->data->vddio_ops->get_schmitt_map(pin, power_cfg, &map); + if (len < 0) + return len; + + for (i = 0; i < len; i++) { + if (map[i] == target) + return i; + } + + return -EINVAL; +} + +int sophgo_pinctrl_reg2schmitt(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg, u32 reg) +{ + const u32 *map; + int len; + + if (!pctrl->data->vddio_ops->get_schmitt_map) + return -ENOTSUPP; + + len = pctrl->data->vddio_ops->get_schmitt_map(pin, power_cfg, &map); + if (len < 0) + return len; + + if (reg >= len) + return -EINVAL; + + return map[reg]; +} + +int sophgo_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct sophgo_pinctrl *pctrl; + const struct sophgo_pinctrl_data *pctrl_data; + int ret; + + pctrl_data = device_get_match_data(dev); + if (!pctrl_data) + return -ENODEV; + + if (pctrl_data->npins == 0) + return dev_err_probe(dev, -EINVAL, "invalid pin data\n"); + + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->pdesc.name = dev_name(dev); + pctrl->pdesc.pins = pctrl_data->pins; + pctrl->pdesc.npins = pctrl_data->npins; + pctrl->pdesc.pctlops = pctrl_data->pctl_ops; + pctrl->pdesc.pmxops = pctrl_data->pmx_ops; + pctrl->pdesc.confops = pctrl_data->pconf_ops; + pctrl->pdesc.owner = THIS_MODULE; + + pctrl->data = pctrl_data; + pctrl->dev = dev; + raw_spin_lock_init(&pctrl->lock); + mutex_init(&pctrl->mutex); + + ret = pctrl->data->cfg_ops->pctrl_init(pdev, pctrl); + if (ret) + return ret; + + platform_set_drvdata(pdev, pctrl); + + ret = devm_pinctrl_register_and_init(dev, &pctrl->pdesc, + pctrl, &pctrl->pctrl_dev); + if (ret) + return dev_err_probe(dev, ret, + "fail to register pinctrl driver\n"); + + return pinctrl_enable(pctrl->pctrl_dev); +} +EXPORT_SYMBOL_GPL(sophgo_pinctrl_probe); + +MODULE_DESCRIPTION("Common pinctrl helper function for the Sophgo SoC"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/sophgo/pinctrl-sophgo.h b/drivers/pinctrl/sophgo/pinctrl-sophgo.h new file mode 100644 index 000000000000..4cd9b5484894 --- /dev/null +++ b/drivers/pinctrl/sophgo/pinctrl-sophgo.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com> + */ + +#ifndef _PINCTRL_SOPHGO_H +#define _PINCTRL_SOPHGO_H + +#include <linux/device.h> +#include <linux/mutex.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> + +#include "../core.h" + +struct sophgo_pinctrl; + +struct sophgo_pin { + u16 id; + u16 flags; +}; + +struct sophgo_pin_mux_config { + const struct sophgo_pin *pin; + u32 config; +}; + +/** + * struct sophgo_cfg_ops - pin configuration operations + * + * @pctrl_init: soc specific init callback + * @verify_pinmux_config: verify the pinmux config for a pin + * @verify_pin_group: verify the whole pinmux group + * @dt_node_to_map_post: post init for the pinmux config map + * @compute_pinconf_config: compute pinconf config + * @set_pinconf_config: set pinconf config (the caller holds lock) + * @set_pinmux_config: set mux config (the caller holds lock) + */ +struct sophgo_cfg_ops { + int (*pctrl_init)(struct platform_device *pdev, + struct sophgo_pinctrl *pctrl); + int (*verify_pinmux_config)(const struct sophgo_pin_mux_config *config); + int (*verify_pin_group)(const struct sophgo_pin_mux_config *pinmuxs, + unsigned int npins); + int (*dt_node_to_map_post)(struct device_node *cur, + struct sophgo_pinctrl *pctrl, + struct sophgo_pin_mux_config *pinmuxs, + unsigned int npins); + int (*compute_pinconf_config)(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp, + unsigned long *configs, + unsigned int num_configs, + u32 *value, u32 *mask); + int (*set_pinconf_config)(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp, + u32 value, u32 mask); + void (*set_pinmux_config)(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *sp, u32 config); +}; + +/** + * struct sophgo_vddio_cfg_ops - pin vddio operations + * + * @get_pull_up: get resistor for pull up; + * @get_pull_down: get resistor for pull down. + * @get_oc_map: get mapping for typical low level output current value to + * register value map. + * @get_schmitt_map: get mapping for register value to typical schmitt + * threshold. + */ +struct sophgo_vddio_cfg_ops { + int (*get_pull_up)(const struct sophgo_pin *pin, const u32 *psmap); + int (*get_pull_down)(const struct sophgo_pin *pin, const u32 *psmap); + int (*get_oc_map)(const struct sophgo_pin *pin, const u32 *psmap, + const u32 **map); + int (*get_schmitt_map)(const struct sophgo_pin *pin, const u32 *psmap, + const u32 **map); +}; + +struct sophgo_pinctrl_data { + const struct pinctrl_pin_desc *pins; + const void *pindata; + const char * const *pdnames; + const struct sophgo_vddio_cfg_ops *vddio_ops; + const struct sophgo_cfg_ops *cfg_ops; + const struct pinctrl_ops *pctl_ops; + const struct pinmux_ops *pmx_ops; + const struct pinconf_ops *pconf_ops; + u16 npins; + u16 npds; + u16 pinsize; +}; + +struct sophgo_pinctrl { + struct device *dev; + struct pinctrl_dev *pctrl_dev; + const struct sophgo_pinctrl_data *data; + struct pinctrl_desc pdesc; + + struct mutex mutex; + raw_spinlock_t lock; + void *priv_ctrl; +}; + +const struct sophgo_pin *sophgo_get_pin(struct sophgo_pinctrl *pctrl, + unsigned long pin_id); +int sophgo_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np, + struct pinctrl_map **maps, unsigned int *num_maps); +int sophgo_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned int fsel, unsigned int gsel); +int sophgo_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id, + unsigned long *configs, unsigned int num_configs); +int sophgo_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int gsel, + unsigned long *configs, unsigned int num_configs); +u32 sophgo_pinctrl_typical_pull_down(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg); +u32 sophgo_pinctrl_typical_pull_up(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg); +int sophgo_pinctrl_oc2reg(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg, u32 target); +int sophgo_pinctrl_reg2oc(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg, u32 reg); +int sophgo_pinctrl_schmitt2reg(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg, u32 target); +int sophgo_pinctrl_reg2schmitt(struct sophgo_pinctrl *pctrl, + const struct sophgo_pin *pin, + const u32 *power_cfg, u32 reg); +int sophgo_pinctrl_probe(struct platform_device *pdev); + +#endif /* _PINCTRL_SOPHGO_H */ diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c index 59fd555ff38d..9996b1c4a07e 100644 --- a/drivers/pinctrl/spacemit/pinctrl-k1.c +++ b/drivers/pinctrl/spacemit/pinctrl-k1.c @@ -2,6 +2,7 @@ /* Copyright (c) 2024 Yixun Lan <dlan@gentoo.org> */ #include <linux/bits.h> +#include <linux/clk.h> #include <linux/cleanup.h> #include <linux/io.h> #include <linux/of.h> @@ -9,6 +10,7 @@ #include <linux/seq_file.h> #include <linux/spinlock.h> #include <linux/module.h> +#include <linux/mutex.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> @@ -720,6 +722,7 @@ static int spacemit_pinctrl_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct spacemit_pinctrl *pctrl; + struct clk *func_clk, *bus_clk; const struct spacemit_pinctrl_data *pctrl_data; int ret; @@ -738,6 +741,14 @@ static int spacemit_pinctrl_probe(struct platform_device *pdev) if (IS_ERR(pctrl->regs)) return PTR_ERR(pctrl->regs); + func_clk = devm_clk_get_enabled(dev, "func"); + if (IS_ERR(func_clk)) + return dev_err_probe(dev, PTR_ERR(func_clk), "failed to get func clock\n"); + + bus_clk = devm_clk_get_enabled(dev, "bus"); + if (IS_ERR(bus_clk)) + return dev_err_probe(dev, PTR_ERR(bus_clk), "failed to get bus clock\n"); + pctrl->pdesc.name = dev_name(dev); pctrl->pdesc.pins = pctrl_data->pins; pctrl->pdesc.npins = pctrl_data->npins; @@ -749,7 +760,10 @@ static int spacemit_pinctrl_probe(struct platform_device *pdev) pctrl->data = pctrl_data; pctrl->dev = dev; raw_spin_lock_init(&pctrl->lock); - mutex_init(&pctrl->mutex); + + ret = devm_mutex_init(dev, &pctrl->mutex); + if (ret) + return ret; platform_set_drvdata(pdev, pctrl); diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index cc0b4d1d7cff..e6ad63df82b7 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -228,11 +228,14 @@ static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); } -static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +static int stm32_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) { struct stm32_gpio_bank *bank = gpiochip_get_data(chip); __stm32_gpio_set(bank, offset, value); + + return 0; } static int stm32_gpio_direction_output(struct gpio_chip *chip, @@ -308,7 +311,7 @@ static const struct gpio_chip stm32_gpio_template = { .request = stm32_gpio_request, .free = pinctrl_gpio_free, .get = stm32_gpio_get, - .set = stm32_gpio_set, + .set_rv = stm32_gpio_set, .direction_input = pinctrl_gpio_direction_input, .direction_output = stm32_gpio_direction_output, .to_irq = stm32_gpio_to_irq, @@ -408,6 +411,7 @@ static struct irq_chip stm32_gpio_irq_chip = { .irq_set_wake = irq_chip_set_wake_parent, .irq_request_resources = stm32_gpio_irq_request_resources, .irq_release_resources = stm32_gpio_irq_release_resources, + .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL, }; static int stm32_gpio_domain_translate(struct irq_domain *d, diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index a78fdbbdfc0c..dc62eba96348 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -131,4 +131,14 @@ config PINCTRL_SUN50I_H616_R default ARM64 && ARCH_SUNXI select PINCTRL_SUNXI +config PINCTRL_SUN55I_A523 + bool "Support for the Allwinner A523 PIO" + default ARM64 && ARCH_SUNXI + select PINCTRL_SUNXI + +config PINCTRL_SUN55I_A523_R + bool "Support for the Allwinner A523 R-PIO" + default ARM64 && ARCH_SUNXI + select PINCTRL_SUNXI + endif diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 2ff5a55927ad..951b3f1e4b4f 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 # Core obj-y += pinctrl-sunxi.o +obj-y += pinctrl-sunxi-dt.o # SoC Drivers obj-$(CONFIG_PINCTRL_SUNIV_F1C100S) += pinctrl-suniv-f1c100s.o @@ -26,5 +27,7 @@ obj-$(CONFIG_PINCTRL_SUN50I_H6) += pinctrl-sun50i-h6.o obj-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o obj-$(CONFIG_PINCTRL_SUN50I_H616) += pinctrl-sun50i-h616.o obj-$(CONFIG_PINCTRL_SUN50I_H616_R) += pinctrl-sun50i-h616-r.o +obj-$(CONFIG_PINCTRL_SUN55I_A523) += pinctrl-sun55i-a523.o +obj-$(CONFIG_PINCTRL_SUN55I_A523_R) += pinctrl-sun55i-a523-r.o obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c b/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c index 8e2aab542fcf..8efe35b77af4 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c @@ -820,15 +820,13 @@ static const struct sunxi_pinctrl_desc d1_pinctrl_data = { static int d1_pinctrl_probe(struct platform_device *pdev) { - unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev); - - return sunxi_pinctrl_init_with_variant(pdev, &d1_pinctrl_data, variant); + return sunxi_pinctrl_init_with_flags(pdev, &d1_pinctrl_data, + SUNXI_PINCTRL_NEW_REG_LAYOUT); } static const struct of_device_id d1_pinctrl_match[] = { { .compatible = "allwinner,sun20i-d1-pinctrl", - .data = (void *)PINCTRL_SUN20I_D1 }, {} }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c index fa47fe36ee5b..b2e82bf927b3 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c @@ -17,6 +17,10 @@ #include "pinctrl-sunxi.h" +#define PINCTRL_SUN4I_A10 BIT(0) +#define PINCTRL_SUN7I_A20 BIT(1) +#define PINCTRL_SUN8I_R40 BIT(2) + static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -1295,8 +1299,8 @@ static int sun4i_a10_pinctrl_probe(struct platform_device *pdev) { unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev); - return sunxi_pinctrl_init_with_variant(pdev, &sun4i_a10_pinctrl_data, - variant); + return sunxi_pinctrl_init_with_flags(pdev, &sun4i_a10_pinctrl_data, + variant); } static const struct of_device_id sun4i_a10_pinctrl_match[] = { diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c new file mode 100644 index 000000000000..69cd2b4ebd7d --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Allwinner A523 SoC r-pinctrl driver. + * + * Copyright (C) 2024 Arm Ltd. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-sunxi.h" + +static const u8 a523_r_nr_bank_pins[SUNXI_PINCTRL_MAX_BANKS] = +/* PL PM */ + { 14, 6 }; + +static const unsigned int a523_r_irq_bank_map[] = { 0, 1 }; + +static const u8 a523_r_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] = +/* PL PM */ + { 14, 14 }; + +static struct sunxi_pinctrl_desc a523_r_pinctrl_data = { + .irq_banks = ARRAY_SIZE(a523_r_irq_bank_map), + .irq_bank_map = a523_r_irq_bank_map, + .irq_read_needs_mux = true, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, + .pin_base = PL_BASE, +}; + +static int a523_r_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_dt_table_init(pdev, a523_r_nr_bank_pins, + a523_r_irq_bank_muxes, + &a523_r_pinctrl_data, + SUNXI_PINCTRL_NEW_REG_LAYOUT); +} + +static const struct of_device_id a523_r_pinctrl_match[] = { + { .compatible = "allwinner,sun55i-a523-r-pinctrl", }, + {} +}; + +static struct platform_driver a523_r_pinctrl_driver = { + .probe = a523_r_pinctrl_probe, + .driver = { + .name = "sun55i-a523-r-pinctrl", + .of_match_table = a523_r_pinctrl_match, + }, +}; +builtin_platform_driver(a523_r_pinctrl_driver); diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c new file mode 100644 index 000000000000..7d2308c37d29 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Allwinner A523 SoC pinctrl driver. + * + * Copyright (C) 2023 Arm Ltd. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-sunxi.h" + +static const u8 a523_nr_bank_pins[SUNXI_PINCTRL_MAX_BANKS] = +/* PA PB PC PD PE PF PG PH PI PJ PK */ + { 0, 15, 17, 24, 16, 7, 15, 20, 17, 28, 24 }; + +static const unsigned int a523_irq_bank_map[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 }; + +static const u8 a523_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] = +/* PA PB PC PD PE PF PG PH PI PJ PK */ + { 0, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}; + +static struct sunxi_pinctrl_desc a523_pinctrl_data = { + .irq_banks = ARRAY_SIZE(a523_irq_bank_map), + .irq_bank_map = a523_irq_bank_map, + .irq_read_needs_mux = true, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, +}; + +static int a523_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_dt_table_init(pdev, a523_nr_bank_pins, + a523_irq_bank_muxes, + &a523_pinctrl_data, + SUNXI_PINCTRL_NEW_REG_LAYOUT | + SUNXI_PINCTRL_ELEVEN_BANKS); +} + +static const struct of_device_id a523_pinctrl_match[] = { + { .compatible = "allwinner,sun55i-a523-pinctrl", }, + {} +}; + +static struct platform_driver a523_pinctrl_driver = { + .probe = a523_pinctrl_probe, + .driver = { + .name = "sun55i-a523-pinctrl", + .of_match_table = a523_pinctrl_match, + }, +}; +builtin_platform_driver(a523_pinctrl_driver); diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i.c b/drivers/pinctrl/sunxi/pinctrl-sun5i.c index 06ecb121c827..6eef314c9377 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun5i.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun5i.c @@ -16,6 +16,10 @@ #include "pinctrl-sunxi.h" +#define PINCTRL_SUN5I_A10S BIT(0) +#define PINCTRL_SUN5I_A13 BIT(1) +#define PINCTRL_SUN5I_GR8 BIT(2) + static const struct sunxi_desc_pin sun5i_pins[] = { SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 0), PINCTRL_SUN5I_A10S, @@ -719,8 +723,8 @@ static int sun5i_pinctrl_probe(struct platform_device *pdev) { unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev); - return sunxi_pinctrl_init_with_variant(pdev, &sun5i_pinctrl_data, - variant); + return sunxi_pinctrl_init_with_flags(pdev, &sun5i_pinctrl_data, + variant); } static const struct of_device_id sun5i_pinctrl_match[] = { diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c index 82ac064931df..8d8c92ce41cf 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c @@ -17,6 +17,9 @@ #include "pinctrl-sunxi.h" +#define PINCTRL_SUN6I_A31 BIT(0) +#define PINCTRL_SUN6I_A31S BIT(1) + static const struct sunxi_desc_pin sun6i_a31_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -972,9 +975,8 @@ static int sun6i_a31_pinctrl_probe(struct platform_device *pdev) unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev); - return sunxi_pinctrl_init_with_variant(pdev, - &sun6i_a31_pinctrl_data, - variant); + return sunxi_pinctrl_init_with_flags(pdev, &sun6i_a31_pinctrl_data, + variant); } static const struct of_device_id sun6i_a31_pinctrl_match[] = { diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c index 49c9a0b6a0eb..696d7dd8d87b 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c @@ -22,6 +22,9 @@ #include "pinctrl-sunxi.h" +#define PINCTRL_SUN8I_V3 BIT(0) +#define PINCTRL_SUN8I_V3S BIT(1) + static const struct sunxi_desc_pin sun8i_v3s_pins[] = { /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), @@ -552,8 +555,8 @@ static int sun8i_v3s_pinctrl_probe(struct platform_device *pdev) { unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev); - return sunxi_pinctrl_init_with_variant(pdev, &sun8i_v3s_pinctrl_data, - variant); + return sunxi_pinctrl_init_with_flags(pdev, &sun8i_v3s_pinctrl_data, + variant); } static const struct of_device_id sun8i_v3s_pinctrl_match[] = { diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c b/drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c new file mode 100644 index 000000000000..4e34b0cd3b73 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017-2025 Arm Ltd. + * + * Generic DT driven Allwinner pinctrl driver routines. + * Builds the pin tables from minimal driver information and pin groups + * described in the DT. Then hands those tables of to the traditional + * sunxi pinctrl driver. + * sunxi_pinctrl_init() expects a table like shown below, previously spelled + * out in a per-SoC .c file. This code generates this table, like so: + * + * SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), // code iterates over every implemented + * // pin, based on pins_per_bank[] array passed in + * + * SUNXI_FUNCTION(0x0, "gpio_in"), // always added, for every pin + * SUNXI_FUNCTION(0x1, "gpio_out"), // always added, for every pin + * + * SUNXI_FUNCTION(0x2, "mmc0"), // based on pingroup found in DT: + * // mmc0-pins { + * // pins = "PF0", "PF1", ... + * // function = "mmc0"; + * // allwinner,pinmux = <2>; + * + * SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 1)), // derived by irq_bank_muxes[] + * // array passed in + */ + +#include <linux/export.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include "pinctrl-sunxi.h" + +#define INVALID_MUX 0xff + +/* + * Return the "index"th element from the "allwinner,pinmux" property. If the + * property does not hold enough entries, return the last one instead. + * For almost every group the pinmux value is actually the same, so this + * allows to just list one value in the property. + */ +static u8 sunxi_pinctrl_dt_read_pinmux(const struct device_node *node, + int index) +{ + int ret, num_elems; + u32 value; + + num_elems = of_property_count_u32_elems(node, "allwinner,pinmux"); + if (num_elems <= 0) + return INVALID_MUX; + + if (index >= num_elems) + index = num_elems - 1; + + ret = of_property_read_u32_index(node, "allwinner,pinmux", index, + &value); + if (ret) + return INVALID_MUX; + + return value; +} + +/* + * Allocate a table with a sunxi_desc_pin structure for every pin needed. + * Fills in the respective pin names ("PA0") and their pin numbers. + * Returns the pins array. We cannot use the member in *desc yet, as this + * is marked as const, and we will need to change the array still. + */ +static struct sunxi_desc_pin *init_pins_table(struct device *dev, + const u8 *pins_per_bank, + struct sunxi_pinctrl_desc *desc) +{ + struct sunxi_desc_pin *pins, *cur_pin; + int name_size = 0; + int port_base = desc->pin_base / PINS_PER_BANK; + char *pin_names, *cur_name; + int i, j; + + /* + * Find the total number of pins. + * Also work out how much memory we need to store all the pin names. + */ + for (i = 0; i < SUNXI_PINCTRL_MAX_BANKS; i++) { + desc->npins += pins_per_bank[i]; + if (pins_per_bank[i] < 10) { + /* 4 bytes for "PXy\0" */ + name_size += pins_per_bank[i] * 4; + } else { + /* 4 bytes for each "PXy\0" */ + name_size += 10 * 4; + + /* 5 bytes for each "PXyy\0" */ + name_size += (pins_per_bank[i] - 10) * 5; + } + } + + if (desc->npins == 0) { + dev_err(dev, "no ports defined\n"); + return ERR_PTR(-EINVAL); + } + + pins = devm_kzalloc(dev, desc->npins * sizeof(*pins), GFP_KERNEL); + if (!pins) + return ERR_PTR(-ENOMEM); + + /* Allocate memory to store the name for every pin. */ + pin_names = devm_kmalloc(dev, name_size, GFP_KERNEL); + if (!pin_names) + return ERR_PTR(-ENOMEM); + + /* Fill the pins array with the name and the number for each pin. */ + cur_name = pin_names; + cur_pin = pins; + for (i = 0; i < SUNXI_PINCTRL_MAX_BANKS; i++) { + for (j = 0; j < pins_per_bank[i]; j++, cur_pin++) { + int nchars = sprintf(cur_name, "P%c%d", + port_base + 'A' + i, j); + + cur_pin->pin.number = (port_base + i) * PINS_PER_BANK + j; + cur_pin->pin.name = cur_name; + cur_name += nchars + 1; + } + } + + return pins; +} + +/* + * Work out the number of functions for each pin. This will visit every + * child node of the pinctrl DT node to find all advertised functions. + * Provide memory to hold the per-function information and assign it to + * the pin table. + * Fill in the GPIO in/out functions already (that every pin has), also add + * an "irq" function at the end, for those pins in IRQ-capable ports. + * We do not fill in the extra functions (those describe in DT nodes) yet. + * We (ab)use the "variant" member in each pin to keep track of the number of + * extra functions needed. At the end this will get reset to 2, so that we + * can add extra function later, after the two GPIO functions. + */ +static int prepare_function_table(struct device *dev, struct device_node *pnode, + struct sunxi_desc_pin *pins, int npins, + unsigned pin_base, const u8 *irq_bank_muxes) +{ + struct device_node *node; + struct property *prop; + struct sunxi_desc_function *func; + int num_funcs, irq_bank, last_bank, i; + + /* + * We need at least three functions per pin: + * - one for GPIO in + * - one for GPIO out + * - one for the sentinel signalling the end of the list + */ + num_funcs = 3 * npins; + + /* + * Add a function for each pin in a bank supporting interrupts. + * We temporarily (ab)use the variant field to store the number of + * functions per pin. This will be cleaned back to 0 before we hand + * over the whole structure to the generic sunxi pinctrl setup code. + */ + for (i = 0; i < npins; i++) { + struct sunxi_desc_pin *pin = &pins[i]; + int bank = (pin->pin.number - pin_base) / PINS_PER_BANK; + + if (irq_bank_muxes[bank]) { + pin->variant++; + num_funcs++; + } + } + + /* + * Go over each pin group (every child of the pinctrl DT node) and + * add the number of special functions each pins has. Also update the + * total number of functions required. + * We might slightly overshoot here in case of double definitions. + */ + for_each_child_of_node(pnode, node) { + const char *name; + + of_property_for_each_string(node, "pins", prop, name) { + for (i = 0; i < npins; i++) { + if (strcmp(pins[i].pin.name, name)) + continue; + + pins[i].variant++; + num_funcs++; + break; + } + } + } + + /* + * Allocate the memory needed for the functions in one table. + * We later use pointers into this table to mark each pin. + */ + func = devm_kzalloc(dev, num_funcs * sizeof(*func), GFP_KERNEL); + if (!func) + return -ENOMEM; + + /* + * Assign the function's memory and fill in GPIOs, IRQ and a sentinel. + * The extra functions will be filled in later. + */ + irq_bank = 0; + last_bank = 0; + for (i = 0; i < npins; i++) { + struct sunxi_desc_pin *pin = &pins[i]; + int bank = (pin->pin.number - pin_base) / PINS_PER_BANK; + int lastfunc = pin->variant + 1; + int irq_mux = irq_bank_muxes[bank]; + + func[0].name = "gpio_in"; + func[0].muxval = 0; + func[1].name = "gpio_out"; + func[1].muxval = 1; + + if (irq_mux) { + if (bank > last_bank) + irq_bank++; + func[lastfunc].muxval = irq_mux; + func[lastfunc].irqbank = irq_bank; + func[lastfunc].irqnum = pin->pin.number % PINS_PER_BANK; + func[lastfunc].name = "irq"; + } + + if (bank > last_bank) + last_bank = bank; + + pin->functions = func; + + /* Skip over the other needed functions and the sentinel. */ + func += pin->variant + 3; + + /* + * Reset the value for filling in the remaining functions + * behind the GPIOs later. + */ + pin->variant = 2; + } + + return 0; +} + +/* + * Iterate over all pins in a single group and add the function name and its + * mux value to the respective pin. + * The "variant" member is again used to temporarily track the number of + * already added functions. + */ +static void fill_pin_function(struct device *dev, struct device_node *node, + struct sunxi_desc_pin *pins, int npins) +{ + const char *name, *funcname; + struct sunxi_desc_function *func; + struct property *prop; + int pin, i, index; + u8 muxval; + + if (of_property_read_string(node, "function", &funcname)) { + dev_warn(dev, "missing \"function\" property\n"); + return; + } + + index = 0; + of_property_for_each_string(node, "pins", prop, name) { + /* Find the index of this pin in our table. */ + for (pin = 0; pin < npins; pin++) + if (!strcmp(pins[pin].pin.name, name)) + break; + if (pin == npins) { + dev_warn(dev, "%s: cannot find pin %s\n", + of_node_full_name(node), name); + index++; + continue; + } + + /* Read the associated mux value. */ + muxval = sunxi_pinctrl_dt_read_pinmux(node, index); + if (muxval == INVALID_MUX) { + dev_warn(dev, "%s: invalid mux value for pin %s\n", + of_node_full_name(node), name); + index++; + continue; + } + + /* + * Check for double definitions by comparing the to-be-added + * function with already assigned ones. + * Ignore identical pairs (function name and mux value the + * same), but warn about conflicting assignments. + */ + for (i = 2; i < pins[pin].variant; i++) { + func = &pins[pin].functions[i]; + + /* Skip over totally unrelated functions. */ + if (strcmp(func->name, funcname) && + func->muxval != muxval) + continue; + + /* Ignore (but skip below) any identical functions. */ + if (!strcmp(func->name, funcname) && + muxval == func->muxval) + break; + + dev_warn(dev, + "pin %s: function %s redefined to mux %d\n", + name, funcname, muxval); + break; + } + + /* Skip any pins with that function already assigned. */ + if (i < pins[pin].variant) { + index++; + continue; + } + + /* Assign function and muxval to the next free slot. */ + func = &pins[pin].functions[pins[pin].variant]; + func->muxval = muxval; + func->name = funcname; + + pins[pin].variant++; + index++; + } +} + +/* + * Initialise the pinctrl table, by building it from driver provided + * information: the number of pins per bank, the IRQ capable banks and their + * IRQ mux value. + * Then iterate over all pinctrl DT node children to enter the function name + * and mux values for each mentioned pin. + * At the end hand over this structure to the actual sunxi pinctrl driver. + */ +int sunxi_pinctrl_dt_table_init(struct platform_device *pdev, + const u8 *pins_per_bank, + const u8 *irq_bank_muxes, + struct sunxi_pinctrl_desc *desc, + unsigned long flags) +{ + struct device_node *pnode = pdev->dev.of_node, *node; + struct sunxi_desc_pin *pins; + int ret, i; + + pins = init_pins_table(&pdev->dev, pins_per_bank, desc); + if (IS_ERR(pins)) + return PTR_ERR(pins); + + ret = prepare_function_table(&pdev->dev, pnode, pins, desc->npins, + desc->pin_base, irq_bank_muxes); + if (ret) + return ret; + + /* + * Now iterate over all groups and add the respective function name + * and mux values to each pin listed within. + */ + for_each_child_of_node(pnode, node) + fill_pin_function(&pdev->dev, node, pins, desc->npins); + + /* Clear the temporary storage. */ + for (i = 0; i < desc->npins; i++) + pins[i].variant = 0; + + desc->pins = pins; + + return sunxi_pinctrl_init_with_flags(pdev, desc, flags); +} diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index bde67ee31417..d63859a2a64e 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -58,13 +58,29 @@ static struct irq_chip sunxi_pinctrl_level_irq_chip; * The following functions calculate the register and the bit offset to access. * They take a pin number which is relative to the start of the current device. */ + +/* + * When using the extended register layout, Bank K does not fit into the + * space used for the other banks. Instead it lives at offset 0x500. + */ +static u32 sunxi_bank_offset(const struct sunxi_pinctrl *pctl, u32 pin) +{ + u32 offset = 0; + + if (pin >= PK_BASE) { + pin -= PK_BASE; + offset = PIO_BANK_K_OFFSET; + } + + return offset + (pin / PINS_PER_BANK) * pctl->bank_mem_size; +} + static void sunxi_mux_reg(const struct sunxi_pinctrl *pctl, u32 pin, u32 *reg, u32 *shift, u32 *mask) { - u32 bank = pin / PINS_PER_BANK; u32 offset = pin % PINS_PER_BANK * MUX_FIELD_WIDTH; - *reg = bank * pctl->bank_mem_size + MUX_REGS_OFFSET + + *reg = sunxi_bank_offset(pctl, pin) + MUX_REGS_OFFSET + offset / BITS_PER_TYPE(u32) * sizeof(u32); *shift = offset % BITS_PER_TYPE(u32); *mask = (BIT(MUX_FIELD_WIDTH) - 1) << *shift; @@ -73,10 +89,9 @@ static void sunxi_mux_reg(const struct sunxi_pinctrl *pctl, static void sunxi_data_reg(const struct sunxi_pinctrl *pctl, u32 pin, u32 *reg, u32 *shift, u32 *mask) { - u32 bank = pin / PINS_PER_BANK; u32 offset = pin % PINS_PER_BANK * DATA_FIELD_WIDTH; - *reg = bank * pctl->bank_mem_size + DATA_REGS_OFFSET + + *reg = sunxi_bank_offset(pctl, pin) + DATA_REGS_OFFSET + offset / BITS_PER_TYPE(u32) * sizeof(u32); *shift = offset % BITS_PER_TYPE(u32); *mask = (BIT(DATA_FIELD_WIDTH) - 1) << *shift; @@ -85,10 +100,9 @@ static void sunxi_data_reg(const struct sunxi_pinctrl *pctl, static void sunxi_dlevel_reg(const struct sunxi_pinctrl *pctl, u32 pin, u32 *reg, u32 *shift, u32 *mask) { - u32 bank = pin / PINS_PER_BANK; u32 offset = pin % PINS_PER_BANK * pctl->dlevel_field_width; - *reg = bank * pctl->bank_mem_size + DLEVEL_REGS_OFFSET + + *reg = sunxi_bank_offset(pctl, pin) + DLEVEL_REGS_OFFSET + offset / BITS_PER_TYPE(u32) * sizeof(u32); *shift = offset % BITS_PER_TYPE(u32); *mask = (BIT(pctl->dlevel_field_width) - 1) << *shift; @@ -97,10 +111,9 @@ static void sunxi_dlevel_reg(const struct sunxi_pinctrl *pctl, static void sunxi_pull_reg(const struct sunxi_pinctrl *pctl, u32 pin, u32 *reg, u32 *shift, u32 *mask) { - u32 bank = pin / PINS_PER_BANK; u32 offset = pin % PINS_PER_BANK * PULL_FIELD_WIDTH; - *reg = bank * pctl->bank_mem_size + pctl->pull_regs_offset + + *reg = sunxi_bank_offset(pctl, pin) + pctl->pull_regs_offset + offset / BITS_PER_TYPE(u32) * sizeof(u32); *shift = offset % BITS_PER_TYPE(u32); *mask = (BIT(PULL_FIELD_WIDTH) - 1) << *shift; @@ -395,6 +408,7 @@ static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, const char *function, *pin_prop; const char *group; int ret, npins, nmaps, configlen = 0, i = 0; + struct pinctrl_map *new_map; *map = NULL; *num_maps = 0; @@ -469,9 +483,13 @@ static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, * We know have the number of maps we need, we can resize our * map array */ - *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL); - if (!*map) - return -ENOMEM; + new_map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL); + if (!new_map) { + ret = -ENOMEM; + goto err_free_map; + } + + *map = new_map; return 0; @@ -723,9 +741,11 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, val = uV > 1800000 && uV <= 2500000 ? BIT(bank) : 0; raw_spin_lock_irqsave(&pctl->lock, flags); - reg = readl(pctl->membase + PIO_POW_MOD_CTL_REG); + reg = readl(pctl->membase + pctl->pow_mod_sel_offset + + PIO_POW_MOD_CTL_OFS); reg &= ~BIT(bank); - writel(reg | val, pctl->membase + PIO_POW_MOD_CTL_REG); + writel(reg | val, pctl->membase + pctl->pow_mod_sel_offset + + PIO_POW_MOD_CTL_OFS); raw_spin_unlock_irqrestore(&pctl->lock, flags); fallthrough; @@ -733,9 +753,10 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, val = uV <= 1800000 ? 1 : 0; raw_spin_lock_irqsave(&pctl->lock, flags); - reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG); + reg = readl(pctl->membase + pctl->pow_mod_sel_offset); reg &= ~(1 << bank); - writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG); + writel(reg | val << bank, + pctl->membase + pctl->pow_mod_sel_offset); raw_spin_unlock_irqrestore(&pctl->lock, flags); return 0; default: @@ -1472,9 +1493,9 @@ static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl, return 0; } -int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, - const struct sunxi_pinctrl_desc *desc, - unsigned long variant) +int sunxi_pinctrl_init_with_flags(struct platform_device *pdev, + const struct sunxi_pinctrl_desc *desc, + unsigned long flags) { struct device_node *node = pdev->dev.of_node; struct pinctrl_desc *pctrl_desc; @@ -1497,8 +1518,8 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, pctl->dev = &pdev->dev; pctl->desc = desc; - pctl->variant = variant; - if (pctl->variant >= PINCTRL_SUN20I_D1) { + pctl->variant = flags & SUNXI_PINCTRL_VARIANT_MASK; + if (flags & SUNXI_PINCTRL_NEW_REG_LAYOUT) { pctl->bank_mem_size = D1_BANK_MEM_SIZE; pctl->pull_regs_offset = D1_PULL_REGS_OFFSET; pctl->dlevel_field_width = D1_DLEVEL_FIELD_WIDTH; @@ -1507,6 +1528,10 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, pctl->pull_regs_offset = PULL_REGS_OFFSET; pctl->dlevel_field_width = DLEVEL_FIELD_WIDTH; } + if (flags & SUNXI_PINCTRL_ELEVEN_BANKS) + pctl->pow_mod_sel_offset = PIO_11B_POW_MOD_SEL_REG; + else + pctl->pow_mod_sel_offset = PIO_POW_MOD_SEL_REG; pctl->irq_array = devm_kcalloc(&pdev->dev, IRQ_PER_BANK * pctl->desc->irq_banks, @@ -1626,10 +1651,9 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, } } - pctl->domain = irq_domain_add_linear(node, - pctl->desc->irq_banks * IRQ_PER_BANK, - &sunxi_pinctrl_irq_domain_ops, - pctl); + pctl->domain = irq_domain_create_linear(of_fwnode_handle(node), + pctl->desc->irq_banks * IRQ_PER_BANK, + &sunxi_pinctrl_irq_domain_ops, pctl); if (!pctl->domain) { dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); ret = -ENOMEM; diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index a87a2f944d60..ad26e4de16a8 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -25,10 +25,15 @@ #define PG_BASE 192 #define PH_BASE 224 #define PI_BASE 256 +#define PJ_BASE 288 +#define PK_BASE 320 #define PL_BASE 352 #define PM_BASE 384 #define PN_BASE 416 +/* maximum number of banks per controller (PA -> PK) */ +#define SUNXI_PINCTRL_MAX_BANKS 11 + #define SUNXI_PINCTRL_PIN(bank, pin) \ PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin) @@ -82,21 +87,16 @@ #define SUN4I_FUNC_INPUT 0 #define SUN4I_FUNC_IRQ 6 -#define PINCTRL_SUN5I_A10S BIT(1) -#define PINCTRL_SUN5I_A13 BIT(2) -#define PINCTRL_SUN5I_GR8 BIT(3) -#define PINCTRL_SUN6I_A31 BIT(4) -#define PINCTRL_SUN6I_A31S BIT(5) -#define PINCTRL_SUN4I_A10 BIT(6) -#define PINCTRL_SUN7I_A20 BIT(7) -#define PINCTRL_SUN8I_R40 BIT(8) -#define PINCTRL_SUN8I_V3 BIT(9) -#define PINCTRL_SUN8I_V3S BIT(10) -/* Variants below here have an updated register layout. */ -#define PINCTRL_SUN20I_D1 BIT(11) - -#define PIO_POW_MOD_SEL_REG 0x340 -#define PIO_POW_MOD_CTL_REG 0x344 +#define SUNXI_PINCTRL_VARIANT_MASK GENMASK(7, 0) +#define SUNXI_PINCTRL_NEW_REG_LAYOUT BIT(8) +#define SUNXI_PINCTRL_PORTF_SWITCH BIT(9) +#define SUNXI_PINCTRL_ELEVEN_BANKS BIT(10) + +#define PIO_POW_MOD_SEL_REG 0x340 +#define PIO_11B_POW_MOD_SEL_REG 0x380 +#define PIO_POW_MOD_CTL_OFS 0x004 + +#define PIO_BANK_K_OFFSET 0x500 enum sunxi_desc_bias_voltage { BIAS_VOLTAGE_NONE, @@ -164,7 +164,7 @@ struct sunxi_pinctrl { struct gpio_chip *chip; const struct sunxi_pinctrl_desc *desc; struct device *dev; - struct sunxi_pinctrl_regulator regulators[9]; + struct sunxi_pinctrl_regulator regulators[11]; struct irq_domain *domain; struct sunxi_pinctrl_function *functions; unsigned nfunctions; @@ -178,6 +178,7 @@ struct sunxi_pinctrl { u32 bank_mem_size; u32 pull_regs_offset; u32 dlevel_field_width; + u32 pow_mod_sel_offset; }; #define SUNXI_PIN(_pin, ...) \ @@ -299,11 +300,17 @@ static inline u32 sunxi_grp_config_reg(u16 pin) return GRP_CFG_REG + bank * 0x4; } -int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, - const struct sunxi_pinctrl_desc *desc, - unsigned long variant); +int sunxi_pinctrl_init_with_flags(struct platform_device *pdev, + const struct sunxi_pinctrl_desc *desc, + unsigned long flags); #define sunxi_pinctrl_init(_dev, _desc) \ - sunxi_pinctrl_init_with_variant(_dev, _desc, 0) + sunxi_pinctrl_init_with_flags(_dev, _desc, 0) + +int sunxi_pinctrl_dt_table_init(struct platform_device *pdev, + const u8 *pins_per_bank, + const u8 *irq_bank_muxes, + struct sunxi_pinctrl_desc *desc, + unsigned long flags); #endif /* __PINCTRL_SUNXI_H */ diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 3b046450bd3f..11ecbd6a9b2a 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -96,6 +96,7 @@ static const struct cfg_param { {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING}, {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE}, + {"nvidia,gpio-mode", TEGRA_PINCONF_PARAM_GPIO_MODE}, }; static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, @@ -278,8 +279,8 @@ static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev, return 0; } -static const struct tegra_pingroup *tegra_pinctrl_get_group(struct pinctrl_dev *pctldev, - unsigned int offset) +static int tegra_pinctrl_get_group_index(struct pinctrl_dev *pctldev, + unsigned int offset) { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); unsigned int group, num_pins, j; @@ -292,12 +293,35 @@ static const struct tegra_pingroup *tegra_pinctrl_get_group(struct pinctrl_dev * continue; for (j = 0; j < num_pins; j++) { if (offset == pins[j]) - return &pmx->soc->groups[group]; + return group; } } - dev_err(pctldev->dev, "Pingroup not found for pin %u\n", offset); - return NULL; + return -EINVAL; +} + +static const struct tegra_pingroup *tegra_pinctrl_get_group(struct pinctrl_dev *pctldev, + unsigned int offset, + int group_index) +{ + struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + if (group_index < 0 || group_index >= pmx->soc->ngroups) + return NULL; + + return &pmx->soc->groups[group_index]; +} + +static struct tegra_pingroup_config *tegra_pinctrl_get_group_config(struct pinctrl_dev *pctldev, + unsigned int offset, + int group_index) +{ + struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + if (group_index < 0) + return NULL; + + return &pmx->pingroup_configs[group_index]; } static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, @@ -306,12 +330,15 @@ static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); const struct tegra_pingroup *group; + struct tegra_pingroup_config *config; + int group_index; u32 value; if (!pmx->soc->sfsel_in_mux) return 0; - group = tegra_pinctrl_get_group(pctldev, offset); + group_index = tegra_pinctrl_get_group_index(pctldev, offset); + group = tegra_pinctrl_get_group(pctldev, offset, group_index); if (!group) return -EINVAL; @@ -319,7 +346,11 @@ static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, if (group->mux_reg < 0 || group->sfsel_bit < 0) return -EINVAL; + config = tegra_pinctrl_get_group_config(pctldev, offset, group_index); + if (!config) + return -EINVAL; value = pmx_readl(pmx, group->mux_bank, group->mux_reg); + config->is_sfsel = (value & BIT(group->sfsel_bit)) != 0; value &= ~BIT(group->sfsel_bit); pmx_writel(pmx, value, group->mux_bank, group->mux_reg); @@ -332,12 +363,15 @@ static void tegra_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev, { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); const struct tegra_pingroup *group; + struct tegra_pingroup_config *config; + int group_index; u32 value; if (!pmx->soc->sfsel_in_mux) return; - group = tegra_pinctrl_get_group(pctldev, offset); + group_index = tegra_pinctrl_get_group_index(pctldev, offset); + group = tegra_pinctrl_get_group(pctldev, offset, group_index); if (!group) return; @@ -345,8 +379,12 @@ static void tegra_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev, if (group->mux_reg < 0 || group->sfsel_bit < 0) return; + config = tegra_pinctrl_get_group_config(pctldev, offset, group_index); + if (!config) + return; value = pmx_readl(pmx, group->mux_bank, group->mux_reg); - value |= BIT(group->sfsel_bit); + if (config->is_sfsel) + value |= BIT(group->sfsel_bit); pmx_writel(pmx, value, group->mux_bank, group->mux_reg); } @@ -471,6 +509,16 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, *bit = g->drvtype_bit; *width = 2; break; + case TEGRA_PINCONF_PARAM_GPIO_MODE: + if (pmx->soc->sfsel_in_mux) { + *bank = g->mux_bank; + *reg = g->mux_reg; + *bit = g->sfsel_bit; + *width = 1; + } else { + *reg = -EINVAL; + } + break; default: dev_err(pmx->dev, "Invalid config param %04x\n", param); return -ENOTSUPP; @@ -791,6 +839,12 @@ int tegra_pinctrl_probe(struct platform_device *pdev, pmx->dev = &pdev->dev; pmx->soc = soc_data; + pmx->pingroup_configs = devm_kcalloc(&pdev->dev, + pmx->soc->ngroups, sizeof(*pmx->pingroup_configs), + GFP_KERNEL); + if (!pmx->pingroup_configs) + return -ENOMEM; + /* * Each mux group will appear in 4 functions' list of groups. * This over-allocates slightly, since not all groups are mux groups. diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index b3289bdf727d..bc7b70913b89 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -8,6 +8,10 @@ #ifndef __PINMUX_TEGRA_H__ #define __PINMUX_TEGRA_H__ +struct tegra_pingroup_config { + bool is_sfsel; +}; + struct tegra_pmx { struct device *dev; struct pinctrl_dev *pctl; @@ -21,6 +25,8 @@ struct tegra_pmx { int nbanks; void __iomem **regs; u32 *backup_regs; + /* Array of size soc->ngroups */ + struct tegra_pingroup_config *pingroup_configs; }; enum tegra_pinconf_param { @@ -54,6 +60,8 @@ enum tegra_pinconf_param { TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, /* argument: Integer, range is HW-dependant */ TEGRA_PINCONF_PARAM_DRIVE_TYPE, + /* argument: Boolean */ + TEGRA_PINCONF_PARAM_GPIO_MODE, }; enum tegra_pinconf_pull { @@ -176,16 +184,22 @@ struct tegra_pingroup { /** * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration - * @ngpios: The number of GPIO pins the pin controller HW affects. - * @pins: An array describing all pins the pin controller affects. - * All pins which are also GPIOs must be listed first within the - * array, and be numbered identically to the GPIO controller's - * numbering. - * @npins: The numbmer of entries in @pins. - * @functions: An array describing all mux functions the SoC supports. - * @nfunctions: The numbmer of entries in @functions. - * @groups: An array describing all pin groups the pin SoC supports. - * @ngroups: The numbmer of entries in @groups. + * @ngpios: The number of GPIO pins the pin controller HW affects. + * @gpio_compatible: Device-tree GPIO compatible string. + * @pins: An array describing all pins the pin controller affects. + * All pins which are also GPIOs must be listed first within the + * array, and be numbered identically to the GPIO controller's + * numbering. + * @npins: The number of entries in @pins. + * @functions: An array describing all mux functions the SoC supports. + * @nfunctions: The number of entries in @functions. + * @groups: An array describing all pin groups the pin SoC supports. + * @ngroups: The number of entries in @groups. + * @hsm_in_mux: High-speed mode field. Only applicable to devices with one pin per group. + * @schmitt_in_mux: Schmitt trigger field. Only applicable to devices with one pin per group. + * @drvtype_in_mux: Drivetype field. Only applicable to devices with one pin per group. + * @sfsel_in_mux: Special function selection field. + * Only applicable to devices with one pin per group. */ struct tegra_pinctrl_soc_data { unsigned ngpios; diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index b71c07d84662..5e3de0df756b 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -3,7 +3,7 @@ menuconfig PINCTRL_UNIPHIER bool "UniPhier SoC pinctrl drivers" depends on ARCH_UNIPHIER || COMPILE_TEST depends on OF && MFD_SYSCON - default y + default ARCH_UNIPHIER select PINMUX select GENERIC_PINCONF |