diff options
Diffstat (limited to 'drivers/pinctrl/sh-pfc/pfc-r8a7794.c')
| -rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 1035 |
1 files changed, 600 insertions, 435 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c index 5248685dbb4e..086f6798b129 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -11,7 +11,6 @@ */ #include <linux/kernel.h> -#include <linux/platform_data/gpio-rcar.h> #include "core.h" #include "sh_pfc.h" @@ -644,10 +643,10 @@ static const u16 pinmux_data[] = { /* IPSR0 */ PINMUX_IPSR_DATA(IP0_0, SD1_CD), - PINMUX_IPSR_MODSEL_DATA(IP0_0, CAN0_RX, SEL_CAN0_0), + PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0), PINMUX_IPSR_DATA(IP0_9_8, SD1_WP), PINMUX_IPSR_DATA(IP0_9_8, IRQ7), - PINMUX_IPSR_MODSEL_DATA(IP0_9_8, CAN0_TX, SEL_CAN0_0), + PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0), PINMUX_IPSR_DATA(IP0_10, MMC_CLK), PINMUX_IPSR_DATA(IP0_10, SD2_CLK), PINMUX_IPSR_DATA(IP0_11, MMC_CMD), @@ -665,68 +664,68 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP0_17, MMC_D5), PINMUX_IPSR_DATA(IP0_17, SD2_WP), PINMUX_IPSR_DATA(IP0_19_18, MMC_D6), - PINMUX_IPSR_MODSEL_DATA(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1), - PINMUX_IPSR_MODSEL_DATA(IP0_19_18, CAN1_RX, SEL_CAN1_0), + PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1), + PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0), PINMUX_IPSR_DATA(IP0_21_20, MMC_D7), - PINMUX_IPSR_MODSEL_DATA(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1), - PINMUX_IPSR_MODSEL_DATA(IP0_21_20, CAN1_TX, SEL_CAN1_0), + PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1), + PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0), PINMUX_IPSR_DATA(IP0_23_22, D0), - PINMUX_IPSR_MODSEL_DATA(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1), + PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1), PINMUX_IPSR_DATA(IP0_23_22, IRQ4), PINMUX_IPSR_DATA(IP0_24, D1), - PINMUX_IPSR_MODSEL_DATA(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1), PINMUX_IPSR_DATA(IP0_25, D2), - PINMUX_IPSR_MODSEL_DATA(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1), PINMUX_IPSR_DATA(IP0_27_26, D3), - PINMUX_IPSR_MODSEL_DATA(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1), - PINMUX_IPSR_MODSEL_DATA(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1), + PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1), + PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1), PINMUX_IPSR_DATA(IP0_29_28, D4), - PINMUX_IPSR_MODSEL_DATA(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1), - PINMUX_IPSR_MODSEL_DATA(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1), + PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1), + PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1), PINMUX_IPSR_DATA(IP0_31_30, D5), - PINMUX_IPSR_MODSEL_DATA(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1), - PINMUX_IPSR_MODSEL_DATA(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3), + PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1), + PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3), /* IPSR1 */ PINMUX_IPSR_DATA(IP1_1_0, D6), - PINMUX_IPSR_MODSEL_DATA(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1), - PINMUX_IPSR_MODSEL_DATA(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3), + PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1), + PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3), PINMUX_IPSR_DATA(IP1_3_2, D7), PINMUX_IPSR_DATA(IP1_3_2, IRQ3), - PINMUX_IPSR_MODSEL_DATA(IP1_3_2, TCLK1, SEL_TMU_0), + PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0), PINMUX_IPSR_DATA(IP1_3_2, PWM6_B), PINMUX_IPSR_DATA(IP1_5_4, D8), PINMUX_IPSR_DATA(IP1_5_4, HSCIF2_HRX), - PINMUX_IPSR_MODSEL_DATA(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1), + PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1), PINMUX_IPSR_DATA(IP1_7_6, D9), PINMUX_IPSR_DATA(IP1_7_6, HSCIF2_HTX), - PINMUX_IPSR_MODSEL_DATA(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1), + PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1), PINMUX_IPSR_DATA(IP1_10_8, D10), PINMUX_IPSR_DATA(IP1_10_8, HSCIF2_HSCK), - PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2), PINMUX_IPSR_DATA(IP1_10_8, IRQ6), PINMUX_IPSR_DATA(IP1_10_8, PWM5_C), PINMUX_IPSR_DATA(IP1_12_11, D11), PINMUX_IPSR_DATA(IP1_12_11, HSCIF2_HCTS_N), - PINMUX_IPSR_MODSEL_DATA(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3), + PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3), PINMUX_IPSR_DATA(IP1_14_13, D12), PINMUX_IPSR_DATA(IP1_14_13, HSCIF2_HRTS_N), - PINMUX_IPSR_MODSEL_DATA(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2), - PINMUX_IPSR_MODSEL_DATA(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3), + PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2), + PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3), PINMUX_IPSR_DATA(IP1_17_15, D13), - PINMUX_IPSR_MODSEL_DATA(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0), + PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0), PINMUX_IPSR_DATA(IP1_17_15, TANS1), PINMUX_IPSR_DATA(IP1_17_15, PWM2_C), - PINMUX_IPSR_MODSEL_DATA(IP1_17_15, TCLK2_B, SEL_TMU_1), + PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1), PINMUX_IPSR_DATA(IP1_19_18, D14), - PINMUX_IPSR_MODSEL_DATA(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0), - PINMUX_IPSR_MODSEL_DATA(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1), + PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0), + PINMUX_IPSR_MSEL(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1), PINMUX_IPSR_DATA(IP1_21_20, D15), - PINMUX_IPSR_MODSEL_DATA(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0), - PINMUX_IPSR_MODSEL_DATA(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1), + PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0), + PINMUX_IPSR_MSEL(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1), PINMUX_IPSR_DATA(IP1_23_22, A0), PINMUX_IPSR_DATA(IP1_23_22, SCIFB1_SCK), PINMUX_IPSR_DATA(IP1_23_22, PWM3_B), @@ -742,58 +741,58 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP1_29_28, TPUTO3_C), PINMUX_IPSR_DATA(IP1_31_30, A6), PINMUX_IPSR_DATA(IP1_31_30, SCIFB0_CTS_N), - PINMUX_IPSR_MODSEL_DATA(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1), PINMUX_IPSR_DATA(IP1_31_30, TPUTO2_C), /* IPSR2 */ PINMUX_IPSR_DATA(IP2_1_0, A7), PINMUX_IPSR_DATA(IP2_1_0, SCIFB0_RTS_N), - PINMUX_IPSR_MODSEL_DATA(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1), PINMUX_IPSR_DATA(IP2_3_2, A8), - PINMUX_IPSR_MODSEL_DATA(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1), + PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0), + PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1), PINMUX_IPSR_DATA(IP2_5_4, A9), - PINMUX_IPSR_MODSEL_DATA(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1), + PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0), + PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1), PINMUX_IPSR_DATA(IP2_7_6, A10), - PINMUX_IPSR_MODSEL_DATA(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1), + PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0), + PINMUX_IPSR_MSEL(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1), PINMUX_IPSR_DATA(IP2_9_8, A11), - PINMUX_IPSR_MODSEL_DATA(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1), + PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0), + PINMUX_IPSR_MSEL(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1), PINMUX_IPSR_DATA(IP2_11_10, A12), - PINMUX_IPSR_MODSEL_DATA(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1), + PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0), + PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1), PINMUX_IPSR_DATA(IP2_13_12, A13), - PINMUX_IPSR_MODSEL_DATA(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1), + PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0), + PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1), PINMUX_IPSR_DATA(IP2_15_14, A14), - PINMUX_IPSR_MODSEL_DATA(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0), - PINMUX_IPSR_MODSEL_DATA(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP2_15_14, DREQ1_N, SEL_LBS_0), + PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0), + PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0), PINMUX_IPSR_DATA(IP2_17_16, A15), - PINMUX_IPSR_MODSEL_DATA(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0), - PINMUX_IPSR_MODSEL_DATA(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP2_17_16, DACK1, SEL_LBS_0), + PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0), + PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0), PINMUX_IPSR_DATA(IP2_20_18, A16), - PINMUX_IPSR_MODSEL_DATA(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0), - PINMUX_IPSR_MODSEL_DATA(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP2_20_18, SPEEDIN, SEL_RSP_0), - PINMUX_IPSR_MODSEL_DATA(IP2_20_18, VSP, SEL_SPDM_0), - PINMUX_IPSR_MODSEL_DATA(IP2_20_18, CAN_CLK_C, SEL_CAN_2), + PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0), + PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1), + PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0), + PINMUX_IPSR_MSEL(IP2_20_18, VSP, SEL_SPDM_0), + PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2), PINMUX_IPSR_DATA(IP2_20_18, TPUTO2_B), PINMUX_IPSR_DATA(IP2_23_21, A17), - PINMUX_IPSR_MODSEL_DATA(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0), - PINMUX_IPSR_MODSEL_DATA(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4), - PINMUX_IPSR_MODSEL_DATA(IP2_23_21, CAN1_RX_B, SEL_CAN1_1), - PINMUX_IPSR_MODSEL_DATA(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1), + PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0), + PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4), + PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1), + PINMUX_IPSR_MSEL(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1), PINMUX_IPSR_DATA(IP2_26_24, A18), - PINMUX_IPSR_MODSEL_DATA(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0), - PINMUX_IPSR_MODSEL_DATA(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4), - PINMUX_IPSR_MODSEL_DATA(IP2_26_24, CAN1_TX_B, SEL_CAN1_1), - PINMUX_IPSR_MODSEL_DATA(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1), + PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0), + PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4), + PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1), + PINMUX_IPSR_MSEL(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1), PINMUX_IPSR_DATA(IP2_29_27, A19), - PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0), + PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0), PINMUX_IPSR_DATA(IP2_29_27, PWM4), PINMUX_IPSR_DATA(IP2_29_27, TPUTO2), PINMUX_IPSR_DATA(IP2_29_27, MOUT0), @@ -831,42 +830,42 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP3_14_13, VI1_DATA11), PINMUX_IPSR_DATA(IP3_17_15, EX_CS2_N), PINMUX_IPSR_DATA(IP3_17_15, PWM0), - PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2), - PINMUX_IPSR_MODSEL_DATA(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP3_17_15, RIF0_SYNC, SEL_DR0_0), + PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP3_17_15, RIF0_SYNC, SEL_DR0_0), PINMUX_IPSR_DATA(IP3_17_15, TPUTO3), PINMUX_IPSR_DATA(IP3_17_15, SCIFB2_TXD), - PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SDATA_B, SEL_FSN_1), + PINMUX_IPSR_MSEL(IP3_17_15, SDATA_B, SEL_FSN_1), PINMUX_IPSR_DATA(IP3_20_18, EX_CS3_N), - PINMUX_IPSR_MODSEL_DATA(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0), - PINMUX_IPSR_MODSEL_DATA(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2), - PINMUX_IPSR_MODSEL_DATA(IP3_20_18, TS_SCK_B, SEL_TSIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP3_20_18, RIF0_CLK, SEL_DR0_0), - PINMUX_IPSR_MODSEL_DATA(IP3_20_18, BPFCLK, SEL_DARC_0), + PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0), + PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP3_20_18, RIF0_CLK, SEL_DR0_0), + PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0), PINMUX_IPSR_DATA(IP3_20_18, SCIFB2_SCK), - PINMUX_IPSR_MODSEL_DATA(IP3_20_18, MDATA_B, SEL_FSN_1), + PINMUX_IPSR_MSEL(IP3_20_18, MDATA_B, SEL_FSN_1), PINMUX_IPSR_DATA(IP3_23_21, EX_CS4_N), - PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0), - PINMUX_IPSR_MODSEL_DATA(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4), - PINMUX_IPSR_MODSEL_DATA(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP3_23_21, RIF0_D0, SEL_DR0_0), - PINMUX_IPSR_MODSEL_DATA(IP3_23_21, FMCLK, SEL_DARC_0), + PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0), + PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4), + PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP3_23_21, RIF0_D0, SEL_DR0_0), + PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0), PINMUX_IPSR_DATA(IP3_23_21, SCIFB2_CTS_N), - PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SCKZ_B, SEL_FSN_1), + PINMUX_IPSR_MSEL(IP3_23_21, SCKZ_B, SEL_FSN_1), PINMUX_IPSR_DATA(IP3_26_24, EX_CS5_N), - PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0), - PINMUX_IPSR_MODSEL_DATA(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4), - PINMUX_IPSR_MODSEL_DATA(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RIF0_D1, SEL_DR1_0), - PINMUX_IPSR_MODSEL_DATA(IP3_26_24, FMIN, SEL_DARC_0), + PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0), + PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4), + PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP3_26_24, RIF0_D1, SEL_DR1_0), + PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0), PINMUX_IPSR_DATA(IP3_26_24, SCIFB2_RTS_N), - PINMUX_IPSR_MODSEL_DATA(IP3_26_24, STM_N_B, SEL_FSN_1), + PINMUX_IPSR_MSEL(IP3_26_24, STM_N_B, SEL_FSN_1), PINMUX_IPSR_DATA(IP3_29_27, BS_N), PINMUX_IPSR_DATA(IP3_29_27, DRACK0), PINMUX_IPSR_DATA(IP3_29_27, PWM1_C), PINMUX_IPSR_DATA(IP3_29_27, TPUTO0_C), PINMUX_IPSR_DATA(IP3_29_27, ATACS01_N), - PINMUX_IPSR_MODSEL_DATA(IP3_29_27, MTS_N_B, SEL_FSN_1), + PINMUX_IPSR_MSEL(IP3_29_27, MTS_N_B, SEL_FSN_1), PINMUX_IPSR_DATA(IP3_30, RD_N), PINMUX_IPSR_DATA(IP3_30, ATACS11_N), PINMUX_IPSR_DATA(IP3_31, RD_WR_N), @@ -874,18 +873,18 @@ static const u16 pinmux_data[] = { /* IPSR4 */ PINMUX_IPSR_DATA(IP4_1_0, EX_WAIT0), - PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_B, SEL_CAN_1), - PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCIF_CLK, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1), + PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0), PINMUX_IPSR_DATA(IP4_1_0, PWMFSW0), PINMUX_IPSR_DATA(IP4_4_2, DU0_DR0), PINMUX_IPSR_DATA(IP4_4_2, LCDOUT16), - PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2), - PINMUX_IPSR_MODSEL_DATA(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3), + PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2), + PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3), PINMUX_IPSR_DATA(IP4_4_2, CC50_STATE0), PINMUX_IPSR_DATA(IP4_7_5, DU0_DR1), PINMUX_IPSR_DATA(IP4_7_5, LCDOUT17), - PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2), - PINMUX_IPSR_MODSEL_DATA(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3), + PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2), + PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3), PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE1), PINMUX_IPSR_DATA(IP4_9_8, DU0_DR2), PINMUX_IPSR_DATA(IP4_9_8, LCDOUT18), @@ -907,13 +906,13 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP4_19_18, CC50_STATE7), PINMUX_IPSR_DATA(IP4_22_20, DU0_DG0), PINMUX_IPSR_DATA(IP4_22_20, LCDOUT8), - PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2), - PINMUX_IPSR_MODSEL_DATA(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3), + PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2), + PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3), PINMUX_IPSR_DATA(IP4_22_20, CC50_STATE8), PINMUX_IPSR_DATA(IP4_25_23, DU0_DG1), PINMUX_IPSR_DATA(IP4_25_23, LCDOUT9), - PINMUX_IPSR_MODSEL_DATA(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2), - PINMUX_IPSR_MODSEL_DATA(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3), + PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2), + PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3), PINMUX_IPSR_DATA(IP4_25_23, CC50_STATE9), PINMUX_IPSR_DATA(IP4_27_26, DU0_DG2), PINMUX_IPSR_DATA(IP4_27_26, LCDOUT10), @@ -937,15 +936,15 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP5_5_4, CC50_STATE15), PINMUX_IPSR_DATA(IP5_8_6, DU0_DB0), PINMUX_IPSR_DATA(IP5_8_6, LCDOUT0), - PINMUX_IPSR_MODSEL_DATA(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2), - PINMUX_IPSR_MODSEL_DATA(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_RX_C, SEL_CAN0_2), + PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2), + PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3), + PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2), PINMUX_IPSR_DATA(IP5_8_6, CC50_STATE16), PINMUX_IPSR_DATA(IP5_11_9, DU0_DB1), PINMUX_IPSR_DATA(IP5_11_9, LCDOUT1), - PINMUX_IPSR_MODSEL_DATA(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), - PINMUX_IPSR_MODSEL_DATA(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3), - PINMUX_IPSR_MODSEL_DATA(IP5_11_9, CAN0_TX_C, SEL_CAN0_2), + PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), + PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3), + PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2), PINMUX_IPSR_DATA(IP5_11_9, CC50_STATE17), PINMUX_IPSR_DATA(IP5_13_12, DU0_DB2), PINMUX_IPSR_DATA(IP5_13_12, LCDOUT2), @@ -1010,501 +1009,501 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7), PINMUX_IPSR_DATA(IP6_16, AVB_RXD6), PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB), - PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C3_SCL, SEL_I2C03_0), - PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2), - PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IETX_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0), + PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2), PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7), PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD), - PINMUX_IPSR_MODSEL_DATA(IP6_22_20, I2C3_SDA, SEL_I2C03_0), - PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2), - PINMUX_IPSR_MODSEL_DATA(IP6_22_20, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0), + PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2), PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER), PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N), - PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2), - PINMUX_IPSR_MODSEL_DATA(IP6_25_23, IERX_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2), + PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2), PINMUX_IPSR_DATA(IP6_25_23, AVB_COL), PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N), - PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1), - PINMUX_IPSR_MODSEL_DATA(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2), - PINMUX_IPSR_MODSEL_DATA(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1), + PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2), + PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1), PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN), - PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ETH_MDIO, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0), PINMUX_IPSR_DATA(IP6_31_29, VI0_G0), - PINMUX_IPSR_MODSEL_DATA(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1), - PINMUX_IPSR_MODSEL_DATA(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3), + PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1), + PINMUX_IPSR_MSEL(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3), PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK), - PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ADIDATA, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP6_31_29, AD_DI, SEL_ADI_0), + PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP6_31_29, AD_DI, SEL_ADI_0), /* IPSR7 */ - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ETH_CRS_DV, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_2_0, VI0_G1), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3), + PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1), + PINMUX_IPSR_MSEL(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3), PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ADICS_SAMP, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP7_2_0, AD_DO, SEL_ADI_0), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ETH_RX_ER, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP7_2_0, AD_DO, SEL_ADI_0), + PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_5_3, VI0_G2), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1), + PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1), PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ADICLK, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP7_5_3, AD_CLK, SEL_ADI_0), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ETH_RXD0, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP7_5_3, AD_CLK, SEL_ADI_0), + PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_8_6, VI0_G3), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_TX_B, SEL_CAN0_1), + PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1), + PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1), PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ADICHS0, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP7_8_6, AD_NCS_N, SEL_ADI_0), - PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ETH_RXD1, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP7_8_6, AD_NCS_N, SEL_ADI_0), + PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_11_9, VI0_G4), - PINMUX_IPSR_MODSEL_DATA(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1), - PINMUX_IPSR_MODSEL_DATA(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3), + PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1), + PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3), PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3), - PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ADICHS1, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ETH_LINK, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_14_12, VI0_G5), - PINMUX_IPSR_MODSEL_DATA(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1), - PINMUX_IPSR_MODSEL_DATA(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3), + PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1), + PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3), PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4), - PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ADICHS2, SEL_RAD_0), - PINMUX_IPSR_MODSEL_DATA(IP7_17_15, ETH_REFCLK, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_17_15, VI0_G6), - PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2), + PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2), PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5), - PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1), - PINMUX_IPSR_MODSEL_DATA(IP7_20_18, ETH_TXD1, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1), + PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_20_18, VI0_G7), - PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3), + PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2), + PINMUX_IPSR_MSEL(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3), PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6), - PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SSI_WS5_B, SEL_SSI5_1), - PINMUX_IPSR_MODSEL_DATA(IP7_23_21, ETH_TX_EN, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1), + PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_23_21, VI0_R0), - PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2), - PINMUX_IPSR_MODSEL_DATA(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3), + PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2), + PINMUX_IPSR_MSEL(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3), PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7), - PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1), - PINMUX_IPSR_MODSEL_DATA(IP7_26_24, ETH_MAGIC, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1), + PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_26_24, VI0_R1), - PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1), PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER), - PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1), - PINMUX_IPSR_MODSEL_DATA(IP7_29_27, ETH_TXD0, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1), + PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0), PINMUX_IPSR_DATA(IP7_29_27, VI0_R2), - PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1), - PINMUX_IPSR_MODSEL_DATA(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4), + PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4), PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK), - PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_WS6_B, SEL_SSI6_1), + PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1), PINMUX_IPSR_DATA(IP7_31, DREQ0_N), PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD), /* IPSR8 */ - PINMUX_IPSR_MODSEL_DATA(IP8_2_0, ETH_MDC, SEL_ETH_0), + PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0), PINMUX_IPSR_DATA(IP8_2_0, VI0_R3), - PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1), - PINMUX_IPSR_MODSEL_DATA(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4), + PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4), PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC), - PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1), - PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1), + PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0), PINMUX_IPSR_DATA(IP8_5_3, VI0_R4), - PINMUX_IPSR_MODSEL_DATA(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2), - PINMUX_IPSR_MODSEL_DATA(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1), + PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2), + PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1), PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO), - PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1), - PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1), + PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0), PINMUX_IPSR_DATA(IP8_8_6, VI0_R5), - PINMUX_IPSR_MODSEL_DATA(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2), - PINMUX_IPSR_MODSEL_DATA(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1), + PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2), + PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1), PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK), - PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_WS78_B, SEL_SSI7_1), + PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1), PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N), PINMUX_IPSR_DATA(IP8_11_9, VI0_R6), - PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4), + PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3), + PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4), PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC), - PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1), + PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1), PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N), PINMUX_IPSR_DATA(IP8_14_12, VI0_R7), - PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4), + PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3), + PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4), PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT), - PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1), - PINMUX_IPSR_MODSEL_DATA(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0), - PINMUX_IPSR_MODSEL_DATA(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1), + PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1), PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS), - PINMUX_IPSR_MODSEL_DATA(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1), - PINMUX_IPSR_MODSEL_DATA(IP8_19_17, I2C0_SCL, SEL_I2C00_0), - PINMUX_IPSR_MODSEL_DATA(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2), + PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1), + PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0), + PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2), PINMUX_IPSR_DATA(IP8_19_17, PWM5), - PINMUX_IPSR_MODSEL_DATA(IP8_19_17, TCLK1_B, SEL_TMU_1), + PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1), PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK), - PINMUX_IPSR_MODSEL_DATA(IP8_19_17, CAN1_RX_D, SEL_CAN1_3), + PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3), PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B), - PINMUX_IPSR_MODSEL_DATA(IP8_22_20, I2C0_SDA, SEL_I2C00_0), - PINMUX_IPSR_MODSEL_DATA(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2), + PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0), + PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2), PINMUX_IPSR_DATA(IP8_22_20, TPUTO0), - PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN_CLK, SEL_CAN_0), + PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0), PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE), - PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN1_TX_D, SEL_CAN1_3), - PINMUX_IPSR_MODSEL_DATA(IP8_25_23, I2C1_SCL, SEL_I2C01_0), - PINMUX_IPSR_MODSEL_DATA(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3), + PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0), + PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0), PINMUX_IPSR_DATA(IP8_25_23, PWM5_B), PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0), - PINMUX_IPSR_MODSEL_DATA(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1), + PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B), - PINMUX_IPSR_MODSEL_DATA(IP8_28_26, I2C1_SDA, SEL_I2C01_0), - PINMUX_IPSR_MODSEL_DATA(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0), + PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0), PINMUX_IPSR_DATA(IP8_28_26, IRQ5), PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1), - PINMUX_IPSR_MODSEL_DATA(IP8_28_26, RIF1_CLK_B, SEL_DR2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP8_28_26, BPFCLK_C, SEL_DARC_2), + PINMUX_IPSR_MSEL(IP8_28_26, RIF1_CLK_B, SEL_DR2_1), + PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2), PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD), - PINMUX_IPSR_MODSEL_DATA(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0), - PINMUX_IPSR_MODSEL_DATA(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2), + PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2), PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2), - PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RIF1_D0_B, SEL_DR2_1), - PINMUX_IPSR_MODSEL_DATA(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP8_31_29, FMCLK_C, SEL_DARC_2), - PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RDS_CLK, SEL_RDS_0), + PINMUX_IPSR_MSEL(IP8_31_29, RIF1_D0_B, SEL_DR2_1), + PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2), + PINMUX_IPSR_MSEL(IP8_31_29, RDS_CLK, SEL_RDS_0), /* IPSR9 */ PINMUX_IPSR_DATA(IP9_2_0, MSIOF0_TXD), - PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0), - PINMUX_IPSR_MODSEL_DATA(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2), + PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2), PINMUX_IPSR_DATA(IP9_2_0, DU1_DR3), - PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RIF1_D1_B, SEL_DR3_1), - PINMUX_IPSR_MODSEL_DATA(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3), - PINMUX_IPSR_MODSEL_DATA(IP9_2_0, FMIN_C, SEL_DARC_2), - PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RDS_DATA, SEL_RDS_0), + PINMUX_IPSR_MSEL(IP9_2_0, RIF1_D1_B, SEL_DR3_1), + PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2), + PINMUX_IPSR_MSEL(IP9_2_0, RDS_DATA, SEL_RDS_0), PINMUX_IPSR_DATA(IP9_5_3, MSIOF0_SCK), PINMUX_IPSR_DATA(IP9_5_3, IRQ0), - PINMUX_IPSR_MODSEL_DATA(IP9_5_3, TS_SDATA, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0), PINMUX_IPSR_DATA(IP9_5_3, DU1_DR4), - PINMUX_IPSR_MODSEL_DATA(IP9_5_3, RIF1_SYNC, SEL_DR2_0), + PINMUX_IPSR_MSEL(IP9_5_3, RIF1_SYNC, SEL_DR2_0), PINMUX_IPSR_DATA(IP9_5_3, TPUTO1_C), PINMUX_IPSR_DATA(IP9_8_6, MSIOF0_SYNC), PINMUX_IPSR_DATA(IP9_8_6, PWM1), - PINMUX_IPSR_MODSEL_DATA(IP9_8_6, TS_SCK, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0), PINMUX_IPSR_DATA(IP9_8_6, DU1_DR5), - PINMUX_IPSR_MODSEL_DATA(IP9_8_6, RIF1_CLK, SEL_DR2_0), - PINMUX_IPSR_MODSEL_DATA(IP9_8_6, BPFCLK_B, SEL_DARC_1), + PINMUX_IPSR_MSEL(IP9_8_6, RIF1_CLK, SEL_DR2_0), + PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1), PINMUX_IPSR_DATA(IP9_11_9, MSIOF0_SS1), - PINMUX_IPSR_MODSEL_DATA(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0), - PINMUX_IPSR_MODSEL_DATA(IP9_11_9, TS_SDEN, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0), + PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0), PINMUX_IPSR_DATA(IP9_11_9, DU1_DR6), - PINMUX_IPSR_MODSEL_DATA(IP9_11_9, RIF1_D0, SEL_DR2_0), - PINMUX_IPSR_MODSEL_DATA(IP9_11_9, FMCLK_B, SEL_DARC_1), - PINMUX_IPSR_MODSEL_DATA(IP9_11_9, RDS_CLK_B, SEL_RDS_1), + PINMUX_IPSR_MSEL(IP9_11_9, RIF1_D0, SEL_DR2_0), + PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1), + PINMUX_IPSR_MSEL(IP9_11_9, RDS_CLK_B, SEL_RDS_1), PINMUX_IPSR_DATA(IP9_14_12, MSIOF0_SS2), - PINMUX_IPSR_MODSEL_DATA(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0), - PINMUX_IPSR_MODSEL_DATA(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0), + PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0), PINMUX_IPSR_DATA(IP9_14_12, DU1_DR7), - PINMUX_IPSR_MODSEL_DATA(IP9_14_12, RIF1_D1, SEL_DR3_0), - PINMUX_IPSR_MODSEL_DATA(IP9_14_12, FMIN_B, SEL_DARC_1), - PINMUX_IPSR_MODSEL_DATA(IP9_14_12, RDS_DATA_B, SEL_RDS_1), - PINMUX_IPSR_MODSEL_DATA(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_16_15, I2C4_SCL, SEL_I2C04_0), + PINMUX_IPSR_MSEL(IP9_14_12, RIF1_D1, SEL_DR3_0), + PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1), + PINMUX_IPSR_MSEL(IP9_14_12, RDS_DATA_B, SEL_RDS_1), + PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0), PINMUX_IPSR_DATA(IP9_16_15, PWM6), PINMUX_IPSR_DATA(IP9_16_15, DU1_DG0), - PINMUX_IPSR_MODSEL_DATA(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_18_17, I2C4_SDA, SEL_I2C04_0), + PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0), PINMUX_IPSR_DATA(IP9_18_17, TPUTO1), PINMUX_IPSR_DATA(IP9_18_17, DU1_DG1), PINMUX_IPSR_DATA(IP9_21_19, HSCIF1_HSCK), PINMUX_IPSR_DATA(IP9_21_19, PWM2), - PINMUX_IPSR_MODSEL_DATA(IP9_21_19, IETX, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0), PINMUX_IPSR_DATA(IP9_21_19, DU1_DG2), - PINMUX_IPSR_MODSEL_DATA(IP9_21_19, REMOCON_B, SEL_RCN_1), - PINMUX_IPSR_MODSEL_DATA(IP9_21_19, SPEEDIN_B, SEL_RSP_1), - PINMUX_IPSR_MODSEL_DATA(IP9_21_19, VSP_B, SEL_SPDM_1), - PINMUX_IPSR_MODSEL_DATA(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0), - PINMUX_IPSR_MODSEL_DATA(IP9_24_22, IECLK, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1), + PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1), + PINMUX_IPSR_MSEL(IP9_21_19, VSP_B, SEL_SPDM_1), + PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0), + PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0), PINMUX_IPSR_DATA(IP9_24_22, DU1_DG3), - PINMUX_IPSR_MODSEL_DATA(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1), + PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1), PINMUX_IPSR_DATA(IP9_24_22, CAN_DEBUG_HW_TRIGGER), PINMUX_IPSR_DATA(IP9_24_22, CC50_STATE32), - PINMUX_IPSR_MODSEL_DATA(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0), - PINMUX_IPSR_MODSEL_DATA(IP9_27_25, IERX, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0), + PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0), PINMUX_IPSR_DATA(IP9_27_25, DU1_DG4), - PINMUX_IPSR_MODSEL_DATA(IP9_27_25, SSI_WS1_B, SEL_SSI1_1), + PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1), PINMUX_IPSR_DATA(IP9_27_25, CAN_STEP0), PINMUX_IPSR_DATA(IP9_27_25, CC50_STATE33), - PINMUX_IPSR_MODSEL_DATA(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0), PINMUX_IPSR_DATA(IP9_30_28, PWM3), - PINMUX_IPSR_MODSEL_DATA(IP9_30_28, TCLK2, SEL_TMU_0), + PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0), PINMUX_IPSR_DATA(IP9_30_28, DU1_DG5), - PINMUX_IPSR_MODSEL_DATA(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1), + PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1), PINMUX_IPSR_DATA(IP9_30_28, CAN_TXCLK), PINMUX_IPSR_DATA(IP9_30_28, CC50_STATE34), /* IPSR10 */ - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, IIC0_SCL, SEL_IIC00_0), + PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP10_2_0, IIC0_SCL, SEL_IIC00_0), PINMUX_IPSR_DATA(IP10_2_0, DU1_DG6), - PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1), + PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1), PINMUX_IPSR_DATA(IP10_2_0, CAN_DEBUGOUT0), PINMUX_IPSR_DATA(IP10_2_0, CC50_STATE35), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, IIC0_SDA, SEL_IIC00_0), + PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP10_5_3, IIC0_SDA, SEL_IIC00_0), PINMUX_IPSR_DATA(IP10_5_3, DU1_DG7), - PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_WS2_B, SEL_SSI2_1), + PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1), PINMUX_IPSR_DATA(IP10_5_3, CAN_DEBUGOUT1), PINMUX_IPSR_DATA(IP10_5_3, CC50_STATE36), - PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IIC1_SCL, SEL_IIC01_0), + PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP10_8_6, IIC1_SCL, SEL_IIC01_0), PINMUX_IPSR_DATA(IP10_8_6, DU1_DB0), - PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1), + PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1), PINMUX_IPSR_DATA(IP10_8_6, USB0_EXTLP), PINMUX_IPSR_DATA(IP10_8_6, CAN_DEBUGOUT2), PINMUX_IPSR_DATA(IP10_8_6, CC50_STATE37), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IIC1_SDA, SEL_IIC01_0), + PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP10_11_9, IIC1_SDA, SEL_IIC01_0), PINMUX_IPSR_DATA(IP10_11_9, DU1_DB1), - PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1), + PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1), PINMUX_IPSR_DATA(IP10_11_9, USB0_OVC1), PINMUX_IPSR_DATA(IP10_11_9, CAN_DEBUGOUT3), PINMUX_IPSR_DATA(IP10_11_9, CC50_STATE38), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0), PINMUX_IPSR_DATA(IP10_14_12, IRQ1), PINMUX_IPSR_DATA(IP10_14_12, DU1_DB2), - PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SSI_WS9_B, SEL_SSI9_1), + PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1), PINMUX_IPSR_DATA(IP10_14_12, USB0_IDIN), PINMUX_IPSR_DATA(IP10_14_12, CAN_DEBUGOUT4), PINMUX_IPSR_DATA(IP10_14_12, CC50_STATE39), - PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0), PINMUX_IPSR_DATA(IP10_17_15, IRQ2), - PINMUX_IPSR_MODSEL_DATA(IP10_17_15, BPFCLK_D, SEL_DARC_3), + PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3), PINMUX_IPSR_DATA(IP10_17_15, DU1_DB3), - PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1), + PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1), PINMUX_IPSR_DATA(IP10_17_15, TANS2), PINMUX_IPSR_DATA(IP10_17_15, CAN_DEBUGOUT5), PINMUX_IPSR_DATA(IP10_17_15, CC50_OSCOUT), - PINMUX_IPSR_MODSEL_DATA(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0), - PINMUX_IPSR_MODSEL_DATA(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4), - PINMUX_IPSR_MODSEL_DATA(IP10_20_18, FMCLK_D, SEL_DARC_3), + PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4), + PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3), PINMUX_IPSR_DATA(IP10_20_18, DU1_DB4), - PINMUX_IPSR_MODSEL_DATA(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2), - PINMUX_IPSR_MODSEL_DATA(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1), + PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2), + PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1), PINMUX_IPSR_DATA(IP10_20_18, CAN_DEBUGOUT6), - PINMUX_IPSR_MODSEL_DATA(IP10_20_18, RDS_CLK_C, SEL_RDS_2), - PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0), - PINMUX_IPSR_MODSEL_DATA(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4), - PINMUX_IPSR_MODSEL_DATA(IP10_23_21, FMIN_D, SEL_DARC_3), + PINMUX_IPSR_MSEL(IP10_20_18, RDS_CLK_C, SEL_RDS_2), + PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4), + PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3), PINMUX_IPSR_DATA(IP10_23_21, DU1_DB5), - PINMUX_IPSR_MODSEL_DATA(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2), - PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SSI_WS4_B, SEL_SSI4_1), + PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2), + PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1), PINMUX_IPSR_DATA(IP10_23_21, CAN_DEBUGOUT7), - PINMUX_IPSR_MODSEL_DATA(IP10_23_21, RDS_DATA_C, SEL_RDS_2), - PINMUX_IPSR_MODSEL_DATA(IP10_26_24, I2C2_SCL, SEL_I2C02_0), - PINMUX_IPSR_MODSEL_DATA(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0), + PINMUX_IPSR_MSEL(IP10_23_21, RDS_DATA_C, SEL_RDS_2), + PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0), + PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0), PINMUX_IPSR_DATA(IP10_26_24, DU1_DB6), - PINMUX_IPSR_MODSEL_DATA(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2), - PINMUX_IPSR_MODSEL_DATA(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1), + PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2), + PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1), PINMUX_IPSR_DATA(IP10_26_24, CAN_DEBUGOUT8), - PINMUX_IPSR_MODSEL_DATA(IP10_29_27, I2C2_SDA, SEL_I2C02_0), - PINMUX_IPSR_MODSEL_DATA(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0), + PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0), + PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0), PINMUX_IPSR_DATA(IP10_29_27, DU1_DB7), - PINMUX_IPSR_MODSEL_DATA(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2), + PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2), PINMUX_IPSR_DATA(IP10_29_27, CAN_DEBUGOUT9), - PINMUX_IPSR_MODSEL_DATA(IP10_31_30, SSI_SCK5, SEL_SSI5_0), - PINMUX_IPSR_MODSEL_DATA(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0), + PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0), + PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0), PINMUX_IPSR_DATA(IP10_31_30, DU1_DOTCLKIN), PINMUX_IPSR_DATA(IP10_31_30, CAN_DEBUGOUT10), /* IPSR11 */ - PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SSI_WS5, SEL_SSI5_0), - PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0), - PINMUX_IPSR_MODSEL_DATA(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2), + PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0), + PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0), + PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2), PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0), PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11), - PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SSI_SDATA5, SEL_SSI5_0), - PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0), - PINMUX_IPSR_MODSEL_DATA(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2), + PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0), + PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0), + PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2), PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1), PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12), - PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SSI_SCK6, SEL_SSI6_0), - PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1), + PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0), + PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1), PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC), PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13), - PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SSI_WS6, SEL_SSI6_0), - PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1), - PINMUX_IPSR_MODSEL_DATA(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2), + PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0), + PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2), PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC), PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14), - PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SSI_SDATA6, SEL_SSI6_0), - PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1), - PINMUX_IPSR_MODSEL_DATA(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2), + PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0), + PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2), PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE), PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15), - PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SSI_SCK78, SEL_SSI7_0), - PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1), - PINMUX_IPSR_MODSEL_DATA(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2), + PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1), + PINMUX_IPSR_MSEL(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2), PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP), - PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SSI_WS78, SEL_SSI7_0), - PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1), - PINMUX_IPSR_MODSEL_DATA(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2), + PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MSEL(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2), PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE), - PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SSI_SDATA7, SEL_SSI7_0), - PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0), + PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1), PINMUX_IPSR_DATA(IP11_20_18, IRQ8), - PINMUX_IPSR_MODSEL_DATA(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3), - PINMUX_IPSR_MODSEL_DATA(IP11_20_18, CAN_CLK_D, SEL_CAN_3), + PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3), + PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3), PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N), PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129), - PINMUX_IPSR_MODSEL_DATA(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1), - PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3), - PINMUX_IPSR_MODSEL_DATA(IP11_23_21, ADIDATA_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP11_23_21, AD_DI_B, SEL_ADI_1), + PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1), + PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3), + PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP11_23_21, AD_DI_B, SEL_ADI_1), PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N), PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129), - PINMUX_IPSR_MODSEL_DATA(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1), - PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3), - PINMUX_IPSR_MODSEL_DATA(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP11_26_24, AD_DO_B, SEL_ADI_1), + PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1), + PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3), + PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP11_26_24, AD_DO_B, SEL_ADI_1), PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0), - PINMUX_IPSR_MODSEL_DATA(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1), + PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1), PINMUX_IPSR_DATA(IP11_29_27, PWM0_B), - PINMUX_IPSR_MODSEL_DATA(IP11_29_27, ADICLK_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP11_29_27, AD_CLK_B, SEL_ADI_1), + PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP11_29_27, AD_CLK_B, SEL_ADI_1), /* IPSR12 */ PINMUX_IPSR_DATA(IP12_2_0, SSI_SCK34), - PINMUX_IPSR_MODSEL_DATA(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1), - PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2), - PINMUX_IPSR_MODSEL_DATA(IP12_2_0, ADICHS0_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP12_2_0, AD_NCS_N_B, SEL_ADI_1), - PINMUX_IPSR_MODSEL_DATA(IP12_2_0, DREQ1_N_B, SEL_LBS_1), + PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1), + PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2), + PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP12_2_0, AD_NCS_N_B, SEL_ADI_1), + PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1), PINMUX_IPSR_DATA(IP12_5_3, SSI_WS34), - PINMUX_IPSR_MODSEL_DATA(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1), - PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2), - PINMUX_IPSR_MODSEL_DATA(IP12_5_3, ADICHS1_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP12_5_3, CAN1_RX_C, SEL_CAN1_2), - PINMUX_IPSR_MODSEL_DATA(IP12_5_3, DACK1_B, SEL_LBS_1), + PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1), + PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2), + PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1), PINMUX_IPSR_DATA(IP12_8_6, SSI_SDATA3), - PINMUX_IPSR_MODSEL_DATA(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1), - PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2), - PINMUX_IPSR_MODSEL_DATA(IP12_8_6, ADICHS2_B, SEL_RAD_1), - PINMUX_IPSR_MODSEL_DATA(IP12_8_6, CAN1_TX_C, SEL_CAN1_2), + PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1), + PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2), + PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2), PINMUX_IPSR_DATA(IP12_8_6, DREQ2_N), - PINMUX_IPSR_MODSEL_DATA(IP12_10_9, SSI_SCK4, SEL_SSI4_0), + PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0), PINMUX_IPSR_DATA(IP12_10_9, MLB_CLK), - PINMUX_IPSR_MODSEL_DATA(IP12_10_9, IETX_B, SEL_IEB_1), + PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1), PINMUX_IPSR_DATA(IP12_10_9, IRD_TX), - PINMUX_IPSR_MODSEL_DATA(IP12_12_11, SSI_WS4, SEL_SSI4_0), + PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0), PINMUX_IPSR_DATA(IP12_12_11, MLB_SIG), - PINMUX_IPSR_MODSEL_DATA(IP12_12_11, IECLK_B, SEL_IEB_1), + PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1), PINMUX_IPSR_DATA(IP12_12_11, IRD_RX), - PINMUX_IPSR_MODSEL_DATA(IP12_14_13, SSI_SDATA4, SEL_SSI4_0), + PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0), PINMUX_IPSR_DATA(IP12_14_13, MLB_DAT), - PINMUX_IPSR_MODSEL_DATA(IP12_14_13, IERX_B, SEL_IEB_1), + PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1), PINMUX_IPSR_DATA(IP12_14_13, IRD_SCK), - PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SSI_SDATA8, SEL_SSI8_0), - PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0), + PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1), PINMUX_IPSR_DATA(IP12_17_15, PWM1_B), PINMUX_IPSR_DATA(IP12_17_15, IRQ9), - PINMUX_IPSR_MODSEL_DATA(IP12_17_15, REMOCON, SEL_RCN_0), + PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0), PINMUX_IPSR_DATA(IP12_17_15, DACK2), - PINMUX_IPSR_MODSEL_DATA(IP12_17_15, ETH_MDIO_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP12_20_18, SSI_SCK1, SEL_SSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2), + PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2), PINMUX_IPSR_DATA(IP12_20_18, VI1_CLK), - PINMUX_IPSR_MODSEL_DATA(IP12_20_18, CAN0_RX_D, SEL_CAN0_3), - PINMUX_IPSR_MODSEL_DATA(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0), - PINMUX_IPSR_MODSEL_DATA(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP12_23_21, SSI_WS1, SEL_SSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2), + PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3), + PINMUX_IPSR_MSEL(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0), + PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2), PINMUX_IPSR_DATA(IP12_23_21, VI1_DATA0), - PINMUX_IPSR_MODSEL_DATA(IP12_23_21, CAN0_TX_D, SEL_CAN0_3), - PINMUX_IPSR_MODSEL_DATA(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0), - PINMUX_IPSR_MODSEL_DATA(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SSI_SDATA1, SEL_SSI1_0), - PINMUX_IPSR_MODSEL_DATA(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3), + PINMUX_IPSR_MSEL(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0), + PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1), PINMUX_IPSR_DATA(IP12_26_24, VI1_DATA1), - PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SDATA, SEL_FSN_0), + PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0), PINMUX_IPSR_DATA(IP12_26_24, ATAG0_N), - PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ETH_RXD0_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SSI_SCK2, SEL_SSI2_0), - PINMUX_IPSR_MODSEL_DATA(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0), + PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1), PINMUX_IPSR_DATA(IP12_29_27, VI1_DATA2), - PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MDATA, SEL_FSN_0), + PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0), PINMUX_IPSR_DATA(IP12_29_27, ATAWR0_N), - PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ETH_RXD1_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1), /* IPSR13 */ - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_WS2, SEL_SSI2_0), - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3), + PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0), + PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3), PINMUX_IPSR_DATA(IP13_2_0, VI1_DATA3), - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCKZ, SEL_FSN_0), + PINMUX_IPSR_MSEL(IP13_2_0, SCKZ, SEL_FSN_0), PINMUX_IPSR_DATA(IP13_2_0, ATACS00_N), - PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ETH_LINK_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP13_5_3, SSI_SDATA2, SEL_SSI2_0), - PINMUX_IPSR_MODSEL_DATA(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1), - PINMUX_IPSR_MODSEL_DATA(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3), + PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0), + PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3), PINMUX_IPSR_DATA(IP13_5_3, VI1_DATA4), - PINMUX_IPSR_MODSEL_DATA(IP13_5_3, STM_N, SEL_FSN_0), + PINMUX_IPSR_MSEL(IP13_5_3, STM_N, SEL_FSN_0), PINMUX_IPSR_DATA(IP13_5_3, ATACS10_N), - PINMUX_IPSR_MODSEL_DATA(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP13_8_6, SSI_SCK9, SEL_SSI9_0), - PINMUX_IPSR_MODSEL_DATA(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1), PINMUX_IPSR_DATA(IP13_8_6, PWM2_B), PINMUX_IPSR_DATA(IP13_8_6, VI1_DATA5), - PINMUX_IPSR_MODSEL_DATA(IP13_8_6, MTS_N, SEL_FSN_0), + PINMUX_IPSR_MSEL(IP13_8_6, MTS_N, SEL_FSN_0), PINMUX_IPSR_DATA(IP13_8_6, EX_WAIT1), - PINMUX_IPSR_MODSEL_DATA(IP13_8_6, ETH_TXD1_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP13_11_9, SSI_WS9, SEL_SSI9_0), - PINMUX_IPSR_MODSEL_DATA(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4), + PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4), PINMUX_IPSR_DATA(IP13_11_9, VI1_DATA6), PINMUX_IPSR_DATA(IP13_11_9, ATARD0_N), - PINMUX_IPSR_MODSEL_DATA(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP13_14_12, SSI_SDATA9, SEL_SSI9_0), - PINMUX_IPSR_MODSEL_DATA(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1), - PINMUX_IPSR_MODSEL_DATA(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4), + PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4), PINMUX_IPSR_DATA(IP13_14_12, VI1_DATA7), PINMUX_IPSR_DATA(IP13_14_12, ATADIR0_N), - PINMUX_IPSR_MODSEL_DATA(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP13_17_15, AUDIO_CLKA, SEL_ADG_0), - PINMUX_IPSR_MODSEL_DATA(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1), - PINMUX_IPSR_MODSEL_DATA(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3), + PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0), + PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1), + PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3), PINMUX_IPSR_DATA(IP13_17_15, VI1_CLKENB), - PINMUX_IPSR_MODSEL_DATA(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1), - PINMUX_IPSR_MODSEL_DATA(IP13_17_15, ETH_TXD0_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP13_20_18, AUDIO_CLKB, SEL_ADG_0), - PINMUX_IPSR_MODSEL_DATA(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1), - PINMUX_IPSR_MODSEL_DATA(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3), + PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1), + PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0), + PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1), + PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3), PINMUX_IPSR_DATA(IP13_20_18, VI1_FIELD), - PINMUX_IPSR_MODSEL_DATA(IP13_20_18, TS_SCK_C, SEL_TSIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP13_20_18, RIF0_CLK_B, SEL_DR0_1), - PINMUX_IPSR_MODSEL_DATA(IP13_20_18, BPFCLK_E, SEL_DARC_4), - PINMUX_IPSR_MODSEL_DATA(IP13_20_18, ETH_MDC_B, SEL_ETH_1), - PINMUX_IPSR_MODSEL_DATA(IP13_23_21, AUDIO_CLKC, SEL_ADG_0), - PINMUX_IPSR_MODSEL_DATA(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1), - PINMUX_IPSR_MODSEL_DATA(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3), + PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP13_20_18, RIF0_CLK_B, SEL_DR0_1), + PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4), + PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0), + PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1), + PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3), PINMUX_IPSR_DATA(IP13_23_21, VI1_HSYNC_N), - PINMUX_IPSR_MODSEL_DATA(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP13_23_21, RIF0_D0_B, SEL_DR0_1), - PINMUX_IPSR_MODSEL_DATA(IP13_23_21, FMCLK_E, SEL_DARC_4), - PINMUX_IPSR_MODSEL_DATA(IP13_23_21, RDS_CLK_D, SEL_RDS_3), - PINMUX_IPSR_MODSEL_DATA(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0), - PINMUX_IPSR_MODSEL_DATA(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1), - PINMUX_IPSR_MODSEL_DATA(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3), + PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP13_23_21, RIF0_D0_B, SEL_DR0_1), + PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4), + PINMUX_IPSR_MSEL(IP13_23_21, RDS_CLK_D, SEL_RDS_3), + PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0), + PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1), + PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3), PINMUX_IPSR_DATA(IP13_26_24, VI1_VSYNC_N), - PINMUX_IPSR_MODSEL_DATA(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2), - PINMUX_IPSR_MODSEL_DATA(IP13_26_24, RIF0_D1_B, SEL_DR1_1), - PINMUX_IPSR_MODSEL_DATA(IP13_26_24, FMIN_E, SEL_DARC_4), - PINMUX_IPSR_MODSEL_DATA(IP13_26_24, RDS_DATA_D, SEL_RDS_3), + PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP13_26_24, RIF0_D1_B, SEL_DR1_1), + PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4), + PINMUX_IPSR_MSEL(IP13_26_24, RDS_DATA_D, SEL_RDS_3), }; static const struct sh_pfc_pin pinmux_pins[] = { @@ -2197,13 +2196,6 @@ static const unsigned int scif0_data_pins[] = { static const unsigned int scif0_data_mux[] = { SCIF0_RXD_MARK, SCIF0_TXD_MARK, }; -static const unsigned int scif0_clk_pins[] = { - /* SCK */ - RCAR_GP_PIN(1, 23), -}; -static const unsigned int scif0_clk_mux[] = { - SCIF_CLK_MARK, -}; static const unsigned int scif0_data_b_pins[] = { /* RX, TX */ RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), @@ -2211,13 +2203,6 @@ static const unsigned int scif0_data_b_pins[] = { static const unsigned int scif0_data_b_mux[] = { SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK, }; -static const unsigned int scif0_clk_b_pins[] = { - /* SCK */ - RCAR_GP_PIN(3, 29), -}; -static const unsigned int scif0_clk_b_mux[] = { - SCIF_CLK_B_MARK, -}; static const unsigned int scif0_data_c_pins[] = { /* RX, TX */ RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), @@ -2788,6 +2773,146 @@ static const unsigned int usb1_mux[] = { USB1_PWEN_MARK, USB1_OVC_MARK, }; +/* - VIN0 ------------------------------------------------------------------- */ +static const union vin_data vin0_data_pins = { + .data24 = { + /* B */ + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), + RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), + /* G */ + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), + RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), + RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), + /* R */ + RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), + RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), + RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), + }, +}; +static const union vin_data vin0_data_mux = { + .data24 = { + /* B */ + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G0_MARK, VI0_G1_MARK, + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R0_MARK, VI0_R1_MARK, + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, + }, +}; +static const unsigned int vin0_data18_pins[] = { + /* B */ + RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), + /* G */ + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), + RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), + RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), + /* R */ + RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), + RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), +}; +static const unsigned int vin0_data18_mux[] = { + /* B */ + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, +}; +static const unsigned int vin0_sync_pins[] = { + RCAR_GP_PIN(3, 11), /* HSYNC */ + RCAR_GP_PIN(3, 12), /* VSYNC */ +}; +static const unsigned int vin0_sync_mux[] = { + VI0_HSYNC_N_MARK, + VI0_VSYNC_N_MARK, +}; +static const unsigned int vin0_field_pins[] = { + RCAR_GP_PIN(3, 10), +}; +static const unsigned int vin0_field_mux[] = { + VI0_FIELD_MARK, +}; +static const unsigned int vin0_clkenb_pins[] = { + RCAR_GP_PIN(3, 9), +}; +static const unsigned int vin0_clkenb_mux[] = { + VI0_CLKENB_MARK, +}; +static const unsigned int vin0_clk_pins[] = { + RCAR_GP_PIN(3, 0), +}; +static const unsigned int vin0_clk_mux[] = { + VI0_CLK_MARK, +}; +/* - VIN1 ------------------------------------------------------------------- */ +static const union vin_data vin1_data_pins = { + .data12 = { + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), + RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), + RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), + }, +}; +static const union vin_data vin1_data_mux = { + .data12 = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, + VI1_DATA8_MARK, VI1_DATA9_MARK, + VI1_DATA10_MARK, VI1_DATA11_MARK, + }, +}; +static const unsigned int vin1_sync_pins[] = { + RCAR_GP_PIN(5, 22), /* HSYNC */ + RCAR_GP_PIN(5, 23), /* VSYNC */ +}; +static const unsigned int vin1_sync_mux[] = { + VI1_HSYNC_N_MARK, + VI1_VSYNC_N_MARK, +}; +static const unsigned int vin1_field_pins[] = { + RCAR_GP_PIN(5, 21), +}; +static const unsigned int vin1_field_mux[] = { + VI1_FIELD_MARK, +}; +static const unsigned int vin1_clkenb_pins[] = { + RCAR_GP_PIN(5, 20), +}; +static const unsigned int vin1_clkenb_mux[] = { + VI1_CLKENB_MARK, +}; +static const unsigned int vin1_clk_pins[] = { + RCAR_GP_PIN(5, 11), +}; +static const unsigned int vin1_clk_mux[] = { + VI1_CLK_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(eth_link), @@ -2884,9 +3009,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(qspi_data2), SH_PFC_PIN_GROUP(qspi_data4), SH_PFC_PIN_GROUP(scif0_data), - SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_data_b), - SH_PFC_PIN_GROUP(scif0_clk_b), SH_PFC_PIN_GROUP(scif0_data_c), SH_PFC_PIN_GROUP(scif0_data_d), SH_PFC_PIN_GROUP(scif1_data), @@ -2965,6 +3088,24 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi2_wp), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), + VIN_DATA_PIN_GROUP(vin0_data, 24), + VIN_DATA_PIN_GROUP(vin0_data, 20), + SH_PFC_PIN_GROUP(vin0_data18), + VIN_DATA_PIN_GROUP(vin0_data, 16), + VIN_DATA_PIN_GROUP(vin0_data, 12), + VIN_DATA_PIN_GROUP(vin0_data, 10), + VIN_DATA_PIN_GROUP(vin0_data, 8), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin0_field), + SH_PFC_PIN_GROUP(vin0_clkenb), + SH_PFC_PIN_GROUP(vin0_clk), + VIN_DATA_PIN_GROUP(vin1_data, 12), + VIN_DATA_PIN_GROUP(vin1_data, 10), + VIN_DATA_PIN_GROUP(vin1_data, 8), + SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin1_field), + SH_PFC_PIN_GROUP(vin1_clkenb), + SH_PFC_PIN_GROUP(vin1_clk), }; static const char * const eth_groups[] = { @@ -3107,9 +3248,7 @@ static const char * const qspi_groups[] = { static const char * const scif0_groups[] = { "scif0_data", - "scif0_clk", "scif0_data_b", - "scif0_clk_b", "scif0_data_c", "scif0_data_d", }; @@ -3247,6 +3386,30 @@ static const char * const usb1_groups[] = { "usb1", }; +static const char * const vin0_groups[] = { + "vin0_data24", + "vin0_data20", + "vin0_data18", + "vin0_data16", + "vin0_data12", + "vin0_data10", + "vin0_data8", + "vin0_sync", + "vin0_field", + "vin0_clkenb", + "vin0_clk", +}; + +static const char * const vin1_groups[] = { + "vin1_data12", + "vin1_data10", + "vin1_data8", + "vin1_sync", + "vin1_field", + "vin1_clkenb", + "vin1_clk", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(eth), SH_PFC_FUNCTION(hscif0), @@ -3283,6 +3446,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -4232,6 +4397,6 @@ const struct sh_pfc_soc_info r8a7794_pinmux_info = { .cfg_regs = pinmux_config_regs, - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; |