diff options
Diffstat (limited to 'drivers/pinctrl/intel/pinctrl-cherryview.c')
| -rw-r--r-- | drivers/pinctrl/intel/pinctrl-cherryview.c | 147 |
1 files changed, 65 insertions, 82 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 6d31ad799987..9b0f4b9ef482 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -10,19 +10,20 @@ * Alan Cox <alan@linux.intel.com> */ +#include <linux/acpi.h> #include <linux/dmi.h> +#include <linux/gpio/driver.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/init.h> +#include <linux/platform_device.h> #include <linux/types.h> -#include <linux/gpio.h> -#include <linux/gpio/driver.h> -#include <linux/acpi.h> + #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> -#include <linux/platform_device.h> + +#include "pinctrl-intel.h" #define CHV_INTSTAT 0x300 #define CHV_INTMASK 0x380 @@ -73,7 +74,7 @@ * @invert_oe: Invert OE for this pin */ struct chv_alternate_function { - unsigned pin; + unsigned int pin; u8 mode; bool invert_oe; }; @@ -90,7 +91,7 @@ struct chv_alternate_function { */ struct chv_pingroup { const char *name; - const unsigned *pins; + const unsigned int *pins; size_t npins; struct chv_alternate_function altfunc; const struct chv_alternate_function *overrides; @@ -98,25 +99,13 @@ struct chv_pingroup { }; /** - * struct chv_function - A CHV pinmux function - * @name: Name of the function - * @groups: An array of groups for this function - * @ngroups: Number of groups in @groups - */ -struct chv_function { - const char *name; - const char * const *groups; - size_t ngroups; -}; - -/** * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs * @base: Start pin number * @npins: Number of pins in this range */ struct chv_gpio_pinrange { - unsigned base; - unsigned npins; + unsigned int base; + unsigned int npins; }; /** @@ -131,6 +120,7 @@ struct chv_gpio_pinrange { * @gpio_ranges: An array of GPIO ranges in this community * @ngpio_ranges: Number of GPIO ranges * @nirqs: Total number of IRQs this community can generate + * @acpi_space_id: An address space ID for ACPI OpRegion handler */ struct chv_community { const char *uid; @@ -138,7 +128,7 @@ struct chv_community { size_t npins; const struct chv_pingroup *groups; size_t ngroups; - const struct chv_function *functions; + const struct intel_function *functions; size_t nfunctions; const struct chv_gpio_pinrange *gpio_ranges; size_t ngpio_ranges; @@ -161,6 +151,8 @@ struct chv_pin_context { * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO * offset (in GPIO number space) * @community: Community this pinctrl instance represents + * @saved_intmask: Interrupt mask saved for system sleep + * @saved_pin_context: Pointer to a context of the pins saved for system sleep * * The first group in @groups is expected to contain all pins that can be * used as GPIOs. @@ -184,7 +176,7 @@ struct chv_pinctrl { .invert_oe = (i), \ } -#define PIN_GROUP(n, p, m, i) \ +#define PIN_GROUP_WITH_ALT(n, p, m, i) \ { \ .name = (n), \ .pins = (p), \ @@ -204,13 +196,6 @@ struct chv_pinctrl { .noverrides = ARRAY_SIZE((o)), \ } -#define FUNCTION(n, g) \ - { \ - .name = (n), \ - .groups = (g), \ - .ngroups = ARRAY_SIZE((g)), \ - } - #define GPIO_PINRANGE(start, end) \ { \ .base = (start), \ @@ -282,7 +267,6 @@ static const struct pinctrl_pin_desc southwest_pins[] = { PINCTRL_PIN(97, "GP_SSP_2_TXD"), }; -static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 }; static const unsigned southwest_uart0_pins[] = { 16, 20 }; static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 }; static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 }; @@ -298,7 +282,6 @@ static const unsigned southwest_i2c4_pins[] = { 46, 50 }; static const unsigned southwest_i2c5_pins[] = { 45, 48 }; static const unsigned southwest_i2c6_pins[] = { 47, 51 }; static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; -static const unsigned southwest_smbus_pins[] = { 79, 81, 82 }; static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; /* LPE I2S TXD pins need to have invert_oe set */ @@ -318,18 +301,18 @@ static const struct chv_alternate_function southwest_spi3_altfuncs[] = { }; static const struct chv_pingroup southwest_groups[] = { - PIN_GROUP("uart0_grp", southwest_uart0_pins, 2, false), - PIN_GROUP("uart1_grp", southwest_uart1_pins, 1, false), - PIN_GROUP("uart2_grp", southwest_uart2_pins, 1, false), - PIN_GROUP("hda_grp", southwest_hda_pins, 2, false), - PIN_GROUP("i2c0_grp", southwest_i2c0_pins, 1, true), - PIN_GROUP("i2c1_grp", southwest_i2c1_pins, 1, true), - PIN_GROUP("i2c2_grp", southwest_i2c2_pins, 1, true), - PIN_GROUP("i2c3_grp", southwest_i2c3_pins, 1, true), - PIN_GROUP("i2c4_grp", southwest_i2c4_pins, 1, true), - PIN_GROUP("i2c5_grp", southwest_i2c5_pins, 1, true), - PIN_GROUP("i2c6_grp", southwest_i2c6_pins, 1, true), - PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true), + PIN_GROUP_WITH_ALT("uart0_grp", southwest_uart0_pins, 2, false), + PIN_GROUP_WITH_ALT("uart1_grp", southwest_uart1_pins, 1, false), + PIN_GROUP_WITH_ALT("uart2_grp", southwest_uart2_pins, 1, false), + PIN_GROUP_WITH_ALT("hda_grp", southwest_hda_pins, 2, false), + PIN_GROUP_WITH_ALT("i2c0_grp", southwest_i2c0_pins, 1, true), + PIN_GROUP_WITH_ALT("i2c1_grp", southwest_i2c1_pins, 1, true), + PIN_GROUP_WITH_ALT("i2c2_grp", southwest_i2c2_pins, 1, true), + PIN_GROUP_WITH_ALT("i2c3_grp", southwest_i2c3_pins, 1, true), + PIN_GROUP_WITH_ALT("i2c4_grp", southwest_i2c4_pins, 1, true), + PIN_GROUP_WITH_ALT("i2c5_grp", southwest_i2c5_pins, 1, true), + PIN_GROUP_WITH_ALT("i2c6_grp", southwest_i2c6_pins, 1, true), + PIN_GROUP_WITH_ALT("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true), PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false, southwest_lpe_altfuncs), @@ -356,7 +339,7 @@ static const char * const southwest_spi3_groups[] = { "spi3_grp" }; * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are * enabled only as GPIOs. */ -static const struct chv_function southwest_functions[] = { +static const struct intel_function southwest_functions[] = { FUNCTION("uart0", southwest_uart0_groups), FUNCTION("uart1", southwest_uart1_groups), FUNCTION("uart2", southwest_uart2_groups), @@ -610,13 +593,13 @@ static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; static const struct chv_pingroup southeast_groups[] = { - PIN_GROUP("pwm0_grp", southeast_pwm0_pins, 1, false), - PIN_GROUP("pwm1_grp", southeast_pwm1_pins, 1, false), - PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, 1, false), - PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, 1, false), - PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, 1, false), - PIN_GROUP("spi1_grp", southeast_spi1_pins, 1, false), - PIN_GROUP("spi2_grp", southeast_spi2_pins, 4, false), + PIN_GROUP_WITH_ALT("pwm0_grp", southeast_pwm0_pins, 1, false), + PIN_GROUP_WITH_ALT("pwm1_grp", southeast_pwm1_pins, 1, false), + PIN_GROUP_WITH_ALT("sdmmc1_grp", southeast_sdmmc1_pins, 1, false), + PIN_GROUP_WITH_ALT("sdmmc2_grp", southeast_sdmmc2_pins, 1, false), + PIN_GROUP_WITH_ALT("sdmmc3_grp", southeast_sdmmc3_pins, 1, false), + PIN_GROUP_WITH_ALT("spi1_grp", southeast_spi1_pins, 1, false), + PIN_GROUP_WITH_ALT("spi2_grp", southeast_spi2_pins, 4, false), }; static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; @@ -627,7 +610,7 @@ static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" }; static const char * const southeast_spi1_groups[] = { "spi1_grp" }; static const char * const southeast_spi2_groups[] = { "spi2_grp" }; -static const struct chv_function southeast_functions[] = { +static const struct intel_function southeast_functions[] = { FUNCTION("pwm0", southeast_pwm0_groups), FUNCTION("pwm1", southeast_pwm1_groups), FUNCTION("sdmmc1", southeast_sdmmc1_groups), @@ -678,11 +661,11 @@ static const struct chv_community *chv_communities[] = { */ static DEFINE_RAW_SPINLOCK(chv_lock); -static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset, - unsigned reg) +static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset, + unsigned int reg) { - unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO; - unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO; + unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO; + unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO; offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no + GPIO_REGS_SIZE * pad_no; @@ -698,7 +681,7 @@ static void chv_writel(u32 value, void __iomem *reg) } /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ -static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset) +static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned int offset) { void __iomem *reg; @@ -714,15 +697,15 @@ static int chv_get_groups_count(struct pinctrl_dev *pctldev) } static const char *chv_get_group_name(struct pinctrl_dev *pctldev, - unsigned group) + unsigned int group) { struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); return pctrl->community->groups[group].name; } -static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, - const unsigned **pins, unsigned *npins) +static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, + const unsigned int **pins, unsigned int *npins) { struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); @@ -732,7 +715,7 @@ static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, } static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned offset) + unsigned int offset) { struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); unsigned long flags; @@ -779,7 +762,7 @@ static int chv_get_functions_count(struct pinctrl_dev *pctldev) } static const char *chv_get_function_name(struct pinctrl_dev *pctldev, - unsigned function) + unsigned int function) { struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); @@ -787,9 +770,9 @@ static const char *chv_get_function_name(struct pinctrl_dev *pctldev, } static int chv_get_function_groups(struct pinctrl_dev *pctldev, - unsigned function, + unsigned int function, const char * const **groups, - unsigned * const ngroups) + unsigned int * const ngroups) { struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); @@ -798,8 +781,8 @@ static int chv_get_function_groups(struct pinctrl_dev *pctldev, return 0; } -static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, - unsigned group) +static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, unsigned int group) { struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); const struct chv_pingroup *grp; @@ -865,7 +848,7 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, - unsigned offset) + unsigned int offset) { struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); unsigned long flags; @@ -925,7 +908,7 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, - unsigned offset) + unsigned int offset) { struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); unsigned long flags; @@ -943,7 +926,7 @@ static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, - unsigned offset, bool input) + unsigned int offset, bool input) { struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); @@ -974,7 +957,7 @@ static const struct pinmux_ops chv_pinmux_ops = { .gpio_set_direction = chv_gpio_set_direction, }; -static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin, +static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) { struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); @@ -1054,7 +1037,7 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin, return 0; } -static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin, +static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned int pin, enum pin_config_param param, u32 arg) { void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); @@ -1141,8 +1124,8 @@ static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin, return 0; } -static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long *configs, unsigned nconfigs) +static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int nconfigs) { struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param; @@ -1243,7 +1226,7 @@ static struct pinctrl_desc chv_pinctrl_desc = { .owner = THIS_MODULE, }; -static int chv_gpio_get(struct gpio_chip *chip, unsigned offset) +static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset) { struct chv_pinctrl *pctrl = gpiochip_get_data(chip); unsigned long flags; @@ -1261,7 +1244,7 @@ static int chv_gpio_get(struct gpio_chip *chip, unsigned offset) return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE); } -static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { struct chv_pinctrl *pctrl = gpiochip_get_data(chip); unsigned long flags; @@ -1283,7 +1266,7 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value) raw_spin_unlock_irqrestore(&chv_lock, flags); } -static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset) +static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { struct chv_pinctrl *pctrl = gpiochip_get_data(chip); u32 ctrl0, direction; @@ -1299,12 +1282,12 @@ static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset) return direction != CHV_PADCTRL0_GPIOCFG_GPO; } -static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { return pinctrl_gpio_direction_input(chip->base + offset); } -static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset, +static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) { chv_gpio_set(chip, offset, value); @@ -1388,7 +1371,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct chv_pinctrl *pctrl = gpiochip_get_data(gc); - unsigned pin = irqd_to_hwirq(d); + unsigned int pin = irqd_to_hwirq(d); irq_flow_handler_t handler; unsigned long flags; u32 intsel, value; @@ -1415,11 +1398,11 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) return 0; } -static int chv_gpio_irq_type(struct irq_data *d, unsigned type) +static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct chv_pinctrl *pctrl = gpiochip_get_data(gc); - unsigned pin = irqd_to_hwirq(d); + unsigned int pin = irqd_to_hwirq(d); unsigned long flags; u32 value; |