diff options
Diffstat (limited to 'drivers/pci')
43 files changed, 1223 insertions, 678 deletions
diff --git a/drivers/pci/access.c b/drivers/pci/access.c index 913d6722ece9..61a45bc0efc8 100644 --- a/drivers/pci/access.c +++ b/drivers/pci/access.c @@ -333,8 +333,7 @@ static size_t pci_vpd_size(struct pci_dev *dev, size_t old_size) (tag == PCI_VPD_LTIN_RW_DATA)) { if (pci_read_vpd(dev, off+1, 2, &header[1]) != 2) { - dev_warn(&dev->dev, - "invalid large VPD tag %02x size at offset %zu", + pci_warn(dev, "invalid large VPD tag %02x size at offset %zu", tag, off + 1); return 0; } @@ -354,8 +353,7 @@ static size_t pci_vpd_size(struct pci_dev *dev, size_t old_size) if ((tag != PCI_VPD_LTIN_ID_STRING) && (tag != PCI_VPD_LTIN_RO_DATA) && (tag != PCI_VPD_LTIN_RW_DATA)) { - dev_warn(&dev->dev, - "invalid %s VPD tag %02x at offset %zu", + pci_warn(dev, "invalid %s VPD tag %02x at offset %zu", (header[0] & PCI_VPD_LRDT) ? "large" : "short", tag, off); return 0; @@ -402,7 +400,7 @@ static int pci_vpd_wait(struct pci_dev *dev) max_sleep *= 2; } - dev_warn(&dev->dev, "VPD access failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n"); + pci_warn(dev, "VPD access failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n"); return -ETIMEDOUT; } diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c index bc56cf19afd3..efe61c0fb4cb 100644 --- a/drivers/pci/bus.c +++ b/drivers/pci/bus.c @@ -289,7 +289,7 @@ bool pci_bus_clip_resource(struct pci_dev *dev, int idx) res->end = end; res->flags &= ~IORESOURCE_UNSET; orig_res.flags &= ~IORESOURCE_UNSET; - dev_printk(KERN_DEBUG, &dev->dev, "%pR clipped to %pR\n", + pci_printk(KERN_DEBUG, dev, "%pR clipped to %pR\n", &orig_res, res); return true; @@ -325,7 +325,7 @@ void pci_bus_add_device(struct pci_dev *dev) dev->match_driver = true; retval = device_attach(&dev->dev); if (retval < 0 && retval != -EPROBE_DEFER) { - dev_warn(&dev->dev, "device attach failed (%d)\n", retval); + pci_warn(dev, "device attach failed (%d)\n", retval); pci_proc_detach_device(dev); pci_remove_sysfs_dev_files(dev); return; diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c index 5db6f1839dad..96f5b986454a 100644 --- a/drivers/pci/hotplug/acpiphp_glue.c +++ b/drivers/pci/hotplug/acpiphp_glue.c @@ -811,10 +811,8 @@ void acpiphp_enumerate_slots(struct pci_bus *bus) handle = adev->handle; bridge = kzalloc(sizeof(struct acpiphp_bridge), GFP_KERNEL); - if (!bridge) { - acpi_handle_err(handle, "No memory for bridge object\n"); + if (!bridge) return; - } INIT_LIST_HEAD(&bridge->slots); kref_init(&bridge->ref); diff --git a/drivers/pci/hotplug/cpqphp_core.c b/drivers/pci/hotplug/cpqphp_core.c index 70967ac75265..27a562618d7f 100644 --- a/drivers/pci/hotplug/cpqphp_core.c +++ b/drivers/pci/hotplug/cpqphp_core.c @@ -835,7 +835,7 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent) bus = pdev->subordinate; if (!bus) { - dev_notice(&pdev->dev, "the device is not a bridge, skipping\n"); + pci_notice(pdev, "the device is not a bridge, skipping\n"); rc = -ENODEV; goto err_disable_device; } @@ -883,7 +883,6 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent) ctrl = kzalloc(sizeof(struct controller), GFP_KERNEL); if (!ctrl) { - err("%s : out of memory\n", __func__); rc = -ENOMEM; goto err_disable_device; } diff --git a/drivers/pci/hotplug/cpqphp_pci.c b/drivers/pci/hotplug/cpqphp_pci.c index e220d49307bd..8897a7775b8c 100644 --- a/drivers/pci/hotplug/cpqphp_pci.c +++ b/drivers/pci/hotplug/cpqphp_pci.c @@ -89,7 +89,9 @@ int cpqhp_configure_device(struct controller *ctrl, struct pci_func *func) pci_lock_rescan_remove(); if (func->pci_dev == NULL) - func->pci_dev = pci_get_bus_and_slot(func->bus, PCI_DEVFN(func->device, func->function)); + func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus, + PCI_DEVFN(func->device, + func->function)); /* No pci device, we need to create it then */ if (func->pci_dev == NULL) { @@ -99,7 +101,9 @@ int cpqhp_configure_device(struct controller *ctrl, struct pci_func *func) if (num) pci_bus_add_devices(ctrl->pci_dev->bus); - func->pci_dev = pci_get_bus_and_slot(func->bus, PCI_DEVFN(func->device, func->function)); + func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus, + PCI_DEVFN(func->device, + func->function)); if (func->pci_dev == NULL) { dbg("ERROR: pci_dev still null\n"); goto out; @@ -129,7 +133,10 @@ int cpqhp_unconfigure_device(struct pci_func *func) pci_lock_rescan_remove(); for (j = 0; j < 8 ; j++) { - struct pci_dev *temp = pci_get_bus_and_slot(func->bus, PCI_DEVFN(func->device, j)); + struct pci_dev *temp = pci_get_domain_bus_and_slot(0, + func->bus, + PCI_DEVFN(func->device, + j)); if (temp) { pci_dev_put(temp); pci_stop_and_remove_bus_device(temp); @@ -319,6 +326,7 @@ int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug) int cloop = 0; int stop_it; int index; + u16 devfn; /* Decide which slots are supported */ @@ -416,7 +424,9 @@ int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug) new_slot->switch_save = 0x10; /* In case of unsupported board */ new_slot->status = DevError; - new_slot->pci_dev = pci_get_bus_and_slot(new_slot->bus, (new_slot->device << 3) | new_slot->function); + devfn = (new_slot->device << 3) | new_slot->function; + new_slot->pci_dev = pci_get_domain_bus_and_slot(0, + new_slot->bus, devfn); for (cloop = 0; cloop < 0x20; cloop++) { rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), cloop << 2, (u32 *) &(new_slot->config_space[cloop])); diff --git a/drivers/pci/hotplug/ibmphp_core.c b/drivers/pci/hotplug/ibmphp_core.c index 73cf84645c82..4985e681e48f 100644 --- a/drivers/pci/hotplug/ibmphp_core.c +++ b/drivers/pci/hotplug/ibmphp_core.c @@ -603,10 +603,8 @@ int ibmphp_update_slot_info(struct slot *slot_cur) u8 mode; info = kmalloc(sizeof(struct hotplug_slot_info), GFP_KERNEL); - if (!info) { - err("out of system memory\n"); + if (!info) return -ENOMEM; - } info->power_status = SLOT_PWRGD(slot_cur->status); info->attention_status = SLOT_ATTN(slot_cur->status, @@ -707,7 +705,8 @@ static void ibm_unconfigure_device(struct pci_func *func) pci_lock_rescan_remove(); for (j = 0; j < 0x08; j++) { - temp = pci_get_bus_and_slot(func->busno, (func->device << 3) | j); + temp = pci_get_domain_bus_and_slot(0, func->busno, + (func->device << 3) | j); if (temp) { pci_stop_and_remove_bus_device(temp); pci_dev_put(temp); @@ -734,14 +733,12 @@ static u8 bus_structure_fixup(u8 busno) return 1; bus = kmalloc(sizeof(*bus), GFP_KERNEL); - if (!bus) { - err("%s - out of memory\n", __func__); + if (!bus) return 1; - } + dev = kmalloc(sizeof(*dev), GFP_KERNEL); if (!dev) { kfree(bus); - err("%s - out of memory\n", __func__); return 1; } @@ -780,7 +777,7 @@ static int ibm_configure_device(struct pci_func *func) if (!(bus_structure_fixup(func->busno))) flag = 1; if (func->dev == NULL) - func->dev = pci_get_bus_and_slot(func->busno, + func->dev = pci_get_domain_bus_and_slot(0, func->busno, PCI_DEVFN(func->device, func->function)); if (func->dev == NULL) { @@ -793,7 +790,7 @@ static int ibm_configure_device(struct pci_func *func) if (num) pci_bus_add_devices(bus); - func->dev = pci_get_bus_and_slot(func->busno, + func->dev = pci_get_domain_bus_and_slot(0, func->busno, PCI_DEVFN(func->device, func->function)); if (func->dev == NULL) { err("ERROR... : pci_dev still NULL\n"); @@ -1101,7 +1098,6 @@ static int enable_slot(struct hotplug_slot *hs) if (!slot_cur->func) { /* We cannot do update_slot_info here, since no memory for * kmalloc n.e.ways, and update_slot_info allocates some */ - err("out of system memory\n"); rc = -ENOMEM; goto error_power; } @@ -1208,7 +1204,6 @@ int ibmphp_do_disable_slot(struct slot *slot_cur) /* We need this for functions that were there on bootup */ slot_cur->func = kzalloc(sizeof(struct pci_func), GFP_KERNEL); if (!slot_cur->func) { - err("out of system memory\n"); rc = -ENOMEM; goto error; } @@ -1306,7 +1301,6 @@ static int __init ibmphp_init(void) ibmphp_pci_bus = kmalloc(sizeof(*ibmphp_pci_bus), GFP_KERNEL); if (!ibmphp_pci_bus) { - err("out of memory\n"); rc = -ENOMEM; goto exit; } diff --git a/drivers/pci/hotplug/ibmphp_pci.c b/drivers/pci/hotplug/ibmphp_pci.c index 25edd0b18b75..c7ce7d8cf998 100644 --- a/drivers/pci/hotplug/ibmphp_pci.c +++ b/drivers/pci/hotplug/ibmphp_pci.c @@ -167,10 +167,9 @@ int ibmphp_configure_card(struct pci_func *func, u8 slotno) goto error; } newfunc = kzalloc(sizeof(*newfunc), GFP_KERNEL); - if (!newfunc) { - err("out of system memory\n"); + if (!newfunc) return -ENOMEM; - } + newfunc->busno = cur_func->busno; newfunc->device = device; cur_func->next = newfunc; @@ -205,10 +204,9 @@ int ibmphp_configure_card(struct pci_func *func, u8 slotno) for (i = 0; i < 32; i++) { if (func->devices[i]) { newfunc = kzalloc(sizeof(*newfunc), GFP_KERNEL); - if (!newfunc) { - err("out of system memory\n"); + if (!newfunc) return -ENOMEM; - } + newfunc->busno = sec_number; newfunc->device = (u8) i; for (j = 0; j < 4; j++) @@ -233,10 +231,9 @@ int ibmphp_configure_card(struct pci_func *func, u8 slotno) } newfunc = kzalloc(sizeof(*newfunc), GFP_KERNEL); - if (!newfunc) { - err("out of system memory\n"); + if (!newfunc) return -ENOMEM; - } + newfunc->busno = cur_func->busno; newfunc->device = device; for (j = 0; j < 4; j++) @@ -279,10 +276,9 @@ int ibmphp_configure_card(struct pci_func *func, u8 slotno) if (func->devices[i]) { debug("inside for loop, device is %x\n", i); newfunc = kzalloc(sizeof(*newfunc), GFP_KERNEL); - if (!newfunc) { - err(" out of system memory\n"); + if (!newfunc) return -ENOMEM; - } + newfunc->busno = sec_number; newfunc->device = (u8) i; for (j = 0; j < 4; j++) @@ -405,10 +401,9 @@ static int configure_device(struct pci_func *func) io[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL); - if (!io[count]) { - err("out of system memory\n"); + if (!io[count]) return -ENOMEM; - } + io[count]->type = IO; io[count]->busno = func->busno; io[count]->devfunc = PCI_DEVFN(func->device, func->function); @@ -442,10 +437,9 @@ static int configure_device(struct pci_func *func) debug("len[count] in PFMEM %x, count %d\n", len[count], count); pfmem[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL); - if (!pfmem[count]) { - err("out of system memory\n"); + if (!pfmem[count]) return -ENOMEM; - } + pfmem[count]->type = PFMEM; pfmem[count]->busno = func->busno; pfmem[count]->devfunc = PCI_DEVFN(func->device, @@ -458,7 +452,6 @@ static int configure_device(struct pci_func *func) } else { mem_tmp = kzalloc(sizeof(*mem_tmp), GFP_KERNEL); if (!mem_tmp) { - err("out of system memory\n"); kfree(pfmem[count]); return -ENOMEM; } @@ -508,10 +501,9 @@ static int configure_device(struct pci_func *func) debug("len[count] in Mem %x, count %d\n", len[count], count); mem[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL); - if (!mem[count]) { - err("out of system memory\n"); + if (!mem[count]) return -ENOMEM; - } + mem[count]->type = MEM; mem[count]->busno = func->busno; mem[count]->devfunc = PCI_DEVFN(func->device, @@ -674,7 +666,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno) bus_io[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL); if (!bus_io[count]) { - err("out of system memory\n"); retval = -ENOMEM; goto error; } @@ -706,7 +697,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno) bus_pfmem[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL); if (!bus_pfmem[count]) { - err("out of system memory\n"); retval = -ENOMEM; goto error; } @@ -722,7 +712,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno) } else { mem_tmp = kzalloc(sizeof(*mem_tmp), GFP_KERNEL); if (!mem_tmp) { - err("out of system memory\n"); retval = -ENOMEM; goto error; } @@ -763,7 +752,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno) bus_mem[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL); if (!bus_mem[count]) { - err("out of system memory\n"); retval = -ENOMEM; goto error; } @@ -834,7 +822,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno) io = kzalloc(sizeof(*io), GFP_KERNEL); if (!io) { - err("out of system memory\n"); retval = -ENOMEM; goto error; } @@ -856,7 +843,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno) debug("it wants %x memory behind the bridge\n", amount_needed->mem); mem = kzalloc(sizeof(*mem), GFP_KERNEL); if (!mem) { - err("out of system memory\n"); retval = -ENOMEM; goto error; } @@ -878,7 +864,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno) debug("it wants %x pfmemory behind the bridge\n", amount_needed->pfmem); pfmem = kzalloc(sizeof(*pfmem), GFP_KERNEL); if (!pfmem) { - err("out of system memory\n"); retval = -ENOMEM; goto error; } @@ -893,7 +878,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno) } else { mem_tmp = kzalloc(sizeof(*mem_tmp), GFP_KERNEL); if (!mem_tmp) { - err("out of system memory\n"); retval = -ENOMEM; goto error; } @@ -924,7 +908,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno) if (!bus) { bus = kzalloc(sizeof(*bus), GFP_KERNEL); if (!bus) { - err("out of system memory\n"); retval = -ENOMEM; goto error; } @@ -1652,10 +1635,9 @@ static int add_new_bus(struct bus_node *bus, struct resource_node *io, struct re } if (io) { io_range = kzalloc(sizeof(*io_range), GFP_KERNEL); - if (!io_range) { - err("out of system memory\n"); + if (!io_range) return -ENOMEM; - } + io_range->start = io->start; io_range->end = io->end; io_range->rangeno = 1; @@ -1664,10 +1646,9 @@ static int add_new_bus(struct bus_node *bus, struct resource_node *io, struct re } if (mem) { mem_range = kzalloc(sizeof(*mem_range), GFP_KERNEL); - if (!mem_range) { - err("out of system memory\n"); + if (!mem_range) return -ENOMEM; - } + mem_range->start = mem->start; mem_range->end = mem->end; mem_range->rangeno = 1; @@ -1676,10 +1657,9 @@ static int add_new_bus(struct bus_node *bus, struct resource_node *io, struct re } if (pfmem) { pfmem_range = kzalloc(sizeof(*pfmem_range), GFP_KERNEL); - if (!pfmem_range) { - err("out of system memory\n"); + if (!pfmem_range) return -ENOMEM; - } + pfmem_range->start = pfmem->start; pfmem_range->end = pfmem->end; pfmem_range->rangeno = 1; diff --git a/drivers/pci/hotplug/ibmphp_res.c b/drivers/pci/hotplug/ibmphp_res.c index aee6e41001e1..b58a7a641e0e 100644 --- a/drivers/pci/hotplug/ibmphp_res.c +++ b/drivers/pci/hotplug/ibmphp_res.c @@ -56,10 +56,8 @@ static struct bus_node * __init alloc_error_bus(struct ebda_pci_rsrc *curr, u8 b } newbus = kzalloc(sizeof(struct bus_node), GFP_KERNEL); - if (!newbus) { - err("out of system memory\n"); + if (!newbus) return NULL; - } if (flag) newbus->busno = busno; @@ -79,10 +77,9 @@ static struct resource_node * __init alloc_resources(struct ebda_pci_rsrc *curr) } rs = kzalloc(sizeof(struct resource_node), GFP_KERNEL); - if (!rs) { - err("out of system memory\n"); + if (!rs) return NULL; - } + rs->busno = curr->bus_num; rs->devfunc = curr->dev_fun; rs->start = curr->start_addr; @@ -99,10 +96,9 @@ static int __init alloc_bus_range(struct bus_node **new_bus, struct range_node * if (first_bus) { newbus = kzalloc(sizeof(struct bus_node), GFP_KERNEL); - if (!newbus) { - err("out of system memory.\n"); + if (!newbus) return -ENOMEM; - } + newbus->busno = curr->bus_num; } else { newbus = *new_bus; @@ -123,7 +119,6 @@ static int __init alloc_bus_range(struct bus_node **new_bus, struct range_node * if (!newrange) { if (first_bus) kfree(newbus); - err("out of system memory\n"); return -ENOMEM; } newrange->start = curr->start_addr; @@ -1707,10 +1702,9 @@ static int __init once_over(void) bus_cur->firstPFMemFromMem = pfmem_cur; mem = kzalloc(sizeof(struct resource_node), GFP_KERNEL); - if (!mem) { - err("out of system memory\n"); + if (!mem) return -ENOMEM; - } + mem->type = MEM; mem->busno = pfmem_cur->busno; mem->devfunc = pfmem_cur->devfunc; @@ -1989,10 +1983,9 @@ static int __init update_bridge_ranges(struct bus_node **bus) if ((start_address) && (start_address <= end_address)) { range = kzalloc(sizeof(struct range_node), GFP_KERNEL); - if (!range) { - err("out of system memory\n"); + if (!range) return -ENOMEM; - } + range->start = start_address; range->end = end_address + 0xfff; @@ -2016,7 +2009,6 @@ static int __init update_bridge_ranges(struct bus_node **bus) io = kzalloc(sizeof(struct resource_node), GFP_KERNEL); if (!io) { kfree(range); - err("out of system memory\n"); return -ENOMEM; } io->type = IO; @@ -2038,10 +2030,9 @@ static int __init update_bridge_ranges(struct bus_node **bus) if ((start_address) && (start_address <= end_address)) { range = kzalloc(sizeof(struct range_node), GFP_KERNEL); - if (!range) { - err("out of system memory\n"); + if (!range) return -ENOMEM; - } + range->start = start_address; range->end = end_address + 0xfffff; @@ -2066,7 +2057,6 @@ static int __init update_bridge_ranges(struct bus_node **bus) mem = kzalloc(sizeof(struct resource_node), GFP_KERNEL); if (!mem) { kfree(range); - err("out of system memory\n"); return -ENOMEM; } mem->type = MEM; @@ -2092,10 +2082,9 @@ static int __init update_bridge_ranges(struct bus_node **bus) if ((start_address) && (start_address <= end_address)) { range = kzalloc(sizeof(struct range_node), GFP_KERNEL); - if (!range) { - err("out of system memory\n"); + if (!range) return -ENOMEM; - } + range->start = start_address; range->end = end_address + 0xfffff; @@ -2119,7 +2108,6 @@ static int __init update_bridge_ranges(struct bus_node **bus) pfmem = kzalloc(sizeof(struct resource_node), GFP_KERNEL); if (!pfmem) { kfree(range); - err("out of system memory\n"); return -ENOMEM; } pfmem->type = PFMEM; diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 7bab0606f1a9..17bea7ccf6d4 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -838,16 +838,22 @@ struct controller *pcie_init(struct pcie_device *dev) struct pci_dev *pdev = dev->port; ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); - if (!ctrl) { - dev_err(&dev->device, "%s: Out of memory\n", __func__); + if (!ctrl) goto abort; - } + ctrl->pcie = dev; pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); if (pdev->hotplug_user_indicators) slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP); + /* + * We assume no Thunderbolt controllers support Command Complete events, + * but some controllers falsely claim they do. + */ + if (pdev->is_thunderbolt) + slot_cap |= PCI_EXP_SLTCAP_NCCS; + ctrl->slot_cap = slot_cap; mutex_init(&ctrl->ctrl_lock); init_waitqueue_head(&ctrl->queue); diff --git a/drivers/pci/hotplug/pciehp_pci.c b/drivers/pci/hotplug/pciehp_pci.c index 2a1ca020cf5a..acc360d1a1fb 100644 --- a/drivers/pci/hotplug/pciehp_pci.c +++ b/drivers/pci/hotplug/pciehp_pci.c @@ -79,7 +79,6 @@ int pciehp_configure_device(struct slot *p_slot) int pciehp_unconfigure_device(struct slot *p_slot) { int rc = 0; - u8 bctl = 0; u8 presence = 0; struct pci_dev *dev, *temp; struct pci_bus *parent = p_slot->ctrl->pcie->port->subordinate; @@ -101,17 +100,6 @@ int pciehp_unconfigure_device(struct slot *p_slot) list_for_each_entry_safe_reverse(dev, temp, &parent->devices, bus_list) { pci_dev_get(dev); - if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && presence) { - pci_read_config_byte(dev, PCI_BRIDGE_CONTROL, &bctl); - if (bctl & PCI_BRIDGE_CTL_VGA) { - ctrl_err(ctrl, - "Cannot remove display device %s\n", - pci_name(dev)); - pci_dev_put(dev); - rc = -EINVAL; - break; - } - } if (!presence) { pci_dev_set_disconnected(dev, NULL); if (pci_has_subordinate(dev)) diff --git a/drivers/pci/hotplug/pnv_php.c b/drivers/pci/hotplug/pnv_php.c index 74f6a17e4614..0373b9d88c6d 100644 --- a/drivers/pci/hotplug/pnv_php.c +++ b/drivers/pci/hotplug/pnv_php.c @@ -266,22 +266,18 @@ static int pnv_php_add_devtree(struct pnv_php_slot *php_slot) fdt1 = kzalloc(0x10000, GFP_KERNEL); if (!fdt1) { ret = -ENOMEM; - dev_warn(&php_slot->pdev->dev, "Cannot alloc FDT blob\n"); goto out; } ret = pnv_pci_get_device_tree(php_slot->dn->phandle, fdt1, 0x10000); if (ret) { - dev_warn(&php_slot->pdev->dev, "Error %d getting FDT blob\n", - ret); + pci_warn(php_slot->pdev, "Error %d getting FDT blob\n", ret); goto free_fdt1; } fdt = kzalloc(fdt_totalsize(fdt1), GFP_KERNEL); if (!fdt) { ret = -ENOMEM; - dev_warn(&php_slot->pdev->dev, "Cannot %d bytes memory\n", - fdt_totalsize(fdt1)); goto free_fdt1; } @@ -290,7 +286,7 @@ static int pnv_php_add_devtree(struct pnv_php_slot *php_slot) dt = of_fdt_unflatten_tree(fdt, php_slot->dn, NULL); if (!dt) { ret = -EINVAL; - dev_warn(&php_slot->pdev->dev, "Cannot unflatten FDT\n"); + pci_warn(php_slot->pdev, "Cannot unflatten FDT\n"); goto free_fdt; } @@ -300,7 +296,7 @@ static int pnv_php_add_devtree(struct pnv_php_slot *php_slot) ret = pnv_php_populate_changeset(&php_slot->ocs, php_slot->dn); if (ret) { pnv_php_reverse_nodes(php_slot->dn); - dev_warn(&php_slot->pdev->dev, "Error %d populating changeset\n", + pci_warn(php_slot->pdev, "Error %d populating changeset\n", ret); goto free_dt; } @@ -308,8 +304,7 @@ static int pnv_php_add_devtree(struct pnv_php_slot *php_slot) php_slot->dn->child = NULL; ret = of_changeset_apply(&php_slot->ocs); if (ret) { - dev_warn(&php_slot->pdev->dev, "Error %d applying changeset\n", - ret); + pci_warn(php_slot->pdev, "Error %d applying changeset\n", ret); goto destroy_changeset; } @@ -345,14 +340,14 @@ int pnv_php_set_slot_power_state(struct hotplug_slot *slot, if (be64_to_cpu(msg.params[1]) != php_slot->dn->phandle || be64_to_cpu(msg.params[2]) != state || be64_to_cpu(msg.params[3]) != OPAL_SUCCESS) { - dev_warn(&php_slot->pdev->dev, "Wrong msg (%lld, %lld, %lld)\n", + pci_warn(php_slot->pdev, "Wrong msg (%lld, %lld, %lld)\n", be64_to_cpu(msg.params[1]), be64_to_cpu(msg.params[2]), be64_to_cpu(msg.params[3])); return -ENOMSG; } } else if (ret < 0) { - dev_warn(&php_slot->pdev->dev, "Error %d powering %s\n", + pci_warn(php_slot->pdev, "Error %d powering %s\n", ret, (state == OPAL_PCI_SLOT_POWER_ON) ? "on" : "off"); return ret; } @@ -379,7 +374,7 @@ static int pnv_php_get_power_state(struct hotplug_slot *slot, u8 *state) */ ret = pnv_pci_get_power_state(php_slot->id, &power_state); if (ret) { - dev_warn(&php_slot->pdev->dev, "Error %d getting power status\n", + pci_warn(php_slot->pdev, "Error %d getting power status\n", ret); } else { *state = power_state; @@ -405,8 +400,7 @@ static int pnv_php_get_adapter_state(struct hotplug_slot *slot, u8 *state) slot->info->adapter_status = presence; ret = 0; } else { - dev_warn(&php_slot->pdev->dev, "Error %d getting presence\n", - ret); + pci_warn(php_slot->pdev, "Error %d getting presence\n", ret); } return ret; @@ -629,8 +623,7 @@ static int pnv_php_register_slot(struct pnv_php_slot *php_slot) ret = pci_hp_register(&php_slot->slot, php_slot->bus, php_slot->slot_no, php_slot->name); if (ret) { - dev_warn(&php_slot->pdev->dev, "Error %d registering slot\n", - ret); + pci_warn(php_slot->pdev, "Error %d registering slot\n", ret); return ret; } @@ -683,7 +676,7 @@ static int pnv_php_enable_msix(struct pnv_php_slot *php_slot) /* Enable MSIx */ ret = pci_enable_msix_exact(pdev, &entry, 1); if (ret) { - dev_warn(&pdev->dev, "Error %d enabling MSIx\n", ret); + pci_warn(pdev, "Error %d enabling MSIx\n", ret); return ret; } @@ -727,7 +720,7 @@ static irqreturn_t pnv_php_interrupt(int irq, void *data) (sts & PCI_EXP_SLTSTA_PDC)) { ret = pnv_pci_get_presence_state(php_slot->id, &presence); if (ret) { - dev_warn(&pdev->dev, "PCI slot [%s] error %d getting presence (0x%04x), to retry the operation.\n", + pci_warn(pdev, "PCI slot [%s] error %d getting presence (0x%04x), to retry the operation.\n", php_slot->name, ret, sts); return IRQ_HANDLED; } @@ -757,12 +750,12 @@ static irqreturn_t pnv_php_interrupt(int irq, void *data) */ event = kzalloc(sizeof(*event), GFP_ATOMIC); if (!event) { - dev_warn(&pdev->dev, "PCI slot [%s] missed hotplug event 0x%04x\n", + pci_warn(pdev, "PCI slot [%s] missed hotplug event 0x%04x\n", php_slot->name, sts); return IRQ_HANDLED; } - dev_info(&pdev->dev, "PCI slot [%s] %s (IRQ: %d)\n", + pci_info(pdev, "PCI slot [%s] %s (IRQ: %d)\n", php_slot->name, added ? "added" : "removed", irq); INIT_WORK(&event->work, pnv_php_event_handler); event->added = added; @@ -782,7 +775,7 @@ static void pnv_php_init_irq(struct pnv_php_slot *php_slot, int irq) /* Allocate workqueue */ php_slot->wq = alloc_workqueue("pciehp-%s", 0, 0, php_slot->name); if (!php_slot->wq) { - dev_warn(&pdev->dev, "Cannot alloc workqueue\n"); + pci_warn(pdev, "Cannot alloc workqueue\n"); pnv_php_disable_irq(php_slot, true); return; } @@ -806,7 +799,7 @@ static void pnv_php_init_irq(struct pnv_php_slot *php_slot, int irq) php_slot->name, php_slot); if (ret) { pnv_php_disable_irq(php_slot, true); - dev_warn(&pdev->dev, "Error %d enabling IRQ %d\n", ret, irq); + pci_warn(pdev, "Error %d enabling IRQ %d\n", ret, irq); return; } @@ -842,7 +835,7 @@ static void pnv_php_enable_irq(struct pnv_php_slot *php_slot) ret = pci_enable_device(pdev); if (ret) { - dev_warn(&pdev->dev, "Error %d enabling device\n", ret); + pci_warn(pdev, "Error %d enabling device\n", ret); return; } diff --git a/drivers/pci/hotplug/sgi_hotplug.c b/drivers/pci/hotplug/sgi_hotplug.c index 339bce0403dd..293bd03eb167 100644 --- a/drivers/pci/hotplug/sgi_hotplug.c +++ b/drivers/pci/hotplug/sgi_hotplug.c @@ -245,18 +245,18 @@ static int sn_slot_enable(struct hotplug_slot *bss_hotplug_slot, if (rc == PCI_SLOT_ALREADY_UP) { - dev_dbg(&slot->pci_bus->self->dev, "is already active\n"); + pci_dbg(slot->pci_bus->self, "is already active\n"); return 1; /* return 1 to user */ } if (rc == PCI_L1_ERR) { - dev_dbg(&slot->pci_bus->self->dev, "L1 failure %d with message: %s", + pci_dbg(slot->pci_bus->self, "L1 failure %d with message: %s", resp.resp_sub_errno, resp.resp_l1_msg); return -EPERM; } if (rc) { - dev_dbg(&slot->pci_bus->self->dev, "insert failed with error %d sub-error %d\n", + pci_dbg(slot->pci_bus->self, "insert failed with error %d sub-error %d\n", rc, resp.resp_sub_errno); return -EIO; } @@ -281,23 +281,23 @@ static int sn_slot_disable(struct hotplug_slot *bss_hotplug_slot, if ((action == PCI_REQ_SLOT_ELIGIBLE) && (rc == PCI_SLOT_ALREADY_DOWN)) { - dev_dbg(&slot->pci_bus->self->dev, "Slot %s already inactive\n", slot->physical_path); + pci_dbg(slot->pci_bus->self, "Slot %s already inactive\n", slot->physical_path); return 1; /* return 1 to user */ } if ((action == PCI_REQ_SLOT_ELIGIBLE) && (rc == PCI_EMPTY_33MHZ)) { - dev_dbg(&slot->pci_bus->self->dev, "Cannot remove last 33MHz card\n"); + pci_dbg(slot->pci_bus->self, "Cannot remove last 33MHz card\n"); return -EPERM; } if ((action == PCI_REQ_SLOT_ELIGIBLE) && (rc == PCI_L1_ERR)) { - dev_dbg(&slot->pci_bus->self->dev, "L1 failure %d with message \n%s\n", + pci_dbg(slot->pci_bus->self, "L1 failure %d with message \n%s\n", resp.resp_sub_errno, resp.resp_l1_msg); return -EPERM; } if ((action == PCI_REQ_SLOT_ELIGIBLE) && rc) { - dev_dbg(&slot->pci_bus->self->dev, "remove failed with error %d sub-error %d\n", + pci_dbg(slot->pci_bus->self, "remove failed with error %d sub-error %d\n", rc, resp.resp_sub_errno); return -EIO; } @@ -308,12 +308,12 @@ static int sn_slot_disable(struct hotplug_slot *bss_hotplug_slot, if ((action == PCI_REQ_SLOT_DISABLE) && !rc) { pcibus_info = SN_PCIBUS_BUSSOFT_INFO(slot->pci_bus); pcibus_info->pbi_enabled_devices &= ~(1 << device_num); - dev_dbg(&slot->pci_bus->self->dev, "remove successful\n"); + pci_dbg(slot->pci_bus->self, "remove successful\n"); return 0; } if ((action == PCI_REQ_SLOT_DISABLE) && rc) { - dev_dbg(&slot->pci_bus->self->dev, "remove failed rc = %d\n", rc); + pci_dbg(slot->pci_bus->self, "remove failed rc = %d\n", rc); } return rc; @@ -366,7 +366,7 @@ static int enable_slot(struct hotplug_slot *bss_hotplug_slot) num_funcs = pci_scan_slot(slot->pci_bus, PCI_DEVFN(slot->device_num + 1, 0)); if (!num_funcs) { - dev_dbg(&slot->pci_bus->self->dev, "no device in slot\n"); + pci_dbg(slot->pci_bus->self, "no device in slot\n"); mutex_unlock(&sn_hotplug_mutex); return -ENODEV; } @@ -412,7 +412,7 @@ static int enable_slot(struct hotplug_slot *bss_hotplug_slot) phandle = acpi_device_handle(PCI_CONTROLLER(slot->pci_bus)->companion); if (acpi_bus_get_device(phandle, &pdevice)) { - dev_dbg(&slot->pci_bus->self->dev, "no parent device, assuming NULL\n"); + pci_dbg(slot->pci_bus->self, "no parent device, assuming NULL\n"); pdevice = NULL; } @@ -463,9 +463,9 @@ static int enable_slot(struct hotplug_slot *bss_hotplug_slot) mutex_unlock(&sn_hotplug_mutex); if (rc == 0) - dev_dbg(&slot->pci_bus->self->dev, "insert operation successful\n"); + pci_dbg(slot->pci_bus->self, "insert operation successful\n"); else - dev_dbg(&slot->pci_bus->self->dev, "insert operation failed rc = %d\n", rc); + pci_dbg(slot->pci_bus->self, "insert operation failed rc = %d\n", rc); return rc; } @@ -643,16 +643,16 @@ static int sn_hotplug_slot_register(struct pci_bus *pci_bus) if (rc) goto register_err; } - dev_dbg(&pci_bus->self->dev, "Registered bus with hotplug\n"); + pci_dbg(pci_bus->self, "Registered bus with hotplug\n"); return rc; register_err: - dev_dbg(&pci_bus->self->dev, "bus failed to register with err = %d\n", + pci_dbg(pci_bus->self, "bus failed to register with err = %d\n", rc); alloc_err: if (rc == -ENOMEM) - dev_dbg(&pci_bus->self->dev, "Memory allocation error\n"); + pci_dbg(pci_bus->self, "Memory allocation error\n"); /* destroy THIS element */ if (bss_hotplug_slot) @@ -685,10 +685,10 @@ static int __init sn_pci_hotplug_init(void) rc = sn_pci_bus_valid(pci_bus); if (rc != 1) { - dev_dbg(&pci_bus->self->dev, "not a valid hotplug bus\n"); + pci_dbg(pci_bus->self, "not a valid hotplug bus\n"); continue; } - dev_dbg(&pci_bus->self->dev, "valid hotplug bus\n"); + pci_dbg(pci_bus->self, "valid hotplug bus\n"); rc = sn_hotplug_slot_register(pci_bus); if (!rc) { diff --git a/drivers/pci/hotplug/shpchp.h b/drivers/pci/hotplug/shpchp.h index 70c7ea6af034..664b1dafc95d 100644 --- a/drivers/pci/hotplug/shpchp.h +++ b/drivers/pci/hotplug/shpchp.h @@ -62,15 +62,15 @@ do { \ #define ctrl_dbg(ctrl, format, arg...) \ do { \ if (shpchp_debug) \ - dev_printk(KERN_DEBUG, &ctrl->pci_dev->dev, \ + pci_printk(KERN_DEBUG, ctrl->pci_dev, \ format, ## arg); \ } while (0) #define ctrl_err(ctrl, format, arg...) \ - dev_err(&ctrl->pci_dev->dev, format, ## arg) + pci_err(ctrl->pci_dev, format, ## arg) #define ctrl_info(ctrl, format, arg...) \ - dev_info(&ctrl->pci_dev->dev, format, ## arg) + pci_info(ctrl->pci_dev, format, ## arg) #define ctrl_warn(ctrl, format, arg...) \ - dev_warn(&ctrl->pci_dev->dev, format, ## arg) + pci_warn(ctrl->pci_dev, format, ## arg) #define SLOT_NAME_SIZE 10 diff --git a/drivers/pci/hotplug/shpchp_core.c b/drivers/pci/hotplug/shpchp_core.c index 7bfb87bd2b7e..2f2b87acf179 100644 --- a/drivers/pci/hotplug/shpchp_core.c +++ b/drivers/pci/hotplug/shpchp_core.c @@ -305,10 +305,9 @@ static int shpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent) return -ENODEV; ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); - if (!ctrl) { - dev_err(&pdev->dev, "%s: Out of memory\n", __func__); + if (!ctrl) goto err_out_none; - } + INIT_LIST_HEAD(&ctrl->slot_list); rc = shpc_init(ctrl, pdev); diff --git a/drivers/pci/hotplug/shpchp_pci.c b/drivers/pci/hotplug/shpchp_pci.c index ea63db58b4b1..79f1682c858e 100644 --- a/drivers/pci/hotplug/shpchp_pci.c +++ b/drivers/pci/hotplug/shpchp_pci.c @@ -78,7 +78,6 @@ int shpchp_configure_device(struct slot *p_slot) int shpchp_unconfigure_device(struct slot *p_slot) { int rc = 0; - u8 bctl = 0; struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate; struct pci_dev *dev, *temp; struct controller *ctrl = p_slot->ctrl; @@ -93,17 +92,6 @@ int shpchp_unconfigure_device(struct slot *p_slot) continue; pci_dev_get(dev); - if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { - pci_read_config_byte(dev, PCI_BRIDGE_CONTROL, &bctl); - if (bctl & PCI_BRIDGE_CTL_VGA) { - ctrl_err(ctrl, - "Cannot remove display device %s\n", - pci_name(dev)); - pci_dev_put(dev); - rc = -EINVAL; - break; - } - } pci_stop_and_remove_bus_device(dev); pci_dev_put(dev); } diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 6bacb8995e96..449a9dbb952d 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -259,19 +259,19 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn) nres++; } if (nres != iov->nres) { - dev_err(&dev->dev, "not enough MMIO resources for SR-IOV\n"); + pci_err(dev, "not enough MMIO resources for SR-IOV\n"); return -ENOMEM; } bus = pci_iov_virtfn_bus(dev, nr_virtfn - 1); if (bus > dev->bus->busn_res.end) { - dev_err(&dev->dev, "can't enable %d VFs (bus %02x out of range of %pR)\n", + pci_err(dev, "can't enable %d VFs (bus %02x out of range of %pR)\n", nr_virtfn, bus, &dev->bus->busn_res); return -ENOMEM; } if (pci_enable_resources(dev, bars)) { - dev_err(&dev->dev, "SR-IOV: IOV BARS not allocated\n"); + pci_err(dev, "SR-IOV: IOV BARS not allocated\n"); return -ENOMEM; } @@ -298,7 +298,7 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn) rc = pcibios_sriov_enable(dev, initial); if (rc) { - dev_err(&dev->dev, "failure %d from pcibios_sriov_enable()\n", rc); + pci_err(dev, "failure %d from pcibios_sriov_enable()\n", rc); goto err_pcibios; } @@ -432,7 +432,7 @@ found: } iov->barsz[i] = resource_size(res); res->end = res->start + resource_size(res) * total - 1; - dev_info(&dev->dev, "VF(n) BAR%d space: %pR (contains BAR%d for %d VFs)\n", + pci_info(dev, "VF(n) BAR%d space: %pR (contains BAR%d for %d VFs)\n", i, res, i, total); i += bar64; nres++; diff --git a/drivers/pci/irq.c b/drivers/pci/irq.c index 10929cd43d5d..2a808e10645f 100644 --- a/drivers/pci/irq.c +++ b/drivers/pci/irq.c @@ -16,11 +16,10 @@ static void pci_note_irq_problem(struct pci_dev *pdev, const char *reason) { struct pci_dev *parent = to_pci_dev(pdev->dev.parent); - dev_err(&pdev->dev, - "Potentially misrouted IRQ (Bridge %s %04x:%04x)\n", + pci_err(pdev, "Potentially misrouted IRQ (Bridge %s %04x:%04x)\n", dev_name(&parent->dev), parent->vendor, parent->device); - dev_err(&pdev->dev, "%s\n", reason); - dev_err(&pdev->dev, "Please report to linux-kernel@vger.kernel.org\n"); + pci_err(pdev, "%s\n", reason); + pci_err(pdev, "Please report to linux-kernel@vger.kernel.org\n"); WARN_ON(1); } diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c index e06607167858..1cd8238a664a 100644 --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -578,7 +578,7 @@ static int msi_verify_entries(struct pci_dev *dev) for_each_pci_msi_entry(entry, dev) { if (!dev->no_64bit_msi || !entry->msg.address_hi) continue; - dev_err(&dev->dev, "Device has broken 64-bit MSI but arch" + pci_err(dev, "Device has broken 64-bit MSI but arch" " tried to assign one above 4G\n"); return -EIO; } @@ -962,7 +962,7 @@ static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, /* Check whether driver already requested for MSI irq */ if (dev->msi_enabled) { - dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); + pci_info(dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); return -EINVAL; } return msix_capability_init(dev, entries, nvec, affd); @@ -1032,8 +1032,7 @@ static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, /* Check whether driver already requested MSI-X irqs */ if (dev->msix_enabled) { - dev_info(&dev->dev, - "can't enable MSI (MSI-X already enabled)\n"); + pci_info(dev, "can't enable MSI (MSI-X already enabled)\n"); return -EINVAL; } diff --git a/drivers/pci/of.c b/drivers/pci/of.c index e112da11630e..e81835bdf4fa 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -8,12 +8,14 @@ * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ +#define pr_fmt(fmt) "PCI: OF: " fmt #include <linux/irqdomain.h> #include <linux/kernel.h> #include <linux/pci.h> #include <linux/of.h> #include <linux/of_irq.h> +#include <linux/of_address.h> #include <linux/of_pci.h> #include "pci.h" @@ -51,8 +53,9 @@ struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus) if (WARN_ON(bus->self || bus->parent)) return NULL; - /* Look for a node pointer in either the intermediary device we - * create above the root bus or it's own parent. Normally only + /* + * Look for a node pointer in either the intermediary device we + * create above the root bus or its own parent. Normally only * the later is populated. */ if (bus->bridge->of_node) @@ -88,3 +91,510 @@ struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus) return NULL; #endif } + + +static inline int __of_pci_pci_compare(struct device_node *node, + unsigned int data) +{ + int devfn; + + devfn = of_pci_get_devfn(node); + if (devfn < 0) + return 0; + + return devfn == data; +} + +struct device_node *of_pci_find_child_device(struct device_node *parent, + unsigned int devfn) +{ + struct device_node *node, *node2; + + for_each_child_of_node(parent, node) { + if (__of_pci_pci_compare(node, devfn)) + return node; + /* + * Some OFs create a parent node "multifunc-device" as + * a fake root for all functions of a multi-function + * device we go down them as well. + */ + if (!strcmp(node->name, "multifunc-device")) { + for_each_child_of_node(node, node2) { + if (__of_pci_pci_compare(node2, devfn)) { + of_node_put(node); + return node2; + } + } + } + } + return NULL; +} +EXPORT_SYMBOL_GPL(of_pci_find_child_device); + +/** + * of_pci_get_devfn() - Get device and function numbers for a device node + * @np: device node + * + * Parses a standard 5-cell PCI resource and returns an 8-bit value that can + * be passed to the PCI_SLOT() and PCI_FUNC() macros to extract the device + * and function numbers respectively. On error a negative error code is + * returned. + */ +int of_pci_get_devfn(struct device_node *np) +{ + u32 reg[5]; + int error; + + error = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg)); + if (error) + return error; + + return (reg[0] >> 8) & 0xff; +} +EXPORT_SYMBOL_GPL(of_pci_get_devfn); + +/** + * of_pci_parse_bus_range() - parse the bus-range property of a PCI device + * @node: device node + * @res: address to a struct resource to return the bus-range + * + * Returns 0 on success or a negative error-code on failure. + */ +int of_pci_parse_bus_range(struct device_node *node, struct resource *res) +{ + u32 bus_range[2]; + int error; + + error = of_property_read_u32_array(node, "bus-range", bus_range, + ARRAY_SIZE(bus_range)); + if (error) + return error; + + res->name = node->name; + res->start = bus_range[0]; + res->end = bus_range[1]; + res->flags = IORESOURCE_BUS; + + return 0; +} +EXPORT_SYMBOL_GPL(of_pci_parse_bus_range); + +/** + * This function will try to obtain the host bridge domain number by + * finding a property called "linux,pci-domain" of the given device node. + * + * @node: device tree node with the domain information + * + * Returns the associated domain number from DT in the range [0-0xffff], or + * a negative value if the required property is not found. + */ +int of_get_pci_domain_nr(struct device_node *node) +{ + u32 domain; + int error; + + error = of_property_read_u32(node, "linux,pci-domain", &domain); + if (error) + return error; + + return (u16)domain; +} +EXPORT_SYMBOL_GPL(of_get_pci_domain_nr); + +/** + * This function will try to find the limitation of link speed by finding + * a property called "max-link-speed" of the given device node. + * + * @node: device tree node with the max link speed information + * + * Returns the associated max link speed from DT, or a negative value if the + * required property is not found or is invalid. + */ +int of_pci_get_max_link_speed(struct device_node *node) +{ + u32 max_link_speed; + + if (of_property_read_u32(node, "max-link-speed", &max_link_speed) || + max_link_speed > 4) + return -EINVAL; + + return max_link_speed; +} +EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed); + +/** + * of_pci_check_probe_only - Setup probe only mode if linux,pci-probe-only + * is present and valid + */ +void of_pci_check_probe_only(void) +{ + u32 val; + int ret; + + ret = of_property_read_u32(of_chosen, "linux,pci-probe-only", &val); + if (ret) { + if (ret == -ENODATA || ret == -EOVERFLOW) + pr_warn("linux,pci-probe-only without valid value, ignoring\n"); + return; + } + + if (val) + pci_add_flags(PCI_PROBE_ONLY); + else + pci_clear_flags(PCI_PROBE_ONLY); + + pr_info("PROBE_ONLY %sabled\n", val ? "en" : "dis"); +} +EXPORT_SYMBOL_GPL(of_pci_check_probe_only); + +#if defined(CONFIG_OF_ADDRESS) +/** + * of_pci_get_host_bridge_resources - Parse PCI host bridge resources from DT + * @dev: device node of the host bridge having the range property + * @busno: bus number associated with the bridge root bus + * @bus_max: maximum number of buses for this bridge + * @resources: list where the range of resources will be added after DT parsing + * @io_base: pointer to a variable that will contain on return the physical + * address for the start of the I/O range. Can be NULL if the caller doesn't + * expect I/O ranges to be present in the device tree. + * + * It is the caller's job to free the @resources list. + * + * This function will parse the "ranges" property of a PCI host bridge device + * node and setup the resource mapping based on its content. It is expected + * that the property conforms with the Power ePAPR document. + * + * It returns zero if the range parsing has been successful or a standard error + * value if it failed. + */ +int of_pci_get_host_bridge_resources(struct device_node *dev, + unsigned char busno, unsigned char bus_max, + struct list_head *resources, resource_size_t *io_base) +{ + struct resource_entry *window; + struct resource *res; + struct resource *bus_range; + struct of_pci_range range; + struct of_pci_range_parser parser; + char range_type[4]; + int err; + + if (io_base) + *io_base = (resource_size_t)OF_BAD_ADDR; + + bus_range = kzalloc(sizeof(*bus_range), GFP_KERNEL); + if (!bus_range) + return -ENOMEM; + + pr_info("host bridge %pOF ranges:\n", dev); + + err = of_pci_parse_bus_range(dev, bus_range); + if (err) { + bus_range->start = busno; + bus_range->end = bus_max; + bus_range->flags = IORESOURCE_BUS; + pr_info(" No bus range found for %pOF, using %pR\n", + dev, bus_range); + } else { + if (bus_range->end > bus_range->start + bus_max) + bus_range->end = bus_range->start + bus_max; + } + pci_add_resource(resources, bus_range); + + /* Check for ranges property */ + err = of_pci_range_parser_init(&parser, dev); + if (err) + goto parse_failed; + + pr_debug("Parsing ranges property...\n"); + for_each_of_pci_range(&parser, &range) { + /* Read next ranges element */ + if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO) + snprintf(range_type, 4, " IO"); + else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM) + snprintf(range_type, 4, "MEM"); + else + snprintf(range_type, 4, "err"); + pr_info(" %s %#010llx..%#010llx -> %#010llx\n", range_type, + range.cpu_addr, range.cpu_addr + range.size - 1, + range.pci_addr); + + /* + * If we failed translation or got a zero-sized region + * then skip this range + */ + if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) + continue; + + res = kzalloc(sizeof(struct resource), GFP_KERNEL); + if (!res) { + err = -ENOMEM; + goto parse_failed; + } + + err = of_pci_range_to_resource(&range, dev, res); + if (err) { + kfree(res); + continue; + } + + if (resource_type(res) == IORESOURCE_IO) { + if (!io_base) { + pr_err("I/O range found for %pOF. Please provide an io_base pointer to save CPU base address\n", + dev); + err = -EINVAL; + goto conversion_failed; + } + if (*io_base != (resource_size_t)OF_BAD_ADDR) + pr_warn("More than one I/O resource converted for %pOF. CPU base address for old range lost!\n", + dev); + *io_base = range.cpu_addr; + } + + pci_add_resource_offset(resources, res, res->start - range.pci_addr); + } + + return 0; + +conversion_failed: + kfree(res); +parse_failed: + resource_list_for_each_entry(window, resources) + kfree(window->res); + pci_free_resource_list(resources); + return err; +} +EXPORT_SYMBOL_GPL(of_pci_get_host_bridge_resources); +#endif /* CONFIG_OF_ADDRESS */ + +/** + * of_pci_map_rid - Translate a requester ID through a downstream mapping. + * @np: root complex device node. + * @rid: PCI requester ID to map. + * @map_name: property name of the map to use. + * @map_mask_name: optional property name of the mask to use. + * @target: optional pointer to a target device node. + * @id_out: optional pointer to receive the translated ID. + * + * Given a PCI requester ID, look up the appropriate implementation-defined + * platform ID and/or the target device which receives transactions on that + * ID, as per the "iommu-map" and "msi-map" bindings. Either of @target or + * @id_out may be NULL if only the other is required. If @target points to + * a non-NULL device node pointer, only entries targeting that node will be + * matched; if it points to a NULL value, it will receive the device node of + * the first matching target phandle, with a reference held. + * + * Return: 0 on success or a standard error code on failure. + */ +int of_pci_map_rid(struct device_node *np, u32 rid, + const char *map_name, const char *map_mask_name, + struct device_node **target, u32 *id_out) +{ + u32 map_mask, masked_rid; + int map_len; + const __be32 *map = NULL; + + if (!np || !map_name || (!target && !id_out)) + return -EINVAL; + + map = of_get_property(np, map_name, &map_len); + if (!map) { + if (target) + return -ENODEV; + /* Otherwise, no map implies no translation */ + *id_out = rid; + return 0; + } + + if (!map_len || map_len % (4 * sizeof(*map))) { + pr_err("%pOF: Error: Bad %s length: %d\n", np, + map_name, map_len); + return -EINVAL; + } + + /* The default is to select all bits. */ + map_mask = 0xffffffff; + + /* + * Can be overridden by "{iommu,msi}-map-mask" property. + * If of_property_read_u32() fails, the default is used. + */ + if (map_mask_name) + of_property_read_u32(np, map_mask_name, &map_mask); + + masked_rid = map_mask & rid; + for ( ; map_len > 0; map_len -= 4 * sizeof(*map), map += 4) { + struct device_node *phandle_node; + u32 rid_base = be32_to_cpup(map + 0); + u32 phandle = be32_to_cpup(map + 1); + u32 out_base = be32_to_cpup(map + 2); + u32 rid_len = be32_to_cpup(map + 3); + + if (rid_base & ~map_mask) { + pr_err("%pOF: Invalid %s translation - %s-mask (0x%x) ignores rid-base (0x%x)\n", + np, map_name, map_name, + map_mask, rid_base); + return -EFAULT; + } + + if (masked_rid < rid_base || masked_rid >= rid_base + rid_len) + continue; + + phandle_node = of_find_node_by_phandle(phandle); + if (!phandle_node) + return -ENODEV; + + if (target) { + if (*target) + of_node_put(phandle_node); + else + *target = phandle_node; + + if (*target != phandle_node) + continue; + } + + if (id_out) + *id_out = masked_rid - rid_base + out_base; + + pr_debug("%pOF: %s, using mask %08x, rid-base: %08x, out-base: %08x, length: %08x, rid: %08x -> %08x\n", + np, map_name, map_mask, rid_base, out_base, + rid_len, rid, masked_rid - rid_base + out_base); + return 0; + } + + pr_err("%pOF: Invalid %s translation - no match for rid 0x%x on %pOF\n", + np, map_name, rid, target && *target ? *target : NULL); + return -EFAULT; +} + +#if IS_ENABLED(CONFIG_OF_IRQ) +/** + * of_irq_parse_pci - Resolve the interrupt for a PCI device + * @pdev: the device whose interrupt is to be resolved + * @out_irq: structure of_irq filled by this function + * + * This function resolves the PCI interrupt for a given PCI device. If a + * device-node exists for a given pci_dev, it will use normal OF tree + * walking. If not, it will implement standard swizzling and walk up the + * PCI tree until an device-node is found, at which point it will finish + * resolving using the OF tree walking. + */ +static int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq) +{ + struct device_node *dn, *ppnode; + struct pci_dev *ppdev; + __be32 laddr[3]; + u8 pin; + int rc; + + /* + * Check if we have a device node, if yes, fallback to standard + * device tree parsing + */ + dn = pci_device_to_OF_node(pdev); + if (dn) { + rc = of_irq_parse_one(dn, 0, out_irq); + if (!rc) + return rc; + } + + /* + * Ok, we don't, time to have fun. Let's start by building up an + * interrupt spec. we assume #interrupt-cells is 1, which is standard + * for PCI. If you do different, then don't use that routine. + */ + rc = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin); + if (rc != 0) + goto err; + /* No pin, exit with no error message. */ + if (pin == 0) + return -ENODEV; + + /* Now we walk up the PCI tree */ + for (;;) { + /* Get the pci_dev of our parent */ + ppdev = pdev->bus->self; + + /* Ouch, it's a host bridge... */ + if (ppdev == NULL) { + ppnode = pci_bus_to_OF_node(pdev->bus); + + /* No node for host bridge ? give up */ + if (ppnode == NULL) { + rc = -EINVAL; + goto err; + } + } else { + /* We found a P2P bridge, check if it has a node */ + ppnode = pci_device_to_OF_node(ppdev); + } + + /* + * Ok, we have found a parent with a device-node, hand over to + * the OF parsing code. + * We build a unit address from the linux device to be used for + * resolution. Note that we use the linux bus number which may + * not match your firmware bus numbering. + * Fortunately, in most cases, interrupt-map-mask doesn't + * include the bus number as part of the matching. + * You should still be careful about that though if you intend + * to rely on this function (you ship a firmware that doesn't + * create device nodes for all PCI devices). + */ + if (ppnode) + break; + + /* + * We can only get here if we hit a P2P bridge with no node; + * let's do standard swizzling and try again + */ + pin = pci_swizzle_interrupt_pin(pdev, pin); + pdev = ppdev; + } + + out_irq->np = ppnode; + out_irq->args_count = 1; + out_irq->args[0] = pin; + laddr[0] = cpu_to_be32((pdev->bus->number << 16) | (pdev->devfn << 8)); + laddr[1] = laddr[2] = cpu_to_be32(0); + rc = of_irq_parse_raw(laddr, out_irq); + if (rc) + goto err; + return 0; +err: + if (rc == -ENOENT) { + dev_warn(&pdev->dev, + "%s: no interrupt-map found, INTx interrupts not available\n", + __func__); + pr_warn_once("%s: possibly some PCI slots don't have level triggered interrupts capability\n", + __func__); + } else { + dev_err(&pdev->dev, "%s: failed with rc=%d\n", __func__, rc); + } + return rc; +} + +/** + * of_irq_parse_and_map_pci() - Decode a PCI IRQ from the device tree and map to a VIRQ + * @dev: The PCI device needing an IRQ + * @slot: PCI slot number; passed when used as map_irq callback. Unused + * @pin: PCI IRQ pin number; passed when used as map_irq callback. Unused + * + * @slot and @pin are unused, but included in the function so that this + * function can be used directly as the map_irq callback to + * pci_assign_irq() and struct pci_host_bridge.map_irq pointer + */ +int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin) +{ + struct of_phandle_args oirq; + int ret; + + ret = of_irq_parse_pci(dev, &oirq); + if (ret) + return 0; /* Proper return code 0 == NO_IRQ */ + + return irq_create_of_mapping(&oirq); +} +EXPORT_SYMBOL_GPL(of_irq_parse_and_map_pci); +#endif /* CONFIG_OF_IRQ */ diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 4708eb9df71b..189e6ccf3589 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -542,7 +542,7 @@ static int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) } if (!error) - dev_dbg(&dev->dev, "power state changed by ACPI to %s\n", + pci_dbg(dev, "power state changed by ACPI to %s\n", acpi_power_state_string(state_conv[state])); return error; diff --git a/drivers/pci/pci-stub.c b/drivers/pci/pci-stub.c index 886fb3570278..e51789e2b6c7 100644 --- a/drivers/pci/pci-stub.c +++ b/drivers/pci/pci-stub.c @@ -28,7 +28,7 @@ MODULE_PARM_DESC(ids, "Initial PCI IDs to add to the stub driver, format is " static int pci_stub_probe(struct pci_dev *dev, const struct pci_device_id *id) { - dev_info(&dev->dev, "claimed by stub\n"); + pci_info(dev, "claimed by stub\n"); return 0; } diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index ccc0e28c6678..7b282f4ba8dc 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -348,7 +348,7 @@ static ssize_t numa_node_store(struct device *dev, return -EINVAL; add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); - dev_alert(&pdev->dev, FW_BUG "Overriding NUMA node to %d. Contact your vendor for updates.", + pci_alert(pdev, FW_BUG "Overriding NUMA node to %d. Contact your vendor for updates.", node); dev->numa_node = node; @@ -411,7 +411,7 @@ static ssize_t msi_bus_store(struct device *dev, struct device_attribute *attr, */ if (!subordinate) { pdev->no_msi = !val; - dev_info(&pdev->dev, "MSI/MSI-X %s for future drivers\n", + pci_info(pdev, "MSI/MSI-X %s for future drivers\n", val ? "allowed" : "disallowed"); return count; } @@ -613,7 +613,7 @@ static ssize_t sriov_numvfs_store(struct device *dev, /* is PF driver loaded w/callback */ if (!pdev->driver || !pdev->driver->sriov_configure) { - dev_info(&pdev->dev, "Driver doesn't support SRIOV configuration via sysfs\n"); + pci_info(pdev, "Driver doesn't support SRIOV configuration via sysfs\n"); ret = -ENOENT; goto exit; } @@ -626,7 +626,7 @@ static ssize_t sriov_numvfs_store(struct device *dev, /* enable VFs */ if (pdev->sriov->num_VFs) { - dev_warn(&pdev->dev, "%d VFs already enabled. Disable before enabling %d VFs\n", + pci_warn(pdev, "%d VFs already enabled. Disable before enabling %d VFs\n", pdev->sriov->num_VFs, num_vfs); ret = -EBUSY; goto exit; @@ -637,7 +637,7 @@ static ssize_t sriov_numvfs_store(struct device *dev, goto exit; if (ret != num_vfs) - dev_warn(&pdev->dev, "%d VFs requested; only %d enabled\n", + pci_warn(pdev, "%d VFs requested; only %d enabled\n", num_vfs, ret); exit: diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 4a7c6864fdf4..364717edd992 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -156,7 +156,7 @@ void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) * Make sure the BAR is actually a memory resource, not an IO resource */ if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { - dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res); + pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res); return NULL; } return ioremap_nocache(res->start, resource_size(res)); @@ -648,7 +648,7 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) */ if (state != PCI_D0 && dev->current_state <= PCI_D3cold && dev->current_state > state) { - dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n", + pci_err(dev, "invalid power transition (from state %d to %d)\n", dev->current_state, state); return -EINVAL; } @@ -696,7 +696,7 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); if (dev->current_state != state && printk_ratelimit()) - dev_info(&dev->dev, "Refused to change power state, currently in D%d\n", + pci_info(dev, "Refused to change power state, currently in D%d\n", dev->current_state); /* @@ -970,7 +970,7 @@ pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) case PM_EVENT_HIBERNATE: return PCI_D3hot; default: - dev_info(&dev->dev, "unrecognized suspend event %d\n", + pci_info(dev, "unrecognized suspend event %d\n", state.event); BUG(); } @@ -1013,7 +1013,7 @@ static int pci_save_pcie_state(struct pci_dev *dev) save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); if (!save_state) { - dev_err(&dev->dev, "buffer not found in %s\n", __func__); + pci_err(dev, "buffer not found in %s\n", __func__); return -ENOMEM; } @@ -1061,7 +1061,7 @@ static int pci_save_pcix_state(struct pci_dev *dev) save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); if (!save_state) { - dev_err(&dev->dev, "buffer not found in %s\n", __func__); + pci_err(dev, "buffer not found in %s\n", __func__); return -ENOMEM; } @@ -1121,7 +1121,7 @@ static void pci_restore_config_dword(struct pci_dev *pdev, int offset, return; for (;;) { - dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n", + pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n", offset, val, saved_val); pci_write_config_dword(pdev, offset, saved_val); if (retry-- <= 0) @@ -1358,7 +1358,7 @@ static void pci_enable_bridge(struct pci_dev *dev) retval = pci_enable_device(dev); if (retval) - dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n", + pci_err(dev, "Error enabling bridge (%d), continuing\n", retval); pci_set_master(dev); } @@ -1863,7 +1863,7 @@ void pci_pme_active(struct pci_dev *dev, bool enable) pme_dev = kmalloc(sizeof(struct pci_pme_device), GFP_KERNEL); if (!pme_dev) { - dev_warn(&dev->dev, "can't enable PME#\n"); + pci_warn(dev, "can't enable PME#\n"); return; } pme_dev->dev = dev; @@ -1887,7 +1887,7 @@ void pci_pme_active(struct pci_dev *dev, bool enable) } } - dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled"); + pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled"); } EXPORT_SYMBOL(pci_pme_active); @@ -2424,7 +2424,7 @@ void pci_pm_init(struct pci_dev *dev) pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { - dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", + pci_err(dev, "unsupported PM cap regs version (%u)\n", pmc & PCI_PM_CAP_VER_MASK); return; } @@ -2444,15 +2444,14 @@ void pci_pm_init(struct pci_dev *dev) dev->d2_support = true; if (dev->d1_support || dev->d2_support) - dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", + pci_printk(KERN_DEBUG, dev, "supports%s%s\n", dev->d1_support ? " D1" : "", dev->d2_support ? " D2" : ""); } pmc &= PCI_PM_CAP_PME_MASK; if (pmc) { - dev_printk(KERN_DEBUG, &dev->dev, - "PME# supported from%s%s%s%s%s\n", + pci_printk(KERN_DEBUG, dev, "PME# supported from%s%s%s%s%s\n", (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", @@ -2544,13 +2543,13 @@ static int pci_ea_read(struct pci_dev *dev, int offset) res = pci_ea_get_resource(dev, bei, prop); if (!res) { - dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei); + pci_err(dev, "Unsupported EA entry BEI: %u\n", bei); goto out; } flags = pci_ea_flags(dev, prop); if (!flags) { - dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop); + pci_err(dev, "Unsupported EA properties: %#x\n", prop); goto out; } @@ -2600,13 +2599,12 @@ static int pci_ea_read(struct pci_dev *dev, int offset) } if (end < start) { - dev_err(&dev->dev, "EA Entry crosses address boundary\n"); + pci_err(dev, "EA Entry crosses address boundary\n"); goto out; } if (ent_size != ent_offset - offset) { - dev_err(&dev->dev, - "EA Entry Size (%d) does not match length read (%d)\n", + pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n", ent_size, ent_offset - offset); goto out; } @@ -2617,16 +2615,16 @@ static int pci_ea_read(struct pci_dev *dev, int offset) res->flags = flags; if (bei <= PCI_EA_BEI_BAR5) - dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", + pci_printk(KERN_DEBUG, dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", bei, res, prop); else if (bei == PCI_EA_BEI_ROM) - dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n", + pci_printk(KERN_DEBUG, dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n", res, prop); else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5) - dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", + pci_printk(KERN_DEBUG, dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", bei - PCI_EA_BEI_VF_BAR0, res, prop); else - dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n", + pci_printk(KERN_DEBUG, dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n", bei, res, prop); out: @@ -2723,13 +2721,11 @@ void pci_allocate_cap_save_buffers(struct pci_dev *dev) error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, PCI_EXP_SAVE_REGS * sizeof(u16)); if (error) - dev_err(&dev->dev, - "unable to preallocate PCI Express save buffer\n"); + pci_err(dev, "unable to preallocate PCI Express save buffer\n"); error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); if (error) - dev_err(&dev->dev, - "unable to preallocate PCI-X save buffer\n"); + pci_err(dev, "unable to preallocate PCI-X save buffer\n"); pci_allocate_vc_save_buffers(dev); } @@ -3066,6 +3062,81 @@ int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) } /** + * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port + * @dev: the PCI device + * @cap_mask: mask of desired AtomicOp sizes, including one or more of: + * PCI_EXP_DEVCAP2_ATOMIC_COMP32 + * PCI_EXP_DEVCAP2_ATOMIC_COMP64 + * PCI_EXP_DEVCAP2_ATOMIC_COMP128 + * + * Return 0 if all upstream bridges support AtomicOp routing, egress + * blocking is disabled on all upstream ports, and the root port supports + * the requested completion capabilities (32-bit, 64-bit and/or 128-bit + * AtomicOp completion), or negative otherwise. + */ +int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) +{ + struct pci_bus *bus = dev->bus; + struct pci_dev *bridge; + u32 cap, ctl2; + + if (!pci_is_pcie(dev)) + return -EINVAL; + + /* + * Per PCIe r4.0, sec 6.15, endpoints and root ports may be + * AtomicOp requesters. For now, we only support endpoints as + * requesters and root ports as completers. No endpoints as + * completers, and no peer-to-peer. + */ + + switch (pci_pcie_type(dev)) { + case PCI_EXP_TYPE_ENDPOINT: + case PCI_EXP_TYPE_LEG_END: + case PCI_EXP_TYPE_RC_END: + break; + default: + return -EINVAL; + } + + while (bus->parent) { + bridge = bus->self; + + pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); + + switch (pci_pcie_type(bridge)) { + /* Ensure switch ports support AtomicOp routing */ + case PCI_EXP_TYPE_UPSTREAM: + case PCI_EXP_TYPE_DOWNSTREAM: + if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) + return -EINVAL; + break; + + /* Ensure root port supports all the sizes we care about */ + case PCI_EXP_TYPE_ROOT_PORT: + if ((cap & cap_mask) != cap_mask) + return -EINVAL; + break; + } + + /* Ensure upstream ports don't block AtomicOps on egress */ + if (!bridge->has_secondary_link) { + pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, + &ctl2); + if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK) + return -EINVAL; + } + + bus = bus->parent; + } + + pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, + PCI_EXP_DEVCTL2_ATOMIC_REQ); + return 0; +} +EXPORT_SYMBOL(pci_enable_atomic_ops_to_root); + +/** * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge * @dev: the PCI device * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) @@ -3198,7 +3269,7 @@ static int __pci_request_region(struct pci_dev *pdev, int bar, return 0; err_out: - dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, + pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar, &pdev->resource[bar]); return -EBUSY; } @@ -3621,7 +3692,7 @@ static void __pci_set_master(struct pci_dev *dev, bool enable) else cmd = old_cmd & ~PCI_COMMAND_MASTER; if (cmd != old_cmd) { - dev_dbg(&dev->dev, "%s bus mastering\n", + pci_dbg(dev, "%s bus mastering\n", enable ? "enabling" : "disabling"); pci_write_config_word(dev, PCI_COMMAND, cmd); } @@ -3722,7 +3793,7 @@ int pci_set_cacheline_size(struct pci_dev *dev) if (cacheline_size == pci_cache_line_size) return 0; - dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n", + pci_printk(KERN_DEBUG, dev, "cache line size of %d is not supported\n", pci_cache_line_size << 2); return -EINVAL; @@ -3751,7 +3822,7 @@ int pci_set_mwi(struct pci_dev *dev) pci_read_config_word(dev, PCI_COMMAND, &cmd); if (!(cmd & PCI_COMMAND_INVALIDATE)) { - dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); + pci_dbg(dev, "enabling Mem-Wr-Inval\n"); cmd |= PCI_COMMAND_INVALIDATE; pci_write_config_word(dev, PCI_COMMAND, cmd); } @@ -3947,13 +4018,13 @@ static void pci_flr_wait(struct pci_dev *dev) pci_read_config_dword(dev, PCI_COMMAND, &id); while (id == ~0) { if (delay > timeout) { - dev_warn(&dev->dev, "not ready %dms after FLR; giving up\n", + pci_warn(dev, "not ready %dms after FLR; giving up\n", 100 + delay - 1); return; } if (delay > 1000) - dev_info(&dev->dev, "not ready %dms after FLR; waiting\n", + pci_info(dev, "not ready %dms after FLR; waiting\n", 100 + delay - 1); msleep(delay); @@ -3962,7 +4033,7 @@ static void pci_flr_wait(struct pci_dev *dev) } if (delay > 1000) - dev_info(&dev->dev, "ready %dms after FLR\n", 100 + delay - 1); + pci_info(dev, "ready %dms after FLR\n", 100 + delay - 1); } /** @@ -3994,7 +4065,7 @@ static bool pcie_has_flr(struct pci_dev *dev) void pcie_flr(struct pci_dev *dev) { if (!pci_wait_for_pending_transaction(dev)) - dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); + pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); pci_flr_wait(dev); @@ -4027,7 +4098,7 @@ static int pci_af_flr(struct pci_dev *dev, int probe) */ if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL, PCI_AF_STATUS_TP << 8)) - dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); + pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); pci_flr_wait(dev); @@ -5150,12 +5221,12 @@ void pci_add_dma_alias(struct pci_dev *dev, u8 devfn) dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX), sizeof(long), GFP_KERNEL); if (!dev->dma_alias_mask) { - dev_warn(&dev->dev, "Unable to allocate DMA alias mask\n"); + pci_warn(dev, "Unable to allocate DMA alias mask\n"); return; } set_bit(devfn, dev->dma_alias_mask); - dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n", + pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n", PCI_SLOT(devfn), PCI_FUNC(devfn)); } @@ -5304,7 +5375,7 @@ static void pci_request_resource_alignment(struct pci_dev *dev, int bar, return; if (r->flags & IORESOURCE_PCI_FIXED) { - dev_info(&dev->dev, "BAR%d %pR: ignoring requested alignment %#llx\n", + pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n", bar, r, (unsigned long long)align); return; } @@ -5341,7 +5412,7 @@ static void pci_request_resource_alignment(struct pci_dev *dev, int bar, * devices and we use the second. */ - dev_info(&dev->dev, "BAR%d %pR: requesting alignment to %#llx\n", + pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n", bar, r, (unsigned long long)align); if (resize) { @@ -5387,13 +5458,11 @@ void pci_reassigndev_resource_alignment(struct pci_dev *dev) if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { - dev_warn(&dev->dev, - "Can't reassign resources to host bridge.\n"); + pci_warn(dev, "Can't reassign resources to host bridge\n"); return; } - dev_info(&dev->dev, - "Disabling memory decoding and releasing memory resources.\n"); + pci_info(dev, "Disabling memory decoding and releasing memory resources\n"); pci_read_config_word(dev, PCI_COMMAND, &command); command &= ~PCI_COMMAND_MEMORY; pci_write_config_word(dev, PCI_COMMAND, command); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index f6b58b32a67c..e90009fff1a9 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -342,6 +342,26 @@ static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, void pci_enable_acs(struct pci_dev *dev); +#ifdef CONFIG_PCIEASPM +void pcie_aspm_init_link_state(struct pci_dev *pdev); +void pcie_aspm_exit_link_state(struct pci_dev *pdev); +void pcie_aspm_pm_state_change(struct pci_dev *pdev); +void pcie_aspm_powersave_config_link(struct pci_dev *pdev); +#else +static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } +static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } +static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } +static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } +#endif + +#ifdef CONFIG_PCIEASPM_DEBUG +void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev); +void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev); +#else +static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { } +static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { } +#endif + #ifdef CONFIG_PCIE_PTM void pci_ptm_init(struct pci_dev *dev); #else diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig index ac53edbc9613..d658dfa53b87 100644 --- a/drivers/pci/pcie/Kconfig +++ b/drivers/pci/pcie/Kconfig @@ -92,7 +92,7 @@ config PCIE_PME config PCIE_DPC bool "PCIe Downstream Port Containment support" - depends on PCIEPORTBUS + depends on PCIEPORTBUS && PCIEAER default n help This enables PCI Express Downstream Port Containment (DPC) diff --git a/drivers/pci/pcie/aer/aer_inject.c b/drivers/pci/pcie/aer/aer_inject.c index 2b6a59266689..b77c01e63673 100644 --- a/drivers/pci/pcie/aer/aer_inject.c +++ b/drivers/pci/pcie/aer/aer_inject.c @@ -344,14 +344,14 @@ static int aer_inject(struct aer_error_inj *einj) return -ENODEV; rpdev = pcie_find_root_port(dev); if (!rpdev) { - dev_err(&dev->dev, "aer_inject: Root port not found\n"); + pci_err(dev, "aer_inject: Root port not found\n"); ret = -ENODEV; goto out_put; } pos_cap_err = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); if (!pos_cap_err) { - dev_err(&dev->dev, "aer_inject: Device doesn't support AER\n"); + pci_err(dev, "aer_inject: Device doesn't support AER\n"); ret = -EPROTONOSUPPORT; goto out_put; } @@ -362,8 +362,7 @@ static int aer_inject(struct aer_error_inj *einj) rp_pos_cap_err = pci_find_ext_capability(rpdev, PCI_EXT_CAP_ID_ERR); if (!rp_pos_cap_err) { - dev_err(&rpdev->dev, - "aer_inject: Root port doesn't support AER\n"); + pci_err(rpdev, "aer_inject: Root port doesn't support AER\n"); ret = -EPROTONOSUPPORT; goto out_put; } @@ -411,16 +410,14 @@ static int aer_inject(struct aer_error_inj *einj) if (!aer_mask_override && einj->cor_status && !(einj->cor_status & ~cor_mask)) { ret = -EINVAL; - dev_warn(&dev->dev, - "aer_inject: The correctable error(s) is masked by device\n"); + pci_warn(dev, "aer_inject: The correctable error(s) is masked by device\n"); spin_unlock_irqrestore(&inject_lock, flags); goto out_put; } if (!aer_mask_override && einj->uncor_status && !(einj->uncor_status & ~uncor_mask)) { ret = -EINVAL; - dev_warn(&dev->dev, - "aer_inject: The uncorrectable error(s) is masked by device\n"); + pci_warn(dev, "aer_inject: The uncorrectable error(s) is masked by device\n"); spin_unlock_irqrestore(&inject_lock, flags); goto out_put; } @@ -483,7 +480,7 @@ static int aer_inject(struct aer_error_inj *einj) einj->cor_status, einj->uncor_status, pci_name(dev)); aer_irq(-1, edev); } else { - dev_err(&rpdev->dev, "aer_inject: AER device not found\n"); + pci_err(rpdev, "aer_inject: AER device not found\n"); ret = -ENODEV; } out_put: diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c index 6ff5f5b4f5e6..bf6c9833a857 100644 --- a/drivers/pci/pcie/aer/aerdrv.c +++ b/drivers/pci/pcie/aer/aerdrv.c @@ -326,7 +326,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev) pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32); pci_reset_bridge_secondary_bus(dev); - dev_printk(KERN_DEBUG, &dev->dev, "Root Port link has been reset\n"); + pci_printk(KERN_DEBUG, dev, "Root Port link has been reset\n"); /* Clear Root Error Status */ pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, ®32); diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c index 744805232155..03e04ca8b2ca 100644 --- a/drivers/pci/pcie/aer/aerdrv_core.c +++ b/drivers/pci/pcie/aer/aerdrv_core.c @@ -226,9 +226,8 @@ static bool find_source_device(struct pci_dev *parent, pci_walk_bus(parent->subordinate, find_device_iter, e_info); if (!e_info->error_dev_num) { - dev_printk(KERN_DEBUG, &parent->dev, - "can't find device of ID%04x\n", - e_info->id); + pci_printk(KERN_DEBUG, parent, "can't find device of ID%04x\n", + e_info->id); return false; } return true; @@ -256,7 +255,7 @@ static int report_error_detected(struct pci_dev *dev, void *data) * of a driver for this device is unaware of * its hw state. */ - dev_printk(KERN_DEBUG, &dev->dev, "device has %s\n", + pci_printk(KERN_DEBUG, dev, "device has %s\n", dev->driver ? "no AER-aware driver" : "no driver"); } @@ -364,7 +363,7 @@ static pci_ers_result_t broadcast_error_message(struct pci_dev *dev, { struct aer_broadcast_data result_data; - dev_printk(KERN_DEBUG, &dev->dev, "broadcast %s message\n", error_mesg); + pci_printk(KERN_DEBUG, dev, "broadcast %s message\n", error_mesg); result_data.state = state; if (cb == report_error_detected) result_data.result = PCI_ERS_RESULT_CAN_RECOVER; @@ -413,7 +412,7 @@ static pci_ers_result_t broadcast_error_message(struct pci_dev *dev, static pci_ers_result_t default_reset_link(struct pci_dev *dev) { pci_reset_bridge_secondary_bus(dev); - dev_printk(KERN_DEBUG, &dev->dev, "downstream link has been reset\n"); + pci_printk(KERN_DEBUG, dev, "downstream link has been reset\n"); return PCI_ERS_RESULT_RECOVERED; } @@ -465,15 +464,13 @@ static pci_ers_result_t reset_link(struct pci_dev *dev) } else if (udev->has_secondary_link) { status = default_reset_link(udev); } else { - dev_printk(KERN_DEBUG, &dev->dev, - "no link-reset support at upstream device %s\n", + pci_printk(KERN_DEBUG, dev, "no link-reset support at upstream device %s\n", pci_name(udev)); return PCI_ERS_RESULT_DISCONNECT; } if (status != PCI_ERS_RESULT_RECOVERED) { - dev_printk(KERN_DEBUG, &dev->dev, - "link reset at upstream device %s failed\n", + pci_printk(KERN_DEBUG, dev, "link reset at upstream device %s failed\n", pci_name(udev)); return PCI_ERS_RESULT_DISCONNECT; } @@ -537,12 +534,12 @@ static void do_recovery(struct pci_dev *dev, int severity) "resume", report_resume); - dev_info(&dev->dev, "AER: Device recovery successful\n"); + pci_info(dev, "AER: Device recovery successful\n"); return; failed: /* TODO: Should kernel panic here? */ - dev_info(&dev->dev, "AER: Device recovery failed\n"); + pci_info(dev, "AER: Device recovery failed\n"); } /** @@ -633,7 +630,8 @@ static void aer_recover_work_func(struct work_struct *work) continue; } cper_print_aer(pdev, entry.severity, entry.regs); - do_recovery(pdev, entry.severity); + if (entry.severity != AER_CORRECTABLE) + do_recovery(pdev, entry.severity); pci_dev_put(pdev); } } @@ -660,7 +658,7 @@ static int get_device_error_info(struct pci_dev *dev, struct aer_err_info *info) /* The device might not support AER */ if (!pos) - return 1; + return 0; if (info->severity == AER_CORRECTABLE) { pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, diff --git a/drivers/pci/pcie/aer/aerdrv_errprint.c b/drivers/pci/pcie/aer/aerdrv_errprint.c index 54c4b691e51f..0a7004a76735 100644 --- a/drivers/pci/pcie/aer/aerdrv_errprint.c +++ b/drivers/pci/pcie/aer/aerdrv_errprint.c @@ -132,7 +132,7 @@ static const char *aer_agent_string[] = { static void __print_tlp_header(struct pci_dev *dev, struct aer_header_log_regs *t) { - dev_err(&dev->dev, " TLP Header: %08x %08x %08x %08x\n", + pci_err(dev, " TLP Header: %08x %08x %08x %08x\n", t->dw0, t->dw1, t->dw2, t->dw3); } @@ -155,10 +155,10 @@ static void __aer_print_error(struct pci_dev *dev, aer_uncorrectable_error_string[i] : NULL; if (errmsg) - dev_err(&dev->dev, " [%2d] %-22s%s\n", i, errmsg, + pci_err(dev, " [%2d] %-22s%s\n", i, errmsg, info->first_error == i ? " (First)" : ""); else - dev_err(&dev->dev, " [%2d] Unknown Error Bit%s\n", + pci_err(dev, " [%2d] Unknown Error Bit%s\n", i, info->first_error == i ? " (First)" : ""); } } @@ -169,7 +169,7 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) int id = ((dev->bus->number << 8) | dev->devfn); if (!info->status) { - dev_err(&dev->dev, "PCIe Bus Error: severity=%s, type=Unaccessible, id=%04x(Unregistered Agent ID)\n", + pci_err(dev, "PCIe Bus Error: severity=%s, type=Unaccessible, id=%04x(Unregistered Agent ID)\n", aer_error_severity_string[info->severity], id); goto out; } @@ -177,11 +177,11 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) layer = AER_GET_LAYER_ERROR(info->severity, info->status); agent = AER_GET_AGENT(info->severity, info->status); - dev_err(&dev->dev, "PCIe Bus Error: severity=%s, type=%s, id=%04x(%s)\n", + pci_err(dev, "PCIe Bus Error: severity=%s, type=%s, id=%04x(%s)\n", aer_error_severity_string[info->severity], aer_error_layer[layer], id, aer_agent_string[agent]); - dev_err(&dev->dev, " device [%04x:%04x] error status/mask=%08x/%08x\n", + pci_err(dev, " device [%04x:%04x] error status/mask=%08x/%08x\n", dev->vendor, dev->device, info->status, info->mask); @@ -192,7 +192,7 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) out: if (info->id && info->error_dev_num > 1 && info->id == id) - dev_err(&dev->dev, " Error of this Agent(%04x) is reported first\n", id); + pci_err(dev, " Error of this Agent(%04x) is reported first\n", id); trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask), info->severity); @@ -200,7 +200,7 @@ out: void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info) { - dev_info(&dev->dev, "AER: %s%s error received: id=%04x\n", + pci_info(dev, "AER: %s%s error received: id=%04x\n", info->multi_error_valid ? "Multiple " : "", aer_error_severity_string[info->severity], info->id); } @@ -242,13 +242,13 @@ void cper_print_aer(struct pci_dev *dev, int aer_severity, layer = AER_GET_LAYER_ERROR(aer_severity, status); agent = AER_GET_AGENT(aer_severity, status); - dev_err(&dev->dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask); + pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask); cper_print_bits("", status, status_strs, status_strs_size); - dev_err(&dev->dev, "aer_layer=%s, aer_agent=%s\n", + pci_err(dev, "aer_layer=%s, aer_agent=%s\n", aer_error_layer[layer], aer_agent_string[agent]); if (aer_severity != AER_CORRECTABLE) - dev_err(&dev->dev, "aer_uncor_severity: 0x%08x\n", + pci_err(dev, "aer_uncor_severity: 0x%08x\n", aer->uncor_severity); if (tlp_header_valid) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 9783e10da3a9..57feef2ecfe7 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -43,18 +43,6 @@ #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \ ASPM_STATE_L1SS) -/* - * When L1 substates are enabled, the LTR L1.2 threshold is a timing parameter - * that decides whether L1.1 or L1.2 is entered (Refer PCIe spec for details). - * Not sure is there is a way to "calculate" this on the fly, but maybe we - * could turn it into a parameter in future. This value has been taken from - * the following files from Intel's coreboot (which is the only code I found - * to have used this): - * https://www.coreboot.org/pipermail/coreboot-gerrit/2015-March/021134.html - * https://review.coreboot.org/#/c/8832/ - */ -#define LTR_L1_2_THRESHOLD_BITS ((1 << 21) | (1 << 23) | (1 << 30)) - struct aspm_latency { u32 l0s; /* L0s latency (nsec) */ u32 l1; /* L1 latency (nsec) */ @@ -278,7 +266,7 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) return; /* Training failed. Restore common clock configurations */ - dev_err(&parent->dev, "ASPM: Could not configure common clock\n"); + pci_err(parent, "ASPM: Could not configure common clock\n"); list_for_each_entry(child, &linkbus->devices, bus_list) pcie_capability_write_word(child, PCI_EXP_LNKCTL, child_reg[PCI_FUNC(child->devfn)]); @@ -328,11 +316,36 @@ static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val) case 2: return val * 100; } - dev_err(&pdev->dev, "%s: Invalid T_PwrOn scale: %u\n", - __func__, scale); + pci_err(pdev, "%s: Invalid T_PwrOn scale: %u\n", __func__, scale); return 0; } +static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) +{ + u64 threshold_ns = threshold_us * 1000; + + /* See PCIe r3.1, sec 7.33.3 and sec 6.18 */ + if (threshold_ns < 32) { + *scale = 0; + *value = threshold_ns; + } else if (threshold_ns < 1024) { + *scale = 1; + *value = threshold_ns >> 5; + } else if (threshold_ns < 32768) { + *scale = 2; + *value = threshold_ns >> 10; + } else if (threshold_ns < 1048576) { + *scale = 3; + *value = threshold_ns >> 15; + } else if (threshold_ns < 33554432) { + *scale = 4; + *value = threshold_ns >> 20; + } else { + *scale = 5; + *value = threshold_ns >> 25; + } +} + struct aspm_register_info { u32 support:2; u32 enabled:2; @@ -443,6 +456,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, struct aspm_register_info *dwreg) { u32 val1, val2, scale1, scale2; + u32 t_common_mode, t_power_on, l1_2_threshold, scale, value; link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr; link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr; @@ -454,16 +468,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, /* Choose the greater of the two Port Common_Mode_Restore_Times */ val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; - if (val1 > val2) - link->l1ss.ctl1 |= val1 << 8; - else - link->l1ss.ctl1 |= val2 << 8; - - /* - * We currently use LTR L1.2 threshold to be fixed constant picked from - * Intel's coreboot. - */ - link->l1ss.ctl1 |= LTR_L1_2_THRESHOLD_BITS; + t_common_mode = max(val1, val2); /* Choose the greater of the two Port T_POWER_ON times */ val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; @@ -472,10 +477,27 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; if (calc_l1ss_pwron(link->pdev, scale1, val1) > - calc_l1ss_pwron(link->downstream, scale2, val2)) + calc_l1ss_pwron(link->downstream, scale2, val2)) { link->l1ss.ctl2 |= scale1 | (val1 << 3); - else + t_power_on = calc_l1ss_pwron(link->pdev, scale1, val1); + } else { link->l1ss.ctl2 |= scale2 | (val2 << 3); + t_power_on = calc_l1ss_pwron(link->downstream, scale2, val2); + } + + /* + * Set LTR_L1.2_THRESHOLD to the time required to transition the + * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if + * downstream devices report (via LTR) that they can tolerate at + * least that much latency. + * + * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and + * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at + * least 4us. + */ + l1_2_threshold = 2 + 4 + t_common_mode + t_power_on; + encode_l12_threshold(l1_2_threshold, &scale, &value); + link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16; } static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) @@ -786,7 +808,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev) */ pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32); if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) { - dev_info(&child->dev, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n"); + pci_info(child, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n"); return -EINVAL; } } @@ -1027,7 +1049,7 @@ static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem) * ignored in this situation. */ if (aspm_disabled) { - dev_warn(&pdev->dev, "can't disable ASPM; OS doesn't have ASPM control\n"); + pci_warn(pdev, "can't disable ASPM; OS doesn't have ASPM control\n"); return; } diff --git a/drivers/pci/pcie/pcie-dpc.c b/drivers/pci/pcie/pcie-dpc.c index 2d976a623ddc..7eb9bc7d4bfd 100644 --- a/drivers/pci/pcie/pcie-dpc.c +++ b/drivers/pci/pcie/pcie-dpc.c @@ -15,34 +15,15 @@ #include <linux/pci.h> #include <linux/pcieport_if.h> #include "../pci.h" - -struct rp_pio_header_log_regs { - u32 dw0; - u32 dw1; - u32 dw2; - u32 dw3; -}; - -struct dpc_rp_pio_regs { - u32 status; - u32 mask; - u32 severity; - u32 syserror; - u32 exception; - - struct rp_pio_header_log_regs header_log; - u32 impspec_log; - u32 tlp_prefix_log[4]; - u32 log_size; - u16 first_error; -}; +#include "aer/aerdrv.h" struct dpc_dev { struct pcie_device *dev; struct work_struct work; - int cap_pos; - bool rp; + u16 cap_pos; + bool rp_extensions; u32 rp_pio_status; + u8 rp_log_size; }; static const char * const rp_pio_error_string[] = { @@ -72,13 +53,13 @@ static int dpc_wait_rp_inactive(struct dpc_dev *dpc) unsigned long timeout = jiffies + HZ; struct pci_dev *pdev = dpc->dev->port; struct device *dev = &dpc->dev->device; - u16 status; + u16 cap = dpc->cap_pos, status; - pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status); + pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); while (status & PCI_EXP_DPC_RP_BUSY && !time_after(jiffies, timeout)) { msleep(10); - pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status); + pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); } if (status & PCI_EXP_DPC_RP_BUSY) { dev_warn(dev, "DPC root port still busy\n"); @@ -104,11 +85,12 @@ static void dpc_wait_link_inactive(struct dpc_dev *dpc) dev_warn(dev, "Link state not disabled for DPC event\n"); } -static void interrupt_event_handler(struct work_struct *work) +static void dpc_work(struct work_struct *work) { struct dpc_dev *dpc = container_of(work, struct dpc_dev, work); struct pci_dev *dev, *temp, *pdev = dpc->dev->port; struct pci_bus *parent = pdev->subordinate; + u16 cap = dpc->cap_pos, ctl; pci_lock_rescan_remove(); list_for_each_entry_safe_reverse(dev, temp, &parent->devices, @@ -124,159 +106,127 @@ static void interrupt_event_handler(struct work_struct *work) pci_unlock_rescan_remove(); dpc_wait_link_inactive(dpc); - if (dpc->rp && dpc_wait_rp_inactive(dpc)) + if (dpc->rp_extensions && dpc_wait_rp_inactive(dpc)) return; - if (dpc->rp && dpc->rp_pio_status) { - pci_write_config_dword(pdev, - dpc->cap_pos + PCI_EXP_DPC_RP_PIO_STATUS, - dpc->rp_pio_status); + if (dpc->rp_extensions && dpc->rp_pio_status) { + pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, + dpc->rp_pio_status); dpc->rp_pio_status = 0; } - pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, + pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS, PCI_EXP_DPC_STATUS_TRIGGER | PCI_EXP_DPC_STATUS_INTERRUPT); -} -static void dpc_rp_pio_print_tlp_header(struct device *dev, - struct rp_pio_header_log_regs *t) -{ - dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n", - t->dw0, t->dw1, t->dw2, t->dw3); + pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl); + pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL, + ctl | PCI_EXP_DPC_CTL_INT_EN); } -static void dpc_rp_pio_print_error(struct dpc_dev *dpc, - struct dpc_rp_pio_regs *rp_pio) +static void dpc_process_rp_pio_error(struct dpc_dev *dpc) { struct device *dev = &dpc->dev->device; + struct pci_dev *pdev = dpc->dev->port; + u16 cap = dpc->cap_pos, dpc_status, first_error; + u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix; int i; - u32 status; + pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status); + pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask); dev_err(dev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n", - rp_pio->status, rp_pio->mask); + status, mask); + + dpc->rp_pio_status = status; + pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev); + pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr); + pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc); dev_err(dev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n", - rp_pio->severity, rp_pio->syserror, rp_pio->exception); + sev, syserr, exc); - status = (rp_pio->status & ~rp_pio->mask); + /* Get First Error Pointer */ + pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status); + first_error = (dpc_status & 0x1f00) >> 8; + status &= ~mask; for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) { - if (!(status & (1 << i))) - continue; - - dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i], - rp_pio->first_error == i ? " (First)" : ""); + if (status & (1 << i)) + dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i], + first_error == i ? " (First)" : ""); } - dpc_rp_pio_print_tlp_header(dev, &rp_pio->header_log); - if (rp_pio->log_size == 4) + if (dpc->rp_log_size < 4) return; - dev_err(dev, "RP PIO ImpSpec Log %#010x\n", rp_pio->impspec_log); + pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG, + &dw0); + pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4, + &dw1); + pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8, + &dw2); + pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12, + &dw3); + dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n", + dw0, dw1, dw2, dw3); - for (i = 0; i < rp_pio->log_size - 5; i++) - dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i, - rp_pio->tlp_prefix_log[i]); + if (dpc->rp_log_size < 5) + return; + pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log); + dev_err(dev, "RP PIO ImpSpec Log %#010x\n", log); + + for (i = 0; i < dpc->rp_log_size - 5; i++) { + pci_read_config_dword(pdev, + cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix); + dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix); + } } -static void dpc_rp_pio_get_info(struct dpc_dev *dpc, - struct dpc_rp_pio_regs *rp_pio) +static irqreturn_t dpc_irq(int irq, void *context) { + struct dpc_dev *dpc = (struct dpc_dev *)context; struct pci_dev *pdev = dpc->dev->port; struct device *dev = &dpc->dev->device; - int i; - u16 cap; - u16 status; - - pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_STATUS, - &rp_pio->status); - pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_MASK, - &rp_pio->mask); - - pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_SEVERITY, - &rp_pio->severity); - pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_SYSERROR, - &rp_pio->syserror); - pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_EXCEPTION, - &rp_pio->exception); + u16 cap = dpc->cap_pos, ctl, status, source, reason, ext_reason; - /* Get First Error Pointer */ - pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status); - rp_pio->first_error = (status & 0x1f00) >> 8; + pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl); - pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap); - rp_pio->log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8; - if (rp_pio->log_size < 4 || rp_pio->log_size > 9) { - dev_err(dev, "RP PIO log size %u is invalid\n", - rp_pio->log_size); - return; - } - - pci_read_config_dword(pdev, - dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG, - &rp_pio->header_log.dw0); - pci_read_config_dword(pdev, - dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4, - &rp_pio->header_log.dw1); - pci_read_config_dword(pdev, - dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8, - &rp_pio->header_log.dw2); - pci_read_config_dword(pdev, - dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12, - &rp_pio->header_log.dw3); - if (rp_pio->log_size == 4) - return; - - pci_read_config_dword(pdev, - dpc->cap_pos + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, - &rp_pio->impspec_log); - for (i = 0; i < rp_pio->log_size - 5; i++) - pci_read_config_dword(pdev, - dpc->cap_pos + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, - &rp_pio->tlp_prefix_log[i]); -} + if (!(ctl & PCI_EXP_DPC_CTL_INT_EN) || ctl == (u16)(~0)) + return IRQ_NONE; -static void dpc_process_rp_pio_error(struct dpc_dev *dpc) -{ - struct dpc_rp_pio_regs rp_pio_regs; + pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status); - dpc_rp_pio_get_info(dpc, &rp_pio_regs); - dpc_rp_pio_print_error(dpc, &rp_pio_regs); + if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT)) + return IRQ_NONE; - dpc->rp_pio_status = rp_pio_regs.status; -} + if (!(status & PCI_EXP_DPC_STATUS_TRIGGER)) { + pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS, + PCI_EXP_DPC_STATUS_INTERRUPT); + return IRQ_HANDLED; + } -static irqreturn_t dpc_irq(int irq, void *context) -{ - struct dpc_dev *dpc = (struct dpc_dev *)context; - struct pci_dev *pdev = dpc->dev->port; - struct device *dev = &dpc->dev->device; - u16 status, source; + pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL, + ctl & ~PCI_EXP_DPC_CTL_INT_EN); - pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status); - pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_SOURCE_ID, + pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, &source); - if (!status || status == (u16)(~0)) - return IRQ_NONE; dev_info(dev, "DPC containment event, status:%#06x source:%#06x\n", status, source); - if (status & PCI_EXP_DPC_STATUS_TRIGGER) { - u16 reason = (status >> 1) & 0x3; - u16 ext_reason = (status >> 5) & 0x3; - - dev_warn(dev, "DPC %s detected, remove downstream devices\n", - (reason == 0) ? "unmasked uncorrectable error" : - (reason == 1) ? "ERR_NONFATAL" : - (reason == 2) ? "ERR_FATAL" : - (ext_reason == 0) ? "RP PIO error" : - (ext_reason == 1) ? "software trigger" : - "reserved error"); - /* show RP PIO error detail information */ - if (reason == 3 && ext_reason == 0) - dpc_process_rp_pio_error(dpc); - - schedule_work(&dpc->work); - } + reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1; + ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5; + + dev_warn(dev, "DPC %s detected, remove downstream devices\n", + (reason == 0) ? "unmasked uncorrectable error" : + (reason == 1) ? "ERR_NONFATAL" : + (reason == 2) ? "ERR_FATAL" : + (ext_reason == 0) ? "RP PIO error" : + (ext_reason == 1) ? "software trigger" : + "reserved error"); + /* show RP PIO error detail information */ + if (dpc->rp_extensions && reason == 3 && ext_reason == 0) + dpc_process_rp_pio_error(dpc); + + schedule_work(&dpc->work); + return IRQ_HANDLED; } @@ -289,13 +239,16 @@ static int dpc_probe(struct pcie_device *dev) int status; u16 ctl, cap; + if (pcie_aer_get_firmware_first(pdev)) + return -ENOTSUPP; + dpc = devm_kzalloc(device, sizeof(*dpc), GFP_KERNEL); if (!dpc) return -ENOMEM; dpc->cap_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC); dpc->dev = dev; - INIT_WORK(&dpc->work, interrupt_event_handler); + INIT_WORK(&dpc->work, dpc_work); set_service_data(dev, dpc); status = devm_request_irq(device, dev->irq, dpc_irq, IRQF_SHARED, @@ -309,15 +262,23 @@ static int dpc_probe(struct pcie_device *dev) pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap); pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl); - dpc->rp = (cap & PCI_EXP_DPC_CAP_RP_EXT); + dpc->rp_extensions = (cap & PCI_EXP_DPC_CAP_RP_EXT); + if (dpc->rp_extensions) { + dpc->rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8; + if (dpc->rp_log_size < 4 || dpc->rp_log_size > 9) { + dev_err(device, "RP PIO log size %u is invalid\n", + dpc->rp_log_size); + dpc->rp_log_size = 0; + } + } ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN; pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl); dev_info(device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n", - cap & 0xf, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT), + cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT), FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP), - FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), (cap >> 8) & 0xf, + FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), dpc->rp_log_size, FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE)); return status; } diff --git a/drivers/pci/pcie/pme.c b/drivers/pci/pcie/pme.c index df290aa58dce..046d9bf64ef1 100644 --- a/drivers/pci/pcie/pme.c +++ b/drivers/pci/pcie/pme.c @@ -198,14 +198,14 @@ static void pcie_pme_handle_request(struct pci_dev *port, u16 req_id) * assuming that the PME was reported by a PCIe-PCI bridge that * used devfn different from zero. */ - dev_dbg(&port->dev, "PME interrupt generated for non-existent device %02x:%02x.%d\n", + pci_dbg(port, "PME interrupt generated for non-existent device %02x:%02x.%d\n", busnr, PCI_SLOT(devfn), PCI_FUNC(devfn)); found = pcie_pme_from_pci_bridge(bus, 0); } out: if (!found) - dev_dbg(&port->dev, "Spurious native PME interrupt!\n"); + pci_dbg(port, "Spurious native PME interrupt!\n"); } /** @@ -345,7 +345,7 @@ static int pcie_pme_probe(struct pcie_device *srv) return ret; } - dev_info(&port->dev, "Signaling PME with IRQ %d\n", srv->irq); + pci_info(port, "Signaling PME with IRQ %d\n", srv->irq); pcie_pme_mark_devices(port); pcie_pme_interrupt_enable(port, true); diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index a59210350c44..ef3bad4ad010 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -216,9 +216,9 @@ static int get_port_device_capability(struct pci_dev *dev) return 0; cap_mask = PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP - | PCIE_PORT_SERVICE_VC | PCIE_PORT_SERVICE_DPC; + | PCIE_PORT_SERVICE_VC; if (pci_aer_available()) - cap_mask |= PCIE_PORT_SERVICE_AER; + cap_mask |= PCIE_PORT_SERVICE_AER | PCIE_PORT_SERVICE_DPC; if (pcie_ports_auto) pcie_port_platform_notify(dev, &cap_mask); diff --git a/drivers/pci/pcie/ptm.c b/drivers/pci/pcie/ptm.c index bab8ac63c4f3..c9f9b15a9e8a 100644 --- a/drivers/pci/pcie/ptm.c +++ b/drivers/pci/pcie/ptm.c @@ -33,7 +33,7 @@ static void pci_ptm_info(struct pci_dev *dev) dev->ptm_granularity); break; } - dev_info(&dev->dev, "PTM enabled%s, %s granularity\n", + pci_info(dev, "PTM enabled%s, %s granularity\n", dev->ptm_root ? " (root)" : "", clock_desc); } diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 14e0ea1ff38b..815c821fe950 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -253,7 +253,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, sz64 = pci_size(l64, sz64, mask64); if (!sz64) { - dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", + pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", pos); goto fail; } @@ -264,7 +264,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; res->start = 0; res->end = 0; - dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", + pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", pos, (unsigned long long)sz64); goto out; } @@ -274,7 +274,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, res->flags |= IORESOURCE_UNSET; res->start = 0; res->end = sz64; - dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", + pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", pos, (unsigned long long)l64); goto out; } @@ -301,7 +301,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, res->flags |= IORESOURCE_UNSET; res->start = 0; res->end = region.end - region.start; - dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n", + pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n", pos, (unsigned long long)region.start); } @@ -312,7 +312,7 @@ fail: res->flags = 0; out: if (res->flags) - dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res); + pci_printk(KERN_DEBUG, dev, "reg 0x%x: %pR\n", pos, res); return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; } @@ -375,7 +375,7 @@ static void pci_read_bridge_io(struct pci_bus *child) region.start = base; region.end = limit + io_granularity - 1; pcibios_bus_to_resource(dev->bus, res, ®ion); - dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); + pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res); } } @@ -397,7 +397,7 @@ static void pci_read_bridge_mmio(struct pci_bus *child) region.start = base; region.end = limit + 0xfffff; pcibios_bus_to_resource(dev->bus, res, ®ion); - dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); + pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res); } } @@ -437,7 +437,7 @@ static void pci_read_bridge_mmio_pref(struct pci_bus *child) limit = (pci_bus_addr_t) limit64; if (base != base64) { - dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", + pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", (unsigned long long) base64); return; } @@ -450,7 +450,7 @@ static void pci_read_bridge_mmio_pref(struct pci_bus *child) region.start = base; region.end = limit + 0xfffff; pcibios_bus_to_resource(dev->bus, res, ®ion); - dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); + pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res); } } @@ -463,7 +463,7 @@ void pci_read_bridge_bases(struct pci_bus *child) if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ return; - dev_info(&dev->dev, "PCI bridge to %pR%s\n", + pci_info(dev, "PCI bridge to %pR%s\n", &child->busn_res, dev->transparent ? " (subtractive decode)" : ""); @@ -480,7 +480,7 @@ void pci_read_bridge_bases(struct pci_bus *child) if (res && res->flags) { pci_bus_add_resource(child, res, PCI_SUBTRACTIVE_DECODE); - dev_printk(KERN_DEBUG, &dev->dev, + pci_printk(KERN_DEBUG, dev, " bridge window %pR (subtractive decode)\n", res); } @@ -1005,11 +1005,11 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, secondary = (buses >> 8) & 0xFF; subordinate = (buses >> 16) & 0xFF; - dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", + pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", secondary, subordinate, pass); if (!primary && (primary != bus->number) && secondary && subordinate) { - dev_warn(&dev->dev, "Primary bus is hard wired to 0\n"); + pci_warn(dev, "Primary bus is hard wired to 0\n"); primary = bus->number; } @@ -1017,7 +1017,7 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, if (!pass && (primary != bus->number || secondary <= bus->number || secondary > subordinate)) { - dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", + pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", secondary, subordinate); broken = 1; } @@ -1058,7 +1058,7 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, cmax = pci_scan_child_bus(child); if (cmax > subordinate) - dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n", + pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", subordinate, cmax); /* subordinate should equal child->busn_res.end */ if (subordinate > max) @@ -1468,7 +1468,7 @@ int pci_setup_device(struct pci_dev *dev) dev->revision = class & 0xff; dev->class = class >> 8; /* upper 3 bytes */ - dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n", + pci_printk(KERN_DEBUG, dev, "[%04x:%04x] type %02x class %#08x\n", dev->vendor, dev->device, dev->hdr_type, dev->class); /* need to have dev->class ready */ @@ -1488,7 +1488,7 @@ int pci_setup_device(struct pci_dev *dev) if (dev->non_compliant_bars) { pci_read_config_word(dev, PCI_COMMAND, &cmd); if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { - dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); + pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); cmd &= ~PCI_COMMAND_IO; cmd &= ~PCI_COMMAND_MEMORY; pci_write_config_word(dev, PCI_COMMAND, cmd); @@ -1521,14 +1521,14 @@ int pci_setup_device(struct pci_dev *dev) res = &dev->resource[0]; res->flags = LEGACY_IO_RESOURCE; pcibios_bus_to_resource(dev->bus, res, ®ion); - dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n", + pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n", res); region.start = 0x3F6; region.end = 0x3F6; res = &dev->resource[1]; res->flags = LEGACY_IO_RESOURCE; pcibios_bus_to_resource(dev->bus, res, ®ion); - dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n", + pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n", res); } if ((progif & 4) == 0) { @@ -1537,14 +1537,14 @@ int pci_setup_device(struct pci_dev *dev) res = &dev->resource[2]; res->flags = LEGACY_IO_RESOURCE; pcibios_bus_to_resource(dev->bus, res, ®ion); - dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n", + pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n", res); region.start = 0x376; region.end = 0x376; res = &dev->resource[3]; res->flags = LEGACY_IO_RESOURCE; pcibios_bus_to_resource(dev->bus, res, ®ion); - dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n", + pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n", res); } } @@ -1577,12 +1577,12 @@ int pci_setup_device(struct pci_dev *dev) break; default: /* unknown header */ - dev_err(&dev->dev, "unknown header type %02x, ignoring device\n", + pci_err(dev, "unknown header type %02x, ignoring device\n", dev->hdr_type); return -EIO; bad: - dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n", + pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", dev->class, dev->hdr_type); dev->class = PCI_CLASS_NOT_DEFINED << 8; } @@ -1606,7 +1606,7 @@ static void pci_configure_mps(struct pci_dev *dev) return; if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { - dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", + pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", mps, pci_name(bridge), p_mps); return; } @@ -1620,12 +1620,12 @@ static void pci_configure_mps(struct pci_dev *dev) rc = pcie_set_mps(dev, p_mps); if (rc) { - dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", + pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", p_mps); return; } - dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n", + pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", p_mps, mps, 128 << dev->pcie_mpss); } @@ -1645,8 +1645,7 @@ static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp) hpp = &pci_default_type0; if (hpp->revision > 1) { - dev_warn(&dev->dev, - "PCI settings rev %d not supported; using defaults\n", + pci_warn(dev, "PCI settings rev %d not supported; using defaults\n", hpp->revision); hpp = &pci_default_type0; } @@ -1684,7 +1683,7 @@ static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp) if (!pos) return; - dev_warn(&dev->dev, "PCI-X settings not supported\n"); + pci_warn(dev, "PCI-X settings not supported\n"); } static bool pcie_root_rcb_set(struct pci_dev *dev) @@ -1714,7 +1713,7 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp) return; if (hpp->revision > 1) { - dev_warn(&dev->dev, "PCIe settings rev %d not supported\n", + pci_warn(dev, "PCIe settings rev %d not supported\n", hpp->revision); return; } @@ -1818,7 +1817,7 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign) */ if (host->no_ext_tags) { if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { - dev_info(&dev->dev, "disabling Extended Tags\n"); + pci_info(dev, "disabling Extended Tags\n"); pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_EXT_TAG); } @@ -1826,7 +1825,7 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign) } if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { - dev_info(&dev->dev, "enabling Extended Tags\n"); + pci_info(dev, "enabling Extended Tags\n"); pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_EXT_TAG); } @@ -1871,10 +1870,42 @@ static void pci_configure_relaxed_ordering(struct pci_dev *dev) if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); - dev_info(&dev->dev, "Disable Relaxed Ordering because the Root Port didn't support it\n"); + pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n"); } } +static void pci_configure_ltr(struct pci_dev *dev) +{ +#ifdef CONFIG_PCIEASPM + u32 cap; + struct pci_dev *bridge; + + if (!pci_is_pcie(dev)) + return; + + pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); + if (!(cap & PCI_EXP_DEVCAP2_LTR)) + return; + + /* + * Software must not enable LTR in an Endpoint unless the Root + * Complex and all intermediate Switches indicate support for LTR. + * PCIe r3.1, sec 6.18. + */ + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) + dev->ltr_path = 1; + else { + bridge = pci_upstream_bridge(dev); + if (bridge && bridge->ltr_path) + dev->ltr_path = 1; + } + + if (dev->ltr_path) + pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, + PCI_EXP_DEVCTL2_LTR_EN); +#endif +} + static void pci_configure_device(struct pci_dev *dev) { struct hotplug_params hpp; @@ -1883,6 +1914,7 @@ static void pci_configure_device(struct pci_dev *dev) pci_configure_mps(dev); pci_configure_extended_tags(dev, NULL); pci_configure_relaxed_ordering(dev); + pci_configure_ltr(dev); memset(&hpp, 0, sizeof(hpp)); ret = pci_get_hp_params(dev, &hpp); @@ -2215,22 +2247,27 @@ static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn) static int only_one_child(struct pci_bus *bus) { - struct pci_dev *parent = bus->self; + struct pci_dev *bridge = bus->self; - if (!parent || !pci_is_pcie(parent)) + /* + * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so + * we scan for all possible devices, not just Device 0. + */ + if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) return 0; - if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT) - return 1; /* - * PCIe downstream ports are bridges that normally lead to only a - * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all - * possible devices, not just device 0. See PCIe spec r3.0, - * sec 7.3.1. + * A PCIe Downstream Port normally leads to a Link with only Device + * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan + * only for Device 0 in that situation. + * + * Checking has_secondary_link is a hack to identify Downstream + * Ports because sometimes Switches are configured such that the + * PCIe Port Type labels are backwards. */ - if (parent->has_secondary_link && - !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) + if (bridge && pci_is_pcie(bridge) && bridge->has_secondary_link) return 1; + return 0; } @@ -2334,7 +2371,7 @@ static void pcie_write_mps(struct pci_dev *dev, int mps) rc = pcie_set_mps(dev, mps); if (rc) - dev_err(&dev->dev, "Failed attempting to set the MPS\n"); + pci_err(dev, "Failed attempting to set the MPS\n"); } static void pcie_write_mrrs(struct pci_dev *dev) @@ -2364,12 +2401,12 @@ static void pcie_write_mrrs(struct pci_dev *dev) if (!rc) break; - dev_warn(&dev->dev, "Failed attempting to set the MRRS\n"); + pci_warn(dev, "Failed attempting to set the MRRS\n"); mrrs /= 2; } if (mrrs < 128) - dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); + pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); } static int pcie_bus_configure_set(struct pci_dev *dev, void *data) @@ -2389,7 +2426,7 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data) pcie_write_mps(dev, mps); pcie_write_mrrs(dev); - dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", + pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", pcie_get_mps(dev), 128 << dev->pcie_mpss, orig_mps, pcie_get_readrq(dev)); @@ -2874,7 +2911,7 @@ int pci_hp_add_bridge(struct pci_dev *dev) break; } if (busnr-- > end) { - dev_err(&dev->dev, "No bus number available for hot-added bridge\n"); + pci_err(dev, "No bus number available for hot-added bridge\n"); return -1; } diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 10684b17d0bd..2637c8c1c3ed 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -19,7 +19,6 @@ #include <linux/init.h> #include <linux/delay.h> #include <linux/acpi.h> -#include <linux/kallsyms.h> #include <linux/dmi.h> #include <linux/pci-aspm.h> #include <linux/ioport.h> @@ -66,7 +65,7 @@ static void quirk_passive_release(struct pci_dev *dev) while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { pci_read_config_byte(d, 0x82, &dlc); if (!(dlc & 1<<1)) { - dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); + pci_info(d, "PIIX3: Enabling Passive Release\n"); dlc |= 1<<1; pci_write_config_byte(d, 0x82, dlc); } @@ -86,7 +85,7 @@ static void quirk_isa_dma_hangs(struct pci_dev *dev) { if (!isa_dma_bridge_buggy) { isa_dma_bridge_buggy = 1; - dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); + pci_info(dev, "Activating ISA DMA hang workarounds\n"); } } /* @@ -115,7 +114,7 @@ static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) pm1a = inw(pmbase); if (pm1a & 0x10) { - dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); + pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); outw(0x10, pmbase); } } @@ -127,7 +126,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk static void quirk_nopcipci(struct pci_dev *dev) { if ((pci_pci_problems & PCIPCI_FAIL) == 0) { - dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); + pci_info(dev, "Disabling direct PCI/PCI transfers\n"); pci_pci_problems |= PCIPCI_FAIL; } } @@ -140,7 +139,7 @@ static void quirk_nopciamd(struct pci_dev *dev) pci_read_config_byte(dev, 0x08, &rev); if (rev == 0x13) { /* Erratum 24 */ - dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); + pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); pci_pci_problems |= PCIAGP_FAIL; } } @@ -152,7 +151,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopci static void quirk_triton(struct pci_dev *dev) { if ((pci_pci_problems&PCIPCI_TRITON) == 0) { - dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); + pci_info(dev, "Limiting direct PCI/PCI transfers\n"); pci_pci_problems |= PCIPCI_TRITON; } } @@ -212,7 +211,7 @@ static void quirk_vialatency(struct pci_dev *dev) busarb &= ~(1<<5); busarb |= (1<<4); pci_write_config_byte(dev, 0x76, busarb); - dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); + pci_info(dev, "Applying VIA southbridge workaround\n"); exit: pci_dev_put(p); } @@ -230,7 +229,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_viala static void quirk_viaetbf(struct pci_dev *dev) { if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { - dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); + pci_info(dev, "Limiting direct PCI/PCI transfers\n"); pci_pci_problems |= PCIPCI_VIAETBF; } } @@ -239,7 +238,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_via static void quirk_vsfx(struct pci_dev *dev) { if ((pci_pci_problems&PCIPCI_VSFX) == 0) { - dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); + pci_info(dev, "Limiting direct PCI/PCI transfers\n"); pci_pci_problems |= PCIPCI_VSFX; } } @@ -254,7 +253,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx) static void quirk_alimagik(struct pci_dev *dev) { if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { - dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); + pci_info(dev, "Limiting direct PCI/PCI transfers\n"); pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; } } @@ -268,7 +267,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagi static void quirk_natoma(struct pci_dev *dev) { if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { - dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); + pci_info(dev, "Limiting direct PCI/PCI transfers\n"); pci_pci_problems |= PCIPCI_NATOMA; } } @@ -313,7 +312,7 @@ static void quirk_extend_bar_to_page(struct pci_dev *dev) r->end = PAGE_SIZE - 1; r->start = 0; r->flags |= IORESOURCE_UNSET; - dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n", + pci_info(dev, "expanded BAR %d to page size: %pR\n", i, r); } } @@ -360,7 +359,7 @@ static void quirk_io(struct pci_dev *dev, int pos, unsigned size, bus_region.end = region + size - 1; pcibios_bus_to_resource(dev->bus, res, &bus_region); - dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", + pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", name, PCI_BASE_ADDRESS_0 + (pos << 2), res); } @@ -381,7 +380,7 @@ static void quirk_cs5536_vsa(struct pci_dev *dev) quirk_io(dev, 0, 8, name); /* SMB */ quirk_io(dev, 1, 256, name); /* GPIO */ quirk_io(dev, 2, 64, name); /* MFGPT */ - dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n", + pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", name); } } @@ -409,7 +408,7 @@ static void quirk_io_region(struct pci_dev *dev, int port, pcibios_bus_to_resource(dev->bus, res, &bus_region); if (!pci_claim_resource(dev, nr)) - dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name); + pci_info(dev, "quirk: %pR claimed by %s\n", res, name); } /* @@ -418,7 +417,7 @@ static void quirk_io_region(struct pci_dev *dev, int port, */ static void quirk_ati_exploding_mce(struct pci_dev *dev) { - dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); + pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ request_region(0x3b0, 0x0C, "RadeonIGP"); request_region(0x3d3, 0x01, "RadeonIGP"); @@ -441,7 +440,7 @@ static void quirk_amd_nl_class(struct pci_dev *pdev) /* Use "USB Device (not host controller)" class */ pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; - dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", + pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", class, pdev->class); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, @@ -488,8 +487,7 @@ static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int p * let's get enough confirmation reports first. */ base &= -size; - dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, - base + size - 1); + pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); } static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) @@ -514,8 +512,7 @@ static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int * reserve it, but let's get enough confirmation reports first. */ base &= -size; - dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, - base + size - 1); + pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); } /* @@ -644,7 +641,7 @@ static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const cha base &= ~(size-1); /* Just print it out for now. We should reserve it after more debugging */ - dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); + pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); } static void quirk_ich6_lpc(struct pci_dev *dev) @@ -679,7 +676,7 @@ static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const cha mask |= 3; /* Just print it out for now. We should reserve it after more debugging */ - dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); + pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); } /* ICH7-10 has the same common LPC generic IO decode registers */ @@ -758,7 +755,7 @@ static void quirk_xio2000a(struct pci_dev *dev) struct pci_dev *pdev; u16 command; - dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); + pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { pci_read_config_word(pdev, PCI_COMMAND, &command); if (command & PCI_COMMAND_FAST_BACK) @@ -788,7 +785,7 @@ static void quirk_via_ioapic(struct pci_dev *dev) else tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ - dev_info(&dev->dev, "%sbling VIA external APIC routing\n", + pci_info(dev, "%sbling VIA external APIC routing\n", tmp == 0 ? "Disa" : "Ena"); /* Offset 0x58: External APIC IRQ output control */ @@ -810,7 +807,7 @@ static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) pci_read_config_byte(dev, 0x5B, &misc_control2); if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { - dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); + pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); } } @@ -829,8 +826,8 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk static void quirk_amd_ioapic(struct pci_dev *dev) { if (dev->revision >= 0x02) { - dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); - dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); + pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); + pci_warn(dev, " : booting with the \"noapic\" option\n"); } } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); @@ -854,7 +851,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_lin static void quirk_amd_8131_mmrbc(struct pci_dev *dev) { if (dev->subordinate && dev->revision <= 0x12) { - dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", + pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", dev->revision); dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; } @@ -962,7 +959,7 @@ static void quirk_via_vlink(struct pci_dev *dev) pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); if (new_irq != irq) { - dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", + pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", irq, new_irq); udelay(15); /* unknown if delay really needed */ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); @@ -1011,7 +1008,7 @@ static void quirk_amd_ordering(struct pci_dev *dev) pci_read_config_dword(dev, 0x4C, &pcic); if ((pcic & 6) != 6) { pcic |= 6; - dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); + pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); pci_write_config_dword(dev, 0x4C, pcic); pci_read_config_dword(dev, 0x84, &pcic); pcic |= (1 << 23); /* Required in this mode */ @@ -1064,7 +1061,7 @@ static void quirk_mediagx_master(struct pci_dev *dev) pci_read_config_byte(dev, 0x41, ®); if (reg & 2) { reg &= ~2; - dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", + pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); pci_write_config_byte(dev, 0x41, reg); } @@ -1087,7 +1084,7 @@ static void quirk_disable_pxb(struct pci_dev *pdev) if (config & (1<<6)) { config &= ~(1<<6); pci_write_config_word(pdev, 0x40, config); - dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); + pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); } } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); @@ -1107,7 +1104,7 @@ static void quirk_amd_ide_mode(struct pci_dev *pdev) pci_write_config_byte(pdev, 0x40, tmp); pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; - dev_info(&pdev->dev, "set SATA to AHCI mode\n"); + pci_info(pdev, "set SATA to AHCI mode\n"); } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); @@ -1145,7 +1142,7 @@ static void quirk_ide_samemode(struct pci_dev *pdev) pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { - dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); + pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); prog &= ~5; pdev->class &= ~5; pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); @@ -1356,10 +1353,10 @@ static void asus_hides_smbus_lpc(struct pci_dev *dev) pci_write_config_word(dev, 0xF2, val & (~0x8)); pci_read_config_word(dev, 0xF2, &val); if (val & 0x8) - dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", + pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); else - dev_info(&dev->dev, "Enabled i801 SMBus device\n"); + pci_info(dev, "Enabled i801 SMBus device\n"); } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); @@ -1411,7 +1408,7 @@ static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) return; iounmap(asus_rcba_base); asus_rcba_base = NULL; - dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); + pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); } static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) @@ -1433,7 +1430,7 @@ static void quirk_sis_96x_smbus(struct pci_dev *dev) u8 val = 0; pci_read_config_byte(dev, 0x77, &val); if (val & 0x10) { - dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); + pci_info(dev, "Enabling SiS 96x SMBus\n"); pci_write_config_byte(dev, 0x77, val & ~0x10); } } @@ -1505,10 +1502,10 @@ static void asus_hides_ac97_lpc(struct pci_dev *dev) pci_write_config_byte(dev, 0x50, val & (~0xc0)); pci_read_config_byte(dev, 0x50, &val); if (val & 0xc0) - dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", + pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); else - dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); + pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); @@ -1599,7 +1596,7 @@ static void quirk_jmicron_async_suspend(struct pci_dev *dev) { if (dev->multifunction) { device_disable_async_suspend(&dev->dev); - dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); + pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); } } DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); @@ -1636,8 +1633,8 @@ static void quirk_pcie_mch(struct pci_dev *pdev) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, quirk_pcie_mch); +DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); /* * It's possible for the MSI to get corrupted if shpc and acpi @@ -1646,7 +1643,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, quirk_pcie_mch); static void quirk_pcie_pxh(struct pci_dev *dev) { dev->no_msi = 1; - dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); + pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); @@ -1692,7 +1689,7 @@ static void quirk_radeon_pm(struct pci_dev *dev) dev->subsystem_device == 0x00e2) { if (dev->d3_delay < 20) { dev->d3_delay = 20; - dev_info(&dev->dev, "extending delay after power-on from D3 to %d msec\n", + pci_info(dev, "extending delay after power-on from D3 to %d msec\n", dev->d3_delay); } } @@ -1736,7 +1733,7 @@ static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) return; dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; - dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n", + pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", dev->vendor, dev->device); } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); @@ -1779,7 +1776,7 @@ static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); - dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", + pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", dev->vendor, dev->device); } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); @@ -1812,7 +1809,7 @@ static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); - dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", + pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", dev->vendor, dev->device); } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); @@ -1845,7 +1842,7 @@ static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) pci_config_dword &= ~AMD_813X_NOIOAMODE; pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); - dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", + pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", dev->vendor, dev->device); } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); @@ -1864,12 +1861,12 @@ static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); if (!pci_config_word) { - dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n", + pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", dev->vendor, dev->device); return; } pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); - dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", + pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", dev->vendor, dev->device); } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); @@ -1913,7 +1910,7 @@ static void quirk_plx_pci9050(struct pci_dev *dev) if (pci_resource_len(dev, bar) == 0x80 && (pci_resource_start(dev, bar) & 0x80)) { struct resource *r = &dev->resource[bar]; - dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", + pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", bar); r->flags |= IORESOURCE_UNSET; r->start = 0; @@ -1960,7 +1957,7 @@ static void quirk_netmos(struct pci_dev *dev) case PCI_DEVICE_ID_NETMOS_9845: case PCI_DEVICE_ID_NETMOS_9855: if (num_parallel) { - dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", + pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", dev->device, num_parallel, num_serial); dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | (dev->class & 0xff); @@ -2046,13 +2043,13 @@ static void quirk_e100_interrupt(struct pci_dev *dev) /* Convert from PCI bus to resource space. */ csr = ioremap(pci_resource_start(dev, 0), 8); if (!csr) { - dev_warn(&dev->dev, "Can't map e100 registers\n"); + pci_warn(dev, "Can't map e100 registers\n"); return; } cmd_hi = readb(csr + 3); if (cmd_hi == 0) { - dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n"); + pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); writeb(1, csr + 3); } @@ -2067,7 +2064,7 @@ DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, */ static void quirk_disable_aspm_l0s(struct pci_dev *dev) { - dev_info(&dev->dev, "Disabling L0s\n"); + pci_info(dev, "Disabling L0s\n"); pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); @@ -2097,7 +2094,7 @@ static void fixup_rev1_53c810(struct pci_dev *dev) return; dev->class = PCI_CLASS_STORAGE_SCSI << 8; - dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", + pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", class, dev->class); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); @@ -2110,7 +2107,7 @@ static void quirk_p64h2_1k_io(struct pci_dev *dev) pci_read_config_word(dev, 0x40, &en1k); if (en1k & 0x200) { - dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); + pci_info(dev, "Enable I/O Space to 1KB granularity\n"); dev->io_window_1k = 1; } } @@ -2126,7 +2123,7 @@ static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) if (pci_read_config_byte(dev, 0xf41, &b) == 0) { if (!(b & 0x20)) { pci_write_config_byte(dev, 0xf41, b | 0x20); - dev_info(&dev->dev, "Linking AER extended capability\n"); + pci_info(dev, "Linking AER extended capability\n"); } } } @@ -2164,7 +2161,7 @@ static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) /* Turn off PCI Bus Parking */ pci_write_config_byte(dev, 0x76, b ^ 0x40); - dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n"); + pci_info(dev, "Disabling VIA CX700 PCI parking\n"); } } @@ -2179,7 +2176,7 @@ static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) /* Disable "Read FIFO Timer" */ pci_write_config_byte(dev, 0x77, 0x0); - dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n"); + pci_info(dev, "Disabling VIA CX700 PCI caching\n"); } } } @@ -2196,7 +2193,7 @@ static void quirk_blacklist_vpd(struct pci_dev *dev) { if (dev->vpd) { dev->vpd->len = 0; - dev_warn(&dev->dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n"); + pci_warn(dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n"); } } @@ -2312,7 +2309,7 @@ static void quirk_unhide_mch_dev6(struct pci_dev *dev) u8 reg; if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { - dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); + pci_info(dev, "Enabling MCH 'Overflow' Device\n"); pci_write_config_byte(dev, 0xF4, reg | 0x02); } } @@ -2351,7 +2348,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); static void quirk_disable_all_msi(struct pci_dev *dev) { pci_no_msi(); - dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); + pci_warn(dev, "MSI quirk detected; MSI disabled\n"); } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); @@ -2366,7 +2363,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); static void quirk_disable_msi(struct pci_dev *dev) { if (dev->subordinate) { - dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); + pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; } } @@ -2406,7 +2403,7 @@ static int msi_ht_cap_enabled(struct pci_dev *dev) if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, &flags) == 0) { - dev_info(&dev->dev, "Found %s HT MSI Mapping\n", + pci_info(dev, "Found %s HT MSI Mapping\n", flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled"); return (flags & HT_MSI_FLAGS_ENABLE) != 0; @@ -2422,7 +2419,7 @@ static int msi_ht_cap_enabled(struct pci_dev *dev) static void quirk_msi_ht_cap(struct pci_dev *dev) { if (dev->subordinate && !msi_ht_cap_enabled(dev)) { - dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); + pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; } } @@ -2446,7 +2443,7 @@ static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) if (!pdev) return; if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { - dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); + pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; } pci_dev_put(pdev); @@ -2465,7 +2462,7 @@ static void ht_enable_msi_mapping(struct pci_dev *dev) if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, &flags) == 0) { - dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); + pci_info(dev, "Enabling HT MSI Mapping\n"); pci_write_config_byte(dev, pos + HT_MSI_FLAGS, flags | HT_MSI_FLAGS_ENABLE); @@ -2492,7 +2489,7 @@ static void nvenet_msi_disable(struct pci_dev *dev) if (board_name && (strstr(board_name, "P5N32-SLI PREMIUM") || strstr(board_name, "P5N32-E SLI"))) { - dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n"); + pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); dev->no_msi = 1; } } @@ -2669,7 +2666,7 @@ static void ht_disable_msi_mapping(struct pci_dev *dev) if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, &flags) == 0) { - dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); + pci_info(dev, "Disabling HT MSI Mapping\n"); pci_write_config_byte(dev, pos + HT_MSI_FLAGS, flags & ~HT_MSI_FLAGS_ENABLE); @@ -2699,9 +2696,10 @@ static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) * HT MSI mapping should be disabled on devices that are below * a non-Hypertransport host bridge. Locate the host bridge... */ - host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); + host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, + PCI_DEVFN(0, 0)); if (host_bridge == NULL) { - dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); + pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); return; } @@ -2770,7 +2768,7 @@ static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) { /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ if (dev->revision < 0x18) { - dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n"); + pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; } } @@ -2899,8 +2897,8 @@ static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) pci_write_config_byte(dev, 0x8E, write_enable); pci_write_config_byte(dev, 0x8D, write_target); - dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); - dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); + pci_notice(dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); + pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); @@ -2935,7 +2933,7 @@ static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) pci_write_config_byte(dev, 0xe1, 0x32); pci_write_config_byte(dev, 0xfc, 0x00); - dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n"); + pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); } pci_read_config_byte(dev, 0xCB, &disable); @@ -2948,8 +2946,8 @@ static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) pci_write_config_byte(dev, 0xCB, disable | 0x02); pci_write_config_byte(dev, 0xCA, write_enable); - dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); - dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); + pci_notice(dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); + pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); @@ -2990,7 +2988,7 @@ static void fixup_ti816x_class(struct pci_dev *dev) /* TI 816x devices do not have class code set when in PCIe boot mode */ dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; - dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n", + pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", class, dev->class); } DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, @@ -3032,7 +3030,7 @@ static void quirk_intel_mc_errata(struct pci_dev *dev) */ err = pci_read_config_word(dev, 0x48, &rcc); if (err) { - dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n"); + pci_err(dev, "Error attempting to read the read completion coalescing register\n"); return; } @@ -3043,7 +3041,7 @@ static void quirk_intel_mc_errata(struct pci_dev *dev) err = pci_write_config_word(dev, 0x48, rcc); if (err) { - dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n"); + pci_err(dev, "Error attempting to write the read completion coalescing register\n"); return; } @@ -3108,7 +3106,7 @@ static ktime_t fixup_debug_start(struct pci_dev *dev, { ktime_t calltime = 0; - dev_dbg(&dev->dev, "calling %pF\n", fn); + pci_dbg(dev, "calling %pF\n", fn); if (initcall_debug) { pr_debug("calling %pF @ %i for %s\n", fn, task_pid_nr(current), dev_name(&dev->dev)); @@ -3150,13 +3148,13 @@ static void disable_igfx_irq(struct pci_dev *dev) { void __iomem *regs = pci_iomap(dev, 0, 0); if (regs == NULL) { - dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n"); + pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); return; } /* Check if any interrupt line is still enabled */ if (readl(regs + I915_DEIER_REG) != 0) { - dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); + pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); writel(0, regs + I915_DEIER_REG); } @@ -3317,13 +3315,13 @@ static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ if (pci_enable_device_mem(pdev)) { - dev_warn(&pdev->dev, "Can't enable device memory\n"); + pci_warn(pdev, "Can't enable device memory\n"); return; } fw_ver = ioremap(pci_resource_start(pdev, 0), 4); if (!fw_ver) { - dev_warn(&pdev->dev, "Can't map ConnectX-4 initialization segment\n"); + pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); goto out; } @@ -3335,7 +3333,7 @@ static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) fw_subminor = fw_sub_min & 0xffff; if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { - dev_warn(&pdev->dev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", + pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", fw_major, fw_minor, fw_subminor, pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); pdev->broken_intx_masking = 1; @@ -3473,7 +3471,7 @@ static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) return; - dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n"); + pci_info(dev, "quirk: cutting power to thunderbolt controller...\n"); /* magic sequence */ acpi_execute_simple_method(SXIO, NULL, 1); @@ -3524,7 +3522,7 @@ static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev) nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI) || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8) goto out; - dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n"); + pci_info(dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n"); device_pm_wait_for_dev(&dev->dev, &nhi->dev); out: pci_dev_put(nhi); @@ -3740,7 +3738,7 @@ static int reset_ivb_igd(struct pci_dev *dev, int probe) goto reset_complete; msleep(10); } while (time_before(jiffies, timeout)); - dev_warn(&dev->dev, "timeout during reset\n"); + pci_warn(dev, "timeout during reset\n"); reset_complete: iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); @@ -4012,7 +4010,7 @@ static void quirk_tw686x_class(struct pci_dev *pdev) /* Use "Multimedia controller" class */ pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; - dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n", + pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", class, pdev->class); } DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, @@ -4032,7 +4030,7 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, static void quirk_relaxedordering_disable(struct pci_dev *dev) { dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; - dev_info(&dev->dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); + pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); } /* @@ -4141,11 +4139,11 @@ static void quirk_disable_root_port_attributes(struct pci_dev *pdev) struct pci_dev *root_port = pci_find_pcie_root_port(pdev); if (!root_port) { - dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n"); + pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); return; } - dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", + pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", dev_name(&pdev->dev)); pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN | @@ -4339,7 +4337,7 @@ static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV); int ret = acs_flags & ~flags ? 0 : 1; - dev_info(&dev->dev, "Using QCOM ACS Quirk (%d)\n", ret); + pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret); return ret; } @@ -4591,7 +4589,7 @@ static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { updcr = readl(rcba_mem + INTEL_UPDCR_REG); if (updcr & INTEL_UPDCR_REG_MASK) { - dev_info(&dev->dev, "Disabling UPDCR peer decodes\n"); + pci_info(dev, "Disabling UPDCR peer decodes\n"); updcr &= ~INTEL_UPDCR_REG_MASK; writel(updcr, rcba_mem + INTEL_UPDCR_REG); } @@ -4618,7 +4616,7 @@ static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) */ pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); if (!(mpc & INTEL_MPC_REG_IRBNCE)) { - dev_info(&dev->dev, "Enabling MPC IRBNCE\n"); + pci_info(dev, "Enabling MPC IRBNCE\n"); mpc |= INTEL_MPC_REG_IRBNCE; pci_write_config_word(dev, INTEL_MPC_REG, mpc); } @@ -4630,7 +4628,7 @@ static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) return -ENOTTY; if (pci_quirk_enable_intel_lpc_acs(dev)) { - dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n"); + pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); return 0; } @@ -4638,7 +4636,7 @@ static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; - dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n"); + pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); return 0; } @@ -4665,7 +4663,7 @@ static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); - dev_info(&dev->dev, "Intel SPT PCH root port ACS workaround enabled\n"); + pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); return 0; } @@ -4800,7 +4798,7 @@ static void quirk_no_ext_tags(struct pci_dev *pdev) return; bridge->no_ext_tags = 1; - dev_info(&pdev->dev, "disabling Extended Tags (this device can't handle them)\n"); + pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); } @@ -4815,7 +4813,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); */ static void quirk_no_ats(struct pci_dev *pdev) { - dev_info(&pdev->dev, "disabling ATS (broken on this device)\n"); + pci_info(pdev, "disabling ATS (broken on this device)\n"); pdev->ats_cap = 0; } diff --git a/drivers/pci/rom.c b/drivers/pci/rom.c index 68ab7c17955a..2f8fcd9ba5c1 100644 --- a/drivers/pci/rom.c +++ b/drivers/pci/rom.c @@ -92,15 +92,15 @@ size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size) void __iomem *pds; /* Standard PCI ROMs start out with these bytes 55 AA */ if (readw(image) != 0xAA55) { - dev_info(&pdev->dev, "Invalid PCI ROM header signature: expecting 0xaa55, got %#06x\n", - readw(image)); + pci_info(pdev, "Invalid PCI ROM header signature: expecting 0xaa55, got %#06x\n", + readw(image)); break; } /* get the PCI data structure and check its "PCIR" signature */ pds = image + readw(image + 24); if (readl(pds) != 0x52494350) { - dev_info(&pdev->dev, "Invalid PCI ROM data signature: expecting 0x52494350, got %#010x\n", - readl(pds)); + pci_info(pdev, "Invalid PCI ROM data signature: expecting 0x52494350, got %#010x\n", + readl(pds)); break; } last_image = readb(pds + 21) & 0x80; diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index b1ad466199ad..b56bfdc18b46 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -67,10 +67,8 @@ static int add_to_list(struct list_head *head, struct pci_dev_resource *tmp; tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); - if (!tmp) { - pr_warn("add_to_list: kmalloc() failed!\n"); + if (!tmp) return -ENOMEM; - } tmp->res = res; tmp->dev = dev; @@ -152,7 +150,7 @@ static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) r_align = pci_resource_alignment(dev, r); if (!r_align) { - dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n", + pci_warn(dev, "BAR %d: %pR has bogus alignment\n", i, r); continue; } @@ -260,7 +258,7 @@ static void reassign_resources_sorted(struct list_head *realloc_head, (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); if (pci_reassign_resource(add_res->dev, idx, add_size, align)) - dev_printk(KERN_DEBUG, &add_res->dev->dev, + pci_printk(KERN_DEBUG, add_res->dev, "failed to add %llx res[%d]=%pR\n", (unsigned long long)add_size, idx, res); @@ -519,7 +517,7 @@ void pci_setup_cardbus(struct pci_bus *bus) struct resource *res; struct pci_bus_region region; - dev_info(&bridge->dev, "CardBus bridge to %pR\n", + pci_info(bridge, "CardBus bridge to %pR\n", &bus->busn_res); res = bus->resource[0]; @@ -529,7 +527,7 @@ void pci_setup_cardbus(struct pci_bus *bus) * The IO resource is allocated a range twice as large as it * would normally need. This allows us to set both IO regs. */ - dev_info(&bridge->dev, " bridge window %pR\n", res); + pci_info(bridge, " bridge window %pR\n", res); pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, region.start); pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, @@ -539,7 +537,7 @@ void pci_setup_cardbus(struct pci_bus *bus) res = bus->resource[1]; pcibios_resource_to_bus(bridge->bus, ®ion, res); if (res->flags & IORESOURCE_IO) { - dev_info(&bridge->dev, " bridge window %pR\n", res); + pci_info(bridge, " bridge window %pR\n", res); pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, region.start); pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, @@ -549,7 +547,7 @@ void pci_setup_cardbus(struct pci_bus *bus) res = bus->resource[2]; pcibios_resource_to_bus(bridge->bus, ®ion, res); if (res->flags & IORESOURCE_MEM) { - dev_info(&bridge->dev, " bridge window %pR\n", res); + pci_info(bridge, " bridge window %pR\n", res); pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, region.start); pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, @@ -559,7 +557,7 @@ void pci_setup_cardbus(struct pci_bus *bus) res = bus->resource[3]; pcibios_resource_to_bus(bridge->bus, ®ion, res); if (res->flags & IORESOURCE_MEM) { - dev_info(&bridge->dev, " bridge window %pR\n", res); + pci_info(bridge, " bridge window %pR\n", res); pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, region.start); pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, @@ -602,7 +600,7 @@ static void pci_setup_bridge_io(struct pci_dev *bridge) l = ((u16) io_limit_lo << 8) | io_base_lo; /* Set up upper 16 bits of I/O base/limit. */ io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); - dev_info(&bridge->dev, " bridge window %pR\n", res); + pci_info(bridge, " bridge window %pR\n", res); } else { /* Clear upper 16 bits of I/O base/limit. */ io_upper16 = 0; @@ -628,7 +626,7 @@ static void pci_setup_bridge_mmio(struct pci_dev *bridge) if (res->flags & IORESOURCE_MEM) { l = (region.start >> 16) & 0xfff0; l |= region.end & 0xfff00000; - dev_info(&bridge->dev, " bridge window %pR\n", res); + pci_info(bridge, " bridge window %pR\n", res); } else { l = 0x0000fff0; } @@ -657,7 +655,7 @@ static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge) bu = upper_32_bits(region.start); lu = upper_32_bits(region.end); } - dev_info(&bridge->dev, " bridge window %pR\n", res); + pci_info(bridge, " bridge window %pR\n", res); } else { l = 0x0000fff0; } @@ -672,7 +670,7 @@ static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) { struct pci_dev *bridge = bus->self; - dev_info(&bridge->dev, "PCI bridge to %pR\n", + pci_info(bridge, "PCI bridge to %pR\n", &bus->busn_res); if (type & IORESOURCE_IO) @@ -944,7 +942,7 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, resource_size(b_res), min_align); if (!size0 && !size1) { if (b_res->start || b_res->end) - dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n", + pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n", b_res, &bus->busn_res); b_res->flags = 0; return; @@ -956,7 +954,7 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, if (size1 > size0 && realloc_head) { add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align); - dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx\n", + pci_printk(KERN_DEBUG, bus->self, "bridge window %pR to %pR add_size %llx\n", b_res, &bus->busn_res, (unsigned long long)size1-size0); } @@ -1061,7 +1059,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, if (order < 0) order = 0; if (order >= ARRAY_SIZE(aligns)) { - dev_warn(&dev->dev, "disabling BAR %d: %pR (bad alignment %#llx)\n", + pci_warn(dev, "disabling BAR %d: %pR (bad alignment %#llx)\n", i, r, (unsigned long long) align); r->flags = 0; continue; @@ -1093,7 +1091,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, resource_size(b_res), add_align); if (!size0 && !size1) { if (b_res->start || b_res->end) - dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n", + pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n", b_res, &bus->busn_res); b_res->flags = 0; return 0; @@ -1103,7 +1101,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, b_res->flags |= IORESOURCE_STARTALIGN; if (size1 > size0 && realloc_head) { add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align); - dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx add_align %llx\n", + pci_printk(KERN_DEBUG, bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n", b_res, &bus->busn_res, (unsigned long long) (size1 - size0), (unsigned long long) add_align); @@ -1407,7 +1405,7 @@ void __pci_bus_assign_resources(const struct pci_bus *bus, break; default: - dev_info(&dev->dev, "not setting up bridge for bus %04x:%02x\n", + pci_info(dev, "not setting up bridge for bus %04x:%02x\n", pci_domain_nr(b), b->number); break; } @@ -1513,7 +1511,7 @@ static void __pci_bridge_assign_resources(const struct pci_dev *bridge, break; default: - dev_info(&bridge->dev, "not setting up bridge for bus %04x:%02x\n", + pci_info(bridge, "not setting up bridge for bus %04x:%02x\n", pci_domain_nr(b), b->number); break; } @@ -1571,7 +1569,7 @@ static void pci_bridge_release_resources(struct pci_bus *bus, release_child_resources(r); if (!release_resource(r)) { type = old_flags = r->flags & PCI_RES_TYPE_MASK; - dev_printk(KERN_DEBUG, &dev->dev, "resource %d %pR released\n", + pci_printk(KERN_DEBUG, dev, "resource %d %pR released\n", PCI_BRIDGE_RESOURCES + idx, r); /* keep the old size */ r->end = resource_size(r) - 1; @@ -1874,7 +1872,7 @@ static void extend_bridge_window(struct pci_dev *bridge, struct resource *res, return; dev_res->add_size = available - resource_size(res); - dev_dbg(&bridge->dev, "bridge window %pR extended by %pa\n", res, + pci_dbg(bridge, "bridge window %pR extended by %pa\n", res, &dev_res->add_size); } @@ -2085,7 +2083,7 @@ again: enable_all: retval = pci_reenable_device(bridge); if (retval) - dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval); + pci_err(bridge, "Error reenabling bridge (%d)\n", retval); pci_set_master(bridge); } EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); @@ -2119,7 +2117,7 @@ int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type) if (ret) goto cleanup; - dev_info(&bridge->dev, "BAR %d: releasing %pR\n", + pci_info(bridge, "BAR %d: releasing %pR\n", i, res); if (res->parent) diff --git a/drivers/pci/setup-irq.c b/drivers/pci/setup-irq.c index 86106c44ce94..774defe2f7e8 100644 --- a/drivers/pci/setup-irq.c +++ b/drivers/pci/setup-irq.c @@ -25,7 +25,7 @@ void pci_assign_irq(struct pci_dev *dev) struct pci_host_bridge *hbrg = pci_find_host_bridge(dev->bus); if (!(hbrg->map_irq)) { - dev_dbg(&dev->dev, "runtime IRQ mapping not provided by arch\n"); + pci_dbg(dev, "runtime IRQ mapping not provided by arch\n"); return; } @@ -55,7 +55,7 @@ void pci_assign_irq(struct pci_dev *dev) } dev->irq = irq; - dev_dbg(&dev->dev, "assign IRQ: got %d\n", dev->irq); + pci_dbg(dev, "assign IRQ: got %d\n", dev->irq); /* Always tell the device, so the driver knows what is the real IRQ to use; the device does not use it. */ diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index e815111f3f81..369d48d6c6f1 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -103,7 +103,7 @@ static void pci_std_update_resource(struct pci_dev *dev, int resno) pci_read_config_dword(dev, reg, &check); if ((new ^ check) & mask) { - dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n", + pci_err(dev, "BAR %d: error updating (%#08x != %#08x)\n", resno, new, check); } @@ -112,7 +112,7 @@ static void pci_std_update_resource(struct pci_dev *dev, int resno) pci_write_config_dword(dev, reg + 4, new); pci_read_config_dword(dev, reg + 4, &check); if (check != new) { - dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n", + pci_err(dev, "BAR %d: error updating (high %#08x != %#08x)\n", resno, new, check); } } @@ -137,7 +137,7 @@ int pci_claim_resource(struct pci_dev *dev, int resource) struct resource *root, *conflict; if (res->flags & IORESOURCE_UNSET) { - dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n", + pci_info(dev, "can't claim BAR %d %pR: no address assigned\n", resource, res); return -EINVAL; } @@ -152,7 +152,7 @@ int pci_claim_resource(struct pci_dev *dev, int resource) root = pci_find_parent_resource(dev, res); if (!root) { - dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n", + pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n", resource, res); res->flags |= IORESOURCE_UNSET; return -EINVAL; @@ -160,7 +160,7 @@ int pci_claim_resource(struct pci_dev *dev, int resource) conflict = request_resource_conflict(root, res); if (conflict) { - dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n", + pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n", resource, res, conflict->name, conflict); res->flags |= IORESOURCE_UNSET; return -EBUSY; @@ -172,7 +172,7 @@ EXPORT_SYMBOL(pci_claim_resource); void pci_disable_bridge_window(struct pci_dev *dev) { - dev_info(&dev->dev, "disabling bridge mem windows\n"); + pci_info(dev, "disabling bridge mem windows\n"); /* MMIO Base/Limit */ pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0); @@ -221,11 +221,11 @@ static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, root = &iomem_resource; } - dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n", + pci_info(dev, "BAR %d: trying firmware assignment %pR\n", resno, res); conflict = request_resource_conflict(root, res); if (conflict) { - dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n", + pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n", resno, res, conflict->name, conflict); res->start = start; res->end = end; @@ -324,7 +324,7 @@ int pci_assign_resource(struct pci_dev *dev, int resno) res->flags |= IORESOURCE_UNSET; align = pci_resource_alignment(dev, res); if (!align) { - dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n", + pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n", resno, res); return -EINVAL; } @@ -338,19 +338,18 @@ int pci_assign_resource(struct pci_dev *dev, int resno) * working, which is better than just leaving it disabled. */ if (ret < 0) { - dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res); + pci_info(dev, "BAR %d: no space for %pR\n", resno, res); ret = pci_revert_fw_address(res, dev, resno, size); } if (ret < 0) { - dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno, - res); + pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res); return ret; } res->flags &= ~IORESOURCE_UNSET; res->flags &= ~IORESOURCE_STARTALIGN; - dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res); + pci_info(dev, "BAR %d: assigned %pR\n", resno, res); if (resno < PCI_BRIDGE_RESOURCES) pci_update_resource(dev, resno); @@ -372,7 +371,7 @@ int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsiz flags = res->flags; res->flags |= IORESOURCE_UNSET; if (!res->parent) { - dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n", + pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n", resno, res); return -EINVAL; } @@ -382,14 +381,14 @@ int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsiz ret = _pci_assign_resource(dev, resno, new_size, min_align); if (ret) { res->flags = flags; - dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n", + pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n", resno, res, (unsigned long long) addsize); return ret; } res->flags &= ~IORESOURCE_UNSET; res->flags &= ~IORESOURCE_STARTALIGN; - dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n", + pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n", resno, res, (unsigned long long) addsize); if (resno < PCI_BRIDGE_RESOURCES) pci_update_resource(dev, resno); @@ -401,7 +400,7 @@ void pci_release_resource(struct pci_dev *dev, int resno) { struct resource *res = dev->resource + resno; - dev_info(&dev->dev, "BAR %d: releasing %pR\n", resno, res); + pci_info(dev, "BAR %d: releasing %pR\n", resno, res); release_resource(res); res->end = resource_size(res) - 1; res->start = 0; @@ -477,13 +476,13 @@ int pci_enable_resources(struct pci_dev *dev, int mask) continue; if (r->flags & IORESOURCE_UNSET) { - dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n", + pci_err(dev, "can't enable device: BAR %d %pR not assigned\n", i, r); return -EINVAL; } if (!r->parent) { - dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n", + pci_err(dev, "can't enable device: BAR %d %pR not claimed\n", i, r); return -EINVAL; } @@ -495,8 +494,7 @@ int pci_enable_resources(struct pci_dev *dev, int mask) } if (cmd != old_cmd) { - dev_info(&dev->dev, "enabling device (%04x -> %04x)\n", - old_cmd, cmd); + pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd); pci_write_config_word(dev, PCI_COMMAND, cmd); } return 0; diff --git a/drivers/pci/syscall.c b/drivers/pci/syscall.c index 83efa001c2e7..e725f99b5479 100644 --- a/drivers/pci/syscall.c +++ b/drivers/pci/syscall.c @@ -28,7 +28,7 @@ SYSCALL_DEFINE5(pciconfig_read, unsigned long, bus, unsigned long, dfn, return -EPERM; err = -ENODEV; - dev = pci_get_bus_and_slot(bus, dfn); + dev = pci_get_domain_bus_and_slot(0, bus, dfn); if (!dev) goto error; @@ -96,7 +96,7 @@ SYSCALL_DEFINE5(pciconfig_write, unsigned long, bus, unsigned long, dfn, if (!capable(CAP_SYS_ADMIN)) return -EPERM; - dev = pci_get_bus_and_slot(bus, dfn); + dev = pci_get_domain_bus_and_slot(0, bus, dfn); if (!dev) return -ENODEV; diff --git a/drivers/pci/vc.c b/drivers/pci/vc.c index 1fa3a3219c45..881b9861aed4 100644 --- a/drivers/pci/vc.c +++ b/drivers/pci/vc.c @@ -57,7 +57,7 @@ static void pci_vc_load_arb_table(struct pci_dev *dev, int pos) PCI_VC_PORT_STATUS_TABLE)) return; - dev_err(&dev->dev, "VC arbitration table failed to load\n"); + pci_err(dev, "VC arbitration table failed to load\n"); } /** @@ -85,7 +85,7 @@ static void pci_vc_load_port_arb_table(struct pci_dev *dev, int pos, int res) if (pci_wait_for_pending(dev, status_pos, PCI_VC_RES_STATUS_TABLE)) return; - dev_err(&dev->dev, "VC%d port arbitration table failed to load\n", res); + pci_err(dev, "VC%d port arbitration table failed to load\n", res); } /** @@ -161,11 +161,11 @@ enable: pci_write_config_dword(dev, ctrl_pos, ctrl); if (!pci_wait_for_pending(dev, status_pos, PCI_VC_RES_STATUS_NEGO)) - dev_err(&dev->dev, "VC%d negotiation stuck pending\n", id); + pci_err(dev, "VC%d negotiation stuck pending\n", id); if (link && !pci_wait_for_pending(link, status_pos2, PCI_VC_RES_STATUS_NEGO)) - dev_err(&link->dev, "VC%d negotiation stuck pending\n", id); + pci_err(link, "VC%d negotiation stuck pending\n", id); } /** @@ -195,8 +195,7 @@ static int pci_vc_do_save_buffer(struct pci_dev *dev, int pos, /* Sanity check buffer size for save/restore */ if (buf && save_state->cap.size != pci_vc_do_save_buffer(dev, pos, NULL, save)) { - dev_err(&dev->dev, - "VC save buffer size does not match @0x%x\n", pos); + pci_err(dev, "VC save buffer size does not match @0x%x\n", pos); return -ENOMEM; } @@ -366,14 +365,14 @@ int pci_save_vc_state(struct pci_dev *dev) save_state = pci_find_saved_ext_cap(dev, vc_caps[i].id); if (!save_state) { - dev_err(&dev->dev, "%s buffer not found in %s\n", + pci_err(dev, "%s buffer not found in %s\n", vc_caps[i].name, __func__); return -ENOMEM; } ret = pci_vc_do_save_buffer(dev, pos, save_state, true); if (ret) { - dev_err(&dev->dev, "%s save unsuccessful %s\n", + pci_err(dev, "%s save unsuccessful %s\n", vc_caps[i].name, __func__); return ret; } @@ -426,8 +425,7 @@ void pci_allocate_vc_save_buffers(struct pci_dev *dev) len = pci_vc_do_save_buffer(dev, pos, NULL, false); if (pci_add_ext_cap_save_buffer(dev, vc_caps[i].id, len)) - dev_err(&dev->dev, - "unable to preallocate %s save buffer\n", + pci_err(dev, "unable to preallocate %s save buffer\n", vc_caps[i].name); } } diff --git a/drivers/pci/xen-pcifront.c b/drivers/pci/xen-pcifront.c index 8fc2e9532575..69888196756d 100644 --- a/drivers/pci/xen-pcifront.c +++ b/drivers/pci/xen-pcifront.c @@ -261,8 +261,8 @@ static int pci_frontend_enable_msix(struct pci_dev *dev, struct msi_desc *entry; if (nvec > SH_INFO_MAX_VEC) { - dev_err(&dev->dev, "too much vector for pci frontend: %x." - " Increase SH_INFO_MAX_VEC.\n", nvec); + pci_err(dev, "too many vectors (0x%x) for PCI frontend:" + " Increase SH_INFO_MAX_VEC\n", nvec); return -EINVAL; } @@ -281,7 +281,7 @@ static int pci_frontend_enable_msix(struct pci_dev *dev, /* we get the result */ for (i = 0; i < nvec; i++) { if (op.msix_entries[i].vector <= 0) { - dev_warn(&dev->dev, "MSI-X entry %d is invalid: %d!\n", + pci_warn(dev, "MSI-X entry %d is invalid: %d!\n", i, op.msix_entries[i].vector); err = -EINVAL; vector[i] = -1; @@ -295,7 +295,7 @@ static int pci_frontend_enable_msix(struct pci_dev *dev, err = op.value; } } else { - dev_err(&dev->dev, "enable msix get err %x\n", err); + pci_err(dev, "enable msix get err %x\n", err); } return err; } @@ -316,7 +316,7 @@ static void pci_frontend_disable_msix(struct pci_dev *dev) /* What should do for error ? */ if (err) - dev_err(&dev->dev, "pci_disable_msix get err %x\n", err); + pci_err(dev, "pci_disable_msix get err %x\n", err); } static int pci_frontend_enable_msi(struct pci_dev *dev, int vector[]) @@ -335,13 +335,13 @@ static int pci_frontend_enable_msi(struct pci_dev *dev, int vector[]) if (likely(!err)) { vector[0] = op.value; if (op.value <= 0) { - dev_warn(&dev->dev, "MSI entry is invalid: %d!\n", + pci_warn(dev, "MSI entry is invalid: %d!\n", op.value); err = -EINVAL; vector[0] = -1; } } else { - dev_err(&dev->dev, "pci frontend enable msi failed for dev " + pci_err(dev, "pci frontend enable msi failed for dev " "%x:%x\n", op.bus, op.devfn); err = -EINVAL; } @@ -560,7 +560,7 @@ static void free_root_bus_devs(struct pci_bus *bus) while (!list_empty(&bus->devices)) { dev = container_of(bus->devices.next, struct pci_dev, bus_list); - dev_dbg(&dev->dev, "removing device\n"); + pci_dbg(dev, "removing device\n"); pci_stop_and_remove_bus_device(dev); } } @@ -595,6 +595,7 @@ static pci_ers_result_t pcifront_common_process(int cmd, struct pci_driver *pdrv; int bus = pdev->sh_info->aer_op.bus; int devfn = pdev->sh_info->aer_op.devfn; + int domain = pdev->sh_info->aer_op.domain; struct pci_dev *pcidev; int flag = 0; @@ -603,7 +604,7 @@ static pci_ers_result_t pcifront_common_process(int cmd, cmd, bus, devfn); result = PCI_ERS_RESULT_NONE; - pcidev = pci_get_bus_and_slot(bus, devfn); + pcidev = pci_get_domain_bus_and_slot(domain, bus, devfn); if (!pcidev || !pcidev->driver) { dev_err(&pdev->xdev->dev, "device or AER driver is NULL\n"); pci_dev_put(pcidev); @@ -613,8 +614,7 @@ static pci_ers_result_t pcifront_common_process(int cmd, if (pdrv) { if (pdrv->err_handler && pdrv->err_handler->error_detected) { - dev_dbg(&pcidev->dev, - "trying to call AER service\n"); + pci_dbg(pcidev, "trying to call AER service\n"); if (pcidev) { flag = 1; switch (cmd) { |