diff options
Diffstat (limited to 'drivers/pci/controller/pcie-mediatek-gen3.c')
| -rw-r--r-- | drivers/pci/controller/pcie-mediatek-gen3.c | 129 |
1 files changed, 88 insertions, 41 deletions
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 74dfef8ce9ec..b55f5973414c 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -15,6 +15,7 @@ #include <linux/irqchip/chained_irq.h> #include <linux/irqdomain.h> #include <linux/kernel.h> +#include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/msi.h> #include <linux/of_device.h> @@ -24,6 +25,7 @@ #include <linux/platform_device.h> #include <linux/pm_domain.h> #include <linux/pm_runtime.h> +#include <linux/regmap.h> #include <linux/reset.h> #include "../pci.h" @@ -125,6 +127,8 @@ #define MAX_NUM_PHY_RESETS 3 +#define PCIE_MTK_RESET_TIME_US 10 + /* Time in ms needed to complete PCIe reset on EN7581 SoC */ #define PCIE_EN7581_RESET_TIME_MS 100 @@ -350,7 +354,8 @@ static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie, dev_dbg(pcie->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n", range_type, *num, (unsigned long long)cpu_addr, - (unsigned long long)pci_addr, (unsigned long long)table_size); + (unsigned long long)pci_addr, + (unsigned long long)table_size); cpu_addr += table_size; pci_addr += table_size; @@ -740,8 +745,8 @@ static int mtk_pcie_init_irq_domains(struct mtk_gen3_pcie *pcie) return -ENODEV; } - pcie->intx_domain = irq_domain_add_linear(intc_node, PCI_NUM_INTX, - &intx_domain_ops, pcie); + pcie->intx_domain = irq_domain_create_linear(of_fwnode_handle(intc_node), PCI_NUM_INTX, + &intx_domain_ops, pcie); if (!pcie->intx_domain) { dev_err(dev, "failed to create INTx IRQ domain\n"); ret = -ENODEV; @@ -751,8 +756,9 @@ static int mtk_pcie_init_irq_domains(struct mtk_gen3_pcie *pcie) /* Setup MSI */ mutex_init(&pcie->lock); - pcie->msi_bottom_domain = irq_domain_add_linear(node, PCIE_MSI_IRQS_NUM, - &mtk_msi_bottom_domain_ops, pcie); + pcie->msi_bottom_domain = irq_domain_create_linear(of_fwnode_handle(node), + PCIE_MSI_IRQS_NUM, + &mtk_msi_bottom_domain_ops, pcie); if (!pcie->msi_bottom_domain) { dev_err(dev, "failed to create MSI bottom domain\n"); ret = -ENODEV; @@ -885,7 +891,8 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) for (i = 0; i < num_resets; i++) pcie->phy_resets[i].id = pcie->soc->phy_resets.id[i]; - ret = devm_reset_control_bulk_get_optional_shared(dev, num_resets, pcie->phy_resets); + ret = devm_reset_control_bulk_get_optional_shared(dev, num_resets, + pcie->phy_resets); if (ret) { dev_err(dev, "failed to get PHY bulk reset\n"); return ret; @@ -915,29 +922,62 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) return pcie->num_clks; } - ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes); - if (ret == 0) { - if (num_lanes == 0 || num_lanes > 16 || (num_lanes != 1 && num_lanes % 2)) + ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes); + if (ret == 0) { + if (num_lanes == 0 || num_lanes > 16 || + (num_lanes != 1 && num_lanes % 2)) dev_warn(dev, "invalid num-lanes, using controller defaults\n"); - else + else pcie->num_lanes = num_lanes; - } + } return 0; } static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) { + struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); struct device *dev = pcie->dev; + struct resource_entry *entry; + struct regmap *pbus_regmap; + u32 val, args[2], size; + resource_size_t addr; int err; - u32 val; /* - * Wait for the time needed to complete the bulk assert in - * mtk_pcie_setup for EN7581 SoC. + * The controller may have been left out of reset by the bootloader + * so make sure that we get a clean start by asserting resets here. + */ + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); + + /* Wait for the time needed to complete the reset lines assert. */ + msleep(PCIE_EN7581_RESET_TIME_MS); + + /* + * Configure PBus base address and base address mask to allow the + * hw to detect if a given address is accessible on PCIe controller. */ - mdelay(PCIE_EN7581_RESET_TIME_MS); + pbus_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, + "mediatek,pbus-csr", + ARRAY_SIZE(args), + args); + if (IS_ERR(pbus_regmap)) + return PTR_ERR(pbus_regmap); + + entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); + if (!entry) + return -ENODEV; + + addr = entry->res->start - entry->offset; + regmap_write(pbus_regmap, args[0], lower_32_bits(addr)); + size = lower_32_bits(resource_size(entry->res)); + regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size))); + /* + * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581 + * requires PHY initialization and power-on before PHY reset deassert. + */ err = phy_init(pcie->phy); if (err) { dev_err(dev, "failed to initialize PHY\n"); @@ -950,7 +990,8 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) goto err_phy_on; } - err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); + err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); if (err) { dev_err(dev, "failed to deassert PHYs\n"); goto err_phy_deassert; @@ -960,17 +1001,11 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) * Wait for the time needed to complete the bulk de-assert above. * This time is specific for EN7581 SoC. */ - mdelay(PCIE_EN7581_RESET_TIME_MS); + msleep(PCIE_EN7581_RESET_TIME_MS); pm_runtime_enable(dev); pm_runtime_get_sync(dev); - err = clk_bulk_prepare(pcie->num_clks, pcie->clks); - if (err) { - dev_err(dev, "failed to prepare clock\n"); - goto err_clk_prepare; - } - val = FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) | FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) | FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) | @@ -983,20 +1018,26 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf); writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG); - err = clk_bulk_enable(pcie->num_clks, pcie->clks); + err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); if (err) { dev_err(dev, "failed to prepare clock\n"); - goto err_clk_enable; + goto err_clk_prepare_enable; } + /* + * Airoha EN7581 performs PCIe reset via clk callbacks since it has a + * hw issue with PCIE_PE_RSTB signal. Add wait for the time needed to + * complete the PCIe reset. + */ + msleep(PCIE_T_PVPERL_MS); + return 0; -err_clk_enable: - clk_bulk_unprepare(pcie->num_clks, pcie->clks); -err_clk_prepare: +err_clk_prepare_enable: pm_runtime_put_sync(dev); pm_runtime_disable(dev); - reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); err_phy_deassert: phy_power_off(pcie->phy); err_phy_on: @@ -1010,8 +1051,18 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) struct device *dev = pcie->dev; int err; + /* + * The controller may have been left out of reset by the bootloader + * so make sure that we get a clean start by asserting resets here. + */ + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); + reset_control_assert(pcie->mac_reset); + usleep_range(PCIE_MTK_RESET_TIME_US, 2 * PCIE_MTK_RESET_TIME_US); + /* PHY power on and enable pipe clock */ - err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); + err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); if (err) { dev_err(dev, "failed to deassert PHYs\n"); return err; @@ -1051,7 +1102,8 @@ err_clk_init: err_phy_on: phy_exit(pcie->phy); err_phy_init: - reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); return err; } @@ -1066,7 +1118,8 @@ static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie) phy_power_off(pcie->phy); phy_exit(pcie->phy); - reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); } static int mtk_pcie_get_controller_max_link_speed(struct mtk_gen3_pcie *pcie) @@ -1093,15 +1146,8 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) * Deassert the line in order to avoid unbalance in deassert_count * counter since the bulk is shared. */ - reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); - /* - * The controller may have been left out of reset by the bootloader - * so make sure that we get a clean start by asserting resets here. - */ - reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); - - reset_control_assert(pcie->mac_reset); - usleep_range(10, 20); + reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); /* Don't touch the hardware registers before power up */ err = pcie->soc->power_up(pcie); @@ -1324,6 +1370,7 @@ static struct platform_driver mtk_pcie_driver = { .name = "mtk-pcie-gen3", .of_match_table = mtk_pcie_of_match, .pm = &mtk_pcie_pm_ops, + .probe_type = PROBE_PREFER_ASYNCHRONOUS, }, }; |