diff options
Diffstat (limited to 'drivers/net')
46 files changed, 6598 insertions, 5417 deletions
diff --git a/drivers/net/7990.c b/drivers/net/7990.c index d396f996af57..0877fc372f4b 100644 --- a/drivers/net/7990.c +++ b/drivers/net/7990.c @@ -565,9 +565,9 @@ int lance_start_xmit (struct sk_buff *skb, struct net_device *dev) ib->btx_ring [entry].length = (-len) | 0xf000; ib->btx_ring [entry].misc = 0; - if (skb->len < ETH_ZLEN) - memset((char *)&ib->tx_buf[entry][0], 0, ETH_ZLEN); - skb_copy_from_linear_data(skb, &ib->tx_buf[entry][0], skblen); + if (skb->len < ETH_ZLEN) + memset((void *)&ib->tx_buf[entry][0], 0, ETH_ZLEN); + skb_copy_from_linear_data(skb, (void *)&ib->tx_buf[entry][0], skblen); /* Now, give the packet to the lance */ ib->btx_ring [entry].tmd1_bits = (LE_T1_POK|LE_T1_OWN); diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index dcdad217df51..279ec625cec4 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -311,7 +311,7 @@ config MAC8390 config MAC89x0 tristate "Macintosh CS89x0 based ethernet cards" - depends on NET_ETHERNET && MAC && BROKEN + depends on NET_ETHERNET && MAC ---help--- Support for CS89x0 chipset based Ethernet cards. If you have a Nubus or LC-PDS network (Ethernet) card of this type, say Y and @@ -337,8 +337,8 @@ config MACSONIC be called macsonic. config MACMACE - bool "Macintosh (AV) onboard MACE ethernet (EXPERIMENTAL)" - depends on NET_ETHERNET && MAC && EXPERIMENTAL + bool "Macintosh (AV) onboard MACE ethernet" + depends on NET_ETHERNET && MAC select CRC32 help Support for the onboard AMD 79C940 MACE Ethernet controller used in @@ -822,7 +822,7 @@ config SMC91X tristate "SMC 91C9x/91C1xxx support" select CRC32 select MII - depends on NET_ETHERNET && (ARM || REDWOOD_5 || REDWOOD_6 || M32R || SUPERH || SOC_AU1X00) + depends on NET_ETHERNET && (ARM || REDWOOD_5 || REDWOOD_6 || M32R || SUPERH || SOC_AU1X00 || BFIN) help This is a driver for SMC's 91x series of Ethernet chipsets, including the SMC91C94 and the SMC91C111. Say Y if you want it @@ -833,8 +833,8 @@ config SMC91X This driver is also available as a module ( = code which can be inserted in and removed from the running kernel whenever you want). The module will be called smc91x. If you want to compile it as a - module, say M here and read <file:Documentation/modules.txt> as well - as <file:Documentation/networking/net-modules.txt>. + module, say M here and read <file:Documentation/kbuild/modules.txt> + as well as <file:Documentation/networking/net-modules.txt>. config SMC9194 tristate "SMC 9194 support" @@ -889,7 +889,7 @@ config SMC911X This driver is also available as a module. The module will be called smc911x. If you want to compile it as a module, say M - here and read <file:Documentation/modules.txt> + here and read <file:Documentation/kbuild/modules.txt> config NET_VENDOR_RACAL bool "Racal-Interlan (Micom) NI cards" diff --git a/drivers/net/Space.c b/drivers/net/Space.c index dd8ed456c8b2..1c3e293fbaf7 100644 --- a/drivers/net/Space.c +++ b/drivers/net/Space.c @@ -83,7 +83,6 @@ extern struct net_device *bagetlance_probe(int unit); extern struct net_device *mvme147lance_probe(int unit); extern struct net_device *tc515_probe(int unit); extern struct net_device *lance_probe(int unit); -extern struct net_device *mace_probe(int unit); extern struct net_device *mac8390_probe(int unit); extern struct net_device *mac89x0_probe(int unit); extern struct net_device *mc32_probe(int unit); @@ -274,9 +273,6 @@ static struct devprobe2 m68k_probes[] __initdata = { #ifdef CONFIG_MVME147_NET /* MVME147 internal Ethernet */ {mvme147lance_probe, 0}, #endif -#ifdef CONFIG_MACMACE /* Mac 68k Quadra AV builtin Ethernet */ - {mace_probe, 0}, -#endif #ifdef CONFIG_MAC8390 /* NuBus NS8390-based cards */ {mac8390_probe, 0}, #endif diff --git a/drivers/net/a2065.c b/drivers/net/a2065.c index 1226cbba0450..81d5a374042a 100644 --- a/drivers/net/a2065.c +++ b/drivers/net/a2065.c @@ -562,7 +562,6 @@ static int lance_start_xmit (struct sk_buff *skb, struct net_device *dev) volatile struct lance_init_block *ib = lp->init_block; int entry, skblen, len; int status = 0; - static int outs; unsigned long flags; skblen = skb->len; @@ -598,17 +597,16 @@ static int lance_start_xmit (struct sk_buff *skb, struct net_device *dev) ib->btx_ring [entry].length = (-len) | 0xf000; ib->btx_ring [entry].misc = 0; - skb_copy_from_linear_data(skb, &ib->tx_buf [entry][0], skblen); + skb_copy_from_linear_data(skb, (void *)&ib->tx_buf [entry][0], skblen); /* Clear the slack of the packet, do I need this? */ if (len != skblen) - memset ((char *) &ib->tx_buf [entry][skblen], 0, len - skblen); + memset ((void *) &ib->tx_buf [entry][skblen], 0, len - skblen); /* Now, give the packet to the lance */ ib->btx_ring [entry].tmd1_bits = (LE_T1_POK|LE_T1_OWN); lp->tx_new = (lp->tx_new+1) & lp->tx_ring_mod_mask; - - outs++; + lp->stats.tx_bytes += skblen; if (TX_BUFFS_AVAIL <= 0) netif_stop_queue(dev); diff --git a/drivers/net/ariadne.c b/drivers/net/ariadne.c index a0e68e718531..a241ae7855a3 100644 --- a/drivers/net/ariadne.c +++ b/drivers/net/ariadne.c @@ -677,6 +677,7 @@ static int ariadne_start_xmit(struct sk_buff *skb, struct net_device *dev) priv->cur_tx -= TX_RING_SIZE; priv->dirty_tx -= TX_RING_SIZE; } + priv->stats.tx_bytes += len; /* Trigger an immediate send poll. */ lance->RAP = CSR0; /* PCnet-ISA Controller Status */ diff --git a/drivers/net/atl1/atl1_param.c b/drivers/net/atl1/atl1_param.c index c407214339f6..bcd0bd891722 100644 --- a/drivers/net/atl1/atl1_param.c +++ b/drivers/net/atl1/atl1_param.c @@ -22,7 +22,6 @@ */ #include <linux/types.h> -#include <linux/pci.h> #include <linux/moduleparam.h> #include "atl1.h" diff --git a/drivers/net/au1000_eth.c b/drivers/net/au1000_eth.c index d10fb80e9a63..c39ab803c5d8 100644 --- a/drivers/net/au1000_eth.c +++ b/drivers/net/au1000_eth.c @@ -45,7 +45,6 @@ #include <linux/bitops.h> #include <linux/slab.h> #include <linux/interrupt.h> -#include <linux/pci.h> #include <linux/init.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index f98a2205a090..88b33c6ddda8 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c @@ -1,6 +1,6 @@ /* bnx2.c: Broadcom NX2 network driver. * - * Copyright (c) 2004, 2005, 2006 Broadcom Corporation + * Copyright (c) 2004-2007 Broadcom Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -54,8 +54,8 @@ #define DRV_MODULE_NAME "bnx2" #define PFX DRV_MODULE_NAME ": " -#define DRV_MODULE_VERSION "1.5.8" -#define DRV_MODULE_RELDATE "April 24, 2007" +#define DRV_MODULE_VERSION "1.5.10" +#define DRV_MODULE_RELDATE "May 1, 2007" #define RUN_AT(x) (jiffies + (x)) @@ -84,6 +84,7 @@ typedef enum { BCM5708, BCM5708S, BCM5709, + BCM5709S, } board_t; /* indexed by board_t, above */ @@ -98,6 +99,7 @@ static const struct { { "Broadcom NetXtreme II BCM5708 1000Base-T" }, { "Broadcom NetXtreme II BCM5708 1000Base-SX" }, { "Broadcom NetXtreme II BCM5709 1000Base-T" }, + { "Broadcom NetXtreme II BCM5709 1000Base-SX" }, }; static struct pci_device_id bnx2_pci_tbl[] = { @@ -117,6 +119,8 @@ static struct pci_device_id bnx2_pci_tbl[] = { PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S }, { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 }, + { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S }, { 0, } }; @@ -230,21 +234,29 @@ static inline u32 bnx2_tx_avail(struct bnx2 *bp) static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset) { + u32 val; + + spin_lock_bh(&bp->indirect_lock); REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); - return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW)); + val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW); + spin_unlock_bh(&bp->indirect_lock); + return val; } static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val) { + spin_lock_bh(&bp->indirect_lock); REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val); + spin_unlock_bh(&bp->indirect_lock); } static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) { offset += cid_addr; + spin_lock_bh(&bp->indirect_lock); if (CHIP_NUM(bp) == CHIP_NUM_5709) { int i; @@ -262,6 +274,7 @@ bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) REG_WR(bp, BNX2_CTX_DATA_ADR, offset); REG_WR(bp, BNX2_CTX_DATA, val); } + spin_unlock_bh(&bp->indirect_lock); } static int @@ -572,8 +585,8 @@ bnx2_report_fw_link(struct bnx2 *bp) if (bp->autoneg) { fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED; - bnx2_read_phy(bp, MII_BMSR, &bmsr); - bnx2_read_phy(bp, MII_BMSR, &bmsr); + bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); + bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); if (!(bmsr & BMSR_ANEGCOMPLETE) || bp->phy_flags & PHY_PARALLEL_DETECT_FLAG) @@ -654,8 +667,8 @@ bnx2_resolve_flow_ctrl(struct bnx2 *bp) return; } - bnx2_read_phy(bp, MII_ADVERTISE, &local_adv); - bnx2_read_phy(bp, MII_LPA, &remote_adv); + bnx2_read_phy(bp, bp->mii_adv, &local_adv); + bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); if (bp->phy_flags & PHY_SERDES_FLAG) { u32 new_local_adv = 0; @@ -700,6 +713,45 @@ bnx2_resolve_flow_ctrl(struct bnx2 *bp) } static int +bnx2_5709s_linkup(struct bnx2 *bp) +{ + u32 val, speed; + + bp->link_up = 1; + + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS); + bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val); + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); + + if ((bp->autoneg & AUTONEG_SPEED) == 0) { + bp->line_speed = bp->req_line_speed; + bp->duplex = bp->req_duplex; + return 0; + } + speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK; + switch (speed) { + case MII_BNX2_GP_TOP_AN_SPEED_10: + bp->line_speed = SPEED_10; + break; + case MII_BNX2_GP_TOP_AN_SPEED_100: + bp->line_speed = SPEED_100; + break; + case MII_BNX2_GP_TOP_AN_SPEED_1G: + case MII_BNX2_GP_TOP_AN_SPEED_1GKV: + bp->line_speed = SPEED_1000; + break; + case MII_BNX2_GP_TOP_AN_SPEED_2_5G: + bp->line_speed = SPEED_2500; + break; + } + if (val & MII_BNX2_GP_TOP_AN_FD) + bp->duplex = DUPLEX_FULL; + else + bp->duplex = DUPLEX_HALF; + return 0; +} + +static int bnx2_5708s_linkup(struct bnx2 *bp) { u32 val; @@ -736,7 +788,7 @@ bnx2_5706s_linkup(struct bnx2 *bp) bp->link_up = 1; bp->line_speed = SPEED_1000; - bnx2_read_phy(bp, MII_BMCR, &bmcr); + bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); if (bmcr & BMCR_FULLDPLX) { bp->duplex = DUPLEX_FULL; } @@ -748,8 +800,8 @@ bnx2_5706s_linkup(struct bnx2 *bp) return 0; } - bnx2_read_phy(bp, MII_ADVERTISE, &local_adv); - bnx2_read_phy(bp, MII_LPA, &remote_adv); + bnx2_read_phy(bp, bp->mii_adv, &local_adv); + bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); common = local_adv & remote_adv; if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) { @@ -770,7 +822,7 @@ bnx2_copper_linkup(struct bnx2 *bp) { u32 bmcr; - bnx2_read_phy(bp, MII_BMCR, &bmcr); + bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); if (bmcr & BMCR_ANENABLE) { u32 local_adv, remote_adv, common; @@ -787,8 +839,8 @@ bnx2_copper_linkup(struct bnx2 *bp) bp->duplex = DUPLEX_HALF; } else { - bnx2_read_phy(bp, MII_ADVERTISE, &local_adv); - bnx2_read_phy(bp, MII_LPA, &remote_adv); + bnx2_read_phy(bp, bp->mii_adv, &local_adv); + bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); common = local_adv & remote_adv; if (common & ADVERTISE_100FULL) { @@ -898,6 +950,145 @@ bnx2_set_mac_link(struct bnx2 *bp) return 0; } +static void +bnx2_enable_bmsr1(struct bnx2 *bp) +{ + if ((bp->phy_flags & PHY_SERDES_FLAG) && + (CHIP_NUM(bp) == CHIP_NUM_5709)) + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, + MII_BNX2_BLK_ADDR_GP_STATUS); +} + +static void +bnx2_disable_bmsr1(struct bnx2 *bp) +{ + if ((bp->phy_flags & PHY_SERDES_FLAG) && + (CHIP_NUM(bp) == CHIP_NUM_5709)) + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, + MII_BNX2_BLK_ADDR_COMBO_IEEEB0); +} + +static int +bnx2_test_and_enable_2g5(struct bnx2 *bp) +{ + u32 up1; + int ret = 1; + + if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) + return 0; + + if (bp->autoneg & AUTONEG_SPEED) + bp->advertising |= ADVERTISED_2500baseX_Full; + + if (CHIP_NUM(bp) == CHIP_NUM_5709) + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); + + bnx2_read_phy(bp, bp->mii_up1, &up1); + if (!(up1 & BCM5708S_UP1_2G5)) { + up1 |= BCM5708S_UP1_2G5; + bnx2_write_phy(bp, bp->mii_up1, up1); + ret = 0; + } + + if (CHIP_NUM(bp) == CHIP_NUM_5709) + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, + MII_BNX2_BLK_ADDR_COMBO_IEEEB0); + + return ret; +} + +static int +bnx2_test_and_disable_2g5(struct bnx2 *bp) +{ + u32 up1; + int ret = 0; + + if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) + return 0; + + if (CHIP_NUM(bp) == CHIP_NUM_5709) + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); + + bnx2_read_phy(bp, bp->mii_up1, &up1); + if (up1 & BCM5708S_UP1_2G5) { + up1 &= ~BCM5708S_UP1_2G5; + bnx2_write_phy(bp, bp->mii_up1, up1); + ret = 1; + } + + if (CHIP_NUM(bp) == CHIP_NUM_5709) + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, + MII_BNX2_BLK_ADDR_COMBO_IEEEB0); + + return ret; +} + +static void +bnx2_enable_forced_2g5(struct bnx2 *bp) +{ + u32 bmcr; + + if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) + return; + + if (CHIP_NUM(bp) == CHIP_NUM_5709) { + u32 val; + + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, + MII_BNX2_BLK_ADDR_SERDES_DIG); + bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val); + val &= ~MII_BNX2_SD_MISC1_FORCE_MSK; + val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G; + bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); + + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, + MII_BNX2_BLK_ADDR_COMBO_IEEEB0); + bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); + + } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { + bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); + bmcr |= BCM5708S_BMCR_FORCE_2500; + } + + if (bp->autoneg & AUTONEG_SPEED) { + bmcr &= ~BMCR_ANENABLE; + if (bp->req_duplex == DUPLEX_FULL) + bmcr |= BMCR_FULLDPLX; + } + bnx2_write_phy(bp, bp->mii_bmcr, bmcr); +} + +static void +bnx2_disable_forced_2g5(struct bnx2 *bp) +{ + u32 bmcr; + + if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) + return; + + if (CHIP_NUM(bp) == CHIP_NUM_5709) { + u32 val; + + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, + MII_BNX2_BLK_ADDR_SERDES_DIG); + bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val); + val &= ~MII_BNX2_SD_MISC1_FORCE; + bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); + + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, + MII_BNX2_BLK_ADDR_COMBO_IEEEB0); + bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); + + } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { + bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); + bmcr &= ~BCM5708S_BMCR_FORCE_2500; + } + + if (bp->autoneg & AUTONEG_SPEED) + bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART; + bnx2_write_phy(bp, bp->mii_bmcr, bmcr); +} + static int bnx2_set_link(struct bnx2 *bp) { @@ -911,8 +1102,10 @@ bnx2_set_link(struct bnx2 *bp) link_up = bp->link_up; - bnx2_read_phy(bp, MII_BMSR, &bmsr); - bnx2_read_phy(bp, MII_BMSR, &bmsr); + bnx2_enable_bmsr1(bp); + bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); + bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); + bnx2_disable_bmsr1(bp); if ((bp->phy_flags & PHY_SERDES_FLAG) && (CHIP_NUM(bp) == CHIP_NUM_5706)) { @@ -933,6 +1126,8 @@ bnx2_set_link(struct bnx2 *bp) bnx2_5706s_linkup(bp); else if (CHIP_NUM(bp) == CHIP_NUM_5708) bnx2_5708s_linkup(bp); + else if (CHIP_NUM(bp) == CHIP_NUM_5709) + bnx2_5709s_linkup(bp); } else { bnx2_copper_linkup(bp); @@ -941,17 +1136,9 @@ bnx2_set_link(struct bnx2 *bp) } else { if ((bp->phy_flags & PHY_SERDES_FLAG) && - (bp->autoneg & AUTONEG_SPEED)) { + (bp->autoneg & AUTONEG_SPEED)) + bnx2_disable_forced_2g5(bp); - u32 bmcr; - - bnx2_read_phy(bp, MII_BMCR, &bmcr); - bmcr &= ~BCM5708S_BMCR_FORCE_2500; - if (!(bmcr & BMCR_ANENABLE)) { - bnx2_write_phy(bp, MII_BMCR, bmcr | - BMCR_ANENABLE); - } - } bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; bp->link_up = 0; } @@ -971,13 +1158,13 @@ bnx2_reset_phy(struct bnx2 *bp) int i; u32 reg; - bnx2_write_phy(bp, MII_BMCR, BMCR_RESET); + bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET); #define PHY_RESET_MAX_WAIT 100 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) { udelay(10); - bnx2_read_phy(bp, MII_BMCR, ®); + bnx2_read_phy(bp, bp->mii_bmcr, ®); if (!(reg & BMCR_RESET)) { udelay(20); break; @@ -1026,34 +1213,40 @@ bnx2_phy_get_pause_adv(struct bnx2 *bp) static int bnx2_setup_serdes_phy(struct bnx2 *bp) { - u32 adv, bmcr, up1; + u32 adv, bmcr; u32 new_adv = 0; if (!(bp->autoneg & AUTONEG_SPEED)) { u32 new_bmcr; int force_link_down = 0; - bnx2_read_phy(bp, MII_ADVERTISE, &adv); + if (bp->req_line_speed == SPEED_2500) { + if (!bnx2_test_and_enable_2g5(bp)) + force_link_down = 1; + } else if (bp->req_line_speed == SPEED_1000) { + if (bnx2_test_and_disable_2g5(bp)) + force_link_down = 1; + } + bnx2_read_phy(bp, bp->mii_adv, &adv); adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF); - bnx2_read_phy(bp, MII_BMCR, &bmcr); - new_bmcr = bmcr & ~(BMCR_ANENABLE | BCM5708S_BMCR_FORCE_2500); + bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); + new_bmcr = bmcr & ~BMCR_ANENABLE; new_bmcr |= BMCR_SPEED1000; - if (bp->req_line_speed == SPEED_2500) { - new_bmcr |= BCM5708S_BMCR_FORCE_2500; - bnx2_read_phy(bp, BCM5708S_UP1, &up1); - if (!(up1 & BCM5708S_UP1_2G5)) { - up1 |= BCM5708S_UP1_2G5; - bnx2_write_phy(bp, BCM5708S_UP1, up1); - force_link_down = 1; + + if (CHIP_NUM(bp) == CHIP_NUM_5709) { + if (bp->req_line_speed == SPEED_2500) + bnx2_enable_forced_2g5(bp); + else if (bp->req_line_speed == SPEED_1000) { + bnx2_disable_forced_2g5(bp); + new_bmcr &= ~0x2000; } + } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { - bnx2_read_phy(bp, BCM5708S_UP1, &up1); - if (up1 & BCM5708S_UP1_2G5) { - up1 &= ~BCM5708S_UP1_2G5; - bnx2_write_phy(bp, BCM5708S_UP1, up1); - force_link_down = 1; - } + if (bp->req_line_speed == SPEED_2500) + new_bmcr |= BCM5708S_BMCR_FORCE_2500; + else + new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500; } if (bp->req_duplex == DUPLEX_FULL) { @@ -1067,49 +1260,48 @@ bnx2_setup_serdes_phy(struct bnx2 *bp) if ((new_bmcr != bmcr) || (force_link_down)) { /* Force a link down visible on the other side */ if (bp->link_up) { - bnx2_write_phy(bp, MII_ADVERTISE, adv & + bnx2_write_phy(bp, bp->mii_adv, adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF)); - bnx2_write_phy(bp, MII_BMCR, bmcr | + bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); bp->link_up = 0; netif_carrier_off(bp->dev); - bnx2_write_phy(bp, MII_BMCR, new_bmcr); + bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); bnx2_report_link(bp); } - bnx2_write_phy(bp, MII_ADVERTISE, adv); - bnx2_write_phy(bp, MII_BMCR, new_bmcr); + bnx2_write_phy(bp, bp->mii_adv, adv); + bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); + } else { + bnx2_resolve_flow_ctrl(bp); + bnx2_set_mac_link(bp); } return 0; } - if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) { - bnx2_read_phy(bp, BCM5708S_UP1, &up1); - up1 |= BCM5708S_UP1_2G5; - bnx2_write_phy(bp, BCM5708S_UP1, up1); - } + bnx2_test_and_enable_2g5(bp); if (bp->advertising & ADVERTISED_1000baseT_Full) new_adv |= ADVERTISE_1000XFULL; new_adv |= bnx2_phy_get_pause_adv(bp); - bnx2_read_phy(bp, MII_ADVERTISE, &adv); - bnx2_read_phy(bp, MII_BMCR, &bmcr); + bnx2_read_phy(bp, bp->mii_adv, &adv); + bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); bp->serdes_an_pending = 0; if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { /* Force a link down visible on the other side */ if (bp->link_up) { - bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); + bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); spin_unlock_bh(&bp->phy_lock); msleep(20); spin_lock_bh(&bp->phy_lock); } - bnx2_write_phy(bp, MII_ADVERTISE, new_adv); - bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | + bnx2_write_phy(bp, bp->mii_adv, new_adv); + bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); /* Speed up link-up time when the link partner * does not autonegotiate which is very common @@ -1122,6 +1314,9 @@ bnx2_setup_serdes_phy(struct bnx2 *bp) bp->current_interval = SERDES_AN_TIMEOUT; bp->serdes_an_pending = 1; mod_timer(&bp->timer, jiffies + bp->current_interval); + } else { + bnx2_resolve_flow_ctrl(bp); + bnx2_set_mac_link(bp); } return 0; @@ -1146,14 +1341,14 @@ bnx2_setup_copper_phy(struct bnx2 *bp) u32 bmcr; u32 new_bmcr; - bnx2_read_phy(bp, MII_BMCR, &bmcr); + bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); if (bp->autoneg & AUTONEG_SPEED) { u32 adv_reg, adv1000_reg; u32 new_adv_reg = 0; u32 new_adv1000_reg = 0; - bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg); + bnx2_read_phy(bp, bp->mii_adv, &adv_reg); adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); @@ -1179,9 +1374,9 @@ bnx2_setup_copper_phy(struct bnx2 *bp) (adv_reg != new_adv_reg) || ((bmcr & BMCR_ANENABLE) == 0)) { - bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg); + bnx2_write_phy(bp, bp->mii_adv, new_adv_reg); bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg); - bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART | + bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART | BMCR_ANENABLE); } else if (bp->link_up) { @@ -1204,21 +1399,21 @@ bnx2_setup_copper_phy(struct bnx2 *bp) if (new_bmcr != bmcr) { u32 bmsr; - bnx2_read_phy(bp, MII_BMSR, &bmsr); - bnx2_read_phy(bp, MII_BMSR, &bmsr); + bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); + bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); if (bmsr & BMSR_LSTATUS) { /* Force link down */ - bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); + bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); spin_unlock_bh(&bp->phy_lock); msleep(50); spin_lock_bh(&bp->phy_lock); - bnx2_read_phy(bp, MII_BMSR, &bmsr); - bnx2_read_phy(bp, MII_BMSR, &bmsr); + bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); + bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); } - bnx2_write_phy(bp, MII_BMCR, new_bmcr); + bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); /* Normally, the new speed is setup after the link has * gone down and up again. In some cases, link will not go @@ -1230,6 +1425,9 @@ bnx2_setup_copper_phy(struct bnx2 *bp) bnx2_resolve_flow_ctrl(bp); bnx2_set_mac_link(bp); } + } else { + bnx2_resolve_flow_ctrl(bp); + bnx2_set_mac_link(bp); } return 0; } @@ -1249,10 +1447,63 @@ bnx2_setup_phy(struct bnx2 *bp) } static int +bnx2_init_5709s_phy(struct bnx2 *bp) +{ + u32 val; + + bp->mii_bmcr = MII_BMCR + 0x10; + bp->mii_bmsr = MII_BMSR + 0x10; + bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1; + bp->mii_adv = MII_ADVERTISE + 0x10; + bp->mii_lpa = MII_LPA + 0x10; + bp->mii_up1 = MII_BNX2_OVER1G_UP1; + + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER); + bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD); + + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); + bnx2_reset_phy(bp); + + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG); + + bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val); + val &= ~MII_BNX2_SD_1000XCTL1_AUTODET; + val |= MII_BNX2_SD_1000XCTL1_FIBER; + bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val); + + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); + bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val); + if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) + val |= BCM5708S_UP1_2G5; + else + val &= ~BCM5708S_UP1_2G5; + bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val); + + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG); + bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val); + val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM; + bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val); + + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0); + + val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN | + MII_BNX2_CL73_BAM_NP_AFT_BP_EN; + bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val); + + bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); + + return 0; +} + +static int bnx2_init_5708s_phy(struct bnx2 *bp) { u32 val; + bnx2_reset_phy(bp); + + bp->mii_up1 = BCM5708S_UP1; + bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3); bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE); bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); @@ -1305,6 +1556,8 @@ bnx2_init_5708s_phy(struct bnx2 *bp) static int bnx2_init_5706s_phy(struct bnx2 *bp) { + bnx2_reset_phy(bp); + bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; if (CHIP_NUM(bp) == CHIP_NUM_5706) @@ -1342,6 +1595,8 @@ bnx2_init_copper_phy(struct bnx2 *bp) { u32 val; + bnx2_reset_phy(bp); + if (bp->phy_flags & PHY_CRC_FIX_FLAG) { bnx2_write_phy(bp, 0x18, 0x0c00); bnx2_write_phy(bp, 0x17, 0x000a); @@ -1396,9 +1651,13 @@ bnx2_init_phy(struct bnx2 *bp) bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG; bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG; - REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); + bp->mii_bmcr = MII_BMCR; + bp->mii_bmsr = MII_BMSR; + bp->mii_bmsr1 = MII_BMSR; + bp->mii_adv = MII_ADVERTISE; + bp->mii_lpa = MII_LPA; - bnx2_reset_phy(bp); + REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); bnx2_read_phy(bp, MII_PHYSID1, &val); bp->phy_id = val << 16; @@ -1410,6 +1669,8 @@ bnx2_init_phy(struct bnx2 *bp) rc = bnx2_init_5706s_phy(bp); else if (CHIP_NUM(bp) == CHIP_NUM_5708) rc = bnx2_init_5708s_phy(bp); + else if (CHIP_NUM(bp) == CHIP_NUM_5709) + rc = bnx2_init_5709s_phy(bp); } else { rc = bnx2_init_copper_phy(bp); @@ -1442,7 +1703,7 @@ bnx2_set_phy_loopback(struct bnx2 *bp) int rc, i; spin_lock_bh(&bp->phy_lock); - rc = bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX | + rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000); spin_unlock_bh(&bp->phy_lock); if (rc) @@ -1681,25 +1942,33 @@ bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index) return 0; } -static void -bnx2_phy_int(struct bnx2 *bp) +static int +bnx2_phy_event_is_set(struct bnx2 *bp, u32 event) { + struct status_block *sblk = bp->status_blk; u32 new_link_state, old_link_state; + int is_set = 1; - new_link_state = bp->status_blk->status_attn_bits & - STATUS_ATTN_BITS_LINK_STATE; - old_link_state = bp->status_blk->status_attn_bits_ack & - STATUS_ATTN_BITS_LINK_STATE; + new_link_state = sblk->status_attn_bits & event; + old_link_state = sblk->status_attn_bits_ack & event; if (new_link_state != old_link_state) { - if (new_link_state) { - REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, - STATUS_ATTN_BITS_LINK_STATE); - } - else { - REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, - STATUS_ATTN_BITS_LINK_STATE); - } + if (new_link_state) + REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event); + else + REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event); + } else + is_set = 0; + + return is_set; +} + +static void +bnx2_phy_int(struct bnx2 *bp) +{ + if (bnx2_phy_event_is_set(bp, STATUS_ATTN_BITS_LINK_STATE)) { + spin_lock(&bp->phy_lock); bnx2_set_link(bp); + spin_unlock(&bp->phy_lock); } } @@ -1993,6 +2262,23 @@ bnx2_msi(int irq, void *dev_instance) } static irqreturn_t +bnx2_msi_1shot(int irq, void *dev_instance) +{ + struct net_device *dev = dev_instance; + struct bnx2 *bp = netdev_priv(dev); + + prefetch(bp->status_blk); + + /* Return here if interrupt is disabled. */ + if (unlikely(atomic_read(&bp->intr_sem) != 0)) + return IRQ_HANDLED; + + netif_rx_schedule(dev); + + return IRQ_HANDLED; +} + +static irqreturn_t bnx2_interrupt(int irq, void *dev_instance) { struct net_device *dev = dev_instance; @@ -2022,6 +2308,8 @@ bnx2_interrupt(int irq, void *dev_instance) return IRQ_HANDLED; } +#define STATUS_ATTN_EVENTS STATUS_ATTN_BITS_LINK_STATE + static inline int bnx2_has_work(struct bnx2 *bp) { @@ -2031,8 +2319,8 @@ bnx2_has_work(struct bnx2 *bp) (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)) return 1; - if ((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != - (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) + if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) != + (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS)) return 1; return 0; @@ -2042,15 +2330,14 @@ static int bnx2_poll(struct net_device *dev, int *budget) { struct bnx2 *bp = netdev_priv(dev); + struct status_block *sblk = bp->status_blk; + u32 status_attn_bits = sblk->status_attn_bits; + u32 status_attn_bits_ack = sblk->status_attn_bits_ack; - if ((bp->status_blk->status_attn_bits & - STATUS_ATTN_BITS_LINK_STATE) != - (bp->status_blk->status_attn_bits_ack & - STATUS_ATTN_BITS_LINK_STATE)) { + if ((status_attn_bits & STATUS_ATTN_EVENTS) != + (status_attn_bits_ack & STATUS_ATTN_EVENTS)) { - spin_lock(&bp->phy_lock); bnx2_phy_int(bp); - spin_unlock(&bp->phy_lock); /* This is needed to take care of transient status * during link changes. @@ -3489,17 +3776,21 @@ bnx2_init_chip(struct bnx2 *bp) REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ if (CHIP_ID(bp) == CHIP_ID_5706_A1) - REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS); + val = BNX2_HC_CONFIG_COLLECT_STATS; else { - REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE | - BNX2_HC_CONFIG_TX_TMR_MODE | - BNX2_HC_CONFIG_COLLECT_STATS); + val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE | + BNX2_HC_CONFIG_COLLECT_STATS; } + if (bp->flags & ONE_SHOT_MSI_FLAG) + val |= BNX2_HC_CONFIG_ONE_SHOT; + + REG_WR(bp, BNX2_HC_CONFIG, val); + /* Clear internal stats counters. */ REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW); - REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); + REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS); if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) & BNX2_PORT_FEATURE_ASF_ENABLED) @@ -3763,10 +4054,11 @@ static int bnx2_test_registers(struct bnx2 *bp) { int ret; - int i; + int i, is_5709; static const struct { u16 offset; u16 flags; +#define BNX2_FL_NOT_5709 1 u32 rw_mask; u32 ro_mask; } reg_tbl[] = { @@ -3774,26 +4066,26 @@ bnx2_test_registers(struct bnx2 *bp) { 0x0090, 0, 0xffffffff, 0x00000000 }, { 0x0094, 0, 0x00000000, 0x00000000 }, - { 0x0404, 0, 0x00003f00, 0x00000000 }, - { 0x0418, 0, 0x00000000, 0xffffffff }, - { 0x041c, 0, 0x00000000, 0xffffffff }, - { 0x0420, 0, 0x00000000, 0x80ffffff }, - { 0x0424, 0, 0x00000000, 0x00000000 }, - { 0x0428, 0, 0x00000000, 0x00000001 }, - { 0x0450, 0, 0x00000000, 0x0000ffff }, - { 0x0454, 0, 0x00000000, 0xffffffff }, - { 0x0458, 0, 0x00000000, 0xffffffff }, - - { 0x0808, 0, 0x00000000, 0xffffffff }, - { 0x0854, 0, 0x00000000, 0xffffffff }, - { 0x0868, 0, 0x00000000, 0x77777777 }, - { 0x086c, 0, 0x00000000, 0x77777777 }, - { 0x0870, 0, 0x00000000, 0x77777777 }, - { 0x0874, 0, 0x00000000, 0x77777777 }, - - { 0x0c00, 0, 0x00000000, 0x00000001 }, - { 0x0c04, 0, 0x00000000, 0x03ff0001 }, - { 0x0c08, 0, 0x0f0ff073, 0x00000000 }, + { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 }, + { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, + { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, + { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff }, + { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 }, + { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, + { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff }, + { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, + { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, + + { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, + { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff }, + { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, + { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, + { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, + { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 }, + + { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 }, + { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 }, + { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 }, { 0x1000, 0, 0x00000000, 0x00000001 }, { 0x1004, 0, 0x00000000, 0x000f0001 }, @@ -3840,7 +4132,6 @@ bnx2_test_registers(struct bnx2 *bp) { 0x5004, 0, 0x00000000, 0x0000007f }, { 0x5008, 0, 0x0f0007ff, 0x00000000 }, - { 0x500c, 0, 0xf800f800, 0x07ff07ff }, { 0x5c00, 0, 0x00000000, 0x00000001 }, { 0x5c04, 0, 0x00000000, 0x0003000f }, @@ -3880,8 +4171,16 @@ bnx2_test_registers(struct bnx2 *bp) }; ret = 0; + is_5709 = 0; + if (CHIP_NUM(bp) == CHIP_NUM_5709) + is_5709 = 1; + for (i = 0; reg_tbl[i].offset != 0xffff; i++) { u32 offset, rw_mask, ro_mask, save_val, val; + u16 flags = reg_tbl[i].flags; + + if (is_5709 && (flags & BNX2_FL_NOT_5709)) + continue; offset = (u32) reg_tbl[i].offset; rw_mask = reg_tbl[i].rw_mask; @@ -3950,10 +4249,10 @@ bnx2_test_memory(struct bnx2 *bp) { int ret = 0; int i; - static const struct { + static struct mem_entry { u32 offset; u32 len; - } mem_tbl[] = { + } mem_tbl_5706[] = { { 0x60000, 0x4000 }, { 0xa0000, 0x3000 }, { 0xe0000, 0x4000 }, @@ -3961,7 +4260,21 @@ bnx2_test_memory(struct bnx2 *bp) { 0x1a0000, 0x4000 }, { 0x160000, 0x4000 }, { 0xffffffff, 0 }, + }, + mem_tbl_5709[] = { + { 0x60000, 0x4000 }, + { 0xa0000, 0x3000 }, + { 0xe0000, 0x4000 }, + { 0x120000, 0x4000 }, + { 0x1a0000, 0x4000 }, + { 0xffffffff, 0 }, }; + struct mem_entry *mem_tbl; + + if (CHIP_NUM(bp) == CHIP_NUM_5709) + mem_tbl = mem_tbl_5709; + else + mem_tbl = mem_tbl_5706; for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset, @@ -4163,8 +4476,10 @@ bnx2_test_link(struct bnx2 *bp) u32 bmsr; spin_lock_bh(&bp->phy_lock); - bnx2_read_phy(bp, MII_BMSR, &bmsr); - bnx2_read_phy(bp, MII_BMSR, &bmsr); + bnx2_enable_bmsr1(bp); + bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); + bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); + bnx2_disable_bmsr1(bp); spin_unlock_bh(&bp->phy_lock); if (bmsr & BMSR_LSTATUS) { @@ -4214,7 +4529,7 @@ bnx2_5706_serdes_timer(struct bnx2 *bp) bp->current_interval = bp->timer_interval; - bnx2_read_phy(bp, MII_BMCR, &bmcr); + bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); if (bmcr & BMCR_ANENABLE) { u32 phy1, phy2; @@ -4232,7 +4547,7 @@ bnx2_5706_serdes_timer(struct bnx2 *bp) bmcr &= ~BMCR_ANENABLE; bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; - bnx2_write_phy(bp, MII_BMCR, bmcr); + bnx2_write_phy(bp, bp->mii_bmcr, bmcr); bp->phy_flags |= PHY_PARALLEL_DETECT_FLAG; } } @@ -4246,9 +4561,9 @@ bnx2_5706_serdes_timer(struct bnx2 *bp) if (phy2 & 0x20) { u32 bmcr; - bnx2_read_phy(bp, MII_BMCR, &bmcr); + bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); bmcr |= BMCR_ANENABLE; - bnx2_write_phy(bp, MII_BMCR, bmcr); + bnx2_write_phy(bp, bp->mii_bmcr, bmcr); bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; } @@ -4272,17 +4587,12 @@ bnx2_5708_serdes_timer(struct bnx2 *bp) else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { u32 bmcr; - bnx2_read_phy(bp, MII_BMCR, &bmcr); - + bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); if (bmcr & BMCR_ANENABLE) { - bmcr &= ~BMCR_ANENABLE; - bmcr |= BMCR_FULLDPLX | BCM5708S_BMCR_FORCE_2500; - bnx2_write_phy(bp, MII_BMCR, bmcr); + bnx2_enable_forced_2g5(bp); bp->current_interval = SERDES_FORCED_TIMEOUT; } else { - bmcr &= ~(BMCR_FULLDPLX | BCM5708S_BMCR_FORCE_2500); - bmcr |= BMCR_ANENABLE; - bnx2_write_phy(bp, MII_BMCR, bmcr); + bnx2_disable_forced_2g5(bp); bp->serdes_an_pending = 2; bp->current_interval = bp->timer_interval; } @@ -4313,7 +4623,7 @@ bnx2_timer(unsigned long data) if (bp->phy_flags & PHY_SERDES_FLAG) { if (CHIP_NUM(bp) == CHIP_NUM_5706) bnx2_5706_serdes_timer(bp); - else if (CHIP_NUM(bp) == CHIP_NUM_5708) + else bnx2_5708_serdes_timer(bp); } @@ -4321,6 +4631,38 @@ bnx2_restart_timer: mod_timer(&bp->timer, jiffies + bp->current_interval); } +static int +bnx2_request_irq(struct bnx2 *bp) +{ + struct net_device *dev = bp->dev; + int rc = 0; + + if (bp->flags & USING_MSI_FLAG) { + irq_handler_t fn = bnx2_msi; + + if (bp->flags & ONE_SHOT_MSI_FLAG) + fn = bnx2_msi_1shot; + + rc = request_irq(bp->pdev->irq, fn, 0, dev->name, dev); + } else + rc = request_irq(bp->pdev->irq, bnx2_interrupt, + IRQF_SHARED, dev->name, dev); + return rc; +} + +static void +bnx2_free_irq(struct bnx2 *bp) +{ + struct net_device *dev = bp->dev; + + if (bp->flags & USING_MSI_FLAG) { + free_irq(bp->pdev->irq, dev); + pci_disable_msi(bp->pdev); + bp->flags &= ~(USING_MSI_FLAG | ONE_SHOT_MSI_FLAG); + } else + free_irq(bp->pdev->irq, dev); +} + /* Called with rtnl_lock */ static int bnx2_open(struct net_device *dev) @@ -4328,6 +4670,8 @@ bnx2_open(struct net_device *dev) struct bnx2 *bp = netdev_priv(dev); int rc; + netif_carrier_off(dev); + bnx2_set_power_state(bp, PCI_D0); bnx2_disable_int(bp); @@ -4335,24 +4679,15 @@ bnx2_open(struct net_device *dev) if (rc) return rc; - if ((CHIP_ID(bp) != CHIP_ID_5706_A0) && - (CHIP_ID(bp) != CHIP_ID_5706_A1) && - !disable_msi) { - + if ((bp->flags & MSI_CAP_FLAG) && !disable_msi) { if (pci_enable_msi(bp->pdev) == 0) { bp->flags |= USING_MSI_FLAG; - rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name, - dev); - } - else { - rc = request_irq(bp->pdev->irq, bnx2_interrupt, - IRQF_SHARED, dev->name, dev); + if (CHIP_NUM(bp) == CHIP_NUM_5709) + bp->flags |= ONE_SHOT_MSI_FLAG; } } - else { - rc = request_irq(bp->pdev->irq, bnx2_interrupt, IRQF_SHARED, - dev->name, dev); - } + rc = bnx2_request_irq(bp); + if (rc) { bnx2_free_mem(bp); return rc; @@ -4361,11 +4696,7 @@ bnx2_open(struct net_device *dev) rc = bnx2_init_nic(bp); if (rc) { - free_irq(bp->pdev->irq, dev); - if (bp->flags & USING_MSI_FLAG) { - pci_disable_msi(bp->pdev); - bp->flags &= ~USING_MSI_FLAG; - } + bnx2_free_irq(bp); bnx2_free_skbs(bp); bnx2_free_mem(bp); return rc; @@ -4389,16 +4720,13 @@ bnx2_open(struct net_device *dev) bp->dev->name); bnx2_disable_int(bp); - free_irq(bp->pdev->irq, dev); - pci_disable_msi(bp->pdev); - bp->flags &= ~USING_MSI_FLAG; + bnx2_free_irq(bp); rc = bnx2_init_nic(bp); - if (!rc) { - rc = request_irq(bp->pdev->irq, bnx2_interrupt, - IRQF_SHARED, dev->name, dev); - } + if (!rc) + rc = bnx2_request_irq(bp); + if (rc) { bnx2_free_skbs(bp); bnx2_free_mem(bp); @@ -4508,40 +4836,53 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) vlan_tag_flags |= (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16)); } - if ((mss = skb_shinfo(skb)->gso_size) && - (skb->len > (bp->dev->mtu + ETH_HLEN))) { + if ((mss = skb_shinfo(skb)->gso_size)) { u32 tcp_opt_len, ip_tcp_len; struct iphdr *iph; - if (skb_header_cloned(skb) && - pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { - dev_kfree_skb(skb); - return NETDEV_TX_OK; - } - vlan_tag_flags |= TX_BD_FLAGS_SW_LSO; - tcp_opt_len = 0; - if (tcp_hdr(skb)->doff > 5) - tcp_opt_len = tcp_optlen(skb); + tcp_opt_len = tcp_optlen(skb); + + if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) { + u32 tcp_off = skb_transport_offset(skb) - + sizeof(struct ipv6hdr) - ETH_HLEN; - ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); + vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) | + TX_BD_FLAGS_SW_FLAGS; + if (likely(tcp_off == 0)) + vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK; + else { + tcp_off >>= 3; + vlan_tag_flags |= ((tcp_off & 0x3) << + TX_BD_FLAGS_TCP6_OFF0_SHL) | + ((tcp_off & 0x10) << + TX_BD_FLAGS_TCP6_OFF4_SHL); + mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL; + } + } else { + if (skb_header_cloned(skb) && + pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { + dev_kfree_skb(skb); + return NETDEV_TX_OK; + } - iph = ip_hdr(skb); - iph->check = 0; - iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len); - tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, - iph->daddr, 0, - IPPROTO_TCP, 0); - if (tcp_opt_len || (iph->ihl > 5)) { - vlan_tag_flags |= ((iph->ihl - 5) + - (tcp_opt_len >> 2)) << 8; + ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); + + iph = ip_hdr(skb); + iph->check = 0; + iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len); + tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, + iph->daddr, 0, + IPPROTO_TCP, + 0); + if (tcp_opt_len || (iph->ihl > 5)) { + vlan_tag_flags |= ((iph->ihl - 5) + + (tcp_opt_len >> 2)) << 8; + } } - } - else - { + } else mss = 0; - } mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE); @@ -4622,11 +4963,7 @@ bnx2_close(struct net_device *dev) else reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; bnx2_reset_chip(bp, reset_code); - free_irq(bp->pdev->irq, dev); - if (bp->flags & USING_MSI_FLAG) { - pci_disable_msi(bp->pdev); - bp->flags &= ~USING_MSI_FLAG; - } + bnx2_free_irq(bp); bnx2_free_skbs(bp); bnx2_free_mem(bp); bp->link_up = 0; @@ -4735,6 +5072,8 @@ bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) if (bp->phy_flags & PHY_SERDES_FLAG) { cmd->supported |= SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE; + if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) + cmd->supported |= SUPPORTED_2500baseX_Full; cmd->port = PORT_FIBRE; } @@ -4798,8 +5137,10 @@ bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) advertising = cmd->advertising; - } - else if (cmd->advertising == ADVERTISED_1000baseT_Full) { + } else if (cmd->advertising == ADVERTISED_2500baseX_Full) { + if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) + return -EINVAL; + } else if (cmd->advertising == ADVERTISED_1000baseT_Full) { advertising = cmd->advertising; } else if (cmd->advertising == ADVERTISED_1000baseT_Half) { @@ -4975,7 +5316,7 @@ bnx2_nway_reset(struct net_device *dev) /* Force a link down visible on the other side */ if (bp->phy_flags & PHY_SERDES_FLAG) { - bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); + bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); spin_unlock_bh(&bp->phy_lock); msleep(20); @@ -4987,9 +5328,9 @@ bnx2_nway_reset(struct net_device *dev) mod_timer(&bp->timer, jiffies + bp->current_interval); } - bnx2_read_phy(bp, MII_BMCR, &bmcr); + bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); bmcr &= ~BMCR_LOOPBACK; - bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); + bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); spin_unlock_bh(&bp->phy_lock); @@ -5209,10 +5550,15 @@ bnx2_set_rx_csum(struct net_device *dev, u32 data) static int bnx2_set_tso(struct net_device *dev, u32 data) { - if (data) + struct bnx2 *bp = netdev_priv(dev); + + if (data) { dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN; - else - dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN); + if (CHIP_NUM(bp) == CHIP_NUM_5709) + dev->features |= NETIF_F_TSO6; + } else + dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 | + NETIF_F_TSO_ECN); return 0; } @@ -5510,6 +5856,17 @@ bnx2_phys_id(struct net_device *dev, u32 data) return 0; } +static int +bnx2_set_tx_csum(struct net_device *dev, u32 data) +{ + struct bnx2 *bp = netdev_priv(dev); + + if (CHIP_NUM(bp) == CHIP_NUM_5709) + return (ethtool_op_set_tx_hw_csum(dev, data)); + else + return (ethtool_op_set_tx_csum(dev, data)); +} + static const struct ethtool_ops bnx2_ethtool_ops = { .get_settings = bnx2_get_settings, .set_settings = bnx2_set_settings, @@ -5532,7 +5889,7 @@ static const struct ethtool_ops bnx2_ethtool_ops = { .get_rx_csum = bnx2_get_rx_csum, .set_rx_csum = bnx2_set_rx_csum, .get_tx_csum = ethtool_op_get_tx_csum, - .set_tx_csum = ethtool_op_set_tx_csum, + .set_tx_csum = bnx2_set_tx_csum, .get_sg = ethtool_op_get_sg, .set_sg = ethtool_op_set_sg, .get_tso = ethtool_op_get_tso, @@ -5562,6 +5919,9 @@ bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) case SIOCGMIIREG: { u32 mii_regval; + if (!netif_running(dev)) + return -EAGAIN; + spin_lock_bh(&bp->phy_lock); err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval); spin_unlock_bh(&bp->phy_lock); @@ -5575,6 +5935,9 @@ bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) if (!capable(CAP_NET_ADMIN)) return -EPERM; + if (!netif_running(dev)) + return -EAGAIN; + spin_lock_bh(&bp->phy_lock); err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in); spin_unlock_bh(&bp->phy_lock); @@ -5676,6 +6039,58 @@ bnx2_get_5709_media(struct bnx2 *bp) } } +static void __devinit +bnx2_get_pci_speed(struct bnx2 *bp) +{ + u32 reg; + + reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS); + if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) { + u32 clkreg; + + bp->flags |= PCIX_FLAG; + + clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS); + + clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; + switch (clkreg) { + case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: + bp->bus_speed_mhz = 133; + break; + + case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: + bp->bus_speed_mhz = 100; + break; + + case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: + case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: + bp->bus_speed_mhz = 66; + break; + + case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: + case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: + bp->bus_speed_mhz = 50; + break; + + case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: + case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: + case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: + bp->bus_speed_mhz = 33; + break; + } + } + else { + if (reg & BNX2_PCICFG_MISC_STATUS_M66EN) + bp->bus_speed_mhz = 66; + else + bp->bus_speed_mhz = 33; + } + + if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET) + bp->flags |= PCI_32BIT_FLAG; + +} + static int __devinit bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) { @@ -5683,6 +6098,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) unsigned long mem_len; int rc; u32 reg; + u64 dma_mask, persist_dma_mask; SET_MODULE_OWNER(dev); SET_NETDEV_DEV(dev, &pdev->dev); @@ -5721,25 +6137,11 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) goto err_out_release; } - if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) { - bp->flags |= USING_DAC_FLAG; - if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) { - dev_err(&pdev->dev, - "pci_set_consistent_dma_mask failed, aborting.\n"); - rc = -EIO; - goto err_out_release; - } - } - else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) { - dev_err(&pdev->dev, "System does not support DMA, aborting.\n"); - rc = -EIO; - goto err_out_release; - } - bp->dev = dev; bp->pdev = pdev; spin_lock_init(&bp->phy_lock); + spin_lock_init(&bp->indirect_lock); INIT_WORK(&bp->reset_task, bnx2_reset_task); dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0); @@ -5767,7 +6169,15 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bp->chip_id = REG_RD(bp, BNX2_MISC_ID); - if (CHIP_NUM(bp) != CHIP_NUM_5709) { + if (CHIP_NUM(bp) == CHIP_NUM_5709) { + if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) { + dev_err(&pdev->dev, + "Cannot find PCIE capability, aborting.\n"); + rc = -EIO; + goto err_out_unmap; + } + bp->flags |= PCIE_FLAG; + } else { bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX); if (bp->pcix_cap == 0) { dev_err(&pdev->dev, @@ -5777,51 +6187,33 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) } } - /* Get bus information. */ - reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS); - if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) { - u32 clkreg; - - bp->flags |= PCIX_FLAG; - - clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS); - - clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; - switch (clkreg) { - case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: - bp->bus_speed_mhz = 133; - break; - - case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: - bp->bus_speed_mhz = 100; - break; - - case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: - case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: - bp->bus_speed_mhz = 66; - break; + if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) { + if (pci_find_capability(pdev, PCI_CAP_ID_MSI)) + bp->flags |= MSI_CAP_FLAG; + } - case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: - case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: - bp->bus_speed_mhz = 50; - break; + /* 5708 cannot support DMA addresses > 40-bit. */ + if (CHIP_NUM(bp) == CHIP_NUM_5708) + persist_dma_mask = dma_mask = DMA_40BIT_MASK; + else + persist_dma_mask = dma_mask = DMA_64BIT_MASK; - case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: - case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: - case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: - bp->bus_speed_mhz = 33; - break; + /* Configure DMA attributes. */ + if (pci_set_dma_mask(pdev, dma_mask) == 0) { + dev->features |= NETIF_F_HIGHDMA; + rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask); + if (rc) { + dev_err(&pdev->dev, + "pci_set_consistent_dma_mask failed, aborting.\n"); + goto err_out_unmap; } - } - else { - if (reg & BNX2_PCICFG_MISC_STATUS_M66EN) - bp->bus_speed_mhz = 66; - else - bp->bus_speed_mhz = 33; + } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) { + dev_err(&pdev->dev, "System does not support DMA, aborting.\n"); + goto err_out_unmap; } - if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET) - bp->flags |= PCI_32BIT_FLAG; + if (!(bp->flags & PCIE_FLAG)) + bnx2_get_pci_speed(bp); /* 5706A0 may falsely detect SERR and PERR. */ if (CHIP_ID(bp) == CHIP_ID_5706_A0) { @@ -6005,6 +6397,26 @@ err_out: return rc; } +static char * __devinit +bnx2_bus_string(struct bnx2 *bp, char *str) +{ + char *s = str; + + if (bp->flags & PCIE_FLAG) { + s += sprintf(s, "PCI Express"); + } else { + s += sprintf(s, "PCI"); + if (bp->flags & PCIX_FLAG) + s += sprintf(s, "-X"); + if (bp->flags & PCI_32BIT_FLAG) + s += sprintf(s, " 32-bit"); + else + s += sprintf(s, " 64-bit"); + s += sprintf(s, " %dMHz", bp->bus_speed_mhz); + } + return str; +} + static int __devinit bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) { @@ -6012,6 +6424,7 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) struct net_device *dev = NULL; struct bnx2 *bp; int rc, i; + char str[40]; if (version_printed++ == 0) printk(KERN_INFO "%s", version); @@ -6052,6 +6465,23 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) dev->poll_controller = poll_bnx2; #endif + pci_set_drvdata(pdev, dev); + + memcpy(dev->dev_addr, bp->mac_addr, 6); + memcpy(dev->perm_addr, bp->mac_addr, 6); + bp->name = board_info[ent->driver_data].name; + + if (CHIP_NUM(bp) == CHIP_NUM_5709) + dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG; + else + dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; +#ifdef BCM_VLAN + dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; +#endif + dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN; + if (CHIP_NUM(bp) == CHIP_NUM_5709) + dev->features |= NETIF_F_TSO6; + if ((rc = register_netdev(dev))) { dev_err(&pdev->dev, "Cannot register net device\n"); if (bp->regview) @@ -6063,20 +6493,13 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) return rc; } - pci_set_drvdata(pdev, dev); - - memcpy(dev->dev_addr, bp->mac_addr, 6); - memcpy(dev->perm_addr, bp->mac_addr, 6); - bp->name = board_info[ent->driver_data].name, - printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, " + printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, " "IRQ %d, ", dev->name, bp->name, ((CHIP_ID(bp) & 0xf000) >> 12) + 'A', ((CHIP_ID(bp) & 0x0ff0) >> 4), - ((bp->flags & PCIX_FLAG) ? "-X" : ""), - ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"), - bp->bus_speed_mhz, + bnx2_bus_string(bp, str), dev->base_addr, bp->pdev->irq); @@ -6085,17 +6508,6 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) printk("%2.2x", dev->dev_addr[i]); printk("\n"); - dev->features |= NETIF_F_SG; - if (bp->flags & USING_DAC_FLAG) - dev->features |= NETIF_F_HIGHDMA; - dev->features |= NETIF_F_IP_CSUM; -#ifdef BCM_VLAN - dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; -#endif - dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN; - - netif_carrier_off(bp->dev); - return 0; } @@ -6140,6 +6552,7 @@ bnx2_suspend(struct pci_dev *pdev, pm_message_t state) reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; bnx2_reset_chip(bp, reset_code); bnx2_free_skbs(bp); + pci_save_state(pdev); bnx2_set_power_state(bp, pci_choose_state(pdev, state)); return 0; } @@ -6153,6 +6566,7 @@ bnx2_resume(struct pci_dev *pdev) if (!netif_running(dev)) return 0; + pci_restore_state(pdev); bnx2_set_power_state(bp, PCI_D0); netif_device_attach(dev); bnx2_init_nic(bp); diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h index 878eee58f12a..bd6288d6350f 100644 --- a/drivers/net/bnx2.h +++ b/drivers/net/bnx2.h @@ -1,6 +1,6 @@ /* bnx2.h: Broadcom NX2 network driver. * - * Copyright (c) 2004, 2005, 2006 Broadcom Corporation + * Copyright (c) 2004-2007 Broadcom Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,8 +24,11 @@ struct tx_bd { u32 tx_bd_haddr_hi; u32 tx_bd_haddr_lo; u32 tx_bd_mss_nbytes; + #define TX_BD_TCP6_OFF2_SHL (14) u32 tx_bd_vlan_tag_flags; #define TX_BD_FLAGS_CONN_FAULT (1<<0) + #define TX_BD_FLAGS_TCP6_OFF0_MSK (3<<1) + #define TX_BD_FLAGS_TCP6_OFF0_SHL (1) #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) #define TX_BD_FLAGS_IP_CKSUM (1<<2) #define TX_BD_FLAGS_VLAN_TAG (1<<3) @@ -34,6 +37,7 @@ struct tx_bd { #define TX_BD_FLAGS_END (1<<6) #define TX_BD_FLAGS_START (1<<7) #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) + #define TX_BD_FLAGS_TCP6_OFF4_SHL (12) #define TX_BD_FLAGS_SW_FLAGS (1<<13) #define TX_BD_FLAGS_SW_SNAP (1<<14) #define TX_BD_FLAGS_SW_LSO (1<<15) @@ -6292,6 +6296,41 @@ struct l2_fhdr { #define MII_BNX2_DSP_ADDRESS 0x17 #define MII_BNX2_DSP_EXPAND_REG 0x0f00 +#define MII_BNX2_BLK_ADDR 0x1f +#define MII_BNX2_BLK_ADDR_IEEE0 0x0000 +#define MII_BNX2_BLK_ADDR_GP_STATUS 0x8120 +#define MII_BNX2_GP_TOP_AN_STATUS1 0x1b +#define MII_BNX2_GP_TOP_AN_SPEED_MSK 0x3f00 +#define MII_BNX2_GP_TOP_AN_SPEED_10 0x0000 +#define MII_BNX2_GP_TOP_AN_SPEED_100 0x0100 +#define MII_BNX2_GP_TOP_AN_SPEED_1G 0x0200 +#define MII_BNX2_GP_TOP_AN_SPEED_2_5G 0x0300 +#define MII_BNX2_GP_TOP_AN_SPEED_1GKV 0x0d00 +#define MII_BNX2_GP_TOP_AN_FD 0x8 +#define MII_BNX2_BLK_ADDR_SERDES_DIG 0x8300 +#define MII_BNX2_SERDES_DIG_1000XCTL1 0x10 +#define MII_BNX2_SD_1000XCTL1_FIBER 0x01 +#define MII_BNX2_SD_1000XCTL1_AUTODET 0x10 +#define MII_BNX2_SERDES_DIG_MISC1 0x18 +#define MII_BNX2_SD_MISC1_FORCE_MSK 0xf +#define MII_BNX2_SD_MISC1_FORCE_2_5G 0x0 +#define MII_BNX2_SD_MISC1_FORCE 0x10 +#define MII_BNX2_BLK_ADDR_OVER1G 0x8320 +#define MII_BNX2_OVER1G_UP1 0x19 +#define MII_BNX2_BLK_ADDR_BAM_NXTPG 0x8350 +#define MII_BNX2_BAM_NXTPG_CTL 0x10 +#define MII_BNX2_NXTPG_CTL_BAM 0x1 +#define MII_BNX2_NXTPG_CTL_T2 0x2 +#define MII_BNX2_BLK_ADDR_CL73_USERB0 0x8370 +#define MII_BNX2_CL73_BAM_CTL1 0x12 +#define MII_BNX2_CL73_BAM_EN 0x8000 +#define MII_BNX2_CL73_BAM_STA_MGR_EN 0x4000 +#define MII_BNX2_CL73_BAM_NP_AFT_BP_EN 0x2000 +#define MII_BNX2_BLK_ADDR_AER 0xffd0 +#define MII_BNX2_AER_AER 0x1e +#define MII_BNX2_AER_AER_AN_MMD 0x3800 +#define MII_BNX2_BLK_ADDR_COMBO_IEEEB0 0xffe0 + #define MIN_ETHERNET_PACKET_SIZE 60 #define MAX_ETHERNET_PACKET_SIZE 1514 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014 @@ -6429,13 +6468,15 @@ struct bnx2 { u32 last_status_idx; u32 flags; -#define PCIX_FLAG 1 -#define PCI_32BIT_FLAG 2 -#define ONE_TDMA_FLAG 4 /* no longer used */ -#define NO_WOL_FLAG 8 -#define USING_DAC_FLAG 0x10 -#define USING_MSI_FLAG 0x20 -#define ASF_ENABLE_FLAG 0x40 +#define PCIX_FLAG 0x00000001 +#define PCI_32BIT_FLAG 0x00000002 +#define ONE_TDMA_FLAG 0x00000004 /* no longer used */ +#define NO_WOL_FLAG 0x00000008 +#define USING_MSI_FLAG 0x00000020 +#define ASF_ENABLE_FLAG 0x00000040 +#define MSI_CAP_FLAG 0x00000080 +#define ONE_SHOT_MSI_FLAG 0x00000100 +#define PCIE_FLAG 0x00000200 /* Put tx producer and consumer fields in separate cache lines. */ @@ -6484,6 +6525,7 @@ struct bnx2 { /* Used to synchronize phy accesses. */ spinlock_t phy_lock; + spinlock_t indirect_lock; u32 phy_flags; #define PHY_SERDES_FLAG 1 @@ -6495,6 +6537,13 @@ struct bnx2 { #define PHY_INT_MODE_LINK_READY_FLAG 0x200 #define PHY_DIS_EARLY_DAC_FLAG 0x400 + u32 mii_bmcr; + u32 mii_bmsr; + u32 mii_bmsr1; + u32 mii_adv; + u32 mii_lpa; + u32 mii_up1; + u32 chip_id; /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ #define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000) diff --git a/drivers/net/bnx2_fw.h b/drivers/net/bnx2_fw.h index 21d368ff424d..b49f439e0f67 100644 --- a/drivers/net/bnx2_fw.h +++ b/drivers/net/bnx2_fw.h @@ -15,680 +15,1071 @@ */ static u8 bnx2_COM_b06FwText[] = { - 0x1f, 0x8b, 0x08, 0x08, 0x09, 0x83, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65, - 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xec, 0x5b, 0x7d, 0x6c, - 0x5b, 0xd7, 0x75, 0x3f, 0xef, 0xf1, 0x51, 0x7a, 0x96, 0x68, 0xf9, 0x99, - 0x7e, 0x96, 0x59, 0x4f, 0xb1, 0x49, 0xf1, 0xc9, 0xd2, 0x62, 0x2d, 0x63, - 0x34, 0x35, 0xd1, 0x3a, 0x26, 0x66, 0x48, 0xda, 0x71, 0x36, 0x67, 0xa0, - 0x1d, 0x05, 0x51, 0x51, 0xaf, 0xd0, 0x48, 0xd9, 0xcd, 0xb2, 0x0c, 0x73, - 0x96, 0xb4, 0x70, 0xbc, 0xb4, 0xa1, 0x25, 0x79, 0xf5, 0x06, 0x45, 0xcf, - 0xb3, 0x34, 0x39, 0xc0, 0x82, 0x41, 0x10, 0x9d, 0x3a, 0x7f, 0x30, 0xa5, - 0xed, 0x7c, 0x19, 0xe8, 0x12, 0x29, 0xb2, 0x93, 0xb5, 0x43, 0xd0, 0xa6, - 0x68, 0xff, 0xe8, 0x8a, 0x6e, 0x30, 0x52, 0x0c, 0xf3, 0x3a, 0xa0, 0x30, - 0xfa, 0xc7, 0xe6, 0x2d, 0x1f, 0xdc, 0xef, 0xdc, 0x77, 0x1f, 0xf9, 0x48, - 0x51, 0x96, 0x1c, 0x34, 0x5d, 0xb7, 0x99, 0x80, 0xf0, 0xde, 0xbd, 0xf7, - 0xbc, 0x7b, 0xcf, 0x3d, 0xdf, 0xe7, 0xdc, 0xab, 0x5f, 0x53, 0xa9, 0x85, - 0xe4, 0x6f, 0x2d, 0xfe, 0xc2, 0x7f, 0xf4, 0xc7, 0xb9, 0xdb, 0x3e, 0x7d, - 0x5b, 0x1f, 0x5e, 0x07, 0x54, 0xdd, 0xaf, 0x72, 0xbf, 0x0f, 0x7f, 0x26, - 0xfe, 0xfa, 0xe4, 0x7b, 0xa3, 0x9f, 0x81, 0xbf, 0x2b, 0x18, 0x1c, 0xfe, - 0x09, 0x91, 0xb2, 0x0c, 0x8c, 0xf7, 0x57, 0x2e, 0x5f, 0x7f, 0x9c, 0x17, - 0x0e, 0xaf, 0x62, 0x9e, 0x9b, 0xbf, 0x9b, 0xbf, 0x9b, 0xbf, 0x9b, 0xbf, - 0x9b, 0xbf, 0x9b, 0xbf, 0x9b, 0xbf, 0xff, 0x3f, 0x3f, 0x9f, 0x13, 0x72, - 0x88, 0x98, 0x85, 0xff, 0x48, 0x57, 0xe3, 0x89, 0xa1, 0xa4, 0x45, 0xba, - 0x2f, 0x7e, 0x65, 0x28, 0x67, 0x11, 0x25, 0x8a, 0xdb, 0xc3, 0x29, 0xfa, - 0xb0, 0x9c, 0x37, 0x35, 0xe2, 0xfe, 0x5b, 0xe2, 0x1f, 0x3c, 0xfd, 0xfa, - 0x9d, 0x91, 0xab, 0xb3, 0x3e, 0xd2, 0x8d, 0xf8, 0xcb, 0xba, 0xb1, 0x8d, - 0xf4, 0x0e, 0x7c, 0xf3, 0x5c, 0xf7, 0x7f, 0xa8, 0xd4, 0xe6, 0xce, 0x75, - 0xa5, 0xfc, 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0xb8, 0x32, 0x8f, 0x2b, 0x23, 0x76, 0xc6, 0xe7, + 0x97, 0x11, 0xb7, 0x8d, 0xd2, 0xda, 0x3c, 0x68, 0x0e, 0x7e, 0x89, 0x5a, + 0xac, 0x74, 0x6d, 0x05, 0xe7, 0xe1, 0x9b, 0xa8, 0xc5, 0x4a, 0xd7, 0x54, + 0xac, 0x74, 0x6d, 0x65, 0x4a, 0xf0, 0xe1, 0xd9, 0xff, 0xdd, 0x14, 0x60, + 0x19, 0x30, 0x85, 0x19, 0xba, 0x4e, 0x53, 0x0d, 0x7a, 0xbf, 0x4e, 0x0c, + 0x78, 0x6c, 0x58, 0x50, 0x05, 0x7f, 0x18, 0xba, 0x62, 0x84, 0xa1, 0x0d, + 0xb8, 0xfd, 0xe3, 0x02, 0x34, 0xd3, 0x79, 0x4a, 0x0c, 0x30, 0x3c, 0x23, + 0x80, 0x79, 0x49, 0x18, 0x9a, 0x97, 0x60, 0x73, 0xaf, 0xfc, 0x0c, 0x90, + 0xbb, 0x7a, 0x6c, 0xc0, 0x6d, 0x7c, 0x48, 0xf9, 0x23, 0x83, 0x56, 0xfe, + 0x30, 0xb0, 0x38, 0xa9, 0x43, 0xf4, 0x37, 0xad, 0x7f, 0x2c, 0x07, 0x1b, + 0x5f, 0x6b, 0x02, 0x9a, 0xdb, 0x3c, 0x85, 0x94, 0xb9, 0x5b, 0x60, 0xbd, + 0x89, 0x75, 0x5d, 0x26, 0xb1, 0x76, 0xc3, 0xd2, 0x42, 0x0c, 0x19, 0xe9, + 0x09, 0x62, 0x06, 0x22, 0x3d, 0xd9, 0x00, 0xcb, 0x4e, 0x16, 0x60, 0x5e, + 0x11, 0x02, 0xd6, 0x0f, 0x0c, 0xd0, 0x3a, 0xe6, 0x00, 0x78, 0x2c, 0xa1, + 0x89, 0x01, 0x74, 0x07, 0x27, 0xd0, 0xfe, 0x7e, 0x65, 0xf0, 0xba, 0xe3, + 0x06, 0x09, 0x88, 0xa1, 0x8b, 0x7a, 0x14, 0xe5, 0x41, 0x79, 0xd4, 0x49, + 0x85, 0x81, 0xc4, 0xfc, 0x04, 0xf2, 0x1f, 0xd0, 0x1f, 0x20, 0x3f, 0x02, + 0xf3, 0x93, 0x33, 0x50, 0x0e, 0xb4, 0x36, 0xaa, 0x79, 0x0d, 0x48, 0x1f, + 0x28, 0x0c, 0x41, 0x65, 0x2a, 0x68, 0x8c, 0x03, 0xc8, 0x5e, 0x22, 0x04, + 0x0d, 0x3b, 0x20, 0x0d, 0x64, 0x37, 0x4f, 0x11, 0x01, 0xf3, 0x93, 0x02, + 0x84, 0x18, 0x1a, 0xe0, 0xf9, 0x89, 0x1d, 0xe8, 0x52, 0x98, 0x9b, 0xfe, + 0xff, 0x3f, 0xa6, 0xc2, 0x02, 0x4c, 0x7b, 0xa0, 0xb5, 0xb5, 0xbf, 0xff, + 0x1f, 0x10, 0x61, 0x61, 0x68, 0x81, 0xaf, 0xd1, 0x0b, 0x94, 0x07, 0x95, + 0x73, 0x0b, 0x80, 0xac, 0x36, 0x78, 0xbd, 0x0d, 0x92, 0x07, 0x89, 0xfd, + 0x02, 0x96, 0x2b, 0xff, 0xff, 0x2f, 0x85, 0xab, 0x05, 0x01, 0x00, 0xb3, + 0x28, 0x79, 0xae, 0x58, 0x7d, 0x00, 0x00, 0x00 }; -static u32 bnx2_COM_b06FwData[(0x0/4) + 1] = { 0x0 }; -static u32 bnx2_COM_b06FwRodata[(0x58/4) + 1] = { - 0x08002428, 0x0800245c, 0x0800245c, 0x0800245c, 0x0800245c, 0x0800245c, - 0x08002380, 0x0800245c, 0x080023e4, 0x0800245c, 0x0800231c, 0x0800245c, - 0x0800245c, 0x0800245c, 0x08002328, 0x00000000, 0x08003240, 0x08003270, - 0x080032a0, 0x080032d0, 0x08003300, 0x00000000, 0x00000000 }; -static u32 bnx2_COM_b06FwBss[(0x88/4) + 1] = { 0x0 }; -static u32 bnx2_COM_b06FwSbss[(0x1c/4) + 1] = { 0x0 }; +static const u32 bnx2_COM_b06FwData[(0x0/4) + 1] = { 0x0 }; +static const u32 bnx2_COM_b06FwRodata[(0x88/4) + 1] = { + 0x08001c1c, 0x08001c4c, 0x08001c4c, 0x08001c4c, 0x08001c4c, 0x08001c4c, + 0x08001b74, 0x08001c4c, 0x08001bdc, 0x08001c4c, 0x08001b08, 0x08001c4c, + 0x08001c4c, 0x08001c4c, 0x08001b14, 0x00000000, 0x08002b58, 0x08002ba8, + 0x08002bd8, 0x08002c08, 0x08002c38, 0x00000000, 0x080060cc, 0x080060cc, + 0x080060cc, 0x080060cc, 0x080060cc, 0x08006100, 0x08006100, 0x08006140, + 0x0800614c, 0x0800614c, 0x080060cc, 0x00000000, 0x00000000 }; +static const u32 bnx2_COM_b06FwBss[(0x88/4) + 1] = { 0x0 }; +static const u32 bnx2_COM_b06FwSbss[(0x60/4) + 1] = { 0x0 }; static struct fw_info bnx2_com_fw_06 = { - .ver_major = 0x1, - .ver_minor = 0x0, - .ver_fix = 0x0, + .ver_major = 0x3, + .ver_minor = 0x4, + .ver_fix = 0x3, - .start_addr = 0x080008b4, + .start_addr = 0x080000b4, .text_addr = 0x08000000, - .text_len = 0x57bc, + .text_len = 0x7d54, .text_index = 0x0, .gz_text = bnx2_COM_b06FwText, .gz_text_len = sizeof(bnx2_COM_b06FwText), - .data_addr = 0x08005840, + .data_addr = 0x08007e00, .data_len = 0x0, .data_index = 0x0, .data = bnx2_COM_b06FwData, - .sbss_addr = 0x08005840, - .sbss_len = 0x1c, + .sbss_addr = 0x08007e00, + .sbss_len = 0x60, .sbss_index = 0x0, .sbss = bnx2_COM_b06FwSbss, - .bss_addr = 0x08005860, + .bss_addr = 0x08007e60, .bss_len = 0x88, .bss_index = 0x0, .bss = bnx2_COM_b06FwBss, - .rodata_addr = 0x080057c0, - .rodata_len = 0x58, + .rodata_addr = 0x08007d58, + .rodata_len = 0x88, .rodata_index = 0x0, .rodata = bnx2_COM_b06FwRodata, }; diff --git a/drivers/net/bnx2_fw2.h b/drivers/net/bnx2_fw2.h index 680c769a3fc0..2c067531f031 100644 --- a/drivers/net/bnx2_fw2.h +++ b/drivers/net/bnx2_fw2.h @@ -1,13 +1,13 @@ /* bnx2_fw2.h: Broadcom NX2 network driver. * - * Copyright (c) 2006 Broadcom Corporation + * Copyright (c) 2004, 2005, 2006, 2007 Broadcom Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, except as noted below. * * This file contains firmware data derived from proprietary unpublished - * source code, Copyright (c) 2006 Broadcom Corporation. + * source code, Copyright (c) 2004, 2005, 2006, 2007 Broadcom Corporation. * * Permission is hereby granted for the distribution of this firmware data * in hexadecimal or equivalent format, provided this copyright notice is @@ -15,3289 +15,3260 @@ */ static u8 bnx2_COM_b09FwText[] = { - 0x1f, 0x8b, 0x08, 0x08, 0xac, 0xfb, 0x2f, 0x45, 0x00, 0x03, 0x74, 0x65, - 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xdc, 0x5b, 0x6b, 0x70, - 0x1b, 0xd7, 0x75, 0x3e, 0xfb, 0x00, 0x09, 0x91, 0x10, 0xb5, 0xa4, 0x60, - 0x1a, 0x96, 0x68, 0x07, 0x20, 0x57, 0x22, 0x6a, 0xb1, 0x29, 0x4c, 0x33, - 0x16, 0x9b, 0xc2, 0x12, 0x02, 0x50, 0xae, 0x26, 0xc3, 0x3a, 0x94, 0xcd, - 0xd8, 0x4a, 0xaa, 0xc9, 0x30, 0x00, 0xa5, 0xf4, 0x61, 0xb7, 0x92, 0xab, - 0xa9, 0x5d, 0xd7, 0xaa, 0x21, 0x92, 0x6a, 0xf5, 0x83, 0xe5, 0x2a, 0x16, - 0x43, 0xa9, 0xd3, 0x74, 0xc2, 0x12, 0x56, 0xac, 0x4e, 0x31, 0x85, 0xfc, - 0xd6, 0x38, 0xb1, 0xc9, 0x4a, 0x76, 0xeb, 0xf4, 0xe1, 0xa6, 0x33, 0xcd, - 0xa3, 0x9d, 0x36, 0xf6, 0xa8, 0x3f, 0xea, 0xe9, 0xd3, 0x33, 0x6e, 0xa7, - 0xea, 0xd8, 0x0e, 0xfa, 0x7d, 0x77, 0x77, 0x81, 0x25, 0x48, 0xbd, 0xfc, - 0xc8, 0x8f, 0x70, 0x06, 0xb3, 0x7b, 0xef, 0xde, 0xbd, 0xf7, 0xdc, 0xf3, - 0xf8, 0xce, 0x63, 0x2f, 0xfb, 0x44, 0x5a, 0xc4, 0xfb, 0x5b, 0x8b, 0x5f, - 0xfc, 0xfe, 0x5f, 0x2d, 0x7c, 0x7c, 0xf0, 0xe3, 0xfd, 0x22, 0xb7, 0xdc, - 0xa2, 0xb7, 0x86, 0x75, 0xf6, 0x1b, 0xf8, 0x45, 0xf1, 0xeb, 0xf7, 0xee, - 0x57, 0xfb, 0xb3, 0xf0, 0x7b, 0x13, 0x0f, 0xc7, 0xfe, 0x55, 0x44, 0xbb, - 0xc4, 0x98, 0xe0, 0x5f, 0xb5, 0x7a, 0xf9, 0xe7, 0x5c, 0x38, 0x7e, 0x89, - 0x67, 0x86, 0xbb, 0x9c, 0xa2, 0x97, 0x3f, 0x09, 0xeb, 0x69, 0x39, 0x94, - 0xb5, 0x25, 0x6c, 0xa4, 0xdf, 0x3c, 0x54, 0xb0, 0x45, 0x32, 0xe5, 0x2d, - 0xf1, 0x9c, 0xbc, 0x57, 0x2d, 0x46, 0x4d, 0x61, 0xff, 0x8d, 0xe9, 0x77, - 0xbf, 0xf6, 0xe2, 0xd6, 0xc4, 0x5b, 0xf3, 0x86, 0x84, 0xad, 0xf4, 0x19, - 0xb1, 0x36, 0x4b, 0xb8, 0x0b, 0xef, 0x7c, 0xb5, 0xf7, 0x3d, 0x91, 0x36, - 0x7f, 0xae, 0x37, 0xab, 0x2f, 0xf6, 0x4a, 0x71, 0x43, 0x3a, 0x2c, 0x7a, - 0x7a, 0xd3, 0xf7, 0xb3, 0x86, 0x35, 0x66, 0xa4, 0x2d, 0x59, 0xac, 0xc8, - 0xc8, 0xde, 0x69, 0x09, 0x87, 0xd3, 0x47, 0x9b, 0x9b, 0x37, 0x49, 0xd8, - 0x4c, 0x8f, 0x1d, 0xfa, 0x6d, 0xfb, 0xd1, 0xaa, 0x6e, 0xdb, 0xc9, 0x05, - 0x89, 0x0c, 0x9e, 0x1a, 0xc0, 0xf3, 0x72, 0x22, 0x29, 0xb2, 0x55, 0x74, - 0xbb, 0x18, 0x31, 0xec, 0xb0, 0x64, 0x2b, 0xb6, 0xe4, 0x2a, 0x22, 0x7f, - 0x5e, 0xd6, 0xe4, 0x94, 0xdd, 0x29, 0x0b, 0x7d, 0xef, 0x56, 0x33, 0xa0, - 0xe5, 0xcf, 0xec, 0xb1, 0x43, 0x53, 0x36, 0xe9, 0x9d, 0x6d, 0x76, 0xe9, - 0x9d, 0x6a, 0x2a, 0xd8, 0xa6, 0x4c, 0x94, 0xd9, 0x37, 0xa2, 0xb3, 0x2f, - 0x94, 0x7e, 0x68, 0xcd, 0x29, 0x3b, 0xe2, 0xf5, 0xed, 0xdc, 0x9e, 0xc5, - 0x7c, 0x93, 0x65, 0x8e, 0x3d, 0x93, 0x2a, 0xd8, 0x51, 0xaf, 0x3f, 0x79, - 0x5b, 0xd6, 0x8e, 0xa1, 0xbf, 0xcb, 0x7b, 0x76, 0xf2, 0xbe, 0x82, 0x6d, - 0x7b, 0xcf, 0xbe, 0x8a, 0xb9, 0x93, 0x5e, 0xff, 0x7d, 0xdb, 0x0a, 0x76, - 0x9f, 0xd7, 0x3f, 0xbd, 0x2d, 0x6b, 0xa7, 0xbc, 0xfe, 0xe4, 0xee, 0x82, - 0x3d, 0xe0, 0xf5, 0x9f, 0xbd, 0x3d, 0x6b, 0x0f, 0x7a, 0xfd, 0x0f, 0x6d, - 0x2d, 0xd8, 0x69, 0xf4, 0x1f, 0x6d, 0xd6, 0x37, 0x59, 0x72, 0xa4, 0x1c, - 0xc7, 0x2f, 0x83, 0x67, 0x43, 0xe8, 0xdb, 0x89, 0xdf, 0x30, 0x7e, 0xbf, - 0xb8, 0x4e, 0xda, 0x46, 0x70, 0xfd, 0xc6, 0x46, 0x97, 0x77, 0xe0, 0x91, - 0x13, 0x96, 0x37, 0x8c, 0x98, 0xbc, 0xd8, 0xfb, 0x06, 0x78, 0x68, 0xc9, - 0x99, 0x8a, 0x68, 0x23, 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0x7d, 0xc4, 0x0b, 0x18, 0x7e, 0x01, 0xcb, 0x95, - 0xff, 0xff, 0x97, 0xc2, 0xd5, 0x82, 0x00, 0x00, 0xd4, 0xc2, 0xcb, 0x42, - 0x60, 0x7c, 0x00, 0x00, 0x00 }; -static u32 bnx2_COM_b09FwData[(0x0/4) + 1] = { 0x0 }; -static u32 bnx2_COM_b09FwRodata[(0x88/4) + 1] = { - 0x08001ad8, 0x08001b14, 0x08001b14, 0x08001b14, 0x08001b14, 0x08001b14, - 0x08001a24, 0x08001b14, 0x08001a98, 0x08001b14, 0x080019ac, 0x08001b14, - 0x08001b14, 0x08001b14, 0x080019b8, 0x0, 0x08002a2c, 0x08002a7c, - 0x08002aac, 0x08002adc, 0x08002b0c, 0x0, 0x08005fac, 0x08005fac, - 0x08005fac, 0x08005fac, 0x08005fac, 0x08005fd8, 0x08005fd8, 0x08006018, - 0x08006024, 0x08006024, 0x08005fac, 0x0, 0x0 }; -static u32 bnx2_COM_b09FwBss[(0x88/4) + 1] = { 0x0 }; -static u32 bnx2_COM_b09FwSbss[(0x5c/4) + 1] = { 0x0 }; + 0x1f, 0x8b, 0x08, 0x00, 0x0e, 0x34, 0xe7, 0x45, 0x00, 0x03, 0xdc, 0x5b, + 0x6d, 0x70, 0x5c, 0xd5, 0x79, 0x7e, 0xef, 0xd9, 0xbb, 0xf2, 0x5a, 0x92, + 0xe5, 0x6b, 0x79, 0x23, 0x16, 0x4b, 0xc0, 0xae, 0x75, 0x6d, 0x69, 0xb0, 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0xce, 0x70, 0x40, 0x00, 0x16, 0x56, + 0xff, 0xff, 0x1f, 0x53, 0x61, 0x01, 0xa6, 0x53, 0xd0, 0x3a, 0xd6, 0xdf, + 0xff, 0x0f, 0x88, 0xb0, 0x30, 0xb4, 0xc0, 0xd7, 0x23, 0xe6, 0xc8, 0x83, + 0xca, 0xd0, 0x05, 0x40, 0x56, 0x1b, 0xbc, 0x4d, 0xc0, 0x02, 0xbe, 0xef, + 0x79, 0x01, 0xc3, 0x2f, 0x60, 0x99, 0xf5, 0xff, 0xff, 0x52, 0xb8, 0x5a, + 0x10, 0x00, 0x00, 0x19, 0x3f, 0x16, 0x21, 0xc4, 0x7d, 0x00, 0x00, 0x00 }; + +static const u32 bnx2_COM_b09FwData[(0x0/4) + 1] = { 0x0 }; +static const u32 bnx2_COM_b09FwRodata[(0x88/4) + 1] = { + 0x08001b68, 0x08001ba4, 0x08001ba4, 0x08001ba4, 0x08001ba4, 0x08001ba4, + 0x08001ab4, 0x08001ba4, 0x08001b28, 0x08001ba4, 0x08001a3c, 0x08001ba4, + 0x08001ba4, 0x08001ba4, 0x08001a48, 0x00000000, 0x08002abc, 0x08002b0c, + 0x08002b3c, 0x08002b6c, 0x08002b9c, 0x00000000, 0x0800604c, 0x0800604c, + 0x0800604c, 0x0800604c, 0x0800604c, 0x08006078, 0x08006078, 0x080060b8, + 0x080060c4, 0x080060c4, 0x0800604c, 0x00000000, 0x00000000 }; +static const u32 bnx2_COM_b09FwBss[(0x88/4) + 1] = { 0x0 }; +static const u32 bnx2_COM_b09FwSbss[(0x60/4) + 1] = { 0x0 }; static struct fw_info bnx2_com_fw_09 = { - .ver_major = 0x1, - .ver_minor = 0x0, - .ver_fix = 0x0, + .ver_major = 0x3, + .ver_minor = 0x4, + .ver_fix = 0x3, - .start_addr = 0x080000b0, + .start_addr = 0x080000b4, .text_addr = 0x08000000, - .text_len = 0x7c5c, + .text_len = 0x7dc0, .text_index = 0x0, .gz_text = bnx2_COM_b09FwText, .gz_text_len = sizeof(bnx2_COM_b09FwText), - .data_addr = 0x08007d00, + .data_addr = 0x08007e60, .data_len = 0x0, .data_index = 0x0, .data = bnx2_COM_b09FwData, - .sbss_addr = 0x08007d00, - .sbss_len = 0x5c, + .sbss_addr = 0x08007e60, + .sbss_len = 0x60, .sbss_index = 0x0, .sbss = bnx2_COM_b09FwSbss, - .bss_addr = 0x08007d60, + .bss_addr = 0x08007ec0, .bss_len = 0x88, .bss_index = 0x0, .bss = bnx2_COM_b09FwBss, - .rodata_addr = 0x08007c60, + .rodata_addr = 0x08007dc0, .rodata_len = 0x88, .rodata_index = 0x0, .rodata = bnx2_COM_b09FwRodata, }; static u8 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0xf9, 0xbf, 0xe7, 0x22, 0xf2, 0x7f, 0x01, 0x95, 0xf6, 0x2d, - 0x58, 0xd0, 0x73, 0x00, 0x00, 0x00 }; -static u32 bnx2_CP_b09FwData[(0x50/4) + 1] = { - 0x00010030, 0x00000030, 0x00000000, 0x00000001, 0x00010fd0, 0x00000fd0, - 0x00001430, 0x0000007f, 0x00030400, 0x00001000, 0x00000030, 0x00000020, - 0x00050200, 0x00001000, 0x00000030, 0x00000010, 0x00010400, 0x00000400, - 0x00001030, 0x00000020, 0x00000000 }; -static u32 bnx2_CP_b09FwRodata[(0x118/4) + 1] = { - 0x080005d8, 0x080007f8, 0x0800073c, 0x08000764, 0x0800078c, 0x080007b4, - 0x08000610, 0x080005fc, 0x08000820, 0x08000820, 0x0800062c, 0x08000648, - 0x08000648, 0x08000820, 0x08000660, 0x08000674, 0x08000820, 0x08000688, - 0x08000820, 0x08000820, 0x0800069c, 0x08000820, 0x08000820, 0x08000820, - 0x08000820, 0x08000820, 0x08000820, 0x08000820, 0x08000820, 0x08000820, - 0x08000820, 0x080006b0, 0x08000820, 0x080006c4, 0x080006d8, 0x080006ec, - 0x08000820, 0x08000700, 0x08000714, 0x08000728, 0x08003740, 0x08003758, - 0x08003768, 0x08003778, 0x08003790, 0x080037a8, 0x080037b8, 0x080037c8, - 0x080037e8, 0x080037f8, 0x08003808, 0x08003898, 0x080037d8, 0x08003818, - 0x08003828, 0x08003840, 0x08003860, 0x08003898, 0x08003878, 0x08003878, - 0x080055f0, 0x080055f0, 0x080055f0, 0x080055f0, 0x080055f0, 0x08005618, - 0x08005618, 0x08005640, 0x08005690, 0x08005660, 0x00000000 }; -static u32 bnx2_CP_b09FwBss[(0x870/4) + 1] = { 0x0 }; -static u32 bnx2_CP_b09FwSbss[(0xe9/4) + 1] = { 0x0 }; + 0x1f, 0x8b, 0x08, 0x00, 0x0f, 0x34, 0xe7, 0x45, 0x00, 0x03, 0xbd, 0x7d, + 0x0d, 0x74, 0x5c, 0x57, 0x7d, 0xe7, 0xff, 0xdd, 0x19, 0x49, 0x63, 0x59, + 0x96, 0x9f, 0xe5, 0x89, 0x32, 0x51, 0x84, 0x3d, 0x23, 0x3d, 0xd9, 0x22, + 0x12, 0xe1, 0xc5, 0x11, 0xac, 0xda, 0x2a, 0xe9, 0x30, 0x92, 0x3f, 0x12, + 0x02, 0xab, 0x10, 0x43, 0xb3, 0x1c, 0x4a, 0xc5, 0x48, 0x4e, 0x02, 0x04, + 0xea, 0x40, 0xe8, 0x86, 0xdd, 0xec, 0x66, 0x32, 0x92, 0x3f, 0x9a, 0x8e, + 0x3d, 0x93, 0x44, 0x89, 0xbd, 0xdd, 0x9c, 0xad, 0x90, 0x14, 0x3b, 0x74, + 0x07, 0x4f, 0xe2, 0x98, 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0x7f, 0xa7, 0x40, 0xe4, 0xff, 0x02, 0xfb, 0x2e, + 0x88, 0x71, 0xec, 0x6e, 0x00, 0x00, 0x00 }; + +static const u32 bnx2_CP_b09FwData[(0x0/4) + 1] = { 0x0 }; +static const u32 bnx2_CP_b09FwRodata[(0x118/4) + 1] = { + 0x0800061c, 0x0800083c, 0x08000780, 0x080007a8, 0x080007d0, 0x080007f8, + 0x08000654, 0x08000640, 0x08000864, 0x08000864, 0x08000670, 0x0800068c, + 0x0800068c, 0x08000864, 0x080006a4, 0x080006b8, 0x08000864, 0x080006cc, + 0x08000864, 0x08000864, 0x080006e0, 0x08000864, 0x08000864, 0x08000864, + 0x08000864, 0x08000864, 0x08000864, 0x08000864, 0x08000864, 0x08000864, + 0x08000864, 0x080006f4, 0x08000864, 0x08000708, 0x0800071c, 0x08000730, + 0x08000864, 0x08000744, 0x08000758, 0x0800076c, 0x08003200, 0x08003218, + 0x08003228, 0x08003238, 0x08003250, 0x08003268, 0x08003278, 0x08003288, + 0x080032a8, 0x080032b8, 0x080032c8, 0x08003358, 0x08003298, 0x080032d8, + 0x080032e8, 0x08003300, 0x08003320, 0x08003358, 0x08003338, 0x08003338, + 0x080050d4, 0x080050d4, 0x080050d4, 0x080050d4, 0x080050d4, 0x080050fc, + 0x080050fc, 0x08005124, 0x08005174, 0x08005144, 0x00000000 }; +static const u32 bnx2_CP_b09FwBss[(0x3b0/4) + 1] = { 0x0 }; +static const u32 bnx2_CP_b09FwSbss[(0xa1/4) + 1] = { 0x0 }; static struct fw_info bnx2_cp_fw_09 = { - .ver_major = 0x1, - .ver_minor = 0x0, - .ver_fix = 0x0, + .ver_major = 0x3, + .ver_minor = 0x4, + .ver_fix = 0x3, .start_addr = 0x0800006c, .text_addr = 0x08000000, - .text_len = 0x73cc, + .text_len = 0x6ee8, .text_index = 0x0, .gz_text = bnx2_CP_b09FwText, .gz_text_len = sizeof(bnx2_CP_b09FwText), - .data_addr = 0x08007500, - .data_len = 0x50, + .data_addr = 0x08007020, + .data_len = 0x0, .data_index = 0x0, .data = bnx2_CP_b09FwData, - .sbss_addr = 0x08007554, - .sbss_len = 0xe9, + .sbss_addr = 0x08007024, + .sbss_len = 0xa1, .sbss_index = 0x0, .sbss = bnx2_CP_b09FwSbss, - .bss_addr = 0x08007640, - .bss_len = 0x870, + .bss_addr = 0x080070d0, + .bss_len = 0x3b0, .bss_index = 0x0, .bss = bnx2_CP_b09FwBss, - .rodata_addr = 0x080073d0, + .rodata_addr = 0x08006ee8, .rodata_len = 0x118, .rodata_index = 0x0, .rodata = bnx2_CP_b09FwRodata, }; static u8 bnx2_RXP_b09FwText[] = { - 0x1f, 0x8b, 0x08, 0x08, 0x19, 0xfd, 0x2f, 0x45, 0x00, 0x03, 0x74, 0x65, - 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xec, 0x5c, 0x6b, 0x6c, - 0x1c, 0xd7, 0x75, 0x3e, 0xf3, 0x20, 0xb5, 0xa2, 0xf8, 0x18, 0x2e, 0x57, - 0xcc, 0x4a, 0x66, 0xec, 0x5d, 0x71, 0x24, 0xb2, 0x16, 0x6b, 0x8c, 0xd8, - 0xad, 0x4d, 0x04, 0x6b, 0x7b, 0x33, 0xbb, 0x92, 0x98, 0x54, 0x85, 0x29, - 0x87, 0x75, 0x0c, 0xc3, 0x75, 0xd9, 0xa5, 0x1a, 0xbb, 0xae, 0x51, 0xc8, - 0x8f, 0xc4, 0x06, 0x6a, 0xd6, 0x9b, 0x25, 0xdd, 0xa8, 0xe9, 0x82, 0x43, - 0x4b, 0xaa, 0xe9, 0x02, 0x69, 0xbb, 0x20, 0xa9, 0xc7, 0x8f, 0x85, 0x56, - 0x76, 0x52, 0xc7, 0xf9, 0xe1, 0x48, 0x50, 0x95, 0x20, 0x28, 0x0c, 0x43, - 0x48, 0x8d, 0xd6, 0x3f, 0xda, 0x40, 0x95, 0x9f, 0x68, 0x92, 0x42, 0x41, - 0x0b, 0xc7, 0x68, 0x6c, 0x4f, 0xbf, 0xef, 0xce, 0x0c, 0xb9, 0xa4, 0x5f, - 0x40, 0x7f, 0xf4, 0x4f, 0xe7, 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0xbc, 0x1f, 0xef, 0xa8, 0x73, 0x80, 0x99, - 0xa6, 0xf8, 0x7e, 0x11, 0x65, 0xfa, 0x46, 0xe6, 0xf0, 0x4c, 0x84, 0x75, - 0xaf, 0xf5, 0x6b, 0xac, 0x7e, 0xf2, 0x41, 0xbf, 0x99, 0xb2, 0x95, 0xcf, - 0x44, 0xb6, 0x94, 0xf1, 0x8b, 0xf5, 0x7e, 0xca, 0xdc, 0xfd, 0x36, 0x7f, - 0x51, 0xf9, 0x8b, 0xa9, 0x7d, 0x0a, 0xe1, 0xb7, 0x3d, 0xf2, 0x94, 0xc9, - 0xdc, 0xf5, 0xb4, 0x1a, 0x2b, 0xfd, 0x34, 0xcc, 0xd3, 0xdd, 0x52, 0xfb, - 0x2b, 0x6f, 0xf7, 0x07, 0x79, 0xee, 0x1c, 0x7b, 0x67, 0x6e, 0xfb, 0x4e, - 0x3a, 0x61, 0x8e, 0x7b, 0x3b, 0x70, 0xab, 0x56, 0x62, 0xe0, 0x41, 0xc8, - 0x3b, 0xbb, 0x45, 0xf3, 0x63, 0xa1, 0xf6, 0x2f, 0x7f, 0x43, 0xf3, 0x73, - 0xd3, 0xc7, 0xf0, 0xdb, 0x7e, 0xda, 0xb6, 0x94, 0x1b, 0x97, 0x02, 0xbf, - 0x91, 0xb6, 0xa1, 0x21, 0x2b, 0x50, 0x47, 0x5e, 0x05, 0x9f, 0x6c, 0xb7, - 0xe5, 0xdf, 0x7f, 0x01, 0x99, 0xe7, 0xd3, 0x46, 0x40, 0x67, 0x00, 0x00, - 0x00 }; -static u32 bnx2_RXP_b09FwData[(0x0/4) + 1] = { 0x0 }; -static u32 bnx2_RXP_b09FwRodata[(0x278/4) + 1] = { - 0x08003fa4, 0x08003ea4, 0x08003f48, 0x08003f60, 0x08003f78, 0x08003f98, - 0x08003fa4, 0x08003fa4, 0x08003eac, 0x00000000, 0x080049d4, 0x08004a0c, - 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004a44, 0x08004c08, - 0x08004b50, 0x08004b88, 0x08004c08, 0x08004ad8, 0x08004c08, 0x08004c08, - 0x08004b88, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, - 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004bc8, - 0x08004c08, 0x08004bc8, 0x08004b50, 0x08004c08, 0x08004c08, 0x08004bc8, - 0x08004bc8, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, - 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, - 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, - 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, - 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, - 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, - 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, - 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, - 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, - 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, - 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, - 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, - 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, - 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, - 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, - 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, 0x08004c08, - 0x08004ab4, 0x00000000, 0x0800602c, 0x08006044, 0x08006044, 0x08006044, - 0x0800602c, 0x08006044, 0x08006044, 0x08006044, 0x0800602c, 0x08006044, - 0x08006044, 0x08006044, 0x0800602c, 0x08006044, 0x08006044, 0x08006044, - 0x08006038, 0x00000000, 0x00000000 }; -static u32 bnx2_RXP_b09FwBss[(0x13dc/4) + 1] = { 0x0 }; -static u32 bnx2_RXP_b09FwSbss[(0x2c/4) + 1] = { 0x0 }; + 0x1f, 0x8b, 0x08, 0x00, 0x0e, 0x34, 0xe7, 0x45, 0x00, 0x03, 0xec, 0x5c, + 0x5d, 0x6c, 0x1c, 0xd7, 0x75, 0x3e, 0xf3, 0x43, 0x6a, 0x49, 0xf1, 0x67, + 0xb8, 0x5c, 0xb1, 0x2b, 0x99, 0x96, 0x77, 0xc9, 0x91, 0xc8, 0x58, 0x8a, + 0x31, 0xa2, 0x09, 0x5b, 0x48, 0x17, 0xf6, 0x76, 0x76, 0x25, 0xb1, 0xb1, + 0x03, 0x53, 0xb6, 0x62, 0x07, 0x45, 0x6a, 0xb0, 0x4b, 0xb9, 0x0e, 0x8c, + 0x06, 0x90, 0xff, 0x52, 0xbf, 0xb0, 0xde, 0x2c, 0xa9, 0x58, 0x4d, 0x17, + 0x9c, 0xb5, 0x4d, 0x9b, 0x0e, 0x60, 0xb7, 0x0b, 0x92, 0x12, 0xf5, 0xb0, + 0xd0, 0xb2, 0xa9, 0xdb, 0xea, 0xc1, 0x8e, 0x09, 0x56, 0xb1, 0x53, 0xa0, + 0x2d, 0x5c, 0x27, 0x69, 0xfc, 0x10, 0x14, 0xaa, 0xec, 0xc4, 0x42, 0xd1, + 0xa2, 0x02, 0x12, 0xd8, 0x29, 0x22, 0x7b, 0xfa, 0x7d, 0x77, 0x66, 0xc8, + 0x25, 0x2d, 0xdb, 0x41, 0x1f, 0xfa, 0xd2, 0xbd, 0xc0, 0x62, 0xee, 0xbd, + 0x73, 0xee, 0xb9, 0xe7, 0x9e, 0xff, 0x73, 0x87, 0xd2, 0x1f, 0x74, 0x48, + 0xbb, 0x84, 0xad, 0x13, 0xbf, 0xd4, 0x89, 0x27, 0x1e, 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0x9c, 0x9f, 0xe3, + 0x9b, 0x50, 0xc7, 0xcb, 0x37, 0x07, 0xbc, 0x9c, 0x77, 0x8e, 0x7d, 0x30, + 0xcf, 0xfd, 0x20, 0x9d, 0x30, 0xdf, 0xbd, 0xbd, 0xf9, 0x3f, 0x52, 0xe5, + 0x3c, 0xf0, 0xce, 0x6e, 0xd1, 0xfc, 0x98, 0xab, 0xfe, 0xdb, 0xdd, 0xd3, + 0xfc, 0xdc, 0xf0, 0x31, 0xfc, 0x6e, 0x80, 0xb6, 0x2d, 0x71, 0xe3, 0x92, + 0x97, 0x3b, 0xaa, 0x6d, 0x68, 0x60, 0x05, 0xea, 0xc8, 0xab, 0xe0, 0x93, + 0x66, 0x5b, 0xfe, 0xfd, 0x07, 0x69, 0x3f, 0x51, 0x42, 0x6c, 0x67, 0x00, + 0x00, 0x00 }; + +static const u32 bnx2_RXP_b09FwData[(0x0/4) + 1] = { 0x0 }; +static const u32 bnx2_RXP_b09FwRodata[(0x278/4) + 1] = { + 0x08004050, 0x08003f50, 0x08003ff4, 0x0800400c, 0x08004024, 0x08004044, + 0x08004050, 0x08004050, 0x08003f58, 0x00000000, 0x08004a0c, 0x08004a44, + 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004a7c, 0x08004c40, + 0x08004b88, 0x08004bc0, 0x08004c40, 0x08004b10, 0x08004c40, 0x08004c40, + 0x08004bc0, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, + 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c00, + 0x08004c40, 0x08004c00, 0x08004b88, 0x08004c40, 0x08004c40, 0x08004c00, + 0x08004c00, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, + 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, + 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, + 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, + 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, + 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, + 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, + 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, + 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, + 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, + 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, + 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, + 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, + 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, + 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, + 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, 0x08004c40, + 0x08004aec, 0x00000000, 0x08006058, 0x08006070, 0x08006070, 0x08006070, + 0x08006058, 0x08006070, 0x08006070, 0x08006070, 0x08006058, 0x08006070, + 0x08006070, 0x08006070, 0x08006058, 0x08006070, 0x08006070, 0x08006070, + 0x08006064, 0x00000000, 0x00000000 }; +static const u32 bnx2_RXP_b09FwBss[(0x13dc/4) + 1] = { 0x0 }; +static const u32 bnx2_RXP_b09FwSbss[(0x20/4) + 1] = { 0x0 }; static struct fw_info bnx2_rxp_fw_09 = { - .ver_major = 0x1, - .ver_minor = 0x0, - .ver_fix = 0x0, + .ver_major = 0x3, + .ver_minor = 0x4, + .ver_fix = 0x3, .start_addr = 0x08003184, .text_addr = 0x08000000, - .text_len = 0x673c, + .text_len = 0x6768, .text_index = 0x0, .gz_text = bnx2_RXP_b09FwText, .gz_text_len = sizeof(bnx2_RXP_b09FwText), - .data_addr = 0x080069e0, + .data_addr = 0x08006a00, .data_len = 0x0, .data_index = 0x0, .data = bnx2_RXP_b09FwData, - .sbss_addr = 0x080069e0, - .sbss_len = 0x2c, + .sbss_addr = 0x08006a00, + .sbss_len = 0x20, .sbss_index = 0x0, .sbss = bnx2_RXP_b09FwSbss, - .bss_addr = 0x08006a10, + .bss_addr = 0x08006a20, .bss_len = 0x13dc, .bss_index = 0x0, .bss = bnx2_RXP_b09FwBss, - .rodata_addr = 0x08006740, + .rodata_addr = 0x08006768, .rodata_len = 0x278, .rodata_index = 0x0, .rodata = bnx2_RXP_b09FwRodata, }; static u8 bnx2_TPAT_b09FwText[] = { - 0x1f, 0x8b, 0x08, 0x08, 0xdb, 0xfd, 0x2f, 0x45, 0x00, 0x03, 0x74, 0x65, - 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xc5, 0x58, 0x5d, 0x6c, - 0x1c, 0x57, 0x15, 0x3e, 0xf3, 0xbb, 0x13, 0x77, 0xed, 0xbd, 0x49, 0x97, - 0x6a, 0x13, 0xb9, 0x74, 0xc6, 0x1e, 0x3b, 0x8b, 0x1c, 0x35, 0x93, 0xb0, - 0x24, 0x16, 0x5a, 0xd1, 0xc9, 0xcc, 0xae, 0x6b, 0xe5, 0x29, 0x86, 0xbc, - 0xf1, 0xb2, 0xac, 0xed, 0x46, 0x54, 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0x6f, 0xc8, 0xf4, 0xde, 0xc5, 0x11, 0xd1, 0xd6, 0xdc, 0x37, 0x30, + 0x37, 0xdb, 0xc4, 0x31, 0xca, 0xf9, 0x72, 0x5e, 0x5b, 0x80, 0x8f, 0x8e, + 0xac, 0x6b, 0xe0, 0x35, 0xce, 0x97, 0x23, 0xd9, 0xfd, 0x12, 0xf6, 0x07, + 0xeb, 0xbf, 0x74, 0x47, 0xad, 0x99, 0xd7, 0x94, 0xe9, 0xdd, 0x69, 0x3c, + 0xc3, 0xf3, 0x13, 0x6c, 0x99, 0x98, 0xba, 0xa0, 0xce, 0x3d, 0xd3, 0xa8, + 0xf1, 0xb8, 0x95, 0xa8, 0x83, 0xf8, 0xae, 0x8b, 0x6b, 0x27, 0x89, 0xf8, + 0x4f, 0x9f, 0x63, 0x3e, 0x13, 0xcd, 0xb0, 0x0e, 0x3e, 0x1b, 0x71, 0xfc, + 0xfc, 0x1b, 0x2f, 0xf3, 0x0a, 0xbd, 0x68, 0x18, 0x00, 0x00, 0x00 }; + +static const u32 bnx2_TPAT_b09FwData[(0x0/4) + 1] = { 0x0 }; +static const u32 bnx2_TPAT_b09FwRodata[(0x0/4) + 1] = { 0x0 }; +static const u32 bnx2_TPAT_b09FwBss[(0x850/4) + 1] = { 0x0 }; +static const u32 bnx2_TPAT_b09FwSbss[(0x2c/4) + 1] = { 0x0 }; static struct fw_info bnx2_tpat_fw_09 = { - .ver_major = 0x1, - .ver_minor = 0x0, - .ver_fix = 0x0, + .ver_major = 0x3, + .ver_minor = 0x4, + .ver_fix = 0x3, .start_addr = 0x08000860, .text_addr = 0x08000800, - .text_len = 0x1480, + .text_len = 0x1864, .text_index = 0x0, .gz_text = bnx2_TPAT_b09FwText, .gz_text_len = sizeof(bnx2_TPAT_b09FwText), - .data_addr = 0x08001ca0, + .data_addr = 0x08002080, .data_len = 0x0, .data_index = 0x0, .data = bnx2_TPAT_b09FwData, - .sbss_addr = 0x08001ca0, - .sbss_len = 0x34, + .sbss_addr = 0x08002088, + .sbss_len = 0x2c, .sbss_index = 0x0, .sbss = bnx2_TPAT_b09FwSbss, - .bss_addr = 0x08001ce0, - .bss_len = 0x250, + .bss_addr = 0x080020c0, + .bss_len = 0x850, .bss_index = 0x0, .bss = bnx2_TPAT_b09FwBss, @@ -3308,732 +3279,769 @@ static struct fw_info bnx2_tpat_fw_09 = { }; static u8 bnx2_TXP_b09FwText[] = { - 0x1f, 0x8b, 0x08, 0x08, 0x51, 0xfe, 0x2f, 0x45, 0x00, 0x03, 0x74, 0x65, - 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xcd, 0x7b, 0x7f, 0x70, - 0x1b, 0xe7, 0x99, 0xde, 0xbb, 0x0b, 0x80, 0x04, 0x29, 0x8a, 0x5a, 0x31, - 0x30, 0x83, 0x38, 0xb4, 0x8d, 0x15, 0x17, 0x34, 0x6d, 0xf2, 0x1c, 0x58, - 0xe5, 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0x04, 0xbf, 0xd7, 0x8d, 0xfa, - 0x39, 0x8e, 0xef, 0x95, 0xf0, 0xb7, 0xa7, 0x8c, 0x01, 0xa8, 0x6b, 0x66, - 0x0a, 0x58, 0xaf, 0xd5, 0xf2, 0xfa, 0xd9, 0x2d, 0xd8, 0x7d, 0x84, 0xbf, - 0x65, 0xc0, 0xdf, 0x23, 0xb0, 0x13, 0xf8, 0xc1, 0xe6, 0x38, 0xaf, 0x59, - 0x4b, 0x04, 0xd7, 0x4c, 0x58, 0xff, 0x1b, 0xed, 0xcc, 0xfa, 0xa1, 0x98, - 0x41, 0x00, 0x00, 0x00 }; -static u32 bnx2_TXP_b09FwData[(0xd0/4) + 1] = { + 0x1f, 0x8b, 0x08, 0x00, 0x0e, 0x34, 0xe7, 0x45, 0x00, 0x03, 0xcd, 0x7c, + 0x6f, 0x70, 0x5b, 0xd7, 0x95, 0xdf, 0x79, 0xef, 0x81, 0x24, 0x48, 0xd1, + 0xd4, 0x13, 0x17, 0x56, 0x60, 0x87, 0x71, 0x00, 0xf1, 0x81, 0x66, 0x42, + 0xae, 0x04, 0x2b, 0x4c, 0xc2, 0x6d, 0xd1, 0xf8, 0x05, 0x00, 0x29, 0x48, + 0xd1, 0x6c, 0x68, 0x95, 0x49, 0x94, 0x54, 0xe3, 0x62, 0x41, 0x52, 0xf1, + 0xb6, 0xce, 0x54, 0x9b, 0x78, 0x5a, 0x4d, 0xeb, 0xad, 0x11, 0x90, 0xfa, + 0xe7, 0x85, 0x04, 0xda, 0x62, 0x44, 0x7f, 0xc8, 0x07, 0x18, 0x80, 0x24, + 0x6f, 0xf2, 0x44, 0x28, 0x9b, 0x7f, 0xfd, 0xd0, 0xac, 0x50, 0x4a, 0xd6, + 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0x65, 0x82, 0xef, 0x94, 0xe3, 0xfa, + 0x11, 0xb9, 0xb2, 0xa0, 0xf6, 0xac, 0xbc, 0xbd, 0x21, 0xee, 0xf9, 0xa8, + 0xfd, 0x6f, 0xf8, 0xb5, 0x49, 0xe5, 0xd7, 0x97, 0x17, 0xd4, 0x3d, 0x17, + 0x2b, 0x39, 0x13, 0xf0, 0xfb, 0xc8, 0x25, 0xac, 0x07, 0xa4, 0x80, 0x9c, + 0xfb, 0xac, 0x75, 0x78, 0x0b, 0x71, 0x0e, 0x69, 0x2d, 0x83, 0xd6, 0xe5, + 0x05, 0xd9, 0xc2, 0x33, 0x25, 0x65, 0xb5, 0xcf, 0xe6, 0xd6, 0xc5, 0xa7, + 0xc5, 0xff, 0x7f, 0x1d, 0x41, 0x2f, 0x16, 0xf2, 0x5c, 0x0b, 0xdf, 0x73, + 0xa6, 0xaf, 0x40, 0x1e, 0x34, 0xc1, 0x7d, 0x9c, 0x66, 0xd3, 0xad, 0x9b, + 0x37, 0xb1, 0x2e, 0xda, 0xf8, 0x0e, 0x05, 0xfe, 0x0e, 0xc3, 0x7e, 0xb0, + 0x4e, 0x56, 0xdb, 0x79, 0xcd, 0xdc, 0xc3, 0xbf, 0x66, 0x60, 0xfb, 0x3f, + 0xe8, 0xf3, 0x49, 0x14, 0x38, 0x46, 0x00, 0x00, 0x00 }; + +static const u32 bnx2_TXP_b09FwData[(0xd0/4) + 1] = { 0x00000000, 0x00000014, 0x00000014, 0x00000014, 0x00000014, 0x00000010, 0x00000030, 0x00000030, 0x00000000, 0x00000000, 0x00000000, 0x00000010, 0x00008000, 0x00000000, 0x00000000, 0x00000000, 0x00008002, 0x00000000, @@ -4043,42 +4051,42 @@ static u32 bnx2_TXP_b09FwData[(0xd0/4) + 1] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; -static u32 bnx2_TXP_b09FwRodata[(0x30/4) + 1] = { - 0x08003be8, 0x08003c14, 0x08003c5c, 0x08003c5c, 0x08003ae8, 0x08003b14, - 0x08003b14, 0x08003c5c, 0x08003c5c, 0x08003c5c, 0x08003b7c, 0x00000000, +static const u32 bnx2_TXP_b09FwRodata[(0x30/4) + 1] = { + 0x08004060, 0x0800408c, 0x080040d4, 0x080040d4, 0x08003f60, 0x08003f8c, + 0x08003f8c, 0x080040d4, 0x080040d4, 0x080040d4, 0x08003ff4, 0x00000000, 0x00000000 }; -static u32 bnx2_TXP_b09FwBss[(0xa20/4) + 1] = { 0x0 }; -static u32 bnx2_TXP_b09FwSbss[(0x80/4) + 1] = { 0x0 }; +static const u32 bnx2_TXP_b09FwBss[(0xa20/4) + 1] = { 0x0 }; +static const u32 bnx2_TXP_b09FwSbss[(0x8c/4) + 1] = { 0x0 }; static struct fw_info bnx2_txp_fw_09 = { - .ver_major = 0x1, - .ver_minor = 0x0, - .ver_fix = 0x0, + .ver_major = 0x3, + .ver_minor = 0x4, + .ver_fix = 0x3, .start_addr = 0x08000060, .text_addr = 0x08000000, - .text_len = 0x4194, + .text_len = 0x4634, .text_index = 0x0, .gz_text = bnx2_TXP_b09FwText, .gz_text_len = sizeof(bnx2_TXP_b09FwText), - .data_addr = 0x080041e0, + .data_addr = 0x08004680, .data_len = 0xd0, .data_index = 0x0, .data = bnx2_TXP_b09FwData, - .sbss_addr = 0x080042b0, - .sbss_len = 0x80, + .sbss_addr = 0x08004750, + .sbss_len = 0x8c, .sbss_index = 0x0, .sbss = bnx2_TXP_b09FwSbss, - .bss_addr = 0x08004330, + .bss_addr = 0x080047e0, .bss_len = 0xa20, .bss_index = 0x0, .bss = bnx2_TXP_b09FwBss, - .rodata_addr = 0x08004198, + .rodata_addr = 0x08004638, .rodata_len = 0x30, .rodata_index = 0x0, .rodata = bnx2_TXP_b09FwRodata, diff --git a/drivers/net/cxgb3/version.h b/drivers/net/cxgb3/version.h index 042e27e291cd..b112317f033e 100644 --- a/drivers/net/cxgb3/version.h +++ b/drivers/net/cxgb3/version.h @@ -38,7 +38,7 @@ #define DRV_VERSION "1.0-ko" /* Firmware version */ -#define FW_VERSION_MAJOR 3 -#define FW_VERSION_MINOR 3 +#define FW_VERSION_MAJOR 4 +#define FW_VERSION_MINOR 0 #define FW_VERSION_MICRO 0 #endif /* __CHELSIO_VERSION_H */ diff --git a/drivers/net/fec_8xx/fec_main.c b/drivers/net/fec_8xx/fec_main.c index e824d5d231af..88efe9731bab 100644 --- a/drivers/net/fec_8xx/fec_main.c +++ b/drivers/net/fec_8xx/fec_main.c @@ -19,7 +19,6 @@ #include <linux/ioport.h> #include <linux/slab.h> #include <linux/interrupt.h> -#include <linux/pci.h> #include <linux/init.h> #include <linux/delay.h> #include <linux/netdevice.h> diff --git a/drivers/net/fec_8xx/fec_mii.c b/drivers/net/fec_8xx/fec_mii.c index e79700abf7b6..b3fa0d6a159c 100644 --- a/drivers/net/fec_8xx/fec_mii.c +++ b/drivers/net/fec_8xx/fec_mii.c @@ -19,7 +19,6 @@ #include <linux/ioport.h> #include <linux/slab.h> #include <linux/interrupt.h> -#include <linux/pci.h> #include <linux/init.h> #include <linux/delay.h> #include <linux/netdevice.h> diff --git a/drivers/net/fs_enet/fs_enet-main.c b/drivers/net/fs_enet/fs_enet-main.c index e2ddd617493a..a4a2a0ea43d3 100644 --- a/drivers/net/fs_enet/fs_enet-main.c +++ b/drivers/net/fs_enet/fs_enet-main.c @@ -24,7 +24,6 @@ #include <linux/ioport.h> #include <linux/slab.h> #include <linux/interrupt.h> -#include <linux/pci.h> #include <linux/init.h> #include <linux/delay.h> #include <linux/netdevice.h> diff --git a/drivers/net/fs_enet/mac-fcc.c b/drivers/net/fs_enet/mac-fcc.c index 8545e84fc9a0..5603121132cd 100644 --- a/drivers/net/fs_enet/mac-fcc.c +++ b/drivers/net/fs_enet/mac-fcc.c @@ -21,7 +21,6 @@ #include <linux/ioport.h> #include <linux/slab.h> #include <linux/interrupt.h> -#include <linux/pci.h> #include <linux/init.h> #include <linux/delay.h> #include <linux/netdevice.h> diff --git a/drivers/net/fs_enet/mac-fec.c b/drivers/net/fs_enet/mac-fec.c index cdcfb96f360f..04b4f80a1cde 100644 --- a/drivers/net/fs_enet/mac-fec.c +++ b/drivers/net/fs_enet/mac-fec.c @@ -21,7 +21,6 @@ #include <linux/ioport.h> #include <linux/slab.h> #include <linux/interrupt.h> -#include <linux/pci.h> #include <linux/init.h> #include <linux/delay.h> #include <linux/netdevice.h> diff --git a/drivers/net/fs_enet/mac-scc.c b/drivers/net/fs_enet/mac-scc.c index 65925b5a224f..d0f28981b55a 100644 --- a/drivers/net/fs_enet/mac-scc.c +++ b/drivers/net/fs_enet/mac-scc.c @@ -21,7 +21,6 @@ #include <linux/ioport.h> #include <linux/slab.h> #include <linux/interrupt.h> -#include <linux/pci.h> #include <linux/init.h> #include <linux/delay.h> #include <linux/netdevice.h> diff --git a/drivers/net/fs_enet/mii-bitbang.c b/drivers/net/fs_enet/mii-bitbang.c index f91447837fd4..d3840108ffbd 100644 --- a/drivers/net/fs_enet/mii-bitbang.c +++ b/drivers/net/fs_enet/mii-bitbang.c @@ -22,7 +22,6 @@ #include <linux/ioport.h> #include <linux/slab.h> #include <linux/interrupt.h> -#include <linux/pci.h> #include <linux/init.h> #include <linux/delay.h> #include <linux/netdevice.h> diff --git a/drivers/net/fs_enet/mii-fec.c b/drivers/net/fs_enet/mii-fec.c index 235b177fb9ac..0a563a83016f 100644 --- a/drivers/net/fs_enet/mii-fec.c +++ b/drivers/net/fs_enet/mii-fec.c @@ -21,7 +21,6 @@ #include <linux/ioport.h> #include <linux/slab.h> #include <linux/interrupt.h> -#include <linux/pci.h> #include <linux/init.h> #include <linux/delay.h> #include <linux/netdevice.h> diff --git a/drivers/net/ibm_emac/ibm_emac_core.c b/drivers/net/ibm_emac/ibm_emac_core.c index 3d82d46f4998..50035ebd4f52 100644 --- a/drivers/net/ibm_emac/ibm_emac_core.c +++ b/drivers/net/ibm_emac/ibm_emac_core.c @@ -27,7 +27,6 @@ #include <linux/delay.h> #include <linux/init.h> #include <linux/types.h> -#include <linux/pci.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/skbuff.h> diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c index fb196fd91855..55ff0fbe525a 100644 --- a/drivers/net/irda/pxaficp_ir.c +++ b/drivers/net/irda/pxaficp_ir.c @@ -134,7 +134,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed) DCSR(si->rxdma) &= ~DCSR_RUN; /* disable FICP */ ICCR0 = 0; - pxa_set_cken(CKEN13_FICP, 0); + pxa_set_cken(CKEN_FICP, 0); /* set board transceiver to SIR mode */ si->pdata->transceiver_mode(si->dev, IR_SIRMODE); @@ -144,7 +144,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed) pxa_gpio_mode(GPIO47_STTXD_MD); /* enable the STUART clock */ - pxa_set_cken(CKEN5_STUART, 1); + pxa_set_cken(CKEN_STUART, 1); } /* disable STUART first */ @@ -169,7 +169,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed) /* disable STUART */ STIER = 0; STISR = 0; - pxa_set_cken(CKEN5_STUART, 0); + pxa_set_cken(CKEN_STUART, 0); /* disable FICP first */ ICCR0 = 0; @@ -182,7 +182,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed) pxa_gpio_mode(GPIO47_ICPTXD_MD); /* enable the FICP clock */ - pxa_set_cken(CKEN13_FICP, 1); + pxa_set_cken(CKEN_FICP, 1); si->speed = speed; pxa_irda_fir_dma_rx_start(si); @@ -593,7 +593,7 @@ static void pxa_irda_shutdown(struct pxa_irda *si) /* disable STUART SIR mode */ STISR = 0; /* disable the STUART clock */ - pxa_set_cken(CKEN5_STUART, 0); + pxa_set_cken(CKEN_STUART, 0); /* disable DMA */ DCSR(si->txdma) &= ~DCSR_RUN; @@ -601,7 +601,7 @@ static void pxa_irda_shutdown(struct pxa_irda *si) /* disable FICP */ ICCR0 = 0; /* disable the FICP clock */ - pxa_set_cken(CKEN13_FICP, 0); + pxa_set_cken(CKEN_FICP, 0); DRCMR17 = 0; DRCMR18 = 0; diff --git a/drivers/net/ixgb/ixgb_osdep.h b/drivers/net/ixgb/ixgb_osdep.h index 8434d752fd81..9e04a6b3ae0d 100644 --- a/drivers/net/ixgb/ixgb_osdep.h +++ b/drivers/net/ixgb/ixgb_osdep.h @@ -34,7 +34,6 @@ #define _IXGB_OSDEP_H_ #include <linux/types.h> -#include <linux/pci.h> #include <linux/delay.h> #include <asm/io.h> #include <linux/interrupt.h> diff --git a/drivers/net/jazzsonic.c b/drivers/net/jazzsonic.c index d34afb52ea7f..75f6f441e876 100644 --- a/drivers/net/jazzsonic.c +++ b/drivers/net/jazzsonic.c @@ -88,6 +88,23 @@ static unsigned short known_revisions[] = 0xffff /* end of list */ }; +static int jazzsonic_open(struct net_device* dev) +{ + if (request_irq(dev->irq, &sonic_interrupt, IRQF_DISABLED, "sonic", dev)) { + printk(KERN_ERR "%s: unable to get IRQ %d.\n", dev->name, dev->irq); + return -EAGAIN; + } + return sonic_open(dev); +} + +static int jazzsonic_close(struct net_device* dev) +{ + int err; + err = sonic_close(dev); + free_irq(dev->irq, dev); + return err; +} + static int __init sonic_probe1(struct net_device *dev) { static unsigned version_printed; @@ -169,8 +186,8 @@ static int __init sonic_probe1(struct net_device *dev) lp->rra_laddr = lp->rda_laddr + (SIZEOF_SONIC_RD * SONIC_NUM_RDS * SONIC_BUS_SCALE(lp->dma_bitmode)); - dev->open = sonic_open; - dev->stop = sonic_close; + dev->open = jazzsonic_open; + dev->stop = jazzsonic_close; dev->hard_start_xmit = sonic_send_packet; dev->get_stats = sonic_get_stats; dev->set_multicast_list = &sonic_multicast_list; @@ -260,8 +277,6 @@ MODULE_DESCRIPTION("Jazz SONIC ethernet driver"); module_param(sonic_debug, int, 0); MODULE_PARM_DESC(sonic_debug, "jazzsonic debug level (1-4)"); -#define SONIC_IRQ_FLAG IRQF_DISABLED - #include "sonic.c" static int __devexit jazz_sonic_device_remove (struct platform_device *pdev) @@ -269,11 +284,11 @@ static int __devexit jazz_sonic_device_remove (struct platform_device *pdev) struct net_device *dev = platform_get_drvdata(pdev); struct sonic_local* lp = netdev_priv(dev); - unregister_netdev (dev); + unregister_netdev(dev); dma_free_coherent(lp->device, SIZEOF_SONIC_DESC * SONIC_BUS_SCALE(lp->dma_bitmode), lp->descriptors, lp->descriptors_laddr); release_region (dev->base_addr, SONIC_MEM_SIZE); - free_netdev (dev); + free_netdev(dev); return 0; } diff --git a/drivers/net/lasi_82596.c b/drivers/net/lasi_82596.c index 0edcd125fd61..6b49fc4bd1a1 100644 --- a/drivers/net/lasi_82596.c +++ b/drivers/net/lasi_82596.c @@ -81,7 +81,6 @@ #include <linux/etherdevice.h> #include <linux/skbuff.h> #include <linux/init.h> -#include <linux/pci.h> #include <linux/types.h> #include <linux/bitops.h> diff --git a/drivers/net/mac8390.c b/drivers/net/mac8390.c index a12bb64e3694..90b0c3ed4bb6 100644 --- a/drivers/net/mac8390.c +++ b/drivers/net/mac8390.c @@ -14,6 +14,8 @@ /* 2001-05-15: support for Cabletron ported from old daynaport driver * and fixed access to Sonic Sys card which masquerades as a Farallon * by rayk@knightsmanor.org */ +/* 2002-12-30: Try to support more cards, some clues from NetBSD driver */ +/* 2003-12-26: Make sure Asante cards always work. */ #include <linux/module.h> #include <linux/kernel.h> @@ -61,25 +63,21 @@ static char version[] = #define DAYNA_8390_BASE 0x80000 #define DAYNA_8390_MEM 0x00000 -#define KINETICS_8390_BASE 0x80000 -#define KINETICS_8390_MEM 0x00000 - #define CABLETRON_8390_BASE 0x90000 #define CABLETRON_8390_MEM 0x00000 +#define INTERLAN_8390_BASE 0xE0000 +#define INTERLAN_8390_MEM 0xD0000 + enum mac8390_type { MAC8390_NONE = -1, MAC8390_APPLE, MAC8390_ASANTE, - MAC8390_FARALLON, /* Apple, Asante, and Farallon are all compatible */ + MAC8390_FARALLON, MAC8390_CABLETRON, MAC8390_DAYNA, MAC8390_INTERLAN, MAC8390_KINETICS, - MAC8390_FOCUS, - MAC8390_SONICSYS, - MAC8390_DAYNA2, - MAC8390_DAYNA3, }; static const char * cardname[] = { @@ -90,10 +88,6 @@ static const char * cardname[] = { "dayna", "interlan", "kinetics", - "focus", - "sonic systems", - "dayna2", - "dayna_lc", }; static int word16[] = { @@ -104,10 +98,6 @@ static int word16[] = { 0, /* dayna */ 1, /* interlan */ 0, /* kinetics */ - 1, /* focus (??) */ - 1, /* sonic systems */ - 1, /* dayna2 */ - 1, /* dayna-lc */ }; /* on which cards do we use NuBus resources? */ @@ -119,10 +109,12 @@ static int useresources[] = { 0, /* dayna */ 0, /* interlan */ 0, /* kinetics */ - 0, /* focus (??) */ - 1, /* sonic systems */ - 1, /* dayna2 */ - 1, /* dayna-lc */ +}; + +enum mac8390_access { + ACCESS_UNKNOWN = 0, + ACCESS_32, + ACCESS_16, }; extern enum mac8390_type mac8390_ident(struct nubus_dev * dev); @@ -134,8 +126,9 @@ static int mac8390_initdev(struct net_device * dev, struct nubus_dev * ndev, static int mac8390_open(struct net_device * dev); static int mac8390_close(struct net_device * dev); static void mac8390_no_reset(struct net_device *dev); +static void interlan_reset(struct net_device *dev); -/* Sane (32-bit chunk memory read/write) - Apple/Asante/Farallon do this*/ +/* Sane (32-bit chunk memory read/write) - Some Farallon and Apple do this*/ static void sane_get_8390_hdr(struct net_device *dev, struct e8390_pkt_hdr *hdr, int ring_page); static void sane_block_input(struct net_device * dev, int count, @@ -172,23 +165,93 @@ static void word_memcpy_fromcard(void *tp, const void *fp, int count); enum mac8390_type __init mac8390_ident(struct nubus_dev * dev) { - if (dev->dr_sw == NUBUS_DRSW_ASANTE) - return MAC8390_ASANTE; - if (dev->dr_sw == NUBUS_DRSW_FARALLON) - return MAC8390_FARALLON; - if (dev->dr_sw == NUBUS_DRSW_KINETICS) - return MAC8390_KINETICS; - if (dev->dr_sw == NUBUS_DRSW_DAYNA) - return MAC8390_DAYNA; - if (dev->dr_sw == NUBUS_DRSW_DAYNA2) - return MAC8390_DAYNA2; - if (dev->dr_sw == NUBUS_DRSW_DAYNA_LC) - return MAC8390_DAYNA3; - if (dev->dr_hw == NUBUS_DRHW_CABLETRON) - return MAC8390_CABLETRON; + switch (dev->dr_sw) { + case NUBUS_DRSW_3COM: + switch (dev->dr_hw) { + case NUBUS_DRHW_APPLE_SONIC_NB: + case NUBUS_DRHW_APPLE_SONIC_LC: + case NUBUS_DRHW_SONNET: + return MAC8390_NONE; + break; + default: + return MAC8390_APPLE; + break; + } + break; + + case NUBUS_DRSW_APPLE: + switch (dev->dr_hw) { + case NUBUS_DRHW_ASANTE_LC: + return MAC8390_NONE; + break; + case NUBUS_DRHW_CABLETRON: + return MAC8390_CABLETRON; + break; + default: + return MAC8390_APPLE; + break; + } + break; + + case NUBUS_DRSW_ASANTE: + return MAC8390_ASANTE; + break; + + case NUBUS_DRSW_TECHWORKS: + case NUBUS_DRSW_DAYNA2: + case NUBUS_DRSW_DAYNA_LC: + if (dev->dr_hw == NUBUS_DRHW_CABLETRON) + return MAC8390_CABLETRON; + else + return MAC8390_APPLE; + break; + + case NUBUS_DRSW_FARALLON: + return MAC8390_FARALLON; + break; + + case NUBUS_DRSW_KINETICS: + switch (dev->dr_hw) { + case NUBUS_DRHW_INTERLAN: + return MAC8390_INTERLAN; + break; + default: + return MAC8390_KINETICS; + break; + } + break; + + case NUBUS_DRSW_DAYNA: + // These correspond to Dayna Sonic cards + // which use the macsonic driver + if (dev->dr_hw == NUBUS_DRHW_SMC9194 || + dev->dr_hw == NUBUS_DRHW_INTERLAN ) + return MAC8390_NONE; + else + return MAC8390_DAYNA; + break; + } return MAC8390_NONE; } +enum mac8390_access __init mac8390_testio(volatile unsigned long membase) +{ + unsigned long outdata = 0xA5A0B5B0; + unsigned long indata = 0x00000000; + /* Try writing 32 bits */ + memcpy((char *)membase, (char *)&outdata, 4); + /* Now compare them */ + if (memcmp((char *)&outdata, (char *)membase, 4) == 0) + return ACCESS_32; + /* Write 16 bit output */ + word_memcpy_tocard((char *)membase, (char *)&outdata, 4); + /* Now read it back */ + word_memcpy_fromcard((char *)&indata, (char *)membase, 4); + if (outdata == indata) + return ACCESS_16; + return ACCESS_UNKNOWN; +} + int __init mac8390_memsize(unsigned long membase) { unsigned long flags; @@ -287,14 +350,6 @@ struct net_device * __init mac8390_probe(int unit) continue; } else { nubus_get_rsrc_mem(dev->dev_addr, &ent, 6); - /* Some Sonic Sys cards masquerade as Farallon */ - if (cardtype == MAC8390_FARALLON && - dev->dev_addr[0] == 0x0 && - dev->dev_addr[1] == 0x40 && - dev->dev_addr[2] == 0x10) { - /* This is really Sonic Sys card */ - cardtype = MAC8390_SONICSYS; - } } if (useresources[cardtype] == 1) { @@ -334,6 +389,17 @@ struct net_device * __init mac8390_probe(int unit) dev->mem_start + mac8390_memsize(dev->mem_start); break; + case MAC8390_INTERLAN: + dev->base_addr = + (int)(ndev->board->slot_addr + + INTERLAN_8390_BASE); + dev->mem_start = + (int)(ndev->board->slot_addr + + INTERLAN_8390_MEM); + dev->mem_end = + dev->mem_start + + mac8390_memsize(dev->mem_start); + break; case MAC8390_CABLETRON: dev->base_addr = (int)(ndev->board->slot_addr + @@ -356,8 +422,8 @@ struct net_device * __init mac8390_probe(int unit) default: printk(KERN_ERR "Card type %s is" - " unsupported, sorry\n", - cardname[cardtype]); + " unsupported, sorry\n", + ndev->board->name); continue; } } @@ -438,7 +504,7 @@ static int __init mac8390_initdev(struct net_device * dev, struct nubus_dev * nd 24, 26, 28, 30 }; - int access_bitmode; + int access_bitmode = 0; /* Now fill in our stuff */ dev->open = &mac8390_open; @@ -468,29 +534,47 @@ static int __init mac8390_initdev(struct net_device * dev, struct nubus_dev * nd /* Fill in model-specific information and functions */ switch(type) { - case MAC8390_SONICSYS: - /* 16 bit card, register map is reversed */ - ei_status.reset_8390 = &mac8390_no_reset; - ei_status.block_input = &slow_sane_block_input; - ei_status.block_output = &slow_sane_block_output; - ei_status.get_8390_hdr = &slow_sane_get_8390_hdr; - ei_status.reg_offset = back4_offsets; - access_bitmode = 0; - break; case MAC8390_FARALLON: case MAC8390_APPLE: + switch(mac8390_testio(dev->mem_start)) { + case ACCESS_UNKNOWN: + printk("Don't know how to access card memory!\n"); + return -ENODEV; + break; + + case ACCESS_16: + /* 16 bit card, register map is reversed */ + ei_status.reset_8390 = &mac8390_no_reset; + ei_status.block_input = &slow_sane_block_input; + ei_status.block_output = &slow_sane_block_output; + ei_status.get_8390_hdr = &slow_sane_get_8390_hdr; + ei_status.reg_offset = back4_offsets; + break; + + case ACCESS_32: + /* 32 bit card, register map is reversed */ + ei_status.reset_8390 = &mac8390_no_reset; + ei_status.block_input = &sane_block_input; + ei_status.block_output = &sane_block_output; + ei_status.get_8390_hdr = &sane_get_8390_hdr; + ei_status.reg_offset = back4_offsets; + access_bitmode = 1; + break; + } + break; + case MAC8390_ASANTE: - case MAC8390_DAYNA2: - case MAC8390_DAYNA3: - /* 32 bit card, register map is reversed */ - /* sane */ + /* Some Asante cards pass the 32 bit test + * but overwrite system memory when run at 32 bit. + * so we run them all at 16 bit. + */ ei_status.reset_8390 = &mac8390_no_reset; - ei_status.block_input = &sane_block_input; - ei_status.block_output = &sane_block_output; - ei_status.get_8390_hdr = &sane_get_8390_hdr; + ei_status.block_input = &slow_sane_block_input; + ei_status.block_output = &slow_sane_block_output; + ei_status.get_8390_hdr = &slow_sane_get_8390_hdr; ei_status.reg_offset = back4_offsets; - access_bitmode = 1; break; + case MAC8390_CABLETRON: /* 16 bit card, register map is short forward */ ei_status.reset_8390 = &mac8390_no_reset; @@ -498,21 +582,30 @@ static int __init mac8390_initdev(struct net_device * dev, struct nubus_dev * nd ei_status.block_output = &slow_sane_block_output; ei_status.get_8390_hdr = &slow_sane_get_8390_hdr; ei_status.reg_offset = fwrd2_offsets; - access_bitmode = 0; break; + case MAC8390_DAYNA: case MAC8390_KINETICS: - /* 16 bit memory */ + /* 16 bit memory, register map is forward */ /* dayna and similar */ ei_status.reset_8390 = &mac8390_no_reset; ei_status.block_input = &dayna_block_input; ei_status.block_output = &dayna_block_output; ei_status.get_8390_hdr = &dayna_get_8390_hdr; ei_status.reg_offset = fwrd4_offsets; - access_bitmode = 0; break; + + case MAC8390_INTERLAN: + /* 16 bit memory, register map is forward */ + ei_status.reset_8390 = &interlan_reset; + ei_status.block_input = &slow_sane_block_input; + ei_status.block_output = &slow_sane_block_output; + ei_status.get_8390_hdr = &slow_sane_get_8390_hdr; + ei_status.reg_offset = fwrd4_offsets; + break; + default: - printk(KERN_ERR "Card type %s is unsupported, sorry\n", cardname[type]); + printk(KERN_ERR "Card type %s is unsupported, sorry\n", ndev->board->name); return -ENODEV; } @@ -530,9 +623,9 @@ static int __init mac8390_initdev(struct net_device * dev, struct nubus_dev * nd printk(":"); } } - printk(" IRQ %d, shared memory at %#lx-%#lx, %d-bit access.\n", - dev->irq, dev->mem_start, dev->mem_end-1, - access_bitmode?32:16); + printk(" IRQ %d, %d KB shared memory at %#lx, %d-bit access.\n", + dev->irq, (int)((dev->mem_end - dev->mem_start)/0x1000) * 4, + dev->mem_start, access_bitmode?32:16); return 0; } @@ -561,6 +654,18 @@ static void mac8390_no_reset(struct net_device *dev) return; } +static void interlan_reset(struct net_device *dev) +{ + unsigned char *target=nubus_slot_addr(IRQ2SLOT(dev->irq)); + if (ei_debug > 1) + printk("Need to reset the NS8390 t=%lu...", jiffies); + ei_status.txing = 0; + target[0xC0000] = 0; + if (ei_debug > 1) + printk("reset complete\n"); + return; +} + /* dayna_memcpy_fromio/dayna_memcpy_toio */ /* directly from daynaport.c by Alan Cox */ static void dayna_memcpy_fromcard(struct net_device *dev, void *to, int from, int count) diff --git a/drivers/net/mac89x0.c b/drivers/net/mac89x0.c index 90e695d53266..26a3b45a4a34 100644 --- a/drivers/net/mac89x0.c +++ b/drivers/net/mac89x0.c @@ -128,7 +128,7 @@ struct net_local { extern void reset_chip(struct net_device *dev); #endif static int net_open(struct net_device *dev); -static int net_send_packet(struct sk_buff *skb, struct net_device *dev); +static int net_send_packet(struct sk_buff *skb, struct net_device *dev); static irqreturn_t net_interrupt(int irq, void *dev_id); static void set_multicast_list(struct net_device *dev); static void net_rx(struct net_device *dev); @@ -374,56 +374,39 @@ net_open(struct net_device *dev) static int net_send_packet(struct sk_buff *skb, struct net_device *dev) { - if (dev->tbusy) { - /* If we get here, some higher level has decided we are broken. - There should really be a "kick me" function call instead. */ - int tickssofar = jiffies - dev->trans_start; - if (tickssofar < 5) - return 1; - if (net_debug > 0) printk("%s: transmit timed out, %s?\n", dev->name, - tx_done(dev) ? "IRQ conflict" : "network cable problem"); - /* Try to restart the adaptor. */ - dev->tbusy=0; - dev->trans_start = jiffies; - } - - /* Block a timer-based transmit from overlapping. This could better be - done with atomic_swap(1, dev->tbusy), but set_bit() works as well. */ - if (test_and_set_bit(0, (void*)&dev->tbusy) != 0) - printk("%s: Transmitter access conflict.\n", dev->name); - else { - struct net_local *lp = netdev_priv(dev); - unsigned long flags; - - if (net_debug > 3) - printk("%s: sent %d byte packet of type %x\n", - dev->name, skb->len, - (skb->data[ETH_ALEN+ETH_ALEN] << 8) - | skb->data[ETH_ALEN+ETH_ALEN+1]); - - /* keep the upload from being interrupted, since we - ask the chip to start transmitting before the - whole packet has been completely uploaded. */ - local_irq_save(flags); + struct net_local *lp = netdev_priv(dev); + unsigned long flags; - /* initiate a transmit sequence */ - writereg(dev, PP_TxCMD, lp->send_cmd); - writereg(dev, PP_TxLength, skb->len); + if (net_debug > 3) + printk("%s: sent %d byte packet of type %x\n", + dev->name, skb->len, + (skb->data[ETH_ALEN+ETH_ALEN] << 8) + | skb->data[ETH_ALEN+ETH_ALEN+1]); - /* Test to see if the chip has allocated memory for the packet */ - if ((readreg(dev, PP_BusST) & READY_FOR_TX_NOW) == 0) { - /* Gasp! It hasn't. But that shouldn't happen since - we're waiting for TxOk, so return 1 and requeue this packet. */ - local_irq_restore(flags); - return 1; - } + /* keep the upload from being interrupted, since we + ask the chip to start transmitting before the + whole packet has been completely uploaded. */ + local_irq_save(flags); + netif_stop_queue(dev); - /* Write the contents of the packet */ - memcpy_toio(dev->mem_start + PP_TxFrame, skb->data, skb->len+1); + /* initiate a transmit sequence */ + writereg(dev, PP_TxCMD, lp->send_cmd); + writereg(dev, PP_TxLength, skb->len); + /* Test to see if the chip has allocated memory for the packet */ + if ((readreg(dev, PP_BusST) & READY_FOR_TX_NOW) == 0) { + /* Gasp! It hasn't. But that shouldn't happen since + we're waiting for TxOk, so return 1 and requeue this packet. */ local_irq_restore(flags); - dev->trans_start = jiffies; + return 1; } + + /* Write the contents of the packet */ + skb_copy_from_linear_data(skb, (void *)(dev->mem_start + PP_TxFrame), + skb->len+1); + + local_irq_restore(flags); + dev->trans_start = jiffies; dev_kfree_skb (skb); return 0; @@ -441,9 +424,6 @@ static irqreturn_t net_interrupt(int irq, void *dev_id) printk ("net_interrupt(): irq %d for unknown device.\n", irq); return IRQ_NONE; } - if (dev->interrupt) - printk("%s: Re-entering the interrupt handler.\n", dev->name); - dev->interrupt = 1; ioaddr = dev->base_addr; lp = netdev_priv(dev); @@ -464,8 +444,7 @@ static irqreturn_t net_interrupt(int irq, void *dev_id) break; case ISQ_TRANSMITTER_EVENT: lp->stats.tx_packets++; - dev->tbusy = 0; - mark_bh(NET_BH); /* Inform upper layers. */ + netif_wake_queue(dev); if ((status & TX_OK) == 0) lp->stats.tx_errors++; if (status & TX_LOST_CRS) lp->stats.tx_carrier_errors++; if (status & TX_SQE_ERROR) lp->stats.tx_heartbeat_errors++; @@ -479,8 +458,7 @@ static irqreturn_t net_interrupt(int irq, void *dev_id) That shouldn't happen since we only ever load one packet. Shrug. Do the right thing anyway. */ - dev->tbusy = 0; - mark_bh(NET_BH); /* Inform upper layers. */ + netif_wake_queue(dev); } if (status & TX_UNDERRUN) { if (net_debug > 0) printk("%s: transmit underrun\n", dev->name); @@ -497,7 +475,6 @@ static irqreturn_t net_interrupt(int irq, void *dev_id) break; } } - dev->interrupt = 0; return IRQ_HANDLED; } @@ -531,7 +508,8 @@ net_rx(struct net_device *dev) } skb_put(skb, length); - memcpy_fromio(skb->data, dev->mem_start + PP_RxFrame, length); + skb_copy_to_linear_data(skb, (void *)(dev->mem_start + PP_RxFrame), + length); if (net_debug > 3)printk("%s: received %d byte packet of type %x\n", dev->name, length, @@ -610,8 +588,6 @@ static void set_multicast_list(struct net_device *dev) static int set_mac_address(struct net_device *dev, void *addr) { int i; - if (dev->start) - return -EBUSY; printk("%s: Setting MAC address to ", dev->name); for (i = 0; i < 6; i++) printk(" %2.2x", dev->dev_addr[i] = ((unsigned char *)addr)[i]); diff --git a/drivers/net/macmace.c b/drivers/net/macmace.c index 27911c07558d..fef3193121f9 100644 --- a/drivers/net/macmace.c +++ b/drivers/net/macmace.c @@ -12,6 +12,11 @@ * Copyright (C) 1998 Alan Cox <alan@redhat.com> * * Modified heavily by Joshua M. Thompson based on Dave Huang's NetBSD driver + * + * Copyright (C) 2007 Finn Thain + * + * Converted to DMA API, converted to unified driver model, + * sync'd some routines with mace.c and fixed various bugs. */ @@ -23,8 +28,9 @@ #include <linux/string.h> #include <linux/crc32.h> #include <linux/bitrev.h> +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> #include <asm/io.h> -#include <asm/pgtable.h> #include <asm/irq.h> #include <asm/macintosh.h> #include <asm/macints.h> @@ -32,13 +38,20 @@ #include <asm/page.h> #include "mace.h" -#define N_TX_RING 1 -#define N_RX_RING 8 -#define N_RX_PAGES ((N_RX_RING * 0x0800 + PAGE_SIZE - 1) / PAGE_SIZE) +static char mac_mace_string[] = "macmace"; +static struct platform_device *mac_mace_device; + +#define N_TX_BUFF_ORDER 0 +#define N_TX_RING (1 << N_TX_BUFF_ORDER) +#define N_RX_BUFF_ORDER 3 +#define N_RX_RING (1 << N_RX_BUFF_ORDER) + #define TX_TIMEOUT HZ -/* Bits in transmit DMA status */ -#define TX_DMA_ERR 0x80 +#define MACE_BUFF_SIZE 0x800 + +/* Chip rev needs workaround on HW & multicast addr change */ +#define BROKEN_ADDRCHG_REV 0x0941 /* The MACE is simply wired down on a Mac68K box */ @@ -47,40 +60,46 @@ struct mace_data { volatile struct mace *mace; - volatile unsigned char *tx_ring; - volatile unsigned char *tx_ring_phys; - volatile unsigned char *rx_ring; - volatile unsigned char *rx_ring_phys; + unsigned char *tx_ring; + dma_addr_t tx_ring_phys; + unsigned char *rx_ring; + dma_addr_t rx_ring_phys; int dma_intr; struct net_device_stats stats; int rx_slot, rx_tail; int tx_slot, tx_sloti, tx_count; + int chipid; + struct device *device; }; struct mace_frame { - u16 len; - u16 status; - u16 rntpc; - u16 rcvcc; - u32 pad1; - u32 pad2; + u8 rcvcnt; + u8 pad1; + u8 rcvsts; + u8 pad2; + u8 rntpc; + u8 pad3; + u8 rcvcc; + u8 pad4; + u32 pad5; + u32 pad6; u8 data[1]; /* And frame continues.. */ }; #define PRIV_BYTES sizeof(struct mace_data) -extern void psc_debug_dump(void); - static int mace_open(struct net_device *dev); static int mace_close(struct net_device *dev); static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev); static struct net_device_stats *mace_stats(struct net_device *dev); static void mace_set_multicast(struct net_device *dev); static int mace_set_address(struct net_device *dev, void *addr); +static void mace_reset(struct net_device *dev); static irqreturn_t mace_interrupt(int irq, void *dev_id); static irqreturn_t mace_dma_intr(int irq, void *dev_id); static void mace_tx_timeout(struct net_device *dev); +static void __mace_set_address(struct net_device *dev, void *addr); /* * Load a receive DMA channel with a base address and ring length @@ -88,7 +107,7 @@ static void mace_tx_timeout(struct net_device *dev); static void mace_load_rxdma_base(struct net_device *dev, int set) { - struct mace_data *mp = (struct mace_data *) dev->priv; + struct mace_data *mp = netdev_priv(dev); psc_write_word(PSC_ENETRD_CMD + set, 0x0100); psc_write_long(PSC_ENETRD_ADDR + set, (u32) mp->rx_ring_phys); @@ -103,7 +122,7 @@ static void mace_load_rxdma_base(struct net_device *dev, int set) static void mace_rxdma_reset(struct net_device *dev) { - struct mace_data *mp = (struct mace_data *) dev->priv; + struct mace_data *mp = netdev_priv(dev); volatile struct mace *mace = mp->mace; u8 maccc = mace->maccc; @@ -130,7 +149,7 @@ static void mace_rxdma_reset(struct net_device *dev) static void mace_txdma_reset(struct net_device *dev) { - struct mace_data *mp = (struct mace_data *) dev->priv; + struct mace_data *mp = netdev_priv(dev); volatile struct mace *mace = mp->mace; u8 maccc; @@ -168,7 +187,7 @@ static void mace_dma_off(struct net_device *dev) * model of Macintrash has a MACE (AV macintoshes) */ -struct net_device *mace_probe(int unit) +static int __devinit mace_probe(struct platform_device *pdev) { int j; struct mace_data *mp; @@ -179,24 +198,28 @@ struct net_device *mace_probe(int unit) int err; if (found || macintosh_config->ether_type != MAC_ETHER_MACE) - return ERR_PTR(-ENODEV); + return -ENODEV; found = 1; /* prevent 'finding' one on every device probe */ dev = alloc_etherdev(PRIV_BYTES); if (!dev) - return ERR_PTR(-ENOMEM); + return -ENOMEM; - if (unit >= 0) - sprintf(dev->name, "eth%d", unit); + mp = netdev_priv(dev); + + mp->device = &pdev->dev; + SET_NETDEV_DEV(dev, &pdev->dev); + SET_MODULE_OWNER(dev); - mp = (struct mace_data *) dev->priv; dev->base_addr = (u32)MACE_BASE; mp->mace = (volatile struct mace *) MACE_BASE; dev->irq = IRQ_MAC_MACE; mp->dma_intr = IRQ_MAC_MACE_DMA; + mp->chipid = mp->mace->chipid_hi << 8 | mp->mace->chipid_lo; + /* * The PROM contains 8 bytes which total 0xFF when XOR'd * together. Due to the usual peculiar apple brain damage @@ -217,7 +240,7 @@ struct net_device *mace_probe(int unit) if (checksum != 0xFF) { free_netdev(dev); - return ERR_PTR(-ENODEV); + return -ENODEV; } memset(&mp->stats, 0, sizeof(mp->stats)); @@ -237,22 +260,98 @@ struct net_device *mace_probe(int unit) err = register_netdev(dev); if (!err) - return dev; + return 0; free_netdev(dev); - return ERR_PTR(err); + return err; +} + +/* + * Reset the chip. + */ + +static void mace_reset(struct net_device *dev) +{ + struct mace_data *mp = netdev_priv(dev); + volatile struct mace *mb = mp->mace; + int i; + + /* soft-reset the chip */ + i = 200; + while (--i) { + mb->biucc = SWRST; + if (mb->biucc & SWRST) { + udelay(10); + continue; + } + break; + } + if (!i) { + printk(KERN_ERR "macmace: cannot reset chip!\n"); + return; + } + + mb->maccc = 0; /* turn off tx, rx */ + mb->imr = 0xFF; /* disable all intrs for now */ + i = mb->ir; + + mb->biucc = XMTSP_64; + mb->utr = RTRD; + mb->fifocc = XMTFW_8 | RCVFW_64 | XMTFWU | RCVFWU; + + mb->xmtfc = AUTO_PAD_XMIT; /* auto-pad short frames */ + mb->rcvfc = 0; + + /* load up the hardware address */ + __mace_set_address(dev, dev->dev_addr); + + /* clear the multicast filter */ + if (mp->chipid == BROKEN_ADDRCHG_REV) + mb->iac = LOGADDR; + else { + mb->iac = ADDRCHG | LOGADDR; + while ((mb->iac & ADDRCHG) != 0) + ; + } + for (i = 0; i < 8; ++i) + mb->ladrf = 0; + + /* done changing address */ + if (mp->chipid != BROKEN_ADDRCHG_REV) + mb->iac = 0; + + mb->plscc = PORTSEL_AUI; } /* * Load the address on a mace controller. */ -static int mace_set_address(struct net_device *dev, void *addr) +static void __mace_set_address(struct net_device *dev, void *addr) { - unsigned char *p = addr; - struct mace_data *mp = (struct mace_data *) dev->priv; + struct mace_data *mp = netdev_priv(dev); volatile struct mace *mb = mp->mace; + unsigned char *p = addr; int i; + + /* load up the hardware address */ + if (mp->chipid == BROKEN_ADDRCHG_REV) + mb->iac = PHYADDR; + else { + mb->iac = ADDRCHG | PHYADDR; + while ((mb->iac & ADDRCHG) != 0) + ; + } + for (i = 0; i < 6; ++i) + mb->padr = dev->dev_addr[i] = p[i]; + if (mp->chipid != BROKEN_ADDRCHG_REV) + mb->iac = 0; +} + +static int mace_set_address(struct net_device *dev, void *addr) +{ + struct mace_data *mp = netdev_priv(dev); + volatile struct mace *mb = mp->mace; unsigned long flags; u8 maccc; @@ -260,15 +359,10 @@ static int mace_set_address(struct net_device *dev, void *addr) maccc = mb->maccc; - /* load up the hardware address */ - mb->iac = ADDRCHG | PHYADDR; - while ((mb->iac & ADDRCHG) != 0); - - for (i = 0; i < 6; ++i) { - mb->padr = dev->dev_addr[i] = p[i]; - } + __mace_set_address(dev, addr); mb->maccc = maccc; + local_irq_restore(flags); return 0; @@ -281,31 +375,11 @@ static int mace_set_address(struct net_device *dev, void *addr) static int mace_open(struct net_device *dev) { - struct mace_data *mp = (struct mace_data *) dev->priv; + struct mace_data *mp = netdev_priv(dev); volatile struct mace *mb = mp->mace; -#if 0 - int i; - i = 200; - while (--i) { - mb->biucc = SWRST; - if (mb->biucc & SWRST) { - udelay(10); - continue; - } - break; - } - if (!i) { - printk(KERN_ERR "%s: software reset failed!!\n", dev->name); - return -EAGAIN; - } -#endif - - mb->biucc = XMTSP_64; - mb->fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | XMTBRST | RCVBRST; - mb->xmtfc = AUTO_PAD_XMIT; - mb->plscc = PORTSEL_AUI; - /* mb->utr = RTRD; */ + /* reset the chip */ + mace_reset(dev); if (request_irq(dev->irq, mace_interrupt, 0, dev->name, dev)) { printk(KERN_ERR "%s: can't get irq %d\n", dev->name, dev->irq); @@ -319,25 +393,21 @@ static int mace_open(struct net_device *dev) /* Allocate the DMA ring buffers */ - mp->rx_ring = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, N_RX_PAGES); - mp->tx_ring = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, 0); - - if (mp->tx_ring==NULL || mp->rx_ring==NULL) { - if (mp->rx_ring) free_pages((u32) mp->rx_ring, N_RX_PAGES); - if (mp->tx_ring) free_pages((u32) mp->tx_ring, 0); - free_irq(dev->irq, dev); - free_irq(mp->dma_intr, dev); - printk(KERN_ERR "%s: unable to allocate DMA buffers\n", dev->name); - return -ENOMEM; + mp->tx_ring = dma_alloc_coherent(mp->device, + N_TX_RING * MACE_BUFF_SIZE, + &mp->tx_ring_phys, GFP_KERNEL); + if (mp->tx_ring == NULL) { + printk(KERN_ERR "%s: unable to allocate DMA tx buffers\n", dev->name); + goto out1; } - mp->rx_ring_phys = (unsigned char *) virt_to_bus((void *)mp->rx_ring); - mp->tx_ring_phys = (unsigned char *) virt_to_bus((void *)mp->tx_ring); - - /* We want the Rx buffer to be uncached and the Tx buffer to be writethrough */ - - kernel_set_cachemode((void *)mp->rx_ring, N_RX_PAGES * PAGE_SIZE, IOMAP_NOCACHE_NONSER); - kernel_set_cachemode((void *)mp->tx_ring, PAGE_SIZE, IOMAP_WRITETHROUGH); + mp->rx_ring = dma_alloc_coherent(mp->device, + N_RX_RING * MACE_BUFF_SIZE, + &mp->rx_ring_phys, GFP_KERNEL); + if (mp->rx_ring == NULL) { + printk(KERN_ERR "%s: unable to allocate DMA rx buffers\n", dev->name); + goto out2; + } mace_dma_off(dev); @@ -348,34 +418,22 @@ static int mace_open(struct net_device *dev) psc_write_word(PSC_ENETWR_CTL, 0x0400); psc_write_word(PSC_ENETRD_CTL, 0x0400); -#if 0 - /* load up the hardware address */ - - mb->iac = ADDRCHG | PHYADDR; - - while ((mb->iac & ADDRCHG) != 0); - - for (i = 0; i < 6; ++i) - mb->padr = dev->dev_addr[i]; - - /* clear the multicast filter */ - mb->iac = ADDRCHG | LOGADDR; - - while ((mb->iac & ADDRCHG) != 0); - - for (i = 0; i < 8; ++i) - mb->ladrf = 0; - - mb->plscc = PORTSEL_GPSI + ENPLSIO; - - mb->maccc = ENXMT | ENRCV; - mb->imr = RCVINT; -#endif - mace_rxdma_reset(dev); mace_txdma_reset(dev); + /* turn it on! */ + mb->maccc = ENXMT | ENRCV; + /* enable all interrupts except receive interrupts */ + mb->imr = RCVINT; return 0; + +out2: + dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE, + mp->tx_ring, mp->tx_ring_phys); +out1: + free_irq(dev->irq, dev); + free_irq(mp->dma_intr, dev); + return -ENOMEM; } /* @@ -384,19 +442,13 @@ static int mace_open(struct net_device *dev) static int mace_close(struct net_device *dev) { - struct mace_data *mp = (struct mace_data *) dev->priv; + struct mace_data *mp = netdev_priv(dev); volatile struct mace *mb = mp->mace; mb->maccc = 0; /* disable rx and tx */ mb->imr = 0xFF; /* disable all irqs */ mace_dma_off(dev); /* disable rx and tx dma */ - free_irq(dev->irq, dev); - free_irq(IRQ_MAC_MACE_DMA, dev); - - free_pages((u32) mp->rx_ring, N_RX_PAGES); - free_pages((u32) mp->tx_ring, 0); - return 0; } @@ -406,15 +458,20 @@ static int mace_close(struct net_device *dev) static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev) { - struct mace_data *mp = (struct mace_data *) dev->priv; + struct mace_data *mp = netdev_priv(dev); + unsigned long flags; - /* Stop the queue if the buffer is full */ + /* Stop the queue since there's only the one buffer */ + local_irq_save(flags); + netif_stop_queue(dev); if (!mp->tx_count) { - netif_stop_queue(dev); - return 1; + printk(KERN_ERR "macmace: tx queue running but no free buffers.\n"); + local_irq_restore(flags); + return NETDEV_TX_BUSY; } mp->tx_count--; + local_irq_restore(flags); mp->stats.tx_packets++; mp->stats.tx_bytes += skb->len; @@ -432,23 +489,26 @@ static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev) dev_kfree_skb(skb); - return 0; + dev->trans_start = jiffies; + return NETDEV_TX_OK; } static struct net_device_stats *mace_stats(struct net_device *dev) { - struct mace_data *p = (struct mace_data *) dev->priv; - return &p->stats; + struct mace_data *mp = netdev_priv(dev); + return &mp->stats; } static void mace_set_multicast(struct net_device *dev) { - struct mace_data *mp = (struct mace_data *) dev->priv; + struct mace_data *mp = netdev_priv(dev); volatile struct mace *mb = mp->mace; int i, j; u32 crc; u8 maccc; + unsigned long flags; + local_irq_save(flags); maccc = mb->maccc; mb->maccc &= ~PROM; @@ -473,116 +533,122 @@ static void mace_set_multicast(struct net_device *dev) } } - mb->iac = ADDRCHG | LOGADDR; - while (mb->iac & ADDRCHG); - - for (i = 0; i < 8; ++i) { - mb->ladrf = multicast_filter[i]; + if (mp->chipid == BROKEN_ADDRCHG_REV) + mb->iac = LOGADDR; + else { + mb->iac = ADDRCHG | LOGADDR; + while ((mb->iac & ADDRCHG) != 0) + ; } + for (i = 0; i < 8; ++i) + mb->ladrf = multicast_filter[i]; + if (mp->chipid != BROKEN_ADDRCHG_REV) + mb->iac = 0; } mb->maccc = maccc; + local_irq_restore(flags); } -/* - * Miscellaneous interrupts are handled here. We may end up - * having to bash the chip on the head for bad errors - */ - static void mace_handle_misc_intrs(struct mace_data *mp, int intr) { volatile struct mace *mb = mp->mace; static int mace_babbles, mace_jabbers; - if (intr & MPCO) { + if (intr & MPCO) mp->stats.rx_missed_errors += 256; - } - mp->stats.rx_missed_errors += mb->mpc; /* reading clears it */ - - if (intr & RNTPCO) { + mp->stats.rx_missed_errors += mb->mpc; /* reading clears it */ + if (intr & RNTPCO) mp->stats.rx_length_errors += 256; - } - mp->stats.rx_length_errors += mb->rntpc; /* reading clears it */ - - if (intr & CERR) { + mp->stats.rx_length_errors += mb->rntpc; /* reading clears it */ + if (intr & CERR) ++mp->stats.tx_heartbeat_errors; - } - if (intr & BABBLE) { - if (mace_babbles++ < 4) { - printk(KERN_DEBUG "mace: babbling transmitter\n"); - } - } - if (intr & JABBER) { - if (mace_jabbers++ < 4) { - printk(KERN_DEBUG "mace: jabbering transceiver\n"); - } - } + if (intr & BABBLE) + if (mace_babbles++ < 4) + printk(KERN_DEBUG "macmace: babbling transmitter\n"); + if (intr & JABBER) + if (mace_jabbers++ < 4) + printk(KERN_DEBUG "macmace: jabbering transceiver\n"); } -/* - * A transmit error has occurred. (We kick the transmit side from - * the DMA completion) - */ - -static void mace_xmit_error(struct net_device *dev) +static irqreturn_t mace_interrupt(int irq, void *dev_id) { - struct mace_data *mp = (struct mace_data *) dev->priv; + struct net_device *dev = (struct net_device *) dev_id; + struct mace_data *mp = netdev_priv(dev); volatile struct mace *mb = mp->mace; - u8 xmtfs, xmtrc; + int intr, fs; + unsigned int flags; - xmtfs = mb->xmtfs; - xmtrc = mb->xmtrc; + /* don't want the dma interrupt handler to fire */ + local_irq_save(flags); - if (xmtfs & XMTSV) { - if (xmtfs & UFLO) { - printk("%s: DMA underrun.\n", dev->name); - mp->stats.tx_errors++; - mp->stats.tx_fifo_errors++; - mace_txdma_reset(dev); + intr = mb->ir; /* read interrupt register */ + mace_handle_misc_intrs(mp, intr); + + if (intr & XMTINT) { + fs = mb->xmtfs; + if ((fs & XMTSV) == 0) { + printk(KERN_ERR "macmace: xmtfs not valid! (fs=%x)\n", fs); + mace_reset(dev); + /* + * XXX mace likes to hang the machine after a xmtfs error. + * This is hard to reproduce, reseting *may* help + */ } - if (xmtfs & RTRY) { - mp->stats.collisions++; + /* dma should have finished */ + if (!mp->tx_count) { + printk(KERN_DEBUG "macmace: tx ring ran out? (fs=%x)\n", fs); + } + /* Update stats */ + if (fs & (UFLO|LCOL|LCAR|RTRY)) { + ++mp->stats.tx_errors; + if (fs & LCAR) + ++mp->stats.tx_carrier_errors; + else if (fs & (UFLO|LCOL|RTRY)) { + ++mp->stats.tx_aborted_errors; + if (mb->xmtfs & UFLO) { + printk(KERN_ERR "%s: DMA underrun.\n", dev->name); + mp->stats.tx_fifo_errors++; + mace_txdma_reset(dev); + } + } } } -} -/* - * A receive interrupt occurred. - */ + if (mp->tx_count) + netif_wake_queue(dev); -static void mace_recv_interrupt(struct net_device *dev) -{ -/* struct mace_data *mp = (struct mace_data *) dev->priv; */ -// volatile struct mace *mb = mp->mace; -} + local_irq_restore(flags); -/* - * Process the chip interrupt - */ + return IRQ_HANDLED; +} -static irqreturn_t mace_interrupt(int irq, void *dev_id) +static void mace_tx_timeout(struct net_device *dev) { - struct net_device *dev = (struct net_device *) dev_id; - struct mace_data *mp = (struct mace_data *) dev->priv; + struct mace_data *mp = netdev_priv(dev); volatile struct mace *mb = mp->mace; - u8 ir; + unsigned long flags; - ir = mb->ir; - mace_handle_misc_intrs(mp, ir); + local_irq_save(flags); - if (ir & XMTINT) { - mace_xmit_error(dev); - } - if (ir & RCVINT) { - mace_recv_interrupt(dev); - } - return IRQ_HANDLED; -} + /* turn off both tx and rx and reset the chip */ + mb->maccc = 0; + printk(KERN_ERR "macmace: transmit timeout - resetting\n"); + mace_txdma_reset(dev); + mace_reset(dev); -static void mace_tx_timeout(struct net_device *dev) -{ -/* struct mace_data *mp = (struct mace_data *) dev->priv; */ -// volatile struct mace *mb = mp->mace; + /* restart rx dma */ + mace_rxdma_reset(dev); + + mp->tx_count = N_TX_RING; + netif_wake_queue(dev); + + /* turn it on! */ + mb->maccc = ENXMT | ENRCV; + /* enable all interrupts except receive interrupts */ + mb->imr = RCVINT; + + local_irq_restore(flags); } /* @@ -591,40 +657,39 @@ static void mace_tx_timeout(struct net_device *dev) static void mace_dma_rx_frame(struct net_device *dev, struct mace_frame *mf) { - struct mace_data *mp = (struct mace_data *) dev->priv; + struct mace_data *mp = netdev_priv(dev); struct sk_buff *skb; + unsigned int frame_status = mf->rcvsts; - if (mf->status & RS_OFLO) { - printk("%s: fifo overflow.\n", dev->name); - mp->stats.rx_errors++; - mp->stats.rx_fifo_errors++; - } - if (mf->status&(RS_CLSN|RS_FRAMERR|RS_FCSERR)) + if (frame_status & (RS_OFLO | RS_CLSN | RS_FRAMERR | RS_FCSERR)) { mp->stats.rx_errors++; + if (frame_status & RS_OFLO) { + printk(KERN_DEBUG "%s: fifo overflow.\n", dev->name); + mp->stats.rx_fifo_errors++; + } + if (frame_status & RS_CLSN) + mp->stats.collisions++; + if (frame_status & RS_FRAMERR) + mp->stats.rx_frame_errors++; + if (frame_status & RS_FCSERR) + mp->stats.rx_crc_errors++; + } else { + unsigned int frame_length = mf->rcvcnt + ((frame_status & 0x0F) << 8 ); - if (mf->status&RS_CLSN) { - mp->stats.collisions++; - } - if (mf->status&RS_FRAMERR) { - mp->stats.rx_frame_errors++; - } - if (mf->status&RS_FCSERR) { - mp->stats.rx_crc_errors++; - } - - skb = dev_alloc_skb(mf->len+2); - if (!skb) { - mp->stats.rx_dropped++; - return; + skb = dev_alloc_skb(frame_length + 2); + if (!skb) { + mp->stats.rx_dropped++; + return; + } + skb_reserve(skb, 2); + memcpy(skb_put(skb, frame_length), mf->data, frame_length); + + skb->protocol = eth_type_trans(skb, dev); + netif_rx(skb); + dev->last_rx = jiffies; + mp->stats.rx_packets++; + mp->stats.rx_bytes += frame_length; } - skb_reserve(skb,2); - memcpy(skb_put(skb, mf->len), mf->data, mf->len); - - skb->protocol = eth_type_trans(skb, dev); - netif_rx(skb); - dev->last_rx = jiffies; - mp->stats.rx_packets++; - mp->stats.rx_bytes += mf->len; } /* @@ -634,7 +699,7 @@ static void mace_dma_rx_frame(struct net_device *dev, struct mace_frame *mf) static irqreturn_t mace_dma_intr(int irq, void *dev_id) { struct net_device *dev = (struct net_device *) dev_id; - struct mace_data *mp = (struct mace_data *) dev->priv; + struct mace_data *mp = netdev_priv(dev); int left, head; u16 status; u32 baka; @@ -661,7 +726,8 @@ static irqreturn_t mace_dma_intr(int irq, void *dev_id) /* Loop through the ring buffer and process new packages */ while (mp->rx_tail < head) { - mace_dma_rx_frame(dev, (struct mace_frame *) (mp->rx_ring + (mp->rx_tail * 0x0800))); + mace_dma_rx_frame(dev, (struct mace_frame*) (mp->rx_ring + + (mp->rx_tail * MACE_BUFF_SIZE))); mp->rx_tail++; } @@ -688,9 +754,76 @@ static irqreturn_t mace_dma_intr(int irq, void *dev_id) psc_write_word(PSC_ENETWR_CMD + mp->tx_sloti, 0x0100); mp->tx_sloti ^= 0x10; mp->tx_count++; - netif_wake_queue(dev); } return IRQ_HANDLED; } MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Macintosh MACE ethernet driver"); + +static int __devexit mac_mace_device_remove (struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + struct mace_data *mp = netdev_priv(dev); + + unregister_netdev(dev); + + free_irq(dev->irq, dev); + free_irq(IRQ_MAC_MACE_DMA, dev); + + dma_free_coherent(mp->device, N_RX_RING * MACE_BUFF_SIZE, + mp->rx_ring, mp->rx_ring_phys); + dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE, + mp->tx_ring, mp->tx_ring_phys); + + free_netdev(dev); + + return 0; +} + +static struct platform_driver mac_mace_driver = { + .probe = mace_probe, + .remove = __devexit_p(mac_mace_device_remove), + .driver = { + .name = mac_mace_string, + }, +}; + +static int __init mac_mace_init_module(void) +{ + int err; + + if ((err = platform_driver_register(&mac_mace_driver))) { + printk(KERN_ERR "Driver registration failed\n"); + return err; + } + + mac_mace_device = platform_device_alloc(mac_mace_string, 0); + if (!mac_mace_device) + goto out_unregister; + + if (platform_device_add(mac_mace_device)) { + platform_device_put(mac_mace_device); + mac_mace_device = NULL; + } + + return 0; + +out_unregister: + platform_driver_unregister(&mac_mace_driver); + + return -ENOMEM; +} + +static void __exit mac_mace_cleanup_module(void) +{ + platform_driver_unregister(&mac_mace_driver); + + if (mac_mace_device) { + platform_device_unregister(mac_mace_device); + mac_mace_device = NULL; + } +} + +module_init(mac_mace_init_module); +module_exit(mac_mace_cleanup_module); diff --git a/drivers/net/macsonic.c b/drivers/net/macsonic.c index 8ca57a0a4c11..e9ecdbf352ae 100644 --- a/drivers/net/macsonic.c +++ b/drivers/net/macsonic.c @@ -130,6 +130,46 @@ static inline void bit_reverse_addr(unsigned char addr[6]) addr[i] = bitrev8(addr[i]); } +static irqreturn_t macsonic_interrupt(int irq, void *dev_id) +{ + irqreturn_t result; + unsigned long flags; + + local_irq_save(flags); + result = sonic_interrupt(irq, dev_id); + local_irq_restore(flags); + return result; +} + +static int macsonic_open(struct net_device* dev) +{ + if (request_irq(dev->irq, &sonic_interrupt, IRQ_FLG_FAST, "sonic", dev)) { + printk(KERN_ERR "%s: unable to get IRQ %d.\n", dev->name, dev->irq); + return -EAGAIN; + } + /* Under the A/UX interrupt scheme, the onboard SONIC interrupt comes + * in at priority level 3. However, we sometimes get the level 2 inter- + * rupt as well, which must prevent re-entrance of the sonic handler. + */ + if (dev->irq == IRQ_AUTO_3) + if (request_irq(IRQ_NUBUS_9, &macsonic_interrupt, IRQ_FLG_FAST, "sonic", dev)) { + printk(KERN_ERR "%s: unable to get IRQ %d.\n", dev->name, IRQ_NUBUS_9); + free_irq(dev->irq, dev); + return -EAGAIN; + } + return sonic_open(dev); +} + +static int macsonic_close(struct net_device* dev) +{ + int err; + err = sonic_close(dev); + free_irq(dev->irq, dev); + if (dev->irq == IRQ_AUTO_3) + free_irq(IRQ_NUBUS_9, dev); + return err; +} + int __init macsonic_init(struct net_device* dev) { struct sonic_local* lp = netdev_priv(dev); @@ -160,8 +200,8 @@ int __init macsonic_init(struct net_device* dev) lp->rra_laddr = lp->rda_laddr + (SIZEOF_SONIC_RD * SONIC_NUM_RDS * SONIC_BUS_SCALE(lp->dma_bitmode)); - dev->open = sonic_open; - dev->stop = sonic_close; + dev->open = macsonic_open; + dev->stop = macsonic_close; dev->hard_start_xmit = sonic_send_packet; dev->get_stats = sonic_get_stats; dev->set_multicast_list = &sonic_multicast_list; @@ -402,7 +442,7 @@ int __init macsonic_ident(struct nubus_dev* ndev) ndev->dr_sw == NUBUS_DRSW_DAYNA) return MACSONIC_DAYNA; - if (ndev->dr_hw == NUBUS_DRHW_SONIC_LC && + if (ndev->dr_hw == NUBUS_DRHW_APPLE_SONIC_LC && ndev->dr_sw == 0) { /* huh? */ return MACSONIC_APPLE16; } @@ -522,7 +562,7 @@ int __init mac_nubus_sonic_probe(struct net_device* dev) return macsonic_init(dev); } -static int __init mac_sonic_probe(struct platform_device *device) +static int __init mac_sonic_probe(struct platform_device *pdev) { struct net_device *dev; struct sonic_local *lp; @@ -534,8 +574,8 @@ static int __init mac_sonic_probe(struct platform_device *device) return -ENOMEM; lp = netdev_priv(dev); - lp->device = &device->dev; - SET_NETDEV_DEV(dev, &device->dev); + lp->device = &pdev->dev; + SET_NETDEV_DEV(dev, &pdev->dev); SET_MODULE_OWNER(dev); /* This will catch fatal stuff like -ENOMEM as well as success */ @@ -572,19 +612,17 @@ MODULE_DESCRIPTION("Macintosh SONIC ethernet driver"); module_param(sonic_debug, int, 0); MODULE_PARM_DESC(sonic_debug, "macsonic debug level (1-4)"); -#define SONIC_IRQ_FLAG IRQ_FLG_FAST - #include "sonic.c" -static int __devexit mac_sonic_device_remove (struct platform_device *device) +static int __devexit mac_sonic_device_remove (struct platform_device *pdev) { - struct net_device *dev = platform_get_drvdata(device); + struct net_device *dev = platform_get_drvdata(pdev); struct sonic_local* lp = netdev_priv(dev); - unregister_netdev (dev); + unregister_netdev(dev); dma_free_coherent(lp->device, SIZEOF_SONIC_DESC * SONIC_BUS_SCALE(lp->dma_bitmode), lp->descriptors, lp->descriptors_laddr); - free_netdev (dev); + free_netdev(dev); return 0; } @@ -607,9 +645,8 @@ static int __init mac_sonic_init_module(void) } mac_sonic_device = platform_device_alloc(mac_sonic_string, 0); - if (!mac_sonic_device) { + if (!mac_sonic_device) goto out_unregister; - } if (platform_device_add(mac_sonic_device)) { platform_device_put(mac_sonic_device); diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h index d2767e6584a9..7053026d6c76 100644 --- a/drivers/net/smc91x.h +++ b/drivers/net/smc91x.h @@ -55,6 +55,53 @@ #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) +#elif defined(CONFIG_BFIN) + +#define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH + +# if defined (CONFIG_BFIN561_EZKIT) +#define SMC_CAN_USE_8BIT 0 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 1 +#define SMC_IO_SHIFT 0 +#define SMC_NOWAIT 1 +#define SMC_USE_BFIN_DMA 0 + + +#define SMC_inw(a, r) readw((a) + (r)) +#define SMC_outw(v, a, r) writew(v, (a) + (r)) +#define SMC_inl(a, r) readl((a) + (r)) +#define SMC_outl(v, a, r) writel(v, (a) + (r)) +#define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l) +#define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l) +# else +#define SMC_CAN_USE_8BIT 0 +#define SMC_CAN_USE_16BIT 1 +#define SMC_CAN_USE_32BIT 0 +#define SMC_IO_SHIFT 0 +#define SMC_NOWAIT 1 +#define SMC_USE_BFIN_DMA 0 + + +#define SMC_inw(a, r) readw((a) + (r)) +#define SMC_outw(v, a, r) writew(v, (a) + (r)) +#define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l) +#define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l) +# endif +/* check if the mac in reg is valid */ +#define SMC_GET_MAC_ADDR(addr) \ + do { \ + unsigned int __v; \ + __v = SMC_inw(ioaddr, ADDR0_REG); \ + addr[0] = __v; addr[1] = __v >> 8; \ + __v = SMC_inw(ioaddr, ADDR1_REG); \ + addr[2] = __v; addr[3] = __v >> 8; \ + __v = SMC_inw(ioaddr, ADDR2_REG); \ + addr[4] = __v; addr[5] = __v >> 8; \ + if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \ + random_ether_addr(addr); \ + } \ + } while (0) #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6) /* We can only do 16-bit reads and writes in the static memory space. */ diff --git a/drivers/net/sonic.c b/drivers/net/sonic.c index c6320c719931..8069f3e32d83 100644 --- a/drivers/net/sonic.c +++ b/drivers/net/sonic.c @@ -50,29 +50,6 @@ static int sonic_open(struct net_device *dev) if (sonic_debug > 2) printk("sonic_open: initializing sonic driver.\n"); - /* - * We don't need to deal with auto-irq stuff since we - * hardwire the sonic interrupt. - */ -/* - * XXX Horrible work around: We install sonic_interrupt as fast interrupt. - * This means that during execution of the handler interrupt are disabled - * covering another bug otherwise corrupting data. This doesn't mean - * this glue works ok under all situations. - * - * Note (dhd): this also appears to prevent lockups on the Macintrash - * when more than one Ethernet card is installed (knock on wood) - * - * Note (fthain): whether the above is still true is anyones guess. Certainly - * the buffer handling algorithms will not tolerate re-entrance without some - * mutual exclusion added. Anyway, the memcpy has now been eliminated from the - * rx code to make this a faster "fast interrupt". - */ - if (request_irq(dev->irq, &sonic_interrupt, SONIC_IRQ_FLAG, "sonic", dev)) { - printk(KERN_ERR "\n%s: unable to get IRQ %d .\n", dev->name, dev->irq); - return -EAGAIN; - } - for (i = 0; i < SONIC_NUM_RRS; i++) { struct sk_buff *skb = dev_alloc_skb(SONIC_RBSIZE + 2); if (skb == NULL) { @@ -169,8 +146,6 @@ static int sonic_close(struct net_device *dev) } } - free_irq(dev->irq, dev); /* release the IRQ */ - return 0; } @@ -178,8 +153,13 @@ static void sonic_tx_timeout(struct net_device *dev) { struct sonic_local *lp = netdev_priv(dev); int i; - /* Stop the interrupts for this */ + /* + * put the Sonic into software-reset mode and + * disable all interrupts before releasing DMA buffers + */ SONIC_WRITE(SONIC_IMR, 0); + SONIC_WRITE(SONIC_ISR, 0x7fff); + SONIC_WRITE(SONIC_CMD, SONIC_CR_RST); /* We could resend the original skbs. Easier to re-initialise. */ for (i = 0; i < SONIC_NUM_TDS; i++) { if(lp->tx_laddr[i]) { diff --git a/drivers/net/sun3_82586.c b/drivers/net/sun3_82586.c index 396c3d961f88..a123ea87893b 100644 --- a/drivers/net/sun3_82586.c +++ b/drivers/net/sun3_82586.c @@ -1023,10 +1023,11 @@ static int sun3_82586_send_packet(struct sk_buff *skb, struct net_device *dev) { len = skb->len; if (len < ETH_ZLEN) { - memset((char *)p->xmit_cbuffs[p->xmit_count], 0, ETH_ZLEN); + memset((void *)p->xmit_cbuffs[p->xmit_count], 0, + ETH_ZLEN); len = ETH_ZLEN; } - skb_copy_from_linear_data(skb, p->xmit_cbuffs[p->xmit_count], skb->len); + skb_copy_from_linear_data(skb, (void *)p->xmit_cbuffs[p->xmit_count], skb->len); #if (NUM_XMIT_BUFFS == 1) # ifdef NO_NOPCOMMANDS diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 9488f49ea569..e5e901ecd808 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -64,8 +64,8 @@ #define DRV_MODULE_NAME "tg3" #define PFX DRV_MODULE_NAME ": " -#define DRV_MODULE_VERSION "3.75" -#define DRV_MODULE_RELDATE "March 23, 2007" +#define DRV_MODULE_VERSION "3.76" +#define DRV_MODULE_RELDATE "May 5, 2007" #define TG3_DEF_MAC_MODE 0 #define TG3_DEF_RX_MODE 0 @@ -1300,9 +1300,11 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state) msleep(1); } } - tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | - WOL_DRV_STATE_SHUTDOWN | - WOL_DRV_WOL | WOL_SET_MAGIC_PKT); + if (tp->tg3_flags & TG3_FLAG_WOL_CAP) + tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | + WOL_DRV_STATE_SHUTDOWN | + WOL_DRV_WOL | + WOL_SET_MAGIC_PKT); pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps); @@ -2593,10 +2595,8 @@ static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) { int current_link_up = 0; - if (!(mac_status & MAC_STATUS_PCS_SYNCED)) { - tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL; + if (!(mac_status & MAC_STATUS_PCS_SYNCED)) goto out; - } if (tp->link_config.autoneg == AUTONEG_ENABLE) { u32 flags; @@ -2614,7 +2614,6 @@ static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) tg3_setup_flow_control(tp, local_adv, remote_adv); - tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL; current_link_up = 1; } for (i = 0; i < 30; i++) { @@ -2637,7 +2636,6 @@ static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) } else { /* Forcing 1000FD link up. */ current_link_up = 1; - tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL; tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); udelay(40); @@ -3021,6 +3019,16 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset) } } + if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) { + u32 val = tr32(PCIE_PWR_MGMT_THRESH); + if (!netif_carrier_ok(tp->dev)) + val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | + tp->pwrmgmt_thresh; + else + val |= PCIE_PWR_MGMT_L1_THRESH_MSK; + tw32(PCIE_PWR_MGMT_THRESH, val); + } + return err; } @@ -3582,8 +3590,12 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id) * Writing non-zero to intr-mbox-0 additional tells the * NIC to stop sending us irqs, engaging "in-intr-handler" * event coalescing. + * + * Flush the mailbox to de-assert the IRQ immediately to prevent + * spurious interrupts. The flush impacts performance but + * excessive spurious interrupts can be worse in some cases. */ - tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); + tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); if (tg3_irq_sync(tp)) goto out; sblk->status &= ~SD_STATUS_UPDATED; @@ -3627,8 +3639,12 @@ static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) * writing non-zero to intr-mbox-0 additional tells the * NIC to stop sending us irqs, engaging "in-intr-handler" * event coalescing. + * + * Flush the mailbox to de-assert the IRQ immediately to prevent + * spurious interrupts. The flush impacts performance but + * excessive spurious interrupts can be worse in some cases. */ - tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); + tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); if (tg3_irq_sync(tp)) goto out; if (netif_rx_schedule_prep(dev)) { @@ -3895,8 +3911,7 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev) entry = tp->tx_prod; base_flags = 0; mss = 0; - if (skb->len > (tp->dev->mtu + ETH_HLEN) && - (mss = skb_shinfo(skb)->gso_size) != 0) { + if ((mss = skb_shinfo(skb)->gso_size) != 0) { int tcp_opt_len, ip_tcp_len; if (skb_header_cloned(skb) && @@ -4053,8 +4068,7 @@ static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev) if (skb->ip_summed == CHECKSUM_PARTIAL) base_flags |= TXD_FLAG_TCPUDP_CSUM; mss = 0; - if (skb->len > (tp->dev->mtu + ETH_HLEN) && - (mss = skb_shinfo(skb)->gso_size) != 0) { + if ((mss = skb_shinfo(skb)->gso_size) != 0) { struct iphdr *iph; int tcp_opt_len, ip_tcp_len, hdr_len; @@ -5934,7 +5948,7 @@ static int tg3_load_tso_firmware(struct tg3 *tp) /* tp->lock is held. */ -static void __tg3_set_mac_addr(struct tg3 *tp) +static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) { u32 addr_high, addr_low; int i; @@ -5946,6 +5960,8 @@ static void __tg3_set_mac_addr(struct tg3 *tp) (tp->dev->dev_addr[4] << 8) | (tp->dev->dev_addr[5] << 0)); for (i = 0; i < 4; i++) { + if (i == 1 && skip_mac_1) + continue; tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); } @@ -5972,7 +5988,7 @@ static int tg3_set_mac_addr(struct net_device *dev, void *p) { struct tg3 *tp = netdev_priv(dev); struct sockaddr *addr = p; - int err = 0; + int err = 0, skip_mac_1 = 0; if (!is_valid_ether_addr(addr->sa_data)) return -EINVAL; @@ -5983,22 +5999,21 @@ static int tg3_set_mac_addr(struct net_device *dev, void *p) return 0; if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { - /* Reset chip so that ASF can re-init any MAC addresses it - * needs. - */ - tg3_netif_stop(tp); - tg3_full_lock(tp, 1); + u32 addr0_high, addr0_low, addr1_high, addr1_low; - tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); - err = tg3_restart_hw(tp, 0); - if (!err) - tg3_netif_start(tp); - tg3_full_unlock(tp); - } else { - spin_lock_bh(&tp->lock); - __tg3_set_mac_addr(tp); - spin_unlock_bh(&tp->lock); + addr0_high = tr32(MAC_ADDR_0_HIGH); + addr0_low = tr32(MAC_ADDR_0_LOW); + addr1_high = tr32(MAC_ADDR_1_HIGH); + addr1_low = tr32(MAC_ADDR_1_LOW); + + /* Skip MAC addr 1 if ASF is using it. */ + if ((addr0_high != addr1_high || addr0_low != addr1_low) && + !(addr1_high == 0 && addr1_low == 0)) + skip_mac_1 = 1; } + spin_lock_bh(&tp->lock); + __tg3_set_mac_addr(tp, skip_mac_1); + spin_unlock_bh(&tp->lock); return err; } @@ -6315,7 +6330,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) tp->rx_jumbo_ptr); /* Initialize MAC address and backoff seed. */ - __tg3_set_mac_addr(tp); + __tg3_set_mac_addr(tp, 0); /* MTU + ethernet header + FCS + optional VLAN tag */ tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8); @@ -6346,8 +6361,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) { if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE && - (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || - tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { + GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) { @@ -6457,6 +6471,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; + tp->grc_local_ctrl &= ~gpio_mask; tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; /* GPIO1 must be driven high for eeprom write protect */ @@ -7036,11 +7051,7 @@ static int tg3_open(struct net_device *dev) if (err) return err; - if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && - (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) && - (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) && - !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) && - (tp->pdev_peer == tp->pdev))) { + if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) { /* All MSI supporting chips should support tagged * status. Assert that this is the case. */ @@ -7399,9 +7410,7 @@ static int tg3_close(struct net_device *dev) tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); tg3_free_rings(tp); - tp->tg3_flags &= - ~(TG3_FLAG_INIT_COMPLETE | - TG3_FLAG_GOT_SERDES_FLOWCTL); + tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; tg3_full_unlock(tp); @@ -8036,7 +8045,10 @@ static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) { struct tg3 *tp = netdev_priv(dev); - wol->supported = WAKE_MAGIC; + if (tp->tg3_flags & TG3_FLAG_WOL_CAP) + wol->supported = WAKE_MAGIC; + else + wol->supported = 0; wol->wolopts = 0; if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) wol->wolopts = WAKE_MAGIC; @@ -8050,8 +8062,7 @@ static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) if (wol->wolopts & ~WAKE_MAGIC) return -EINVAL; if ((wol->wolopts & WAKE_MAGIC) && - tp->tg3_flags2 & TG3_FLG2_ANY_SERDES && - !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP)) + !(tp->tg3_flags & TG3_FLAG_WOL_CAP)) return -EINVAL; spin_lock_bh(&tp->lock); @@ -9289,7 +9300,7 @@ static void __devinit tg3_get_nvram_size(struct tg3 *tp) return; } } - tp->nvram_size = 0x20000; + tp->nvram_size = 0x80000; } static void __devinit tg3_get_nvram_info(struct tg3 *tp) @@ -9408,33 +9419,31 @@ static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) { - u32 nvcfg1; + u32 nvcfg1, protect = 0; nvcfg1 = tr32(NVRAM_CFG1); /* NVRAM protection for TPM */ - if (nvcfg1 & (1 << 27)) + if (nvcfg1 & (1 << 27)) { tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM; + protect = 1; + } - switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { - case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ: - case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ: - tp->nvram_jedecnum = JEDEC_ATMEL; - tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; - tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; - - nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; - tw32(NVRAM_CFG1, nvcfg1); - break; - case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: + nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; + switch (nvcfg1) { case FLASH_5755VENDOR_ATMEL_FLASH_1: case FLASH_5755VENDOR_ATMEL_FLASH_2: case FLASH_5755VENDOR_ATMEL_FLASH_3: - case FLASH_5755VENDOR_ATMEL_FLASH_4: tp->nvram_jedecnum = JEDEC_ATMEL; tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; tp->tg3_flags2 |= TG3_FLG2_FLASH; tp->nvram_pagesize = 264; + if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1) + tp->nvram_size = (protect ? 0x3e200 : 0x80000); + else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) + tp->nvram_size = (protect ? 0x1f200 : 0x40000); + else + tp->nvram_size = (protect ? 0x1f200 : 0x20000); break; case FLASH_5752VENDOR_ST_M45PE10: case FLASH_5752VENDOR_ST_M45PE20: @@ -9443,6 +9452,12 @@ static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; tp->tg3_flags2 |= TG3_FLG2_FLASH; tp->nvram_pagesize = 256; + if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) + tp->nvram_size = (protect ? 0x10000 : 0x20000); + else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) + tp->nvram_size = (protect ? 0x10000 : 0x40000); + else + tp->nvram_size = (protect ? 0x20000 : 0x80000); break; } } @@ -9518,6 +9533,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp) } tg3_enable_nvram_access(tp); + tp->nvram_size = 0; + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) tg3_get_5752_nvram_info(tp); else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) @@ -9529,7 +9546,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp) else tg3_get_nvram_info(tp); - tg3_get_nvram_size(tp); + if (tp->nvram_size == 0) + tg3_get_nvram_size(tp); tg3_disable_nvram_access(tp); tg3_nvram_unlock(tp); @@ -9996,14 +10014,16 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) tp->phy_id = PHY_ID_INVALID; tp->led_ctrl = LED_CTRL_MODE_PHY_1; - /* Assume an onboard device by default. */ - tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT; + /* Assume an onboard device and WOL capable by default. */ + tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP; if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; tp->tg3_flags2 |= TG3_FLG2_IS_NIC; } + if (tr32(VCPU_CFGSHDW) & VCPU_CFGSHDW_ASPM_DBNC) + tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; return; } @@ -10120,8 +10140,9 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; } - if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL) - tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP; + if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES && + !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) + tp->tg3_flags &= ~TG3_FLAG_WOL_CAP; if (cfg2 & (1 << 17)) tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING; @@ -10130,6 +10151,14 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) /* bootcode if bit 18 is set */ if (cfg2 & (1 << 18)) tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS; + + if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { + u32 cfg3; + + tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); + if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) + tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; + } } } @@ -10399,6 +10428,8 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp) } } +static struct pci_dev * __devinit tg3_find_peer(struct tg3 *); + static int __devinit tg3_get_invariants(struct tg3 *tp) { static struct pci_device_id write_reorder_chipsets[] = { @@ -10554,6 +10585,10 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff; tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff; + if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || + (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) + tp->pdev_peer = tg3_find_peer(tp); + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || @@ -10567,6 +10602,14 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) tp->tg3_flags2 |= TG3_FLG2_5705_PLUS; if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { + tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI; + if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || + GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || + (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && + tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && + tp->pdev_peer == tp->pdev)) + tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI; + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { @@ -10668,17 +10711,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG; - /* Back to back register writes can cause problems on this chip, - * the workaround is to read back all reg writes except those to - * mailbox regs. See tg3_write_indirect_reg32(). - * - * PCI Express 5750_A0 rev chips need this workaround too. - */ - if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || - ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && - tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) - tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG; - if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED; if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) @@ -10702,8 +10734,19 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) /* Various workaround register access methods */ if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) tp->write32 = tg3_write_indirect_reg32; - else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) + else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || + ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && + tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { + /* + * Back to back register writes can cause problems on these + * chips, the workaround is to read back all reg writes + * except those to mailbox regs. + * + * See tg3_write_indirect_reg32(). + */ tp->write32 = tg3_write_flush_reg32; + } + if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) || (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) { @@ -10983,6 +11026,10 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) */ tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE; + if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) + tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & + PCIE_PWR_MGMT_L1_THRESH_MSK; + return err; } @@ -11892,10 +11939,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, tp->rx_pending = 63; } - if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || - (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) - tp->pdev_peer = tg3_find_peer(tp); - err = tg3_get_device_address(tp); if (err) { printk(KERN_ERR PFX "Could not obtain valid ethernet address, " diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index d515ed23841b..4d334cf5a243 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -131,6 +131,7 @@ #define CHIPREV_ID_5752_A0_HW 0x5000 #define CHIPREV_ID_5752_A0 0x6000 #define CHIPREV_ID_5752_A1 0x6001 +#define CHIPREV_ID_5714_A2 0x9002 #define CHIPREV_ID_5906_A1 0xc001 #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) #define ASIC_REV_5700 0x07 @@ -1149,6 +1150,9 @@ #define VCPU_STATUS_INIT_DONE 0x04000000 #define VCPU_STATUS_DRV_RESET 0x08000000 +#define VCPU_CFGSHDW 0x00005104 +#define VCPU_CFGSHDW_ASPM_DBNC 0x00001000 + /* Mailboxes */ #define GRCMBOX_BASE 0x00005600 #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ @@ -1506,6 +1510,8 @@ #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 #define PCIE_TRANS_CFG_LOM 0x00000020 +#define PCIE_PWR_MGMT_THRESH 0x00007d28 +#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 #define TG3_EEPROM_MAGIC 0x669955aa #define TG3_EEPROM_MAGIC_FW 0xa5000000 @@ -1592,6 +1598,9 @@ #define SHASTA_EXT_LED_MAC 0x00010000 #define SHASTA_EXT_LED_COMBO 0x00018000 +#define NIC_SRAM_DATA_CFG_3 0x00000d3c +#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002 + #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 @@ -2199,7 +2208,7 @@ struct tg3 { #define TG3_FLAG_USE_LINKCHG_REG 0x00000008 #define TG3_FLAG_USE_MI_INTERRUPT 0x00000010 #define TG3_FLAG_ENABLE_ASF 0x00000020 -#define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040 +#define TG3_FLAG_ASPM_WORKAROUND 0x00000040 #define TG3_FLAG_POLL_SERDES 0x00000080 #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100 #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200 @@ -2215,14 +2224,14 @@ struct tg3 { #define TG3_FLAG_PCI_32BIT 0x00080000 #define TG3_FLAG_SRAM_USE_CONFIG 0x00100000 #define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000 -#define TG3_FLAG_SERDES_WOL_CAP 0x00400000 +#define TG3_FLAG_WOL_CAP 0x00400000 #define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000 #define TG3_FLAG_10_100_ONLY 0x01000000 #define TG3_FLAG_PAUSE_AUTONEG 0x02000000 #define TG3_FLAG_IN_RESET_TASK 0x04000000 #define TG3_FLAG_40BIT_DMA_BUG 0x08000000 #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000 -#define TG3_FLAG_GOT_SERDES_FLOWCTL 0x20000000 +#define TG3_FLAG_SUPPORT_MSI 0x20000000 #define TG3_FLAG_CHIP_RESETTING 0x40000000 #define TG3_FLAG_INIT_COMPLETE 0x80000000 u32 tg3_flags2; @@ -2288,6 +2297,7 @@ struct tg3 { u32 grc_local_ctrl; u32 dma_rwctrl; u32 coalesce_mode; + u32 pwrmgmt_thresh; /* PCI block */ u16 pci_chip_rev_id; diff --git a/drivers/net/tokenring/madgemc.c b/drivers/net/tokenring/madgemc.c index ed274d6909d0..f8f4d74f01f1 100644 --- a/drivers/net/tokenring/madgemc.c +++ b/drivers/net/tokenring/madgemc.c @@ -23,7 +23,6 @@ static const char version[] = "madgemc.c: v0.91 23/01/2000 by Adam Fritzler\n"; #include <linux/mca.h> #include <linux/kernel.h> #include <linux/errno.h> -#include <linux/pci.h> #include <linux/init.h> #include <linux/netdevice.h> #include <linux/trdevice.h> diff --git a/drivers/net/tokenring/smctr.c b/drivers/net/tokenring/smctr.c index 9bbea5c8acf4..58d7e5d452fa 100644 --- a/drivers/net/tokenring/smctr.c +++ b/drivers/net/tokenring/smctr.c @@ -41,7 +41,6 @@ #include <linux/time.h> #include <linux/errno.h> #include <linux/init.h> -#include <linux/pci.h> #include <linux/mca-legacy.h> #include <linux/delay.h> #include <linux/netdevice.h> diff --git a/drivers/net/tulip/21142.c b/drivers/net/tulip/21142.c index 942b839ccc5b..6c400ccd38b4 100644 --- a/drivers/net/tulip/21142.c +++ b/drivers/net/tulip/21142.c @@ -14,7 +14,6 @@ */ -#include <linux/pci.h> #include <linux/delay.h> #include "tulip.h" diff --git a/drivers/net/tulip/pnic.c b/drivers/net/tulip/pnic.c index 85a521e0d052..be82a2effee3 100644 --- a/drivers/net/tulip/pnic.c +++ b/drivers/net/tulip/pnic.c @@ -15,7 +15,6 @@ */ #include <linux/kernel.h> -#include <linux/pci.h> #include <linux/jiffies.h> #include "tulip.h" diff --git a/drivers/net/tulip/pnic2.c b/drivers/net/tulip/pnic2.c index c31be0e377a8..4e4a879c3fa5 100644 --- a/drivers/net/tulip/pnic2.c +++ b/drivers/net/tulip/pnic2.c @@ -76,7 +76,6 @@ -#include <linux/pci.h> #include "tulip.h" #include <linux/delay.h> diff --git a/drivers/net/tulip/timer.c b/drivers/net/tulip/timer.c index df326fe1cc8f..d2c1f42109b0 100644 --- a/drivers/net/tulip/timer.c +++ b/drivers/net/tulip/timer.c @@ -14,7 +14,6 @@ */ -#include <linux/pci.h> #include "tulip.h" diff --git a/drivers/net/tulip/tulip.h b/drivers/net/tulip/tulip.h index c840d2e67b23..16f26a8364f0 100644 --- a/drivers/net/tulip/tulip.h +++ b/drivers/net/tulip/tulip.h @@ -22,6 +22,7 @@ #include <linux/netdevice.h> #include <linux/timer.h> #include <linux/delay.h> +#include <linux/pci.h> #include <asm/io.h> #include <asm/irq.h> diff --git a/drivers/net/wan/lmc/lmc_media.c b/drivers/net/wan/lmc/lmc_media.c index ae01555d24cf..574737b55f39 100644 --- a/drivers/net/wan/lmc/lmc_media.c +++ b/drivers/net/wan/lmc/lmc_media.c @@ -8,7 +8,6 @@ #include <linux/ioport.h> #include <linux/slab.h> #include <linux/interrupt.h> -#include <linux/pci.h> #include <linux/in.h> #include <linux/if_arp.h> #include <linux/netdevice.h> diff --git a/drivers/net/wan/lmc/lmc_proto.c b/drivers/net/wan/lmc/lmc_proto.c index 74876c0073e8..31e1799571ad 100644 --- a/drivers/net/wan/lmc/lmc_proto.c +++ b/drivers/net/wan/lmc/lmc_proto.c @@ -27,7 +27,6 @@ #include <linux/ioport.h> #include <linux/slab.h> #include <linux/interrupt.h> -#include <linux/pci.h> #include <linux/in.h> #include <linux/if_arp.h> #include <linux/netdevice.h> diff --git a/drivers/net/wan/pc300_tty.c b/drivers/net/wan/pc300_tty.c index 07dbdfbfc15d..e24a7b095dd6 100644 --- a/drivers/net/wan/pc300_tty.c +++ b/drivers/net/wan/pc300_tty.c @@ -38,7 +38,6 @@ #include <linux/module.h> #include <linux/kernel.h> -#include <linux/pci.h> #include <linux/errno.h> #include <linux/string.h> #include <linux/init.h> diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig index c4b3dc291a5a..0184614517f9 100644 --- a/drivers/net/wireless/Kconfig +++ b/drivers/net/wireless/Kconfig @@ -153,8 +153,8 @@ config IPW2100 If you want to compile the driver as a module ( = code which can be inserted in and removed from the running kernel whenever you want), - say M here and read <file:Documentation/modules.txt>. The module - will be called ipw2100.ko. + say M here and read <file:Documentation/kbuild/modules.txt>. + The module will be called ipw2100.ko. config IPW2100_MONITOR bool "Enable promiscuous mode" @@ -208,8 +208,8 @@ config IPW2200 If you want to compile the driver as a module ( = code which can be inserted in and removed from the running kernel whenever you want), - say M here and read <file:Documentation/modules.txt>. The module - will be called ipw2200.ko. + say M here and read <file:Documentation/kbuild/modules.txt>. + The module will be called ipw2200.ko. config IPW2200_MONITOR bool "Enable promiscuous mode" @@ -517,8 +517,8 @@ config PRISM54 If you want to compile the driver as a module ( = code which can be inserted in and removed from the running kernel whenever you want), - say M here and read <file:Documentation/modules.txt>. The module - will be called prism54.ko. + say M here and read <file:Documentation/kbuild/modules.txt>. + The module will be called prism54.ko. config USB_ZD1201 tristate "USB ZD1201 based Wireless device support" diff --git a/drivers/net/wireless/strip.c b/drivers/net/wireless/strip.c index 2a299a0676a6..ef32a5c1e818 100644 --- a/drivers/net/wireless/strip.c +++ b/drivers/net/wireless/strip.c @@ -1971,8 +1971,7 @@ static struct net_device *get_strip_dev(struct strip *strip_info) sizeof(zero_address))) { struct net_device *dev; read_lock_bh(&dev_base_lock); - dev = dev_base; - while (dev) { + for_each_netdev(dev) { if (dev->type == strip_info->dev->type && !memcmp(dev->dev_addr, &strip_info->true_dev_addr, @@ -1983,7 +1982,6 @@ static struct net_device *get_strip_dev(struct strip *strip_info) read_unlock_bh(&dev_base_lock); return (dev); } - dev = dev->next; } read_unlock_bh(&dev_base_lock); } |