diff options
Diffstat (limited to 'drivers/net/ethernet/ti/cpsw.c')
| -rw-r--r-- | drivers/net/ethernet/ti/cpsw.c | 630 |
1 files changed, 464 insertions, 166 deletions
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index df55e2403746..02c24777e23b 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -24,6 +24,7 @@ #include <linux/if_ether.h> #include <linux/etherdevice.h> #include <linux/netdevice.h> +#include <linux/net_tstamp.h> #include <linux/phy.h> #include <linux/workqueue.h> #include <linux/delay.h> @@ -35,6 +36,7 @@ #include <linux/platform_data/cpsw.h> #include "cpsw_ale.h" +#include "cpts.h" #include "davinci_cpdma.h" #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ @@ -70,10 +72,37 @@ do { \ dev_notice(priv->dev, format, ## __VA_ARGS__); \ } while (0) +#define ALE_ALL_PORTS 0x7 + #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) #define CPSW_MINOR_VERSION(reg) (reg & 0xff) #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) +#define CPSW_VERSION_1 0x19010a +#define CPSW_VERSION_2 0x19010c + +#define HOST_PORT_NUM 0 +#define SLIVER_SIZE 0x40 + +#define CPSW1_HOST_PORT_OFFSET 0x028 +#define CPSW1_SLAVE_OFFSET 0x050 +#define CPSW1_SLAVE_SIZE 0x040 +#define CPSW1_CPDMA_OFFSET 0x100 +#define CPSW1_STATERAM_OFFSET 0x200 +#define CPSW1_CPTS_OFFSET 0x500 +#define CPSW1_ALE_OFFSET 0x600 +#define CPSW1_SLIVER_OFFSET 0x700 + +#define CPSW2_HOST_PORT_OFFSET 0x108 +#define CPSW2_SLAVE_OFFSET 0x200 +#define CPSW2_SLAVE_SIZE 0x100 +#define CPSW2_CPDMA_OFFSET 0x800 +#define CPSW2_STATERAM_OFFSET 0xa00 +#define CPSW2_CPTS_OFFSET 0xc00 +#define CPSW2_ALE_OFFSET 0xd00 +#define CPSW2_SLIVER_OFFSET 0xd80 +#define CPSW2_BD_OFFSET 0x2000 + #define CPDMA_RXTHRESH 0x0c0 #define CPDMA_RXFREE 0x0e0 #define CPDMA_TXHDP 0x00 @@ -81,21 +110,6 @@ do { \ #define CPDMA_TXCP 0x40 #define CPDMA_RXCP 0x60 -#define cpsw_dma_regs(base, offset) \ - (void __iomem *)((base) + (offset)) -#define cpsw_dma_rxthresh(base, offset) \ - (void __iomem *)((base) + (offset) + CPDMA_RXTHRESH) -#define cpsw_dma_rxfree(base, offset) \ - (void __iomem *)((base) + (offset) + CPDMA_RXFREE) -#define cpsw_dma_txhdp(base, offset) \ - (void __iomem *)((base) + (offset) + CPDMA_TXHDP) -#define cpsw_dma_rxhdp(base, offset) \ - (void __iomem *)((base) + (offset) + CPDMA_RXHDP) -#define cpsw_dma_txcp(base, offset) \ - (void __iomem *)((base) + (offset) + CPDMA_TXCP) -#define cpsw_dma_rxcp(base, offset) \ - (void __iomem *)((base) + (offset) + CPDMA_RXCP) - #define CPSW_POLL_WEIGHT 64 #define CPSW_MIN_PACKET_SIZE 60 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) @@ -129,7 +143,7 @@ static int rx_packet_max = CPSW_MAX_PACKET_SIZE; module_param(rx_packet_max, int, 0); MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); -struct cpsw_ss_regs { +struct cpsw_wr_regs { u32 id_ver; u32 soft_reset; u32 control; @@ -140,26 +154,98 @@ struct cpsw_ss_regs { u32 misc_en; }; -struct cpsw_regs { +struct cpsw_ss_regs { u32 id_ver; u32 control; u32 soft_reset; u32 stat_port_en; u32 ptype; + u32 soft_idle; + u32 thru_rate; + u32 gap_thresh; + u32 tx_start_wds; + u32 flow_control; + u32 vlan_ltype; + u32 ts_ltype; + u32 dlr_ltype; }; -struct cpsw_slave_regs { - u32 max_blks; - u32 blk_cnt; - u32 flow_thresh; - u32 port_vlan; - u32 tx_pri_map; - u32 ts_ctl; - u32 ts_seq_ltype; - u32 ts_vlan; - u32 sa_lo; - u32 sa_hi; -}; +/* CPSW_PORT_V1 */ +#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ +#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ +#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ +#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ +#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ +#define CPSW1_TS_CTL 0x14 /* Time Sync Control */ +#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ +#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ + +/* CPSW_PORT_V2 */ +#define CPSW2_CONTROL 0x00 /* Control Register */ +#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ +#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ +#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ +#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ +#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ +#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ + +/* CPSW_PORT_V1 and V2 */ +#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ +#define SA_HI 0x24 /* CPGMAC_SL Source Address High */ +#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ + +/* CPSW_PORT_V2 only */ +#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ +#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ +#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ +#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ +#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ +#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ +#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ +#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ + +/* Bit definitions for the CPSW2_CONTROL register */ +#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ +#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ +#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ +#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ +#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ +#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ +#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ +#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ +#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ +#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ +#define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ +#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ +#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ +#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ +#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ +#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ + +#define CTRL_TS_BITS \ + (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ + TS_ANNEX_D_EN | TS_LTYPE1_EN) + +#define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) +#define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN) +#define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN) + +/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ +#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ +#define TS_SEQ_ID_OFFSET_MASK (0x3f) +#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ +#define TS_MSG_TYPE_EN_MASK (0xffff) + +/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ +#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) + +/* Bit definitions for the CPSW1_TS_CTL register */ +#define CPSW_V1_TS_RX_EN BIT(0) +#define CPSW_V1_TS_TX_EN BIT(4) +#define CPSW_V1_MSG_TYPE_OFS 16 + +/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ +#define CPSW_V1_SEQ_ID_OFS_SHIFT 16 struct cpsw_host_regs { u32 max_blks; @@ -185,7 +271,7 @@ struct cpsw_sliver_regs { }; struct cpsw_slave { - struct cpsw_slave_regs __iomem *regs; + void __iomem *regs; struct cpsw_sliver_regs __iomem *sliver; int slave_num; u32 mac_control; @@ -193,19 +279,30 @@ struct cpsw_slave { struct phy_device *phy; }; +static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) +{ + return __raw_readl(slave->regs + offset); +} + +static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) +{ + __raw_writel(val, slave->regs + offset); +} + struct cpsw_priv { spinlock_t lock; struct platform_device *pdev; struct net_device *ndev; struct resource *cpsw_res; - struct resource *cpsw_ss_res; + struct resource *cpsw_wr_res; struct napi_struct napi; struct device *dev; struct cpsw_platform_data data; - struct cpsw_regs __iomem *regs; - struct cpsw_ss_regs __iomem *ss_regs; + struct cpsw_ss_regs __iomem *regs; + struct cpsw_wr_regs __iomem *wr_regs; struct cpsw_host_regs __iomem *host_port_regs; u32 msg_enable; + u32 version; struct net_device_stats stats; int rx_packet_max; int host_port; @@ -218,6 +315,7 @@ struct cpsw_priv { /* snapshot of IRQ numbers */ u32 irqs_table[4]; u32 num_irqs; + struct cpts cpts; }; #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) @@ -228,10 +326,34 @@ struct cpsw_priv { (func)((priv)->slaves + idx, ##arg); \ } while (0) +static void cpsw_ndo_set_rx_mode(struct net_device *ndev) +{ + struct cpsw_priv *priv = netdev_priv(ndev); + + if (ndev->flags & IFF_PROMISC) { + /* Enable promiscuous mode */ + dev_err(priv->dev, "Ignoring Promiscuous mode\n"); + return; + } + + /* Clear all mcast from ALE */ + cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); + + if (!netdev_mc_empty(ndev)) { + struct netdev_hw_addr *ha; + + /* program multicast address list into ALE register */ + netdev_for_each_mc_addr(ha, ndev) { + cpsw_ale_add_mcast(priv->ale, (u8 *)ha->addr, + ALE_ALL_PORTS << priv->host_port, 0, 0); + } + } +} + static void cpsw_intr_enable(struct cpsw_priv *priv) { - __raw_writel(0xFF, &priv->ss_regs->tx_en); - __raw_writel(0xFF, &priv->ss_regs->rx_en); + __raw_writel(0xFF, &priv->wr_regs->tx_en); + __raw_writel(0xFF, &priv->wr_regs->rx_en); cpdma_ctlr_int_ctrl(priv->dma, true); return; @@ -239,8 +361,8 @@ static void cpsw_intr_enable(struct cpsw_priv *priv) static void cpsw_intr_disable(struct cpsw_priv *priv) { - __raw_writel(0, &priv->ss_regs->tx_en); - __raw_writel(0, &priv->ss_regs->rx_en); + __raw_writel(0, &priv->wr_regs->tx_en); + __raw_writel(0, &priv->wr_regs->rx_en); cpdma_ctlr_int_ctrl(priv->dma, false); return; @@ -254,6 +376,7 @@ void cpsw_tx_handler(void *token, int len, int status) if (unlikely(netif_queue_stopped(ndev))) netif_start_queue(ndev); + cpts_tx_timestamp(&priv->cpts, skb); priv->stats.tx_packets++; priv->stats.tx_bytes += len; dev_kfree_skb_any(skb); @@ -274,6 +397,7 @@ void cpsw_rx_handler(void *token, int len, int status) } if (likely(status >= 0)) { skb_put(skb, len); + cpts_rx_timestamp(&priv->cpts, skb); skb->protocol = eth_type_trans(skb, ndev); netif_receive_skb(skb); priv->stats.rx_bytes += len; @@ -359,8 +483,8 @@ static inline void soft_reset(const char *module, void __iomem *reg) static void cpsw_set_slave_mac(struct cpsw_slave *slave, struct cpsw_priv *priv) { - __raw_writel(mac_hi(priv->mac_addr), &slave->regs->sa_hi); - __raw_writel(mac_lo(priv->mac_addr), &slave->regs->sa_lo); + slave_write(slave, mac_hi(priv->mac_addr), SA_HI); + slave_write(slave, mac_lo(priv->mac_addr), SA_LO); } static void _cpsw_adjust_link(struct cpsw_slave *slave, @@ -446,7 +570,15 @@ static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) /* setup priority mapping */ __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); - __raw_writel(TX_PRIORITY_MAPPING, &slave->regs->tx_pri_map); + + switch (priv->version) { + case CPSW_VERSION_1: + slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); + break; + case CPSW_VERSION_2: + slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); + break; + } /* setup max packet size, and mac address */ __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); @@ -505,7 +637,7 @@ static int cpsw_ndo_open(struct net_device *ndev) pm_runtime_get_sync(&priv->pdev->dev); - reg = __raw_readl(&priv->regs->id_ver); + reg = priv->version; dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), @@ -566,12 +698,12 @@ static int cpsw_ndo_stop(struct net_device *ndev) struct cpsw_priv *priv = netdev_priv(ndev); cpsw_info(priv, ifdown, "shutting down cpsw device\n"); - cpsw_intr_disable(priv); - cpdma_ctlr_int_ctrl(priv->dma, false); - cpdma_ctlr_stop(priv->dma); netif_stop_queue(priv->ndev); napi_disable(&priv->napi); netif_carrier_off(priv->ndev); + cpsw_intr_disable(priv); + cpdma_ctlr_int_ctrl(priv->dma, false); + cpdma_ctlr_stop(priv->dma); cpsw_ale_stop(priv->ale); for_each_slave(priv, cpsw_slave_stop, priv); pm_runtime_put_sync(&priv->pdev->dev); @@ -592,6 +724,11 @@ static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, return NETDEV_TX_OK; } + if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && priv->cpts.tx_enable) + skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; + + skb_tx_timestamp(skb); + ret = cpdma_chan_submit(priv->txch, skb, skb->data, skb->len, GFP_KERNEL); if (unlikely(ret != 0)) { @@ -629,6 +766,130 @@ static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags) dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n"); } +#ifdef CONFIG_TI_CPTS + +static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) +{ + struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave]; + u32 ts_en, seq_id; + + if (!priv->cpts.tx_enable && !priv->cpts.rx_enable) { + slave_write(slave, 0, CPSW1_TS_CTL); + return; + } + + seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; + ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; + + if (priv->cpts.tx_enable) + ts_en |= CPSW_V1_TS_TX_EN; + + if (priv->cpts.rx_enable) + ts_en |= CPSW_V1_TS_RX_EN; + + slave_write(slave, ts_en, CPSW1_TS_CTL); + slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); +} + +static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) +{ + struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave]; + u32 ctrl, mtype; + + ctrl = slave_read(slave, CPSW2_CONTROL); + ctrl &= ~CTRL_ALL_TS_MASK; + + if (priv->cpts.tx_enable) + ctrl |= CTRL_TX_TS_BITS; + + if (priv->cpts.rx_enable) + ctrl |= CTRL_RX_TS_BITS; + + mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; + + slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); + slave_write(slave, ctrl, CPSW2_CONTROL); + __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); +} + +static int cpsw_hwtstamp_ioctl(struct cpsw_priv *priv, struct ifreq *ifr) +{ + struct cpts *cpts = &priv->cpts; + struct hwtstamp_config cfg; + + if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) + return -EFAULT; + + /* reserved for future extensions */ + if (cfg.flags) + return -EINVAL; + + switch (cfg.tx_type) { + case HWTSTAMP_TX_OFF: + cpts->tx_enable = 0; + break; + case HWTSTAMP_TX_ON: + cpts->tx_enable = 1; + break; + default: + return -ERANGE; + } + + switch (cfg.rx_filter) { + case HWTSTAMP_FILTER_NONE: + cpts->rx_enable = 0; + break; + case HWTSTAMP_FILTER_ALL: + case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: + case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: + case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: + return -ERANGE; + case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: + case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: + case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: + case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: + case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: + case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: + case HWTSTAMP_FILTER_PTP_V2_EVENT: + case HWTSTAMP_FILTER_PTP_V2_SYNC: + case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: + cpts->rx_enable = 1; + cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; + break; + default: + return -ERANGE; + } + + switch (priv->version) { + case CPSW_VERSION_1: + cpsw_hwtstamp_v1(priv); + break; + case CPSW_VERSION_2: + cpsw_hwtstamp_v2(priv); + break; + default: + return -ENOTSUPP; + } + + return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; +} + +#endif /*CONFIG_TI_CPTS*/ + +static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) +{ + struct cpsw_priv *priv = netdev_priv(dev); + + if (!netif_running(dev)) + return -EINVAL; + +#ifdef CONFIG_TI_CPTS + if (cmd == SIOCSHWTSTAMP) + return cpsw_hwtstamp_ioctl(priv, req); +#endif + return -ENOTSUPP; +} + static void cpsw_ndo_tx_timeout(struct net_device *ndev) { struct cpsw_priv *priv = netdev_priv(ndev); @@ -669,10 +930,12 @@ static const struct net_device_ops cpsw_netdev_ops = { .ndo_stop = cpsw_ndo_stop, .ndo_start_xmit = cpsw_ndo_start_xmit, .ndo_change_rx_flags = cpsw_ndo_change_rx_flags, + .ndo_do_ioctl = cpsw_ndo_ioctl, .ndo_validate_addr = eth_validate_addr, .ndo_change_mtu = eth_change_mtu, .ndo_tx_timeout = cpsw_ndo_tx_timeout, .ndo_get_stats = cpsw_ndo_get_stats, + .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = cpsw_ndo_poll_controller, #endif @@ -699,22 +962,56 @@ static void cpsw_set_msglevel(struct net_device *ndev, u32 value) priv->msg_enable = value; } +static int cpsw_get_ts_info(struct net_device *ndev, + struct ethtool_ts_info *info) +{ +#ifdef CONFIG_TI_CPTS + struct cpsw_priv *priv = netdev_priv(ndev); + + info->so_timestamping = + SOF_TIMESTAMPING_TX_HARDWARE | + SOF_TIMESTAMPING_TX_SOFTWARE | + SOF_TIMESTAMPING_RX_HARDWARE | + SOF_TIMESTAMPING_RX_SOFTWARE | + SOF_TIMESTAMPING_SOFTWARE | + SOF_TIMESTAMPING_RAW_HARDWARE; + info->phc_index = priv->cpts.phc_index; + info->tx_types = + (1 << HWTSTAMP_TX_OFF) | + (1 << HWTSTAMP_TX_ON); + info->rx_filters = + (1 << HWTSTAMP_FILTER_NONE) | + (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); +#else + info->so_timestamping = + SOF_TIMESTAMPING_TX_SOFTWARE | + SOF_TIMESTAMPING_RX_SOFTWARE | + SOF_TIMESTAMPING_SOFTWARE; + info->phc_index = -1; + info->tx_types = 0; + info->rx_filters = 0; +#endif + return 0; +} + static const struct ethtool_ops cpsw_ethtool_ops = { .get_drvinfo = cpsw_get_drvinfo, .get_msglevel = cpsw_get_msglevel, .set_msglevel = cpsw_set_msglevel, .get_link = ethtool_op_get_link, + .get_ts_info = cpsw_get_ts_info, }; -static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv) +static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, + u32 slave_reg_ofs, u32 sliver_reg_ofs) { void __iomem *regs = priv->regs; int slave_num = slave->slave_num; struct cpsw_slave_data *data = priv->data.slave_data + slave_num; slave->data = data; - slave->regs = regs + data->slave_reg_ofs; - slave->sliver = regs + data->sliver_reg_ofs; + slave->regs = regs + slave_reg_ofs; + slave->sliver = regs + sliver_reg_ofs; } static int cpsw_probe_dt(struct cpsw_platform_data *data, @@ -734,49 +1031,40 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data, } data->slaves = prop; - data->slave_data = kzalloc(sizeof(struct cpsw_slave_data) * - data->slaves, GFP_KERNEL); - if (!data->slave_data) { - pr_err("Could not allocate slave memory.\n"); - return -EINVAL; - } - - data->no_bd_ram = of_property_read_bool(node, "no_bd_ram"); - - if (of_property_read_u32(node, "cpdma_channels", &prop)) { - pr_err("Missing cpdma_channels property in the DT.\n"); + if (of_property_read_u32(node, "cpts_active_slave", &prop)) { + pr_err("Missing cpts_active_slave property in the DT.\n"); ret = -EINVAL; goto error_ret; } - data->channels = prop; + data->cpts_active_slave = prop; - if (of_property_read_u32(node, "host_port_no", &prop)) { - pr_err("Missing host_port_no property in the DT.\n"); + if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { + pr_err("Missing cpts_clock_mult property in the DT.\n"); ret = -EINVAL; goto error_ret; } - data->host_port_num = prop; + data->cpts_clock_mult = prop; - if (of_property_read_u32(node, "cpdma_reg_ofs", &prop)) { - pr_err("Missing cpdma_reg_ofs property in the DT.\n"); + if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { + pr_err("Missing cpts_clock_shift property in the DT.\n"); ret = -EINVAL; goto error_ret; } - data->cpdma_reg_ofs = prop; + data->cpts_clock_shift = prop; - if (of_property_read_u32(node, "cpdma_sram_ofs", &prop)) { - pr_err("Missing cpdma_sram_ofs property in the DT.\n"); - ret = -EINVAL; - goto error_ret; + data->slave_data = kzalloc(sizeof(struct cpsw_slave_data) * + data->slaves, GFP_KERNEL); + if (!data->slave_data) { + pr_err("Could not allocate slave memory.\n"); + return -EINVAL; } - data->cpdma_sram_ofs = prop; - if (of_property_read_u32(node, "ale_reg_ofs", &prop)) { - pr_err("Missing ale_reg_ofs property in the DT.\n"); + if (of_property_read_u32(node, "cpdma_channels", &prop)) { + pr_err("Missing cpdma_channels property in the DT.\n"); ret = -EINVAL; goto error_ret; } - data->ale_reg_ofs = prop; + data->channels = prop; if (of_property_read_u32(node, "ale_entries", &prop)) { pr_err("Missing ale_entries property in the DT.\n"); @@ -785,27 +1073,6 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data, } data->ale_entries = prop; - if (of_property_read_u32(node, "host_port_reg_ofs", &prop)) { - pr_err("Missing host_port_reg_ofs property in the DT.\n"); - ret = -EINVAL; - goto error_ret; - } - data->host_port_reg_ofs = prop; - - if (of_property_read_u32(node, "hw_stats_reg_ofs", &prop)) { - pr_err("Missing hw_stats_reg_ofs property in the DT.\n"); - ret = -EINVAL; - goto error_ret; - } - data->hw_stats_reg_ofs = prop; - - if (of_property_read_u32(node, "bd_ram_ofs", &prop)) { - pr_err("Missing bd_ram_ofs property in the DT.\n"); - ret = -EINVAL; - goto error_ret; - } - data->bd_ram_ofs = prop; - if (of_property_read_u32(node, "bd_ram_size", &prop)) { pr_err("Missing bd_ram_size property in the DT.\n"); ret = -EINVAL; @@ -827,33 +1094,34 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data, } data->mac_control = prop; - for_each_child_of_node(node, slave_node) { + /* + * Populate all the child nodes here... + */ + ret = of_platform_populate(node, NULL, NULL, &pdev->dev); + /* We do not want to force this, as in some cases may not have child */ + if (ret) + pr_warn("Doesn't have any child node\n"); + + for_each_node_by_name(slave_node, "slave") { struct cpsw_slave_data *slave_data = data->slave_data + i; - const char *phy_id = NULL; const void *mac_addr = NULL; - - if (of_property_read_string(slave_node, "phy_id", &phy_id)) { + u32 phyid; + int lenp; + const __be32 *parp; + struct device_node *mdio_node; + struct platform_device *mdio; + + parp = of_get_property(slave_node, "phy_id", &lenp); + if ((parp == NULL) && (lenp != (sizeof(void *) * 2))) { pr_err("Missing slave[%d] phy_id property\n", i); ret = -EINVAL; goto error_ret; } - slave_data->phy_id = phy_id; - - if (of_property_read_u32(slave_node, "slave_reg_ofs", &prop)) { - pr_err("Missing slave[%d] slave_reg_ofs property\n", i); - ret = -EINVAL; - goto error_ret; - } - slave_data->slave_reg_ofs = prop; - - if (of_property_read_u32(slave_node, "sliver_reg_ofs", - &prop)) { - pr_err("Missing slave[%d] sliver_reg_ofs property\n", - i); - ret = -EINVAL; - goto error_ret; - } - slave_data->sliver_reg_ofs = prop; + mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); + phyid = be32_to_cpup(parp+1); + mdio = of_find_device_by_node(mdio_node); + snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), + PHY_ID_FMT, mdio->name, phyid); mac_addr = of_get_mac_address(slave_node); if (mac_addr) @@ -876,8 +1144,9 @@ static int __devinit cpsw_probe(struct platform_device *pdev) struct cpsw_priv *priv; struct cpdma_params dma_params; struct cpsw_ale_params ale_params; - void __iomem *regs; + void __iomem *ss_regs, *wr_regs; struct resource *res; + u32 slave_offset, sliver_offset, slave_size; int ret = 0, i, k = 0; ndev = alloc_etherdev(sizeof(struct cpsw_priv)); @@ -895,6 +1164,11 @@ static int __devinit cpsw_probe(struct platform_device *pdev) priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); priv->rx_packet_max = max(rx_packet_max, 128); + /* + * This may be required here for child devices. + */ + pm_runtime_enable(&pdev->dev); + if (cpsw_probe_dt(&priv->data, pdev)) { pr_err("cpsw: platform data missing\n"); ret = -ENODEV; @@ -921,7 +1195,6 @@ static int __devinit cpsw_probe(struct platform_device *pdev) for (i = 0; i < data->slaves; i++) priv->slaves[i].slave_num = i; - pm_runtime_enable(&pdev->dev); priv->clk = clk_get(&pdev->dev, "fck"); if (IS_ERR(priv->clk)) { dev_err(&pdev->dev, "fck is not found\n"); @@ -935,63 +1208,86 @@ static int __devinit cpsw_probe(struct platform_device *pdev) ret = -ENOENT; goto clean_clk_ret; } - if (!request_mem_region(priv->cpsw_res->start, resource_size(priv->cpsw_res), ndev->name)) { dev_err(priv->dev, "failed request i/o region\n"); ret = -ENXIO; goto clean_clk_ret; } - - regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res)); - if (!regs) { + ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res)); + if (!ss_regs) { dev_err(priv->dev, "unable to map i/o region\n"); goto clean_cpsw_iores_ret; } - priv->regs = regs; - priv->host_port = data->host_port_num; - priv->host_port_regs = regs + data->host_port_reg_ofs; + priv->regs = ss_regs; + priv->version = __raw_readl(&priv->regs->id_ver); + priv->host_port = HOST_PORT_NUM; - priv->cpsw_ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (!priv->cpsw_ss_res) { + priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!priv->cpsw_wr_res) { dev_err(priv->dev, "error getting i/o resource\n"); ret = -ENOENT; - goto clean_clk_ret; + goto clean_iomap_ret; } - - if (!request_mem_region(priv->cpsw_ss_res->start, - resource_size(priv->cpsw_ss_res), ndev->name)) { + if (!request_mem_region(priv->cpsw_wr_res->start, + resource_size(priv->cpsw_wr_res), ndev->name)) { dev_err(priv->dev, "failed request i/o region\n"); ret = -ENXIO; - goto clean_clk_ret; + goto clean_iomap_ret; } - - regs = ioremap(priv->cpsw_ss_res->start, - resource_size(priv->cpsw_ss_res)); - if (!regs) { + wr_regs = ioremap(priv->cpsw_wr_res->start, + resource_size(priv->cpsw_wr_res)); + if (!wr_regs) { dev_err(priv->dev, "unable to map i/o region\n"); - goto clean_cpsw_ss_iores_ret; + goto clean_cpsw_wr_iores_ret; } - priv->ss_regs = regs; - - for_each_slave(priv, cpsw_slave_init, priv); + priv->wr_regs = wr_regs; memset(&dma_params, 0, sizeof(dma_params)); + memset(&ale_params, 0, sizeof(ale_params)); + + switch (priv->version) { + case CPSW_VERSION_1: + priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; + priv->cpts.reg = ss_regs + CPSW1_CPTS_OFFSET; + dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; + dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; + ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; + slave_offset = CPSW1_SLAVE_OFFSET; + slave_size = CPSW1_SLAVE_SIZE; + sliver_offset = CPSW1_SLIVER_OFFSET; + dma_params.desc_mem_phys = 0; + break; + case CPSW_VERSION_2: + priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; + priv->cpts.reg = ss_regs + CPSW2_CPTS_OFFSET; + dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; + dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; + ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; + slave_offset = CPSW2_SLAVE_OFFSET; + slave_size = CPSW2_SLAVE_SIZE; + sliver_offset = CPSW2_SLIVER_OFFSET; + dma_params.desc_mem_phys = + (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET; + break; + default: + dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); + ret = -ENODEV; + goto clean_cpsw_wr_iores_ret; + } + for (i = 0; i < priv->data.slaves; i++) { + struct cpsw_slave *slave = &priv->slaves[i]; + cpsw_slave_init(slave, priv, slave_offset, sliver_offset); + slave_offset += slave_size; + sliver_offset += SLIVER_SIZE; + } + dma_params.dev = &pdev->dev; - dma_params.dmaregs = cpsw_dma_regs((u32)priv->regs, - data->cpdma_reg_ofs); - dma_params.rxthresh = cpsw_dma_rxthresh((u32)priv->regs, - data->cpdma_reg_ofs); - dma_params.rxfree = cpsw_dma_rxfree((u32)priv->regs, - data->cpdma_reg_ofs); - dma_params.txhdp = cpsw_dma_txhdp((u32)priv->regs, - data->cpdma_sram_ofs); - dma_params.rxhdp = cpsw_dma_rxhdp((u32)priv->regs, - data->cpdma_sram_ofs); - dma_params.txcp = cpsw_dma_txcp((u32)priv->regs, - data->cpdma_sram_ofs); - dma_params.rxcp = cpsw_dma_rxcp((u32)priv->regs, - data->cpdma_sram_ofs); + dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; + dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; + dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; + dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; + dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; dma_params.num_chan = data->channels; dma_params.has_soft_reset = true; @@ -999,16 +1295,13 @@ static int __devinit cpsw_probe(struct platform_device *pdev) dma_params.desc_mem_size = data->bd_ram_size; dma_params.desc_align = 16; dma_params.has_ext_regs = true; - dma_params.desc_mem_phys = data->no_bd_ram ? 0 : - (u32 __force)priv->cpsw_res->start + data->bd_ram_ofs; - dma_params.desc_hw_addr = data->hw_ram_addr ? - data->hw_ram_addr : dma_params.desc_mem_phys ; + dma_params.desc_hw_addr = dma_params.desc_mem_phys; priv->dma = cpdma_ctlr_create(&dma_params); if (!priv->dma) { dev_err(priv->dev, "error initializing dma\n"); ret = -ENOMEM; - goto clean_iomap_ret; + goto clean_wr_iomap_ret; } priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), @@ -1022,10 +1315,7 @@ static int __devinit cpsw_probe(struct platform_device *pdev) goto clean_dma_ret; } - memset(&ale_params, 0, sizeof(ale_params)); ale_params.dev = &ndev->dev; - ale_params.ale_regs = (void *)((u32)priv->regs) + - ((u32)data->ale_reg_ofs); ale_params.ale_ageout = ale_ageout; ale_params.ale_entries = data->ale_entries; ale_params.ale_ports = data->slaves; @@ -1072,6 +1362,10 @@ static int __devinit cpsw_probe(struct platform_device *pdev) goto clean_irq_ret; } + if (cpts_register(&pdev->dev, &priv->cpts, + data->cpts_clock_mult, data->cpts_clock_shift)) + dev_err(priv->dev, "error registering cpts device\n"); + cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n", priv->cpsw_res->start, ndev->irq); @@ -1085,11 +1379,13 @@ clean_dma_ret: cpdma_chan_destroy(priv->txch); cpdma_chan_destroy(priv->rxch); cpdma_ctlr_destroy(priv->dma); +clean_wr_iomap_ret: + iounmap(priv->wr_regs); +clean_cpsw_wr_iores_ret: + release_mem_region(priv->cpsw_wr_res->start, + resource_size(priv->cpsw_wr_res)); clean_iomap_ret: iounmap(priv->regs); -clean_cpsw_ss_iores_ret: - release_mem_region(priv->cpsw_ss_res->start, - resource_size(priv->cpsw_ss_res)); clean_cpsw_iores_ret: release_mem_region(priv->cpsw_res->start, resource_size(priv->cpsw_res)); @@ -1111,6 +1407,7 @@ static int __devexit cpsw_remove(struct platform_device *pdev) pr_info("removing device"); platform_set_drvdata(pdev, NULL); + cpts_unregister(&priv->cpts); free_irq(ndev->irq, priv); cpsw_ale_destroy(priv->ale); cpdma_chan_destroy(priv->txch); @@ -1119,8 +1416,9 @@ static int __devexit cpsw_remove(struct platform_device *pdev) iounmap(priv->regs); release_mem_region(priv->cpsw_res->start, resource_size(priv->cpsw_res)); - release_mem_region(priv->cpsw_ss_res->start, - resource_size(priv->cpsw_ss_res)); + iounmap(priv->wr_regs); + release_mem_region(priv->cpsw_wr_res->start, + resource_size(priv->cpsw_wr_res)); pm_runtime_disable(&pdev->dev); clk_put(priv->clk); kfree(priv->slaves); |