tristate "Intel(R) PRO/1000 PCI-Express Gigabit Ethernet support"

depends on PCI && (!SPARC32 || BROKEN)

select CRC32

---help---

This driver supports the PCI-Express Intel(R) PRO/1000 gigabit

ethernet family of adapters. For PCI or PCI-X e1000 adapters,

config IGB

tristate "Intel(R) 82575/82576 PCI-Express Gigabit Ethernet support"

depends on PCI

select I2C

select I2C_ALGOBIT

---help---

tristate "Intel(R) 10GbE PCI Express adapters support"

depends on PCI

select MDIO

---help---

This driver supports Intel(R) 10GbE PCI Express family of

adapters. For more information on how to identify your adapter, go

config I40E

tristate "Intel(R) Ethernet Controller XL710 Family support"

depends on PCI

---help---

This driver supports Intel(R) Ethernet Controller XL710 Family of

tristate "Intel(R) FM10000 Ethernet Switch Host Interface Support"

default n

depends on PCI_MSI

---help---

This driver supports Intel(R) FM10000 Ethernet Switch Host

Interface. For more information on how to identify your adapter,

return 0;

}

static int e100_asf(struct nic *nic)

{

/* ASF can be enabled from eeprom */

.ndo_validate_addr = eth_validate_addr,

.ndo_set_rx_mode = e100_set_multicast_list,

.ndo_set_mac_address = e100_set_mac_address,

.ndo_do_ioctl = e100_do_ioctl,

.ndo_tx_timeout = e100_tx_timeout,

#ifdef CONFIG_NET_POLL_CONTROLLER

hw->subsystem_vendor_id != PCI_VENDOR_ID_VMWARE)

netdev->priv_flags |= IFF_UNICAST_FLT;

adapter->en_mng_pt = e1000_enable_mng_pass_thru(hw);

/* initialize eeprom parameters */

{

struct e1000_adapter *adapter = netdev_priv(netdev);

struct e1000_hw *hw = &adapter->hw;

/* Adapter-specific max frame size limits. */

switch (hw->mac_type) {

{

struct e1000_adapter *adapter = netdev_priv(netdev);

enable_irq(adapter->pdev->irq);

}

#endif

/**

* e1000e_sanitize_systim - sanitize raw cycle counter reads

* @hw: pointer to the HW structure

*

* Errata for 82574/82583 possible bad bits read from SYSTIMH/L:

* check to see that the time is incrementing at a reasonable

* rate and is a multiple of incvalue.

**/

{

u64 time_delta, rem, temp;

u32 incvalue;

int i;

incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;

for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {

/* latch SYSTIMH on read of SYSTIML */

time_delta = systim_next - systim;

temp = time_delta;

* e1000e_cyclecounter_read - read raw cycle counter (used by time counter)

* @cc: cyclecounter structure

**/

{

struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,

cc);

struct e1000_hw *hw = &adapter->hw;

u32 systimel, systimeh;

/* SYSTIMH latching upon SYSTIML read does not work well.

* This means that if SYSTIML overflows after we read it but before

* we read SYSTIMH, the value of SYSTIMH has been incremented and we

systimel = systimel_2;

}

}

if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW)

systim = e1000e_sanitize_systim(hw, systim);

int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;

/* Jumbo frame support */

!(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {

e_err("Jumbo Frames not supported.\n");

return -EINVAL;

}

/* Jumbo frame workaround on 82579 and newer requires CRC be stripped */

if ((adapter->hw.mac.type >= e1000_pch2lan) &&

!(adapter->flags2 & FLAG2_CRC_STRIPPING) &&

e1000_intr_msix(adapter->pdev->irq, netdev);

break;

case E1000E_INT_MODE_MSI:

enable_irq(adapter->pdev->irq);

break;

default: /* E1000E_INT_MODE_LEGACY */

enable_irq(adapter->pdev->irq);

break;

}

netdev->vlan_features |= NETIF_F_HIGHDMA;

}

if (e1000e_enable_mng_pass_thru(&adapter->hw))

adapter->flags |= FLAG_MNG_PT_ENABLED;

unsigned long flags;

int i;

u32 tsync_ctrl;

tsync_ctrl = er32(TSYNCTXCTL);

tsync_ctrl |= E1000_TSYNCTXCTL_START_SYNC |

return err;

}

/**

* fm10k_tx_timeout - Respond to a Tx Hang

* @netdev: network interface device structure

.ndo_validate_addr = eth_validate_addr,

.ndo_start_xmit = fm10k_xmit_frame,

.ndo_set_mac_address = fm10k_set_mac,

.ndo_tx_timeout = fm10k_tx_timeout,

.ndo_vlan_rx_add_vid = fm10k_vlan_rx_add_vid,

.ndo_vlan_rx_kill_vid = fm10k_vlan_rx_kill_vid,

dev->hw_features |= hw_features;

return dev;

}

#include <linux/iommu.h>

#include <linux/slab.h>

#include <linux/list.h>

#include <linux/string.h>

#include <linux/in.h>

#include <linux/ip.h>

#define I40E_FLAG_NO_DCB_SUPPORT BIT_ULL(45)

#define I40E_FLAG_USE_SET_LLDP_MIB BIT_ULL(46)

#define I40E_FLAG_STOP_FW_LLDP BIT_ULL(47)

#define I40E_FLAG_PF_MAC BIT_ULL(50)

#define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT_ULL(51)

/* tracks features that get auto disabled by errors */

u64 auto_disable_flags;

struct ptp_clock_info ptp_caps;

struct sk_buff *ptp_tx_skb;

struct hwtstamp_config tstamp_config;

u64 ptp_base_adj;

u32 tx_hwtstamp_timeouts;

u32 rx_hwtstamp_cleared;

bool ptp_tx;

bool ptp_rx;

u16 rss_table_size; /* HW RSS table size */

u16 phy_led_val;

};

enum i40e_filter_state {

I40E_FILTER_INVALID = 0, /* Invalid state */

I40E_FILTER_NEW, /* New, not sent to FW yet */

/* There is no 'removed' state; the filter struct is freed */

};

struct i40e_mac_filter {

u8 macaddr[ETH_ALEN];

#define I40E_VLAN_ANY -1

s16 vlan;

enum i40e_filter_state state;

};

#define I40E_VSI_FLAG_VEB_OWNER BIT(1)

unsigned long flags;

/* VSI stats */

struct rtnl_link_stats64 net_stats;

u16 veb_idx; /* index of VEB parent */

struct kobject *kobj; /* sysfs object */

bool current_isup; /* Sync 'link up' logging */

void *priv; /* client driver data reference. */

unsigned long hung_detected; /* Set/Reset for hung_detection logic */

cpumask_t affinity_mask;

struct rcu_head rcu; /* to avoid race with update stats on free */

char name[I40E_INT_NAME_STR_LEN];

bool arm_wb_state;

void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,

u16 rss_table_size, u16 rss_size);

struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);

void i40e_update_stats(struct i40e_vsi *vsi);

void i40e_update_eth_stats(struct i40e_vsi *vsi);

struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);

bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);

void i40e_set_ethtool_ops(struct net_device *netdev);

struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,

int i40e_sync_vsi_filters(struct i40e_vsi *vsi);

struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,

u16 uplink, u32 param1);

int i40e_vsi_release(struct i40e_vsi *vsi);

#ifdef I40E_FCOE

void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,

struct i40e_vsi_context *ctxt,

void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,

u8 *msg, u16 len);

int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);

struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,

u16 downlink_seid, u8 enabled_tc);

int i40e_close(struct net_device *netdev);

int i40e_vsi_open(struct i40e_vsi *vsi);

void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);

int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid);

bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);

#ifdef I40E_FCOE

int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,

struct tc_to_netdev *tc);

desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);

desc_idx = ntc;

flags = le16_to_cpu(desc->flags);

if (flags & I40E_AQ_FLAG_ERR) {

ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;

i40e_debug(hw,

I40E_DEBUG_AQ_MESSAGE,

"AQRX: Event received with error 0x%X.\n",

I40E_PHY_TYPE_1000BASE_LX = 0x1C,

I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,

I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,

I40E_PHY_TYPE_MAX

};

#define I40E_LINK_SPEED_10GB_SHIFT 0x3

#define I40E_LINK_SPEED_40GB_SHIFT 0x4

#define I40E_LINK_SPEED_20GB_SHIFT 0x5

enum i40e_aq_link_speed {

I40E_LINK_SPEED_UNKNOWN = 0,

I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT),

I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT),

I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT),

};

struct i40e_aqc_module_desc {

#define I40E_AQ_PHY_LINK_ENABLED 0x08

#define I40E_AQ_PHY_AN_ENABLED 0x10

#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20

__le16 eee_capability;

#define I40E_AQ_EEE_100BASE_TX 0x0002

#define I40E_AQ_EEE_1000BASE_T 0x0004

__le32 eeer_val;

u8 d3_lpan;

#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01

u8 phy_id[4];

u8 module_type[3];

u8 qualified_module_count;

__le16 eee_capability;

__le32 eeer;

u8 low_power_ctrl;

};

I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);

#define I40E_AQ_LINK_TX_DRAINED 0x01

#define I40E_AQ_LINK_TX_FLUSHED 0x03

#define I40E_AQ_LINK_FORCED_40G 0x10

u8 loopback; /* use defines from i40e_aqc_set_lb_mode */

__le16 max_frame_size;

u8 config;

#define I40E_AQ_CONFIG_CRC_ENA 0x04

#define I40E_AQ_CONFIG_PACING_MASK 0x78

u8 external_power_ability;

}

cdev->client->ops->close(&cdev->lan_info, cdev->client,

reset);

i40e_client_release_qvlist(&cdev->lan_info);

}

}

}

/**

* i40e_client_add_instance - add a client instance struct to the instance list

* @pf: pointer to the board struct

* @client: pointer to a client struct in the client list.

if (test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))

continue;

} else {

client->name);

}

continue;

if (!existing) {

dev_info(&pf->pdev->dev, "Added instance of Client %s to PF%d bus=0x%02x func=0x%02x\n",

client->name, pf->hw.pf_id,

pf->hw.bus.device, pf->hw.bus.func);

}

mutex_lock(&i40e_client_instance_mutex);

}

mutex_unlock(&i40e_client_instance_mutex);

}

continue;

pf = (struct i40e_pf *)cdev->lan_info.pf;

if (test_bit(__I40E_CLIENT_INSTANCE_OPENED, &cdev->state)) {

if (client->ops && client->ops->close)

client->ops->close(&cdev->lan_info, client,

false);

}

/* delete the client instance from the list */

list_move(&cdev->list, &cdevs_tmp);

dev_info(&pf->pdev->dev, "Deleted client instance of Client %s\n",

client->name);

}

mutex_unlock(&i40e_client_instance_mutex);

/* free the client device and release its vsi */

ret = -ENODEV;

goto out;

}

out:

mutex_unlock(&i40e_client_mutex);

return ret;

struct i40e_info lan_info;

struct i40e_client *client;

unsigned long state;

};

struct i40e_client {

case I40E_DEV_ID_10G_BASE_T4:

case I40E_DEV_ID_20G_KR2:

case I40E_DEV_ID_20G_KR2_A:

hw->mac.type = I40E_MAC_XL710;

break;

case I40E_DEV_ID_KX_X722:

case I40E_PHY_TYPE_1000BASE_LX:

case I40E_PHY_TYPE_40GBASE_SR4:

case I40E_PHY_TYPE_40GBASE_LR4:

media = I40E_MEDIA_TYPE_FIBER;

break;

case I40E_PHY_TYPE_100BASE_TX:

case I40E_PHY_TYPE_10GBASE_SFPP_CU:

case I40E_PHY_TYPE_40GBASE_AOC:

case I40E_PHY_TYPE_10GBASE_AOC:

media = I40E_MEDIA_TYPE_DA;

break;

case I40E_PHY_TYPE_1000BASE_KX:

case I40E_PHY_TYPE_10GBASE_KR:

case I40E_PHY_TYPE_40GBASE_KR4:

case I40E_PHY_TYPE_20GBASE_KR2:

media = I40E_MEDIA_TYPE_BACKPLANE;

break;

case I40E_PHY_TYPE_SGMII:

if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)

status = I40E_ERR_UNKNOWN_PHY;

hw->phy.phy_types = le32_to_cpu(abilities->phy_type);

return status;

}

config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;

/* Copy over all the old settings */

config.phy_type = abilities.phy_type;

config.link_speed = abilities.link_speed;

config.eee_capability = abilities.eee_capability;

config.eeer = abilities.eeer_val;

config.low_power_ctrl = abilities.d3_lpan;

status = i40e_aq_set_phy_config(hw, &config, NULL);

if (status)

else

hw_link_info->crc_enable = false;

hw_link_info->lse_enable = true;

else

hw_link_info->lse_enable = false;

hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)

hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;

}

/**

* i40e_aq_set_vsi_broadcast

* @hw: pointer to the hw struct

* @seid: vsi number

if (status)

return status;

status = i40e_aq_get_phy_capabilities(hw, false, false,

&abilities, NULL);

if (status)

break;

case I40E_AQ_CAP_ID_MNG_MODE:

p->management_mode = number;

break;

case I40E_AQ_CAP_ID_NPAR_ACTIVE:

p->npar_enable = number;

/* partition id is 1-based, and functions are evenly spread

* across the ports as partitions

*/

/* additional HW specific goodies that might

* someday be HW version specific

}

/**

* @hw: pointer to the HW structure

* @page: registers page number

* @reg: register address in the page

*

* Reads specified PHY register value

**/

{

i40e_status status = I40E_ERR_TIMEOUT;

u32 command = 0;

command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |

(page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |

(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |

(I40E_GLGEN_MSCA_MDICMD_MASK) |

(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);

wr32(hw, I40E_GLGEN_MSCA(port_num), command);

command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |

(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |

(I40E_GLGEN_MSCA_MDICMD_MASK) |

(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);

status = I40E_ERR_TIMEOUT;

}

/**

* @hw: pointer to the HW structure

* @page: registers page number

* @reg: register address in the page

*

* Writes value to specified PHY register

**/

{

i40e_status status = I40E_ERR_TIMEOUT;

u32 command = 0;

command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |

(page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |

(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |

(I40E_GLGEN_MSCA_MDICMD_MASK) |

(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);

wr32(hw, I40E_GLGEN_MSCA(port_num), command);

command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |

(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |

(I40E_GLGEN_MSCA_MDICMD_MASK) |

(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);

status = I40E_ERR_TIMEOUT;

}

/**

* i40e_get_phy_address

* @hw: pointer to the HW structure

* @dev_num: PHY port num that address we want

for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,

led_addr++) {

if (status)

goto phy_blinking_end;

led_ctl = led_reg;

if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {

led_reg = 0;

I40E_PHY_COM_REG_PAGE,

led_addr, phy_addr,

led_reg);

if (time > 0 && interval > 0) {

for (i = 0; i < time * 1000; i += interval) {

if (status)

goto restore_config;

if (led_reg & I40E_PHY_LED_MANUAL_ON)

led_reg = 0;

else

led_reg = I40E_PHY_LED_MANUAL_ON;

if (status)

goto restore_config;

msleep(interval);

}

restore_config:

phy_blinking_end:

return status;

for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,

temp_addr++) {

if (status)

return status;

*val = reg_val;

i = rd32(hw, I40E_PFGEN_PORTNUM);

port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);

phy_addr = i40e_get_phy_address(hw, port_num);

if (status)

return status;

led_ctl = led_reg;

if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {

led_reg = 0;

if (status)

return status;

}

if (status)

goto restore_config;

if (on)

led_reg = I40E_PHY_LED_MANUAL_ON;

else

led_reg = 0;

if (status)

goto restore_config;

if (mode & I40E_PHY_LED_MODE_ORIG) {

led_ctl = (mode & I40E_PHY_LED_MODE_MASK);

I40E_PHY_COM_REG_PAGE,

led_addr, phy_addr, led_ctl);

}

return status;

restore_config:

return status;

}

struct rtnl_link_stats64 *nstat;

struct i40e_mac_filter *f;

struct i40e_vsi *vsi;

vsi = i40e_dbg_find_vsi(pf, seid);

if (!vsi) {

pf->hw.mac.addr,

pf->hw.mac.san_addr,

pf->hw.mac.port_addr);

dev_info(&pf->pdev->dev,

}

vsi->active_filters, vsi->promisc_threshold,

(test_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state) ?

"ON" : "OFF"));

dev_info(&pf->pdev->dev, "deleting relay %d\n", veb_seid);

i40e_veb_release(pf->veb[i]);

} else if (strncmp(cmd_buf, "add pvid", 8) == 0) {

i40e_status ret;

u16 vid;

dev_info(&pf->pdev->dev,

"dump debug fwdata <cluster_id> <table_id> <index>\n");

}

} else if (strncmp(cmd_buf, "pfr", 3) == 0) {

dev_info(&pf->pdev->dev, "debugfs: forcing PFR\n");

i40e_do_reset_safe(pf, BIT(__I40E_PF_RESET_REQUESTED));

dev_info(&pf->pdev->dev, " del vsi [vsi_seid]\n");

dev_info(&pf->pdev->dev, " add relay <uplink_seid> <vsi_seid>\n");

dev_info(&pf->pdev->dev, " del relay <relay_seid>\n");

dev_info(&pf->pdev->dev, " add pvid <vsi_seid> <vid>\n");

dev_info(&pf->pdev->dev, " del pvid <vsi_seid>\n");

dev_info(&pf->pdev->dev, " dump switch\n");

dev_info(&pf->pdev->dev, " dump desc aq\n");

dev_info(&pf->pdev->dev, " dump reset stats\n");

dev_info(&pf->pdev->dev, " dump debug fwdata <cluster_id> <table_id> <index>\n");

dev_info(&pf->pdev->dev, " read <reg>\n");

dev_info(&pf->pdev->dev, " write <reg> <value>\n");

dev_info(&pf->pdev->dev, " clear_stats vsi [seid]\n");

#define I40E_DEV_ID_20G_KR2 0x1587

#define I40E_DEV_ID_20G_KR2_A 0x1588

#define I40E_DEV_ID_10G_BASE_T4 0x1589

#define I40E_DEV_ID_KX_X722 0x37CE

#define I40E_DEV_ID_QSFP_X722 0x37CF

#define I40E_DEV_ID_SFP_X722 0x37D0

* The PF_STATs are appended to the netdev stats only when ethtool -S

* is queried on the base PF netdev, not on the VMDq or FCoE netdev.

*/

I40E_PF_STAT("rx_bytes", stats.eth.rx_bytes),

I40E_PF_STAT("tx_bytes", stats.eth.tx_bytes),

I40E_PF_STAT("rx_unicast", stats.eth.rx_unicast),

I40E_ETH_TEST_REG = 0,

I40E_ETH_TEST_EEPROM,

I40E_ETH_TEST_INTR,

I40E_ETH_TEST_LINK,

};

"Register test (offline)",

"Eeprom test (offline)",

"Interrupt test (offline)",

"Link test (on/offline)"

};

#define I40E_TEST_LEN (sizeof(i40e_gstrings_test) / ETH_GSTRING_LEN)

"MFP",

"LinkPolling",

"flow-director-atr",

"veb-stats",

"hw-atr-eviction",

};

};

/**

* i40e_partition_setting_complaint - generic complaint for MFP restriction

static void i40e_phy_type_to_ethtool(struct i40e_pf *pf, u32 *supported,

u32 *advertising)

{

struct i40e_link_status *hw_link_info = &pf->hw.phy.link_info;

*supported = 0x0;

*advertising = 0x0;

*advertising |= ADVERTISED_20000baseKR2_Full;

}

if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_KR) {

*advertising |= ADVERTISED_Autoneg;

if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)

}

if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_KX4) {

*supported |= SUPPORTED_10000baseKX4_Full |

*advertising |= ADVERTISED_10000baseKX4_Full;

}

if (phy_types & I40E_CAP_PHY_TYPE_1000BASE_KX) {

*advertising |= ADVERTISED_Autoneg;

if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)

}

}

ADVERTISED_1000baseKX_Full |

ADVERTISED_Autoneg;

break;

default:

/* if we got here and link is up something bad is afoot */

netdev_info(netdev, "WARNING: Link is up but PHY type 0x%x is not recognized.\n",

case I40E_LINK_SPEED_40GB:

ethtool_cmd_speed_set(ecmd, SPEED_40000);

break;

case I40E_LINK_SPEED_20GB:

ethtool_cmd_speed_set(ecmd, SPEED_20000);

break;

{

struct i40e_netdev_priv *np = netdev_priv(netdev);

struct i40e_pf *pf = np->vsi->back;

return pf->msg_enable;

}

if (I40E_DEBUG_USER & data)

pf->hw.debug_mask = data;

}

static int i40e_get_regs_len(struct net_device *netdev)

sizeof(drvinfo->fw_version));

strlcpy(drvinfo->bus_info, pci_name(pf->pdev),

sizeof(drvinfo->bus_info));

if (pf->hw.pf_id == 0)

}

static void i40e_get_ringparam(struct net_device *netdev,

{

struct i40e_ring *tx_rings = NULL, *rx_rings = NULL;

struct i40e_netdev_priv *np = netdev_priv(netdev);

struct i40e_vsi *vsi = np->vsi;

struct i40e_pf *pf = vsi->back;

u32 new_rx_count, new_tx_count;

}

for (i = 0; i < vsi->num_queue_pairs; i++) {

struct i40e_ring *ring;

u16 unused;

*/

rx_rings[i].desc = NULL;

rx_rings[i].rx_bi = NULL;

err = i40e_setup_rx_descriptors(&rx_rings[i]);

if (err)

goto rx_unwind;

return I40E_VSI_STATS_LEN(netdev);

}

case ETH_SS_PRIV_FLAGS:

default:

return -EOPNOTSUPP;

}

switch (stringset) {

case ETH_SS_TEST:

break;

case ETH_SS_STATS:

for (i = 0; i < I40E_NETDEV_STATS_LEN; i++) {

/* BUG_ON(p - data != I40E_STATS_LEN * ETH_GSTRING_LEN); */

break;

case ETH_SS_PRIV_FLAGS:

break;

default:

break;

info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);

info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |

return 0;

}

return *data;

}

static inline bool i40e_active_vfs(struct i40e_pf *pf)

{

struct i40e_vf *vfs = pf->vf;

static inline bool i40e_active_vmdqs(struct i40e_pf *pf)

{

}

static void i40e_diag_test(struct net_device *netdev,

data[I40E_ETH_TEST_REG] = 1;

data[I40E_ETH_TEST_EEPROM] = 1;

data[I40E_ETH_TEST_INTR] = 1;

data[I40E_ETH_TEST_LINK] = 1;

eth_test->flags |= ETH_TEST_FL_FAILED;

clear_bit(__I40E_TESTING, &pf->state);

if (i40e_intr_test(netdev, &data[I40E_ETH_TEST_INTR]))

eth_test->flags |= ETH_TEST_FL_FAILED;

/* run reg test last, a reset is required after it */

if (i40e_reg_test(netdev, &data[I40E_ETH_TEST_REG]))

eth_test->flags |= ETH_TEST_FL_FAILED;

data[I40E_ETH_TEST_REG] = 0;

data[I40E_ETH_TEST_EEPROM] = 0;

data[I40E_ETH_TEST_INTR] = 0;

}

skip_ol_tests:

switch (state) {

case ETHTOOL_ID_ACTIVE:

pf->led_status = i40e_led_get(hw);

} else {

i40e_aq_set_phy_debug(hw, I40E_PHY_DEBUG_ALL, NULL);

}

return blink_freq;

case ETHTOOL_ID_ON:

i40e_led_set(hw, 0xf, false);

else

ret = i40e_led_set_phy(hw, true, pf->led_status, 0);

break;

case ETHTOOL_ID_OFF:

i40e_led_set(hw, 0x0, false);

else

ret = i40e_led_set_phy(hw, false, pf->led_status, 0);

break;

case ETHTOOL_ID_INACTIVE:

} else {

ret = i40e_led_set_phy(hw, false, pf->led_status,

(pf->phy_led_val |

* same PCI function.

*/

netdev->dev_port = 1;

/* use san mac */

ether_addr_copy(netdev->dev_addr, hw->mac.san_addr);

#define DRV_VERSION_MAJOR 1

#define DRV_VERSION_MINOR 6

#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \

__stringify(DRV_VERSION_MINOR) "." \

__stringify(DRV_VERSION_BUILD) DRV_KERN

{PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_I_X722), 0},

{PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},

{PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},

/* required last entry */

{0, }

};

#define I40E_MAX_VF_COUNT 128

static int debug = -1;

MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");

MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");

void i40e_service_event_schedule(struct i40e_pf *pf)

{

if (!test_bit(__I40E_DOWN, &pf->state) &&

queue_work(i40e_wq, &pf->service_task);

}

* @vsi: the VSI to be searched

* @macaddr: the MAC address

* @vlan: the vlan

*

* Returns ptr to the filter object or NULL

**/

static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,

{

struct i40e_mac_filter *f;

if (!vsi || !macaddr)

return NULL;

if ((ether_addr_equal(macaddr, f->macaddr)) &&

return f;

}

return NULL;

* i40e_find_mac - Find a mac addr in the macvlan filters list

* @vsi: the VSI to be searched

* @macaddr: the MAC address we are searching for

*

* Returns the first filter with the provided MAC address or NULL if

* MAC address was not found

**/

{

struct i40e_mac_filter *f;

if (!vsi || !macaddr)

return NULL;

return f;

}

return NULL;

**/

bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)

{

*/

}

/**

*

*

{

}

}

}

/**

* @vsi: the VSI to be searched

* @macaddr: the MAC address

* @vlan: the vlan

*

* Returns ptr to the filter object or NULL when no memory available.

*

* being held.

**/

struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,

{

struct i40e_mac_filter *f;

if (!vsi || !macaddr)

return NULL;

if (!f) {

f = kzalloc(sizeof(*f), GFP_ATOMIC);

if (!f)

ether_addr_copy(f->macaddr, macaddr);

f->vlan = vlan;

f->state = I40E_FILTER_FAILED;

else

f->state = I40E_FILTER_NEW;

vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;

vsi->back->flags |= I40E_FLAG_FILTER_SYNC;

}

return f;

}

/**

* @vsi: the VSI to be searched

* @macaddr: the MAC address

*

* being held.

* ANOTHER NOTE: This function MUST be called from within the context of

* the "safe" variants of any list iterators, e.g. list_for_each_entry_safe()

* instead of list_for_each_entry().

**/

{

struct i40e_mac_filter *f;

if (!vsi || !macaddr)

return;

}

}

}

}

/**

else

netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);

ether_addr_copy(netdev->dev_addr, addr->sa_data);

if (vsi->type == I40E_VSI_MAIN) {

i40e_status ret;

}

/**

* i40e_set_rx_mode - NDO callback to set the netdev filters

* @netdev: network interface device structure

**/

#endif

{

struct i40e_netdev_priv *np = netdev_priv(netdev);

struct i40e_vsi *vsi = np->vsi;

/* check for other flag changes */

if (vsi->current_netdev_flags != vsi->netdev->flags) {

}

/**

* @from: Pointer to list which contains MAC filter entries - changes to

* those entries needs to be undone.

*

**/

{

/* Move the element back into MAC filter list*/

}

}

* @count: Number of filters added

* @add_list: return data from fw

* @head: pointer to first filter in current batch

*

* MAC filter entries from list were slated to be added to device. Returns

* number of successful filters. Note that 0 does NOT mean success!

static int

i40e_update_filter_state(int count,

struct i40e_aqc_add_macvlan_element_data *add_list,

{

int retval = 0;

int i;

*/

add_head->state = I40E_FILTER_FAILED;

}

}

return retval;

}

/**

* i40e_sync_vsi_filters - Update the VSI filter list to the HW

* @vsi: ptr to the VSI

*

**/

int i40e_sync_vsi_filters(struct i40e_vsi *vsi)

{

struct i40e_hw *hw = &vsi->back->hw;

bool promisc_changed = false;

char vsi_name[16] = "PF";

int filter_list_len = 0;

i40e_status aq_ret = 0;

struct i40e_pf *pf;

int num_add = 0;

int num_del = 0;

u16 cmd_flags;

int list_size;

/* empty array typed pointers, kcalloc later */

struct i40e_aqc_add_macvlan_element_data *add_list;

vsi->current_netdev_flags = vsi->netdev->flags;

}

if (vsi->type == I40E_VSI_SRIOV)

snprintf(vsi_name, sizeof(vsi_name) - 1, "VF %d", vsi->vf_id);

if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {

vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;

/* Create a list of filters to delete. */

if (f->state == I40E_FILTER_REMOVE) {

/* Move the element into temporary del_list */

}

if (f->state == I40E_FILTER_NEW) {

}

}

}

/* Now process 'del_list' outside the lock */

filter_list_len = hw->aq.asq_buf_size /

sizeof(struct i40e_aqc_remove_macvlan_element_data);

list_size = filter_list_len *

sizeof(struct i40e_aqc_remove_macvlan_element_data);

del_list = kzalloc(list_size, GFP_ATOMIC);

cmd_flags = 0;

/* add to delete list */

ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);

if (f->vlan == I40E_VLAN_ANY) {

/* flush a full buffer */

if (num_del == filter_list_len) {

memset(del_list, 0, list_size);

}

/* Release memory for MAC filter entries which were

* synced up with HW.

*/

kfree(f);

}

if (num_del) {

}

kfree(del_list);

del_list = NULL;

}

/* Do all the adds now. */

filter_list_len = hw->aq.asq_buf_size /

sizeof(struct i40e_aqc_add_macvlan_element_data);

list_size = filter_list_len *

sizeof(struct i40e_aqc_add_macvlan_element_data);

add_list = kzalloc(list_size, GFP_ATOMIC);

num_add = 0;

if (test_bit(__I40E_FILTER_OVERFLOW_PROMISC,

&vsi->state)) {

f->state = I40E_FILTER_FAILED;

continue;

}

/* add to add array */

if (num_add == 0)

add_head = f;

cpu_to_le16((u16)(f->vlan));

}

add_list[num_add].queue_number = 0;

cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;

add_list[num_add].flags = cpu_to_le16(cmd_flags);

num_add++;

/* flush a full buffer */

if (num_add == filter_list_len) {

memset(add_list, 0, list_size);

num_add = 0;

}

}

if (num_add) {

}

/* Now move all of the filters from the temp add list back to

* the VSI's list.

*/

}

kfree(add_list);

add_list = NULL;

}

if (test_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state) &&

(vsi->active_filters < vsi->promisc_threshold)) {

}

/* if the VF is not trusted do not do promisc */

clear_bit(__I40E_CONFIG_BUSY, &vsi->state);

return retval;

}

/**

static int i40e_change_mtu(struct net_device *netdev, int new_mtu)

{

struct i40e_netdev_priv *np = netdev_priv(netdev);

struct i40e_vsi *vsi = np->vsi;

netdev_info(netdev, "changing MTU from %d to %d\n",

netdev->mtu, new_mtu);

netdev->mtu = new_mtu;

}

/**

* @vsi: the vsi being configured

* @vid: vlan id to be added (0 = untagged only , -1 = any)

**/

{

if (!add_f) {

dev_info(&vsi->back->pdev->dev,

"Could not add vlan filter %d for %pM\n",

vid, f->macaddr);

return -ENOMEM;

}

}

/* schedule our worker thread which will take care of

* applying the new filter changes

}

/**

* @vsi: the vsi being configured

* @vid: vlan id to be removed (0 = untagged only , -1 = any)

*

{

}

/* schedule our worker thread which will take care of

* applying the new filter changes

*/

i40e_service_event_schedule(vsi->back);

}

/**

struct i40e_vsi *vsi = np->vsi;

int ret = 0;

return -EINVAL;

/* If the network stack called us with vid = 0 then

if (vid)

ret = i40e_vsi_add_vlan(vsi, vid);

set_bit(vid, vsi->active_vlans);

return ret;

}

/**

* i40e_vsi_request_irq_msix - Initialize MSI-X interrupts

* @vsi: the VSI being configured

* @basename: name for the vector

int rx_int_idx = 0;

int tx_int_idx = 0;

int vector, err;

for (vector = 0; vector < q_vectors; vector++) {

struct i40e_q_vector *q_vector = vsi->q_vectors[vector];

if (q_vector->tx.ring && q_vector->rx.ring) {

snprintf(q_vector->name, sizeof(q_vector->name) - 1,

"%s-%s-%d", basename, "TxRx", rx_int_idx++);

/* skip this unused q_vector */

continue;

}

vsi->irq_handler,

0,

q_vector->name,

"MSIX request_irq failed, error: %d\n", err);

goto free_queue_irqs;

}

/* assign the mask for this irq */

}

vsi->irqs_ready = true;

free_queue_irqs:

while (vector) {

vector--;

}

return err;

}

(ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {

ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;

icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;

}

/* only q0 is used in MSI/Legacy mode, and none are used in MSIX */

}

/**

* @vsi: the VSI being configured

**/

{

int ret = 0;

/* do rx first for enable and last for disable */

return ret;

}

/**

* i40e_vsi_free_irq - Free the irq association with the OS

* @vsi: the VSI being configured

**/

vsi->irqs_ready = false;

for (i = 0; i < vsi->num_q_vectors; i++) {

/* free only the irqs that were actually requested */

if (!vsi->q_vectors[i] ||

!vsi->q_vectors[i]->num_ringpairs)

continue;

/* clear the affinity_mask in the IRQ descriptor */

/* Tear down the interrupt queue link list

*

*/

void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)

{

char *speed = "Unknown";

char *fc = "Unknown";

return;

vsi->current_isup = isup;

if (!isup) {

netdev_info(vsi->netdev, "NIC Link is Down\n");

return;

case I40E_LINK_SPEED_20GB:

speed = "20 G";

break;

case I40E_LINK_SPEED_10GB:

speed = "10 G";

break;

i40e_configure_msi_and_legacy(vsi);

/* start rings */

if (err)

return err;

netif_tx_disable(vsi->netdev);

}

i40e_vsi_disable_irq(vsi);

i40e_napi_disable_all(vsi);

for (i = 0; i < vsi->num_queue_pairs; i++) {

}

/**

* i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters

* @pf: board private structure

**/

static void i40e_fdir_sb_setup(struct i40e_pf *pf)

{

struct i40e_vsi *vsi;

/* quick workaround for an NVM issue that leaves a critical register

* uninitialized

0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,

0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,

0x95b3a76d};

for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)

wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);

return;

/* find existing VSI and see if it needs configuring */

/* create a new VSI if none exists */

if (!vsi) {

**/

static void i40e_fdir_teardown(struct i40e_pf *pf)

{

i40e_fdir_filter_exit(pf);

}

/**

/* don't bother with service tasks if a reset is in progress */

if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {

return;

}

i40e_detect_recover_hung(pf);

i40e_sync_filters_subtask(pf);

i40e_reset_subtask(pf);

i40e_sync_udp_filters_subtask(pf);

i40e_clean_adminq_subtask(pf);

/* If the tasks have taken longer than one timer cycle or there

* is more work to be done, reschedule the service task now

pf->rss_table_size : 64;

vsi->netdev_registered = false;

vsi->work_limit = I40E_DEFAULT_IRQ_WORK;

vsi->irqs_ready = false;

ret = i40e_set_num_rings_in_vsi(vsi);

i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);

/* Initialize VSI lock */

pf->vsi[vsi_idx] = vsi;

ret = vsi_idx;

goto unlock_pf;

i40e_pf_config_rss(pf);

}

return pf->alloc_rss_size;

}

int err = 0;

int size;

/* Set default capability flags */

pf->flags = I40E_FLAG_RX_CSUM_ENABLED |

I40E_FLAG_MSI_ENABLED |

I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE |

I40E_FLAG_NO_PCI_LINK_CHECK |

I40E_FLAG_USE_SET_LLDP_MIB |

} else if ((pf->hw.aq.api_maj_ver > 1) ||

((pf->hw.aq.api_maj_ver == 1) &&

(pf->hw.aq.api_min_ver > 4))) {

0, 0, nlflags, filter_mask, NULL);

}

/**

* i40e_features_check - Validate encapsulated packet conforms to limits

* @skb: skb buff

struct net_device *dev,

netdev_features_t features)

{

return features;

}

static const struct net_device_ops i40e_netdev_ops = {

struct i40e_hw *hw = &pf->hw;

struct i40e_netdev_priv *np;

struct net_device *netdev;

u8 mac_addr[ETH_ALEN];

int etherdev_size;

* which must be replaced by a normal filter.

*/

i40e_rm_default_mac_filter(vsi, mac_addr);

} else {

/* relate the VSI_VMDQ name to the VSI_MAIN name */

snprintf(netdev->name, IFNAMSIZ, "%sv%%d",

pf->vsi[pf->lan_vsi]->netdev->name);

random_ether_addr(mac_addr);

}

ether_addr_copy(netdev->dev_addr, mac_addr);

ether_addr_copy(netdev->perm_addr, mac_addr);

i40e_fcoe_config_netdev(netdev, vsi);

#endif

return 0;

}

static int i40e_add_vsi(struct i40e_vsi *vsi)

{

int ret = -ENODEV;

struct i40e_pf *pf = vsi->back;

struct i40e_hw *hw = &pf->hw;

struct i40e_vsi_context ctxt;

u8 enabled_tc = 0x1; /* TC0 enabled */

int f_count = 0;

vsi->seid = ctxt.seid;

vsi->id = ctxt.vsi_number;

}

vsi->active_filters = 0;

clear_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state);

/* If macvlan filters already exist, force them to get loaded */

f->state = I40E_FILTER_NEW;

f_count++;

}

if (f_count) {

vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;

**/

int i40e_vsi_release(struct i40e_vsi *vsi)

{

struct i40e_veb *veb = NULL;

struct i40e_pf *pf;

u16 uplink_seid;

pf = vsi->back;

i40e_vsi_disable_irq(vsi);

}

i40e_sync_vsi_filters(vsi);

mutex_init(&hw->aq.asq_mutex);

mutex_init(&hw->aq.arq_mutex);

/* do a special CORER for clearing PXE mode once at init */

if (hw->revision_id == 0 &&

err = i40e_init_pf_dcb(pf);

if (err) {

dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);

/* Continue without DCB enabled */

}

#endif /* CONFIG_I40E_DCB */

dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n",

i40e_stat_str(&pf->hw, err),

i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));

/* Add a filter to drop all Flow control frames from any VSI from being

* transmitted. By doing so we stop a malicious VF from sending out

pf->main_vsi_seid);

if ((pf->hw.device_id == I40E_DEV_ID_10G_BASE_T) ||

/* print a string summarizing features */

i40e_print_features(pf);

*((u16 *)&bytes[2]) = hw->nvm_wait_opcode;

}

return 0;

}

switch (hw->nvmupd_state) {

case I40E_NVMUPD_STATE_INIT:

status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno);

}

hw->nvm_wait_opcode = 0;

switch (hw->nvmupd_state) {

case I40E_NVMUPD_STATE_INIT_WAIT:

hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;

u16 seid, bool enable,

u16 vid,

struct i40e_asq_cmd_details *cmd_details);

i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,

u16 seid, bool enable,

struct i40e_asq_cmd_details *cmd_details);

u32 reg_addr, u32 reg_val,

struct i40e_asq_cmd_details *cmd_details);

void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);

u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num);

i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,

u32 time, u32 interval);

{

struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);

struct timespec64 now, then;

then = ns_to_timespec64(delta);

i40e_ptp_read(pf, &now);

now = timespec64_add(now, then);

i40e_ptp_write(pf, (const struct timespec64 *)&now);

return 0;

}

static int i40e_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)

{

struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);

i40e_ptp_read(pf, ts);

return 0;

}

const struct timespec64 *ts)

{

struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);

i40e_ptp_write(pf, ts);

return 0;

}

}

/**

* i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung

* @vsi: The VSI with the rings relevant to 1588

*

{

struct i40e_pf *pf = vsi->back;

struct i40e_hw *hw = &pf->hw;

/* Since we cannot turn off the Rx timestamp logic if the device is

* configured for Tx timestamping, we check if Rx timestamping is

if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx)

return;

}

}

/**

hw = &pf->hw;

return;

lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index));

hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index));

ns = (((u64)hi) << 32) | lo;

i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns);

case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:

case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:

case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:

pf->ptp_rx = true;

tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK |

I40E_PRTTSYN_CTL1_TSYNTYPE_V1 |

config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;

break;

case HWTSTAMP_FILTER_PTP_V2_EVENT:

case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:

case HWTSTAMP_FILTER_PTP_V2_SYNC:

case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:

case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:

case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:

pf->ptp_rx = true;

tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK |

break;

case HWTSTAMP_FILTER_ALL:

default:

}

/* Clear out all 1588-related registers to clear and unlatch them. */

rd32(hw, I40E_PRTTSYN_STAT_0);

rd32(hw, I40E_PRTTSYN_TXTIME_H);

rd32(hw, I40E_PRTTSYN_RXTIME_H(0));

rd32(hw, I40E_PRTTSYN_RXTIME_H(1));

rd32(hw, I40E_PRTTSYN_RXTIME_H(2));

rd32(hw, I40E_PRTTSYN_RXTIME_H(3));

/* Enable/disable the Tx timestamp interrupt based on user input. */

regval = rd32(hw, I40E_PRTTSYN_CTL0);

return;

}

/* ensure we have a clock device */

err = i40e_ptp_create_clock(pf);

struct device *dev;

dma_addr_t dma;

u32 td_cmd = 0;

u16 i;

/* find existing FDIR VSI */

if (!vsi)

return -ENOENT;

dev = tx_ring->dev;

/* we need two descriptors to add/del a filter and we can wait */

msleep_interruptible(1);

dma = dma_map_single(dev, raw_packet,

I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);

return err ? -EOPNOTSUPP : 0;

}

#define I40E_IP_DUMMY_PACKET_LEN 34

/**

* i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for

case UDP_V4_FLOW:

ret = i40e_add_del_fdir_udpv4(vsi, input, add);

break;

case IP_USER_FLOW:

switch (input->ip4_proto) {

case IPPROTO_TCP:

case IPPROTO_UDP:

ret = i40e_add_del_fdir_udpv4(vsi, input, add);

break;

ret = i40e_add_del_fdir_ipv4(vsi, input, add);

break;

}

break;

default:

dev_info(&pf->pdev->dev, "Could not specify spec type %d\n",

input->flow_type);

ret = -EINVAL;

return 0;

}

/**

* i40e_clean_tx_irq - Reclaim resources after transmit completes

unsigned int j = i40e_get_tx_pending(tx_ring, false);

if (budget &&

!test_bit(__I40E_DOWN, &vsi->state) &&

(I40E_DESC_UNUSED(tx_ring) != tx_ring->count))

tx_ring->arm_wb = true;

* because each write-back erases this info.

*/

rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);

rx_desc++;

bi++;

u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);

u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>

I40E_RXD_QW1_STATUS_SHIFT;

I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT;

i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);

while (likely(total_rx_packets < budget)) {

union i40e_rx_desc *rx_desc;

struct sk_buff *skb;

u16 vlan_tag;

u8 rx_ptype;

u64 qword;

rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean);

/* status_error_len will always be zero for unused descriptors

* because it's cleared in cleanup, and overlaps with hdr_addr

* which is always zero because packet split isn't used, if the

* hardware wrote DD then it will be non-zero

*/

break;

/* This memory barrier is needed to keep us from reading

/* probably a little skewed due to removing CRC */

total_rx_bytes += skb->len;

/* populate checksum, VLAN, and protocol */

i40e_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype);

/* If work not completed, return budget and polling will return */

if (!clean_complete) {

tx_only:

}

}

if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)

/* Work is done so exit the polling mode and re-enable the interrupt */

napi_complete_done(napi, work_done);

i40e_irq_dynamic_enable_icr0(vsi->back, false);

}

/**

u32 td_tag = 0;

dma_addr_t dma;

u16 gso_segs;

if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {

td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;

tx_bi = &tx_ring->tx_bi[i];

}

i++;

if (i == tx_ring->count)

tx_ring->next_to_use = i;

i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);

/* Algorithm to optimize tail and RS bit setting:

*

*

* pending and interrupts were disabled the service task will

* trigger a force WB.

*/

tx_ring->packet_stride = 0;

}

tx_desc->cmd_type_offset_bsz =

/* notify HW of packet */

writel(i, tx_ring->tail);

}

return;

dma_error:

#define I40E_MAX_DATA_PER_TXD_ALIGNED \

(I40E_MAX_DATA_PER_TXD & ~(I40E_MAX_READ_REQ_SIZE - 1))

*/

static inline unsigned int i40e_txd_use_count(unsigned int size)

{

}

/* Tx Descriptors needed, worst case */

u8 atr_sample_rate;

u8 atr_count;

bool ring_active; /* is ring online or not */

bool arm_wb; /* do something to arm write back */

u8 packet_stride;

u16 flags;

#define I40E_TXR_FLAGS_WB_ON_ITR BIT(0)

/* stats structs */

struct i40e_queue_stats stats;

I40E_DEBUG_ALL = 0xFFFFFFFF

};

I40E_GLGEN_MSCA_OPCODE_SHIFT)

I40E_GLGEN_MSCA_OPCODE_SHIFT)

I40E_GLGEN_MSCA_OPCODE_SHIFT)

#define I40E_PHY_COM_REG_PAGE 0x1E

#define I40E_PHY_LED_LINK_MODE_MASK 0xF0

#define I40E_MODULE_TYPE_1000BASE_T 0x08

};

struct i40e_phy_info {

struct i40e_link_status link_info;

struct i40e_link_status link_info_old;

bool get_link_info;

enum i40e_media_type media_type;

/* all the phy types the NVM is capable of */

#define I40E_HW_CAP_MAX_GPIO 30

/* Capabilities of a PF or a VF or the whole device */

struct i40e_hw_capabilities {

#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3

u32 management_mode;

u32 npar_enable;

u32 os2bmc;

u32 valid_functions;

I40E_NVMUPD_STATE_WRITING,

I40E_NVMUPD_STATE_INIT_WAIT,

I40E_NVMUPD_STATE_WRITE_WAIT,

};

/* nvm_access definition and its masks/shifts need to be accessible to

#define I40E_VIRTCHNL_VF_OFFLOAD_RSS_PF 0X00080000

#define I40E_VIRTCHNL_VF_OFFLOAD_ENCAP_CSUM 0X00100000

struct i40e_virtchnl_vf_resource {

u16 num_vsis;

u16 num_queue_pairs;

}

if (type == I40E_VSI_SRIOV) {

u64 hena = i40e_pf_get_default_rss_hena(pf);

vf->lan_vsi_idx = vsi->idx;

vf->lan_vsi_id = vsi->id;

if (vf->port_vlan_id)

i40e_vsi_add_pvid(vsi, vf->port_vlan_id);

if (is_valid_ether_addr(vf->default_lan_addr.addr)) {

f = i40e_add_filter(vsi, vf->default_lan_addr.addr,

if (!f)

dev_info(&pf->pdev->dev,

"Could not add MAC filter %pM for VF %d\n",

vf->default_lan_addr.addr, vf->vf_id);

}

i40e_write_rx_ctl(&pf->hw, I40E_VFQF_HENA1(0, vf->vf_id),

(u32)hena);

i40e_write_rx_ctl(&pf->hw, I40E_VFQF_HENA1(1, vf->vf_id),

i40e_vsi_release(pf->vsi[vf->lan_vsi_idx]);

vf->lan_vsi_idx = 0;

vf->lan_vsi_id = 0;

}

msix_vf = pf->hw.func_caps.num_msix_vectors_vf;

if (vf->lan_vsi_idx == 0)

goto complete_reset;

complete_reset:

/* reallocate VF resources to reset the VSI state */

i40e_free_vf_res(vf);

i40e_notify_client_of_vf_enable(pf, 0);

for (i = 0; i < pf->num_alloc_vfs; i++)

if (test_bit(I40E_VF_STAT_INIT, &pf->vf[i].vf_states))

/* Disable IOV before freeing resources. This lets any VF drivers

* running in the host get themselves cleaned up before we yank

static inline int i40e_getnum_vf_vsi_vlan_filters(struct i40e_vsi *vsi)

{

struct i40e_mac_filter *f;

if (f->vlan >= 0 && f->vlan <= I40E_MAX_VLANID)

num_vlans++;

}

struct i40e_vsi *vsi;

bool alluni = false;

int aq_err = 0;

vsi = i40e_find_vsi_from_id(pf, info->vsi_id);

if (!test_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states) ||

vf->port_vlan_id,

NULL);

} else if (i40e_getnum_vf_vsi_vlan_filters(vsi)) {

if (f->vlan < 0 || f->vlan > I40E_MAX_VLANID)

continue;

aq_ret = i40e_aq_set_vsi_mc_promisc_on_vlan(hw,

vf->vf_id,

i40e_stat_str(&pf->hw, aq_ret),

i40e_aq_str(&pf->hw, aq_err));

}

}

vf->port_vlan_id,

NULL);

} else if (i40e_getnum_vf_vsi_vlan_filters(vsi)) {

aq_ret = 0;

if (f->vlan >= 0 && f->vlan <= I40E_MAX_VLANID) {

aq_ret =

allmulti, NULL,

true);

aq_err = pf->hw.aq.asq_last_status;

dev_err(&pf->pdev->dev,

"VF %d failed to set unicast promiscuous mode %8.8x err %s aq_err %s\n",

vf->vf_id, info->flags,

i40e_stat_str(&pf->hw, aq_ret),

i40e_aq_str(&pf->hw, aq_err));

}

if (!aq_ret) {

dev_info(&pf->pdev->dev,

"VF %d successfully set unicast promiscuous mode\n",

goto error_param;

}

aq_ret = I40E_ERR_TIMEOUT;

error_param:

/* send the response to the VF */

goto error_param;

}

error_param:

/* send the response to the VF */

/* Lock once, because all function inside for loop accesses VSI's

* MAC filter list which needs to be protected using same lock.

*/

/* add new addresses to the list */

for (i = 0; i < al->num_elements; i++) {

struct i40e_mac_filter *f;

if (!f) {

if (i40e_is_vsi_in_vlan(vsi))

else

}

if (!f) {

"Unable to add MAC filter %pM for VF %d\n",

al->list[i].addr, vf->vf_id);

ret = I40E_ERR_PARAM;

goto error_param;

} else {

vf->num_mac++;

}

}

/* program the updated filter list */

ret = i40e_sync_vsi_filters(vsi);

}

vsi = pf->vsi[vf->lan_vsi_idx];

/* delete addresses from the list */

for (i = 0; i < al->num_elements; i++)

ret = I40E_ERR_INVALID_MAC_ADDR;

goto error_param;

} else {

vf->num_mac--;

}

/* program the updated filter list */

ret = i40e_sync_vsi_filters(vsi);

}

for (i = 0; i < vfl->num_elements; i++) {

if (test_bit(I40E_VF_STAT_UC_PROMISC, &vf->vf_states))

i40e_aq_set_vsi_uc_promisc_on_vlan(&pf->hw, vsi->seid,

false,

vfl->vlan_id[i],

NULL);

}

error_param:

struct i40e_mac_filter *f;

struct i40e_vf *vf;

int ret = 0;

/* validate the request */

if (vf_id >= pf->num_alloc_vfs) {

}

/* Lock once because below invoked function add/del_filter requires

*/

/* delete the temporary mac address */

if (!is_zero_ether_addr(vf->default_lan_addr.addr))

i40e_del_filter(vsi, vf->default_lan_addr.addr,

/* Delete all the filters for this VSI - we're going to kill it

* anyway.

*/

dev_info(&pf->pdev->dev, "Setting MAC %pM on VF %d\n", mac, vf_id);

/* program mac filter */

u16 vlanprio = vlan_id | (qos << I40E_VLAN_PRIORITY_SHIFT);

struct i40e_netdev_priv *np = netdev_priv(netdev);

struct i40e_pf *pf = np->vsi->back;

struct i40e_vsi *vsi;

struct i40e_vf *vf;

int ret = 0;

/* duplicate request, so just return success */

goto error_pvid;

dev_err(&pf->pdev->dev,

"VF %d has already configured VLAN filters and the administrator is requesting a port VLAN override.\nPlease unload and reload the VF driver for this change to take effect.\n",

vf_id);

*/

if ((!(vlan_id || qos) ||

vlanprio != le16_to_cpu(vsi->info.pvid)) &&

if (ret) {

dev_info(&vsi->back->pdev->dev,

}

}

if (vlan_id || qos)

ret = i40e_vsi_add_pvid(vsi, vlanprio);

else

dev_info(&pf->pdev->dev, "Setting VLAN %d, QOS 0x%x on VF %d\n",

vlan_id, qos, vf_id);

if (ret) {

dev_info(&vsi->back->pdev->dev,

"add VF VLAN failed, ret=%d aq_err=%d\n", ret,

vsi->back->hw.aq.asq_last_status);

goto error_pvid;

}

}

if (ret) {

dev_err(&pf->pdev->dev, "Unable to update VF vsi context\n");

goto error_pvid;

}

/* The Port VLAN needs to be saved across resets the same as the

* default LAN MAC address.

*/

case I40E_LINK_SPEED_40GB:

speed = 40000;

break;

case I40E_LINK_SPEED_20GB:

speed = 20000;

break;

}

if (max_tx_rate > speed) {

max_tx_rate, vf->vf_id);

ret = -EINVAL;

goto error;

desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);

desc_idx = ntc;

flags = le16_to_cpu(desc->flags);

if (flags & I40E_AQ_FLAG_ERR) {

ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;

i40e_debug(hw,

I40E_DEBUG_AQ_MESSAGE,

"AQRX: Event received with error 0x%X.\n",

I40E_PHY_TYPE_1000BASE_LX = 0x1C,

I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,

I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,

I40E_PHY_TYPE_MAX

};

#define I40E_LINK_SPEED_10GB_SHIFT 0x3

#define I40E_LINK_SPEED_40GB_SHIFT 0x4

#define I40E_LINK_SPEED_20GB_SHIFT 0x5

enum i40e_aq_link_speed {

I40E_LINK_SPEED_UNKNOWN = 0,

I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT),

I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT),

I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT),

};

struct i40e_aqc_module_desc {

#define I40E_AQ_PHY_LINK_ENABLED 0x08

#define I40E_AQ_PHY_AN_ENABLED 0x10

#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20

__le16 eee_capability;

#define I40E_AQ_EEE_100BASE_TX 0x0002

#define I40E_AQ_EEE_1000BASE_T 0x0004

__le32 eeer_val;

u8 d3_lpan;

#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01

u8 phy_id[4];

u8 module_type[3];

u8 qualified_module_count;

__le16 eee_capability;

__le32 eeer;

u8 low_power_ctrl;

};

I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);

#define I40E_AQ_LINK_TX_DRAINED 0x01

#define I40E_AQ_LINK_TX_FLUSHED 0x03

#define I40E_AQ_LINK_FORCED_40G 0x10

u8 loopback; /* use defines from i40e_aqc_set_lb_mode */

__le16 max_frame_size;

u8 config;

#define I40E_AQ_CONFIG_CRC_ENA 0x04

#define I40E_AQ_CONFIG_PACING_MASK 0x78

u8 external_power_ability;

case I40E_DEV_ID_10G_BASE_T4:

case I40E_DEV_ID_20G_KR2:

case I40E_DEV_ID_20G_KR2_A:

hw->mac.type = I40E_MAC_XL710;

break;

case I40E_DEV_ID_SFP_X722:

#define I40E_DEV_ID_20G_KR2 0x1587

#define I40E_DEV_ID_20G_KR2_A 0x1588

#define I40E_DEV_ID_10G_BASE_T4 0x1589

#define I40E_DEV_ID_VF 0x154C

#define I40E_DEV_ID_VF_HV 0x1571

#define I40E_DEV_ID_SFP_X722 0x37D0

u16 reg, u8 phy_addr, u16 *value);

i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page,

u16 reg, u8 phy_addr, u16 value);

u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num);

i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,

u32 time, u32 interval);

return 0;

}

/**

* i40e_clean_tx_irq - Reclaim resources after transmit completes

unsigned int j = i40evf_get_tx_pending(tx_ring, false);

if (budget &&

!test_bit(__I40E_DOWN, &vsi->state) &&

(I40E_DESC_UNUSED(tx_ring) != tx_ring->count))

tx_ring->arm_wb = true;

* because each write-back erases this info.

*/

rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);

rx_desc++;

bi++;

while (likely(total_rx_packets < budget)) {

union i40e_rx_desc *rx_desc;

struct sk_buff *skb;

u16 vlan_tag;

u8 rx_ptype;

u64 qword;

rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean);

/* status_error_len will always be zero for unused descriptors

* because it's cleared in cleanup, and overlaps with hdr_addr

* which is always zero because packet split isn't used, if the

* hardware wrote DD then it will be non-zero

*/

break;

/* This memory barrier is needed to keep us from reading

/* probably a little skewed due to removing CRC */

total_rx_bytes += skb->len;

/* populate checksum, VLAN, and protocol */

i40evf_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype);

/* If work not completed, return budget and polling will return */

if (!clean_complete) {

tx_only:

}

}

if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)

/* Work is done so exit the polling mode and re-enable the interrupt */

napi_complete_done(napi, work_done);

}

/**

u32 td_tag = 0;

dma_addr_t dma;

u16 gso_segs;

if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {

td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;

tx_bi = &tx_ring->tx_bi[i];

}

i++;

if (i == tx_ring->count)

tx_ring->next_to_use = i;

i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);

/* Algorithm to optimize tail and RS bit setting:

*

*

* pending and interrupts were disabled the service task will

* trigger a force WB.

*/

tx_ring->packet_stride = 0;

}

tx_desc->cmd_type_offset_bsz =

/* notify HW of packet */

writel(i, tx_ring->tail);

}

return;

dma_error:

#define I40E_MAX_DATA_PER_TXD_ALIGNED \

(I40E_MAX_DATA_PER_TXD & ~(I40E_MAX_READ_REQ_SIZE - 1))

*/

static inline unsigned int i40e_txd_use_count(unsigned int size)

{

}

/* Tx Descriptors needed, worst case */

bool ring_active; /* is ring online or not */

bool arm_wb; /* do something to arm write back */

u8 packet_stride;

u16 flags;

#define I40E_TXR_FLAGS_WB_ON_ITR BIT(0)

#define I40E_MODULE_TYPE_1000BASE_T 0x08

};

struct i40e_phy_info {

struct i40e_link_status link_info;

struct i40e_link_status link_info_old;

bool get_link_info;

enum i40e_media_type media_type;

/* all the phy types the NVM is capable of */

#define I40E_HW_CAP_MAX_GPIO 30

/* Capabilities of a PF or a VF or the whole device */

struct i40e_hw_capabilities {

#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3

u32 management_mode;

u32 npar_enable;

u32 os2bmc;

u32 valid_functions;

I40E_NVMUPD_STATE_WRITING,

I40E_NVMUPD_STATE_INIT_WAIT,

I40E_NVMUPD_STATE_WRITE_WAIT,

};

/* nvm_access definition and its masks/shifts need to be accessible to

#define I40E_VIRTCHNL_VF_OFFLOAD_RSS_PF 0X00080000

#define I40E_VIRTCHNL_VF_OFFLOAD_ENCAP_CSUM 0X00100000

struct i40e_virtchnl_vf_resource {

u16 num_vsis;

u16 num_queue_pairs;

int v_idx; /* vector index in list */

char name[IFNAMSIZ + 9];

bool arm_wb_state;

};

/* Helper macros to switch between ints/sec and what the register uses.

case I40E_LINK_SPEED_40GB:

ethtool_cmd_speed_set(ecmd, SPEED_40000);

break;

case I40E_LINK_SPEED_20GB:

ethtool_cmd_speed_set(ecmd, SPEED_20000);

break;

#define DRV_VERSION_MAJOR 1

#define DRV_VERSION_MINOR 6

#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \

__stringify(DRV_VERSION_MINOR) "." \

__stringify(DRV_VERSION_BUILD) \

{

struct i40e_hw *hw = &adapter->hw;

wr32(hw, I40E_VFINT_DYN_CTL01, 0);

/* read flush */

#endif

/**

* i40evf_request_traffic_irqs - Initialize MSI-X interrupts

* @adapter: board private structure

*

{

int vector, err, q_vectors;

int rx_int_idx = 0, tx_int_idx = 0;

i40evf_irq_disable(adapter);

/* Decrement for Other and TCP Timer vectors */

for (vector = 0; vector < q_vectors; vector++) {

struct i40e_q_vector *q_vector = &adapter->q_vectors[vector];

if (q_vector->tx.ring && q_vector->rx.ring) {

snprintf(q_vector->name, sizeof(q_vector->name) - 1,

/* skip this unused q_vector */

continue;

}

if (err) {

dev_info(&adapter->pdev->dev,

"Request_irq failed, error: %d\n", err);

goto free_queue_irqs;

}

/* assign the mask for this irq */

}

return 0;

free_queue_irqs:

while (vector) {

vector--;

}

return err;

}

**/

static void i40evf_free_traffic_irqs(struct i40evf_adapter *adapter)

{

q_vectors = adapter->num_msix_vectors - NONQ_VECS;

}

}

{

struct net_device *netdev = adapter->netdev;

free_irq(adapter->msix_entries[0].vector, netdev);

}

int q_idx, num_q_vectors;

int napi_vectors;

num_q_vectors = adapter->num_msix_vectors - NONQ_VECS;

napi_vectors = adapter->num_active_queues;

netif_napi_del(&q_vector->napi);

}

kfree(adapter->q_vectors);

}

/**

**/

void i40evf_reset_interrupt_capability(struct i40evf_adapter *adapter)

{

pci_disable_msix(adapter->pdev);

kfree(adapter->msix_entries);

adapter->msix_entries = NULL;

schedule_work(&adapter->adminq_task);

}

#define I40EVF_RESET_WAIT_MS 10

#define I40EVF_RESET_WAIT_COUNT 500

/**

/* wait until the reset is complete and the PF is responding to us */

for (i = 0; i < I40EVF_RESET_WAIT_COUNT; i++) {

reg_val = rd32(hw, I40E_VFGEN_RSTAT) &

I40E_VFGEN_RSTAT_VFR_STATE_MASK;

if (reg_val == I40E_VFR_VFACTIVE)

break;

}

pci_set_master(adapter->pdev);

dev_err(&adapter->pdev->dev, "Reset never finished (%x)\n",

reg_val);

return; /* Do not attempt to reinit. It's dead, Jim. */

}

static int i40evf_change_mtu(struct net_device *netdev, int new_mtu)

{

struct i40evf_adapter *adapter = netdev_priv(netdev);

netdev->mtu = new_mtu;

adapter->flags |= I40EVF_FLAG_RESET_NEEDED;

return 0;

}

#define I40EVF_VLAN_FEATURES (NETIF_F_HW_VLAN_CTAG_TX |\

NETIF_F_HW_VLAN_CTAG_RX |\

NETIF_F_HW_VLAN_CTAG_FILTER)

.ndo_tx_timeout = i40evf_tx_timeout,

.ndo_vlan_rx_add_vid = i40evf_vlan_rx_add_vid,

.ndo_vlan_rx_kill_vid = i40evf_vlan_rx_kill_vid,

.ndo_fix_features = i40evf_fix_features,

#ifdef CONFIG_NET_POLL_CONTROLLER

.ndo_poll_controller = i40evf_netpoll,

i40evf_set_ethtool_ops(netdev);

netdev->watchdog_timeo = 5 * HZ;

if (!is_valid_ether_addr(adapter->hw.mac.addr)) {

dev_info(&pdev->dev, "Invalid MAC address %pM, using random\n",

adapter->hw.mac.addr);

msleep(50);

}

if (adapter->watchdog_timer.function)

del_timer_sync(&adapter->watchdog_timer);

case I40E_LINK_SPEED_40GB:

speed = "40 G";

break;

case I40E_LINK_SPEED_20GB:

speed = "20 G";

break;

#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */

/* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */

/* PBA constants */

#define E1000_PBA_34K 0x0022

struct igb_rx_buffer {

dma_addr_t dma;

struct page *page;

};

struct igb_tx_queue_stats {

netdev->priv_flags |= IFF_UNICAST_FLT;

adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);

/* before reading the NVM, reset the controller to put the device in a

if (!buffer_info->page)

continue;

buffer_info->page = NULL;

}

/* initialize outer IP header fields */

if (ip.v4->version == 4) {

/* IP header will have to cancel out any data that

* is not a part of the outer IP header

*/

type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;

ip.v4->tot_len = 0;

struct pci_dev *pdev = adapter->pdev;

int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;

/* adjust max frame to be at least the size of a standard frame */

if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))

max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;

/* transfer page from old buffer to new buffer */

*new_buff = *old_buff;

}

static inline bool igb_page_is_reserved(struct page *page)

struct page *page,

unsigned int truesize)

{

/* avoid re-using remote pages */

if (unlikely(igb_page_is_reserved(page)))

return false;

#if (PAGE_SIZE < 8192)

/* if we are only owner of page we can reuse it */

return false;

/* flip page offset to other buffer */

return false;

#endif

*/

return true;

}

return true;

/* this page cannot be reused so discard it */

return false;

}

page = rx_buffer->page;

prefetchw(page);

if (likely(!skb)) {

void *page_addr = page_address(page) +

rx_buffer->page_offset;

prefetchw(skb->data);

}

/* pull page into skb */

if (igb_add_rx_frag(rx_ring, rx_buffer, size, rx_desc, skb)) {

/* hand second half of page back to the ring */

igb_reuse_rx_page(rx_ring, rx_buffer);

} else {

}

/* clear contents of rx_buffer */

}

/* map page for use */

/* if mapping failed free memory back to system since

* there isn't much point in holding memory we can't use

bi->dma = dma;

bi->page = page;

bi->page_offset = 0;

return true;

}

if (!igb_alloc_mapped_page(rx_ring, bi))

break;

/* Refresh the desc even if buffer_addrs didn't change

* because each write-back erases this info.

*/

static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);

/* SYSTIM read access for the 82576 */

{

struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);

struct e1000_hw *hw = &igb->hw;

}

/* SYSTIM read access for the 82580 */

{

struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);

struct e1000_hw *hw = &igb->hw;

return 0;

}

{

struct igb_adapter *igb = container_of(ptp, struct igb_adapter,

ptp_caps);

u64 rate;

u32 inca;

neg_adj = 1;

}

inca = rate & INCVALUE_MASK;

if (neg_adj)

adapter->ptp_caps.max_adj = 62499999;

adapter->ptp_caps.n_ext_ts = 0;

adapter->ptp_caps.pps = 0;

adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;

adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;

adapter->ptp_caps.settime64 = igb_ptp_settime_82576;

adapter->ptp_caps.n_pins = IGB_N_SDP;

adapter->ptp_caps.pps = 1;

adapter->ptp_caps.pin_config = adapter->sdp_config;

adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;

adapter->ptp_caps.gettime64 = igb_ptp_gettime_i210;

adapter->ptp_caps.settime64 = igb_ptp_settime_i210;

#define E1000_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */

#define E1000_TXD_STAT_DD 0x00000001 /* Desc Done */

/* 802.1q VLAN Packet Size */

#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */

/* initialize outer IP header fields */

if (ip.v4->version == 4) {

/* IP header will have to cancel out any data that

* is not a part of the outer IP header

*/

type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;

ip.v4->tot_len = 0;

struct igbvf_adapter *adapter = netdev_priv(netdev);

int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;

while (test_and_set_bit(__IGBVF_RESETTING, &adapter->state))

usleep_range(1000, 2000);

/* igbvf_down has a dependency on max_frame_size */

NETIF_F_HW_VLAN_CTAG_RX |

NETIF_F_HW_VLAN_CTAG_TX;

/*reset the controller to put the device in a known good state */

err = hw->mac.ops.reset_hw(hw);

if (err) {

#include "ixgb.h"

#define IXGB_ALL_RAR_ENTRIES 16

netdev->vlan_features |= NETIF_F_HIGHDMA;

}

/* make sure the EEPROM is good */

if (!ixgb_validate_eeprom_checksum(&adapter->hw)) {

{

struct ixgb_adapter *adapter = netdev_priv(netdev);

int max_frame = new_mtu + ENET_HEADER_SIZE + ENET_FCS_LENGTH;

if (netif_running(netdev))

ixgb_down(adapter, true);

struct ixgbe_ring *tx_ring);

u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter);

void ixgbe_store_reta(struct ixgbe_adapter *adapter);

#endif /* _IXGBE_H_ */

}

/* Negotiate the fc mode to use */

/* Disable any previous flow control settings */

fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);

.get_link_capabilities = &ixgbe_get_link_capabilities_82598,

.led_on = &ixgbe_led_on_generic,

.led_off = &ixgbe_led_off_generic,

.blink_led_start = &ixgbe_blink_led_start_generic,

.blink_led_stop = &ixgbe_blink_led_stop_generic,

.set_rar = &ixgbe_set_rar_generic,

.set_vfta = &ixgbe_set_vfta_82598,

.fc_enable = &ixgbe_fc_enable_82598,

.setup_fc = ixgbe_setup_fc_generic,

.set_fw_drv_ver = NULL,

.acquire_swfw_sync = &ixgbe_acquire_swfw_sync,

.release_swfw_sync = &ixgbe_release_swfw_sync,

.get_link_capabilities = &ixgbe_get_link_capabilities_82599,

.led_on = &ixgbe_led_on_generic,

.led_off = &ixgbe_led_off_generic,