diff options
Diffstat (limited to 'drivers/net/e1000/e1000_hw.c')
| -rw-r--r-- | drivers/net/e1000/e1000_hw.c | 1541 |
1 files changed, 770 insertions, 771 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c index 7c6888c58c21..9a4b6cbddf2c 100644 --- a/drivers/net/e1000/e1000_hw.c +++ b/drivers/net/e1000/e1000_hw.c @@ -33,106 +33,107 @@ #include "e1000_hw.h" -static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); -static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); -static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data); -static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); -static int32_t e1000_get_software_semaphore(struct e1000_hw *hw); +static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask); +static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask); +static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data); +static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data); +static s32 e1000_get_software_semaphore(struct e1000_hw *hw); static void e1000_release_software_semaphore(struct e1000_hw *hw); -static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw); -static int32_t e1000_check_downshift(struct e1000_hw *hw); -static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity); +static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw); +static s32 e1000_check_downshift(struct e1000_hw *hw); +static s32 e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity); static void e1000_clear_hw_cntrs(struct e1000_hw *hw); static void e1000_clear_vfta(struct e1000_hw *hw); -static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw); -static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up); -static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw); -static int32_t e1000_detect_gig_phy(struct e1000_hw *hw); -static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank); -static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw); -static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length); -static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); -static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw); -static int32_t e1000_get_software_flag(struct e1000_hw *hw); -static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw); -static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout); -static int32_t e1000_id_led_init(struct e1000_hw *hw); -static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size); -static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw); +static s32 e1000_commit_shadow_ram(struct e1000_hw *hw); +static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, + bool link_up); +static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw); +static s32 e1000_detect_gig_phy(struct e1000_hw *hw); +static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank); +static s32 e1000_get_auto_rd_done(struct e1000_hw *hw); +static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, u16 *max_length); +static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); +static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); +static s32 e1000_get_software_flag(struct e1000_hw *hw); +static s32 e1000_ich8_cycle_init(struct e1000_hw *hw); +static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout); +static s32 e1000_id_led_init(struct e1000_hw *hw); +static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, u32 cnf_base_addr, u32 cnf_size); +static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw); static void e1000_init_rx_addrs(struct e1000_hw *hw); static void e1000_initialize_hardware_bits(struct e1000_hw *hw); -static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); -static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw); -static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw); -static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum); -static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr); -static int32_t e1000_mng_write_commit(struct e1000_hw *hw); -static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); -static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); -static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); -static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); -static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); -static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); +static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); +static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw); +static s32 e1000_mng_enable_host_if(struct e1000_hw *hw); +static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, u16 offset, u8 *sum); +static s32 e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr); +static s32 e1000_mng_write_commit(struct e1000_hw *hw); +static s32 e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); +static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); +static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); +static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); +static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); +static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); -static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data); -static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); -static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); -static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data); -static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data); -static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data); -static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); -static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); +static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data); +static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte); +static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte); +static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data); +static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size, u16 *data); +static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size, u16 data); +static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); +static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); static void e1000_release_software_flag(struct e1000_hw *hw); -static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); -static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active); -static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop); +static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); +static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); +static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop); static void e1000_set_pci_express_master_disable(struct e1000_hw *hw); -static int32_t e1000_wait_autoneg(struct e1000_hw *hw); -static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value); -static int32_t e1000_set_phy_type(struct e1000_hw *hw); +static s32 e1000_wait_autoneg(struct e1000_hw *hw); +static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value); +static s32 e1000_set_phy_type(struct e1000_hw *hw); static void e1000_phy_init_script(struct e1000_hw *hw); -static int32_t e1000_setup_copper_link(struct e1000_hw *hw); -static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw); -static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw); -static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw); -static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw); -static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); -static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); -static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, - uint16_t count); -static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw); -static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw); -static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset, - uint16_t words, uint16_t *data); -static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw, - uint16_t offset, uint16_t words, - uint16_t *data); -static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw); -static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd); -static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd); -static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, - uint16_t count); -static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, - uint16_t phy_data); -static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr, - uint16_t *phy_data); -static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count); -static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); +static s32 e1000_setup_copper_link(struct e1000_hw *hw); +static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw); +static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw); +static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); +static s32 e1000_config_mac_to_phy(struct e1000_hw *hw); +static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl); +static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl); +static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, + u16 count); +static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw); +static s32 e1000_phy_reset_dsp(struct e1000_hw *hw); +static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, + u16 words, u16 *data); +static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, + u16 offset, u16 words, + u16 *data); +static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw); +static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd); +static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd); +static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, + u16 count); +static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, + u16 phy_data); +static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw,u32 reg_addr, + u16 *phy_data); +static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count); +static s32 e1000_acquire_eeprom(struct e1000_hw *hw); static void e1000_release_eeprom(struct e1000_hw *hw); static void e1000_standby_eeprom(struct e1000_hw *hw); -static int32_t e1000_set_vco_speed(struct e1000_hw *hw); -static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); -static int32_t e1000_set_phy_mode(struct e1000_hw *hw); -static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer); -static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length); -static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, - uint16_t duplex); -static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); +static s32 e1000_set_vco_speed(struct e1000_hw *hw); +static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw); +static s32 e1000_set_phy_mode(struct e1000_hw *hw); +static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer); +static u8 e1000_calculate_mng_checksum(char *buffer, u32 length); +static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, + u16 duplex); +static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw); /* IGP cable length table */ static const -uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = +u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, @@ -143,7 +144,7 @@ uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; static const -uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = +u16 e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, @@ -158,7 +159,7 @@ uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = * * hw - Struct containing variables accessed by shared code *****************************************************************************/ -static int32_t +static s32 e1000_set_phy_type(struct e1000_hw *hw) { DEBUGFUNC("e1000_set_phy_type"); @@ -212,8 +213,8 @@ e1000_set_phy_type(struct e1000_hw *hw) static void e1000_phy_init_script(struct e1000_hw *hw) { - uint32_t ret_val; - uint16_t phy_saved_data; + u32 ret_val; + u16 phy_saved_data; DEBUGFUNC("e1000_phy_init_script"); @@ -271,7 +272,7 @@ e1000_phy_init_script(struct e1000_hw *hw) e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); if (hw->mac_type == e1000_82547) { - uint16_t fused, fine, coarse; + u16 fused, fine, coarse; /* Move to analog registers page */ e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); @@ -305,7 +306,7 @@ e1000_phy_init_script(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code *****************************************************************************/ -int32_t +s32 e1000_set_mac_type(struct e1000_hw *hw) { DEBUGFUNC("e1000_set_mac_type"); @@ -425,22 +426,22 @@ e1000_set_mac_type(struct e1000_hw *hw) switch (hw->mac_type) { case e1000_ich8lan: - hw->swfwhw_semaphore_present = TRUE; - hw->asf_firmware_present = TRUE; + hw->swfwhw_semaphore_present = true; + hw->asf_firmware_present = true; break; case e1000_80003es2lan: - hw->swfw_sync_present = TRUE; + hw->swfw_sync_present = true; /* fall through */ case e1000_82571: case e1000_82572: case e1000_82573: - hw->eeprom_semaphore_present = TRUE; + hw->eeprom_semaphore_present = true; /* fall through */ case e1000_82541: case e1000_82547: case e1000_82541_rev_2: case e1000_82547_rev_2: - hw->asf_firmware_present = TRUE; + hw->asf_firmware_present = true; break; default: break; @@ -450,20 +451,20 @@ e1000_set_mac_type(struct e1000_hw *hw) * FD mode */ if (hw->mac_type == e1000_82543) - hw->bad_tx_carr_stats_fd = TRUE; + hw->bad_tx_carr_stats_fd = true; /* capable of receiving management packets to the host */ if (hw->mac_type >= e1000_82571) - hw->has_manc2h = TRUE; + hw->has_manc2h = true; /* In rare occasions, ESB2 systems would end up started without * the RX unit being turned on. */ if (hw->mac_type == e1000_80003es2lan) - hw->rx_needs_kicking = TRUE; + hw->rx_needs_kicking = true; if (hw->mac_type > e1000_82544) - hw->has_smbus = TRUE; + hw->has_smbus = true; return E1000_SUCCESS; } @@ -476,13 +477,13 @@ e1000_set_mac_type(struct e1000_hw *hw) void e1000_set_media_type(struct e1000_hw *hw) { - uint32_t status; + u32 status; DEBUGFUNC("e1000_set_media_type"); if (hw->mac_type != e1000_82543) { /* tbi_compatibility is only valid on 82543 */ - hw->tbi_compatibility_en = FALSE; + hw->tbi_compatibility_en = false; } switch (hw->device_id) { @@ -513,7 +514,7 @@ e1000_set_media_type(struct e1000_hw *hw) if (status & E1000_STATUS_TBIMODE) { hw->media_type = e1000_media_type_fiber; /* tbi_compatibility not valid on fiber */ - hw->tbi_compatibility_en = FALSE; + hw->tbi_compatibility_en = false; } else { hw->media_type = e1000_media_type_copper; } @@ -527,17 +528,17 @@ e1000_set_media_type(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code *****************************************************************************/ -int32_t +s32 e1000_reset_hw(struct e1000_hw *hw) { - uint32_t ctrl; - uint32_t ctrl_ext; - uint32_t icr; - uint32_t manc; - uint32_t led_ctrl; - uint32_t timeout; - uint32_t extcnf_ctrl; - int32_t ret_val; + u32 ctrl; + u32 ctrl_ext; + u32 icr; + u32 manc; + u32 led_ctrl; + u32 timeout; + u32 extcnf_ctrl; + s32 ret_val; DEBUGFUNC("e1000_reset_hw"); @@ -569,7 +570,7 @@ e1000_reset_hw(struct e1000_hw *hw) E1000_WRITE_FLUSH(hw); /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ - hw->tbi_compatibility_on = FALSE; + hw->tbi_compatibility_on = false; /* Delay to allow any outstanding PCI transactions to complete before * resetting the device @@ -682,7 +683,7 @@ e1000_reset_hw(struct e1000_hw *hw) msleep(20); break; case e1000_82573: - if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { + if (!e1000_is_onboard_nvm_eeprom(hw)) { udelay(10); ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); ctrl_ext |= E1000_CTRL_EXT_EE_RST; @@ -729,7 +730,7 @@ e1000_reset_hw(struct e1000_hw *hw) } if (hw->mac_type == e1000_ich8lan) { - uint32_t kab = E1000_READ_REG(hw, KABGTXD); + u32 kab = E1000_READ_REG(hw, KABGTXD); kab |= E1000_KABGTXD_BGSQLBIAS; E1000_WRITE_REG(hw, KABGTXD, kab); } @@ -751,10 +752,10 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw) { if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) { /* Settings common to all PCI-express silicon */ - uint32_t reg_ctrl, reg_ctrl_ext; - uint32_t reg_tarc0, reg_tarc1; - uint32_t reg_tctl; - uint32_t reg_txdctl, reg_txdctl1; + u32 reg_ctrl, reg_ctrl_ext; + u32 reg_tarc0, reg_tarc1; + u32 reg_tctl; + u32 reg_txdctl, reg_txdctl1; /* link autonegotiation/sync workarounds */ reg_tarc0 = E1000_READ_REG(hw, TARC0); @@ -865,15 +866,15 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw) * configuration and flow control settings. Clears all on-chip counters. Leaves * the transmit and receive units disabled and uninitialized. *****************************************************************************/ -int32_t +s32 e1000_init_hw(struct e1000_hw *hw) { - uint32_t ctrl; - uint32_t i; - int32_t ret_val; - uint32_t mta_size; - uint32_t reg_data; - uint32_t ctrl_ext; + u32 ctrl; + u32 i; + s32 ret_val; + u32 mta_size; + u32 reg_data; + u32 ctrl_ext; DEBUGFUNC("e1000_init_hw"); @@ -1019,7 +1020,7 @@ e1000_init_hw(struct e1000_hw *hw) if (hw->mac_type == e1000_82573) { - uint32_t gcr = E1000_READ_REG(hw, GCR); + u32 gcr = E1000_READ_REG(hw, GCR); gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; E1000_WRITE_REG(hw, GCR, gcr); } @@ -1053,11 +1054,11 @@ e1000_init_hw(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code. *****************************************************************************/ -static int32_t +static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) { - uint16_t eeprom_data; - int32_t ret_val; + u16 eeprom_data; + s32 ret_val; DEBUGFUNC("e1000_adjust_serdes_amplitude"); @@ -1099,12 +1100,12 @@ e1000_adjust_serdes_amplitude(struct e1000_hw *hw) * established. Assumes the hardware has previously been reset and the * transmitter and receiver are not enabled. *****************************************************************************/ -int32_t +s32 e1000_setup_link(struct e1000_hw *hw) { - uint32_t ctrl_ext; - int32_t ret_val; - uint16_t eeprom_data; + u32 ctrl_ext; + s32 ret_val; + u16 eeprom_data; DEBUGFUNC("e1000_setup_link"); @@ -1232,15 +1233,15 @@ e1000_setup_link(struct e1000_hw *hw) * link. Assumes the hardware has been previously reset and the transmitter * and receiver are not enabled. *****************************************************************************/ -static int32_t +static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) { - uint32_t ctrl; - uint32_t status; - uint32_t txcw = 0; - uint32_t i; - uint32_t signal = 0; - int32_t ret_val; + u32 ctrl; + u32 status; + u32 txcw = 0; + u32 i; + u32 signal = 0; + s32 ret_val; DEBUGFUNC("e1000_setup_fiber_serdes_link"); @@ -1379,12 +1380,12 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code ******************************************************************************/ -static int32_t +static s32 e1000_copper_link_preconfig(struct e1000_hw *hw) { - uint32_t ctrl; - int32_t ret_val; - uint16_t phy_data; + u32 ctrl; + s32 ret_val; + u16 phy_data; DEBUGFUNC("e1000_copper_link_preconfig"); @@ -1428,7 +1429,7 @@ e1000_copper_link_preconfig(struct e1000_hw *hw) if (hw->mac_type <= e1000_82543 || hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) - hw->phy_reset_disable = FALSE; + hw->phy_reset_disable = false; return E1000_SUCCESS; } @@ -1439,12 +1440,12 @@ e1000_copper_link_preconfig(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code *********************************************************************/ -static int32_t +static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw) { - uint32_t led_ctrl; - int32_t ret_val; - uint16_t phy_data; + u32 led_ctrl; + s32 ret_val; + u16 phy_data; DEBUGFUNC("e1000_copper_link_igp_setup"); @@ -1470,7 +1471,7 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw) /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ if (hw->phy_type == e1000_phy_igp) { /* disable lplu d3 during driver init */ - ret_val = e1000_set_d3_lplu_state(hw, FALSE); + ret_val = e1000_set_d3_lplu_state(hw, false); if (ret_val) { DEBUGOUT("Error Disabling LPLU D3\n"); return ret_val; @@ -1478,7 +1479,7 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw) } /* disable lplu d0 during driver init */ - ret_val = e1000_set_d0_lplu_state(hw, FALSE); + ret_val = e1000_set_d0_lplu_state(hw, false); if (ret_val) { DEBUGOUT("Error Disabling LPLU D0\n"); return ret_val; @@ -1586,12 +1587,12 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code *********************************************************************/ -static int32_t +static s32 e1000_copper_link_ggp_setup(struct e1000_hw *hw) { - int32_t ret_val; - uint16_t phy_data; - uint32_t reg_data; + s32 ret_val; + u16 phy_data; + u32 reg_data; DEBUGFUNC("e1000_copper_link_ggp_setup"); @@ -1691,7 +1692,7 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw) * firmware will have already initialized them. We only initialize * them if the HW is not in IAMT mode. */ - if (e1000_check_mng_mode(hw) == FALSE) { + if (!e1000_check_mng_mode(hw)) { /* Enable Electrical Idle on the PHY */ phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, @@ -1734,11 +1735,11 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code *********************************************************************/ -static int32_t +static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw) { - int32_t ret_val; - uint16_t phy_data; + s32 ret_val; + u16 phy_data; DEBUGFUNC("e1000_copper_link_mgp_setup"); @@ -1838,11 +1839,11 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code *********************************************************************/ -static int32_t +static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) { - int32_t ret_val; - uint16_t phy_data; + s32 ret_val; + u16 phy_data; DEBUGFUNC("e1000_copper_link_autoneg"); @@ -1892,7 +1893,7 @@ e1000_copper_link_autoneg(struct e1000_hw *hw) } } - hw->get_link_status = TRUE; + hw->get_link_status = true; return E1000_SUCCESS; } @@ -1909,10 +1910,10 @@ e1000_copper_link_autoneg(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code ******************************************************************************/ -static int32_t +static s32 e1000_copper_link_postconfig(struct e1000_hw *hw) { - int32_t ret_val; + s32 ret_val; DEBUGFUNC("e1000_copper_link_postconfig"); if (hw->mac_type >= e1000_82544) { @@ -1932,7 +1933,7 @@ e1000_copper_link_postconfig(struct e1000_hw *hw) /* Config DSP to improve Giga link quality */ if (hw->phy_type == e1000_phy_igp) { - ret_val = e1000_config_dsp_after_link_change(hw, TRUE); + ret_val = e1000_config_dsp_after_link_change(hw, true); if (ret_val) { DEBUGOUT("Error Configuring DSP after link up\n"); return ret_val; @@ -1947,13 +1948,13 @@ e1000_copper_link_postconfig(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code ******************************************************************************/ -static int32_t +static s32 e1000_setup_copper_link(struct e1000_hw *hw) { - int32_t ret_val; - uint16_t i; - uint16_t phy_data; - uint16_t reg_data; + s32 ret_val; + u16 i; + u16 phy_data; + u16 reg_data; DEBUGFUNC("e1000_setup_copper_link"); @@ -2061,12 +2062,12 @@ e1000_setup_copper_link(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code ******************************************************************************/ -static int32_t -e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) +static s32 +e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex) { - int32_t ret_val = E1000_SUCCESS; - uint32_t tipg; - uint16_t reg_data; + s32 ret_val = E1000_SUCCESS; + u32 tipg; + u16 reg_data; DEBUGFUNC("e1000_configure_kmrn_for_10_100"); @@ -2097,12 +2098,12 @@ e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) return ret_val; } -static int32_t +static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw) { - int32_t ret_val = E1000_SUCCESS; - uint16_t reg_data; - uint32_t tipg; + s32 ret_val = E1000_SUCCESS; + u16 reg_data; + u32 tipg; DEBUGFUNC("e1000_configure_kmrn_for_1000"); @@ -2134,12 +2135,12 @@ e1000_configure_kmrn_for_1000(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code ******************************************************************************/ -int32_t +s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) { - int32_t ret_val; - uint16_t mii_autoneg_adv_reg; - uint16_t mii_1000t_ctrl_reg; + s32 ret_val; + u16 mii_autoneg_adv_reg; + u16 mii_1000t_ctrl_reg; DEBUGFUNC("e1000_phy_setup_autoneg"); @@ -2283,15 +2284,15 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code ******************************************************************************/ -static int32_t +static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) { - uint32_t ctrl; - int32_t ret_val; - uint16_t mii_ctrl_reg; - uint16_t mii_status_reg; - uint16_t phy_data; - uint16_t i; + u32 ctrl; + s32 ret_val; + u16 mii_ctrl_reg; + u16 mii_status_reg; + u16 phy_data; + u16 i; DEBUGFUNC("e1000_phy_force_speed_duplex"); @@ -2537,7 +2538,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw) void e1000_config_collision_dist(struct e1000_hw *hw) { - uint32_t tctl, coll_dist; + u32 tctl, coll_dist; DEBUGFUNC("e1000_config_collision_dist"); @@ -2564,12 +2565,12 @@ e1000_config_collision_dist(struct e1000_hw *hw) * The contents of the PHY register containing the needed information need to * be passed in. ******************************************************************************/ -static int32_t +static s32 e1000_config_mac_to_phy(struct e1000_hw *hw) { - uint32_t ctrl; - int32_t ret_val; - uint16_t phy_data; + u32 ctrl; + s32 ret_val; + u16 phy_data; DEBUGFUNC("e1000_config_mac_to_phy"); @@ -2623,10 +2624,10 @@ e1000_config_mac_to_phy(struct e1000_hw *hw) * by the PHY rather than the MAC. Software must also configure these * bits when link is forced on a fiber connection. *****************************************************************************/ -int32_t +s32 e1000_force_mac_fc(struct e1000_hw *hw) { - uint32_t ctrl; + u32 ctrl; DEBUGFUNC("e1000_force_mac_fc"); @@ -2690,15 +2691,15 @@ e1000_force_mac_fc(struct e1000_hw *hw) * based on the flow control negotiated by the PHY. In TBI mode, the TFCE * and RFCE bits will be automaticaly set to the negotiated flow control mode. *****************************************************************************/ -static int32_t +static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) { - int32_t ret_val; - uint16_t mii_status_reg; - uint16_t mii_nway_adv_reg; - uint16_t mii_nway_lp_ability_reg; - uint16_t speed; - uint16_t duplex; + s32 ret_val; + u16 mii_status_reg; + u16 mii_nway_adv_reg; + u16 mii_nway_lp_ability_reg; + u16 speed; + u16 duplex; DEBUGFUNC("e1000_config_fc_after_link_up"); @@ -2895,17 +2896,17 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw) * * Called by any function that needs to check the link status of the adapter. *****************************************************************************/ -int32_t +s32 e1000_check_for_link(struct e1000_hw *hw) { - uint32_t rxcw = 0; - uint32_t ctrl; - uint32_t status; - uint32_t rctl; - uint32_t icr; - uint32_t signal = 0; - int32_t ret_val; - uint16_t phy_data; + u32 rxcw = 0; + u32 ctrl; + u32 status; + u32 rctl; + u32 icr; + u32 signal = 0; + s32 ret_val; + u16 phy_data; DEBUGFUNC("e1000_check_for_link"); @@ -2923,7 +2924,7 @@ e1000_check_for_link(struct e1000_hw *hw) if (hw->media_type == e1000_media_type_fiber) { signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; if (status & E1000_STATUS_LU) - hw->get_link_status = FALSE; + hw->get_link_status = false; } } @@ -2947,7 +2948,7 @@ e1000_check_for_link(struct e1000_hw *hw) return ret_val; if (phy_data & MII_SR_LINK_STATUS) { - hw->get_link_status = FALSE; + hw->get_link_status = false; /* Check if there was DownShift, must be checked immediately after * link-up */ e1000_check_downshift(hw); @@ -2973,7 +2974,7 @@ e1000_check_for_link(struct e1000_hw *hw) } else { /* No link detected */ - e1000_config_dsp_after_link_change(hw, FALSE); + e1000_config_dsp_after_link_change(hw, false); return 0; } @@ -2983,7 +2984,7 @@ e1000_check_for_link(struct e1000_hw *hw) if (!hw->autoneg) return -E1000_ERR_CONFIG; /* optimize the dsp settings for the igp phy */ - e1000_config_dsp_after_link_change(hw, TRUE); + e1000_config_dsp_after_link_change(hw, true); /* We have a M88E1000 PHY and Auto-Neg is enabled. If we * have Si on board that is 82544 or newer, Auto @@ -3021,7 +3022,7 @@ e1000_check_for_link(struct e1000_hw *hw) * at gigabit speed, we turn on TBI compatibility. */ if (hw->tbi_compatibility_en) { - uint16_t speed, duplex; + u16 speed, duplex; ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); if (ret_val) { DEBUGOUT("Error getting link speed and duplex\n"); @@ -3036,7 +3037,7 @@ e1000_check_for_link(struct e1000_hw *hw) rctl = E1000_READ_REG(hw, RCTL); rctl &= ~E1000_RCTL_SBP; E1000_WRITE_REG(hw, RCTL, rctl); - hw->tbi_compatibility_on = FALSE; + hw->tbi_compatibility_on = false; } } else { /* If TBI compatibility is was previously off, turn it on. For @@ -3045,7 +3046,7 @@ e1000_check_for_link(struct e1000_hw *hw) * will look like CRC errors to to the hardware. */ if (!hw->tbi_compatibility_on) { - hw->tbi_compatibility_on = TRUE; + hw->tbi_compatibility_on = true; rctl = E1000_READ_REG(hw, RCTL); rctl |= E1000_RCTL_SBP; E1000_WRITE_REG(hw, RCTL, rctl); @@ -3098,7 +3099,7 @@ e1000_check_for_link(struct e1000_hw *hw) E1000_WRITE_REG(hw, TXCW, hw->txcw); E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); - hw->serdes_link_down = FALSE; + hw->serdes_link_down = false; } /* If we force link for non-auto-negotiation switch, check link status * based on MAC synchronization for internal serdes media type. @@ -3109,11 +3110,11 @@ e1000_check_for_link(struct e1000_hw *hw) udelay(10); if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { if (!(rxcw & E1000_RXCW_IV)) { - hw->serdes_link_down = FALSE; + hw->serdes_link_down = false; DEBUGOUT("SERDES: Link is up.\n"); } } else { - hw->serdes_link_down = TRUE; + hw->serdes_link_down = true; DEBUGOUT("SERDES: Link is down.\n"); } } @@ -3131,14 +3132,14 @@ e1000_check_for_link(struct e1000_hw *hw) * speed - Speed of the connection * duplex - Duplex setting of the connection *****************************************************************************/ -int32_t +s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, - uint16_t *speed, - uint16_t *duplex) + u16 *speed, + u16 *duplex) { - uint32_t status; - int32_t ret_val; - uint16_t phy_data; + u32 status; + s32 ret_val; + u16 phy_data; DEBUGFUNC("e1000_get_speed_and_duplex"); @@ -3213,12 +3214,12 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw, * * hw - Struct containing variables accessed by shared code ******************************************************************************/ -static int32_t +static s32 e1000_wait_autoneg(struct e1000_hw *hw) { - int32_t ret_val; - uint16_t i; - uint16_t phy_data; + s32 ret_val; + u16 i; + u16 phy_data; DEBUGFUNC("e1000_wait_autoneg"); DEBUGOUT("Waiting for Auto-Neg to complete.\n"); @@ -3250,7 +3251,7 @@ e1000_wait_autoneg(struct e1000_hw *hw) ******************************************************************************/ static void e1000_raise_mdi_clk(struct e1000_hw *hw, - uint32_t *ctrl) + u32 *ctrl) { /* Raise the clock input to the Management Data Clock (by setting the MDC * bit), and then delay 10 microseconds. @@ -3268,7 +3269,7 @@ e1000_raise_mdi_clk(struct e1000_hw *hw, ******************************************************************************/ static void e1000_lower_mdi_clk(struct e1000_hw *hw, - uint32_t *ctrl) + u32 *ctrl) { /* Lower the clock input to the Management Data Clock (by clearing the MDC * bit), and then delay 10 microseconds. @@ -3289,11 +3290,11 @@ e1000_lower_mdi_clk(struct e1000_hw *hw, ******************************************************************************/ static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, - uint32_t data, - uint16_t count) + u32 data, + u16 count) { - uint32_t ctrl; - uint32_t mask; + u32 ctrl; + u32 mask; /* We need to shift "count" number of bits out to the PHY. So, the value * in the "data" parameter will be shifted out to the PHY one bit at a @@ -3337,12 +3338,12 @@ e1000_shift_out_mdi_bits(struct e1000_hw *hw, * * Bits are shifted in in MSB to LSB order. ******************************************************************************/ -static uint16_t +static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw) { - uint32_t ctrl; - uint16_t data = 0; - uint8_t i; + u32 ctrl; + u16 data = 0; + u8 i; /* In order to read a register from the PHY, we need to shift in a total * of 18 bits from the PHY. The first two bit (turnaround) times are used @@ -3383,13 +3384,13 @@ e1000_shift_in_mdi_bits(struct e1000_hw *hw) return data; } -static int32_t -e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) +static s32 +e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask) { - uint32_t swfw_sync = 0; - uint32_t swmask = mask; - uint32_t fwmask = mask << 16; - int32_t timeout = 200; + u32 swfw_sync = 0; + u32 swmask = mask; + u32 fwmask = mask << 16; + s32 timeout = 200; DEBUGFUNC("e1000_swfw_sync_acquire"); @@ -3428,10 +3429,10 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) } static void -e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) +e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask) { - uint32_t swfw_sync; - uint32_t swmask = mask; + u32 swfw_sync; + u32 swmask = mask; DEBUGFUNC("e1000_swfw_sync_release"); @@ -3463,13 +3464,13 @@ e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) * hw - Struct containing variables accessed by shared code * reg_addr - address of the PHY register to read ******************************************************************************/ -int32_t +s32 e1000_read_phy_reg(struct e1000_hw *hw, - uint32_t reg_addr, - uint16_t *phy_data) + u32 reg_addr, + u16 *phy_data) { - uint32_t ret_val; - uint16_t swfw; + u32 ret_val; + u16 swfw; DEBUGFUNC("e1000_read_phy_reg"); @@ -3487,7 +3488,7 @@ e1000_read_phy_reg(struct e1000_hw *hw, hw->phy_type == e1000_phy_igp_2) && (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, - (uint16_t)reg_addr); + (u16)reg_addr); if (ret_val) { e1000_swfw_sync_release(hw, swfw); return ret_val; @@ -3498,14 +3499,14 @@ e1000_read_phy_reg(struct e1000_hw *hw, /* Select Configuration Page */ if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, - (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); + (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT)); } else { /* Use Alternative Page Select register to access * registers 30 and 31 */ ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT_ALT, - (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); + (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT)); } if (ret_val) { @@ -3522,13 +3523,13 @@ e1000_read_phy_reg(struct e1000_hw *hw, return ret_val; } -static int32_t -e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, - uint16_t *phy_data) +static s32 +e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, + u16 *phy_data) { - uint32_t i; - uint32_t mdic = 0; - const uint32_t phy_addr = 1; + u32 i; + u32 mdic = 0; + const u32 phy_addr = 1; DEBUGFUNC("e1000_read_phy_reg_ex"); @@ -3562,7 +3563,7 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, DEBUGOUT("MDI Error\n"); return -E1000_ERR_PHY; } - *phy_data = (uint16_t) mdic; + *phy_data = (u16) mdic; } else { /* We must first send a preamble through the MDIO pin to signal the * beginning of an MII instruction. This is done by sending 32 @@ -3602,12 +3603,12 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, * reg_addr - address of the PHY register to write * data - data to write to the PHY ******************************************************************************/ -int32_t -e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, - uint16_t phy_data) +s32 +e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, + u16 phy_data) { - uint32_t ret_val; - uint16_t swfw; + u32 ret_val; + u16 swfw; DEBUGFUNC("e1000_write_phy_reg"); @@ -3625,7 +3626,7 @@ e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, hw->phy_type == e1000_phy_igp_2) && (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, - (uint16_t)reg_addr); + (u16)reg_addr); if (ret_val) { e1000_swfw_sync_release(hw, swfw); return ret_val; @@ -3636,14 +3637,14 @@ e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, /* Select Configuration Page */ if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, - (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); + (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT)); } else { /* Use Alternative Page Select register to access * registers 30 and 31 */ ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT_ALT, - (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); + (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT)); } if (ret_val) { @@ -3660,13 +3661,13 @@ e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, return ret_val; } -static int32_t -e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, - uint16_t phy_data) +static s32 +e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, + u16 phy_data) { - uint32_t i; - uint32_t mdic = 0; - const uint32_t phy_addr = 1; + u32 i; + u32 mdic = 0; + const u32 phy_addr = 1; DEBUGFUNC("e1000_write_phy_reg_ex"); @@ -3680,7 +3681,7 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, * for the PHY register in the MDI Control register. The MAC will take * care of interfacing with the PHY to send the desired data. */ - mdic = (((uint32_t) phy_data) | + mdic = (((u32) phy_data) | (reg_addr << E1000_MDIC_REG_SHIFT) | (phy_addr << E1000_MDIC_PHY_SHIFT) | (E1000_MDIC_OP_WRITE)); @@ -3714,7 +3715,7 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); mdic <<= 16; - mdic |= (uint32_t) phy_data; + mdic |= (u32) phy_data; e1000_shift_out_mdi_bits(hw, mdic, 32); } @@ -3722,13 +3723,13 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, return E1000_SUCCESS; } -static int32_t +static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, - uint32_t reg_addr, - uint16_t *data) + u32 reg_addr, + u16 *data) { - uint32_t reg_val; - uint16_t swfw; + u32 reg_val; + u16 swfw; DEBUGFUNC("e1000_read_kmrn_reg"); if ((hw->mac_type == e1000_80003es2lan) && @@ -3749,19 +3750,19 @@ e1000_read_kmrn_reg(struct e1000_hw *hw, /* Read the data returned */ reg_val = E1000_READ_REG(hw, KUMCTRLSTA); - *data = (uint16_t)reg_val; + *data = (u16)reg_val; e1000_swfw_sync_release(hw, swfw); return E1000_SUCCESS; } -static int32_t +static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, - uint32_t reg_addr, - uint16_t data) + u32 reg_addr, + u16 data) { - uint32_t reg_val; - uint16_t swfw; + u32 reg_val; + u16 swfw; DEBUGFUNC("e1000_write_kmrn_reg"); if ((hw->mac_type == e1000_80003es2lan) && @@ -3787,13 +3788,13 @@ e1000_write_kmrn_reg(struct e1000_hw *hw, * * hw - Struct containing variables accessed by shared code ******************************************************************************/ -int32_t +s32 e1000_phy_hw_reset(struct e1000_hw *hw) { - uint32_t ctrl, ctrl_ext; - uint32_t led_ctrl; - int32_t ret_val; - uint16_t swfw; + u32 ctrl, ctrl_ext; + u32 led_ctrl; + s32 ret_val; + u16 swfw; DEBUGFUNC("e1000_phy_hw_reset"); @@ -3881,11 +3882,11 @@ e1000_phy_hw_reset(struct e1000_hw *hw) * * Sets bit 15 of the MII Control register ******************************************************************************/ -int32_t +s32 e1000_phy_reset(struct e1000_hw *hw) { - int32_t ret_val; - uint16_t phy_data; + s32 ret_val; + u16 phy_data; DEBUGFUNC("e1000_phy_reset"); @@ -3936,9 +3937,9 @@ e1000_phy_reset(struct e1000_hw *hw) void e1000_phy_powerdown_workaround(struct e1000_hw *hw) { - int32_t reg; - uint16_t phy_data; - int32_t retry = 0; + s32 reg; + u16 phy_data; + s32 retry = 0; DEBUGFUNC("e1000_phy_powerdown_workaround"); @@ -3986,13 +3987,13 @@ e1000_phy_powerdown_workaround(struct e1000_hw *hw) * * hw - struct containing variables accessed by shared code ******************************************************************************/ -static int32_t +static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw) { - int32_t ret_val; - int32_t reg; - int32_t cnt; - uint16_t phy_data; + s32 ret_val; + s32 reg; + s32 cnt; + u16 phy_data; if (hw->kmrn_lock_loss_workaround_disabled) return E1000_SUCCESS; @@ -4039,12 +4040,12 @@ e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code ******************************************************************************/ -static int32_t +static s32 e1000_detect_gig_phy(struct e1000_hw *hw) { - int32_t phy_init_status, ret_val; - uint16_t phy_id_high, phy_id_low; - boolean_t match = FALSE; + s32 phy_init_status, ret_val; + u16 phy_id_high, phy_id_low; + bool match = false; DEBUGFUNC("e1000_detect_gig_phy"); @@ -4075,46 +4076,46 @@ e1000_detect_gig_phy(struct e1000_hw *hw) if (ret_val) return ret_val; - hw->phy_id = (uint32_t) (phy_id_high << 16); + hw->phy_id = (u32) (phy_id_high << 16); udelay(20); ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); if (ret_val) return ret_val; - hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); - hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; + hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK); + hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK; switch (hw->mac_type) { case e1000_82543: - if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; + if (hw->phy_id == M88E1000_E_PHY_ID) match = true; break; case e1000_82544: - if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; + if (hw->phy_id == M88E1000_I_PHY_ID) match = true; break; case e1000_82540: case e1000_82545: case e1000_82545_rev_3: case e1000_82546: case e1000_82546_rev_3: - if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; + if (hw->phy_id == M88E1011_I_PHY_ID) match = true; break; case e1000_82541: case e1000_82541_rev_2: case e1000_82547: case e1000_82547_rev_2: - if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; + if (hw->phy_id == IGP01E1000_I_PHY_ID) match = true; break; case e1000_82573: - if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; + if (hw->phy_id == M88E1111_I_PHY_ID) match = true; break; case e1000_80003es2lan: - if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; + if (hw->phy_id == GG82563_E_PHY_ID) match = true; break; case e1000_ich8lan: - if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE; - if (hw->phy_id == IFE_E_PHY_ID) match = TRUE; - if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE; - if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE; + if (hw->phy_id == IGP03E1000_E_PHY_ID) match = true; + if (hw->phy_id == IFE_E_PHY_ID) match = true; + if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = true; + if (hw->phy_id == IFE_C_E_PHY_ID) match = true; break; default: DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); @@ -4135,10 +4136,10 @@ e1000_detect_gig_phy(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code ******************************************************************************/ -static int32_t +static s32 e1000_phy_reset_dsp(struct e1000_hw *hw) { - int32_t ret_val; + s32 ret_val; DEBUGFUNC("e1000_phy_reset_dsp"); do { @@ -4162,12 +4163,12 @@ e1000_phy_reset_dsp(struct e1000_hw *hw) * hw - Struct containing variables accessed by shared code * phy_info - PHY information structure ******************************************************************************/ -static int32_t +static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) { - int32_t ret_val; - uint16_t phy_data, min_length, max_length, average; + s32 ret_val; + u16 phy_data, min_length, max_length, average; e1000_rev_polarity polarity; DEBUGFUNC("e1000_phy_igp_get_info"); @@ -4239,12 +4240,12 @@ e1000_phy_igp_get_info(struct e1000_hw *hw, * hw - Struct containing variables accessed by shared code * phy_info - PHY information structure ******************************************************************************/ -static int32_t +static s32 e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) { - int32_t ret_val; - uint16_t phy_data; + s32 ret_val; + u16 phy_data; e1000_rev_polarity polarity; DEBUGFUNC("e1000_phy_ife_get_info"); @@ -4289,12 +4290,12 @@ e1000_phy_ife_get_info(struct e1000_hw *hw, * hw - Struct containing variables accessed by shared code * phy_info - PHY information structure ******************************************************************************/ -static int32_t +static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) { - int32_t ret_val; - uint16_t phy_data; + s32 ret_val; + u16 phy_data; e1000_rev_polarity polarity; DEBUGFUNC("e1000_phy_m88_get_info"); @@ -4368,12 +4369,12 @@ e1000_phy_m88_get_info(struct e1000_hw *hw, * hw - Struct containing variables accessed by shared code * phy_info - PHY information structure ******************************************************************************/ -int32_t +s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) { - int32_t ret_val; - uint16_t phy_data; + s32 ret_val; + u16 phy_data; DEBUGFUNC("e1000_phy_get_info"); @@ -4414,7 +4415,7 @@ e1000_phy_get_info(struct e1000_hw *hw, return e1000_phy_m88_get_info(hw, phy_info); } -int32_t +s32 e1000_validate_mdi_setting(struct e1000_hw *hw) { DEBUGFUNC("e1000_validate_mdi_settings"); @@ -4435,13 +4436,13 @@ e1000_validate_mdi_setting(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code *****************************************************************************/ -int32_t +s32 e1000_init_eeprom_params(struct e1000_hw *hw) { struct e1000_eeprom_info *eeprom = &hw->eeprom; - uint32_t eecd = E1000_READ_REG(hw, EECD); - int32_t ret_val = E1000_SUCCESS; - uint16_t eeprom_size; + u32 eecd = E1000_READ_REG(hw, EECD); + s32 ret_val = E1000_SUCCESS; + u16 eeprom_size; DEBUGFUNC("e1000_init_eeprom_params"); @@ -4455,8 +4456,8 @@ e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->opcode_bits = 3; eeprom->address_bits = 6; eeprom->delay_usec = 50; - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; + eeprom->use_eerd = false; + eeprom->use_eewr = false; break; case e1000_82540: case e1000_82545: @@ -4473,8 +4474,8 @@ e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->word_size = 64; eeprom->address_bits = 6; } - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; + eeprom->use_eerd = false; + eeprom->use_eewr = false; break; case e1000_82541: case e1000_82541_rev_2: @@ -4503,8 +4504,8 @@ e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->address_bits = 6; } } - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; + eeprom->use_eerd = false; + eeprom->use_eewr = false; break; case e1000_82571: case e1000_82572: @@ -4518,8 +4519,8 @@ e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->page_size = 8; eeprom->address_bits = 8; } - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; + eeprom->use_eerd = false; + eeprom->use_eewr = false; break; case e1000_82573: eeprom->type = e1000_eeprom_spi; @@ -4532,9 +4533,9 @@ e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->page_size = 8; eeprom->address_bits = 8; } - eeprom->use_eerd = TRUE; - eeprom->use_eewr = TRUE; - if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { + eeprom->use_eerd = true; + eeprom->use_eewr = true; + if (!e1000_is_onboard_nvm_eeprom(hw)) { eeprom->type = e1000_eeprom_flash; eeprom->word_size = 2048; @@ -4555,24 +4556,24 @@ e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->page_size = 8; eeprom->address_bits = 8; } - eeprom->use_eerd = TRUE; - eeprom->use_eewr = FALSE; + eeprom->use_eerd = true; + eeprom->use_eewr = false; break; case e1000_ich8lan: { - int32_t i = 0; - uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); + s32 i = 0; + u32 flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); eeprom->type = e1000_eeprom_ich8; - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; + eeprom->use_eerd = false; + eeprom->use_eewr = false; eeprom->word_size = E1000_SHADOW_RAM_WORDS; /* Zero the shadow RAM structure. But don't load it from NVM * so as to save time for driver init */ if (hw->eeprom_shadow_ram != NULL) { for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { - hw->eeprom_shadow_ram[i].modified = FALSE; + hw->eeprom_shadow_ram[i].modified = false; hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; } } @@ -4585,7 +4586,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw) hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; - hw->flash_bank_size /= 2 * sizeof(uint16_t); + hw->flash_bank_size /= 2 * sizeof(u16); break; } @@ -4610,7 +4611,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw) if (eeprom_size) eeprom_size++; } else { - eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> + eeprom_size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> E1000_EECD_SIZE_EX_SHIFT); } @@ -4627,7 +4628,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw) *****************************************************************************/ static void e1000_raise_ee_clk(struct e1000_hw *hw, - uint32_t *eecd) + u32 *eecd) { /* Raise the clock input to the EEPROM (by setting the SK bit), and then * wait <delay> microseconds. @@ -4646,7 +4647,7 @@ e1000_raise_ee_clk(struct e1000_hw *hw, *****************************************************************************/ static void e1000_lower_ee_clk(struct e1000_hw *hw, - uint32_t *eecd) + u32 *eecd) { /* Lower the clock input to the EEPROM (by clearing the SK bit), and then * wait 50 microseconds. @@ -4666,12 +4667,12 @@ e1000_lower_ee_clk(struct e1000_hw *hw, *****************************************************************************/ static void e1000_shift_out_ee_bits(struct e1000_hw *hw, - uint16_t data, - uint16_t count) + u16 data, + u16 count) { struct e1000_eeprom_info *eeprom = &hw->eeprom; - uint32_t eecd; - uint32_t mask; + u32 eecd; + u32 mask; /* We need to shift "count" bits out to the EEPROM. So, value in the * "data" parameter will be shifted out to the EEPROM one bit at a time. @@ -4717,13 +4718,13 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw, * * hw - Struct containing variables accessed by shared code *****************************************************************************/ -static uint16_t +static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, - uint16_t count) + u16 count) { - uint32_t eecd; - uint32_t i; - uint16_t data; + u32 eecd; + u32 i; + u16 data; /* In order to read a register from the EEPROM, we need to shift 'count' * bits in from the EEPROM. Bits are "shifted in" by raising the clock @@ -4761,11 +4762,11 @@ e1000_shift_in_ee_bits(struct e1000_hw *hw, * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This * function should be called before issuing a command to the EEPROM. *****************************************************************************/ -static int32_t +static s32 e1000_acquire_eeprom(struct e1000_hw *hw) { struct e1000_eeprom_info *eeprom = &hw->eeprom; - uint32_t eecd, i=0; + u32 eecd, i=0; DEBUGFUNC("e1000_acquire_eeprom"); @@ -4824,7 +4825,7 @@ static void e1000_standby_eeprom(struct e1000_hw *hw) { struct e1000_eeprom_info *eeprom = &hw->eeprom; - uint32_t eecd; + u32 eecd; eecd = E1000_READ_REG(hw, EECD); @@ -4872,7 +4873,7 @@ e1000_standby_eeprom(struct e1000_hw *hw) static void e1000_release_eeprom(struct e1000_hw *hw) { - uint32_t eecd; + u32 eecd; DEBUGFUNC("e1000_release_eeprom"); @@ -4920,11 +4921,11 @@ e1000_release_eeprom(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code *****************************************************************************/ -static int32_t +static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw) { - uint16_t retry_count = 0; - uint8_t spi_stat_reg; + u16 retry_count = 0; + u8 spi_stat_reg; DEBUGFUNC("e1000_spi_eeprom_ready"); @@ -4937,7 +4938,7 @@ e1000_spi_eeprom_ready(struct e1000_hw *hw) do { e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, hw->eeprom.opcode_bits); - spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); + spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8); if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) break; @@ -4966,14 +4967,14 @@ e1000_spi_eeprom_ready(struct e1000_hw *hw) * data - word read from the EEPROM * words - number of words to read *****************************************************************************/ -int32_t +s32 e1000_read_eeprom(struct e1000_hw *hw, - uint16_t offset, - uint16_t words, - uint16_t *data) + u16 offset, + u16 words, + u16 *data) { struct e1000_eeprom_info *eeprom = &hw->eeprom; - uint32_t i = 0; + u32 i = 0; DEBUGFUNC("e1000_read_eeprom"); @@ -4994,15 +4995,14 @@ e1000_read_eeprom(struct e1000_hw *hw, * directly. In this case, we need to acquire the EEPROM so that * FW or other port software does not interrupt. */ - if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && - hw->eeprom.use_eerd == FALSE) { + if (e1000_is_onboard_nvm_eeprom(hw) && !hw->eeprom.use_eerd) { /* Prepare the EEPROM for bit-bang reading */ if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) return -E1000_ERR_EEPROM; } /* Eerd register EEPROM access requires no eeprom aquire/release */ - if (eeprom->use_eerd == TRUE) + if (eeprom->use_eerd) return e1000_read_eeprom_eerd(hw, offset, words, data); /* ICH EEPROM access is done via the ICH flash controller */ @@ -5012,8 +5012,8 @@ e1000_read_eeprom(struct e1000_hw *hw, /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have * acquired the EEPROM at this point, so any returns should relase it */ if (eeprom->type == e1000_eeprom_spi) { - uint16_t word_in; - uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; + u16 word_in; + u8 read_opcode = EEPROM_READ_OPCODE_SPI; if (e1000_spi_eeprom_ready(hw)) { e1000_release_eeprom(hw); @@ -5028,7 +5028,7 @@ e1000_read_eeprom(struct e1000_hw *hw, /* Send the READ command (opcode + addr) */ e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); - e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); + e1000_shift_out_ee_bits(hw, (u16)(offset*2), eeprom->address_bits); /* Read the data. The address of the eeprom internally increments with * each byte (spi) being read, saving on the overhead of eeprom setup @@ -5044,7 +5044,7 @@ e1000_read_eeprom(struct e1000_hw *hw, /* Send the READ command (opcode + addr) */ e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, eeprom->opcode_bits); - e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), + e1000_shift_out_ee_bits(hw, (u16)(offset + i), eeprom->address_bits); /* Read the data. For microwire, each word requires the overhead @@ -5068,14 +5068,14 @@ e1000_read_eeprom(struct e1000_hw *hw, * data - word read from the EEPROM * words - number of words to read *****************************************************************************/ -static int32_t +static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, - uint16_t offset, - uint16_t words, - uint16_t *data) + u16 offset, + u16 words, + u16 *data) { - uint32_t i, eerd = 0; - int32_t error = 0; + u32 i, eerd = 0; + s32 error = 0; for (i = 0; i < words; i++) { eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + @@ -5102,15 +5102,15 @@ e1000_read_eeprom_eerd(struct e1000_hw *hw, * data - word read from the EEPROM * words - number of words to read *****************************************************************************/ -static int32_t +static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, - uint16_t offset, - uint16_t words, - uint16_t *data) + u16 offset, + u16 words, + u16 *data) { - uint32_t register_value = 0; - uint32_t i = 0; - int32_t error = 0; + u32 register_value = 0; + u32 i = 0; + s32 error = 0; if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) return -E1000_ERR_SWFW_SYNC; @@ -5143,12 +5143,12 @@ e1000_write_eeprom_eewr(struct e1000_hw *hw, * * hw - Struct containing variables accessed by shared code *****************************************************************************/ -static int32_t +static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) { - uint32_t attempts = 100000; - uint32_t i, reg = 0; - int32_t done = E1000_ERR_EEPROM; + u32 attempts = 100000; + u32 i, reg = 0; + s32 done = E1000_ERR_EEPROM; for (i = 0; i < attempts; i++) { if (eerd == E1000_EEPROM_POLL_READ) @@ -5171,15 +5171,15 @@ e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) * * hw - Struct containing variables accessed by shared code ****************************************************************************/ -static boolean_t +static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) { - uint32_t eecd = 0; + u32 eecd = 0; DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); if (hw->mac_type == e1000_ich8lan) - return FALSE; + return false; if (hw->mac_type == e1000_82573) { eecd = E1000_READ_REG(hw, EECD); @@ -5189,10 +5189,10 @@ e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) /* If both bits are set, device is Flash type */ if (eecd == 0x03) { - return FALSE; + return false; } } - return TRUE; + return true; } /****************************************************************************** @@ -5204,16 +5204,15 @@ e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is * valid. *****************************************************************************/ -int32_t +s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw) { - uint16_t checksum = 0; - uint16_t i, eeprom_data; + u16 checksum = 0; + u16 i, eeprom_data; DEBUGFUNC("e1000_validate_eeprom_checksum"); - if ((hw->mac_type == e1000_82573) && - (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) { + if ((hw->mac_type == e1000_82573) && !e1000_is_onboard_nvm_eeprom(hw)) { /* Check bit 4 of word 10h. If it is 0, firmware is done updating * 10h-12h. Checksum may need to be fixed. */ e1000_read_eeprom(hw, 0x10, 1, &eeprom_data); @@ -5253,7 +5252,7 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw) checksum += eeprom_data; } - if (checksum == (uint16_t) EEPROM_SUM) + if (checksum == (u16) EEPROM_SUM) return E1000_SUCCESS; else { DEBUGOUT("EEPROM Checksum Invalid\n"); @@ -5269,12 +5268,12 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw) * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. * Writes the difference to word offset 63 of the EEPROM. *****************************************************************************/ -int32_t +s32 e1000_update_eeprom_checksum(struct e1000_hw *hw) { - uint32_t ctrl_ext; - uint16_t checksum = 0; - uint16_t i, eeprom_data; + u32 ctrl_ext; + u16 checksum = 0; + u16 i, eeprom_data; DEBUGFUNC("e1000_update_eeprom_checksum"); @@ -5285,7 +5284,7 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw) } checksum += eeprom_data; } - checksum = (uint16_t) EEPROM_SUM - checksum; + checksum = (u16) EEPROM_SUM - checksum; if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { DEBUGOUT("EEPROM Write Error\n"); return -E1000_ERR_EEPROM; @@ -5314,14 +5313,14 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw) * If e1000_update_eeprom_checksum is not called after this function, the * EEPROM will most likely contain an invalid checksum. *****************************************************************************/ -int32_t +s32 e1000_write_eeprom(struct e1000_hw *hw, - uint16_t offset, - uint16_t words, - uint16_t *data) + u16 offset, + u16 words, + u16 *data) { struct e1000_eeprom_info *eeprom = &hw->eeprom; - int32_t status = 0; + s32 status = 0; DEBUGFUNC("e1000_write_eeprom"); @@ -5339,7 +5338,7 @@ e1000_write_eeprom(struct e1000_hw *hw, } /* 82573 writes only through eewr */ - if (eeprom->use_eewr == TRUE) + if (eeprom->use_eewr) return e1000_write_eeprom_eewr(hw, offset, words, data); if (eeprom->type == e1000_eeprom_ich8) @@ -5371,19 +5370,19 @@ e1000_write_eeprom(struct e1000_hw *hw, * data - pointer to array of 8 bit words to be written to the EEPROM * *****************************************************************************/ -static int32_t +static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, - uint16_t offset, - uint16_t words, - uint16_t *data) + u16 offset, + u16 words, + u16 *data) { struct e1000_eeprom_info *eeprom = &hw->eeprom; - uint16_t widx = 0; + u16 widx = 0; DEBUGFUNC("e1000_write_eeprom_spi"); while (widx < words) { - uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; + u8 write_opcode = EEPROM_WRITE_OPCODE_SPI; if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; @@ -5402,14 +5401,14 @@ e1000_write_eeprom_spi(struct e1000_hw *hw, /* Send the Write command (8-bit opcode + addr) */ e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); - e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2), + e1000_shift_out_ee_bits(hw, (u16)((offset + widx)*2), eeprom->address_bits); /* Send the data */ /* Loop to allow for up to whole page write (32 bytes) of eeprom */ while (widx < words) { - uint16_t word_out = data[widx]; + u16 word_out = data[widx]; word_out = (word_out >> 8) | (word_out << 8); e1000_shift_out_ee_bits(hw, word_out, 16); widx++; @@ -5437,16 +5436,16 @@ e1000_write_eeprom_spi(struct e1000_hw *hw, * data - pointer to array of 16 bit words to be written to the EEPROM * *****************************************************************************/ -static int32_t +static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, - uint16_t offset, - uint16_t words, - uint16_t *data) + u16 offset, + u16 words, + u16 *data) { struct e1000_eeprom_info *eeprom = &hw->eeprom; - uint32_t eecd; - uint16_t words_written = 0; - uint16_t i = 0; + u32 eecd; + u16 words_written = 0; + u16 i = 0; DEBUGFUNC("e1000_write_eeprom_microwire"); @@ -5457,9 +5456,9 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw, * EEPROM into write/erase mode. */ e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, - (uint16_t)(eeprom->opcode_bits + 2)); + (u16)(eeprom->opcode_bits + 2)); - e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); + e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2)); /* Prepare the EEPROM */ e1000_standby_eeprom(hw); @@ -5469,7 +5468,7 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw, e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, eeprom->opcode_bits); - e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written), + e1000_shift_out_ee_bits(hw, (u16)(offset + words_written), eeprom->address_bits); /* Send the data */ @@ -5507,9 +5506,9 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw, * EEPROM out of write/erase mode. */ e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, - (uint16_t)(eeprom->opcode_bits + 2)); + (u16)(eeprom->opcode_bits + 2)); - e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); + e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2)); return E1000_SUCCESS; } @@ -5524,19 +5523,19 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw, * data - word read from the EEPROM * words - number of words to read *****************************************************************************/ -static int32_t +static s32 e1000_commit_shadow_ram(struct e1000_hw *hw) { - uint32_t attempts = 100000; - uint32_t eecd = 0; - uint32_t flop = 0; - uint32_t i = 0; - int32_t error = E1000_SUCCESS; - uint32_t old_bank_offset = 0; - uint32_t new_bank_offset = 0; - uint8_t low_byte = 0; - uint8_t high_byte = 0; - boolean_t sector_write_failed = FALSE; + u32 attempts = 100000; + u32 eecd = 0; + u32 flop = 0; + u32 i = 0; + s32 error = E1000_SUCCESS; + u32 old_bank_offset = 0; + u32 new_bank_offset = 0; + u8 low_byte = 0; + u8 high_byte = 0; + bool sector_write_failed = false; if (hw->mac_type == e1000_82573) { /* The flop register will be used to determine if flash type is STM */ @@ -5588,24 +5587,24 @@ e1000_commit_shadow_ram(struct e1000_hw *hw) e1000_erase_ich8_4k_segment(hw, 0); } - sector_write_failed = FALSE; + sector_write_failed = false; /* Loop for every byte in the shadow RAM, * which is in units of words. */ for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { /* Determine whether to write the value stored * in the other NVM bank or a modified value stored * in the shadow RAM */ - if (hw->eeprom_shadow_ram[i].modified == TRUE) { - low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word; + if (hw->eeprom_shadow_ram[i].modified) { + low_byte = (u8)hw->eeprom_shadow_ram[i].eeprom_word; udelay(100); error = e1000_verify_write_ich8_byte(hw, (i << 1) + new_bank_offset, low_byte); if (error != E1000_SUCCESS) - sector_write_failed = TRUE; + sector_write_failed = true; else { high_byte = - (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8); + (u8)(hw->eeprom_shadow_ram[i].eeprom_word >> 8); udelay(100); } } else { @@ -5616,7 +5615,7 @@ e1000_commit_shadow_ram(struct e1000_hw *hw) (i << 1) + new_bank_offset, low_byte); if (error != E1000_SUCCESS) - sector_write_failed = TRUE; + sector_write_failed = true; else { e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1, &high_byte); @@ -5624,10 +5623,10 @@ e1000_commit_shadow_ram(struct e1000_hw *hw) } } - /* If the write of the low byte was successful, go ahread and + /* If the write of the low byte was successful, go ahead and * write the high byte while checking to make sure that if it * is the signature byte, then it is handled properly */ - if (sector_write_failed == FALSE) { + if (!sector_write_failed) { /* If the word is 0x13, then make sure the signature bits * (15:14) are 11b until the commit has completed. * This will allow us to write 10b which indicates the @@ -5640,7 +5639,7 @@ e1000_commit_shadow_ram(struct e1000_hw *hw) error = e1000_verify_write_ich8_byte(hw, (i << 1) + new_bank_offset + 1, high_byte); if (error != E1000_SUCCESS) - sector_write_failed = TRUE; + sector_write_failed = true; } else { /* If the write failed then break from the loop and @@ -5651,7 +5650,7 @@ e1000_commit_shadow_ram(struct e1000_hw *hw) /* Don't bother writing the segment valid bits if sector * programming failed. */ - if (sector_write_failed == FALSE) { + if (!sector_write_failed) { /* Finally validate the new segment by setting bit 15:14 * to 10b in word 0x13 , this can be done without an * erase as well since these bits are 11 to start with @@ -5673,7 +5672,7 @@ e1000_commit_shadow_ram(struct e1000_hw *hw) /* Clear the now not used entry in the cache */ for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { - hw->eeprom_shadow_ram[i].modified = FALSE; + hw->eeprom_shadow_ram[i].modified = false; hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; } } @@ -5688,11 +5687,11 @@ e1000_commit_shadow_ram(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code *****************************************************************************/ -int32_t +s32 e1000_read_mac_addr(struct e1000_hw * hw) { - uint16_t offset; - uint16_t eeprom_data, i; + u16 offset; + u16 eeprom_data, i; DEBUGFUNC("e1000_read_mac_addr"); @@ -5702,8 +5701,8 @@ e1000_read_mac_addr(struct e1000_hw * hw) DEBUGOUT("EEPROM Read Error\n"); return -E1000_ERR_EEPROM; } - hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); - hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); + hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF); + hw->perm_mac_addr[i+1] = (u8) (eeprom_data >> 8); } switch (hw->mac_type) { @@ -5735,8 +5734,8 @@ e1000_read_mac_addr(struct e1000_hw * hw) static void e1000_init_rx_addrs(struct e1000_hw *hw) { - uint32_t i; - uint32_t rar_num; + u32 i; + u32 rar_num; DEBUGFUNC("e1000_init_rx_addrs"); @@ -5750,7 +5749,7 @@ e1000_init_rx_addrs(struct e1000_hw *hw) /* Reserve a spot for the Locally Administered Address to work around * an 82571 issue in which a reset on one port will reload the MAC on * the other port. */ - if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) + if ((hw->mac_type == e1000_82571) && (hw->laa_is_present)) rar_num -= 1; if (hw->mac_type == e1000_ich8lan) rar_num = E1000_RAR_ENTRIES_ICH8LAN; @@ -5771,11 +5770,11 @@ e1000_init_rx_addrs(struct e1000_hw *hw) * hw - Struct containing variables accessed by shared code * mc_addr - the multicast address to hash *****************************************************************************/ -uint32_t +u32 e1000_hash_mc_addr(struct e1000_hw *hw, - uint8_t *mc_addr) + u8 *mc_addr) { - uint32_t hash_value = 0; + u32 hash_value = 0; /* The portion of the address that is used for the hash table is * determined by the mc_filter_type setting. @@ -5788,37 +5787,37 @@ e1000_hash_mc_addr(struct e1000_hw *hw, case 0: if (hw->mac_type == e1000_ich8lan) { /* [47:38] i.e. 0x158 for above example address */ - hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2)); + hash_value = ((mc_addr[4] >> 6) | (((u16) mc_addr[5]) << 2)); } else { /* [47:36] i.e. 0x563 for above example address */ - hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); + hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4)); } break; case 1: if (hw->mac_type == e1000_ich8lan) { /* [46:37] i.e. 0x2B1 for above example address */ - hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3)); + hash_value = ((mc_addr[4] >> 5) | (((u16) mc_addr[5]) << 3)); } else { /* [46:35] i.e. 0xAC6 for above example address */ - hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); + hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5)); } break; case 2: if (hw->mac_type == e1000_ich8lan) { /*[45:36] i.e. 0x163 for above example address */ - hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); + hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4)); } else { /* [45:34] i.e. 0x5D8 for above example address */ - hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); + hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6)); } break; case 3: if (hw->mac_type == e1000_ich8lan) { /* [43:34] i.e. 0x18D for above example address */ - hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); + hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6)); } else { /* [43:32] i.e. 0x634 for above example address */ - hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); + hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8)); } break; } @@ -5838,11 +5837,11 @@ e1000_hash_mc_addr(struct e1000_hw *hw, *****************************************************************************/ void e1000_mta_set(struct e1000_hw *hw, - uint32_t hash_value) + u32 hash_value) { - uint32_t hash_bit, hash_reg; - uint32_t mta; - uint32_t temp; + u32 hash_bit, hash_reg; + u32 mta; + u32 temp; /* The MTA is a register array of 128 32-bit registers. * It is treated like an array of 4096 bits. We want to set @@ -5887,18 +5886,18 @@ e1000_mta_set(struct e1000_hw *hw, *****************************************************************************/ void e1000_rar_set(struct e1000_hw *hw, - uint8_t *addr, - uint32_t index) + u8 *addr, + u32 index) { - uint32_t rar_low, rar_high; + u32 rar_low, rar_high; /* HW expects these in little endian so we reverse the byte order * from network order (big endian) to little endian */ - rar_low = ((uint32_t) addr[0] | - ((uint32_t) addr[1] << 8) | - ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); - rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); + rar_low = ((u32) addr[0] | + ((u32) addr[1] << 8) | + ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); + rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx * unit hang. @@ -5922,7 +5921,7 @@ e1000_rar_set(struct e1000_hw *hw, case e1000_82571: case e1000_82572: case e1000_80003es2lan: - if (hw->leave_av_bit_off == TRUE) + if (hw->leave_av_bit_off) break; default: /* Indicate to hardware the Address is Valid. */ @@ -5945,10 +5944,10 @@ e1000_rar_set(struct e1000_hw *hw, *****************************************************************************/ void e1000_write_vfta(struct e1000_hw *hw, - uint32_t offset, - uint32_t value) + u32 offset, + u32 value) { - uint32_t temp; + u32 temp; if (hw->mac_type == e1000_ich8lan) return; @@ -5973,10 +5972,10 @@ e1000_write_vfta(struct e1000_hw *hw, static void e1000_clear_vfta(struct e1000_hw *hw) { - uint32_t offset; - uint32_t vfta_value = 0; - uint32_t vfta_offset = 0; - uint32_t vfta_bit_in_reg = 0; + u32 offset; + u32 vfta_value = 0; + u32 vfta_offset = 0; + u32 vfta_bit_in_reg = 0; if (hw->mac_type == e1000_ich8lan) return; @@ -6004,15 +6003,15 @@ e1000_clear_vfta(struct e1000_hw *hw) } } -static int32_t +static s32 e1000_id_led_init(struct e1000_hw * hw) { - uint32_t ledctl; - const uint32_t ledctl_mask = 0x000000FF; - const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; - const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; - uint16_t eeprom_data, i, temp; - const uint16_t led_mask = 0x0F; + u32 ledctl; + const u32 ledctl_mask = 0x000000FF; + const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; + const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; + u16 eeprom_data, i, temp; + const u16 led_mask = 0x0F; DEBUGFUNC("e1000_id_led_init"); @@ -6087,11 +6086,11 @@ e1000_id_led_init(struct e1000_hw * hw) * * hw - Struct containing variables accessed by shared code *****************************************************************************/ -int32_t +s32 e1000_setup_led(struct e1000_hw *hw) { - uint32_t ledctl; - int32_t ret_val = E1000_SUCCESS; + u32 ledctl; + s32 ret_val = E1000_SUCCESS; DEBUGFUNC("e1000_setup_led"); @@ -6112,7 +6111,7 @@ e1000_setup_led(struct e1000_hw *hw) if (ret_val) return ret_val; ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, - (uint16_t)(hw->phy_spd_default & + (u16)(hw->phy_spd_default & ~IGP01E1000_GMII_SPD)); if (ret_val) return ret_val; @@ -6146,11 +6145,11 @@ e1000_setup_led(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code *****************************************************************************/ -int32_t +s32 e1000_blink_led_start(struct e1000_hw *hw) { - int16_t i; - uint32_t ledctl_blink = 0; + s16 i; + u32 ledctl_blink = 0; DEBUGFUNC("e1000_id_led_blink_on"); @@ -6181,10 +6180,10 @@ e1000_blink_led_start(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code *****************************************************************************/ -int32_t +s32 e1000_cleanup_led(struct e1000_hw *hw) { - int32_t ret_val = E1000_SUCCESS; + s32 ret_val = E1000_SUCCESS; DEBUGFUNC("e1000_cleanup_led"); @@ -6223,10 +6222,10 @@ e1000_cleanup_led(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code *****************************************************************************/ -int32_t +s32 e1000_led_on(struct e1000_hw *hw) { - uint32_t ctrl = E1000_READ_REG(hw, CTRL); + u32 ctrl = E1000_READ_REG(hw, CTRL); DEBUGFUNC("e1000_led_on"); @@ -6274,10 +6273,10 @@ e1000_led_on(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code *****************************************************************************/ -int32_t +s32 e1000_led_off(struct e1000_hw *hw) { - uint32_t ctrl = E1000_READ_REG(hw, CTRL); + u32 ctrl = E1000_READ_REG(hw, CTRL); DEBUGFUNC("e1000_led_off"); @@ -6328,7 +6327,7 @@ e1000_led_off(struct e1000_hw *hw) static void e1000_clear_hw_cntrs(struct e1000_hw *hw) { - volatile uint32_t temp; + volatile u32 temp; temp = E1000_READ_REG(hw, CRCERRS); temp = E1000_READ_REG(hw, SYMERRS); @@ -6425,7 +6424,7 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw) * hw - Struct containing variables accessed by shared code * * Call this after e1000_init_hw. You may override the IFS defaults by setting - * hw->ifs_params_forced to TRUE. However, you must initialize hw-> + * hw->ifs_params_forced to true. However, you must initialize hw-> * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio * before calling this function. *****************************************************************************/ @@ -6442,7 +6441,7 @@ e1000_reset_adaptive(struct e1000_hw *hw) hw->ifs_step_size = IFS_STEP; hw->ifs_ratio = IFS_RATIO; } - hw->in_ifs_mode = FALSE; + hw->in_ifs_mode = false; E1000_WRITE_REG(hw, AIT, 0); } else { DEBUGOUT("Not in Adaptive IFS mode!\n"); @@ -6465,7 +6464,7 @@ e1000_update_adaptive(struct e1000_hw *hw) if (hw->adaptive_ifs) { if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { if (hw->tx_packet_delta > MIN_NUM_XMITS) { - hw->in_ifs_mode = TRUE; + hw->in_ifs_mode = true; if (hw->current_ifs_val < hw->ifs_max_val) { if (hw->current_ifs_val == 0) hw->current_ifs_val = hw->ifs_min_val; @@ -6477,7 +6476,7 @@ e1000_update_adaptive(struct e1000_hw *hw) } else { if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { hw->current_ifs_val = 0; - hw->in_ifs_mode = FALSE; + hw->in_ifs_mode = false; E1000_WRITE_REG(hw, AIT, 0); } } @@ -6496,10 +6495,10 @@ e1000_update_adaptive(struct e1000_hw *hw) void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, - uint32_t frame_len, - uint8_t *mac_addr) + u32 frame_len, + u8 *mac_addr) { - uint64_t carry_bit; + u64 carry_bit; /* First adjust the frame length. */ frame_len--; @@ -6528,7 +6527,7 @@ e1000_tbi_adjust_stats(struct e1000_hw *hw, * since the test for a multicast frame will test positive on * a broadcast frame. */ - if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) + if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff)) /* Broadcast packet */ stats->bprc++; else if (*mac_addr & 0x01) @@ -6574,9 +6573,9 @@ e1000_tbi_adjust_stats(struct e1000_hw *hw, void e1000_get_bus_info(struct e1000_hw *hw) { - int32_t ret_val; - uint16_t pci_ex_link_status; - uint32_t status; + s32 ret_val; + u16 pci_ex_link_status; + u32 status; switch (hw->mac_type) { case e1000_82542_rev2_0: @@ -6648,8 +6647,8 @@ e1000_get_bus_info(struct e1000_hw *hw) *****************************************************************************/ static void e1000_write_reg_io(struct e1000_hw *hw, - uint32_t offset, - uint32_t value) + u32 offset, + u32 value) { unsigned long io_addr = hw->io_base; unsigned long io_data = hw->io_base + 4; @@ -6673,15 +6672,15 @@ e1000_write_reg_io(struct e1000_hw *hw, * register to the minimum and maximum range. * For IGP phy's, the function calculates the range by the AGC registers. *****************************************************************************/ -static int32_t +static s32 e1000_get_cable_length(struct e1000_hw *hw, - uint16_t *min_length, - uint16_t *max_length) + u16 *min_length, + u16 *max_length) { - int32_t ret_val; - uint16_t agc_value = 0; - uint16_t i, phy_data; - uint16_t cable_length; + s32 ret_val; + u16 agc_value = 0; + u16 i, phy_data; + u16 cable_length; DEBUGFUNC("e1000_get_cable_length"); @@ -6752,9 +6751,9 @@ e1000_get_cable_length(struct e1000_hw *hw, break; } } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ - uint16_t cur_agc_value; - uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; - uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = + u16 cur_agc_value; + u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; + u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {IGP01E1000_PHY_AGC_A, IGP01E1000_PHY_AGC_B, IGP01E1000_PHY_AGC_C, @@ -6800,9 +6799,9 @@ e1000_get_cable_length(struct e1000_hw *hw, IGP01E1000_AGC_RANGE; } else if (hw->phy_type == e1000_phy_igp_2 || hw->phy_type == e1000_phy_igp_3) { - uint16_t cur_agc_index, max_agc_index = 0; - uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; - uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = + u16 cur_agc_index, max_agc_index = 0; + u16 min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; + u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {IGP02E1000_PHY_AGC_A, IGP02E1000_PHY_AGC_B, IGP02E1000_PHY_AGC_C, @@ -6864,12 +6863,12 @@ e1000_get_cable_length(struct e1000_hw *hw, * return 0. If the link speed is 1000 Mbps the polarity status is in the * IGP01E1000_PHY_PCS_INIT_REG. *****************************************************************************/ -static int32_t +static s32 e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity) { - int32_t ret_val; - uint16_t phy_data; + s32 ret_val; + u16 phy_data; DEBUGFUNC("e1000_check_polarity"); @@ -6940,11 +6939,11 @@ e1000_check_polarity(struct e1000_hw *hw, * Link Health register. In IGP this bit is latched high, so the driver must * read it immediately after link is established. *****************************************************************************/ -static int32_t +static s32 e1000_check_downshift(struct e1000_hw *hw) { - int32_t ret_val; - uint16_t phy_data; + s32 ret_val; + u16 phy_data; DEBUGFUNC("e1000_check_downshift"); @@ -6968,7 +6967,7 @@ e1000_check_downshift(struct e1000_hw *hw) M88E1000_PSSR_DOWNSHIFT_SHIFT; } else if (hw->phy_type == e1000_phy_ife) { /* e1000_phy_ife supports 10/100 speed only */ - hw->speed_downgraded = FALSE; + hw->speed_downgraded = false; } return E1000_SUCCESS; @@ -6986,18 +6985,18 @@ e1000_check_downshift(struct e1000_hw *hw) * ****************************************************************************/ -static int32_t +static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, - boolean_t link_up) + bool link_up) { - int32_t ret_val; - uint16_t phy_data, phy_saved_data, speed, duplex, i; - uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = + s32 ret_val; + u16 phy_data, phy_saved_data, speed, duplex, i; + u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {IGP01E1000_PHY_AGC_PARAM_A, IGP01E1000_PHY_AGC_PARAM_B, IGP01E1000_PHY_AGC_PARAM_C, IGP01E1000_PHY_AGC_PARAM_D}; - uint16_t min_length, max_length; + u16 min_length, max_length; DEBUGFUNC("e1000_config_dsp_after_link_change"); @@ -7039,8 +7038,8 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw, if ((hw->ffe_config_state == e1000_ffe_config_enabled) && (min_length < e1000_igp_cable_length_50)) { - uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; - uint32_t idle_errs = 0; + u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; + u32 idle_errs = 0; /* clear previous idle error counts */ ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, @@ -7174,11 +7173,11 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw, * * hw - Struct containing variables accessed by shared code ****************************************************************************/ -static int32_t +static s32 e1000_set_phy_mode(struct e1000_hw *hw) { - int32_t ret_val; - uint16_t eeprom_data; + s32 ret_val; + u16 eeprom_data; DEBUGFUNC("e1000_set_phy_mode"); @@ -7198,7 +7197,7 @@ e1000_set_phy_mode(struct e1000_hw *hw) if (ret_val) return ret_val; - hw->phy_reset_disable = FALSE; + hw->phy_reset_disable = false; } } @@ -7219,13 +7218,13 @@ e1000_set_phy_mode(struct e1000_hw *hw) * ****************************************************************************/ -static int32_t +static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, - boolean_t active) + bool active) { - uint32_t phy_ctrl = 0; - int32_t ret_val; - uint16_t phy_data; + u32 phy_ctrl = 0; + s32 ret_val; + u16 phy_data; DEBUGFUNC("e1000_set_d3_lplu_state"); if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 @@ -7349,13 +7348,13 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw, * ****************************************************************************/ -static int32_t +static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, - boolean_t active) + bool active) { - uint32_t phy_ctrl = 0; - int32_t ret_val; - uint16_t phy_data; + u32 phy_ctrl = 0; + s32 ret_val; + u16 phy_data; DEBUGFUNC("e1000_set_d0_lplu_state"); if (hw->mac_type <= e1000_82547_rev_2) @@ -7440,12 +7439,12 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, * * hw - Struct containing variables accessed by shared code *****************************************************************************/ -static int32_t +static s32 e1000_set_vco_speed(struct e1000_hw *hw) { - int32_t ret_val; - uint16_t default_page = 0; - uint16_t phy_data; + s32 ret_val; + u16 default_page = 0; + u16 phy_data; DEBUGFUNC("e1000_set_vco_speed"); @@ -7504,18 +7503,18 @@ e1000_set_vco_speed(struct e1000_hw *hw) * * returns: - E1000_SUCCESS . ****************************************************************************/ -static int32_t -e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer) +static s32 +e1000_host_if_read_cookie(struct e1000_hw * hw, u8 *buffer) { - uint8_t i; - uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; - uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; + u8 i; + u32 offset = E1000_MNG_DHCP_COOKIE_OFFSET; + u8 length = E1000_MNG_DHCP_COOKIE_LENGTH; length = (length >> 2); offset = (offset >> 2); for (i = 0; i < length; i++) { - *((uint32_t *) buffer + i) = + *((u32 *) buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); } return E1000_SUCCESS; @@ -7531,11 +7530,11 @@ e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer) * timeout * - E1000_SUCCESS for success. ****************************************************************************/ -static int32_t +static s32 e1000_mng_enable_host_if(struct e1000_hw * hw) { - uint32_t hicr; - uint8_t i; + u32 hicr; + u8 i; /* Check that the host interface is enabled. */ hicr = E1000_READ_REG(hw, HICR); @@ -7565,14 +7564,14 @@ e1000_mng_enable_host_if(struct e1000_hw * hw) * * returns - E1000_SUCCESS for success. ****************************************************************************/ -static int32_t -e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer, - uint16_t length, uint16_t offset, uint8_t *sum) +static s32 +e1000_mng_host_if_write(struct e1000_hw * hw, u8 *buffer, + u16 length, u16 offset, u8 *sum) { - uint8_t *tmp; - uint8_t *bufptr = buffer; - uint32_t data = 0; - uint16_t remaining, i, j, prev_bytes; + u8 *tmp; + u8 *bufptr = buffer; + u32 data = 0; + u16 remaining, i, j, prev_bytes; /* sum = only sum of the data and it is not checksum */ @@ -7580,14 +7579,14 @@ e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer, return -E1000_ERR_PARAM; } - tmp = (uint8_t *)&data; + tmp = (u8 *)&data; prev_bytes = offset & 0x3; offset &= 0xFFFC; offset >>= 2; if (prev_bytes) { data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); - for (j = prev_bytes; j < sizeof(uint32_t); j++) { + for (j = prev_bytes; j < sizeof(u32); j++) { *(tmp + j) = *bufptr++; *sum += *(tmp + j); } @@ -7605,7 +7604,7 @@ e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer, /* The device driver writes the relevant command block into the * ram area. */ for (i = 0; i < length; i++) { - for (j = 0; j < sizeof(uint32_t); j++) { + for (j = 0; j < sizeof(u32); j++) { *(tmp + j) = *bufptr++; *sum += *(tmp + j); } @@ -7613,7 +7612,7 @@ e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer, E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); } if (remaining) { - for (j = 0; j < sizeof(uint32_t); j++) { + for (j = 0; j < sizeof(u32); j++) { if (j < remaining) *(tmp + j) = *bufptr++; else @@ -7633,23 +7632,23 @@ e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer, * * returns - E1000_SUCCESS for success. ****************************************************************************/ -static int32_t +static s32 e1000_mng_write_cmd_header(struct e1000_hw * hw, struct e1000_host_mng_command_header * hdr) { - uint16_t i; - uint8_t sum; - uint8_t *buffer; + u16 i; + u8 sum; + u8 *buffer; /* Write the whole command header structure which includes sum of * the buffer */ - uint16_t length = sizeof(struct e1000_host_mng_command_header); + u16 length = sizeof(struct e1000_host_mng_command_header); sum = hdr->checksum; hdr->checksum = 0; - buffer = (uint8_t *) hdr; + buffer = (u8 *) hdr; i = length; while (i--) sum += buffer[i]; @@ -7659,7 +7658,7 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw, length >>= 2; /* The device driver writes the relevant command block into the ram area. */ for (i = 0; i < length; i++) { - E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); + E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((u32 *) hdr + i)); E1000_WRITE_FLUSH(hw); } @@ -7673,10 +7672,10 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw, * * returns - E1000_SUCCESS for success. ****************************************************************************/ -static int32_t +static s32 e1000_mng_write_commit(struct e1000_hw * hw) { - uint32_t hicr; + u32 hicr; hicr = E1000_READ_REG(hw, HICR); /* Setting this bit tells the ARC that a new command is pending. */ @@ -7689,35 +7688,35 @@ e1000_mng_write_commit(struct e1000_hw * hw) /***************************************************************************** * This function checks the mode of the firmware. * - * returns - TRUE when the mode is IAMT or FALSE. + * returns - true when the mode is IAMT or false. ****************************************************************************/ -boolean_t +bool e1000_check_mng_mode(struct e1000_hw *hw) { - uint32_t fwsm; + u32 fwsm; fwsm = E1000_READ_REG(hw, FWSM); if (hw->mac_type == e1000_ich8lan) { if ((fwsm & E1000_FWSM_MODE_MASK) == (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) - return TRUE; + return true; } else if ((fwsm & E1000_FWSM_MODE_MASK) == (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) - return TRUE; + return true; - return FALSE; + return false; } /***************************************************************************** * This function writes the dhcp info . ****************************************************************************/ -int32_t -e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, - uint16_t length) +s32 +e1000_mng_write_dhcp_info(struct e1000_hw * hw, u8 *buffer, + u16 length) { - int32_t ret_val; + s32 ret_val; struct e1000_host_mng_command_header hdr; hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; @@ -7745,11 +7744,11 @@ e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, * * returns - checksum of buffer contents. ****************************************************************************/ -static uint8_t -e1000_calculate_mng_checksum(char *buffer, uint32_t length) +static u8 +e1000_calculate_mng_checksum(char *buffer, u32 length) { - uint8_t sum = 0; - uint32_t i; + u8 sum = 0; + u32 i; if (!buffer) return 0; @@ -7757,23 +7756,23 @@ e1000_calculate_mng_checksum(char *buffer, uint32_t length) for (i=0; i < length; i++) sum += buffer[i]; - return (uint8_t) (0 - sum); + return (u8) (0 - sum); } /***************************************************************************** * This function checks whether tx pkt filtering needs to be enabled or not. * - * returns - TRUE for packet filtering or FALSE. + * returns - true for packet filtering or false. ****************************************************************************/ -boolean_t +bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) { /* called in init as well as watchdog timer functions */ - int32_t ret_val, checksum; - boolean_t tx_filter = FALSE; + s32 ret_val, checksum; + bool tx_filter = false; struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); - uint8_t *buffer = (uint8_t *) &(hw->mng_cookie); + u8 *buffer = (u8 *) &(hw->mng_cookie); if (e1000_check_mng_mode(hw)) { ret_val = e1000_mng_enable_host_if(hw); @@ -7787,11 +7786,11 @@ e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) E1000_MNG_DHCP_COOKIE_LENGTH)) { if (hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) - tx_filter = TRUE; + tx_filter = true; } else - tx_filter = TRUE; + tx_filter = true; } else - tx_filter = TRUE; + tx_filter = true; } } @@ -7804,41 +7803,41 @@ e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code * - * returns: - TRUE/FALSE + * returns: - true/false * *****************************************************************************/ -uint32_t +u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw) { - uint32_t manc; - uint32_t fwsm, factps; + u32 manc; + u32 fwsm, factps; if (hw->asf_firmware_present) { manc = E1000_READ_REG(hw, MANC); if (!(manc & E1000_MANC_RCV_TCO_EN) || !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) - return FALSE; - if (e1000_arc_subsystem_valid(hw) == TRUE) { + return false; + if (e1000_arc_subsystem_valid(hw)) { fwsm = E1000_READ_REG(hw, FWSM); factps = E1000_READ_REG(hw, FACTPS); if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) == e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG)) - return TRUE; + return true; } else if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) - return TRUE; + return true; } - return FALSE; + return false; } -static int32_t +static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw) { - int32_t ret_val; - uint16_t mii_status_reg; - uint16_t i; + s32 ret_val; + u16 mii_status_reg; + u16 i; /* Polarity reversal workaround for forced 10F/10H links. */ @@ -7930,7 +7929,7 @@ e1000_polarity_reversal_workaround(struct e1000_hw *hw) static void e1000_set_pci_express_master_disable(struct e1000_hw *hw) { - uint32_t ctrl; + u32 ctrl; DEBUGFUNC("e1000_set_pci_express_master_disable"); @@ -7953,10 +7952,10 @@ e1000_set_pci_express_master_disable(struct e1000_hw *hw) * E1000_SUCCESS master requests disabled. * ******************************************************************************/ -int32_t +s32 e1000_disable_pciex_master(struct e1000_hw *hw) { - int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ + s32 timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ DEBUGFUNC("e1000_disable_pciex_master"); @@ -7991,10 +7990,10 @@ e1000_disable_pciex_master(struct e1000_hw *hw) * E1000_SUCCESS at any other case. * ******************************************************************************/ -static int32_t +static s32 e1000_get_auto_rd_done(struct e1000_hw *hw) { - int32_t timeout = AUTO_READ_DONE_TIMEOUT; + s32 timeout = AUTO_READ_DONE_TIMEOUT; DEBUGFUNC("e1000_get_auto_rd_done"); @@ -8039,11 +8038,11 @@ e1000_get_auto_rd_done(struct e1000_hw *hw) * E1000_SUCCESS at any other case. * ***************************************************************************/ -static int32_t +static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) { - int32_t timeout = PHY_CFG_TIMEOUT; - uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; + s32 timeout = PHY_CFG_TIMEOUT; + u32 cfg_mask = E1000_EEPROM_CFG_DONE; DEBUGFUNC("e1000_get_phy_cfg_done"); @@ -8086,11 +8085,11 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw) * E1000_SUCCESS at any other case. * ***************************************************************************/ -static int32_t +static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) { - int32_t timeout; - uint32_t swsm; + s32 timeout; + u32 swsm; DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); @@ -8139,7 +8138,7 @@ e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) { - uint32_t swsm; + u32 swsm; DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); @@ -8165,11 +8164,11 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) * E1000_SUCCESS at any other case. * ***************************************************************************/ -static int32_t +static s32 e1000_get_software_semaphore(struct e1000_hw *hw) { - int32_t timeout = hw->eeprom.word_size + 1; - uint32_t swsm; + s32 timeout = hw->eeprom.word_size + 1; + u32 swsm; DEBUGFUNC("e1000_get_software_semaphore"); @@ -8204,7 +8203,7 @@ e1000_get_software_semaphore(struct e1000_hw *hw) static void e1000_release_software_semaphore(struct e1000_hw *hw) { - uint32_t swsm; + u32 swsm; DEBUGFUNC("e1000_release_software_semaphore"); @@ -8229,11 +8228,11 @@ e1000_release_software_semaphore(struct e1000_hw *hw) * E1000_SUCCESS * *****************************************************************************/ -int32_t +s32 e1000_check_phy_reset_block(struct e1000_hw *hw) { - uint32_t manc = 0; - uint32_t fwsm = 0; + u32 manc = 0; + u32 fwsm = 0; if (hw->mac_type == e1000_ich8lan) { fwsm = E1000_READ_REG(hw, FWSM); @@ -8247,10 +8246,10 @@ e1000_check_phy_reset_block(struct e1000_hw *hw) E1000_BLK_PHY_RESET : E1000_SUCCESS; } -static uint8_t +static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw) { - uint32_t fwsm; + u32 fwsm; /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC * may not be provided a DMA clock when no manageability features are @@ -8264,14 +8263,14 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw) case e1000_80003es2lan: fwsm = E1000_READ_REG(hw, FWSM); if ((fwsm & E1000_FWSM_MODE_MASK) != 0) - return TRUE; + return true; break; case e1000_ich8lan: - return TRUE; + return true; default: break; } - return FALSE; + return false; } @@ -8284,10 +8283,10 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw) * returns: E1000_SUCCESS * *****************************************************************************/ -static int32_t -e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop) +static s32 +e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop) { - uint32_t gcr_reg = 0; + u32 gcr_reg = 0; DEBUGFUNC("e1000_set_pci_ex_no_snoop"); @@ -8304,7 +8303,7 @@ e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop) E1000_WRITE_REG(hw, GCR, gcr_reg); } if (hw->mac_type == e1000_ich8lan) { - uint32_t ctrl_ext; + u32 ctrl_ext; E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL); @@ -8325,11 +8324,11 @@ e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop) * hw: Struct containing variables accessed by shared code * ***************************************************************************/ -static int32_t +static s32 e1000_get_software_flag(struct e1000_hw *hw) { - int32_t timeout = PHY_CFG_TIMEOUT; - uint32_t extcnf_ctrl; + s32 timeout = PHY_CFG_TIMEOUT; + u32 extcnf_ctrl; DEBUGFUNC("e1000_get_software_flag"); @@ -8367,7 +8366,7 @@ e1000_get_software_flag(struct e1000_hw *hw) static void e1000_release_software_flag(struct e1000_hw *hw) { - uint32_t extcnf_ctrl; + u32 extcnf_ctrl; DEBUGFUNC("e1000_release_software_flag"); @@ -8389,16 +8388,16 @@ e1000_release_software_flag(struct e1000_hw *hw) * data - word read from the EEPROM * words - number of words to read *****************************************************************************/ -static int32_t -e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, - uint16_t *data) +static s32 +e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, + u16 *data) { - int32_t error = E1000_SUCCESS; - uint32_t flash_bank = 0; - uint32_t act_offset = 0; - uint32_t bank_offset = 0; - uint16_t word = 0; - uint16_t i = 0; + s32 error = E1000_SUCCESS; + u32 flash_bank = 0; + u32 act_offset = 0; + u32 bank_offset = 0; + u16 word = 0; + u16 i = 0; /* We need to know which is the valid flash bank. In the event * that we didn't allocate eeprom_shadow_ram, we may not be @@ -8417,7 +8416,7 @@ e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, for (i = 0; i < words; i++) { if (hw->eeprom_shadow_ram != NULL && - hw->eeprom_shadow_ram[offset+i].modified == TRUE) { + hw->eeprom_shadow_ram[offset+i].modified) { data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; } else { /* The NVM part needs a byte offset, hence * 2 */ @@ -8445,12 +8444,12 @@ e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, * words - number of words to write * data - words to write to the EEPROM *****************************************************************************/ -static int32_t -e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, - uint16_t *data) +static s32 +e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, + u16 *data) { - uint32_t i = 0; - int32_t error = E1000_SUCCESS; + u32 i = 0; + s32 error = E1000_SUCCESS; error = e1000_get_software_flag(hw); if (error != E1000_SUCCESS) @@ -8466,7 +8465,7 @@ e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, if (hw->eeprom_shadow_ram != NULL) { for (i = 0; i < words; i++) { if ((offset + i) < E1000_SHADOW_RAM_WORDS) { - hw->eeprom_shadow_ram[offset+i].modified = TRUE; + hw->eeprom_shadow_ram[offset+i].modified = true; hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i]; } else { error = -E1000_ERR_EEPROM; @@ -8492,12 +8491,12 @@ e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, * * hw - The pointer to the hw structure ****************************************************************************/ -static int32_t +static s32 e1000_ich8_cycle_init(struct e1000_hw *hw) { union ich8_hws_flash_status hsfsts; - int32_t error = E1000_ERR_EEPROM; - int32_t i = 0; + s32 error = E1000_ERR_EEPROM; + s32 i = 0; DEBUGFUNC("e1000_ich8_cycle_init"); @@ -8559,13 +8558,13 @@ e1000_ich8_cycle_init(struct e1000_hw *hw) * * hw - The pointer to the hw structure ****************************************************************************/ -static int32_t -e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout) +static s32 +e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout) { union ich8_hws_flash_ctrl hsflctl; union ich8_hws_flash_status hsfsts; - int32_t error = E1000_ERR_EEPROM; - uint32_t i = 0; + s32 error = E1000_ERR_EEPROM; + u32 i = 0; /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); @@ -8594,16 +8593,16 @@ e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout) * size - Size of data to read, 1=byte 2=word * data - Pointer to the word to store the value read. *****************************************************************************/ -static int32_t -e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, - uint32_t size, uint16_t* data) +static s32 +e1000_read_ich8_data(struct e1000_hw *hw, u32 index, + u32 size, u16* data) { union ich8_hws_flash_status hsfsts; union ich8_hws_flash_ctrl hsflctl; - uint32_t flash_linear_address; - uint32_t flash_data = 0; - int32_t error = -E1000_ERR_EEPROM; - int32_t count = 0; + u32 flash_linear_address; + u32 flash_data = 0; + s32 error = -E1000_ERR_EEPROM; + s32 count = 0; DEBUGFUNC("e1000_read_ich8_data"); @@ -8641,9 +8640,9 @@ e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, if (error == E1000_SUCCESS) { flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0); if (size == 1) { - *data = (uint8_t)(flash_data & 0x000000FF); + *data = (u8)(flash_data & 0x000000FF); } else if (size == 2) { - *data = (uint16_t)(flash_data & 0x0000FFFF); + *data = (u16)(flash_data & 0x0000FFFF); } break; } else { @@ -8673,16 +8672,16 @@ e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, * size - Size of data to read, 1=byte 2=word * data - The byte(s) to write to the NVM. *****************************************************************************/ -static int32_t -e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, - uint16_t data) +static s32 +e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size, + u16 data) { union ich8_hws_flash_status hsfsts; union ich8_hws_flash_ctrl hsflctl; - uint32_t flash_linear_address; - uint32_t flash_data = 0; - int32_t error = -E1000_ERR_EEPROM; - int32_t count = 0; + u32 flash_linear_address; + u32 flash_data = 0; + s32 error = -E1000_ERR_EEPROM; + s32 count = 0; DEBUGFUNC("e1000_write_ich8_data"); @@ -8711,9 +8710,9 @@ e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); if (size == 1) - flash_data = (uint32_t)data & 0x00FF; + flash_data = (u32)data & 0x00FF; else - flash_data = (uint32_t)data; + flash_data = (u32)data; E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); @@ -8748,15 +8747,15 @@ e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, * index - The index of the byte to read. * data - Pointer to a byte to store the value read. *****************************************************************************/ -static int32_t -e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data) +static s32 +e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8* data) { - int32_t status = E1000_SUCCESS; - uint16_t word = 0; + s32 status = E1000_SUCCESS; + u16 word = 0; status = e1000_read_ich8_data(hw, index, 1, &word); if (status == E1000_SUCCESS) { - *data = (uint8_t)word; + *data = (u8)word; } return status; @@ -8771,11 +8770,11 @@ e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data) * index - The index of the byte to write. * byte - The byte to write to the NVM. *****************************************************************************/ -static int32_t -e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte) +static s32 +e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte) { - int32_t error = E1000_SUCCESS; - int32_t program_retries = 0; + s32 error = E1000_SUCCESS; + s32 program_retries = 0; DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); @@ -8804,11 +8803,11 @@ e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte) * index - The index of the byte to read. * data - The byte to write to the NVM. *****************************************************************************/ -static int32_t -e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data) +static s32 +e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 data) { - int32_t status = E1000_SUCCESS; - uint16_t word = (uint16_t)data; + s32 status = E1000_SUCCESS; + u16 word = (u16)data; status = e1000_write_ich8_data(hw, index, 1, word); @@ -8822,10 +8821,10 @@ e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data) * index - The starting byte index of the word to read. * data - Pointer to a word to store the value read. *****************************************************************************/ -static int32_t -e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data) +static s32 +e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data) { - int32_t status = E1000_SUCCESS; + s32 status = E1000_SUCCESS; status = e1000_read_ich8_data(hw, index, 2, data); return status; } @@ -8841,19 +8840,19 @@ e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data) * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the * bank size may be 4, 8 or 64 KBytes *****************************************************************************/ -static int32_t -e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank) +static s32 +e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank) { union ich8_hws_flash_status hsfsts; union ich8_hws_flash_ctrl hsflctl; - uint32_t flash_linear_address; - int32_t count = 0; - int32_t error = E1000_ERR_EEPROM; - int32_t iteration; - int32_t sub_sector_size = 0; - int32_t bank_size; - int32_t j = 0; - int32_t error_flag = 0; + u32 flash_linear_address; + s32 count = 0; + s32 error = E1000_ERR_EEPROM; + s32 iteration; + s32 sub_sector_size = 0; + s32 bank_size; + s32 j = 0; + s32 error_flag = 0; hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); @@ -8931,16 +8930,16 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank) return error; } -static int32_t +static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, - uint32_t cnf_base_addr, uint32_t cnf_size) + u32 cnf_base_addr, u32 cnf_size) { - uint32_t ret_val = E1000_SUCCESS; - uint16_t word_addr, reg_data, reg_addr; - uint16_t i; + u32 ret_val = E1000_SUCCESS; + u16 word_addr, reg_data, reg_addr; + u16 i; /* cnf_base_addr is in DWORD */ - word_addr = (uint16_t)(cnf_base_addr << 1); + word_addr = (u16)(cnf_base_addr << 1); /* cnf_size is returned in size of dwords */ for (i = 0; i < cnf_size; i++) { @@ -8956,7 +8955,7 @@ e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, if (ret_val != E1000_SUCCESS) return ret_val; - ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data); + ret_val = e1000_write_phy_reg_ex(hw, (u32)reg_addr, reg_data); e1000_release_software_flag(hw); } @@ -8973,10 +8972,10 @@ e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, * * hw: Struct containing variables accessed by shared code *****************************************************************************/ -static int32_t +static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw) { - uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop; + u32 reg_data, cnf_base_addr, cnf_size, ret_val, loop; if (hw->phy_type != e1000_phy_igp_3) return E1000_SUCCESS; |