diff options
Diffstat (limited to 'drivers/media/platform/omap3isp')
| -rw-r--r-- | drivers/media/platform/omap3isp/isp.c | 340 | ||||
| -rw-r--r-- | drivers/media/platform/omap3isp/ispccdc.c | 1 | ||||
| -rw-r--r-- | drivers/media/platform/omap3isp/ispccp2.c | 1 | ||||
| -rw-r--r-- | drivers/media/platform/omap3isp/ispcsi2.c | 1 | ||||
| -rw-r--r-- | drivers/media/platform/omap3isp/isppreview.c | 1 | ||||
| -rw-r--r-- | drivers/media/platform/omap3isp/ispreg.h | 584 | ||||
| -rw-r--r-- | drivers/media/platform/omap3isp/ispresizer.c | 1 | ||||
| -rw-r--r-- | drivers/media/platform/omap3isp/ispstat.c | 2 | ||||
| -rw-r--r-- | drivers/media/platform/omap3isp/ispvideo.c | 15 |
9 files changed, 513 insertions, 433 deletions
diff --git a/drivers/media/platform/omap3isp/isp.c b/drivers/media/platform/omap3isp/isp.c index 83216fc7156b..327c5716922a 100644 --- a/drivers/media/platform/omap3isp/isp.c +++ b/drivers/media/platform/omap3isp/isp.c @@ -719,6 +719,10 @@ static int isp_pipeline_enable(struct isp_pipeline *pipe, s_stream, mode); pipe->do_propagation = true; } + + /* Stop at the first external sub-device. */ + if (subdev->dev != isp->dev) + break; } return 0; @@ -833,6 +837,10 @@ static int isp_pipeline_disable(struct isp_pipeline *pipe) &subdev->entity); failure = -ETIMEDOUT; } + + /* Stop at the first external sub-device. */ + if (subdev->dev != isp->dev) + break; } return failure; @@ -2014,136 +2022,6 @@ enum isp_of_phy { ISP_OF_PHY_CSIPHY2, }; -static int isp_fwnode_parse(struct device *dev, - struct v4l2_fwnode_endpoint *vep, - struct v4l2_async_subdev *asd) -{ - struct isp_async_subdev *isd = - container_of(asd, struct isp_async_subdev, asd); - struct isp_bus_cfg *buscfg = &isd->bus; - bool csi1 = false; - unsigned int i; - - dev_dbg(dev, "parsing endpoint %pOF, interface %u\n", - to_of_node(vep->base.local_fwnode), vep->base.port); - - switch (vep->base.port) { - case ISP_OF_PHY_PARALLEL: - buscfg->interface = ISP_INTERFACE_PARALLEL; - buscfg->bus.parallel.data_lane_shift = - vep->bus.parallel.data_shift; - buscfg->bus.parallel.clk_pol = - !!(vep->bus.parallel.flags - & V4L2_MBUS_PCLK_SAMPLE_FALLING); - buscfg->bus.parallel.hs_pol = - !!(vep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW); - buscfg->bus.parallel.vs_pol = - !!(vep->bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW); - buscfg->bus.parallel.fld_pol = - !!(vep->bus.parallel.flags & V4L2_MBUS_FIELD_EVEN_LOW); - buscfg->bus.parallel.data_pol = - !!(vep->bus.parallel.flags & V4L2_MBUS_DATA_ACTIVE_LOW); - buscfg->bus.parallel.bt656 = vep->bus_type == V4L2_MBUS_BT656; - break; - - case ISP_OF_PHY_CSIPHY1: - case ISP_OF_PHY_CSIPHY2: - switch (vep->bus_type) { - case V4L2_MBUS_CCP2: - case V4L2_MBUS_CSI1: - dev_dbg(dev, "CSI-1/CCP-2 configuration\n"); - csi1 = true; - break; - case V4L2_MBUS_CSI2_DPHY: - dev_dbg(dev, "CSI-2 configuration\n"); - csi1 = false; - break; - default: - dev_err(dev, "unsupported bus type %u\n", - vep->bus_type); - return -EINVAL; - } - - switch (vep->base.port) { - case ISP_OF_PHY_CSIPHY1: - if (csi1) - buscfg->interface = ISP_INTERFACE_CCP2B_PHY1; - else - buscfg->interface = ISP_INTERFACE_CSI2C_PHY1; - break; - case ISP_OF_PHY_CSIPHY2: - if (csi1) - buscfg->interface = ISP_INTERFACE_CCP2B_PHY2; - else - buscfg->interface = ISP_INTERFACE_CSI2A_PHY2; - break; - } - if (csi1) { - buscfg->bus.ccp2.lanecfg.clk.pos = - vep->bus.mipi_csi1.clock_lane; - buscfg->bus.ccp2.lanecfg.clk.pol = - vep->bus.mipi_csi1.lane_polarity[0]; - dev_dbg(dev, "clock lane polarity %u, pos %u\n", - buscfg->bus.ccp2.lanecfg.clk.pol, - buscfg->bus.ccp2.lanecfg.clk.pos); - - buscfg->bus.ccp2.lanecfg.data[0].pos = - vep->bus.mipi_csi1.data_lane; - buscfg->bus.ccp2.lanecfg.data[0].pol = - vep->bus.mipi_csi1.lane_polarity[1]; - - dev_dbg(dev, "data lane polarity %u, pos %u\n", - buscfg->bus.ccp2.lanecfg.data[0].pol, - buscfg->bus.ccp2.lanecfg.data[0].pos); - - buscfg->bus.ccp2.strobe_clk_pol = - vep->bus.mipi_csi1.clock_inv; - buscfg->bus.ccp2.phy_layer = vep->bus.mipi_csi1.strobe; - buscfg->bus.ccp2.ccp2_mode = - vep->bus_type == V4L2_MBUS_CCP2; - buscfg->bus.ccp2.vp_clk_pol = 1; - - buscfg->bus.ccp2.crc = 1; - } else { - buscfg->bus.csi2.lanecfg.clk.pos = - vep->bus.mipi_csi2.clock_lane; - buscfg->bus.csi2.lanecfg.clk.pol = - vep->bus.mipi_csi2.lane_polarities[0]; - dev_dbg(dev, "clock lane polarity %u, pos %u\n", - buscfg->bus.csi2.lanecfg.clk.pol, - buscfg->bus.csi2.lanecfg.clk.pos); - - buscfg->bus.csi2.num_data_lanes = - vep->bus.mipi_csi2.num_data_lanes; - - for (i = 0; i < buscfg->bus.csi2.num_data_lanes; i++) { - buscfg->bus.csi2.lanecfg.data[i].pos = - vep->bus.mipi_csi2.data_lanes[i]; - buscfg->bus.csi2.lanecfg.data[i].pol = - vep->bus.mipi_csi2.lane_polarities[i + 1]; - dev_dbg(dev, - "data lane %u polarity %u, pos %u\n", i, - buscfg->bus.csi2.lanecfg.data[i].pol, - buscfg->bus.csi2.lanecfg.data[i].pos); - } - /* - * FIXME: now we assume the CRC is always there. - * Implement a way to obtain this information from the - * sensor. Frame descriptors, perhaps? - */ - buscfg->bus.csi2.crc = 1; - } - break; - - default: - dev_warn(dev, "%pOF: invalid interface %u\n", - to_of_node(vep->base.local_fwnode), vep->base.port); - return -EINVAL; - } - - return 0; -} - static int isp_subdev_notifier_complete(struct v4l2_async_notifier *async) { struct isp_device *isp = container_of(async, struct isp_device, @@ -2173,6 +2051,201 @@ static int isp_subdev_notifier_complete(struct v4l2_async_notifier *async) return media_device_register(&isp->media_dev); } +static void isp_parse_of_parallel_endpoint(struct device *dev, + struct v4l2_fwnode_endpoint *vep, + struct isp_bus_cfg *buscfg) +{ + buscfg->interface = ISP_INTERFACE_PARALLEL; + buscfg->bus.parallel.data_lane_shift = vep->bus.parallel.data_shift; + buscfg->bus.parallel.clk_pol = + !!(vep->bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING); + buscfg->bus.parallel.hs_pol = + !!(vep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW); + buscfg->bus.parallel.vs_pol = + !!(vep->bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW); + buscfg->bus.parallel.fld_pol = + !!(vep->bus.parallel.flags & V4L2_MBUS_FIELD_EVEN_LOW); + buscfg->bus.parallel.data_pol = + !!(vep->bus.parallel.flags & V4L2_MBUS_DATA_ACTIVE_LOW); + buscfg->bus.parallel.bt656 = vep->bus_type == V4L2_MBUS_BT656; +} + +static void isp_parse_of_csi2_endpoint(struct device *dev, + struct v4l2_fwnode_endpoint *vep, + struct isp_bus_cfg *buscfg) +{ + unsigned int i; + + buscfg->bus.csi2.lanecfg.clk.pos = vep->bus.mipi_csi2.clock_lane; + buscfg->bus.csi2.lanecfg.clk.pol = + vep->bus.mipi_csi2.lane_polarities[0]; + dev_dbg(dev, "clock lane polarity %u, pos %u\n", + buscfg->bus.csi2.lanecfg.clk.pol, + buscfg->bus.csi2.lanecfg.clk.pos); + + buscfg->bus.csi2.num_data_lanes = vep->bus.mipi_csi2.num_data_lanes; + + for (i = 0; i < buscfg->bus.csi2.num_data_lanes; i++) { + buscfg->bus.csi2.lanecfg.data[i].pos = + vep->bus.mipi_csi2.data_lanes[i]; + buscfg->bus.csi2.lanecfg.data[i].pol = + vep->bus.mipi_csi2.lane_polarities[i + 1]; + dev_dbg(dev, + "data lane %u polarity %u, pos %u\n", i, + buscfg->bus.csi2.lanecfg.data[i].pol, + buscfg->bus.csi2.lanecfg.data[i].pos); + } + /* + * FIXME: now we assume the CRC is always there. Implement a way to + * obtain this information from the sensor. Frame descriptors, perhaps? + */ + buscfg->bus.csi2.crc = 1; +} + +static void isp_parse_of_csi1_endpoint(struct device *dev, + struct v4l2_fwnode_endpoint *vep, + struct isp_bus_cfg *buscfg) +{ + buscfg->bus.ccp2.lanecfg.clk.pos = vep->bus.mipi_csi1.clock_lane; + buscfg->bus.ccp2.lanecfg.clk.pol = vep->bus.mipi_csi1.lane_polarity[0]; + dev_dbg(dev, "clock lane polarity %u, pos %u\n", + buscfg->bus.ccp2.lanecfg.clk.pol, + buscfg->bus.ccp2.lanecfg.clk.pos); + + buscfg->bus.ccp2.lanecfg.data[0].pos = vep->bus.mipi_csi1.data_lane; + buscfg->bus.ccp2.lanecfg.data[0].pol = + vep->bus.mipi_csi1.lane_polarity[1]; + + dev_dbg(dev, "data lane polarity %u, pos %u\n", + buscfg->bus.ccp2.lanecfg.data[0].pol, + buscfg->bus.ccp2.lanecfg.data[0].pos); + + buscfg->bus.ccp2.strobe_clk_pol = vep->bus.mipi_csi1.clock_inv; + buscfg->bus.ccp2.phy_layer = vep->bus.mipi_csi1.strobe; + buscfg->bus.ccp2.ccp2_mode = vep->bus_type == V4L2_MBUS_CCP2; + buscfg->bus.ccp2.vp_clk_pol = 1; + + buscfg->bus.ccp2.crc = 1; +} + +static int isp_alloc_isd(struct isp_async_subdev **isd, + struct isp_bus_cfg **buscfg) +{ + struct isp_async_subdev *__isd; + + __isd = kzalloc(sizeof(*__isd), GFP_KERNEL); + if (!__isd) + return -ENOMEM; + + *isd = __isd; + *buscfg = &__isd->bus; + + return 0; +} + +static struct { + u32 phy; + u32 csi2_if; + u32 csi1_if; +} isp_bus_interfaces[2] = { + { ISP_OF_PHY_CSIPHY1, + ISP_INTERFACE_CSI2C_PHY1, ISP_INTERFACE_CCP2B_PHY1 }, + { ISP_OF_PHY_CSIPHY2, + ISP_INTERFACE_CSI2A_PHY2, ISP_INTERFACE_CCP2B_PHY2 }, +}; + +static int isp_parse_of_endpoints(struct isp_device *isp) +{ + struct fwnode_handle *ep; + struct isp_async_subdev *isd = NULL; + struct isp_bus_cfg *buscfg; + unsigned int i; + + ep = fwnode_graph_get_endpoint_by_id( + dev_fwnode(isp->dev), ISP_OF_PHY_PARALLEL, 0, + FWNODE_GRAPH_ENDPOINT_NEXT); + + if (ep) { + struct v4l2_fwnode_endpoint vep = { + .bus_type = V4L2_MBUS_PARALLEL + }; + int ret; + + dev_dbg(isp->dev, "parsing parallel interface\n"); + + ret = v4l2_fwnode_endpoint_parse(ep, &vep); + + if (!ret) { + ret = isp_alloc_isd(&isd, &buscfg); + if (ret) + return ret; + } + + if (!ret) { + isp_parse_of_parallel_endpoint(isp->dev, &vep, buscfg); + ret = v4l2_async_notifier_add_fwnode_remote_subdev( + &isp->notifier, ep, &isd->asd); + } + + fwnode_handle_put(ep); + if (ret) + kfree(isd); + } + + for (i = 0; i < ARRAY_SIZE(isp_bus_interfaces); i++) { + struct v4l2_fwnode_endpoint vep = { + .bus_type = V4L2_MBUS_CSI2_DPHY + }; + int ret; + + ep = fwnode_graph_get_endpoint_by_id( + dev_fwnode(isp->dev), isp_bus_interfaces[i].phy, 0, + FWNODE_GRAPH_ENDPOINT_NEXT); + + if (!ep) + continue; + + dev_dbg(isp->dev, "parsing serial interface %u, node %pOF\n", i, + to_of_node(ep)); + + ret = isp_alloc_isd(&isd, &buscfg); + if (ret) + return ret; + + ret = v4l2_fwnode_endpoint_parse(ep, &vep); + if (!ret) { + buscfg->interface = isp_bus_interfaces[i].csi2_if; + isp_parse_of_csi2_endpoint(isp->dev, &vep, buscfg); + } else if (ret == -ENXIO) { + vep = (struct v4l2_fwnode_endpoint) + { .bus_type = V4L2_MBUS_CSI1 }; + ret = v4l2_fwnode_endpoint_parse(ep, &vep); + + if (ret == -ENXIO) { + vep = (struct v4l2_fwnode_endpoint) + { .bus_type = V4L2_MBUS_CCP2 }; + ret = v4l2_fwnode_endpoint_parse(ep, &vep); + } + if (!ret) { + buscfg->interface = + isp_bus_interfaces[i].csi1_if; + isp_parse_of_csi1_endpoint(isp->dev, &vep, + buscfg); + } + } + + if (!ret) + ret = v4l2_async_notifier_add_fwnode_remote_subdev( + &isp->notifier, ep, &isd->asd); + + fwnode_handle_put(ep); + if (ret) + kfree(isd); + } + + return 0; +} + static const struct v4l2_async_notifier_operations isp_subdev_notifier_ops = { .complete = isp_subdev_notifier_complete, }; @@ -2223,14 +2296,12 @@ static int isp_probe(struct platform_device *pdev) mutex_init(&isp->isp_mutex); spin_lock_init(&isp->stat_lock); v4l2_async_notifier_init(&isp->notifier); + isp->dev = &pdev->dev; - ret = v4l2_async_notifier_parse_fwnode_endpoints( - &pdev->dev, &isp->notifier, sizeof(struct isp_async_subdev), - isp_fwnode_parse); + ret = isp_parse_of_endpoints(isp); if (ret < 0) goto error; - isp->dev = &pdev->dev; isp->ref_count = 0; ret = dma_coerce_mask_and_coherent(isp->dev, DMA_BIT_MASK(32)); @@ -2324,7 +2395,6 @@ static int isp_probe(struct platform_device *pdev) /* Interrupt */ ret = platform_get_irq(pdev, 0); if (ret <= 0) { - dev_err(isp->dev, "No IRQ resource\n"); ret = -ENODEV; goto error_iommu; } diff --git a/drivers/media/platform/omap3isp/ispccdc.c b/drivers/media/platform/omap3isp/ispccdc.c index 1ba8a5ba343f..e2f336c715a4 100644 --- a/drivers/media/platform/omap3isp/ispccdc.c +++ b/drivers/media/platform/omap3isp/ispccdc.c @@ -2602,6 +2602,7 @@ int omap3isp_ccdc_register_entities(struct isp_ccdc_device *ccdc, int ret; /* Register the subdev and video node. */ + ccdc->subdev.dev = vdev->mdev->dev; ret = v4l2_device_register_subdev(vdev, &ccdc->subdev); if (ret < 0) goto error; diff --git a/drivers/media/platform/omap3isp/ispccp2.c b/drivers/media/platform/omap3isp/ispccp2.c index efca45bb02c8..d0a49cdfd22d 100644 --- a/drivers/media/platform/omap3isp/ispccp2.c +++ b/drivers/media/platform/omap3isp/ispccp2.c @@ -1031,6 +1031,7 @@ int omap3isp_ccp2_register_entities(struct isp_ccp2_device *ccp2, int ret; /* Register the subdev and video nodes. */ + ccp2->subdev.dev = vdev->mdev->dev; ret = v4l2_device_register_subdev(vdev, &ccp2->subdev); if (ret < 0) goto error; diff --git a/drivers/media/platform/omap3isp/ispcsi2.c b/drivers/media/platform/omap3isp/ispcsi2.c index e85917f4a50c..fd493c5e4e24 100644 --- a/drivers/media/platform/omap3isp/ispcsi2.c +++ b/drivers/media/platform/omap3isp/ispcsi2.c @@ -1198,6 +1198,7 @@ int omap3isp_csi2_register_entities(struct isp_csi2_device *csi2, int ret; /* Register the subdev and video nodes. */ + csi2->subdev.dev = vdev->mdev->dev; ret = v4l2_device_register_subdev(vdev, &csi2->subdev); if (ret < 0) goto error; diff --git a/drivers/media/platform/omap3isp/isppreview.c b/drivers/media/platform/omap3isp/isppreview.c index 40e22400cf5e..97d660606d98 100644 --- a/drivers/media/platform/omap3isp/isppreview.c +++ b/drivers/media/platform/omap3isp/isppreview.c @@ -2225,6 +2225,7 @@ int omap3isp_preview_register_entities(struct isp_prev_device *prev, int ret; /* Register the subdev and video nodes. */ + prev->subdev.dev = vdev->mdev->dev; ret = v4l2_device_register_subdev(vdev, &prev->subdev); if (ret < 0) goto error; diff --git a/drivers/media/platform/omap3isp/ispreg.h b/drivers/media/platform/omap3isp/ispreg.h index 38e2b99b3f10..86b6ebb0438d 100644 --- a/drivers/media/platform/omap3isp/ispreg.h +++ b/drivers/media/platform/omap3isp/ispreg.h @@ -45,7 +45,7 @@ #define ISPCCP2_REVISION (0x000) #define ISPCCP2_SYSCONFIG (0x004) -#define ISPCCP2_SYSCONFIG_SOFT_RESET (1 << 1) +#define ISPCCP2_SYSCONFIG_SOFT_RESET BIT(1) #define ISPCCP2_SYSCONFIG_AUTO_IDLE 0x1 #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT 12 #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_FORCE \ @@ -55,44 +55,44 @@ #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART \ (0x2 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT) #define ISPCCP2_SYSSTATUS (0x008) -#define ISPCCP2_SYSSTATUS_RESET_DONE (1 << 0) +#define ISPCCP2_SYSSTATUS_RESET_DONE BIT(0) #define ISPCCP2_LC01_IRQENABLE (0x00C) #define ISPCCP2_LC01_IRQSTATUS (0x010) -#define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ (1 << 11) -#define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ (1 << 10) -#define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ (1 << 9) -#define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ (1 << 8) -#define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ (1 << 7) -#define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ (1 << 5) -#define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ (1 << 4) -#define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ (1 << 3) -#define ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ (1 << 2) -#define ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ (1 << 1) -#define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ (1 << 0) +#define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ BIT(11) +#define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ BIT(10) +#define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ BIT(9) +#define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ BIT(8) +#define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ BIT(7) +#define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ BIT(5) +#define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ BIT(4) +#define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ BIT(3) +#define ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ BIT(2) +#define ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ BIT(1) +#define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ BIT(0) #define ISPCCP2_LC23_IRQENABLE (0x014) #define ISPCCP2_LC23_IRQSTATUS (0x018) #define ISPCCP2_LCM_IRQENABLE (0x02C) -#define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ (1 << 0) -#define ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ (1 << 1) +#define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ BIT(0) +#define ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ BIT(1) #define ISPCCP2_LCM_IRQSTATUS (0x030) #define ISPCCP2_CTRL (0x040) -#define ISPCCP2_CTRL_IF_EN (1 << 0) -#define ISPCCP2_CTRL_PHY_SEL (1 << 1) +#define ISPCCP2_CTRL_IF_EN BIT(0) +#define ISPCCP2_CTRL_PHY_SEL BIT(1) #define ISPCCP2_CTRL_PHY_SEL_CLOCK (0 << 1) #define ISPCCP2_CTRL_PHY_SEL_STROBE (1 << 1) #define ISPCCP2_CTRL_PHY_SEL_MASK 0x1 #define ISPCCP2_CTRL_PHY_SEL_SHIFT 1 -#define ISPCCP2_CTRL_IO_OUT_SEL (1 << 2) +#define ISPCCP2_CTRL_IO_OUT_SEL BIT(2) #define ISPCCP2_CTRL_IO_OUT_SEL_MASK 0x1 #define ISPCCP2_CTRL_IO_OUT_SEL_SHIFT 2 -#define ISPCCP2_CTRL_MODE (1 << 4) -#define ISPCCP2_CTRL_VP_CLK_FORCE_ON (1 << 9) -#define ISPCCP2_CTRL_INV (1 << 10) +#define ISPCCP2_CTRL_MODE BIT(4) +#define ISPCCP2_CTRL_VP_CLK_FORCE_ON BIT(9) +#define ISPCCP2_CTRL_INV BIT(10) #define ISPCCP2_CTRL_INV_MASK 0x1 #define ISPCCP2_CTRL_INV_SHIFT 10 -#define ISPCCP2_CTRL_VP_ONLY_EN (1 << 11) -#define ISPCCP2_CTRL_VP_CLK_POL (1 << 12) +#define ISPCCP2_CTRL_VP_ONLY_EN BIT(11) +#define ISPCCP2_CTRL_VP_CLK_POL BIT(12) #define ISPCCP2_CTRL_VP_CLK_POL_MASK 0x1 #define ISPCCP2_CTRL_VP_CLK_POL_SHIFT 12 #define ISPCCP2_CTRL_VPCLK_DIV_SHIFT 15 @@ -102,12 +102,12 @@ #define ISPCCP2_DBG (0x044) #define ISPCCP2_GNQ (0x048) #define ISPCCP2_LCx_CTRL(x) ((0x050)+0x30*(x)) -#define ISPCCP2_LCx_CTRL_CHAN_EN (1 << 0) -#define ISPCCP2_LCx_CTRL_CRC_EN (1 << 19) +#define ISPCCP2_LCx_CTRL_CHAN_EN BIT(0) +#define ISPCCP2_LCx_CTRL_CRC_EN BIT(19) #define ISPCCP2_LCx_CTRL_CRC_MASK 0x1 #define ISPCCP2_LCx_CTRL_CRC_SHIFT 2 #define ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0 19 -#define ISPCCP2_LCx_CTRL_REGION_EN (1 << 1) +#define ISPCCP2_LCx_CTRL_REGION_EN BIT(1) #define ISPCCP2_LCx_CTRL_REGION_MASK 0x1 #define ISPCCP2_LCx_CTRL_REGION_SHIFT 1 #define ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0 0x3f @@ -127,8 +127,8 @@ #define ISPCCP2_LCx_DAT_PONG_ADDR(x) ((0x074)+0x30*(x)) #define ISPCCP2_LCx_DAT_OFST(x) ((0x078)+0x30*(x)) #define ISPCCP2_LCM_CTRL (0x1D0) -#define ISPCCP2_LCM_CTRL_CHAN_EN (1 << 0) -#define ISPCCP2_LCM_CTRL_DST_PORT (1 << 2) +#define ISPCCP2_LCM_CTRL_CHAN_EN BIT(0) +#define ISPCCP2_LCM_CTRL_DST_PORT BIT(2) #define ISPCCP2_LCM_CTRL_DST_PORT_SHIFT 2 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_SHIFT 3 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_MASK 0x11 @@ -138,8 +138,8 @@ #define ISPCCP2_LCM_CTRL_SRC_FORMAT_MASK 0x7 #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT 20 #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_MASK 0x3 -#define ISPCCP2_LCM_CTRL_SRC_DPCM_PRED (1 << 22) -#define ISPCCP2_LCM_CTRL_SRC_PACK (1 << 23) +#define ISPCCP2_LCM_CTRL_SRC_DPCM_PRED BIT(22) +#define ISPCCP2_LCM_CTRL_SRC_PACK BIT(23) #define ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT 24 #define ISPCCP2_LCM_CTRL_DST_FORMAT_MASK 0x7 #define ISPCCP2_LCM_VSIZE (0x1D4) @@ -201,19 +201,19 @@ /* SBL */ #define ISPSBL_PCR 0x4 -#define ISPSBL_PCR_H3A_AEAWB_WBL_OVF (1 << 16) -#define ISPSBL_PCR_H3A_AF_WBL_OVF (1 << 17) -#define ISPSBL_PCR_RSZ4_WBL_OVF (1 << 18) -#define ISPSBL_PCR_RSZ3_WBL_OVF (1 << 19) -#define ISPSBL_PCR_RSZ2_WBL_OVF (1 << 20) -#define ISPSBL_PCR_RSZ1_WBL_OVF (1 << 21) -#define ISPSBL_PCR_PRV_WBL_OVF (1 << 22) -#define ISPSBL_PCR_CCDC_WBL_OVF (1 << 23) -#define ISPSBL_PCR_CCDCPRV_2_RSZ_OVF (1 << 24) -#define ISPSBL_PCR_CSIA_WBL_OVF (1 << 25) -#define ISPSBL_PCR_CSIB_WBL_OVF (1 << 26) +#define ISPSBL_PCR_H3A_AEAWB_WBL_OVF BIT(16) +#define ISPSBL_PCR_H3A_AF_WBL_OVF BIT(17) +#define ISPSBL_PCR_RSZ4_WBL_OVF BIT(18) +#define ISPSBL_PCR_RSZ3_WBL_OVF BIT(19) +#define ISPSBL_PCR_RSZ2_WBL_OVF BIT(20) +#define ISPSBL_PCR_RSZ1_WBL_OVF BIT(21) +#define ISPSBL_PCR_PRV_WBL_OVF BIT(22) +#define ISPSBL_PCR_CCDC_WBL_OVF BIT(23) +#define ISPSBL_PCR_CCDCPRV_2_RSZ_OVF BIT(24) +#define ISPSBL_PCR_CSIA_WBL_OVF BIT(25) +#define ISPSBL_PCR_CSIB_WBL_OVF BIT(26) #define ISPSBL_CCDC_WR_0 (0x028) -#define ISPSBL_CCDC_WR_0_DATA_READY (1 << 21) +#define ISPSBL_CCDC_WR_0_DATA_READY BIT(21) #define ISPSBL_CCDC_WR_1 (0x02C) #define ISPSBL_CCDC_WR_2 (0x030) #define ISPSBL_CCDC_WR_3 (0x034) @@ -366,16 +366,16 @@ #define ISP_INT_CLR 0xFF113F11 #define ISPPRV_PCR_EN 1 -#define ISPPRV_PCR_BUSY (1 << 1) -#define ISPPRV_PCR_SOURCE (1 << 2) -#define ISPPRV_PCR_ONESHOT (1 << 3) -#define ISPPRV_PCR_WIDTH (1 << 4) -#define ISPPRV_PCR_INVALAW (1 << 5) -#define ISPPRV_PCR_DRKFEN (1 << 6) -#define ISPPRV_PCR_DRKFCAP (1 << 7) -#define ISPPRV_PCR_HMEDEN (1 << 8) -#define ISPPRV_PCR_NFEN (1 << 9) -#define ISPPRV_PCR_CFAEN (1 << 10) +#define ISPPRV_PCR_BUSY BIT(1) +#define ISPPRV_PCR_SOURCE BIT(2) +#define ISPPRV_PCR_ONESHOT BIT(3) +#define ISPPRV_PCR_WIDTH BIT(4) +#define ISPPRV_PCR_INVALAW BIT(5) +#define ISPPRV_PCR_DRKFEN BIT(6) +#define ISPPRV_PCR_DRKFCAP BIT(7) +#define ISPPRV_PCR_HMEDEN BIT(8) +#define ISPPRV_PCR_NFEN BIT(9) +#define ISPPRV_PCR_CFAEN BIT(10) #define ISPPRV_PCR_CFAFMT_SHIFT 11 #define ISPPRV_PCR_CFAFMT_MASK 0x7800 #define ISPPRV_PCR_CFAFMT_BAYER (0 << 11) @@ -384,22 +384,22 @@ #define ISPPRV_PCR_CFAFMT_DNSPL (3 << 11) #define ISPPRV_PCR_CFAFMT_HONEYCOMB (4 << 11) #define ISPPRV_PCR_CFAFMT_RRGGBBFOVEON (5 << 11) -#define ISPPRV_PCR_YNENHEN (1 << 15) -#define ISPPRV_PCR_SUPEN (1 << 16) +#define ISPPRV_PCR_YNENHEN BIT(15) +#define ISPPRV_PCR_SUPEN BIT(16) #define ISPPRV_PCR_YCPOS_SHIFT 17 #define ISPPRV_PCR_YCPOS_YCrYCb (0 << 17) #define ISPPRV_PCR_YCPOS_YCbYCr (1 << 17) #define ISPPRV_PCR_YCPOS_CbYCrY (2 << 17) #define ISPPRV_PCR_YCPOS_CrYCbY (3 << 17) -#define ISPPRV_PCR_RSZPORT (1 << 19) -#define ISPPRV_PCR_SDRPORT (1 << 20) -#define ISPPRV_PCR_SCOMP_EN (1 << 21) +#define ISPPRV_PCR_RSZPORT BIT(19) +#define ISPPRV_PCR_SDRPORT BIT(20) +#define ISPPRV_PCR_SCOMP_EN BIT(21) #define ISPPRV_PCR_SCOMP_SFT_SHIFT (22) #define ISPPRV_PCR_SCOMP_SFT_MASK (7 << 22) -#define ISPPRV_PCR_GAMMA_BYPASS (1 << 26) -#define ISPPRV_PCR_DCOREN (1 << 27) -#define ISPPRV_PCR_DCCOUP (1 << 28) -#define ISPPRV_PCR_DRK_FAIL (1 << 31) +#define ISPPRV_PCR_GAMMA_BYPASS BIT(26) +#define ISPPRV_PCR_DCOREN BIT(27) +#define ISPPRV_PCR_DCCOUP BIT(28) +#define ISPPRV_PCR_DRK_FAIL BIT(31) #define ISPPRV_HORZ_INFO_EPH_SHIFT 0 #define ISPPRV_HORZ_INFO_EPH_MASK 0x3fff @@ -423,8 +423,8 @@ #define ISPPRV_AVE_ODDDIST_4 0x3 #define ISPPRV_HMED_THRESHOLD_SHIFT 0 -#define ISPPRV_HMED_EVENDIST (1 << 8) -#define ISPPRV_HMED_ODDDIST (1 << 9) +#define ISPPRV_HMED_EVENDIST BIT(8) +#define ISPPRV_HMED_ODDDIST BIT(9) #define ISPPRV_WBGAIN_COEF0_SHIFT 0 #define ISPPRV_WBGAIN_COEF1_SHIFT 8 @@ -517,8 +517,8 @@ /* Define bit fields within selected registers */ #define ISP_REVISION_SHIFT 0 -#define ISP_SYSCONFIG_AUTOIDLE (1 << 0) -#define ISP_SYSCONFIG_SOFTRESET (1 << 1) +#define ISP_SYSCONFIG_AUTOIDLE BIT(0) +#define ISP_SYSCONFIG_SOFTRESET BIT(1) #define ISP_SYSCONFIG_MIDLEMODE_SHIFT 12 #define ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY 0x0 #define ISP_SYSCONFIG_MIDLEMODE_NOSTANBY 0x1 @@ -526,68 +526,68 @@ #define ISP_SYSSTATUS_RESETDONE 0 -#define IRQ0ENABLE_CSIA_IRQ (1 << 0) -#define IRQ0ENABLE_CSIC_IRQ (1 << 1) -#define IRQ0ENABLE_CCP2_LCM_IRQ (1 << 3) -#define IRQ0ENABLE_CCP2_LC0_IRQ (1 << 4) -#define IRQ0ENABLE_CCP2_LC1_IRQ (1 << 5) -#define IRQ0ENABLE_CCP2_LC2_IRQ (1 << 6) -#define IRQ0ENABLE_CCP2_LC3_IRQ (1 << 7) +#define IRQ0ENABLE_CSIA_IRQ BIT(0) +#define IRQ0ENABLE_CSIC_IRQ BIT(1) +#define IRQ0ENABLE_CCP2_LCM_IRQ BIT(3) +#define IRQ0ENABLE_CCP2_LC0_IRQ BIT(4) +#define IRQ0ENABLE_CCP2_LC1_IRQ BIT(5) +#define IRQ0ENABLE_CCP2_LC2_IRQ BIT(6) +#define IRQ0ENABLE_CCP2_LC3_IRQ BIT(7) #define IRQ0ENABLE_CSIB_IRQ (IRQ0ENABLE_CCP2_LCM_IRQ | \ IRQ0ENABLE_CCP2_LC0_IRQ | \ IRQ0ENABLE_CCP2_LC1_IRQ | \ IRQ0ENABLE_CCP2_LC2_IRQ | \ IRQ0ENABLE_CCP2_LC3_IRQ) -#define IRQ0ENABLE_CCDC_VD0_IRQ (1 << 8) -#define IRQ0ENABLE_CCDC_VD1_IRQ (1 << 9) -#define IRQ0ENABLE_CCDC_VD2_IRQ (1 << 10) -#define IRQ0ENABLE_CCDC_ERR_IRQ (1 << 11) -#define IRQ0ENABLE_H3A_AF_DONE_IRQ (1 << 12) -#define IRQ0ENABLE_H3A_AWB_DONE_IRQ (1 << 13) -#define IRQ0ENABLE_HIST_DONE_IRQ (1 << 16) -#define IRQ0ENABLE_CCDC_LSC_DONE_IRQ (1 << 17) -#define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ (1 << 18) -#define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ (1 << 19) -#define IRQ0ENABLE_PRV_DONE_IRQ (1 << 20) -#define IRQ0ENABLE_RSZ_DONE_IRQ (1 << 24) -#define IRQ0ENABLE_OVF_IRQ (1 << 25) -#define IRQ0ENABLE_PING_IRQ (1 << 26) -#define IRQ0ENABLE_PONG_IRQ (1 << 27) -#define IRQ0ENABLE_MMU_ERR_IRQ (1 << 28) -#define IRQ0ENABLE_OCP_ERR_IRQ (1 << 29) -#define IRQ0ENABLE_SEC_ERR_IRQ (1 << 30) -#define IRQ0ENABLE_HS_VS_IRQ (1 << 31) - -#define IRQ0STATUS_CSIA_IRQ (1 << 0) -#define IRQ0STATUS_CSI2C_IRQ (1 << 1) -#define IRQ0STATUS_CCP2_LCM_IRQ (1 << 3) -#define IRQ0STATUS_CCP2_LC0_IRQ (1 << 4) +#define IRQ0ENABLE_CCDC_VD0_IRQ BIT(8) +#define IRQ0ENABLE_CCDC_VD1_IRQ BIT(9) +#define IRQ0ENABLE_CCDC_VD2_IRQ BIT(10) +#define IRQ0ENABLE_CCDC_ERR_IRQ BIT(11) +#define IRQ0ENABLE_H3A_AF_DONE_IRQ BIT(12) +#define IRQ0ENABLE_H3A_AWB_DONE_IRQ BIT(13) +#define IRQ0ENABLE_HIST_DONE_IRQ BIT(16) +#define IRQ0ENABLE_CCDC_LSC_DONE_IRQ BIT(17) +#define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ BIT(18) +#define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ BIT(19) +#define IRQ0ENABLE_PRV_DONE_IRQ BIT(20) +#define IRQ0ENABLE_RSZ_DONE_IRQ BIT(24) +#define IRQ0ENABLE_OVF_IRQ BIT(25) +#define IRQ0ENABLE_PING_IRQ BIT(26) +#define IRQ0ENABLE_PONG_IRQ BIT(27) +#define IRQ0ENABLE_MMU_ERR_IRQ BIT(28) +#define IRQ0ENABLE_OCP_ERR_IRQ BIT(29) +#define IRQ0ENABLE_SEC_ERR_IRQ BIT(30) +#define IRQ0ENABLE_HS_VS_IRQ BIT(31) + +#define IRQ0STATUS_CSIA_IRQ BIT(0) +#define IRQ0STATUS_CSI2C_IRQ BIT(1) +#define IRQ0STATUS_CCP2_LCM_IRQ BIT(3) +#define IRQ0STATUS_CCP2_LC0_IRQ BIT(4) #define IRQ0STATUS_CSIB_IRQ (IRQ0STATUS_CCP2_LCM_IRQ | \ IRQ0STATUS_CCP2_LC0_IRQ) -#define IRQ0STATUS_CSIB_LC1_IRQ (1 << 5) -#define IRQ0STATUS_CSIB_LC2_IRQ (1 << 6) -#define IRQ0STATUS_CSIB_LC3_IRQ (1 << 7) -#define IRQ0STATUS_CCDC_VD0_IRQ (1 << 8) -#define IRQ0STATUS_CCDC_VD1_IRQ (1 << 9) -#define IRQ0STATUS_CCDC_VD2_IRQ (1 << 10) -#define IRQ0STATUS_CCDC_ERR_IRQ (1 << 11) -#define IRQ0STATUS_H3A_AF_DONE_IRQ (1 << 12) -#define IRQ0STATUS_H3A_AWB_DONE_IRQ (1 << 13) -#define IRQ0STATUS_HIST_DONE_IRQ (1 << 16) -#define IRQ0STATUS_CCDC_LSC_DONE_IRQ (1 << 17) -#define IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ (1 << 18) -#define IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ (1 << 19) -#define IRQ0STATUS_PRV_DONE_IRQ (1 << 20) -#define IRQ0STATUS_RSZ_DONE_IRQ (1 << 24) -#define IRQ0STATUS_OVF_IRQ (1 << 25) -#define IRQ0STATUS_PING_IRQ (1 << 26) -#define IRQ0STATUS_PONG_IRQ (1 << 27) -#define IRQ0STATUS_MMU_ERR_IRQ (1 << 28) -#define IRQ0STATUS_OCP_ERR_IRQ (1 << 29) -#define IRQ0STATUS_SEC_ERR_IRQ (1 << 30) -#define IRQ0STATUS_HS_VS_IRQ (1 << 31) +#define IRQ0STATUS_CSIB_LC1_IRQ BIT(5) +#define IRQ0STATUS_CSIB_LC2_IRQ BIT(6) +#define IRQ0STATUS_CSIB_LC3_IRQ BIT(7) +#define IRQ0STATUS_CCDC_VD0_IRQ BIT(8) +#define IRQ0STATUS_CCDC_VD1_IRQ BIT(9) +#define IRQ0STATUS_CCDC_VD2_IRQ BIT(10) +#define IRQ0STATUS_CCDC_ERR_IRQ BIT(11) +#define IRQ0STATUS_H3A_AF_DONE_IRQ BIT(12) +#define IRQ0STATUS_H3A_AWB_DONE_IRQ BIT(13) +#define IRQ0STATUS_HIST_DONE_IRQ BIT(16) +#define IRQ0STATUS_CCDC_LSC_DONE_IRQ BIT(17) +#define IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ BIT(18) +#define IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ BIT(19) +#define IRQ0STATUS_PRV_DONE_IRQ BIT(20) +#define IRQ0STATUS_RSZ_DONE_IRQ BIT(24) +#define IRQ0STATUS_OVF_IRQ BIT(25) +#define IRQ0STATUS_PING_IRQ BIT(26) +#define IRQ0STATUS_PONG_IRQ BIT(27) +#define IRQ0STATUS_MMU_ERR_IRQ BIT(28) +#define IRQ0STATUS_OCP_ERR_IRQ BIT(29) +#define IRQ0STATUS_SEC_ERR_IRQ BIT(30) +#define IRQ0STATUS_HS_VS_IRQ BIT(31) #define TCTRL_GRESET_LEN 0 @@ -607,20 +607,20 @@ #define ISPCTRL_PAR_BRIDGE_MASK (0x3 << 2) #define ISPCTRL_PAR_CLK_POL_SHIFT 4 -#define ISPCTRL_PAR_CLK_POL_INV (1 << 4) -#define ISPCTRL_PING_PONG_EN (1 << 5) +#define ISPCTRL_PAR_CLK_POL_INV BIT(4) +#define ISPCTRL_PING_PONG_EN BIT(5) #define ISPCTRL_SHIFT_SHIFT 6 #define ISPCTRL_SHIFT_0 (0x0 << 6) #define ISPCTRL_SHIFT_2 (0x1 << 6) #define ISPCTRL_SHIFT_4 (0x2 << 6) #define ISPCTRL_SHIFT_MASK (0x3 << 6) -#define ISPCTRL_CCDC_CLK_EN (1 << 8) -#define ISPCTRL_SCMP_CLK_EN (1 << 9) -#define ISPCTRL_H3A_CLK_EN (1 << 10) -#define ISPCTRL_HIST_CLK_EN (1 << 11) -#define ISPCTRL_PREV_CLK_EN (1 << 12) -#define ISPCTRL_RSZ_CLK_EN (1 << 13) +#define ISPCTRL_CCDC_CLK_EN BIT(8) +#define ISPCTRL_SCMP_CLK_EN BIT(9) +#define ISPCTRL_H3A_CLK_EN BIT(10) +#define ISPCTRL_HIST_CLK_EN BIT(11) +#define ISPCTRL_PREV_CLK_EN BIT(12) +#define ISPCTRL_RSZ_CLK_EN BIT(13) #define ISPCTRL_SYNC_DETECT_SHIFT 14 #define ISPCTRL_SYNC_DETECT_HSFALL (0x0 << ISPCTRL_SYNC_DETECT_SHIFT) #define ISPCTRL_SYNC_DETECT_HSRISE (0x1 << ISPCTRL_SYNC_DETECT_SHIFT) @@ -628,17 +628,17 @@ #define ISPCTRL_SYNC_DETECT_VSRISE (0x3 << ISPCTRL_SYNC_DETECT_SHIFT) #define ISPCTRL_SYNC_DETECT_MASK (0x3 << ISPCTRL_SYNC_DETECT_SHIFT) -#define ISPCTRL_CCDC_RAM_EN (1 << 16) -#define ISPCTRL_PREV_RAM_EN (1 << 17) -#define ISPCTRL_SBL_RD_RAM_EN (1 << 18) -#define ISPCTRL_SBL_WR1_RAM_EN (1 << 19) -#define ISPCTRL_SBL_WR0_RAM_EN (1 << 20) -#define ISPCTRL_SBL_AUTOIDLE (1 << 21) -#define ISPCTRL_SBL_SHARED_WPORTC (1 << 26) -#define ISPCTRL_SBL_SHARED_RPORTA (1 << 27) -#define ISPCTRL_SBL_SHARED_RPORTB (1 << 28) -#define ISPCTRL_JPEG_FLUSH (1 << 30) -#define ISPCTRL_CCDC_FLUSH (1 << 31) +#define ISPCTRL_CCDC_RAM_EN BIT(16) +#define ISPCTRL_PREV_RAM_EN BIT(17) +#define ISPCTRL_SBL_RD_RAM_EN BIT(18) +#define ISPCTRL_SBL_WR1_RAM_EN BIT(19) +#define ISPCTRL_SBL_WR0_RAM_EN BIT(20) +#define ISPCTRL_SBL_AUTOIDLE BIT(21) +#define ISPCTRL_SBL_SHARED_WPORTC BIT(26) +#define ISPCTRL_SBL_SHARED_RPORTA BIT(27) +#define ISPCTRL_SBL_SHARED_RPORTB BIT(28) +#define ISPCTRL_JPEG_FLUSH BIT(30) +#define ISPCTRL_CCDC_FLUSH BIT(31) #define ISPSECURE_SECUREMODE 0 @@ -655,20 +655,20 @@ #define ISPTCTRL_CTRL_DIVC_SHIFT 10 #define ISPTCTRL_CTRL_DIVC_NOCLOCK (0x0 << 10) -#define ISPTCTRL_CTRL_SHUTEN (1 << 21) -#define ISPTCTRL_CTRL_PSTRBEN (1 << 22) -#define ISPTCTRL_CTRL_STRBEN (1 << 23) -#define ISPTCTRL_CTRL_SHUTPOL (1 << 24) -#define ISPTCTRL_CTRL_STRBPSTRBPOL (1 << 26) +#define ISPTCTRL_CTRL_SHUTEN BIT(21) +#define ISPTCTRL_CTRL_PSTRBEN BIT(22) +#define ISPTCTRL_CTRL_STRBEN BIT(23) +#define ISPTCTRL_CTRL_SHUTPOL BIT(24) +#define ISPTCTRL_CTRL_STRBPSTRBPOL BIT(26) #define ISPTCTRL_CTRL_INSEL_SHIFT 27 #define ISPTCTRL_CTRL_INSEL_PARALLEL (0x0 << 27) #define ISPTCTRL_CTRL_INSEL_CSIA (0x1 << 27) #define ISPTCTRL_CTRL_INSEL_CSIB (0x2 << 27) -#define ISPTCTRL_CTRL_GRESETEn (1 << 29) -#define ISPTCTRL_CTRL_GRESETPOL (1 << 30) -#define ISPTCTRL_CTRL_GRESETDIR (1 << 31) +#define ISPTCTRL_CTRL_GRESETEn BIT(29) +#define ISPTCTRL_CTRL_GRESETPOL BIT(30) +#define ISPTCTRL_CTRL_GRESETDIR BIT(31) #define ISPTCTRL_FRAME_SHUT_SHIFT 0 #define ISPTCTRL_FRAME_PSTRB_SHIFT 6 @@ -679,33 +679,33 @@ #define ISPCCDC_PID_TID_SHIFT 16 #define ISPCCDC_PCR_EN 1 -#define ISPCCDC_PCR_BUSY (1 << 1) +#define ISPCCDC_PCR_BUSY BIT(1) #define ISPCCDC_SYN_MODE_VDHDOUT 0x1 -#define ISPCCDC_SYN_MODE_FLDOUT (1 << 1) -#define ISPCCDC_SYN_MODE_VDPOL (1 << 2) -#define ISPCCDC_SYN_MODE_HDPOL (1 << 3) -#define ISPCCDC_SYN_MODE_FLDPOL (1 << 4) -#define ISPCCDC_SYN_MODE_EXWEN (1 << 5) -#define ISPCCDC_SYN_MODE_DATAPOL (1 << 6) -#define ISPCCDC_SYN_MODE_FLDMODE (1 << 7) +#define ISPCCDC_SYN_MODE_FLDOUT BIT(1) +#define ISPCCDC_SYN_MODE_VDPOL BIT(2) +#define ISPCCDC_SYN_MODE_HDPOL BIT(3) +#define ISPCCDC_SYN_MODE_FLDPOL BIT(4) +#define ISPCCDC_SYN_MODE_EXWEN BIT(5) +#define ISPCCDC_SYN_MODE_DATAPOL BIT(6) +#define ISPCCDC_SYN_MODE_FLDMODE BIT(7) #define ISPCCDC_SYN_MODE_DATSIZ_MASK (0x7 << 8) #define ISPCCDC_SYN_MODE_DATSIZ_8_16 (0x0 << 8) #define ISPCCDC_SYN_MODE_DATSIZ_12 (0x4 << 8) #define ISPCCDC_SYN_MODE_DATSIZ_11 (0x5 << 8) #define ISPCCDC_SYN_MODE_DATSIZ_10 (0x6 << 8) #define ISPCCDC_SYN_MODE_DATSIZ_8 (0x7 << 8) -#define ISPCCDC_SYN_MODE_PACK8 (1 << 11) +#define ISPCCDC_SYN_MODE_PACK8 BIT(11) #define ISPCCDC_SYN_MODE_INPMOD_MASK (3 << 12) #define ISPCCDC_SYN_MODE_INPMOD_RAW (0 << 12) #define ISPCCDC_SYN_MODE_INPMOD_YCBCR16 (1 << 12) #define ISPCCDC_SYN_MODE_INPMOD_YCBCR8 (2 << 12) -#define ISPCCDC_SYN_MODE_LPF (1 << 14) -#define ISPCCDC_SYN_MODE_FLDSTAT (1 << 15) -#define ISPCCDC_SYN_MODE_VDHDEN (1 << 16) -#define ISPCCDC_SYN_MODE_WEN (1 << 17) -#define ISPCCDC_SYN_MODE_VP2SDR (1 << 18) -#define ISPCCDC_SYN_MODE_SDR2RSZ (1 << 19) +#define ISPCCDC_SYN_MODE_LPF BIT(14) +#define ISPCCDC_SYN_MODE_FLDSTAT BIT(15) +#define ISPCCDC_SYN_MODE_VDHDEN BIT(16) +#define ISPCCDC_SYN_MODE_WEN BIT(17) +#define ISPCCDC_SYN_MODE_VP2SDR BIT(18) +#define ISPCCDC_SYN_MODE_SDR2RSZ BIT(19) #define ISPCCDC_HD_VD_WID_VDW_SHIFT 0 #define ISPCCDC_HD_VD_WID_HDW_SHIFT 16 @@ -731,7 +731,7 @@ #define ISPCCDC_HSIZE_OFF_SHIFT 0 -#define ISPCCDC_SDOFST_FIINV (1 << 14) +#define ISPCCDC_SDOFST_FIINV BIT(14) #define ISPCCDC_SDOFST_FOFST_SHIFT 12 #define ISPCCDC_SDOFST_FOFST_MASK (3 << 12) #define ISPCCDC_SDOFST_LOFST3_SHIFT 0 @@ -743,7 +743,7 @@ #define ISPCCDC_CLAMP_OBST_SHIFT 10 #define ISPCCDC_CLAMP_OBSLN_SHIFT 25 #define ISPCCDC_CLAMP_OBSLEN_SHIFT 28 -#define ISPCCDC_CLAMP_CLAMPEN (1 << 31) +#define ISPCCDC_CLAMP_CLAMPEN BIT(31) #define ISPCCDC_COLPTN_R_Ye 0x0 #define ISPCCDC_COLPTN_Gr_Cy 0x1 @@ -772,8 +772,8 @@ #define ISPCCDC_BLKCMP_R_YE_SHIFT 24 #define ISPCCDC_FPC_FPNUM_SHIFT 0 -#define ISPCCDC_FPC_FPCEN (1 << 15) -#define ISPCCDC_FPC_FPERR (1 << 16) +#define ISPCCDC_FPC_FPCEN BIT(15) +#define ISPCCDC_FPC_FPERR BIT(16) #define ISPCCDC_VDINT_1_SHIFT 0 #define ISPCCDC_VDINT_1_MASK 0x00007fff @@ -784,23 +784,23 @@ #define ISPCCDC_ALAW_GWDI_11_2 (0x4 << 0) #define ISPCCDC_ALAW_GWDI_10_1 (0x5 << 0) #define ISPCCDC_ALAW_GWDI_9_0 (0x6 << 0) -#define ISPCCDC_ALAW_CCDTBL (1 << 3) +#define ISPCCDC_ALAW_CCDTBL BIT(3) #define ISPCCDC_REC656IF_R656ON 1 -#define ISPCCDC_REC656IF_ECCFVH (1 << 1) +#define ISPCCDC_REC656IF_ECCFVH BIT(1) -#define ISPCCDC_CFG_BW656 (1 << 5) +#define ISPCCDC_CFG_BW656 BIT(5) #define ISPCCDC_CFG_FIDMD_SHIFT 6 -#define ISPCCDC_CFG_WENLOG (1 << 8) +#define ISPCCDC_CFG_WENLOG BIT(8) #define ISPCCDC_CFG_WENLOG_AND (0 << 8) #define ISPCCDC_CFG_WENLOG_OR (1 << 8) -#define ISPCCDC_CFG_Y8POS (1 << 11) -#define ISPCCDC_CFG_BSWD (1 << 12) -#define ISPCCDC_CFG_MSBINVI (1 << 13) -#define ISPCCDC_CFG_VDLC (1 << 15) +#define ISPCCDC_CFG_Y8POS BIT(11) +#define ISPCCDC_CFG_BSWD BIT(12) +#define ISPCCDC_CFG_MSBINVI BIT(13) +#define ISPCCDC_CFG_VDLC BIT(15) #define ISPCCDC_FMTCFG_FMTEN 0x1 -#define ISPCCDC_FMTCFG_LNALT (1 << 1) +#define ISPCCDC_FMTCFG_LNALT BIT(1) #define ISPCCDC_FMTCFG_LNUM_SHIFT 2 #define ISPCCDC_FMTCFG_PLEN_ODD_SHIFT 4 #define ISPCCDC_FMTCFG_PLEN_EVEN_SHIFT 8 @@ -809,7 +809,7 @@ #define ISPCCDC_FMTCFG_VPIN_11_2 (0x4 << 12) #define ISPCCDC_FMTCFG_VPIN_10_1 (0x5 << 12) #define ISPCCDC_FMTCFG_VPIN_9_0 (0x6 << 12) -#define ISPCCDC_FMTCFG_VPEN (1 << 15) +#define ISPCCDC_FMTCFG_VPEN BIT(15) #define ISPCCDC_FMTCFG_VPIF_FRQ_MASK 0x003f0000 #define ISPCCDC_FMTCFG_VPIF_FRQ_SHIFT 16 @@ -839,9 +839,9 @@ #define ISPRSZ_PID_CID_SHIFT 8 #define ISPRSZ_PID_TID_SHIFT 16 -#define ISPRSZ_PCR_ENABLE (1 << 0) -#define ISPRSZ_PCR_BUSY (1 << 1) -#define ISPRSZ_PCR_ONESHOT (1 << 2) +#define ISPRSZ_PCR_ENABLE BIT(0) +#define ISPRSZ_PCR_BUSY BIT(1) +#define ISPRSZ_PCR_ONESHOT BIT(2) #define ISPRSZ_CNT_HRSZ_SHIFT 0 #define ISPRSZ_CNT_HRSZ_MASK \ @@ -853,10 +853,10 @@ #define ISPRSZ_CNT_HSTPH_MASK (0x7 << ISPRSZ_CNT_HSTPH_SHIFT) #define ISPRSZ_CNT_VSTPH_SHIFT 23 #define ISPRSZ_CNT_VSTPH_MASK (0x7 << ISPRSZ_CNT_VSTPH_SHIFT) -#define ISPRSZ_CNT_YCPOS (1 << 26) -#define ISPRSZ_CNT_INPTYP (1 << 27) -#define ISPRSZ_CNT_INPSRC (1 << 28) -#define ISPRSZ_CNT_CBILIN (1 << 29) +#define ISPRSZ_CNT_YCPOS BIT(26) +#define ISPRSZ_CNT_INPTYP BIT(27) +#define ISPRSZ_CNT_INPSRC BIT(28) +#define ISPRSZ_CNT_CBILIN BIT(29) #define ISPRSZ_OUT_SIZE_HORZ_SHIFT 0 #define ISPRSZ_OUT_SIZE_HORZ_MASK \ @@ -1081,8 +1081,8 @@ #define ISPH3A_PCR_AF_RGBPOS_SHIFT 11 #define ISPH3A_PCR_AEW_AVE2LMT_SHIFT 22 #define ISPH3A_PCR_AEW_AVE2LMT_MASK 0xFFC00000 -#define ISPH3A_PCR_BUSYAF (1 << 15) -#define ISPH3A_PCR_BUSYAEAWB (1 << 18) +#define ISPH3A_PCR_BUSYAF BIT(15) +#define ISPH3A_PCR_BUSYAEAWB BIT(18) #define ISPH3A_AEWWIN1_WINHC_SHIFT 0 #define ISPH3A_AEWWIN1_WINHC_MASK 0x3F @@ -1166,15 +1166,15 @@ #define ISPHIST_HV_INFO_MASK 0x3FFF3FFF -#define ISPCCDC_LSC_ENABLE 1 -#define ISPCCDC_LSC_BUSY (1 << 7) +#define ISPCCDC_LSC_ENABLE BIT(0) +#define ISPCCDC_LSC_BUSY BIT(7) #define ISPCCDC_LSC_GAIN_MODE_N_MASK 0x700 #define ISPCCDC_LSC_GAIN_MODE_N_SHIFT 8 #define ISPCCDC_LSC_GAIN_MODE_M_MASK 0x3800 #define ISPCCDC_LSC_GAIN_MODE_M_SHIFT 12 #define ISPCCDC_LSC_GAIN_FORMAT_MASK 0xE #define ISPCCDC_LSC_GAIN_FORMAT_SHIFT 1 -#define ISPCCDC_LSC_AFTER_REFORMATTER_MASK (1<<6) +#define ISPCCDC_LSC_AFTER_REFORMATTER_MASK BIT(6) #define ISPCCDC_LSC_INITIAL_X_MASK 0x3F #define ISPCCDC_LSC_INITIAL_X_SHIFT 0 @@ -1196,43 +1196,43 @@ (0x1 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT) #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART \ (0x2 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT) -#define ISPCSI2_SYSCONFIG_SOFT_RESET (1 << 1) -#define ISPCSI2_SYSCONFIG_AUTO_IDLE (1 << 0) +#define ISPCSI2_SYSCONFIG_SOFT_RESET BIT(1) +#define ISPCSI2_SYSCONFIG_AUTO_IDLE BIT(0) #define ISPCSI2_SYSSTATUS (0x014) -#define ISPCSI2_SYSSTATUS_RESET_DONE (1 << 0) +#define ISPCSI2_SYSSTATUS_RESET_DONE BIT(0) #define ISPCSI2_IRQSTATUS (0x018) -#define ISPCSI2_IRQSTATUS_OCP_ERR_IRQ (1 << 14) -#define ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ (1 << 13) -#define ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ (1 << 12) -#define ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ (1 << 11) -#define ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ (1 << 10) -#define ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ (1 << 9) -#define ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ (1 << 8) -#define ISPCSI2_IRQSTATUS_CONTEXT(n) (1 << (n)) +#define ISPCSI2_IRQSTATUS_OCP_ERR_IRQ BIT(14) +#define ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ BIT(13) +#define ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ BIT(12) +#define ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ BIT(11) +#define ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ BIT(10) +#define ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ BIT(9) +#define ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ BIT(8) +#define ISPCSI2_IRQSTATUS_CONTEXT(n) BIT(n) #define ISPCSI2_IRQENABLE (0x01c) #define ISPCSI2_CTRL (0x040) -#define ISPCSI2_CTRL_VP_CLK_EN (1 << 15) -#define ISPCSI2_CTRL_VP_ONLY_EN (1 << 11) +#define ISPCSI2_CTRL_VP_CLK_EN BIT(15) +#define ISPCSI2_CTRL_VP_ONLY_EN BIT(11) #define ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT 8 #define ISPCSI2_CTRL_VP_OUT_CTRL_MASK \ (3 << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT) -#define ISPCSI2_CTRL_DBG_EN (1 << 7) +#define ISPCSI2_CTRL_DBG_EN BIT(7) #define ISPCSI2_CTRL_BURST_SIZE_SHIFT 5 #define ISPCSI2_CTRL_BURST_SIZE_MASK \ (3 << ISPCSI2_CTRL_BURST_SIZE_SHIFT) -#define ISPCSI2_CTRL_FRAME (1 << 3) -#define ISPCSI2_CTRL_ECC_EN (1 << 2) -#define ISPCSI2_CTRL_SECURE (1 << 1) -#define ISPCSI2_CTRL_IF_EN (1 << 0) +#define ISPCSI2_CTRL_FRAME BIT(3) +#define ISPCSI2_CTRL_ECC_EN BIT(2) +#define ISPCSI2_CTRL_SECURE BIT(1) +#define ISPCSI2_CTRL_IF_EN BIT(0) #define ISPCSI2_DBG_H (0x044) #define ISPCSI2_GNQ (0x048) #define ISPCSI2_PHY_CFG (0x050) -#define ISPCSI2_PHY_CFG_RESET_CTRL (1 << 30) -#define ISPCSI2_PHY_CFG_RESET_DONE (1 << 29) +#define ISPCSI2_PHY_CFG_RESET_CTRL BIT(30) +#define ISPCSI2_PHY_CFG_RESET_DONE BIT(29) #define ISPCSI2_PHY_CFG_PWR_CMD_SHIFT 27 #define ISPCSI2_PHY_CFG_PWR_CMD_MASK \ (0x3 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT) @@ -1251,7 +1251,7 @@ (0x1 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT) #define ISPCSI2_PHY_CFG_PWR_STATUS_ULPW \ (0x2 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT) -#define ISPCSI2_PHY_CFG_PWR_AUTO (1 << 24) +#define ISPCSI2_PHY_CFG_PWR_AUTO BIT(24) #define ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n) (3 + ((n) * 4)) #define ISPCSI2_PHY_CFG_DATA_POL_MASK(n) \ @@ -1300,63 +1300,63 @@ (0x5 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT) #define ISPCSI2_PHY_IRQSTATUS (0x054) -#define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMEXIT (1 << 26) -#define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMENTER (1 << 25) -#define ISPCSI2_PHY_IRQSTATUS_STATEULPM5 (1 << 24) -#define ISPCSI2_PHY_IRQSTATUS_STATEULPM4 (1 << 23) -#define ISPCSI2_PHY_IRQSTATUS_STATEULPM3 (1 << 22) -#define ISPCSI2_PHY_IRQSTATUS_STATEULPM2 (1 << 21) -#define ISPCSI2_PHY_IRQSTATUS_STATEULPM1 (1 << 20) -#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL5 (1 << 19) -#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL4 (1 << 18) -#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL3 (1 << 17) -#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL2 (1 << 16) -#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL1 (1 << 15) -#define ISPCSI2_PHY_IRQSTATUS_ERRESC5 (1 << 14) -#define ISPCSI2_PHY_IRQSTATUS_ERRESC4 (1 << 13) -#define ISPCSI2_PHY_IRQSTATUS_ERRESC3 (1 << 12) -#define ISPCSI2_PHY_IRQSTATUS_ERRESC2 (1 << 11) -#define ISPCSI2_PHY_IRQSTATUS_ERRESC1 (1 << 10) -#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS5 (1 << 9) -#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS4 (1 << 8) -#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS3 (1 << 7) -#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS2 (1 << 6) -#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS1 (1 << 5) -#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS5 (1 << 4) -#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS4 (1 << 3) -#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS3 (1 << 2) -#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS2 (1 << 1) -#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS1 1 +#define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMEXIT BIT(26) +#define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMENTER BIT(25) +#define ISPCSI2_PHY_IRQSTATUS_STATEULPM5 BIT(24) +#define ISPCSI2_PHY_IRQSTATUS_STATEULPM4 BIT(23) +#define ISPCSI2_PHY_IRQSTATUS_STATEULPM3 BIT(22) +#define ISPCSI2_PHY_IRQSTATUS_STATEULPM2 BIT(21) +#define ISPCSI2_PHY_IRQSTATUS_STATEULPM1 BIT(20) +#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL5 BIT(19) +#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL4 BIT(18) +#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL3 BIT(17) +#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL2 BIT(16) +#define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL1 BIT(15) +#define ISPCSI2_PHY_IRQSTATUS_ERRESC5 BIT(14) +#define ISPCSI2_PHY_IRQSTATUS_ERRESC4 BIT(13) +#define ISPCSI2_PHY_IRQSTATUS_ERRESC3 BIT(12) +#define ISPCSI2_PHY_IRQSTATUS_ERRESC2 BIT(11) +#define ISPCSI2_PHY_IRQSTATUS_ERRESC1 BIT(10) +#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS5 BIT(9) +#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS4 BIT(8) +#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS3 BIT(7) +#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS2 BIT(6) +#define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS1 BIT(5) +#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS5 BIT(4) +#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS4 BIT(3) +#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS3 BIT(2) +#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS2 BIT(1) +#define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS1 BIT(0) #define ISPCSI2_SHORT_PACKET (0x05c) #define ISPCSI2_PHY_IRQENABLE (0x060) -#define ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT (1 << 26) -#define ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER (1 << 25) -#define ISPCSI2_PHY_IRQENABLE_STATEULPM5 (1 << 24) -#define ISPCSI2_PHY_IRQENABLE_STATEULPM4 (1 << 23) -#define ISPCSI2_PHY_IRQENABLE_STATEULPM3 (1 << 22) -#define ISPCSI2_PHY_IRQENABLE_STATEULPM2 (1 << 21) -#define ISPCSI2_PHY_IRQENABLE_STATEULPM1 (1 << 20) -#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 (1 << 19) -#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 (1 << 18) -#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 (1 << 17) -#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 (1 << 16) -#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 (1 << 15) -#define ISPCSI2_PHY_IRQENABLE_ERRESC5 (1 << 14) -#define ISPCSI2_PHY_IRQENABLE_ERRESC4 (1 << 13) -#define ISPCSI2_PHY_IRQENABLE_ERRESC3 (1 << 12) -#define ISPCSI2_PHY_IRQENABLE_ERRESC2 (1 << 11) -#define ISPCSI2_PHY_IRQENABLE_ERRESC1 (1 << 10) -#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 (1 << 9) -#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 (1 << 8) -#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 (1 << 7) -#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 (1 << 6) -#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 (1 << 5) -#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 (1 << 4) -#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 (1 << 3) -#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 (1 << 2) -#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 (1 << 1) -#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS1 (1 << 0) +#define ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT BIT(26) +#define ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER BIT(25) +#define ISPCSI2_PHY_IRQENABLE_STATEULPM5 BIT(24) +#define ISPCSI2_PHY_IRQENABLE_STATEULPM4 BIT(23) +#define ISPCSI2_PHY_IRQENABLE_STATEULPM3 BIT(22) +#define ISPCSI2_PHY_IRQENABLE_STATEULPM2 BIT(21) +#define ISPCSI2_PHY_IRQENABLE_STATEULPM1 BIT(20) +#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 BIT(19) +#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 BIT(18) +#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 BIT(17) +#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 BIT(16) +#define ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 BIT(15) +#define ISPCSI2_PHY_IRQENABLE_ERRESC5 BIT(14) +#define ISPCSI2_PHY_IRQENABLE_ERRESC4 BIT(13) +#define ISPCSI2_PHY_IRQENABLE_ERRESC3 BIT(12) +#define ISPCSI2_PHY_IRQENABLE_ERRESC2 BIT(11) +#define ISPCSI2_PHY_IRQENABLE_ERRESC1 BIT(10) +#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 BIT(9) +#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 BIT(8) +#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 BIT(7) +#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 BIT(6) +#define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 BIT(5) +#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 BIT(4) +#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 BIT(3) +#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 BIT(2) +#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 BIT(1) +#define ISPCSI2_PHY_IRQENABLE_ERRSOTHS1 BIT(0) #define ISPCSI2_DBG_P (0x068) #define ISPCSI2_TIMING (0x06c) @@ -1371,12 +1371,12 @@ #define ISPCSI2_CTX_CTRL1_COUNT_SHIFT 8 #define ISPCSI2_CTX_CTRL1_COUNT_MASK \ (0xff << ISPCSI2_CTX_CTRL1_COUNT_SHIFT) -#define ISPCSI2_CTX_CTRL1_EOF_EN (1 << 7) -#define ISPCSI2_CTX_CTRL1_EOL_EN (1 << 6) -#define ISPCSI2_CTX_CTRL1_CS_EN (1 << 5) -#define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK (1 << 4) -#define ISPCSI2_CTX_CTRL1_PING_PONG (1 << 3) -#define ISPCSI2_CTX_CTRL1_CTX_EN (1 << 0) +#define ISPCSI2_CTX_CTRL1_EOF_EN BIT(7) +#define ISPCSI2_CTX_CTRL1_EOL_EN BIT(6) +#define ISPCSI2_CTX_CTRL1_CS_EN BIT(5) +#define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK BIT(4) +#define ISPCSI2_CTX_CTRL1_PING_PONG BIT(3) +#define ISPCSI2_CTX_CTRL1_CTX_EN BIT(0) #define ISPCSI2_CTX_CTRL2(n) ((0x074) + 0x20 * (n)) #define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT 13 @@ -1385,7 +1385,7 @@ #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT 11 #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK \ (0x3 << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT) -#define ISPCSI2_CTX_CTRL2_DPCM_PRED (1 << 10) +#define ISPCSI2_CTX_CTRL2_DPCM_PRED BIT(10) #define ISPCSI2_CTX_CTRL2_FORMAT_SHIFT 0 #define ISPCSI2_CTX_CTRL2_FORMAT_MASK \ (0x3ff << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT) @@ -1401,24 +1401,24 @@ #define ISPCSI2_CTX_DAT_PING_ADDR(n) ((0x07c) + 0x20 * (n)) #define ISPCSI2_CTX_DAT_PONG_ADDR(n) ((0x080) + 0x20 * (n)) #define ISPCSI2_CTX_IRQENABLE(n) ((0x084) + 0x20 * (n)) -#define ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ (1 << 8) -#define ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ (1 << 7) -#define ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ (1 << 6) -#define ISPCSI2_CTX_IRQENABLE_CS_IRQ (1 << 5) -#define ISPCSI2_CTX_IRQENABLE_LE_IRQ (1 << 3) -#define ISPCSI2_CTX_IRQENABLE_LS_IRQ (1 << 2) -#define ISPCSI2_CTX_IRQENABLE_FE_IRQ (1 << 1) -#define ISPCSI2_CTX_IRQENABLE_FS_IRQ (1 << 0) +#define ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ BIT(8) +#define ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ BIT(7) +#define ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ BIT(6) +#define ISPCSI2_CTX_IRQENABLE_CS_IRQ BIT(5) +#define ISPCSI2_CTX_IRQENABLE_LE_IRQ BIT(3) +#define ISPCSI2_CTX_IRQENABLE_LS_IRQ BIT(2) +#define ISPCSI2_CTX_IRQENABLE_FE_IRQ BIT(1) +#define ISPCSI2_CTX_IRQENABLE_FS_IRQ BIT(0) #define ISPCSI2_CTX_IRQSTATUS(n) ((0x088) + 0x20 * (n)) -#define ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ (1 << 8) -#define ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ (1 << 7) -#define ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ (1 << 6) -#define ISPCSI2_CTX_IRQSTATUS_CS_IRQ (1 << 5) -#define ISPCSI2_CTX_IRQSTATUS_LE_IRQ (1 << 3) -#define ISPCSI2_CTX_IRQSTATUS_LS_IRQ (1 << 2) -#define ISPCSI2_CTX_IRQSTATUS_FE_IRQ (1 << 1) -#define ISPCSI2_CTX_IRQSTATUS_FS_IRQ (1 << 0) +#define ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ BIT(8) +#define ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ BIT(7) +#define ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ BIT(6) +#define ISPCSI2_CTX_IRQSTATUS_CS_IRQ BIT(5) +#define ISPCSI2_CTX_IRQSTATUS_LE_IRQ BIT(3) +#define ISPCSI2_CTX_IRQSTATUS_LS_IRQ BIT(2) +#define ISPCSI2_CTX_IRQSTATUS_FE_IRQ BIT(1) +#define ISPCSI2_CTX_IRQSTATUS_FS_IRQ BIT(0) #define ISPCSI2_CTX_CTRL3(n) ((0x08c) + 0x20 * (n)) #define ISPCSI2_CTX_CTRL3_ALPHA_SHIFT 5 @@ -1454,9 +1454,9 @@ (0xff << ISPCSIPHY_REG0_THS_SETTLE_SHIFT) #define ISPCSIPHY_REG1 (0x004) -#define ISPCSIPHY_REG1_RESET_DONE_CTRLCLK (1 << 29) +#define ISPCSIPHY_REG1_RESET_DONE_CTRLCLK BIT(29) /* This field is for OMAP3630 only */ -#define ISPCSIPHY_REG1_CLOCK_MISS_DETECTOR_STATUS (1 << 25) +#define ISPCSIPHY_REG1_CLOCK_MISS_DETECTOR_STATUS BIT(25) #define ISPCSIPHY_REG1_TCLK_TERM_SHIFT 18 #define ISPCSIPHY_REG1_TCLK_TERM_MASK \ (0x7f << ISPCSIPHY_REG1_TCLK_TERM_SHIFT) @@ -1498,11 +1498,11 @@ */ /* OMAP343X_CONTROL_CSIRXFE */ -#define OMAP343X_CONTROL_CSIRXFE_CSIB_INV (1 << 7) -#define OMAP343X_CONTROL_CSIRXFE_RESENABLE (1 << 8) -#define OMAP343X_CONTROL_CSIRXFE_SELFORM (1 << 10) -#define OMAP343X_CONTROL_CSIRXFE_PWRDNZ (1 << 12) -#define OMAP343X_CONTROL_CSIRXFE_RESET (1 << 13) +#define OMAP343X_CONTROL_CSIRXFE_CSIB_INV BIT(7) +#define OMAP343X_CONTROL_CSIRXFE_RESENABLE BIT(8) +#define OMAP343X_CONTROL_CSIRXFE_SELFORM BIT(10) +#define OMAP343X_CONTROL_CSIRXFE_PWRDNZ BIT(12) +#define OMAP343X_CONTROL_CSIRXFE_RESET BIT(13) /* OMAP3630_CONTROL_CAMERA_PHY_CTRL */ #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY1_SHIFT 2 @@ -1513,6 +1513,6 @@ #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_GPI 0x3 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_MASK 0x3 /* CCP2B: set to receive data from PHY2 instead of PHY1 */ -#define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2 (1 << 4) +#define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2 BIT(4) #endif /* OMAP3_ISP_REG_H */ diff --git a/drivers/media/platform/omap3isp/ispresizer.c b/drivers/media/platform/omap3isp/ispresizer.c index 21ca6954df72..78d9dd7ea2da 100644 --- a/drivers/media/platform/omap3isp/ispresizer.c +++ b/drivers/media/platform/omap3isp/ispresizer.c @@ -1681,6 +1681,7 @@ int omap3isp_resizer_register_entities(struct isp_res_device *res, int ret; /* Register the subdev and video nodes. */ + res->subdev.dev = vdev->mdev->dev; ret = v4l2_device_register_subdev(vdev, &res->subdev); if (ret < 0) goto error; diff --git a/drivers/media/platform/omap3isp/ispstat.c b/drivers/media/platform/omap3isp/ispstat.c index 62b2eacb96fd..5b9b57f4d9bf 100644 --- a/drivers/media/platform/omap3isp/ispstat.c +++ b/drivers/media/platform/omap3isp/ispstat.c @@ -1026,6 +1026,8 @@ void omap3isp_stat_unregister_entities(struct ispstat *stat) int omap3isp_stat_register_entities(struct ispstat *stat, struct v4l2_device *vdev) { + stat->subdev.dev = vdev->mdev->dev; + return v4l2_device_register_subdev(vdev, &stat->subdev); } diff --git a/drivers/media/platform/omap3isp/ispvideo.c b/drivers/media/platform/omap3isp/ispvideo.c index 499a7284c5a8..ee183c35ff3b 100644 --- a/drivers/media/platform/omap3isp/ispvideo.c +++ b/drivers/media/platform/omap3isp/ispvideo.c @@ -658,10 +658,6 @@ isp_video_querycap(struct file *file, void *fh, struct v4l2_capability *cap) cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING | V4L2_CAP_DEVICE_CAPS; - if (video->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) - cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; - else - cap->device_caps = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING; return 0; } @@ -1024,8 +1020,8 @@ static int isp_video_check_external_subdevs(struct isp_video *video, ctrls.count = 1; ctrls.controls = &ctrl; - - ret = v4l2_g_ext_ctrls(pipe->external->ctrl_handler, NULL, &ctrls); + ret = v4l2_g_ext_ctrls(pipe->external->ctrl_handler, &video->video, + NULL, &ctrls); if (ret < 0) { dev_warn(isp->dev, "no pixel rate control in subdev %s\n", pipe->external->name); @@ -1460,6 +1456,13 @@ int omap3isp_video_init(struct isp_video *video, const char *name) video->video.vfl_type = VFL_TYPE_GRABBER; video->video.release = video_device_release_empty; video->video.ioctl_ops = &isp_video_ioctl_ops; + if (video->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) + video->video.device_caps = V4L2_CAP_VIDEO_CAPTURE + | V4L2_CAP_STREAMING; + else + video->video.device_caps = V4L2_CAP_VIDEO_OUTPUT + | V4L2_CAP_STREAMING; + video->pipe.stream_state = ISP_PIPELINE_STREAM_STOPPED; video_set_drvdata(&video->video, video); |