diff options
Diffstat (limited to 'drivers/media/i2c')
39 files changed, 8798 insertions, 1340 deletions
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 69c56e24a612..fae2baabb773 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -3,7 +3,7 @@ # Multimedia Video device configuration # -if VIDEO_V4L2 +if VIDEO_DEV comment "IR I2C driver auto-selected by 'Autoselect ancillary drivers'" depends on MEDIA_SUBDRV_AUTOSELECT && I2C && RC_CORE @@ -22,705 +22,6 @@ config VIDEO_IR_I2C In doubt, say Y. # -# V4L2 I2C drivers that aren't related with Camera support -# - -comment "audio, video and radio I2C drivers auto-selected by 'Autoselect ancillary drivers'" - depends on MEDIA_HIDE_ANCILLARY_SUBDRV -# -# Encoder / Decoder module configuration -# - -menu "Audio decoders, processors and mixers" - visible if !MEDIA_HIDE_ANCILLARY_SUBDRV - -config VIDEO_TVAUDIO - tristate "Simple audio decoder chips" - depends on VIDEO_V4L2 && I2C - help - Support for several audio decoder chips found on some bt8xx boards: - Philips: tda9840, tda9873h, tda9874h/a, tda9850, tda985x, tea6300, - tea6320, tea6420, tda8425, ta8874z. - Microchip: pic16c54 based design on ProVideo PV951 board. - - To compile this driver as a module, choose M here: the - module will be called tvaudio. - -config VIDEO_TDA7432 - tristate "Philips TDA7432 audio processor" - depends on VIDEO_V4L2 && I2C - help - Support for tda7432 audio decoder chip found on some bt8xx boards. - - To compile this driver as a module, choose M here: the - module will be called tda7432. - -config VIDEO_TDA9840 - tristate "Philips TDA9840 audio processor" - depends on I2C - help - Support for tda9840 audio decoder chip found on some Zoran boards. - - To compile this driver as a module, choose M here: the - module will be called tda9840. - -config VIDEO_TDA1997X - tristate "NXP TDA1997x HDMI receiver" - depends on VIDEO_V4L2 && I2C - depends on SND_SOC - select HDMI - select SND_PCM - select V4L2_FWNODE - select MEDIA_CONTROLLER - select VIDEO_V4L2_SUBDEV_API - help - V4L2 subdevice driver for the NXP TDA1997x HDMI receivers. - - To compile this driver as a module, choose M here: the - module will be called tda1997x. - -config VIDEO_TEA6415C - tristate "Philips TEA6415C audio processor" - depends on I2C - help - Support for tea6415c audio decoder chip found on some bt8xx boards. - - To compile this driver as a module, choose M here: the - module will be called tea6415c. - -config VIDEO_TEA6420 - tristate "Philips TEA6420 audio processor" - depends on I2C - help - Support for tea6420 audio decoder chip found on some bt8xx boards. - - To compile this driver as a module, choose M here: the - module will be called tea6420. - -config VIDEO_MSP3400 - tristate "Micronas MSP34xx audio decoders" - depends on VIDEO_V4L2 && I2C - help - Support for the Micronas MSP34xx series of audio decoders. - - To compile this driver as a module, choose M here: the - module will be called msp3400. - -config VIDEO_CS3308 - tristate "Cirrus Logic CS3308 audio ADC" - depends on VIDEO_V4L2 && I2C - help - Support for the Cirrus Logic CS3308 High Performance 8-Channel - Analog Volume Control - - To compile this driver as a module, choose M here: the - module will be called cs3308. - -config VIDEO_CS5345 - tristate "Cirrus Logic CS5345 audio ADC" - depends on VIDEO_V4L2 && I2C - help - Support for the Cirrus Logic CS5345 24-bit, 192 kHz - stereo A/D converter. - - To compile this driver as a module, choose M here: the - module will be called cs5345. - -config VIDEO_CS53L32A - tristate "Cirrus Logic CS53L32A audio ADC" - depends on VIDEO_V4L2 && I2C - help - Support for the Cirrus Logic CS53L32A low voltage - stereo A/D converter. - - To compile this driver as a module, choose M here: the - module will be called cs53l32a. - -config VIDEO_TLV320AIC23B - tristate "Texas Instruments TLV320AIC23B audio codec" - depends on VIDEO_V4L2 && I2C - help - Support for the Texas Instruments TLV320AIC23B audio codec. - - To compile this driver as a module, choose M here: the - module will be called tlv320aic23b. - -config VIDEO_UDA1342 - tristate "Philips UDA1342 audio codec" - depends on VIDEO_V4L2 && I2C - help - Support for the Philips UDA1342 audio codec. - - To compile this driver as a module, choose M here: the - module will be called uda1342. - -config VIDEO_WM8775 - tristate "Wolfson Microelectronics WM8775 audio ADC with input mixer" - depends on VIDEO_V4L2 && I2C - help - Support for the Wolfson Microelectronics WM8775 high - performance stereo A/D Converter with a 4 channel input mixer. - - To compile this driver as a module, choose M here: the - module will be called wm8775. - -config VIDEO_WM8739 - tristate "Wolfson Microelectronics WM8739 stereo audio ADC" - depends on VIDEO_V4L2 && I2C - help - Support for the Wolfson Microelectronics WM8739 - stereo A/D Converter. - - To compile this driver as a module, choose M here: the - module will be called wm8739. - -config VIDEO_VP27SMPX - tristate "Panasonic VP27's internal MPX" - depends on VIDEO_V4L2 && I2C - help - Support for the internal MPX of the Panasonic VP27s tuner. - - To compile this driver as a module, choose M here: the - module will be called vp27smpx. - -config VIDEO_SONY_BTF_MPX - tristate "Sony BTF's internal MPX" - depends on VIDEO_V4L2 && I2C - help - Support for the internal MPX of the Sony BTF-PG472Z tuner. - - To compile this driver as a module, choose M here: the - module will be called sony-btf-mpx. -endmenu - -menu "RDS decoders" - visible if !MEDIA_HIDE_ANCILLARY_SUBDRV - -config VIDEO_SAA6588 - tristate "SAA6588 Radio Chip RDS decoder support" - depends on VIDEO_V4L2 && I2C - - help - Support for this Radio Data System (RDS) decoder. This allows - seeing radio station identification transmitted using this - standard. - - To compile this driver as a module, choose M here: the - module will be called saa6588. -endmenu - -menu "Video decoders" - visible if !MEDIA_HIDE_ANCILLARY_SUBDRV - -config VIDEO_ADV7180 - tristate "Analog Devices ADV7180 decoder" - depends on GPIOLIB && VIDEO_V4L2 && I2C - select MEDIA_CONTROLLER - select VIDEO_V4L2_SUBDEV_API - select V4L2_ASYNC - help - Support for the Analog Devices ADV7180 video decoder. - - To compile this driver as a module, choose M here: the - module will be called adv7180. - -config VIDEO_ADV7183 - tristate "Analog Devices ADV7183 decoder" - depends on VIDEO_V4L2 && I2C - help - V4l2 subdevice driver for the Analog Devices - ADV7183 video decoder. - - To compile this driver as a module, choose M here: the - module will be called adv7183. - -config VIDEO_ADV748X - tristate "Analog Devices ADV748x decoder" - depends on VIDEO_V4L2 && I2C - depends on OF - select MEDIA_CONTROLLER - select VIDEO_V4L2_SUBDEV_API - select REGMAP_I2C - select V4L2_FWNODE - help - V4L2 subdevice driver for the Analog Devices - ADV7481 and ADV7482 HDMI/Analog video decoders. - - To compile this driver as a module, choose M here: the - module will be called adv748x. - -config VIDEO_ADV7604 - tristate "Analog Devices ADV7604 decoder" - depends on VIDEO_V4L2 && I2C - depends on GPIOLIB || COMPILE_TEST - select MEDIA_CONTROLLER - select VIDEO_V4L2_SUBDEV_API - select REGMAP_I2C - select HDMI - select V4L2_FWNODE - help - Support for the Analog Devices ADV7604 video decoder. - - This is a Analog Devices Component/Graphics Digitizer - with 4:1 Multiplexed HDMI Receiver. - - To compile this driver as a module, choose M here: the - module will be called adv7604. - -config VIDEO_ADV7604_CEC - bool "Enable Analog Devices ADV7604 CEC support" - depends on VIDEO_ADV7604 - select CEC_CORE - help - When selected the adv7604 will support the optional - HDMI CEC feature. - -config VIDEO_ADV7842 - tristate "Analog Devices ADV7842 decoder" - depends on VIDEO_V4L2 && I2C - select MEDIA_CONTROLLER - select VIDEO_V4L2_SUBDEV_API - select HDMI - help - Support for the Analog Devices ADV7842 video decoder. - - This is a Analog Devices Component/Graphics/SD Digitizer - with 2:1 Multiplexed HDMI Receiver. - - To compile this driver as a module, choose M here: the - module will be called adv7842. - -config VIDEO_ADV7842_CEC - bool "Enable Analog Devices ADV7842 CEC support" - depends on VIDEO_ADV7842 - select CEC_CORE - help - When selected the adv7842 will support the optional - HDMI CEC feature. - -config VIDEO_BT819 - tristate "BT819A VideoStream decoder" - depends on VIDEO_V4L2 && I2C - help - Support for BT819A video decoder. - - To compile this driver as a module, choose M here: the - module will be called bt819. - -config VIDEO_BT856 - tristate "BT856 VideoStream decoder" - depends on VIDEO_V4L2 && I2C - help - Support for BT856 video decoder. - - To compile this driver as a module, choose M here: the - module will be called bt856. - -config VIDEO_BT866 - tristate "BT866 VideoStream decoder" - depends on VIDEO_V4L2 && I2C - help - Support for BT866 video decoder. - - To compile this driver as a module, choose M here: the - module will be called bt866. - -config VIDEO_KS0127 - tristate "KS0127 video decoder" - depends on VIDEO_V4L2 && I2C - help - Support for KS0127 video decoder. - - This chip is used on AverMedia AVS6EYES Zoran-based MJPEG - cards. - - To compile this driver as a module, choose M here: the - module will be called ks0127. - -config VIDEO_ML86V7667 - tristate "OKI ML86V7667 video decoder" - depends on VIDEO_V4L2 && I2C - help - Support for the OKI Semiconductor ML86V7667 video decoder. - - To compile this driver as a module, choose M here: the - module will be called ml86v7667. - -config VIDEO_SAA7110 - tristate "Philips SAA7110 video decoder" - depends on VIDEO_V4L2 && I2C - help - Support for the Philips SAA7110 video decoders. - - To compile this driver as a module, choose M here: the - module will be called saa7110. - -config VIDEO_SAA711X - tristate "Philips SAA7111/3/4/5 video decoders" - depends on VIDEO_V4L2 && I2C - help - Support for the Philips SAA7111/3/4/5 video decoders. - - To compile this driver as a module, choose M here: the - module will be called saa7115. - -config VIDEO_TC358743 - tristate "Toshiba TC358743 decoder" - depends on VIDEO_V4L2 && I2C - select MEDIA_CONTROLLER - select VIDEO_V4L2_SUBDEV_API - select HDMI - select V4L2_FWNODE - help - Support for the Toshiba TC358743 HDMI to MIPI CSI-2 bridge. - - To compile this driver as a module, choose M here: the - module will be called tc358743. - -config VIDEO_TC358743_CEC - bool "Enable Toshiba TC358743 CEC support" - depends on VIDEO_TC358743 - select CEC_CORE - help - When selected the tc358743 will support the optional - HDMI CEC feature. - -config VIDEO_TVP514X - tristate "Texas Instruments TVP514x video decoder" - depends on VIDEO_V4L2 && I2C - select V4L2_FWNODE - help - This is a Video4Linux2 sensor driver for the TI TVP5146/47 - decoder. It is currently working with the TI OMAP3 camera - controller. - - To compile this driver as a module, choose M here: the - module will be called tvp514x. - -config VIDEO_TVP5150 - tristate "Texas Instruments TVP5150 video decoder" - depends on VIDEO_V4L2 && I2C - select V4L2_FWNODE - select REGMAP_I2C - help - Support for the Texas Instruments TVP5150 video decoder. - - To compile this driver as a module, choose M here: the - module will be called tvp5150. - -config VIDEO_TVP7002 - tristate "Texas Instruments TVP7002 video decoder" - depends on VIDEO_V4L2 && I2C - select V4L2_FWNODE - help - Support for the Texas Instruments TVP7002 video decoder. - - To compile this driver as a module, choose M here: the - module will be called tvp7002. - -config VIDEO_TW2804 - tristate "Techwell TW2804 multiple video decoder" - depends on VIDEO_V4L2 && I2C - help - Support for the Techwell tw2804 multiple video decoder. - - To compile this driver as a module, choose M here: the - module will be called tw2804. - -config VIDEO_TW9903 - tristate "Techwell TW9903 video decoder" - depends on VIDEO_V4L2 && I2C - help - Support for the Techwell tw9903 multi-standard video decoder - with high quality down scaler. - - To compile this driver as a module, choose M here: the - module will be called tw9903. - -config VIDEO_TW9906 - tristate "Techwell TW9906 video decoder" - depends on VIDEO_V4L2 && I2C - help - Support for the Techwell tw9906 enhanced multi-standard comb filter - video decoder with YCbCr input support. - - To compile this driver as a module, choose M here: the - module will be called tw9906. - -config VIDEO_TW9910 - tristate "Techwell TW9910 video decoder" - depends on VIDEO_V4L2 && I2C - select V4L2_ASYNC - help - Support for Techwell TW9910 NTSC/PAL/SECAM video decoder. - - To compile this driver as a module, choose M here: the - module will be called tw9910. - -config VIDEO_VPX3220 - tristate "vpx3220a, vpx3216b & vpx3214c video decoders" - depends on VIDEO_V4L2 && I2C - help - Support for VPX322x video decoders. - - To compile this driver as a module, choose M here: the - module will be called vpx3220. - -config VIDEO_MAX9286 - tristate "Maxim MAX9286 GMSL deserializer support" - depends on I2C && I2C_MUX - depends on VIDEO_V4L2 - depends on OF_GPIO - select V4L2_FWNODE - select VIDEO_V4L2_SUBDEV_API - select MEDIA_CONTROLLER - help - This driver supports the Maxim MAX9286 GMSL deserializer. - - To compile this driver as a module, choose M here: the - module will be called max9286. - -comment "Video and audio decoders" - -config VIDEO_SAA717X - tristate "Philips SAA7171/3/4 audio/video decoders" - depends on VIDEO_V4L2 && I2C - help - Support for the Philips SAA7171/3/4 audio/video decoders. - - To compile this driver as a module, choose M here: the - module will be called saa717x. - -source "drivers/media/i2c/cx25840/Kconfig" - -endmenu - -menu "Video encoders" - visible if !MEDIA_HIDE_ANCILLARY_SUBDRV - -config VIDEO_SAA7127 - tristate "Philips SAA7127/9 digital video encoders" - depends on VIDEO_V4L2 && I2C - help - Support for the Philips SAA7127/9 digital video encoders. - - To compile this driver as a module, choose M here: the - module will be called saa7127. - -config VIDEO_SAA7185 - tristate "Philips SAA7185 video encoder" - depends on VIDEO_V4L2 && I2C - help - Support for the Philips SAA7185 video encoder. - - To compile this driver as a module, choose M here: the - module will be called saa7185. - -config VIDEO_ADV7170 - tristate "Analog Devices ADV7170 video encoder" - depends on VIDEO_V4L2 && I2C - help - Support for the Analog Devices ADV7170 video encoder driver - - To compile this driver as a module, choose M here: the - module will be called adv7170. - -config VIDEO_ADV7175 - tristate "Analog Devices ADV7175 video encoder" - depends on VIDEO_V4L2 && I2C - help - Support for the Analog Devices ADV7175 video encoder driver - - To compile this driver as a module, choose M here: the - module will be called adv7175. - -config VIDEO_ADV7343 - tristate "ADV7343 video encoder" - depends on I2C - select V4L2_ASYNC - help - Support for Analog Devices I2C bus based ADV7343 encoder. - - To compile this driver as a module, choose M here: the - module will be called adv7343. - -config VIDEO_ADV7393 - tristate "ADV7393 video encoder" - depends on I2C - help - Support for Analog Devices I2C bus based ADV7393 encoder. - - To compile this driver as a module, choose M here: the - module will be called adv7393. - -config VIDEO_ADV7511 - tristate "Analog Devices ADV7511 encoder" - depends on VIDEO_V4L2 && I2C - depends on DRM_I2C_ADV7511=n || COMPILE_TEST - select MEDIA_CONTROLLER - select VIDEO_V4L2_SUBDEV_API - select HDMI - help - Support for the Analog Devices ADV7511 video encoder. - - This is a Analog Devices HDMI transmitter. - - To compile this driver as a module, choose M here: the - module will be called adv7511. - -config VIDEO_ADV7511_CEC - bool "Enable Analog Devices ADV7511 CEC support" - depends on VIDEO_ADV7511 - select CEC_CORE - help - When selected the adv7511 will support the optional - HDMI CEC feature. - -config VIDEO_AD9389B - tristate "Analog Devices AD9389B encoder" - depends on VIDEO_V4L2 && I2C - select MEDIA_CONTROLLER - select VIDEO_V4L2_SUBDEV_API - - help - Support for the Analog Devices AD9389B video encoder. - - This is a Analog Devices HDMI transmitter. - - To compile this driver as a module, choose M here: the - module will be called ad9389b. - -config VIDEO_AK881X - tristate "AK8813/AK8814 video encoders" - depends on I2C - help - Video output driver for AKM AK8813 and AK8814 TV encoders - -config VIDEO_THS8200 - tristate "Texas Instruments THS8200 video encoder" - depends on VIDEO_V4L2 && I2C - select V4L2_ASYNC - help - Support for the Texas Instruments THS8200 video encoder. - - To compile this driver as a module, choose M here: the - module will be called ths8200. -endmenu - -menu "Video improvement chips" - visible if !MEDIA_HIDE_ANCILLARY_SUBDRV - -config VIDEO_UPD64031A - tristate "NEC Electronics uPD64031A Ghost Reduction" - depends on VIDEO_V4L2 && I2C - select V4L2_ASYNC - help - Support for the NEC Electronics uPD64031A Ghost Reduction - video chip. It is most often found in NTSC TV cards made for - Japan and is used to reduce the 'ghosting' effect that can - be present in analog TV broadcasts. - - To compile this driver as a module, choose M here: the - module will be called upd64031a. - -config VIDEO_UPD64083 - tristate "NEC Electronics uPD64083 3-Dimensional Y/C separation" - depends on VIDEO_V4L2 && I2C - help - Support for the NEC Electronics uPD64083 3-Dimensional Y/C - separation video chip. It is used to improve the quality of - the colors of a composite signal. - - To compile this driver as a module, choose M here: the - module will be called upd64083. -endmenu - -menu "Audio/Video compression chips" - visible if !MEDIA_HIDE_ANCILLARY_SUBDRV - -config VIDEO_SAA6752HS - tristate "Philips SAA6752HS MPEG-2 Audio/Video Encoder" - depends on VIDEO_V4L2 && I2C - select CRC32 - help - Support for the Philips SAA6752HS MPEG-2 video and MPEG-audio/AC-3 - audio encoder with multiplexer. - - To compile this driver as a module, choose M here: the - module will be called saa6752hs. - -endmenu - -menu "SDR tuner chips" - visible if !MEDIA_HIDE_ANCILLARY_SUBDRV - -config SDR_MAX2175 - tristate "Maxim 2175 RF to Bits tuner" - depends on VIDEO_V4L2 && MEDIA_SDR_SUPPORT && I2C - select REGMAP_I2C - select V4L2_ASYNC - help - Support for Maxim 2175 tuner. It is an advanced analog/digital - radio receiver with RF-to-Bits front-end designed for SDR solutions. - - To compile this driver as a module, choose M here; the - module will be called max2175. - - -endmenu - -menu "Miscellaneous helper chips" - visible if !MEDIA_HIDE_ANCILLARY_SUBDRV - -config VIDEO_THS7303 - tristate "THS7303/53 Video Amplifier" - depends on VIDEO_V4L2 && I2C - select V4L2_ASYNC - help - Support for TI THS7303/53 video amplifier - - To compile this driver as a module, choose M here: the - module will be called ths7303. - -config VIDEO_M52790 - tristate "Mitsubishi M52790 A/V switch" - depends on VIDEO_V4L2 && I2C - help - Support for the Mitsubishi M52790 A/V switch. - - To compile this driver as a module, choose M here: the - module will be called m52790. - -config VIDEO_I2C - tristate "I2C transport video support" - depends on VIDEO_V4L2 && I2C - select VIDEOBUF2_VMALLOC - imply HWMON - help - Enable the I2C transport video support which supports the - following: - * Panasonic AMG88xx Grid-Eye Sensors - * Melexis MLX90640 Thermal Cameras - - To compile this driver as a module, choose M here: the - module will be called video-i2c - -config VIDEO_ST_MIPID02 - tristate "STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge" - depends on I2C && VIDEO_V4L2 - select MEDIA_CONTROLLER - select VIDEO_V4L2_SUBDEV_API - select V4L2_FWNODE - help - Support for STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge. - It is used to allow usage of CSI-2 sensor with PARALLEL port - controller. - - To compile this driver as a module, choose M here: the - module will be called st-mipid02. -endmenu - -# # V4L2 I2C drivers that are related with Camera support # @@ -735,7 +36,7 @@ config VIDEO_CCS_PLL config VIDEO_HI556 tristate "Hynix Hi-556 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_FWNODE @@ -748,7 +49,7 @@ config VIDEO_HI556 config VIDEO_HI846 tristate "Hynix Hi-846 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_FWNODE @@ -759,9 +60,22 @@ config VIDEO_HI846 To compile this driver as a module, choose M here: the module will be called hi846. +config VIDEO_HI847 + tristate "Hynix Hi-847 sensor support" + depends on I2C && VIDEO_DEV + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the Hynix + Hi-847 camera. + + To compile this driver as a module, choose M here: the + module will be called hi847. + config VIDEO_IMX208 tristate "Sony IMX208 sensor support" - depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API + depends on I2C && VIDEO_DEV && VIDEO_V4L2_SUBDEV_API depends on MEDIA_CAMERA_SUPPORT help This is a Video4Linux2 sensor driver for the Sony @@ -772,7 +86,7 @@ config VIDEO_IMX208 config VIDEO_IMX214 tristate "Sony IMX214 sensor support" - depends on GPIOLIB && I2C && VIDEO_V4L2 + depends on GPIOLIB && I2C && VIDEO_DEV select V4L2_FWNODE select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API @@ -786,7 +100,7 @@ config VIDEO_IMX214 config VIDEO_IMX219 tristate "Sony IMX219 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_FWNODE @@ -799,7 +113,7 @@ config VIDEO_IMX219 config VIDEO_IMX258 tristate "Sony IMX258 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API help @@ -811,7 +125,7 @@ config VIDEO_IMX258 config VIDEO_IMX274 tristate "Sony IMX274 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select REGMAP_I2C @@ -821,7 +135,7 @@ config VIDEO_IMX274 config VIDEO_IMX290 tristate "Sony IMX290 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select REGMAP_I2C @@ -835,7 +149,7 @@ config VIDEO_IMX290 config VIDEO_IMX319 tristate "Sony IMX319 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API help @@ -848,7 +162,7 @@ config VIDEO_IMX319 config VIDEO_IMX334 tristate "Sony IMX334 sensor support" depends on OF_GPIO - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select VIDEO_V4L2_SUBDEV_API select MEDIA_CONTROLLER select V4L2_FWNODE @@ -862,7 +176,7 @@ config VIDEO_IMX334 config VIDEO_IMX335 tristate "Sony IMX335 sensor support" depends on OF_GPIO - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select VIDEO_V4L2_SUBDEV_API select MEDIA_CONTROLLER select V4L2_FWNODE @@ -875,7 +189,7 @@ config VIDEO_IMX335 config VIDEO_IMX355 tristate "Sony IMX355 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API help @@ -888,7 +202,7 @@ config VIDEO_IMX355 config VIDEO_IMX412 tristate "Sony IMX412 sensor support" depends on OF_GPIO - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select VIDEO_V4L2_SUBDEV_API select MEDIA_CONTROLLER select V4L2_FWNODE @@ -899,9 +213,119 @@ config VIDEO_IMX412 To compile this driver as a module, choose M here: the module will be called imx412. +config VIDEO_MAX9271_LIB + tristate + +config VIDEO_MT9M001 + tristate "mt9m001 support" + depends on I2C && VIDEO_DEV + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + help + This driver supports MT9M001 cameras from Micron, monochrome + and colour models. + +config VIDEO_MT9M032 + tristate "MT9M032 camera sensor support" + depends on I2C && VIDEO_DEV + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select VIDEO_APTINA_PLL + help + This driver supports MT9M032 camera sensors from Aptina, monochrome + models only. + +config VIDEO_MT9M111 + tristate "mt9m111, mt9m112 and mt9m131 support" + depends on I2C && VIDEO_DEV + select V4L2_FWNODE + help + This driver supports MT9M111, MT9M112 and MT9M131 cameras from + Micron/Aptina + +config VIDEO_MT9P031 + tristate "Aptina MT9P031 support" + depends on I2C && VIDEO_DEV + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select VIDEO_APTINA_PLL + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the Aptina + (Micron) mt9p031 5 Mpixel camera. + +config VIDEO_MT9T001 + tristate "Aptina MT9T001 support" + depends on I2C && VIDEO_DEV + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + help + This is a Video4Linux2 sensor driver for the Aptina + (Micron) mt0t001 3 Mpixel camera. + +config VIDEO_MT9T112 + tristate "Aptina MT9T111/MT9T112 support" + depends on I2C && VIDEO_DEV + help + This is a Video4Linux2 sensor driver for the Aptina + (Micron) MT9T111 and MT9T112 3 Mpixel camera. + + To compile this driver as a module, choose M here: the + module will be called mt9t112. + +config VIDEO_MT9V011 + tristate "Micron mt9v011 sensor support" + depends on I2C && VIDEO_DEV + help + This is a Video4Linux2 sensor driver for the Micron + mt0v011 1.3 Mpixel camera. It currently only works with the + em28xx driver. + +config VIDEO_MT9V032 + tristate "Micron MT9V032 sensor support" + depends on I2C && VIDEO_DEV + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select REGMAP_I2C + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the Micron + MT9V032 752x480 CMOS sensor. + +config VIDEO_MT9V111 + tristate "Aptina MT9V111 sensor support" + depends on I2C && VIDEO_DEV + help + This is a Video4Linux2 sensor driver for the Aptina/Micron + MT9V111 sensor. + + To compile this driver as a module, choose M here: the + module will be called mt9v111. + +config VIDEO_NOON010PC30 + tristate "Siliconfile NOON010PC30 sensor support" + depends on I2C && VIDEO_DEV + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + help + This driver supports NOON010PC30 CIF camera from Siliconfile + +config VIDEO_OG01A1B + tristate "OmniVision OG01A1B sensor support" + depends on I2C && VIDEO_DEV + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the OmniVision + OG01A1B camera. + + To compile this driver as a module, choose M here: the + module will be called og01a1b. + config VIDEO_OV02A10 tristate "OmniVision OV02A10 sensor support" - depends on VIDEO_V4L2 && I2C + depends on VIDEO_DEV && I2C select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_FWNODE @@ -912,9 +336,42 @@ config VIDEO_OV02A10 To compile this driver as a module, choose M here: the module will be called ov02a10. +config VIDEO_OV08D10 + tristate "OmniVision OV08D10 sensor support" + depends on I2C && VIDEO_DEV + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the OmniVision + OV08D10 camera sensor. + + To compile this driver as a module, choose M here: the + module will be called ov08d10. + +config VIDEO_OV13858 + tristate "OmniVision OV13858 sensor support" + depends on I2C && VIDEO_DEV + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the OmniVision + OV13858 camera. + +config VIDEO_OV13B10 + tristate "OmniVision OV13B10 sensor support" + depends on I2C && VIDEO_DEV + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the OmniVision + OV13B10 camera. + config VIDEO_OV2640 tristate "OmniVision OV2640 sensor support" - depends on VIDEO_V4L2 && I2C + depends on VIDEO_DEV && I2C help This is a Video4Linux2 sensor driver for the OmniVision OV2640 camera. @@ -924,7 +381,7 @@ config VIDEO_OV2640 config VIDEO_OV2659 tristate "OmniVision OV2659 sensor support" - depends on VIDEO_V4L2 && I2C && GPIOLIB + depends on VIDEO_DEV && I2C && GPIOLIB select V4L2_FWNODE help This is a Video4Linux2 sensor driver for the OmniVision @@ -935,7 +392,7 @@ config VIDEO_OV2659 config VIDEO_OV2680 tristate "OmniVision OV2680 sensor support" - depends on VIDEO_V4L2 && I2C + depends on VIDEO_DEV && I2C select MEDIA_CONTROLLER select V4L2_FWNODE help @@ -947,7 +404,7 @@ config VIDEO_OV2680 config VIDEO_OV2685 tristate "OmniVision OV2685 sensor support" - depends on VIDEO_V4L2 && I2C + depends on VIDEO_DEV && I2C select MEDIA_CONTROLLER select V4L2_FWNODE help @@ -959,7 +416,7 @@ config VIDEO_OV2685 config VIDEO_OV2740 tristate "OmniVision OV2740 sensor support" - depends on VIDEO_V4L2 && I2C + depends on VIDEO_DEV && I2C depends on ACPI || COMPILE_TEST select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API @@ -975,7 +432,7 @@ config VIDEO_OV2740 config VIDEO_OV5640 tristate "OmniVision OV5640 sensor support" depends on OF - depends on GPIOLIB && VIDEO_V4L2 && I2C + depends on GPIOLIB && VIDEO_DEV && I2C select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_FWNODE @@ -986,7 +443,7 @@ config VIDEO_OV5640 config VIDEO_OV5645 tristate "OmniVision OV5645 sensor support" depends on OF - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_FWNODE @@ -999,7 +456,7 @@ config VIDEO_OV5645 config VIDEO_OV5647 tristate "OmniVision OV5647 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_FWNODE @@ -1012,7 +469,7 @@ config VIDEO_OV5647 config VIDEO_OV5648 tristate "OmniVision OV5648 sensor support" - depends on I2C && PM && VIDEO_V4L2 + depends on I2C && PM && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_FWNODE @@ -1023,19 +480,9 @@ config VIDEO_OV5648 To compile this driver as a module, choose M here: the module will be called ov5648. -config VIDEO_OV6650 - tristate "OmniVision OV6650 sensor support" - depends on I2C && VIDEO_V4L2 - help - This is a Video4Linux2 sensor driver for the OmniVision - OV6650 camera. - - To compile this driver as a module, choose M here: the - module will be called ov6650. - config VIDEO_OV5670 tristate "OmniVision OV5670 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_FWNODE @@ -1048,7 +495,7 @@ config VIDEO_OV5670 config VIDEO_OV5675 tristate "OmniVision OV5675 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_FWNODE @@ -1061,7 +508,7 @@ config VIDEO_OV5675 config VIDEO_OV5693 tristate "OmniVision OV5693 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select V4L2_FWNODE help This is a Video4Linux2 sensor driver for the OmniVision @@ -1072,7 +519,7 @@ config VIDEO_OV5693 config VIDEO_OV5695 tristate "OmniVision OV5695 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select V4L2_FWNODE help This is a Video4Linux2 sensor driver for the OmniVision @@ -1081,9 +528,19 @@ config VIDEO_OV5695 To compile this driver as a module, choose M here: the module will be called ov5695. +config VIDEO_OV6650 + tristate "OmniVision OV6650 sensor support" + depends on I2C && VIDEO_DEV + help + This is a Video4Linux2 sensor driver for the OmniVision + OV6650 camera. + + To compile this driver as a module, choose M here: the + module will be called ov6650. + config VIDEO_OV7251 tristate "OmniVision OV7251 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_FWNODE @@ -1094,21 +551,9 @@ config VIDEO_OV7251 To compile this driver as a module, choose M here: the module will be called ov7251. -config VIDEO_OV772X - tristate "OmniVision OV772x sensor support" - depends on I2C && VIDEO_V4L2 - select REGMAP_SCCB - select V4L2_FWNODE - help - This is a Video4Linux2 sensor driver for the OmniVision - OV772x camera. - - To compile this driver as a module, choose M here: the - module will be called ov772x. - config VIDEO_OV7640 tristate "OmniVision OV7640 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV help This is a Video4Linux2 sensor driver for the OmniVision OV7640 camera. @@ -1118,16 +563,28 @@ config VIDEO_OV7640 config VIDEO_OV7670 tristate "OmniVision OV7670 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select V4L2_FWNODE help This is a Video4Linux2 sensor driver for the OmniVision OV7670 VGA camera. It currently only works with the M88ALP01 controller. +config VIDEO_OV772X + tristate "OmniVision OV772x sensor support" + depends on I2C && VIDEO_DEV + select REGMAP_SCCB + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the OmniVision + OV772x camera. + + To compile this driver as a module, choose M here: the + module will be called ov772x. + config VIDEO_OV7740 tristate "OmniVision OV7740 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select REGMAP_SCCB help This is a Video4Linux2 sensor driver for the OmniVision @@ -1135,7 +592,7 @@ config VIDEO_OV7740 config VIDEO_OV8856 tristate "OmniVision OV8856 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_FWNODE @@ -1148,7 +605,7 @@ config VIDEO_OV8856 config VIDEO_OV8865 tristate "OmniVision OV8865 sensor support" - depends on I2C && PM && VIDEO_V4L2 + depends on I2C && PM && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_FWNODE @@ -1162,7 +619,7 @@ config VIDEO_OV8865 config VIDEO_OV9282 tristate "OmniVision OV9282 sensor support" depends on OF_GPIO - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select VIDEO_V4L2_SUBDEV_API select MEDIA_CONTROLLER select V4L2_FWNODE @@ -1175,14 +632,14 @@ config VIDEO_OV9282 config VIDEO_OV9640 tristate "OmniVision OV9640 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV help This is a Video4Linux2 sensor driver for the OmniVision OV9640 camera sensor. config VIDEO_OV9650 tristate "OmniVision OV9650/OV9652 sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select REGMAP_SCCB @@ -1192,7 +649,7 @@ config VIDEO_OV9650 config VIDEO_OV9734 tristate "OmniVision OV9734 sensor support" - depends on VIDEO_V4L2 && I2C + depends on VIDEO_DEV && I2C depends on ACPI || COMPILE_TEST select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API @@ -1204,141 +661,6 @@ config VIDEO_OV9734 To compile this driver as a module, choose M here: the module's name is ov9734. -config VIDEO_OV13858 - tristate "OmniVision OV13858 sensor support" - depends on I2C && VIDEO_V4L2 - select MEDIA_CONTROLLER - select VIDEO_V4L2_SUBDEV_API - select V4L2_FWNODE - help - This is a Video4Linux2 sensor driver for the OmniVision - OV13858 camera. - -config VIDEO_OV13B10 - tristate "OmniVision OV13B10 sensor support" - depends on I2C && VIDEO_V4L2 - select MEDIA_CONTROLLER - select VIDEO_V4L2_SUBDEV_API - select V4L2_FWNODE - help - This is a Video4Linux2 sensor driver for the OmniVision - OV13B10 camera. - -config VIDEO_VS6624 - tristate "ST VS6624 sensor support" - depends on VIDEO_V4L2 && I2C - help - This is a Video4Linux2 sensor driver for the ST VS6624 - camera. - - To compile this driver as a module, choose M here: the - module will be called vs6624. - -config VIDEO_MT9M001 - tristate "mt9m001 support" - depends on I2C && VIDEO_V4L2 - select MEDIA_CONTROLLER - select VIDEO_V4L2_SUBDEV_API - help - This driver supports MT9M001 cameras from Micron, monochrome - and colour models. - -config VIDEO_MT9M032 - tristate "MT9M032 camera sensor support" - depends on I2C && VIDEO_V4L2 - select MEDIA_CONTROLLER - select VIDEO_V4L2_SUBDEV_API - select VIDEO_APTINA_PLL - help - This driver supports MT9M032 camera sensors from Aptina, monochrome - models only. - -config VIDEO_MT9M111 - tristate "mt9m111, mt9m112 and mt9m131 support" - depends on I2C && VIDEO_V4L2 - select V4L2_FWNODE - help - This driver supports MT9M111, MT9M112 and MT9M131 cameras from - Micron/Aptina - -config VIDEO_MT9P031 - tristate "Aptina MT9P031 support" - depends on I2C && VIDEO_V4L2 - select MEDIA_CONTROLLER - select VIDEO_V4L2_SUBDEV_API - select VIDEO_APTINA_PLL - select V4L2_FWNODE - help - This is a Video4Linux2 sensor driver for the Aptina - (Micron) mt9p031 5 Mpixel camera. - -config VIDEO_MT9T001 - tristate "Aptina MT9T001 support" - depends on I2C && VIDEO_V4L2 - select MEDIA_CONTROLLER - select VIDEO_V4L2_SUBDEV_API - help - This is a Video4Linux2 sensor driver for the Aptina - (Micron) mt0t001 3 Mpixel camera. - -config VIDEO_MT9T112 - tristate "Aptina MT9T111/MT9T112 support" - depends on I2C && VIDEO_V4L2 - help - This is a Video4Linux2 sensor driver for the Aptina - (Micron) MT9T111 and MT9T112 3 Mpixel camera. - - To compile this driver as a module, choose M here: the - module will be called mt9t112. - -config VIDEO_MT9V011 - tristate "Micron mt9v011 sensor support" - depends on I2C && VIDEO_V4L2 - help - This is a Video4Linux2 sensor driver for the Micron - mt0v011 1.3 Mpixel camera. It currently only works with the - em28xx driver. - -config VIDEO_MT9V032 - tristate "Micron MT9V032 sensor support" - depends on I2C && VIDEO_V4L2 - select MEDIA_CONTROLLER - select VIDEO_V4L2_SUBDEV_API - select REGMAP_I2C - select V4L2_FWNODE - help - This is a Video4Linux2 sensor driver for the Micron - MT9V032 752x480 CMOS sensor. - -config VIDEO_MT9V111 - tristate "Aptina MT9V111 sensor support" - depends on I2C && VIDEO_V4L2 - help - This is a Video4Linux2 sensor driver for the Aptina/Micron - MT9V111 sensor. - - To compile this driver as a module, choose M here: the - module will be called mt9v111. - -config VIDEO_SR030PC30 - tristate "Siliconfile SR030PC30 sensor support" - depends on I2C && VIDEO_V4L2 - help - This driver supports SR030PC30 VGA camera from Siliconfile - -config VIDEO_NOON010PC30 - tristate "Siliconfile NOON010PC30 sensor support" - depends on I2C && VIDEO_V4L2 - select MEDIA_CONTROLLER - select VIDEO_V4L2_SUBDEV_API - help - This driver supports NOON010PC30 CIF camera from Siliconfile - -source "drivers/media/i2c/m5mols/Kconfig" - -config VIDEO_MAX9271_LIB - tristate - config VIDEO_RDACM20 tristate "IMI RDACM20 camera support" depends on I2C @@ -1369,7 +691,7 @@ config VIDEO_RDACM21 config VIDEO_RJ54N1 tristate "Sharp RJ54N1CB0C sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV help This is a V4L2 sensor driver for Sharp RJ54N1CB0C CMOS image sensor. @@ -1377,27 +699,19 @@ config VIDEO_RJ54N1 To compile this driver as a module, choose M here: the module will be called rj54n1. -config VIDEO_S5K6AA - tristate "Samsung S5K6AAFX sensor support" - depends on I2C && VIDEO_V4L2 - select MEDIA_CONTROLLER - select VIDEO_V4L2_SUBDEV_API - help - This is a V4L2 sensor driver for Samsung S5K6AA(FX) 1.3M - camera sensor with an embedded SoC image signal processor. - -config VIDEO_S5K6A3 - tristate "Samsung S5K6A3 sensor support" - depends on I2C && VIDEO_V4L2 +config VIDEO_S5C73M3 + tristate "Samsung S5C73M3 sensor support" + depends on I2C && SPI && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE help - This is a V4L2 sensor driver for Samsung S5K6A3 raw - camera sensor. + This is a V4L2 sensor driver for Samsung S5C73M3 + 8 Mpixel camera. config VIDEO_S5K4ECGX tristate "Samsung S5K4ECGX sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select CRC32 @@ -1407,7 +721,7 @@ config VIDEO_S5K4ECGX config VIDEO_S5K5BAF tristate "Samsung S5K5BAF sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_FWNODE @@ -1415,18 +729,43 @@ config VIDEO_S5K5BAF This is a V4L2 sensor driver for Samsung S5K5BAF 2M camera sensor with an embedded SoC image signal processor. -source "drivers/media/i2c/ccs/Kconfig" -source "drivers/media/i2c/et8ek8/Kconfig" +config VIDEO_S5K6A3 + tristate "Samsung S5K6A3 sensor support" + depends on I2C && VIDEO_DEV + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + help + This is a V4L2 sensor driver for Samsung S5K6A3 raw + camera sensor. -config VIDEO_S5C73M3 - tristate "Samsung S5C73M3 sensor support" - depends on I2C && SPI && VIDEO_V4L2 +config VIDEO_S5K6AA + tristate "Samsung S5K6AAFX sensor support" + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API - select V4L2_FWNODE help - This is a V4L2 sensor driver for Samsung S5C73M3 - 8 Mpixel camera. + This is a V4L2 sensor driver for Samsung S5K6AA(FX) 1.3M + camera sensor with an embedded SoC image signal processor. + +config VIDEO_SR030PC30 + tristate "Siliconfile SR030PC30 sensor support" + depends on I2C && VIDEO_DEV + help + This driver supports SR030PC30 VGA camera from Siliconfile + +config VIDEO_VS6624 + tristate "ST VS6624 sensor support" + depends on VIDEO_DEV && I2C + help + This is a Video4Linux2 sensor driver for the ST VS6624 + camera. + + To compile this driver as a module, choose M here: the + module will be called vs6624. + +source "drivers/media/i2c/ccs/Kconfig" +source "drivers/media/i2c/et8ek8/Kconfig" +source "drivers/media/i2c/m5mols/Kconfig" endmenu @@ -1435,7 +774,7 @@ menu "Lens drivers" config VIDEO_AD5820 tristate "AD5820 lens voice coil support" - depends on GPIOLIB && I2C && VIDEO_V4L2 + depends on GPIOLIB && I2C && VIDEO_DEV select MEDIA_CONTROLLER select V4L2_ASYNC help @@ -1444,7 +783,7 @@ config VIDEO_AD5820 config VIDEO_AK7375 tristate "AK7375 lens voice coil support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_ASYNC @@ -1456,7 +795,7 @@ config VIDEO_AK7375 config VIDEO_DW9714 tristate "DW9714 lens voice coil support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_ASYNC @@ -1468,7 +807,7 @@ config VIDEO_DW9714 config VIDEO_DW9768 tristate "DW9768 lens voice coil support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_FWNODE @@ -1480,7 +819,7 @@ config VIDEO_DW9768 config VIDEO_DW9807_VCM tristate "DW9807 lens voice coil support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_ASYNC @@ -1497,7 +836,7 @@ menu "Flash devices" config VIDEO_ADP1653 tristate "ADP1653 flash support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select V4L2_ASYNC help @@ -1506,7 +845,7 @@ config VIDEO_ADP1653 config VIDEO_LM3560 tristate "LM3560 dual flash driver support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select REGMAP_I2C select V4L2_ASYNC @@ -1516,13 +855,727 @@ config VIDEO_LM3560 config VIDEO_LM3646 tristate "LM3646 dual flash driver support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select REGMAP_I2C select V4L2_ASYNC help This is a driver for the lm3646 dual flash controllers. It controls flash, torch LEDs. + +endmenu + +# +# V4L2 I2C drivers that aren't related with Camera support +# + +comment "audio, video and radio I2C drivers auto-selected by 'Autoselect ancillary drivers'" + depends on MEDIA_HIDE_ANCILLARY_SUBDRV +# +# Encoder / Decoder module configuration +# + +menu "Audio decoders, processors and mixers" + visible if !MEDIA_HIDE_ANCILLARY_SUBDRV + +config VIDEO_CS3308 + tristate "Cirrus Logic CS3308 audio ADC" + depends on VIDEO_DEV && I2C + help + Support for the Cirrus Logic CS3308 High Performance 8-Channel + Analog Volume Control + + To compile this driver as a module, choose M here: the + module will be called cs3308. + +config VIDEO_CS5345 + tristate "Cirrus Logic CS5345 audio ADC" + depends on VIDEO_DEV && I2C + help + Support for the Cirrus Logic CS5345 24-bit, 192 kHz + stereo A/D converter. + + To compile this driver as a module, choose M here: the + module will be called cs5345. + +config VIDEO_CS53L32A + tristate "Cirrus Logic CS53L32A audio ADC" + depends on VIDEO_DEV && I2C + help + Support for the Cirrus Logic CS53L32A low voltage + stereo A/D converter. + + To compile this driver as a module, choose M here: the + module will be called cs53l32a. + +config VIDEO_MSP3400 + tristate "Micronas MSP34xx audio decoders" + depends on VIDEO_DEV && I2C + help + Support for the Micronas MSP34xx series of audio decoders. + + To compile this driver as a module, choose M here: the + module will be called msp3400. + +config VIDEO_SONY_BTF_MPX + tristate "Sony BTF's internal MPX" + depends on VIDEO_DEV && I2C + help + Support for the internal MPX of the Sony BTF-PG472Z tuner. + + To compile this driver as a module, choose M here: the + module will be called sony-btf-mpx. + +config VIDEO_TDA1997X + tristate "NXP TDA1997x HDMI receiver" + depends on VIDEO_DEV && I2C + depends on SND_SOC + select HDMI + select SND_PCM + select V4L2_FWNODE + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + help + V4L2 subdevice driver for the NXP TDA1997x HDMI receivers. + + To compile this driver as a module, choose M here: the + module will be called tda1997x. + +config VIDEO_TDA7432 + tristate "Philips TDA7432 audio processor" + depends on VIDEO_DEV && I2C + help + Support for tda7432 audio decoder chip found on some bt8xx boards. + + To compile this driver as a module, choose M here: the + module will be called tda7432. + +config VIDEO_TDA9840 + tristate "Philips TDA9840 audio processor" + depends on I2C + help + Support for tda9840 audio decoder chip found on some Zoran boards. + + To compile this driver as a module, choose M here: the + module will be called tda9840. + +config VIDEO_TEA6415C + tristate "Philips TEA6415C audio processor" + depends on I2C + help + Support for tea6415c audio decoder chip found on some bt8xx boards. + + To compile this driver as a module, choose M here: the + module will be called tea6415c. + +config VIDEO_TEA6420 + tristate "Philips TEA6420 audio processor" + depends on I2C + help + Support for tea6420 audio decoder chip found on some bt8xx boards. + + To compile this driver as a module, choose M here: the + module will be called tea6420. + +config VIDEO_TLV320AIC23B + tristate "Texas Instruments TLV320AIC23B audio codec" + depends on VIDEO_DEV && I2C + help + Support for the Texas Instruments TLV320AIC23B audio codec. + + To compile this driver as a module, choose M here: the + module will be called tlv320aic23b. + +config VIDEO_TVAUDIO + tristate "Simple audio decoder chips" + depends on VIDEO_DEV && I2C + help + Support for several audio decoder chips found on some bt8xx boards: + Philips: tda9840, tda9873h, tda9874h/a, tda9850, tda985x, tea6300, + tea6320, tea6420, tda8425, ta8874z. + Microchip: pic16c54 based design on ProVideo PV951 board. + + To compile this driver as a module, choose M here: the + module will be called tvaudio. + +config VIDEO_UDA1342 + tristate "Philips UDA1342 audio codec" + depends on VIDEO_DEV && I2C + help + Support for the Philips UDA1342 audio codec. + + To compile this driver as a module, choose M here: the + module will be called uda1342. + +config VIDEO_VP27SMPX + tristate "Panasonic VP27's internal MPX" + depends on VIDEO_DEV && I2C + help + Support for the internal MPX of the Panasonic VP27s tuner. + + To compile this driver as a module, choose M here: the + module will be called vp27smpx. + +config VIDEO_WM8739 + tristate "Wolfson Microelectronics WM8739 stereo audio ADC" + depends on VIDEO_DEV && I2C + help + Support for the Wolfson Microelectronics WM8739 + stereo A/D Converter. + + To compile this driver as a module, choose M here: the + module will be called wm8739. + +config VIDEO_WM8775 + tristate "Wolfson Microelectronics WM8775 audio ADC with input mixer" + depends on VIDEO_DEV && I2C + help + Support for the Wolfson Microelectronics WM8775 high + performance stereo A/D Converter with a 4 channel input mixer. + + To compile this driver as a module, choose M here: the + module will be called wm8775. + +endmenu + +menu "RDS decoders" + visible if !MEDIA_HIDE_ANCILLARY_SUBDRV + +config VIDEO_SAA6588 + tristate "SAA6588 Radio Chip RDS decoder support" + depends on VIDEO_DEV && I2C + + help + Support for this Radio Data System (RDS) decoder. This allows + seeing radio station identification transmitted using this + standard. + + To compile this driver as a module, choose M here: the + module will be called saa6588. + +endmenu + +menu "Video decoders" + visible if !MEDIA_HIDE_ANCILLARY_SUBDRV + +config VIDEO_ADV7180 + tristate "Analog Devices ADV7180 decoder" + depends on GPIOLIB && VIDEO_DEV && I2C + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_ASYNC + help + Support for the Analog Devices ADV7180 video decoder. + + To compile this driver as a module, choose M here: the + module will be called adv7180. + +config VIDEO_ADV7183 + tristate "Analog Devices ADV7183 decoder" + depends on VIDEO_DEV && I2C + help + V4l2 subdevice driver for the Analog Devices + ADV7183 video decoder. + + To compile this driver as a module, choose M here: the + module will be called adv7183. + +config VIDEO_ADV748X + tristate "Analog Devices ADV748x decoder" + depends on VIDEO_DEV && I2C + depends on OF + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select REGMAP_I2C + select V4L2_FWNODE + help + V4L2 subdevice driver for the Analog Devices + ADV7481 and ADV7482 HDMI/Analog video decoders. + + To compile this driver as a module, choose M here: the + module will be called adv748x. + +config VIDEO_ADV7604 + tristate "Analog Devices ADV7604 decoder" + depends on VIDEO_DEV && I2C + depends on GPIOLIB || COMPILE_TEST + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select REGMAP_I2C + select HDMI + select V4L2_FWNODE + help + Support for the Analog Devices ADV7604 video decoder. + + This is a Analog Devices Component/Graphics Digitizer + with 4:1 Multiplexed HDMI Receiver. + + To compile this driver as a module, choose M here: the + module will be called adv7604. + +config VIDEO_ADV7604_CEC + bool "Enable Analog Devices ADV7604 CEC support" + depends on VIDEO_ADV7604 + select CEC_CORE + help + When selected the adv7604 will support the optional + HDMI CEC feature. + +config VIDEO_ADV7842 + tristate "Analog Devices ADV7842 decoder" + depends on VIDEO_DEV && I2C + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select HDMI + help + Support for the Analog Devices ADV7842 video decoder. + + This is a Analog Devices Component/Graphics/SD Digitizer + with 2:1 Multiplexed HDMI Receiver. + + To compile this driver as a module, choose M here: the + module will be called adv7842. + +config VIDEO_ADV7842_CEC + bool "Enable Analog Devices ADV7842 CEC support" + depends on VIDEO_ADV7842 + select CEC_CORE + help + When selected the adv7842 will support the optional + HDMI CEC feature. + +config VIDEO_BT819 + tristate "BT819A VideoStream decoder" + depends on VIDEO_DEV && I2C + help + Support for BT819A video decoder. + + To compile this driver as a module, choose M here: the + module will be called bt819. + +config VIDEO_BT856 + tristate "BT856 VideoStream decoder" + depends on VIDEO_DEV && I2C + help + Support for BT856 video decoder. + + To compile this driver as a module, choose M here: the + module will be called bt856. + +config VIDEO_BT866 + tristate "BT866 VideoStream decoder" + depends on VIDEO_DEV && I2C + help + Support for BT866 video decoder. + + To compile this driver as a module, choose M here: the + module will be called bt866. + +config VIDEO_ISL7998X + tristate "Intersil ISL7998x video decoder" + depends on VIDEO_DEV && I2C + depends on OF_GPIO + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + help + Support for Intersil ISL7998x analog to MIPI-CSI2 or + BT.656 decoder. + +config VIDEO_KS0127 + tristate "KS0127 video decoder" + depends on VIDEO_DEV && I2C + help + Support for KS0127 video decoder. + + This chip is used on AverMedia AVS6EYES Zoran-based MJPEG + cards. + + To compile this driver as a module, choose M here: the + module will be called ks0127. + +config VIDEO_MAX9286 + tristate "Maxim MAX9286 GMSL deserializer support" + depends on I2C && I2C_MUX + depends on VIDEO_DEV + depends on OF_GPIO + select V4L2_FWNODE + select VIDEO_V4L2_SUBDEV_API + select MEDIA_CONTROLLER + help + This driver supports the Maxim MAX9286 GMSL deserializer. + + To compile this driver as a module, choose M here: the + module will be called max9286. + +config VIDEO_ML86V7667 + tristate "OKI ML86V7667 video decoder" + depends on VIDEO_DEV && I2C + help + Support for the OKI Semiconductor ML86V7667 video decoder. + + To compile this driver as a module, choose M here: the + module will be called ml86v7667. + +config VIDEO_SAA7110 + tristate "Philips SAA7110 video decoder" + depends on VIDEO_DEV && I2C + help + Support for the Philips SAA7110 video decoders. + + To compile this driver as a module, choose M here: the + module will be called saa7110. + +config VIDEO_SAA711X + tristate "Philips SAA7111/3/4/5 video decoders" + depends on VIDEO_DEV && I2C + help + Support for the Philips SAA7111/3/4/5 video decoders. + + To compile this driver as a module, choose M here: the + module will be called saa7115. + +config VIDEO_TC358743 + tristate "Toshiba TC358743 decoder" + depends on VIDEO_DEV && I2C + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select HDMI + select V4L2_FWNODE + help + Support for the Toshiba TC358743 HDMI to MIPI CSI-2 bridge. + + To compile this driver as a module, choose M here: the + module will be called tc358743. + +config VIDEO_TC358743_CEC + bool "Enable Toshiba TC358743 CEC support" + depends on VIDEO_TC358743 + select CEC_CORE + help + When selected the tc358743 will support the optional + HDMI CEC feature. + +config VIDEO_TVP514X + tristate "Texas Instruments TVP514x video decoder" + depends on VIDEO_DEV && I2C + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the TI TVP5146/47 + decoder. It is currently working with the TI OMAP3 camera + controller. + + To compile this driver as a module, choose M here: the + module will be called tvp514x. + +config VIDEO_TVP5150 + tristate "Texas Instruments TVP5150 video decoder" + depends on VIDEO_DEV && I2C + select V4L2_FWNODE + select REGMAP_I2C + help + Support for the Texas Instruments TVP5150 video decoder. + + To compile this driver as a module, choose M here: the + module will be called tvp5150. + +config VIDEO_TVP7002 + tristate "Texas Instruments TVP7002 video decoder" + depends on VIDEO_DEV && I2C + select V4L2_FWNODE + help + Support for the Texas Instruments TVP7002 video decoder. + + To compile this driver as a module, choose M here: the + module will be called tvp7002. + +config VIDEO_TW2804 + tristate "Techwell TW2804 multiple video decoder" + depends on VIDEO_DEV && I2C + help + Support for the Techwell tw2804 multiple video decoder. + + To compile this driver as a module, choose M here: the + module will be called tw2804. + +config VIDEO_TW9903 + tristate "Techwell TW9903 video decoder" + depends on VIDEO_DEV && I2C + help + Support for the Techwell tw9903 multi-standard video decoder + with high quality down scaler. + + To compile this driver as a module, choose M here: the + module will be called tw9903. + +config VIDEO_TW9906 + tristate "Techwell TW9906 video decoder" + depends on VIDEO_DEV && I2C + help + Support for the Techwell tw9906 enhanced multi-standard comb filter + video decoder with YCbCr input support. + + To compile this driver as a module, choose M here: the + module will be called tw9906. + +config VIDEO_TW9910 + tristate "Techwell TW9910 video decoder" + depends on VIDEO_DEV && I2C + select V4L2_ASYNC + help + Support for Techwell TW9910 NTSC/PAL/SECAM video decoder. + + To compile this driver as a module, choose M here: the + module will be called tw9910. + +config VIDEO_VPX3220 + tristate "vpx3220a, vpx3216b & vpx3214c video decoders" + depends on VIDEO_DEV && I2C + help + Support for VPX322x video decoders. + + To compile this driver as a module, choose M here: the + module will be called vpx3220. + +comment "Video and audio decoders" + +config VIDEO_SAA717X + tristate "Philips SAA7171/3/4 audio/video decoders" + depends on VIDEO_DEV && I2C + help + Support for the Philips SAA7171/3/4 audio/video decoders. + + To compile this driver as a module, choose M here: the + module will be called saa717x. + +source "drivers/media/i2c/cx25840/Kconfig" + +endmenu + +menu "Video encoders" + visible if !MEDIA_HIDE_ANCILLARY_SUBDRV + +config VIDEO_AD9389B + tristate "Analog Devices AD9389B encoder" + depends on VIDEO_DEV && I2C + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + + help + Support for the Analog Devices AD9389B video encoder. + + This is a Analog Devices HDMI transmitter. + + To compile this driver as a module, choose M here: the + module will be called ad9389b. + +config VIDEO_ADV7170 + tristate "Analog Devices ADV7170 video encoder" + depends on VIDEO_DEV && I2C + help + Support for the Analog Devices ADV7170 video encoder driver + + To compile this driver as a module, choose M here: the + module will be called adv7170. + +config VIDEO_ADV7175 + tristate "Analog Devices ADV7175 video encoder" + depends on VIDEO_DEV && I2C + help + Support for the Analog Devices ADV7175 video encoder driver + + To compile this driver as a module, choose M here: the + module will be called adv7175. + +config VIDEO_ADV7343 + tristate "ADV7343 video encoder" + depends on I2C + select V4L2_ASYNC + help + Support for Analog Devices I2C bus based ADV7343 encoder. + + To compile this driver as a module, choose M here: the + module will be called adv7343. + +config VIDEO_ADV7393 + tristate "ADV7393 video encoder" + depends on I2C + help + Support for Analog Devices I2C bus based ADV7393 encoder. + + To compile this driver as a module, choose M here: the + module will be called adv7393. + +config VIDEO_ADV7511 + tristate "Analog Devices ADV7511 encoder" + depends on VIDEO_DEV && I2C + depends on DRM_I2C_ADV7511=n || COMPILE_TEST + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select HDMI + help + Support for the Analog Devices ADV7511 video encoder. + + This is a Analog Devices HDMI transmitter. + + To compile this driver as a module, choose M here: the + module will be called adv7511. + +config VIDEO_ADV7511_CEC + bool "Enable Analog Devices ADV7511 CEC support" + depends on VIDEO_ADV7511 + select CEC_CORE + help + When selected the adv7511 will support the optional + HDMI CEC feature. + +config VIDEO_AK881X + tristate "AK8813/AK8814 video encoders" + depends on I2C + help + Video output driver for AKM AK8813 and AK8814 TV encoders + +config VIDEO_SAA7127 + tristate "Philips SAA7127/9 digital video encoders" + depends on VIDEO_DEV && I2C + help + Support for the Philips SAA7127/9 digital video encoders. + + To compile this driver as a module, choose M here: the + module will be called saa7127. + +config VIDEO_SAA7185 + tristate "Philips SAA7185 video encoder" + depends on VIDEO_DEV && I2C + help + Support for the Philips SAA7185 video encoder. + + To compile this driver as a module, choose M here: the + module will be called saa7185. + +config VIDEO_THS8200 + tristate "Texas Instruments THS8200 video encoder" + depends on VIDEO_DEV && I2C + select V4L2_ASYNC + help + Support for the Texas Instruments THS8200 video encoder. + + To compile this driver as a module, choose M here: the + module will be called ths8200. + +endmenu + +menu "Video improvement chips" + visible if !MEDIA_HIDE_ANCILLARY_SUBDRV + +config VIDEO_UPD64031A + tristate "NEC Electronics uPD64031A Ghost Reduction" + depends on VIDEO_DEV && I2C + select V4L2_ASYNC + help + Support for the NEC Electronics uPD64031A Ghost Reduction + video chip. It is most often found in NTSC TV cards made for + Japan and is used to reduce the 'ghosting' effect that can + be present in analog TV broadcasts. + + To compile this driver as a module, choose M here: the + module will be called upd64031a. + +config VIDEO_UPD64083 + tristate "NEC Electronics uPD64083 3-Dimensional Y/C separation" + depends on VIDEO_DEV && I2C + help + Support for the NEC Electronics uPD64083 3-Dimensional Y/C + separation video chip. It is used to improve the quality of + the colors of a composite signal. + + To compile this driver as a module, choose M here: the + module will be called upd64083. + +endmenu + +menu "Audio/Video compression chips" + visible if !MEDIA_HIDE_ANCILLARY_SUBDRV + +config VIDEO_SAA6752HS + tristate "Philips SAA6752HS MPEG-2 Audio/Video Encoder" + depends on VIDEO_DEV && I2C + select CRC32 + help + Support for the Philips SAA6752HS MPEG-2 video and MPEG-audio/AC-3 + audio encoder with multiplexer. + + To compile this driver as a module, choose M here: the + module will be called saa6752hs. + +endmenu + +menu "SDR tuner chips" + visible if !MEDIA_HIDE_ANCILLARY_SUBDRV + +config SDR_MAX2175 + tristate "Maxim 2175 RF to Bits tuner" + depends on VIDEO_DEV && MEDIA_SDR_SUPPORT && I2C + select REGMAP_I2C + select V4L2_ASYNC + help + Support for Maxim 2175 tuner. It is an advanced analog/digital + radio receiver with RF-to-Bits front-end designed for SDR solutions. + + To compile this driver as a module, choose M here; the + module will be called max2175. + +endmenu + +menu "Miscellaneous helper chips" + visible if !MEDIA_HIDE_ANCILLARY_SUBDRV + +config VIDEO_I2C + tristate "I2C transport video support" + depends on VIDEO_DEV && I2C + select VIDEOBUF2_VMALLOC + imply HWMON + help + Enable the I2C transport video support which supports the + following: + * Panasonic AMG88xx Grid-Eye Sensors + * Melexis MLX90640 Thermal Cameras + + To compile this driver as a module, choose M here: the + module will be called video-i2c + +config VIDEO_M52790 + tristate "Mitsubishi M52790 A/V switch" + depends on VIDEO_DEV && I2C + help + Support for the Mitsubishi M52790 A/V switch. + + To compile this driver as a module, choose M here: the + module will be called m52790. + +config VIDEO_ST_MIPID02 + tristate "STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge" + depends on I2C && VIDEO_DEV + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + Support for STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge. + It is used to allow usage of CSI-2 sensor with PARALLEL port + controller. + + To compile this driver as a module, choose M here: the + module will be called st-mipid02. + +config VIDEO_THS7303 + tristate "THS7303/53 Video Amplifier" + depends on VIDEO_DEV && I2C + select V4L2_ASYNC + help + Support for TI THS7303/53 video amplifier + + To compile this driver as a module, choose M here: the + module will be called ths7303. + endmenu -endif # VIDEO_V4L2 +endif # VIDEO_DEV diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index b01f6cd05ee8..3e1696963e7f 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -1,31 +1,11 @@ # SPDX-License-Identifier: GPL-2.0 -msp3400-objs := msp3400-driver.o msp3400-kthreads.o -obj-$(CONFIG_VIDEO_MSP3400) += msp3400.o -obj-$(CONFIG_VIDEO_CCS) += ccs/ -obj-$(CONFIG_VIDEO_ET8EK8) += et8ek8/ -obj-$(CONFIG_VIDEO_CX25840) += cx25840/ -obj-$(CONFIG_VIDEO_M5MOLS) += m5mols/ +msp3400-objs := msp3400-driver.o msp3400-kthreads.o -obj-$(CONFIG_VIDEO_APTINA_PLL) += aptina-pll.o -obj-$(CONFIG_VIDEO_TVAUDIO) += tvaudio.o -obj-$(CONFIG_VIDEO_TDA7432) += tda7432.o -obj-$(CONFIG_VIDEO_SAA6588) += saa6588.o -obj-$(CONFIG_VIDEO_TDA9840) += tda9840.o -obj-$(CONFIG_VIDEO_TDA1997X) += tda1997x.o -obj-$(CONFIG_VIDEO_TEA6415C) += tea6415c.o -obj-$(CONFIG_VIDEO_TEA6420) += tea6420.o -obj-$(CONFIG_VIDEO_SAA7110) += saa7110.o -obj-$(CONFIG_VIDEO_SAA711X) += saa7115.o -obj-$(CONFIG_VIDEO_SAA717X) += saa717x.o -obj-$(CONFIG_VIDEO_SAA7127) += saa7127.o -obj-$(CONFIG_VIDEO_SAA7185) += saa7185.o -obj-$(CONFIG_VIDEO_SAA6752HS) += saa6752hs.o -obj-$(CONFIG_VIDEO_AD5820) += ad5820.o -obj-$(CONFIG_VIDEO_AK7375) += ak7375.o -obj-$(CONFIG_VIDEO_DW9714) += dw9714.o -obj-$(CONFIG_VIDEO_DW9768) += dw9768.o -obj-$(CONFIG_VIDEO_DW9807_VCM) += dw9807-vcm.o +obj-$(CONFIG_SDR_MAX2175) += max2175.o +obj-$(CONFIG_VIDEO_AD5820) += ad5820.o +obj-$(CONFIG_VIDEO_AD9389B) += ad9389b.o +obj-$(CONFIG_VIDEO_ADP1653) += adp1653.o obj-$(CONFIG_VIDEO_ADV7170) += adv7170.o obj-$(CONFIG_VIDEO_ADV7175) += adv7175.o obj-$(CONFIG_VIDEO_ADV7180) += adv7180.o @@ -33,39 +13,68 @@ obj-$(CONFIG_VIDEO_ADV7183) += adv7183.o obj-$(CONFIG_VIDEO_ADV7343) += adv7343.o obj-$(CONFIG_VIDEO_ADV7393) += adv7393.o obj-$(CONFIG_VIDEO_ADV748X) += adv748x/ +obj-$(CONFIG_VIDEO_ADV7511) += adv7511-v4l2.o obj-$(CONFIG_VIDEO_ADV7604) += adv7604.o obj-$(CONFIG_VIDEO_ADV7842) += adv7842.o -obj-$(CONFIG_VIDEO_AD9389B) += ad9389b.o -obj-$(CONFIG_VIDEO_ADV7511) += adv7511-v4l2.o -obj-$(CONFIG_VIDEO_VPX3220) += vpx3220.o -obj-$(CONFIG_VIDEO_VS6624) += vs6624.o +obj-$(CONFIG_VIDEO_AK7375) += ak7375.o +obj-$(CONFIG_VIDEO_AK881X) += ak881x.o +obj-$(CONFIG_VIDEO_APTINA_PLL) += aptina-pll.o obj-$(CONFIG_VIDEO_BT819) += bt819.o obj-$(CONFIG_VIDEO_BT856) += bt856.o obj-$(CONFIG_VIDEO_BT866) += bt866.o -obj-$(CONFIG_VIDEO_KS0127) += ks0127.o -obj-$(CONFIG_VIDEO_THS7303) += ths7303.o -obj-$(CONFIG_VIDEO_THS8200) += ths8200.o -obj-$(CONFIG_VIDEO_TVP5150) += tvp5150.o -obj-$(CONFIG_VIDEO_TVP514X) += tvp514x.o -obj-$(CONFIG_VIDEO_TVP7002) += tvp7002.o -obj-$(CONFIG_VIDEO_TW2804) += tw2804.o -obj-$(CONFIG_VIDEO_TW9903) += tw9903.o -obj-$(CONFIG_VIDEO_TW9906) += tw9906.o -obj-$(CONFIG_VIDEO_TW9910) += tw9910.o +obj-$(CONFIG_VIDEO_CCS) += ccs/ +obj-$(CONFIG_VIDEO_CCS_PLL) += ccs-pll.o obj-$(CONFIG_VIDEO_CS3308) += cs3308.o obj-$(CONFIG_VIDEO_CS5345) += cs5345.o obj-$(CONFIG_VIDEO_CS53L32A) += cs53l32a.o +obj-$(CONFIG_VIDEO_CX25840) += cx25840/ +obj-$(CONFIG_VIDEO_DW9714) += dw9714.o +obj-$(CONFIG_VIDEO_DW9768) += dw9768.o +obj-$(CONFIG_VIDEO_DW9807_VCM) += dw9807-vcm.o +obj-$(CONFIG_VIDEO_ET8EK8) += et8ek8/ +obj-$(CONFIG_VIDEO_HI556) += hi556.o +obj-$(CONFIG_VIDEO_HI846) += hi846.o +obj-$(CONFIG_VIDEO_HI847) += hi847.o +obj-$(CONFIG_VIDEO_I2C) += video-i2c.o +obj-$(CONFIG_VIDEO_IMX208) += imx208.o +obj-$(CONFIG_VIDEO_IMX214) += imx214.o +obj-$(CONFIG_VIDEO_IMX219) += imx219.o +obj-$(CONFIG_VIDEO_IMX258) += imx258.o +obj-$(CONFIG_VIDEO_IMX274) += imx274.o +obj-$(CONFIG_VIDEO_IMX290) += imx290.o +obj-$(CONFIG_VIDEO_IMX319) += imx319.o +obj-$(CONFIG_VIDEO_IMX334) += imx334.o +obj-$(CONFIG_VIDEO_IMX335) += imx335.o +obj-$(CONFIG_VIDEO_IMX355) += imx355.o +obj-$(CONFIG_VIDEO_IMX412) += imx412.o +obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o +obj-$(CONFIG_VIDEO_ISL7998X) += isl7998x.o +obj-$(CONFIG_VIDEO_KS0127) += ks0127.o +obj-$(CONFIG_VIDEO_LM3560) += lm3560.o +obj-$(CONFIG_VIDEO_LM3646) += lm3646.o obj-$(CONFIG_VIDEO_M52790) += m52790.o -obj-$(CONFIG_VIDEO_TLV320AIC23B) += tlv320aic23b.o -obj-$(CONFIG_VIDEO_UDA1342) += uda1342.o -obj-$(CONFIG_VIDEO_WM8775) += wm8775.o -obj-$(CONFIG_VIDEO_WM8739) += wm8739.o -obj-$(CONFIG_VIDEO_VP27SMPX) += vp27smpx.o -obj-$(CONFIG_VIDEO_SONY_BTF_MPX) += sony-btf-mpx.o -obj-$(CONFIG_VIDEO_UPD64031A) += upd64031a.o -obj-$(CONFIG_VIDEO_UPD64083) += upd64083.o +obj-$(CONFIG_VIDEO_M5MOLS) += m5mols/ +obj-$(CONFIG_VIDEO_MAX9271_LIB) += max9271.o +obj-$(CONFIG_VIDEO_MAX9286) += max9286.o +obj-$(CONFIG_VIDEO_ML86V7667) += ml86v7667.o +obj-$(CONFIG_VIDEO_MSP3400) += msp3400.o +obj-$(CONFIG_VIDEO_MT9M001) += mt9m001.o +obj-$(CONFIG_VIDEO_MT9M032) += mt9m032.o +obj-$(CONFIG_VIDEO_MT9M111) += mt9m111.o +obj-$(CONFIG_VIDEO_MT9P031) += mt9p031.o +obj-$(CONFIG_VIDEO_MT9T001) += mt9t001.o +obj-$(CONFIG_VIDEO_MT9T112) += mt9t112.o +obj-$(CONFIG_VIDEO_MT9V011) += mt9v011.o +obj-$(CONFIG_VIDEO_MT9V032) += mt9v032.o +obj-$(CONFIG_VIDEO_MT9V111) += mt9v111.o +obj-$(CONFIG_VIDEO_NOON010PC30) += noon010pc30.o +obj-$(CONFIG_VIDEO_OG01A1B) += og01a1b.o obj-$(CONFIG_VIDEO_OV02A10) += ov02a10.o +obj-$(CONFIG_VIDEO_OV08D10) += ov08d10.o +obj-$(CONFIG_VIDEO_OV13858) += ov13858.o +obj-$(CONFIG_VIDEO_OV13B10) += ov13b10.o obj-$(CONFIG_VIDEO_OV2640) += ov2640.o +obj-$(CONFIG_VIDEO_OV2659) += ov2659.o obj-$(CONFIG_VIDEO_OV2680) += ov2680.o obj-$(CONFIG_VIDEO_OV2685) += ov2685.o obj-$(CONFIG_VIDEO_OV2740) += ov2740.o @@ -89,51 +98,46 @@ obj-$(CONFIG_VIDEO_OV9282) += ov9282.o obj-$(CONFIG_VIDEO_OV9640) += ov9640.o obj-$(CONFIG_VIDEO_OV9650) += ov9650.o obj-$(CONFIG_VIDEO_OV9734) += ov9734.o -obj-$(CONFIG_VIDEO_OV13858) += ov13858.o -obj-$(CONFIG_VIDEO_OV13B10) += ov13b10.o -obj-$(CONFIG_VIDEO_MT9M001) += mt9m001.o -obj-$(CONFIG_VIDEO_MT9M032) += mt9m032.o -obj-$(CONFIG_VIDEO_MT9M111) += mt9m111.o -obj-$(CONFIG_VIDEO_MT9P031) += mt9p031.o -obj-$(CONFIG_VIDEO_MT9T001) += mt9t001.o -obj-$(CONFIG_VIDEO_MT9T112) += mt9t112.o -obj-$(CONFIG_VIDEO_MT9V011) += mt9v011.o -obj-$(CONFIG_VIDEO_MT9V032) += mt9v032.o -obj-$(CONFIG_VIDEO_MT9V111) += mt9v111.o -obj-$(CONFIG_VIDEO_SR030PC30) += sr030pc30.o -obj-$(CONFIG_VIDEO_NOON010PC30) += noon010pc30.o -obj-$(CONFIG_VIDEO_RJ54N1) += rj54n1cb0c.o -obj-$(CONFIG_VIDEO_S5K6AA) += s5k6aa.o -obj-$(CONFIG_VIDEO_S5K6A3) += s5k6a3.o -obj-$(CONFIG_VIDEO_S5K4ECGX) += s5k4ecgx.o -obj-$(CONFIG_VIDEO_S5K5BAF) += s5k5baf.o -obj-$(CONFIG_VIDEO_S5C73M3) += s5c73m3/ -obj-$(CONFIG_VIDEO_ADP1653) += adp1653.o -obj-$(CONFIG_VIDEO_LM3560) += lm3560.o -obj-$(CONFIG_VIDEO_LM3646) += lm3646.o -obj-$(CONFIG_VIDEO_CCS_PLL) += ccs-pll.o -obj-$(CONFIG_VIDEO_AK881X) += ak881x.o -obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o -obj-$(CONFIG_VIDEO_I2C) += video-i2c.o -obj-$(CONFIG_VIDEO_ML86V7667) += ml86v7667.o -obj-$(CONFIG_VIDEO_OV2659) += ov2659.o -obj-$(CONFIG_VIDEO_TC358743) += tc358743.o -obj-$(CONFIG_VIDEO_HI556) += hi556.o -obj-$(CONFIG_VIDEO_HI846) += hi846.o -obj-$(CONFIG_VIDEO_IMX208) += imx208.o -obj-$(CONFIG_VIDEO_IMX214) += imx214.o -obj-$(CONFIG_VIDEO_IMX219) += imx219.o -obj-$(CONFIG_VIDEO_IMX258) += imx258.o -obj-$(CONFIG_VIDEO_IMX274) += imx274.o -obj-$(CONFIG_VIDEO_IMX290) += imx290.o -obj-$(CONFIG_VIDEO_IMX319) += imx319.o -obj-$(CONFIG_VIDEO_IMX334) += imx334.o -obj-$(CONFIG_VIDEO_IMX335) += imx335.o -obj-$(CONFIG_VIDEO_IMX355) += imx355.o -obj-$(CONFIG_VIDEO_IMX412) += imx412.o -obj-$(CONFIG_VIDEO_MAX9286) += max9286.o -obj-$(CONFIG_VIDEO_MAX9271_LIB) += max9271.o -obj-$(CONFIG_VIDEO_RDACM20) += rdacm20.o -obj-$(CONFIG_VIDEO_RDACM21) += rdacm21.o +obj-$(CONFIG_VIDEO_RDACM20) += rdacm20.o +obj-$(CONFIG_VIDEO_RDACM21) += rdacm21.o +obj-$(CONFIG_VIDEO_RJ54N1) += rj54n1cb0c.o +obj-$(CONFIG_VIDEO_S5C73M3) += s5c73m3/ +obj-$(CONFIG_VIDEO_S5K4ECGX) += s5k4ecgx.o +obj-$(CONFIG_VIDEO_S5K5BAF) += s5k5baf.o +obj-$(CONFIG_VIDEO_S5K6A3) += s5k6a3.o +obj-$(CONFIG_VIDEO_S5K6AA) += s5k6aa.o +obj-$(CONFIG_VIDEO_SAA6588) += saa6588.o +obj-$(CONFIG_VIDEO_SAA6752HS) += saa6752hs.o +obj-$(CONFIG_VIDEO_SAA7110) += saa7110.o +obj-$(CONFIG_VIDEO_SAA711X) += saa7115.o +obj-$(CONFIG_VIDEO_SAA7127) += saa7127.o +obj-$(CONFIG_VIDEO_SAA717X) += saa717x.o +obj-$(CONFIG_VIDEO_SAA7185) += saa7185.o +obj-$(CONFIG_VIDEO_SONY_BTF_MPX) += sony-btf-mpx.o +obj-$(CONFIG_VIDEO_SR030PC30) += sr030pc30.o obj-$(CONFIG_VIDEO_ST_MIPID02) += st-mipid02.o -obj-$(CONFIG_SDR_MAX2175) += max2175.o +obj-$(CONFIG_VIDEO_TC358743) += tc358743.o +obj-$(CONFIG_VIDEO_TDA1997X) += tda1997x.o +obj-$(CONFIG_VIDEO_TDA7432) += tda7432.o +obj-$(CONFIG_VIDEO_TDA9840) += tda9840.o +obj-$(CONFIG_VIDEO_TEA6415C) += tea6415c.o +obj-$(CONFIG_VIDEO_TEA6420) += tea6420.o +obj-$(CONFIG_VIDEO_THS7303) += ths7303.o +obj-$(CONFIG_VIDEO_THS8200) += ths8200.o +obj-$(CONFIG_VIDEO_TLV320AIC23B) += tlv320aic23b.o +obj-$(CONFIG_VIDEO_TVAUDIO) += tvaudio.o +obj-$(CONFIG_VIDEO_TVP514X) += tvp514x.o +obj-$(CONFIG_VIDEO_TVP5150) += tvp5150.o +obj-$(CONFIG_VIDEO_TVP7002) += tvp7002.o +obj-$(CONFIG_VIDEO_TW2804) += tw2804.o +obj-$(CONFIG_VIDEO_TW9903) += tw9903.o +obj-$(CONFIG_VIDEO_TW9906) += tw9906.o +obj-$(CONFIG_VIDEO_TW9910) += tw9910.o +obj-$(CONFIG_VIDEO_UDA1342) += uda1342.o +obj-$(CONFIG_VIDEO_UPD64031A) += upd64031a.o +obj-$(CONFIG_VIDEO_UPD64083) += upd64083.o +obj-$(CONFIG_VIDEO_VP27SMPX) += vp27smpx.o +obj-$(CONFIG_VIDEO_VPX3220) += vpx3220.o +obj-$(CONFIG_VIDEO_VS6624) += vs6624.o +obj-$(CONFIG_VIDEO_WM8739) += wm8739.o +obj-$(CONFIG_VIDEO_WM8775) += wm8775.o diff --git a/drivers/media/i2c/adv7180.c b/drivers/media/i2c/adv7180.c index d9a99fcfacb1..4f5db195e66d 100644 --- a/drivers/media/i2c/adv7180.c +++ b/drivers/media/i2c/adv7180.c @@ -784,16 +784,16 @@ static int adv7180_get_mbus_config(struct v4l2_subdev *sd, if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { cfg->type = V4L2_MBUS_CSI2_DPHY; - cfg->flags = V4L2_MBUS_CSI2_1_LANE | - V4L2_MBUS_CSI2_CHANNEL_0 | - V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; + cfg->bus.mipi_csi2.num_data_lanes = 1; + cfg->bus.mipi_csi2.flags = 0; } else { /* * The ADV7180 sensor supports BT.601/656 output modes. * The BT.656 is default and not yet configurable by s/w. */ - cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING | - V4L2_MBUS_DATA_ACTIVE_HIGH; + cfg->bus.parallel.flags = V4L2_MBUS_MASTER | + V4L2_MBUS_PCLK_SAMPLE_RISING | + V4L2_MBUS_DATA_ACTIVE_HIGH; cfg->type = V4L2_MBUS_BT656; } diff --git a/drivers/media/i2c/adv7183.c b/drivers/media/i2c/adv7183.c index 92cafdea3f1f..ba746a19fd39 100644 --- a/drivers/media/i2c/adv7183.c +++ b/drivers/media/i2c/adv7183.c @@ -7,7 +7,7 @@ #include <linux/delay.h> #include <linux/errno.h> -#include <linux/gpio.h> +#include <linux/gpio/consumer.h> #include <linux/i2c.h> #include <linux/init.h> #include <linux/module.h> @@ -28,8 +28,8 @@ struct adv7183 { v4l2_std_id std; /* Current set standard */ u32 input; u32 output; - unsigned reset_pin; - unsigned oe_pin; + struct gpio_desc *reset_pin; + struct gpio_desc *oe_pin; struct v4l2_mbus_framefmt fmt; }; @@ -465,9 +465,9 @@ static int adv7183_s_stream(struct v4l2_subdev *sd, int enable) struct adv7183 *decoder = to_adv7183(sd); if (enable) - gpio_set_value(decoder->oe_pin, 0); + gpiod_set_value(decoder->oe_pin, 1); else - gpio_set_value(decoder->oe_pin, 1); + gpiod_set_value(decoder->oe_pin, 0); udelay(1); return 0; } @@ -531,7 +531,6 @@ static int adv7183_probe(struct i2c_client *client, struct v4l2_subdev_format fmt = { .which = V4L2_SUBDEV_FORMAT_ACTIVE, }; - const unsigned *pin_array; /* Check if the adapter supports the needed features */ if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) @@ -540,29 +539,28 @@ static int adv7183_probe(struct i2c_client *client, v4l_info(client, "chip found @ 0x%02x (%s)\n", client->addr << 1, client->adapter->name); - pin_array = client->dev.platform_data; - if (pin_array == NULL) - return -EINVAL; - decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL); if (decoder == NULL) return -ENOMEM; - decoder->reset_pin = pin_array[0]; - decoder->oe_pin = pin_array[1]; - - if (devm_gpio_request_one(&client->dev, decoder->reset_pin, - GPIOF_OUT_INIT_LOW, "ADV7183 Reset")) { - v4l_err(client, "failed to request GPIO %d\n", decoder->reset_pin); - return -EBUSY; - } - - if (devm_gpio_request_one(&client->dev, decoder->oe_pin, - GPIOF_OUT_INIT_HIGH, - "ADV7183 Output Enable")) { - v4l_err(client, "failed to request GPIO %d\n", decoder->oe_pin); - return -EBUSY; - } + /* + * Requesting high will assert reset, the line should be + * flagged as active low in descriptor table or machine description. + */ + decoder->reset_pin = devm_gpiod_get(&client->dev, "reset", + GPIOD_OUT_HIGH); + if (IS_ERR(decoder->reset_pin)) + return PTR_ERR(decoder->reset_pin); + gpiod_set_consumer_name(decoder->reset_pin, "ADV7183 Reset"); + /* + * Requesting low will start with output disabled, the line should be + * flagged as active low in descriptor table or machine description. + */ + decoder->oe_pin = devm_gpiod_get(&client->dev, "oe", + GPIOD_OUT_LOW); + if (IS_ERR(decoder->oe_pin)) + return PTR_ERR(decoder->oe_pin); + gpiod_set_consumer_name(decoder->reset_pin, "ADV7183 Output Enable"); sd = &decoder->sd; v4l2_i2c_subdev_init(sd, client, &adv7183_ops); @@ -594,7 +592,8 @@ static int adv7183_probe(struct i2c_client *client, /* reset chip */ /* reset pulse width at least 5ms */ mdelay(10); - gpio_set_value(decoder->reset_pin, 1); + /* De-assert reset line (descriptor tagged active low) */ + gpiod_set_value(decoder->reset_pin, 0); /* wait 5ms before any further i2c writes are performed */ mdelay(5); diff --git a/drivers/media/i2c/adv748x/adv748x-csi2.c b/drivers/media/i2c/adv748x/adv748x-csi2.c index 589e9644fcdc..bd4f3fe0e309 100644 --- a/drivers/media/i2c/adv748x/adv748x-csi2.c +++ b/drivers/media/i2c/adv748x/adv748x-csi2.c @@ -222,23 +222,7 @@ static int adv748x_csi2_get_mbus_config(struct v4l2_subdev *sd, unsigned int pad return -EINVAL; config->type = V4L2_MBUS_CSI2_DPHY; - switch (tx->active_lanes) { - case 1: - config->flags = V4L2_MBUS_CSI2_1_LANE; - break; - - case 2: - config->flags = V4L2_MBUS_CSI2_2_LANE; - break; - - case 3: - config->flags = V4L2_MBUS_CSI2_3_LANE; - break; - - case 4: - config->flags = V4L2_MBUS_CSI2_4_LANE; - break; - } + config->bus.mipi_csi2.num_data_lanes = tx->active_lanes; return 0; } diff --git a/drivers/media/i2c/adv7511-v4l2.c b/drivers/media/i2c/adv7511-v4l2.c index 8e13cae40ec5..202e0cd83f90 100644 --- a/drivers/media/i2c/adv7511-v4l2.c +++ b/drivers/media/i2c/adv7511-v4l2.c @@ -17,7 +17,6 @@ #include <linux/i2c.h> #include <linux/delay.h> #include <linux/videodev2.h> -#include <linux/gpio.h> #include <linux/workqueue.h> #include <linux/hdmi.h> #include <linux/v4l2-dv-timings.h> @@ -522,7 +521,7 @@ static void log_infoframe(struct v4l2_subdev *sd, const struct adv7511_cfg_read_ buffer[3] = 0; buffer[3] = hdmi_infoframe_checksum(buffer, len + 4); - if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) < 0) { + if (hdmi_infoframe_unpack(&frame, buffer, len + 4) < 0) { v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc); return; } diff --git a/drivers/media/i2c/adv7604.c b/drivers/media/i2c/adv7604.c index a2fa408d2d9f..bb0c8fc6d383 100644 --- a/drivers/media/i2c/adv7604.c +++ b/drivers/media/i2c/adv7604.c @@ -2484,7 +2484,7 @@ static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index, buffer[i + 3] = infoframe_read(sd, adv76xx_cri[index].payload_addr + i); - if (hdmi_infoframe_unpack(frame, buffer, sizeof(buffer)) < 0) { + if (hdmi_infoframe_unpack(frame, buffer, len + 3) < 0) { v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, adv76xx_cri[index].desc); return -ENOENT; diff --git a/drivers/media/i2c/adv7842.c b/drivers/media/i2c/adv7842.c index 9d6eed0f8281..22caa070273b 100644 --- a/drivers/media/i2c/adv7842.c +++ b/drivers/media/i2c/adv7842.c @@ -2583,7 +2583,7 @@ static void log_infoframe(struct v4l2_subdev *sd, const struct adv7842_cfg_read_ for (i = 0; i < len; i++) buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i); - if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) < 0) { + if (hdmi_infoframe_unpack(&frame, buffer, len + 3) < 0) { v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc); return; } diff --git a/drivers/media/i2c/ccs/Kconfig b/drivers/media/i2c/ccs/Kconfig index 59f35b33ddc1..71671db3d993 100644 --- a/drivers/media/i2c/ccs/Kconfig +++ b/drivers/media/i2c/ccs/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only config VIDEO_CCS tristate "MIPI CCS/SMIA++/SMIA sensor support" - depends on I2C && VIDEO_V4L2 && HAVE_CLK + depends on I2C && VIDEO_DEV && HAVE_CLK select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select VIDEO_CCS_PLL diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 9158d3ce45c0..03e841b8443f 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -17,7 +17,6 @@ #include <linux/delay.h> #include <linux/device.h> #include <linux/firmware.h> -#include <linux/gpio.h> #include <linux/gpio/consumer.h> #include <linux/module.h> #include <linux/pm_runtime.h> diff --git a/drivers/media/i2c/cx25840/Kconfig b/drivers/media/i2c/cx25840/Kconfig index e392f8e023f6..46f15702cf55 100644 --- a/drivers/media/i2c/cx25840/Kconfig +++ b/drivers/media/i2c/cx25840/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only config VIDEO_CX25840 tristate "Conexant CX2584x audio/video decoders" - depends on VIDEO_V4L2 && I2C + depends on VIDEO_DEV && I2C help Support for the Conexant CX2584x audio/video decoders. diff --git a/drivers/media/i2c/dw9714.c b/drivers/media/i2c/dw9714.c index 3863dfeb8293..cd7008ad8f2f 100644 --- a/drivers/media/i2c/dw9714.c +++ b/drivers/media/i2c/dw9714.c @@ -5,6 +5,7 @@ #include <linux/i2c.h> #include <linux/module.h> #include <linux/pm_runtime.h> +#include <linux/regulator/consumer.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> #include <media/v4l2-event.h> @@ -36,6 +37,7 @@ struct dw9714_device { struct v4l2_ctrl_handler ctrls_vcm; struct v4l2_subdev sd; u16 current_val; + struct regulator *vcc; }; static inline struct dw9714_device *to_dw9714_vcm(struct v4l2_ctrl *ctrl) @@ -145,6 +147,16 @@ static int dw9714_probe(struct i2c_client *client) if (dw9714_dev == NULL) return -ENOMEM; + dw9714_dev->vcc = devm_regulator_get(&client->dev, "vcc"); + if (IS_ERR(dw9714_dev->vcc)) + return PTR_ERR(dw9714_dev->vcc); + + rval = regulator_enable(dw9714_dev->vcc); + if (rval < 0) { + dev_err(&client->dev, "failed to enable vcc: %d\n", rval); + return rval; + } + v4l2_i2c_subdev_init(&dw9714_dev->sd, client, &dw9714_ops); dw9714_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; @@ -181,8 +193,18 @@ static int dw9714_remove(struct i2c_client *client) { struct v4l2_subdev *sd = i2c_get_clientdata(client); struct dw9714_device *dw9714_dev = sd_to_dw9714_vcm(sd); + int ret; pm_runtime_disable(&client->dev); + if (!pm_runtime_status_suspended(&client->dev)) { + ret = regulator_disable(dw9714_dev->vcc); + if (ret) { + dev_err(&client->dev, + "Failed to disable vcc: %d\n", ret); + return ret; + } + } + pm_runtime_set_suspended(&client->dev); dw9714_subdev_cleanup(dw9714_dev); return 0; @@ -200,6 +222,9 @@ static int __maybe_unused dw9714_vcm_suspend(struct device *dev) struct dw9714_device *dw9714_dev = sd_to_dw9714_vcm(sd); int ret, val; + if (pm_runtime_suspended(&client->dev)) + return 0; + for (val = dw9714_dev->current_val & ~(DW9714_CTRL_STEPS - 1); val >= 0; val -= DW9714_CTRL_STEPS) { ret = dw9714_i2c_write(client, @@ -208,7 +233,12 @@ static int __maybe_unused dw9714_vcm_suspend(struct device *dev) dev_err_once(dev, "%s I2C failure: %d", __func__, ret); usleep_range(DW9714_CTRL_DELAY_US, DW9714_CTRL_DELAY_US + 10); } - return 0; + + ret = regulator_disable(dw9714_dev->vcc); + if (ret) + dev_err(dev, "Failed to disable vcc: %d\n", ret); + + return ret; } /* @@ -224,6 +254,16 @@ static int __maybe_unused dw9714_vcm_resume(struct device *dev) struct dw9714_device *dw9714_dev = sd_to_dw9714_vcm(sd); int ret, val; + if (pm_runtime_suspended(&client->dev)) + return 0; + + ret = regulator_enable(dw9714_dev->vcc); + if (ret) { + dev_err(dev, "Failed to enable vcc: %d\n", ret); + return ret; + } + usleep_range(1000, 2000); + for (val = dw9714_dev->current_val % DW9714_CTRL_STEPS; val < dw9714_dev->current_val + DW9714_CTRL_STEPS - 1; val += DW9714_CTRL_STEPS) { diff --git a/drivers/media/i2c/et8ek8/Kconfig b/drivers/media/i2c/et8ek8/Kconfig index afcc4ea764f6..398dd4d21df1 100644 --- a/drivers/media/i2c/et8ek8/Kconfig +++ b/drivers/media/i2c/et8ek8/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only config VIDEO_ET8EK8 tristate "ET8EK8 camera sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_FWNODE diff --git a/drivers/media/i2c/hi847.c b/drivers/media/i2c/hi847.c new file mode 100644 index 000000000000..7e85349e1852 --- /dev/null +++ b/drivers/media/i2c/hi847.c @@ -0,0 +1,3012 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2022 Intel Corporation. + +#include <asm/unaligned.h> +#include <linux/acpi.h> +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/pm_runtime.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-device.h> +#include <media/v4l2-fwnode.h> + +#define HI847_REG_VALUE_08BIT 1 +#define HI847_REG_VALUE_16BIT 2 +#define HI847_REG_VALUE_24BIT 3 + +#define HI847_LINK_FREQ_400MHZ 400000000ULL +#define HI847_LINK_FREQ_200MHZ 200000000ULL +#define HI847_SCLK 72000000ULL +#define HI847_MCLK 19200000 +#define HI847_DATA_LANES 4 +#define HI847_RGB_DEPTH 10 + +#define HI847_REG_CHIP_ID 0x0716 +#define HI847_CHIP_ID 0x0847 + +#define HI847_REG_MODE_SELECT 0x0B00 +#define HI847_MODE_STANDBY 0x0000 +#define HI847_MODE_STREAMING 0x0100 + +#define HI847_REG_MODE_TG 0x027E +#define HI847_REG_MODE_TG_ENABLE 0x0100 +#define HI847_REG_MODE_TG_DISABLE 0x0000 + +/* vertical-timings from sensor */ +#define HI847_REG_FLL 0x020E +#define HI847_FLL_30FPS 0x0B51 +#define HI847_FLL_30FPS_MIN 0x0B51 +#define HI847_FLL_60FPS 0x05A9 +#define HI847_FLL_60FPS_MIN 0x05A9 +#define HI847_FLL_MAX 0x7fff + +/* horizontal-timings from sensor */ +#define HI847_REG_LLP 0x0206 + +/* Exposure controls from sensor */ +#define HI847_REG_EXPOSURE 0x020A +#define HI847_EXPOSURE_MIN 4 +#define HI847_EXPOSURE_MAX_MARGIN 4 +#define HI847_EXPOSURE_STEP 1 + +/* Analog gain controls from sensor */ +#define HI847_REG_ANALOG_GAIN 0x0212 +#define HI847_ANAL_GAIN_MIN 0 +#define HI847_ANAL_GAIN_MAX 240 +#define HI847_ANAL_GAIN_STEP 1 + +/* Digital gain controls from sensor */ +#define HI847_REG_MWB_GR_GAIN 0x0214 +#define HI847_REG_MWB_GB_GAIN 0x0216 +#define HI847_REG_MWB_R_GAIN 0x0218 +#define HI847_REG_MWB_B_GAIN 0x021A +#define HI847_DGTL_GAIN_MIN 1 +#define HI847_DGTL_GAIN_MAX 8191 +#define HI847_DGTL_GAIN_STEP 1 +#define HI847_DGTL_GAIN_DEFAULT 512 + +/* Test Pattern Control */ +#define HI847_REG_ISP 0X0B04 +#define HI847_REG_ISP_TPG_EN 0x0001 +#define HI847_REG_TEST_PATTERN 0x0C0A + +/* Flip Mirror Controls from sensor */ +#define HI847_REG_MIRROR_FLIP 0x0202 + +#define HI847_REG_FORMAT_X 0x0F04 +#define HI847_REG_FORMAT_Y 0x0F06 + +enum { + HI847_LINK_FREQ_400MHZ_INDEX, + HI847_LINK_FREQ_200MHZ_INDEX, +}; + +struct hi847_reg { + u16 address; + u16 val; +}; + +struct hi847_reg_list { + u32 num_of_regs; + const struct hi847_reg *regs; +}; + +struct hi847_link_freq_config { + const struct hi847_reg_list reg_list; +}; + +struct hi847_mode { + /* Frame width in pixels */ + u32 width; + + /* Frame height in pixels */ + u32 height; + + /* Horizontal timining size */ + u32 llp; + + /* Default vertical timining size */ + u32 fll_def; + + /* Min vertical timining size */ + u32 fll_min; + + /* Link frequency needed for this resolution */ + u32 link_freq_index; + + /* Sensor register settings for this resolution */ + const struct hi847_reg_list reg_list; +}; + +#define to_hi847(_sd) container_of(_sd, struct hi847, sd) + +//SENSOR_INITIALIZATION +static const struct hi847_reg mipi_data_rate_lane_4[] = { + {0x0790, 0x0100}, + {0x2000, 0x0000}, + {0x2002, 0x0058}, + {0x2006, 0x40B2}, + {0x2008, 0xB05C}, + {0x200A, 0x8446}, + {0x200C, 0x40B2}, + {0x200E, 0xB082}, + {0x2010, 0x8450}, + {0x2012, 0x40B2}, + {0x2014, 0xB0AE}, + {0x2016, 0x84C6}, + {0x2018, 0x40B2}, + {0x201A, 0xB11A}, + {0x201C, 0x84BC}, + {0x201E, 0x40B2}, + {0x2020, 0xB34A}, + {0x2022, 0x84B4}, + {0x2024, 0x40B2}, + {0x2026, 0xB386}, + {0x2028, 0x84B0}, + {0x202A, 0x40B2}, + {0x202C, 0xB3B4}, + {0x202E, 0x84B8}, + {0x2030, 0x40B2}, + {0x2032, 0xB0F4}, + {0x2034, 0x8470}, + {0x2036, 0x40B2}, + {0x2038, 0xB3EA}, + {0x203A, 0x847C}, + {0x203C, 0x40B2}, + {0x203E, 0xB658}, + {0x2040, 0x8478}, + {0x2042, 0x40B2}, + {0x2044, 0xB67E}, + {0x2046, 0x847E}, + {0x2048, 0x40B2}, + {0x204A, 0xB78E}, + {0x204C, 0x843A}, + {0x204E, 0x40B2}, + {0x2050, 0xB980}, + {0x2052, 0x845C}, + {0x2054, 0x40B2}, + {0x2056, 0xB9B0}, + {0x2058, 0x845E}, + {0x205A, 0x4130}, + {0x205C, 0x1292}, + {0x205E, 0xD016}, + {0x2060, 0xB3D2}, + {0x2062, 0x0B00}, + {0x2064, 0x2002}, + {0x2066, 0xD2E2}, + {0x2068, 0x0381}, + {0x206A, 0x93C2}, + {0x206C, 0x0263}, + {0x206E, 0x2001}, + {0x2070, 0x4130}, + {0x2072, 0x422D}, + {0x2074, 0x403E}, + {0x2076, 0x888E}, + {0x2078, 0x403F}, + {0x207A, 0x192A}, + {0x207C, 0x1292}, + {0x207E, 0x843E}, + {0x2080, 0x3FF7}, + {0x2082, 0x422D}, + {0x2084, 0x403E}, + {0x2086, 0x192A}, + {0x2088, 0x403F}, + {0x208A, 0x888E}, + {0x208C, 0x1292}, + {0x208E, 0x843E}, + {0x2090, 0xB3D2}, + {0x2092, 0x0267}, + {0x2094, 0x2403}, + {0x2096, 0xD0F2}, + {0x2098, 0x0040}, + {0x209A, 0x0381}, + {0x209C, 0x90F2}, + {0x209E, 0x0010}, + {0x20A0, 0x0260}, + {0x20A2, 0x2002}, + {0x20A4, 0x1292}, + {0x20A6, 0x84BC}, + {0x20A8, 0x1292}, + {0x20AA, 0xD020}, + {0x20AC, 0x4130}, + {0x20AE, 0x1292}, + {0x20B0, 0x8470}, + {0x20B2, 0x1292}, + {0x20B4, 0x8452}, + {0x20B6, 0x0900}, + {0x20B8, 0x7118}, + {0x20BA, 0x1292}, + {0x20BC, 0x848E}, + {0x20BE, 0x0900}, + {0x20C0, 0x7112}, + {0x20C2, 0x0800}, + {0x20C4, 0x7A20}, + {0x20C6, 0x4292}, + {0x20C8, 0x87DE}, + {0x20CA, 0x7334}, + {0x20CC, 0x0F00}, + {0x20CE, 0x7304}, + {0x20D0, 0x421F}, + {0x20D2, 0x8718}, + {0x20D4, 0x1292}, + {0x20D6, 0x846E}, + {0x20D8, 0x1292}, + {0x20DA, 0x8488}, + {0x20DC, 0x0B00}, + {0x20DE, 0x7114}, + {0x20E0, 0x0002}, + {0x20E2, 0x1292}, + {0x20E4, 0x848C}, + {0x20E6, 0x1292}, + {0x20E8, 0x8454}, + {0x20EA, 0x43C2}, + {0x20EC, 0x86EE}, + {0x20EE, 0x1292}, + {0x20F0, 0x8444}, + {0x20F2, 0x4130}, + {0x20F4, 0x4392}, + {0x20F6, 0x7360}, + {0x20F8, 0xB3D2}, + {0x20FA, 0x0B00}, + {0x20FC, 0x2402}, + {0x20FE, 0xC2E2}, + {0x2100, 0x0381}, + {0x2102, 0x0900}, + {0x2104, 0x732C}, + {0x2106, 0x4382}, + {0x2108, 0x7360}, + {0x210A, 0x422D}, + {0x210C, 0x403E}, + {0x210E, 0x87F0}, + {0x2110, 0x403F}, + {0x2112, 0x87E8}, + {0x2114, 0x1292}, + {0x2116, 0x843E}, + {0x2118, 0x4130}, + {0x211A, 0x120B}, + {0x211C, 0x120A}, + {0x211E, 0x4392}, + {0x2120, 0x87FA}, + {0x2122, 0x4392}, + {0x2124, 0x760E}, + {0x2126, 0x0900}, + {0x2128, 0x760C}, + {0x212A, 0x421B}, + {0x212C, 0x760A}, + {0x212E, 0x903B}, + {0x2130, 0x0201}, + {0x2132, 0x2408}, + {0x2134, 0x903B}, + {0x2136, 0x0102}, + {0x2138, 0x2405}, + {0x213A, 0x4292}, + {0x213C, 0x030A}, + {0x213E, 0x87F8}, + {0x2140, 0x1292}, + {0x2142, 0x849A}, + {0x2144, 0x903B}, + {0x2146, 0x0020}, + {0x2148, 0x2010}, + {0x214A, 0x403B}, + {0x214C, 0x8498}, + {0x214E, 0x422F}, + {0x2150, 0x12AB}, + {0x2152, 0x403F}, + {0x2154, 0x0028}, + {0x2156, 0x12AB}, + {0x2158, 0x403B}, + {0x215A, 0x84C4}, + {0x215C, 0x407F}, + {0x215E, 0xFFAA}, + {0x2160, 0x12AB}, + {0x2162, 0x407F}, + {0x2164, 0x0055}, + {0x2166, 0x12AB}, + {0x2168, 0x3FDC}, + {0x216A, 0x903B}, + {0x216C, 0x0021}, + {0x216E, 0x2890}, + {0x2170, 0x903B}, + {0x2172, 0x0100}, + {0x2174, 0x200D}, + {0x2176, 0x403F}, + {0x2178, 0x0028}, + {0x217A, 0x1292}, + {0x217C, 0x8498}, + {0x217E, 0x425F}, + {0x2180, 0x0306}, + {0x2182, 0x1292}, + {0x2184, 0x84C4}, + {0x2186, 0x4FC2}, + {0x2188, 0x0318}, + {0x218A, 0x0261}, + {0x218C, 0x0000}, + {0x218E, 0x3FC9}, + {0x2190, 0x903B}, + {0x2192, 0x0101}, + {0x2194, 0x2858}, + {0x2196, 0x903B}, + {0x2198, 0x0200}, + {0x219A, 0x2450}, + {0x219C, 0x903B}, + {0x219E, 0x0201}, + {0x21A0, 0x2C47}, + {0x21A2, 0x903B}, + {0x21A4, 0x0102}, + {0x21A6, 0x2041}, + {0x21A8, 0x93E2}, + {0x21AA, 0x0262}, + {0x21AC, 0x240A}, + {0x21AE, 0x425F}, + {0x21B0, 0x0306}, + {0x21B2, 0x1292}, + {0x21B4, 0x84C4}, + {0x21B6, 0x4F4E}, + {0x21B8, 0x4EC2}, + {0x21BA, 0x0318}, + {0x21BC, 0x0260}, + {0x21BE, 0x0000}, + {0x21C0, 0x3FB0}, + {0x21C2, 0x403A}, + {0x21C4, 0x8030}, + {0x21C6, 0x4382}, + {0x21C8, 0x0326}, + {0x21CA, 0x4382}, + {0x21CC, 0x0328}, + {0x21CE, 0x421B}, + {0x21D0, 0x030C}, + {0x21D2, 0x930B}, + {0x21D4, 0x2420}, + {0x21D6, 0x4A5F}, + {0x21D8, 0x0001}, + {0x21DA, 0x1292}, + {0x21DC, 0x84C4}, + {0x21DE, 0x4F4E}, + {0x21E0, 0x4A5F}, + {0x21E2, 0x0001}, + {0x21E4, 0x9F0E}, + {0x21E6, 0x2402}, + {0x21E8, 0x5392}, + {0x21EA, 0x0326}, + {0x21EC, 0x4ECA}, + {0x21EE, 0x0001}, + {0x21F0, 0x533B}, + {0x21F2, 0x2411}, + {0x21F4, 0x4A6F}, + {0x21F6, 0x1292}, + {0x21F8, 0x84C4}, + {0x21FA, 0x4F4E}, + {0x21FC, 0x4A6F}, + {0x21FE, 0x9F0E}, + {0x2200, 0x2402}, + {0x2202, 0x5392}, + {0x2204, 0x0326}, + {0x2206, 0x4ECA}, + {0x2208, 0x0000}, + {0x220A, 0x533B}, + {0x220C, 0x532A}, + {0x220E, 0x0260}, + {0x2210, 0x0000}, + {0x2212, 0x930B}, + {0x2214, 0x23E0}, + {0x2216, 0x40B2}, + {0x2218, 0xAA55}, + {0x221A, 0x0328}, + {0x221C, 0xB0F2}, + {0x221E, 0x0040}, + {0x2220, 0x0381}, + {0x2222, 0x277F}, + {0x2224, 0xD3D2}, + {0x2226, 0x0267}, + {0x2228, 0x3F7C}, + {0x222A, 0x0261}, + {0x222C, 0x0000}, + {0x222E, 0x3F79}, + {0x2230, 0x903B}, + {0x2232, 0x0201}, + {0x2234, 0x23FA}, + {0x2236, 0x1292}, + {0x2238, 0x84C0}, + {0x223A, 0x3F73}, + {0x223C, 0x1292}, + {0x223E, 0x84C0}, + {0x2240, 0x0261}, + {0x2242, 0x0000}, + {0x2244, 0x3F6E}, + {0x2246, 0x903B}, + {0x2248, 0x0040}, + {0x224A, 0x2018}, + {0x224C, 0x422F}, + {0x224E, 0x1292}, + {0x2250, 0x8498}, + {0x2252, 0x12B0}, + {0x2254, 0xF0EA}, + {0x2256, 0x907F}, + {0x2258, 0xFFAA}, + {0x225A, 0x240D}, + {0x225C, 0x5392}, + {0x225E, 0x0312}, + {0x2260, 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0x0619}, + {0x296A, 0x2B46}, + {0x296C, 0x50F2}, + {0x296E, 0xFFF0}, + {0x2970, 0x0619}, + {0x2972, 0x3F42}, + {0x2974, 0x5031}, + {0x2976, 0x000C}, + {0x2978, 0x4139}, + {0x297A, 0x413A}, + {0x297C, 0x413B}, + {0x297E, 0x4130}, + {0x2980, 0x0900}, + {0x2982, 0x7312}, + {0x2984, 0x421F}, + {0x2986, 0x0A08}, + {0x2988, 0xF03F}, + {0x298A, 0xF7FF}, + {0x298C, 0x4F82}, + {0x298E, 0x0A88}, + {0x2990, 0x0900}, + {0x2992, 0x7312}, + {0x2994, 0x421F}, + {0x2996, 0x0A0E}, + {0x2998, 0xF03F}, + {0x299A, 0x7FFF}, + {0x299C, 0x4F82}, + {0x299E, 0x0A8E}, + {0x29A0, 0x0900}, + {0x29A2, 0x7312}, + {0x29A4, 0x421F}, + {0x29A6, 0x0A1E}, + {0x29A8, 0xC31F}, + {0x29AA, 0x4F82}, + {0x29AC, 0x0A9E}, + {0x29AE, 0x4130}, + {0x29B0, 0x4292}, + {0x29B2, 0x0A08}, + {0x29B4, 0x0A88}, + {0x29B6, 0x0900}, + {0x29B8, 0x7312}, + {0x29BA, 0x4292}, + {0x29BC, 0x0A0E}, + {0x29BE, 0x0A8E}, + {0x29C0, 0x0900}, + {0x29C2, 0x7312}, + {0x29C4, 0x4292}, + {0x29C6, 0x0A1E}, + {0x29C8, 0x0A9E}, + {0x29CA, 0x4130}, + {0x29CC, 0x7400}, + {0x29CE, 0x8058}, + {0x29D0, 0x1807}, + {0x29D2, 0x00E0}, + {0x29D4, 0x7002}, + {0x29D6, 0x17C7}, + {0x29D8, 0x0045}, + {0x29DA, 0x0006}, + {0x29DC, 0x17CC}, + {0x29DE, 0x0015}, + {0x29E0, 0x1512}, + {0x29E2, 0x216F}, + {0x29E4, 0x005B}, + {0x29E6, 0x005D}, + {0x29E8, 0x00DE}, + {0x29EA, 0x00DD}, + {0x29EC, 0x5023}, + {0x29EE, 0x00DE}, + {0x29F0, 0x005B}, + {0x29F2, 0x0410}, + {0x29F4, 0x0091}, + {0x29F6, 0x0015}, + {0x29F8, 0x0040}, + {0x29FA, 0x7023}, + {0x29FC, 0x1653}, + {0x29FE, 0x0156}, + {0x2A00, 0x0001}, + {0x2A02, 0x2081}, + {0x2A04, 0x7020}, + {0x2A06, 0x2F99}, + {0x2A08, 0x005C}, + {0x2A0A, 0x0000}, + {0x2A0C, 0x5040}, + {0x2A0E, 0x0045}, + {0x2A10, 0x213A}, + {0x2A12, 0x0303}, + {0x2A14, 0x0148}, + {0x2A16, 0x0049}, + {0x2A18, 0x0045}, + {0x2A1A, 0x0046}, + {0x2A1C, 0x05DD}, + {0x2A1E, 0x00DE}, + {0x2A20, 0x00DD}, + {0x2A22, 0x00DC}, + {0x2A24, 0x00DE}, + {0x2A26, 0x04D6}, + {0x2A28, 0x2014}, + {0x2A2A, 0x2081}, + {0x2A2C, 0x7087}, + {0x2A2E, 0x2F99}, + {0x2A30, 0x005C}, + {0x2A32, 0x0002}, + {0x2A34, 0x5060}, + {0x2A36, 0x31C0}, + {0x2A38, 0x2122}, + {0x2A3A, 0x7800}, + {0x2A3C, 0xC08C}, + {0x2A3E, 0x0001}, + {0x2A40, 0x9038}, + {0x2A42, 0x59F7}, + {0x2A44, 0x907A}, + {0x2A46, 0x03D8}, + {0x2A48, 0x8D90}, + {0x2A4A, 0x01C0}, + {0x2A4C, 0x7400}, + {0x2A4E, 0x8058}, + {0x2A50, 0x1807}, + {0x2A52, 0x00E0}, + {0x2A54, 0x7002}, + {0x2A56, 0x17C7}, + {0x2A58, 0x0045}, + {0x2A5A, 0x0006}, + {0x2A5C, 0x17CC}, + {0x2A5E, 0x0015}, + {0x2A60, 0x1512}, + {0x2A62, 0x216F}, + {0x2A64, 0x005B}, + {0x2A66, 0x005D}, + {0x2A68, 0x00DE}, + {0x2A6A, 0x00DD}, + {0x2A6C, 0x5023}, + {0x2A6E, 0x00DE}, + {0x2A70, 0x005B}, + {0x2A72, 0x0410}, + {0x2A74, 0x0091}, + {0x2A76, 0x0015}, + {0x2A78, 0x0040}, + {0x2A7A, 0x7023}, + {0x2A7C, 0x1653}, + {0x2A7E, 0x0156}, + {0x2A80, 0x0001}, + {0x2A82, 0x2081}, + {0x2A84, 0x7020}, + {0x2A86, 0x2F99}, + {0x2A88, 0x005C}, + {0x2A8A, 0x0000}, + {0x2A8C, 0x5040}, + {0x2A8E, 0x0045}, + {0x2A90, 0x213A}, + {0x2A92, 0x0303}, + {0x2A94, 0x0148}, + {0x2A96, 0x0049}, + {0x2A98, 0x0045}, + {0x2A9A, 0x0046}, + {0x2A9C, 0x05DD}, + {0x2A9E, 0x00DE}, + {0x2AA0, 0x00DD}, + {0x2AA2, 0x00DC}, + {0x2AA4, 0x00DE}, + {0x2AA6, 0x0296}, + {0x2AA8, 0x2014}, + {0x2AAA, 0x2081}, + {0x2AAC, 0x7087}, + {0x2AAE, 0x2F99}, + {0x2AB0, 0x005C}, + {0x2AB2, 0x0002}, + {0x2AB4, 0x5060}, + {0x2AB6, 0x31C0}, + {0x2AB8, 0x2122}, + {0x2ABA, 0x7800}, + {0x2ABC, 0xC08C}, + {0x2ABE, 0x0001}, + {0x2AC0, 0x9038}, + {0x2AC2, 0x59F7}, + {0x2AC4, 0x907A}, + {0x2AC6, 0x03D8}, + {0x2AC8, 0x8D90}, + {0x2ACA, 0x01C0}, + {0x2ACC, 0x7400}, + {0x2ACE, 0x2002}, + {0x2AD0, 0x70DF}, + {0x2AD2, 0x2F21}, + {0x2AD4, 0x04C1}, + {0x2AD6, 0x0D80}, + {0x2AD8, 0x7800}, + {0x2ADA, 0x0041}, + {0x2ADC, 0x7400}, + {0x2ADE, 0x2004}, + {0x2AE0, 0x70DF}, + {0x2AE2, 0x2F21}, + {0x2AE4, 0x04C2}, + {0x2AE6, 0x0D80}, + {0x2AE8, 0x7800}, + {0x2AEA, 0x7400}, + {0x2AEC, 0x2008}, + {0x2AEE, 0x70DF}, + {0x2AF0, 0x2F21}, + {0x2AF2, 0x04C3}, + {0x2AF4, 0x0D80}, + {0x2AF6, 0x7800}, + {0x2AF8, 0x7400}, + {0x2AFA, 0x0004}, + {0x2AFC, 0x70DF}, + {0x2AFE, 0x2F22}, + {0x2B00, 0x7008}, + {0x2B02, 0x2F1F}, + {0x2B04, 0x7021}, + {0x2B06, 0x2F01}, + {0x2B08, 0x7800}, + {0x2B0A, 0x7400}, + {0x2B0C, 0x0002}, + {0x2B0E, 0x70DF}, + {0x2B10, 0x3F5F}, + {0x2B12, 0x703A}, + {0x2B14, 0x2F01}, + {0x2B16, 0x7800}, + {0x2B18, 0x7400}, + {0x2B1A, 0x2010}, + {0x2B1C, 0x70DF}, + {0x2B1E, 0x3F40}, + {0x2B20, 0x700A}, + {0x2B22, 0x0FC0}, + {0x2B24, 0x7800}, + {0x2B26, 0x7400}, + {0x2B28, 0x2004}, + {0x2B2A, 0x70DF}, + {0x2B2C, 0x2F21}, + {0x2B2E, 0x04C2}, + {0x2B30, 0x0D80}, + {0x2B32, 0x7800}, + {0x2B34, 0x0041}, + {0x2B36, 0x7400}, + {0x2B38, 0x2002}, + {0x2B3A, 0x70DF}, + {0x2B3C, 0x2F22}, + {0x2B3E, 0x04C1}, + {0x2B40, 0x0D80}, + {0x2B42, 0x7800}, + {0x2B44, 0x7400}, + {0x2B46, 0x0001}, + {0x2B48, 0x70DF}, + {0x2B4A, 0x3F5F}, + {0x2B4C, 0x703A}, + {0x2B4E, 0x2F01}, + {0x2B50, 0x7800}, + {0x2B52, 0x7400}, + {0x2B54, 0x200A}, + {0x2B56, 0x70DF}, + {0x2B58, 0x3F40}, + {0x2B5A, 0x700A}, + {0x2B5C, 0x0FC0}, + {0x2B5E, 0x7800}, + {0x2B60, 0x7400}, + {0x2B62, 0x2015}, + {0x2B64, 0x70DF}, + {0x2B66, 0x3F5F}, + {0x2B68, 0x703A}, + {0x2B6A, 0x2F01}, + {0x2B6C, 0x7800}, + {0x2B6E, 0x7400}, + {0x2B70, 0x7800}, + {0x2B72, 0x007F}, + {0x2B74, 0x0000}, + {0x2B76, 0xB9CC}, + {0x2B78, 0x0000}, + {0x2B7A, 0xB9CC}, + {0x2B7C, 0xBA3C}, + {0x2B7E, 0x0002}, + {0x2B80, 0x0000}, + {0x2B82, 0xBA4C}, + {0x2B84, 0x0000}, + {0x2B86, 0xBA4C}, + {0x2B88, 0xBABC}, + {0x2B8A, 0x0002}, + {0x2B8C, 0x0063}, + {0x2B8E, 0xBB26}, + {0x2B90, 0x0063}, + {0x2B92, 0xBB36}, + {0x2B94, 0x0063}, + {0x2B96, 0xBAEA}, + {0x2B98, 0x0063}, + {0x2B9A, 0xBAF8}, + {0x2B9C, 0xBADA}, + {0x2B9E, 0x0004}, + {0x2BA0, 0x0063}, + {0x2BA2, 0xBAEA}, + {0x2BA4, 0x0063}, + {0x2BA6, 0xBB18}, + {0x2BA8, 0x0063}, + {0x2BAA, 0xBB26}, + {0x2BAC, 0x0063}, + {0x2BAE, 0xBB44}, + {0x2BB0, 0xBADA}, + {0x2BB2, 0x0004}, + {0x2BB4, 0x0063}, + {0x2BB6, 0xBACC}, + {0x2BB8, 0x0063}, + {0x2BBA, 0xBADC}, + {0x2BBC, 0x0063}, + {0x2BBE, 0xBAEA}, + {0x2BC0, 0x0063}, + {0x2BC2, 0xBAF8}, + {0x2BC4, 0xBADA}, + {0x2BC6, 0x0004}, + {0x2BC8, 0x0063}, + {0x2BCA, 0xBAEA}, + {0x2BCC, 0x0063}, + {0x2BCE, 0xBB18}, + {0x2BD0, 0x0063}, + {0x2BD2, 0xBACC}, + {0x2BD4, 0x0063}, + {0x2BD6, 0xBB0A}, + {0x2BD8, 0xBADA}, + {0x2BDA, 0x0004}, + {0x2BDC, 0x0063}, + {0x2BDE, 0xBACC}, + {0x2BE0, 0x0063}, + {0x2BE2, 0xBADC}, + {0x2BE4, 0x0063}, + {0x2BE6, 0xBAEA}, + {0x2BE8, 0x0063}, + {0x2BEA, 0xBB18}, + {0x2BEC, 0xBADA}, + {0x2BEE, 0x0004}, + {0x2BF0, 0xFFFF}, + {0x2BF2, 0xBB6E}, + {0x2BF4, 0x0000}, + {0x2BF6, 0x0000}, + {0x2BF8, 0x0000}, + {0x2BFA, 0x0000}, + {0x2BFC, 0x0000}, + {0x2BFE, 0x0000}, + {0x2C00, 0xBB72}, + {0x2C02, 0x0001}, + {0x2C04, 0x0063}, + {0x2C06, 0xBB52}, + {0x2C08, 0x0063}, + {0x2C0A, 0xBB60}, + {0x2C0C, 0x0000}, + {0x2C0E, 0x0000}, + {0x2C10, 0x0000}, + {0x2C12, 0x0000}, + {0x2C14, 0xBADA}, + {0x2C16, 0x0002}, + {0x2C18, 0x0066}, + {0x2C1A, 0x0067}, + {0x2C1C, 0x00AF}, + {0x2C1E, 0x01CF}, + {0x2C20, 0x0087}, + {0x2C22, 0x0083}, + {0x2C24, 0x011B}, + {0x2C26, 0x035A}, + {0x2C28, 0x00FA}, + {0x2C2A, 0x00F2}, + {0x2C2C, 0x00A6}, + {0x2C2E, 0x00A4}, + {0x2C30, 0xFFFF}, + {0x2C32, 0x002C}, + {0x2C34, 0x0058}, + {0x2C36, 0x0000}, + {0x2C38, 0x0000}, + {0x2C3A, 0xBC18}, + {0x2C3C, 0xBB74}, + {0x2C3E, 0xBB80}, + {0x2C40, 0xBC32}, + {0x2C42, 0xBB8C}, + {0x2C44, 0xBBA0}, + {0x2C46, 0xBB8C}, + {0x2C48, 0xBBA0}, + {0x2C4A, 0xBC04}, + {0x2C4C, 0xBC04}, + {0x2C4E, 0xBBF0}, + {0x2C50, 0xBBF0}, + {0x2C52, 0xBBB4}, + {0x2C54, 0xBBC8}, + {0x2C56, 0xBBB4}, + {0x2C58, 0xBBC8}, + {0x2C5A, 0xBC04}, + {0x2C5C, 0xBC04}, + {0x2C5E, 0xBBF0}, + {0x2C60, 0xBBF0}, + {0x2C62, 0xBB8C}, + {0x2C64, 0xBBA0}, + {0x2C66, 0xBB8C}, + {0x2C68, 0xBBA0}, + {0x2C6A, 0xBC04}, + {0x2C6C, 0xBC04}, + {0x2C6E, 0xBBF0}, + {0x2C70, 0xBBF0}, + {0x2C72, 0xBBB4}, + {0x2C74, 0xBBC8}, + {0x2C76, 0xBBB4}, + {0x2C78, 0xBBC8}, + {0x2C7A, 0xBC04}, + {0x2C7C, 0xBC04}, + {0x2C7E, 0xBBF0}, + {0x2C80, 0xBBF0}, + {0x3800, 0x880E}, + {0x3802, 0xBC62}, + {0x3804, 0xBC40}, + {0x3806, 0xD13E}, + {0x3808, 0xBC42}, + {0x380A, 0xBC3C}, + {0x380C, 0x0000}, + {0x380E, 0x0040}, + {0x3810, 0x0040}, + {0x3812, 0x0040}, + {0x3814, 0x0043}, + {0x3816, 0x0046}, + {0x3818, 0x004B}, + {0x381A, 0x004D}, + {0x381C, 0x0051}, + {0x381E, 0x0055}, + {0x3820, 0x005A}, + {0x3822, 0x005E}, + {0x3824, 0x0062}, + {0x3826, 0x0067}, + {0x3828, 0x006C}, + {0x382A, 0x0070}, + {0x382C, 0x0078}, + {0x382E, 0x0086}, + {0x3830, 0x0090}, + {0x3832, 0x0096}, + {0x3834, 0x009D}, + {0x3836, 0x00A5}, + {0x3838, 0x00AD}, + {0x383A, 0x00B4}, + {0x383C, 0x00B9}, + {0x383E, 0x00BE}, + {0x3840, 0x00C3}, + {0x3842, 0x00C8}, + {0x3844, 0x00CD}, + {0x3846, 0x00D2}, + {0x3848, 0x00D7}, + {0x384A, 0x00DC}, + {0x384C, 0x00DC}, + {0x384E, 0x0000}, + {0x3850, 0x0000}, + {0x3852, 0x0000}, + {0x3854, 0x0000}, + {0x3856, 0x0000}, + {0x3858, 0x0000}, + {0x385A, 0x0000}, + {0x385C, 0x0000}, + {0x385E, 0x0000}, + {0x3860, 0x0000}, + {0x3862, 0x0000}, + {0x3864, 0x0000}, + {0x3866, 0x0000}, + {0x3868, 0x0000}, + {0x386A, 0x0000}, + {0x386C, 0x0000}, + {0x386E, 0x0000}, + {0x3870, 0x0000}, + {0x3872, 0x0000}, + {0x3874, 0x0000}, + {0x3876, 0x0000}, + {0x3878, 0x0000}, + {0x387A, 0x0000}, + {0x387C, 0x0000}, + {0x387E, 0x0000}, + {0x3880, 0x0000}, + {0x3882, 0x0000}, + {0x3884, 0x0000}, + {0x3886, 0x0000}, + {0x3888, 0x0000}, + {0x388A, 0x0000}, + {0x388C, 0x0000}, + {0x026A, 0xFFFF}, + {0x026C, 0x00FF}, + {0x026E, 0x0000}, + {0x0360, 0x1E8E}, + {0x040E, 0x01EB}, + {0x0600, 0x1130}, + {0x0602, 0x3112}, + {0x0604, 0x8048}, + {0x0606, 0x00E9}, + {0x067A, 0x0404}, + {0x067C, 0x0404}, + {0x06A8, 0x0240}, + {0x06AA, 0x00CA}, + {0x06AC, 0x0041}, + {0x06B4, 0x3FFF}, + {0x06DE, 0x0404}, + {0x06E0, 0x0404}, + {0x06E2, 0xFF00}, + {0x06E4, 0x8333}, + {0x06E6, 0x8333}, + {0x06E8, 0x8333}, + {0x06EA, 0x8333}, + {0x052A, 0x0000}, + {0x052C, 0x0000}, + {0x0F06, 0x0002}, + {0x0A04, 0xB4C5}, + {0x0A06, 0xC400}, + {0x0A08, 0x988A}, + {0x0A0A, 0xA387}, + {0x0A0E, 0xEEC0}, + {0x0A12, 0x0000}, + {0x0A18, 0x0010}, + {0x0A1C, 0x0040}, + {0x0A20, 0x0015}, + {0x0C00, 0x0021}, + {0x0C16, 0x0002}, + {0x0708, 0x6FC0}, + {0x070C, 0x0000}, + {0x120C, 0x1428}, + {0x121A, 0x0000}, + {0x121C, 0x1896}, + {0x121E, 0x0032}, + {0x1220, 0x0000}, + {0x1222, 0x96FF}, + {0x1244, 0x0000}, + {0x105C, 0x0F0B}, + {0x1958, 0x0000}, + {0x195A, 0x004C}, + {0x195C, 0x0097}, + {0x195E, 0x0221}, + {0x1960, 0x03FE}, + {0x1980, 0x00E0}, + {0x1982, 0x0010}, + {0x1984, 0x2018}, + {0x1986, 0x0008}, + {0x1988, 0x0000}, + {0x198A, 0x0000}, + {0x198C, 0x0880}, + {0x198E, 0x0000}, + {0x1990, 0x1A00}, + {0x1992, 0x0000}, + {0x1994, 0x2800}, + {0x1996, 0x0002}, + {0x1962, 0x0000}, + {0x1964, 0x004C}, + {0x1966, 0x0097}, + {0x1968, 0x0221}, + {0x196A, 0x03FE}, + {0x19C0, 0x00E0}, + {0x19C2, 0x0010}, + {0x19C4, 0x2018}, + {0x19C6, 0x0008}, + {0x19C8, 0x0000}, + {0x19CA, 0x0000}, + {0x19CC, 0x0880}, + {0x19CE, 0x0000}, + {0x19D0, 0x1A00}, + {0x19D2, 0x0000}, + {0x19D4, 0x2800}, + {0x19D6, 0x0002}, + {0x196C, 0x0000}, + {0x196E, 0x004C}, + {0x1970, 0x0097}, + {0x1972, 0x0221}, + {0x1974, 0x03FE}, + {0x1A00, 0x00E0}, + {0x1A02, 0x0010}, + {0x1A04, 0x2018}, + {0x1A06, 0x0008}, + {0x1A08, 0x0000}, + {0x1A0A, 0x0000}, + {0x1A0C, 0x0880}, + {0x1A0E, 0x0000}, + {0x1A10, 0x1A00}, + {0x1A12, 0x0000}, + {0x1A14, 0x2800}, + {0x1A16, 0x0002}, + {0x1976, 0x0000}, + {0x1978, 0x004C}, + {0x197A, 0x0097}, + {0x197C, 0x0221}, + {0x197E, 0x03FE}, + {0x1A40, 0x00E0}, + {0x1A42, 0x0010}, + {0x1A44, 0x2018}, + {0x1A46, 0x0008}, + {0x1A48, 0x0000}, + {0x1A4A, 0x0000}, + {0x1A4C, 0x0880}, + {0x1A4E, 0x0000}, + {0x1A50, 0x1A00}, + {0x1A52, 0x0000}, + {0x1A54, 0x2800}, + {0x1A56, 0x0002}, + {0x192A, 0x0201}, + {0x0384, 0x0001}, + {0x027E, 0x0100}, +}; + +static const struct hi847_reg mode_3264x2448_regs[] = { + {0x0B00, 0x0000}, + {0x0204, 0x0000}, + {0x0206, 0x033C}, + {0x020A, 0x0B4D}, + {0x020E, 0x0B51}, + {0x0214, 0x0200}, + {0x0216, 0x0200}, + {0x0218, 0x0200}, + {0x021A, 0x0200}, + {0x0224, 0x002E}, + {0x022A, 0x0017}, + {0x022C, 0x0E1F}, + {0x022E, 0x09C1}, + {0x0234, 0x1111}, + {0x0236, 0x1111}, + {0x0238, 0x1111}, + {0x023A, 0x1111}, + {0x0250, 0x0000}, + {0x0252, 0x0006}, + {0x0254, 0x0000}, + {0x0256, 0x0000}, + {0x0258, 0x0000}, + {0x025A, 0x0000}, + {0x025C, 0x0000}, + {0x025E, 0x0202}, + {0x0268, 0x00CD}, + {0x0440, 0x0002}, + {0x0F00, 0x0000}, + {0x0F04, 0x0008}, + {0x0F06, 0x0002}, + {0x0B02, 0x0100}, + {0x0B04, 0x00DC}, + {0x0B12, 0x0CC0}, + {0x0B14, 0x0990}, + {0x0B20, 0x0100}, + {0x1100, 0x1100}, + {0x1102, 0x0008}, + {0x1108, 0x0202}, + {0x1118, 0x0000}, + {0x0A10, 0xB040}, + {0x0C14, 0x0008}, + {0x0C18, 0x0CC0}, + {0x0C1A, 0x0990}, + {0x0730, 0x0001}, + {0x0732, 0x0000}, + {0x0734, 0x0300}, + {0x0736, 0x004B}, + {0x0738, 0x0001}, + {0x073C, 0x0900}, + {0x0740, 0x0000}, + {0x0742, 0x0000}, + {0x0744, 0x0300}, + {0x0746, 0x007D}, + {0x0748, 0x0002}, + {0x074A, 0x0900}, + {0x074C, 0x0000}, + {0x074E, 0x0100}, + {0x0750, 0x0000}, + {0x1200, 0x0946}, + {0x1202, 0x1A00}, + {0x120E, 0x6027}, + {0x1210, 0x8027}, + {0x1246, 0x0105}, + {0x1000, 0x0300}, + {0x1002, 0xC311}, + {0x1004, 0x2BB0}, + {0x1010, 0x087B}, + {0x1012, 0x0040}, + {0x1014, 0x0020}, + {0x1016, 0x0020}, + {0x101A, 0x0020}, + {0x1020, 0xC107}, + {0x1022, 0x081E}, + {0x1024, 0x0509}, + {0x1026, 0x0B0A}, + {0x1028, 0x1409}, + {0x102A, 0x0B05}, + {0x102C, 0x1400}, + {0x1038, 0x0000}, + {0x103E, 0x0001}, + {0x1040, 0x0000}, + {0x1042, 0x0008}, + {0x1044, 0x0120}, + {0x1046, 0x01B0}, + {0x1048, 0x0090}, + {0x1066, 0x089C}, + {0x1600, 0x0000}, + {0x1608, 0x0028}, + {0x160A, 0x0C80}, + {0x160C, 0x001A}, + {0x160E, 0x0960}, + {0x0252, 0x0009}, + {0x0202, 0x0000}, +}; + +static const struct hi847_reg mode_1632x1224_regs[] = { + {0x0B00, 0x0000}, + {0x0204, 0x0200}, + {0x0206, 0x033C}, + {0x020A, 0x05A5}, + {0x020E, 0x05A9}, + {0x0214, 0x0200}, + {0x0216, 0x0200}, + {0x0218, 0x0200}, + {0x021A, 0x0200}, + {0x0224, 0x002C}, + {0x022A, 0x0015}, + {0x022C, 0x0E2D}, + {0x022E, 0x09C1}, + {0x0234, 0x3311}, + {0x0236, 0x3311}, + {0x0238, 0x3311}, + {0x023A, 0x2222}, + {0x0250, 0x0000}, + {0x0252, 0x0006}, + {0x0254, 0x0000}, + {0x0256, 0x0000}, + {0x0258, 0x0000}, + {0x025A, 0x0000}, + {0x025C, 0x0000}, + {0x025E, 0x0202}, + {0x0268, 0x00CD}, + {0x0440, 0x0002}, + {0x0F00, 0x0400}, + {0x0F04, 0x0004}, + {0x0F06, 0x0002}, + {0x0B02, 0x0100}, + {0x0B04, 0x00FC}, + {0x0B12, 0x0660}, + {0x0B14, 0x04C8}, + {0x0B20, 0x0200}, + {0x1100, 0x1100}, + {0x1102, 0x0008}, + {0x1108, 0x0402}, + {0x1118, 0x0000}, + {0x0A10, 0xB060}, + {0x0C14, 0x0008}, + {0x0C18, 0x0CC0}, + {0x0C1A, 0x04C8}, + {0x0730, 0x0001}, + {0x0732, 0x0000}, + {0x0734, 0x0300}, + {0x0736, 0x004B}, + {0x0738, 0x0001}, + {0x073C, 0x0900}, + {0x0740, 0x0000}, + {0x0742, 0x0000}, + {0x0744, 0x0300}, + {0x0746, 0x007D}, + {0x0748, 0x0002}, + {0x074A, 0x0900}, + {0x074C, 0x0100}, + {0x074E, 0x0100}, + {0x0750, 0x0000}, + {0x1200, 0x0946}, + {0x1202, 0x1A00}, + {0x120E, 0x6027}, + {0x1210, 0x8027}, + {0x1246, 0x0105}, + {0x1000, 0x0300}, + {0x1002, 0xC311}, + {0x1004, 0x2BB0}, + {0x1010, 0x042B}, + {0x1012, 0x0012}, + {0x1014, 0x0020}, + {0x1016, 0x0020}, + {0x101A, 0x0020}, + {0x1020, 0xC103}, + {0x1022, 0x040F}, + {0x1024, 0x0304}, + {0x1026, 0x0607}, + {0x1028, 0x0D06}, + {0x102A, 0x0605}, + {0x102C, 0x0C00}, + {0x1038, 0x0000}, + {0x103E, 0x0101}, + {0x1040, 0x0000}, + {0x1042, 0x0008}, + {0x1044, 0x0120}, + {0x1046, 0x01B0}, + {0x1048, 0x0090}, + {0x1066, 0x043B}, + {0x1600, 0x0400}, + {0x1608, 0x0028}, + {0x160A, 0x0C80}, + {0x160C, 0x001A}, + {0x160E, 0x0960}, + {0x0252, 0x0009}, + {0x0202, 0x0000}, +}; + +static const char * const hi847_test_pattern_menu[] = { + "No Pattern", + "Solid Colour", + "100% Colour Bars", + "Fade To Grey Colour Bars", + "PN9", + "Horizontal Gradient Pattern", + "Vertical Gradient Pattern", + "Check Board", + "Slant Pattern", +}; + +static const s64 link_freq_menu_items[] = { + HI847_LINK_FREQ_400MHZ, + HI847_LINK_FREQ_200MHZ, +}; + +static const struct hi847_link_freq_config link_freq_configs[] = { + [HI847_LINK_FREQ_400MHZ_INDEX] = { + .reg_list = { + .num_of_regs = ARRAY_SIZE(mipi_data_rate_lane_4), + .regs = mipi_data_rate_lane_4, + } + }, + [HI847_LINK_FREQ_200MHZ_INDEX] = { + .reg_list = { + .num_of_regs = ARRAY_SIZE(mipi_data_rate_lane_4), + .regs = mipi_data_rate_lane_4, + } + } +}; + +static const struct hi847_mode supported_modes[] = { + { + .width = 3264, + .height = 2448, + .fll_def = HI847_FLL_30FPS, + .fll_min = HI847_FLL_30FPS_MIN, + .llp = 0x033C, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mode_3264x2448_regs), + .regs = mode_3264x2448_regs, + }, + .link_freq_index = HI847_LINK_FREQ_400MHZ_INDEX, + }, + { + .width = 1632, + .height = 1224, + .fll_def = HI847_FLL_60FPS, + .fll_min = HI847_FLL_60FPS_MIN, + .llp = 0x033C, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mode_1632x1224_regs), + .regs = mode_1632x1224_regs, + }, + .link_freq_index = HI847_LINK_FREQ_200MHZ_INDEX, + } +}; + +struct hi847 { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_ctrl_handler ctrl_handler; + + /* V4L2 Controls */ + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *vblank; + struct v4l2_ctrl *hblank; + struct v4l2_ctrl *exposure; + struct v4l2_ctrl *vflip; + struct v4l2_ctrl *hflip; + + /* Current mode */ + const struct hi847_mode *cur_mode; + + /* To serialize asynchronus callbacks */ + struct mutex mutex; + + /* Streaming on/off */ + bool streaming; +}; + +static u64 to_pixel_rate(u32 f_index) +{ + u64 pixel_rate = link_freq_menu_items[f_index] * 2 * HI847_DATA_LANES; + + do_div(pixel_rate, HI847_RGB_DEPTH); + + return pixel_rate; +} + +static int hi847_read_reg(struct hi847 *hi847, u16 reg, u16 len, u32 *val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&hi847->sd); + struct i2c_msg msgs[2]; + u8 addr_buf[2]; + u8 data_buf[4] = {0}; + int ret; + + if (len > 4) + return -EINVAL; + + put_unaligned_be16(reg, addr_buf); + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = sizeof(addr_buf); + msgs[0].buf = addr_buf; + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = len; + msgs[1].buf = &data_buf[4 - len]; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) + return -EIO; + + *val = get_unaligned_be32(data_buf); + + return 0; +} + +static int hi847_write_reg(struct hi847 *hi847, u16 reg, u16 len, u32 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&hi847->sd); + u8 buf[6]; + + if (len > 4) + return -EINVAL; + + put_unaligned_be16(reg, buf); + put_unaligned_be32(val << 8 * (4 - len), buf + 2); + if (i2c_master_send(client, buf, len + 2) != len + 2) + return -EIO; + + return 0; +} + +static int hi847_write_reg_list(struct hi847 *hi847, + const struct hi847_reg_list *r_list) +{ + struct i2c_client *client = v4l2_get_subdevdata(&hi847->sd); + unsigned int i; + int ret; + + for (i = 0; i < r_list->num_of_regs; i++) { + ret = hi847_write_reg(hi847, r_list->regs[i].address, + HI847_REG_VALUE_16BIT, + r_list->regs[i].val); + if (ret) { + dev_err_ratelimited(&client->dev, + "failed to write reg 0x%4.4x. error = %d", + r_list->regs[i].address, ret); + return ret; + } + } + + return 0; +} + +static int hi847_update_digital_gain(struct hi847 *hi847, u32 d_gain) +{ + int ret; + + ret = hi847_write_reg(hi847, HI847_REG_MWB_GR_GAIN, + HI847_REG_VALUE_16BIT, d_gain); + if (ret) + return ret; + + ret = hi847_write_reg(hi847, HI847_REG_MWB_GB_GAIN, + HI847_REG_VALUE_16BIT, d_gain); + if (ret) + return ret; + + ret = hi847_write_reg(hi847, HI847_REG_MWB_R_GAIN, + HI847_REG_VALUE_16BIT, d_gain); + if (ret) + return ret; + + return hi847_write_reg(hi847, HI847_REG_MWB_B_GAIN, + HI847_REG_VALUE_16BIT, d_gain); +} + +static int hi847_test_pattern(struct hi847 *hi847, u32 pattern) +{ + int ret; + u32 val; + + if (pattern) { + ret = hi847_read_reg(hi847, HI847_REG_ISP, + HI847_REG_VALUE_16BIT, &val); + if (ret) + return ret; + + ret = hi847_write_reg(hi847, HI847_REG_ISP, + HI847_REG_VALUE_16BIT, + val | HI847_REG_ISP_TPG_EN); + if (ret) + return ret; + } + + ret = hi847_read_reg(hi847, HI847_REG_TEST_PATTERN, + HI847_REG_VALUE_16BIT, &val); + if (ret) + return ret; + + return hi847_write_reg(hi847, HI847_REG_TEST_PATTERN, + HI847_REG_VALUE_16BIT, val | pattern << 8); +} + +static int hi847_grbg_shift(struct hi847 *hi847) +{ + int ret; + int hflip, vflip; + + /* regs shift for full size */ + static const u32 FORMAT_X_SHIFT_1[2][2] = { + { 0x0008, 0x0007, }, + { 0x0008, 0x0007, }, + }; + + static const u32 FORMAT_Y_SHIFT_1[2][2] = { + { 0x0002, 0x0002, }, + { 0x0001, 0x0001, }, + }; + + /* regs shift for binning size */ + static const u32 FORMAT_X_SHIFT_2[2][2] = { + { 0x0004, 0x0003, }, + { 0x0004, 0x0003, }, + }; + + static const u32 FORMAT_Y_SHIFT_2[2][2] = { + { 0x0002, 0x0002, }, + { 0x0001, 0x0001, }, + }; + + hflip = hi847->hflip->val; + vflip = hi847->vflip->val; + + if (hi847->cur_mode->width == 3264) { + ret = hi847_write_reg(hi847, HI847_REG_FORMAT_X, + HI847_REG_VALUE_16BIT, + FORMAT_X_SHIFT_1[vflip][hflip]); + if (ret) + return ret; + + return hi847_write_reg(hi847, HI847_REG_FORMAT_Y, + HI847_REG_VALUE_16BIT, + FORMAT_Y_SHIFT_1[vflip][hflip]); + } else { + ret = hi847_write_reg(hi847, HI847_REG_FORMAT_X, + HI847_REG_VALUE_16BIT, + FORMAT_X_SHIFT_2[vflip][hflip]); + if (ret) + return ret; + + return hi847_write_reg(hi847, HI847_REG_FORMAT_Y, + HI847_REG_VALUE_16BIT, + FORMAT_Y_SHIFT_2[vflip][hflip]); + } +} + +static int hi847_set_ctrl_hflip(struct hi847 *hi847, u32 ctrl_val) +{ + int ret; + u32 val; + + ret = hi847_read_reg(hi847, HI847_REG_MIRROR_FLIP, + HI847_REG_VALUE_16BIT, &val); + if (ret) + return ret; + + ret = hi847_grbg_shift(hi847); + if (ret) + return ret; + + return hi847_write_reg(hi847, HI847_REG_MIRROR_FLIP, + HI847_REG_VALUE_16BIT, + ctrl_val ? val | BIT(8) : val & ~BIT(8)); +} + +static int hi847_set_ctrl_vflip(struct hi847 *hi847, u8 ctrl_val) +{ + int ret; + u32 val; + + ret = hi847_read_reg(hi847, HI847_REG_MIRROR_FLIP, + HI847_REG_VALUE_16BIT, &val); + if (ret) + return ret; + + ret = hi847_grbg_shift(hi847); + if (ret) + return ret; + + return hi847_write_reg(hi847, HI847_REG_MIRROR_FLIP, + HI847_REG_VALUE_16BIT, + ctrl_val ? val | BIT(9) : val & ~BIT(9)); +} + +static int hi847_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct hi847 *hi847 = container_of(ctrl->handler, + struct hi847, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&hi847->sd); + s64 exposure_max; + int ret = 0; + + /* Propagate change of current control to all related controls */ + if (ctrl->id == V4L2_CID_VBLANK) { + /* Update max exposure while meeting expected vblanking */ + exposure_max = hi847->cur_mode->height + ctrl->val - + HI847_EXPOSURE_MAX_MARGIN; + __v4l2_ctrl_modify_range(hi847->exposure, + hi847->exposure->minimum, + exposure_max, hi847->exposure->step, + exposure_max); + } + + /* V4L2 controls values will be applied only when power is already up */ + if (!pm_runtime_get_if_in_use(&client->dev)) + return 0; + + switch (ctrl->id) { + case V4L2_CID_ANALOGUE_GAIN: + ret = hi847_write_reg(hi847, HI847_REG_ANALOG_GAIN, + HI847_REG_VALUE_16BIT, ctrl->val); + break; + + case V4L2_CID_DIGITAL_GAIN: + ret = hi847_update_digital_gain(hi847, ctrl->val); + break; + + case V4L2_CID_EXPOSURE: + ret = hi847_write_reg(hi847, HI847_REG_EXPOSURE, + HI847_REG_VALUE_16BIT, ctrl->val); + break; + + case V4L2_CID_VBLANK: + /* Update FLL that meets expected vertical blanking */ + ret = hi847_write_reg(hi847, HI847_REG_FLL, + HI847_REG_VALUE_16BIT, + hi847->cur_mode->height + ctrl->val); + break; + + case V4L2_CID_TEST_PATTERN: + ret = hi847_test_pattern(hi847, ctrl->val); + break; + + case V4L2_CID_HFLIP: + hi847_set_ctrl_hflip(hi847, ctrl->val); + break; + + case V4L2_CID_VFLIP: + hi847_set_ctrl_vflip(hi847, ctrl->val); + break; + + default: + ret = -EINVAL; + break; + } + + pm_runtime_put(&client->dev); + + return ret; +} + +static const struct v4l2_ctrl_ops hi847_ctrl_ops = { + .s_ctrl = hi847_set_ctrl, +}; + +static int hi847_init_controls(struct hi847 *hi847) +{ + struct v4l2_ctrl_handler *ctrl_hdlr; + s64 exposure_max, h_blank; + int ret; + + ctrl_hdlr = &hi847->ctrl_handler; + ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8); + if (ret) + return ret; + + ctrl_hdlr->lock = &hi847->mutex; + hi847->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &hi847_ctrl_ops, + V4L2_CID_LINK_FREQ, + ARRAY_SIZE(link_freq_menu_items) - 1, + 0, link_freq_menu_items); + if (hi847->link_freq) + hi847->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + hi847->pixel_rate = v4l2_ctrl_new_std + (ctrl_hdlr, &hi847_ctrl_ops, + V4L2_CID_PIXEL_RATE, 0, + to_pixel_rate(HI847_LINK_FREQ_400MHZ_INDEX), + 1, + to_pixel_rate(HI847_LINK_FREQ_400MHZ_INDEX)); + hi847->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &hi847_ctrl_ops, + V4L2_CID_VBLANK, + hi847->cur_mode->fll_min - + hi847->cur_mode->height, + HI847_FLL_MAX - + hi847->cur_mode->height, 1, + hi847->cur_mode->fll_def - + hi847->cur_mode->height); + + h_blank = hi847->cur_mode->llp - hi847->cur_mode->width; + + hi847->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &hi847_ctrl_ops, + V4L2_CID_HBLANK, h_blank, h_blank, 1, + h_blank); + if (hi847->hblank) + hi847->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + v4l2_ctrl_new_std(ctrl_hdlr, &hi847_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, + HI847_ANAL_GAIN_MIN, HI847_ANAL_GAIN_MAX, + HI847_ANAL_GAIN_STEP, HI847_ANAL_GAIN_MIN); + v4l2_ctrl_new_std(ctrl_hdlr, &hi847_ctrl_ops, V4L2_CID_DIGITAL_GAIN, + HI847_DGTL_GAIN_MIN, HI847_DGTL_GAIN_MAX, + HI847_DGTL_GAIN_STEP, HI847_DGTL_GAIN_DEFAULT); + exposure_max = hi847->cur_mode->fll_def - HI847_EXPOSURE_MAX_MARGIN; + hi847->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &hi847_ctrl_ops, + V4L2_CID_EXPOSURE, + HI847_EXPOSURE_MIN, exposure_max, + HI847_EXPOSURE_STEP, + exposure_max); + v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &hi847_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(hi847_test_pattern_menu) - 1, + 0, 0, hi847_test_pattern_menu); + hi847->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &hi847_ctrl_ops, + V4L2_CID_HFLIP, 0, 1, 1, 0); + hi847->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &hi847_ctrl_ops, + V4L2_CID_VFLIP, 0, 1, 1, 0); + + if (ctrl_hdlr->error) + return ctrl_hdlr->error; + + hi847->sd.ctrl_handler = ctrl_hdlr; + + return 0; +} + +static void hi847_assign_pad_format(const struct hi847_mode *mode, + struct v4l2_mbus_framefmt *fmt) +{ + fmt->width = mode->width; + fmt->height = mode->height; + fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; + fmt->field = V4L2_FIELD_NONE; +} + +static int hi847_start_streaming(struct hi847 *hi847) +{ + struct i2c_client *client = v4l2_get_subdevdata(&hi847->sd); + const struct hi847_reg_list *reg_list; + int link_freq_index, ret; + + link_freq_index = hi847->cur_mode->link_freq_index; + reg_list = &link_freq_configs[link_freq_index].reg_list; + ret = hi847_write_reg_list(hi847, reg_list); + if (ret) { + dev_err(&client->dev, "failed to set plls"); + return ret; + } + + reg_list = &hi847->cur_mode->reg_list; + ret = hi847_write_reg_list(hi847, reg_list); + if (ret) { + dev_err(&client->dev, "failed to set mode"); + return ret; + } + + ret = __v4l2_ctrl_handler_setup(hi847->sd.ctrl_handler); + if (ret) + return ret; + + ret = hi847_write_reg(hi847, HI847_REG_MODE_TG, + HI847_REG_VALUE_16BIT, HI847_REG_MODE_TG_ENABLE); + + ret = hi847_write_reg(hi847, HI847_REG_MODE_SELECT, + HI847_REG_VALUE_16BIT, HI847_MODE_STREAMING); + + if (ret) { + dev_err(&client->dev, "failed to set stream"); + return ret; + } + + return 0; +} + +static void hi847_stop_streaming(struct hi847 *hi847) +{ + struct i2c_client *client = v4l2_get_subdevdata(&hi847->sd); + + if (hi847_write_reg(hi847, HI847_REG_MODE_TG, + HI847_REG_VALUE_16BIT, HI847_REG_MODE_TG_DISABLE)) + dev_err(&client->dev, "failed to set stream 0x%x", + HI847_REG_MODE_TG); + + if (hi847_write_reg(hi847, HI847_REG_MODE_SELECT, + HI847_REG_VALUE_16BIT, HI847_MODE_STANDBY)) + dev_err(&client->dev, "failed to set stream 0x%x", + HI847_REG_MODE_SELECT); +} + +static int hi847_set_stream(struct v4l2_subdev *sd, int enable) +{ + struct hi847 *hi847 = to_hi847(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (hi847->streaming == enable) + return 0; + + mutex_lock(&hi847->mutex); + if (enable) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + mutex_unlock(&hi847->mutex); + return ret; + } + + ret = hi847_start_streaming(hi847); + if (ret) { + enable = 0; + hi847_stop_streaming(hi847); + pm_runtime_put(&client->dev); + } + } else { + hi847_stop_streaming(hi847); + pm_runtime_put(&client->dev); + } + + hi847->streaming = enable; + mutex_unlock(&hi847->mutex); + + return ret; +} + +static int __maybe_unused hi847_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct hi847 *hi847 = to_hi847(sd); + + mutex_lock(&hi847->mutex); + if (hi847->streaming) + hi847_stop_streaming(hi847); + + mutex_unlock(&hi847->mutex); + + return 0; +} + +static int __maybe_unused hi847_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct hi847 *hi847 = to_hi847(sd); + int ret; + + mutex_lock(&hi847->mutex); + if (hi847->streaming) { + ret = hi847_start_streaming(hi847); + if (ret) + goto error; + } + + mutex_unlock(&hi847->mutex); + + return 0; + +error: + hi847_stop_streaming(hi847); + hi847->streaming = 0; + mutex_unlock(&hi847->mutex); + return ret; +} + +static int hi847_set_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct hi847 *hi847 = to_hi847(sd); + const struct hi847_mode *mode; + s32 vblank_def, h_blank; + + mode = v4l2_find_nearest_size(supported_modes, + ARRAY_SIZE(supported_modes), width, + height, fmt->format.width, + fmt->format.height); + + mutex_lock(&hi847->mutex); + hi847_assign_pad_format(mode, &fmt->format); + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { + *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = + fmt->format; + } else { + hi847->cur_mode = mode; + __v4l2_ctrl_s_ctrl(hi847->link_freq, mode->link_freq_index); + __v4l2_ctrl_s_ctrl_int64(hi847->pixel_rate, + to_pixel_rate(mode->link_freq_index)); + + /* Update limits and set FPS to default */ + vblank_def = mode->fll_def - mode->height; + __v4l2_ctrl_modify_range(hi847->vblank, + mode->fll_min - mode->height, + HI847_FLL_MAX - mode->height, 1, + vblank_def); + __v4l2_ctrl_s_ctrl(hi847->vblank, vblank_def); + + h_blank = hi847->cur_mode->llp - hi847->cur_mode->width; + + __v4l2_ctrl_modify_range(hi847->hblank, h_blank, h_blank, 1, + h_blank); + } + + mutex_unlock(&hi847->mutex); + + return 0; +} + +static int hi847_get_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct hi847 *hi847 = to_hi847(sd); + + mutex_lock(&hi847->mutex); + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) + fmt->format = *v4l2_subdev_get_try_format(&hi847->sd, + sd_state, + fmt->pad); + else + hi847_assign_pad_format(hi847->cur_mode, &fmt->format); + + mutex_unlock(&hi847->mutex); + + return 0; +} + +static int hi847_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index > 0) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_SGRBG10_1X10; + + return 0; +} + +static int hi847_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + if (fse->index >= ARRAY_SIZE(supported_modes)) + return -EINVAL; + + if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) + return -EINVAL; + + fse->min_width = supported_modes[fse->index].width; + fse->max_width = fse->min_width; + fse->min_height = supported_modes[fse->index].height; + fse->max_height = fse->min_height; + + return 0; +} + +static int hi847_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct hi847 *hi847 = to_hi847(sd); + + mutex_lock(&hi847->mutex); + hi847_assign_pad_format(&supported_modes[0], + v4l2_subdev_get_try_format(sd, fh->state, 0)); + mutex_unlock(&hi847->mutex); + + return 0; +} + +static const struct v4l2_subdev_video_ops hi847_video_ops = { + .s_stream = hi847_set_stream, +}; + +static const struct v4l2_subdev_pad_ops hi847_pad_ops = { + .set_fmt = hi847_set_format, + .get_fmt = hi847_get_format, + .enum_mbus_code = hi847_enum_mbus_code, + .enum_frame_size = hi847_enum_frame_size, +}; + +static const struct v4l2_subdev_ops hi847_subdev_ops = { + .video = &hi847_video_ops, + .pad = &hi847_pad_ops, +}; + +static const struct media_entity_operations hi847_subdev_entity_ops = { + .link_validate = v4l2_subdev_link_validate, +}; + +static const struct v4l2_subdev_internal_ops hi847_internal_ops = { + .open = hi847_open, +}; + +static int hi847_identify_module(struct hi847 *hi847) +{ + struct i2c_client *client = v4l2_get_subdevdata(&hi847->sd); + int ret; + u32 val; + + ret = hi847_read_reg(hi847, HI847_REG_CHIP_ID, + HI847_REG_VALUE_16BIT, &val); + if (ret) + return ret; + + if (val != HI847_CHIP_ID) { + dev_err(&client->dev, "chip id mismatch: %x!=%x", + HI847_CHIP_ID, val); + return -ENXIO; + } + + return 0; +} + +static int hi847_check_hwcfg(struct device *dev) +{ + struct fwnode_handle *ep; + struct fwnode_handle *fwnode = dev_fwnode(dev); + struct v4l2_fwnode_endpoint bus_cfg = { + .bus_type = V4L2_MBUS_CSI2_DPHY + }; + u32 mclk; + int ret; + unsigned int i, j; + + if (!fwnode) + return -ENXIO; + + ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk); + if (ret) { + dev_err(dev, "can't get clock frequency"); + return ret; + } + + if (mclk != HI847_MCLK) { + dev_err(dev, "external clock %d is not supported", mclk); + return -EINVAL; + } + + ep = fwnode_graph_get_next_endpoint(fwnode, NULL); + if (!ep) + return -ENXIO; + + ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); + fwnode_handle_put(ep); + if (ret) + return ret; + + if (bus_cfg.bus.mipi_csi2.num_data_lanes != HI847_DATA_LANES) { + dev_err(dev, "number of CSI2 data lanes %d is not supported", + bus_cfg.bus.mipi_csi2.num_data_lanes); + ret = -EINVAL; + goto check_hwcfg_error; + } + + if (!bus_cfg.nr_of_link_frequencies) { + dev_err(dev, "no link frequencies defined"); + ret = -EINVAL; + goto check_hwcfg_error; + } + + for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { + for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { + if (link_freq_menu_items[i] == + bus_cfg.link_frequencies[j]) + break; + } + + if (j == bus_cfg.nr_of_link_frequencies) { + dev_err(dev, "no link frequency %lld supported", + link_freq_menu_items[i]); + ret = -EINVAL; + goto check_hwcfg_error; + } + } + +check_hwcfg_error: + v4l2_fwnode_endpoint_free(&bus_cfg); + + return ret; +} + +static int hi847_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct hi847 *hi847 = to_hi847(sd); + + v4l2_async_unregister_subdev(sd); + media_entity_cleanup(&sd->entity); + v4l2_ctrl_handler_free(sd->ctrl_handler); + pm_runtime_disable(&client->dev); + mutex_destroy(&hi847->mutex); + + return 0; +} + +static int hi847_probe(struct i2c_client *client) +{ + struct hi847 *hi847; + int ret; + + hi847 = devm_kzalloc(&client->dev, sizeof(*hi847), GFP_KERNEL); + if (!hi847) + return -ENOMEM; + + ret = hi847_check_hwcfg(&client->dev); + if (ret) { + dev_err(&client->dev, "failed to get HW configuration: %d", + ret); + return ret; + } + + v4l2_i2c_subdev_init(&hi847->sd, client, &hi847_subdev_ops); + ret = hi847_identify_module(hi847); + if (ret) { + dev_err(&client->dev, "failed to find sensor: %d", ret); + return ret; + } + + mutex_init(&hi847->mutex); + hi847->cur_mode = &supported_modes[0]; + ret = hi847_init_controls(hi847); + if (ret) { + dev_err(&client->dev, "failed to init controls: %d", ret); + goto probe_error_v4l2_ctrl_handler_free; + } + + hi847->sd.internal_ops = &hi847_internal_ops; + hi847->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + hi847->sd.entity.ops = &hi847_subdev_entity_ops; + hi847->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + hi847->pad.flags = MEDIA_PAD_FL_SOURCE; + ret = media_entity_pads_init(&hi847->sd.entity, 1, &hi847->pad); + if (ret) { + dev_err(&client->dev, "failed to init entity pads: %d", ret); + goto probe_error_v4l2_ctrl_handler_free; + } + + ret = v4l2_async_register_subdev_sensor(&hi847->sd); + if (ret < 0) { + dev_err(&client->dev, "failed to register V4L2 subdev: %d", + ret); + goto probe_error_media_entity_cleanup; + } + + pm_runtime_set_active(&client->dev); + pm_runtime_enable(&client->dev); + pm_runtime_idle(&client->dev); + + return 0; + +probe_error_media_entity_cleanup: + media_entity_cleanup(&hi847->sd.entity); + +probe_error_v4l2_ctrl_handler_free: + v4l2_ctrl_handler_free(hi847->sd.ctrl_handler); + mutex_destroy(&hi847->mutex); + + return ret; +} + +static const struct dev_pm_ops hi847_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(hi847_suspend, hi847_resume) +}; + +#ifdef CONFIG_ACPI +static const struct acpi_device_id hi847_acpi_ids[] = { + {"HYV0847"}, + {} +}; + +MODULE_DEVICE_TABLE(acpi, hi847_acpi_ids); +#endif + +static struct i2c_driver hi847_i2c_driver = { + .driver = { + .name = "hi847", + .pm = &hi847_pm_ops, + .acpi_match_table = ACPI_PTR(hi847_acpi_ids), + }, + .probe_new = hi847_probe, + .remove = hi847_remove, +}; + +module_i2c_driver(hi847_i2c_driver); + +MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>"); +MODULE_DESCRIPTION("Hynix HI847 sensor driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/media/i2c/imx274.c b/drivers/media/i2c/imx274.c index 2aa15b9c23cc..7de1f2948e53 100644 --- a/drivers/media/i2c/imx274.c +++ b/drivers/media/i2c/imx274.c @@ -11,13 +11,11 @@ #include <linux/clk.h> #include <linux/delay.h> -#include <linux/gpio.h> #include <linux/gpio/consumer.h> #include <linux/i2c.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/of_gpio.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> diff --git a/drivers/media/i2c/isl7998x.c b/drivers/media/i2c/isl7998x.c new file mode 100644 index 000000000000..dc3068549dfa --- /dev/null +++ b/drivers/media/i2c/isl7998x.c @@ -0,0 +1,1628 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intersil ISL7998x analog to MIPI CSI-2 or BT.656 decoder driver. + * + * Copyright (C) 2018-2019 Marek Vasut <marex@denx.de> + * Copyright (C) 2021 Michael Tretter <kernel@pengutronix.de> + */ + +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/of_graph.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> +#include <linux/slab.h> +#include <linux/v4l2-mediabus.h> +#include <linux/videodev2.h> + +#include <media/v4l2-async.h> +#include <media/v4l2-common.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-device.h> +#include <media/v4l2-fwnode.h> +#include <media/v4l2-ioctl.h> + +/* + * This control allows to activate and deactivate the test pattern on + * selected output channels. + * This value is ISL7998x specific. + */ +#define V4L2_CID_TEST_PATTERN_CHANNELS (V4L2_CID_USER_ISL7998X_BASE + 0) + +/* + * This control allows to specify the color of the test pattern. + * This value is ISL7998x specific. + */ +#define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_ISL7998X_BASE + 1) + +/* + * This control allows to specify the bar pattern in the test pattern. + * This value is ISL7998x specific. + */ +#define V4L2_CID_TEST_PATTERN_BARS (V4L2_CID_USER_ISL7998X_BASE + 2) + +#define ISL7998X_INPUTS 4 + +#define ISL7998X_REG(page, reg) (((page) << 8) | (reg)) + +#define ISL7998X_REG_PN_SIZE 256 +#define ISL7998X_REG_PN_BASE(n) ((n) * ISL7998X_REG_PN_SIZE) + +#define ISL7998X_REG_PX_DEC_PAGE(page) ISL7998X_REG((page), 0xff) +#define ISL7998X_REG_PX_DEC_PAGE_MASK 0xf +#define ISL7998X_REG_P0_PRODUCT_ID_CODE ISL7998X_REG(0, 0x00) +#define ISL7998X_REG_P0_PRODUCT_REV_CODE ISL7998X_REG(0, 0x01) +#define ISL7998X_REG_P0_SW_RESET_CTL ISL7998X_REG(0, 0x02) +#define ISL7998X_REG_P0_IO_BUFFER_CTL ISL7998X_REG(0, 0x03) +#define ISL7998X_REG_P0_IO_BUFFER_CTL_1_1 ISL7998X_REG(0, 0x04) +#define ISL7998X_REG_P0_IO_PAD_PULL_EN_CTL ISL7998X_REG(0, 0x05) +#define ISL7998X_REG_P0_IO_BUFFER_CTL_1_2 ISL7998X_REG(0, 0x06) +#define ISL7998X_REG_P0_VIDEO_IN_CHAN_CTL ISL7998X_REG(0, 0x07) +#define ISL7998X_REG_P0_CLK_CTL_1 ISL7998X_REG(0, 0x08) +#define ISL7998X_REG_P0_CLK_CTL_2 ISL7998X_REG(0, 0x09) +#define ISL7998X_REG_P0_CLK_CTL_3 ISL7998X_REG(0, 0x0a) +#define ISL7998X_REG_P0_CLK_CTL_4 ISL7998X_REG(0, 0x0b) +#define ISL7998X_REG_P0_MPP1_SYNC_CTL ISL7998X_REG(0, 0x0c) +#define ISL7998X_REG_P0_MPP2_SYNC_CTL ISL7998X_REG(0, 0x0d) +#define ISL7998X_REG_P0_IRQ_SYNC_CTL ISL7998X_REG(0, 0x0e) +#define ISL7998X_REG_P0_INTERRUPT_STATUS ISL7998X_REG(0, 0x10) +#define ISL7998X_REG_P0_CHAN_1_IRQ ISL7998X_REG(0, 0x11) +#define ISL7998X_REG_P0_CHAN_2_IRQ ISL7998X_REG(0, 0x12) +#define ISL7998X_REG_P0_CHAN_3_IRQ ISL7998X_REG(0, 0x13) +#define ISL7998X_REG_P0_CHAN_4_IRQ ISL7998X_REG(0, 0x14) +#define ISL7998X_REG_P0_SHORT_DIAG_IRQ ISL7998X_REG(0, 0x15) +#define ISL7998X_REG_P0_CHAN_1_IRQ_EN ISL7998X_REG(0, 0x16) +#define ISL7998X_REG_P0_CHAN_2_IRQ_EN ISL7998X_REG(0, 0x17) +#define ISL7998X_REG_P0_CHAN_3_IRQ_EN ISL7998X_REG(0, 0x18) +#define ISL7998X_REG_P0_CHAN_4_IRQ_EN ISL7998X_REG(0, 0x19) +#define ISL7998X_REG_P0_SHORT_DIAG_IRQ_EN ISL7998X_REG(0, 0x1a) +#define ISL7998X_REG_P0_CHAN_1_STATUS ISL7998X_REG(0, 0x1b) +#define ISL7998X_REG_P0_CHAN_2_STATUS ISL7998X_REG(0, 0x1c) +#define ISL7998X_REG_P0_CHAN_3_STATUS ISL7998X_REG(0, 0x1d) +#define ISL7998X_REG_P0_CHAN_4_STATUS ISL7998X_REG(0, 0x1e) +#define ISL7998X_REG_P0_SHORT_DIAG_STATUS ISL7998X_REG(0, 0x1f) +#define ISL7998X_REG_P0_CLOCK_DELAY ISL7998X_REG(0, 0x20) + +#define ISL7998X_REG_PX_DEC_INPUT_FMT(pg) ISL7998X_REG((pg), 0x02) +#define ISL7998X_REG_PX_DEC_STATUS_1(pg) ISL7998X_REG((pg), 0x03) +#define ISL7998X_REG_PX_DEC_STATUS_1_VDLOSS BIT(7) +#define ISL7998X_REG_PX_DEC_STATUS_1_HLOCK BIT(6) +#define ISL7998X_REG_PX_DEC_STATUS_1_VLOCK BIT(3) +#define ISL7998X_REG_PX_DEC_HS_DELAY_CTL(pg) ISL7998X_REG((pg), 0x04) +#define ISL7998X_REG_PX_DEC_ANCTL(pg) ISL7998X_REG((pg), 0x06) +#define ISL7998X_REG_PX_DEC_CROP_HI(pg) ISL7998X_REG((pg), 0x07) +#define ISL7998X_REG_PX_DEC_VDELAY_LO(pg) ISL7998X_REG((pg), 0x08) +#define ISL7998X_REG_PX_DEC_VACTIVE_LO(pg) ISL7998X_REG((pg), 0x09) +#define ISL7998X_REG_PX_DEC_HDELAY_LO(pg) ISL7998X_REG((pg), 0x0a) +#define ISL7998X_REG_PX_DEC_HACTIVE_LO(pg) ISL7998X_REG((pg), 0x0b) +#define ISL7998X_REG_PX_DEC_CNTRL1(pg) ISL7998X_REG((pg), 0x0c) +#define ISL7998X_REG_PX_DEC_CSC_CTL(pg) ISL7998X_REG((pg), 0x0d) +#define ISL7998X_REG_PX_DEC_BRIGHT(pg) ISL7998X_REG((pg), 0x10) +#define ISL7998X_REG_PX_DEC_CONTRAST(pg) ISL7998X_REG((pg), 0x11) +#define ISL7998X_REG_PX_DEC_SHARPNESS(pg) ISL7998X_REG((pg), 0x12) +#define ISL7998X_REG_PX_DEC_SAT_U(pg) ISL7998X_REG((pg), 0x13) +#define ISL7998X_REG_PX_DEC_SAT_V(pg) ISL7998X_REG((pg), 0x14) +#define ISL7998X_REG_PX_DEC_HUE(pg) ISL7998X_REG((pg), 0x15) +#define ISL7998X_REG_PX_DEC_VERT_PEAK(pg) ISL7998X_REG((pg), 0x17) +#define ISL7998X_REG_PX_DEC_CORING(pg) ISL7998X_REG((pg), 0x18) +#define ISL7998X_REG_PX_DEC_SDT(pg) ISL7998X_REG((pg), 0x1c) +#define ISL7998X_REG_PX_DEC_SDT_DET BIT(7) +#define ISL7998X_REG_PX_DEC_SDT_NOW GENMASK(6, 4) +#define ISL7998X_REG_PX_DEC_SDT_STANDARD GENMASK(2, 0) +#define ISL7998X_REG_PX_DEC_SDT_STANDARD_NTSC_M 0 +#define ISL7998X_REG_PX_DEC_SDT_STANDARD_PAL 1 +#define ISL7998X_REG_PX_DEC_SDT_STANDARD_SECAM 2 +#define ISL7998X_REG_PX_DEC_SDT_STANDARD_NTSC_443 3 +#define ISL7998X_REG_PX_DEC_SDT_STANDARD_PAL_M 4 +#define ISL7998X_REG_PX_DEC_SDT_STANDARD_PAL_CN 5 +#define ISL7998X_REG_PX_DEC_SDT_STANDARD_PAL_60 6 +#define ISL7998X_REG_PX_DEC_SDT_STANDARD_UNKNOWN 7 +#define ISL7998X_REG_PX_DEC_SDTR(pg) ISL7998X_REG((pg), 0x1d) +#define ISL7998X_REG_PX_DEC_SDTR_ATSTART BIT(7) +#define ISL7998X_REG_PX_DEC_CLMPG(pg) ISL7998X_REG((pg), 0x20) +#define ISL7998X_REG_PX_DEC_IAGC(pg) ISL7998X_REG((pg), 0x21) +#define ISL7998X_REG_PX_DEC_AGCGAIN(pg) ISL7998X_REG((pg), 0x22) +#define ISL7998X_REG_PX_DEC_PEAKWT(pg) ISL7998X_REG((pg), 0x23) +#define ISL7998X_REG_PX_DEC_CLMPL(pg) ISL7998X_REG((pg), 0x24) +#define ISL7998X_REG_PX_DEC_SYNCT(pg) ISL7998X_REG((pg), 0x25) +#define ISL7998X_REG_PX_DEC_MISSCNT(pg) ISL7998X_REG((pg), 0x26) +#define ISL7998X_REG_PX_DEC_PCLAMP(pg) ISL7998X_REG((pg), 0x27) +#define ISL7998X_REG_PX_DEC_VERT_CTL_1(pg) ISL7998X_REG((pg), 0x28) +#define ISL7998X_REG_PX_DEC_VERT_CTL_2(pg) ISL7998X_REG((pg), 0x29) +#define ISL7998X_REG_PX_DEC_CLR_KILL_LVL(pg) ISL7998X_REG((pg), 0x2a) +#define ISL7998X_REG_PX_DEC_COMB_FILTER_CTL(pg) ISL7998X_REG((pg), 0x2b) +#define ISL7998X_REG_PX_DEC_LUMA_DELAY(pg) ISL7998X_REG((pg), 0x2c) +#define ISL7998X_REG_PX_DEC_MISC1(pg) ISL7998X_REG((pg), 0x2d) +#define ISL7998X_REG_PX_DEC_MISC2(pg) ISL7998X_REG((pg), 0x2e) +#define ISL7998X_REG_PX_DEC_MISC3(pg) ISL7998X_REG((pg), 0x2f) +#define ISL7998X_REG_PX_DEC_MVSN(pg) ISL7998X_REG((pg), 0x30) +#define ISL7998X_REG_PX_DEC_CSTATUS2(pg) ISL7998X_REG((pg), 0x31) +#define ISL7998X_REG_PX_DEC_HFREF(pg) ISL7998X_REG((pg), 0x32) +#define ISL7998X_REG_PX_DEC_CLMD(pg) ISL7998X_REG((pg), 0x33) +#define ISL7998X_REG_PX_DEC_ID_DET_CTL(pg) ISL7998X_REG((pg), 0x34) +#define ISL7998X_REG_PX_DEC_CLCNTL(pg) ISL7998X_REG((pg), 0x35) +#define ISL7998X_REG_PX_DEC_DIFF_CLMP_CTL_1(pg) ISL7998X_REG((pg), 0x36) +#define ISL7998X_REG_PX_DEC_DIFF_CLMP_CTL_2(pg) ISL7998X_REG((pg), 0x37) +#define ISL7998X_REG_PX_DEC_DIFF_CLMP_CTL_3(pg) ISL7998X_REG((pg), 0x38) +#define ISL7998X_REG_PX_DEC_DIFF_CLMP_CTL_4(pg) ISL7998X_REG((pg), 0x39) +#define ISL7998X_REG_PX_DEC_SHORT_DET_CTL(pg) ISL7998X_REG((pg), 0x3a) +#define ISL7998X_REG_PX_DEC_SHORT_DET_CTL_1(pg) ISL7998X_REG((pg), 0x3b) +#define ISL7998X_REG_PX_DEC_AFE_TST_MUX_CTL(pg) ISL7998X_REG((pg), 0x3c) +#define ISL7998X_REG_PX_DEC_DATA_CONV(pg) ISL7998X_REG((pg), 0x3d) +#define ISL7998X_REG_PX_DEC_INTERNAL_TEST(pg) ISL7998X_REG((pg), 0x3f) +#define ISL7998X_REG_PX_DEC_H_DELAY_CTL(pg) ISL7998X_REG((pg), 0x43) +#define ISL7998X_REG_PX_DEC_H_DELAY_II_HI(pg) ISL7998X_REG((pg), 0x44) +#define ISL7998X_REG_PX_DEC_H_DELAY_II_LOW(pg) ISL7998X_REG((pg), 0x45) + +#define ISL7998X_REG_PX_ACA_CTL_1(pg) ISL7998X_REG((pg), 0x80) +#define ISL7998X_REG_PX_ACA_GAIN_CTL(pg) ISL7998X_REG((pg), 0x81) +#define ISL7998X_REG_PX_ACA_Y_AVG_HI_LIMIT(pg) ISL7998X_REG((pg), 0x82) +#define ISL7998X_REG_PX_ACA_Y_AVG_LO_LIMIT(pg) ISL7998X_REG((pg), 0x83) +#define ISL7998X_REG_PX_ACA_Y_DET_THRESHOLD(pg) ISL7998X_REG((pg), 0x84) +#define ISL7998X_REG_PX_ACA_BLACK_LVL(pg) ISL7998X_REG((pg), 0x85) +#define ISL7998X_REG_PX_ACA_CENTER_LVL(pg) ISL7998X_REG((pg), 0x86) +#define ISL7998X_REG_PX_ACA_WHITE_LVL(pg) ISL7998X_REG((pg), 0x87) +#define ISL7998X_REG_PX_ACA_MEAN_OFF_LIMIT(pg) ISL7998X_REG((pg), 0x88) +#define ISL7998X_REG_PX_ACA_MEAN_OFF_UPGAIN(pg) ISL7998X_REG((pg), 0x89) +#define ISL7998X_REG_PX_ACA_MEAN_OFF_SLOPE(pg) ISL7998X_REG((pg), 0x8a) +#define ISL7998X_REG_PX_ACA_MEAN_OFF_DNGAIN(pg) ISL7998X_REG((pg), 0x8b) +#define ISL7998X_REG_PX_ACA_DELTA_CO_THRES(pg) ISL7998X_REG((pg), 0x8c) +#define ISL7998X_REG_PX_ACA_DELTA_SLOPE(pg) ISL7998X_REG((pg), 0x8d) +#define ISL7998X_REG_PX_ACA_LO_HI_AVG_THRES(pg) ISL7998X_REG((pg), 0x8e) +#define ISL7998X_REG_PX_ACA_LO_MAX_LVL_CTL(pg) ISL7998X_REG((pg), 0x8f) +#define ISL7998X_REG_PX_ACA_HI_MAX_LVL_CTL(pg) ISL7998X_REG((pg), 0x90) +#define ISL7998X_REG_PX_ACA_LO_UPGAIN_CTL(pg) ISL7998X_REG((pg), 0x91) +#define ISL7998X_REG_PX_ACA_LO_DNGAIN_CTL(pg) ISL7998X_REG((pg), 0x92) +#define ISL7998X_REG_PX_ACA_HI_UPGAIN_CTL(pg) ISL7998X_REG((pg), 0x93) +#define ISL7998X_REG_PX_ACA_HI_DNGAIN_CTL(pg) ISL7998X_REG((pg), 0x94) +#define ISL7998X_REG_PX_ACA_LOPASS_FLT_COEF(pg) ISL7998X_REG((pg), 0x95) +#define ISL7998X_REG_PX_ACA_PDF_INDEX(pg) ISL7998X_REG((pg), 0x96) +#define ISL7998X_REG_PX_ACA_HIST_WIN_H_STT(pg) ISL7998X_REG((pg), 0x97) +#define ISL7998X_REG_PX_ACA_HIST_WIN_H_SZ1(pg) ISL7998X_REG((pg), 0x98) +#define ISL7998X_REG_PX_ACA_HIST_WIN_H_SZ2(pg) ISL7998X_REG((pg), 0x99) +#define ISL7998X_REG_PX_ACA_HIST_WIN_V_STT(pg) ISL7998X_REG((pg), 0x9a) +#define ISL7998X_REG_PX_ACA_HIST_WIN_V_SZ1(pg) ISL7998X_REG((pg), 0x9b) +#define ISL7998X_REG_PX_ACA_HIST_WIN_V_SZ2(pg) ISL7998X_REG((pg), 0x9c) +#define ISL7998X_REG_PX_ACA_Y_AVG(pg) ISL7998X_REG((pg), 0xa0) +#define ISL7998X_REG_PX_ACA_Y_AVG_LIM(pg) ISL7998X_REG((pg), 0xa1) +#define ISL7998X_REG_PX_ACA_LO_AVG(pg) ISL7998X_REG((pg), 0xa2) +#define ISL7998X_REG_PX_ACA_HI_AVG(pg) ISL7998X_REG((pg), 0xa3) +#define ISL7998X_REG_PX_ACA_Y_MAX(pg) ISL7998X_REG((pg), 0xa4) +#define ISL7998X_REG_PX_ACA_Y_MIN(pg) ISL7998X_REG((pg), 0xa5) +#define ISL7998X_REG_PX_ACA_MOFFSET(pg) ISL7998X_REG((pg), 0xa6) +#define ISL7998X_REG_PX_ACA_LO_GAIN(pg) ISL7998X_REG((pg), 0xa7) +#define ISL7998X_REG_PX_ACA_HI_GAIN(pg) ISL7998X_REG((pg), 0xa8) +#define ISL7998X_REG_PX_ACA_LL_SLOPE(pg) ISL7998X_REG((pg), 0xa9) +#define ISL7998X_REG_PX_ACA_LH_SLOPE(pg) ISL7998X_REG((pg), 0xaa) +#define ISL7998X_REG_PX_ACA_HL_SLOPE(pg) ISL7998X_REG((pg), 0xab) +#define ISL7998X_REG_PX_ACA_HH_SLOPE(pg) ISL7998X_REG((pg), 0xac) +#define ISL7998X_REG_PX_ACA_X_LOW(pg) ISL7998X_REG((pg), 0xad) +#define ISL7998X_REG_PX_ACA_X_MEAN(pg) ISL7998X_REG((pg), 0xae) +#define ISL7998X_REG_PX_ACA_X_HIGH(pg) ISL7998X_REG((pg), 0xaf) +#define ISL7998X_REG_PX_ACA_Y_LOW(pg) ISL7998X_REG((pg), 0xb0) +#define ISL7998X_REG_PX_ACA_Y_MEAN(pg) ISL7998X_REG((pg), 0xb1) +#define ISL7998X_REG_PX_ACA_Y_HIGH(pg) ISL7998X_REG((pg), 0xb2) +#define ISL7998X_REG_PX_ACA_CTL_2(pg) ISL7998X_REG((pg), 0xb3) +#define ISL7998X_REG_PX_ACA_CTL_3(pg) ISL7998X_REG((pg), 0xb4) +#define ISL7998X_REG_PX_ACA_CTL_4(pg) ISL7998X_REG((pg), 0xb5) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_HIST(pg) ISL7998X_REG((pg), 0xc0) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_TL_H(pg) ISL7998X_REG((pg), 0xc1) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_TL_L(pg) ISL7998X_REG((pg), 0xc2) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_TL_H(pg) ISL7998X_REG((pg), 0xc3) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_TL_L(pg) ISL7998X_REG((pg), 0xc4) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_TR_H(pg) ISL7998X_REG((pg), 0xc5) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_TR_L(pg) ISL7998X_REG((pg), 0xc6) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_TR_H(pg) ISL7998X_REG((pg), 0xc7) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_TR_L(pg) ISL7998X_REG((pg), 0xc8) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_BL_H(pg) ISL7998X_REG((pg), 0xc9) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_BL_L(pg) ISL7998X_REG((pg), 0xca) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_BL_H(pg) ISL7998X_REG((pg), 0xcb) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_BL_L(pg) ISL7998X_REG((pg), 0xcc) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_BR_H(pg) ISL7998X_REG((pg), 0xcd) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_BR_L(pg) ISL7998X_REG((pg), 0xce) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_BR_H(pg) ISL7998X_REG((pg), 0xcf) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_BR_L(pg) ISL7998X_REG((pg), 0xd0) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_LM_H(pg) ISL7998X_REG((pg), 0xd1) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_LM_L(pg) ISL7998X_REG((pg), 0xd2) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_LM_H(pg) ISL7998X_REG((pg), 0xd3) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_LM_L(pg) ISL7998X_REG((pg), 0xd4) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_TM_H(pg) ISL7998X_REG((pg), 0xd5) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_TM_L(pg) ISL7998X_REG((pg), 0xd6) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_TM_H(pg) ISL7998X_REG((pg), 0xd7) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_TM_L(pg) ISL7998X_REG((pg), 0xd8) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_BM_H(pg) ISL7998X_REG((pg), 0xd9) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_BM_L(pg) ISL7998X_REG((pg), 0xda) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_BM_H(pg) ISL7998X_REG((pg), 0xdb) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_BM_L(pg) ISL7998X_REG((pg), 0xdc) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_RM_H(pg) ISL7998X_REG((pg), 0xdd) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_RM_L(pg) ISL7998X_REG((pg), 0xde) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_RM_H(pg) ISL7998X_REG((pg), 0xdf) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_RM_L(pg) ISL7998X_REG((pg), 0xe0) +#define ISL7998X_REG_PX_ACA_HIST_DATA_LO(pg) ISL7998X_REG((pg), 0xe1) +#define ISL7998X_REG_PX_ACA_HIST_DATA_MID(pg) ISL7998X_REG((pg), 0xe2) +#define ISL7998X_REG_PX_ACA_HIST_DATA_HI(pg) ISL7998X_REG((pg), 0xe3) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_CLR(pg) ISL7998X_REG((pg), 0xe4) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_CB_CLR(pg) ISL7998X_REG((pg), 0xe5) +#define ISL7998X_REG_PX_ACA_FLEX_WIN_CR_CLR(pg) ISL7998X_REG((pg), 0xe6) +#define ISL7998X_REG_PX_ACA_XFER_HIST_HOST(pg) ISL7998X_REG((pg), 0xe7) + +#define ISL7998X_REG_P5_LI_ENGINE_CTL ISL7998X_REG(5, 0x00) +#define ISL7998X_REG_P5_LI_ENGINE_LINE_CTL ISL7998X_REG(5, 0x01) +#define ISL7998X_REG_P5_LI_ENGINE_PIC_WIDTH ISL7998X_REG(5, 0x02) +#define ISL7998X_REG_P5_LI_ENGINE_SYNC_CTL ISL7998X_REG(5, 0x03) +#define ISL7998X_REG_P5_LI_ENGINE_VC_ASSIGNMENT ISL7998X_REG(5, 0x04) +#define ISL7998X_REG_P5_LI_ENGINE_TYPE_CTL ISL7998X_REG(5, 0x05) +#define ISL7998X_REG_P5_LI_ENGINE_FIFO_CTL ISL7998X_REG(5, 0x06) +#define ISL7998X_REG_P5_MIPI_READ_START_CTL ISL7998X_REG(5, 0x07) +#define ISL7998X_REG_P5_PSEUDO_FRM_FIELD_CTL ISL7998X_REG(5, 0x08) +#define ISL7998X_REG_P5_ONE_FIELD_MODE_CTL ISL7998X_REG(5, 0x09) +#define ISL7998X_REG_P5_MIPI_INT_HW_TST_CTR ISL7998X_REG(5, 0x0a) +#define ISL7998X_REG_P5_TP_GEN_BAR_PATTERN ISL7998X_REG(5, 0x0b) +#define ISL7998X_REG_P5_MIPI_PCNT_PSFRM ISL7998X_REG(5, 0x0c) +#define ISL7998X_REG_P5_LI_ENGINE_TP_GEN_CTL ISL7998X_REG(5, 0x0d) +#define ISL7998X_REG_P5_MIPI_VBLANK_PSFRM ISL7998X_REG(5, 0x0e) +#define ISL7998X_REG_P5_LI_ENGINE_CTL_2 ISL7998X_REG(5, 0x0f) +#define ISL7998X_REG_P5_MIPI_WCNT_1 ISL7998X_REG(5, 0x10) +#define ISL7998X_REG_P5_MIPI_WCNT_2 ISL7998X_REG(5, 0x11) +#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_1 ISL7998X_REG(5, 0x12) +#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_2 ISL7998X_REG(5, 0x13) +#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_3 ISL7998X_REG(5, 0x14) +#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_4 ISL7998X_REG(5, 0x15) +#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_5 ISL7998X_REG(5, 0x16) +#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_6 ISL7998X_REG(5, 0x17) +#define ISL7998X_REG_P5_MIPI_DPHY_PARAMS_1 ISL7998X_REG(5, 0x18) +#define ISL7998X_REG_P5_MIPI_DPHY_SOT_PERIOD ISL7998X_REG(5, 0x19) +#define ISL7998X_REG_P5_MIPI_DPHY_EOT_PERIOD ISL7998X_REG(5, 0x1a) +#define ISL7998X_REG_P5_MIPI_DPHY_PARAMS_2 ISL7998X_REG(5, 0x1b) +#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_7 ISL7998X_REG(5, 0x1c) +#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_8 ISL7998X_REG(5, 0x1d) +#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_9 ISL7998X_REG(5, 0x1e) +#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_10 ISL7998X_REG(5, 0x1f) +#define ISL7998X_REG_P5_TP_GEN_MIPI ISL7998X_REG(5, 0x20) +#define ISL7998X_REG_P5_ESC_MODE_TIME_CTL ISL7998X_REG(5, 0x21) +#define ISL7998X_REG_P5_AUTO_TEST_ERR_DET ISL7998X_REG(5, 0x22) +#define ISL7998X_REG_P5_MIPI_TIMING ISL7998X_REG(5, 0x23) +#define ISL7998X_REG_P5_PIC_HEIGHT_HIGH ISL7998X_REG(5, 0x24) +#define ISL7998X_REG_P5_PIC_HEIGHT_LOW ISL7998X_REG(5, 0x25) +#define ISL7998X_REG_P5_MIPI_SP_HS_TRL_CTL ISL7998X_REG(5, 0x26) +#define ISL7998X_REG_P5_FIFO_THRSH_CNT_1 ISL7998X_REG(5, 0x28) +#define ISL7998X_REG_P5_FIFO_THRSH_CNT_2 ISL7998X_REG(5, 0x29) +#define ISL7998X_REG_P5_TP_GEN_RND_SYNC_CTL_1 ISL7998X_REG(5, 0x2a) +#define ISL7998X_REG_P5_TP_GEN_RND_SYNC_CTL_2 ISL7998X_REG(5, 0x2b) +#define ISL7998X_REG_P5_PSF_FIELD_END_CTL_1 ISL7998X_REG(5, 0x2c) +#define ISL7998X_REG_P5_PSF_FIELD_END_CTL_2 ISL7998X_REG(5, 0x2d) +#define ISL7998X_REG_P5_PSF_FIELD_END_CTL_3 ISL7998X_REG(5, 0x2e) +#define ISL7998X_REG_P5_PSF_FIELD_END_CTL_4 ISL7998X_REG(5, 0x2f) +#define ISL7998X_REG_P5_MIPI_ANA_DATA_CTL_1 ISL7998X_REG(5, 0x30) +#define ISL7998X_REG_P5_MIPI_ANA_DATA_CTL_2 ISL7998X_REG(5, 0x31) +#define ISL7998X_REG_P5_MIPI_ANA_CLK_CTL ISL7998X_REG(5, 0x32) +#define ISL7998X_REG_P5_PLL_ANA_STATUS ISL7998X_REG(5, 0x33) +#define ISL7998X_REG_P5_PLL_ANA_MISC_CTL ISL7998X_REG(5, 0x34) +#define ISL7998X_REG_P5_MIPI_ANA ISL7998X_REG(5, 0x35) +#define ISL7998X_REG_P5_PLL_ANA ISL7998X_REG(5, 0x36) +#define ISL7998X_REG_P5_TOTAL_PF_LINE_CNT_1 ISL7998X_REG(5, 0x38) +#define ISL7998X_REG_P5_TOTAL_PF_LINE_CNT_2 ISL7998X_REG(5, 0x39) +#define ISL7998X_REG_P5_H_LINE_CNT_1 ISL7998X_REG(5, 0x3a) +#define ISL7998X_REG_P5_H_LINE_CNT_2 ISL7998X_REG(5, 0x3b) +#define ISL7998X_REG_P5_HIST_LINE_CNT_1 ISL7998X_REG(5, 0x3c) +#define ISL7998X_REG_P5_HIST_LINE_CNT_2 ISL7998X_REG(5, 0x3d) + +static const struct reg_sequence isl7998x_init_seq_1[] = { + { ISL7998X_REG_P0_SHORT_DIAG_IRQ_EN, 0xff }, + { ISL7998X_REG_PX_DEC_SDT(0x1), 0x00 }, + { ISL7998X_REG_PX_DEC_SHORT_DET_CTL_1(0x1), 0x03 }, + { ISL7998X_REG_PX_DEC_SDT(0x2), 0x00 }, + { ISL7998X_REG_PX_DEC_SHORT_DET_CTL_1(0x2), 0x03 }, + { ISL7998X_REG_PX_DEC_SDT(0x3), 0x00 }, + { ISL7998X_REG_PX_DEC_SHORT_DET_CTL_1(0x3), 0x03 }, + { ISL7998X_REG_PX_DEC_SDT(0x4), 0x00 }, + { ISL7998X_REG_PX_DEC_SHORT_DET_CTL_1(0x4), 0x03 }, + { ISL7998X_REG_P5_LI_ENGINE_CTL, 0x00 }, + { ISL7998X_REG_P0_SW_RESET_CTL, 0x1f, 10 }, + { ISL7998X_REG_P0_IO_BUFFER_CTL, 0x00 }, + { ISL7998X_REG_P0_MPP2_SYNC_CTL, 0xc9 }, + { ISL7998X_REG_P0_IRQ_SYNC_CTL, 0xc9 }, + { ISL7998X_REG_P0_CHAN_1_IRQ, 0x03 }, + { ISL7998X_REG_P0_CHAN_2_IRQ, 0x00 }, + { ISL7998X_REG_P0_CHAN_3_IRQ, 0x00 }, + { ISL7998X_REG_P0_CHAN_4_IRQ, 0x00 }, + { ISL7998X_REG_P5_LI_ENGINE_CTL, 0x02 }, + { ISL7998X_REG_P5_LI_ENGINE_LINE_CTL, 0x85 }, + { ISL7998X_REG_P5_LI_ENGINE_PIC_WIDTH, 0xa0 }, + { ISL7998X_REG_P5_LI_ENGINE_SYNC_CTL, 0x18 }, + { ISL7998X_REG_P5_LI_ENGINE_TYPE_CTL, 0x40 }, + { ISL7998X_REG_P5_LI_ENGINE_FIFO_CTL, 0x40 }, + { ISL7998X_REG_P5_MIPI_WCNT_1, 0x05 }, + { ISL7998X_REG_P5_MIPI_WCNT_2, 0xa0 }, + { ISL7998X_REG_P5_TP_GEN_MIPI, 0x00 }, + { ISL7998X_REG_P5_ESC_MODE_TIME_CTL, 0x0c }, + { ISL7998X_REG_P5_MIPI_SP_HS_TRL_CTL, 0x00 }, + { ISL7998X_REG_P5_TP_GEN_RND_SYNC_CTL_1, 0x00 }, + { ISL7998X_REG_P5_TP_GEN_RND_SYNC_CTL_2, 0x19 }, + { ISL7998X_REG_P5_PSF_FIELD_END_CTL_1, 0x18 }, + { ISL7998X_REG_P5_PSF_FIELD_END_CTL_2, 0xf1 }, + { ISL7998X_REG_P5_PSF_FIELD_END_CTL_3, 0x00 }, + { ISL7998X_REG_P5_PSF_FIELD_END_CTL_4, 0xf1 }, + { ISL7998X_REG_P5_MIPI_ANA_DATA_CTL_1, 0x00 }, + { ISL7998X_REG_P5_MIPI_ANA_DATA_CTL_2, 0x00 }, + { ISL7998X_REG_P5_MIPI_ANA_CLK_CTL, 0x00 }, + { ISL7998X_REG_P5_PLL_ANA_STATUS, 0xc0 }, + { ISL7998X_REG_P5_PLL_ANA_MISC_CTL, 0x18 }, + { ISL7998X_REG_P5_PLL_ANA, 0x00 }, + { ISL7998X_REG_P0_SW_RESET_CTL, 0x10, 10 }, + /* Page 0xf means write to all of pages 1,2,3,4 */ + { ISL7998X_REG_PX_DEC_VDELAY_LO(0xf), 0x14 }, + { ISL7998X_REG_PX_DEC_MISC3(0xf), 0xe6 }, + { ISL7998X_REG_PX_DEC_CLMD(0xf), 0x85 }, + { ISL7998X_REG_PX_DEC_H_DELAY_II_LOW(0xf), 0x11 }, + { ISL7998X_REG_PX_ACA_XFER_HIST_HOST(0xf), 0x00 }, + { ISL7998X_REG_P0_CLK_CTL_1, 0x1f }, + { ISL7998X_REG_P0_CLK_CTL_2, 0x43 }, + { ISL7998X_REG_P0_CLK_CTL_3, 0x4f }, +}; + +static const struct reg_sequence isl7998x_init_seq_2[] = { + { ISL7998X_REG_P5_LI_ENGINE_SYNC_CTL, 0x10 }, + { ISL7998X_REG_P5_LI_ENGINE_VC_ASSIGNMENT, 0xe4 }, + { ISL7998X_REG_P5_LI_ENGINE_TYPE_CTL, 0x00 }, + { ISL7998X_REG_P5_LI_ENGINE_FIFO_CTL, 0x60 }, + { ISL7998X_REG_P5_MIPI_READ_START_CTL, 0x2b }, + { ISL7998X_REG_P5_PSEUDO_FRM_FIELD_CTL, 0x02 }, + { ISL7998X_REG_P5_ONE_FIELD_MODE_CTL, 0x00 }, + { ISL7998X_REG_P5_MIPI_INT_HW_TST_CTR, 0x62 }, + { ISL7998X_REG_P5_TP_GEN_BAR_PATTERN, 0x02 }, + { ISL7998X_REG_P5_MIPI_PCNT_PSFRM, 0x36 }, + { ISL7998X_REG_P5_LI_ENGINE_TP_GEN_CTL, 0x00 }, + { ISL7998X_REG_P5_MIPI_VBLANK_PSFRM, 0x6c }, + { ISL7998X_REG_P5_LI_ENGINE_CTL_2, 0x00 }, + { ISL7998X_REG_P5_MIPI_WCNT_1, 0x05 }, + { ISL7998X_REG_P5_MIPI_WCNT_2, 0xa0 }, + { ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_1, 0x77 }, + { ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_2, 0x17 }, + { ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_3, 0x08 }, + { ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_4, 0x38 }, + { ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_5, 0x14 }, + { ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_6, 0xf6 }, + { ISL7998X_REG_P5_MIPI_DPHY_PARAMS_1, 0x00 }, + { ISL7998X_REG_P5_MIPI_DPHY_SOT_PERIOD, 0x17 }, + { ISL7998X_REG_P5_MIPI_DPHY_EOT_PERIOD, 0x0a }, + { ISL7998X_REG_P5_MIPI_DPHY_PARAMS_2, 0x71 }, + { ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_7, 0x7a }, + { ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_8, 0x0f }, + { ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_9, 0x8c }, + { ISL7998X_REG_P5_MIPI_SP_HS_TRL_CTL, 0x08 }, + { ISL7998X_REG_P5_FIFO_THRSH_CNT_1, 0x01 }, + { ISL7998X_REG_P5_FIFO_THRSH_CNT_2, 0x0e }, + { ISL7998X_REG_P5_TP_GEN_RND_SYNC_CTL_1, 0x00 }, + { ISL7998X_REG_P5_TP_GEN_RND_SYNC_CTL_2, 0x00 }, + { ISL7998X_REG_P5_TOTAL_PF_LINE_CNT_1, 0x03 }, + { ISL7998X_REG_P5_TOTAL_PF_LINE_CNT_2, 0xc0 }, + { ISL7998X_REG_P5_H_LINE_CNT_1, 0x06 }, + { ISL7998X_REG_P5_H_LINE_CNT_2, 0xb3 }, + { ISL7998X_REG_P5_HIST_LINE_CNT_1, 0x00 }, + { ISL7998X_REG_P5_HIST_LINE_CNT_2, 0xf1 }, + { ISL7998X_REG_P5_LI_ENGINE_FIFO_CTL, 0x00 }, + { ISL7998X_REG_P5_MIPI_ANA, 0x00 }, + /* + * Wait a bit after reset so that the chip can capture a frame + * and update internal line counters. + */ + { ISL7998X_REG_P0_SW_RESET_CTL, 0x00, 50 }, +}; + +enum isl7998x_pads { + ISL7998X_PAD_OUT, + ISL7998X_PAD_VIN1, + ISL7998X_PAD_VIN2, + ISL7998X_PAD_VIN3, + ISL7998X_PAD_VIN4, + ISL7998X_NUM_PADS +}; + +struct isl7998x_datafmt { + u32 code; + enum v4l2_colorspace colorspace; +}; + +static const struct isl7998x_datafmt isl7998x_colour_fmts[] = { + { MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_SRGB }, +}; + +/* Menu items for LINK_FREQ V4L2 control */ +static const s64 link_freq_menu_items[] = { + /* 1 channel, 1 lane or 2 channels, 2 lanes */ + 108000000, + /* 2 channels, 1 lane or 4 channels, 2 lanes */ + 216000000, + /* 4 channels, 1 lane */ + 432000000, +}; + +/* Menu items for TEST_PATTERN V4L2 control */ +static const char * const isl7998x_test_pattern_menu[] = { + "Disabled", + "Enabled", +}; + +static const char * const isl7998x_test_pattern_bars[] = { + "bbbbwb", "bbbwwb", "bbwbwb", "bbwwwb", +}; + +static const char * const isl7998x_test_pattern_colors[] = { + "Yellow", "Blue", "Green", "Pink", +}; + +struct isl7998x_mode { + unsigned int width; + unsigned int height; + enum v4l2_field field; +}; + +static const struct isl7998x_mode supported_modes[] = { + { + .width = 720, + .height = 576, + .field = V4L2_FIELD_SEQ_TB, + }, + { + .width = 720, + .height = 480, + .field = V4L2_FIELD_SEQ_BT, + }, +}; + +static const struct isl7998x_video_std { + const v4l2_std_id norm; + unsigned int id; + const struct isl7998x_mode *mode; +} isl7998x_std_res[] = { + { V4L2_STD_NTSC_443, + ISL7998X_REG_PX_DEC_SDT_STANDARD_NTSC_443, + &supported_modes[1] }, + { V4L2_STD_PAL_M, + ISL7998X_REG_PX_DEC_SDT_STANDARD_PAL_M, + &supported_modes[1] }, + { V4L2_STD_PAL_Nc, + ISL7998X_REG_PX_DEC_SDT_STANDARD_PAL_CN, + &supported_modes[0] }, + { V4L2_STD_PAL_N, + ISL7998X_REG_PX_DEC_SDT_STANDARD_PAL, + &supported_modes[0] }, + { V4L2_STD_PAL_60, + ISL7998X_REG_PX_DEC_SDT_STANDARD_PAL_60, + &supported_modes[1] }, + { V4L2_STD_NTSC, + ISL7998X_REG_PX_DEC_SDT_STANDARD_NTSC_M, + &supported_modes[1] }, + { V4L2_STD_PAL, + ISL7998X_REG_PX_DEC_SDT_STANDARD_PAL, + &supported_modes[0] }, + { V4L2_STD_SECAM, + ISL7998X_REG_PX_DEC_SDT_STANDARD_SECAM, + &supported_modes[0] }, + { V4L2_STD_UNKNOWN, + ISL7998X_REG_PX_DEC_SDT_STANDARD_UNKNOWN, + &supported_modes[1] }, +}; + +struct isl7998x { + struct v4l2_subdev subdev; + struct regmap *regmap; + struct gpio_desc *pd_gpio; + struct gpio_desc *rstb_gpio; + unsigned int nr_mipi_lanes; + u32 nr_inputs; + + const struct isl7998x_datafmt *fmt; + v4l2_std_id norm; + struct media_pad pads[ISL7998X_NUM_PADS]; + + int enabled; + + /* protect fmt, norm, enabled */ + struct mutex lock; + + struct v4l2_ctrl_handler ctrl_handler; + /* protect ctrl_handler */ + struct mutex ctrl_mutex; + + /* V4L2 Controls */ + struct v4l2_ctrl *link_freq; + u8 test_pattern; + u8 test_pattern_bars; + u8 test_pattern_chans; + u8 test_pattern_color; +}; + +static struct isl7998x *sd_to_isl7998x(struct v4l2_subdev *sd) +{ + return container_of(sd, struct isl7998x, subdev); +} + +static struct isl7998x *i2c_to_isl7998x(const struct i2c_client *client) +{ + return sd_to_isl7998x(i2c_get_clientdata(client)); +} + +static unsigned int isl7998x_norm_to_val(v4l2_std_id norm) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(isl7998x_std_res); i++) + if (isl7998x_std_res[i].norm & norm) + break; + if (i == ARRAY_SIZE(isl7998x_std_res)) + return ISL7998X_REG_PX_DEC_SDT_STANDARD_UNKNOWN; + + return isl7998x_std_res[i].id; +} + +static const struct isl7998x_mode *isl7998x_norm_to_mode(v4l2_std_id norm) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(isl7998x_std_res); i++) + if (isl7998x_std_res[i].norm & norm) + break; + /* Use NTSC default resolution during standard detection */ + if (i == ARRAY_SIZE(isl7998x_std_res)) + return &supported_modes[1]; + + return isl7998x_std_res[i].mode; +} + +static int isl7998x_get_nr_inputs(struct device_node *of_node) +{ + struct device_node *port; + unsigned int inputs = 0; + unsigned int i; + + if (of_graph_get_endpoint_count(of_node) > ISL7998X_NUM_PADS) + return -EINVAL; + + /* + * The driver does not provide means to remap the input ports. It + * always configures input ports to start from VID1. Ensure that the + * device tree is correct. + */ + for (i = ISL7998X_PAD_VIN1; i <= ISL7998X_PAD_VIN4; i++) { + port = of_graph_get_port_by_id(of_node, i); + if (!port) + continue; + + inputs |= BIT(i); + of_node_put(port); + } + + switch (inputs) { + case BIT(ISL7998X_PAD_VIN1): + return 1; + case BIT(ISL7998X_PAD_VIN1) | BIT(ISL7998X_PAD_VIN2): + return 2; + case BIT(ISL7998X_PAD_VIN1) | BIT(ISL7998X_PAD_VIN2) | + BIT(ISL7998X_PAD_VIN3) | BIT(ISL7998X_PAD_VIN4): + return 4; + default: + return -EINVAL; + } +} + +static int isl7998x_wait_power_on(struct isl7998x *isl7998x) +{ + struct device *dev = isl7998x->subdev.dev; + u32 chip_id; + int ret; + int err; + + ret = read_poll_timeout(regmap_read, err, !err, 2000, 20000, false, + isl7998x->regmap, + ISL7998X_REG_P0_PRODUCT_ID_CODE, &chip_id); + if (ret) { + dev_err(dev, "timeout while waiting for ISL7998X\n"); + return ret; + } + + dev_dbg(dev, "Found ISL799%x\n", chip_id); + + return ret; +} + +static int isl7998x_set_standard(struct isl7998x *isl7998x, v4l2_std_id norm) +{ + const struct isl7998x_mode *mode = isl7998x_norm_to_mode(norm); + unsigned int val = isl7998x_norm_to_val(norm); + unsigned int width = mode->width; + unsigned int i; + int ret; + + for (i = 0; i < ISL7998X_INPUTS; i++) { + ret = regmap_write_bits(isl7998x->regmap, + ISL7998X_REG_PX_DEC_SDT(i + 1), + ISL7998X_REG_PX_DEC_SDT_STANDARD, + val); + if (ret) + return ret; + } + + ret = regmap_write(isl7998x->regmap, + ISL7998X_REG_P5_LI_ENGINE_LINE_CTL, + 0x20 | ((width >> 7) & 0x1f)); + if (ret) + return ret; + + ret = regmap_write(isl7998x->regmap, + ISL7998X_REG_P5_LI_ENGINE_PIC_WIDTH, + (width << 1) & 0xff); + if (ret) + return ret; + + return 0; +} + +static int isl7998x_init(struct isl7998x *isl7998x) +{ + const unsigned int lanes = isl7998x->nr_mipi_lanes; + const u32 isl7998x_video_in_chan_map[] = { 0x00, 0x11, 0x02, 0x02 }; + const struct reg_sequence isl7998x_init_seq_custom[] = { + { ISL7998X_REG_P0_VIDEO_IN_CHAN_CTL, + isl7998x_video_in_chan_map[isl7998x->nr_inputs - 1] }, + { ISL7998X_REG_P0_CLK_CTL_4, + (lanes == 1) ? 0x40 : 0x41 }, + { ISL7998X_REG_P5_LI_ENGINE_CTL, + (lanes == 1) ? 0x01 : 0x02 }, + }; + struct device *dev = isl7998x->subdev.dev; + struct regmap *regmap = isl7998x->regmap; + int ret; + + dev_dbg(dev, "configuring %d lanes for %d inputs (norm %s)\n", + isl7998x->nr_mipi_lanes, isl7998x->nr_inputs, + v4l2_norm_to_name(isl7998x->norm)); + + ret = regmap_register_patch(regmap, isl7998x_init_seq_1, + ARRAY_SIZE(isl7998x_init_seq_1)); + if (ret) + return ret; + + mutex_lock(&isl7998x->lock); + ret = isl7998x_set_standard(isl7998x, isl7998x->norm); + mutex_unlock(&isl7998x->lock); + if (ret) + return ret; + + ret = regmap_register_patch(regmap, isl7998x_init_seq_custom, + ARRAY_SIZE(isl7998x_init_seq_custom)); + if (ret) + return ret; + + return regmap_register_patch(regmap, isl7998x_init_seq_2, + ARRAY_SIZE(isl7998x_init_seq_2)); +} + +static int isl7998x_set_test_pattern(struct isl7998x *isl7998x) +{ + const struct reg_sequence isl7998x_init_seq_tpg_off[] = { + { ISL7998X_REG_P5_LI_ENGINE_TP_GEN_CTL, 0 }, + { ISL7998X_REG_P5_LI_ENGINE_CTL_2, 0 } + }; + const struct reg_sequence isl7998x_init_seq_tpg_on[] = { + { ISL7998X_REG_P5_TP_GEN_BAR_PATTERN, + isl7998x->test_pattern_bars << 6 }, + { ISL7998X_REG_P5_LI_ENGINE_CTL_2, + isl7998x->norm & V4L2_STD_PAL ? BIT(2) : 0 }, + { ISL7998X_REG_P5_LI_ENGINE_TP_GEN_CTL, + (isl7998x->test_pattern_chans << 4) | + (isl7998x->test_pattern_color << 2) } + }; + struct device *dev = isl7998x->subdev.dev; + struct regmap *regmap = isl7998x->regmap; + int ret; + + if (pm_runtime_get_if_in_use(dev) <= 0) + return 0; + + if (isl7998x->test_pattern != 0) { + dev_dbg(dev, "enabling test pattern: channels 0x%x, %s, %s\n", + isl7998x->test_pattern_chans, + isl7998x_test_pattern_bars[isl7998x->test_pattern_bars], + isl7998x_test_pattern_colors[isl7998x->test_pattern_color]); + ret = regmap_register_patch(regmap, isl7998x_init_seq_tpg_on, + ARRAY_SIZE(isl7998x_init_seq_tpg_on)); + } else { + ret = regmap_register_patch(regmap, isl7998x_init_seq_tpg_off, + ARRAY_SIZE(isl7998x_init_seq_tpg_off)); + } + + pm_runtime_put(dev); + + return ret; +} + +#ifdef CONFIG_VIDEO_ADV_DEBUG +static int isl7998x_g_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) +{ + struct isl7998x *isl7998x = sd_to_isl7998x(sd); + int ret; + u32 val; + + ret = regmap_read(isl7998x->regmap, reg->reg, &val); + if (ret) + return ret; + + reg->size = 1; + reg->val = val; + + return 0; +} + +static int isl7998x_s_register(struct v4l2_subdev *sd, + const struct v4l2_dbg_register *reg) +{ + struct isl7998x *isl7998x = sd_to_isl7998x(sd); + + return regmap_write(isl7998x->regmap, reg->reg, reg->val); +} +#endif + +static int isl7998x_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) +{ + struct isl7998x *isl7998x = sd_to_isl7998x(sd); + + mutex_lock(&isl7998x->lock); + *norm = isl7998x->norm; + mutex_unlock(&isl7998x->lock); + + return 0; +} + +static int isl7998x_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) +{ + struct isl7998x *isl7998x = sd_to_isl7998x(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct device *dev = &client->dev; + int ret = 0; + + mutex_lock(&isl7998x->lock); + if (isl7998x->enabled) { + ret = -EBUSY; + mutex_unlock(&isl7998x->lock); + return ret; + } + isl7998x->norm = norm; + mutex_unlock(&isl7998x->lock); + + if (pm_runtime_get_if_in_use(dev) <= 0) + return ret; + + ret = isl7998x_set_standard(isl7998x, norm); + + pm_runtime_put(dev); + + return ret; +} + +static int isl7998x_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) +{ + struct isl7998x *isl7998x = sd_to_isl7998x(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct device *dev = &client->dev; + unsigned int std_id[ISL7998X_INPUTS]; + unsigned int i; + int ret; + u32 reg; + + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + dev_dbg(dev, "starting video standard detection\n"); + + mutex_lock(&isl7998x->lock); + if (isl7998x->enabled) { + ret = -EBUSY; + goto out_unlock; + } + + ret = isl7998x_set_standard(isl7998x, V4L2_STD_UNKNOWN); + if (ret) + goto out_unlock; + + for (i = 0; i < ISL7998X_INPUTS; i++) { + ret = regmap_write(isl7998x->regmap, + ISL7998X_REG_PX_DEC_SDTR(i + 1), + ISL7998X_REG_PX_DEC_SDTR_ATSTART); + if (ret) + goto out_reset_std; + } + + for (i = 0; i < ISL7998X_INPUTS; i++) { + ret = regmap_read_poll_timeout(isl7998x->regmap, + ISL7998X_REG_PX_DEC_SDT(i + 1), + reg, + !(reg & ISL7998X_REG_PX_DEC_SDT_DET), + 2000, 500 * USEC_PER_MSEC); + if (ret) + goto out_reset_std; + std_id[i] = FIELD_GET(ISL7998X_REG_PX_DEC_SDT_NOW, reg); + } + + /* + * According to Renesas FAE, all input cameras must have the + * same standard on this chip. + */ + for (i = 0; i < isl7998x->nr_inputs; i++) { + dev_dbg(dev, "input %d: detected %s\n", + i, v4l2_norm_to_name(isl7998x_std_res[std_id[i]].norm)); + if (std_id[0] != std_id[i]) + dev_warn(dev, + "incompatible standards: %s on input %d (expected %s)\n", + v4l2_norm_to_name(isl7998x_std_res[std_id[i]].norm), i, + v4l2_norm_to_name(isl7998x_std_res[std_id[0]].norm)); + } + + *std = isl7998x_std_res[std_id[0]].norm; + +out_reset_std: + isl7998x_set_standard(isl7998x, isl7998x->norm); +out_unlock: + mutex_unlock(&isl7998x->lock); + pm_runtime_put(dev); + + return ret; +} + +static int isl7998x_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *std) +{ + *std = V4L2_STD_ALL; + + return 0; +} + +static int isl7998x_g_input_status(struct v4l2_subdev *sd, u32 *status) +{ + struct isl7998x *isl7998x = sd_to_isl7998x(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct device *dev = &client->dev; + unsigned int i; + int ret = 0; + u32 reg; + + if (!pm_runtime_active(dev)) { + *status |= V4L2_IN_ST_NO_POWER; + return 0; + } + + for (i = 0; i < isl7998x->nr_inputs; i++) { + ret = regmap_read(isl7998x->regmap, + ISL7998X_REG_PX_DEC_STATUS_1(i + 1), ®); + if (!ret) { + if (reg & ISL7998X_REG_PX_DEC_STATUS_1_VDLOSS) + *status |= V4L2_IN_ST_NO_SIGNAL; + if (!(reg & ISL7998X_REG_PX_DEC_STATUS_1_HLOCK)) + *status |= V4L2_IN_ST_NO_H_LOCK; + if (!(reg & ISL7998X_REG_PX_DEC_STATUS_1_VLOCK)) + *status |= V4L2_IN_ST_NO_V_LOCK; + } + } + + return ret; +} + +static int isl7998x_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct isl7998x *isl7998x = sd_to_isl7998x(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct device *dev = &client->dev; + int ret = 0; + u32 reg; + + dev_dbg(dev, "stream %s\n", enable ? "ON" : "OFF"); + + mutex_lock(&isl7998x->lock); + if (isl7998x->enabled == enable) + goto out; + isl7998x->enabled = enable; + + if (enable) { + ret = isl7998x_set_test_pattern(isl7998x); + if (ret) + goto out; + } + + regmap_read(isl7998x->regmap, + ISL7998X_REG_P5_LI_ENGINE_CTL, ®); + if (enable) + reg &= ~BIT(7); + else + reg |= BIT(7); + ret = regmap_write(isl7998x->regmap, + ISL7998X_REG_P5_LI_ENGINE_CTL, reg); + +out: + mutex_unlock(&isl7998x->lock); + + return ret; +} + +static int isl7998x_pre_streamon(struct v4l2_subdev *sd, u32 flags) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct device *dev = &client->dev; + + return pm_runtime_resume_and_get(dev); +} + +static int isl7998x_post_streamoff(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct device *dev = &client->dev; + + pm_runtime_put(dev); + + return 0; +} + +static int isl7998x_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= ARRAY_SIZE(isl7998x_colour_fmts)) + return -EINVAL; + + code->code = isl7998x_colour_fmts[code->index].code; + + return 0; +} + +static int isl7998x_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + if (fse->index >= ARRAY_SIZE(supported_modes)) + return -EINVAL; + + if (fse->code != isl7998x_colour_fmts[0].code) + return -EINVAL; + + fse->min_width = supported_modes[fse->index].width; + fse->max_width = fse->min_width; + fse->min_height = supported_modes[fse->index].height; + fse->max_height = fse->min_height; + + return 0; +} + +static int isl7998x_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + struct isl7998x *isl7998x = sd_to_isl7998x(sd); + struct v4l2_mbus_framefmt *mf = &format->format; + const struct isl7998x_mode *mode; + + mutex_lock(&isl7998x->lock); + + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + format->format = *v4l2_subdev_get_try_format(sd, sd_state, + format->pad); + goto out; + } + + mode = isl7998x_norm_to_mode(isl7998x->norm); + + mf->width = mode->width; + mf->height = mode->height; + mf->code = isl7998x->fmt->code; + mf->field = mode->field; + mf->colorspace = 0; + +out: + mutex_unlock(&isl7998x->lock); + + return 0; +} + +static int isl7998x_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *format) +{ + struct isl7998x *isl7998x = sd_to_isl7998x(sd); + struct v4l2_mbus_framefmt *mf = &format->format; + const struct isl7998x_mode *mode; + + mutex_lock(&isl7998x->lock); + + mode = isl7998x_norm_to_mode(isl7998x->norm); + + mf->width = mode->width; + mf->height = mode->height; + mf->code = isl7998x->fmt->code; + mf->field = mode->field; + + if (format->which == V4L2_SUBDEV_FORMAT_TRY) + *v4l2_subdev_get_try_format(sd, sd_state, format->pad) = format->format; + + mutex_unlock(&isl7998x->lock); + + return 0; +} + +static int isl7998x_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct isl7998x *isl7998x = container_of(ctrl->handler, + struct isl7998x, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_TEST_PATTERN_BARS: + mutex_lock(&isl7998x->lock); + isl7998x->test_pattern_bars = ctrl->val & 0x3; + ret = isl7998x_set_test_pattern(isl7998x); + mutex_unlock(&isl7998x->lock); + break; + case V4L2_CID_TEST_PATTERN_CHANNELS: + mutex_lock(&isl7998x->lock); + isl7998x->test_pattern_chans = ctrl->val & 0xf; + ret = isl7998x_set_test_pattern(isl7998x); + mutex_unlock(&isl7998x->lock); + break; + case V4L2_CID_TEST_PATTERN_COLOR: + mutex_lock(&isl7998x->lock); + isl7998x->test_pattern_color = ctrl->val & 0x3; + ret = isl7998x_set_test_pattern(isl7998x); + mutex_unlock(&isl7998x->lock); + break; + case V4L2_CID_TEST_PATTERN: + mutex_lock(&isl7998x->lock); + isl7998x->test_pattern = ctrl->val; + ret = isl7998x_set_test_pattern(isl7998x); + mutex_unlock(&isl7998x->lock); + break; + } + + return ret; +} + +static const struct v4l2_subdev_core_ops isl7998x_subdev_core_ops = { +#ifdef CONFIG_VIDEO_ADV_DEBUG + .g_register = isl7998x_g_register, + .s_register = isl7998x_s_register, +#endif +}; + +static const struct v4l2_subdev_video_ops isl7998x_subdev_video_ops = { + .g_std = isl7998x_g_std, + .s_std = isl7998x_s_std, + .querystd = isl7998x_querystd, + .g_tvnorms = isl7998x_g_tvnorms, + .g_input_status = isl7998x_g_input_status, + .s_stream = isl7998x_s_stream, + .pre_streamon = isl7998x_pre_streamon, + .post_streamoff = isl7998x_post_streamoff, +}; + +static const struct v4l2_subdev_pad_ops isl7998x_subdev_pad_ops = { + .enum_mbus_code = isl7998x_enum_mbus_code, + .enum_frame_size = isl7998x_enum_frame_size, + .get_fmt = isl7998x_get_fmt, + .set_fmt = isl7998x_set_fmt, +}; + +static const struct v4l2_subdev_ops isl7998x_subdev_ops = { + .core = &isl7998x_subdev_core_ops, + .video = &isl7998x_subdev_video_ops, + .pad = &isl7998x_subdev_pad_ops, +}; + +static const struct media_entity_operations isl7998x_entity_ops = { + .link_validate = v4l2_subdev_link_validate, +}; + +static const struct v4l2_ctrl_ops isl7998x_ctrl_ops = { + .s_ctrl = isl7998x_set_ctrl, +}; + +static const struct v4l2_ctrl_config isl7998x_ctrls[] = { + { + .ops = &isl7998x_ctrl_ops, + .id = V4L2_CID_TEST_PATTERN_BARS, + .type = V4L2_CTRL_TYPE_MENU, + .name = "Test Pattern Bars", + .max = ARRAY_SIZE(isl7998x_test_pattern_bars) - 1, + .def = 0, + .qmenu = isl7998x_test_pattern_bars, + }, { + .ops = &isl7998x_ctrl_ops, + .id = V4L2_CID_TEST_PATTERN_CHANNELS, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test Pattern Channels", + .min = 0, + .max = 0xf, + .step = 1, + .def = 0xf, + .flags = 0, + }, { + .ops = &isl7998x_ctrl_ops, + .id = V4L2_CID_TEST_PATTERN_COLOR, + .type = V4L2_CTRL_TYPE_MENU, + .name = "Test Pattern Color", + .max = ARRAY_SIZE(isl7998x_test_pattern_colors) - 1, + .def = 0, + .qmenu = isl7998x_test_pattern_colors, + }, +}; + +#define ISL7998X_REG_DECODER_ACA_READABLE_RANGE(page) \ + /* Decoder range */ \ + regmap_reg_range(ISL7998X_REG_PX_DEC_INPUT_FMT(page), \ + ISL7998X_REG_PX_DEC_HS_DELAY_CTL(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_ANCTL(page), \ + ISL7998X_REG_PX_DEC_CSC_CTL(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_BRIGHT(page), \ + ISL7998X_REG_PX_DEC_HUE(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_VERT_PEAK(page), \ + ISL7998X_REG_PX_DEC_CORING(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_SDT(page), \ + ISL7998X_REG_PX_DEC_SDTR(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_CLMPG(page), \ + ISL7998X_REG_PX_DEC_DATA_CONV(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_INTERNAL_TEST(page), \ + ISL7998X_REG_PX_DEC_INTERNAL_TEST(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_H_DELAY_CTL(page), \ + ISL7998X_REG_PX_DEC_H_DELAY_II_LOW(page)), \ + /* ACA range */ \ + regmap_reg_range(ISL7998X_REG_PX_ACA_CTL_1(page), \ + ISL7998X_REG_PX_ACA_HIST_WIN_V_SZ2(page)), \ + regmap_reg_range(ISL7998X_REG_PX_ACA_Y_AVG(page), \ + ISL7998X_REG_PX_ACA_CTL_4(page)), \ + regmap_reg_range(ISL7998X_REG_PX_ACA_FLEX_WIN_HIST(page), \ + ISL7998X_REG_PX_ACA_XFER_HIST_HOST(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_PAGE(page), \ + ISL7998X_REG_PX_DEC_PAGE(page)) + +#define ISL7998X_REG_DECODER_ACA_WRITEABLE_RANGE(page) \ + /* Decoder range */ \ + regmap_reg_range(ISL7998X_REG_PX_DEC_INPUT_FMT(page), \ + ISL7998X_REG_PX_DEC_INPUT_FMT(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_HS_DELAY_CTL(page), \ + ISL7998X_REG_PX_DEC_HS_DELAY_CTL(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_ANCTL(page), \ + ISL7998X_REG_PX_DEC_CSC_CTL(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_BRIGHT(page), \ + ISL7998X_REG_PX_DEC_HUE(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_VERT_PEAK(page), \ + ISL7998X_REG_PX_DEC_CORING(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_SDT(page), \ + ISL7998X_REG_PX_DEC_SDTR(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_CLMPG(page), \ + ISL7998X_REG_PX_DEC_MISC3(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_CLMD(page), \ + ISL7998X_REG_PX_DEC_DATA_CONV(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_INTERNAL_TEST(page), \ + ISL7998X_REG_PX_DEC_INTERNAL_TEST(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_H_DELAY_CTL(page), \ + ISL7998X_REG_PX_DEC_H_DELAY_II_LOW(page)), \ + /* ACA range */ \ + regmap_reg_range(ISL7998X_REG_PX_ACA_CTL_1(page), \ + ISL7998X_REG_PX_ACA_HIST_WIN_V_SZ2(page)), \ + regmap_reg_range(ISL7998X_REG_PX_ACA_CTL_2(page), \ + ISL7998X_REG_PX_ACA_CTL_4(page)), \ + regmap_reg_range(ISL7998X_REG_PX_ACA_FLEX_WIN_HIST(page), \ + ISL7998X_REG_PX_ACA_HIST_DATA_LO(page)), \ + regmap_reg_range(ISL7998X_REG_PX_ACA_XFER_HIST_HOST(page), \ + ISL7998X_REG_PX_ACA_XFER_HIST_HOST(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_PAGE(page), \ + ISL7998X_REG_PX_DEC_PAGE(page)) + +#define ISL7998X_REG_DECODER_ACA_VOLATILE_RANGE(page) \ + /* Decoder range */ \ + regmap_reg_range(ISL7998X_REG_PX_DEC_STATUS_1(page), \ + ISL7998X_REG_PX_DEC_STATUS_1(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_SDT(page), \ + ISL7998X_REG_PX_DEC_SDT(page)), \ + regmap_reg_range(ISL7998X_REG_PX_DEC_MVSN(page), \ + ISL7998X_REG_PX_DEC_HFREF(page)), \ + /* ACA range */ \ + regmap_reg_range(ISL7998X_REG_PX_ACA_Y_AVG(page), \ + ISL7998X_REG_PX_ACA_Y_HIGH(page)), \ + regmap_reg_range(ISL7998X_REG_PX_ACA_HIST_DATA_LO(page), \ + ISL7998X_REG_PX_ACA_FLEX_WIN_CR_CLR(page)) + +static const struct regmap_range isl7998x_readable_ranges[] = { + regmap_reg_range(ISL7998X_REG_P0_PRODUCT_ID_CODE, + ISL7998X_REG_P0_IRQ_SYNC_CTL), + regmap_reg_range(ISL7998X_REG_P0_INTERRUPT_STATUS, + ISL7998X_REG_P0_CLOCK_DELAY), + regmap_reg_range(ISL7998X_REG_PX_DEC_PAGE(0), + ISL7998X_REG_PX_DEC_PAGE(0)), + + ISL7998X_REG_DECODER_ACA_READABLE_RANGE(1), + ISL7998X_REG_DECODER_ACA_READABLE_RANGE(2), + ISL7998X_REG_DECODER_ACA_READABLE_RANGE(3), + ISL7998X_REG_DECODER_ACA_READABLE_RANGE(4), + + regmap_reg_range(ISL7998X_REG_P5_LI_ENGINE_CTL, + ISL7998X_REG_P5_MIPI_SP_HS_TRL_CTL), + regmap_reg_range(ISL7998X_REG_P5_FIFO_THRSH_CNT_1, + ISL7998X_REG_P5_PLL_ANA), + regmap_reg_range(ISL7998X_REG_P5_TOTAL_PF_LINE_CNT_1, + ISL7998X_REG_P5_HIST_LINE_CNT_2), + regmap_reg_range(ISL7998X_REG_PX_DEC_PAGE(5), + ISL7998X_REG_PX_DEC_PAGE(5)), +}; + +static const struct regmap_range isl7998x_writeable_ranges[] = { + regmap_reg_range(ISL7998X_REG_P0_SW_RESET_CTL, + ISL7998X_REG_P0_IRQ_SYNC_CTL), + regmap_reg_range(ISL7998X_REG_P0_CHAN_1_IRQ, + ISL7998X_REG_P0_SHORT_DIAG_IRQ_EN), + regmap_reg_range(ISL7998X_REG_P0_CLOCK_DELAY, + ISL7998X_REG_P0_CLOCK_DELAY), + regmap_reg_range(ISL7998X_REG_PX_DEC_PAGE(0), + ISL7998X_REG_PX_DEC_PAGE(0)), + + ISL7998X_REG_DECODER_ACA_WRITEABLE_RANGE(1), + ISL7998X_REG_DECODER_ACA_WRITEABLE_RANGE(2), + ISL7998X_REG_DECODER_ACA_WRITEABLE_RANGE(3), + ISL7998X_REG_DECODER_ACA_WRITEABLE_RANGE(4), + + regmap_reg_range(ISL7998X_REG_P5_LI_ENGINE_CTL, + ISL7998X_REG_P5_ESC_MODE_TIME_CTL), + regmap_reg_range(ISL7998X_REG_P5_MIPI_SP_HS_TRL_CTL, + ISL7998X_REG_P5_PLL_ANA), + regmap_reg_range(ISL7998X_REG_P5_TOTAL_PF_LINE_CNT_1, + ISL7998X_REG_P5_HIST_LINE_CNT_2), + regmap_reg_range(ISL7998X_REG_PX_DEC_PAGE(5), + ISL7998X_REG_PX_DEC_PAGE(5)), + + ISL7998X_REG_DECODER_ACA_WRITEABLE_RANGE(0xf), +}; + +static const struct regmap_range isl7998x_volatile_ranges[] = { + /* Product id code register is used to check availability */ + regmap_reg_range(ISL7998X_REG_P0_PRODUCT_ID_CODE, + ISL7998X_REG_P0_PRODUCT_ID_CODE), + regmap_reg_range(ISL7998X_REG_P0_MPP1_SYNC_CTL, + ISL7998X_REG_P0_IRQ_SYNC_CTL), + regmap_reg_range(ISL7998X_REG_P0_INTERRUPT_STATUS, + ISL7998X_REG_P0_INTERRUPT_STATUS), + regmap_reg_range(ISL7998X_REG_P0_CHAN_1_STATUS, + ISL7998X_REG_P0_SHORT_DIAG_STATUS), + + ISL7998X_REG_DECODER_ACA_VOLATILE_RANGE(1), + ISL7998X_REG_DECODER_ACA_VOLATILE_RANGE(2), + ISL7998X_REG_DECODER_ACA_VOLATILE_RANGE(3), + ISL7998X_REG_DECODER_ACA_VOLATILE_RANGE(4), + + regmap_reg_range(ISL7998X_REG_P5_AUTO_TEST_ERR_DET, + ISL7998X_REG_P5_PIC_HEIGHT_LOW), +}; + +static const struct regmap_access_table isl7998x_readable_table = { + .yes_ranges = isl7998x_readable_ranges, + .n_yes_ranges = ARRAY_SIZE(isl7998x_readable_ranges), +}; + +static const struct regmap_access_table isl7998x_writeable_table = { + .yes_ranges = isl7998x_writeable_ranges, + .n_yes_ranges = ARRAY_SIZE(isl7998x_writeable_ranges), +}; + +static const struct regmap_access_table isl7998x_volatile_table = { + .yes_ranges = isl7998x_volatile_ranges, + .n_yes_ranges = ARRAY_SIZE(isl7998x_volatile_ranges), +}; + +static const struct regmap_range_cfg isl7998x_ranges[] = { + { + .range_min = ISL7998X_REG_PN_BASE(0), + .range_max = ISL7998X_REG_PX_ACA_XFER_HIST_HOST(0xf), + .selector_reg = ISL7998X_REG_PX_DEC_PAGE(0), + .selector_mask = ISL7998X_REG_PX_DEC_PAGE_MASK, + .window_start = 0, + .window_len = 256, + } +}; + +static const struct regmap_config isl7998x_regmap = { + .reg_bits = 8, + .val_bits = 8, + .max_register = ISL7998X_REG_PX_ACA_XFER_HIST_HOST(0xf), + .ranges = isl7998x_ranges, + .num_ranges = ARRAY_SIZE(isl7998x_ranges), + .rd_table = &isl7998x_readable_table, + .wr_table = &isl7998x_writeable_table, + .volatile_table = &isl7998x_volatile_table, + .cache_type = REGCACHE_RBTREE, +}; + +static int isl7998x_mc_init(struct isl7998x *isl7998x) +{ + unsigned int i; + + isl7998x->subdev.entity.ops = &isl7998x_entity_ops; + isl7998x->subdev.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; + + isl7998x->pads[ISL7998X_PAD_OUT].flags = MEDIA_PAD_FL_SOURCE; + for (i = ISL7998X_PAD_VIN1; i < ISL7998X_NUM_PADS; i++) + isl7998x->pads[i].flags = MEDIA_PAD_FL_SINK; + + return media_entity_pads_init(&isl7998x->subdev.entity, + ISL7998X_NUM_PADS, + isl7998x->pads); +} + +static int get_link_freq_menu_index(unsigned int lanes, + unsigned int inputs) +{ + int ret = -EINVAL; + + switch (lanes) { + case 1: + if (inputs == 1) + ret = 0; + if (inputs == 2) + ret = 1; + if (inputs == 4) + ret = 2; + break; + case 2: + if (inputs == 2) + ret = 0; + if (inputs == 4) + ret = 1; + break; + default: + break; + } + + return ret; +} + +static void isl7998x_remove_controls(struct isl7998x *isl7998x) +{ + v4l2_ctrl_handler_free(&isl7998x->ctrl_handler); + mutex_destroy(&isl7998x->ctrl_mutex); +} + +static int isl7998x_init_controls(struct isl7998x *isl7998x) +{ + struct v4l2_subdev *sd = &isl7998x->subdev; + int link_freq_index; + unsigned int i; + int ret; + + ret = v4l2_ctrl_handler_init(&isl7998x->ctrl_handler, + 2 + ARRAY_SIZE(isl7998x_ctrls)); + if (ret) + return ret; + + mutex_init(&isl7998x->ctrl_mutex); + isl7998x->ctrl_handler.lock = &isl7998x->ctrl_mutex; + link_freq_index = get_link_freq_menu_index(isl7998x->nr_mipi_lanes, + isl7998x->nr_inputs); + if (link_freq_index < 0 || + link_freq_index >= ARRAY_SIZE(link_freq_menu_items)) { + dev_err(sd->dev, + "failed to find MIPI link freq: %d lanes, %d inputs\n", + isl7998x->nr_mipi_lanes, isl7998x->nr_inputs); + ret = -EINVAL; + goto err; + } + + isl7998x->link_freq = v4l2_ctrl_new_int_menu(&isl7998x->ctrl_handler, + &isl7998x_ctrl_ops, + V4L2_CID_LINK_FREQ, + ARRAY_SIZE(link_freq_menu_items) - 1, + link_freq_index, + link_freq_menu_items); + if (isl7998x->link_freq) + isl7998x->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + for (i = 0; i < ARRAY_SIZE(isl7998x_ctrls); i++) + v4l2_ctrl_new_custom(&isl7998x->ctrl_handler, + &isl7998x_ctrls[i], NULL); + + v4l2_ctrl_new_std_menu_items(&isl7998x->ctrl_handler, + &isl7998x_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(isl7998x_test_pattern_menu) - 1, + 0, 0, isl7998x_test_pattern_menu); + + ret = isl7998x->ctrl_handler.error; + if (ret) + goto err; + + isl7998x->subdev.ctrl_handler = &isl7998x->ctrl_handler; + v4l2_ctrl_handler_setup(&isl7998x->ctrl_handler); + + return 0; + +err: + isl7998x_remove_controls(isl7998x); + + return ret; +} + +static int isl7998x_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct v4l2_fwnode_endpoint endpoint = { + .bus_type = V4L2_MBUS_CSI2_DPHY, + }; + struct fwnode_handle *ep; + struct isl7998x *isl7998x; + struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); + int nr_inputs; + int ret; + + ret = i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA); + if (!ret) { + dev_warn(&adapter->dev, + "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n"); + return -EIO; + } + + isl7998x = devm_kzalloc(dev, sizeof(*isl7998x), GFP_KERNEL); + if (!isl7998x) + return -ENOMEM; + + isl7998x->pd_gpio = devm_gpiod_get_optional(dev, "powerdown", + GPIOD_OUT_HIGH); + if (IS_ERR(isl7998x->pd_gpio)) + return dev_err_probe(dev, PTR_ERR(isl7998x->pd_gpio), + "Failed to retrieve/request PD GPIO\n"); + + isl7998x->rstb_gpio = devm_gpiod_get_optional(dev, "reset", + GPIOD_OUT_HIGH); + if (IS_ERR(isl7998x->rstb_gpio)) + return dev_err_probe(dev, PTR_ERR(isl7998x->rstb_gpio), + "Failed to retrieve/request RSTB GPIO\n"); + + isl7998x->regmap = devm_regmap_init_i2c(client, &isl7998x_regmap); + if (IS_ERR(isl7998x->regmap)) + return dev_err_probe(dev, PTR_ERR(isl7998x->regmap), + "Failed to allocate register map\n"); + + ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), + ISL7998X_PAD_OUT, 0, 0); + if (!ep) + return dev_err_probe(dev, -EINVAL, "Missing endpoint node\n"); + + ret = v4l2_fwnode_endpoint_parse(ep, &endpoint); + fwnode_handle_put(ep); + if (ret) + return dev_err_probe(dev, ret, "Failed to parse endpoint\n"); + + if (endpoint.bus.mipi_csi2.num_data_lanes == 0 || + endpoint.bus.mipi_csi2.num_data_lanes > 2) + return dev_err_probe(dev, -EINVAL, + "Invalid number of MIPI lanes\n"); + + isl7998x->nr_mipi_lanes = endpoint.bus.mipi_csi2.num_data_lanes; + + nr_inputs = isl7998x_get_nr_inputs(dev->of_node); + if (nr_inputs < 0) + return dev_err_probe(dev, nr_inputs, + "Invalid number of input ports\n"); + isl7998x->nr_inputs = nr_inputs; + + v4l2_i2c_subdev_init(&isl7998x->subdev, client, &isl7998x_subdev_ops); + isl7998x->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + + ret = isl7998x_mc_init(isl7998x); + if (ret < 0) + return ret; + + isl7998x->fmt = &isl7998x_colour_fmts[0]; + isl7998x->norm = V4L2_STD_NTSC; + isl7998x->enabled = 0; + + mutex_init(&isl7998x->lock); + + ret = isl7998x_init_controls(isl7998x); + if (ret) + goto err_entity_cleanup; + + ret = v4l2_async_register_subdev(&isl7998x->subdev); + if (ret < 0) + goto err_controls_cleanup; + + pm_runtime_enable(dev); + + return 0; + +err_controls_cleanup: + isl7998x_remove_controls(isl7998x); +err_entity_cleanup: + media_entity_cleanup(&isl7998x->subdev.entity); + + return ret; +} + +static int isl7998x_remove(struct i2c_client *client) +{ + struct isl7998x *isl7998x = i2c_to_isl7998x(client); + + pm_runtime_disable(&client->dev); + v4l2_async_unregister_subdev(&isl7998x->subdev); + isl7998x_remove_controls(isl7998x); + media_entity_cleanup(&isl7998x->subdev.entity); + + return 0; +} + +static const struct of_device_id isl7998x_of_match[] = { + { .compatible = "isil,isl79987", }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, isl7998x_of_match); + +static const struct i2c_device_id isl7998x_id[] = { + { "isl79987", 0 }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(i2c, isl7998x_id); + +static int __maybe_unused isl7998x_runtime_resume(struct device *dev) +{ + struct v4l2_subdev *sd = dev_get_drvdata(dev); + struct isl7998x *isl7998x = sd_to_isl7998x(sd); + int ret; + + gpiod_set_value(isl7998x->rstb_gpio, 1); + gpiod_set_value(isl7998x->pd_gpio, 0); + gpiod_set_value(isl7998x->rstb_gpio, 0); + + ret = isl7998x_wait_power_on(isl7998x); + if (ret) + goto err; + + ret = isl7998x_init(isl7998x); + if (ret) + goto err; + + return 0; + +err: + gpiod_set_value(isl7998x->pd_gpio, 1); + + return ret; +} + +static int __maybe_unused isl7998x_runtime_suspend(struct device *dev) +{ + struct v4l2_subdev *sd = dev_get_drvdata(dev); + struct isl7998x *isl7998x = sd_to_isl7998x(sd); + + gpiod_set_value(isl7998x->pd_gpio, 1); + + return 0; +} + +static const struct dev_pm_ops isl7998x_pm_ops = { + SET_RUNTIME_PM_OPS(isl7998x_runtime_suspend, + isl7998x_runtime_resume, + NULL) +}; + +static struct i2c_driver isl7998x_i2c_driver = { + .driver = { + .name = "isl7998x", + .of_match_table = of_match_ptr(isl7998x_of_match), + .pm = &isl7998x_pm_ops, + }, + .probe_new = isl7998x_probe, + .remove = isl7998x_remove, + .id_table = isl7998x_id, +}; + +module_i2c_driver(isl7998x_i2c_driver); + +MODULE_DESCRIPTION("Intersil ISL7998x Analog to MIPI CSI-2/BT656 decoder"); +MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/media/i2c/m5mols/Kconfig b/drivers/media/i2c/m5mols/Kconfig index 6f0ef33b7ee1..7f0af32f4376 100644 --- a/drivers/media/i2c/m5mols/Kconfig +++ b/drivers/media/i2c/m5mols/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only config VIDEO_M5MOLS tristate "Fujitsu M-5MOLS 8MP sensor support" - depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_DEV select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API help diff --git a/drivers/media/i2c/m5mols/m5mols.h b/drivers/media/i2c/m5mols/m5mols.h index 60c102fa7df5..d8545d2280af 100644 --- a/drivers/media/i2c/m5mols/m5mols.h +++ b/drivers/media/i2c/m5mols/m5mols.h @@ -13,6 +13,7 @@ #define M5MOLS_H #include <linux/sizes.h> +#include <linux/gpio/consumer.h> #include <media/v4l2-subdev.h> #include "m5mols_reg.h" @@ -181,6 +182,7 @@ struct m5mols_version { * @stabilization: image stabilization control * @jpeg_quality: JPEG compression quality control * @set_power: optional power callback to the board code + * @reset: GPIO driving the reset pin of M-5MOLS * @lock: mutex protecting the structure fields below * @ffmt: current fmt according to resolution type * @res_type: current resolution type @@ -224,6 +226,7 @@ struct m5mols_info { struct v4l2_ctrl *jpeg_quality; int (*set_power)(struct device *dev, int on); + struct gpio_desc *reset; struct mutex lock; diff --git a/drivers/media/i2c/m5mols/m5mols_capture.c b/drivers/media/i2c/m5mols/m5mols_capture.c index e1b1d689c044..275c5b2539fd 100644 --- a/drivers/media/i2c/m5mols/m5mols_capture.c +++ b/drivers/media/i2c/m5mols/m5mols_capture.c @@ -15,7 +15,6 @@ #include <linux/irq.h> #include <linux/interrupt.h> #include <linux/delay.h> -#include <linux/gpio.h> #include <linux/regulator/consumer.h> #include <linux/videodev2.h> #include <media/v4l2-ctrls.h> diff --git a/drivers/media/i2c/m5mols/m5mols_core.c b/drivers/media/i2c/m5mols/m5mols_core.c index e29be0242f07..c19590389bfe 100644 --- a/drivers/media/i2c/m5mols/m5mols_core.c +++ b/drivers/media/i2c/m5mols/m5mols_core.c @@ -14,7 +14,7 @@ #include <linux/irq.h> #include <linux/interrupt.h> #include <linux/delay.h> -#include <linux/gpio.h> +#include <linux/gpio/consumer.h> #include <linux/regulator/consumer.h> #include <linux/videodev2.h> #include <linux/module.h> @@ -752,7 +752,6 @@ static int m5mols_sensor_power(struct m5mols_info *info, bool enable) { struct v4l2_subdev *sd = &info->sd; struct i2c_client *client = v4l2_get_subdevdata(sd); - const struct m5mols_platform_data *pdata = info->pdata; int ret; if (info->power == enable) @@ -772,7 +771,7 @@ static int m5mols_sensor_power(struct m5mols_info *info, bool enable) return ret; } - gpio_set_value(pdata->gpio_reset, !pdata->reset_polarity); + gpiod_set_value(info->reset, 0); info->power = 1; return ret; @@ -785,7 +784,7 @@ static int m5mols_sensor_power(struct m5mols_info *info, bool enable) if (info->set_power) info->set_power(&client->dev, 0); - gpio_set_value(pdata->gpio_reset, pdata->reset_polarity); + gpiod_set_value(info->reset, 1); info->isp_ready = 0; info->power = 0; @@ -944,7 +943,6 @@ static int m5mols_probe(struct i2c_client *client, const struct i2c_device_id *id) { const struct m5mols_platform_data *pdata = client->dev.platform_data; - unsigned long gpio_flags; struct m5mols_info *info; struct v4l2_subdev *sd; int ret; @@ -954,11 +952,6 @@ static int m5mols_probe(struct i2c_client *client, return -EINVAL; } - if (!gpio_is_valid(pdata->gpio_reset)) { - dev_err(&client->dev, "No valid RESET GPIO specified\n"); - return -EINVAL; - } - if (!client->irq) { dev_err(&client->dev, "Interrupt not assigned\n"); return -EINVAL; @@ -968,18 +961,16 @@ static int m5mols_probe(struct i2c_client *client, if (!info) return -ENOMEM; + /* This asserts reset, descriptor shall have polarity specified */ + info->reset = devm_gpiod_get(&client->dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(info->reset)) + return PTR_ERR(info->reset); + /* Notice: the "N" in M5MOLS_NRST implies active low */ + gpiod_set_consumer_name(info->reset, "M5MOLS_NRST"); + info->pdata = pdata; info->set_power = pdata->set_power; - gpio_flags = pdata->reset_polarity - ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW; - ret = devm_gpio_request_one(&client->dev, pdata->gpio_reset, gpio_flags, - "M5MOLS_NRST"); - if (ret) { - dev_err(&client->dev, "Failed to request gpio: %d\n", ret); - return ret; - } - ret = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(supplies), supplies); if (ret) { diff --git a/drivers/media/i2c/max2175.c b/drivers/media/i2c/max2175.c index bc46a0957b40..0eea200124d2 100644 --- a/drivers/media/i2c/max2175.c +++ b/drivers/media/i2c/max2175.c @@ -257,7 +257,7 @@ static const struct regmap_config max2175_regmap_config = { .reg_defaults = max2175_reg_defaults, .num_reg_defaults = ARRAY_SIZE(max2175_reg_defaults), .volatile_table = &max2175_volatile_regs, - .cache_type = REGCACHE_FLAT, + .cache_type = REGCACHE_RBTREE, }; struct max2175 { diff --git a/drivers/media/i2c/max9286.c b/drivers/media/i2c/max9286.c index eb2b8e42335b..d2a4915ed9f7 100644 --- a/drivers/media/i2c/max9286.c +++ b/drivers/media/i2c/max9286.c @@ -15,6 +15,7 @@ #include <linux/fwnode.h> #include <linux/gpio/consumer.h> #include <linux/gpio/driver.h> +#include <linux/gpio/machine.h> #include <linux/i2c.h> #include <linux/i2c-mux.h> #include <linux/module.h> @@ -168,6 +169,8 @@ struct max9286_priv { u32 init_rev_chan_mv; u32 rev_chan_mv; + u32 gpio_poc[2]; + struct v4l2_ctrl_handler ctrls; struct v4l2_ctrl *pixelrate; @@ -846,6 +849,10 @@ static const struct v4l2_subdev_internal_ops max9286_subdev_internal_ops = { .open = max9286_open, }; +static const struct media_entity_operations max9286_media_ops = { + .link_validate = v4l2_subdev_link_validate +}; + static int max9286_s_ctrl(struct v4l2_ctrl *ctrl) { switch (ctrl->id) { @@ -895,6 +902,7 @@ static int max9286_v4l2_register(struct max9286_priv *priv) goto err_async; priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; + priv->sd.entity.ops = &max9286_media_ops; priv->pads[MAX9286_SRC_PAD].flags = MEDIA_PAD_FL_SOURCE; for (i = 0; i < MAX9286_SRC_PAD; i++) @@ -1025,20 +1033,27 @@ static int max9286_setup(struct max9286_priv *priv) return 0; } -static void max9286_gpio_set(struct gpio_chip *chip, - unsigned int offset, int value) +static int max9286_gpio_set(struct max9286_priv *priv, unsigned int offset, + int value) { - struct max9286_priv *priv = gpiochip_get_data(chip); - if (value) priv->gpio_state |= BIT(offset); else priv->gpio_state &= ~BIT(offset); - max9286_write(priv, 0x0f, MAX9286_0X0F_RESERVED | priv->gpio_state); + return max9286_write(priv, 0x0f, + MAX9286_0X0F_RESERVED | priv->gpio_state); +} + +static void max9286_gpiochip_set(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct max9286_priv *priv = gpiochip_get_data(chip); + + max9286_gpio_set(priv, offset, value); } -static int max9286_gpio_get(struct gpio_chip *chip, unsigned int offset) +static int max9286_gpiochip_get(struct gpio_chip *chip, unsigned int offset) { struct max9286_priv *priv = gpiochip_get_data(chip); @@ -1057,13 +1072,10 @@ static int max9286_register_gpio(struct max9286_priv *priv) gpio->owner = THIS_MODULE; gpio->ngpio = 2; gpio->base = -1; - gpio->set = max9286_gpio_set; - gpio->get = max9286_gpio_get; + gpio->set = max9286_gpiochip_set; + gpio->get = max9286_gpiochip_get; gpio->can_sleep = true; - /* GPIO values default to high */ - priv->gpio_state = BIT(0) | BIT(1); - ret = devm_gpiochip_add_data(dev, gpio, priv); if (ret) dev_err(dev, "Unable to create gpio_chip\n"); @@ -1071,6 +1083,70 @@ static int max9286_register_gpio(struct max9286_priv *priv) return ret; } +static int max9286_parse_gpios(struct max9286_priv *priv) +{ + struct device *dev = &priv->client->dev; + int ret; + + /* GPIO values default to high */ + priv->gpio_state = BIT(0) | BIT(1); + + /* + * Parse the "gpio-poc" vendor property. If the property is not + * specified the camera power is controlled by a regulator. + */ + ret = of_property_read_u32_array(dev->of_node, "maxim,gpio-poc", + priv->gpio_poc, 2); + if (ret == -EINVAL) { + /* + * If gpio lines are not used for the camera power, register + * a gpio controller for consumers. + */ + ret = max9286_register_gpio(priv); + if (ret) + return ret; + + priv->regulator = devm_regulator_get(dev, "poc"); + if (IS_ERR(priv->regulator)) { + return dev_err_probe(dev, PTR_ERR(priv->regulator), + "Unable to get PoC regulator (%ld)\n", + PTR_ERR(priv->regulator)); + } + + return 0; + } + + /* If the property is specified make sure it is well formed. */ + if (ret || priv->gpio_poc[0] > 1 || + (priv->gpio_poc[1] != GPIO_ACTIVE_HIGH && + priv->gpio_poc[1] != GPIO_ACTIVE_LOW)) { + dev_err(dev, "Invalid 'gpio-poc' property\n"); + return -EINVAL; + } + + return 0; +} + +static int max9286_poc_enable(struct max9286_priv *priv, bool enable) +{ + int ret; + + /* If the regulator is not available, use gpio to control power. */ + if (!priv->regulator) + ret = max9286_gpio_set(priv, priv->gpio_poc[0], + enable ^ priv->gpio_poc[1]); + else if (enable) + ret = regulator_enable(priv->regulator); + else + ret = regulator_disable(priv->regulator); + + if (ret < 0) + dev_err(&priv->client->dev, "Unable to turn power %s\n", + enable ? "on" : "off"); + + return ret; +} + static int max9286_init(struct device *dev) { struct max9286_priv *priv; @@ -1080,17 +1156,14 @@ static int max9286_init(struct device *dev) client = to_i2c_client(dev); priv = i2c_get_clientdata(client); - /* Enable the bus power. */ - ret = regulator_enable(priv->regulator); - if (ret < 0) { - dev_err(&client->dev, "Unable to turn PoC on\n"); + ret = max9286_poc_enable(priv, true); + if (ret) return ret; - } ret = max9286_setup(priv); if (ret) { dev_err(dev, "Unable to setup max9286\n"); - goto err_regulator; + goto err_poc_disable; } /* @@ -1100,7 +1173,7 @@ static int max9286_init(struct device *dev) ret = max9286_v4l2_register(priv); if (ret) { dev_err(dev, "Failed to register with V4L2\n"); - goto err_regulator; + goto err_poc_disable; } ret = max9286_i2c_mux_init(priv); @@ -1116,8 +1189,8 @@ static int max9286_init(struct device *dev) err_v4l2_register: max9286_v4l2_unregister(priv); -err_regulator: - regulator_disable(priv->regulator); +err_poc_disable: + max9286_poc_enable(priv, false); return ret; } @@ -1288,18 +1361,10 @@ static int max9286_probe(struct i2c_client *client) */ max9286_configure_i2c(priv, false); - ret = max9286_register_gpio(priv); + ret = max9286_parse_gpios(priv); if (ret) goto err_powerdown; - priv->regulator = devm_regulator_get(&client->dev, "poc"); - if (IS_ERR(priv->regulator)) { - ret = PTR_ERR(priv->regulator); - dev_err_probe(&client->dev, ret, - "Unable to get PoC regulator\n"); - goto err_powerdown; - } - ret = max9286_parse_dt(priv); if (ret) goto err_powerdown; @@ -1326,7 +1391,7 @@ static int max9286_remove(struct i2c_client *client) max9286_v4l2_unregister(priv); - regulator_disable(priv->regulator); + max9286_poc_enable(priv, false); gpiod_set_value_cansleep(priv->gpiod_pwdn, 0); diff --git a/drivers/media/i2c/ml86v7667.c b/drivers/media/i2c/ml86v7667.c index 4a1410ebb4c8..48cc0b0922f4 100644 --- a/drivers/media/i2c/ml86v7667.c +++ b/drivers/media/i2c/ml86v7667.c @@ -223,9 +223,10 @@ static int ml86v7667_get_mbus_config(struct v4l2_subdev *sd, unsigned int pad, struct v4l2_mbus_config *cfg) { - cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING | - V4L2_MBUS_DATA_ACTIVE_HIGH; cfg->type = V4L2_MBUS_BT656; + cfg->bus.parallel.flags = V4L2_MBUS_MASTER | + V4L2_MBUS_PCLK_SAMPLE_RISING | + V4L2_MBUS_DATA_ACTIVE_HIGH; return 0; } diff --git a/drivers/media/i2c/mt9m001.c b/drivers/media/i2c/mt9m001.c index c9f0bd997ea7..ad13b0c890c0 100644 --- a/drivers/media/i2c/mt9m001.c +++ b/drivers/media/i2c/mt9m001.c @@ -695,10 +695,12 @@ static int mt9m001_get_mbus_config(struct v4l2_subdev *sd, struct v4l2_mbus_config *cfg) { /* MT9M001 has all capture_format parameters fixed */ - cfg->flags = V4L2_MBUS_PCLK_SAMPLE_FALLING | - V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH | - V4L2_MBUS_DATA_ACTIVE_HIGH | V4L2_MBUS_MASTER; cfg->type = V4L2_MBUS_PARALLEL; + cfg->bus.parallel.flags = V4L2_MBUS_PCLK_SAMPLE_FALLING | + V4L2_MBUS_HSYNC_ACTIVE_HIGH | + V4L2_MBUS_VSYNC_ACTIVE_HIGH | + V4L2_MBUS_DATA_ACTIVE_HIGH | + V4L2_MBUS_MASTER; return 0; } diff --git a/drivers/media/i2c/mt9m111.c b/drivers/media/i2c/mt9m111.c index 91a44359bcd3..afc86efa9e3e 100644 --- a/drivers/media/i2c/mt9m111.c +++ b/drivers/media/i2c/mt9m111.c @@ -9,7 +9,6 @@ #include <linux/slab.h> #include <linux/i2c.h> #include <linux/log2.h> -#include <linux/gpio.h> #include <linux/delay.h> #include <linux/regulator/consumer.h> #include <linux/v4l2-mediabus.h> @@ -1143,14 +1142,16 @@ static int mt9m111_get_mbus_config(struct v4l2_subdev *sd, { struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev); - cfg->flags = V4L2_MBUS_MASTER | - V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH | - V4L2_MBUS_DATA_ACTIVE_HIGH; + cfg->type = V4L2_MBUS_PARALLEL; - cfg->flags |= mt9m111->pclk_sample ? V4L2_MBUS_PCLK_SAMPLE_RISING : - V4L2_MBUS_PCLK_SAMPLE_FALLING; + cfg->bus.parallel.flags = V4L2_MBUS_MASTER | + V4L2_MBUS_HSYNC_ACTIVE_HIGH | + V4L2_MBUS_VSYNC_ACTIVE_HIGH | + V4L2_MBUS_DATA_ACTIVE_HIGH; - cfg->type = V4L2_MBUS_PARALLEL; + cfg->bus.parallel.flags |= mt9m111->pclk_sample ? + V4L2_MBUS_PCLK_SAMPLE_RISING : + V4L2_MBUS_PCLK_SAMPLE_FALLING; return 0; } diff --git a/drivers/media/i2c/noon010pc30.c b/drivers/media/i2c/noon010pc30.c index f3ac379ef34a..bc5187f46365 100644 --- a/drivers/media/i2c/noon010pc30.c +++ b/drivers/media/i2c/noon010pc30.c @@ -10,7 +10,7 @@ */ #include <linux/delay.h> -#include <linux/gpio.h> +#include <linux/gpio/consumer.h> #include <linux/i2c.h> #include <linux/slab.h> #include <linux/regulator/consumer.h> @@ -130,8 +130,8 @@ struct noon010_info { struct media_pad pad; struct v4l2_ctrl_handler hdl; struct regulator_bulk_data supply[NOON010_NUM_SUPPLIES]; - u32 gpio_nreset; - u32 gpio_nstby; + struct gpio_desc *reset; + struct gpio_desc *stby; /* Protects the struct members below */ struct mutex lock; @@ -393,29 +393,33 @@ static int power_enable(struct noon010_info *info) return 0; } - if (gpio_is_valid(info->gpio_nstby)) - gpio_set_value(info->gpio_nstby, 0); + /* Assert standby: line should be flagged active low in descriptor */ + if (info->stby) + gpiod_set_value(info->stby, 1); - if (gpio_is_valid(info->gpio_nreset)) - gpio_set_value(info->gpio_nreset, 0); + /* Assert reset: line should be flagged active low in descriptor */ + if (info->reset) + gpiod_set_value(info->reset, 1); ret = regulator_bulk_enable(NOON010_NUM_SUPPLIES, info->supply); if (ret) return ret; - if (gpio_is_valid(info->gpio_nreset)) { + /* De-assert reset and standby */ + if (info->reset) { msleep(50); - gpio_set_value(info->gpio_nreset, 1); + gpiod_set_value(info->reset, 0); } - if (gpio_is_valid(info->gpio_nstby)) { + if (info->stby) { udelay(1000); - gpio_set_value(info->gpio_nstby, 1); + gpiod_set_value(info->stby, 0); } - if (gpio_is_valid(info->gpio_nreset)) { + /* Cycle reset: assert and deassert */ + if (info->reset) { udelay(1000); - gpio_set_value(info->gpio_nreset, 0); + gpiod_set_value(info->reset, 1); msleep(100); - gpio_set_value(info->gpio_nreset, 1); + gpiod_set_value(info->reset, 0); msleep(20); } info->power = 1; @@ -438,11 +442,12 @@ static int power_disable(struct noon010_info *info) if (ret) return ret; - if (gpio_is_valid(info->gpio_nstby)) - gpio_set_value(info->gpio_nstby, 0); + /* Assert standby and reset */ + if (info->stby) + gpiod_set_value(info->stby, 1); - if (gpio_is_valid(info->gpio_nreset)) - gpio_set_value(info->gpio_nreset, 0); + if (info->reset) + gpiod_set_value(info->reset, 1); info->power = 0; @@ -741,34 +746,24 @@ static int noon010_probe(struct i2c_client *client, goto np_err; info->i2c_reg_page = -1; - info->gpio_nreset = -EINVAL; - info->gpio_nstby = -EINVAL; info->curr_fmt = &noon010_formats[0]; info->curr_win = &noon010_sizes[0]; - if (gpio_is_valid(pdata->gpio_nreset)) { - ret = devm_gpio_request_one(&client->dev, pdata->gpio_nreset, - GPIOF_OUT_INIT_LOW, - "NOON010PC30 NRST"); - if (ret) { - dev_err(&client->dev, "GPIO request error: %d\n", ret); - goto np_err; - } - info->gpio_nreset = pdata->gpio_nreset; - gpio_export(info->gpio_nreset, 0); + /* Request reset asserted so we get put into reset */ + info->reset = devm_gpiod_get(&client->dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(info->reset)) { + ret = PTR_ERR(info->reset); + goto np_err; } + gpiod_set_consumer_name(info->reset, "NOON010PC30 NRST"); - if (gpio_is_valid(pdata->gpio_nstby)) { - ret = devm_gpio_request_one(&client->dev, pdata->gpio_nstby, - GPIOF_OUT_INIT_LOW, - "NOON010PC30 NSTBY"); - if (ret) { - dev_err(&client->dev, "GPIO request error: %d\n", ret); - goto np_err; - } - info->gpio_nstby = pdata->gpio_nstby; - gpio_export(info->gpio_nstby, 0); + /* Request standby asserted so we get put into standby */ + info->stby = devm_gpiod_get(&client->dev, "standby", GPIOD_OUT_HIGH); + if (IS_ERR(info->stby)) { + ret = PTR_ERR(info->stby); + goto np_err; } + gpiod_set_consumer_name(info->reset, "NOON010PC30 STBY"); for (i = 0; i < NOON010_NUM_SUPPLIES; i++) info->supply[i].supply = noon010_supply_name[i]; diff --git a/drivers/media/i2c/og01a1b.c b/drivers/media/i2c/og01a1b.c new file mode 100644 index 000000000000..87179fc04e00 --- /dev/null +++ b/drivers/media/i2c/og01a1b.c @@ -0,0 +1,1128 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2022 Intel Corporation. + +#include <asm/unaligned.h> +#include <linux/acpi.h> +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/pm_runtime.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-device.h> +#include <media/v4l2-fwnode.h> + +#define OG01A1B_REG_VALUE_08BIT 1 +#define OG01A1B_REG_VALUE_16BIT 2 +#define OG01A1B_REG_VALUE_24BIT 3 + +#define OG01A1B_LINK_FREQ_500MHZ 500000000ULL +#define OG01A1B_SCLK 120000000LL +#define OG01A1B_MCLK 19200000 +#define OG01A1B_DATA_LANES 2 +#define OG01A1B_RGB_DEPTH 10 + +#define OG01A1B_REG_CHIP_ID 0x300a +#define OG01A1B_CHIP_ID 0x470141 + +#define OG01A1B_REG_MODE_SELECT 0x0100 +#define OG01A1B_MODE_STANDBY 0x00 +#define OG01A1B_MODE_STREAMING 0x01 + +/* vertical-timings from sensor */ +#define OG01A1B_REG_VTS 0x380e +#define OG01A1B_VTS_120FPS 0x0498 +#define OG01A1B_VTS_120FPS_MIN 0x0498 +#define OG01A1B_VTS_MAX 0x7fff + +/* horizontal-timings from sensor */ +#define OG01A1B_REG_HTS 0x380c + +/* Exposure controls from sensor */ +#define OG01A1B_REG_EXPOSURE 0x3501 +#define OG01A1B_EXPOSURE_MIN 1 +#define OG01A1B_EXPOSURE_MAX_MARGIN 14 +#define OG01A1B_EXPOSURE_STEP 1 + +/* Analog gain controls from sensor */ +#define OG01A1B_REG_ANALOG_GAIN 0x3508 +#define OG01A1B_ANAL_GAIN_MIN 16 +#define OG01A1B_ANAL_GAIN_MAX 248 /* Max = 15.5x */ +#define OG01A1B_ANAL_GAIN_STEP 1 + +/* Digital gain controls from sensor */ +#define OG01A1B_REG_DIG_GAIN 0x350a +#define OG01A1B_DGTL_GAIN_MIN 1024 +#define OG01A1B_DGTL_GAIN_MAX 16384 /* Max = 16x */ +#define OG01A1B_DGTL_GAIN_STEP 1 +#define OG01A1B_DGTL_GAIN_DEFAULT 1024 + +/* Group Access */ +#define OG01A1B_REG_GROUP_ACCESS 0x3208 +#define OG01A1B_GROUP_HOLD_START 0x0 +#define OG01A1B_GROUP_HOLD_END 0x10 +#define OG01A1B_GROUP_HOLD_LAUNCH 0xa0 + +/* Test Pattern Control */ +#define OG01A1B_REG_TEST_PATTERN 0x5100 +#define OG01A1B_TEST_PATTERN_ENABLE BIT(7) +#define OG01A1B_TEST_PATTERN_BAR_SHIFT 2 + +#define to_og01a1b(_sd) container_of(_sd, struct og01a1b, sd) + +enum { + OG01A1B_LINK_FREQ_1000MBPS, +}; + +struct og01a1b_reg { + u16 address; + u8 val; +}; + +struct og01a1b_reg_list { + u32 num_of_regs; + const struct og01a1b_reg *regs; +}; + +struct og01a1b_link_freq_config { + const struct og01a1b_reg_list reg_list; +}; + +struct og01a1b_mode { + /* Frame width in pixels */ + u32 width; + + /* Frame height in pixels */ + u32 height; + + /* Horizontal timining size */ + u32 hts; + + /* Default vertical timining size */ + u32 vts_def; + + /* Min vertical timining size */ + u32 vts_min; + + /* Link frequency needed for this resolution */ + u32 link_freq_index; + + /* Sensor register settings for this resolution */ + const struct og01a1b_reg_list reg_list; +}; + +static const struct og01a1b_reg mipi_data_rate_1000mbps[] = { + {0x0103, 0x01}, + {0x0303, 0x02}, + {0x0304, 0x00}, + {0x0305, 0xd2}, + {0x0323, 0x02}, + {0x0324, 0x01}, + {0x0325, 0x77}, +}; + +static const struct og01a1b_reg mode_1280x1024_regs[] = { + {0x0300, 0x0a}, + {0x0301, 0x29}, + {0x0302, 0x31}, + {0x0303, 0x02}, + {0x0304, 0x00}, + {0x0305, 0xd2}, + {0x0306, 0x00}, + {0x0307, 0x01}, + {0x0308, 0x02}, + {0x0309, 0x00}, + {0x0310, 0x00}, + {0x0311, 0x00}, + {0x0312, 0x07}, + {0x0313, 0x00}, + {0x0314, 0x00}, + {0x0315, 0x00}, + {0x0320, 0x02}, + {0x0321, 0x01}, + {0x0322, 0x01}, + {0x0323, 0x02}, + {0x0324, 0x01}, + {0x0325, 0x77}, + {0x0326, 0xce}, + {0x0327, 0x04}, + {0x0329, 0x02}, + {0x032a, 0x04}, + {0x032b, 0x04}, + {0x032c, 0x02}, + {0x032d, 0x01}, + {0x032e, 0x00}, + {0x300d, 0x02}, + {0x300e, 0x04}, + {0x3021, 0x08}, + {0x301e, 0x03}, + {0x3103, 0x00}, + {0x3106, 0x08}, + {0x3107, 0x40}, + {0x3216, 0x01}, + {0x3217, 0x00}, + {0x3218, 0xc0}, + {0x3219, 0x55}, + {0x3500, 0x00}, + {0x3501, 0x04}, + {0x3502, 0x8a}, + {0x3506, 0x01}, + {0x3507, 0x72}, + {0x3508, 0x01}, + {0x3509, 0x00}, + {0x350a, 0x01}, + {0x350b, 0x00}, + {0x350c, 0x00}, + {0x3541, 0x00}, + {0x3542, 0x40}, + {0x3605, 0xe0}, + {0x3606, 0x41}, + {0x3614, 0x20}, + {0x3620, 0x0b}, + {0x3630, 0x07}, + {0x3636, 0xa0}, + {0x3637, 0xf9}, + {0x3638, 0x09}, + {0x3639, 0x38}, + {0x363f, 0x09}, + {0x3640, 0x17}, + {0x3662, 0x04}, + {0x3665, 0x80}, + {0x3670, 0x68}, + {0x3674, 0x00}, + {0x3677, 0x3f}, + {0x3679, 0x00}, + {0x369f, 0x19}, + {0x36a0, 0x03}, + {0x36a2, 0x19}, + {0x36a3, 0x03}, + {0x370d, 0x66}, + {0x370f, 0x00}, + {0x3710, 0x03}, + {0x3715, 0x03}, + {0x3716, 0x03}, + {0x3717, 0x06}, + {0x3733, 0x00}, + {0x3778, 0x00}, + {0x37a8, 0x0f}, + {0x37a9, 0x01}, + {0x37aa, 0x07}, + {0x37bd, 0x1c}, + {0x37c1, 0x2f}, + {0x37c3, 0x09}, + {0x37c8, 0x1d}, + {0x37ca, 0x30}, + {0x37df, 0x00}, + {0x3800, 0x00}, + {0x3801, 0x00}, + {0x3802, 0x00}, + {0x3803, 0x00}, + {0x3804, 0x05}, + {0x3805, 0x0f}, + {0x3806, 0x04}, + {0x3807, 0x0f}, + {0x3808, 0x05}, + {0x3809, 0x00}, + {0x380a, 0x04}, + {0x380b, 0x00}, + {0x380c, 0x03}, + {0x380d, 0x50}, + {0x380e, 0x04}, + {0x380f, 0x98}, + {0x3810, 0x00}, + {0x3811, 0x08}, + {0x3812, 0x00}, + {0x3813, 0x08}, + {0x3814, 0x11}, + {0x3815, 0x11}, + {0x3820, 0x40}, + {0x3821, 0x04}, + {0x3826, 0x00}, + {0x3827, 0x00}, + {0x382a, 0x08}, + {0x382b, 0x52}, + {0x382d, 0xba}, + {0x383d, 0x14}, + {0x384a, 0xa2}, + {0x3866, 0x0e}, + {0x3867, 0x07}, + {0x3884, 0x00}, + {0x3885, 0x08}, + {0x3893, 0x68}, + {0x3894, 0x2a}, + {0x3898, 0x00}, + {0x3899, 0x31}, + {0x389a, 0x04}, + {0x389b, 0x00}, + {0x389c, 0x0b}, + {0x389d, 0xad}, + {0x389f, 0x08}, + {0x38a0, 0x00}, + {0x38a1, 0x00}, + {0x38a8, 0x70}, + {0x38ac, 0xea}, + {0x38b2, 0x00}, + {0x38b3, 0x08}, + {0x38bc, 0x20}, + {0x38c4, 0x0c}, + {0x38c5, 0x3a}, + {0x38c7, 0x3a}, + {0x38e1, 0xc0}, + {0x38ec, 0x3c}, + {0x38f0, 0x09}, + {0x38f1, 0x6f}, + {0x38fe, 0x3c}, + {0x391e, 0x00}, + {0x391f, 0x00}, + {0x3920, 0xa5}, + {0x3921, 0x00}, + {0x3922, 0x00}, + {0x3923, 0x00}, + {0x3924, 0x05}, + {0x3925, 0x00}, + {0x3926, 0x00}, + {0x3927, 0x00}, + {0x3928, 0x1a}, + {0x3929, 0x01}, + {0x392a, 0xb4}, + {0x392b, 0x00}, + {0x392c, 0x10}, + {0x392f, 0x40}, + {0x4000, 0xcf}, + {0x4003, 0x40}, + {0x4008, 0x00}, + {0x4009, 0x07}, + {0x400a, 0x02}, + {0x400b, 0x54}, + {0x400c, 0x00}, + {0x400d, 0x07}, + {0x4010, 0xc0}, + {0x4012, 0x02}, + {0x4014, 0x04}, + {0x4015, 0x04}, + {0x4017, 0x02}, + {0x4042, 0x01}, + {0x4306, 0x04}, + {0x4307, 0x12}, + {0x4509, 0x00}, + {0x450b, 0x83}, + {0x4604, 0x68}, + {0x4608, 0x0a}, + {0x4700, 0x06}, + {0x4800, 0x64}, + {0x481b, 0x3c}, + {0x4825, 0x32}, + {0x4833, 0x18}, + {0x4837, 0x0f}, + {0x4850, 0x40}, + {0x4860, 0x00}, + {0x4861, 0xec}, + {0x4864, 0x00}, + {0x4883, 0x00}, + {0x4888, 0x90}, + {0x4889, 0x05}, + {0x488b, 0x04}, + {0x4f00, 0x04}, + {0x4f10, 0x04}, + {0x4f21, 0x01}, + {0x4f22, 0x40}, + {0x4f23, 0x44}, + {0x4f24, 0x51}, + {0x4f25, 0x41}, + {0x5000, 0x1f}, + {0x500a, 0x00}, + {0x5100, 0x00}, + {0x5111, 0x20}, + {0x3020, 0x20}, + {0x3613, 0x03}, + {0x38c9, 0x02}, + {0x5304, 0x01}, + {0x3620, 0x08}, + {0x3639, 0x58}, + {0x363a, 0x10}, + {0x3674, 0x04}, + {0x3780, 0xff}, + {0x3781, 0xff}, + {0x3782, 0x00}, + {0x3783, 0x01}, + {0x3798, 0xa3}, + {0x37aa, 0x10}, + {0x38a8, 0xf0}, + {0x38c4, 0x09}, + {0x38c5, 0xb0}, + {0x38df, 0x80}, + {0x38ff, 0x05}, + {0x4010, 0xf1}, + {0x4011, 0x70}, + {0x3667, 0x80}, + {0x4d00, 0x4a}, + {0x4d01, 0x18}, + {0x4d02, 0xbb}, + {0x4d03, 0xde}, + {0x4d04, 0x93}, + {0x4d05, 0xff}, + {0x4d09, 0x0a}, + {0x37aa, 0x16}, + {0x3606, 0x42}, + {0x3605, 0x00}, + {0x36a2, 0x17}, + {0x300d, 0x0a}, + {0x4d00, 0x4d}, + {0x4d01, 0x95}, + {0x3d8C, 0x70}, + {0x3d8d, 0xE9}, + {0x5300, 0x00}, + {0x5301, 0x10}, + {0x5302, 0x00}, + {0x5303, 0xE3}, + {0x3d88, 0x00}, + {0x3d89, 0x10}, + {0x3d8a, 0x00}, + {0x3d8b, 0xE3}, + {0x4f22, 0x00}, +}; + +static const char * const og01a1b_test_pattern_menu[] = { + "Disabled", + "Standard Color Bar", + "Top-Bottom Darker Color Bar", + "Right-Left Darker Color Bar", + "Bottom-Top Darker Color Bar" +}; + +static const s64 link_freq_menu_items[] = { + OG01A1B_LINK_FREQ_500MHZ, +}; + +static const struct og01a1b_link_freq_config link_freq_configs[] = { + [OG01A1B_LINK_FREQ_1000MBPS] = { + .reg_list = { + .num_of_regs = ARRAY_SIZE(mipi_data_rate_1000mbps), + .regs = mipi_data_rate_1000mbps, + } + } +}; + +static const struct og01a1b_mode supported_modes[] = { + { + .width = 1280, + .height = 1024, + .hts = 848, + .vts_def = OG01A1B_VTS_120FPS, + .vts_min = OG01A1B_VTS_120FPS_MIN, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mode_1280x1024_regs), + .regs = mode_1280x1024_regs, + }, + .link_freq_index = OG01A1B_LINK_FREQ_1000MBPS, + }, +}; + +struct og01a1b { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_ctrl_handler ctrl_handler; + + /* V4L2 Controls */ + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *vblank; + struct v4l2_ctrl *hblank; + struct v4l2_ctrl *exposure; + + /* Current mode */ + const struct og01a1b_mode *cur_mode; + + /* To serialize asynchronus callbacks */ + struct mutex mutex; + + /* Streaming on/off */ + bool streaming; +}; + +static u64 to_pixel_rate(u32 f_index) +{ + u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OG01A1B_DATA_LANES; + + do_div(pixel_rate, OG01A1B_RGB_DEPTH); + + return pixel_rate; +} + +static u64 to_pixels_per_line(u32 hts, u32 f_index) +{ + u64 ppl = hts * to_pixel_rate(f_index); + + do_div(ppl, OG01A1B_SCLK); + + return ppl; +} + +static int og01a1b_read_reg(struct og01a1b *og01a1b, u16 reg, u16 len, u32 *val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd); + struct i2c_msg msgs[2]; + u8 addr_buf[2]; + u8 data_buf[4] = {0}; + int ret; + + if (len > 4) + return -EINVAL; + + put_unaligned_be16(reg, addr_buf); + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = sizeof(addr_buf); + msgs[0].buf = addr_buf; + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = len; + msgs[1].buf = &data_buf[4 - len]; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) + return -EIO; + + *val = get_unaligned_be32(data_buf); + + return 0; +} + +static int og01a1b_write_reg(struct og01a1b *og01a1b, u16 reg, u16 len, u32 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd); + u8 buf[6]; + + if (len > 4) + return -EINVAL; + + put_unaligned_be16(reg, buf); + put_unaligned_be32(val << 8 * (4 - len), buf + 2); + if (i2c_master_send(client, buf, len + 2) != len + 2) + return -EIO; + + return 0; +} + +static int og01a1b_write_reg_list(struct og01a1b *og01a1b, + const struct og01a1b_reg_list *r_list) +{ + struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd); + unsigned int i; + int ret; + + for (i = 0; i < r_list->num_of_regs; i++) { + ret = og01a1b_write_reg(og01a1b, r_list->regs[i].address, 1, + r_list->regs[i].val); + if (ret) { + dev_err_ratelimited(&client->dev, + "failed to write reg 0x%4.4x. error = %d", + r_list->regs[i].address, ret); + return ret; + } + } + + return 0; +} + +static int og01a1b_test_pattern(struct og01a1b *og01a1b, u32 pattern) +{ + if (pattern) + pattern = (pattern - 1) << OG01A1B_TEST_PATTERN_BAR_SHIFT | + OG01A1B_TEST_PATTERN_ENABLE; + + return og01a1b_write_reg(og01a1b, OG01A1B_REG_TEST_PATTERN, + OG01A1B_REG_VALUE_08BIT, pattern); +} + +static int og01a1b_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct og01a1b *og01a1b = container_of(ctrl->handler, + struct og01a1b, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd); + s64 exposure_max; + int ret = 0; + + /* Propagate change of current control to all related controls */ + if (ctrl->id == V4L2_CID_VBLANK) { + /* Update max exposure while meeting expected vblanking */ + exposure_max = og01a1b->cur_mode->height + ctrl->val - + OG01A1B_EXPOSURE_MAX_MARGIN; + __v4l2_ctrl_modify_range(og01a1b->exposure, + og01a1b->exposure->minimum, + exposure_max, og01a1b->exposure->step, + exposure_max); + } + + /* V4L2 controls values will be applied only when power is already up */ + if (!pm_runtime_get_if_in_use(&client->dev)) + return 0; + + switch (ctrl->id) { + case V4L2_CID_ANALOGUE_GAIN: + ret = og01a1b_write_reg(og01a1b, OG01A1B_REG_ANALOG_GAIN, + OG01A1B_REG_VALUE_16BIT, + ctrl->val << 4); + break; + + case V4L2_CID_DIGITAL_GAIN: + ret = og01a1b_write_reg(og01a1b, OG01A1B_REG_DIG_GAIN, + OG01A1B_REG_VALUE_24BIT, + ctrl->val << 6); + break; + + case V4L2_CID_EXPOSURE: + ret = og01a1b_write_reg(og01a1b, OG01A1B_REG_EXPOSURE, + OG01A1B_REG_VALUE_16BIT, ctrl->val); + break; + + case V4L2_CID_VBLANK: + ret = og01a1b_write_reg(og01a1b, OG01A1B_REG_VTS, + OG01A1B_REG_VALUE_16BIT, + og01a1b->cur_mode->height + ctrl->val); + break; + + case V4L2_CID_TEST_PATTERN: + ret = og01a1b_test_pattern(og01a1b, ctrl->val); + break; + + default: + ret = -EINVAL; + break; + } + + pm_runtime_put(&client->dev); + + return ret; +} + +static const struct v4l2_ctrl_ops og01a1b_ctrl_ops = { + .s_ctrl = og01a1b_set_ctrl, +}; + +static int og01a1b_init_controls(struct og01a1b *og01a1b) +{ + struct v4l2_ctrl_handler *ctrl_hdlr; + s64 exposure_max, h_blank; + int ret; + + ctrl_hdlr = &og01a1b->ctrl_handler; + ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8); + if (ret) + return ret; + + ctrl_hdlr->lock = &og01a1b->mutex; + og01a1b->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, + &og01a1b_ctrl_ops, + V4L2_CID_LINK_FREQ, + ARRAY_SIZE + (link_freq_menu_items) - 1, + 0, link_freq_menu_items); + if (og01a1b->link_freq) + og01a1b->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + og01a1b->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &og01a1b_ctrl_ops, + V4L2_CID_PIXEL_RATE, 0, + to_pixel_rate + (OG01A1B_LINK_FREQ_1000MBPS), + 1, + to_pixel_rate + (OG01A1B_LINK_FREQ_1000MBPS)); + og01a1b->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &og01a1b_ctrl_ops, + V4L2_CID_VBLANK, + og01a1b->cur_mode->vts_min - + og01a1b->cur_mode->height, + OG01A1B_VTS_MAX - + og01a1b->cur_mode->height, 1, + og01a1b->cur_mode->vts_def - + og01a1b->cur_mode->height); + h_blank = to_pixels_per_line(og01a1b->cur_mode->hts, + og01a1b->cur_mode->link_freq_index) - + og01a1b->cur_mode->width; + og01a1b->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &og01a1b_ctrl_ops, + V4L2_CID_HBLANK, h_blank, h_blank, + 1, h_blank); + if (og01a1b->hblank) + og01a1b->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + v4l2_ctrl_new_std(ctrl_hdlr, &og01a1b_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, + OG01A1B_ANAL_GAIN_MIN, OG01A1B_ANAL_GAIN_MAX, + OG01A1B_ANAL_GAIN_STEP, OG01A1B_ANAL_GAIN_MIN); + v4l2_ctrl_new_std(ctrl_hdlr, &og01a1b_ctrl_ops, V4L2_CID_DIGITAL_GAIN, + OG01A1B_DGTL_GAIN_MIN, OG01A1B_DGTL_GAIN_MAX, + OG01A1B_DGTL_GAIN_STEP, OG01A1B_DGTL_GAIN_DEFAULT); + exposure_max = (og01a1b->cur_mode->vts_def - + OG01A1B_EXPOSURE_MAX_MARGIN); + og01a1b->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &og01a1b_ctrl_ops, + V4L2_CID_EXPOSURE, + OG01A1B_EXPOSURE_MIN, + exposure_max, + OG01A1B_EXPOSURE_STEP, + exposure_max); + v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &og01a1b_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(og01a1b_test_pattern_menu) - 1, + 0, 0, og01a1b_test_pattern_menu); + + if (ctrl_hdlr->error) + return ctrl_hdlr->error; + + og01a1b->sd.ctrl_handler = ctrl_hdlr; + + return 0; +} + +static void og01a1b_update_pad_format(const struct og01a1b_mode *mode, + struct v4l2_mbus_framefmt *fmt) +{ + fmt->width = mode->width; + fmt->height = mode->height; + fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; + fmt->field = V4L2_FIELD_NONE; +} + +static int og01a1b_start_streaming(struct og01a1b *og01a1b) +{ + struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd); + const struct og01a1b_reg_list *reg_list; + int link_freq_index, ret; + + link_freq_index = og01a1b->cur_mode->link_freq_index; + reg_list = &link_freq_configs[link_freq_index].reg_list; + + ret = og01a1b_write_reg_list(og01a1b, reg_list); + if (ret) { + dev_err(&client->dev, "failed to set plls"); + return ret; + } + + reg_list = &og01a1b->cur_mode->reg_list; + ret = og01a1b_write_reg_list(og01a1b, reg_list); + if (ret) { + dev_err(&client->dev, "failed to set mode"); + return ret; + } + + ret = __v4l2_ctrl_handler_setup(og01a1b->sd.ctrl_handler); + if (ret) + return ret; + + ret = og01a1b_write_reg(og01a1b, OG01A1B_REG_MODE_SELECT, + OG01A1B_REG_VALUE_08BIT, + OG01A1B_MODE_STREAMING); + if (ret) { + dev_err(&client->dev, "failed to set stream"); + return ret; + } + + return 0; +} + +static void og01a1b_stop_streaming(struct og01a1b *og01a1b) +{ + struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd); + + if (og01a1b_write_reg(og01a1b, OG01A1B_REG_MODE_SELECT, + OG01A1B_REG_VALUE_08BIT, OG01A1B_MODE_STANDBY)) + dev_err(&client->dev, "failed to set stream"); +} + +static int og01a1b_set_stream(struct v4l2_subdev *sd, int enable) +{ + struct og01a1b *og01a1b = to_og01a1b(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (og01a1b->streaming == enable) + return 0; + + mutex_lock(&og01a1b->mutex); + if (enable) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + mutex_unlock(&og01a1b->mutex); + return ret; + } + + ret = og01a1b_start_streaming(og01a1b); + if (ret) { + enable = 0; + og01a1b_stop_streaming(og01a1b); + pm_runtime_put(&client->dev); + } + } else { + og01a1b_stop_streaming(og01a1b); + pm_runtime_put(&client->dev); + } + + og01a1b->streaming = enable; + mutex_unlock(&og01a1b->mutex); + + return ret; +} + +static int __maybe_unused og01a1b_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct og01a1b *og01a1b = to_og01a1b(sd); + + mutex_lock(&og01a1b->mutex); + if (og01a1b->streaming) + og01a1b_stop_streaming(og01a1b); + + mutex_unlock(&og01a1b->mutex); + + return 0; +} + +static int __maybe_unused og01a1b_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct og01a1b *og01a1b = to_og01a1b(sd); + int ret; + + mutex_lock(&og01a1b->mutex); + if (og01a1b->streaming) { + ret = og01a1b_start_streaming(og01a1b); + if (ret) { + og01a1b->streaming = false; + og01a1b_stop_streaming(og01a1b); + mutex_unlock(&og01a1b->mutex); + return ret; + } + } + + mutex_unlock(&og01a1b->mutex); + + return 0; +} + +static int og01a1b_set_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct og01a1b *og01a1b = to_og01a1b(sd); + const struct og01a1b_mode *mode; + s32 vblank_def, h_blank; + + mode = v4l2_find_nearest_size(supported_modes, + ARRAY_SIZE(supported_modes), width, + height, fmt->format.width, + fmt->format.height); + + mutex_lock(&og01a1b->mutex); + og01a1b_update_pad_format(mode, &fmt->format); + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { + *v4l2_subdev_get_try_format(sd, sd_state, + fmt->pad) = fmt->format; + } else { + og01a1b->cur_mode = mode; + __v4l2_ctrl_s_ctrl(og01a1b->link_freq, mode->link_freq_index); + __v4l2_ctrl_s_ctrl_int64(og01a1b->pixel_rate, + to_pixel_rate(mode->link_freq_index)); + + /* Update limits and set FPS to default */ + vblank_def = mode->vts_def - mode->height; + __v4l2_ctrl_modify_range(og01a1b->vblank, + mode->vts_min - mode->height, + OG01A1B_VTS_MAX - mode->height, 1, + vblank_def); + __v4l2_ctrl_s_ctrl(og01a1b->vblank, vblank_def); + h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) - + mode->width; + __v4l2_ctrl_modify_range(og01a1b->hblank, h_blank, h_blank, 1, + h_blank); + } + + mutex_unlock(&og01a1b->mutex); + + return 0; +} + +static int og01a1b_get_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct og01a1b *og01a1b = to_og01a1b(sd); + + mutex_lock(&og01a1b->mutex); + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) + fmt->format = *v4l2_subdev_get_try_format(&og01a1b->sd, + sd_state, + fmt->pad); + else + og01a1b_update_pad_format(og01a1b->cur_mode, &fmt->format); + + mutex_unlock(&og01a1b->mutex); + + return 0; +} + +static int og01a1b_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index > 0) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_SGRBG10_1X10; + + return 0; +} + +static int og01a1b_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + if (fse->index >= ARRAY_SIZE(supported_modes)) + return -EINVAL; + + if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) + return -EINVAL; + + fse->min_width = supported_modes[fse->index].width; + fse->max_width = fse->min_width; + fse->min_height = supported_modes[fse->index].height; + fse->max_height = fse->min_height; + + return 0; +} + +static int og01a1b_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct og01a1b *og01a1b = to_og01a1b(sd); + + mutex_lock(&og01a1b->mutex); + og01a1b_update_pad_format(&supported_modes[0], + v4l2_subdev_get_try_format(sd, fh->state, 0)); + mutex_unlock(&og01a1b->mutex); + + return 0; +} + +static const struct v4l2_subdev_video_ops og01a1b_video_ops = { + .s_stream = og01a1b_set_stream, +}; + +static const struct v4l2_subdev_pad_ops og01a1b_pad_ops = { + .set_fmt = og01a1b_set_format, + .get_fmt = og01a1b_get_format, + .enum_mbus_code = og01a1b_enum_mbus_code, + .enum_frame_size = og01a1b_enum_frame_size, +}; + +static const struct v4l2_subdev_ops og01a1b_subdev_ops = { + .video = &og01a1b_video_ops, + .pad = &og01a1b_pad_ops, +}; + +static const struct media_entity_operations og01a1b_subdev_entity_ops = { + .link_validate = v4l2_subdev_link_validate, +}; + +static const struct v4l2_subdev_internal_ops og01a1b_internal_ops = { + .open = og01a1b_open, +}; + +static int og01a1b_identify_module(struct og01a1b *og01a1b) +{ + struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd); + int ret; + u32 val; + + ret = og01a1b_read_reg(og01a1b, OG01A1B_REG_CHIP_ID, + OG01A1B_REG_VALUE_24BIT, &val); + if (ret) + return ret; + + if (val != OG01A1B_CHIP_ID) { + dev_err(&client->dev, "chip id mismatch: %x!=%x", + OG01A1B_CHIP_ID, val); + return -ENXIO; + } + + return 0; +} + +static int og01a1b_check_hwcfg(struct device *dev) +{ + struct fwnode_handle *ep; + struct fwnode_handle *fwnode = dev_fwnode(dev); + struct v4l2_fwnode_endpoint bus_cfg = { + .bus_type = V4L2_MBUS_CSI2_DPHY + }; + u32 mclk; + int ret; + unsigned int i, j; + + if (!fwnode) + return -ENXIO; + + ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk); + + if (ret) { + dev_err(dev, "can't get clock frequency"); + return ret; + } + + if (mclk != OG01A1B_MCLK) { + dev_err(dev, "external clock %d is not supported", mclk); + return -EINVAL; + } + + ep = fwnode_graph_get_next_endpoint(fwnode, NULL); + if (!ep) + return -ENXIO; + + ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); + fwnode_handle_put(ep); + if (ret) + return ret; + + if (bus_cfg.bus.mipi_csi2.num_data_lanes != OG01A1B_DATA_LANES) { + dev_err(dev, "number of CSI2 data lanes %d is not supported", + bus_cfg.bus.mipi_csi2.num_data_lanes); + ret = -EINVAL; + goto check_hwcfg_error; + } + + if (!bus_cfg.nr_of_link_frequencies) { + dev_err(dev, "no link frequencies defined"); + ret = -EINVAL; + goto check_hwcfg_error; + } + + for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { + for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { + if (link_freq_menu_items[i] == + bus_cfg.link_frequencies[j]) + break; + } + + if (j == bus_cfg.nr_of_link_frequencies) { + dev_err(dev, "no link frequency %lld supported", + link_freq_menu_items[i]); + ret = -EINVAL; + goto check_hwcfg_error; + } + } + +check_hwcfg_error: + v4l2_fwnode_endpoint_free(&bus_cfg); + + return ret; +} + +static int og01a1b_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct og01a1b *og01a1b = to_og01a1b(sd); + + v4l2_async_unregister_subdev(sd); + media_entity_cleanup(&sd->entity); + v4l2_ctrl_handler_free(sd->ctrl_handler); + pm_runtime_disable(&client->dev); + mutex_destroy(&og01a1b->mutex); + + return 0; +} + +static int og01a1b_probe(struct i2c_client *client) +{ + struct og01a1b *og01a1b; + int ret; + + ret = og01a1b_check_hwcfg(&client->dev); + if (ret) { + dev_err(&client->dev, "failed to check HW configuration: %d", + ret); + return ret; + } + + og01a1b = devm_kzalloc(&client->dev, sizeof(*og01a1b), GFP_KERNEL); + if (!og01a1b) + return -ENOMEM; + + v4l2_i2c_subdev_init(&og01a1b->sd, client, &og01a1b_subdev_ops); + ret = og01a1b_identify_module(og01a1b); + if (ret) { + dev_err(&client->dev, "failed to find sensor: %d", ret); + return ret; + } + + mutex_init(&og01a1b->mutex); + og01a1b->cur_mode = &supported_modes[0]; + ret = og01a1b_init_controls(og01a1b); + if (ret) { + dev_err(&client->dev, "failed to init controls: %d", ret); + goto probe_error_v4l2_ctrl_handler_free; + } + + og01a1b->sd.internal_ops = &og01a1b_internal_ops; + og01a1b->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + og01a1b->sd.entity.ops = &og01a1b_subdev_entity_ops; + og01a1b->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + og01a1b->pad.flags = MEDIA_PAD_FL_SOURCE; + ret = media_entity_pads_init(&og01a1b->sd.entity, 1, &og01a1b->pad); + if (ret) { + dev_err(&client->dev, "failed to init entity pads: %d", ret); + goto probe_error_v4l2_ctrl_handler_free; + } + + ret = v4l2_async_register_subdev_sensor(&og01a1b->sd); + if (ret < 0) { + dev_err(&client->dev, "failed to register V4L2 subdev: %d", + ret); + goto probe_error_media_entity_cleanup; + } + + /* + * Device is already turned on by i2c-core with ACPI domain PM. + * Enable runtime PM and turn off the device. + */ + pm_runtime_set_active(&client->dev); + pm_runtime_enable(&client->dev); + pm_runtime_idle(&client->dev); + + return 0; + +probe_error_media_entity_cleanup: + media_entity_cleanup(&og01a1b->sd.entity); + +probe_error_v4l2_ctrl_handler_free: + v4l2_ctrl_handler_free(og01a1b->sd.ctrl_handler); + mutex_destroy(&og01a1b->mutex); + + return ret; +} + +static const struct dev_pm_ops og01a1b_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(og01a1b_suspend, og01a1b_resume) +}; + +#ifdef CONFIG_ACPI +static const struct acpi_device_id og01a1b_acpi_ids[] = { + {"OVTI01AC"}, + {} +}; + +MODULE_DEVICE_TABLE(acpi, og01a1b_acpi_ids); +#endif + +static struct i2c_driver og01a1b_i2c_driver = { + .driver = { + .name = "og01a1b", + .pm = &og01a1b_pm_ops, + .acpi_match_table = ACPI_PTR(og01a1b_acpi_ids), + }, + .probe_new = og01a1b_probe, + .remove = og01a1b_remove, +}; + +module_i2c_driver(og01a1b_i2c_driver); + +MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>"); +MODULE_DESCRIPTION("OmniVision OG01A1B sensor driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/media/i2c/ov08d10.c b/drivers/media/i2c/ov08d10.c new file mode 100644 index 000000000000..e5ef6466a3ec --- /dev/null +++ b/drivers/media/i2c/ov08d10.c @@ -0,0 +1,1528 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2022 Intel Corporation. + +#include <linux/acpi.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/pm_runtime.h> +#include <linux/regulator/consumer.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-device.h> +#include <media/v4l2-fwnode.h> + +#define OV08D10_SCLK 144000000ULL +#define OV08D10_XVCLK_19_2 19200000 +#define OV08D10_ROWCLK 36000 +#define OV08D10_DATA_LANES 2 +#define OV08D10_RGB_DEPTH 10 + +#define OV08D10_REG_PAGE 0xfd +#define OV08D10_REG_GLOBAL_EFFECTIVE 0x01 +#define OV08D10_REG_CHIP_ID_0 0x00 +#define OV08D10_REG_CHIP_ID_1 0x01 +#define OV08D10_ID_MASK GENMASK(15, 0) +#define OV08D10_CHIP_ID 0x5608 + +#define OV08D10_REG_MODE_SELECT 0xa0 +#define OV08D10_MODE_STANDBY 0x00 +#define OV08D10_MODE_STREAMING 0x01 + +/* vertical-timings from sensor */ +#define OV08D10_REG_VTS_H 0x05 +#define OV08D10_REG_VTS_L 0x06 +#define OV08D10_VTS_MAX 0x7fff + +/* Exposure controls from sensor */ +#define OV08D10_REG_EXPOSURE_H 0x02 +#define OV08D10_REG_EXPOSURE_M 0x03 +#define OV08D10_REG_EXPOSURE_L 0x04 +#define OV08D10_EXPOSURE_MIN 6 +#define OV08D10_EXPOSURE_MAX_MARGIN 6 +#define OV08D10_EXPOSURE_STEP 1 + +/* Analog gain controls from sensor */ +#define OV08D10_REG_ANALOG_GAIN 0x24 +#define OV08D10_ANAL_GAIN_MIN 128 +#define OV08D10_ANAL_GAIN_MAX 2047 +#define OV08D10_ANAL_GAIN_STEP 1 + +/* Digital gain controls from sensor */ +#define OV08D10_REG_MWB_DGAIN_C 0x21 +#define OV08D10_REG_MWB_DGAIN_F 0x22 +#define OV08D10_DGTL_GAIN_MIN 0 +#define OV08D10_DGTL_GAIN_MAX 4095 +#define OV08D10_DGTL_GAIN_STEP 1 +#define OV08D10_DGTL_GAIN_DEFAULT 1024 + +/* Test Pattern Control */ +#define OV08D10_REG_TEST_PATTERN 0x12 +#define OV08D10_TEST_PATTERN_ENABLE 0x01 +#define OV08D10_TEST_PATTERN_DISABLE 0x00 + +/* Flip Mirror Controls from sensor */ +#define OV08D10_REG_FLIP_OPT 0x32 +#define OV08D10_REG_FLIP_MASK 0x3 + +#define to_ov08d10(_sd) container_of(_sd, struct ov08d10, sd) + +struct ov08d10_reg { + u8 address; + u8 val; +}; + +struct ov08d10_reg_list { + u32 num_of_regs; + const struct ov08d10_reg *regs; +}; + +struct ov08d10_link_freq_config { + const struct ov08d10_reg_list reg_list; +}; + +struct ov08d10_mode { + /* Frame width in pixels */ + u32 width; + + /* Frame height in pixels */ + u32 height; + + /* Horizontal timining size */ + u32 hts; + + /* Default vertical timining size */ + u32 vts_def; + + /* Min vertical timining size */ + u32 vts_min; + + /* Link frequency needed for this resolution */ + u32 link_freq_index; + + /* Sensor register settings for this resolution */ + const struct ov08d10_reg_list reg_list; + + /* Number of data lanes */ + u8 data_lanes; +}; + +/* 3280x2460, 3264x2448 need 720Mbps/lane, 2 lanes */ +static const struct ov08d10_reg mipi_data_rate_720mbps[] = { + {0xfd, 0x00}, + {0x11, 0x2a}, + {0x14, 0x43}, + {0x1a, 0x04}, + {0x1b, 0xe1}, + {0x1e, 0x13}, + {0xb7, 0x02} +}; + +/* 1632x1224 needs 360Mbps/lane, 2 lanes */ +static const struct ov08d10_reg mipi_data_rate_360mbps[] = { + {0xfd, 0x00}, + {0x1a, 0x04}, + {0x1b, 0xe1}, + {0x1d, 0x00}, + {0x1c, 0x19}, + {0x11, 0x2a}, + {0x14, 0x54}, + {0x1e, 0x13}, + {0xb7, 0x02} +}; + +static const struct ov08d10_reg lane_2_mode_3280x2460[] = { + /* 3280x2460 resolution */ + {0xfd, 0x01}, + {0x12, 0x00}, + {0x03, 0x12}, + {0x04, 0x58}, + {0x07, 0x05}, + {0x21, 0x02}, + {0x24, 0x30}, + {0x33, 0x03}, + {0x01, 0x03}, + {0x19, 0x10}, + {0x42, 0x55}, + {0x43, 0x00}, + {0x47, 0x07}, + {0x48, 0x08}, + {0xb2, 0x7f}, + {0xb3, 0x7b}, + {0xbd, 0x08}, + {0xd2, 0x57}, + {0xd3, 0x10}, + {0xd4, 0x08}, + {0xd5, 0x08}, + {0xd6, 0x06}, + {0xb1, 0x00}, + {0xb4, 0x00}, + {0xb7, 0x0a}, + {0xbc, 0x44}, + {0xbf, 0x48}, + {0xc1, 0x10}, + {0xc3, 0x24}, + {0xc8, 0x03}, + {0xc9, 0xf8}, + {0xe1, 0x33}, + {0xe2, 0xbb}, + {0x51, 0x0c}, + {0x52, 0x0a}, + {0x57, 0x8c}, + {0x59, 0x09}, + {0x5a, 0x08}, + {0x5e, 0x10}, + {0x60, 0x02}, + {0x6d, 0x5c}, + {0x76, 0x16}, + {0x7c, 0x11}, + {0x90, 0x28}, + {0x91, 0x16}, + {0x92, 0x1c}, + {0x93, 0x24}, + {0x95, 0x48}, + {0x9c, 0x06}, + {0xca, 0x0c}, + {0xce, 0x0d}, + {0xfd, 0x01}, + {0xc0, 0x00}, + {0xdd, 0x18}, + {0xde, 0x19}, + {0xdf, 0x32}, + {0xe0, 0x70}, + {0xfd, 0x01}, + {0xc2, 0x05}, + {0xd7, 0x88}, + {0xd8, 0x77}, + {0xd9, 0x00}, + {0xfd, 0x07}, + {0x00, 0xf8}, + {0x01, 0x2b}, + {0x05, 0x40}, + {0x08, 0x06}, + {0x09, 0x11}, + {0x28, 0x6f}, + {0x2a, 0x20}, + {0x2b, 0x05}, + {0x5e, 0x10}, + {0x52, 0x00}, + {0x53, 0x7c}, + {0x54, 0x00}, + {0x55, 0x7c}, + {0x56, 0x00}, + {0x57, 0x7c}, + {0x58, 0x00}, + {0x59, 0x7c}, + {0xfd, 0x02}, + {0x9a, 0x30}, + {0xa8, 0x02}, + {0xfd, 0x02}, + {0xa1, 0x01}, + {0xa2, 0x09}, + {0xa3, 0x9c}, + {0xa5, 0x00}, + {0xa6, 0x0c}, + {0xa7, 0xd0}, + {0xfd, 0x00}, + {0x24, 0x01}, + {0xc0, 0x16}, + {0xc1, 0x08}, + {0xc2, 0x30}, + {0x8e, 0x0c}, + {0x8f, 0xd0}, + {0x90, 0x09}, + {0x91, 0x9c}, + {0xfd, 0x05}, + {0x04, 0x40}, + {0x07, 0x00}, + {0x0d, 0x01}, + {0x0f, 0x01}, + {0x10, 0x00}, + {0x11, 0x00}, + {0x12, 0x0c}, + {0x13, 0xcf}, + {0x14, 0x00}, + {0x15, 0x00}, + {0xfd, 0x00}, + {0x20, 0x0f}, + {0xe7, 0x03}, + {0xe7, 0x00} +}; + +static const struct ov08d10_reg lane_2_mode_3264x2448[] = { + /* 3264x2448 resolution */ + {0xfd, 0x01}, + {0x12, 0x00}, + {0x03, 0x12}, + {0x04, 0x58}, + {0x07, 0x05}, + {0x21, 0x02}, + {0x24, 0x30}, + {0x33, 0x03}, + {0x01, 0x03}, + {0x19, 0x10}, + {0x42, 0x55}, + {0x43, 0x00}, + {0x47, 0x07}, + {0x48, 0x08}, + {0xb2, 0x7f}, + {0xb3, 0x7b}, + {0xbd, 0x08}, + {0xd2, 0x57}, + {0xd3, 0x10}, + {0xd4, 0x08}, + {0xd5, 0x08}, + {0xd6, 0x06}, + {0xb1, 0x00}, + {0xb4, 0x00}, + {0xb7, 0x0a}, + {0xbc, 0x44}, + {0xbf, 0x48}, + {0xc1, 0x10}, + {0xc3, 0x24}, + {0xc8, 0x03}, + {0xc9, 0xf8}, + {0xe1, 0x33}, + {0xe2, 0xbb}, + {0x51, 0x0c}, + {0x52, 0x0a}, + {0x57, 0x8c}, + {0x59, 0x09}, + {0x5a, 0x08}, + {0x5e, 0x10}, + {0x60, 0x02}, + {0x6d, 0x5c}, + {0x76, 0x16}, + {0x7c, 0x11}, + {0x90, 0x28}, + {0x91, 0x16}, + {0x92, 0x1c}, + {0x93, 0x24}, + {0x95, 0x48}, + {0x9c, 0x06}, + {0xca, 0x0c}, + {0xce, 0x0d}, + {0xfd, 0x01}, + {0xc0, 0x00}, + {0xdd, 0x18}, + {0xde, 0x19}, + {0xdf, 0x32}, + {0xe0, 0x70}, + {0xfd, 0x01}, + {0xc2, 0x05}, + {0xd7, 0x88}, + {0xd8, 0x77}, + {0xd9, 0x00}, + {0xfd, 0x07}, + {0x00, 0xf8}, + {0x01, 0x2b}, + {0x05, 0x40}, + {0x08, 0x06}, + {0x09, 0x11}, + {0x28, 0x6f}, + {0x2a, 0x20}, + {0x2b, 0x05}, + {0x5e, 0x10}, + {0x52, 0x00}, + {0x53, 0x7c}, + {0x54, 0x00}, + {0x55, 0x7c}, + {0x56, 0x00}, + {0x57, 0x7c}, + {0x58, 0x00}, + {0x59, 0x7c}, + {0xfd, 0x02}, + {0x9a, 0x30}, + {0xa8, 0x02}, + {0xfd, 0x02}, + {0xa1, 0x09}, + {0xa2, 0x09}, + {0xa3, 0x90}, + {0xa5, 0x08}, + {0xa6, 0x0c}, + {0xa7, 0xc0}, + {0xfd, 0x00}, + {0x24, 0x01}, + {0xc0, 0x16}, + {0xc1, 0x08}, + {0xc2, 0x30}, + {0x8e, 0x0c}, + {0x8f, 0xc0}, + {0x90, 0x09}, + {0x91, 0x90}, + {0xfd, 0x05}, + {0x04, 0x40}, + {0x07, 0x00}, + {0x0d, 0x01}, + {0x0f, 0x01}, + {0x10, 0x00}, + {0x11, 0x00}, + {0x12, 0x0c}, + {0x13, 0xcf}, + {0x14, 0x00}, + {0x15, 0x00}, + {0xfd, 0x00}, + {0x20, 0x0f}, + {0xe7, 0x03}, + {0xe7, 0x00} +}; + +static const struct ov08d10_reg lane_2_mode_1632x1224[] = { + /* 1640x1232 resolution */ + {0xfd, 0x01}, + {0x1a, 0x0a}, + {0x1b, 0x08}, + {0x2a, 0x01}, + {0x2b, 0x9a}, + {0xfd, 0x01}, + {0x12, 0x00}, + {0x03, 0x05}, + {0x04, 0xe2}, + {0x07, 0x05}, + {0x21, 0x02}, + {0x24, 0x30}, + {0x33, 0x03}, + {0x31, 0x06}, + {0x33, 0x03}, + {0x01, 0x03}, + {0x19, 0x10}, + {0x42, 0x55}, + {0x43, 0x00}, + {0x47, 0x07}, + {0x48, 0x08}, + {0xb2, 0x7f}, + {0xb3, 0x7b}, + {0xbd, 0x08}, + {0xd2, 0x57}, + {0xd3, 0x10}, + {0xd4, 0x08}, + {0xd5, 0x08}, + {0xd6, 0x06}, + {0xb1, 0x00}, + {0xb4, 0x00}, + {0xb7, 0x0a}, + {0xbc, 0x44}, + {0xbf, 0x48}, + {0xc1, 0x10}, + {0xc3, 0x24}, + {0xc8, 0x03}, + {0xc9, 0xf8}, + {0xe1, 0x33}, + {0xe2, 0xbb}, + {0x51, 0x0c}, + {0x52, 0x0a}, + {0x57, 0x8c}, + {0x59, 0x09}, + {0x5a, 0x08}, + {0x5e, 0x10}, + {0x60, 0x02}, + {0x6d, 0x5c}, + {0x76, 0x16}, + {0x7c, 0x1a}, + {0x90, 0x28}, + {0x91, 0x16}, + {0x92, 0x1c}, + {0x93, 0x24}, + {0x95, 0x48}, + {0x9c, 0x06}, + {0xca, 0x0c}, + {0xce, 0x0d}, + {0xfd, 0x01}, + {0xc0, 0x00}, + {0xdd, 0x18}, + {0xde, 0x19}, + {0xdf, 0x32}, + {0xe0, 0x70}, + {0xfd, 0x01}, + {0xc2, 0x05}, + {0xd7, 0x88}, + {0xd8, 0x77}, + {0xd9, 0x00}, + {0xfd, 0x07}, + {0x00, 0xf8}, + {0x01, 0x2b}, + {0x05, 0x40}, + {0x08, 0x03}, + {0x09, 0x08}, + {0x28, 0x6f}, + {0x2a, 0x20}, + {0x2b, 0x05}, + {0x2c, 0x01}, + {0x50, 0x02}, + {0x51, 0x03}, + {0x5e, 0x00}, + {0x52, 0x00}, + {0x53, 0x7c}, + {0x54, 0x00}, + {0x55, 0x7c}, + {0x56, 0x00}, + {0x57, 0x7c}, + {0x58, 0x00}, + {0x59, 0x7c}, + {0xfd, 0x02}, + {0x9a, 0x30}, + {0xa8, 0x02}, + {0xfd, 0x02}, + {0xa9, 0x04}, + {0xaa, 0xd0}, + {0xab, 0x06}, + {0xac, 0x68}, + {0xa1, 0x09}, + {0xa2, 0x04}, + {0xa3, 0xc8}, + {0xa5, 0x04}, + {0xa6, 0x06}, + {0xa7, 0x60}, + {0xfd, 0x05}, + {0x06, 0x80}, + {0x18, 0x06}, + {0x19, 0x68}, + {0xfd, 0x00}, + {0x24, 0x01}, + {0xc0, 0x16}, + {0xc1, 0x08}, + {0xc2, 0x30}, + {0x8e, 0x06}, + {0x8f, 0x60}, + {0x90, 0x04}, + {0x91, 0xc8}, + {0x93, 0x0e}, + {0x94, 0x77}, + {0x95, 0x77}, + {0x96, 0x10}, + {0x98, 0x88}, + {0x9c, 0x1a}, + {0xfd, 0x05}, + {0x04, 0x40}, + {0x07, 0x99}, + {0x0d, 0x03}, + {0x0f, 0x03}, + {0x10, 0x00}, + {0x11, 0x00}, + {0x12, 0x0c}, + {0x13, 0xcf}, + {0x14, 0x00}, + {0x15, 0x00}, + {0xfd, 0x00}, + {0x20, 0x0f}, + {0xe7, 0x03}, + {0xe7, 0x00}, +}; + +static const char * const ov08d10_test_pattern_menu[] = { + "Disabled", + "Standard Color Bar", +}; + +struct ov08d10 { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_ctrl_handler ctrl_handler; + + struct clk *xvclk; + + /* V4L2 Controls */ + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *vblank; + struct v4l2_ctrl *hblank; + struct v4l2_ctrl *vflip; + struct v4l2_ctrl *hflip; + struct v4l2_ctrl *exposure; + + /* Current mode */ + const struct ov08d10_mode *cur_mode; + + /* To serialize asynchronus callbacks */ + struct mutex mutex; + + /* Streaming on/off */ + bool streaming; + + /* lanes index */ + u8 nlanes; + + const struct ov08d10_lane_cfg *priv_lane; + u8 modes_size; +}; + +struct ov08d10_lane_cfg { + const s64 link_freq_menu[2]; + const struct ov08d10_link_freq_config link_freq_configs[2]; + const struct ov08d10_mode sp_modes[3]; +}; + +static const struct ov08d10_lane_cfg lane_cfg_2 = { + { + 720000000, + 360000000, + }, + {{ + .reg_list = { + .num_of_regs = + ARRAY_SIZE(mipi_data_rate_720mbps), + .regs = mipi_data_rate_720mbps, + } + }, + { + .reg_list = { + .num_of_regs = + ARRAY_SIZE(mipi_data_rate_360mbps), + .regs = mipi_data_rate_360mbps, + } + }}, + {{ + .width = 3280, + .height = 2460, + .hts = 1840, + .vts_def = 2504, + .vts_min = 2504, + .reg_list = { + .num_of_regs = ARRAY_SIZE(lane_2_mode_3280x2460), + .regs = lane_2_mode_3280x2460, + }, + .link_freq_index = 0, + .data_lanes = 2, + }, + { + .width = 3264, + .height = 2448, + .hts = 1840, + .vts_def = 2504, + .vts_min = 2504, + .reg_list = { + .num_of_regs = ARRAY_SIZE(lane_2_mode_3264x2448), + .regs = lane_2_mode_3264x2448, + }, + .link_freq_index = 0, + .data_lanes = 2, + }, + { + .width = 1632, + .height = 1224, + .hts = 1912, + .vts_def = 3736, + .vts_min = 3736, + .reg_list = { + .num_of_regs = ARRAY_SIZE(lane_2_mode_1632x1224), + .regs = lane_2_mode_1632x1224, + }, + .link_freq_index = 1, + .data_lanes = 2, + }} +}; + +static u32 ov08d10_get_format_code(struct ov08d10 *ov08d10) +{ + static const u32 codes[2][2] = { + { MEDIA_BUS_FMT_SGRBG10_1X10, MEDIA_BUS_FMT_SRGGB10_1X10}, + { MEDIA_BUS_FMT_SBGGR10_1X10, MEDIA_BUS_FMT_SGBRG10_1X10}, + }; + + return codes[ov08d10->vflip->val][ov08d10->hflip->val]; +} + +static unsigned int ov08d10_modes_num(const struct ov08d10 *ov08d10) +{ + unsigned int i, count = 0; + + for (i = 0; i < ARRAY_SIZE(ov08d10->priv_lane->sp_modes); i++) { + if (ov08d10->priv_lane->sp_modes[i].width == 0) + break; + count++; + } + + return count; +} + +static u64 to_rate(const s64 *link_freq_menu, + u32 f_index, u8 nlanes) +{ + u64 pixel_rate = link_freq_menu[f_index] * 2 * nlanes; + + do_div(pixel_rate, OV08D10_RGB_DEPTH); + + return pixel_rate; +} + +static u64 to_pixels_per_line(const s64 *link_freq_menu, u32 hts, + u32 f_index, u8 nlanes) +{ + u64 ppl = hts * to_rate(link_freq_menu, f_index, nlanes); + + do_div(ppl, OV08D10_SCLK); + + return ppl; +} + +static int ov08d10_write_reg_list(struct ov08d10 *ov08d10, + const struct ov08d10_reg_list *r_list) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); + unsigned int i; + int ret; + + for (i = 0; i < r_list->num_of_regs; i++) { + ret = i2c_smbus_write_byte_data(client, r_list->regs[i].address, + r_list->regs[i].val); + if (ret) { + dev_err_ratelimited(&client->dev, + "failed to write reg 0x%2.2x. error = %d", + r_list->regs[i].address, ret); + return ret; + } + } + + return 0; +} + +static int ov08d10_update_analog_gain(struct ov08d10 *ov08d10, u32 a_gain) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); + u8 val; + int ret; + + val = ((a_gain >> 3) & 0xFF); + /* CIS control registers */ + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); + if (ret < 0) + return ret; + + /* update AGAIN */ + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_ANALOG_GAIN, val); + if (ret < 0) + return ret; + + return i2c_smbus_write_byte_data(client, + OV08D10_REG_GLOBAL_EFFECTIVE, 0x01); +} + +static int ov08d10_update_digital_gain(struct ov08d10 *ov08d10, u32 d_gain) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); + u8 val; + int ret; + + d_gain = (d_gain >> 1); + /* CIS control registers */ + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); + if (ret < 0) + return ret; + + val = ((d_gain >> 8) & 0x3F); + /* update DGAIN */ + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_MWB_DGAIN_C, val); + if (ret < 0) + return ret; + + val = d_gain & 0xFF; + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_MWB_DGAIN_F, val); + if (ret < 0) + return ret; + + return i2c_smbus_write_byte_data(client, + OV08D10_REG_GLOBAL_EFFECTIVE, 0x01); +} + +static int ov08d10_set_exposure(struct ov08d10 *ov08d10, u32 exposure) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); + u8 val; + u8 hts_h, hts_l; + u32 hts, cur_vts, exp_cal; + int ret; + + cur_vts = ov08d10->cur_mode->vts_def; + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); + if (ret < 0) + return ret; + + hts_h = i2c_smbus_read_byte_data(client, 0x37); + hts_l = i2c_smbus_read_byte_data(client, 0x38); + hts = ((hts_h << 8) | (hts_l)); + exp_cal = 66 * OV08D10_ROWCLK / hts; + exposure = exposure * exp_cal / (cur_vts - OV08D10_EXPOSURE_MAX_MARGIN); + /* CIS control registers */ + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); + if (ret < 0) + return ret; + + /* update exposure */ + val = ((exposure >> 16) & 0xFF); + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_EXPOSURE_H, val); + if (ret < 0) + return ret; + + val = ((exposure >> 8) & 0xFF); + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_EXPOSURE_M, val); + if (ret < 0) + return ret; + + val = exposure & 0xFF; + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_EXPOSURE_L, val); + if (ret < 0) + return ret; + + return i2c_smbus_write_byte_data(client, + OV08D10_REG_GLOBAL_EFFECTIVE, 0x01); +} + +static int ov08d10_set_vblank(struct ov08d10 *ov08d10, u32 vblank) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); + u8 val; + int ret; + + /* CIS control registers */ + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); + if (ret < 0) + return ret; + + val = ((vblank >> 8) & 0xFF); + /* update vblank */ + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_VTS_H, val); + if (ret < 0) + return ret; + + val = vblank & 0xFF; + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_VTS_L, val); + if (ret < 0) + return ret; + + return i2c_smbus_write_byte_data(client, + OV08D10_REG_GLOBAL_EFFECTIVE, 0x01); +} + +static int ov08d10_test_pattern(struct ov08d10 *ov08d10, u32 pattern) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); + u8 val; + int ret; + + if (pattern) + val = OV08D10_TEST_PATTERN_ENABLE; + else + val = OV08D10_TEST_PATTERN_DISABLE; + + /* CIS control registers */ + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(client, + OV08D10_REG_TEST_PATTERN, val); + if (ret < 0) + return ret; + + return i2c_smbus_write_byte_data(client, + OV08D10_REG_GLOBAL_EFFECTIVE, 0x01); +} + +static int ov08d10_set_ctrl_flip(struct ov08d10 *ov08d10, u32 ctrl_val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); + u8 val; + int ret; + + /* System control registers */ + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); + if (ret < 0) + return ret; + + ret = i2c_smbus_read_byte_data(client, OV08D10_REG_FLIP_OPT); + if (ret < 0) + return ret; + + val = ret | (ctrl_val & OV08D10_REG_FLIP_MASK); + + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_FLIP_OPT, val); + + if (ret < 0) + return ret; + + return i2c_smbus_write_byte_data(client, + OV08D10_REG_GLOBAL_EFFECTIVE, 0x01); +} + +static int ov08d10_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov08d10 *ov08d10 = container_of(ctrl->handler, + struct ov08d10, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); + s64 exposure_max; + int ret; + + /* Propagate change of current control to all related controls */ + if (ctrl->id == V4L2_CID_VBLANK) { + /* Update max exposure while meeting expected vblanking */ + exposure_max = ov08d10->cur_mode->height + ctrl->val - + OV08D10_EXPOSURE_MAX_MARGIN; + __v4l2_ctrl_modify_range(ov08d10->exposure, + ov08d10->exposure->minimum, + exposure_max, ov08d10->exposure->step, + exposure_max); + } + + /* V4L2 controls values will be applied only when power is already up */ + if (!pm_runtime_get_if_in_use(&client->dev)) + return 0; + + switch (ctrl->id) { + case V4L2_CID_ANALOGUE_GAIN: + ret = ov08d10_update_analog_gain(ov08d10, ctrl->val); + break; + + case V4L2_CID_DIGITAL_GAIN: + ret = ov08d10_update_digital_gain(ov08d10, ctrl->val); + break; + + case V4L2_CID_EXPOSURE: + ret = ov08d10_set_exposure(ov08d10, ctrl->val); + break; + + case V4L2_CID_VBLANK: + ret = ov08d10_set_vblank(ov08d10, ctrl->val); + break; + + case V4L2_CID_TEST_PATTERN: + ret = ov08d10_test_pattern(ov08d10, ctrl->val); + break; + + case V4L2_CID_HFLIP: + case V4L2_CID_VFLIP: + ret = ov08d10_set_ctrl_flip(ov08d10, + ov08d10->hflip->val | + ov08d10->vflip->val << 1); + break; + + default: + ret = -EINVAL; + break; + } + + pm_runtime_put(&client->dev); + + return ret; +} + +static const struct v4l2_ctrl_ops ov08d10_ctrl_ops = { + .s_ctrl = ov08d10_set_ctrl, +}; + +static int ov08d10_init_controls(struct ov08d10 *ov08d10) +{ + struct v4l2_ctrl_handler *ctrl_hdlr; + u8 link_freq_size; + s64 exposure_max; + s64 vblank_def; + s64 vblank_min; + s64 h_blank; + s64 pixel_rate_max; + const struct ov08d10_mode *mode; + int ret; + + ctrl_hdlr = &ov08d10->ctrl_handler; + ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8); + if (ret) + return ret; + + ctrl_hdlr->lock = &ov08d10->mutex; + link_freq_size = ARRAY_SIZE(ov08d10->priv_lane->link_freq_menu); + ov08d10->link_freq = + v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov08d10_ctrl_ops, + V4L2_CID_LINK_FREQ, + link_freq_size - 1, + 0, + ov08d10->priv_lane->link_freq_menu); + if (ov08d10->link_freq) + ov08d10->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + pixel_rate_max = to_rate(ov08d10->priv_lane->link_freq_menu, 0, + ov08d10->cur_mode->data_lanes); + ov08d10->pixel_rate = + v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, + V4L2_CID_PIXEL_RATE, 0, pixel_rate_max, 1, + pixel_rate_max); + + mode = ov08d10->cur_mode; + vblank_def = mode->vts_def - mode->height; + vblank_min = mode->vts_min - mode->height; + ov08d10->vblank = + v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, + V4L2_CID_VBLANK, vblank_min, + OV08D10_VTS_MAX - mode->height, 1, + vblank_def); + + h_blank = to_pixels_per_line(ov08d10->priv_lane->link_freq_menu, + mode->hts, mode->link_freq_index, + mode->data_lanes) - + mode->width; + ov08d10->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, + V4L2_CID_HBLANK, h_blank, h_blank, + 1, h_blank); + if (ov08d10->hblank) + ov08d10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, + OV08D10_ANAL_GAIN_MIN, OV08D10_ANAL_GAIN_MAX, + OV08D10_ANAL_GAIN_STEP, OV08D10_ANAL_GAIN_MIN); + + v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, V4L2_CID_DIGITAL_GAIN, + OV08D10_DGTL_GAIN_MIN, OV08D10_DGTL_GAIN_MAX, + OV08D10_DGTL_GAIN_STEP, OV08D10_DGTL_GAIN_DEFAULT); + + exposure_max = mode->vts_def - OV08D10_EXPOSURE_MAX_MARGIN; + ov08d10->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, + V4L2_CID_EXPOSURE, + OV08D10_EXPOSURE_MIN, + exposure_max, + OV08D10_EXPOSURE_STEP, + exposure_max); + + v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov08d10_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(ov08d10_test_pattern_menu) - 1, + 0, 0, ov08d10_test_pattern_menu); + + ov08d10->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, + V4L2_CID_HFLIP, 0, 1, 1, 0); + ov08d10->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, + V4L2_CID_VFLIP, 0, 1, 1, 0); + if (ctrl_hdlr->error) + return ctrl_hdlr->error; + + ov08d10->sd.ctrl_handler = ctrl_hdlr; + + return 0; +} + +static void ov08d10_update_pad_format(struct ov08d10 *ov08d10, + const struct ov08d10_mode *mode, + struct v4l2_mbus_framefmt *fmt) +{ + fmt->width = mode->width; + fmt->height = mode->height; + fmt->code = ov08d10_get_format_code(ov08d10); + fmt->field = V4L2_FIELD_NONE; +} + +static int ov08d10_start_streaming(struct ov08d10 *ov08d10) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); + const struct ov08d10_reg_list *reg_list; + int link_freq_index, ret; + + link_freq_index = ov08d10->cur_mode->link_freq_index; + reg_list = + &ov08d10->priv_lane->link_freq_configs[link_freq_index].reg_list; + + /* soft reset */ + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x00); + if (ret < 0) { + dev_err(&client->dev, "failed to reset sensor"); + return ret; + } + ret = i2c_smbus_write_byte_data(client, 0x20, 0x0e); + if (ret < 0) { + dev_err(&client->dev, "failed to reset sensor"); + return ret; + } + usleep_range(3000, 4000); + ret = i2c_smbus_write_byte_data(client, 0x20, 0x0b); + if (ret < 0) { + dev_err(&client->dev, "failed to reset sensor"); + return ret; + } + + /* update sensor setting */ + ret = ov08d10_write_reg_list(ov08d10, reg_list); + if (ret) { + dev_err(&client->dev, "failed to set plls"); + return ret; + } + + reg_list = &ov08d10->cur_mode->reg_list; + ret = ov08d10_write_reg_list(ov08d10, reg_list); + if (ret) { + dev_err(&client->dev, "failed to set mode"); + return ret; + } + + ret = __v4l2_ctrl_handler_setup(ov08d10->sd.ctrl_handler); + if (ret) + return ret; + + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x00); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_MODE_SELECT, + OV08D10_MODE_STREAMING); + if (ret < 0) + return ret; + + return i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); +} + +static void ov08d10_stop_streaming(struct ov08d10 *ov08d10) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); + int ret; + + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x00); + if (ret < 0) { + dev_err(&client->dev, "failed to stop streaming"); + return; + } + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_MODE_SELECT, + OV08D10_MODE_STANDBY); + if (ret < 0) { + dev_err(&client->dev, "failed to stop streaming"); + return; + } + + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01); + if (ret < 0) { + dev_err(&client->dev, "failed to stop streaming"); + return; + } +} + +static int ov08d10_set_stream(struct v4l2_subdev *sd, int enable) +{ + struct ov08d10 *ov08d10 = to_ov08d10(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (ov08d10->streaming == enable) + return 0; + + mutex_lock(&ov08d10->mutex); + if (enable) { + ret = pm_runtime_resume_and_get(&client->dev); + if (ret < 0) { + mutex_unlock(&ov08d10->mutex); + return ret; + } + + ret = ov08d10_start_streaming(ov08d10); + if (ret) { + enable = 0; + ov08d10_stop_streaming(ov08d10); + pm_runtime_put(&client->dev); + } + } else { + ov08d10_stop_streaming(ov08d10); + pm_runtime_put(&client->dev); + } + + ov08d10->streaming = enable; + + /* vflip and hflip cannot change during streaming */ + __v4l2_ctrl_grab(ov08d10->vflip, enable); + __v4l2_ctrl_grab(ov08d10->hflip, enable); + + mutex_unlock(&ov08d10->mutex); + + return ret; +} + +static int __maybe_unused ov08d10_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov08d10 *ov08d10 = to_ov08d10(sd); + + mutex_lock(&ov08d10->mutex); + if (ov08d10->streaming) + ov08d10_stop_streaming(ov08d10); + + mutex_unlock(&ov08d10->mutex); + + return 0; +} + +static int __maybe_unused ov08d10_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov08d10 *ov08d10 = to_ov08d10(sd); + int ret; + + mutex_lock(&ov08d10->mutex); + + if (ov08d10->streaming) { + ret = ov08d10_start_streaming(ov08d10); + if (ret) { + ov08d10->streaming = false; + ov08d10_stop_streaming(ov08d10); + mutex_unlock(&ov08d10->mutex); + return ret; + } + } + + mutex_unlock(&ov08d10->mutex); + + return 0; +} + +static int ov08d10_set_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct ov08d10 *ov08d10 = to_ov08d10(sd); + const struct ov08d10_mode *mode; + s32 vblank_def, h_blank; + s64 pixel_rate; + + mode = v4l2_find_nearest_size(ov08d10->priv_lane->sp_modes, + ov08d10->modes_size, + width, height, fmt->format.width, + fmt->format.height); + + mutex_lock(&ov08d10->mutex); + ov08d10_update_pad_format(ov08d10, mode, &fmt->format); + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { + *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = + fmt->format; + } else { + ov08d10->cur_mode = mode; + __v4l2_ctrl_s_ctrl(ov08d10->link_freq, mode->link_freq_index); + pixel_rate = to_rate(ov08d10->priv_lane->link_freq_menu, + mode->link_freq_index, + ov08d10->cur_mode->data_lanes); + __v4l2_ctrl_s_ctrl_int64(ov08d10->pixel_rate, pixel_rate); + + /* Update limits and set FPS to default */ + vblank_def = mode->vts_def - mode->height; + __v4l2_ctrl_modify_range(ov08d10->vblank, + mode->vts_min - mode->height, + OV08D10_VTS_MAX - mode->height, 1, + vblank_def); + __v4l2_ctrl_s_ctrl(ov08d10->vblank, vblank_def); + h_blank = to_pixels_per_line(ov08d10->priv_lane->link_freq_menu, + mode->hts, + mode->link_freq_index, + ov08d10->cur_mode->data_lanes) + - mode->width; + __v4l2_ctrl_modify_range(ov08d10->hblank, h_blank, h_blank, 1, + h_blank); + } + + mutex_unlock(&ov08d10->mutex); + + return 0; +} + +static int ov08d10_get_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct ov08d10 *ov08d10 = to_ov08d10(sd); + + mutex_lock(&ov08d10->mutex); + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) + fmt->format = *v4l2_subdev_get_try_format(&ov08d10->sd, + sd_state, + fmt->pad); + else + ov08d10_update_pad_format(ov08d10, ov08d10->cur_mode, + &fmt->format); + + mutex_unlock(&ov08d10->mutex); + + return 0; +} + +static int ov08d10_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct ov08d10 *ov08d10 = to_ov08d10(sd); + + if (code->index > 0) + return -EINVAL; + + mutex_lock(&ov08d10->mutex); + code->code = ov08d10_get_format_code(ov08d10); + mutex_unlock(&ov08d10->mutex); + + return 0; +} + +static int ov08d10_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct ov08d10 *ov08d10 = to_ov08d10(sd); + + if (fse->index >= ov08d10->modes_size) + return -EINVAL; + + mutex_lock(&ov08d10->mutex); + if (fse->code != ov08d10_get_format_code(ov08d10)) { + mutex_unlock(&ov08d10->mutex); + return -EINVAL; + } + mutex_unlock(&ov08d10->mutex); + + fse->min_width = ov08d10->priv_lane->sp_modes[fse->index].width; + fse->max_width = fse->min_width; + fse->min_height = ov08d10->priv_lane->sp_modes[fse->index].height; + fse->max_height = fse->min_height; + + return 0; +} + +static int ov08d10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct ov08d10 *ov08d10 = to_ov08d10(sd); + + mutex_lock(&ov08d10->mutex); + ov08d10_update_pad_format(ov08d10, &ov08d10->priv_lane->sp_modes[0], + v4l2_subdev_get_try_format(sd, fh->state, 0)); + mutex_unlock(&ov08d10->mutex); + + return 0; +} + +static const struct v4l2_subdev_video_ops ov08d10_video_ops = { + .s_stream = ov08d10_set_stream, +}; + +static const struct v4l2_subdev_pad_ops ov08d10_pad_ops = { + .set_fmt = ov08d10_set_format, + .get_fmt = ov08d10_get_format, + .enum_mbus_code = ov08d10_enum_mbus_code, + .enum_frame_size = ov08d10_enum_frame_size, +}; + +static const struct v4l2_subdev_ops ov08d10_subdev_ops = { + .video = &ov08d10_video_ops, + .pad = &ov08d10_pad_ops, +}; + +static const struct v4l2_subdev_internal_ops ov08d10_internal_ops = { + .open = ov08d10_open, +}; + +static int ov08d10_identify_module(struct ov08d10 *ov08d10) +{ + struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd); + u32 val; + u16 chip_id; + int ret; + + /* System control registers */ + ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x00); + if (ret < 0) + return ret; + + /* Validate the chip ID */ + ret = i2c_smbus_read_byte_data(client, OV08D10_REG_CHIP_ID_0); + if (ret < 0) + return ret; + + val = ret << 8; + + ret = i2c_smbus_read_byte_data(client, OV08D10_REG_CHIP_ID_1); + if (ret < 0) + return ret; + + chip_id = val | ret; + + if ((chip_id & OV08D10_ID_MASK) != OV08D10_CHIP_ID) { + dev_err(&client->dev, "unexpected sensor id(0x%04x)\n", + chip_id); + return -EINVAL; + } + + return 0; +} + +static int ov08d10_get_hwcfg(struct ov08d10 *ov08d10, struct device *dev) +{ + struct fwnode_handle *ep; + struct fwnode_handle *fwnode = dev_fwnode(dev); + struct v4l2_fwnode_endpoint bus_cfg = { + .bus_type = V4L2_MBUS_CSI2_DPHY + }; + u32 xvclk_rate; + unsigned int i, j; + int ret; + + if (!fwnode) + return -ENXIO; + + ret = fwnode_property_read_u32(fwnode, "clock-frequency", &xvclk_rate); + if (ret) + return ret; + + if (xvclk_rate != OV08D10_XVCLK_19_2) + dev_warn(dev, "external clock rate %u is unsupported", + xvclk_rate); + + ep = fwnode_graph_get_next_endpoint(fwnode, NULL); + if (!ep) + return -ENXIO; + + ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); + fwnode_handle_put(ep); + if (ret) + return ret; + + /* Get number of data lanes */ + if (bus_cfg.bus.mipi_csi2.num_data_lanes != 2) { + dev_err(dev, "number of CSI2 data lanes %d is not supported", + bus_cfg.bus.mipi_csi2.num_data_lanes); + ret = -EINVAL; + goto check_hwcfg_error; + } + + dev_dbg(dev, "Using %u data lanes\n", ov08d10->cur_mode->data_lanes); + + ov08d10->priv_lane = &lane_cfg_2; + ov08d10->modes_size = ov08d10_modes_num(ov08d10); + + if (!bus_cfg.nr_of_link_frequencies) { + dev_err(dev, "no link frequencies defined"); + ret = -EINVAL; + goto check_hwcfg_error; + } + + for (i = 0; i < ARRAY_SIZE(ov08d10->priv_lane->link_freq_menu); i++) { + for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { + if (ov08d10->priv_lane->link_freq_menu[i] == + bus_cfg.link_frequencies[j]) + break; + } + + if (j == bus_cfg.nr_of_link_frequencies) { + dev_err(dev, "no link frequency %lld supported", + ov08d10->priv_lane->link_freq_menu[i]); + ret = -EINVAL; + goto check_hwcfg_error; + } + } + +check_hwcfg_error: + v4l2_fwnode_endpoint_free(&bus_cfg); + + return ret; +} + +static int ov08d10_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov08d10 *ov08d10 = to_ov08d10(sd); + + v4l2_async_unregister_subdev(sd); + media_entity_cleanup(&sd->entity); + v4l2_ctrl_handler_free(sd->ctrl_handler); + pm_runtime_disable(&client->dev); + mutex_destroy(&ov08d10->mutex); + + return 0; +} + +static int ov08d10_probe(struct i2c_client *client) +{ + struct ov08d10 *ov08d10; + int ret; + + ov08d10 = devm_kzalloc(&client->dev, sizeof(*ov08d10), GFP_KERNEL); + if (!ov08d10) + return -ENOMEM; + + ret = ov08d10_get_hwcfg(ov08d10, &client->dev); + if (ret) { + dev_err(&client->dev, "failed to get HW configuration: %d", + ret); + return ret; + } + + v4l2_i2c_subdev_init(&ov08d10->sd, client, &ov08d10_subdev_ops); + + ret = ov08d10_identify_module(ov08d10); + if (ret) { + dev_err(&client->dev, "failed to find sensor: %d", ret); + return ret; + } + + mutex_init(&ov08d10->mutex); + ov08d10->cur_mode = &ov08d10->priv_lane->sp_modes[0]; + ret = ov08d10_init_controls(ov08d10); + if (ret) { + dev_err(&client->dev, "failed to init controls: %d", ret); + goto probe_error_v4l2_ctrl_handler_free; + } + + ov08d10->sd.internal_ops = &ov08d10_internal_ops; + ov08d10->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + ov08d10->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + ov08d10->pad.flags = MEDIA_PAD_FL_SOURCE; + ret = media_entity_pads_init(&ov08d10->sd.entity, 1, &ov08d10->pad); + if (ret) { + dev_err(&client->dev, "failed to init entity pads: %d", ret); + goto probe_error_v4l2_ctrl_handler_free; + } + + ret = v4l2_async_register_subdev_sensor(&ov08d10->sd); + if (ret < 0) { + dev_err(&client->dev, "failed to register V4L2 subdev: %d", + ret); + goto probe_error_media_entity_cleanup; + } + + /* + * Device is already turned on by i2c-core with ACPI domain PM. + * Enable runtime PM and turn off the device. + */ + pm_runtime_set_active(&client->dev); + pm_runtime_enable(&client->dev); + pm_runtime_idle(&client->dev); + + return 0; + +probe_error_media_entity_cleanup: + media_entity_cleanup(&ov08d10->sd.entity); + +probe_error_v4l2_ctrl_handler_free: + v4l2_ctrl_handler_free(ov08d10->sd.ctrl_handler); + mutex_destroy(&ov08d10->mutex); + + return ret; +} + +static const struct dev_pm_ops ov08d10_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(ov08d10_suspend, ov08d10_resume) +}; + +#ifdef CONFIG_ACPI +static const struct acpi_device_id ov08d10_acpi_ids[] = { + { "OVTI08D1" }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(acpi, ov08d10_acpi_ids); +#endif + +static struct i2c_driver ov08d10_i2c_driver = { + .driver = { + .name = "ov08d10", + .pm = &ov08d10_pm_ops, + .acpi_match_table = ACPI_PTR(ov08d10_acpi_ids), + }, + .probe_new = ov08d10_probe, + .remove = ov08d10_remove, +}; + +module_i2c_driver(ov08d10_i2c_driver); + +MODULE_AUTHOR("Su, Jimmy <jimmy.su@intel.com>"); +MODULE_DESCRIPTION("OmniVision ov08d10 sensor driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/media/i2c/ov2740.c b/drivers/media/i2c/ov2740.c index bab720c7c1de..d5f0eabf20c6 100644 --- a/drivers/media/i2c/ov2740.c +++ b/drivers/media/i2c/ov2740.c @@ -1162,6 +1162,7 @@ static int ov2740_probe(struct i2c_client *client) if (!ov2740) return -ENOMEM; + v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops); full_power = acpi_dev_state_d0(&client->dev); if (full_power) { ret = ov2740_identify_module(ov2740); @@ -1171,13 +1172,6 @@ static int ov2740_probe(struct i2c_client *client) } } - v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops); - ret = ov2740_identify_module(ov2740); - if (ret) { - dev_err(&client->dev, "failed to find sensor: %d", ret); - return ret; - } - mutex_init(&ov2740->mutex); ov2740->cur_mode = &supported_modes[0]; ret = ov2740_init_controls(ov2740); diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c index ddbd71394db3..db5a19babe67 100644 --- a/drivers/media/i2c/ov5640.c +++ b/drivers/media/i2c/ov5640.c @@ -2293,7 +2293,6 @@ static int ov5640_set_fmt(struct v4l2_subdev *sd, struct ov5640_dev *sensor = to_ov5640_dev(sd); const struct ov5640_mode_info *new_mode; struct v4l2_mbus_framefmt *mbus_fmt = &format->format; - struct v4l2_mbus_framefmt *fmt; int ret; if (format->pad != 0) @@ -2311,12 +2310,10 @@ static int ov5640_set_fmt(struct v4l2_subdev *sd, if (ret) goto out; - if (format->which == V4L2_SUBDEV_FORMAT_TRY) - fmt = v4l2_subdev_get_try_format(sd, sd_state, 0); - else - fmt = &sensor->fmt; - - *fmt = *mbus_fmt; + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + *v4l2_subdev_get_try_format(sd, sd_state, 0) = *mbus_fmt; + goto out; + } if (new_mode != sensor->current_mode) { sensor->current_mode = new_mode; @@ -2325,6 +2322,9 @@ static int ov5640_set_fmt(struct v4l2_subdev *sd, if (mbus_fmt->code != sensor->fmt.code) sensor->pending_fmt_change = true; + /* update format even if code is unchanged, resolution might change */ + sensor->fmt = *mbus_fmt; + __v4l2_ctrl_s_ctrl_int64(sensor->ctrls.pixel_rate, ov5640_calc_pixel_rate(sensor)); out: diff --git a/drivers/media/i2c/ov5648.c b/drivers/media/i2c/ov5648.c index 947d437ed0ef..930ff6897044 100644 --- a/drivers/media/i2c/ov5648.c +++ b/drivers/media/i2c/ov5648.c @@ -639,7 +639,7 @@ struct ov5648_ctrls { struct v4l2_ctrl *pixel_rate; struct v4l2_ctrl_handler handler; -} __packed; +}; struct ov5648_sensor { struct device *dev; @@ -1112,7 +1112,7 @@ static int ov5648_pad_configure(struct ov5648_sensor *sensor) static int ov5648_mipi_configure(struct ov5648_sensor *sensor) { - struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 = + struct v4l2_mbus_config_mipi_csi2 *bus_mipi_csi2 = &sensor->endpoint.bus.mipi_csi2; unsigned int lanes_count = bus_mipi_csi2->num_data_lanes; int ret; @@ -1692,7 +1692,7 @@ static int ov5648_state_mipi_configure(struct ov5648_sensor *sensor, u32 mbus_code) { struct ov5648_ctrls *ctrls = &sensor->ctrls; - struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 = + struct v4l2_mbus_config_mipi_csi2 *bus_mipi_csi2 = &sensor->endpoint.bus.mipi_csi2; unsigned long mipi_clk_rate; unsigned int bits_per_sample; @@ -1778,8 +1778,14 @@ static int ov5648_state_configure(struct ov5648_sensor *sensor, static int ov5648_state_init(struct ov5648_sensor *sensor) { - return ov5648_state_configure(sensor, &ov5648_modes[0], - ov5648_mbus_codes[0]); + int ret; + + mutex_lock(&sensor->mutex); + ret = ov5648_state_configure(sensor, &ov5648_modes[0], + ov5648_mbus_codes[0]); + mutex_unlock(&sensor->mutex); + + return ret; } /* Sensor Base */ diff --git a/drivers/media/i2c/ov5675.c b/drivers/media/i2c/ov5675.c index 00925850fa7c..82ba9f56baec 100644 --- a/drivers/media/i2c/ov5675.c +++ b/drivers/media/i2c/ov5675.c @@ -50,14 +50,21 @@ #define OV5675_ANAL_GAIN_STEP 1 /* Digital gain controls from sensor */ +#define OV5675_REG_DIGITAL_GAIN 0x350a #define OV5675_REG_MWB_R_GAIN 0x5019 #define OV5675_REG_MWB_G_GAIN 0x501b #define OV5675_REG_MWB_B_GAIN 0x501d -#define OV5675_DGTL_GAIN_MIN 0 +#define OV5675_DGTL_GAIN_MIN 1024 #define OV5675_DGTL_GAIN_MAX 4095 #define OV5675_DGTL_GAIN_STEP 1 #define OV5675_DGTL_GAIN_DEFAULT 1024 +/* Group Access */ +#define OV5675_REG_GROUP_ACCESS 0x3208 +#define OV5675_GROUP_HOLD_START 0x0 +#define OV5675_GROUP_HOLD_END 0x10 +#define OV5675_GROUP_HOLD_LAUNCH 0xa0 + /* Test Pattern Control */ #define OV5675_REG_TEST_PATTERN 0x4503 #define OV5675_TEST_PATTERN_ENABLE BIT(7) @@ -587,6 +594,12 @@ static int ov5675_update_digital_gain(struct ov5675 *ov5675, u32 d_gain) { int ret; + ret = ov5675_write_reg(ov5675, OV5675_REG_GROUP_ACCESS, + OV5675_REG_VALUE_08BIT, + OV5675_GROUP_HOLD_START); + if (ret) + return ret; + ret = ov5675_write_reg(ov5675, OV5675_REG_MWB_R_GAIN, OV5675_REG_VALUE_16BIT, d_gain); if (ret) @@ -597,8 +610,21 @@ static int ov5675_update_digital_gain(struct ov5675 *ov5675, u32 d_gain) if (ret) return ret; - return ov5675_write_reg(ov5675, OV5675_REG_MWB_B_GAIN, - OV5675_REG_VALUE_16BIT, d_gain); + ret = ov5675_write_reg(ov5675, OV5675_REG_MWB_B_GAIN, + OV5675_REG_VALUE_16BIT, d_gain); + if (ret) + return ret; + + ret = ov5675_write_reg(ov5675, OV5675_REG_GROUP_ACCESS, + OV5675_REG_VALUE_08BIT, + OV5675_GROUP_HOLD_END); + if (ret) + return ret; + + ret = ov5675_write_reg(ov5675, OV5675_REG_GROUP_ACCESS, + OV5675_REG_VALUE_08BIT, + OV5675_GROUP_HOLD_LAUNCH); + return ret; } static int ov5675_test_pattern(struct ov5675 *ov5675, u32 pattern) diff --git a/drivers/media/i2c/ov5693.c b/drivers/media/i2c/ov5693.c index 2784fcf67f3b..117ff5403312 100644 --- a/drivers/media/i2c/ov5693.c +++ b/drivers/media/i2c/ov5693.c @@ -950,7 +950,6 @@ static int ov5693_set_fmt(struct v4l2_subdev *sd, unsigned int width, height; unsigned int hblank; int exposure_max; - int ret = 0; crop = __ov5693_get_pad_crop(ov5693, state, format->pad, format->which); @@ -982,13 +981,13 @@ static int ov5693_set_fmt(struct v4l2_subdev *sd, format->format = *fmt; if (format->which == V4L2_SUBDEV_FORMAT_TRY) - return ret; + return 0; mutex_lock(&ov5693->lock); - ov5693->mode.binning_x = hratio > 1 ? true : false; + ov5693->mode.binning_x = hratio > 1; ov5693->mode.inc_x_odd = hratio > 1 ? 3 : 1; - ov5693->mode.binning_y = vratio > 1 ? true : false; + ov5693->mode.binning_y = vratio > 1; ov5693->mode.inc_y_odd = vratio > 1 ? 3 : 1; ov5693->mode.vts = __ov5693_calc_vts(fmt->height); @@ -1012,7 +1011,7 @@ static int ov5693_set_fmt(struct v4l2_subdev *sd, exposure_max)); mutex_unlock(&ov5693->lock); - return ret; + return 0; } static int ov5693_get_selection(struct v4l2_subdev *sd, diff --git a/drivers/media/i2c/ov6650.c b/drivers/media/i2c/ov6650.c index f67412150b16..6458e96d9091 100644 --- a/drivers/media/i2c/ov6650.c +++ b/drivers/media/i2c/ov6650.c @@ -472,9 +472,16 @@ static int ov6650_get_selection(struct v4l2_subdev *sd, { struct i2c_client *client = v4l2_get_subdevdata(sd); struct ov6650 *priv = to_ov6650(client); + struct v4l2_rect *rect; - if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) - return -EINVAL; + if (sel->which == V4L2_SUBDEV_FORMAT_TRY) { + /* pre-select try crop rectangle */ + rect = &sd_state->pads->try_crop; + + } else { + /* pre-select active crop rectangle */ + rect = &priv->rect; + } switch (sel->target) { case V4L2_SEL_TGT_CROP_BOUNDS: @@ -483,14 +490,33 @@ static int ov6650_get_selection(struct v4l2_subdev *sd, sel->r.width = W_CIF; sel->r.height = H_CIF; return 0; + case V4L2_SEL_TGT_CROP: - sel->r = priv->rect; + /* use selected crop rectangle */ + sel->r = *rect; return 0; + default: return -EINVAL; } } +static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect) +{ + return width > rect->width >> 1 || height > rect->height >> 1; +} + +static void ov6650_bind_align_crop_rectangle(struct v4l2_rect *rect) +{ + v4l_bound_align_image(&rect->width, 2, W_CIF, 1, + &rect->height, 2, H_CIF, 1, 0); + v4l_bound_align_image(&rect->left, DEF_HSTRT << 1, + (DEF_HSTRT << 1) + W_CIF - (__s32)rect->width, 1, + &rect->top, DEF_VSTRT << 1, + (DEF_VSTRT << 1) + H_CIF - (__s32)rect->height, + 1, 0); +} + static int ov6650_set_selection(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_selection *sel) @@ -499,18 +525,30 @@ static int ov6650_set_selection(struct v4l2_subdev *sd, struct ov6650 *priv = to_ov6650(client); int ret; - if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE || - sel->target != V4L2_SEL_TGT_CROP) + if (sel->target != V4L2_SEL_TGT_CROP) return -EINVAL; - v4l_bound_align_image(&sel->r.width, 2, W_CIF, 1, - &sel->r.height, 2, H_CIF, 1, 0); - v4l_bound_align_image(&sel->r.left, DEF_HSTRT << 1, - (DEF_HSTRT << 1) + W_CIF - (__s32)sel->r.width, 1, - &sel->r.top, DEF_VSTRT << 1, - (DEF_VSTRT << 1) + H_CIF - (__s32)sel->r.height, - 1, 0); + ov6650_bind_align_crop_rectangle(&sel->r); + + if (sel->which == V4L2_SUBDEV_FORMAT_TRY) { + struct v4l2_rect *crop = &sd_state->pads->try_crop; + struct v4l2_mbus_framefmt *mf = &sd_state->pads->try_fmt; + /* detect current pad config scaling factor */ + bool half_scale = !is_unscaled_ok(mf->width, mf->height, crop); + /* store new crop rectangle */ + *crop = sel->r; + + /* adjust frame size */ + mf->width = crop->width >> half_scale; + mf->height = crop->height >> half_scale; + + return 0; + } + + /* V4L2_SUBDEV_FORMAT_ACTIVE */ + + /* apply new crop rectangle */ ret = ov6650_reg_write(client, REG_HSTRT, sel->r.left >> 1); if (!ret) { priv->rect.width += priv->rect.left - sel->r.left; @@ -562,30 +600,13 @@ static int ov6650_get_fmt(struct v4l2_subdev *sd, return 0; } -static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect) -{ - return width > rect->width >> 1 || height > rect->height >> 1; -} - #define to_clkrc(div) ((div) - 1) /* set the format we will capture in */ -static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf) +static int ov6650_s_fmt(struct v4l2_subdev *sd, u32 code, bool half_scale) { struct i2c_client *client = v4l2_get_subdevdata(sd); struct ov6650 *priv = to_ov6650(client); - bool half_scale = !is_unscaled_ok(mf->width, mf->height, &priv->rect); - struct v4l2_subdev_selection sel = { - .which = V4L2_SUBDEV_FORMAT_ACTIVE, - .target = V4L2_SEL_TGT_CROP, - .r.left = priv->rect.left + (priv->rect.width >> 1) - - (mf->width >> (1 - half_scale)), - .r.top = priv->rect.top + (priv->rect.height >> 1) - - (mf->height >> (1 - half_scale)), - .r.width = mf->width << half_scale, - .r.height = mf->height << half_scale, - }; - u32 code = mf->code; u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask; int ret; @@ -653,9 +674,7 @@ static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf) coma_mask |= COMA_QCIF; } - ret = ov6650_set_selection(sd, NULL, &sel); - if (!ret) - ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask); + ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask); if (!ret) { priv->half_scale = half_scale; @@ -674,14 +693,12 @@ static int ov6650_set_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf = &format->format; struct i2c_client *client = v4l2_get_subdevdata(sd); struct ov6650 *priv = to_ov6650(client); + struct v4l2_rect *crop; + bool half_scale; if (format->pad) return -EINVAL; - if (is_unscaled_ok(mf->width, mf->height, &priv->rect)) - v4l_bound_align_image(&mf->width, 2, W_CIF, 1, - &mf->height, 2, H_CIF, 1, 0); - switch (mf->code) { case MEDIA_BUS_FMT_Y10_1X10: mf->code = MEDIA_BUS_FMT_Y8_1X8; @@ -699,10 +716,17 @@ static int ov6650_set_fmt(struct v4l2_subdev *sd, break; } + if (format->which == V4L2_SUBDEV_FORMAT_TRY) + crop = &sd_state->pads->try_crop; + else + crop = &priv->rect; + + half_scale = !is_unscaled_ok(mf->width, mf->height, crop); + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { - /* store media bus format code and frame size in pad config */ - sd_state->pads->try_fmt.width = mf->width; - sd_state->pads->try_fmt.height = mf->height; + /* store new mbus frame format code and size in pad config */ + sd_state->pads->try_fmt.width = crop->width >> half_scale; + sd_state->pads->try_fmt.height = crop->height >> half_scale; sd_state->pads->try_fmt.code = mf->code; /* return default mbus frame format updated with pad config */ @@ -712,9 +736,11 @@ static int ov6650_set_fmt(struct v4l2_subdev *sd, mf->code = sd_state->pads->try_fmt.code; } else { - /* apply new media bus format code and frame size */ - int ret = ov6650_s_fmt(sd, mf); + int ret = 0; + /* apply new media bus frame format and scaling if changed */ + if (mf->code != priv->code || half_scale != priv->half_scale) + ret = ov6650_s_fmt(sd, mf->code, half_scale); if (ret) return ret; @@ -738,6 +764,33 @@ static int ov6650_enum_mbus_code(struct v4l2_subdev *sd, return 0; } +static int ov6650_enum_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_interval_enum *fie) +{ + int i; + + /* enumerate supported frame intervals not exceeding 1 second */ + if (fie->index > CLKRC_DIV_MASK || + GET_CLKRC_DIV(fie->index) > FRAME_RATE_MAX) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(ov6650_codes); i++) + if (fie->code == ov6650_codes[i]) + break; + if (i == ARRAY_SIZE(ov6650_codes)) + return -EINVAL; + + if (!fie->width || fie->width > W_CIF || + !fie->height || fie->height > H_CIF) + return -EINVAL; + + fie->interval.numerator = GET_CLKRC_DIV(fie->index); + fie->interval.denominator = FRAME_RATE_MAX; + + return 0; +} + static int ov6650_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *ival) { @@ -890,9 +943,8 @@ static int ov6650_video_probe(struct v4l2_subdev *sd) if (!ret) ret = ov6650_prog_dflt(client, xclk->clkrc); if (!ret) { - struct v4l2_mbus_framefmt mf = ov6650_def_fmt; - - ret = ov6650_s_fmt(sd, &mf); + /* driver default frame format, no scaling */ + ret = ov6650_s_fmt(sd, ov6650_def_fmt.code, false); } if (!ret) ret = v4l2_ctrl_handler_setup(&priv->hdl); @@ -932,54 +984,18 @@ static int ov6650_get_mbus_config(struct v4l2_subdev *sd, if (ret) return ret; - cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_DATA_ACTIVE_HIGH - | ((comj & COMJ_VSYNC_HIGH) ? V4L2_MBUS_VSYNC_ACTIVE_HIGH - : V4L2_MBUS_VSYNC_ACTIVE_LOW) - | ((comf & COMF_HREF_LOW) ? V4L2_MBUS_HSYNC_ACTIVE_LOW - : V4L2_MBUS_HSYNC_ACTIVE_HIGH) - | ((comj & COMJ_PCLK_RISING) ? V4L2_MBUS_PCLK_SAMPLE_RISING - : V4L2_MBUS_PCLK_SAMPLE_FALLING); cfg->type = V4L2_MBUS_PARALLEL; + cfg->bus.parallel.flags = V4L2_MBUS_MASTER | V4L2_MBUS_DATA_ACTIVE_HIGH + | ((comj & COMJ_VSYNC_HIGH) ? V4L2_MBUS_VSYNC_ACTIVE_HIGH + : V4L2_MBUS_VSYNC_ACTIVE_LOW) + | ((comf & COMF_HREF_LOW) ? V4L2_MBUS_HSYNC_ACTIVE_LOW + : V4L2_MBUS_HSYNC_ACTIVE_HIGH) + | ((comj & COMJ_PCLK_RISING) ? V4L2_MBUS_PCLK_SAMPLE_RISING + : V4L2_MBUS_PCLK_SAMPLE_FALLING); return 0; } -/* Alter bus settings on camera side */ -static int ov6650_set_mbus_config(struct v4l2_subdev *sd, - unsigned int pad, - struct v4l2_mbus_config *cfg) -{ - struct i2c_client *client = v4l2_get_subdevdata(sd); - int ret = 0; - - if (cfg->flags & V4L2_MBUS_PCLK_SAMPLE_RISING) - ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_PCLK_RISING, 0); - else if (cfg->flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) - ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_PCLK_RISING); - if (ret) - return ret; - - if (cfg->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) - ret = ov6650_reg_rmw(client, REG_COMF, COMF_HREF_LOW, 0); - else if (cfg->flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) - ret = ov6650_reg_rmw(client, REG_COMF, 0, COMF_HREF_LOW); - if (ret) - return ret; - - if (cfg->flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) - ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_VSYNC_HIGH, 0); - else if (cfg->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) - ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_VSYNC_HIGH); - if (ret) - return ret; - - /* - * Update the configuration to report what is actually applied to - * the hardware. - */ - return ov6650_get_mbus_config(sd, pad, cfg); -} - static const struct v4l2_subdev_video_ops ov6650_video_ops = { .s_stream = ov6650_s_stream, .g_frame_interval = ov6650_g_frame_interval, @@ -987,13 +1003,13 @@ static const struct v4l2_subdev_video_ops ov6650_video_ops = { }; static const struct v4l2_subdev_pad_ops ov6650_pad_ops = { - .enum_mbus_code = ov6650_enum_mbus_code, - .get_selection = ov6650_get_selection, - .set_selection = ov6650_set_selection, - .get_fmt = ov6650_get_fmt, - .set_fmt = ov6650_set_fmt, - .get_mbus_config = ov6650_get_mbus_config, - .set_mbus_config = ov6650_set_mbus_config, + .enum_mbus_code = ov6650_enum_mbus_code, + .enum_frame_interval = ov6650_enum_frame_interval, + .get_selection = ov6650_get_selection, + .set_selection = ov6650_set_selection, + .get_fmt = ov6650_get_fmt, + .set_fmt = ov6650_set_fmt, + .get_mbus_config = ov6650_get_mbus_config, }; static const struct v4l2_subdev_ops ov6650_subdev_ops = { diff --git a/drivers/media/i2c/ov8865.c b/drivers/media/i2c/ov8865.c index d9d016cfa9ac..b8f4f0d3e33d 100644 --- a/drivers/media/i2c/ov8865.c +++ b/drivers/media/i2c/ov8865.c @@ -457,8 +457,8 @@ #define OV8865_NATIVE_WIDTH 3296 #define OV8865_NATIVE_HEIGHT 2528 -#define OV8865_ACTIVE_START_TOP 32 -#define OV8865_ACTIVE_START_LEFT 80 +#define OV8865_ACTIVE_START_LEFT 16 +#define OV8865_ACTIVE_START_TOP 40 #define OV8865_ACTIVE_WIDTH 3264 #define OV8865_ACTIVE_HEIGHT 2448 @@ -1471,7 +1471,7 @@ static int ov8865_charge_pump_configure(struct ov8865_sensor *sensor) static int ov8865_mipi_configure(struct ov8865_sensor *sensor) { - struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 = + struct v4l2_mbus_config_mipi_csi2 *bus_mipi_csi2 = &sensor->endpoint.bus.mipi_csi2; unsigned int lanes_count = bus_mipi_csi2->num_data_lanes; int ret; @@ -2241,7 +2241,7 @@ static int ov8865_state_mipi_configure(struct ov8865_sensor *sensor, u32 mbus_code) { struct ov8865_ctrls *ctrls = &sensor->ctrls; - struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 = + struct v4l2_mbus_config_mipi_csi2 *bus_mipi_csi2 = &sensor->endpoint.bus.mipi_csi2; unsigned long mipi_clk_rate; unsigned int bits_per_sample; @@ -2838,8 +2838,8 @@ static int ov8865_get_selection(struct v4l2_subdev *subdev, switch (sel->target) { case V4L2_SEL_TGT_CROP: mutex_lock(&sensor->mutex); - __ov8865_get_pad_crop(sensor, state, sel->pad, - sel->which, &sel->r); + __ov8865_get_pad_crop(sensor, state, sel->pad, + sel->which, &sel->r); mutex_unlock(&sensor->mutex); break; case V4L2_SEL_TGT_NATIVE_SIZE: diff --git a/drivers/media/i2c/ov9640.c b/drivers/media/i2c/ov9640.c index 0bab8c2cf160..9f44ed52d164 100644 --- a/drivers/media/i2c/ov9640.c +++ b/drivers/media/i2c/ov9640.c @@ -652,10 +652,12 @@ static int ov9640_get_mbus_config(struct v4l2_subdev *sd, unsigned int pad, struct v4l2_mbus_config *cfg) { - cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER | - V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH | - V4L2_MBUS_DATA_ACTIVE_HIGH; cfg->type = V4L2_MBUS_PARALLEL; + cfg->bus.parallel.flags = V4L2_MBUS_PCLK_SAMPLE_RISING | + V4L2_MBUS_MASTER | + V4L2_MBUS_VSYNC_ACTIVE_HIGH | + V4L2_MBUS_HSYNC_ACTIVE_HIGH | + V4L2_MBUS_DATA_ACTIVE_HIGH; return 0; } diff --git a/drivers/media/i2c/saa7115.c b/drivers/media/i2c/saa7115.c index a958bbc2c33d..15ff80e6301e 100644 --- a/drivers/media/i2c/saa7115.c +++ b/drivers/media/i2c/saa7115.c @@ -1129,7 +1129,7 @@ static void saa711x_set_lcr(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_forma static int saa711x_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *sliced) { - static u16 lcr2vbi[] = { + static const u16 lcr2vbi[] = { 0, V4L2_SLICED_TELETEXT_B, 0, /* 1 */ 0, V4L2_SLICED_CAPTION_525, /* 4 */ V4L2_SLICED_WSS_625, 0, /* 5 */ diff --git a/drivers/media/i2c/tc358743.c b/drivers/media/i2c/tc358743.c index 3205cd8298dd..e18b8947ad7e 100644 --- a/drivers/media/i2c/tc358743.c +++ b/drivers/media/i2c/tc358743.c @@ -69,7 +69,7 @@ static const struct v4l2_dv_timings_cap tc358743_timings_cap = { struct tc358743_state { struct tc358743_platform_data pdata; - struct v4l2_fwnode_bus_mipi_csi2 bus; + struct v4l2_mbus_config_mipi_csi2 bus; struct v4l2_subdev sd; struct media_pad pad; struct v4l2_ctrl_handler hdl; @@ -717,7 +717,7 @@ static void tc358743_set_csi(struct v4l2_subdev *sd) ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0)); i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags & - V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) ? MASK_CONTCLKMODE : 0); + V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK) ? 0 : MASK_CONTCLKMODE); i2c_wr32(sd, STARTCNTRL, MASK_START); i2c_wr32(sd, CSI_START, MASK_STRT); @@ -1613,24 +1613,8 @@ static int tc358743_get_mbus_config(struct v4l2_subdev *sd, cfg->type = V4L2_MBUS_CSI2_DPHY; /* Support for non-continuous CSI-2 clock is missing in the driver */ - cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; - - switch (state->csi_lanes_in_use) { - case 1: - cfg->flags |= V4L2_MBUS_CSI2_1_LANE; - break; - case 2: - cfg->flags |= V4L2_MBUS_CSI2_2_LANE; - break; - case 3: - cfg->flags |= V4L2_MBUS_CSI2_3_LANE; - break; - case 4: - cfg->flags |= V4L2_MBUS_CSI2_4_LANE; - break; - default: - return -EINVAL; - } + cfg->bus.mipi_csi2.flags = 0; + cfg->bus.mipi_csi2.num_data_lanes = state->csi_lanes_in_use; return 0; } @@ -2055,7 +2039,7 @@ static int tc358743_probe(struct i2c_client *client) /* platform data */ if (pdata) { state->pdata = *pdata; - state->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; + state->bus.flags = 0; } else { err = tc358743_probe_of(state); if (err == -ENODEV) diff --git a/drivers/media/i2c/tvp5150.c b/drivers/media/i2c/tvp5150.c index 4b16ffcaef98..65472438444b 100644 --- a/drivers/media/i2c/tvp5150.c +++ b/drivers/media/i2c/tvp5150.c @@ -1198,8 +1198,10 @@ static int tvp5150_get_mbus_config(struct v4l2_subdev *sd, struct tvp5150 *decoder = to_tvp5150(sd); cfg->type = decoder->mbus_type; - cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING - | V4L2_MBUS_FIELD_EVEN_LOW | V4L2_MBUS_DATA_ACTIVE_HIGH; + cfg->bus.parallel.flags = V4L2_MBUS_MASTER + | V4L2_MBUS_PCLK_SAMPLE_RISING + | V4L2_MBUS_FIELD_EVEN_LOW + | V4L2_MBUS_DATA_ACTIVE_HIGH; return 0; } |