diff options
Diffstat (limited to 'drivers/i2c/busses/i2c-octeon.c')
| -rw-r--r-- | drivers/i2c/busses/i2c-octeon.c | 307 |
1 files changed, 137 insertions, 170 deletions
diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c index 32914ab42a19..46fb6c42934f 100644 --- a/drivers/i2c/busses/i2c-octeon.c +++ b/drivers/i2c/busses/i2c-octeon.c @@ -2,7 +2,7 @@ * (C) Copyright 2009-2010 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com * - * Portions Copyright (C) 2010, 2011 Cavium Networks, Inc. + * Portions Copyright (C) 2010 - 2016 Cavium, Inc. * * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors. * @@ -26,39 +26,48 @@ #define DRV_NAME "i2c-octeon" -/* The previous out-of-tree version was implicitly version 1.0. */ -#define DRV_VERSION "2.0" - -/* register offsets */ -#define SW_TWSI 0x00 -#define TWSI_INT 0x10 +/* Register offsets */ +#define SW_TWSI 0x00 +#define TWSI_INT 0x10 /* Controller command patterns */ -#define SW_TWSI_V 0x8000000000000000ull -#define SW_TWSI_EOP_TWSI_DATA 0x0C00000100000000ull -#define SW_TWSI_EOP_TWSI_CTL 0x0C00000200000000ull -#define SW_TWSI_EOP_TWSI_CLKCTL 0x0C00000300000000ull -#define SW_TWSI_EOP_TWSI_STAT 0x0C00000300000000ull -#define SW_TWSI_EOP_TWSI_RST 0x0C00000700000000ull -#define SW_TWSI_OP_TWSI_CLK 0x0800000000000000ull -#define SW_TWSI_R 0x0100000000000000ull +#define SW_TWSI_V BIT_ULL(63) /* Valid bit */ +#define SW_TWSI_R BIT_ULL(56) /* Result or read bit */ + +/* Controller opcode word (bits 60:57) */ +#define SW_TWSI_OP_SHIFT 57 +#define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT) +#define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */ + +/* Controller extended opcode word (bits 34:32) */ +#define SW_TWSI_EOP_SHIFT 32 +#define SW_TWSI_EOP_TWSI_DATA (SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT) +#define SW_TWSI_EOP_TWSI_CTL (SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT) +#define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT) +#define SW_TWSI_EOP_TWSI_STAT (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT) +#define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT) /* Controller command and status bits */ -#define TWSI_CTL_CE 0x80 -#define TWSI_CTL_ENAB 0x40 -#define TWSI_CTL_STA 0x20 -#define TWSI_CTL_STP 0x10 -#define TWSI_CTL_IFLG 0x08 -#define TWSI_CTL_AAK 0x04 +#define TWSI_CTL_CE 0x80 +#define TWSI_CTL_ENAB 0x40 /* Bus enable */ +#define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */ +#define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */ +#define TWSI_CTL_IFLG 0x08 /* HW event, SW writes 0 to ACK */ +#define TWSI_CTL_AAK 0x04 /* Assert ACK */ /* Some status values */ -#define STAT_START 0x08 -#define STAT_RSTART 0x10 -#define STAT_TXADDR_ACK 0x18 -#define STAT_TXDATA_ACK 0x28 -#define STAT_RXADDR_ACK 0x40 -#define STAT_RXDATA_ACK 0x50 -#define STAT_IDLE 0xF8 +#define STAT_START 0x08 +#define STAT_RSTART 0x10 +#define STAT_TXADDR_ACK 0x18 +#define STAT_TXDATA_ACK 0x28 +#define STAT_RXADDR_ACK 0x40 +#define STAT_RXDATA_ACK 0x50 +#define STAT_IDLE 0xF8 + +/* TWSI_INT values */ +#define TWSI_INT_CORE_EN BIT_ULL(6) +#define TWSI_INT_SDA_OVR BIT_ULL(8) +#define TWSI_INT_SCL_OVR BIT_ULL(9) struct octeon_i2c { wait_queue_head_t queue; @@ -66,23 +75,19 @@ struct octeon_i2c { int irq; u32 twsi_freq; int sys_freq; - resource_size_t twsi_phys; void __iomem *twsi_base; - resource_size_t regsize; struct device *dev; }; /** - * octeon_i2c_write_sw - write an I2C core register. - * @i2c: The struct octeon_i2c. - * @eop_reg: Register selector. - * @data: Value to be written. + * octeon_i2c_write_sw - write an I2C core register + * @i2c: The struct octeon_i2c + * @eop_reg: Register selector + * @data: Value to be written * * The I2C core registers are accessed indirectly via the SW_TWSI CSR. */ -static void octeon_i2c_write_sw(struct octeon_i2c *i2c, - u64 eop_reg, - u8 data) +static void octeon_i2c_write_sw(struct octeon_i2c *i2c, u64 eop_reg, u8 data) { u64 tmp; @@ -93,9 +98,9 @@ static void octeon_i2c_write_sw(struct octeon_i2c *i2c, } /** - * octeon_i2c_read_sw - write an I2C core register. - * @i2c: The struct octeon_i2c. - * @eop_reg: Register selector. + * octeon_i2c_read_sw - read lower bits of an I2C core register + * @i2c: The struct octeon_i2c + * @eop_reg: Register selector * * Returns the data. * @@ -115,8 +120,8 @@ static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg) /** * octeon_i2c_write_int - write the TWSI_INT register - * @i2c: The struct octeon_i2c. - * @data: Value to be written. + * @i2c: The struct octeon_i2c + * @data: Value to be written */ static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data) { @@ -125,57 +130,52 @@ static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data) } /** - * octeon_i2c_int_enable - enable the TS interrupt. - * @i2c: The struct octeon_i2c. + * octeon_i2c_int_enable - enable the CORE interrupt + * @i2c: The struct octeon_i2c * * The interrupt will be asserted when there is non-STAT_IDLE state in * the SW_TWSI_EOP_TWSI_STAT register. */ static void octeon_i2c_int_enable(struct octeon_i2c *i2c) { - octeon_i2c_write_int(i2c, 0x40); + octeon_i2c_write_int(i2c, TWSI_INT_CORE_EN); } -/** - * octeon_i2c_int_disable - disable the TS interrupt. - * @i2c: The struct octeon_i2c. - */ +/* disable the CORE interrupt */ static void octeon_i2c_int_disable(struct octeon_i2c *i2c) { + /* clear TS/ST/IFLG events */ octeon_i2c_write_int(i2c, 0); } /** - * octeon_i2c_unblock - unblock the bus. - * @i2c: The struct octeon_i2c. + * octeon_i2c_unblock - unblock the bus + * @i2c: The struct octeon_i2c * - * If there was a reset while a device was driving 0 to bus, - * bus is blocked. We toggle it free manually by some clock - * cycles and send a stop. + * If there was a reset while a device was driving 0 to bus, bus is blocked. + * We toggle it free manually by some clock cycles and send a stop. */ static void octeon_i2c_unblock(struct octeon_i2c *i2c) { int i; dev_dbg(i2c->dev, "%s\n", __func__); + for (i = 0; i < 9; i++) { - octeon_i2c_write_int(i2c, 0x0); + octeon_i2c_write_int(i2c, 0); udelay(5); - octeon_i2c_write_int(i2c, 0x200); + octeon_i2c_write_int(i2c, TWSI_INT_SCL_OVR); udelay(5); } - octeon_i2c_write_int(i2c, 0x300); + /* hand-crank a STOP */ + octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR | TWSI_INT_SCL_OVR); udelay(5); - octeon_i2c_write_int(i2c, 0x100); + octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR); udelay(5); - octeon_i2c_write_int(i2c, 0x0); + octeon_i2c_write_int(i2c, 0); } -/** - * octeon_i2c_isr - the interrupt service routine. - * @int: The irq, unused. - * @dev_id: Our struct octeon_i2c. - */ +/* interrupt service routine */ static irqreturn_t octeon_i2c_isr(int irq, void *dev_id) { struct octeon_i2c *i2c = dev_id; @@ -193,24 +193,20 @@ static int octeon_i2c_test_iflg(struct octeon_i2c *i2c) } /** - * octeon_i2c_wait - wait for the IFLG to be set. - * @i2c: The struct octeon_i2c. + * octeon_i2c_wait - wait for the IFLG to be set + * @i2c: The struct octeon_i2c * * Returns 0 on success, otherwise a negative errno. */ static int octeon_i2c_wait(struct octeon_i2c *i2c) { - long result; + long time_left; octeon_i2c_int_enable(i2c); - - result = wait_event_timeout(i2c->queue, - octeon_i2c_test_iflg(i2c), - i2c->adap.timeout); - + time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c), + i2c->adap.timeout); octeon_i2c_int_disable(i2c); - - if (result == 0) { + if (!time_left) { dev_dbg(i2c->dev, "%s: timeout\n", __func__); return -ETIMEDOUT; } @@ -219,18 +215,18 @@ static int octeon_i2c_wait(struct octeon_i2c *i2c) } /** - * octeon_i2c_start - send START to the bus. - * @i2c: The struct octeon_i2c. + * octeon_i2c_start - send START to the bus + * @i2c: The struct octeon_i2c * * Returns 0 on success, otherwise a negative errno. */ static int octeon_i2c_start(struct octeon_i2c *i2c) { - u8 data; int result; + u8 data; octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, - TWSI_CTL_ENAB | TWSI_CTL_STA); + TWSI_CTL_ENAB | TWSI_CTL_STA); result = octeon_i2c_wait(i2c); if (result) { @@ -243,7 +239,6 @@ static int octeon_i2c_start(struct octeon_i2c *i2c) octeon_i2c_unblock(i2c); octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB | TWSI_CTL_STA); - result = octeon_i2c_wait(i2c); } if (result) @@ -259,34 +254,19 @@ static int octeon_i2c_start(struct octeon_i2c *i2c) return 0; } -/** - * octeon_i2c_stop - send STOP to the bus. - * @i2c: The struct octeon_i2c. - * - * Returns 0 on success, otherwise a negative errno. - */ -static int octeon_i2c_stop(struct octeon_i2c *i2c) +/* send STOP to the bus */ +static void octeon_i2c_stop(struct octeon_i2c *i2c) { - u8 data; - octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB | TWSI_CTL_STP); - - data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT); - - if (data != STAT_IDLE) { - dev_err(i2c->dev, "%s: bad status(0x%x)\n", __func__, data); - return -EIO; - } - return 0; } /** - * octeon_i2c_write - send data to the bus. - * @i2c: The struct octeon_i2c. - * @target: Target address. - * @data: Pointer to the data to be sent. - * @length: Length of the data. + * octeon_i2c_write - send data to the bus via low-level controller + * @i2c: The struct octeon_i2c + * @target: Target address + * @data: Pointer to the data to be sent + * @length: Length of the data * * The address is sent over the bus, then the data. * @@ -311,6 +291,7 @@ static int octeon_i2c_write(struct octeon_i2c *i2c, int target, for (i = 0; i < length; i++) { tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT); + if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) { dev_err(i2c->dev, "%s: bad status before write (0x%x)\n", @@ -330,20 +311,21 @@ static int octeon_i2c_write(struct octeon_i2c *i2c, int target, } /** - * octeon_i2c_read - receive data from the bus. - * @i2c: The struct octeon_i2c. - * @target: Target address. - * @data: Pointer to the location to store the datae . - * @length: Length of the data. + * octeon_i2c_read - receive data from the bus via low-level controller + * @i2c: The struct octeon_i2c + * @target: Target address + * @data: Pointer to the location to store the data + * @rlength: Length of the data + * @recv_len: flag for length byte * * The address is sent over the bus, then the data is read. * * Returns 0 on success, otherwise a negative errno. */ static int octeon_i2c_read(struct octeon_i2c *i2c, int target, - u8 *data, int length) + u8 *data, u16 *rlength, bool recv_len) { - int i, result; + int i, result, length = *rlength; u8 tmp; if (length < 1) @@ -353,7 +335,7 @@ static int octeon_i2c_read(struct octeon_i2c *i2c, int target, if (result) return result; - octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target<<1) | 1); + octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target << 1) | 1); octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB); result = octeon_i2c_wait(i2c); @@ -362,6 +344,7 @@ static int octeon_i2c_read(struct octeon_i2c *i2c, int target, for (i = 0; i < length; i++) { tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT); + if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) { dev_err(i2c->dev, "%s: bad status before read (0x%x)\n", @@ -369,52 +352,59 @@ static int octeon_i2c_read(struct octeon_i2c *i2c, int target, return -EIO; } - if (i+1 < length) + if (i + 1 < length) octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, - TWSI_CTL_ENAB | TWSI_CTL_AAK); + TWSI_CTL_ENAB | TWSI_CTL_AAK); else octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, - TWSI_CTL_ENAB); + TWSI_CTL_ENAB); result = octeon_i2c_wait(i2c); if (result) return result; data[i] = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_DATA); + if (recv_len && i == 0) { + if (data[i] > I2C_SMBUS_BLOCK_MAX + 1) { + dev_err(i2c->dev, + "%s: read len > I2C_SMBUS_BLOCK_MAX %d\n", + __func__, data[i]); + return -EPROTO; + } + length += data[i]; + } } + *rlength = length; return 0; } /** - * octeon_i2c_xfer - The driver's master_xfer function. - * @adap: Pointer to the i2c_adapter structure. - * @msgs: Pointer to the messages to be processed. - * @num: Length of the MSGS array. + * octeon_i2c_xfer - The driver's master_xfer function + * @adap: Pointer to the i2c_adapter structure + * @msgs: Pointer to the messages to be processed + * @num: Length of the MSGS array * - * Returns the number of messages processed, or a negative errno on - * failure. + * Returns the number of messages processed, or a negative errno on failure. */ -static int octeon_i2c_xfer(struct i2c_adapter *adap, - struct i2c_msg *msgs, +static int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) { - struct i2c_msg *pmsg; - int i; - int ret = 0; struct octeon_i2c *i2c = i2c_get_adapdata(adap); + int i, ret = 0; for (i = 0; ret == 0 && i < num; i++) { - pmsg = &msgs[i]; + struct i2c_msg *pmsg = &msgs[i]; + dev_dbg(i2c->dev, "Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n", pmsg->flags & I2C_M_RD ? "read" : "write", pmsg->len, pmsg->addr, i + 1, num); if (pmsg->flags & I2C_M_RD) ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf, - pmsg->len); + &pmsg->len, pmsg->flags & I2C_M_RECV_LEN); else ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf, - pmsg->len); + pmsg->len); } octeon_i2c_stop(i2c); @@ -423,7 +413,8 @@ static int octeon_i2c_xfer(struct i2c_adapter *adap, static u32 octeon_i2c_functionality(struct i2c_adapter *adap) { - return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | + I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_SMBUS_BLOCK_PROC_CALL; } static const struct i2c_algorithm octeon_i2c_algo = { @@ -438,10 +429,8 @@ static struct i2c_adapter octeon_i2c_ops = { .timeout = HZ / 50, }; -/** - * octeon_i2c_setclock - Calculate and set clock divisors. - */ -static int octeon_i2c_setclock(struct octeon_i2c *i2c) +/* calculate and set clock divisors */ +static void octeon_i2c_set_clock(struct octeon_i2c *i2c) { int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff; int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000; @@ -449,8 +438,7 @@ static int octeon_i2c_setclock(struct octeon_i2c *i2c) for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) { /* * An mdiv value of less than 2 seems to not work well - * with ds1337 RTCs, so we constrain it to larger - * values. + * with ds1337 RTCs, so we constrain it to larger values. */ for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) { /* @@ -460,6 +448,7 @@ static int octeon_i2c_setclock(struct octeon_i2c *i2c) tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10; tclk *= (1 << ndiv_idx); thp_base = (i2c->sys_freq / (tclk * 2)) - 1; + for (inc = 0; inc <= 1; inc++) { thp_idx = thp_base + inc; if (thp_idx < 5 || thp_idx > 0xff) @@ -480,11 +469,9 @@ static int octeon_i2c_setclock(struct octeon_i2c *i2c) } octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp); octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv); - - return 0; } -static int octeon_i2c_initlowlevel(struct octeon_i2c *i2c) +static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c) { u8 status; int tries; @@ -507,9 +494,10 @@ static int octeon_i2c_initlowlevel(struct octeon_i2c *i2c) static int octeon_i2c_probe(struct platform_device *pdev) { - int irq, result = 0; - struct octeon_i2c *i2c; + struct device_node *node = pdev->dev.of_node; struct resource *res_mem; + struct octeon_i2c *i2c; + int irq, result = 0; /* All adaptors have an irq. */ irq = platform_get_irq(pdev, 0); @@ -518,31 +506,25 @@ static int octeon_i2c_probe(struct platform_device *pdev) i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); if (!i2c) { - dev_err(&pdev->dev, "kzalloc failed\n"); result = -ENOMEM; goto out; } i2c->dev = &pdev->dev; res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - - if (res_mem == NULL) { - dev_err(i2c->dev, "found no memory resource\n"); - result = -ENXIO; + i2c->twsi_base = devm_ioremap_resource(&pdev->dev, res_mem); + if (IS_ERR(i2c->twsi_base)) { + result = PTR_ERR(i2c->twsi_base); goto out; } - i2c->twsi_phys = res_mem->start; - i2c->regsize = resource_size(res_mem); /* * "clock-rate" is a legacy binding, the official binding is * "clock-frequency". Try the official one first and then * fall back if it doesn't exist. */ - if (of_property_read_u32(pdev->dev.of_node, - "clock-frequency", &i2c->twsi_freq) && - of_property_read_u32(pdev->dev.of_node, - "clock-rate", &i2c->twsi_freq)) { + if (of_property_read_u32(node, "clock-frequency", &i2c->twsi_freq) && + of_property_read_u32(node, "clock-rate", &i2c->twsi_freq)) { dev_err(i2c->dev, "no I2C 'clock-rate' or 'clock-frequency' property\n"); result = -ENXIO; @@ -551,13 +533,6 @@ static int octeon_i2c_probe(struct platform_device *pdev) i2c->sys_freq = octeon_get_io_clock_rate(); - if (!devm_request_mem_region(&pdev->dev, i2c->twsi_phys, i2c->regsize, - res_mem->name)) { - dev_err(i2c->dev, "request_mem_region failed\n"); - goto out; - } - i2c->twsi_base = devm_ioremap(&pdev->dev, i2c->twsi_phys, i2c->regsize); - init_waitqueue_head(&i2c->queue); i2c->irq = irq; @@ -569,21 +544,17 @@ static int octeon_i2c_probe(struct platform_device *pdev) goto out; } - result = octeon_i2c_initlowlevel(i2c); + result = octeon_i2c_init_lowlevel(i2c); if (result) { dev_err(i2c->dev, "init low level failed\n"); goto out; } - result = octeon_i2c_setclock(i2c); - if (result) { - dev_err(i2c->dev, "clock init failed\n"); - goto out; - } + octeon_i2c_set_clock(i2c); i2c->adap = octeon_i2c_ops; i2c->adap.dev.parent = &pdev->dev; - i2c->adap.dev.of_node = pdev->dev.of_node; + i2c->adap.dev.of_node = node; i2c_set_adapdata(&i2c->adap, i2c); platform_set_drvdata(pdev, i2c); @@ -592,8 +563,7 @@ static int octeon_i2c_probe(struct platform_device *pdev) dev_err(i2c->dev, "failed to add adapter\n"); goto out; } - dev_info(i2c->dev, "version %s\n", DRV_VERSION); - + dev_info(i2c->dev, "probed\n"); return 0; out: @@ -608,10 +578,8 @@ static int octeon_i2c_remove(struct platform_device *pdev) return 0; }; -static struct of_device_id octeon_i2c_match[] = { - { - .compatible = "cavium,octeon-3860-twsi", - }, +static const struct of_device_id octeon_i2c_match[] = { + { .compatible = "cavium,octeon-3860-twsi", }, {}, }; MODULE_DEVICE_TABLE(of, octeon_i2c_match); @@ -630,4 +598,3 @@ module_platform_driver(octeon_i2c_driver); MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>"); MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors"); MODULE_LICENSE("GPL"); -MODULE_VERSION(DRV_VERSION); |