diff options
Diffstat (limited to 'drivers/gpu/drm/sun4i')
| -rw-r--r-- | drivers/gpu/drm/sun4i/Kconfig | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/sun4i/Makefile | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun4i_backend.c | 32 | ||||
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun4i_crtc.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun4i_drv.c | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun4i_frontend.c | 354 | ||||
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun4i_frontend.h | 52 | ||||
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun4i_layer.c | 63 | ||||
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun4i_lvds.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun4i_rgb.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun4i_tcon.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun4i_tv.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun6i_drc.c | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c | 292 | ||||
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 34 | ||||
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | 17 | ||||
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun8i_mixer.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 2 |
20 files changed, 483 insertions, 399 deletions
diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig index c2c042287c19..1dbbc3a1b763 100644 --- a/drivers/gpu/drm/sun4i/Kconfig +++ b/drivers/gpu/drm/sun4i/Kconfig @@ -45,10 +45,11 @@ config DRM_SUN6I_DSI default MACH_SUN8I select CRC_CCITT select DRM_MIPI_DSI + select PHY_SUN6I_MIPI_DPHY help Choose this option if you want have an Allwinner SoC with MIPI-DSI support. If M is selected the module will be called - sun6i-dsi + sun6i_mipi_dsi. config DRM_SUN8I_DW_HDMI tristate "Support for Allwinner version of DesignWare HDMI" diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile index 0eb38ac8e86e..0d04f2447b01 100644 --- a/drivers/gpu/drm/sun4i/Makefile +++ b/drivers/gpu/drm/sun4i/Makefile @@ -24,9 +24,6 @@ sun4i-tcon-y += sun4i_lvds.o sun4i-tcon-y += sun4i_tcon.o sun4i-tcon-y += sun4i_rgb.o -sun6i-dsi-y += sun6i_mipi_dphy.o -sun6i-dsi-y += sun6i_mipi_dsi.o - obj-$(CONFIG_DRM_SUN4I) += sun4i-drm.o obj-$(CONFIG_DRM_SUN4I) += sun4i-tcon.o obj-$(CONFIG_DRM_SUN4I) += sun4i_tv.o @@ -37,7 +34,7 @@ ifdef CONFIG_DRM_SUN4I_BACKEND obj-$(CONFIG_DRM_SUN4I) += sun4i-frontend.o endif obj-$(CONFIG_DRM_SUN4I_HDMI) += sun4i-drm-hdmi.o -obj-$(CONFIG_DRM_SUN6I_DSI) += sun6i-dsi.o +obj-$(CONFIG_DRM_SUN6I_DSI) += sun6i_mipi_dsi.o obj-$(CONFIG_DRM_SUN8I_DW_HDMI) += sun8i-drm-hdmi.o obj-$(CONFIG_DRM_SUN8I_MIXER) += sun8i-mixer.o obj-$(CONFIG_DRM_SUN8I_TCON_TOP) += sun8i_tcon_top.o diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c index a021bab11a4f..4c0d51f73237 100644 --- a/drivers/gpu/drm/sun4i/sun4i_backend.c +++ b/drivers/gpu/drm/sun4i/sun4i_backend.c @@ -14,10 +14,10 @@ #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> -#include <drm/drm_crtc_helper.h> #include <drm/drm_fb_cma_helper.h> #include <drm/drm_gem_cma_helper.h> #include <drm/drm_plane_helper.h> +#include <drm/drm_probe_helper.h> #include <linux/component.h> #include <linux/list.h> @@ -45,28 +45,6 @@ static const u32 sunxi_rgb2yuv_coef[12] = { 0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808 }; -/* - * These coefficients are taken from the A33 BSP from Allwinner. - * - * The first three values of each row are coded as 13-bit signed fixed-point - * numbers, with 10 bits for the fractional part. The fourth value is a - * constant coded as a 14-bit signed fixed-point number with 4 bits for the - * fractional part. - * - * The values in table order give the following colorspace translation: - * G = 1.164 * Y - 0.391 * U - 0.813 * V + 135 - * R = 1.164 * Y + 1.596 * V - 222 - * B = 1.164 * Y + 2.018 * U + 276 - * - * This seems to be a conversion from Y[16:235] UV[16:240] to RGB[0:255], - * following the BT601 spec. - */ -static const u32 sunxi_bt601_yuv2rgb_coef[12] = { - 0x000004a7, 0x00001e6f, 0x00001cbf, 0x00000877, - 0x000004a7, 0x00000000, 0x00000662, 0x00003211, - 0x000004a7, 0x00000812, 0x00000000, 0x00002eb1, -}; - static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine) { int i; @@ -163,7 +141,6 @@ static const uint32_t sun4i_backend_formats[] = { DRM_FORMAT_ARGB1555, DRM_FORMAT_ARGB4444, DRM_FORMAT_ARGB8888, - DRM_FORMAT_BGRX8888, DRM_FORMAT_RGB565, DRM_FORMAT_RGB888, DRM_FORMAT_RGBA4444, @@ -245,7 +222,8 @@ static int sun4i_backend_update_yuv_format(struct sun4i_backend *backend, SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN); /* TODO: Add support for the multi-planar YUV formats */ - if (format->num_planes == 1) + if (drm_format_info_is_yuv_packed(format) && + drm_format_info_is_yuv_sampling_422(format)) val |= SUN4I_BACKEND_IYUVCTL_FBFMT_PACKED_YUV422; else DRM_DEBUG_DRIVER("Unsupported YUV format (0x%x)\n", fmt); @@ -1035,6 +1013,10 @@ static const struct of_device_id sun4i_backend_of_table[] = { .data = &sun7i_backend_quirks, }, { + .compatible = "allwinner,sun8i-a23-display-backend", + .data = &sun8i_a33_backend_quirks, + }, + { .compatible = "allwinner,sun8i-a33-display-backend", .data = &sun8i_a33_backend_quirks, }, diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c b/drivers/gpu/drm/sun4i/sun4i_crtc.c index 3eedf335a935..cdb881e34470 100644 --- a/drivers/gpu/drm/sun4i/sun4i_crtc.c +++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c @@ -13,8 +13,8 @@ #include <drm/drmP.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> -#include <drm/drm_crtc_helper.h> #include <drm/drm_modes.h> +#include <drm/drm_probe_helper.h> #include <linux/clk-provider.h> #include <linux/ioport.h> diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c index 9e4c375ccc96..3ebd9f5e2719 100644 --- a/drivers/gpu/drm/sun4i/sun4i_drv.c +++ b/drivers/gpu/drm/sun4i/sun4i_drv.c @@ -16,11 +16,11 @@ #include <linux/of_reserved_mem.h> #include <drm/drmP.h> -#include <drm/drm_crtc_helper.h> #include <drm/drm_fb_cma_helper.h> -#include <drm/drm_gem_cma_helper.h> #include <drm/drm_fb_helper.h> +#include <drm/drm_gem_cma_helper.h> #include <drm/drm_of.h> +#include <drm/drm_probe_helper.h> #include "sun4i_drv.h" #include "sun4i_frontend.h" @@ -97,6 +97,7 @@ static int sun4i_drv_bind(struct device *dev) } drm_mode_config_init(drm); + drm->mode_config.allow_fb_modifiers = true; ret = component_bind_all(drm->dev, drm); if (ret) { @@ -164,6 +165,7 @@ static bool sun4i_drv_node_is_frontend(struct device_node *node) of_device_is_compatible(node, "allwinner,sun5i-a13-display-frontend") || of_device_is_compatible(node, "allwinner,sun6i-a31-display-frontend") || of_device_is_compatible(node, "allwinner,sun7i-a20-display-frontend") || + of_device_is_compatible(node, "allwinner,sun8i-a23-display-frontend") || of_device_is_compatible(node, "allwinner,sun8i-a33-display-frontend") || of_device_is_compatible(node, "allwinner,sun9i-a80-display-frontend"); } @@ -403,6 +405,7 @@ static const struct of_device_id sun4i_drv_of_table[] = { { .compatible = "allwinner,sun6i-a31-display-engine" }, { .compatible = "allwinner,sun6i-a31s-display-engine" }, { .compatible = "allwinner,sun7i-a20-display-engine" }, + { .compatible = "allwinner,sun8i-a23-display-engine" }, { .compatible = "allwinner,sun8i-a33-display-engine" }, { .compatible = "allwinner,sun8i-a83t-display-engine" }, { .compatible = "allwinner,sun8i-h3-display-engine" }, diff --git a/drivers/gpu/drm/sun4i/sun4i_frontend.c b/drivers/gpu/drm/sun4i/sun4i_frontend.c index 1a7ebc45747e..346c8071bd38 100644 --- a/drivers/gpu/drm/sun4i/sun4i_frontend.c +++ b/drivers/gpu/drm/sun4i/sun4i_frontend.c @@ -10,6 +10,7 @@ #include <linux/clk.h> #include <linux/component.h> #include <linux/module.h> +#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> @@ -48,10 +49,38 @@ static const u32 sun4i_frontend_horz_coef[64] = { 0x03ff0000, 0x0000fd41, 0x01ff0000, 0x0000fe42, }; +/* + * These coefficients are taken from the A33 BSP from Allwinner. + * + * The first three values of each row are coded as 13-bit signed fixed-point + * numbers, with 10 bits for the fractional part. The fourth value is a + * constant coded as a 14-bit signed fixed-point number with 4 bits for the + * fractional part. + * + * The values in table order give the following colorspace translation: + * G = 1.164 * Y - 0.391 * U - 0.813 * V + 135 + * R = 1.164 * Y + 1.596 * V - 222 + * B = 1.164 * Y + 2.018 * U + 276 + * + * This seems to be a conversion from Y[16:235] UV[16:240] to RGB[0:255], + * following the BT601 spec. + */ +const u32 sunxi_bt601_yuv2rgb_coef[12] = { + 0x000004a7, 0x00001e6f, 0x00001cbf, 0x00000877, + 0x000004a7, 0x00000000, 0x00000662, 0x00003211, + 0x000004a7, 0x00000812, 0x00000000, 0x00002eb1, +}; +EXPORT_SYMBOL(sunxi_bt601_yuv2rgb_coef); + static void sun4i_frontend_scaler_init(struct sun4i_frontend *frontend) { int i; + if (frontend->data->has_coef_access_ctrl) + regmap_write_bits(frontend->regs, SUN4I_FRONTEND_FRM_CTRL_REG, + SUN4I_FRONTEND_FRM_CTRL_COEF_ACCESS_CTRL, + SUN4I_FRONTEND_FRM_CTRL_COEF_ACCESS_CTRL); + for (i = 0; i < 32; i++) { regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZCOEF0_REG(i), sun4i_frontend_horz_coef[2 * i]); @@ -67,9 +96,11 @@ static void sun4i_frontend_scaler_init(struct sun4i_frontend *frontend) sun4i_frontend_vert_coef[i]); } - regmap_update_bits(frontend->regs, SUN4I_FRONTEND_FRM_CTRL_REG, - SUN4I_FRONTEND_FRM_CTRL_COEF_ACCESS_CTRL, - SUN4I_FRONTEND_FRM_CTRL_COEF_ACCESS_CTRL); + if (frontend->data->has_coef_rdy) + regmap_write_bits(frontend->regs, + SUN4I_FRONTEND_FRM_CTRL_REG, + SUN4I_FRONTEND_FRM_CTRL_COEF_RDY, + SUN4I_FRONTEND_FRM_CTRL_COEF_RDY); } int sun4i_frontend_init(struct sun4i_frontend *frontend) @@ -84,59 +115,228 @@ void sun4i_frontend_exit(struct sun4i_frontend *frontend) } EXPORT_SYMBOL(sun4i_frontend_exit); +static bool sun4i_frontend_format_chroma_requires_swap(uint32_t fmt) +{ + switch (fmt) { + case DRM_FORMAT_YVU411: + case DRM_FORMAT_YVU420: + case DRM_FORMAT_YVU422: + case DRM_FORMAT_YVU444: + return true; + + default: + return false; + } +} + +static bool sun4i_frontend_format_supports_tiling(uint32_t fmt) +{ + switch (fmt) { + case DRM_FORMAT_NV12: + case DRM_FORMAT_NV16: + case DRM_FORMAT_NV21: + case DRM_FORMAT_NV61: + case DRM_FORMAT_YUV411: + case DRM_FORMAT_YUV420: + case DRM_FORMAT_YUV422: + case DRM_FORMAT_YVU420: + case DRM_FORMAT_YVU422: + case DRM_FORMAT_YVU411: + return true; + + default: + return false; + } +} + void sun4i_frontend_update_buffer(struct sun4i_frontend *frontend, struct drm_plane *plane) { struct drm_plane_state *state = plane->state; struct drm_framebuffer *fb = state->fb; + unsigned int strides[3] = {}; + dma_addr_t paddr; + bool swap; + + if (fb->modifier == DRM_FORMAT_MOD_ALLWINNER_TILED) { + unsigned int width = state->src_w >> 16; + unsigned int offset; + + strides[0] = SUN4I_FRONTEND_LINESTRD_TILED(fb->pitches[0]); + + /* + * The X1 offset is the offset to the bottom-right point in the + * end tile, which is the final pixel (at offset width - 1) + * within the end tile (with a 32-byte mask). + */ + offset = (width - 1) & (32 - 1); + + regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF0_REG, + SUN4I_FRONTEND_TB_OFF_X1(offset)); + + if (fb->format->num_planes > 1) { + strides[1] = + SUN4I_FRONTEND_LINESTRD_TILED(fb->pitches[1]); + + regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF1_REG, + SUN4I_FRONTEND_TB_OFF_X1(offset)); + } + + if (fb->format->num_planes > 2) { + strides[2] = + SUN4I_FRONTEND_LINESTRD_TILED(fb->pitches[2]); + + regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF2_REG, + SUN4I_FRONTEND_TB_OFF_X1(offset)); + } + } else { + strides[0] = fb->pitches[0]; + + if (fb->format->num_planes > 1) + strides[1] = fb->pitches[1]; + + if (fb->format->num_planes > 2) + strides[2] = fb->pitches[2]; + } /* Set the line width */ DRM_DEBUG_DRIVER("Frontend stride: %d bytes\n", fb->pitches[0]); regmap_write(frontend->regs, SUN4I_FRONTEND_LINESTRD0_REG, - fb->pitches[0]); + strides[0]); + + if (fb->format->num_planes > 1) + regmap_write(frontend->regs, SUN4I_FRONTEND_LINESTRD1_REG, + strides[1]); + + if (fb->format->num_planes > 2) + regmap_write(frontend->regs, SUN4I_FRONTEND_LINESTRD2_REG, + strides[2]); + + /* Some planar formats require chroma channel swapping by hand. */ + swap = sun4i_frontend_format_chroma_requires_swap(fb->format->format); /* Set the physical address of the buffer in memory */ paddr = drm_fb_cma_get_gem_addr(fb, state, 0); paddr -= PHYS_OFFSET; - DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr); + DRM_DEBUG_DRIVER("Setting buffer #0 address to %pad\n", &paddr); regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR0_REG, paddr); + + if (fb->format->num_planes > 1) { + paddr = drm_fb_cma_get_gem_addr(fb, state, swap ? 2 : 1); + paddr -= PHYS_OFFSET; + DRM_DEBUG_DRIVER("Setting buffer #1 address to %pad\n", &paddr); + regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR1_REG, + paddr); + } + + if (fb->format->num_planes > 2) { + paddr = drm_fb_cma_get_gem_addr(fb, state, swap ? 1 : 2); + paddr -= PHYS_OFFSET; + DRM_DEBUG_DRIVER("Setting buffer #2 address to %pad\n", &paddr); + regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR2_REG, + paddr); + } } EXPORT_SYMBOL(sun4i_frontend_update_buffer); -static int sun4i_frontend_drm_format_to_input_fmt(uint32_t fmt, u32 *val) +static int +sun4i_frontend_drm_format_to_input_fmt(const struct drm_format_info *format, + u32 *val) { - switch (fmt) { - case DRM_FORMAT_XRGB8888: + if (!format->is_yuv) *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_RGB; - return 0; - - default: + else if (drm_format_info_is_yuv_sampling_411(format)) + *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV411; + else if (drm_format_info_is_yuv_sampling_420(format)) + *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV420; + else if (drm_format_info_is_yuv_sampling_422(format)) + *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV422; + else if (drm_format_info_is_yuv_sampling_444(format)) + *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV444; + else return -EINVAL; - } + + return 0; } -static int sun4i_frontend_drm_format_to_input_mode(uint32_t fmt, u32 *val) +static int +sun4i_frontend_drm_format_to_input_mode(const struct drm_format_info *format, + uint64_t modifier, u32 *val) { - if (drm_format_num_planes(fmt) == 1) + bool tiled = (modifier == DRM_FORMAT_MOD_ALLWINNER_TILED); + + switch (format->num_planes) { + case 1: *val = SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_PACKED; - else - return -EINVAL; + return 0; - return 0; + case 2: + *val = tiled ? SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_SEMIPLANAR + : SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_SEMIPLANAR; + return 0; + + case 3: + *val = tiled ? SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_PLANAR + : SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_PLANAR; + return 0; + + default: + return -EINVAL; + } } -static int sun4i_frontend_drm_format_to_input_sequence(uint32_t fmt, u32 *val) +static int +sun4i_frontend_drm_format_to_input_sequence(const struct drm_format_info *format, + u32 *val) { - switch (fmt) { + /* Planar formats have an explicit input sequence. */ + if (drm_format_info_is_yuv_planar(format)) { + *val = 0; + return 0; + } + + switch (format->format) { case DRM_FORMAT_BGRX8888: *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_BGRX; return 0; + case DRM_FORMAT_NV12: + *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UV; + return 0; + + case DRM_FORMAT_NV16: + *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UV; + return 0; + + case DRM_FORMAT_NV21: + *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VU; + return 0; + + case DRM_FORMAT_NV61: + *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VU; + return 0; + + case DRM_FORMAT_UYVY: + *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UYVY; + return 0; + + case DRM_FORMAT_VYUY: + *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VYUY; + return 0; + case DRM_FORMAT_XRGB8888: *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_XRGB; return 0; + case DRM_FORMAT_YUYV: + *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_YUYV; + return 0; + + case DRM_FORMAT_YVYU: + *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_YVYU; + return 0; + default: return -EINVAL; } @@ -160,14 +360,32 @@ static int sun4i_frontend_drm_format_to_output_fmt(uint32_t fmt, u32 *val) static const uint32_t sun4i_frontend_formats[] = { DRM_FORMAT_BGRX8888, + DRM_FORMAT_NV12, + DRM_FORMAT_NV16, + DRM_FORMAT_NV21, + DRM_FORMAT_NV61, + DRM_FORMAT_UYVY, + DRM_FORMAT_VYUY, DRM_FORMAT_XRGB8888, + DRM_FORMAT_YUV411, + DRM_FORMAT_YUV420, + DRM_FORMAT_YUV422, + DRM_FORMAT_YUV444, + DRM_FORMAT_YUYV, + DRM_FORMAT_YVU411, + DRM_FORMAT_YVU420, + DRM_FORMAT_YVU422, + DRM_FORMAT_YVU444, + DRM_FORMAT_YVYU, }; bool sun4i_frontend_format_is_supported(uint32_t fmt, uint64_t modifier) { unsigned int i; - if (modifier != DRM_FORMAT_MOD_LINEAR) + if (modifier == DRM_FORMAT_MOD_ALLWINNER_TILED) + return sun4i_frontend_format_supports_tiling(fmt); + else if (modifier != DRM_FORMAT_MOD_LINEAR) return false; for (i = 0; i < ARRAY_SIZE(sun4i_frontend_formats); i++) @@ -183,9 +401,12 @@ int sun4i_frontend_update_formats(struct sun4i_frontend *frontend, { struct drm_plane_state *state = plane->state; struct drm_framebuffer *fb = state->fb; - uint32_t format = fb->format->format; + const struct drm_format_info *format = fb->format; + uint64_t modifier = fb->modifier; u32 out_fmt_val; u32 in_fmt_val, in_mod_val, in_ps_val; + unsigned int i; + u32 bypass; int ret; ret = sun4i_frontend_drm_format_to_input_fmt(format, &in_fmt_val); @@ -194,7 +415,8 @@ int sun4i_frontend_update_formats(struct sun4i_frontend *frontend, return ret; } - ret = sun4i_frontend_drm_format_to_input_mode(format, &in_mod_val); + ret = sun4i_frontend_drm_format_to_input_mode(format, modifier, + &in_mod_val); if (ret) { DRM_DEBUG_DRIVER("Invalid input mode\n"); return ret; @@ -216,16 +438,39 @@ int sun4i_frontend_update_formats(struct sun4i_frontend *frontend, * I have no idea what this does exactly, but it seems to be * related to the scaler FIR filter phase parameters. */ - regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZPHASE_REG, 0x400); - regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZPHASE_REG, 0x400); - regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE0_REG, 0x400); - regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE0_REG, 0x400); - regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE1_REG, 0x400); - regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE1_REG, 0x400); + regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZPHASE_REG, + frontend->data->ch_phase[0].horzphase); + regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZPHASE_REG, + frontend->data->ch_phase[1].horzphase); + regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE0_REG, + frontend->data->ch_phase[0].vertphase[0]); + regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE0_REG, + frontend->data->ch_phase[1].vertphase[0]); + regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE1_REG, + frontend->data->ch_phase[0].vertphase[1]); + regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE1_REG, + frontend->data->ch_phase[1].vertphase[1]); + + /* + * Checking the input format is sufficient since we currently only + * support RGB output formats to the backend. If YUV output formats + * ever get supported, an YUV input and output would require bypassing + * the CSC engine too. + */ + if (format->is_yuv) { + /* Setup the CSC engine for YUV to RGB conversion. */ + bypass = 0; + + for (i = 0; i < ARRAY_SIZE(sunxi_bt601_yuv2rgb_coef); i++) + regmap_write(frontend->regs, + SUN4I_FRONTEND_CSC_COEF_REG(i), + sunxi_bt601_yuv2rgb_coef[i]); + } else { + bypass = SUN4I_FRONTEND_BYPASS_CSC_EN; + } regmap_update_bits(frontend->regs, SUN4I_FRONTEND_BYPASS_REG, - SUN4I_FRONTEND_BYPASS_CSC_EN, - SUN4I_FRONTEND_BYPASS_CSC_EN); + SUN4I_FRONTEND_BYPASS_CSC_EN, bypass); regmap_write(frontend->regs, SUN4I_FRONTEND_INPUT_FMT_REG, in_mod_val | in_fmt_val | in_ps_val); @@ -321,6 +566,10 @@ static int sun4i_frontend_bind(struct device *dev, struct device *master, frontend->dev = dev; frontend->node = dev->of_node; + frontend->data = of_device_get_match_data(dev); + if (!frontend->data) + return -ENODEV; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); regs = devm_ioremap_resource(dev, res); if (IS_ERR(regs)) @@ -433,8 +682,51 @@ static const struct dev_pm_ops sun4i_frontend_pm_ops = { .runtime_suspend = sun4i_frontend_runtime_suspend, }; +static const struct sun4i_frontend_data sun4i_a10_frontend = { + .ch_phase = { + { + .horzphase = 0, + .vertphase = { 0, 0 }, + }, + { + .horzphase = 0xfc000, + .vertphase = { 0xfc000, 0xfc000 }, + }, + }, + .has_coef_rdy = true, +}; + +static const struct sun4i_frontend_data sun8i_a33_frontend = { + .ch_phase = { + { + .horzphase = 0x400, + .vertphase = { 0x400, 0x400 }, + }, + { + .horzphase = 0x400, + .vertphase = { 0x400, 0x400 }, + }, + }, + .has_coef_access_ctrl = true, +}; + const struct of_device_id sun4i_frontend_of_table[] = { - { .compatible = "allwinner,sun8i-a33-display-frontend" }, + { + .compatible = "allwinner,sun4i-a10-display-frontend", + .data = &sun4i_a10_frontend + }, + { + .compatible = "allwinner,sun7i-a20-display-frontend", + .data = &sun4i_a10_frontend + }, + { + .compatible = "allwinner,sun8i-a23-display-frontend", + .data = &sun8i_a33_frontend + }, + { + .compatible = "allwinner,sun8i-a33-display-frontend", + .data = &sun8i_a33_frontend + }, { } }; EXPORT_SYMBOL(sun4i_frontend_of_table); diff --git a/drivers/gpu/drm/sun4i/sun4i_frontend.h b/drivers/gpu/drm/sun4i/sun4i_frontend.h index ad146e8d8d70..0c382c1ddb0f 100644 --- a/drivers/gpu/drm/sun4i/sun4i_frontend.h +++ b/drivers/gpu/drm/sun4i/sun4i_frontend.h @@ -22,12 +22,49 @@ #define SUN4I_FRONTEND_BYPASS_CSC_EN BIT(1) #define SUN4I_FRONTEND_BUF_ADDR0_REG 0x020 +#define SUN4I_FRONTEND_BUF_ADDR1_REG 0x024 +#define SUN4I_FRONTEND_BUF_ADDR2_REG 0x028 + +#define SUN4I_FRONTEND_TB_OFF0_REG 0x030 +#define SUN4I_FRONTEND_TB_OFF1_REG 0x034 +#define SUN4I_FRONTEND_TB_OFF2_REG 0x038 +#define SUN4I_FRONTEND_TB_OFF_X1(x1) ((x1) << 16) +#define SUN4I_FRONTEND_TB_OFF_Y0(y0) ((y0) << 8) +#define SUN4I_FRONTEND_TB_OFF_X0(x0) (x0) #define SUN4I_FRONTEND_LINESTRD0_REG 0x040 +#define SUN4I_FRONTEND_LINESTRD1_REG 0x044 +#define SUN4I_FRONTEND_LINESTRD2_REG 0x048 + +/* + * In tiled mode, the stride is defined as the distance between the start of the + * end line of the current tile and the start of the first line in the next + * vertical tile. + * + * Tiles are represented in row-major order, thus the end line of current tile + * starts at: 31 * 32 (31 lines of 32 cols), the next vertical tile starts at: + * 32-bit-aligned-width * 32 and the distance is: + * 32 * (32-bit-aligned-width - 31). + */ +#define SUN4I_FRONTEND_LINESTRD_TILED(stride) (((stride) - 31) * 32) #define SUN4I_FRONTEND_INPUT_FMT_REG 0x04c +#define SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_PLANAR (0 << 8) #define SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_PACKED (1 << 8) +#define SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_SEMIPLANAR (2 << 8) +#define SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_PLANAR (4 << 8) +#define SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_SEMIPLANAR (6 << 8) +#define SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV444 (0 << 4) +#define SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV422 (1 << 4) +#define SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV420 (2 << 4) +#define SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV411 (3 << 4) #define SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_RGB (5 << 4) +#define SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UYVY 0 +#define SUN4I_FRONTEND_INPUT_FMT_DATA_PS_YUYV 1 +#define SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VYUY 2 +#define SUN4I_FRONTEND_INPUT_FMT_DATA_PS_YVYU 3 +#define SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UV 0 +#define SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VU 1 #define SUN4I_FRONTEND_INPUT_FMT_DATA_PS_BGRX 0 #define SUN4I_FRONTEND_INPUT_FMT_DATA_PS_XRGB 1 @@ -35,6 +72,8 @@ #define SUN4I_FRONTEND_OUTPUT_FMT_DATA_FMT_BGRX8888 1 #define SUN4I_FRONTEND_OUTPUT_FMT_DATA_FMT_XRGB8888 2 +#define SUN4I_FRONTEND_CSC_COEF_REG(c) (0x070 + (0x4 * (c))) + #define SUN4I_FRONTEND_CH0_INSIZE_REG 0x100 #define SUN4I_FRONTEND_INSIZE(h, w) ((((h) - 1) << 16) | (((w) - 1))) @@ -73,6 +112,16 @@ struct drm_plane; struct regmap; struct reset_control; +struct sun4i_frontend_data { + bool has_coef_access_ctrl; + bool has_coef_rdy; + + struct { + u32 horzphase; + u32 vertphase[2]; + } ch_phase[2]; +}; + struct sun4i_frontend { struct list_head list; struct device *dev; @@ -83,9 +132,12 @@ struct sun4i_frontend { struct clk *ram_clk; struct regmap *regs; struct reset_control *reset; + + const struct sun4i_frontend_data *data; }; extern const struct of_device_id sun4i_frontend_of_table[]; +extern const u32 sunxi_bt601_yuv2rgb_coef[12]; int sun4i_frontend_init(struct sun4i_frontend *frontend); void sun4i_frontend_exit(struct sun4i_frontend *frontend); diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c index 416da5376701..d18862629301 100644 --- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c @@ -11,7 +11,7 @@ #include <drm/drmP.h> #include <drm/drm_atomic_helper.h> -#include <drm/drm_crtc_helper.h> +#include <drm/drm_probe_helper.h> #include <drm/drm_edid.h> #include <drm/drm_encoder.h> #include <drm/drm_of.h> @@ -52,7 +52,8 @@ static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi, u8 buffer[17]; int i, ret; - ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); + ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, + &hdmi->connector, mode); if (ret < 0) { DRM_ERROR("Failed to get infoframes from mode\n"); return ret; diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c b/drivers/gpu/drm/sun4i/sun4i_layer.c index 29631e0efde3..a514fe88d441 100644 --- a/drivers/gpu/drm/sun4i/sun4i_layer.c +++ b/drivers/gpu/drm/sun4i/sun4i_layer.c @@ -114,6 +114,18 @@ static void sun4i_backend_layer_atomic_update(struct drm_plane *plane, sun4i_backend_layer_enable(backend, layer->id, true); } +static bool sun4i_layer_format_mod_supported(struct drm_plane *plane, + uint32_t format, uint64_t modifier) +{ + struct sun4i_layer *layer = plane_to_sun4i_layer(plane); + + if (IS_ERR_OR_NULL(layer->backend->frontend)) + sun4i_backend_format_is_supported(format, modifier); + + return sun4i_backend_format_is_supported(format, modifier) || + sun4i_frontend_format_is_supported(format, modifier); +} + static const struct drm_plane_helper_funcs sun4i_backend_layer_helper_funcs = { .prepare_fb = drm_gem_fb_prepare_fb, .atomic_disable = sun4i_backend_layer_atomic_disable, @@ -127,6 +139,7 @@ static const struct drm_plane_funcs sun4i_backend_layer_funcs = { .disable_plane = drm_atomic_helper_disable_plane, .reset = sun4i_backend_layer_reset, .update_plane = drm_atomic_helper_update_plane, + .format_mod_supported = sun4i_layer_format_mod_supported, }; static const uint32_t sun4i_layer_formats[] = { @@ -138,17 +151,53 @@ static const uint32_t sun4i_layer_formats[] = { DRM_FORMAT_RGBA4444, DRM_FORMAT_RGB888, DRM_FORMAT_RGB565, + DRM_FORMAT_NV12, + DRM_FORMAT_NV16, + DRM_FORMAT_NV21, + DRM_FORMAT_NV61, DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, DRM_FORMAT_XRGB8888, + DRM_FORMAT_YUV411, + DRM_FORMAT_YUV420, + DRM_FORMAT_YUV422, + DRM_FORMAT_YUV444, DRM_FORMAT_YUYV, + DRM_FORMAT_YVU411, + DRM_FORMAT_YVU420, + DRM_FORMAT_YVU422, + DRM_FORMAT_YVU444, DRM_FORMAT_YVYU, }; +static const uint32_t sun4i_backend_layer_formats[] = { + DRM_FORMAT_ARGB8888, + DRM_FORMAT_ARGB4444, + DRM_FORMAT_ARGB1555, + DRM_FORMAT_RGBA5551, + DRM_FORMAT_RGBA4444, + DRM_FORMAT_RGB888, + DRM_FORMAT_RGB565, + DRM_FORMAT_UYVY, + DRM_FORMAT_VYUY, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_YUYV, + DRM_FORMAT_YVYU, +}; + +static const uint64_t sun4i_layer_modifiers[] = { + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_ALLWINNER_TILED, + DRM_FORMAT_MOD_INVALID +}; + static struct sun4i_layer *sun4i_layer_init_one(struct drm_device *drm, struct sun4i_backend *backend, enum drm_plane_type type) { + const uint64_t *modifiers = sun4i_layer_modifiers; + const uint32_t *formats = sun4i_layer_formats; + unsigned int formats_len = ARRAY_SIZE(sun4i_layer_formats); struct sun4i_layer *layer; int ret; @@ -156,12 +205,19 @@ static struct sun4i_layer *sun4i_layer_init_one(struct drm_device *drm, if (!layer) return ERR_PTR(-ENOMEM); + layer->backend = backend; + + if (IS_ERR_OR_NULL(backend->frontend)) { + formats = sun4i_backend_layer_formats; + formats_len = ARRAY_SIZE(sun4i_backend_layer_formats); + modifiers = NULL; + } + /* possible crtcs are set later */ ret = drm_universal_plane_init(drm, &layer->plane, 0, &sun4i_backend_layer_funcs, - sun4i_layer_formats, - ARRAY_SIZE(sun4i_layer_formats), - NULL, type, NULL); + formats, formats_len, + modifiers, type, NULL); if (ret) { dev_err(drm->dev, "Couldn't initialize layer\n"); return ERR_PTR(ret); @@ -169,7 +225,6 @@ static struct sun4i_layer *sun4i_layer_init_one(struct drm_device *drm, drm_plane_helper_add(&layer->plane, &sun4i_backend_layer_helper_funcs); - layer->backend = backend; drm_plane_create_alpha_property(&layer->plane); drm_plane_create_zpos_property(&layer->plane, 0, 0, diff --git a/drivers/gpu/drm/sun4i/sun4i_lvds.c b/drivers/gpu/drm/sun4i/sun4i_lvds.c index e7eb0d1e17be..147b97ed1a09 100644 --- a/drivers/gpu/drm/sun4i/sun4i_lvds.c +++ b/drivers/gpu/drm/sun4i/sun4i_lvds.c @@ -8,9 +8,9 @@ #include <drm/drmP.h> #include <drm/drm_atomic_helper.h> -#include <drm/drm_crtc_helper.h> #include <drm/drm_of.h> #include <drm/drm_panel.h> +#include <drm/drm_probe_helper.h> #include "sun4i_crtc.h" #include "sun4i_tcon.h" diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c b/drivers/gpu/drm/sun4i/sun4i_rgb.c index f4a22689eb54..cae19e7bbeaa 100644 --- a/drivers/gpu/drm/sun4i/sun4i_rgb.c +++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c @@ -14,9 +14,9 @@ #include <drm/drmP.h> #include <drm/drm_atomic_helper.h> -#include <drm/drm_crtc_helper.h> #include <drm/drm_of.h> #include <drm/drm_panel.h> +#include <drm/drm_probe_helper.h> #include "sun4i_crtc.h" #include "sun4i_tcon.h" diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index cf45d0f940f9..7136fc91c603 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -14,11 +14,11 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_connector.h> #include <drm/drm_crtc.h> -#include <drm/drm_crtc_helper.h> #include <drm/drm_encoder.h> #include <drm/drm_modes.h> #include <drm/drm_of.h> #include <drm/drm_panel.h> +#include <drm/drm_probe_helper.h> #include <uapi/drm/drm_mode.h> @@ -1496,6 +1496,7 @@ const struct of_device_id sun4i_tcon_of_table[] = { { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks }, { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks }, { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks }, + { .compatible = "allwinner,sun8i-a23-tcon", .data = &sun8i_a33_quirks }, { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks }, { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks }, { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks }, diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c index 1a838d208211..e8700a362064 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tv.c +++ b/drivers/gpu/drm/sun4i/sun4i_tv.c @@ -18,9 +18,9 @@ #include <drm/drmP.h> #include <drm/drm_atomic_helper.h> -#include <drm/drm_crtc_helper.h> #include <drm/drm_of.h> #include <drm/drm_panel.h> +#include <drm/drm_probe_helper.h> #include "sun4i_crtc.h" #include "sun4i_drv.h" diff --git a/drivers/gpu/drm/sun4i/sun6i_drc.c b/drivers/gpu/drm/sun4i/sun6i_drc.c index 88eb268fdf73..442094a4af7a 100644 --- a/drivers/gpu/drm/sun4i/sun6i_drc.c +++ b/drivers/gpu/drm/sun4i/sun6i_drc.c @@ -101,6 +101,7 @@ static int sun6i_drc_remove(struct platform_device *pdev) static const struct of_device_id sun6i_drc_of_table[] = { { .compatible = "allwinner,sun6i-a31-drc" }, { .compatible = "allwinner,sun6i-a31s-drc" }, + { .compatible = "allwinner,sun8i-a23-drc" }, { .compatible = "allwinner,sun8i-a33-drc" }, { .compatible = "allwinner,sun9i-a80-drc" }, { } diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c deleted file mode 100644 index e4d19431fa0e..000000000000 --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c +++ /dev/null @@ -1,292 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2016 Allwinnertech Co., Ltd. - * Copyright (C) 2017-2018 Bootlin - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - */ - -#include <linux/bitops.h> -#include <linux/clk.h> -#include <linux/of_address.h> -#include <linux/regmap.h> -#include <linux/reset.h> - -#include "sun6i_mipi_dsi.h" - -#define SUN6I_DPHY_GCTL_REG 0x00 -#define SUN6I_DPHY_GCTL_LANE_NUM(n) ((((n) - 1) & 3) << 4) -#define SUN6I_DPHY_GCTL_EN BIT(0) - -#define SUN6I_DPHY_TX_CTL_REG 0x04 -#define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT BIT(28) - -#define SUN6I_DPHY_TX_TIME0_REG 0x10 -#define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n) (((n) & 0xff) << 24) -#define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n) (((n) & 0xff) << 16) -#define SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(n) ((n) & 0xff) - -#define SUN6I_DPHY_TX_TIME1_REG 0x14 -#define SUN6I_DPHY_TX_TIME1_CLK_POST(n) (((n) & 0xff) << 24) -#define SUN6I_DPHY_TX_TIME1_CLK_PRE(n) (((n) & 0xff) << 16) -#define SUN6I_DPHY_TX_TIME1_CLK_ZERO(n) (((n) & 0xff) << 8) -#define SUN6I_DPHY_TX_TIME1_CLK_PREPARE(n) ((n) & 0xff) - -#define SUN6I_DPHY_TX_TIME2_REG 0x18 -#define SUN6I_DPHY_TX_TIME2_CLK_TRAIL(n) ((n) & 0xff) - -#define SUN6I_DPHY_TX_TIME3_REG 0x1c - -#define SUN6I_DPHY_TX_TIME4_REG 0x20 -#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n) (((n) & 0xff) << 8) -#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n) ((n) & 0xff) - -#define SUN6I_DPHY_ANA0_REG 0x4c -#define SUN6I_DPHY_ANA0_REG_PWS BIT(31) -#define SUN6I_DPHY_ANA0_REG_DMPC BIT(28) -#define SUN6I_DPHY_ANA0_REG_DMPD(n) (((n) & 0xf) << 24) -#define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12) -#define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8) - -#define SUN6I_DPHY_ANA1_REG 0x50 -#define SUN6I_DPHY_ANA1_REG_VTTMODE BIT(31) -#define SUN6I_DPHY_ANA1_REG_CSMPS(n) (((n) & 3) << 28) -#define SUN6I_DPHY_ANA1_REG_SVTT(n) (((n) & 0xf) << 24) - -#define SUN6I_DPHY_ANA2_REG 0x54 -#define SUN6I_DPHY_ANA2_EN_P2S_CPU(n) (((n) & 0xf) << 24) -#define SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK GENMASK(27, 24) -#define SUN6I_DPHY_ANA2_EN_CK_CPU BIT(4) -#define SUN6I_DPHY_ANA2_REG_ENIB BIT(1) - -#define SUN6I_DPHY_ANA3_REG 0x58 -#define SUN6I_DPHY_ANA3_EN_VTTD(n) (((n) & 0xf) << 28) -#define SUN6I_DPHY_ANA3_EN_VTTD_MASK GENMASK(31, 28) -#define SUN6I_DPHY_ANA3_EN_VTTC BIT(27) -#define SUN6I_DPHY_ANA3_EN_DIV BIT(26) -#define SUN6I_DPHY_ANA3_EN_LDOC BIT(25) -#define SUN6I_DPHY_ANA3_EN_LDOD BIT(24) -#define SUN6I_DPHY_ANA3_EN_LDOR BIT(18) - -#define SUN6I_DPHY_ANA4_REG 0x5c -#define SUN6I_DPHY_ANA4_REG_DMPLVC BIT(24) -#define SUN6I_DPHY_ANA4_REG_DMPLVD(n) (((n) & 0xf) << 20) -#define SUN6I_DPHY_ANA4_REG_CKDV(n) (((n) & 0x1f) << 12) -#define SUN6I_DPHY_ANA4_REG_TMSC(n) (((n) & 3) << 10) -#define SUN6I_DPHY_ANA4_REG_TMSD(n) (((n) & 3) << 8) -#define SUN6I_DPHY_ANA4_REG_TXDNSC(n) (((n) & 3) << 6) -#define SUN6I_DPHY_ANA4_REG_TXDNSD(n) (((n) & 3) << 4) -#define SUN6I_DPHY_ANA4_REG_TXPUSC(n) (((n) & 3) << 2) -#define SUN6I_DPHY_ANA4_REG_TXPUSD(n) ((n) & 3) - -#define SUN6I_DPHY_DBG5_REG 0xf4 - -int sun6i_dphy_init(struct sun6i_dphy *dphy, unsigned int lanes) -{ - reset_control_deassert(dphy->reset); - clk_prepare_enable(dphy->mod_clk); - clk_set_rate_exclusive(dphy->mod_clk, 150000000); - - regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG, - SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT); - - regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG, - SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) | - SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) | - SUN6I_DPHY_TX_TIME0_HS_TRAIL(10)); - - regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG, - SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) | - SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) | - SUN6I_DPHY_TX_TIME1_CLK_PRE(3) | - SUN6I_DPHY_TX_TIME1_CLK_POST(10)); - - regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG, - SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30)); - - regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0); - - regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG, - SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) | - SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3)); - - regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG, - SUN6I_DPHY_GCTL_LANE_NUM(lanes) | - SUN6I_DPHY_GCTL_EN); - - return 0; -} - -int sun6i_dphy_power_on(struct sun6i_dphy *dphy, unsigned int lanes) -{ - u8 lanes_mask = GENMASK(lanes - 1, 0); - - regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG, - SUN6I_DPHY_ANA0_REG_PWS | - SUN6I_DPHY_ANA0_REG_DMPC | - SUN6I_DPHY_ANA0_REG_SLV(7) | - SUN6I_DPHY_ANA0_REG_DMPD(lanes_mask) | - SUN6I_DPHY_ANA0_REG_DEN(lanes_mask)); - - regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG, - SUN6I_DPHY_ANA1_REG_CSMPS(1) | - SUN6I_DPHY_ANA1_REG_SVTT(7)); - - regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG, - SUN6I_DPHY_ANA4_REG_CKDV(1) | - SUN6I_DPHY_ANA4_REG_TMSC(1) | - SUN6I_DPHY_ANA4_REG_TMSD(1) | - SUN6I_DPHY_ANA4_REG_TXDNSC(1) | - SUN6I_DPHY_ANA4_REG_TXDNSD(1) | - SUN6I_DPHY_ANA4_REG_TXPUSC(1) | - SUN6I_DPHY_ANA4_REG_TXPUSD(1) | - SUN6I_DPHY_ANA4_REG_DMPLVC | - SUN6I_DPHY_ANA4_REG_DMPLVD(lanes_mask)); - - regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG, - SUN6I_DPHY_ANA2_REG_ENIB); - udelay(5); - - regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG, - SUN6I_DPHY_ANA3_EN_LDOR | - SUN6I_DPHY_ANA3_EN_LDOC | - SUN6I_DPHY_ANA3_EN_LDOD); - udelay(1); - - regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG, - SUN6I_DPHY_ANA3_EN_VTTC | - SUN6I_DPHY_ANA3_EN_VTTD_MASK, - SUN6I_DPHY_ANA3_EN_VTTC | - SUN6I_DPHY_ANA3_EN_VTTD(lanes_mask)); - udelay(1); - - regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG, - SUN6I_DPHY_ANA3_EN_DIV, - SUN6I_DPHY_ANA3_EN_DIV); - udelay(1); - - regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG, - SUN6I_DPHY_ANA2_EN_CK_CPU, - SUN6I_DPHY_ANA2_EN_CK_CPU); - udelay(1); - - regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA1_REG, - SUN6I_DPHY_ANA1_REG_VTTMODE, - SUN6I_DPHY_ANA1_REG_VTTMODE); - - regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG, - SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK, - SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask)); - - return 0; -} - -int sun6i_dphy_power_off(struct sun6i_dphy *dphy) -{ - regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA1_REG, - SUN6I_DPHY_ANA1_REG_VTTMODE, 0); - - return 0; -} - -int sun6i_dphy_exit(struct sun6i_dphy *dphy) -{ - clk_rate_exclusive_put(dphy->mod_clk); - clk_disable_unprepare(dphy->mod_clk); - reset_control_assert(dphy->reset); - - return 0; -} - -static struct regmap_config sun6i_dphy_regmap_config = { - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, - .max_register = SUN6I_DPHY_DBG5_REG, - .name = "mipi-dphy", -}; - -static const struct of_device_id sun6i_dphy_of_table[] = { - { .compatible = "allwinner,sun6i-a31-mipi-dphy" }, - { } -}; - -int sun6i_dphy_probe(struct sun6i_dsi *dsi, struct device_node *node) -{ - struct sun6i_dphy *dphy; - struct resource res; - void __iomem *regs; - int ret; - - if (!of_match_node(sun6i_dphy_of_table, node)) { - dev_err(dsi->dev, "Incompatible D-PHY\n"); - return -EINVAL; - } - - dphy = devm_kzalloc(dsi->dev, sizeof(*dphy), GFP_KERNEL); - if (!dphy) - return -ENOMEM; - - ret = of_address_to_resource(node, 0, &res); - if (ret) { - dev_err(dsi->dev, "phy: Couldn't get our resources\n"); - return ret; - } - - regs = devm_ioremap_resource(dsi->dev, &res); - if (IS_ERR(regs)) { - dev_err(dsi->dev, "Couldn't map the DPHY encoder registers\n"); - return PTR_ERR(regs); - } - - dphy->regs = devm_regmap_init_mmio(dsi->dev, regs, - &sun6i_dphy_regmap_config); - if (IS_ERR(dphy->regs)) { - dev_err(dsi->dev, "Couldn't create the DPHY encoder regmap\n"); - return PTR_ERR(dphy->regs); - } - - dphy->reset = of_reset_control_get_shared(node, NULL); - if (IS_ERR(dphy->reset)) { - dev_err(dsi->dev, "Couldn't get our reset line\n"); - return PTR_ERR(dphy->reset); - } - - dphy->bus_clk = of_clk_get_by_name(node, "bus"); - if (IS_ERR(dphy->bus_clk)) { - dev_err(dsi->dev, "Couldn't get the DPHY bus clock\n"); - ret = PTR_ERR(dphy->bus_clk); - goto err_free_reset; - } - regmap_mmio_attach_clk(dphy->regs, dphy->bus_clk); - - dphy->mod_clk = of_clk_get_by_name(node, "mod"); - if (IS_ERR(dphy->mod_clk)) { - dev_err(dsi->dev, "Couldn't get the DPHY mod clock\n"); - ret = PTR_ERR(dphy->mod_clk); - goto err_free_bus; - } - - dsi->dphy = dphy; - - return 0; - -err_free_bus: - regmap_mmio_detach_clk(dphy->regs); - clk_put(dphy->bus_clk); -err_free_reset: - reset_control_put(dphy->reset); - return ret; -} - -int sun6i_dphy_remove(struct sun6i_dsi *dsi) -{ - struct sun6i_dphy *dphy = dsi->dphy; - - regmap_mmio_detach_clk(dphy->regs); - clk_put(dphy->mod_clk); - clk_put(dphy->bus_clk); - reset_control_put(dphy->reset); - - return 0; -} diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c index e3b34a345546..318994cd1b85 100644 --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c @@ -16,12 +16,13 @@ #include <linux/slab.h> #include <linux/phy/phy.h> +#include <linux/phy/phy-mipi-dphy.h> #include <drm/drmP.h> #include <drm/drm_atomic_helper.h> -#include <drm/drm_crtc_helper.h> #include <drm/drm_mipi_dsi.h> #include <drm/drm_panel.h> +#include <drm/drm_probe_helper.h> #include "sun4i_drv.h" #include "sun6i_mipi_dsi.h" @@ -616,6 +617,8 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder) struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder); struct mipi_dsi_device *device = dsi->device; + union phy_configure_opts opts = { 0 }; + struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy; u16 delay; DRM_DEBUG_DRIVER("Enabling DSI output\n"); @@ -634,8 +637,15 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder) sun6i_dsi_setup_format(dsi, mode); sun6i_dsi_setup_timings(dsi, mode); - sun6i_dphy_init(dsi->dphy, device->lanes); - sun6i_dphy_power_on(dsi->dphy, device->lanes); + phy_init(dsi->dphy); + + phy_mipi_dphy_get_default_config(mode->clock * 1000, + mipi_dsi_pixel_format_to_bpp(device->format), + device->lanes, cfg); + + phy_set_mode(dsi->dphy, PHY_MODE_MIPI_DPHY); + phy_configure(dsi->dphy, &opts); + phy_power_on(dsi->dphy); if (!IS_ERR(dsi->panel)) drm_panel_prepare(dsi->panel); @@ -673,8 +683,8 @@ static void sun6i_dsi_encoder_disable(struct drm_encoder *encoder) drm_panel_unprepare(dsi->panel); } - sun6i_dphy_power_off(dsi->dphy); - sun6i_dphy_exit(dsi->dphy); + phy_power_off(dsi->dphy); + phy_exit(dsi->dphy); pm_runtime_put(dsi->dev); } @@ -967,7 +977,6 @@ static const struct component_ops sun6i_dsi_ops = { static int sun6i_dsi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct device_node *dphy_node; struct sun6i_dsi *dsi; struct resource *res; void __iomem *base; @@ -1013,11 +1022,10 @@ static int sun6i_dsi_probe(struct platform_device *pdev) */ clk_set_rate_exclusive(dsi->mod_clk, 297000000); - dphy_node = of_parse_phandle(dev->of_node, "phys", 0); - ret = sun6i_dphy_probe(dsi, dphy_node); - of_node_put(dphy_node); - if (ret) { + dsi->dphy = devm_phy_get(dev, "dphy"); + if (IS_ERR(dsi->dphy)) { dev_err(dev, "Couldn't get the MIPI D-PHY\n"); + ret = PTR_ERR(dsi->dphy); goto err_unprotect_clk; } @@ -1026,7 +1034,7 @@ static int sun6i_dsi_probe(struct platform_device *pdev) ret = mipi_dsi_host_register(&dsi->host); if (ret) { dev_err(dev, "Couldn't register MIPI-DSI host\n"); - goto err_remove_phy; + goto err_pm_disable; } ret = component_add(&pdev->dev, &sun6i_dsi_ops); @@ -1039,9 +1047,8 @@ static int sun6i_dsi_probe(struct platform_device *pdev) err_remove_dsi_host: mipi_dsi_host_unregister(&dsi->host); -err_remove_phy: +err_pm_disable: pm_runtime_disable(dev); - sun6i_dphy_remove(dsi); err_unprotect_clk: clk_rate_exclusive_put(dsi->mod_clk); return ret; @@ -1055,7 +1062,6 @@ static int sun6i_dsi_remove(struct platform_device *pdev) component_del(&pdev->dev, &sun6i_dsi_ops); mipi_dsi_host_unregister(&dsi->host); pm_runtime_disable(dev); - sun6i_dphy_remove(dsi); clk_rate_exclusive_put(dsi->mod_clk); return 0; diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h index dbbc5b3ecbda..a07090579f84 100644 --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h @@ -13,13 +13,6 @@ #include <drm/drm_encoder.h> #include <drm/drm_mipi_dsi.h> -struct sun6i_dphy { - struct clk *bus_clk; - struct clk *mod_clk; - struct regmap *regs; - struct reset_control *reset; -}; - struct sun6i_dsi { struct drm_connector connector; struct drm_encoder encoder; @@ -29,7 +22,7 @@ struct sun6i_dsi { struct clk *mod_clk; struct regmap *regs; struct reset_control *reset; - struct sun6i_dphy *dphy; + struct phy *dphy; struct device *dev; struct sun4i_drv *drv; @@ -52,12 +45,4 @@ static inline struct sun6i_dsi *encoder_to_sun6i_dsi(const struct drm_encoder *e return container_of(encoder, struct sun6i_dsi, encoder); }; -int sun6i_dphy_probe(struct sun6i_dsi *dsi, struct device_node *node); -int sun6i_dphy_remove(struct sun6i_dsi *dsi); - -int sun6i_dphy_init(struct sun6i_dphy *dphy, unsigned int lanes); -int sun6i_dphy_power_on(struct sun6i_dphy *dphy, unsigned int lanes); -int sun6i_dphy_power_off(struct sun6i_dphy *dphy); -int sun6i_dphy_exit(struct sun6i_dphy *dphy); - #endif /* _SUN6I_MIPI_DSI_H_ */ diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c index 44a9ba7d8433..30a2eff55687 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -14,10 +14,10 @@ #include <drm/drmP.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> -#include <drm/drm_crtc_helper.h> #include <drm/drm_fb_cma_helper.h> #include <drm/drm_gem_cma_helper.h> #include <drm/drm_plane_helper.h> +#include <drm/drm_probe_helper.h> #include <linux/component.h> #include <linux/dma-mapping.h> diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c index 18534263a05d..a342ec8b131e 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c @@ -16,11 +16,11 @@ #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> -#include <drm/drm_crtc_helper.h> #include <drm/drm_fb_cma_helper.h> #include <drm/drm_gem_cma_helper.h> #include <drm/drm_gem_framebuffer_helper.h> #include <drm/drm_plane_helper.h> +#include <drm/drm_probe_helper.h> #include <drm/drmP.h> #include "sun8i_ui_layer.h" diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c index 87be898f9b7a..8a0616238467 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c @@ -10,11 +10,11 @@ #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> -#include <drm/drm_crtc_helper.h> #include <drm/drm_fb_cma_helper.h> #include <drm/drm_gem_cma_helper.h> #include <drm/drm_gem_framebuffer_helper.h> #include <drm/drm_plane_helper.h> +#include <drm/drm_probe_helper.h> #include <drm/drmP.h> #include "sun8i_vi_layer.h" |