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path: root/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
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Diffstat (limited to 'drivers/gpu/drm/rcar-du/rcar_du_crtc.c')
-rw-r--r--drivers/gpu/drm/rcar-du/rcar_du_crtc.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index c89751c26f9c..2f8776c1ec8f 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -261,6 +261,14 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr);
escr = ESCR_DCLKSEL_DCLKIN | div;
+ } else if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) {
+ /*
+ * Use the LVDS PLL output as the dot clock when outputting to
+ * the LVDS encoder on an SoC that supports this clock routing
+ * option. We use the clock directly in that case, without any
+ * additional divider.
+ */
+ escr = ESCR_DCLKSEL_DCLKIN;
} else {
struct du_clk_params params = { .diff = (unsigned long)-1 };