diff options
Diffstat (limited to 'drivers/gpu/drm/msm/adreno/a4xx.xml.h')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a4xx.xml.h | 420 |
1 files changed, 288 insertions, 132 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a4xx.xml.h b/drivers/gpu/drm/msm/adreno/a4xx.xml.h index 5a24c416d2dd..755723fd8ba5 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a4xx.xml.h @@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15053 bytes, from 2014-11-09 15:45:47) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 63169 bytes, from 2014-11-13 22:44:18) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 49097 bytes, from 2014-11-14 15:38:00) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15085 bytes, from 2014-12-20 21:49:41) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 64344 bytes, from 2014-12-12 20:22:26) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 51069 bytes, from 2014-12-21 15:51:54) Copyright (C) 2013-2014 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) @@ -63,72 +63,82 @@ enum a4xx_rb_blend_opcode { }; enum a4xx_vtx_fmt { - VFMT4_FLOAT_32 = 1, - VFMT4_FLOAT_32_32 = 2, - VFMT4_FLOAT_32_32_32 = 3, - VFMT4_FLOAT_32_32_32_32 = 4, - VFMT4_FLOAT_16 = 5, - VFMT4_FLOAT_16_16 = 6, - VFMT4_FLOAT_16_16_16 = 7, - VFMT4_FLOAT_16_16_16_16 = 8, - VFMT4_FIXED_32 = 9, - VFMT4_FIXED_32_32 = 10, - VFMT4_FIXED_32_32_32 = 11, - VFMT4_FIXED_32_32_32_32 = 12, - VFMT4_SHORT_16 = 16, - VFMT4_SHORT_16_16 = 17, - VFMT4_SHORT_16_16_16 = 18, - VFMT4_SHORT_16_16_16_16 = 19, - VFMT4_USHORT_16 = 20, - VFMT4_USHORT_16_16 = 21, - VFMT4_USHORT_16_16_16 = 22, - VFMT4_USHORT_16_16_16_16 = 23, - VFMT4_NORM_SHORT_16 = 24, - VFMT4_NORM_SHORT_16_16 = 25, - VFMT4_NORM_SHORT_16_16_16 = 26, - VFMT4_NORM_SHORT_16_16_16_16 = 27, - VFMT4_NORM_USHORT_16 = 28, - VFMT4_NORM_USHORT_16_16 = 29, - VFMT4_NORM_USHORT_16_16_16 = 30, - VFMT4_NORM_USHORT_16_16_16_16 = 31, - VFMT4_UBYTE_8 = 40, - VFMT4_UBYTE_8_8 = 41, - VFMT4_UBYTE_8_8_8 = 42, - VFMT4_UBYTE_8_8_8_8 = 43, - VFMT4_NORM_UBYTE_8 = 44, - VFMT4_NORM_UBYTE_8_8 = 45, - VFMT4_NORM_UBYTE_8_8_8 = 46, - VFMT4_NORM_UBYTE_8_8_8_8 = 47, - VFMT4_BYTE_8 = 48, - VFMT4_BYTE_8_8 = 49, - VFMT4_BYTE_8_8_8 = 50, - VFMT4_BYTE_8_8_8_8 = 51, - VFMT4_NORM_BYTE_8 = 52, - VFMT4_NORM_BYTE_8_8 = 53, - VFMT4_NORM_BYTE_8_8_8 = 54, - VFMT4_NORM_BYTE_8_8_8_8 = 55, - VFMT4_UINT_10_10_10_2 = 60, - VFMT4_NORM_UINT_10_10_10_2 = 61, - VFMT4_INT_10_10_10_2 = 62, - VFMT4_NORM_INT_10_10_10_2 = 63, + VFMT4_32_FLOAT = 1, + VFMT4_32_32_FLOAT = 2, + VFMT4_32_32_32_FLOAT = 3, + VFMT4_32_32_32_32_FLOAT = 4, + VFMT4_16_FLOAT = 5, + VFMT4_16_16_FLOAT = 6, + VFMT4_16_16_16_FLOAT = 7, + VFMT4_16_16_16_16_FLOAT = 8, + VFMT4_32_FIXED = 9, + VFMT4_32_32_FIXED = 10, + VFMT4_32_32_32_FIXED = 11, + VFMT4_32_32_32_32_FIXED = 12, + VFMT4_16_SINT = 16, + VFMT4_16_16_SINT = 17, + VFMT4_16_16_16_SINT = 18, + VFMT4_16_16_16_16_SINT = 19, + VFMT4_16_UINT = 20, + VFMT4_16_16_UINT = 21, + VFMT4_16_16_16_UINT = 22, + VFMT4_16_16_16_16_UINT = 23, + VFMT4_16_SNORM = 24, + VFMT4_16_16_SNORM = 25, + VFMT4_16_16_16_SNORM = 26, + VFMT4_16_16_16_16_SNORM = 27, + VFMT4_16_UNORM = 28, + VFMT4_16_16_UNORM = 29, + VFMT4_16_16_16_UNORM = 30, + VFMT4_16_16_16_16_UNORM = 31, + VFMT4_32_32_SINT = 37, + VFMT4_8_UINT = 40, + VFMT4_8_8_UINT = 41, + VFMT4_8_8_8_UINT = 42, + VFMT4_8_8_8_8_UINT = 43, + VFMT4_8_UNORM = 44, + VFMT4_8_8_UNORM = 45, + VFMT4_8_8_8_UNORM = 46, + VFMT4_8_8_8_8_UNORM = 47, + VFMT4_8_SINT = 48, + VFMT4_8_8_SINT = 49, + VFMT4_8_8_8_SINT = 50, + VFMT4_8_8_8_8_SINT = 51, + VFMT4_8_SNORM = 52, + VFMT4_8_8_SNORM = 53, + VFMT4_8_8_8_SNORM = 54, + VFMT4_8_8_8_8_SNORM = 55, + VFMT4_10_10_10_2_UINT = 60, + VFMT4_10_10_10_2_UNORM = 61, + VFMT4_10_10_10_2_SINT = 62, + VFMT4_10_10_10_2_SNORM = 63, }; enum a4xx_tex_fmt { - TFMT4_NORM_USHORT_565 = 11, - TFMT4_NORM_USHORT_5551 = 10, - TFMT4_NORM_USHORT_4444 = 8, - TFMT4_NORM_UINT_X8Z24 = 71, - TFMT4_NORM_UINT_2_10_10_10 = 33, - TFMT4_NORM_UINT_A8 = 3, - TFMT4_NORM_UINT_L8_A8 = 13, - TFMT4_NORM_UINT_8 = 4, - TFMT4_NORM_UINT_8_8_8_8 = 28, - TFMT4_FLOAT_16 = 20, - TFMT4_FLOAT_16_16 = 40, - TFMT4_FLOAT_16_16_16_16 = 53, - TFMT4_FLOAT_32 = 43, - TFMT4_FLOAT_32_32 = 56, - TFMT4_FLOAT_32_32_32_32 = 63, + TFMT4_5_6_5_UNORM = 11, + TFMT4_5_5_5_1_UNORM = 10, + TFMT4_4_4_4_4_UNORM = 8, + TFMT4_X8Z24_UNORM = 71, + TFMT4_10_10_10_2_UNORM = 33, + TFMT4_A8_UNORM = 3, + TFMT4_L8_A8_UNORM = 13, + TFMT4_8_UNORM = 4, + TFMT4_8_8_UNORM = 14, + TFMT4_8_8_8_8_UNORM = 28, + TFMT4_16_FLOAT = 20, + TFMT4_16_16_FLOAT = 40, + TFMT4_16_16_16_16_FLOAT = 53, + TFMT4_32_FLOAT = 43, + TFMT4_32_32_FLOAT = 56, + TFMT4_32_32_32_32_FLOAT = 63, +}; + +enum a4xx_tex_fetchsize { + TFETCH4_1_BYTE = 0, + TFETCH4_2_BYTE = 1, + TFETCH4_4_BYTE = 2, + TFETCH4_8_BYTE = 3, + TFETCH4_16_BYTE = 4, }; enum a4xx_depth_format { @@ -264,14 +274,19 @@ static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK; } -#define REG_A4XX_RB_MSAA_CONTROL2 0x000020a3 -#define A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__MASK 0x00000380 -#define A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__SHIFT 7 -static inline uint32_t A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES(uint32_t val) +#define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3 +#define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001 +#define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002 +#define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004 +#define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008 +#define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020 +#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380 +#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7 +static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) { - return ((val) << A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__MASK; + return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK; } -#define A4XX_RB_MSAA_CONTROL2_VARYING 0x00001000 +#define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } @@ -362,7 +377,69 @@ static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_r return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; } +#define REG_A4XX_RB_BLEND_RED 0x000020f3 +#define A4XX_RB_BLEND_RED_UINT__MASK 0x00007fff +#define A4XX_RB_BLEND_RED_UINT__SHIFT 0 +static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val) +{ + return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK; +} +#define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 +#define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16 +static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) +{ + return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK; +} + +#define REG_A4XX_RB_BLEND_GREEN 0x000020f4 +#define A4XX_RB_BLEND_GREEN_UINT__MASK 0x00007fff +#define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0 +static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val) +{ + return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK; +} +#define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 +#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 +static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) +{ + return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK; +} + +#define REG_A4XX_RB_BLEND_BLUE 0x000020f5 +#define A4XX_RB_BLEND_BLUE_UINT__MASK 0x00007fff +#define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0 +static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val) +{ + return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK; +} +#define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 +#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 +static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) +{ + return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK; +} + +#define REG_A4XX_RB_BLEND_ALPHA 0x000020f6 +#define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x00007fff +#define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0 +static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) +{ + return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK; +} +#define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 +#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 +static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) +{ + return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK; +} + #define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8 +#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff +#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 +static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) +{ + return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; +} #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 @@ -372,7 +449,7 @@ static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare } #define REG_A4XX_RB_FS_OUTPUT 0x000020f9 -#define A4XX_RB_FS_OUTPUT_ENABLE_COLOR_PIPE 0x00000001 +#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND 0x00000001 #define A4XX_RB_FS_OUTPUT_FAST_CLEAR 0x00000100 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16 @@ -416,11 +493,11 @@ static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) } #define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd -#define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xfffffff0 -#define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 4 +#define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0 +#define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) { - return ((val >> 4) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK; + return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK; } #define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe @@ -508,7 +585,7 @@ static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) #define A4XX_RB_DEPTH_PITCH__SHIFT 0 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) { - return ((val >> 4) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK; + return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK; } #define REG_A4XX_RB_DEPTH_PITCH2 0x00002105 @@ -516,7 +593,7 @@ static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) #define A4XX_RB_DEPTH_PITCH2__SHIFT 0 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val) { - return ((val >> 4) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK; + return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK; } #define REG_A4XX_RB_STENCIL_CONTROL 0x00002106 @@ -630,7 +707,11 @@ static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val) return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK; } -#define REG_A4XX_RB_VPORT_Z_CLAMP_MAX_15 0x0000213f +static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } + +static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } + +static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } #define REG_A4XX_RBBM_HW_VERSION 0x00000000 @@ -1121,7 +1202,9 @@ static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) { return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; } +#define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000 #define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000 +#define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000 #define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 @@ -1384,6 +1467,12 @@ static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val) #define REG_A4XX_VFD_CONTROL_2 0x00002202 #define REG_A4XX_VFD_CONTROL_3 0x00002203 +#define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00 +#define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8 +static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val) +{ + return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK; +} #define REG_A4XX_VFD_CONTROL_4 0x00002204 @@ -1405,12 +1494,7 @@ static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; } #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000 -#define A4XX_VFD_FETCH_INSTR_0_STEPRATE__MASK 0xff000000 -#define A4XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT 24 -static inline uint32_t A4XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) -{ - return ((val) << A4XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_STEPRATE__MASK; -} +#define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; } @@ -1423,6 +1507,12 @@ static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val) } static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; } +#define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff +#define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0 +static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val) +{ + return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK; +} static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; } @@ -1446,6 +1536,7 @@ static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val) { return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK; } +#define A4XX_VFD_DECODE_INSTR_INT 0x00100000 #define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) @@ -1585,7 +1676,47 @@ static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; } -#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f +#define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077 +#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003 +#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0 +static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val) +{ + return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK; +} + +#define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078 +#define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 +#define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 +#define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 +#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 +#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 +static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) +{ + return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; +} +#define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 +#define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000 + +#define REG_A4XX_GRAS_SC_CONTROL 0x0000207b +#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c +#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2 +static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) +{ + return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; +} +#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380 +#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7 +static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val) +{ + return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; +} +#define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800 +#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 +#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 +static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) +{ + return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; +} #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 @@ -1647,46 +1778,34 @@ static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; } -#define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077 -#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003 -#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0 -static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val) +#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e +#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000 +#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff +#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0 +static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val) { - return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK; + return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK; } - -#define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078 -#define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 -#define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 -#define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 -#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 -#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 -static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) +#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000 +#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16 +static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val) { - return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; + return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK; } -#define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 -#define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000 -#define REG_A4XX_GRAS_SC_CONTROL 0x0000207b -#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c -#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2 -static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) -{ - return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; -} -#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380 -#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7 -static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val) +#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f +#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000 +#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff +#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0 +static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val) { - return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; + return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK; } -#define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800 -#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 -#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 -static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) +#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000 +#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16 +static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val) { - return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; + return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK; } #define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80 @@ -1742,6 +1861,12 @@ static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize } #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 +#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000 +#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16 +static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val) +{ + return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK; +} #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORD 0x02000000 #define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2 @@ -1751,6 +1876,12 @@ static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) { return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; } +#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc +#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2 +static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) +{ + return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; +} #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3 #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff @@ -1965,15 +2096,13 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) #define REG_A4XX_UNKNOWN_20F2 0x000020f2 -#define REG_A4XX_UNKNOWN_20F3 0x000020f3 - -#define REG_A4XX_UNKNOWN_20F4 0x000020f4 - -#define REG_A4XX_UNKNOWN_20F5 0x000020f5 - -#define REG_A4XX_UNKNOWN_20F6 0x000020f6 - #define REG_A4XX_UNKNOWN_20F7 0x000020f7 +#define A4XX_UNKNOWN_20F7__MASK 0xffffffff +#define A4XX_UNKNOWN_20F7__SHIFT 0 +static inline uint32_t A4XX_UNKNOWN_20F7(float val) +{ + return ((fui(val)) << A4XX_UNKNOWN_20F7__SHIFT) & A4XX_UNKNOWN_20F7__MASK; +} #define REG_A4XX_UNKNOWN_2152 0x00002152 @@ -2000,6 +2129,7 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) #define REG_A4XX_UNKNOWN_23A0 0x000023a0 #define REG_A4XX_TEX_SAMP_0 0x00000000 +#define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 #define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1 static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val) @@ -2038,17 +2168,19 @@ static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val { return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK; } +#define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 +#define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val) { - return ((((uint32_t)(val * 64.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK; + return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK; } #define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val) { - return ((((uint32_t)(val * 64.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK; + return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK; } #define REG_A4XX_TEX_CONST_0 0x00000000 @@ -2077,6 +2209,12 @@ static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val) { return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK; } +#define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 +#define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16 +static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val) +{ + return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK; +} #define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000 #define A4XX_TEX_CONST_0_FMT__SHIFT 22 static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val) @@ -2105,6 +2243,12 @@ static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val) } #define REG_A4XX_TEX_CONST_2 0x00000002 +#define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f +#define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0 +static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val) +{ + return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK; +} #define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00 #define A4XX_TEX_CONST_2_PITCH__SHIFT 9 static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val) @@ -2119,19 +2263,31 @@ static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) } #define REG_A4XX_TEX_CONST_3 0x00000003 -#define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x0000000f +#define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) { return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK; } +#define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000 +#define A4XX_TEX_CONST_3_DEPTH__SHIFT 18 +static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val) +{ + return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK; +} #define REG_A4XX_TEX_CONST_4 0x00000004 -#define A4XX_TEX_CONST_4_BASE__MASK 0xffffffff -#define A4XX_TEX_CONST_4_BASE__SHIFT 0 +#define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f +#define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0 +static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val) +{ + return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK; +} +#define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0 +#define A4XX_TEX_CONST_4_BASE__SHIFT 5 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) { - return ((val) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK; + return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK; } #define REG_A4XX_TEX_CONST_5 0x00000005 |