diff options
Diffstat (limited to 'drivers/gpu/drm/i915/display')
159 files changed, 8335 insertions, 2829 deletions
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index b39aae9165df..87f6b9602b16 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -7,15 +7,18 @@ #include <linux/string_helpers.h> +#include <drm/drm_print.h> + #include "g4x_dp.h" -#include "i915_drv.h" #include "i915_reg.h" +#include "i915_utils.h" #include "intel_audio.h" #include "intel_backlight.h" #include "intel_connector.h" #include "intel_crtc.h" #include "intel_de.h" #include "intel_display_power.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dp_aux.h" @@ -28,7 +31,6 @@ #include "intel_hotplug.h" #include "intel_pch_display.h" #include "intel_pps.h" -#include "vlv_sideband.h" static const struct dpll g4x_dpll[] = { { .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, }, @@ -60,14 +62,13 @@ static void g4x_dp_set_clock(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); const struct dpll *divisor = NULL; int i, count = 0; if (display->platform.g4x) { divisor = g4x_dpll; count = ARRAY_SIZE(g4x_dpll); - } else if (HAS_PCH_SPLIT(dev_priv)) { + } else if (HAS_PCH_SPLIT(display)) { divisor = pch_dpll; count = ARRAY_SIZE(pch_dpll); } else if (display->platform.cherryview) { @@ -93,7 +94,6 @@ static void intel_dp_prepare(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); enum port port = encoder->port; struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); @@ -141,7 +141,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder, intel_dp->DP |= DP_ENHANCED_FRAMING; intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe); - } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { + } else if (HAS_PCH_CPT(display) && port != PORT_A) { intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; intel_de_rmw(display, TRANS_DP_CTL(crtc->pipe), @@ -183,7 +183,7 @@ static void assert_dp_port(struct intel_dp *intel_dp, bool state) static void assert_edp_pll(struct intel_display *display, bool state) { - bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE; + bool cur_state = intel_de_read(display, DP_A) & EDP_PLL_ENABLE; INTEL_DISPLAY_STATE_WARN(display, cur_state != state, "eDP PLL state assertion failure (expected %s, current %s)\n", @@ -205,12 +205,12 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp, drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n", pipe_config->port_clock); - intel_dp->DP &= ~DP_PLL_FREQ_MASK; + intel_dp->DP &= ~EDP_PLL_FREQ_MASK; if (pipe_config->port_clock == 162000) - intel_dp->DP |= DP_PLL_FREQ_162MHZ; + intel_dp->DP |= EDP_PLL_FREQ_162MHZ; else - intel_dp->DP |= DP_PLL_FREQ_270MHZ; + intel_dp->DP |= EDP_PLL_FREQ_270MHZ; intel_de_write(display, DP_A, intel_dp->DP); intel_de_posting_read(display, DP_A); @@ -225,7 +225,7 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp, if (display->platform.ironlake) intel_wait_for_vblank_if_active(display, !crtc->pipe); - intel_dp->DP |= DP_PLL_ENABLE; + intel_dp->DP |= EDP_PLL_ENABLE; intel_de_write(display, DP_A, intel_dp->DP); intel_de_posting_read(display, DP_A); @@ -243,7 +243,7 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp, drm_dbg_kms(display->drm, "disabling eDP PLL\n"); - intel_dp->DP &= ~DP_PLL_ENABLE; + intel_dp->DP &= ~EDP_PLL_ENABLE; intel_de_write(display, DP_A, intel_dp->DP); intel_de_posting_read(display, DP_A); @@ -277,7 +277,6 @@ bool g4x_dp_port_enabled(struct intel_display *display, i915_reg_t dp_reg, enum port port, enum pipe *pipe) { - struct drm_i915_private *dev_priv = to_i915(display->drm); bool ret; u32 val; @@ -287,13 +286,13 @@ bool g4x_dp_port_enabled(struct intel_display *display, /* asserts want to know the pipe even if the port is disabled */ if (display->platform.ivybridge && port == PORT_A) - *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB; - else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) + *pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_IVB, val); + else if (HAS_PCH_CPT(display) && port != PORT_A) ret &= cpt_dp_port_selected(display, port, pipe); else if (display->platform.cherryview) - *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV; + *pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_CHV, val); else - *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT; + *pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK, val); return ret; } @@ -338,7 +337,6 @@ static void intel_dp_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); u32 tmp, flags = 0; enum port port = encoder->port; @@ -353,7 +351,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder, pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; - if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { + if (HAS_PCH_CPT(display) && port != PORT_A) { u32 trans_dp = intel_de_read(display, TRANS_DP_CTL(crtc->pipe)); @@ -389,13 +387,12 @@ static void intel_dp_get_config(struct intel_encoder *encoder, if (display->platform.g4x && tmp & DP_COLOR_RANGE_16_235) pipe_config->limited_color_range = true; - pipe_config->lane_count = - ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; + pipe_config->lane_count = REG_FIELD_GET(DP_PORT_WIDTH_MASK, tmp) + 1; g4x_dp_get_m_n(pipe_config); if (port == PORT_A) { - if ((intel_de_read(display, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) + if ((intel_de_read(display, DP_A) & EDP_PLL_FREQ_MASK) == EDP_PLL_FREQ_162MHZ) pipe_config->port_clock = 162000; else pipe_config->port_clock = 270000; @@ -416,7 +413,6 @@ intel_dp_link_down(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); enum port port = encoder->port; @@ -429,7 +425,7 @@ intel_dp_link_down(struct intel_encoder *encoder, drm_dbg_kms(display->drm, "\n"); if ((display->platform.ivybridge && port == PORT_A) || - (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { + (HAS_PCH_CPT(display) && port != PORT_A)) { intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT; intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; } else { @@ -448,7 +444,7 @@ intel_dp_link_down(struct intel_encoder *encoder, * to transcoder A after disabling it to allow the * matching HDMI port to be enabled on transcoder A. */ - if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { + if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B && port != PORT_A) { /* * We get CPU/PCH FIFO underruns on the other pipe when * doing the workaround. Sweep them under the rug. @@ -581,16 +577,10 @@ static void chv_post_disable_dp(struct intel_atomic_state *state, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - intel_dp_link_down(encoder, old_crtc_state); - vlv_dpio_get(dev_priv); - /* Assert data lane reset */ chv_data_lane_soft_reset(encoder, old_crtc_state, true); - - vlv_dpio_put(dev_priv); } static void @@ -1223,10 +1213,10 @@ static int g4x_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); int ret; - if (HAS_PCH_SPLIT(i915) && encoder->port != PORT_A) + if (HAS_PCH_SPLIT(display) && encoder->port != PORT_A) crtc_state->has_pch_encoder = true; ret = intel_dp_compute_config(encoder, crtc_state, conn_state); @@ -1279,7 +1269,6 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = { bool g4x_dp_init(struct intel_display *display, i915_reg_t output_reg, enum port port) { - struct drm_i915_private *dev_priv = to_i915(display->drm); const struct intel_bios_encoder_data *devdata; struct intel_digital_port *dig_port; struct intel_encoder *intel_encoder; @@ -1353,7 +1342,7 @@ bool g4x_dp_init(struct intel_display *display, intel_encoder->audio_disable = g4x_dp_audio_disable; if ((display->platform.ivybridge && port == PORT_A) || - (HAS_PCH_CPT(dev_priv) && port != PORT_A)) + (HAS_PCH_CPT(display) && port != PORT_A)) dig_port->dp.set_link_train = cpt_set_link_train; else dig_port->dp.set_link_train = g4x_set_link_train; @@ -1370,7 +1359,7 @@ bool g4x_dp_init(struct intel_display *display, intel_encoder->set_signal_levels = g4x_set_signal_levels; if (display->platform.valleyview || display->platform.cherryview || - (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) { + (HAS_PCH_SPLIT(display) && port != PORT_A)) { dig_port->dp.preemph_max = intel_dp_preemph_max_3; dig_port->dp.voltage_max = intel_dp_voltage_max_3; } else { diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c index 3dc2c59a3df0..2610f5702fb9 100644 --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c @@ -5,8 +5,9 @@ * HDMI support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code). */ +#include <drm/drm_print.h> + #include "g4x_hdmi.h" -#include "i915_drv.h" #include "i915_reg.h" #include "intel_atomic.h" #include "intel_audio.h" @@ -14,6 +15,7 @@ #include "intel_crtc.h" #include "intel_de.h" #include "intel_display_power.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dp_aux.h" #include "intel_dpio_phy.h" @@ -22,13 +24,11 @@ #include "intel_hdmi.h" #include "intel_hotplug.h" #include "intel_sdvo.h" -#include "vlv_sideband.h" static void intel_hdmi_prepare(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; @@ -37,7 +37,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder, intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); hdmi_val = SDVO_ENCODING_HDMI; - if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) + if (!HAS_PCH_SPLIT(display) && crtc_state->limited_color_range) hdmi_val |= HDMI_COLOR_RANGE_16_235; if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; @@ -52,7 +52,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder, if (crtc_state->has_hdmi_sink) hdmi_val |= HDMI_MODE_SELECT_HDMI; - if (HAS_PCH_CPT(dev_priv)) + if (HAS_PCH_CPT(display)) hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); else if (display->platform.cherryview) hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); @@ -134,9 +134,8 @@ static int g4x_hdmi_compute_config(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(encoder->base.dev); - if (HAS_PCH_SPLIT(i915)) { + if (HAS_PCH_SPLIT(display)) { crtc_state->has_pch_encoder = true; if (!intel_fdi_compute_pipe_bpp(crtc_state)) return -EINVAL; @@ -155,7 +154,6 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); u32 tmp, flags = 0; int dotclock; @@ -186,7 +184,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, if (tmp & HDMI_AUDIO_ENABLE) pipe_config->has_audio = true; - if (!HAS_PCH_SPLIT(dev_priv) && + if (!HAS_PCH_SPLIT(display) && tmp & HDMI_COLOR_RANGE_16_235) pipe_config->limited_color_range = true; @@ -383,7 +381,6 @@ static void intel_disable_hdmi(struct intel_atomic_state *state, const struct drm_connector_state *old_conn_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); struct intel_digital_port *dig_port = hdmi_to_dig_port(intel_hdmi); @@ -401,7 +398,7 @@ static void intel_disable_hdmi(struct intel_atomic_state *state, * to transcoder A after disabling it to allow the * matching DP port to be enabled on transcoder A. */ - if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { + if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B) { /* * We get CPU/PCH FIFO underruns on the other pipe when * doing the workaround. Sweep them under the rug. @@ -539,15 +536,8 @@ static void chv_hdmi_post_disable(struct intel_atomic_state *state, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { - struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(display->drm); - - vlv_dpio_get(dev_priv); - /* Assert data lane reset */ chv_data_lane_soft_reset(encoder, old_crtc_state, true); - - vlv_dpio_put(dev_priv); } static void chv_hdmi_pre_enable(struct intel_atomic_state *state, @@ -682,7 +672,6 @@ static bool assert_hdmi_port_valid(struct intel_display *display, enum port port bool g4x_hdmi_init(struct intel_display *display, i915_reg_t hdmi_reg, enum port port) { - struct drm_i915_private *dev_priv = to_i915(display->drm); const struct intel_bios_encoder_data *devdata; struct intel_digital_port *dig_port; struct intel_encoder *intel_encoder; @@ -724,7 +713,7 @@ bool g4x_hdmi_init(struct intel_display *display, intel_encoder->hotplug = intel_hdmi_hotplug; intel_encoder->compute_config = g4x_hdmi_compute_config; - if (HAS_PCH_SPLIT(dev_priv)) { + if (HAS_PCH_SPLIT(display)) { intel_encoder->disable = pch_disable_hdmi; intel_encoder->post_disable = pch_post_disable_hdmi; } else { @@ -745,9 +734,9 @@ bool g4x_hdmi_init(struct intel_display *display, intel_encoder->post_disable = vlv_hdmi_post_disable; } else { intel_encoder->pre_enable = intel_hdmi_pre_enable; - if (HAS_PCH_CPT(dev_priv)) + if (HAS_PCH_CPT(display)) intel_encoder->enable = cpt_enable_hdmi; - else if (HAS_PCH_IBX(dev_priv)) + else if (HAS_PCH_IBX(display)) intel_encoder->enable = ibx_enable_hdmi; else intel_encoder->enable = g4x_enable_hdmi; diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c index 4307e2ed03d9..0d33782f11be 100644 --- a/drivers/gpu/drm/i915/display/hsw_ips.c +++ b/drivers/gpu/drm/i915/display/hsw_ips.c @@ -10,6 +10,7 @@ #include "i915_reg.h" #include "intel_color_regs.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_rpm.h" #include "intel_display_types.h" #include "intel_pcode.h" diff --git a/drivers/gpu/drm/i915/display/i9xx_display_sr.c b/drivers/gpu/drm/i915/display/i9xx_display_sr.c index 32abe9743014..935419441709 100644 --- a/drivers/gpu/drm/i915/display/i9xx_display_sr.c +++ b/drivers/gpu/drm/i915/display/i9xx_display_sr.c @@ -5,10 +5,10 @@ #include <drm/drm_device.h> -#include "i915_reg.h" #include "i9xx_display_sr.h" #include "i9xx_wm_regs.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_gmbus.h" #include "intel_pci_config.h" diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 5e8344fdfc28..8f15333a4b07 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -2,20 +2,23 @@ /* * Copyright © 2020 Intel Corporation */ + #include <linux/kernel.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_blend.h> #include <drm/drm_fourcc.h> +#include <drm/drm_print.h> -#include "i915_drv.h" #include "i915_reg.h" +#include "i915_utils.h" #include "i9xx_plane.h" #include "i9xx_plane_regs.h" #include "intel_atomic.h" #include "intel_atomic_plane.h" #include "intel_de.h" #include "intel_display_irq.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_fb.h" #include "intel_fbc.h" @@ -631,92 +634,84 @@ static void bdw_primary_enable_flip_done(struct intel_plane *plane) { struct intel_display *display = to_intel_display(plane); - struct drm_i915_private *i915 = to_i915(plane->base.dev); enum pipe pipe = plane->pipe; - spin_lock_irq(&i915->irq_lock); + spin_lock_irq(&display->irq.lock); bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE); - spin_unlock_irq(&i915->irq_lock); + spin_unlock_irq(&display->irq.lock); } static void bdw_primary_disable_flip_done(struct intel_plane *plane) { struct intel_display *display = to_intel_display(plane); - struct drm_i915_private *i915 = to_i915(plane->base.dev); enum pipe pipe = plane->pipe; - spin_lock_irq(&i915->irq_lock); + spin_lock_irq(&display->irq.lock); bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE); - spin_unlock_irq(&i915->irq_lock); + spin_unlock_irq(&display->irq.lock); } static void ivb_primary_enable_flip_done(struct intel_plane *plane) { struct intel_display *display = to_intel_display(plane); - struct drm_i915_private *i915 = to_i915(plane->base.dev); - spin_lock_irq(&i915->irq_lock); + spin_lock_irq(&display->irq.lock); ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)); - spin_unlock_irq(&i915->irq_lock); + spin_unlock_irq(&display->irq.lock); } static void ivb_primary_disable_flip_done(struct intel_plane *plane) { struct intel_display *display = to_intel_display(plane); - struct drm_i915_private *i915 = to_i915(plane->base.dev); - spin_lock_irq(&i915->irq_lock); + spin_lock_irq(&display->irq.lock); ilk_disable_display_irq(display, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)); - spin_unlock_irq(&i915->irq_lock); + spin_unlock_irq(&display->irq.lock); } static void ilk_primary_enable_flip_done(struct intel_plane *plane) { struct intel_display *display = to_intel_display(plane); - struct drm_i915_private *i915 = to_i915(plane->base.dev); - spin_lock_irq(&i915->irq_lock); + spin_lock_irq(&display->irq.lock); ilk_enable_display_irq(display, DE_PLANE_FLIP_DONE(plane->i9xx_plane)); - spin_unlock_irq(&i915->irq_lock); + spin_unlock_irq(&display->irq.lock); } static void ilk_primary_disable_flip_done(struct intel_plane *plane) { struct intel_display *display = to_intel_display(plane); - struct drm_i915_private *i915 = to_i915(plane->base.dev); - spin_lock_irq(&i915->irq_lock); + spin_lock_irq(&display->irq.lock); ilk_disable_display_irq(display, DE_PLANE_FLIP_DONE(plane->i9xx_plane)); - spin_unlock_irq(&i915->irq_lock); + spin_unlock_irq(&display->irq.lock); } static void vlv_primary_enable_flip_done(struct intel_plane *plane) { struct intel_display *display = to_intel_display(plane); - struct drm_i915_private *i915 = to_i915(plane->base.dev); enum pipe pipe = plane->pipe; - spin_lock_irq(&i915->irq_lock); + spin_lock_irq(&display->irq.lock); i915_enable_pipestat(display, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV); - spin_unlock_irq(&i915->irq_lock); + spin_unlock_irq(&display->irq.lock); } static void vlv_primary_disable_flip_done(struct intel_plane *plane) { struct intel_display *display = to_intel_display(plane); - struct drm_i915_private *i915 = to_i915(plane->base.dev); enum pipe pipe = plane->pipe; - spin_lock_irq(&i915->irq_lock); + spin_lock_irq(&display->irq.lock); i915_disable_pipestat(display, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV); - spin_unlock_irq(&i915->irq_lock); + spin_unlock_irq(&display->irq.lock); } static bool i9xx_plane_can_async_flip(u64 modifier) @@ -828,7 +823,7 @@ unsigned int vlv_plane_min_alignment(struct intel_plane *plane, { struct intel_display *display = to_intel_display(plane); - if (intel_plane_can_async_flip(plane, fb->modifier)) + if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier)) return 256 * 1024; /* FIXME undocumented so not sure what's actually needed */ @@ -852,7 +847,7 @@ static unsigned int g4x_primary_min_alignment(struct intel_plane *plane, { struct intel_display *display = to_intel_display(plane); - if (intel_plane_can_async_flip(plane, fb->modifier)) + if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier)) return 256 * 1024; if (intel_scanout_needs_vtd_wa(display)) @@ -897,6 +892,7 @@ static const struct drm_plane_funcs i965_plane_funcs = { .atomic_duplicate_state = intel_plane_duplicate_state, .atomic_destroy_state = intel_plane_destroy_state, .format_mod_supported = i965_plane_format_mod_supported, + .format_mod_supported_async = intel_plane_format_mod_supported_async, }; static const struct drm_plane_funcs i8xx_plane_funcs = { @@ -906,6 +902,7 @@ static const struct drm_plane_funcs i8xx_plane_funcs = { .atomic_duplicate_state = intel_plane_duplicate_state, .atomic_destroy_state = intel_plane_destroy_state, .format_mod_supported = i8xx_plane_format_mod_supported, + .format_mod_supported_async = intel_plane_format_mod_supported_async, }; struct intel_plane * diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c index 40751f1547b7..1f9db5118777 100644 --- a/drivers/gpu/drm/i915/display/i9xx_wm.c +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c @@ -11,6 +11,7 @@ #include "intel_bo.h" #include "intel_de.h" #include "intel_display.h" +#include "intel_display_regs.h" #include "intel_display_trace.h" #include "intel_fb.h" #include "intel_mchbar_regs.h" @@ -107,43 +108,41 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct intel_display *dis static void chv_set_memory_dvfs(struct intel_display *display, bool enable) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 val; - vlv_punit_get(dev_priv); + vlv_punit_get(display->drm); - val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); + val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2); if (enable) val &= ~FORCE_DDR_HIGH_FREQ; else val |= FORCE_DDR_HIGH_FREQ; val &= ~FORCE_DDR_LOW_FREQ; val |= FORCE_DDR_FREQ_REQ_ACK; - vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); + vlv_punit_write(display->drm, PUNIT_REG_DDR_SETUP2, val); - if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & + if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2) & FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) drm_err(display->drm, "timed out waiting for Punit DDR DVFS request\n"); - vlv_punit_put(dev_priv); + vlv_punit_put(display->drm); } static void chv_set_memory_pm5(struct intel_display *display, bool enable) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 val; - vlv_punit_get(dev_priv); + vlv_punit_get(display->drm); - val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); + val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); if (enable) val |= DSP_MAXFIFO_PM5_ENABLE; else val &= ~DSP_MAXFIFO_PM5_ENABLE; - vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); + vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); - vlv_punit_put(dev_priv); + vlv_punit_put(display->drm); } #define FW_WM(value, plane) \ @@ -3900,7 +3899,6 @@ static void g4x_wm_sanitize(struct intel_display *display) static void vlv_wm_get_hw_state(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct vlv_wm_values *wm = &display->wm.vlv; struct intel_crtc *crtc; u32 val; @@ -3911,9 +3909,9 @@ static void vlv_wm_get_hw_state(struct intel_display *display) wm->level = VLV_WM_LEVEL_PM2; if (display->platform.cherryview) { - vlv_punit_get(dev_priv); + vlv_punit_get(display->drm); - val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); + val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); if (val & DSP_MAXFIFO_PM5_ENABLE) wm->level = VLV_WM_LEVEL_PM5; @@ -3926,23 +3924,23 @@ static void vlv_wm_get_hw_state(struct intel_display *display) * HIGH/LOW bits so that we don't actually change * the current state. */ - val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); + val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2); val |= FORCE_DDR_FREQ_REQ_ACK; - vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); + vlv_punit_write(display->drm, PUNIT_REG_DDR_SETUP2, val); - if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & + if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2) & FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) { drm_dbg_kms(display->drm, "Punit not acking DDR DVFS request, " "assuming DDR DVFS is disabled\n"); display->wm.num_levels = VLV_WM_LEVEL_PM5 + 1; } else { - val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); + val = vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2); if ((val & FORCE_DDR_HIGH_FREQ) == 0) wm->level = VLV_WM_LEVEL_DDR_DVFS; } - vlv_punit_put(dev_priv); + vlv_punit_put(display->drm); } for_each_intel_crtc(display->drm, crtc) { @@ -4143,10 +4141,8 @@ static const struct intel_wm_funcs nop_funcs = { void i9xx_wm_init(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - /* For FIFO watermark updates */ - if (HAS_PCH_SPLIT(dev_priv)) { + if (HAS_PCH_SPLIT(display)) { ilk_setup_wm_latency(display); display->funcs.wm = &ilk_wm_funcs; } else if (display->platform.valleyview || display->platform.cherryview) { diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index ca7033251e91..8d9cb73a93a7 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -45,6 +45,7 @@ #include "intel_crtc.h" #include "intel_ddi.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_dsi.h" #include "intel_dsi_vbt.h" #include "intel_panel.h" @@ -192,12 +193,12 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host, else tmp &= ~PAYLOAD_PRESENT; - tmp &= ~VBLANK_FENCE; + tmp &= ~(VBLANK_FENCE | LP_DATA_TRANSFER | PIPELINE_FLUSH); if (enable_lpdt) tmp |= LP_DATA_TRANSFER; else - tmp &= ~LP_DATA_TRANSFER; + tmp |= PIPELINE_FLUSH; tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); @@ -658,7 +659,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, { struct intel_display *display = to_intel_display(encoder); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); - struct intel_shared_dpll *pll = crtc_state->shared_dpll; + struct intel_dpll *pll = crtc_state->intel_dpll; enum phy phy; u32 val; @@ -1276,6 +1277,8 @@ static void gen11_dsi_enable(struct intel_atomic_state *state, intel_backlight_enable(crtc_state, conn_state); intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); + intel_panel_prepare(crtc_state, conn_state); + intel_crtc_vblank_on(crtc_state); } @@ -1409,6 +1412,8 @@ static void gen11_dsi_disable(struct intel_atomic_state *state, { struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); + intel_panel_unprepare(old_conn_state); + /* step1: turn off backlight */ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); intel_backlight_disable(old_conn_state); diff --git a/drivers/gpu/drm/i915/display/icl_dsi_regs.h b/drivers/gpu/drm/i915/display/icl_dsi_regs.h index d4845ac65acc..b601b7632339 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi_regs.h +++ b/drivers/gpu/drm/i915/display/icl_dsi_regs.h @@ -272,6 +272,7 @@ #define PAYLOAD_PRESENT (1 << 31) #define LP_DATA_TRANSFER (1 << 30) #define VBLANK_FENCE (1 << 29) +#define PIPELINE_FLUSH (1 << 28) #define PARAM_WC_MASK (0xffff << 8) #define PARAM_WC_LOWER_SHIFT 8 #define PARAM_WC_UPPER_SHIFT 16 diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index 55f3ae1e68c9..dfdde8e4eabe 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -5,12 +5,15 @@ #include <linux/debugfs.h> +#include <drm/drm_print.h> + #include "intel_alpm.h" #include "intel_crtc.h" #include "intel_de.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dp_aux.h" +#include "intel_psr.h" #include "intel_psr_regs.h" bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp) @@ -23,7 +26,14 @@ bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp) return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP; } -void intel_alpm_init_dpcd(struct intel_dp *intel_dp) +bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) || + (crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp)); +} + +void intel_alpm_init(struct intel_dp *intel_dp) { u8 dpcd; @@ -31,6 +41,7 @@ void intel_alpm_init_dpcd(struct intel_dp *intel_dp) return; intel_dp->alpm_dpcd = dpcd; + mutex_init(&intel_dp->alpm_parameters.lock); } /* @@ -276,6 +287,14 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, int waketime_in_lines, first_sdp_position; int context_latency, guardband; + if (intel_dp->alpm_parameters.lobf_disable_debug) { + drm_dbg_kms(display->drm, "LOBF is disabled by debug flag\n"); + return; + } + + if (intel_dp->alpm_parameters.sink_alpm_error) + return; + if (!intel_dp_is_edp(intel_dp)) return; @@ -288,6 +307,10 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, if (crtc_state->has_psr) return; + if (crtc_state->vrr.vmin != crtc_state->vrr.vmax || + crtc_state->vrr.vmin != crtc_state->vrr.flipline) + return; + if (!(intel_alpm_aux_wake_supported(intel_dp) || intel_alpm_aux_less_wake_supported(intel_dp))) return; @@ -313,58 +336,173 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, { struct intel_display *display = to_intel_display(intel_dp); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - enum port port = dp_to_dig_port(intel_dp)->base.port; u32 alpm_ctl; - if (DISPLAY_VER(display) < 20 || - (!intel_dp->psr.sel_update_enabled && !intel_dp_is_edp(intel_dp))) + if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) && + !crtc_state->has_lobf)) return; + mutex_lock(&intel_dp->alpm_parameters.lock); /* * Panel Replay on eDP is always using ALPM aux less. I.e. no need to * check panel support at this point. */ - if ((intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) || - (crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp))) { + if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) { alpm_ctl = ALPM_CTL_ALPM_ENABLE | ALPM_CTL_ALPM_AUX_LESS_ENABLE | ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS | ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp->alpm_parameters.aux_less_wake_lines); - intel_de_write(display, - PORT_ALPM_CTL(port), - PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE | - PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) | - PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) | - PORT_ALPM_CTL_SILENCE_PERIOD( - intel_dp->alpm_parameters.silence_period_sym_clocks)); - - intel_de_write(display, - PORT_ALPM_LFPS_CTL(port), - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) | - PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION( - intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) | - PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION( - intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) | - PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION( - intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms)); + if (intel_dp->as_sdp_supported) { + u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1; + + if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & + DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP) + pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU; + if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & + DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR)) + pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE; + + intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder), + pr_alpm_ctl); + } + } else { alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE | ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp->alpm_parameters.fast_wake_lines); } - if (crtc_state->has_lobf) + if (crtc_state->has_lobf) { alpm_ctl |= ALPM_CTL_LOBF_ENABLE; + drm_dbg_kms(display->drm, "Link off between frames (LOBF) enabled\n"); + } alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp->alpm_parameters.check_entry_lines); intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl); + mutex_unlock(&intel_dp->alpm_parameters.lock); } void intel_alpm_configure(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { lnl_alpm_configure(intel_dp, crtc_state); + intel_dp->alpm_parameters.transcoder = crtc_state->cpu_transcoder; +} + +void intel_alpm_port_configure(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(intel_dp); + enum port port = dp_to_dig_port(intel_dp)->base.port; + u32 alpm_ctl_val = 0, lfps_ctl_val = 0; + + if (DISPLAY_VER(display) < 20) + return; + + if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) { + alpm_ctl_val = PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE | + PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) | + PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) | + PORT_ALPM_CTL_SILENCE_PERIOD( + intel_dp->alpm_parameters.silence_period_sym_clocks); + lfps_ctl_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) | + PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION( + intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) | + PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION( + intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) | + PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION( + intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms); + } + + intel_de_write(display, PORT_ALPM_CTL(port), alpm_ctl_val); + + intel_de_write(display, PORT_ALPM_LFPS_CTL(port), lfps_ctl_val); +} + +void intel_alpm_pre_plane_update(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(state); + const struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + const struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + struct intel_encoder *encoder; + + if (DISPLAY_VER(display) < 20) + return; + + if (crtc_state->has_lobf || crtc_state->has_lobf == old_crtc_state->has_lobf) + return; + + for_each_intel_encoder_mask(display->drm, encoder, + crtc_state->uapi.encoder_mask) { + struct intel_dp *intel_dp; + + if (!intel_encoder_is_dp(encoder)) + continue; + + intel_dp = enc_to_intel_dp(encoder); + + if (!intel_dp_is_edp(intel_dp)) + continue; + + if (old_crtc_state->has_lobf) { + mutex_lock(&intel_dp->alpm_parameters.lock); + intel_de_write(display, ALPM_CTL(display, cpu_transcoder), 0); + drm_dbg_kms(display->drm, "Link off between frames (LOBF) disabled\n"); + mutex_unlock(&intel_dp->alpm_parameters.lock); + } + } +} + +void intel_alpm_enable_sink(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + u8 val; + + if (!intel_psr_needs_alpm(intel_dp, crtc_state) && !crtc_state->has_lobf) + return; + + val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE; + + if (crtc_state->has_panel_replay || (crtc_state->has_lobf && + intel_alpm_aux_less_wake_supported(intel_dp))) + val |= DP_ALPM_MODE_AUX_LESS; + + drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val); +} + +void intel_alpm_post_plane_update(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(state); + const struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + const struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); + struct intel_encoder *encoder; + + if (crtc_state->has_psr || !crtc_state->has_lobf || + crtc_state->has_lobf == old_crtc_state->has_lobf) + return; + + for_each_intel_encoder_mask(display->drm, encoder, + crtc_state->uapi.encoder_mask) { + struct intel_dp *intel_dp; + + if (!intel_encoder_is_dp(encoder)) + continue; + + intel_dp = enc_to_intel_dp(encoder); + + if (intel_dp_is_edp(intel_dp)) { + intel_alpm_enable_sink(intel_dp, crtc_state); + intel_alpm_configure(intel_dp, crtc_state); + } + } } static int i915_edp_lobf_info_show(struct seq_file *m, void *data) @@ -403,6 +541,32 @@ out: DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_info); +static int +i915_edp_lobf_debug_get(void *data, u64 *val) +{ + struct intel_connector *connector = data; + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); + + *val = intel_dp->alpm_parameters.lobf_disable_debug; + + return 0; +} + +static int +i915_edp_lobf_debug_set(void *data, u64 val) +{ + struct intel_connector *connector = data; + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); + + intel_dp->alpm_parameters.lobf_disable_debug = val; + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_edp_lobf_debug_fops, + i915_edp_lobf_debug_get, i915_edp_lobf_debug_set, + "%llu\n"); + void intel_alpm_lobf_debugfs_add(struct intel_connector *connector) { struct intel_display *display = to_intel_display(connector); @@ -412,6 +576,55 @@ void intel_alpm_lobf_debugfs_add(struct intel_connector *connector) connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) return; + debugfs_create_file("i915_edp_lobf_debug", 0644, root, + connector, &i915_edp_lobf_debug_fops); + debugfs_create_file("i915_edp_lobf_info", 0444, root, connector, &i915_edp_lobf_info_fops); } + +void intel_alpm_disable(struct intel_dp *intel_dp) +{ + struct intel_display *display = to_intel_display(intel_dp); + enum transcoder cpu_transcoder = intel_dp->alpm_parameters.transcoder; + + if (DISPLAY_VER(display) < 20 || !intel_dp->alpm_dpcd) + return; + + mutex_lock(&intel_dp->alpm_parameters.lock); + + intel_de_rmw(display, ALPM_CTL(display, cpu_transcoder), + ALPM_CTL_ALPM_ENABLE | ALPM_CTL_LOBF_ENABLE | + ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0); + + intel_de_rmw(display, + PORT_ALPM_CTL(cpu_transcoder), + PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0); + + drm_dbg_kms(display->drm, "Disabling ALPM\n"); + mutex_unlock(&intel_dp->alpm_parameters.lock); +} + +bool intel_alpm_get_error(struct intel_dp *intel_dp) +{ + struct intel_display *display = to_intel_display(intel_dp); + struct drm_dp_aux *aux = &intel_dp->aux; + u8 val; + int r; + + r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); + if (r != 1) { + drm_err(display->drm, "Error reading ALPM status\n"); + return true; + } + + if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { + drm_dbg_kms(display->drm, "ALPM lock timeout error\n"); + + /* Clearing error */ + drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); + return true; + } + + return false; +} diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h index 8c409b10dce6..a861c20b5d79 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.h +++ b/drivers/gpu/drm/i915/display/intel_alpm.h @@ -12,8 +12,10 @@ struct intel_dp; struct intel_crtc_state; struct drm_connector_state; struct intel_connector; +struct intel_atomic_state; +struct intel_crtc; -void intel_alpm_init_dpcd(struct intel_dp *intel_dp); +void intel_alpm_init(struct intel_dp *intel_dp); bool intel_alpm_compute_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, @@ -21,7 +23,19 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, struct drm_connector_state *conn_state); void intel_alpm_configure(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); +void intel_alpm_enable_sink(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state); +void intel_alpm_pre_plane_update(struct intel_atomic_state *state, + struct intel_crtc *crtc); +void intel_alpm_port_configure(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state); +void intel_alpm_post_plane_update(struct intel_atomic_state *state, + struct intel_crtc *crtc); void intel_alpm_lobf_debugfs_add(struct intel_connector *connector); bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp); bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp); +bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state); +void intel_alpm_disable(struct intel_dp *intel_dp); +bool intel_alpm_get_error(struct intel_dp *intel_dp); #endif diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index e83feca5c9c9..f85edb374c97 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -274,7 +274,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) crtc_state->do_async_flip = false; crtc_state->fb_bits = 0; crtc_state->update_planes = 0; - crtc_state->dsb_color_vblank = NULL; + crtc_state->dsb_color = NULL; crtc_state->dsb_commit = NULL; crtc_state->use_dsb = false; @@ -310,7 +310,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc, { struct intel_crtc_state *crtc_state = to_intel_crtc_state(state); - drm_WARN_ON(crtc->dev, crtc_state->dsb_color_vblank); + drm_WARN_ON(crtc->dev, crtc_state->dsb_color); drm_WARN_ON(crtc->dev, crtc_state->dsb_commit); __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 7276179df878..15ede7678636 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -42,7 +42,6 @@ #include <drm/drm_gem_atomic_helper.h> #include "gem/i915_gem_object.h" -#include "i915_config.h" #include "i915_scheduler_types.h" #include "i915_vma.h" #include "i9xx_plane_regs.h" @@ -174,11 +173,27 @@ bool intel_plane_needs_physical(struct intel_plane *plane) DISPLAY_INFO(display)->cursor_needs_physical; } -bool intel_plane_can_async_flip(struct intel_plane *plane, u64 modifier) +bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format, + u64 modifier) { + if (intel_format_info_is_yuv_semiplanar(drm_format_info(format), modifier) || + format == DRM_FORMAT_C8) + return false; + return plane->can_async_flip && plane->can_async_flip(modifier); } +bool intel_plane_format_mod_supported_async(struct drm_plane *plane, + u32 format, + u64 modifier) +{ + if (!plane->funcs->format_mod_supported(plane, format, modifier)) + return false; + + return intel_plane_can_async_flip(to_intel_plane(plane), + format, modifier); +} + unsigned int intel_adjusted_rate(const struct drm_rect *src, const struct drm_rect *dst, unsigned int rate) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h index 6efac923dcbc..317320c32285 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h @@ -21,7 +21,8 @@ enum plane_id; struct intel_plane * intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id); -bool intel_plane_can_async_flip(struct intel_plane *plane, u64 modifier); +bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format, + u64 modifier); unsigned int intel_adjusted_rate(const struct drm_rect *src, const struct drm_rect *dst, unsigned int rate); @@ -89,5 +90,8 @@ int intel_atomic_add_affected_planes(struct intel_atomic_state *state, int intel_atomic_check_planes(struct intel_atomic_state *state); u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state); +bool intel_plane_format_mod_supported_async(struct drm_plane *plane, + u32 format, + u64 modifier); #endif /* __INTEL_ATOMIC_PLANE_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index ea935a5d94c8..55af3a553c58 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -27,9 +27,9 @@ #include <drm/drm_edid.h> #include <drm/drm_eld.h> #include <drm/drm_fixed.h> +#include <drm/drm_print.h> #include <drm/intel/i915_component.h> -#include "i915_drv.h" #include "intel_atomic.h" #include "intel_audio.h" #include "intel_audio_regs.h" @@ -397,6 +397,19 @@ hsw_audio_config_update(struct intel_encoder *encoder, hsw_hdmi_audio_config_update(encoder, crtc_state); } +static void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state, + bool enable) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder trans = crtc_state->cpu_transcoder; + + if (!HAS_DP20(display)) + return; + + intel_de_rmw(display, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT, + enable && crtc_state->sdp_split_enable ? AUD_ENABLE_SDP_SPLIT : 0); +} + static void hsw_audio_codec_disable(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) @@ -430,6 +443,8 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder, if (needs_wa_14020863754(display)) intel_de_rmw(display, AUD_CHICKENBIT_REG3, DACBE_DISABLE_MIN_HBLANK_FIX, 0); + intel_audio_sdp_split_update(old_crtc_state, false); + mutex_unlock(&display->audio.mutex); } @@ -555,6 +570,8 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) enable_audio_dsc_wa(encoder, crtc_state); + intel_audio_sdp_split_update(crtc_state, true); + if (needs_wa_14020863754(display)) intel_de_rmw(display, AUD_CHICKENBIT_REG3, 0, DACBE_DISABLE_MIN_HBLANK_FIX); @@ -587,19 +604,17 @@ static void ibx_audio_regs_init(struct intel_display *display, enum pipe pipe, struct ibx_audio_regs *regs) { - struct drm_i915_private *i915 = to_i915(display->drm); - if (display->platform.valleyview || display->platform.cherryview) { regs->hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); regs->aud_config = VLV_AUD_CFG(pipe); regs->aud_cntl_st = VLV_AUD_CNTL_ST(pipe); regs->aud_cntrl_st2 = VLV_AUD_CNTL_ST2; - } else if (HAS_PCH_CPT(i915)) { + } else if (HAS_PCH_CPT(display)) { regs->hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); regs->aud_config = CPT_AUD_CFG(pipe); regs->aud_cntl_st = CPT_AUD_CNTL_ST(pipe); regs->aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; - } else if (HAS_PCH_IBX(i915)) { + } else if (HAS_PCH_IBX(display)) { regs->hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); regs->aud_config = IBX_AUD_CFG(pipe); regs->aud_cntl_st = IBX_AUD_CNTL_ST(pipe); @@ -683,16 +698,6 @@ static void ibx_audio_codec_enable(struct intel_encoder *encoder, mutex_unlock(&display->audio.mutex); } -void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state) -{ - struct intel_display *display = to_intel_display(crtc_state); - enum transcoder trans = crtc_state->cpu_transcoder; - - if (HAS_DP20(display)) - intel_de_rmw(display, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT, - crtc_state->sdp_split_enable ? AUD_ENABLE_SDP_SPLIT : 0); -} - bool intel_audio_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -889,12 +894,10 @@ static const struct intel_audio_funcs hsw_audio_funcs = { */ void intel_audio_hooks_init(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - if (display->platform.g4x) display->funcs.audio = &g4x_audio_funcs; else if (display->platform.valleyview || display->platform.cherryview || - HAS_PCH_CPT(i915) || HAS_PCH_IBX(i915)) + HAS_PCH_CPT(display) || HAS_PCH_IBX(display)) display->funcs.audio = &ibx_audio_funcs; else if (display->platform.haswell || DISPLAY_VER(display) >= 8) display->funcs.audio = &hsw_audio_funcs; diff --git a/drivers/gpu/drm/i915/display/intel_audio.h b/drivers/gpu/drm/i915/display/intel_audio.h index ad49eefa7182..42cf886f3d24 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.h +++ b/drivers/gpu/drm/i915/display/intel_audio.h @@ -31,6 +31,5 @@ int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state); void intel_audio_init(struct intel_display *display); void intel_audio_register(struct intel_display *display); void intel_audio_deinit(struct intel_display *display); -void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_AUDIO_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c index 4f3fa966c537..e007380e9a63 100644 --- a/drivers/gpu/drm/i915/display/intel_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_backlight.c @@ -7,15 +7,18 @@ #include <linux/kernel.h> #include <linux/pwm.h> #include <linux/string_helpers.h> - #include <acpi/video.h> -#include "i915_drv.h" +#include <drm/drm_file.h> +#include <drm/drm_print.h> + #include "i915_reg.h" +#include "i915_utils.h" #include "intel_backlight.h" #include "intel_backlight_regs.h" #include "intel_connector.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_rpm.h" #include "intel_display_types.h" #include "intel_dp_aux_backlight.h" @@ -473,7 +476,6 @@ static void lpt_enable_backlight(const struct intel_crtc_state *crtc_state, { struct intel_connector *connector = to_intel_connector(conn_state->connector); struct intel_display *display = to_intel_display(connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); struct intel_panel *panel = &connector->panel; u32 pch_ctl1, pch_ctl2; @@ -486,7 +488,7 @@ static void lpt_enable_backlight(const struct intel_crtc_state *crtc_state, intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1); } - if (HAS_PCH_LPT(i915)) + if (HAS_PCH_LPT(display)) intel_de_rmw(display, SOUTH_CHICKEN2, LPT_PWM_GRANULARITY, panel->backlight.alternate_pwm_increment ? LPT_PWM_GRANULARITY : 0); @@ -503,7 +505,7 @@ static void lpt_enable_backlight(const struct intel_crtc_state *crtc_state, pch_ctl1 |= BLM_PCH_POLARITY; /* After LPT, override is the default. */ - if (HAS_PCH_LPT(i915)) + if (HAS_PCH_LPT(display)) pch_ctl1 |= BLM_PCH_OVERRIDE_ENABLE; intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1); @@ -1064,7 +1066,7 @@ static u32 spt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) */ static u32 lpt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; u32 mul, clock; @@ -1073,7 +1075,7 @@ static u32 lpt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) else mul = 128; - if (HAS_PCH_LPT_H(i915)) + if (HAS_PCH_LPT_H(display)) clock = MHz(135); /* LPT:H */ else clock = MHz(24); /* LPT:LP */ @@ -1230,12 +1232,11 @@ static u32 get_backlight_min_vbt(struct intel_connector *connector) static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unused) { struct intel_display *display = to_intel_display(connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); struct intel_panel *panel = &connector->panel; u32 cpu_ctl2, pch_ctl1, pch_ctl2, val; bool alt, cpu_mode; - if (HAS_PCH_LPT(i915)) + if (HAS_PCH_LPT(display)) alt = intel_de_read(display, SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY; else alt = intel_de_read(display, SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY; @@ -1259,7 +1260,7 @@ static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unus panel->backlight.pwm_enabled = pch_ctl1 & BLM_PCH_PWM_ENABLE; - cpu_mode = panel->backlight.pwm_enabled && HAS_PCH_LPT(i915) && + cpu_mode = panel->backlight.pwm_enabled && HAS_PCH_LPT(display) && !(pch_ctl1 & BLM_PCH_OVERRIDE_ENABLE) && (cpu_ctl2 & BLM_PWM_ENABLE); @@ -1466,15 +1467,13 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused) static int cnp_num_backlight_controllers(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - - if (INTEL_PCH_TYPE(i915) >= PCH_MTL) + if (INTEL_PCH_TYPE(display) >= PCH_MTL) return 2; - if (INTEL_PCH_TYPE(i915) >= PCH_DG1) + if (INTEL_PCH_TYPE(display) >= PCH_DG1) return 1; - if (INTEL_PCH_TYPE(i915) >= PCH_ICP) + if (INTEL_PCH_TYPE(display) >= PCH_ICP) return 2; return 1; @@ -1482,14 +1481,12 @@ static int cnp_num_backlight_controllers(struct intel_display *display) static bool cnp_backlight_controller_is_valid(struct intel_display *display, int controller) { - struct drm_i915_private *i915 = to_i915(display->drm); - if (controller < 0 || controller >= cnp_num_backlight_controllers(display)) return false; if (controller == 1 && - INTEL_PCH_TYPE(i915) >= PCH_ICP && - INTEL_PCH_TYPE(i915) <= PCH_ADP) + INTEL_PCH_TYPE(display) >= PCH_ICP && + INTEL_PCH_TYPE(display) <= PCH_ADP) return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT; return true; @@ -1818,7 +1815,6 @@ void intel_backlight_init_funcs(struct intel_panel *panel) struct intel_connector *connector = container_of(panel, struct intel_connector, panel); struct intel_display *display = to_intel_display(connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI && intel_dsi_dcs_init_backlight_funcs(connector) == 0) @@ -1826,14 +1822,14 @@ void intel_backlight_init_funcs(struct intel_panel *panel) if (display->platform.geminilake || display->platform.broxton) { panel->backlight.pwm_funcs = &bxt_pwm_funcs; - } else if (INTEL_PCH_TYPE(i915) >= PCH_CNP) { + } else if (INTEL_PCH_TYPE(display) >= PCH_CNP) { panel->backlight.pwm_funcs = &cnp_pwm_funcs; - } else if (INTEL_PCH_TYPE(i915) >= PCH_LPT_H) { - if (HAS_PCH_LPT(i915)) + } else if (INTEL_PCH_TYPE(display) >= PCH_LPT_H) { + if (HAS_PCH_LPT(display)) panel->backlight.pwm_funcs = &lpt_pwm_funcs; else panel->backlight.pwm_funcs = &spt_pwm_funcs; - } else if (HAS_PCH_SPLIT(i915)) { + } else if (HAS_PCH_SPLIT(display)) { panel->backlight.pwm_funcs = &pch_pwm_funcs; } else if (display->platform.valleyview || display->platform.cherryview) { if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI) { diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index fabfcf2caa69..9ce41e689d50 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -37,6 +37,7 @@ #include "i915_drv.h" #include "intel_display.h" +#include "intel_display_core.h" #include "intel_display_rpm.h" #include "intel_display_types.h" #include "intel_gmbus.h" @@ -2245,28 +2246,27 @@ static const u8 adlp_ddc_pin_map[] = { static u8 map_ddc_pin(struct intel_display *display, u8 vbt_pin) { - struct drm_i915_private *i915 = to_i915(display->drm); const u8 *ddc_pin_map; int i, n_entries; - if (INTEL_PCH_TYPE(i915) >= PCH_MTL || display->platform.alderlake_p) { + if (INTEL_PCH_TYPE(display) >= PCH_MTL || display->platform.alderlake_p) { ddc_pin_map = adlp_ddc_pin_map; n_entries = ARRAY_SIZE(adlp_ddc_pin_map); } else if (display->platform.alderlake_s) { ddc_pin_map = adls_ddc_pin_map; n_entries = ARRAY_SIZE(adls_ddc_pin_map); - } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { + } else if (INTEL_PCH_TYPE(display) >= PCH_DG1) { return vbt_pin; - } else if (display->platform.rocketlake && INTEL_PCH_TYPE(i915) == PCH_TGP) { + } else if (display->platform.rocketlake && INTEL_PCH_TYPE(display) == PCH_TGP) { ddc_pin_map = rkl_pch_tgp_ddc_pin_map; n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); - } else if (HAS_PCH_TGP(i915) && DISPLAY_VER(display) == 9) { + } else if (HAS_PCH_TGP(display) && DISPLAY_VER(display) == 9) { ddc_pin_map = gen9bc_tgp_ddc_pin_map; n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map); - } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { + } else if (INTEL_PCH_TYPE(display) >= PCH_ICP) { ddc_pin_map = icp_ddc_pin_map; n_entries = ARRAY_SIZE(icp_ddc_pin_map); - } else if (HAS_PCH_CNP(i915)) { + } else if (HAS_PCH_CNP(display)) { ddc_pin_map = cnp_ddc_pin_map; n_entries = ARRAY_SIZE(cnp_ddc_pin_map); } else { @@ -2865,8 +2865,6 @@ parse_general_definitions(struct intel_display *display) static void init_vbt_defaults(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - display->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC; /* general features */ @@ -2883,7 +2881,7 @@ init_vbt_defaults(struct intel_display *display) * clock for LVDS. */ display->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(display, - !HAS_PCH_SPLIT(i915)); + !HAS_PCH_SPLIT(display)); drm_dbg_kms(display->drm, "Set default to SSC at %d kHz\n", display->vbt.lvds_ssc_freq); } @@ -3126,7 +3124,7 @@ static const struct vbt_header *intel_bios_get_vbt(struct intel_display *display * If the OpRegion does not have VBT, look in SPI flash * through MMIO or PCI mapping */ - if (!vbt && IS_DGFX(i915)) + if (!vbt && display->platform.dgfx) with_intel_display_rpm(display) vbt = oprom_get_vbt(display, intel_rom_spi(i915), sizep, "SPI flash"); diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h index f9841f0498c6..6cd7a011b8c4 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.h +++ b/drivers/gpu/drm/i915/display/intel_bios.h @@ -24,7 +24,7 @@ /* * Please use intel_vbt_defs.h for VBT private data, to hide and abstract away * the VBT from the rest of the driver. Add the parsed, clean data to struct - * intel_vbt_data within struct drm_i915_private. + * intel_vbt_data within struct intel_display. */ #ifndef _INTEL_BIOS_H_ diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index a5dd2932b852..6c2ab2e0dc91 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -5,6 +5,8 @@ #include <drm/drm_atomic_state_helper.h> +#include "soc/intel_dram.h" + #include "i915_drv.h" #include "i915_reg.h" #include "i915_utils.h" @@ -12,10 +14,11 @@ #include "intel_bw.h" #include "intel_cdclk.h" #include "intel_display_core.h" +#include "intel_display_regs.h" #include "intel_display_types.h" -#include "skl_watermark.h" #include "intel_mchbar_regs.h" #include "intel_pcode.h" +#include "skl_watermark.h" /* Parameters for Qclk Geyserville (QGV) */ struct intel_qgv_point { @@ -218,11 +221,10 @@ intel_read_qgv_point_info(struct intel_display *display, } static int icl_get_qgv_points(struct intel_display *display, + const struct dram_info *dram_info, struct intel_qgv_info *qi, bool is_y_tile) { - struct drm_i915_private *i915 = to_i915(display->drm); - const struct dram_info *dram_info = &i915->dram_info; int i, ret; qi->num_points = dram_info->num_qgv_points; @@ -418,19 +420,20 @@ static const struct intel_sa_info xe3lpd_sa_info = { .derating = 10, }; -static int icl_get_bw_info(struct intel_display *display, const struct intel_sa_info *sa) +static int icl_get_bw_info(struct intel_display *display, + const struct dram_info *dram_info, + const struct intel_sa_info *sa) { - struct drm_i915_private *i915 = to_i915(display->drm); struct intel_qgv_info qi = {}; bool is_y_tile = true; /* assume y tile may be used */ - int num_channels = max_t(u8, 1, i915->dram_info.num_channels); + int num_channels = max_t(u8, 1, dram_info->num_channels); int ipqdepth, ipqdepthpch = 16; int dclk_max; int maxdebw; int num_groups = ARRAY_SIZE(display->bw.max); int i, ret; - ret = icl_get_qgv_points(display, &qi, is_y_tile); + ret = icl_get_qgv_points(display, dram_info, &qi, is_y_tile); if (ret) { drm_dbg_kms(display->drm, "Failed to get memory subsystem information, ignoring bandwidth limits"); @@ -488,11 +491,11 @@ static int icl_get_bw_info(struct intel_display *display, const struct intel_sa_ return 0; } -static int tgl_get_bw_info(struct intel_display *display, const struct intel_sa_info *sa) +static int tgl_get_bw_info(struct intel_display *display, + const struct dram_info *dram_info, + const struct intel_sa_info *sa) { - struct drm_i915_private *i915 = to_i915(display->drm); struct intel_qgv_info qi = {}; - const struct dram_info *dram_info = &i915->dram_info; bool is_y_tile = true; /* assume y tile may be used */ int num_channels = max_t(u8, 1, dram_info->num_channels); int ipqdepth, ipqdepthpch = 16; @@ -502,7 +505,7 @@ static int tgl_get_bw_info(struct intel_display *display, const struct intel_sa_ int num_groups = ARRAY_SIZE(display->bw.max); int i, ret; - ret = icl_get_qgv_points(display, &qi, is_y_tile); + ret = icl_get_qgv_points(display, dram_info, &qi, is_y_tile); if (ret) { drm_dbg_kms(display->drm, "Failed to get memory subsystem information, ignoring bandwidth limits"); @@ -632,15 +635,15 @@ static void dg2_get_bw_info(struct intel_display *display) } static int xe2_hpd_get_bw_info(struct intel_display *display, + const struct dram_info *dram_info, const struct intel_sa_info *sa) { - struct drm_i915_private *i915 = to_i915(display->drm); struct intel_qgv_info qi = {}; - int num_channels = i915->dram_info.num_channels; + int num_channels = dram_info->num_channels; int peakbw, maxdebw; int ret, i; - ret = icl_get_qgv_points(display, &qi, true); + ret = icl_get_qgv_points(display, dram_info, &qi, true); if (ret) { drm_dbg_kms(display->drm, "Failed to get memory subsystem information, ignoring bandwidth limits"); @@ -763,32 +766,32 @@ static unsigned int icl_qgv_bw(struct intel_display *display, void intel_bw_init_hw(struct intel_display *display) { - const struct dram_info *dram_info = &to_i915(display->drm)->dram_info; + const struct dram_info *dram_info = intel_dram_info(display->drm); if (!HAS_DISPLAY(display)) return; if (DISPLAY_VER(display) >= 30) - tgl_get_bw_info(display, &xe3lpd_sa_info); + tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info); else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx && dram_info->type == INTEL_DRAM_GDDR_ECC) - xe2_hpd_get_bw_info(display, &xe2_hpd_ecc_sa_info); + xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info); else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) - xe2_hpd_get_bw_info(display, &xe2_hpd_sa_info); + xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info); else if (DISPLAY_VER(display) >= 14) - tgl_get_bw_info(display, &mtl_sa_info); + tgl_get_bw_info(display, dram_info, &mtl_sa_info); else if (display->platform.dg2) dg2_get_bw_info(display); else if (display->platform.alderlake_p) - tgl_get_bw_info(display, &adlp_sa_info); + tgl_get_bw_info(display, dram_info, &adlp_sa_info); else if (display->platform.alderlake_s) - tgl_get_bw_info(display, &adls_sa_info); + tgl_get_bw_info(display, dram_info, &adls_sa_info); else if (display->platform.rocketlake) - tgl_get_bw_info(display, &rkl_sa_info); + tgl_get_bw_info(display, dram_info, &rkl_sa_info); else if (DISPLAY_VER(display) == 12) - tgl_get_bw_info(display, &tgl_sa_info); + tgl_get_bw_info(display, dram_info, &tgl_sa_info); else if (DISPLAY_VER(display) == 11) - icl_get_bw_info(display, &icl_sa_info); + icl_get_bw_info(display, dram_info, &icl_sa_info); } static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 6830950aae3f..38b3094b37d7 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -38,6 +38,7 @@ #include "intel_cdclk.h" #include "intel_crtc.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_mchbar_regs.h" #include "intel_pci_config.h" @@ -567,20 +568,18 @@ static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) static void vlv_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 val; - vlv_iosf_sb_get(dev_priv, - BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); + vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); - cdclk_config->vco = vlv_get_hpll_vco(dev_priv); - cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", + cdclk_config->vco = vlv_get_hpll_vco(display->drm); + cdclk_config->cdclk = vlv_get_cck_clock(display->drm, "cdclk", CCK_DISPLAY_CLOCK_CONTROL, cdclk_config->vco); - val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); + val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); - vlv_iosf_sb_put(dev_priv, + vlv_iosf_sb_put(display->drm, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); if (display->platform.valleyview) @@ -658,16 +657,16 @@ static void vlv_set_cdclk(struct intel_display *display, */ wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); - vlv_iosf_sb_get(dev_priv, + vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_BUNIT) | BIT(VLV_IOSF_SB_PUNIT)); - val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); + val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); val &= ~DSPFREQGUAR_MASK; val |= (cmd << DSPFREQGUAR_SHIFT); - vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); - if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & + vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); + if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 50)) { drm_err(display->drm, @@ -681,12 +680,12 @@ static void vlv_set_cdclk(struct intel_display *display, cdclk) - 1; /* adjust cdclk divider */ - val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); + val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL); val &= ~CCK_FREQUENCY_VALUES; val |= divider; - vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); + vlv_cck_write(display->drm, CCK_DISPLAY_CLOCK_CONTROL, val); - if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & + if (wait_for((vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL) & CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 50)) drm_err(display->drm, @@ -694,7 +693,7 @@ static void vlv_set_cdclk(struct intel_display *display, } /* adjust self-refresh exit latency value */ - val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); + val = vlv_bunit_read(display->drm, BUNIT_REG_BISOC); val &= ~0x7f; /* @@ -705,9 +704,9 @@ static void vlv_set_cdclk(struct intel_display *display, val |= 4500 / 250; /* 4.5 usec */ else val |= 3000 / 250; /* 3.0 usec */ - vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); + vlv_bunit_write(display->drm, BUNIT_REG_BISOC, val); - vlv_iosf_sb_put(dev_priv, + vlv_iosf_sb_put(display->drm, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_BUNIT) | BIT(VLV_IOSF_SB_PUNIT)); @@ -723,7 +722,6 @@ static void chv_set_cdclk(struct intel_display *display, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { - struct drm_i915_private *dev_priv = to_i915(display->drm); int cdclk = cdclk_config->cdclk; u32 val, cmd = cdclk_config->voltage_level; intel_wakeref_t wakeref; @@ -747,19 +745,19 @@ static void chv_set_cdclk(struct intel_display *display, */ wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); - vlv_punit_get(dev_priv); - val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); + vlv_punit_get(display->drm); + val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); val &= ~DSPFREQGUAR_MASK_CHV; val |= (cmd << DSPFREQGUAR_SHIFT_CHV); - vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); - if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & + vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); + if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 50)) { drm_err(display->drm, "timed out waiting for CDclk change\n"); } - vlv_punit_put(dev_priv); + vlv_punit_put(display->drm); intel_update_cdclk(display); @@ -3494,7 +3492,6 @@ static int dg1_rawclk(struct intel_display *display) static int cnp_rawclk(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); int divider, fraction; u32 rawclk; @@ -3514,7 +3511,7 @@ static int cnp_rawclk(struct intel_display *display) rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, fraction) - 1); - if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) + if (INTEL_PCH_TYPE(display) >= PCH_ICP) rawclk |= ICP_RAWCLK_NUM(numerator); } @@ -3529,10 +3526,8 @@ static int pch_rawclk(struct intel_display *display) static int vlv_hrawclk(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - /* RAWCLK_FREQ_VLV register updated from power well code */ - return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", + return vlv_get_cck_clock_hpll(display->drm, "hrawclk", CCK_DISPLAY_REF_CLOCK_CONTROL); } @@ -3553,21 +3548,20 @@ static int i9xx_hrawclk(struct intel_display *display) */ u32 intel_read_rawclk(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 freq; - if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL) + if (INTEL_PCH_TYPE(display) >= PCH_MTL) /* * MTL always uses a 38.4 MHz rawclk. The bspec tells us * "RAWCLK_FREQ defaults to the values for 38.4 and does * not need to be programmed." */ freq = 38400; - else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) + else if (INTEL_PCH_TYPE(display) >= PCH_DG1) freq = dg1_rawclk(display); - else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) + else if (INTEL_PCH_TYPE(display) >= PCH_CNP) freq = cnp_rawclk(display); - else if (HAS_PCH_SPLIT(dev_priv)) + else if (HAS_PCH_SPLIT(display)) freq = pch_rawclk(display); else if (display->platform.valleyview || display->platform.cherryview) freq = vlv_hrawclk(display); diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c index 07d7f4e8f60f..165138b95cb2 100644 --- a/drivers/gpu/drm/i915/display/intel_cmtg.c +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c @@ -9,14 +9,13 @@ #include <drm/drm_device.h> #include <drm/drm_print.h> -#include "i915_drv.h" -#include "i915_reg.h" -#include "intel_crtc.h" #include "intel_cmtg.h" #include "intel_cmtg_regs.h" +#include "intel_crtc.h" #include "intel_de.h" #include "intel_display_device.h" #include "intel_display_power.h" +#include "intel_display_regs.h" /** * DOC: Common Primary Timing Generator (CMTG) diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h index 668e41d65e86..945a35578284 100644 --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h @@ -6,7 +6,7 @@ #ifndef __INTEL_CMTG_REGS_H__ #define __INTEL_CMTG_REGS_H__ -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" #define CMTG_CLK_SEL _MMIO(0x46160) #define CMTG_CLK_SEL_A_MASK REG_GENMASK(31, 29) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 98dddf72c0eb..671db6926e4c 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1339,8 +1339,8 @@ static void ilk_lut_write(const struct intel_crtc_state *crtc_state, { struct intel_display *display = to_intel_display(crtc_state); - if (crtc_state->dsb_color_vblank) - intel_dsb_reg_write(crtc_state->dsb_color_vblank, reg, val); + if (crtc_state->dsb_color) + intel_dsb_reg_write(crtc_state->dsb_color, reg, val); else intel_de_write_fw(display, reg, val); } @@ -1350,8 +1350,8 @@ static void ilk_lut_write_indexed(const struct intel_crtc_state *crtc_state, { struct intel_display *display = to_intel_display(crtc_state); - if (crtc_state->dsb_color_vblank) - intel_dsb_reg_write_indexed(crtc_state->dsb_color_vblank, reg, val); + if (crtc_state->dsb_color) + intel_dsb_reg_write_indexed(crtc_state->dsb_color, reg, val); else intel_de_write_fw(display, reg, val); } @@ -1389,7 +1389,7 @@ static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state, for (i = 0; i < 256; i++) { ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i), i9xx_lut_8(&lut[i])); - if (crtc_state->dsb_color_vblank) + if (crtc_state->dsb_color) ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i), i9xx_lut_8(&lut[i])); } @@ -1917,7 +1917,7 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); - if (crtc_state->dsb_color_vblank) + if (crtc_state->dsb_color) return; display->funcs.color->load_luts(crtc_state); @@ -1965,6 +1965,25 @@ void intel_color_modeset(const struct intel_crtc_state *crtc_state) } } +bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state) +{ + return crtc_state->dsb_color; +} + +bool intel_color_uses_chained_dsb(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + + return crtc_state->dsb_color && !HAS_DOUBLE_BUFFERED_LUT(display); +} + +bool intel_color_uses_gosub_dsb(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + + return crtc_state->dsb_color && HAS_DOUBLE_BUFFERED_LUT(display); +} + void intel_color_prepare_commit(struct intel_atomic_state *state, struct intel_crtc *crtc) { @@ -1982,47 +2001,53 @@ void intel_color_prepare_commit(struct intel_atomic_state *state, if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut) return; - crtc_state->dsb_color_vblank = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024); - if (!crtc_state->dsb_color_vblank) + if (HAS_DOUBLE_BUFFERED_LUT(display)) + crtc_state->dsb_color = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 1024); + else + crtc_state->dsb_color = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024); + + if (!intel_color_uses_dsb(crtc_state)) return; display->funcs.color->load_luts(crtc_state); - if (crtc_state->use_dsb) { - intel_vrr_send_push(crtc_state->dsb_color_vblank, crtc_state); - intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color_vblank); - intel_vrr_check_push_sent(crtc_state->dsb_color_vblank, crtc_state); - intel_dsb_interrupt(crtc_state->dsb_color_vblank); + if (crtc_state->use_dsb && intel_color_uses_chained_dsb(crtc_state)) { + intel_vrr_send_push(crtc_state->dsb_color, crtc_state); + intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color); + intel_vrr_check_push_sent(crtc_state->dsb_color, crtc_state); + intel_dsb_interrupt(crtc_state->dsb_color); } - intel_dsb_finish(crtc_state->dsb_color_vblank); + if (intel_color_uses_gosub_dsb(crtc_state)) + intel_dsb_gosub_finish(crtc_state->dsb_color); + else + intel_dsb_finish(crtc_state->dsb_color); } void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state) { - if (crtc_state->dsb_color_vblank) { - intel_dsb_cleanup(crtc_state->dsb_color_vblank); - crtc_state->dsb_color_vblank = NULL; + if (crtc_state->dsb_color) { + intel_dsb_cleanup(crtc_state->dsb_color); + crtc_state->dsb_color = NULL; } } void intel_color_wait_commit(const struct intel_crtc_state *crtc_state) { - if (crtc_state->dsb_color_vblank) - intel_dsb_wait(crtc_state->dsb_color_vblank); -} - -bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state) -{ - return crtc_state->dsb_color_vblank; + if (crtc_state->dsb_color) + intel_dsb_wait(crtc_state->dsb_color); } static bool intel_can_preload_luts(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); + if (HAS_DOUBLE_BUFFERED_LUT(display)) + return false; + return !old_crtc_state->post_csc_lut && !old_crtc_state->pre_csc_lut; } diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h index 9d66457c1e89..bf7a12ce9df0 100644 --- a/drivers/gpu/drm/i915/display/intel_color.h +++ b/drivers/gpu/drm/i915/display/intel_color.h @@ -24,6 +24,8 @@ void intel_color_prepare_commit(struct intel_atomic_state *state, struct intel_crtc *crtc); void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state); bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state); +bool intel_color_uses_chained_dsb(const struct intel_crtc_state *crtc_state); +bool intel_color_uses_gosub_dsb(const struct intel_crtc_state *crtc_state); void intel_color_wait_commit(const struct intel_crtc_state *crtc_state); void intel_color_commit_noarm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index f5cc38dbe559..112749f97c26 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -5,11 +5,11 @@ #include <drm/drm_print.h> -#include "i915_reg.h" #include "i915_utils.h" #include "intel_combo_phy.h" #include "intel_combo_phy_regs.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #define for_each_combo_phy(__display, __phy) \ diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h index ee41acdccf4e..3694f95376c2 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h @@ -6,7 +6,7 @@ #ifndef __INTEL_COMBO_PHY_REGS__ #define __INTEL_COMBO_PHY_REGS__ -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" #define _ICL_COMBOPHY_A 0x162000 #define _ICL_COMBOPHY_B 0x6C000 diff --git a/drivers/gpu/drm/i915/display/intel_connector.c b/drivers/gpu/drm/i915/display/intel_connector.c index 6c81c9f2fd09..2867d76d1a5e 100644 --- a/drivers/gpu/drm/i915/display/intel_connector.c +++ b/drivers/gpu/drm/i915/display/intel_connector.c @@ -32,7 +32,6 @@ #include "i915_drv.h" #include "i915_utils.h" -#include "intel_backlight.h" #include "intel_connector.h" #include "intel_display_core.h" #include "intel_display_debugfs.h" @@ -153,36 +152,36 @@ void intel_connector_destroy(struct drm_connector *connector) kfree(connector); } -int intel_connector_register(struct drm_connector *connector) +int intel_connector_register(struct drm_connector *_connector) { - struct intel_connector *intel_connector = to_intel_connector(connector); - struct drm_i915_private *i915 = to_i915(connector->dev); + struct intel_connector *connector = to_intel_connector(_connector); + struct drm_i915_private *i915 = to_i915(_connector->dev); int ret; - ret = intel_backlight_device_register(intel_connector); + ret = intel_panel_register(connector); if (ret) goto err; if (i915_inject_probe_failure(i915)) { ret = -EFAULT; - goto err_backlight; + goto err_panel; } - intel_connector_debugfs_add(intel_connector); + intel_connector_debugfs_add(connector); return 0; -err_backlight: - intel_backlight_device_unregister(intel_connector); +err_panel: + intel_panel_unregister(connector); err: return ret; } -void intel_connector_unregister(struct drm_connector *connector) +void intel_connector_unregister(struct drm_connector *_connector) { - struct intel_connector *intel_connector = to_intel_connector(connector); + struct intel_connector *connector = to_intel_connector(_connector); - intel_backlight_device_unregister(intel_connector); + intel_panel_unregister(connector); } void intel_connector_attach_encoder(struct intel_connector *connector, @@ -209,8 +208,7 @@ enum pipe intel_connector_get_pipe(struct intel_connector *connector) { struct intel_display *display = to_intel_display(connector); - drm_WARN_ON(display->drm, - !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); + drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex); if (!connector->base.state->crtc) return INVALID_PIPE; diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index cca22d2402e8..898c5d9e8f7a 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -31,11 +31,9 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> #include <drm/drm_edid.h> +#include <drm/drm_print.h> #include <drm/drm_probe_helper.h> -#include "i915_drv.h" -#include "i915_irq.h" -#include "i915_reg.h" #include "intel_connector.h" #include "intel_crt.h" #include "intel_crt_regs.h" @@ -44,6 +42,7 @@ #include "intel_ddi_buf_trans.h" #include "intel_de.h" #include "intel_display_driver.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_fdi.h" #include "intel_fdi_regs.h" @@ -91,13 +90,12 @@ static struct intel_crt *intel_attached_crt(struct intel_connector *connector) bool intel_crt_port_enabled(struct intel_display *display, i915_reg_t adpa_reg, enum pipe *pipe) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 val; val = intel_de_read(display, adpa_reg); /* asserts want to know the pipe even if the port is disabled */ - if (HAS_PCH_CPT(dev_priv)) + if (HAS_PCH_CPT(display)) *pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK_CPT, val); else *pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK, val); @@ -177,7 +175,6 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crt *crt = intel_encoder_to_crt(encoder); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; @@ -194,14 +191,14 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, adpa |= ADPA_VSYNC_ACTIVE_HIGH; /* For CPT allow 3 pipe config, for others just use A or B */ - if (HAS_PCH_LPT(dev_priv)) + if (HAS_PCH_LPT(display)) ; /* Those bits don't exist here */ - else if (HAS_PCH_CPT(dev_priv)) + else if (HAS_PCH_CPT(display)) adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe); else adpa |= ADPA_PIPE_SEL(crtc->pipe); - if (!HAS_PCH_SPLIT(dev_priv)) + if (!HAS_PCH_SPLIT(display)) intel_de_write(display, BCLRPAT(display, crtc->pipe), 0); switch (mode) { @@ -356,7 +353,6 @@ intel_crt_mode_valid(struct drm_connector *connector, const struct drm_display_mode *mode) { struct intel_display *display = to_intel_display(connector->dev); - struct drm_i915_private *dev_priv = to_i915(connector->dev); int max_dotclk = display->cdclk.max_dotclk_freq; enum drm_mode_status status; int max_clock; @@ -368,9 +364,9 @@ intel_crt_mode_valid(struct drm_connector *connector, if (mode->clock < 25000) return MODE_CLOCK_LOW; - if (HAS_PCH_LPT(dev_priv)) + if (HAS_PCH_LPT(display)) max_clock = 180000; - else if (IS_VALLEYVIEW(dev_priv)) + else if (display->platform.valleyview) /* * 270 MHz due to current DPLL limits, * DAC limit supposedly 355 MHz. @@ -387,7 +383,7 @@ intel_crt_mode_valid(struct drm_connector *connector, return MODE_CLOCK_HIGH; /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ - if (HAS_PCH_LPT(dev_priv) && + if (HAS_PCH_LPT(display) && ilk_get_lanes_required(mode->clock, 270000, 24) > 2) return MODE_CLOCK_HIGH; @@ -438,7 +434,6 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder, struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; @@ -457,7 +452,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder, crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; /* LPT FDI RX only supports 8bpc. */ - if (HAS_PCH_LPT(dev_priv)) { + if (HAS_PCH_LPT(display)) { /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */ if (crtc_state->bw_constrained && crtc_state->pipe_bpp < 24) { drm_dbg_kms(display->drm, @@ -482,13 +477,12 @@ static bool ilk_crt_detect_hotplug(struct drm_connector *connector) { struct intel_display *display = to_intel_display(connector->dev); struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); - struct drm_i915_private *dev_priv = to_i915(connector->dev); u32 adpa; bool ret; /* The first time through, trigger an explicit detection cycle */ if (crt->force_hotplug_required) { - bool turn_off_dac = HAS_PCH_SPLIT(dev_priv); + bool turn_off_dac = HAS_PCH_SPLIT(display); u32 save_adpa; crt->force_hotplug_required = false; @@ -583,15 +577,14 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) static bool intel_crt_detect_hotplug(struct drm_connector *connector) { struct intel_display *display = to_intel_display(connector->dev); - struct drm_i915_private *dev_priv = to_i915(connector->dev); u32 stat; bool ret = false; int i, tries = 0; - if (HAS_PCH_SPLIT(dev_priv)) + if (HAS_PCH_SPLIT(display)) return ilk_crt_detect_hotplug(connector); - if (IS_VALLEYVIEW(dev_priv)) + if (display->platform.valleyview) return valleyview_crt_detect_hotplug(connector); /* @@ -599,7 +592,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector) * to get a reliable result. */ - if (IS_G45(dev_priv)) + if (display->platform.g45) tries = 2; else tries = 1; @@ -940,7 +933,6 @@ out: static int intel_crt_get_modes(struct drm_connector *connector) { struct intel_display *display = to_intel_display(connector->dev); - struct drm_i915_private *dev_priv = to_i915(connector->dev); struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); struct intel_encoder *encoder = &crt->base; intel_wakeref_t wakeref; @@ -953,7 +945,7 @@ static int intel_crt_get_modes(struct drm_connector *connector) wakeref = intel_display_power_get(display, encoder->power_domain); ret = intel_crt_ddc_get_modes(connector, connector->ddc); - if (ret || !IS_G4X(dev_priv)) + if (ret || !display->platform.g4x) goto out; /* Try to probe digital port for output in DVI-I -> VGA mode. */ @@ -1012,16 +1004,15 @@ static const struct drm_encoder_funcs intel_crt_enc_funcs = { void intel_crt_init(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_connector *connector; struct intel_crt *crt; i915_reg_t adpa_reg; u8 ddc_pin; u32 adpa; - if (HAS_PCH_SPLIT(dev_priv)) + if (HAS_PCH_SPLIT(display)) adpa_reg = PCH_ADPA; - else if (IS_VALLEYVIEW(dev_priv)) + else if (display->platform.valleyview) adpa_reg = VLV_ADPA; else adpa_reg = ADPA; @@ -1069,7 +1060,7 @@ void intel_crt_init(struct intel_display *display) crt->base.type = INTEL_OUTPUT_ANALOG; crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI); - if (IS_I830(dev_priv)) + if (display->platform.i830) crt->base.pipe_mask = BIT(PIPE_A); else crt->base.pipe_mask = ~0; @@ -1109,7 +1100,7 @@ void intel_crt_init(struct intel_display *display) intel_ddi_buf_trans_init(&crt->base); } else { - if (HAS_PCH_SPLIT(dev_priv)) { + if (HAS_PCH_SPLIT(display)) { crt->base.compute_config = pch_crt_compute_config; crt->base.disable = pch_disable_crt; crt->base.post_disable = pch_post_disable_crt; @@ -1131,7 +1122,7 @@ void intel_crt_init(struct intel_display *display) * polarity and link reversal bits or not, instead of relying on the * BIOS. */ - if (HAS_PCH_LPT(dev_priv)) { + if (HAS_PCH_LPT(display)) { u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | FDI_RX_LINK_REVERSAL_OVERRIDE; diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 5b2603ef2ff7..a88317ea4e9c 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -124,7 +124,7 @@ void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - crtc->block_dc_for_vblank = intel_psr_needs_block_dc_vblank(crtc_state); + crtc->vblank_psr_notify = intel_psr_needs_vblank_notification(crtc_state); assert_vblank_disabled(&crtc->base); drm_crtc_set_max_vblank_count(&crtc->base, @@ -154,9 +154,9 @@ void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state) drm_crtc_vblank_off(&crtc->base); assert_vblank_disabled(&crtc->base); - crtc->block_dc_for_vblank = false; + crtc->vblank_psr_notify = false; - flush_work(&display->irq.vblank_dc_work); + flush_work(&display->irq.vblank_notify_work); } struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc) @@ -305,7 +305,6 @@ static const struct drm_crtc_funcs i8xx_crtc_funcs = { int intel_crtc_init(struct intel_display *display, enum pipe pipe) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_plane *primary, *cursor; const struct drm_crtc_funcs *funcs; struct intel_crtc *crtc; @@ -333,7 +332,7 @@ int intel_crtc_init(struct intel_display *display, enum pipe pipe) for_each_sprite(display, pipe, sprite) { struct intel_plane *plane; - if (DISPLAY_VER(dev_priv) >= 9) + if (DISPLAY_VER(display) >= 9) plane = skl_universal_plane_create(display, pipe, PLANE_2 + sprite); else plane = intel_sprite_plane_create(display, pipe, sprite); @@ -418,10 +417,13 @@ int intel_crtc_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, static bool intel_crtc_needs_vblank_work(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); + return crtc_state->hw.active && !crtc_state->preload_luts && !intel_crtc_needs_modeset(crtc_state) && - intel_crtc_needs_color_update(crtc_state) && + (intel_crtc_needs_color_update(crtc_state) && + !HAS_DOUBLE_BUFFERED_LUT(display)) && !intel_color_uses_dsb(crtc_state) && !crtc_state->use_dsb; } diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 3276a5b4a9b0..6bd4f6a28cae 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -9,10 +9,10 @@ #include <drm/drm_blend.h> #include <drm/drm_damage_helper.h> #include <drm/drm_fourcc.h> +#include <drm/drm_print.h> #include <drm/drm_vblank.h> -#include "i915_drv.h" -#include "i915_reg.h" +#include "i915_utils.h" #include "intel_atomic.h" #include "intel_atomic_plane.h" #include "intel_cursor.h" diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 22595766eac5..83c8df9dbc0c 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -6,8 +6,10 @@ #include <linux/log2.h> #include <linux/math64.h> -#include "i915_drv.h" -#include "i915_reg.h" +#include <drm/drm_print.h> + +#include "i915_utils.h" +#include "intel_alpm.h" #include "intel_cx0_phy.h" #include "intel_cx0_phy_regs.h" #include "intel_ddi.h" @@ -2761,9 +2763,9 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder, val |= XELPDP_FORWARD_CLOCK_UNGATE; if (!is_dp && is_hdmi_frl(port_clock)) - val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_DIV18CLK); + val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK); else - val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK); + val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK); /* TODO: HDMI FRL */ /* DP2.0 10G and 20G rates enable MPLLA*/ @@ -2774,7 +2776,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder, intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE | - XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_SSC_ENABLE_PLLA | + XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_SSC_ENABLE_PLLA | XELPDP_SSC_ENABLE_PLLB, val); } @@ -3097,10 +3099,7 @@ int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder) val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)); - if (DISPLAY_VER(display) >= 30) - clock = REG_FIELD_GET(XE3_DDI_CLOCK_SELECT_MASK, val); - else - clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val); + clock = XELPDP_DDI_CLOCK_SELECT_GET(display, val); drm_WARN_ON(display->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE)); drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_REQUEST)); @@ -3168,13 +3167,9 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder, * clock muxes, gating and SSC */ - if (DISPLAY_VER(display) >= 30) { - mask = XE3_DDI_CLOCK_SELECT_MASK; - val |= XE3_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(display, crtc_state->port_clock)); - } else { - mask = XELPDP_DDI_CLOCK_SELECT_MASK; - val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(display, crtc_state->port_clock)); - } + mask = XELPDP_DDI_CLOCK_SELECT_MASK(display); + val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, + intel_mtl_tbt_clock_select(display, crtc_state->port_clock)); mask |= XELPDP_FORWARD_CLOCK_UNGATE; val |= XELPDP_FORWARD_CLOCK_UNGATE; @@ -3229,6 +3224,37 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder, intel_cx0pll_enable(encoder, crtc_state); } +/* + * According to HAS we need to enable MAC Transmitting LFPS in the "PHY Common + * Control 0" PIPE register in case of AUX Less ALPM is going to be used. This + * function is doing that and is called by link retrain sequence. + */ +void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(encoder); + u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder); + bool enable = intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), + crtc_state); + int i; + + if (DISPLAY_VER(display) < 20) + return; + + for (i = 0; i < 4; i++) { + int tx = i % 2 + 1; + u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; + + if (!(owned_lane_mask & lane_mask)) + continue; + + intel_cx0_rmw(encoder, lane_mask, PHY_CMN1_CONTROL(tx, 0), + CONTROL0_MAC_TRANSMIT_LFPS, + enable ? CONTROL0_MAC_TRANSMIT_LFPS : 0, + MB_WRITE_COMMITTED); + } +} + static u8 cx0_power_control_disable_val(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); @@ -3287,7 +3313,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder) /* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), - XELPDP_DDI_CLOCK_SELECT_MASK, 0); + XELPDP_DDI_CLOCK_SELECT_MASK(display), 0); intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), XELPDP_FORWARD_CLOCK_UNGATE, 0); @@ -3336,7 +3362,7 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder) * 5. Program PORT CLOCK CTRL register to disable and gate clocks */ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), - XELPDP_DDI_CLOCK_SELECT_MASK | + XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_FORWARD_CLOCK_UNGATE, 0); /* 6. Program DDI_CLK_VALFREQ to 0. */ @@ -3365,7 +3391,7 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder, * handling is done via the standard shared DPLL framework. */ val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)); - clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val); + clock = XELPDP_DDI_CLOCK_SELECT_GET(display, val); if (clock == XELPDP_DDI_CLOCK_SELECT_MAXPCLK || clock == XELPDP_DDI_CLOCK_SELECT_DIV18CLK) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h index a8f811ca5e7b..c5a7b529955b 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h @@ -43,5 +43,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder); void intel_cx0_pll_power_save_wa(struct intel_display *display); +void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); #endif /* __INTEL_CX0_PHY_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index 960f7f778fb8..77eae1d845f7 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -6,8 +6,8 @@ #ifndef __INTEL_CX0_PHY_REGS_H__ #define __INTEL_CX0_PHY_REGS_H__ -#include "i915_reg_defs.h" #include "intel_display_limits.h" +#include "intel_display_reg_defs.h" /* DDI Buffer Control */ #define _DDI_CLK_VALFREQ_A 0x64030 @@ -192,10 +192,17 @@ #define XELPDP_TBT_CLOCK_REQUEST REG_BIT(19) #define XELPDP_TBT_CLOCK_ACK REG_BIT(18) -#define XELPDP_DDI_CLOCK_SELECT_MASK REG_GENMASK(15, 12) -#define XE3_DDI_CLOCK_SELECT_MASK REG_GENMASK(16, 12) -#define XELPDP_DDI_CLOCK_SELECT(val) REG_FIELD_PREP(XELPDP_DDI_CLOCK_SELECT_MASK, val) -#define XE3_DDI_CLOCK_SELECT(val) REG_FIELD_PREP(XE3_DDI_CLOCK_SELECT_MASK, val) +#define _XELPDP_DDI_CLOCK_SELECT_MASK REG_GENMASK(15, 12) +#define _XE3_DDI_CLOCK_SELECT_MASK REG_GENMASK(16, 12) +#define XELPDP_DDI_CLOCK_SELECT_MASK(display) (DISPLAY_VER(display) >= 30 ? \ + _XE3_DDI_CLOCK_SELECT_MASK : _XELPDP_DDI_CLOCK_SELECT_MASK) +#define XELPDP_DDI_CLOCK_SELECT_PREP(display, val) (DISPLAY_VER(display) >= 30 ? \ + REG_FIELD_PREP(_XE3_DDI_CLOCK_SELECT_MASK, (val)) : \ + REG_FIELD_PREP(_XELPDP_DDI_CLOCK_SELECT_MASK, (val))) +#define XELPDP_DDI_CLOCK_SELECT_GET(display, val) (DISPLAY_VER(display) >= 30 ? \ + REG_FIELD_GET(_XE3_DDI_CLOCK_SELECT_MASK, (val)) : \ + REG_FIELD_GET(_XELPDP_DDI_CLOCK_SELECT_MASK, (val))) + #define XELPDP_DDI_CLOCK_SELECT_NONE 0x0 #define XELPDP_DDI_CLOCK_SELECT_MAXPCLK 0x8 #define XELPDP_DDI_CLOCK_SELECT_DIV18CLK 0x9 @@ -278,6 +285,9 @@ #define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control)) #define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6) +#define PHY_CMN1_CONTROL(tx, control) (0x800 + ((tx) - 1) * 0x200 + (control)) +#define CONTROL0_MAC_TRANSMIT_LFPS REG_BIT(1) + /* C20 Registers */ #define PHY_C20_WR_ADDRESS_L 0xC02 #define PHY_C20_WR_ADDRESS_H 0xC03 diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index b48ed5df7a96..cbd1060e9664 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -30,11 +30,13 @@ #include <drm/display/drm_dp_helper.h> #include <drm/display/drm_scdc_helper.h> +#include <drm/drm_print.h> #include <drm/drm_privacy_screen_consumer.h> -#include "i915_drv.h" #include "i915_reg.h" +#include "i915_utils.h" #include "icl_dsi.h" +#include "intel_alpm.h" #include "intel_audio.h" #include "intel_audio_regs.h" #include "intel_backlight.h" @@ -48,6 +50,7 @@ #include "intel_ddi_buf_trans.h" #include "intel_de.h" #include "intel_display_power.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dkl_phy.h" #include "intel_dkl_phy_regs.h" @@ -234,7 +237,7 @@ static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) port_name(port)); } -static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) +static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll) { switch (pll->info->id) { case DPLL_ID_WRPLL1: @@ -258,7 +261,7 @@ static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll *pll = crtc_state->intel_dpll; int clock = crtc_state->port_clock; const enum intel_dpll_id id = pll->info->id; @@ -1559,7 +1562,7 @@ static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t return !(intel_de_read(display, reg) & clk_off); } -static struct intel_shared_dpll * +static struct intel_dpll * _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, u32 clk_sel_mask, u32 clk_sel_shift) { @@ -1567,14 +1570,14 @@ _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift; - return intel_get_shared_dpll_by_id(display, id); + return intel_get_dpll_by_id(display, id); } static void adls_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll *pll = crtc_state->intel_dpll; enum phy phy = intel_encoder_to_phy(encoder); if (drm_WARN_ON(display->drm, !pll)) @@ -1604,7 +1607,7 @@ static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } -static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) +static struct intel_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); @@ -1618,7 +1621,7 @@ static void rkl_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll *pll = crtc_state->intel_dpll; enum phy phy = intel_encoder_to_phy(encoder); if (drm_WARN_ON(display->drm, !pll)) @@ -1648,7 +1651,7 @@ static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } -static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) +static struct intel_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); @@ -1662,7 +1665,7 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll *pll = crtc_state->intel_dpll; enum phy phy = intel_encoder_to_phy(encoder); if (drm_WARN_ON(display->drm, !pll)) @@ -1701,7 +1704,7 @@ static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } -static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) +static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); @@ -1721,14 +1724,14 @@ static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) if (phy >= PHY_C) id += DPLL_ID_DG1_DPLL2; - return intel_get_shared_dpll_by_id(display, id); + return intel_get_dpll_by_id(display, id); } static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll *pll = crtc_state->intel_dpll; enum phy phy = intel_encoder_to_phy(encoder); if (drm_WARN_ON(display->drm, !pll)) @@ -1758,7 +1761,7 @@ static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); } -struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) +struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); @@ -1772,7 +1775,7 @@ static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll *pll = crtc_state->intel_dpll; enum port port = encoder->port; if (drm_WARN_ON(display->drm, !pll)) @@ -1815,7 +1818,7 @@ static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll *pll = crtc_state->intel_dpll; enum tc_port tc_port = intel_encoder_to_tc(encoder); enum port port = encoder->port; @@ -1866,7 +1869,7 @@ static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); } -static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) +static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum tc_port tc_port = intel_encoder_to_tc(encoder); @@ -1893,10 +1896,10 @@ static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode return NULL; } - return intel_get_shared_dpll_by_id(display, id); + return intel_get_dpll_by_id(display, id); } -static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) +static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder->base.dev); enum intel_dpll_id id; @@ -1916,14 +1919,14 @@ static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) return NULL; } - return intel_get_shared_dpll_by_id(display, id); + return intel_get_dpll_by_id(display, id); } static void skl_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll *pll = crtc_state->intel_dpll; enum port port = encoder->port; if (drm_WARN_ON(display->drm, !pll)) @@ -1965,7 +1968,7 @@ static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); } -static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) +static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; @@ -1984,14 +1987,14 @@ static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); - return intel_get_shared_dpll_by_id(display, id); + return intel_get_dpll_by_id(display, id); } void hsw_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll *pll = crtc_state->intel_dpll; enum port port = encoder->port; if (drm_WARN_ON(display->drm, !pll)) @@ -2016,7 +2019,7 @@ bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; } -static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) +static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; @@ -2051,7 +2054,7 @@ static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) return NULL; } - return intel_get_shared_dpll_by_id(display, id); + return intel_get_dpll_by_id(display, id); } void intel_ddi_enable_clock(struct intel_encoder *encoder, @@ -2758,7 +2761,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, * 4. Enable the port PLL. * * The PLL enabling itself was already done before this function by - * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only + * hsw_crtc_enable()->intel_enable_dpll(). We need only * configure the PLL to port mapping here. */ intel_ddi_enable_clock(encoder, crtc_state); @@ -3505,9 +3508,6 @@ static void intel_ddi_enable(struct intel_atomic_state *state, intel_vrr_transcoder_enable(crtc_state); - /* Enable/Disable DP2.0 SDP split config before transcoder */ - intel_audio_sdp_split_update(crtc_state); - /* 128b/132b SST */ if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); @@ -3553,6 +3553,7 @@ static void intel_ddi_disable_dp(struct intel_atomic_state *state, intel_dp->link.active = false; intel_psr_disable(intel_dp, old_crtc_state); + intel_alpm_disable(intel_dp); intel_edp_backlight_off(old_conn_state); /* Disable the decompression in DP Sink */ intel_dp_sink_disable_decompression(state, @@ -3647,7 +3648,7 @@ void intel_ddi_update_active_dpll(struct intel_atomic_state *state, for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, intel_crtc_joined_pipe_mask(crtc_state)) - intel_update_active_dpll(state, pipe_crtc, encoder); + intel_dpll_update_active(state, pipe_crtc, encoder); } /* @@ -3740,6 +3741,18 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, intel_ddi_buf_enable(encoder, intel_dp->DP); intel_dp->DP |= DDI_BUF_CTL_ENABLE; + + /* + * 6.k If AUX-Less ALPM is going to be enabled: + * i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL here + */ + intel_alpm_port_configure(intel_dp, crtc_state); + + /* + * ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE + * register + */ + intel_lnl_mac_transmit_lfps(encoder, crtc_state); } static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, @@ -4184,7 +4197,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, void intel_ddi_get_clock(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, - struct intel_shared_dpll *pll) + struct intel_dpll *pll) { struct intel_display *display = to_intel_display(encoder); enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; @@ -4200,7 +4213,7 @@ void intel_ddi_get_clock(struct intel_encoder *encoder, icl_set_active_port_dpll(crtc_state, port_dpll_id); - crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll, + crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, &crtc_state->dpll_hw_state); } @@ -4254,7 +4267,7 @@ static void icl_ddi_combo_get_config(struct intel_encoder *encoder, intel_ddi_get_config(encoder, crtc_state); } -static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) +static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) { return pll->info->id == DPLL_ID_ICL_TBTPLL; } @@ -4264,7 +4277,7 @@ icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; + const struct intel_dpll *pll = crtc_state->intel_dpll; if (drm_WARN_ON(display->drm, !pll)) return ICL_PORT_DPLL_DEFAULT; @@ -4287,7 +4300,7 @@ intel_ddi_port_pll_type(struct intel_encoder *encoder, static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, - struct intel_shared_dpll *pll) + struct intel_dpll *pll) { struct intel_display *display = to_intel_display(encoder); enum icl_port_dpll_id port_dpll_id; @@ -4310,10 +4323,10 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, icl_set_active_port_dpll(crtc_state, port_dpll_id); - if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) + if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll)) crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port); else - crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll, + crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, &crtc_state->dpll_hw_state); } @@ -4902,9 +4915,7 @@ static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port) static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - - if (HAS_PCH_TGP(dev_priv)) + if (HAS_PCH_TGP(display)) return tgl_hpd_pin(display, port); if (port >= PORT_TC1) @@ -4923,12 +4934,10 @@ static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port) static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - if (port == PORT_D) return HPD_PORT_A; - if (HAS_PCH_TGP(dev_priv)) + if (HAS_PCH_TGP(display)) return icl_hpd_pin(display, port); return HPD_PORT_A + port - PORT_A; @@ -4936,9 +4945,7 @@ static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port) static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - - if (HAS_PCH_TGP(dev_priv)) + if (HAS_PCH_TGP(display)) return icl_hpd_pin(display, port); return HPD_PORT_A + port - PORT_A; diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index 353eb04079e9..f6f511bb0431 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -16,9 +16,9 @@ struct intel_crtc; struct intel_crtc_state; struct intel_display; struct intel_dp; +struct intel_dpll; struct intel_dpll_hw_state; struct intel_encoder; -struct intel_shared_dpll; enum pipe; enum port; enum transcoder; @@ -40,7 +40,7 @@ void intel_ddi_enable_clock(struct intel_encoder *encoder, void intel_ddi_disable_clock(struct intel_encoder *encoder); void intel_ddi_get_clock(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, - struct intel_shared_dpll *pll); + struct intel_dpll *pll); void hsw_ddi_enable_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void hsw_ddi_disable_clock(struct intel_encoder *encoder); @@ -50,7 +50,7 @@ intel_ddi_port_pll_type(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void hsw_ddi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state); -struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder); +struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder); void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port); diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h index 655467a6ba87..9ecdcf6b73e4 100644 --- a/drivers/gpu/drm/i915/display/intel_de.h +++ b/drivers/gpu/drm/i915/display/intel_de.h @@ -6,7 +6,6 @@ #ifndef __INTEL_DE_H__ #define __INTEL_DE_H__ -#include "intel_display_conversion.h" #include "intel_display_core.h" #include "intel_dmc_wl.h" #include "intel_dsb.h" @@ -19,7 +18,7 @@ static inline struct intel_uncore *__to_uncore(struct intel_display *display) } static inline u32 -__intel_de_read(struct intel_display *display, i915_reg_t reg) +intel_de_read(struct intel_display *display, i915_reg_t reg) { u32 val; @@ -31,7 +30,6 @@ __intel_de_read(struct intel_display *display, i915_reg_t reg) return val; } -#define intel_de_read(p,...) __intel_de_read(__to_intel_display(p), __VA_ARGS__) static inline u8 intel_de_read8(struct intel_display *display, i915_reg_t reg) @@ -66,7 +64,7 @@ intel_de_read64_2x32(struct intel_display *display, } static inline void -__intel_de_posting_read(struct intel_display *display, i915_reg_t reg) +intel_de_posting_read(struct intel_display *display, i915_reg_t reg) { intel_dmc_wl_get(display, reg); @@ -74,10 +72,9 @@ __intel_de_posting_read(struct intel_display *display, i915_reg_t reg) intel_dmc_wl_put(display, reg); } -#define intel_de_posting_read(p,...) __intel_de_posting_read(__to_intel_display(p), __VA_ARGS__) static inline void -__intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val) +intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val) { intel_dmc_wl_get(display, reg); @@ -85,7 +82,6 @@ __intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val) intel_dmc_wl_put(display, reg); } -#define intel_de_write(p,...) __intel_de_write(__to_intel_display(p), __VA_ARGS__) static inline u32 __intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg, @@ -95,8 +91,7 @@ __intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg, } static inline u32 -__intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, - u32 set) +intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set) { u32 val; @@ -108,15 +103,14 @@ __intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, return val; } -#define intel_de_rmw(p,...) __intel_de_rmw(__to_intel_display(p), __VA_ARGS__) static inline int __intel_de_wait_for_register_nowl(struct intel_display *display, i915_reg_t reg, - u32 mask, u32 value, unsigned int timeout) + u32 mask, u32 value, unsigned int timeout_ms) { return intel_wait_for_register(__to_uncore(display), reg, mask, - value, timeout); + value, timeout_ms); } static inline int @@ -131,14 +125,14 @@ __intel_de_wait_for_register_atomic_nowl(struct intel_display *display, static inline int intel_de_wait(struct intel_display *display, i915_reg_t reg, - u32 mask, u32 value, unsigned int timeout) + u32 mask, u32 value, unsigned int timeout_ms) { int ret; intel_dmc_wl_get(display, reg); ret = __intel_de_wait_for_register_nowl(display, reg, mask, value, - timeout); + timeout_ms); intel_dmc_wl_put(display, reg); @@ -147,14 +141,14 @@ intel_de_wait(struct intel_display *display, i915_reg_t reg, static inline int intel_de_wait_fw(struct intel_display *display, i915_reg_t reg, - u32 mask, u32 value, unsigned int timeout) + u32 mask, u32 value, unsigned int timeout_ms, u32 *out_value) { int ret; intel_dmc_wl_get(display, reg); ret = intel_wait_for_register_fw(__to_uncore(display), reg, mask, - value, timeout); + value, timeout_ms, out_value); intel_dmc_wl_put(display, reg); @@ -182,16 +176,16 @@ intel_de_wait_custom(struct intel_display *display, i915_reg_t reg, static inline int intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg, - u32 mask, unsigned int timeout) + u32 mask, unsigned int timeout_ms) { - return intel_de_wait(display, reg, mask, mask, timeout); + return intel_de_wait(display, reg, mask, mask, timeout_ms); } static inline int intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg, - u32 mask, unsigned int timeout) + u32 mask, unsigned int timeout_ms) { - return intel_de_wait(display, reg, mask, 0, timeout); + return intel_de_wait(display, reg, mask, 0, timeout_ms); } /* diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index db524d01e574..6ec786198f43 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -55,6 +55,7 @@ #include "i9xx_plane.h" #include "i9xx_plane_regs.h" #include "i9xx_wm.h" +#include "intel_alpm.h" #include "intel_atomic.h" #include "intel_atomic_plane.h" #include "intel_audio.h" @@ -66,13 +67,14 @@ #include "intel_crt.h" #include "intel_crtc.h" #include "intel_crtc_state_dump.h" +#include "intel_cursor.h" #include "intel_cursor_regs.h" #include "intel_cx0_phy.h" -#include "intel_cursor.h" #include "intel_ddi.h" #include "intel_de.h" #include "intel_display_driver.h" #include "intel_display_power.h" +#include "intel_display_regs.h" #include "intel_display_rpm.h" #include "intel_display_types.h" #include "intel_dmc.h" @@ -104,7 +106,6 @@ #include "intel_panel.h" #include "intel_pch_display.h" #include "intel_pch_refclk.h" -#include "intel_pcode.h" #include "intel_pfit.h" #include "intel_pipe_crc.h" #include "intel_plane_initial.h" @@ -139,46 +140,47 @@ static void bdw_set_pipe_misc(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state); /* returns HPLL frequency in kHz */ -int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) +int vlv_get_hpll_vco(struct drm_device *drm) { int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; /* Obtain SKU information */ - hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & + hpll_freq = vlv_cck_read(drm, CCK_FUSE_REG) & CCK_FUSE_HPLL_FREQ_MASK; return vco_freq[hpll_freq] * 1000; } -int vlv_get_cck_clock(struct drm_i915_private *dev_priv, +int vlv_get_cck_clock(struct drm_device *drm, const char *name, u32 reg, int ref_freq) { u32 val; int divider; - val = vlv_cck_read(dev_priv, reg); + val = vlv_cck_read(drm, reg); divider = val & CCK_FREQUENCY_VALUES; - drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != + drm_WARN(drm, (val & CCK_FREQUENCY_STATUS) != (divider << CCK_FREQUENCY_STATUS_SHIFT), "%s change in progress\n", name); return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); } -int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, +int vlv_get_cck_clock_hpll(struct drm_device *drm, const char *name, u32 reg) { + struct drm_i915_private *dev_priv = to_i915(drm); int hpll; - vlv_cck_get(dev_priv); + vlv_cck_get(drm); if (dev_priv->hpll_freq == 0) - dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); + dev_priv->hpll_freq = vlv_get_hpll_vco(drm); - hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); + hpll = vlv_get_cck_clock(drm, name, reg, dev_priv->hpll_freq); - vlv_cck_put(dev_priv); + vlv_cck_put(drm); return hpll; } @@ -190,7 +192,7 @@ void intel_update_czclk(struct intel_display *display) if (!display->platform.valleyview && !display->platform.cherryview) return; - dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", + dev_priv->czclk_freq = vlv_get_cck_clock_hpll(display->drm, "czclk", CCK_CZ_CLOCK_CONTROL); drm_dbg_kms(display->drm, "CZ clock rate: %d kHz\n", dev_priv->czclk_freq); @@ -1043,14 +1045,13 @@ static void intel_post_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *dev_priv = to_i915(state->base.dev); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; - intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); + intel_frontbuffer_flip(display, new_crtc_state->fb_bits); if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) intel_update_watermarks(display); @@ -1079,6 +1080,8 @@ static void intel_post_plane_update(struct intel_atomic_state *state, if (audio_enabling(old_crtc_state, new_crtc_state)) intel_encoders_audio_enable(state, crtc); + intel_alpm_post_plane_update(state, crtc); + intel_psr_post_plane_update(state, crtc); } @@ -1174,6 +1177,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; + intel_alpm_pre_plane_update(state, crtc); intel_psr_pre_plane_update(state, crtc); if (intel_crtc_vrr_disabling(state, crtc)) { @@ -1281,7 +1285,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, static void intel_crtc_disable_planes(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); unsigned int update_mask = new_crtc_state->update_planes; @@ -1303,7 +1307,7 @@ static void intel_crtc_disable_planes(struct intel_atomic_state *state, fb_bits |= plane->frontbuffer_bit; } - intel_frontbuffer_flip(dev_priv, fb_bits); + intel_frontbuffer_flip(display, fb_bits); } static void intel_encoders_update_prepare(struct intel_atomic_state *state) @@ -1322,7 +1326,7 @@ static void intel_encoders_update_prepare(struct intel_atomic_state *state) if (intel_crtc_needs_modeset(new_crtc_state)) continue; - new_crtc_state->shared_dpll = old_crtc_state->shared_dpll; + new_crtc_state->intel_dpll = old_crtc_state->intel_dpll; new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; } } @@ -1510,7 +1514,6 @@ static void ilk_crtc_enable(struct intel_atomic_state *state, struct intel_display *display = to_intel_display(crtc); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; if (drm_WARN_ON(display->drm, crtc->active)) @@ -1562,7 +1565,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state, intel_encoders_enable(state, crtc); - if (HAS_PCH_CPT(dev_priv)) + if (HAS_PCH_CPT(display)) intel_wait_for_pipe_scanline_moving(crtc); /* @@ -1661,8 +1664,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, intel_encoders_pre_pll_enable(state, crtc); - if (new_crtc_state->shared_dpll) - intel_enable_shared_dpll(new_crtc_state); + if (new_crtc_state->intel_dpll) + intel_dpll_enable(new_crtc_state); intel_encoders_pre_enable(state, crtc); @@ -1791,7 +1794,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state, intel_encoders_disable(state, crtc); intel_encoders_post_disable(state, crtc); - intel_disable_shared_dpll(old_crtc_state); + intel_dpll_disable(old_crtc_state); intel_encoders_post_pll_disable(state, crtc); @@ -1957,7 +1960,7 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, if (HAS_DDI(display) && crtc_state->has_audio) set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); - if (crtc_state->shared_dpll) + if (crtc_state->intel_dpll) set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); if (crtc_state->dsc.compression_enable) @@ -2404,14 +2407,6 @@ static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) return 0; } -static bool intel_crtc_needs_wa_14015401596(const struct intel_crtc_state *crtc_state) -{ - struct intel_display *display = to_intel_display(crtc_state); - - return intel_vrr_possible(crtc_state) && crtc_state->has_psr && - IS_DISPLAY_VER(display, 13, 14); -} - static int intel_crtc_vblank_delay(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); @@ -2420,9 +2415,7 @@ static int intel_crtc_vblank_delay(const struct intel_crtc_state *crtc_state) if (!HAS_DSB(display)) return 0; - /* Wa_14015401596 */ - if (intel_crtc_needs_wa_14015401596(crtc_state)) - vblank_delay = max(vblank_delay, 1); + vblank_delay = max(vblank_delay, intel_psr_min_vblank_delay(crtc_state)); return vblank_delay; } @@ -2534,15 +2527,13 @@ intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes, void intel_panel_sanitize_ssc(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - /* * There may be no VBT; and if the BIOS enabled SSC we can * just keep using it to avoid unnecessary flicker. Whereas if the * BIOS isn't using it, don't assume it will work even if the VBT * indicates as much. */ - if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { + if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) { bool bios_lvds_use_ssc = intel_de_read(display, PCH_DREF_CONTROL) & DREF_SSC1_ENABLE; @@ -2724,6 +2715,19 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta intel_de_write(display, TRANS_VTOTAL(display, pipe), VACTIVE(crtc_vdisplay - 1) | VTOTAL(crtc_vtotal - 1)); + + if (DISPLAY_VER(display) >= 30) { + /* + * Address issues for resolutions with high refresh rate that + * have small Hblank, specifically where Hblank is smaller than + * one MTP. Simulations indicate this will address the + * jitter issues that currently causes BS to be immediately + * followed by BE which DPRX devices are unable to handle. + * https://groups.vesa.org/wg/DP/document/20494 + */ + intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder), + crtc_state->min_hblank); + } } static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state) @@ -2867,6 +2871,10 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc, adjusted_mode->crtc_vdisplay + intel_de_read(display, TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder)); + + if (DISPLAY_VER(display) >= 30) + pipe_config->min_hblank = intel_de_read(display, + DP_MIN_HBLANK_CTL(cpu_transcoder)); } static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) @@ -4218,7 +4226,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, crtc_state->update_wm_post = true; if (intel_crtc_needs_modeset(crtc_state)) { - ret = intel_dpll_crtc_get_shared_dpll(state, crtc); + ret = intel_dpll_crtc_get_dpll(state, crtc); if (ret) return ret; } @@ -4311,6 +4319,22 @@ compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, return 0; } +int intel_display_min_pipe_bpp(void) +{ + return 6 * 3; +} + +int intel_display_max_pipe_bpp(struct intel_display *display) +{ + if (display->platform.g4x || display->platform.valleyview || + display->platform.cherryview) + return 10*3; + else if (DISPLAY_VER(display) >= 5) + return 12*3; + else + return 8*3; +} + static int compute_baseline_pipe_bpp(struct intel_atomic_state *state, struct intel_crtc *crtc) @@ -4320,17 +4344,9 @@ compute_baseline_pipe_bpp(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); struct drm_connector *connector; struct drm_connector_state *connector_state; - int bpp, i; - - if (display->platform.g4x || display->platform.valleyview || - display->platform.cherryview) - bpp = 10*3; - else if (DISPLAY_VER(display) >= 5) - bpp = 12*3; - else - bpp = 8*3; + int i; - crtc_state->pipe_bpp = bpp; + crtc_state->pipe_bpp = intel_display_max_pipe_bpp(display); /* Clamp display bpp to connector max bpp */ for_each_new_connector_in_state(&state->base, connector, connector_state, i) { @@ -4494,7 +4510,7 @@ copy_joiner_crtc_state_modeset(struct intel_atomic_state *state, /* preserve some things from the slave's original crtc state */ saved_state->uapi = secondary_crtc_state->uapi; saved_state->scaler_state = secondary_crtc_state->scaler_state; - saved_state->shared_dpll = secondary_crtc_state->shared_dpll; + saved_state->intel_dpll = secondary_crtc_state->intel_dpll; saved_state->crc_enabled = secondary_crtc_state->crc_enabled; intel_crtc_free_hw_state(secondary_crtc_state); @@ -4557,7 +4573,7 @@ intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, saved_state->uapi = crtc_state->uapi; saved_state->inherited = crtc_state->inherited; saved_state->scaler_state = crtc_state->scaler_state; - saved_state->shared_dpll = crtc_state->shared_dpll; + saved_state->intel_dpll = crtc_state->intel_dpll; saved_state->dpll_hw_state = crtc_state->dpll_hw_state; memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, sizeof(saved_state->icl_port_dplls)); @@ -5217,6 +5233,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(lane_count); PIPE_CONF_CHECK_X(lane_lat_optim_mask); + PIPE_CONF_CHECK_I(min_hblank); + if (HAS_DOUBLE_BUFFERED_M_N(display)) { if (!fastset || !pipe_config->update_m_n) PIPE_CONF_CHECK_M_N(dp_m_n); @@ -5309,7 +5327,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(double_wide); if (display->dpll.mgr) - PIPE_CONF_CHECK_P(shared_dpll); + PIPE_CONF_CHECK_P(intel_dpll); /* FIXME convert everything over the dpll_mgr */ if (display->dpll.mgr || HAS_GMCH(display)) @@ -6021,22 +6039,16 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in if (!plane->async_flip) continue; - if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->modifier)) { + if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->format->format, + new_plane_state->hw.fb->modifier)) { drm_dbg_kms(display->drm, - "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n", + "[PLANE:%d:%s] pixel format %p4cc / modifier 0x%llx does not support async flip\n", plane->base.base.id, plane->base.name, + &new_plane_state->hw.fb->format->format, new_plane_state->hw.fb->modifier); return -EINVAL; } - if (intel_format_info_is_yuv_semiplanar(new_plane_state->hw.fb->format, - new_plane_state->hw.fb->modifier)) { - drm_dbg_kms(display->drm, - "[PLANE:%d:%s] Planar formats do not support async flips\n", - plane->base.base.id, plane->base.name); - return -EINVAL; - } - /* * We turn the first async flip request into a sync flip * so that we can reconfigure the plane (eg. change modifier). @@ -6425,7 +6437,7 @@ int intel_atomic_check(struct drm_device *dev, any_ms = true; - intel_release_shared_dplls(state, crtc); + intel_dpll_release(state, crtc); } if (any_ms && !check_digital_port_conflicts(state)) { @@ -6547,7 +6559,6 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, { struct intel_display *display = to_intel_display(new_crtc_state); struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); /* * Update pipe size and adjust fitter if needed: the reason for this is @@ -6563,7 +6574,7 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, if (DISPLAY_VER(display) >= 9) { if (new_crtc_state->pch_pfit.enabled) skl_pfit_enable(new_crtc_state); - } else if (HAS_PCH_SPLIT(dev_priv)) { + } else if (HAS_PCH_SPLIT(display)) { if (new_crtc_state->pch_pfit.enabled) ilk_pfit_enable(new_crtc_state); else if (old_crtc_state->pch_pfit.enabled) @@ -6628,6 +6639,7 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state, struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + bool modeset = intel_crtc_needs_modeset(new_crtc_state); drm_WARN_ON(display->drm, new_crtc_state->use_dsb); @@ -6636,10 +6648,15 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state, * get a catastrophic underrun even if the two operations * end up happening in two different frames. */ - if (DISPLAY_VER(display) >= 9 && - !intel_crtc_needs_modeset(new_crtc_state)) + if (DISPLAY_VER(display) >= 9 && !modeset) skl_detach_scalers(NULL, new_crtc_state); + if (!modeset && + intel_crtc_needs_color_update(new_crtc_state) && + !intel_color_uses_dsb(new_crtc_state) && + HAS_DOUBLE_BUFFERED_LUT(display)) + intel_color_load_luts(new_crtc_state); + if (intel_crtc_vrr_enabling(state, crtc)) intel_vrr_enable(new_crtc_state); } @@ -6664,6 +6681,8 @@ static void intel_enable_crtc(struct intel_atomic_state *state, intel_crtc_update_active_timings(pipe_crtc_state, false); } + intel_psr_notify_pipe_change(state, crtc, true); + display->funcs.display->crtc_enable(state, crtc); /* vblanks work again, re-enable pipe CRC. */ @@ -6729,13 +6748,13 @@ static void intel_update_crtc(struct intel_atomic_state *state, if (new_crtc_state->use_dsb) { intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->dsb_event); - intel_dsb_commit(new_crtc_state->dsb_commit, false); + intel_dsb_commit(new_crtc_state->dsb_commit); } else { /* Perform vblank evasion around commit operation */ intel_pipe_update_start(state, crtc); if (new_crtc_state->dsb_commit) - intel_dsb_commit(new_crtc_state->dsb_commit, false); + intel_dsb_commit(new_crtc_state->dsb_commit); commit_pipe_pre_planes(state, crtc); @@ -6783,6 +6802,8 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state, intel_crtc_joined_pipe_mask(old_crtc_state)) intel_crtc_disable_pipe_crc(pipe_crtc); + intel_psr_notify_pipe_change(state, crtc, false); + display->funcs.display->crtc_disable(state, crtc); for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, @@ -7178,7 +7199,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - if (!new_crtc_state->use_dsb && !new_crtc_state->dsb_color_vblank) + if (!new_crtc_state->use_dsb && !new_crtc_state->dsb_color) return; /* @@ -7224,20 +7245,24 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, if (DISPLAY_VER(display) >= 9) skl_detach_scalers(new_crtc_state->dsb_commit, new_crtc_state); - - if (!new_crtc_state->dsb_color_vblank) { - intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1); - - intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); - intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit); - intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state); - intel_dsb_interrupt(new_crtc_state->dsb_commit); - } } - if (new_crtc_state->dsb_color_vblank) + if (intel_color_uses_chained_dsb(new_crtc_state)) intel_dsb_chain(state, new_crtc_state->dsb_commit, - new_crtc_state->dsb_color_vblank, true); + new_crtc_state->dsb_color, true); + else if (intel_color_uses_gosub_dsb(new_crtc_state)) + intel_dsb_gosub(new_crtc_state->dsb_commit, + new_crtc_state->dsb_color); + + if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(new_crtc_state)) { + intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1); + + intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); + intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit); + intel_vrr_check_push_sent(new_crtc_state->dsb_commit, + new_crtc_state); + intel_dsb_interrupt(new_crtc_state->dsb_commit); + } intel_dsb_finish(new_crtc_state->dsb_commit); } @@ -7426,7 +7451,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) * * FIXME get rid of this funny new->old swapping */ - old_crtc_state->dsb_color_vblank = fetch_and_zero(&new_crtc_state->dsb_color_vblank); + old_crtc_state->dsb_color = fetch_and_zero(&new_crtc_state->dsb_color); old_crtc_state->dsb_commit = fetch_and_zero(&new_crtc_state->dsb_commit); } @@ -7519,7 +7544,7 @@ static int intel_atomic_swap_state(struct intel_atomic_state *state) intel_atomic_swap_global_state(state); - intel_shared_dpll_swap_state(state); + intel_dpll_swap_state(state); intel_atomic_track_fbs(state); @@ -7639,15 +7664,13 @@ static bool ilk_has_edp_a(struct intel_display *display) static bool intel_ddi_crt_present(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - if (DISPLAY_VER(display) >= 9) return false; if (display->platform.haswell_ult || display->platform.broadwell_ult) return false; - if (HAS_PCH_LPT_H(dev_priv) && + if (HAS_PCH_LPT_H(display) && intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) return false; @@ -7669,7 +7692,6 @@ bool assert_port_valid(struct intel_display *display, enum port port) void intel_setup_outputs(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_encoder *encoder; bool dpd_is_edp = false; @@ -7686,7 +7708,7 @@ void intel_setup_outputs(struct intel_display *display) if (display->platform.geminilake || display->platform.broxton) vlv_dsi_init(display); - } else if (HAS_PCH_SPLIT(dev_priv)) { + } else if (HAS_PCH_SPLIT(display)) { int found; /* @@ -8054,13 +8076,11 @@ static const struct intel_display_funcs i9xx_display_funcs = { */ void intel_init_display_hooks(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - if (DISPLAY_VER(display) >= 9) { display->funcs.display = &skl_display_funcs; } else if (HAS_DDI(display)) { display->funcs.display = &ddi_display_funcs; - } else if (HAS_PCH_SPLIT(dev_priv)) { + } else if (HAS_PCH_SPLIT(display)) { display->funcs.display = &pch_split_display_funcs; } else if (display->platform.cherryview || display->platform.valleyview) { diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 3b54a62c290a..37e2ab301a80 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -30,38 +30,21 @@ #include "i915_reg_defs.h" #include "intel_display_limits.h" -enum drm_scaling_filter; -struct dpll; struct drm_atomic_state; -struct drm_connector; struct drm_device; struct drm_display_mode; struct drm_encoder; -struct drm_file; -struct drm_format_info; -struct drm_framebuffer; -struct drm_i915_private; -struct drm_mode_fb_cmd2; struct drm_modeset_acquire_ctx; -struct drm_plane; -struct drm_plane_state; -struct i915_address_space; -struct i915_gtt_view; struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; struct intel_digital_port; struct intel_display; -struct intel_dp; struct intel_encoder; -struct intel_initial_plane_config; struct intel_link_m_n; struct intel_plane; struct intel_plane_state; struct intel_power_domain_mask; -struct pci_dev; -struct work_struct; - #define pipe_name(p) ((p) + 'A') @@ -452,10 +435,10 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state); void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state); void i830_enable_pipe(struct intel_display *display, enum pipe pipe); void i830_disable_pipe(struct intel_display *display, enum pipe pipe); -int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); -int vlv_get_cck_clock(struct drm_i915_private *dev_priv, +int vlv_get_hpll_vco(struct drm_device *drm); +int vlv_get_cck_clock(struct drm_device *drm, const char *name, u32 reg, int ref_freq); -int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, +int vlv_get_cck_clock_hpll(struct drm_device *drm, const char *name, u32 reg); bool intel_has_pending_fb_unpin(struct intel_display *display); void intel_encoder_destroy(struct drm_encoder *encoder); @@ -524,6 +507,9 @@ void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state); bool intel_crtc_vrr_disabling(struct intel_atomic_state *state, struct intel_crtc *crtc); +int intel_display_min_pipe_bpp(void); +int intel_display_max_pipe_bpp(struct intel_display *display); + /* modesetting */ int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state, const char *reason, u8 pipe_mask); diff --git a/drivers/gpu/drm/i915/display/intel_display_conversion.c b/drivers/gpu/drm/i915/display/intel_display_conversion.c index 0578b68404da..4d565935e2cc 100644 --- a/drivers/gpu/drm/i915/display/intel_display_conversion.c +++ b/drivers/gpu/drm/i915/display/intel_display_conversion.c @@ -2,10 +2,11 @@ /* Copyright © 2024 Intel Corporation */ #include "i915_drv.h" +#include "intel_display_conversion.h" struct intel_display *__i915_to_display(struct drm_i915_private *i915) { - return &i915->display; + return i915->display; } struct intel_display *__drm_to_display(struct drm_device *drm) diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index eb6d6f2d0f75..32cb0e59c81e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -21,17 +21,15 @@ #include "intel_display_limits.h" #include "intel_display_params.h" #include "intel_display_power.h" +#include "intel_dmc_wl.h" #include "intel_dpll_mgr.h" #include "intel_fbc.h" #include "intel_global_state.h" #include "intel_gmbus.h" #include "intel_opregion.h" -#include "intel_dmc_wl.h" +#include "intel_pch.h" #include "intel_wm_types.h" -struct task_struct; - -struct drm_i915_private; struct drm_property; struct drm_property_blob; struct i915_audio_component; @@ -44,7 +42,7 @@ struct intel_color_funcs; struct intel_crtc; struct intel_crtc_state; struct intel_dmc; -struct intel_dpll_funcs; +struct intel_dpll_global_funcs; struct intel_dpll_mgr; struct intel_fbdev; struct intel_fdi_funcs; @@ -52,6 +50,7 @@ struct intel_hotplug_funcs; struct intel_initial_plane_config; struct intel_opregion; struct intel_overlay; +struct task_struct; /* Amount of SAGV/QGV points, BSpec precisely defines this */ #define I915_NUM_QGV_POINTS 8 @@ -123,11 +122,11 @@ struct intel_audio { * intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per * dpll, because on some platforms plls share registers. */ -struct intel_dpll { +struct intel_dpll_global { struct mutex lock; - int num_shared_dpll; - struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; + int num_dpll; + struct intel_dpll dplls[I915_NUM_PLLS]; const struct intel_dpll_mgr *mgr; struct { @@ -180,7 +179,7 @@ struct intel_hotplug { /* * Queuing of hotplug_work, reenable_work and poll_init_work is - * enabled. Protected by drm_i915_private::irq_lock. + * enabled. Protected by intel_display::irq::lock. */ bool detection_work_enabled; @@ -289,6 +288,9 @@ struct intel_display { /* Platform (and subplatform, if any) identification */ struct intel_display_platforms platform; + /* Intel PCH: where the south display engine lives */ + enum intel_pch pch_type; + /* Display functions */ struct { /* Top level crtc-ish functions */ @@ -298,7 +300,7 @@ struct intel_display { const struct intel_cdclk_funcs *cdclk; /* Display pll funcs */ - const struct intel_dpll_funcs *dpll; + const struct intel_dpll_global_funcs *dpll; /* irq display functions */ const struct intel_hotplug_funcs *hotplug; @@ -426,7 +428,7 @@ struct intel_display { * reused when sending message to gsc cs. * this is only populated post Meteorlake */ - struct intel_hdcp_gsc_message *hdcp_message; + struct intel_hdcp_gsc_context *gsc_context; /* Mutex to protect the above hdcp related values. */ struct mutex hdcp_mutex; } hdcp; @@ -454,6 +456,9 @@ struct intel_display { } ips; struct { + /* protects the irq masks */ + spinlock_t lock; + /* * Most platforms treat the display irq block as an always-on * power domain. vlv/chv can disable it at runtime and need @@ -466,9 +471,9 @@ struct intel_display { /* For i915gm/i945gm vblank irq workaround */ u8 vblank_enabled; - int vblank_wa_num_pipes; + int vblank_enable_count; - struct work_struct vblank_dc_work; + struct work_struct vblank_notify_work; u32 de_irq_mask[I915_MAX_PIPES]; u32 pipestat_irq_mask[I915_MAX_PIPES]; @@ -534,6 +539,11 @@ struct intel_display { } sagv; struct { + /* LPT/WPT IOSF sideband protection */ + struct mutex lock; + } sbi; + + struct { /* * DG2: Mask of PHYs that were not calibrated by the firmware * and should not be used. @@ -565,7 +575,7 @@ struct intel_display { /* Grouping using named structs. Keep sorted. */ struct drm_dp_tunnel_mgr *dp_tunnel_mgr; struct intel_audio audio; - struct intel_dpll dpll; + struct intel_dpll_global dpll; struct intel_fbc *fbc[I915_MAX_FBCS]; struct intel_frontbuffer_tracking fb_tracking; struct intel_hotplug hotplug; @@ -575,6 +585,8 @@ struct intel_display { struct intel_vbt_data vbt; struct intel_dmc_wl wl; struct intel_wm wm; + + struct work_struct psr_dc5_dc6_wa_work; }; #endif /* __INTEL_DISPLAY_CORE_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 4c208fdb9137..ce3f9810c42d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -4,15 +4,16 @@ */ #include <linux/debugfs.h> +#include <linux/string_choices.h> #include <linux/string_helpers.h> #include <drm/drm_debugfs.h> +#include <drm/drm_drv.h> #include <drm/drm_edid.h> +#include <drm/drm_file.h> #include <drm/drm_fourcc.h> #include "hsw_ips.h" -#include "i915_drv.h" -#include "i915_irq.h" #include "i915_reg.h" #include "i9xx_wm_regs.h" #include "intel_alpm.h" @@ -24,6 +25,7 @@ #include "intel_display_debugfs_params.h" #include "intel_display_power.h" #include "intel_display_power_well.h" +#include "intel_display_regs.h" #include "intel_display_rpm.h" #include "intel_display_types.h" #include "intel_dmc.h" @@ -38,6 +40,7 @@ #include "intel_hdcp.h" #include "intel_hdmi.h" #include "intel_hotplug.h" +#include "intel_link_bw.h" #include "intel_panel.h" #include "intel_pps.h" #include "intel_psr.h" @@ -53,10 +56,9 @@ static struct intel_display *node_to_intel_display(struct drm_info_node *node) static int intel_display_caps(struct seq_file *m, void *data) { struct intel_display *display = node_to_intel_display(m->private); - struct drm_i915_private *i915 = to_i915(display->drm); struct drm_printer p = drm_seq_file_printer(m); - drm_printf(&p, "PCH type: %d\n", INTEL_PCH_TYPE(i915)); + drm_printf(&p, "PCH type: %d\n", INTEL_PCH_TYPE(display)); intel_display_device_info_print(DISPLAY_INFO(display), DISPLAY_RUNTIME_INFO(display), &p); @@ -85,7 +87,6 @@ static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) static int i915_sr_status(struct seq_file *m, void *unused) { struct intel_display *display = node_to_intel_display(m->private); - struct drm_i915_private *dev_priv = to_i915(display->drm); intel_wakeref_t wakeref; bool sr_enabled = false; @@ -93,7 +94,7 @@ static int i915_sr_status(struct seq_file *m, void *unused) if (DISPLAY_VER(display) >= 9) /* no global SR status; inspect per-plane WM */; - else if (HAS_PCH_SPLIT(dev_priv)) + else if (HAS_PCH_SPLIT(display)) sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE; else if (display->platform.i965gm || display->platform.g4x || display->platform.i945g || display->platform.i945gm) @@ -558,6 +559,8 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc) seq_printf(m, "\tpipe src=" DRM_RECT_FMT ", dither=%s, bpp=%d\n", DRM_RECT_ARG(&crtc_state->pipe_src), str_yes_no(crtc_state->dither), crtc_state->pipe_bpp); + seq_printf(m, "\tport_clock=%d, lane_count=%d\n", + crtc_state->port_clock, crtc_state->lane_count); intel_scaler_info(m, crtc); @@ -617,7 +620,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused) { struct intel_display *display = node_to_intel_display(m->private); struct drm_printer p = drm_seq_file_printer(m); - struct intel_shared_dpll *pll; + struct intel_dpll *pll; int i; drm_modeset_lock_all(display->drm); @@ -626,7 +629,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused) display->dpll.ref_clks.nssc, display->dpll.ref_clks.ssc); - for_each_shared_dpll(display, pll, i) { + for_each_dpll(display, pll, i) { drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index, pll->info->name, pll->info->id); drm_printf(&p, " pipe_mask: 0x%x, active: 0x%x, on: %s\n", @@ -971,7 +974,7 @@ static ssize_t i915_dsc_fec_support_write(struct file *file, return ret; drm_dbg(display->drm, "Got %s for DSC Enable\n", - (dsc_enable) ? "true" : "false"); + str_true_false(dsc_enable)); intel_dp->force_dsc_en = dsc_enable; *offp += len; @@ -1182,7 +1185,7 @@ static ssize_t i915_dsc_fractional_bpp_write(struct file *file, return ret; drm_dbg(display->drm, "Got %s for DSC Fractional BPP Enable\n", - (dsc_fractional_bpp_enable) ? "true" : "false"); + str_true_false(dsc_fractional_bpp_enable)); intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable; *offp += len; @@ -1324,6 +1327,7 @@ void intel_connector_debugfs_add(struct intel_connector *connector) intel_psr_connector_debugfs_add(connector); intel_alpm_lobf_debugfs_add(connector); intel_dp_link_training_debugfs_add(connector); + intel_link_bw_connector_debugfs_add(connector); if (DISPLAY_VER(display) >= 11 && ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !connector->mst.dp) || diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 738ae522c8f4..a4070f40e26f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -3,11 +3,13 @@ * Copyright © 2023 Intel Corporation */ -#include <drm/intel/pciids.h> -#include <drm/drm_color_mgmt.h> #include <linux/pci.h> -#include "i915_drv.h" +#include <drm/drm_color_mgmt.h> +#include <drm/drm_drv.h> +#include <drm/drm_print.h> +#include <drm/intel/pciids.h> + #include "i915_reg.h" #include "intel_cx0_phy_regs.h" #include "intel_de.h" @@ -16,6 +18,7 @@ #include "intel_display_params.h" #include "intel_display_power.h" #include "intel_display_reg_defs.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_fbc.h" #include "intel_step.h" @@ -1619,13 +1622,17 @@ static void display_platforms_or(struct intel_display_platforms *dst, struct intel_display *intel_display_device_probe(struct pci_dev *pdev) { - struct intel_display *display = to_intel_display(pdev); + struct intel_display *display; const struct intel_display_device_info *info; struct intel_display_ip_ver ip_ver = {}; const struct platform_desc *desc; const struct subplatform_desc *subdesc; enum intel_step step; + display = kzalloc(sizeof(*display), GFP_KERNEL); + if (!display) + return ERR_PTR(-ENOMEM); + /* Add drm device backpointer as early as possible. */ display->drm = pci_get_drvdata(pdev); @@ -1706,12 +1713,15 @@ no_display: void intel_display_device_remove(struct intel_display *display) { + if (!display) + return; + intel_display_params_free(&display->params); + kfree(display); } static void __intel_display_device_info_runtime_init(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(display); enum pipe pipe; @@ -1775,7 +1785,7 @@ static void __intel_display_device_info_runtime_init(struct intel_display *displ goto display_fused_off; } - if (IS_DISPLAY_VER(display, 7, 8) && HAS_PCH_SPLIT(i915)) { + if (IS_DISPLAY_VER(display, 7, 8) && HAS_PCH_SPLIT(display)) { u32 fuse_strap = intel_de_read(display, FUSE_STRAP); u32 sfuse_strap = intel_de_read(display, SFUSE_STRAP); @@ -1790,7 +1800,7 @@ static void __intel_display_device_info_runtime_init(struct intel_display *displ */ if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || - (HAS_PCH_CPT(i915) && + (HAS_PCH_CPT(display) && !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { drm_info(display->drm, "Display fused off, disabling\n"); diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 368b0d3417c2..0ac5484c0043 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -157,12 +157,14 @@ struct intel_display_platforms { #define HAS_DMC(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dmc) #define HAS_DMC_WAKELOCK(__display) (DISPLAY_VER(__display) >= 20) #define HAS_DOUBLE_BUFFERED_M_N(__display) (DISPLAY_VER(__display) >= 9 || (__display)->platform.broadwell) +#define HAS_DOUBLE_BUFFERED_LUT(__display) (DISPLAY_VER(__display) >= 30) #define HAS_DOUBLE_WIDE(__display) (DISPLAY_VER(__display) < 4) #define HAS_DP20(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14) #define HAS_DPT(__display) (DISPLAY_VER(__display) >= 13) #define HAS_DP_MST(__display) (DISPLAY_INFO(__display)->has_dp_mst) #define HAS_DSB(__display) (DISPLAY_INFO(__display)->has_dsb) #define HAS_DSC(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dsc) +#define HAS_DSC_3ENGINES(__display) (DISPLAY_VERx100(__display) == 1401 && HAS_DSC(__display)) #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display)) #define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0) #define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30) @@ -171,6 +173,7 @@ struct intel_display_platforms { #define HAS_GMBUS_BURST_READ(__display) (DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake) #define HAS_GMBUS_IRQ(__display) (DISPLAY_VER(__display) >= 4) #define HAS_GMCH(__display) (DISPLAY_INFO(__display)->has_gmch) +#define HAS_FDI(__display) (IS_DISPLAY_VER((__display), 5, 8) && !HAS_GMCH(__display)) #define HAS_HOTPLUG(__display) (DISPLAY_INFO(__display)->has_hotplug) #define HAS_HW_SAGV_WM(__display) (DISPLAY_VER(__display) >= 13 && !(__display)->platform.dgfx) #define HAS_IPC(__display) (DISPLAY_INFO(__display)->has_ipc) @@ -180,6 +183,7 @@ struct intel_display_platforms { #define HAS_MBUS_JOINING(__display) ((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14) #define HAS_MSO(__display) (DISPLAY_VER(__display) >= 12) #define HAS_OVERLAY(__display) (DISPLAY_INFO(__display)->has_overlay) +#define HAS_PIPEDMC(__display) (DISPLAY_VER(__display) >= 12) #define HAS_PSR(__display) (DISPLAY_INFO(__display)->has_psr) #define HAS_PSR_HW_TRACKING(__display) (DISPLAY_INFO(__display)->has_psr_hw_tracking) #define HAS_PSR2_SEL_FETCH(__display) (DISPLAY_VER(__display) >= 12) diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index efee8925987e..ec799a1773e4 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -27,6 +27,7 @@ #include "intel_cdclk.h" #include "intel_color.h" #include "intel_crtc.h" +#include "intel_display_core.h" #include "intel_display_debugfs.h" #include "intel_display_driver.h" #include "intel_display_irq.h" @@ -54,6 +55,7 @@ #include "intel_plane_initial.h" #include "intel_pmdemand.h" #include "intel_pps.h" +#include "intel_psr.h" #include "intel_quirks.h" #include "intel_vga.h" #include "intel_wm.h" @@ -180,6 +182,9 @@ static void intel_plane_possible_crtcs_init(struct intel_display *display) void intel_display_driver_early_probe(struct intel_display *display) { + /* This must be called before any calls to HAS_PCH_* */ + intel_pch_detect(display); + if (!HAS_DISPLAY(display)) return; @@ -223,6 +228,8 @@ int intel_display_driver_probe_noirq(struct intel_display *display) if (ret) goto cleanup_bios; + intel_psr_dc5_dc6_wa_init(display); + /* FIXME: completely on the wrong abstraction layer */ ret = intel_power_domains_init(display); if (ret < 0) @@ -237,32 +244,52 @@ int intel_display_driver_probe_noirq(struct intel_display *display) intel_dmc_init(display); + display->hotplug.dp_wq = alloc_ordered_workqueue("intel-dp", 0); + if (!display->hotplug.dp_wq) { + ret = -ENOMEM; + goto cleanup_vga_client_pw_domain_dmc; + } + display->wq.modeset = alloc_ordered_workqueue("i915_modeset", 0); + if (!display->wq.modeset) { + ret = -ENOMEM; + goto cleanup_wq_dp; + } + display->wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI | WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); + if (!display->wq.flip) { + ret = -ENOMEM; + goto cleanup_wq_modeset; + } + display->wq.cleanup = alloc_workqueue("i915_cleanup", WQ_HIGHPRI, 0); + if (!display->wq.cleanup) { + ret = -ENOMEM; + goto cleanup_wq_flip; + } intel_mode_config_init(display); ret = intel_cdclk_init(display); if (ret) - goto cleanup_vga_client_pw_domain_dmc; + goto cleanup_wq_cleanup; ret = intel_color_init(display); if (ret) - goto cleanup_vga_client_pw_domain_dmc; + goto cleanup_wq_cleanup; ret = intel_dbuf_init(display); if (ret) - goto cleanup_vga_client_pw_domain_dmc; + goto cleanup_wq_cleanup; ret = intel_bw_init(display); if (ret) - goto cleanup_vga_client_pw_domain_dmc; + goto cleanup_wq_cleanup; ret = intel_pmdemand_init(display); if (ret) - goto cleanup_vga_client_pw_domain_dmc; + goto cleanup_wq_cleanup; intel_init_quirks(display); @@ -270,6 +297,14 @@ int intel_display_driver_probe_noirq(struct intel_display *display) return 0; +cleanup_wq_cleanup: + destroy_workqueue(display->wq.cleanup); +cleanup_wq_flip: + destroy_workqueue(display->wq.flip); +cleanup_wq_modeset: + destroy_workqueue(display->wq.modeset); +cleanup_wq_dp: + destroy_workqueue(display->hotplug.dp_wq); cleanup_vga_client_pw_domain_dmc: intel_dmc_fini(display); intel_power_domains_driver_remove(display); @@ -415,7 +450,6 @@ bool intel_display_driver_check_access(struct intel_display *display) /* part #2: call after irq install, but before gem init */ int intel_display_driver_probe_nogem(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); enum pipe pipe; int ret; @@ -441,7 +475,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display) } intel_plane_possible_crtcs_init(display); - intel_shared_dpll_init(display); + intel_dpll_init(display); intel_fdi_pll_freq_update(display); intel_update_czclk(display); @@ -453,8 +487,6 @@ int intel_display_driver_probe_nogem(struct intel_display *display) intel_hti_init(display); - /* Just disable it once at startup */ - intel_vga_disable(display); intel_setup_outputs(display); ret = intel_dp_tunnel_mgr_init(display); @@ -464,7 +496,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display) intel_display_driver_disable_user_access(display); drm_modeset_lock_all(display->drm); - intel_modeset_setup_hw_state(i915, display->drm->mode_config.acquire_ctx); + intel_modeset_setup_hw_state(display, display->drm->mode_config.acquire_ctx); intel_acpi_assign_connector_fwnodes(display); drm_modeset_unlock_all(display->drm); @@ -525,7 +557,6 @@ int intel_display_driver_probe(struct intel_display *display) void intel_display_driver_register(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS, "i915 display info:"); @@ -552,7 +583,7 @@ void intel_display_driver_register(struct intel_display *display) drm_kms_helper_poll_init(display->drm); intel_hpd_poll_disable(display); - intel_fbdev_setup(i915); + intel_fbdev_setup(display); intel_display_device_info_print(DISPLAY_INFO(display), DISPLAY_RUNTIME_INFO(display), &p); @@ -609,6 +640,7 @@ void intel_display_driver_remove_noirq(struct intel_display *display) intel_gmbus_teardown(display); + destroy_workqueue(display->hotplug.dp_wq); destroy_workqueue(display->wq.flip); destroy_workqueue(display->wq.modeset); destroy_workqueue(display->wq.cleanup); @@ -687,13 +719,11 @@ __intel_display_driver_resume(struct intel_display *display, struct drm_atomic_state *state, struct drm_modeset_acquire_ctx *ctx) { - struct drm_i915_private *i915 = to_i915(display->drm); struct drm_crtc_state *crtc_state; struct drm_crtc *crtc; int ret, i; - intel_modeset_setup_hw_state(i915, ctx); - intel_vga_redisable(display); + intel_modeset_setup_hw_state(display, ctx); if (!state) return 0; diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index d2a35e3630b1..8d0dcf252bed 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -5,7 +5,6 @@ #include <drm/drm_vblank.h> -#include "gt/intel_rps.h" #include "i915_drv.h" #include "i915_irq.h" #include "i915_reg.h" @@ -14,9 +13,12 @@ #include "intel_crtc.h" #include "intel_de.h" #include "intel_display_irq.h" +#include "intel_display_regs.h" #include "intel_display_rpm.h" +#include "intel_display_rps.h" #include "intel_display_trace.h" #include "intel_display_types.h" +#include "intel_dmc.h" #include "intel_dmc_wl.h" #include "intel_dp_aux.h" #include "intel_dsb.h" @@ -135,7 +137,7 @@ void ilk_update_display_irq(struct intel_display *display, struct drm_i915_private *dev_priv = to_i915(display->drm); u32 new_val; - lockdep_assert_held(&dev_priv->irq_lock); + lockdep_assert_held(&display->irq.lock); drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask); new_val = dev_priv->irq_mask; @@ -173,7 +175,7 @@ void bdw_update_port_irq(struct intel_display *display, u32 new_val; u32 old_val; - lockdep_assert_held(&dev_priv->irq_lock); + lockdep_assert_held(&display->irq.lock); drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask); @@ -206,7 +208,7 @@ static void bdw_update_pipe_irq(struct intel_display *display, struct drm_i915_private *dev_priv = to_i915(display->drm); u32 new_val; - lockdep_assert_held(&dev_priv->irq_lock); + lockdep_assert_held(&display->irq.lock); drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask); @@ -254,7 +256,7 @@ void ibx_display_interrupt_update(struct intel_display *display, drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask); - lockdep_assert_held(&dev_priv->irq_lock); + lockdep_assert_held(&display->irq.lock); if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv))) return; @@ -276,11 +278,10 @@ void ibx_disable_display_interrupt(struct intel_display *display, u32 bits) u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 status_mask = display->irq.pipestat_irq_mask[pipe]; u32 enable_mask = status_mask << 16; - lockdep_assert_held(&dev_priv->irq_lock); + lockdep_assert_held(&display->irq.lock); if (DISPLAY_VER(display) < 5) goto out; @@ -329,7 +330,7 @@ void i915_enable_pipestat(struct intel_display *display, "pipe %c: status_mask=0x%x\n", pipe_name(pipe), status_mask); - lockdep_assert_held(&dev_priv->irq_lock); + lockdep_assert_held(&display->irq.lock); drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv)); if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == status_mask) @@ -353,7 +354,7 @@ void i915_disable_pipestat(struct intel_display *display, "pipe %c: status_mask=0x%x\n", pipe_name(pipe), status_mask); - lockdep_assert_held(&dev_priv->irq_lock); + lockdep_assert_held(&display->irq.lock); drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv)); if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == 0) @@ -377,28 +378,23 @@ static bool i915_has_legacy_blc_interrupt(struct intel_display *display) return IS_DISPLAY_VER(display, 3, 4) && display->platform.mobile; } -/** - * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion - * @display: display device - */ -void i915_enable_asle_pipestat(struct intel_display *display) +/* enable ASLE pipestat for OpRegion */ +static void i915_enable_asle_pipestat(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - if (!intel_opregion_asle_present(display)) return; if (!i915_has_legacy_blc_interrupt(display)) return; - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); i915_enable_pipestat(display, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); if (DISPLAY_VER(display) >= 4) i915_enable_pipestat(display, PIPE_A, PIPE_LEGACY_BLC_EVENT_STATUS); - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); } #if IS_ENABLED(CONFIG_DEBUG_FS) @@ -517,14 +513,13 @@ static void i9xx_pipestat_irq_reset(struct intel_display *display) void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]) { - struct drm_i915_private *dev_priv = to_i915(display->drm); enum pipe pipe; - spin_lock(&dev_priv->irq_lock); + spin_lock(&display->irq.lock); if ((display->platform.valleyview || display->platform.cherryview) && !display->irq.vlv_display_irqs_enabled) { - spin_unlock(&dev_priv->irq_lock); + spin_unlock(&display->irq.lock); return; } @@ -579,7 +574,7 @@ void i9xx_pipestat_irq_ack(struct intel_display *display, intel_de_write(display, reg, enable_mask); } } - spin_unlock(&dev_priv->irq_lock); + spin_unlock(&display->irq.lock); } void i915_pipestat_irq_handler(struct intel_display *display, @@ -879,7 +874,6 @@ static void ilk_gtt_fault_irq_handler(struct intel_display *display) void ilk_display_irq_handler(struct intel_display *display, u32 de_iir) { - struct drm_i915_private *dev_priv = to_i915(display->drm); enum pipe pipe; u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; @@ -916,7 +910,7 @@ void ilk_display_irq_handler(struct intel_display *display, u32 de_iir) if (de_iir & DE_PCH_EVENT) { u32 pch_iir = intel_de_read(display, SDEIIR); - if (HAS_PCH_CPT(dev_priv)) + if (HAS_PCH_CPT(display)) cpt_irq_handler(display, pch_iir); else ibx_irq_handler(display, pch_iir); @@ -926,12 +920,11 @@ void ilk_display_irq_handler(struct intel_display *display, u32 de_iir) } if (DISPLAY_VER(display) == 5 && de_iir & DE_PCU_EVENT) - gen5_rps_irq_handler(&to_gt(dev_priv)->rps); + ilk_display_rps_irq_handler(display); } void ivb_display_irq_handler(struct intel_display *display, u32 de_iir) { - struct drm_i915_private *dev_priv = to_i915(display->drm); enum pipe pipe; u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; @@ -969,7 +962,7 @@ void ivb_display_irq_handler(struct intel_display *display, u32 de_iir) } /* check event from PCH */ - if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) { + if (!HAS_PCH_NOP(display) && (de_iir & DE_PCH_EVENT_IVB)) { u32 pch_iir = intel_de_read(display, SDEIIR); cpt_irq_handler(display, pch_iir); @@ -1025,7 +1018,15 @@ static u32 gen8_de_port_aux_mask(struct intel_display *display) static u32 gen8_de_pipe_fault_mask(struct intel_display *display) { - if (DISPLAY_VER(display) >= 14) + if (DISPLAY_VER(display) >= 20) + return MTL_PLANE_ATS_FAULT | + GEN9_PIPE_CURSOR_FAULT | + GEN11_PIPE_PLANE5_FAULT | + GEN9_PIPE_PLANE4_FAULT | + GEN9_PIPE_PLANE3_FAULT | + GEN9_PIPE_PLANE2_FAULT | + GEN9_PIPE_PLANE1_FAULT; + else if (DISPLAY_VER(display) >= 14) return MTL_PIPEDMC_ATS_FAULT | MTL_PLANE_ATS_FAULT | GEN12_PIPEDMC_FAULT | @@ -1311,7 +1312,6 @@ static u32 gen8_de_pipe_flip_done_mask(struct intel_display *display) static void gen8_read_and_ack_pch_irqs(struct intel_display *display, u32 *pch_iir, u32 *pica_iir) { - struct drm_i915_private *i915 = to_i915(display->drm); u32 pica_ier = 0; *pica_iir = 0; @@ -1325,7 +1325,7 @@ static void gen8_read_and_ack_pch_irqs(struct intel_display *display, u32 *pch_i * their flags both in the PICA and SDE IIR. */ if (*pch_iir & SDE_PICAINTERRUPT) { - drm_WARN_ON(display->drm, INTEL_PCH_TYPE(i915) < PCH_MTL); + drm_WARN_ON(display->drm, INTEL_PCH_TYPE(display) < PCH_MTL); pica_ier = intel_de_rmw(display, PICAINTERRUPT_IER, ~0, 0); *pica_iir = intel_de_read(display, PICAINTERRUPT_IIR); @@ -1340,7 +1340,6 @@ static void gen8_read_and_ack_pch_irqs(struct intel_display *display, u32 *pch_i void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 iir; enum pipe pipe; @@ -1429,7 +1428,8 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl) iir = intel_de_read(display, GEN8_DE_PIPE_IIR(pipe)); if (!iir) { drm_err_ratelimited(display->drm, - "The master control interrupt lied (DE PIPE)!\n"); + "The master control interrupt lied (DE PIPE %c)!\n", + pipe_name(pipe)); continue; } @@ -1452,6 +1452,9 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl) intel_dsb_irq_handler(display, pipe, INTEL_DSB_2); } + if (HAS_PIPEDMC(display) && iir & GEN12_PIPEDMC_INTERRUPT) + intel_pipedmc_irq_handler(display, pipe); + if (iir & GEN8_PIPE_CDCLK_CRC_DONE) hsw_pipe_crc_irq_handler(display, pipe); @@ -1465,7 +1468,7 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl) pipe, fault_errors); } - if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && + if (HAS_PCH_SPLIT(display) && !HAS_PCH_NOP(display) && master_ctl & GEN8_DE_PCH_IRQ) { u32 pica_iir; @@ -1479,9 +1482,9 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl) if (pica_iir) xelpdp_pica_irq_handler(display, pica_iir); - if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) + if (INTEL_PCH_TYPE(display) >= PCH_ICP) icp_irq_handler(display, iir); - else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT) + else if (INTEL_PCH_TYPE(display) >= PCH_SPT) spt_irq_handler(display, iir); else cpt_irq_handler(display, iir); @@ -1573,13 +1576,12 @@ void i915gm_irq_cstate_wa(struct intel_display *display, bool enable) int i8xx_enable_vblank(struct drm_crtc *crtc) { struct intel_display *display = to_intel_display(crtc->dev); - struct drm_i915_private *dev_priv = to_i915(crtc->dev); enum pipe pipe = to_intel_crtc(crtc)->pipe; unsigned long irqflags; - spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + spin_lock_irqsave(&display->irq.lock, irqflags); i915_enable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS); - spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); + spin_unlock_irqrestore(&display->irq.lock, irqflags); return 0; } @@ -1587,13 +1589,12 @@ int i8xx_enable_vblank(struct drm_crtc *crtc) void i8xx_disable_vblank(struct drm_crtc *crtc) { struct intel_display *display = to_intel_display(crtc->dev); - struct drm_i915_private *dev_priv = to_i915(crtc->dev); enum pipe pipe = to_intel_crtc(crtc)->pipe; unsigned long irqflags; - spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + spin_lock_irqsave(&display->irq.lock, irqflags); i915_disable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS); - spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); + spin_unlock_irqrestore(&display->irq.lock, irqflags); } int i915gm_enable_vblank(struct drm_crtc *crtc) @@ -1617,14 +1618,13 @@ void i915gm_disable_vblank(struct drm_crtc *crtc) int i965_enable_vblank(struct drm_crtc *crtc) { struct intel_display *display = to_intel_display(crtc->dev); - struct drm_i915_private *dev_priv = to_i915(crtc->dev); enum pipe pipe = to_intel_crtc(crtc)->pipe; unsigned long irqflags; - spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + spin_lock_irqsave(&display->irq.lock, irqflags); i915_enable_pipestat(display, pipe, PIPE_START_VBLANK_INTERRUPT_STATUS); - spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); + spin_unlock_irqrestore(&display->irq.lock, irqflags); return 0; } @@ -1632,28 +1632,26 @@ int i965_enable_vblank(struct drm_crtc *crtc) void i965_disable_vblank(struct drm_crtc *crtc) { struct intel_display *display = to_intel_display(crtc->dev); - struct drm_i915_private *dev_priv = to_i915(crtc->dev); enum pipe pipe = to_intel_crtc(crtc)->pipe; unsigned long irqflags; - spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + spin_lock_irqsave(&display->irq.lock, irqflags); i915_disable_pipestat(display, pipe, PIPE_START_VBLANK_INTERRUPT_STATUS); - spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); + spin_unlock_irqrestore(&display->irq.lock, irqflags); } int ilk_enable_vblank(struct drm_crtc *crtc) { struct intel_display *display = to_intel_display(crtc->dev); - struct drm_i915_private *dev_priv = to_i915(crtc->dev); enum pipe pipe = to_intel_crtc(crtc)->pipe; unsigned long irqflags; u32 bit = DISPLAY_VER(display) >= 7 ? DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); - spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + spin_lock_irqsave(&display->irq.lock, irqflags); ilk_enable_display_irq(display, bit); - spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); + spin_unlock_irqrestore(&display->irq.lock, irqflags); /* Even though there is no DMC, frame counter can get stuck when * PSR is active as no frames are generated. @@ -1667,15 +1665,14 @@ int ilk_enable_vblank(struct drm_crtc *crtc) void ilk_disable_vblank(struct drm_crtc *crtc) { struct intel_display *display = to_intel_display(crtc->dev); - struct drm_i915_private *dev_priv = to_i915(crtc->dev); enum pipe pipe = to_intel_crtc(crtc)->pipe; unsigned long irqflags; u32 bit = DISPLAY_VER(display) >= 7 ? DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); - spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + spin_lock_irqsave(&display->irq.lock, irqflags); ilk_disable_display_irq(display, bit); - spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); + spin_unlock_irqrestore(&display->irq.lock, irqflags); } static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc, @@ -1701,39 +1698,31 @@ static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc, return true; } -static void intel_display_vblank_dc_work(struct work_struct *work) +static void intel_display_vblank_notify_work(struct work_struct *work) { struct intel_display *display = - container_of(work, typeof(*display), irq.vblank_dc_work); - int vblank_wa_num_pipes = READ_ONCE(display->irq.vblank_wa_num_pipes); + container_of(work, typeof(*display), irq.vblank_notify_work); + int vblank_enable_count = READ_ONCE(display->irq.vblank_enable_count); - /* - * NOTE: intel_display_power_set_target_dc_state is used only by PSR - * code for DC3CO handling. DC3CO target state is currently disabled in - * PSR code. If DC3CO is taken into use we need take that into account - * here as well. - */ - intel_display_power_set_target_dc_state(display, vblank_wa_num_pipes ? DC_STATE_DISABLE : - DC_STATE_EN_UPTO_DC6); + intel_psr_notify_vblank_enable_disable(display, vblank_enable_count); } int bdw_enable_vblank(struct drm_crtc *_crtc) { struct intel_crtc *crtc = to_intel_crtc(_crtc); struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; unsigned long irqflags; if (gen11_dsi_configure_te(crtc, true)) return 0; - if (crtc->block_dc_for_vblank && display->irq.vblank_wa_num_pipes++ == 0) - schedule_work(&display->irq.vblank_dc_work); + if (crtc->vblank_psr_notify && display->irq.vblank_enable_count++ == 0) + schedule_work(&display->irq.vblank_notify_work); - spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + spin_lock_irqsave(&display->irq.lock, irqflags); bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_VBLANK); - spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); + spin_unlock_irqrestore(&display->irq.lock, irqflags); /* Even if there is no DMC, frame counter can get stuck when * PSR is active as no frames are generated, so check only for PSR. @@ -1748,19 +1737,18 @@ void bdw_disable_vblank(struct drm_crtc *_crtc) { struct intel_crtc *crtc = to_intel_crtc(_crtc); struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; unsigned long irqflags; if (gen11_dsi_configure_te(crtc, false)) return; - spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + spin_lock_irqsave(&display->irq.lock, irqflags); bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_VBLANK); - spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); + spin_unlock_irqrestore(&display->irq.lock, irqflags); - if (crtc->block_dc_for_vblank && --display->irq.vblank_wa_num_pipes == 0) - schedule_work(&display->irq.vblank_dc_work); + if (crtc->vblank_psr_notify && --display->irq.vblank_enable_count == 0) + schedule_work(&display->irq.vblank_notify_work); } static u32 vlv_dpinvgtt_pipe_fault_mask(enum pipe pipe) @@ -1894,8 +1882,10 @@ static void _vlv_display_irq_reset(struct intel_display *display) void vlv_display_irq_reset(struct intel_display *display) { + spin_lock_irq(&display->irq.lock); if (display->irq.vlv_display_irqs_enabled) _vlv_display_irq_reset(display); + spin_unlock_irq(&display->irq.lock); } void i9xx_display_irq_reset(struct intel_display *display) @@ -1908,22 +1898,48 @@ void i9xx_display_irq_reset(struct intel_display *display) i9xx_pipestat_irq_reset(display); } +void i915_display_irq_postinstall(struct intel_display *display) +{ + /* + * Interrupt setup is already guaranteed to be single-threaded, this is + * just to make the assert_spin_locked check happy. + */ + spin_lock_irq(&display->irq.lock); + i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); + i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); + spin_unlock_irq(&display->irq.lock); + + i915_enable_asle_pipestat(display); +} + +void i965_display_irq_postinstall(struct intel_display *display) +{ + /* + * Interrupt setup is already guaranteed to be single-threaded, this is + * just to make the assert_spin_locked check happy. + */ + spin_lock_irq(&display->irq.lock); + i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); + i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); + i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); + spin_unlock_irq(&display->irq.lock); + + i915_enable_asle_pipestat(display); +} + static u32 vlv_error_mask(void) { /* TODO enable other errors too? */ return VLV_ERROR_PAGE_TABLE; } -void vlv_display_irq_postinstall(struct intel_display *display) +static void _vlv_display_irq_postinstall(struct intel_display *display) { struct drm_i915_private *dev_priv = to_i915(display->drm); u32 pipestat_mask; u32 enable_mask; enum pipe pipe; - if (!display->irq.vlv_display_irqs_enabled) - return; - if (display->platform.cherryview) intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_CHV | @@ -1960,8 +1976,30 @@ void vlv_display_irq_postinstall(struct intel_display *display) intel_display_irq_regs_init(display, VLV_IRQ_REGS, dev_priv->irq_mask, enable_mask); } +void vlv_display_irq_postinstall(struct intel_display *display) +{ + spin_lock_irq(&display->irq.lock); + if (display->irq.vlv_display_irqs_enabled) + _vlv_display_irq_postinstall(display); + spin_unlock_irq(&display->irq.lock); +} + +void ibx_display_irq_reset(struct intel_display *display) +{ + struct drm_i915_private *i915 = to_i915(display->drm); + + if (HAS_PCH_NOP(i915)) + return; + + gen2_irq_reset(to_intel_uncore(display->drm), SDE_IRQ_REGS); + + if (HAS_PCH_CPT(i915) || HAS_PCH_LPT(i915)) + intel_de_write(display, SERR_INT, 0xffffffff); +} + void gen8_display_irq_reset(struct intel_display *display) { + struct drm_i915_private *i915 = to_i915(display->drm); enum pipe pipe; if (!HAS_DISPLAY(display)) @@ -1977,11 +2015,13 @@ void gen8_display_irq_reset(struct intel_display *display) intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS); intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS); + + if (HAS_PCH_SPLIT(i915)) + ibx_display_irq_reset(display); } void gen11_display_irq_reset(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); enum pipe pipe; u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C) | BIT(TRANSCODER_D); @@ -2026,7 +2066,7 @@ void gen11_display_irq_reset(struct intel_display *display) else intel_display_irq_regs_reset(display, GEN11_DE_HPD_IRQ_REGS); - if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) + if (INTEL_PCH_TYPE(display) >= PCH_ICP) intel_display_irq_regs_reset(display, SDE_IRQ_REGS); } @@ -2038,10 +2078,10 @@ void gen8_irq_power_well_post_enable(struct intel_display *display, gen8_de_pipe_flip_done_mask(display); enum pipe pipe; - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); if (!intel_irqs_enabled(dev_priv)) { - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); return; } @@ -2050,7 +2090,7 @@ void gen8_irq_power_well_post_enable(struct intel_display *display, display->irq.de_irq_mask[pipe], ~display->irq.de_irq_mask[pipe] | extra_ier); - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); } void gen8_irq_power_well_pre_disable(struct intel_display *display, @@ -2059,17 +2099,17 @@ void gen8_irq_power_well_pre_disable(struct intel_display *display, struct drm_i915_private *dev_priv = to_i915(display->drm); enum pipe pipe; - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); if (!intel_irqs_enabled(dev_priv)) { - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); return; } for_each_pipe_masked(display, pipe, pipe_mask) intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); /* make sure we're done processing display irqs */ intel_synchronize_irq(dev_priv); @@ -2088,15 +2128,14 @@ void gen8_irq_power_well_pre_disable(struct intel_display *display, */ static void ibx_irq_postinstall(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 mask; - if (HAS_PCH_NOP(dev_priv)) + if (HAS_PCH_NOP(display)) return; - if (HAS_PCH_IBX(dev_priv)) + if (HAS_PCH_IBX(display)) mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; - else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) + else if (HAS_PCH_CPT(display) || HAS_PCH_LPT(display)) mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; else mask = SDE_GMBUS_CPT; @@ -2108,32 +2147,37 @@ void valleyview_enable_display_irqs(struct intel_display *display) { struct drm_i915_private *dev_priv = to_i915(display->drm); - lockdep_assert_held(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); if (display->irq.vlv_display_irqs_enabled) - return; + goto out; display->irq.vlv_display_irqs_enabled = true; if (intel_irqs_enabled(dev_priv)) { _vlv_display_irq_reset(display); - vlv_display_irq_postinstall(display); + _vlv_display_irq_postinstall(display); } + +out: + spin_unlock_irq(&display->irq.lock); } void valleyview_disable_display_irqs(struct intel_display *display) { struct drm_i915_private *dev_priv = to_i915(display->drm); - lockdep_assert_held(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); if (!display->irq.vlv_display_irqs_enabled) - return; + goto out; display->irq.vlv_display_irqs_enabled = false; if (intel_irqs_enabled(dev_priv)) _vlv_display_irq_reset(display); +out: + spin_unlock_irq(&display->irq.lock); } void ilk_de_irq_postinstall(struct intel_display *display) @@ -2184,8 +2228,6 @@ static void icp_irq_postinstall(struct intel_display *display); void gen8_de_irq_postinstall(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - u32 de_pipe_masked = gen8_de_pipe_fault_mask(display) | GEN8_PIPE_CDCLK_CRC_DONE; u32 de_pipe_enables; @@ -2201,9 +2243,9 @@ void gen8_de_irq_postinstall(struct intel_display *display) if (DISPLAY_VER(display) >= 14) mtp_irq_postinstall(display); - else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) + else if (INTEL_PCH_TYPE(display) >= PCH_ICP) icp_irq_postinstall(display); - else if (HAS_PCH_SPLIT(dev_priv)) + else if (HAS_PCH_SPLIT(display)) ibx_irq_postinstall(display); if (DISPLAY_VER(display) < 11) @@ -2230,6 +2272,10 @@ void gen8_de_irq_postinstall(struct intel_display *display) GEN12_DSB_INT(INTEL_DSB_1) | GEN12_DSB_INT(INTEL_DSB_2); + /* TODO figure PIPEDMC interrupts for pre-LNL */ + if (DISPLAY_VER(display) >= 20) + de_pipe_masked |= GEN12_PIPEDMC_INTERRUPT; + de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN | gen8_de_pipe_flip_done_mask(display); @@ -2323,9 +2369,40 @@ void dg1_de_irq_postinstall(struct intel_display *display) void intel_display_irq_init(struct intel_display *display) { + spin_lock_init(&display->irq.lock); + display->drm->vblank_disable_immediate = true; intel_hotplug_irq_init(display); - INIT_WORK(&display->irq.vblank_dc_work, intel_display_vblank_dc_work); + INIT_WORK(&display->irq.vblank_notify_work, + intel_display_vblank_notify_work); +} + +struct intel_display_irq_snapshot { + u32 derrmr; +}; + +struct intel_display_irq_snapshot * +intel_display_irq_snapshot_capture(struct intel_display *display) +{ + struct intel_display_irq_snapshot *snapshot; + + snapshot = kzalloc(sizeof(*snapshot), GFP_ATOMIC); + if (!snapshot) + return NULL; + + if (DISPLAY_VER(display) >= 6 && DISPLAY_VER(display) < 20 && !HAS_GMCH(display)) + snapshot->derrmr = intel_de_read(display, DERRMR); + + return snapshot; +} + +void intel_display_irq_snapshot_print(const struct intel_display_irq_snapshot *snapshot, + struct drm_printer *p) +{ + if (!snapshot) + return; + + drm_printf(p, "DERRMR: 0x%08x\n", snapshot->derrmr); } diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h index f72727768351..c66db3851da4 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.h +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h @@ -12,7 +12,9 @@ enum pipe; struct drm_crtc; +struct drm_printer; struct intel_display; +struct intel_display_irq_snapshot; void valleyview_enable_display_irqs(struct intel_display *display); void valleyview_disable_display_irqs(struct intel_display *display); @@ -54,10 +56,13 @@ u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl); void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir); void i9xx_display_irq_reset(struct intel_display *display); +void ibx_display_irq_reset(struct intel_display *display); void vlv_display_irq_reset(struct intel_display *display); void gen8_display_irq_reset(struct intel_display *display); void gen11_display_irq_reset(struct intel_display *display); +void i915_display_irq_postinstall(struct intel_display *display); +void i965_display_irq_postinstall(struct intel_display *display); void vlv_display_irq_postinstall(struct intel_display *display); void ilk_de_irq_postinstall(struct intel_display *display); void gen8_de_irq_postinstall(struct intel_display *display); @@ -67,7 +72,6 @@ void dg1_de_irq_postinstall(struct intel_display *display); u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe); void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask); void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask); -void i915_enable_asle_pipestat(struct intel_display *display); void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); @@ -82,4 +86,7 @@ void intel_display_irq_init(struct intel_display *display); void i915gm_irq_cstate_wa(struct intel_display *display, bool enable); +struct intel_display_irq_snapshot *intel_display_irq_snapshot_capture(struct intel_display *display); +void intel_display_irq_snapshot_print(const struct intel_display_irq_snapshot *snapshot, struct drm_printer *p); + #endif /* __INTEL_DISPLAY_IRQ_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index c78315eb44fa..fe3a8e90b97a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5,6 +5,8 @@ #include <linux/string_helpers.h> +#include "soc/intel_dram.h" + #include "i915_drv.h" #include "i915_irq.h" #include "i915_reg.h" @@ -16,6 +18,7 @@ #include "intel_display_power.h" #include "intel_display_power_map.h" #include "intel_display_power_well.h" +#include "intel_display_regs.h" #include "intel_display_rpm.h" #include "intel_display_types.h" #include "intel_dmc.h" @@ -323,6 +326,35 @@ unlock: mutex_unlock(&power_domains->lock); } +/** + * intel_display_power_get_current_dc_state - Set target dc state. + * @display: display device + * + * This function set the "DC off" power well target_dc_state, + * based upon this target_dc_stste, "DC off" power well will + * enable desired DC state. + */ +u32 intel_display_power_get_current_dc_state(struct intel_display *display) +{ + struct i915_power_well *power_well; + struct i915_power_domains *power_domains = &display->power.domains; + u32 current_dc_state = DC_STATE_DISABLE; + + mutex_lock(&power_domains->lock); + power_well = lookup_power_well(display, SKL_DISP_DC_OFF); + + if (drm_WARN_ON(display->drm, !power_well)) + goto unlock; + + current_dc_state = intel_power_well_is_enabled(display, power_well) ? + DC_STATE_DISABLE : power_domains->target_dc_state; + +unlock: + mutex_unlock(&power_domains->lock); + + return current_dc_state; +} + static void __async_put_domains_mask(struct i915_power_domains *power_domains, struct intel_power_domain_mask *mask) { @@ -1365,11 +1397,9 @@ static void hsw_restore_lcpll(struct intel_display *display) */ static void hsw_enable_pc8(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - drm_dbg_kms(display->drm, "Enabling package C8+\n"); - if (HAS_PCH_LPT_LP(dev_priv)) + if (HAS_PCH_LPT_LP(display)) intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, PCH_LP_PARTITION_LEVEL_DISABLE, 0); @@ -1415,14 +1445,13 @@ static void intel_pch_reset_handshake(struct intel_display *display, static void skl_display_core_init(struct intel_display *display, bool resume) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; struct i915_power_well *well; gen9_set_dc_state(display, DC_STATE_DISABLE); /* enable PCH reset handshake */ - intel_pch_reset_handshake(display, !HAS_PCH_NOP(dev_priv)); + intel_pch_reset_handshake(display, !HAS_PCH_NOP(display)); if (!HAS_DISPLAY(display)) return; @@ -1578,9 +1607,7 @@ static const struct buddy_page_mask wa_1409767108_buddy_page_masks[] = { static void tgl_bw_buddy_init(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - enum intel_dram_type type = dev_priv->dram_info.type; - u8 num_channels = dev_priv->dram_info.num_channels; + const struct dram_info *dram_info = intel_dram_info(display->drm); const struct buddy_page_mask *table; unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask; int config, i; @@ -1597,8 +1624,8 @@ static void tgl_bw_buddy_init(struct intel_display *display) table = tgl_buddy_page_masks; for (config = 0; table[config].page_mask != 0; config++) - if (table[config].num_channels == num_channels && - table[config].type == type) + if (table[config].num_channels == dram_info->num_channels && + table[config].type == dram_info->type) break; if (table[config].page_mask == 0) { @@ -1624,20 +1651,19 @@ static void tgl_bw_buddy_init(struct intel_display *display) static void icl_display_core_init(struct intel_display *display, bool resume) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; struct i915_power_well *well; gen9_set_dc_state(display, DC_STATE_DISABLE); /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */ - if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && - INTEL_PCH_TYPE(dev_priv) < PCH_DG1) + if (INTEL_PCH_TYPE(display) >= PCH_TGP && + INTEL_PCH_TYPE(display) < PCH_DG1) intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0, PCH_DPMGUNIT_CLOCK_GATE_DISABLE); /* 1. Enable PCH reset handshake. */ - intel_pch_reset_handshake(display, !HAS_PCH_NOP(dev_priv)); + intel_pch_reset_handshake(display, !HAS_PCH_NOP(display)); if (!HAS_DISPLAY(display)) return; @@ -1858,12 +1884,11 @@ static void vlv_cmnlane_wa(struct intel_display *display) static bool vlv_punit_is_power_gated(struct intel_display *display, u32 reg0) { - struct drm_i915_private *dev_priv = to_i915(display->drm); bool ret; - vlv_punit_get(dev_priv); - ret = (vlv_punit_read(dev_priv, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE; - vlv_punit_put(dev_priv); + vlv_punit_get(display->drm); + ret = (vlv_punit_read(display->drm, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE; + vlv_punit_put(display->drm); return ret; } @@ -1908,7 +1933,6 @@ static void intel_power_domains_verify_state(struct intel_display *display); */ void intel_power_domains_init_hw(struct intel_display *display, bool resume) { - struct drm_i915_private *i915 = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; power_domains->initializing = true; @@ -1932,9 +1956,9 @@ void intel_power_domains_init_hw(struct intel_display *display, bool resume) assert_isp_power_gated(display); } else if (display->platform.broadwell || display->platform.haswell) { hsw_assert_cdclk(display); - intel_pch_reset_handshake(display, !HAS_PCH_NOP(i915)); + intel_pch_reset_handshake(display, !HAS_PCH_NOP(display)); } else if (display->platform.ivybridge) { - intel_pch_reset_handshake(display, !HAS_PCH_NOP(i915)); + intel_pch_reset_handshake(display, !HAS_PCH_NOP(display)); } /* @@ -2229,8 +2253,6 @@ static void intel_power_domains_verify_state(struct intel_display *display) void intel_display_power_suspend_late(struct intel_display *display, bool s2idle) { - struct drm_i915_private *i915 = to_i915(display->drm); - intel_power_domains_suspend(display, s2idle); if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || @@ -2241,14 +2263,12 @@ void intel_display_power_suspend_late(struct intel_display *display, bool s2idle } /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ - if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1) - intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS); + if (INTEL_PCH_TYPE(display) >= PCH_CNP && INTEL_PCH_TYPE(display) < PCH_DG1) + intel_de_rmw(display, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS); } void intel_display_power_resume_early(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || display->platform.broxton) { gen9_sanitize_dc_state(display); @@ -2258,8 +2278,8 @@ void intel_display_power_resume_early(struct intel_display *display) } /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ - if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1) - intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0); + if (INTEL_PCH_TYPE(display) >= PCH_CNP && INTEL_PCH_TYPE(display) < PCH_DG1) + intel_de_rmw(display, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0); intel_power_domains_resume(display); } diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index 1b53d67f9b60..f8813b0e16df 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -183,6 +183,7 @@ void intel_display_power_suspend(struct intel_display *display); void intel_display_power_resume(struct intel_display *display); void intel_display_power_set_target_dc_state(struct intel_display *display, u32 state); +u32 intel_display_power_get_current_dc_state(struct intel_display *display); bool intel_display_power_is_enabled(struct intel_display *display, enum intel_display_power_domain domain); diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c index ab1163744bc5..77268802b55e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c @@ -5,12 +5,12 @@ #include <drm/drm_print.h> -#include "i915_reg.h" #include "intel_display_core.h" #include "intel_display_power_map.h" #include "intel_display_power_well.h" +#include "intel_display_regs.h" #include "intel_display_types.h" -#include "vlv_sideband_reg.h" +#include "vlv_iosf_sb_reg.h" #define __LIST_INLINE_ELEMS(__elem_type, ...) \ ((__elem_type[]) { __VA_ARGS__ }) diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index b9b4359751cc..cba96f920fd2 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -13,6 +13,7 @@ #include "intel_de.h" #include "intel_display_irq.h" #include "intel_display_power_well.h" +#include "intel_display_regs.h" #include "intel_display_rpm.h" #include "intel_display_types.h" #include "intel_dkl_phy.h" @@ -25,12 +26,13 @@ #include "intel_hotplug.h" #include "intel_pcode.h" #include "intel_pps.h" +#include "intel_psr.h" #include "intel_tc.h" #include "intel_vga.h" #include "skl_watermark.h" #include "vlv_dpio_phy_regs.h" +#include "vlv_iosf_sb_reg.h" #include "vlv_sideband.h" -#include "vlv_sideband_reg.h" struct i915_power_well_regs { i915_reg_t bios; @@ -760,6 +762,9 @@ void gen9_set_dc_state(struct intel_display *display, u32 state) state & ~power_domains->allowed_dc_mask)) state &= power_domains->allowed_dc_mask; + if (!power_domains->initializing) + intel_psr_notify_dc5_dc6(display); + val = intel_de_read(display, DC_STATE_EN); mask = gen9_dc_mask(display); drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n", @@ -805,7 +810,6 @@ static void tgl_disable_dc3co(struct intel_display *display) static void assert_can_enable_dc5(struct intel_display *display) { - struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm); enum i915_power_well_id high_pg; /* Power wells at this level and above must be disabled for DC5 entry */ @@ -1098,7 +1102,6 @@ static void i830_pipes_power_well_sync_hw(struct intel_display *display, static void vlv_set_power_well(struct intel_display *display, struct i915_power_well *power_well, bool enable) { - struct drm_i915_private *dev_priv = to_i915(display->drm); int pw_idx = i915_power_well_instance(power_well)->vlv.idx; u32 mask; u32 state; @@ -1108,29 +1111,29 @@ static void vlv_set_power_well(struct intel_display *display, state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) : PUNIT_PWRGT_PWR_GATE(pw_idx); - vlv_punit_get(dev_priv); + vlv_punit_get(display->drm); #define COND \ - ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) + ((vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS) & mask) == state) if (COND) goto out; - ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); + ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL); ctrl &= ~mask; ctrl |= state; - vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); + vlv_punit_write(display->drm, PUNIT_REG_PWRGT_CTRL, ctrl); if (wait_for(COND, 100)) drm_err(display->drm, "timeout setting power well state %08x (%08x)\n", state, - vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); + vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL)); #undef COND out: - vlv_punit_put(dev_priv); + vlv_punit_put(display->drm); } static void vlv_power_well_enable(struct intel_display *display, @@ -1148,7 +1151,6 @@ static void vlv_power_well_disable(struct intel_display *display, static bool vlv_power_well_enabled(struct intel_display *display, struct i915_power_well *power_well) { - struct drm_i915_private *dev_priv = to_i915(display->drm); int pw_idx = i915_power_well_instance(power_well)->vlv.idx; bool enabled = false; u32 mask; @@ -1158,9 +1160,9 @@ static bool vlv_power_well_enabled(struct intel_display *display, mask = PUNIT_PWRGT_MASK(pw_idx); ctrl = PUNIT_PWRGT_PWR_ON(pw_idx); - vlv_punit_get(dev_priv); + vlv_punit_get(display->drm); - state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; + state = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS) & mask; /* * We only ever set the power-on and power-gate states, anything * else is unexpected. @@ -1174,10 +1176,10 @@ static bool vlv_power_well_enabled(struct intel_display *display, * A transient state at this point would mean some unexpected party * is poking at the power controls too. */ - ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; + ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL) & mask; drm_WARN_ON(display->drm, ctrl != state); - vlv_punit_put(dev_priv); + vlv_punit_put(display->drm); return enabled; } @@ -1208,7 +1210,6 @@ static void vlv_init_display_clock_gating(struct intel_display *display) static void vlv_display_power_well_init(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_encoder *encoder; enum pipe pipe; @@ -1232,9 +1233,7 @@ static void vlv_display_power_well_init(struct intel_display *display) vlv_init_display_clock_gating(display); - spin_lock_irq(&dev_priv->irq_lock); valleyview_enable_display_irqs(display); - spin_unlock_irq(&dev_priv->irq_lock); /* * During driver initialization/resume we can avoid restoring the @@ -1252,7 +1251,7 @@ static void vlv_display_power_well_init(struct intel_display *display) intel_crt_reset(&encoder->base); } - intel_vga_redisable_power_on(display); + intel_vga_disable(display); intel_pps_unlock_regs_wa(display); } @@ -1261,9 +1260,7 @@ static void vlv_display_power_well_deinit(struct intel_display *display) { struct drm_i915_private *dev_priv = to_i915(display->drm); - spin_lock_irq(&dev_priv->irq_lock); valleyview_disable_display_irqs(display); - spin_unlock_irq(&dev_priv->irq_lock); /* make sure we're done processing display irqs */ intel_synchronize_irq(dev_priv); @@ -1438,7 +1435,6 @@ static void assert_chv_phy_status(struct intel_display *display) static void chv_dpio_cmn_power_well_enable(struct intel_display *display, struct i915_power_well *power_well) { - struct drm_i915_private *dev_priv = to_i915(display->drm); enum i915_power_well_id id = i915_power_well_instance(power_well)->id; enum dpio_phy phy; u32 tmp; @@ -1462,30 +1458,30 @@ static void chv_dpio_cmn_power_well_enable(struct intel_display *display, drm_err(display->drm, "Display PHY %d is not power up\n", phy); - vlv_dpio_get(dev_priv); + vlv_dpio_get(display->drm); /* Enable dynamic power down */ - tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW28); + tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW28); tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW28, tmp); + vlv_dpio_write(display->drm, phy, CHV_CMN_DW28, tmp); if (id == VLV_DISP_PW_DPIO_CMN_BC) { - tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW6_CH1); + tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW6_CH1); tmp |= DPIO_DYNPWRDOWNEN_CH1; - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW6_CH1, tmp); + vlv_dpio_write(display->drm, phy, CHV_CMN_DW6_CH1, tmp); } else { /* * Force the non-existing CL2 off. BXT does this * too, so maybe it saves some power even though * CL2 doesn't exist? */ - tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW30); + tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW30); tmp |= DPIO_CL2_LDOFUSE_PWRENB; - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW30, tmp); + vlv_dpio_write(display->drm, phy, CHV_CMN_DW30, tmp); } - vlv_dpio_put(dev_priv); + vlv_dpio_put(display->drm); display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); intel_de_write(display, DISPLAY_PHY_CONTROL, @@ -1536,7 +1532,6 @@ static void chv_dpio_cmn_power_well_disable(struct intel_display *display, static void assert_chv_phy_powergate(struct intel_display *display, enum dpio_phy phy, enum dpio_channel ch, bool override, unsigned int mask) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 reg, val, expected, actual; /* @@ -1554,9 +1549,9 @@ static void assert_chv_phy_powergate(struct intel_display *display, enum dpio_ph else reg = CHV_CMN_DW6_CH1; - vlv_dpio_get(dev_priv); - val = vlv_dpio_read(dev_priv, phy, reg); - vlv_dpio_put(dev_priv); + vlv_dpio_get(display->drm); + val = vlv_dpio_read(display->drm, phy, reg); + vlv_dpio_put(display->drm); /* * This assumes !override is only used when the port is disabled. @@ -1666,14 +1661,13 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder, static bool chv_pipe_power_well_enabled(struct intel_display *display, struct i915_power_well *power_well) { - struct drm_i915_private *dev_priv = to_i915(display->drm); enum pipe pipe = PIPE_A; bool enabled; u32 state, ctrl; - vlv_punit_get(dev_priv); + vlv_punit_get(display->drm); - state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); + state = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); /* * We only ever set the power-on and power-gate states, anything * else is unexpected. @@ -1686,10 +1680,10 @@ static bool chv_pipe_power_well_enabled(struct intel_display *display, * A transient state at this point would mean some unexpected party * is poking at the power controls too. */ - ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); + ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); drm_WARN_ON(display->drm, ctrl << 16 != state); - vlv_punit_put(dev_priv); + vlv_punit_put(display->drm); return enabled; } @@ -1698,36 +1692,35 @@ static void chv_set_pipe_power_well(struct intel_display *display, struct i915_power_well *power_well, bool enable) { - struct drm_i915_private *dev_priv = to_i915(display->drm); enum pipe pipe = PIPE_A; u32 state; u32 ctrl; state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); - vlv_punit_get(dev_priv); + vlv_punit_get(display->drm); #define COND \ - ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state) + ((vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state) if (COND) goto out; - ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); + ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); ctrl &= ~DP_SSC_MASK(pipe); ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); - vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl); + vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, ctrl); if (wait_for(COND, 100)) drm_err(display->drm, "timeout setting power well state %08x (%08x)\n", state, - vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM)); + vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM)); #undef COND out: - vlv_punit_put(dev_priv); + vlv_punit_put(display->drm); } static void chv_pipe_power_well_sync_hw(struct intel_display *display, diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h new file mode 100644 index 000000000000..e101105da4af --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -0,0 +1,2935 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright © 2025 Intel Corporation */ + +#ifndef __INTEL_DISPLAY_REGS_H__ +#define __INTEL_DISPLAY_REGS_H__ + +#include "intel_display_reg_defs.h" + +#define _GEN7_PIPEA_DE_LOAD_SL 0x70068 +#define _GEN7_PIPEB_DE_LOAD_SL 0x71068 +#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) + +#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) +#define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ +#define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ +#define DPIO_SFR_BYPASS (1 << 1) +#define DPIO_CMNRST (1 << 0) + +#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) +#define MIPIO_RST_CTRL (1 << 2) + +#define _BXT_PHY_CTL_DDI_A 0x64C00 +#define _BXT_PHY_CTL_DDI_B 0x64C10 +#define _BXT_PHY_CTL_DDI_C 0x64C20 +#define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) +#define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) +#define BXT_PHY_LANE_ENABLED (1 << 8) +#define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ + _BXT_PHY_CTL_DDI_B) + +#define _PHY_CTL_FAMILY_DDI 0x64C90 +#define _PHY_CTL_FAMILY_EDP 0x64C80 +#define _PHY_CTL_FAMILY_DDI_C 0x64CA0 +#define COMMON_RESET_DIS (1 << 31) +#define BXT_PHY_CTL_FAMILY(phy) \ + _MMIO(_PICK_EVEN_2RANGES(phy, 1, \ + _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \ + _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C)) + +/* UAIMI scratch pad register 1 */ +#define UAIMI_SPR1 _MMIO(0x4F074) +/* SKL VccIO mask */ +#define SKL_VCCIO_MASK 0x1 +/* SKL balance leg register */ +#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) +/* I_boost values */ +#define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) +#define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) +/* Balance leg disable bits */ +#define BALANCE_LEG_DISABLE_SHIFT 23 +#define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) + +#define ILK_GTT_FAULT _MMIO(0x44040) /* ilk/snb */ +#define GTT_FAULT_INVALID_GTT_PTE (1 << 7) +#define GTT_FAULT_INVALID_PTE_DATA (1 << 6) +#define GTT_FAULT_CURSOR_B_FAULT (1 << 5) +#define GTT_FAULT_CURSOR_A_FAULT (1 << 4) +#define GTT_FAULT_SPRITE_B_FAULT (1 << 3) +#define GTT_FAULT_SPRITE_A_FAULT (1 << 2) +#define GTT_FAULT_PRIMARY_B_FAULT (1 << 1) +#define GTT_FAULT_PRIMARY_A_FAULT (1 << 0) + +#define DERRMR _MMIO(0x44050) +/* Note that HBLANK events are reserved on bdw+ */ +#define DERRMR_PIPEA_SCANLINE (1 << 0) +#define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1) +#define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2) +#define DERRMR_PIPEA_VBLANK (1 << 3) +#define DERRMR_PIPEA_HBLANK (1 << 5) +#define DERRMR_PIPEB_SCANLINE (1 << 8) +#define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9) +#define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10) +#define DERRMR_PIPEB_VBLANK (1 << 11) +#define DERRMR_PIPEB_HBLANK (1 << 13) +/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ +#define DERRMR_PIPEC_SCANLINE (1 << 14) +#define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15) +#define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20) +#define DERRMR_PIPEC_VBLANK (1 << 21) +#define DERRMR_PIPEC_HBLANK (1 << 22) + +#define VLV_IRQ_REGS I915_IRQ_REGS(VLV_IMR, \ + VLV_IER, \ + VLV_IIR) + +#define VLV_EIR _MMIO(VLV_DISPLAY_BASE + 0x20b0) +#define VLV_EMR _MMIO(VLV_DISPLAY_BASE + 0x20b4) +#define VLV_ESR _MMIO(VLV_DISPLAY_BASE + 0x20b8) +#define VLV_ERROR_GUNIT_TLB_DATA (1 << 6) +#define VLV_ERROR_GUNIT_TLB_PTE (1 << 5) +#define VLV_ERROR_PAGE_TABLE (1 << 4) +#define VLV_ERROR_CLAIM (1 << 0) + +#define VLV_ERROR_REGS I915_ERROR_REGS(VLV_EMR, VLV_EIR) + +#define _MBUS_ABOX0_CTL 0x45038 +#define _MBUS_ABOX1_CTL 0x45048 +#define _MBUS_ABOX2_CTL 0x4504C +#define MBUS_ABOX_CTL(x) \ + _MMIO(_PICK_EVEN_2RANGES(x, 2, \ + _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL, \ + _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL)) + +#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) +#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) +#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) +#define MBUS_ABOX_B_CREDIT(x) ((x) << 16) +#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) +#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) +#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) +#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) + +#define IPS_CTL _MMIO(0x43408) +#define IPS_ENABLE REG_BIT(31) +#define IPS_FALSE_COLOR REG_BIT(4) + +/* + * Clock control & power management + */ +#define _DPLL_A 0x6014 +#define _DPLL_B 0x6018 +#define _CHV_DPLL_C 0x6030 +#define DPLL(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \ + (pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) + +#define VGA0 _MMIO(0x6000) +#define VGA1 _MMIO(0x6004) +#define VGA_PD _MMIO(0x6010) +#define VGA0_PD_P2_DIV_4 (1 << 7) +#define VGA0_PD_P1_DIV_2 (1 << 5) +#define VGA0_PD_P1_SHIFT 0 +#define VGA0_PD_P1_MASK (0x1f << 0) +#define VGA1_PD_P2_DIV_4 (1 << 15) +#define VGA1_PD_P1_DIV_2 (1 << 13) +#define VGA1_PD_P1_SHIFT 8 +#define VGA1_PD_P1_MASK (0x1f << 8) +#define DPLL_VCO_ENABLE (1 << 31) +#define DPLL_SDVO_HIGH_SPEED (1 << 30) +#define DPLL_DVO_2X_MODE (1 << 30) +#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) +#define DPLL_SYNCLOCK_ENABLE (1 << 29) +#define DPLL_REF_CLK_ENABLE_VLV (1 << 29) +#define DPLL_VGA_MODE_DIS (1 << 28) +#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ +#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ +#define DPLL_MODE_MASK (3 << 26) +#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ +#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ +#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ +#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ +#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ +#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ +#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ +#define DPLL_LOCK_VLV (1 << 15) +#define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) +#define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) +#define DPLL_SSC_REF_CLK_CHV (1 << 13) +#define DPLL_PORTC_READY_MASK (0xf << 4) +#define DPLL_PORTB_READY_MASK (0xf) + +#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 + +/* Additional CHV pll/phy registers */ +#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) +#define DPLL_PORTD_READY_MASK (0xf) +#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) +#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27)) +#define PHY_LDO_DELAY_0NS 0x0 +#define PHY_LDO_DELAY_200NS 0x1 +#define PHY_LDO_DELAY_600NS 0x2 +#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23)) +#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) +#define PHY_CH_SU_PSR 0x1 +#define PHY_CH_DEEP_PSR 0x7 +#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2)) +#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) +#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) +#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) +#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch)))) +#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) + +/* + * The i830 generation, in LVDS mode, defines P1 as the bit number set within + * this field (only one bit may be set). + */ +#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 +#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 +#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 +/* i830, required in DVO non-gang */ +#define PLL_P2_DIVIDE_BY_4 (1 << 23) +#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ +#define PLL_REF_INPUT_DREFCLK (0 << 13) +#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ +#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ +#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) +#define PLL_REF_INPUT_MASK (3 << 13) +#define PLL_LOAD_PULSE_PHASE_SHIFT 9 +/* Ironlake */ +# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 +# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) +# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) +# define DPLL_FPA1_P1_POST_DIV_SHIFT 0 +# define DPLL_FPA1_P1_POST_DIV_MASK 0xff + +/* + * Parallel to Serial Load Pulse phase selection. + * Selects the phase for the 10X DPLL clock for the PCIe + * digital display port. The range is 4 to 13; 10 or more + * is just a flip delay. The default is 6 + */ +#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) +#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) +/* + * SDVO multiplier for 945G/GM. Not used on 965. + */ +#define SDVO_MULTIPLIER_MASK 0x000000ff +#define SDVO_MULTIPLIER_SHIFT_HIRES 4 +#define SDVO_MULTIPLIER_SHIFT_VGA 0 + +#define _DPLL_A_MD 0x601c +#define _DPLL_B_MD 0x6020 +#define _CHV_DPLL_C_MD 0x603c +#define DPLL_MD(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \ + (pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) + +/* + * UDI pixel divider, controlling how many pixels are stuffed into a packet. + * + * Value is pixels minus 1. Must be set to 1 pixel for SDVO. + */ +#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 +#define DPLL_MD_UDI_DIVIDER_SHIFT 24 +/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ +#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 +#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 +/* + * SDVO/UDI pixel multiplier. + * + * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus + * clock rate is 10 times the DPLL clock. At low resolution/refresh rate + * modes, the bus rate would be below the limits, so SDVO allows for stuffing + * dummy bytes in the datastream at an increased clock rate, with both sides of + * the link knowing how many bytes are fill. + * + * So, for a mode with a dotclock of 65Mhz, we would want to double the clock + * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be + * set to 130Mhz, and the SDVO multiplier set to 2x in this register and + * through an SDVO command. + * + * This register field has values of multiplication factor minus 1, with + * a maximum multiplier of 5 for SDVO. + */ +#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 +#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 +/* + * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. + * This best be set to the default value (3) or the CRT won't work. No, + * I don't entirely understand what this does... + */ +#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f +#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 + +#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) + +#define _FPA0 0x6040 +#define _FPA1 0x6044 +#define _FPB0 0x6048 +#define _FPB1 0x604c +#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) +#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) +#define FP_N_DIV_MASK 0x003f0000 +#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 +#define FP_N_DIV_SHIFT 16 +#define FP_M1_DIV_MASK 0x00003f00 +#define FP_M1_DIV_SHIFT 8 +#define FP_M2_DIV_MASK 0x0000003f +#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff +#define FP_M2_DIV_SHIFT 0 + +#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) +#define FW_CSPWRDWNEN (1 << 15) + +#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) + +#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) +#define CDCLK_FREQ_SHIFT 4 +#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) +#define CZCLK_FREQ_MASK 0xf + +#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) +#define PFI_CREDIT_63 (9 << 28) /* chv only */ +#define PFI_CREDIT_31 (8 << 28) /* chv only */ +#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ +#define PFI_CREDIT_RESEND (1 << 27) +#define VGA_FAST_MODE_DISABLE (1 << 14) + +#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) + +#define PEG_BAND_GAP_DATA _MMIO(0x14d68) + +/* + * Overlay regs + */ +#define OVADD _MMIO(0x30000) +#define DOVSTA _MMIO(0x30008) +#define OC_BUF (0x3 << 20) +#define OGAMC5 _MMIO(0x30010) +#define OGAMC4 _MMIO(0x30014) +#define OGAMC3 _MMIO(0x30018) +#define OGAMC2 _MMIO(0x3001c) +#define OGAMC1 _MMIO(0x30020) +#define OGAMC0 _MMIO(0x30024) + +#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) +#define BXT_GMBUS_GATING_DIS (1 << 14) +#define DG2_DPFC_GATING_DIS REG_BIT(31) + +#define GEN9_CLKGATE_DIS_5 _MMIO(0x46540) +#define DPCE_GATING_DIS REG_BIT(17) + +#define _CLKGATE_DIS_PSL_A 0x46520 +#define _CLKGATE_DIS_PSL_B 0x46524 +#define _CLKGATE_DIS_PSL_C 0x46528 +#define DUPS1_GATING_DIS (1 << 15) +#define DUPS2_GATING_DIS (1 << 19) +#define DUPS3_GATING_DIS (1 << 23) +#define CURSOR_GATING_DIS REG_BIT(28) +#define DPF_GATING_DIS (1 << 10) +#define DPF_RAM_GATING_DIS (1 << 9) +#define DPFR_GATING_DIS (1 << 8) + +#define CLKGATE_DIS_PSL(pipe) \ + _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) + +#define _CLKGATE_DIS_PSL_EXT_A 0x4654C +#define _CLKGATE_DIS_PSL_EXT_B 0x46550 +#define PIPEDMC_GATING_DIS REG_BIT(12) + +#define CLKGATE_DIS_PSL_EXT(pipe) \ + _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B) + +/* + * Display engine regs + */ +/* Pipe/transcoder A timing regs */ +#define _TRANS_HTOTAL_A 0x60000 +#define _TRANS_HTOTAL_B 0x61000 +#define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A) +#define HTOTAL_MASK REG_GENMASK(31, 16) +#define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK, (htotal)) +#define HACTIVE_MASK REG_GENMASK(15, 0) +#define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK, (hdisplay)) + +#define _TRANS_HBLANK_A 0x60004 +#define _TRANS_HBLANK_B 0x61004 +#define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A) +#define HBLANK_END_MASK REG_GENMASK(31, 16) +#define HBLANK_END(hblank_end) REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end)) +#define HBLANK_START_MASK REG_GENMASK(15, 0) +#define HBLANK_START(hblank_start) REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start)) + +#define _TRANS_HSYNC_A 0x60008 +#define _TRANS_HSYNC_B 0x61008 +#define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A) +#define HSYNC_END_MASK REG_GENMASK(31, 16) +#define HSYNC_END(hsync_end) REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end)) +#define HSYNC_START_MASK REG_GENMASK(15, 0) +#define HSYNC_START(hsync_start) REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start)) + +#define _TRANS_VTOTAL_A 0x6000c +#define _TRANS_VTOTAL_B 0x6100c +#define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A) +#define VTOTAL_MASK REG_GENMASK(31, 16) +#define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK, (vtotal)) +#define VACTIVE_MASK REG_GENMASK(15, 0) +#define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK, (vdisplay)) + +#define _TRANS_VBLANK_A 0x60010 +#define _TRANS_VBLANK_B 0x61010 +#define TRANS_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A) +#define VBLANK_END_MASK REG_GENMASK(31, 16) +#define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end)) +#define VBLANK_START_MASK REG_GENMASK(15, 0) +#define VBLANK_START(vblank_start) REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start)) + +#define _TRANS_VSYNC_A 0x60014 +#define _TRANS_VSYNC_B 0x61014 +#define TRANS_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A) +#define VSYNC_END_MASK REG_GENMASK(31, 16) +#define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end)) +#define VSYNC_START_MASK REG_GENMASK(15, 0) +#define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start)) + +#define _PIPEASRC 0x6001c +#define _PIPEBSRC 0x6101c +#define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC) +#define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16) +#define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w)) +#define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0) +#define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h)) + +#define _BCLRPAT_A 0x60020 +#define _BCLRPAT_B 0x61020 +#define BCLRPAT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) + +#define _TRANS_VSYNCSHIFT_A 0x60028 +#define _TRANS_VSYNCSHIFT_B 0x61028 +#define TRANS_VSYNCSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A) + +#define _TRANS_MULT_A 0x6002c +#define _TRANS_MULT_B 0x6102c +#define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) + +/* Hotplug control (945+ only) */ +#define PORT_HOTPLUG_EN(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) +#define PORTB_HOTPLUG_INT_EN (1 << 29) +#define PORTC_HOTPLUG_INT_EN (1 << 28) +#define PORTD_HOTPLUG_INT_EN (1 << 27) +#define SDVOB_HOTPLUG_INT_EN (1 << 26) +#define SDVOC_HOTPLUG_INT_EN (1 << 25) +#define TV_HOTPLUG_INT_EN (1 << 18) +#define CRT_HOTPLUG_INT_EN (1 << 9) +#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ + PORTC_HOTPLUG_INT_EN | \ + PORTD_HOTPLUG_INT_EN | \ + SDVOC_HOTPLUG_INT_EN | \ + SDVOB_HOTPLUG_INT_EN | \ + CRT_HOTPLUG_INT_EN) +#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) +#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) +/* must use period 64 on GM45 according to docs */ +#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) +#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) +#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) +#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) +#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) +#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) +#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) +#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) +#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) +#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) +#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) +#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) + +#define PORT_HOTPLUG_STAT(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) +/* HDMI/DP bits are g4x+ */ +#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) +#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) +#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) +#define PORTD_HOTPLUG_INT_STATUS (3 << 21) +#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) +#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) +#define PORTC_HOTPLUG_INT_STATUS (3 << 19) +#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) +#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) +#define PORTB_HOTPLUG_INT_STATUS (3 << 17) +#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) +#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) +/* CRT/TV common between gen3+ */ +#define CRT_HOTPLUG_INT_STATUS (1 << 11) +#define TV_HOTPLUG_INT_STATUS (1 << 10) +#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) +#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) +#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) +#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) +#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) +#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) +#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) +#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) + +/* SDVO is different across gen3/4 */ +#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) +#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) +/* + * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, + * since reality corrobates that they're the same as on gen3. But keep these + * bits here (and the comment!) to help any other lost wanderers back onto the + * right tracks. + */ +#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) +#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) +#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) +#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) +#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ + SDVOB_HOTPLUG_INT_STATUS_G4X | \ + SDVOC_HOTPLUG_INT_STATUS_G4X | \ + PORTB_HOTPLUG_INT_STATUS | \ + PORTC_HOTPLUG_INT_STATUS | \ + PORTD_HOTPLUG_INT_STATUS) + +#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ + SDVOB_HOTPLUG_INT_STATUS_I915 | \ + SDVOC_HOTPLUG_INT_STATUS_I915 | \ + PORTB_HOTPLUG_INT_STATUS | \ + PORTC_HOTPLUG_INT_STATUS | \ + PORTD_HOTPLUG_INT_STATUS) + +/* SDVO and HDMI port control. + * The same register may be used for SDVO or HDMI */ +#define _GEN3_SDVOB 0x61140 +#define _GEN3_SDVOC 0x61160 +#define GEN3_SDVOB _MMIO(_GEN3_SDVOB) +#define GEN3_SDVOC _MMIO(_GEN3_SDVOC) +#define GEN4_HDMIB GEN3_SDVOB +#define GEN4_HDMIC GEN3_SDVOC +#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) +#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) +#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) +#define PCH_SDVOB _MMIO(0xe1140) +#define PCH_HDMIB PCH_SDVOB +#define PCH_HDMIC _MMIO(0xe1150) +#define PCH_HDMID _MMIO(0xe1160) + +#define PORT_DFT_I9XX _MMIO(0x61150) +#define DC_BALANCE_RESET (1 << 25) +#define PORT_DFT2_G4X(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) +#define DC_BALANCE_RESET_VLV (1 << 31) +#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) +#define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */ +#define PIPE_B_SCRAMBLE_RESET REG_BIT(1) +#define PIPE_A_SCRAMBLE_RESET REG_BIT(0) + +/* Gen 3 SDVO bits: */ +#define SDVO_ENABLE (1 << 31) +#define SDVO_PIPE_SEL_SHIFT 30 +#define SDVO_PIPE_SEL_MASK (1 << 30) +#define SDVO_PIPE_SEL(pipe) ((pipe) << 30) +#define SDVO_STALL_SELECT (1 << 29) +#define SDVO_INTERRUPT_ENABLE (1 << 26) +/* + * 915G/GM SDVO pixel multiplier. + * Programmed value is multiplier - 1, up to 5x. + * \sa DPLL_MD_UDI_MULTIPLIER_MASK + */ +#define SDVO_PORT_MULTIPLY_MASK (7 << 23) +#define SDVO_PORT_MULTIPLY_SHIFT 23 +#define SDVO_PHASE_SELECT_MASK (15 << 19) +#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) +#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) +#define SDVOC_GANG_MODE (1 << 16) /* Port C only */ +#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ +#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ +#define SDVO_DETECTED (1 << 2) +/* Bits to be preserved when writing */ +#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ + SDVO_INTERRUPT_ENABLE) +#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) + +/* Gen 4 SDVO/HDMI bits: */ +#define SDVO_COLOR_FORMAT_8bpc (0 << 26) +#define SDVO_COLOR_FORMAT_MASK (7 << 26) +#define SDVO_ENCODING_SDVO (0 << 10) +#define SDVO_ENCODING_HDMI (2 << 10) +#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ +#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ +#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ +#define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */ +/* VSYNC/HSYNC bits new with 965, default is to be set */ +#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) +#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) + +/* Gen 5 (IBX) SDVO/HDMI bits: */ +#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ +#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ + +/* Gen 6 (CPT) SDVO/HDMI bits: */ +#define SDVO_PIPE_SEL_SHIFT_CPT 29 +#define SDVO_PIPE_SEL_MASK_CPT (3 << 29) +#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) + +/* CHV SDVO/HDMI bits: */ +#define SDVO_PIPE_SEL_SHIFT_CHV 24 +#define SDVO_PIPE_SEL_MASK_CHV (3 << 24) +#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) + +/* Video Data Island Packet control */ +#define VIDEO_DIP_DATA _MMIO(0x61178) +/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC + * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte + * of the infoframe structure specified by CEA-861. */ +#define VIDEO_DIP_DATA_SIZE 32 +#define VIDEO_DIP_ASYNC_DATA_SIZE 36 +#define VIDEO_DIP_GMP_DATA_SIZE 36 +#define VIDEO_DIP_VSC_DATA_SIZE 36 +#define VIDEO_DIP_PPS_DATA_SIZE 132 +#define VIDEO_DIP_CTL _MMIO(0x61170) +/* Pre HSW: */ +#define VIDEO_DIP_ENABLE (1 << 31) +#define VIDEO_DIP_PORT(port) ((port) << 29) +#define VIDEO_DIP_PORT_MASK (3 << 29) +#define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ +#define VIDEO_DIP_ENABLE_AVI (1 << 21) +#define VIDEO_DIP_ENABLE_VENDOR (2 << 21) +#define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ +#define VIDEO_DIP_ENABLE_SPD (8 << 21) +#define VIDEO_DIP_SELECT_AVI (0 << 19) +#define VIDEO_DIP_SELECT_VENDOR (1 << 19) +#define VIDEO_DIP_SELECT_GAMUT (2 << 19) +#define VIDEO_DIP_SELECT_SPD (3 << 19) +#define VIDEO_DIP_SELECT_MASK (3 << 19) +#define VIDEO_DIP_FREQ_ONCE (0 << 16) +#define VIDEO_DIP_FREQ_VSYNC (1 << 16) +#define VIDEO_DIP_FREQ_2VSYNC (2 << 16) +#define VIDEO_DIP_FREQ_MASK (3 << 16) +/* HSW and later: */ +#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) +#define PSR_VSC_BIT_7_SET (1 << 27) +#define VSC_SELECT_MASK (0x3 << 25) +#define VSC_SELECT_SHIFT 25 +#define VSC_DIP_HW_HEA_DATA (0 << 25) +#define VSC_DIP_HW_HEA_SW_DATA (1 << 25) +#define VSC_DIP_HW_DATA_SW_HEA (2 << 25) +#define VSC_DIP_SW_HEA_DATA (3 << 25) +#define VDIP_ENABLE_PPS (1 << 24) +#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) +#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) +#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) +#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) +#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) +#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) +/* ADL and later: */ +#define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23) + +#define PCH_GTC_CTL _MMIO(0xe7000) +#define PCH_GTC_ENABLE (1 << 31) + +/* Display Port */ +#define DP_A _MMIO(0x64000) /* eDP */ +#define DP_B _MMIO(0x64100) +#define DP_C _MMIO(0x64200) +#define DP_D _MMIO(0x64300) +#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) +#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) +#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) +#define DP_PORT_EN REG_BIT(31) +#define DP_PIPE_SEL_MASK REG_GENMASK(30, 30) +#define DP_PIPE_SEL(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK, (pipe)) +#define DP_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) +#define DP_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK_IVB, (pipe)) +#define DP_PIPE_SEL_SHIFT_CHV 16 +#define DP_PIPE_SEL_MASK_CHV REG_GENMASK(17, 16) +#define DP_PIPE_SEL_CHV(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK_CHV, (pipe)) +#define DP_LINK_TRAIN_MASK REG_GENMASK(29, 28) +#define DP_LINK_TRAIN_PAT_1 REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 0) +#define DP_LINK_TRAIN_PAT_2 REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 1) +#define DP_LINK_TRAIN_PAT_IDLE REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 2) +#define DP_LINK_TRAIN_OFF REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 3) +#define DP_LINK_TRAIN_MASK_CPT REG_GENMASK(10, 8) +#define DP_LINK_TRAIN_PAT_1_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 0) +#define DP_LINK_TRAIN_PAT_2_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 1) +#define DP_LINK_TRAIN_PAT_IDLE_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 2) +#define DP_LINK_TRAIN_OFF_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 3) +#define DP_VOLTAGE_MASK REG_GENMASK(27, 25) +#define DP_VOLTAGE_0_4 REG_FIELD_PREP(DP_VOLTAGE_MASK, 0) +#define DP_VOLTAGE_0_6 REG_FIELD_PREP(DP_VOLTAGE_MASK, 1) +#define DP_VOLTAGE_0_8 REG_FIELD_PREP(DP_VOLTAGE_MASK, 2) +#define DP_VOLTAGE_1_2 REG_FIELD_PREP(DP_VOLTAGE_MASK, 3) +#define DP_PRE_EMPHASIS_MASK REG_GENMASK(24, 22) +#define DP_PRE_EMPHASIS_0 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 0) +#define DP_PRE_EMPHASIS_3_5 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 1) +#define DP_PRE_EMPHASIS_6 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 2) +#define DP_PRE_EMPHASIS_9_5 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 3) +#define DP_PORT_WIDTH_MASK REG_GENMASK(21, 19) +#define DP_PORT_WIDTH(width) REG_FIELD_PREP(DP_PORT_WIDTH_MASK, (width) - 1) +#define DP_ENHANCED_FRAMING REG_BIT(18) +#define EDP_PLL_FREQ_MASK REG_GENMASK(17, 16) +#define EDP_PLL_FREQ_270MHZ REG_FIELD_PREP(EDP_PLL_FREQ_MASK, 0) +#define EDP_PLL_FREQ_162MHZ REG_FIELD_PREP(EDP_PLL_FREQ_MASK, 1) +#define DP_PORT_REVERSAL REG_BIT(15) +#define EDP_PLL_ENABLE REG_BIT(14) +#define DP_CLOCK_OUTPUT_ENABLE REG_BIT(13) +#define DP_SCRAMBLING_DISABLE REG_BIT(12) +#define DP_SCRAMBLING_DISABLE_ILK REG_BIT(7) +#define DP_COLOR_RANGE_16_235 REG_BIT(8) +#define DP_AUDIO_OUTPUT_ENABLE REG_BIT(6) +#define DP_SYNC_VS_HIGH REG_BIT(4) +#define DP_SYNC_HS_HIGH REG_BIT(3) +#define DP_DETECTED REG_BIT(2) + +/* + * Computing GMCH M and N values for the Display Port link + * + * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes + * + * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) + * + * The GMCH value is used internally + * + * bytes_per_pixel is the number of bytes coming out of the plane, + * which is after the LUTs, so we want the bytes for our color format. + * For our current usage, this is always 3, one byte for R, G and B. + */ +#define _PIPEA_DATA_M_G4X 0x70050 +#define _PIPEB_DATA_M_G4X 0x71050 +#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) +/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ +#define TU_SIZE_MASK REG_GENMASK(30, 25) +#define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */ +#define DATA_LINK_M_N_MASK REG_GENMASK(23, 0) +#define DATA_LINK_N_MAX (0x800000) + +#define _PIPEA_DATA_N_G4X 0x70054 +#define _PIPEB_DATA_N_G4X 0x71054 +#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) + +/* + * Computing Link M and N values for the Display Port link + * + * Link M / N = pixel_clock / ls_clk + * + * (the DP spec calls pixel_clock the 'strm_clk') + * + * The Link value is transmitted in the Main Stream + * Attributes and VB-ID. + */ +#define _PIPEA_LINK_M_G4X 0x70060 +#define _PIPEB_LINK_M_G4X 0x71060 +#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) + +#define _PIPEA_LINK_N_G4X 0x70064 +#define _PIPEB_LINK_N_G4X 0x71064 +#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) + +/* Pipe A */ +#define _PIPEADSL 0x70000 +#define PIPEDSL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEADSL) +#define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */ +#define PIPEDSL_LINE_MASK REG_GENMASK(19, 0) + +#define _TRANSACONF 0x70008 +#define TRANSCONF(dev_priv, trans) _MMIO_PIPE2(dev_priv, (trans), _TRANSACONF) +#define TRANSCONF_ENABLE REG_BIT(31) +#define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */ +#define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+ */ +#define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */ +#define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */ +#define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */ +#define TRANSCONF_PIPE_LOCKED REG_BIT(25) +#define TRANSCONF_FORCE_BORDER REG_BIT(25) +#define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */ +#define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */ +#define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0) +#define TRANSCONF_GAMMA_MODE_10BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1) +#define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */ +#define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */ +#define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */ +#define TRANSCONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */ +#define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0) +#define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */ +#define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */ +#define TRANSCONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6) +#define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */ +/* + * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display, + * DBL=power saving pixel doubling, PF-ID* requires panel fitter + */ +#define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */ +#define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */ +#define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0) +#define TRANSCONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1) +#define TRANSCONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3) +#define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */ +#define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */ +#define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20) +#define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */ +#define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x)) +#define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16) +#define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv only */ +#define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14) +#define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13) +#define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */ +#define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */ +#define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */ +#define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */ +#define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */ +#define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */ +#define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0) +#define TRANSCONF_BPC_10 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1) +#define TRANSCONF_BPC_6 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2) +#define TRANSCONF_BPC_12 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3) +#define TRANSCONF_DITHER_EN REG_BIT(4) +#define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2) +#define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0) +#define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1) +#define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2) +#define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3) +#define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0) +#define TRANSCONF_PIXEL_COUNT_SCALING_X4 1 + +#define _PIPEASTAT 0x70024 +#define PIPESTAT(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT) +#define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) +#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) +#define PIPE_CRC_ERROR_ENABLE (1UL << 29) +#define PIPE_CRC_DONE_ENABLE (1UL << 28) +#define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) +#define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) +#define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) +#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) +#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) +#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) +#define PIPE_DPST_EVENT_ENABLE (1UL << 23) +#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) +#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) +#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) +#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) +#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) +#define PERF_COUNTER_INTERRUPT_EN (1UL << 19) +#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ +#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ +#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) +#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) +#define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) +#define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) +#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) +#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) +#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) +#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) +#define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) +#define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) +#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) +#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) +#define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) +#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) +#define PIPE_DPST_EVENT_STATUS (1UL << 7) +#define PIPE_A_PSR_STATUS_VLV (1UL << 6) +#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) +#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) +#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) +#define PIPE_B_PSR_STATUS_VLV (1UL << 3) +#define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) +#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ +#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ +#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) +#define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) +#define PIPE_HBLANK_INT_STATUS (1UL << 0) +#define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) +#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 +#define PIPESTAT_INT_STATUS_MASK 0x0000ffff + +#define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ +#define PIPE_ARB_CTL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A) +#define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13) + +#define _PIPE_MISC_A 0x70030 +#define _PIPE_MISC_B 0x71030 +#define PIPE_MISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B) +#define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */ +#define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */ +#define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */ +#define PIPE_MISC_PSR_MASK_PRIMARY_FLIP REG_BIT(23) /* bdw */ +#define PIPE_MISC_PSR_MASK_SPRITE_ENABLE REG_BIT(22) /* bdw */ +#define PIPE_MISC_PSR_MASK_PIPE_REG_WRITE REG_BIT(21) /* skl+ */ +#define PIPE_MISC_PSR_MASK_CURSOR_MOVE REG_BIT(21) /* bdw */ +#define PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT REG_BIT(20) +#define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11) +#define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ +/* + * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with + * valid values of: 6, 8, 10 BPC. + * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of: + * 6, 8, 10, 12 BPC. + */ +#define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5) +#define PIPE_MISC_BPC_8 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0) +#define PIPE_MISC_BPC_10 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 1) +#define PIPE_MISC_BPC_6 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 2) +#define PIPE_MISC_BPC_12_ADLP REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 4) /* adlp+ */ +#define PIPE_MISC_DITHER_ENABLE REG_BIT(4) +#define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2) +#define PIPE_MISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0) +#define PIPE_MISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1) +#define PIPE_MISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2) +#define PIPE_MISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3) + +#define _PIPE_MISC2_A 0x7002C +#define _PIPE_MISC2_B 0x7102C +#define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B) +#define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24) +#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80) +#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20) +#define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */ +#define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id)) + +#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ +#define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16) +#define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16) +#define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27) +#define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26) +#define PLANEC_INVALID_GTT_INT_EN REG_BIT(25) +#define CURSORC_INVALID_GTT_INT_EN REG_BIT(24) +#define CURSORB_INVALID_GTT_INT_EN REG_BIT(23) +#define CURSORA_INVALID_GTT_INT_EN REG_BIT(22) +#define SPRITED_INVALID_GTT_INT_EN REG_BIT(21) +#define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20) +#define PLANEB_INVALID_GTT_INT_EN REG_BIT(19) +#define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18) +#define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17) +#define PLANEA_INVALID_GTT_INT_EN REG_BIT(16) +#define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0) +#define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0) +#define SPRITEF_INVALID_GTT_STATUS REG_BIT(11) +#define SPRITEE_INVALID_GTT_STATUS REG_BIT(10) +#define PLANEC_INVALID_GTT_STATUS REG_BIT(9) +#define CURSORC_INVALID_GTT_STATUS REG_BIT(8) +#define CURSORB_INVALID_GTT_STATUS REG_BIT(7) +#define CURSORA_INVALID_GTT_STATUS REG_BIT(6) +#define SPRITED_INVALID_GTT_STATUS REG_BIT(5) +#define SPRITEC_INVALID_GTT_STATUS REG_BIT(4) +#define PLANEB_INVALID_GTT_STATUS REG_BIT(3) +#define SPRITEB_INVALID_GTT_STATUS REG_BIT(2) +#define SPRITEA_INVALID_GTT_STATUS REG_BIT(1) +#define PLANEA_INVALID_GTT_STATUS REG_BIT(0) + +#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) +#define CBR_PND_DEADLINE_DISABLE (1 << 31) +#define CBR_PWM_CLOCK_MUX_SELECT (1 << 30) + +#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) +#define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */ + +/* + * The two pipe frame counter registers are not synchronized, so + * reading a stable value is somewhat tricky. The following code + * should work: + * + * do { + * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> + * PIPE_FRAME_HIGH_SHIFT; + * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> + * PIPE_FRAME_LOW_SHIFT); + * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> + * PIPE_FRAME_HIGH_SHIFT); + * } while (high1 != high2); + * frame = (high1 << 8) | low1; + */ +#define _PIPEAFRAMEHIGH 0x70040 +#define PIPEFRAME(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH) +#define PIPE_FRAME_HIGH_MASK 0x0000ffff +#define PIPE_FRAME_HIGH_SHIFT 0 + +#define _PIPEAFRAMEPIXEL 0x70044 +#define PIPEFRAMEPIXEL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL) +#define PIPE_FRAME_LOW_MASK 0xff000000 +#define PIPE_FRAME_LOW_SHIFT 24 +#define PIPE_PIXEL_MASK 0x00ffffff +#define PIPE_PIXEL_SHIFT 0 + +/* GM45+ just has to be different */ +#define _PIPEA_FRMCOUNT_G4X 0x70040 +#define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X) + +#define _PIPEA_FLIPCOUNT_G4X 0x70044 +#define PIPE_FLIPCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X) + +/* CHV pipe B blender */ +#define _CHV_BLEND_A 0x60a00 +#define CHV_BLEND(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A) +#define CHV_BLEND_MASK REG_GENMASK(31, 30) +#define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0) +#define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1) +#define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2) + +#define _CHV_CANVAS_A 0x60a04 +#define CHV_CANVAS(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A) +#define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20) +#define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10) +#define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0) + +/* Display/Sprite base address macros */ +#define DISP_BASEADDR_MASK (0xfffff000) +#define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) +#define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) + +/* + * VBIOS flags + * gen2: + * [00:06] alm,mgm + * [10:16] all + * [30:32] alm,mgm + * gen3+: + * [00:0f] all + * [10:1f] all + * [30:32] all + */ +#define SWF0(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) +#define SWF1(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) +#define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) +#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) + +#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) +#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) +#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ +#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ +#define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ +#define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ +#define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ +#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) +#define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) +#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) +#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) + +/* refresh rate hardware control */ +#define RR_HW_CTL _MMIO(0x45300) +#define RR_HW_LOW_POWER_FRAMES_MASK 0xff +#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 + +#define _PIPEA_DATA_M1 0x60030 +#define _PIPEB_DATA_M1 0x61030 +#define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1) + +#define _PIPEA_DATA_N1 0x60034 +#define _PIPEB_DATA_N1 0x61034 +#define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1) + +#define _PIPEA_DATA_M2 0x60038 +#define _PIPEB_DATA_M2 0x61038 +#define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2) + +#define _PIPEA_DATA_N2 0x6003c +#define _PIPEB_DATA_N2 0x6103c +#define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2) + +#define _PIPEA_LINK_M1 0x60040 +#define _PIPEB_LINK_M1 0x61040 +#define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1) + +#define _PIPEA_LINK_N1 0x60044 +#define _PIPEB_LINK_N1 0x61044 +#define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1) + +#define _PIPEA_LINK_M2 0x60048 +#define _PIPEB_LINK_M2 0x61048 +#define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2) + +#define _PIPEA_LINK_N2 0x6004c +#define _PIPEB_LINK_N2 0x6104c +#define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2) + +/* + * Skylake scalers + */ +#define _ID(id, a, b) _PICK_EVEN(id, a, b) +#define _PS_1A_CTRL 0x68180 +#define _PS_2A_CTRL 0x68280 +#define _PS_1B_CTRL 0x68980 +#define _PS_2B_CTRL 0x68A80 +#define _PS_1C_CTRL 0x69180 +#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ + _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ + _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) +#define PS_SCALER_EN REG_BIT(31) +#define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */ +#define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0) +#define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1) +#define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */ +#define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0) +#define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1) +#define SKL_PS_SCALER_MODE_NV12 REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2) +#define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */ +#define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0) +#define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1) +#define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */ +#define PS_BINDING_MASK REG_GENMASK(27, 25) +#define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0) +#define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1) +#define PS_FILTER_MASK REG_GENMASK(24, 23) +#define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0) +#define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1) +#define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2) +#define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3) +#define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */ +#define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0) +#define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1) +#define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */ +#define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */ +#define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */ +#define PS_VERT3TAP REG_BIT(21) /* skl/bxt */ +#define PS_VERT_INT_INVERT_FIELD REG_BIT(20) +#define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */ +#define PS_PWRUP_PROGRESS REG_BIT(17) +#define PS_V_FILTER_BYPASS REG_BIT(8) +#define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */ +#define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */ +#define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0) +#define PS_VADAPT_MODE_MOD_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1) +#define PS_VADAPT_MODE_MOST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3) +#define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */ +#define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1) +#define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */ +#define PS_Y_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set)) +#define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */ +#define PS_Y_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set)) +#define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */ +#define PS_UV_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set)) +#define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */ +#define PS_UV_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set)) + +#define _PS_PWR_GATE_1A 0x68160 +#define _PS_PWR_GATE_2A 0x68260 +#define _PS_PWR_GATE_1B 0x68960 +#define _PS_PWR_GATE_2B 0x68A60 +#define _PS_PWR_GATE_1C 0x69160 +#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ + _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ + _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) +#define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31) +#define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3) +#define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0) +#define PS_PWR_GATE_SETTLING_TIME_64 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1) +#define PS_PWR_GATE_SETTLING_TIME_96 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2) +#define PS_PWR_GATE_SETTLING_TIME_128 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3) +#define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0) +#define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0) +#define PS_PWR_GATE_SLPEN_16 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1) +#define PS_PWR_GATE_SLPEN_24 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2) +#define PS_PWR_GATE_SLPEN_32 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3) + +#define _PS_WIN_POS_1A 0x68170 +#define _PS_WIN_POS_2A 0x68270 +#define _PS_WIN_POS_1B 0x68970 +#define _PS_WIN_POS_2B 0x68A70 +#define _PS_WIN_POS_1C 0x69170 +#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ + _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ + _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) +#define PS_WIN_XPOS_MASK REG_GENMASK(31, 16) +#define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x)) +#define PS_WIN_YPOS_MASK REG_GENMASK(15, 0) +#define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y)) + +#define _PS_WIN_SZ_1A 0x68174 +#define _PS_WIN_SZ_2A 0x68274 +#define _PS_WIN_SZ_1B 0x68974 +#define _PS_WIN_SZ_2B 0x68A74 +#define _PS_WIN_SZ_1C 0x69174 +#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ + _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ + _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) +#define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16) +#define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w)) +#define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0) +#define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h)) + +#define _PS_VSCALE_1A 0x68184 +#define _PS_VSCALE_2A 0x68284 +#define _PS_VSCALE_1B 0x68984 +#define _PS_VSCALE_2B 0x68A84 +#define _PS_VSCALE_1C 0x69184 +#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ + _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ + _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) + +#define _PS_HSCALE_1A 0x68190 +#define _PS_HSCALE_2A 0x68290 +#define _PS_HSCALE_1B 0x68990 +#define _PS_HSCALE_2B 0x68A90 +#define _PS_HSCALE_1C 0x69190 +#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ + _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ + _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) + +#define _PS_VPHASE_1A 0x68188 +#define _PS_VPHASE_2A 0x68288 +#define _PS_VPHASE_1B 0x68988 +#define _PS_VPHASE_2B 0x68A88 +#define _PS_VPHASE_1C 0x69188 +#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ + _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ + _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) +#define PS_Y_PHASE_MASK REG_GENMASK(31, 16) +#define PS_Y_PHASE(x) REG_FIELD_PREP(PS_Y_PHASE_MASK, (x)) +#define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0) +#define PS_UV_RGB_PHASE(x) REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x)) +#define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ +#define PS_PHASE_TRIP (1 << 0) + +#define _PS_HPHASE_1A 0x68194 +#define _PS_HPHASE_2A 0x68294 +#define _PS_HPHASE_1B 0x68994 +#define _PS_HPHASE_2B 0x68A94 +#define _PS_HPHASE_1C 0x69194 +#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ + _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ + _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) + +#define _PS_ECC_STAT_1A 0x681D0 +#define _PS_ECC_STAT_2A 0x682D0 +#define _PS_ECC_STAT_1B 0x689D0 +#define _PS_ECC_STAT_2B 0x68AD0 +#define _PS_ECC_STAT_1C 0x691D0 +#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ + _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ + _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) + +#define _PS_COEF_SET0_INDEX_1A 0x68198 +#define _PS_COEF_SET0_INDEX_2A 0x68298 +#define _PS_COEF_SET0_INDEX_1B 0x68998 +#define _PS_COEF_SET0_INDEX_2B 0x68A98 +#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \ + _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \ + _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8) +#define PS_COEF_INDEX_AUTO_INC REG_BIT(10) + +#define _PS_COEF_SET0_DATA_1A 0x6819C +#define _PS_COEF_SET0_DATA_2A 0x6829C +#define _PS_COEF_SET0_DATA_1B 0x6899C +#define _PS_COEF_SET0_DATA_2B 0x68A9C +#define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \ + _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \ + _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8) + +/* More Ivybridge lolz */ +#define DE_ERR_INT_IVB (1 << 30) +#define DE_GSE_IVB (1 << 29) +#define DE_PCH_EVENT_IVB (1 << 28) +#define DE_DP_A_HOTPLUG_IVB (1 << 27) +#define DE_AUX_CHANNEL_A_IVB (1 << 26) +#define DE_EDP_PSR_INT_HSW (1 << 19) +#define DE_SPRITEC_FLIP_DONE_IVB (1 << 14) +#define DE_PLANEC_FLIP_DONE_IVB (1 << 13) +#define DE_PIPEC_VBLANK_IVB (1 << 10) +#define DE_SPRITEB_FLIP_DONE_IVB (1 << 9) +#define DE_PLANEB_FLIP_DONE_IVB (1 << 8) +#define DE_PIPEB_VBLANK_IVB (1 << 5) +#define DE_SPRITEA_FLIP_DONE_IVB (1 << 4) +#define DE_PLANEA_FLIP_DONE_IVB (1 << 3) +#define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane))) +#define DE_PIPEA_VBLANK_IVB (1 << 0) +#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) + +#define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c) + +#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) +#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) +#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) +#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) +#define GEN8_PIPE_FIFO_UNDERRUN REG_BIT(31) +#define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29) +#define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28) +#define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */ +#define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl-mtl */ +#define MTL_PIPEDMC_ATS_FAULT REG_BIT(24) /* mtl */ +#define GEN12_PIPEDMC_FLIPQ_DONE REG_BIT(24) /* tgl-adl */ +#define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */ +#define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */ +#define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */ +#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */ +#define MTL_PLANE_ATS_FAULT REG_BIT(18) /* mtl+ */ +#define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */ +#define MTL_PIPEDMC_FLIPQ_DONE REG_BIT(17) /* mtl */ +#define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */ +#define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */ +#define GEN12_DSB_2_INT REG_BIT(15) /* tgl+ */ +#define GEN12_DSB_1_INT REG_BIT(14) /* tgl+ */ +#define GEN12_DSB_0_INT REG_BIT(13) /* tgl+ */ +#define GEN12_DSB_INT(dsb_id) REG_BIT(13 + (dsb_id)) +#define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */ +#define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */ +#define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */ +#define GEN9_PIPE_PLANE3_FAULT REG_BIT(9) /* skl+ */ +#define GEN8_PIPE_SPRITE_FAULT REG_BIT(9) /* bdw */ +#define GEN9_PIPE_PLANE2_FAULT REG_BIT(8) /* skl+ */ +#define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) /* bdw */ +#define GEN9_PIPE_PLANE1_FAULT REG_BIT(7) /* skl+ */ +#define GEN9_PIPE_PLANE4_FLIP_DONE REG_BIT(6) /* skl+ */ +#define GEN9_PIPE_PLANE3_FLIP_DONE REG_BIT(5) /* skl+ */ +#define GEN8_PIPE_SPRITE_FLIP_DONE REG_BIT(5) /* bdw */ +#define GEN9_PIPE_PLANE2_FLIP_DONE REG_BIT(4) /* skl+ */ +#define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */ +#define GEN9_PIPE_PLANE1_FLIP_DONE REG_BIT(3) /* skl+ */ +#define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) \ + REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */ +#define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2) +#define GEN8_PIPE_VSYNC REG_BIT(1) +#define GEN8_PIPE_VBLANK REG_BIT(0) + +#define GEN8_DE_PIPE_IRQ_REGS(pipe) I915_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \ + GEN8_DE_PIPE_IER(pipe), \ + GEN8_DE_PIPE_IIR(pipe)) + +#define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) +#define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1) + +#define GEN8_DE_PORT_ISR _MMIO(0x44440) +#define GEN8_DE_PORT_IMR _MMIO(0x44444) +#define GEN8_DE_PORT_IIR _MMIO(0x44448) +#define GEN8_DE_PORT_IER _MMIO(0x4444c) +#define DSI1_NON_TE (1 << 31) +#define DSI0_NON_TE (1 << 30) +#define ICL_AUX_CHANNEL_E (1 << 29) +#define ICL_AUX_CHANNEL_F (1 << 28) +#define GEN9_AUX_CHANNEL_D (1 << 27) +#define GEN9_AUX_CHANNEL_C (1 << 26) +#define GEN9_AUX_CHANNEL_B (1 << 25) +#define DSI1_TE (1 << 24) +#define DSI0_TE (1 << 23) +#define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) +#define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \ + GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \ + GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) +#define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) +#define BXT_DE_PORT_GMBUS (1 << 1) +#define GEN8_AUX_CHANNEL_A (1 << 0) +#define TGL_DE_PORT_AUX_USBC6 REG_BIT(13) +#define XELPD_DE_PORT_AUX_DDIE REG_BIT(13) +#define TGL_DE_PORT_AUX_USBC5 REG_BIT(12) +#define XELPD_DE_PORT_AUX_DDID REG_BIT(12) +#define TGL_DE_PORT_AUX_USBC4 REG_BIT(11) +#define TGL_DE_PORT_AUX_USBC3 REG_BIT(10) +#define TGL_DE_PORT_AUX_USBC2 REG_BIT(9) +#define TGL_DE_PORT_AUX_USBC1 REG_BIT(8) +#define TGL_DE_PORT_AUX_DDIC REG_BIT(2) +#define TGL_DE_PORT_AUX_DDIB REG_BIT(1) +#define TGL_DE_PORT_AUX_DDIA REG_BIT(0) + +#define GEN8_DE_PORT_IRQ_REGS I915_IRQ_REGS(GEN8_DE_PORT_IMR, \ + GEN8_DE_PORT_IER, \ + GEN8_DE_PORT_IIR) + +#define GEN8_DE_MISC_ISR _MMIO(0x44460) +#define GEN8_DE_MISC_IMR _MMIO(0x44464) +#define GEN8_DE_MISC_IIR _MMIO(0x44468) +#define GEN8_DE_MISC_IER _MMIO(0x4446c) +#define XELPDP_RM_TIMEOUT REG_BIT(29) +#define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27) +#define GEN8_DE_MISC_GSE REG_BIT(27) +#define GEN8_DE_EDP_PSR REG_BIT(19) +#define XELPDP_PMDEMAND_RSP REG_BIT(3) +#define XE2LPD_DBUF_OVERLAP_DETECTED REG_BIT(1) + +#define GEN8_DE_MISC_IRQ_REGS I915_IRQ_REGS(GEN8_DE_MISC_IMR, \ + GEN8_DE_MISC_IER, \ + GEN8_DE_MISC_IIR) + +#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) +#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) +#define GEN11_AUDIO_CODEC_IRQ (1 << 24) +#define GEN11_DE_PCH_IRQ (1 << 23) +#define GEN11_DE_MISC_IRQ (1 << 22) +#define GEN11_DE_HPD_IRQ (1 << 21) +#define GEN11_DE_PORT_IRQ (1 << 20) +#define GEN11_DE_PIPE_C (1 << 18) +#define GEN11_DE_PIPE_B (1 << 17) +#define GEN11_DE_PIPE_A (1 << 16) + +#define GEN11_DE_HPD_ISR _MMIO(0x44470) +#define GEN11_DE_HPD_IMR _MMIO(0x44474) +#define GEN11_DE_HPD_IIR _MMIO(0x44478) +#define GEN11_DE_HPD_IER _MMIO(0x4447c) +#define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) +#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \ + GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \ + GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \ + GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \ + GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \ + GEN11_TC_HOTPLUG(HPD_PORT_TC1)) +#define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) +#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \ + GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \ + GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \ + GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \ + GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \ + GEN11_TBT_HOTPLUG(HPD_PORT_TC1)) + +#define GEN11_DE_HPD_IRQ_REGS I915_IRQ_REGS(GEN11_DE_HPD_IMR, \ + GEN11_DE_HPD_IER, \ + GEN11_DE_HPD_IIR) + +#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) +#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) +#define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) +#define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) +#define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) +#define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4)) + +#define PICAINTERRUPT_ISR _MMIO(0x16FE50) +#define PICAINTERRUPT_IMR _MMIO(0x16FE54) +#define PICAINTERRUPT_IIR _MMIO(0x16FE58) +#define PICAINTERRUPT_IER _MMIO(0x16FE5C) +#define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) +#define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16) +#define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin)) +#define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8) +#define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin)) +#define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6) +#define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) +#define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0) + +#define PICAINTERRUPT_IRQ_REGS I915_IRQ_REGS(PICAINTERRUPT_IMR, \ + PICAINTERRUPT_IER, \ + PICAINTERRUPT_IIR) + +#define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200)) +#define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6) +#define XELPDP_TBT_HPD_LONG_DETECT REG_BIT(5) +#define XELPDP_TBT_HPD_SHORT_DETECT REG_BIT(4) +#define XELPDP_DP_ALT_HOTPLUG_ENABLE REG_BIT(2) +#define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1) +#define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0) + +#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword)) +#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16) +#define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12) +#define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8) +#define XE3_PMDEMAND_PIPES_MASK REG_GENMASK(7, 4) +#define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6) +#define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4) +#define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0) + +#define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31) +#define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20) +#define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8) +#define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4) +#define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0) + +#define GEN12_DCPR_STATUS_1 _MMIO(0x46440) +#define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26) + +#define FUSE_STRAP _MMIO(0x42014) +#define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31) +#define ILK_INTERNAL_DISPLAY_DISABLE REG_BIT(30) +#define ILK_DISPLAY_DEBUG_DISABLE REG_BIT(29) +#define IVB_PIPE_C_DISABLE REG_BIT(28) +#define ILK_HDCP_DISABLE REG_BIT(25) +#define ILK_eDP_A_DISABLE REG_BIT(24) +#define HSW_CDCLK_LIMIT REG_BIT(24) +#define ILK_DESKTOP REG_BIT(23) +#define HSW_CPU_SSC_ENABLE REG_BIT(21) + +#define FUSE_STRAP3 _MMIO(0x42020) +#define HSW_REF_CLK_SELECT REG_BIT(1) + +#define CHICKEN_MISC_2 _MMIO(0x42084) +#define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */ +#define BMG_DARB_HALF_BLK_END_BURST REG_BIT(27) +#define KBL_ARB_FILL_SPARE_14 REG_BIT(14) +#define KBL_ARB_FILL_SPARE_13 REG_BIT(13) +#define GLK_CL2_PWR_DOWN REG_BIT(12) +#define GLK_CL1_PWR_DOWN REG_BIT(11) +#define GLK_CL0_PWR_DOWN REG_BIT(10) + +#define CHICKEN_MISC_3 _MMIO(0x42088) +#define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) - TRANSCODER_A) +#define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A) +#define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A) + +#define CHICKEN_MISC_4 _MMIO(0x4208c) +#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13) +#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0) +#define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x)) + +#define _CHICKEN_TRANS_A 0x420c0 +#define _CHICKEN_TRANS_B 0x420c4 +#define _CHICKEN_TRANS_C 0x420c8 +#define _CHICKEN_TRANS_EDP 0x420cc +#define _CHICKEN_TRANS_D 0x420d8 +#define _CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ + [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ + [TRANSCODER_A] = _CHICKEN_TRANS_A, \ + [TRANSCODER_B] = _CHICKEN_TRANS_B, \ + [TRANSCODER_C] = _CHICKEN_TRANS_C, \ + [TRANSCODER_D] = _CHICKEN_TRANS_D)) +#define _MTL_CHICKEN_TRANS_A 0x604e0 +#define _MTL_CHICKEN_TRANS_B 0x614e0 +#define _MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \ + _MTL_CHICKEN_TRANS_A, \ + _MTL_CHICKEN_TRANS_B) +#define CHICKEN_TRANS(display, trans) (DISPLAY_VER(display) >= 14 ? _MTL_CHICKEN_TRANS(trans) : _CHICKEN_TRANS(trans)) +#define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */ +#define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */ +#define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) +#define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x) +#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */ +#define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23) +#define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19) +#define ADLP_1_BASED_X_GRANULARITY REG_BIT(18) +#define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18) +#define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */ +#define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */ +#define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15) +#define DP_FEC_BS_JITTER_WA REG_BIT(15) +#define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) +#define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4) +#define HDCP_LINE_REKEY_DISABLE REG_BIT(0) + +#define DISP_ARB_CTL2 _MMIO(0x45004) +#define DISP_DATA_PARTITION_5_6 REG_BIT(6) +#define DISP_IPC_ENABLE REG_BIT(3) + +#define GEN7_MSG_CTL _MMIO(0x45010) +#define WAIT_FOR_PCH_RESET_ACK (1 << 1) +#define WAIT_FOR_PCH_FLR_ACK (1 << 0) + +#define _BW_BUDDY0_CTL 0x45130 +#define _BW_BUDDY1_CTL 0x45140 +#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ + _BW_BUDDY0_CTL, \ + _BW_BUDDY1_CTL)) +#define BW_BUDDY_DISABLE REG_BIT(31) +#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) +#define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x) + +#define _BW_BUDDY0_PAGE_MASK 0x45134 +#define _BW_BUDDY1_PAGE_MASK 0x45144 +#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ + _BW_BUDDY0_PAGE_MASK, \ + _BW_BUDDY1_PAGE_MASK)) + +#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) +#define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6) +#define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4) + +#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) +#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) +#define DCPR_MASK_LPMODE REG_BIT(26) +#define DCPR_SEND_RESP_IMM REG_BIT(25) +#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24) + +#define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438) +#define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19) + +#define SKL_DFSM _MMIO(0x51000) +#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) +#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) +#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) +#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) +#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) +#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) +#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) +#define ICL_DFSM_DMC_DISABLE (1 << 23) +#define SKL_DFSM_PIPE_A_DISABLE (1 << 30) +#define SKL_DFSM_PIPE_B_DISABLE (1 << 21) +#define SKL_DFSM_PIPE_C_DISABLE (1 << 28) +#define TGL_DFSM_PIPE_D_DISABLE (1 << 22) +#define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7) +#define XE2LPD_DFSM_DBUF_OVERLAP_DISABLE (1 << 3) + +#define XE2LPD_DE_CAP _MMIO(0x41100) +#define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30) +#define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28) +#define XE2LPD_DE_CAP_DSC_REMOVED 1 +#define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26) +#define XE2LPD_DE_CAP_SCALER_SINGLE 1 + +#define SKL_DSSM _MMIO(0x51004) +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) + +/*GEN11 chicken */ +#define _PIPEA_CHICKEN 0x70038 +#define _PIPEB_CHICKEN 0x71038 +#define _PIPEC_CHICKEN 0x72038 +#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ + _PIPEB_CHICKEN) +#define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30) +#define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30) +#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15) +#define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12) +#define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7) + +#define PCH_DISPLAY_BASE 0xc0000u + +/* south display engine interrupt: IBX */ +#define SDE_AUDIO_POWER_D (1 << 27) +#define SDE_AUDIO_POWER_C (1 << 26) +#define SDE_AUDIO_POWER_B (1 << 25) +#define SDE_AUDIO_POWER_SHIFT (25) +#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) +#define SDE_GMBUS (1 << 24) +#define SDE_AUDIO_HDCP_TRANSB (1 << 23) +#define SDE_AUDIO_HDCP_TRANSA (1 << 22) +#define SDE_AUDIO_HDCP_MASK (3 << 22) +#define SDE_AUDIO_TRANSB (1 << 21) +#define SDE_AUDIO_TRANSA (1 << 20) +#define SDE_AUDIO_TRANS_MASK (3 << 20) +#define SDE_POISON (1 << 19) +/* 18 reserved */ +#define SDE_FDI_RXB (1 << 17) +#define SDE_FDI_RXA (1 << 16) +#define SDE_FDI_MASK (3 << 16) +#define SDE_AUXD (1 << 15) +#define SDE_AUXC (1 << 14) +#define SDE_AUXB (1 << 13) +#define SDE_AUX_MASK (7 << 13) +/* 12 reserved */ +#define SDE_CRT_HOTPLUG (1 << 11) +#define SDE_PORTD_HOTPLUG (1 << 10) +#define SDE_PORTC_HOTPLUG (1 << 9) +#define SDE_PORTB_HOTPLUG (1 << 8) +#define SDE_SDVOB_HOTPLUG (1 << 6) +#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ + SDE_SDVOB_HOTPLUG | \ + SDE_PORTB_HOTPLUG | \ + SDE_PORTC_HOTPLUG | \ + SDE_PORTD_HOTPLUG) +#define SDE_TRANSB_CRC_DONE (1 << 5) +#define SDE_TRANSB_CRC_ERR (1 << 4) +#define SDE_TRANSB_FIFO_UNDER (1 << 3) +#define SDE_TRANSA_CRC_DONE (1 << 2) +#define SDE_TRANSA_CRC_ERR (1 << 1) +#define SDE_TRANSA_FIFO_UNDER (1 << 0) +#define SDE_TRANS_MASK (0x3f) + +/* south display engine interrupt: CPT - CNP */ +#define SDE_AUDIO_POWER_D_CPT (1 << 31) +#define SDE_AUDIO_POWER_C_CPT (1 << 30) +#define SDE_AUDIO_POWER_B_CPT (1 << 29) +#define SDE_AUDIO_POWER_SHIFT_CPT 29 +#define SDE_AUDIO_POWER_MASK_CPT (7 << 29) +#define SDE_AUXD_CPT (1 << 27) +#define SDE_AUXC_CPT (1 << 26) +#define SDE_AUXB_CPT (1 << 25) +#define SDE_AUX_MASK_CPT (7 << 25) +#define SDE_PORTE_HOTPLUG_SPT (1 << 25) +#define SDE_PORTA_HOTPLUG_SPT (1 << 24) +#define SDE_PORTD_HOTPLUG_CPT (1 << 23) +#define SDE_PORTC_HOTPLUG_CPT (1 << 22) +#define SDE_PORTB_HOTPLUG_CPT (1 << 21) +#define SDE_CRT_HOTPLUG_CPT (1 << 19) +#define SDE_SDVOB_HOTPLUG_CPT (1 << 18) +#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ + SDE_SDVOB_HOTPLUG_CPT | \ + SDE_PORTD_HOTPLUG_CPT | \ + SDE_PORTC_HOTPLUG_CPT | \ + SDE_PORTB_HOTPLUG_CPT) +#define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ + SDE_PORTD_HOTPLUG_CPT | \ + SDE_PORTC_HOTPLUG_CPT | \ + SDE_PORTB_HOTPLUG_CPT | \ + SDE_PORTA_HOTPLUG_SPT) +#define SDE_GMBUS_CPT (1 << 17) +#define SDE_ERROR_CPT (1 << 16) +#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) +#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) +#define SDE_FDI_RXC_CPT (1 << 8) +#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) +#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) +#define SDE_FDI_RXB_CPT (1 << 4) +#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) +#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) +#define SDE_FDI_RXA_CPT (1 << 0) +#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ + SDE_AUDIO_CP_REQ_B_CPT | \ + SDE_AUDIO_CP_REQ_A_CPT) +#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ + SDE_AUDIO_CP_CHG_B_CPT | \ + SDE_AUDIO_CP_CHG_A_CPT) +#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ + SDE_FDI_RXB_CPT | \ + SDE_FDI_RXA_CPT) + +/* south display engine interrupt: ICP/TGP/MTP */ +#define SDE_PICAINTERRUPT REG_BIT(31) +#define SDE_GMBUS_ICP (1 << 23) +#define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin)) +#define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */ +#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin)) +#define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \ + SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \ + SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ + SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) +#define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \ + SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \ + SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \ + SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \ + SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \ + SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1)) + +#define SDE_IRQ_REGS I915_IRQ_REGS(SDEIMR, \ + SDEIER, \ + SDEIIR) + +#define SERR_INT _MMIO(0xc4040) +#define SERR_INT_POISON (1 << 31) +#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) + +/* digital port hotplug */ +#define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ +#define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ +#define BXT_DDIA_HPD_INVERT (1 << 27) +#define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ +#define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ +#define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ +#define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ +#define PORTD_HOTPLUG_ENABLE (1 << 20) +#define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ +#define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ +#define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ +#define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ +#define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ +#define PORTD_HOTPLUG_STATUS_MASK (3 << 16) +#define PORTD_HOTPLUG_NO_DETECT (0 << 16) +#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) +#define PORTD_HOTPLUG_LONG_DETECT (2 << 16) +#define PORTC_HOTPLUG_ENABLE (1 << 12) +#define BXT_DDIC_HPD_INVERT (1 << 11) +#define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ +#define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ +#define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ +#define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ +#define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ +#define PORTC_HOTPLUG_STATUS_MASK (3 << 8) +#define PORTC_HOTPLUG_NO_DETECT (0 << 8) +#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) +#define PORTC_HOTPLUG_LONG_DETECT (2 << 8) +#define PORTB_HOTPLUG_ENABLE (1 << 4) +#define BXT_DDIB_HPD_INVERT (1 << 3) +#define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ +#define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ +#define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ +#define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ +#define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ +#define PORTB_HOTPLUG_STATUS_MASK (3 << 0) +#define PORTB_HOTPLUG_NO_DETECT (0 << 0) +#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) +#define PORTB_HOTPLUG_LONG_DETECT (2 << 0) +#define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ + BXT_DDIB_HPD_INVERT | \ + BXT_DDIC_HPD_INVERT) + +#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ +#define PORTE_HOTPLUG_ENABLE (1 << 4) +#define PORTE_HOTPLUG_STATUS_MASK (3 << 0) +#define PORTE_HOTPLUG_NO_DETECT (0 << 0) +#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) +#define PORTE_HOTPLUG_LONG_DETECT (2 << 0) + +/* This register is a reuse of PCH_PORT_HOTPLUG register. The + * functionality covered in PCH_PORT_HOTPLUG is split into + * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. + */ +#define SHOTPLUG_CTL_DDI _MMIO(0xc4030) +#define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4)) +#define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4)) +#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) +#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4)) +#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4)) +#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4)) +#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) + +#define SHOTPLUG_CTL_TC _MMIO(0xc4034) +#define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) +#define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) +#define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) + +#define SHPD_FILTER_CNT _MMIO(0xc4038) +#define SHPD_FILTER_CNT_500_ADJ 0x001D9 +#define SHPD_FILTER_CNT_250 0x000F8 + +#define _PCH_DPLL_A 0xc6014 +#define _PCH_DPLL_B 0xc6018 +#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) + +#define _PCH_FPA0 0xc6040 +#define _PCH_FPB0 0xc6048 +#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) +#define FP_CB_TUNE (0x3 << 22) + +#define _PCH_FPA1 0xc6044 +#define _PCH_FPB1 0xc604c +#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) + +#define PCH_DPLL_TEST _MMIO(0xc606c) + +#define PCH_DREF_CONTROL _MMIO(0xC6200) +#define DREF_CONTROL_MASK 0x7fc3 +#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) +#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) +#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) +#define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) +#define DREF_SSC_SOURCE_DISABLE (0 << 11) +#define DREF_SSC_SOURCE_ENABLE (2 << 11) +#define DREF_SSC_SOURCE_MASK (3 << 11) +#define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) +#define DREF_NONSPREAD_CK505_ENABLE (1 << 9) +#define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) +#define DREF_NONSPREAD_SOURCE_MASK (3 << 9) +#define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) +#define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) +#define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) +#define DREF_SSC4_DOWNSPREAD (0 << 6) +#define DREF_SSC4_CENTERSPREAD (1 << 6) +#define DREF_SSC1_DISABLE (0 << 1) +#define DREF_SSC1_ENABLE (1 << 1) +#define DREF_SSC4_DISABLE (0) +#define DREF_SSC4_ENABLE (1) + +#define PCH_RAWCLK_FREQ _MMIO(0xc6204) +#define FDL_TP1_TIMER_SHIFT 12 +#define FDL_TP1_TIMER_MASK (3 << 12) +#define FDL_TP2_TIMER_SHIFT 10 +#define FDL_TP2_TIMER_MASK (3 << 10) +#define RAWCLK_FREQ_MASK 0x3ff +#define CNP_RAWCLK_DIV_MASK (0x3ff << 16) +#define CNP_RAWCLK_DIV(div) ((div) << 16) +#define CNP_RAWCLK_FRAC_MASK (0xf << 26) +#define CNP_RAWCLK_DEN(den) ((den) << 26) +#define ICP_RAWCLK_NUM(num) ((num) << 11) + +#define PCH_DPLL_TMR_CFG _MMIO(0xc6208) + +#define PCH_SSC4_PARMS _MMIO(0xc6210) +#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) + +#define PCH_DPLL_SEL _MMIO(0xc7000) +#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) +#define TRANS_DPLLA_SEL(pipe) 0 +#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) + +/* transcoder */ +#define _PCH_TRANS_HTOTAL_A 0xe0000 +#define _PCH_TRANS_HTOTAL_B 0xe1000 +#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) +#define TRANS_HTOTAL_SHIFT 16 +#define TRANS_HACTIVE_SHIFT 0 + +#define _PCH_TRANS_HBLANK_A 0xe0004 +#define _PCH_TRANS_HBLANK_B 0xe1004 +#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) +#define TRANS_HBLANK_END_SHIFT 16 +#define TRANS_HBLANK_START_SHIFT 0 + +#define _PCH_TRANS_HSYNC_A 0xe0008 +#define _PCH_TRANS_HSYNC_B 0xe1008 +#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) +#define TRANS_HSYNC_END_SHIFT 16 +#define TRANS_HSYNC_START_SHIFT 0 + +#define _PCH_TRANS_VTOTAL_A 0xe000c +#define _PCH_TRANS_VTOTAL_B 0xe100c +#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) +#define TRANS_VTOTAL_SHIFT 16 +#define TRANS_VACTIVE_SHIFT 0 + +#define _PCH_TRANS_VBLANK_A 0xe0010 +#define _PCH_TRANS_VBLANK_B 0xe1010 +#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) +#define TRANS_VBLANK_END_SHIFT 16 +#define TRANS_VBLANK_START_SHIFT 0 + +#define _PCH_TRANS_VSYNC_A 0xe0014 +#define _PCH_TRANS_VSYNC_B 0xe1014 +#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) +#define TRANS_VSYNC_END_SHIFT 16 +#define TRANS_VSYNC_START_SHIFT 0 + +#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 +#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 +#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) + +#define _PCH_TRANSA_DATA_M1 0xe0030 +#define _PCH_TRANSB_DATA_M1 0xe1030 +#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) + +#define _PCH_TRANSA_DATA_N1 0xe0034 +#define _PCH_TRANSB_DATA_N1 0xe1034 +#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) + +#define _PCH_TRANSA_DATA_M2 0xe0038 +#define _PCH_TRANSB_DATA_M2 0xe1038 +#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) + +#define _PCH_TRANSA_DATA_N2 0xe003c +#define _PCH_TRANSB_DATA_N2 0xe103c +#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) + +#define _PCH_TRANSA_LINK_M1 0xe0040 +#define _PCH_TRANSB_LINK_M1 0xe1040 +#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) + +#define _PCH_TRANSA_LINK_N1 0xe0044 +#define _PCH_TRANSB_LINK_N1 0xe1044 +#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) + +#define _PCH_TRANSA_LINK_M2 0xe0048 +#define _PCH_TRANSB_LINK_M2 0xe1048 +#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) + +#define _PCH_TRANSA_LINK_N2 0xe004c +#define _PCH_TRANSB_LINK_N2 0xe104c +#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) + +/* Per-transcoder DIP controls (PCH) */ +#define _VIDEO_DIP_CTL_A 0xe0200 +#define _VIDEO_DIP_CTL_B 0xe1200 +#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) + +#define _VIDEO_DIP_DATA_A 0xe0208 +#define _VIDEO_DIP_DATA_B 0xe1208 +#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) + +#define _VIDEO_DIP_GCP_A 0xe0210 +#define _VIDEO_DIP_GCP_B 0xe1210 +#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) +#define GCP_COLOR_INDICATION (1 << 2) +#define GCP_DEFAULT_PHASE_ENABLE (1 << 1) +#define GCP_AV_MUTE (1 << 0) + +/* Per-transcoder DIP controls (VLV) */ +#define _VLV_VIDEO_DIP_CTL_A 0x60200 +#define _VLV_VIDEO_DIP_CTL_B 0x61170 +#define _CHV_VIDEO_DIP_CTL_C 0x611f0 +#define VLV_TVIDEO_DIP_CTL(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \ + _VLV_VIDEO_DIP_CTL_A, \ + _VLV_VIDEO_DIP_CTL_B, \ + _CHV_VIDEO_DIP_CTL_C) + +#define _VLV_VIDEO_DIP_DATA_A 0x60208 +#define _VLV_VIDEO_DIP_DATA_B 0x61174 +#define _CHV_VIDEO_DIP_DATA_C 0x611f4 +#define VLV_TVIDEO_DIP_DATA(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \ + _VLV_VIDEO_DIP_DATA_A, \ + _VLV_VIDEO_DIP_DATA_B, \ + _CHV_VIDEO_DIP_DATA_C) + +#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210 +#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178 +#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C 0x611f8 +#define VLV_TVIDEO_DIP_GCP(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \ + _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ + _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, \ + _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) + +/* Haswell DIP controls */ +#define _HSW_VIDEO_DIP_CTL_A 0x60200 +#define _HSW_VIDEO_DIP_CTL_B 0x61200 +#define HSW_TVIDEO_DIP_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A) + +#define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 +#define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 +#define HSW_TVIDEO_DIP_AVI_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) + +#define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 +#define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 +#define HSW_TVIDEO_DIP_VS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) + +#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 +#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 +#define HSW_TVIDEO_DIP_SPD_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) + +#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 +#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 +#define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) + +#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 +#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 +#define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) + +/*ADLP and later: */ +#define _ADL_VIDEO_DIP_AS_DATA_A 0x60484 +#define _ADL_VIDEO_DIP_AS_DATA_B 0x61484 +#define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans,\ + _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4) + +#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 +#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 +#define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) + +#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 +#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 +#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 +#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 +#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 +#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 +#define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 +#define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 +#define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 +#define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 + +#define _HSW_VIDEO_DIP_GCP_A 0x60210 +#define _HSW_VIDEO_DIP_GCP_B 0x61210 +#define HSW_TVIDEO_DIP_GCP(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A) + +#define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350 +#define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350 +#define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) + +#define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 +#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 +#define ICL_VIDEO_DIP_PPS_ECC(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) + +#define _HSW_STEREO_3D_CTL_A 0x70020 +#define _HSW_STEREO_3D_CTL_B 0x71020 +#define HSW_STEREO_3D_CTL(dev_priv, trans) _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A) +#define S3D_ENABLE (1 << 31) + +#define _PCH_TRANSACONF 0xf0008 +#define _PCH_TRANSBCONF 0xf1008 +#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) +#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ +#define TRANS_ENABLE REG_BIT(31) +#define TRANS_STATE_ENABLE REG_BIT(30) +#define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */ +#define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */ +#define TRANS_INTERLACE_MASK REG_GENMASK(23, 21) +#define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0) +#define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */ +#define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3) +#define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */ +#define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0) +#define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1) +#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2) +#define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3) + +#define PCH_DP_B _MMIO(0xe4100) +#define PCH_DP_C _MMIO(0xe4200) +#define PCH_DP_D _MMIO(0xe4300) + +/* CPT */ +#define _TRANS_DP_CTL_A 0xe0300 +#define _TRANS_DP_CTL_B 0xe1300 +#define _TRANS_DP_CTL_C 0xe2300 +#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) +#define TRANS_DP_OUTPUT_ENABLE REG_BIT(31) +#define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29) +#define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3) +#define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B) +#define TRANS_DP_AUDIO_ONLY REG_BIT(26) +#define TRANS_DP_ENH_FRAMING REG_BIT(18) +#define TRANS_DP_BPC_MASK REG_GENMASK(10, 9) +#define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0) +#define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1) +#define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2) +#define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3) +#define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4) +#define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3) + +#define _TRANS_DP2_CTL_A 0x600a0 +#define _TRANS_DP2_CTL_B 0x610a0 +#define _TRANS_DP2_CTL_C 0x620a0 +#define _TRANS_DP2_CTL_D 0x630a0 +#define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B) +#define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31) +#define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30) +#define TRANS_DP2_DEBUG_ENABLE REG_BIT(23) + +#define _TRANS_DP2_VFREQHIGH_A 0x600a4 +#define _TRANS_DP2_VFREQHIGH_B 0x610a4 +#define _TRANS_DP2_VFREQHIGH_C 0x620a4 +#define _TRANS_DP2_VFREQHIGH_D 0x630a4 +#define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B) +#define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8) +#define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz)) + +#define _TRANS_DP2_VFREQLOW_A 0x600a8 +#define _TRANS_DP2_VFREQLOW_B 0x610a8 +#define _TRANS_DP2_VFREQLOW_C 0x620a8 +#define _TRANS_DP2_VFREQLOW_D 0x630a8 +#define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B) + +#define _DP_MIN_HBLANK_CTL_A 0x600ac +#define _DP_MIN_HBLANK_CTL_B 0x610ac +#define DP_MIN_HBLANK_CTL(trans) _MMIO_TRANS(trans, _DP_MIN_HBLANK_CTL_A, _DP_MIN_HBLANK_CTL_B) + +/* SNB eDP training params */ +/* SNB A-stepping */ +#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) +#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) +#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) +#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) +/* SNB B-stepping */ +#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22) +#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22) +#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22) +#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22) +#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22) +#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22) + +/* IVB */ +#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) +#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) +#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) +#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) +#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) +#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) +#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22) + +/* legacy values */ +#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) +#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) +#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) +#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) +#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) + +#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22) + +#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) +#define PIXEL_OVERLAP_CNT_MASK (3 << 30) +#define PIXEL_OVERLAP_CNT_SHIFT 30 + +/* + * HSW - ICL power wells + * + * Platforms have up to 3 power well control register sets, each set + * controlling up to 16 power wells via a request/status HW flag tuple: + * - main (HSW_PWR_WELL_CTL[1-4]) + * - AUX (ICL_PWR_WELL_CTL_AUX[1-4]) + * - DDI (ICL_PWR_WELL_CTL_DDI[1-4]) + * Each control register set consists of up to 4 registers used by different + * sources that can request a power well to be enabled: + * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1) + * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2) + * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set) + * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4) + */ +#define HSW_PWR_WELL_CTL1 _MMIO(0x45400) +#define HSW_PWR_WELL_CTL2 _MMIO(0x45404) +#define HSW_PWR_WELL_CTL3 _MMIO(0x45408) +#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C) +#define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) +#define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) + +/* HSW/BDW power well */ +#define HSW_PW_CTL_IDX_GLOBAL 15 + +/* SKL/BXT/GLK power wells */ +#define SKL_PW_CTL_IDX_PW_2 15 +#define SKL_PW_CTL_IDX_PW_1 14 +#define GLK_PW_CTL_IDX_AUX_C 10 +#define GLK_PW_CTL_IDX_AUX_B 9 +#define GLK_PW_CTL_IDX_AUX_A 8 +#define SKL_PW_CTL_IDX_DDI_D 4 +#define SKL_PW_CTL_IDX_DDI_C 3 +#define SKL_PW_CTL_IDX_DDI_B 2 +#define SKL_PW_CTL_IDX_DDI_A_E 1 +#define GLK_PW_CTL_IDX_DDI_A 1 +#define SKL_PW_CTL_IDX_MISC_IO 0 + +/* ICL/TGL - power wells */ +#define TGL_PW_CTL_IDX_PW_5 4 +#define ICL_PW_CTL_IDX_PW_4 3 +#define ICL_PW_CTL_IDX_PW_3 2 +#define ICL_PW_CTL_IDX_PW_2 1 +#define ICL_PW_CTL_IDX_PW_1 0 + +/* XE_LPD - power wells */ +#define XELPD_PW_CTL_IDX_PW_D 8 +#define XELPD_PW_CTL_IDX_PW_C 7 +#define XELPD_PW_CTL_IDX_PW_B 6 +#define XELPD_PW_CTL_IDX_PW_A 5 + +#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) +#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) +#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) +#define TGL_PW_CTL_IDX_AUX_TBT6 14 +#define TGL_PW_CTL_IDX_AUX_TBT5 13 +#define TGL_PW_CTL_IDX_AUX_TBT4 12 +#define ICL_PW_CTL_IDX_AUX_TBT4 11 +#define TGL_PW_CTL_IDX_AUX_TBT3 11 +#define ICL_PW_CTL_IDX_AUX_TBT3 10 +#define TGL_PW_CTL_IDX_AUX_TBT2 10 +#define ICL_PW_CTL_IDX_AUX_TBT2 9 +#define TGL_PW_CTL_IDX_AUX_TBT1 9 +#define ICL_PW_CTL_IDX_AUX_TBT1 8 +#define TGL_PW_CTL_IDX_AUX_TC6 8 +#define XELPD_PW_CTL_IDX_AUX_E 8 +#define TGL_PW_CTL_IDX_AUX_TC5 7 +#define XELPD_PW_CTL_IDX_AUX_D 7 +#define TGL_PW_CTL_IDX_AUX_TC4 6 +#define ICL_PW_CTL_IDX_AUX_F 5 +#define TGL_PW_CTL_IDX_AUX_TC3 5 +#define ICL_PW_CTL_IDX_AUX_E 4 +#define TGL_PW_CTL_IDX_AUX_TC2 4 +#define ICL_PW_CTL_IDX_AUX_D 3 +#define TGL_PW_CTL_IDX_AUX_TC1 3 +#define ICL_PW_CTL_IDX_AUX_C 2 +#define ICL_PW_CTL_IDX_AUX_B 1 +#define ICL_PW_CTL_IDX_AUX_A 0 + +#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) +#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) +#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) +#define XELPD_PW_CTL_IDX_DDI_E 8 +#define TGL_PW_CTL_IDX_DDI_TC6 8 +#define XELPD_PW_CTL_IDX_DDI_D 7 +#define TGL_PW_CTL_IDX_DDI_TC5 7 +#define TGL_PW_CTL_IDX_DDI_TC4 6 +#define ICL_PW_CTL_IDX_DDI_F 5 +#define TGL_PW_CTL_IDX_DDI_TC3 5 +#define ICL_PW_CTL_IDX_DDI_E 4 +#define TGL_PW_CTL_IDX_DDI_TC2 4 +#define ICL_PW_CTL_IDX_DDI_D 3 +#define TGL_PW_CTL_IDX_DDI_TC1 3 +#define ICL_PW_CTL_IDX_DDI_C 2 +#define ICL_PW_CTL_IDX_DDI_B 1 +#define ICL_PW_CTL_IDX_DDI_A 0 + +/* HSW - power well misc debug registers */ +#define HSW_PWR_WELL_CTL5 _MMIO(0x45410) +#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) +#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) +#define HSW_PWR_WELL_FORCE_ON (1 << 19) +#define HSW_PWR_WELL_CTL6 _MMIO(0x45414) + +#define SKL_FUSE_STATUS _MMIO(0x42000) +#define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) +/* + * PG0 is HW controlled, so doesn't have a corresponding power well control knob + * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 + */ +#define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ + ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) +/* + * PG0 is HW controlled, so doesn't have a corresponding power well control knob + * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 + */ +#define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ + ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) +#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) + +/* Per-pipe DDI Function Control */ +#define _TRANS_DDI_FUNC_CTL_A 0x60400 +#define _TRANS_DDI_FUNC_CTL_B 0x61400 +#define _TRANS_DDI_FUNC_CTL_C 0x62400 +#define _TRANS_DDI_FUNC_CTL_D 0x63400 +#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 +#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 +#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 +#define TRANS_DDI_FUNC_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL_A) + +#define TRANS_DDI_FUNC_ENABLE (1 << 31) +/* Those bits are ignored by pipe EDP since it can only connect to DDI A */ +#define TRANS_DDI_PORT_SHIFT 28 +#define TGL_TRANS_DDI_PORT_SHIFT 27 +#define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT) +#define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT) +#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) +#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT) +#define TRANS_DDI_MODE_SELECT_MASK (7 << 24) +#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) +#define TRANS_DDI_MODE_SELECT_DVI (1 << 24) +#define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) +#define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) +#define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) +#define TRANS_DDI_BPC_MASK (7 << 20) +#define TRANS_DDI_BPC_8 (0 << 20) +#define TRANS_DDI_BPC_10 (1 << 20) +#define TRANS_DDI_BPC_6 (2 << 20) +#define TRANS_DDI_BPC_12 (3 << 20) +#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) +#define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x)) +#define TRANS_DDI_PVSYNC (1 << 17) +#define TRANS_DDI_PHSYNC (1 << 16) +#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) +#define XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(15) +#define TRANS_DDI_EDP_INPUT_MASK (7 << 12) +#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) +#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) +#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) +#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) +#define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) +#define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12) +#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) +#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ + REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans) +#define TRANS_DDI_HDCP_SIGNALLING (1 << 9) +#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) +#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) +#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) +#define TRANS_DDI_HDCP_SELECT REG_BIT(5) +#define TRANS_DDI_BFI_ENABLE (1 << 4) +#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) +#define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1) +#define TRANS_DDI_PORT_WIDTH(width) REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1) +#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) +#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ + | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ + | TRANS_DDI_HDMI_SCRAMBLING) + +#define _TRANS_DDI_FUNC_CTL2_A 0x60404 +#define _TRANS_DDI_FUNC_CTL2_B 0x61404 +#define _TRANS_DDI_FUNC_CTL2_C 0x62404 +#define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 +#define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 +#define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 +#define TRANS_DDI_FUNC_CTL2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A) +#define PORT_SYNC_MODE_ENABLE REG_BIT(4) +#define CMTG_SECONDARY_MODE REG_BIT(3) +#define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0) +#define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x)) + +#define TRANS_CMTG_CHICKEN _MMIO(0x6fa90) +#define DISABLE_DPT_CLK_GATING REG_BIT(1) + +/* DisplayPort Transport Control */ +#define _DP_TP_CTL_A 0x64040 +#define _DP_TP_CTL_B 0x64140 +#define _TGL_DP_TP_CTL_A 0x60540 +#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) +#define TGL_DP_TP_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A) +#define DP_TP_CTL_ENABLE REG_BIT(31) +#define DP_TP_CTL_FEC_ENABLE REG_BIT(30) +#define DP_TP_CTL_MODE_MASK REG_BIT(27) +#define DP_TP_CTL_MODE_SST REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 0) +#define DP_TP_CTL_MODE_MST REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 1) +#define DP_TP_CTL_FORCE_ACT REG_BIT(25) +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK REG_GENMASK(20, 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 0) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 1) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 2) +#define DP_TP_CTL_ENHANCED_FRAME_ENABLE REG_BIT(18) +#define DP_TP_CTL_FDI_AUTOTRAIN REG_BIT(15) +#define DP_TP_CTL_LINK_TRAIN_MASK REG_GENMASK(10, 8) +#define DP_TP_CTL_LINK_TRAIN_PAT1 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 0) +#define DP_TP_CTL_LINK_TRAIN_PAT2 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 1) +#define DP_TP_CTL_LINK_TRAIN_PAT3 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 4) +#define DP_TP_CTL_LINK_TRAIN_PAT4 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 5) +#define DP_TP_CTL_LINK_TRAIN_IDLE REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 2) +#define DP_TP_CTL_LINK_TRAIN_NORMAL REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 3) +#define DP_TP_CTL_SCRAMBLE_DISABLE REG_BIT(7) + +/* DisplayPort Transport Status */ +#define _DP_TP_STATUS_A 0x64044 +#define _DP_TP_STATUS_B 0x64144 +#define _TGL_DP_TP_STATUS_A 0x60544 +#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) +#define TGL_DP_TP_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A) +#define DP_TP_STATUS_FEC_ENABLE_LIVE REG_BIT(28) +#define DP_TP_STATUS_IDLE_DONE REG_BIT(25) +#define DP_TP_STATUS_ACT_SENT REG_BIT(24) +#define DP_TP_STATUS_MODE_STATUS_MST REG_BIT(23) +#define DP_TP_STATUS_STREAMS_ENABLED_MASK REG_GENMASK(18, 16) /* 17:16 on hsw but bit 18 mbz */ +#define DP_TP_STATUS_AUTOTRAIN_DONE REG_BIT(12) +#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2_MASK REG_GENMASK(9, 8) +#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1_MASK REG_GENMASK(5, 4) +#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0_MASK REG_GENMASK(1, 0) + +/* DDI Buffer Control */ +#define _DDI_BUF_CTL_A 0x64000 +#define _DDI_BUF_CTL_B 0x64100 +/* Known as DDI_CTL_DE in MTL+ */ +#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) +#define DDI_BUF_CTL_ENABLE REG_BIT(31) +#define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29) +#define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28) +#define DDI_BUF_EMP_MASK REG_GENMASK(27, 24) +#define DDI_BUF_TRANS_SELECT(n) REG_FIELD_PREP(DDI_BUF_EMP_MASK, (n)) +#define DDI_BUF_PHY_LINK_RATE_MASK REG_GENMASK(23, 20) +#define DDI_BUF_PHY_LINK_RATE(r) REG_FIELD_PREP(DDI_BUF_PHY_LINK_RATE_MASK, (r)) +#define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18) +#define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0) +#define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1) +#define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2) +#define DDI_BUF_PORT_REVERSAL REG_BIT(16) +#define DDI_BUF_LANE_STAGGER_DELAY_MASK REG_GENMASK(15, 8) +#define DDI_BUF_LANE_STAGGER_DELAY(symbols) REG_FIELD_PREP(DDI_BUF_LANE_STAGGER_DELAY_MASK, \ + (symbols)) +#define DDI_BUF_IS_IDLE REG_BIT(7) +#define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) +#define DDI_A_4_LANES REG_BIT(4) +#define DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1) +#define DDI_PORT_WIDTH(width) REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \ + ((width) == 3 ? 4 : (width) - 1)) +#define DDI_PORT_WIDTH_SHIFT 1 +#define DDI_INIT_DISPLAY_DETECTED REG_BIT(0) + +/* DDI Buffer Translations */ +#define _DDI_BUF_TRANS_A 0x64E00 +#define _DDI_BUF_TRANS_B 0x64E60 +#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) +#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) +#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) + +/* DDI DP Compliance Control */ +#define _DDI_DP_COMP_CTL_A 0x605F0 +#define _DDI_DP_COMP_CTL_B 0x615F0 +#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) +#define DDI_DP_COMP_CTL_ENABLE (1 << 31) +#define DDI_DP_COMP_CTL_D10_2 (0 << 28) +#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) +#define DDI_DP_COMP_CTL_PRBS7 (2 << 28) +#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28) +#define DDI_DP_COMP_CTL_HBR2 (4 << 28) +#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) +#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) + +/* DDI DP Compliance Pattern */ +#define _DDI_DP_COMP_PAT_A 0x605F4 +#define _DDI_DP_COMP_PAT_B 0x615F4 +#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4) + +/* LPT PIXCLK_GATE */ +#define PIXCLK_GATE _MMIO(0xC6020) +#define PIXCLK_GATE_UNGATE (1 << 0) +#define PIXCLK_GATE_GATE (0 << 0) + +/* SPLL */ +#define SPLL_CTL _MMIO(0x46020) +#define SPLL_PLL_ENABLE (1 << 31) +#define SPLL_REF_BCLK (0 << 28) +#define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ +#define SPLL_REF_NON_SSC_HSW (2 << 28) +#define SPLL_REF_PCH_SSC_BDW (2 << 28) +#define SPLL_REF_LCPLL (3 << 28) +#define SPLL_REF_MASK (3 << 28) +#define SPLL_FREQ_810MHz (0 << 26) +#define SPLL_FREQ_1350MHz (1 << 26) +#define SPLL_FREQ_2700MHz (2 << 26) +#define SPLL_FREQ_MASK (3 << 26) + +/* WRPLL */ +#define _WRPLL_CTL1 0x46040 +#define _WRPLL_CTL2 0x46060 +#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) +#define WRPLL_PLL_ENABLE (1 << 31) +#define WRPLL_REF_BCLK (0 << 28) +#define WRPLL_REF_PCH_SSC (1 << 28) +#define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ +#define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */ +#define WRPLL_REF_LCPLL (3 << 28) +#define WRPLL_REF_MASK (3 << 28) +/* WRPLL divider programming */ +#define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0) +#define WRPLL_DIVIDER_REF_MASK (0xff) +#define WRPLL_DIVIDER_POST(x) ((x) << 8) +#define WRPLL_DIVIDER_POST_MASK (0x3f << 8) +#define WRPLL_DIVIDER_POST_SHIFT 8 +#define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16) +#define WRPLL_DIVIDER_FB_SHIFT 16 +#define WRPLL_DIVIDER_FB_MASK (0xff << 16) + +/* Port clock selection */ +#define _PORT_CLK_SEL_A 0x46100 +#define _PORT_CLK_SEL_B 0x46104 +#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) +#define PORT_CLK_SEL_MASK REG_GENMASK(31, 29) +#define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0) +#define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1) +#define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2) +#define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3) +#define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll)) +#define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4) +#define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5) +#define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7) + +/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ +#define DDI_CLK_SEL(port) PORT_CLK_SEL(port) +#define DDI_CLK_SEL_MASK REG_GENMASK(31, 28) +#define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0) +#define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8) +#define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC) +#define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD) +#define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE) +#define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF) + +/* Transcoder clock selection */ +#define _TRANS_CLK_SEL_A 0x46140 +#define _TRANS_CLK_SEL_B 0x46144 +#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) +/* For each transcoder, we need to select the corresponding port clock */ +#define TRANS_CLK_SEL_DISABLED (0x0 << 29) +#define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) +#define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28) +#define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28) + +#define CDCLK_FREQ _MMIO(0x46200) + +#define _TRANSA_MSA_MISC 0x60410 +#define _TRANSB_MSA_MISC 0x61410 +#define _TRANSC_MSA_MISC 0x62410 +#define _TRANS_EDP_MSA_MISC 0x6f410 +#define TRANS_MSA_MISC(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANSA_MSA_MISC) +/* See DP_MSA_MISC_* for the bit definitions */ + +#define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C +#define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C +#define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C +#define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C +#define TRANS_SET_CONTEXT_LATENCY(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY) +#define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0) +#define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x)) + +/* LCPLL Control */ +#define LCPLL_CTL _MMIO(0x130040) +#define LCPLL_PLL_DISABLE (1 << 31) +#define LCPLL_PLL_LOCK (1 << 30) +#define LCPLL_REF_NON_SSC (0 << 28) +#define LCPLL_REF_BCLK (2 << 28) +#define LCPLL_REF_PCH_SSC (3 << 28) +#define LCPLL_REF_MASK (3 << 28) +#define LCPLL_CLK_FREQ_MASK (3 << 26) +#define LCPLL_CLK_FREQ_450 (0 << 26) +#define LCPLL_CLK_FREQ_54O_BDW (1 << 26) +#define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) +#define LCPLL_CLK_FREQ_675_BDW (3 << 26) +#define LCPLL_CD_CLOCK_DISABLE (1 << 25) +#define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24) +#define LCPLL_CD2X_CLOCK_DISABLE (1 << 23) +#define LCPLL_POWER_DOWN_ALLOW (1 << 22) +#define LCPLL_CD_SOURCE_FCLK (1 << 21) +#define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19) + +/* + * SKL Clocks + */ +/* CDCLK_CTL */ +#define CDCLK_CTL _MMIO(0x46000) +#define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26) +#define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0) +#define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1) +#define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2) +#define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3) +#define MDCLK_SOURCE_SEL_MASK REG_GENMASK(25, 25) +#define MDCLK_SOURCE_SEL_CD2XCLK REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0) +#define MDCLK_SOURCE_SEL_CDCLK_PLL REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1) +#define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22) +#define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0) +#define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1) +#define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2) +#define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3) +#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) +#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) +#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) +#define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19) +#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) +#define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe) +#define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE +#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) +#define CDCLK_FREQ_DECIMAL_MASK (0x7ff) + +/* CDCLK_SQUASH_CTL */ +#define CDCLK_SQUASH_CTL _MMIO(0x46008) +#define CDCLK_SQUASH_ENABLE REG_BIT(31) +#define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24) +#define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x)) +#define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0) +#define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x)) + +/* LCPLL_CTL */ +#define LCPLL1_CTL _MMIO(0x46010) +#define LCPLL2_CTL _MMIO(0x46014) +#define LCPLL_PLL_ENABLE (1 << 31) + +/* DPLL control1 */ +#define DPLL_CTRL1 _MMIO(0x6C058) +#define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) +#define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) +#define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) +#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) +#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) +#define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) +#define DPLL_CTRL1_LINK_RATE_2700 0 +#define DPLL_CTRL1_LINK_RATE_1350 1 +#define DPLL_CTRL1_LINK_RATE_810 2 +#define DPLL_CTRL1_LINK_RATE_1620 3 +#define DPLL_CTRL1_LINK_RATE_1080 4 +#define DPLL_CTRL1_LINK_RATE_2160 5 + +/* DPLL control2 */ +#define DPLL_CTRL2 _MMIO(0x6C05C) +#define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) +#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) +#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) +#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) +#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) + +/* DPLL Status */ +#define DPLL_STATUS _MMIO(0x6C060) +#define DPLL_LOCK(id) (1 << ((id) * 8)) + +/* DPLL cfg */ +#define _DPLL1_CFGCR1 0x6C040 +#define _DPLL2_CFGCR1 0x6C048 +#define _DPLL3_CFGCR1 0x6C050 +#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) +#define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) +#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) +#define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) +#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) + +#define _DPLL1_CFGCR2 0x6C044 +#define _DPLL2_CFGCR2 0x6C04C +#define _DPLL3_CFGCR2 0x6C054 +#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) +#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) +#define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) +#define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) +#define DPLL_CFGCR2_KDIV_MASK (3 << 5) +#define DPLL_CFGCR2_KDIV(x) ((x) << 5) +#define DPLL_CFGCR2_KDIV_5 (0 << 5) +#define DPLL_CFGCR2_KDIV_2 (1 << 5) +#define DPLL_CFGCR2_KDIV_3 (2 << 5) +#define DPLL_CFGCR2_KDIV_1 (3 << 5) +#define DPLL_CFGCR2_PDIV_MASK (7 << 2) +#define DPLL_CFGCR2_PDIV(x) ((x) << 2) +#define DPLL_CFGCR2_PDIV_1 (0 << 2) +#define DPLL_CFGCR2_PDIV_2 (1 << 2) +#define DPLL_CFGCR2_PDIV_3 (2 << 2) +#define DPLL_CFGCR2_PDIV_7 (4 << 2) +#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2) +#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) + +/* ICL Clocks */ +#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) +#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ + (tc_port) + 12 : \ + (tc_port) - TC_PORT_4 + 21)) +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ + (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ + ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) + +/* + * DG1 Clocks + * First registers controls the first A and B, while the second register + * controls the phy C and D. The bits on these registers are the + * same, but refer to different phys + */ +#define _DG1_DPCLKA_CFGCR0 0x164280 +#define _DG1_DPCLKA1_CFGCR0 0x16C280 +#define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2) +#define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2) +#define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \ + _DG1_DPCLKA_CFGCR0, \ + _DG1_DPCLKA1_CFGCR0) +#define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10) +#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2) +#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) +#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) + +/* ADLS Clocks */ +#define _ADLS_DPCLKA_CFGCR0 0x164280 +#define _ADLS_DPCLKA_CFGCR1 0x1642BC +#define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \ + _ADLS_DPCLKA_CFGCR0, \ + _ADLS_DPCLKA_CFGCR1) +#define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2) +/* ADLS DPCLKA_CFGCR0 DDI mask */ +#define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4) +#define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2) +#define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0) +/* ADLS DPCLKA_CFGCR1 DDI mask */ +#define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2) +#define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0) +#define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \ + ADLS_DPCLKA_DDIA_SEL_MASK, \ + ADLS_DPCLKA_DDIB_SEL_MASK, \ + ADLS_DPCLKA_DDII_SEL_MASK, \ + ADLS_DPCLKA_DDIJ_SEL_MASK, \ + ADLS_DPCLKA_DDIK_SEL_MASK) + +/* ICL PLL */ +#define _DPLL0_ENABLE 0x46010 +#define _DPLL1_ENABLE 0x46014 +#define _ADLS_DPLL2_ENABLE 0x46018 +#define _ADLS_DPLL3_ENABLE 0x46030 +#define PLL_ENABLE REG_BIT(31) +#define PLL_LOCK REG_BIT(30) +#define PLL_POWER_ENABLE REG_BIT(27) +#define PLL_POWER_STATE REG_BIT(26) +#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ + _DPLL0_ENABLE, _DPLL1_ENABLE, \ + _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE)) + +#define _DG2_PLL3_ENABLE 0x4601C + +#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ + _DPLL0_ENABLE, _DPLL1_ENABLE, \ + _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE)) + +#define TBT_PLL_ENABLE _MMIO(0x46020) + +#define _MG_PLL1_ENABLE 0x46030 +#define _MG_PLL2_ENABLE 0x46034 +#define _MG_PLL3_ENABLE 0x46038 +#define _MG_PLL4_ENABLE 0x4603C +/* Bits are the same as _DPLL0_ENABLE */ +#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ + _MG_PLL2_ENABLE) + +/* DG1 PLL */ +#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _DPLL0_ENABLE, _DPLL1_ENABLE, \ + _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)) + +/* ADL-P Type C PLL */ +#define PORTTC1_PLL_ENABLE 0x46038 +#define PORTTC2_PLL_ENABLE 0x46040 +#define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \ + PORTTC1_PLL_ENABLE, \ + PORTTC2_PLL_ENABLE) + +#define _ICL_DPLL0_CFGCR0 0x164000 +#define _ICL_DPLL1_CFGCR0 0x164080 +#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ + _ICL_DPLL1_CFGCR0) +#define DPLL_CFGCR0_HDMI_MODE (1 << 30) +#define DPLL_CFGCR0_SSC_ENABLE (1 << 29) +#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) +#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) +#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) +#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) +#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) +#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) +#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) +#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) +#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) +#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) +#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) +#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) +#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) +#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) + +#define _ICL_DPLL0_CFGCR1 0x164004 +#define _ICL_DPLL1_CFGCR1 0x164084 +#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ + _ICL_DPLL1_CFGCR1) +#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) +#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) +#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) +#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) +#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) +#define DPLL_CFGCR1_KDIV_MASK (7 << 6) +#define DPLL_CFGCR1_KDIV_SHIFT (6) +#define DPLL_CFGCR1_KDIV(x) ((x) << 6) +#define DPLL_CFGCR1_KDIV_1 (1 << 6) +#define DPLL_CFGCR1_KDIV_2 (2 << 6) +#define DPLL_CFGCR1_KDIV_3 (4 << 6) +#define DPLL_CFGCR1_PDIV_MASK (0xf << 2) +#define DPLL_CFGCR1_PDIV_SHIFT (2) +#define DPLL_CFGCR1_PDIV(x) ((x) << 2) +#define DPLL_CFGCR1_PDIV_2 (1 << 2) +#define DPLL_CFGCR1_PDIV_3 (2 << 2) +#define DPLL_CFGCR1_PDIV_5 (4 << 2) +#define DPLL_CFGCR1_PDIV_7 (8 << 2) +#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) +#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) +#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0) + +#define _TGL_DPLL0_CFGCR0 0x164284 +#define _TGL_DPLL1_CFGCR0 0x16428C +#define _TGL_TBTPLL_CFGCR0 0x16429C +#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ + _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0)) +#define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ + _TGL_DPLL1_CFGCR0) + +#define _TGL_DPLL0_DIV0 0x164B00 +#define _TGL_DPLL1_DIV0 0x164C00 +#define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0) +#define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) +#define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val)) + +#define _TGL_DPLL0_CFGCR1 0x164288 +#define _TGL_DPLL1_CFGCR1 0x164290 +#define _TGL_TBTPLL_CFGCR1 0x1642A0 +#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ + _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1)) +#define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ + _TGL_DPLL1_CFGCR1) + +#define _DG1_DPLL2_CFGCR0 0x16C284 +#define _DG1_DPLL3_CFGCR0 0x16C28C +#define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ + _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0)) + +#define _DG1_DPLL2_CFGCR1 0x16C288 +#define _DG1_DPLL3_CFGCR1 0x16C290 +#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ + _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1)) + +/* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ +#define _ADLS_DPLL4_CFGCR0 0x164294 +#define _ADLS_DPLL3_CFGCR0 0x1642C0 +#define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ + _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0)) + +#define _ADLS_DPLL4_CFGCR1 0x164298 +#define _ADLS_DPLL3_CFGCR1 0x1642C4 +#define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ + _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1)) + +/* BXT display engine PLL */ +#define BXT_DE_PLL_CTL _MMIO(0x6d000) +#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ +#define BXT_DE_PLL_RATIO_MASK 0xff + +#define BXT_DE_PLL_ENABLE _MMIO(0x46070) +#define BXT_DE_PLL_PLL_ENABLE (1 << 31) +#define BXT_DE_PLL_LOCK (1 << 30) +#define BXT_DE_PLL_FREQ_REQ (1 << 23) +#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22) +#define ICL_CDCLK_PLL_RATIO(x) (x) +#define ICL_CDCLK_PLL_RATIO_MASK 0xff + +/* GEN9 DC */ +#define DC_STATE_EN _MMIO(0x45504) +#define DC_STATE_DISABLE 0 +#define DC_STATE_EN_DC3CO REG_BIT(30) +#define DC_STATE_DC3CO_STATUS REG_BIT(29) +#define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21) +#define HOLD_PHY_PG1_LATCH REG_BIT(20) +#define DC_STATE_EN_UPTO_DC5 (1 << 0) +#define DC_STATE_EN_DC9 (1 << 3) +#define DC_STATE_EN_UPTO_DC6 (2 << 0) +#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 + +#define DC_STATE_DEBUG _MMIO(0x45520) +#define DC_STATE_DEBUG_MASK_CORES (1 << 0) +#define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) + +#define D_COMP_BDW _MMIO(0x138144) + +/* Pipe WM_LINETIME - watermark line time */ +#define _WM_LINETIME_A 0x45270 +#define _WM_LINETIME_B 0x45274 +#define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B) +#define HSW_LINETIME_MASK REG_GENMASK(8, 0) +#define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x)) +#define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16) +#define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x)) + +/* SFUSE_STRAP */ +#define SFUSE_STRAP _MMIO(0xc2014) +#define SFUSE_STRAP_FUSE_LOCK (1 << 13) +#define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) +#define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) +#define SFUSE_STRAP_CRT_DISABLED (1 << 6) +#define SFUSE_STRAP_DDIF_DETECTED (1 << 3) +#define SFUSE_STRAP_DDIB_DETECTED (1 << 2) +#define SFUSE_STRAP_DDIC_DETECTED (1 << 1) +#define SFUSE_STRAP_DDID_DETECTED (1 << 0) + +/* Gen4+ Timestamp and Pipe Frame time stamp registers */ +#define GEN4_TIMESTAMP _MMIO(0x2358) +#define ILK_TIMESTAMP_HI _MMIO(0x70070) +#define IVB_TIMESTAMP_CTR _MMIO(0x44070) + +/* g4x+, except vlv/chv! */ +#define _PIPE_FRMTMSTMP_A 0x70048 +#define _PIPE_FRMTMSTMP_B 0x71048 +#define PIPE_FRMTMSTMP(pipe) \ + _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B) + +/* g4x+, except vlv/chv! */ +#define _PIPE_FLIPTMSTMP_A 0x7004C +#define _PIPE_FLIPTMSTMP_B 0x7104C +#define PIPE_FLIPTMSTMP(pipe) \ + _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B) + +/* tgl+ */ +#define _PIPE_FLIPDONETMSTMP_A 0x70054 +#define _PIPE_FLIPDONETMSTMP_B 0x71054 +#define PIPE_FLIPDONETIMSTMP(pipe) \ + _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B) + +#define _VLV_PIPE_MSA_MISC_A 0x70048 +#define VLV_PIPE_MSA_MISC(__display, pipe) \ + _MMIO_PIPE2(__display, pipe, _VLV_PIPE_MSA_MISC_A) +#define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31) +#define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */ + +#define _ICL_PHY_MISC_A 0x64C00 +#define _ICL_PHY_MISC_B 0x64C04 +#define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */ +#define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B) +#define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \ + ICL_PHY_MISC(port)) +#define ICL_PHY_MISC_MUX_DDID (1 << 28) +#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) +#define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20) + +#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0) +#define MODULAR_FIA_MASK (1 << 4) +#define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6)) +#define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5)) +#define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8) +#define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8)) +#define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8)) + +#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890) +#define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx)) + +#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894) +#define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx)) + +#define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880) +#define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4) +#define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4)) +#define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4)) + +#define _TCSS_DDI_STATUS_1 0x161500 +#define _TCSS_DDI_STATUS_2 0x161504 +#define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \ + _TCSS_DDI_STATUS_1, \ + _TCSS_DDI_STATUS_2)) +#define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25) +#define TCSS_DDI_STATUS_READY REG_BIT(2) +#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1) +#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0) + +#define CLKREQ_POLICY _MMIO(0x101038) +#define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) + +#define CLKGATE_DIS_MISC _MMIO(0x46534) +#define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21) + +#define _MTL_CLKGATE_DIS_TRANS_A 0x604E8 +#define _MTL_CLKGATE_DIS_TRANS_B 0x614E8 +#define MTL_CLKGATE_DIS_TRANS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A) +#define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7) + +#define _MTL_PIPE_CLKGATE_DIS2_A 0x60114 +#define _MTL_PIPE_CLKGATE_DIS2_B 0x61114 +#define MTL_PIPE_CLKGATE_DIS2(pipe) _MMIO_PIPE(pipe, _MTL_PIPE_CLKGATE_DIS2_A, _MTL_PIPE_CLKGATE_DIS2_B) +#define MTL_DPFC_GATING_DIS REG_BIT(6) + +#define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710 +#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8) +#define MTL_TRCD_MASK REG_GENMASK(31, 24) +#define MTL_TRP_MASK REG_GENMASK(23, 16) +#define MTL_DCLK_MASK REG_GENMASK(15, 0) + +#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4) +#define MTL_TRAS_MASK REG_GENMASK(16, 8) +#define MTL_TRDPRE_MASK REG_GENMASK(7, 0) + + + +#endif /* __INTEL_DISPLAY_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.c b/drivers/gpu/drm/i915/display/intel_display_reset.c index 1dbd3e841df3..f5f38dca14d7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reset.c +++ b/drivers/gpu/drm/i915/display/intel_display_reset.c @@ -8,6 +8,7 @@ #include "i915_drv.h" #include "intel_clock_gating.h" #include "intel_cx0_phy.h" +#include "intel_display_core.h" #include "intel_display_driver.h" #include "intel_display_reset.h" #include "intel_display_types.h" diff --git a/drivers/gpu/drm/i915/display/intel_display_rpm.c b/drivers/gpu/drm/i915/display/intel_display_rpm.c index 48da67dd0136..56c4024201c1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_rpm.c +++ b/drivers/gpu/drm/i915/display/intel_display_rpm.c @@ -2,6 +2,7 @@ /* Copyright © 2025 Intel Corporation */ #include "i915_drv.h" +#include "intel_display_core.h" #include "intel_display_rpm.h" #include "intel_runtime_pm.h" diff --git a/drivers/gpu/drm/i915/display/intel_display_rps.c b/drivers/gpu/drm/i915/display/intel_display_rps.c index 4074a1879828..82ea1ec482e4 100644 --- a/drivers/gpu/drm/i915/display/intel_display_rps.c +++ b/drivers/gpu/drm/i915/display/intel_display_rps.c @@ -8,6 +8,9 @@ #include "gt/intel_rps.h" #include "i915_drv.h" +#include "i915_reg.h" +#include "intel_display_core.h" +#include "intel_display_irq.h" #include "intel_display_rps.h" #include "intel_display_types.h" @@ -43,12 +46,13 @@ static int do_rps_boost(struct wait_queue_entry *_wait, void intel_display_rps_boost_after_vblank(struct drm_crtc *crtc, struct dma_fence *fence) { + struct intel_display *display = to_intel_display(crtc->dev); struct wait_rps_boost *wait; if (!dma_fence_is_i915(fence)) return; - if (DISPLAY_VER(to_i915(crtc->dev)) < 6) + if (DISPLAY_VER(display) < 6) return; if (drm_crtc_vblank_get(crtc)) @@ -81,3 +85,24 @@ void intel_display_rps_mark_interactive(struct intel_display *display, intel_rps_mark_interactive(&to_gt(i915)->rps, interactive); state->rps_interactive = interactive; } + +void ilk_display_rps_enable(struct intel_display *display) +{ + spin_lock(&display->irq.lock); + ilk_enable_display_irq(display, DE_PCU_EVENT); + spin_unlock(&display->irq.lock); +} + +void ilk_display_rps_disable(struct intel_display *display) +{ + spin_lock(&display->irq.lock); + ilk_disable_display_irq(display, DE_PCU_EVENT); + spin_unlock(&display->irq.lock); +} + +void ilk_display_rps_irq_handler(struct intel_display *display) +{ + struct drm_i915_private *i915 = to_i915(display->drm); + + gen5_rps_irq_handler(&to_gt(i915)->rps); +} diff --git a/drivers/gpu/drm/i915/display/intel_display_rps.h b/drivers/gpu/drm/i915/display/intel_display_rps.h index 556891edb2dd..183d154f2c7c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_rps.h +++ b/drivers/gpu/drm/i915/display/intel_display_rps.h @@ -13,10 +13,34 @@ struct drm_crtc; struct intel_atomic_state; struct intel_display; +#ifdef I915 void intel_display_rps_boost_after_vblank(struct drm_crtc *crtc, struct dma_fence *fence); void intel_display_rps_mark_interactive(struct intel_display *display, struct intel_atomic_state *state, bool interactive); +void ilk_display_rps_enable(struct intel_display *display); +void ilk_display_rps_disable(struct intel_display *display); +void ilk_display_rps_irq_handler(struct intel_display *display); +#else +static inline void intel_display_rps_boost_after_vblank(struct drm_crtc *crtc, + struct dma_fence *fence) +{ +} +static inline void intel_display_rps_mark_interactive(struct intel_display *display, + struct intel_atomic_state *state, + bool interactive) +{ +} +static inline void ilk_display_rps_enable(struct intel_display *display) +{ +} +static inline void ilk_display_rps_disable(struct intel_display *display) +{ +} +static inline void ilk_display_rps_irq_handler(struct intel_display *display) +{ +} +#endif #endif /* __INTEL_DISPLAY_RPS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_snapshot.c b/drivers/gpu/drm/i915/display/intel_display_snapshot.c index 25ba043cbb65..66087302fdbc 100644 --- a/drivers/gpu/drm/i915/display/intel_display_snapshot.c +++ b/drivers/gpu/drm/i915/display/intel_display_snapshot.c @@ -7,6 +7,7 @@ #include "intel_display_core.h" #include "intel_display_device.h" +#include "intel_display_irq.h" #include "intel_display_params.h" #include "intel_display_snapshot.h" #include "intel_dmc.h" @@ -20,6 +21,7 @@ struct intel_display_snapshot { struct intel_display_params params; struct intel_overlay_snapshot *overlay; struct intel_dmc_snapshot *dmc; + struct intel_display_irq_snapshot *irq; }; struct intel_display_snapshot *intel_display_snapshot_capture(struct intel_display *display) @@ -38,6 +40,7 @@ struct intel_display_snapshot *intel_display_snapshot_capture(struct intel_displ intel_display_params_copy(&snapshot->params); + snapshot->irq = intel_display_irq_snapshot_capture(display); snapshot->overlay = intel_overlay_snapshot_capture(display); snapshot->dmc = intel_dmc_snapshot_capture(display); @@ -57,6 +60,7 @@ void intel_display_snapshot_print(const struct intel_display_snapshot *snapshot, intel_display_device_info_print(&snapshot->info, &snapshot->runtime_info, p); intel_display_params_dump(&snapshot->params, display->drm->driver->name, p); + intel_display_irq_snapshot_print(snapshot->irq, p); intel_overlay_snapshot_print(snapshot->overlay, p); intel_dmc_snapshot_print(snapshot->dmc, p); } @@ -68,6 +72,7 @@ void intel_display_snapshot_free(struct intel_display_snapshot *snapshot) intel_display_params_free(&snapshot->params); + kfree(snapshot->irq); kfree(snapshot->overlay); kfree(snapshot->dmc); kfree(snapshot); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 94468a9d2e0d..30c7315fc25e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -37,6 +37,7 @@ #include <drm/drm_crtc.h> #include <drm/drm_encoder.h> #include <drm/drm_framebuffer.h> +#include <drm/drm_panel.h> #include <drm/drm_rect.h> #include <drm/drm_vblank_work.h> #include <drm/intel/i915_hdcp_interface.h> @@ -384,6 +385,9 @@ struct intel_vbt_panel_data { }; struct intel_panel { + /* Simple drm_panel */ + struct drm_panel *base; + /* Fixed EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ const struct drm_edid *fixed_edid; @@ -550,6 +554,10 @@ struct intel_connector { struct intel_dp *dp; } mst; + struct { + int force_bpp_x16; + } link; + /* Work struct to schedule a uevent on link train failure */ struct work_struct modeset_retry_work; @@ -591,7 +599,7 @@ struct intel_atomic_state { bool dpll_set, modeset; - struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; + struct intel_dpll_state dpll_state[I915_NUM_PLLS]; struct intel_dp_tunnel_inherited_state *inherited_dp_tunnels; @@ -1075,8 +1083,8 @@ struct intel_crtc_state { * haswell. */ struct dpll dpll; - /* Selected dpll when shared or NULL. */ - struct intel_shared_dpll *shared_dpll; + /* Selected dpll or NULL. */ + struct intel_dpll *intel_dpll; /* Actual register state of the dpll, for shared dpll cross-checking. */ struct intel_dpll_hw_state dpll_hw_state; @@ -1086,7 +1094,7 @@ struct intel_crtc_state { * setting shared_dpll and dpll_hw_state to one of these reserved ones. */ struct icl_port_dpll { - struct intel_shared_dpll *pll; + struct intel_dpll *pll; struct intel_dpll_hw_state hw_state; } icl_port_dplls[ICL_PORT_DPLL_COUNT]; @@ -1114,6 +1122,7 @@ struct intel_crtc_state { bool wm_level_disabled; u32 dc3co_exitline; u16 su_y_granularity; + u8 active_non_psr_pipes; /* * Frequency the dpll for the port should run at. Differs from the @@ -1292,7 +1301,7 @@ struct intel_crtc_state { enum transcoder mst_master_transcoder; /* For DSB based pipe updates */ - struct intel_dsb *dsb_color_vblank, *dsb_commit; + struct intel_dsb *dsb_color, *dsb_commit; bool use_dsb; u32 psr2_man_track_ctl; @@ -1387,7 +1396,7 @@ struct intel_crtc { /* armed event for DSB based updates */ struct drm_pending_vblank_event *dsb_event; - /* Access to these should be protected by dev_priv->irq_lock. */ + /* Access to these should be protected by display->irq.lock. */ bool cpu_fifo_underrun_disabled; bool pch_fifo_underrun_disabled; @@ -1439,7 +1448,7 @@ struct intel_crtc { struct intel_pipe_crc pipe_crc; #endif - bool block_dc_for_vblank; + bool vblank_psr_notify; }; struct intel_plane_error { @@ -1650,6 +1659,8 @@ struct intel_psr { u8 entry_setup_frames; bool link_ok; + + u8 active_non_psr_pipes; }; struct intel_dp { @@ -1662,7 +1673,9 @@ struct intel_dp { bool use_max_params; u8 dpcd[DP_RECEIVER_CAP_SIZE]; u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; - u8 pr_dpcd; + u8 pr_dpcd[DP_PANEL_REPLAY_CAP_SIZE]; +#define INTEL_PR_DPCD_INDEX(pr_dpcd_register) ((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT) + u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE]; @@ -1805,12 +1818,16 @@ struct intel_dp { struct { u8 io_wake_lines; u8 fast_wake_lines; + enum transcoder transcoder; + struct mutex lock; /* LNL and beyond */ u8 check_entry_lines; u8 aux_less_wake_lines; u8 silence_period_sym_clocks; u8 lfps_half_cycle_num_of_syms; + bool lobf_disable_debug; + bool sink_alpm_error; } alpm_parameters; u8 alpm_dpcd; diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c index da429c332914..f57280e9d041 100644 --- a/drivers/gpu/drm/i915/display/intel_display_wa.c +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c @@ -6,6 +6,7 @@ #include "i915_reg.h" #include "intel_de.h" #include "intel_display_core.h" +#include "intel_display_regs.h" #include "intel_display_wa.h" static void gen11_display_wa_apply(struct intel_display *display) diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.c b/drivers/gpu/drm/i915/display/intel_dkl_phy.c index dad7192132ad..35e919eae369 100644 --- a/drivers/gpu/drm/i915/display/intel_dkl_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.c @@ -25,7 +25,9 @@ dkl_phy_set_hip_idx(struct intel_display *display, struct intel_dkl_phy_reg reg) { enum tc_port tc_port = DKL_REG_TC_PORT(reg); - drm_WARN_ON(display->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS); + if (drm_WARN_ON(display->drm, + tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS)) + return; intel_de_write(display, HIP_INDEX_REG(tc_port), diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h index 56085b32956d..3d8fa667cc73 100644 --- a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h @@ -8,6 +8,8 @@ #include <linux/types.h> +#include "intel_display_reg_defs.h" + struct intel_dkl_phy_reg { u32 reg:24; u32 bank_idx:4; diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 98f80a6c63e8..a10e56e7cf31 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -27,9 +27,12 @@ #include "i915_drv.h" #include "i915_reg.h" +#include "intel_crtc.h" #include "intel_de.h" -#include "intel_display_rpm.h" #include "intel_display_power_well.h" +#include "intel_display_regs.h" +#include "intel_display_rpm.h" +#include "intel_display_types.h" #include "intel_dmc.h" #include "intel_dmc_regs.h" #include "intel_step.h" @@ -173,7 +176,6 @@ MODULE_FIRMWARE(BXT_DMC_PATH); static const char *dmc_firmware_default(struct intel_display *display, u32 *size) { - struct drm_i915_private *i915 = to_i915(display->drm); const char *fw_path = NULL; u32 max_fw_size = 0; @@ -189,39 +191,39 @@ static const char *dmc_firmware_default(struct intel_display *display, u32 *size } else if (DISPLAY_VERx100(display) == 1400) { fw_path = MTL_DMC_PATH; max_fw_size = XELPDP_DMC_MAX_FW_SIZE; - } else if (IS_DG2(i915)) { + } else if (display->platform.dg2) { fw_path = DG2_DMC_PATH; max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; - } else if (IS_ALDERLAKE_P(i915)) { + } else if (display->platform.alderlake_p) { fw_path = ADLP_DMC_PATH; max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; - } else if (IS_ALDERLAKE_S(i915)) { + } else if (display->platform.alderlake_s) { fw_path = ADLS_DMC_PATH; max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; - } else if (IS_DG1(i915)) { + } else if (display->platform.dg1) { fw_path = DG1_DMC_PATH; max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; - } else if (IS_ROCKETLAKE(i915)) { + } else if (display->platform.rocketlake) { fw_path = RKL_DMC_PATH; max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; - } else if (IS_TIGERLAKE(i915)) { + } else if (display->platform.tigerlake) { fw_path = TGL_DMC_PATH; max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; } else if (DISPLAY_VER(display) == 11) { fw_path = ICL_DMC_PATH; max_fw_size = ICL_DMC_MAX_FW_SIZE; - } else if (IS_GEMINILAKE(i915)) { + } else if (display->platform.geminilake) { fw_path = GLK_DMC_PATH; max_fw_size = GLK_DMC_MAX_FW_SIZE; - } else if (IS_KABYLAKE(i915) || - IS_COFFEELAKE(i915) || - IS_COMETLAKE(i915)) { + } else if (display->platform.kabylake || + display->platform.coffeelake || + display->platform.cometlake) { fw_path = KBL_DMC_PATH; max_fw_size = KBL_DMC_MAX_FW_SIZE; - } else if (IS_SKYLAKE(i915)) { + } else if (display->platform.skylake) { fw_path = SKL_DMC_PATH; max_fw_size = SKL_DMC_MAX_FW_SIZE; - } else if (IS_BROXTON(i915)) { + } else if (display->platform.broxton) { fw_path = BXT_DMC_PATH; max_fw_size = BXT_DMC_MAX_FW_SIZE; } @@ -426,7 +428,7 @@ static void disable_event_handler(struct intel_display *display, REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, DMC_EVT_CTL_TYPE_EDGE_0_1) | REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, - DMC_EVT_CTL_EVENT_ID_FALSE)); + DMC_EVENT_FALSE)); intel_de_write(display, htp_reg, 0); } @@ -491,6 +493,17 @@ static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable) adlp_pipedmc_clock_gating_wa(display, enable); } +static u32 pipedmc_interrupt_mask(struct intel_display *display) +{ + /* + * FIXME PIPEDMC_ERROR not enabled for now due to LNL pipe B + * triggering it during the first DC state transition. Figure + * out what is going on... + */ + return PIPEDMC_GTT_FAULT | + PIPEDMC_ATS_FAULT; +} + void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe) { enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); @@ -498,6 +511,11 @@ void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe) if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) return; + if (DISPLAY_VER(display) >= 20) { + intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); + intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display)); + } + if (DISPLAY_VER(display) >= 14) intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); else @@ -515,6 +533,19 @@ void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe) intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); else intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); + + if (DISPLAY_VER(display) >= 20) { + intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0); + intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); + } +} + +static u32 dmc_evt_ctl_disable(void) +{ + return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, + DMC_EVT_CTL_TYPE_EDGE_0_1) | + REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, + DMC_EVENT_FALSE); } static bool is_dmc_evt_ctl_reg(struct intel_display *display, @@ -537,12 +568,79 @@ static bool is_dmc_evt_htp_reg(struct intel_display *display, return offset >= start && offset < end; } +static bool is_event_handler(struct intel_display *display, + enum intel_dmc_id dmc_id, + unsigned int event_id, + i915_reg_t reg, u32 data) +{ + return is_dmc_evt_ctl_reg(display, dmc_id, reg) && + REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == event_id; +} + +static void dmc_configure_event(struct intel_display *display, + enum intel_dmc_id dmc_id, + unsigned int event_id, + bool enable) +{ + struct intel_dmc *dmc = display_to_dmc(display); + int num_handlers = 0; + int i; + + for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { + i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; + u32 data = dmc->dmc_info[dmc_id].mmiodata[i]; + + if (!is_event_handler(display, dmc_id, event_id, reg, data)) + continue; + + intel_de_write(display, reg, enable ? data : dmc_evt_ctl_disable()); + num_handlers++; + } + + drm_WARN_ONCE(display->drm, num_handlers != 1, + "DMC %d has %d handlers for event 0x%x\n", + dmc_id, num_handlers, event_id); +} + +/** + * intel_dmc_block_pkgc() - block PKG C-state + * @display: display instance + * @pipe: pipe which register use to block + * @block: block/unblock + * + * This interface is target for Wa_16025596647 usage. I.e. to set/clear + * PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS bit in PIPEDMC_BLOCK_PKGC_SW register. + */ +void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, + bool block) +{ + intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(pipe), + PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS, block ? + PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS : 0); +} + +/** + * intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank() - start of PKG + * C-state exit + * @display: display instance + * @pipe: pipe which register use to block + * @enable: enable/disable + * + * This interface is target for Wa_16025596647 usage. I.e. start the package C + * exit at the start of the undelayed vblank + */ +void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display, + enum pipe pipe, bool enable) +{ + enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); + + dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_VBLANK, enable); +} + static bool disable_dmc_evt(struct intel_display *display, enum intel_dmc_id dmc_id, i915_reg_t reg, u32 data) { - struct drm_i915_private *i915 = to_i915(display->drm); - if (!is_dmc_evt_ctl_reg(display, dmc_id, reg)) return false; @@ -551,13 +649,13 @@ static bool disable_dmc_evt(struct intel_display *display, return true; /* also disable the flip queue event on the main DMC on TGL */ - if (IS_TIGERLAKE(i915) && - REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_CLK_MSEC) + if (display->platform.tigerlake && + is_event_handler(display, dmc_id, MAINDMC_EVENT_CLK_MSEC, reg, data)) return true; /* also disable the HRR event on the main DMC on TGL/ADLS */ - if ((IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915)) && - REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_VBLANK_A) + if ((display->platform.tigerlake || display->platform.alderlake_s) && + is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg, data)) return true; return false; @@ -570,10 +668,7 @@ static u32 dmc_mmiodata(struct intel_display *display, if (disable_dmc_evt(display, dmc_id, dmc->dmc_info[dmc_id].mmioaddr[i], dmc->dmc_info[dmc_id].mmiodata[i])) - return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, - DMC_EVT_CTL_TYPE_EDGE_0_1) | - REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, - DMC_EVT_CTL_EVENT_ID_FALSE); + return dmc_evt_ctl_disable(); else return dmc->dmc_info[dmc_id].mmiodata[i]; } @@ -588,7 +683,6 @@ static u32 dmc_mmiodata(struct intel_display *display, */ void intel_dmc_load_program(struct intel_display *display) { - struct drm_i915_private *i915 __maybe_unused = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; struct intel_dmc *dmc = display_to_dmc(display); enum intel_dmc_id dmc_id; @@ -1012,9 +1106,7 @@ static void intel_dmc_runtime_pm_put(struct intel_display *display) static const char *dmc_fallback_path(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - - if (IS_ALDERLAKE_P(i915)) + if (display->platform.alderlake_p) return ADLP_DMC_FALLBACK_PATH; return NULL; @@ -1279,7 +1371,6 @@ static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 * static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) { struct intel_display *display = m->private; - struct drm_i915_private *i915 = to_i915(display->drm); struct intel_dmc *dmc = display_to_dmc(display); struct ref_tracker *wakeref; i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; @@ -1299,7 +1390,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) seq_printf(m, "Pipe A fw loaded: %s\n", str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA))); seq_printf(m, "Pipe B fw needed: %s\n", - str_yes_no(IS_ALDERLAKE_P(i915) || + str_yes_no(display->platform.alderlake_p || DISPLAY_VER(display) >= 14)); seq_printf(m, "Pipe B fw loaded: %s\n", str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB))); @@ -1313,7 +1404,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) if (DISPLAY_VER(display) >= 12) { i915_reg_t dc3co_reg; - if (IS_DGFX(i915) || DISPLAY_VER(display) >= 14) { + if (display->platform.dgfx || DISPLAY_VER(display) >= 14) { dc3co_reg = DG1_DMC_DEBUG3; dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; } else { @@ -1325,9 +1416,9 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) seq_printf(m, "DC3CO count: %d\n", intel_de_read(display, dc3co_reg)); } else { - dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT : + dc5_reg = display->platform.broxton ? BXT_DMC_DC3_DC5_COUNT : SKL_DMC_DC3_DC5_COUNT; - if (!IS_GEMINILAKE(i915) && !IS_BROXTON(i915)) + if (!display->platform.geminilake && !display->platform.broxton) dc6_reg = SKL_DMC_DC5_DC6_COUNT; } @@ -1362,3 +1453,29 @@ void intel_dmc_debugfs_register(struct intel_display *display) debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root, display, &intel_dmc_debugfs_status_fops); } + +void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe) +{ + struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); + u32 tmp; + + if (DISPLAY_VER(display) >= 20) { + tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe)); + intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp); + + if (tmp & PIPEDMC_ATS_FAULT) + drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC ATS fault\n", + crtc->base.base.id, crtc->base.name); + if (tmp & PIPEDMC_GTT_FAULT) + drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC GTT fault\n", + crtc->base.base.id, crtc->base.name); + if (tmp & PIPEDMC_ERROR) + drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC error\n", + crtc->base.base.id, crtc->base.name); + } + + tmp = intel_de_read(display, PIPEDMC_STATUS(pipe)) & PIPEDMC_INT_VECTOR_MASK; + if (tmp) + drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC interrupt vector 0x%x\n", + crtc->base.base.id, crtc->base.name, tmp); +} diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h index c78426eb4cd5..a98e8deff13a 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.h +++ b/drivers/gpu/drm/i915/display/intel_dmc.h @@ -18,6 +18,10 @@ void intel_dmc_load_program(struct intel_display *display); void intel_dmc_disable_program(struct intel_display *display); void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe); void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe); +void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, + bool block); +void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display, + enum pipe pipe, bool enable); void intel_dmc_fini(struct intel_display *display); void intel_dmc_suspend(struct intel_display *display); void intel_dmc_resume(struct intel_display *display); @@ -30,4 +34,6 @@ void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool star void assert_dmc_loaded(struct intel_display *display); +void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe); + #endif /* __INTEL_DMC_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h index 1bf446f96a10..6f406315dd65 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h @@ -6,7 +6,273 @@ #ifndef __INTEL_DMC_REGS_H__ #define __INTEL_DMC_REGS_H__ -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" + +enum dmc_event_id { + DMC_EVENT_TRUE = 0x0, + DMC_EVENT_FALSE = 0x1, +}; + +enum maindmc_event_id { + MAINDMC_EVENT_CMP_ZERO = 0x8, + MAINDMC_EVENT_CMP_ODD = 0x9, + MAINDMC_EVENT_CMP_NEG = 0xa, + MAINDMC_EVENT_CMP_CARRY = 0xb, + + MAINDMC_EVENT_TMR0_DONE = 0x14, + MAINDMC_EVENT_TMR1_DONE = 0x15, + MAINDMC_EVENT_TMR2_DONE = 0x16, + MAINDMC_EVENT_COUNT0_DONE = 0x17, + MAINDMC_EVENT_COUNT1_DONE = 0x18, + MAINDMC_EVENT_PERF_CNTR_DARBF = 0x19, + + MAINDMC_EVENT_SCANLINE_INRANGE_FQ_A_TRIGGER = 0x22, + MAINDMC_EVENT_SCANLINE_INRANGE_FQ_B_TRIGGER = 0x23, + MAINDMC_EVENT_SCANLINE_INRANGE_FQ_C_TRIGGER = 0x24, + MAINDMC_EVENT_SCANLINE_INRANGE_FQ_D_TRIGGER = 0x25, + MAINDMC_EVENT_1KHZ_FQ_A_TRIGGER = 0x26, + MAINDMC_EVENT_1KHZ_FQ_B_TRIGGER = 0x27, + MAINDMC_EVENT_1KHZ_FQ_C_TRIGGER = 0x28, + MAINDMC_EVENT_1KHZ_FQ_D_TRIGGER = 0x29, + MAINDMC_EVENT_SCANLINE_COMP_A = 0x2a, + MAINDMC_EVENT_SCANLINE_COMP_B = 0x2b, + MAINDMC_EVENT_SCANLINE_COMP_C = 0x2c, + MAINDMC_EVENT_SCANLINE_COMP_D = 0x2d, + MAINDMC_EVENT_VBLANK_DELAYED_A = 0x2e, + MAINDMC_EVENT_VBLANK_DELAYED_B = 0x2f, + MAINDMC_EVENT_VBLANK_DELAYED_C = 0x30, + MAINDMC_EVENT_VBLANK_DELAYED_D = 0x31, + MAINDMC_EVENT_VBLANK_A = 0x32, + MAINDMC_EVENT_VBLANK_B = 0x33, + MAINDMC_EVENT_VBLANK_C = 0x34, + MAINDMC_EVENT_VBLANK_D = 0x35, + MAINDMC_EVENT_HBLANK_A = 0x36, + MAINDMC_EVENT_HBLANK_B = 0x37, + MAINDMC_EVENT_HBLANK_C = 0x38, + MAINDMC_EVENT_HBLANK_D = 0x39, + MAINDMC_EVENT_VSYNC_A = 0x3a, + MAINDMC_EVENT_VSYNC_B = 0x3b, + MAINDMC_EVENT_VSYNC_C = 0x3c, + MAINDMC_EVENT_VSYNC_D = 0x3d, + MAINDMC_EVENT_SCANLINE_A = 0x3e, + MAINDMC_EVENT_SCANLINE_B = 0x3f, + MAINDMC_EVENT_SCANLINE_C = 0x40, + MAINDMC_EVENT_SCANLINE_D = 0x41, + + MAINDMC_EVENT_PLANE1_FLIP_A = 0x42, + MAINDMC_EVENT_PLANE2_FLIP_A = 0x43, + MAINDMC_EVENT_PLANE3_FLIP_A = 0x44, + MAINDMC_EVENT_PLANE4_FLIP_A = 0x45, + MAINDMC_EVENT_PLANE5_FLIP_A = 0x46, + MAINDMC_EVENT_PLANE6_FLIP_A = 0x47, + MAINDMC_EVENT_PLANE7_FLIP_A = 0x48, + MAINDMC_EVENT_PLANE1_FLIP_B = 0x49, + MAINDMC_EVENT_PLANE2_FLIP_B = 0x4a, + MAINDMC_EVENT_PLANE3_FLIP_B = 0x4b, + MAINDMC_EVENT_PLANE4_FLIP_B = 0x4c, + MAINDMC_EVENT_PLANE5_FLIP_B = 0x4d, + MAINDMC_EVENT_PLANE6_FLIP_B = 0x4e, + MAINDMC_EVENT_PLANE7_FLIP_B = 0x4f, + MAINDMC_EVENT_PLANE1_FLIP_C = 0x50, + MAINDMC_EVENT_PLANE2_FLIP_C = 0x51, + MAINDMC_EVENT_PLANE3_FLIP_C = 0x52, + MAINDMC_EVENT_PLANE4_FLIP_C = 0x53, + MAINDMC_EVENT_PLANE5_FLIP_C = 0x54, + MAINDMC_EVENT_PLANE6_FLIP_C = 0x55, + MAINDMC_EVENT_PLANE7_FLIP_C = 0x56, + MAINDMC_EVENT_PLANE1_FLIP_D = 0x57, + MAINDMC_EVENT_PLANE2_FLIP_D = 0x58, + MAINDMC_EVENT_PLANE3_FLIP_D = 0x59, + MAINDMC_EVENT_PLANE4_FLIP_D = 0x5a, + MAINDMC_EVENT_PLANE5_FLIP_D = 0x5b, + MAINDMC_EVENT_PLANE6_FLIP_D = 0x5c, + MAINDMC_EVENT_PLANE7_FLIP_D = 0x5d, + MAINDMC_EVENT_PLANE1_FLIP_DONE_A = 0x5e, + MAINDMC_EVENT_PLANE2_FLIP_DONE_A = 0x5f, + MAINDMC_EVENT_PLANE3_FLIP_DONE_A = 0x60, + MAINDMC_EVENT_PLANE4_FLIP_DONE_A = 0x61, + MAINDMC_EVENT_PLANE5_FLIP_DONE_A = 0x62, + MAINDMC_EVENT_PLANE6_FLIP_DONE_A = 0x63, + MAINDMC_EVENT_PLANE7_FLIP_DONE_A = 0x64, + MAINDMC_EVENT_PLANE1_FLIP_DONE_B = 0x65, + MAINDMC_EVENT_PLANE2_FLIP_DONE_B = 0x66, + MAINDMC_EVENT_PLANE3_FLIP_DONE_B = 0x67, + MAINDMC_EVENT_PLANE4_FLIP_DONE_B = 0x68, + MAINDMC_EVENT_PLANE5_FLIP_DONE_B = 0x69, + MAINDMC_EVENT_PLANE6_FLIP_DONE_B = 0x6a, + MAINDMC_EVENT_PLANE7_FLIP_DONE_B = 0x6b, + MAINDMC_EVENT_PLANE1_FLIP_DONE_C = 0x6c, + MAINDMC_EVENT_PLANE2_FLIP_DONE_C = 0x6d, + MAINDMC_EVENT_PLANE3_FLIP_DONE_C = 0x6e, + MAINDMC_EVENT_PLANE4_FLIP_DONE_C = 0x6f, + MAINDMC_EVENT_PLANE5_FLIP_DONE_C = 0x70, + MAINDMC_EVENT_PLANE6_FLIP_DONE_C = 0x71, + MAINDMC_EVENT_PLANE7_FLIP_DONE_C = 0x72, + MAINDMC_EVENT_PLANE1_FLIP_DONE_D = 0x73, + MAINDMC_EVENT_PLANE2_FLIP_DONE_D = 0x74, + MAINDMC_EVENT_PLANE3_FLIP_DONE_D = 0x75, + MAINDMC_EVENT_PLANE4_FLIP_DONE_D = 0x76, + MAINDMC_EVENT_PLANE5_FLIP_DONE_D = 0x77, + MAINDMC_EVENT_PLANE6_FLIP_DONE_D = 0x78, + MAINDMC_EVENT_PLANE7_FLIP_DONE_D = 0x79, + + MAINDMC_EVENT_WIDI_GTT_FAULT_SL1 = 0x7d, + MAINDMC_EVENT_WIDI_GTT_FAULT_SL2 = 0x7e, + MAINDMC_EVENT_WIDI_CAP_ACTIVE_SL1 = 0x7f, + MAINDMC_EVENT_WIDI_CAP_ACTIVE_SL2 = 0x80, + + MAINDMC_EVENT_RENUKE_A = 0x85, + MAINDMC_EVENT_RENUKE_B = 0x86, + MAINDMC_EVENT_RENUKE_C = 0x87, + MAINDMC_EVENT_RENUKE_D = 0x88, + MAINDMC_EVENT_DPFC_FIFO_FULL_A = 0x89, + MAINDMC_EVENT_DPFC_FIFO_FULL_B = 0x8a, + MAINDMC_EVENT_DPFC_FIFO_FULL_C = 0x8b, + MAINDMC_EVENT_DPFC_FIFO_FULL_D = 0x8c, + MAINDMC_EVENT_DPFC_PIXEL_CNT_MISMATCH_A = 0x8d, + MAINDMC_EVENT_DPFC_PIXEL_CNT_MISMATCH_B = 0x8e, + MAINDMC_EVENT_DPFC_PIXEL_CNT_MISMATCH_C = 0x8f, + MAINDMC_EVENT_DPFC_PIXEL_CNT_MISMATCH_D = 0x90, + MAINDMC_EVENT_DPFC_COMPTAG_UNDERRUN_A = 0x91, + MAINDMC_EVENT_DPFC_COMPTAG_UNDERRUN_B = 0x92, + MAINDMC_EVENT_DPFC_COMPTAG_UNDERRUN_C = 0x93, + MAINDMC_EVENT_DPFC_COMPTAG_UNDERRUN_D = 0x94, + MAINDMC_EVENT_DPFC_FIFO_NOT_EMPTY_A = 0x95, + MAINDMC_EVENT_DPFC_FIFO_NOT_EMPTY_B = 0x96, + MAINDMC_EVENT_DPFC_FIFO_NOT_EMPTY_C = 0x97, + MAINDMC_EVENT_DPFC_FIFO_NOT_EMPTY_D = 0x98, + MAINDMC_EVENT_DPFC_COMPTAG_MISMATCH_A = 0x99, + MAINDMC_EVENT_DPFC_COMPTAG_MISMATCH_B = 0x9a, + MAINDMC_EVENT_DPFC_COMPTAG_MISMATCH_C = 0x9b, + MAINDMC_EVENT_DPFC_COMPTAG_MISMATCH_D = 0x9c, + MAINDMC_EVENT_DISP_PCH_INT = 0x9d, + MAINDMC_EVENT_GTT_ERR = 0x9e, + MAINDMC_EVENT_VTD_ERR = 0x9f, + MAINDMC_EVENT_FULL_FQ_WAKE_TRIGGER_A = 0xa0, + MAINDMC_EVENT_FULL_FQ_WAKE_TRIGGER_B = 0xa1, + MAINDMC_EVENT_FULL_FQ_WAKE_TRIGGER_C = 0xa2, + MAINDMC_EVENT_FULL_FQ_WAKE_TRIGGER_D = 0xa3, + MAINDMC_EVENT_PIPEDMC_CHICKEN_FW_EVENT_A = 0xa4, + MAINDMC_EVENT_PIPEDMC_CHICKEN_FW_EVENT_B = 0xa5, + MAINDMC_EVENT_PIPEDMC_CHICKEN_FW_EVENT_C = 0xa6, + MAINDMC_EVENT_PIPEDMC_CHICKEN_FW_EVENT_D = 0xa7, + + MAINDMC_EVENT_DC_CLOCK_OFF_START_EDP = 0xb2, + MAINDMC_EVENT_DC_CLOCK_OFF_START_DSI = 0xb3, + MAINDMC_EVENT_DCPR_DMC_CSR_START = 0xb4, + MAINDMC_EVENT_IN_PSR = 0xb5, + + MAINDMC_EVENT_IN_MEMUP = 0xb7, + MAINDMC_EVENT_IN_VGA = 0xb8, + + MAINDMC_EVENT_IN_KVM_SESSION = 0xba, + MAINDMC_EVENT_DEWAKE = 0xbb, + + MAINDMC_EVENT_TRAP_HIT = 0xbd, + MAINDMC_EVENT_CLK_USEC = 0xbe, + MAINDMC_EVENT_CLK_MSEC = 0xbf, + + MAINDMC_EVENT_CHICKEN1 = 0xc8, + MAINDMC_EVENT_CHICKEN2 = 0xc9, + MAINDMC_EVENT_CHICKEN3 = 0xca, + MAINDMC_EVENT_DDT_UBP = 0xcb, + + MAINDMC_EVENT_HP_LATENCY = 0xcd, + MAINDMC_EVENT_LP_LATENCY = 0xce, + MAINDMC_EVENT_WIDI_LP_REQ_SL1 = 0xcf, + MAINDMC_EVENT_WIDI_LP_REQ_SL2 = 0xd0, + + MAINDMC_EVENT_DG_DMC_EVT_0 = 0xd3, + MAINDMC_EVENT_DG_DMC_EVT_1 = 0xd4, + MAINDMC_EVENT_DG_DMC_EVT_2 = 0xd5, + MAINDMC_EVENT_DG_DMC_EVT_3 = 0xd6, + MAINDMC_EVENT_DG_DMC_EVT_4 = 0xd7, + MAINDMC_EVENT_DACFE_CLK_STOP = 0xd8, + MAINDMC_EVENT_DACFE_AZILIA_SDI_WAKE = 0xd9, + MAINDMC_EVENT_AUDIO_DOUBLE_FUNC_GRP_RST = 0xda, + MAINDMC_EVENT_AUDIO_CMD_VALID = 0xdb, + MAINDMC_EVENT_AUDIO_FRM_SYNC_BCLK = 0xdc, + MAINDMC_EVENT_AUDIO_FRM_SYNC_CDCLK = 0xdd, + MAINDMC_EVENT_AUDIO_PRESENCE_DETECT_A = 0xde, + MAINDMC_EVENT_AUDIO_PRESENCE_DETECT_B = 0xdf, + MAINDMC_EVENT_AUDIO_PRESENCE_DETECT_C = 0xe0, + MAINDMC_EVENT_AUDIO_PRESENCE_DETECT_E = 0xe1, + MAINDMC_EVENT_CMTG_SCANLINE_IN_GB_DC6v = 0xe2, + MAINDMC_EVENT_DCPR_CMTG_SCANLINE_OUTSIDE_GB = 0xe3, + MAINDMC_EVENT_DC6v_BACKWARD_COMPAT = 0xe4, + MAINDMC_EVENT_DPMA_PM_ABORT = 0xe5, + + MAINDMC_EVENT_STACK_OVF = 0xfc, + MAINDMC_EVENT_NO_CLAIM = 0xfd, + MAINDMC_EVENT_UNK_CMD = 0xfe, + MAINDMC_EVENT_HTP_MOD = 0xff, +}; + +enum pipedmc_event_id { + PIPEDMC_EVENT_TMR0_DONE = 0x14, + PIPEDMC_EVENT_TMR1_DONE = 0x15, + PIPEDMC_EVENT_TMR2_DONE = 0x16, + PIPEDMC_EVENT_COUNT0_DONE = 0x17, + PIPEDMC_EVENT_COUNT1_DONE = 0x18, + PIPEDMC_EVENT_PGA_PGB_RESTORE_DONE = 0x19, + PIPEDMC_EVENT_PG1_PG2_RESTORE_DONE = 0x1a, + PIPEDMC_EVENT_PGA_PGB_SAVE_DONE = 0x1b, + PIPEDMC_EVENT_PG1_PG2_SAVE_DONE = 0x1c, + + PIPEDMC_EVENT_FULL_FQ_WAKE_TRIGGER = 0x2b, + PIPEDMC_EVENT_1KHZ_FQ_TRIGGER = 0x2c, + PIPEDMC_EVENT_SCANLINE_INRANGE_FQ_TRIGGER = 0x2d, + PIPEDMC_EVENT_SCANLINE_INRANGE = 0x2e, + PIPEDMC_EVENT_SCANLINE_OUTRANGE = 0x2f, + PIPEDMC_EVENT_SCANLINE_EQUAL = 0x30, + PIPEDMC_EVENT_DELAYED_VBLANK = 0x31, + PIPEDMC_EVENT_VBLANK = 0x32, + PIPEDMC_EVENT_HBLANK = 0x33, + PIPEDMC_EVENT_VSYNC = 0x34, + PIPEDMC_EVENT_SCANLINE_FROM_DMUX = 0x35, + PIPEDMC_EVENT_PLANE1_FLIP = 0x36, + PIPEDMC_EVENT_PLANE2_FLIP = 0x37, + PIPEDMC_EVENT_PLANE3_FLIP = 0x38, + PIPEDMC_EVENT_PLANE4_FLIP = 0x39, + PIPEDMC_EVENT_PLANE5_FLIP = 0x3a, + PIPEDMC_EVENT_PLANE6_FLIP = 0x3b, + PIPEDMC_EVENT_PLANE7_FLIP = 0x3c, + PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER = 0x3d, + + PIPEDMC_EVENT_PLANE1_FLIP_DONE = 0x56, + PIPEDMC_EVENT_PLANE2_FLIP_DONE = 0x57, + PIPEDMC_EVENT_PLANE3_FLIP_DONE = 0x58, + PIPEDMC_EVENT_PLANE4_FLIP_DONE = 0x59, + PIPEDMC_EVENT_PLANE5_FLIP_DONE = 0x5a, + PIPEDMC_EVENT_PLANE6_FLIP_DONE = 0x5b, + PIPEDMC_EVENT_PLANE7_FLIP_DONE = 0x5c, + + PIPEDMC_EVENT_GTT_ERR = 0x9b, + + PIPEDMC_EVENT_IN_PSR = 0xb5, + PIPEDMC_EVENT_DSI_DMC_IDLE = 0xb6, + PIPEDMC_EVENT_PSR2_DMC_IDLE = 0xb7, + PIPEDMC_EVENT_IN_VGA = 0xb8, + + PIPEDMC_EVENT_TRAP_HIT = 0xbd, + PIPEDMC_EVENT_CLK_USEC = 0xbe, + PIPEDMC_EVENT_CLK_MSEC = 0xbf, + + PIPEDMC_EVENT_CHICKEN1 = 0xc8, + PIPEDMC_EVENT_CHICKEN2 = 0xc9, + PIPEDMC_EVENT_CHICKEN3 = 0xca, + PIPEDMC_EVENT_DDT_UBP = 0xcb, + + PIPEDMC_EVENT_LP_LATENCY = 0xce, + + PIPEDMC_EVENT_LACE_PART_A_HIST_TRIGGER = 0xdf, + PIPEDMC_EVENT_LACE_PART_B_HIST_TRIGGER = 0xe0, + + PIPEDMC_EVENT_STACK_OVF = 0xfc, + PIPEDMC_EVENT_NO_CLAIM = 0xfd, + PIPEDMC_EVENT_UNK_CMD = 0xfe, + PIPEDMC_EVENT_HTP_MOD = 0xff, +}; #define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4) #define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0 @@ -21,6 +287,36 @@ #define MTL_PIPEDMC_CONTROL _MMIO(0x45250) #define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4) +#define _PIPEDMC_STATUS_A 0x5f06c +#define _PIPEDMC_STATUS_B 0x5f46c +#define PIPEDMC_STATUS(pipe) _MMIO_PIPE((pipe), _PIPEDMC_STATUS_A, _PIPEDMC_STATUS_B) +#define PIPEDMC_SSP REG_GENMASK(31, 16) +#define PIPEDMC_INT_VECTOR_MASK REG_GENMASK(15, 8) +/* PIPEDMC_INT_VECTOR values defined by firmware */ +#define PIPEDMC_INT_VECTOR_SCANLINE_COMP_ERROR REG_FIELD_PREP(PIPEDMC_INT_VECTOR_MASK, 0x1) +#define PIPEDMC_INT_VECTOR_DC6V_FLIPQ_OVERLAP_ERROR REG_FIELD_PREP(PIPEDMC_INT_VECTOR_MASK, 0x2) +#define PIPEDMC_INT_VECTOR_FLIPQ_PROG_DONE REG_FIELD_PREP(PIPEDMC_INT_VECTOR_MASK, 0xff) /* Wa_16018781658:lnl[a0] */ +#define PIPEDMC_EVT_PENDING REG_GENMASK(7, 0) + +#define _PIPEDMC_INTERRUPT_A 0x5f190 /* lnl+ */ +#define _PIPEDMC_INTERRUPT_B 0x5f590 /* lnl+ */ +#define PIPEDMC_INTERRUPT(pipe) _MMIO_PIPE((pipe), _PIPEDMC_INTERRUPT_A, _PIPEDMC_INTERRUPT_B) +#define _PIPEDMC_INTERRUPT_MASK_A 0x5f194 /* lnl+ */ +#define _PIPEDMC_INTERRUPT_MASK_B 0x5f594 /* lnl+ */ +#define PIPEDMC_INTERRUPT_MASK(pipe) _MMIO_PIPE((pipe), _PIPEDMC_INTERRUPT_MASK_A, _PIPEDMC_INTERRUPT_MASK_B) +#define PIPEDMC_FLIPQ_PROG_DONE REG_BIT(3) +#define PIPEDMC_ERROR REG_BIT(2) +#define PIPEDMC_GTT_FAULT REG_BIT(1) +#define PIPEDMC_ATS_FAULT REG_BIT(0) + +#define PIPEDMC_BLOCK_PKGC_SW_A 0x5f1d0 +#define PIPEDMC_BLOCK_PKGC_SW_B 0x5F5d0 +#define PIPEDMC_BLOCK_PKGC_SW(pipe) _MMIO_PIPE(pipe, \ + PIPEDMC_BLOCK_PKGC_SW_A, \ + PIPEDMC_BLOCK_PKGC_SW_B) +#define PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS BIT(31) +#define PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_UNTIL_NEXT_FRAMESTART BIT(15) + #define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000 #define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000 @@ -57,12 +353,7 @@ #define DMC_EVT_CTL_TYPE_LEVEL_1 1 #define DMC_EVT_CTL_TYPE_EDGE_1_0 2 #define DMC_EVT_CTL_TYPE_EDGE_0_1 3 - #define DMC_EVT_CTL_EVENT_ID_MASK REG_GENMASK(15, 8) -#define DMC_EVT_CTL_EVENT_ID_FALSE 0x01 -#define DMC_EVT_CTL_EVENT_ID_VBLANK_A 0x32 /* main DMC */ -/* An event handler scheduled to run at a 1 kHz frequency. */ -#define DMC_EVT_CTL_EVENT_ID_CLK_MSEC 0xbf #define DMC_HTP_ADDR_SKL 0x00500034 #define DMC_SSP_BASE _MMIO(0x8F074) diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c index 7e2ce0c2f6c3..44b3ee5c9be4 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c @@ -8,8 +8,8 @@ #include <drm/drm_print.h> #include "i915_drv.h" -#include "i915_reg.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_dmc_regs.h" #include "intel_dmc_wl.h" diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index aeb14a5455fd..277b40b13948 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -27,6 +27,8 @@ #include <linux/export.h> #include <linux/i2c.h> +#include <linux/log2.h> +#include <linux/math.h> #include <linux/notifier.h> #include <linux/seq_buf.h> #include <linux/slab.h> @@ -34,7 +36,6 @@ #include <linux/string_helpers.h> #include <linux/timekeeping.h> #include <linux/types.h> - #include <asm/byteorder.h> #include <drm/display/drm_dp_helper.h> @@ -45,12 +46,11 @@ #include <drm/drm_crtc.h> #include <drm/drm_edid.h> #include <drm/drm_fixed.h> +#include <drm/drm_print.h> #include <drm/drm_probe_helper.h> #include "g4x_dp.h" -#include "i915_drv.h" -#include "i915_irq.h" -#include "i915_reg.h" +#include "i915_utils.h" #include "intel_alpm.h" #include "intel_atomic.h" #include "intel_audio.h" @@ -58,10 +58,12 @@ #include "intel_combo_phy_regs.h" #include "intel_connector.h" #include "intel_crtc.h" +#include "intel_crtc_state_dump.h" #include "intel_cx0_phy.h" #include "intel_ddi.h" #include "intel_de.h" #include "intel_display_driver.h" +#include "intel_display_regs.h" #include "intel_display_rpm.h" #include "intel_display_types.h" #include "intel_dp.h" @@ -92,7 +94,6 @@ #include "intel_tc.h" #include "intel_vdsc.h" #include "intel_vrr.h" -#include "intel_crtc_state_dump.h" /* DP DSC throughput values used for slice count calculations KPixels/s */ #define DP_DSC_PEAK_PIXEL_RATE 2720000 @@ -846,7 +847,7 @@ small_joiner_ram_size_bits(struct intel_display *display) return 6144 * 8; } -u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp) +static u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp) { u32 bits_per_pixel = bpp; int i; @@ -938,6 +939,7 @@ static u32 ultrajoiner_ram_max_bpp(u32 mode_hdisplay) return ultrajoiner_ram_bits() / mode_hdisplay; } +/* TODO: return a bpp_x16 value */ static u32 get_max_compressed_bpp_with_joiner(struct intel_display *display, u32 mode_clock, u32 mode_hdisplay, @@ -954,6 +956,7 @@ u32 get_max_compressed_bpp_with_joiner(struct intel_display *display, return max_bpp; } +/* TODO: return a bpp_x16 value */ u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display, u32 link_clock, u32 lane_count, u32 mode_clock, u32 mode_hdisplay, @@ -1050,10 +1053,11 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes; /* - * 3 DSC Slices per pipe need 3 DSC engines, - * which is supported only with Ultrajoiner. + * 3 DSC Slices per pipe need 3 DSC engines, which is supported only + * with Ultrajoiner only for some platforms. */ - if (valid_dsc_slicecount[i] == 3 && num_joined_pipes != 4) + if (valid_dsc_slicecount[i] == 3 && + (!HAS_DSC_3ENGINES(display) || num_joined_pipes != 4)) continue; if (test_slice_count > @@ -1193,7 +1197,7 @@ intel_dp_output_format(struct intel_connector *connector, int intel_dp_min_bpp(enum intel_output_format output_format) { if (output_format == INTEL_OUTPUT_FORMAT_RGB) - return 6 * 3; + return intel_display_min_pipe_bpp(); else return 8 * 3; } @@ -2065,7 +2069,7 @@ int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector pipe_config, bpc) >> 4; } -static int dsc_src_min_compressed_bpp(void) +int intel_dp_dsc_min_src_compressed_bpp(void) { /* Min Compressed bpp supported by source is 8 */ return 8; @@ -2097,7 +2101,7 @@ static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp) /* * Note: for pre-13 display you still need to check the validity of each step. */ -static int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector) +int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector) { struct intel_display *display = to_intel_display(connector); u8 incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); @@ -2105,12 +2109,19 @@ static int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector) if (DISPLAY_VER(display) < 14 || !incr) return fxp_q4_from_int(1); + if (connector->mst.dp && + !connector->link.force_bpp_x16 && !connector->mst.dp->force_dsc_fractional_bpp_en) + return fxp_q4_from_int(1); + /* fxp q4 */ return fxp_q4_from_int(1) / incr; } -/* Note: This is not universally usable! */ -static bool intel_dp_dsc_valid_bpp(struct intel_dp *intel_dp, int bpp_x16) +/* + * Note: for bpp_x16 to be valid it must be also within the source/sink's + * min..max bpp capability range. + */ +bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16) { struct intel_display *display = to_intel_display(intel_dp); int i; @@ -2148,24 +2159,16 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, const struct intel_connector *connector = to_intel_connector(conn_state->connector); const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; int output_bpp; - int dsc_min_bpp; - int dsc_max_bpp; int min_bpp_x16, max_bpp_x16, bpp_step_x16; int dsc_joiner_max_bpp; int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config); int bpp_x16; int ret; - dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16); - dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->clock, adjusted_mode->hdisplay, num_joined_pipes); - dsc_max_bpp = min(dsc_joiner_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16)); - - /* FIXME: remove the round trip via integers */ - min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp); - max_bpp_x16 = fxp_q4_from_int(dsc_max_bpp); + max_bpp_x16 = min(fxp_q4_from_int(dsc_joiner_max_bpp), limits->link.max_bpp_x16); bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector); @@ -2173,8 +2176,12 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp); max_bpp_x16 = min(max_bpp_x16, fxp_q4_from_int(output_bpp) - bpp_step_x16); + drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16)); + min_bpp_x16 = round_up(limits->link.min_bpp_x16, bpp_step_x16); + max_bpp_x16 = round_down(max_bpp_x16, bpp_step_x16); + for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) { - if (!intel_dp_dsc_valid_bpp(intel_dp, bpp_x16)) + if (!intel_dp_dsc_valid_compressed_bpp(intel_dp, bpp_x16)) continue; ret = dsc_compute_link_config(intel_dp, @@ -2477,7 +2484,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; - dsc_src_min_bpp = dsc_src_min_compressed_bpp(); + dsc_src_min_bpp = intel_dp_dsc_min_src_compressed_bpp(); dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state); dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); limits->link.min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp); @@ -2522,6 +2529,7 @@ intel_dp_dsc_compute_pipe_bpp_limits(struct intel_dp *intel_dp, bool intel_dp_compute_config_limits(struct intel_dp *intel_dp, + struct intel_connector *connector, struct intel_crtc_state *crtc_state, bool respect_downstream_limits, bool dsc, @@ -2575,7 +2583,7 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp, intel_dp_test_compute_config(intel_dp, crtc_state, limits); return intel_dp_compute_config_link_bpp_limits(intel_dp, - intel_dp->attached_connector, + connector, crtc_state, dsc, limits); @@ -2636,7 +2644,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes); dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en || - !intel_dp_compute_config_limits(intel_dp, pipe_config, + !intel_dp_compute_config_limits(intel_dp, connector, pipe_config, respect_downstream_limits, false, &limits); @@ -2670,7 +2678,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, str_yes_no(ret), str_yes_no(joiner_needs_dsc), str_yes_no(intel_dp->force_dsc_en)); - if (!intel_dp_compute_config_limits(intel_dp, pipe_config, + if (!intel_dp_compute_config_limits(intel_dp, connector, pipe_config, respect_downstream_limits, true, &limits)) @@ -3103,6 +3111,76 @@ intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, } } +int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + struct intel_connector *connector = to_intel_connector(conn_state->connector); + int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8; + /* + * min symbol cycles is 3(BS,VBID, BE) for 128b/132b and + * 5(BS, VBID, MVID, MAUD, BE) for 8b/10b + */ + int min_sym_cycles = intel_dp_is_uhbr(crtc_state) ? 3 : 5; + bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); + int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state); + int min_hblank; + int max_lane_count = 4; + int hactive_sym_cycles, htotal_sym_cycles; + int dsc_slices = 0; + int link_bpp_x16; + + if (DISPLAY_VER(display) < 30) + return 0; + + /* MIN_HBLANK should be set only for 8b/10b MST or for 128b/132b SST/MST */ + if (!is_mst && !intel_dp_is_uhbr(crtc_state)) + return 0; + + if (crtc_state->dsc.compression_enable) { + dsc_slices = intel_dp_dsc_get_slice_count(connector, + adjusted_mode->crtc_clock, + adjusted_mode->crtc_hdisplay, + num_joined_pipes); + if (!dsc_slices) { + drm_dbg(display->drm, "failed to calculate dsc slice count\n"); + return -EINVAL; + } + } + + if (crtc_state->dsc.compression_enable) + link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16; + else + link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(crtc_state->output_format, + crtc_state->pipe_bpp)); + + /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */ + hactive_sym_cycles = drm_dp_link_symbol_cycles(max_lane_count, + adjusted_mode->hdisplay, + dsc_slices, + link_bpp_x16, + symbol_size, is_mst); + htotal_sym_cycles = adjusted_mode->htotal * hactive_sym_cycles / + adjusted_mode->hdisplay; + + min_hblank = htotal_sym_cycles - hactive_sym_cycles; + /* minimum Hblank calculation: https://groups.vesa.org/wg/DP/document/20494 */ + min_hblank = max(min_hblank, min_sym_cycles); + + /* + * adjust the BlankingStart/BlankingEnd framing control from + * the calculated value + */ + min_hblank = min_hblank - 2; + + min_hblank = min(10, min_hblank); + crtc_state->min_hblank = min_hblank; + + return 0; +} + int intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, @@ -3202,6 +3280,10 @@ intel_dp_compute_config(struct intel_encoder *encoder, &pipe_config->dp_m_n); } + ret = intel_dp_compute_min_hblank(pipe_config, conn_state); + if (ret) + return ret; + /* FIXME: abstract this better */ if (pipe_config->splitter.enable) pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count; @@ -4455,6 +4537,23 @@ intel_dp_mst_disconnect(struct intel_dp *intel_dp) static bool intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi) { + struct intel_display *display = to_intel_display(intel_dp); + + /* + * Display WA for HSD #13013007775: mtl/arl/lnl + * Read the sink count and link service IRQ registers in separate + * transactions to prevent disconnecting the sink on a TBT link + * inadvertently. + */ + if (IS_DISPLAY_VER(display, 14, 20) && !display->platform.battlemage) { + if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 3) != 3) + return false; + + /* DP_SINK_COUNT_ESI + 3 == DP_LINK_SERVICE_IRQ_VECTOR_ESI0 */ + return drm_dp_dpcd_readb(&intel_dp->aux, DP_LINK_SERVICE_IRQ_VECTOR_ESI0, + &esi[3]) == 1; + } + return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4; } @@ -5391,6 +5490,11 @@ intel_dp_short_pulse(struct intel_dp *intel_dp) intel_psr_short_pulse(intel_dp); + if (intel_alpm_get_error(intel_dp)) { + intel_alpm_disable(intel_dp); + intel_dp->alpm_parameters.sink_alpm_error = true; + } + if (intel_dp_test_short_pulse(intel_dp)) reprobe_needed = true; @@ -5686,6 +5790,28 @@ intel_dp_detect_sdp_caps(struct intel_dp *intel_dp) drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd); } +static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external) +{ + struct intel_connector *connector = intel_dp->attached_connector; + + if (intel_dp_is_edp(intel_dp)) + return false; + + if (force_on_external) + return true; + + if (intel_dp->is_mst) + return false; + + return drm_edid_has_quirk(&connector->base, DRM_EDID_QUIRK_DP_DPCD_PROBE); +} + +void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external) +{ + drm_dp_dpcd_set_probe(&intel_dp->aux, + intel_dp_needs_dpcd_probe(intel_dp, force_on_external)); +} + static int intel_dp_detect(struct drm_connector *_connector, struct drm_modeset_acquire_ctx *ctx, @@ -5814,6 +5940,8 @@ out_unset_edid: if (status != connector_status_connected && !intel_dp->is_mst) intel_dp_unset_edid(intel_dp); + intel_dp_dpcd_set_probe(intel_dp, false); + if (!intel_dp_is_edp(intel_dp)) drm_dp_set_subconnector_property(&connector->base, status, @@ -5826,23 +5954,26 @@ out_vdd_off: } static void -intel_dp_force(struct drm_connector *connector) +intel_dp_force(struct drm_connector *_connector) { - struct intel_display *display = to_intel_display(connector->dev); - struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); + struct intel_connector *connector = to_intel_connector(_connector); + struct intel_display *display = to_intel_display(connector); + struct intel_dp *intel_dp = intel_attached_dp(connector); drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", - connector->base.id, connector->name); + connector->base.base.id, connector->base.name); if (!intel_display_driver_check_access(display)) return; intel_dp_unset_edid(intel_dp); - if (connector->status != connector_status_connected) + if (connector->base.status != connector_status_connected) return; intel_dp_set_edid(intel_dp); + + intel_dp_dpcd_set_probe(intel_dp, false); } static int intel_dp_get_modes(struct drm_connector *_connector) @@ -5878,24 +6009,25 @@ static int intel_dp_get_modes(struct drm_connector *_connector) } static int -intel_dp_connector_register(struct drm_connector *connector) +intel_dp_connector_register(struct drm_connector *_connector) { - struct intel_display *display = to_intel_display(connector->dev); - struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); + struct intel_connector *connector = to_intel_connector(_connector); + struct intel_display *display = to_intel_display(connector); + struct intel_dp *intel_dp = intel_attached_dp(connector); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); int ret; - ret = intel_connector_register(connector); + ret = intel_connector_register(&connector->base); if (ret) return ret; drm_dbg_kms(display->drm, "registering %s bus for %s\n", - intel_dp->aux.name, connector->kdev->kobj.name); + intel_dp->aux.name, connector->base.kdev->kobj.name); - intel_dp->aux.dev = connector->kdev; + intel_dp->aux.dev = connector->base.kdev; ret = drm_dp_aux_register(&intel_dp->aux); if (!ret) - drm_dp_cec_register_connector(&intel_dp->aux, connector); + drm_dp_cec_register_connector(&intel_dp->aux, &connector->base); if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata)) return ret; @@ -5906,20 +6038,21 @@ intel_dp_connector_register(struct drm_connector *connector) */ if (intel_lspcon_init(dig_port)) { if (intel_lspcon_detect_hdr_capability(dig_port)) - drm_connector_attach_hdr_output_metadata_property(connector); + drm_connector_attach_hdr_output_metadata_property(&connector->base); } return ret; } static void -intel_dp_connector_unregister(struct drm_connector *connector) +intel_dp_connector_unregister(struct drm_connector *_connector) { - struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); + struct intel_connector *connector = to_intel_connector(_connector); + struct intel_dp *intel_dp = intel_attached_dp(connector); drm_dp_cec_unregister_connector(&intel_dp->aux); drm_dp_aux_unregister(&intel_dp->aux); - intel_connector_unregister(connector); + intel_connector_unregister(&connector->base); } void intel_dp_connector_sync_state(struct intel_connector *connector, @@ -5980,21 +6113,21 @@ static int intel_modeset_tile_group(struct intel_atomic_state *state, { struct intel_display *display = to_intel_display(state); struct drm_connector_list_iter conn_iter; - struct drm_connector *connector; + struct intel_connector *connector; int ret = 0; drm_connector_list_iter_begin(display->drm, &conn_iter); - drm_for_each_connector_iter(connector, &conn_iter) { + for_each_intel_connector_iter(connector, &conn_iter) { struct drm_connector_state *conn_state; struct intel_crtc_state *crtc_state; struct intel_crtc *crtc; - if (!connector->has_tile || - connector->tile_group->id != tile_group_id) + if (!connector->base.has_tile || + connector->base.tile_group->id != tile_group_id) continue; conn_state = drm_atomic_get_connector_state(&state->base, - connector); + &connector->base); if (IS_ERR(conn_state)) { ret = PTR_ERR(conn_state); break; @@ -6058,10 +6191,11 @@ static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, } static int intel_modeset_synced_crtcs(struct intel_atomic_state *state, - struct drm_connector *connector) + struct drm_connector *_connector) { + struct intel_connector *connector = to_intel_connector(_connector); const struct drm_connector_state *old_conn_state = - drm_atomic_get_old_connector_state(&state->base, connector); + drm_atomic_get_old_connector_state(&state->base, &connector->base); const struct intel_crtc_state *old_crtc_state; struct intel_crtc *crtc; u8 transcoders; @@ -6083,17 +6217,18 @@ static int intel_modeset_synced_crtcs(struct intel_atomic_state *state, transcoders); } -static int intel_dp_connector_atomic_check(struct drm_connector *conn, +static int intel_dp_connector_atomic_check(struct drm_connector *_connector, struct drm_atomic_state *_state) { - struct intel_display *display = to_intel_display(conn->dev); + struct intel_connector *connector = to_intel_connector(_connector); + struct intel_display *display = to_intel_display(connector); struct intel_atomic_state *state = to_intel_atomic_state(_state); - struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn); - struct intel_connector *intel_conn = to_intel_connector(conn); - struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder); + struct drm_connector_state *conn_state = + drm_atomic_get_new_connector_state(_state, &connector->base); + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); int ret; - ret = intel_digital_connector_atomic_check(conn, &state->base); + ret = intel_digital_connector_atomic_check(&connector->base, &state->base); if (ret) return ret; @@ -6103,12 +6238,12 @@ static int intel_dp_connector_atomic_check(struct drm_connector *conn, return ret; } - if (!intel_connector_needs_modeset(state, conn)) + if (!intel_connector_needs_modeset(state, &connector->base)) return 0; ret = intel_dp_tunnel_atomic_check_state(state, intel_dp, - intel_conn); + connector); if (ret) return ret; @@ -6119,26 +6254,26 @@ static int intel_dp_connector_atomic_check(struct drm_connector *conn, if (DISPLAY_VER(display) < 9) return 0; - if (conn->has_tile) { - ret = intel_modeset_tile_group(state, conn->tile_group->id); + if (connector->base.has_tile) { + ret = intel_modeset_tile_group(state, connector->base.tile_group->id); if (ret) return ret; } - return intel_modeset_synced_crtcs(state, conn); + return intel_modeset_synced_crtcs(state, &connector->base); } -static void intel_dp_oob_hotplug_event(struct drm_connector *connector, +static void intel_dp_oob_hotplug_event(struct drm_connector *_connector, enum drm_connector_status hpd_state) { - struct intel_display *display = to_intel_display(connector->dev); - struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); - struct drm_i915_private *i915 = to_i915(connector->dev); + struct intel_connector *connector = to_intel_connector(_connector); + struct intel_display *display = to_intel_display(connector); + struct intel_encoder *encoder = intel_attached_encoder(connector); bool hpd_high = hpd_state == connector_status_connected; unsigned int hpd_pin = encoder->hpd_pin; bool need_work = false; - spin_lock_irq(&i915->irq_lock); + spin_lock_irq(&display->irq.lock); if (hpd_high != test_bit(hpd_pin, &display->hotplug.oob_hotplug_last_state)) { display->hotplug.event_bits |= BIT(hpd_pin); @@ -6147,7 +6282,7 @@ static void intel_dp_oob_hotplug_event(struct drm_connector *connector, hpd_high); need_work = true; } - spin_unlock_irq(&i915->irq_lock); + spin_unlock_irq(&display->irq.lock); if (need_work) intel_hpd_schedule_detection(display); @@ -6211,10 +6346,11 @@ intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd) * complete the DP tunnel BW request for the latter connector/encoder * waiting for this encoder's DPRX read, perform a dummy read here. */ - if (long_hpd) + if (long_hpd) { + intel_dp_dpcd_set_probe(intel_dp, true); + intel_dp_read_dprx_caps(intel_dp, dpcd); - if (long_hpd) { intel_dp->reset_link_params = true; intel_dp_invalidate_source_oui(intel_dp); @@ -6279,36 +6415,37 @@ intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder) } static void -intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) +intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *_connector) { + struct intel_connector *connector = to_intel_connector(_connector); struct intel_display *display = to_intel_display(intel_dp); enum port port = dp_to_dig_port(intel_dp)->base.port; if (!intel_dp_is_edp(intel_dp)) - drm_connector_attach_dp_subconnector_property(connector); + drm_connector_attach_dp_subconnector_property(&connector->base); if (!display->platform.g4x && port != PORT_A) - intel_attach_force_audio_property(connector); + intel_attach_force_audio_property(&connector->base); - intel_attach_broadcast_rgb_property(connector); + intel_attach_broadcast_rgb_property(&connector->base); if (HAS_GMCH(display)) - drm_connector_attach_max_bpc_property(connector, 6, 10); + drm_connector_attach_max_bpc_property(&connector->base, 6, 10); else if (DISPLAY_VER(display) >= 5) - drm_connector_attach_max_bpc_property(connector, 6, 12); + drm_connector_attach_max_bpc_property(&connector->base, 6, 12); /* Register HDMI colorspace for case of lspcon */ if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) { - drm_connector_attach_content_type_property(connector); - intel_attach_hdmi_colorspace_property(connector); + drm_connector_attach_content_type_property(&connector->base); + intel_attach_hdmi_colorspace_property(&connector->base); } else { - intel_attach_dp_colorspace_property(connector); + intel_attach_dp_colorspace_property(&connector->base); } if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base)) - drm_connector_attach_hdr_output_metadata_property(connector); + drm_connector_attach_hdr_output_metadata_property(&connector->base); if (HAS_VRR(display)) - drm_connector_attach_vrr_capable_property(connector); + drm_connector_attach_vrr_capable_property(&connector->base); } static void @@ -6343,7 +6480,6 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, struct intel_connector *connector) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct drm_display_mode *fixed_mode; struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; bool has_dpcd; @@ -6360,7 +6496,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, */ if (intel_get_lvds_encoder(display)) { drm_WARN_ON(display->drm, - !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); + !(HAS_PCH_IBX(display) || HAS_PCH_CPT(display))); drm_info(display->drm, "LVDS was detected, not registering eDP\n"); @@ -6391,7 +6527,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, */ intel_hpd_enable_detection(encoder); - intel_alpm_init_dpcd(intel_dp); + intel_alpm_init(intel_dp); /* Cache DPCD and EDID for edp. */ has_dpcd = intel_edp_init_dpcd(intel_dp, connector); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 9189db4c2594..0657f5681196 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -147,6 +147,7 @@ int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_con int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector, const struct intel_crtc_state *pipe_config, int bpc); +bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16); u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, int mode_clock, int mode_hdisplay, int num_joined_pipes); @@ -173,8 +174,6 @@ bool intel_dp_supports_dsc(struct intel_dp *intel_dp, const struct intel_connector *connector, const struct intel_crtc_state *crtc_state); -u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp); - void intel_ddi_update_pipe(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, @@ -194,6 +193,7 @@ void intel_dp_wait_source_oui(struct intel_dp *intel_dp); int intel_dp_output_bpp(enum intel_output_format output_format, int bpp); bool intel_dp_compute_config_limits(struct intel_dp *intel_dp, + struct intel_connector *connector, struct intel_crtc_state *crtc_state, bool respect_downstream_limits, bool dsc, @@ -208,5 +208,11 @@ bool intel_dp_has_connector(struct intel_dp *intel_dp, const struct drm_connector_state *conn_state); int intel_dp_dsc_max_src_input_bpc(struct intel_display *display); int intel_dp_dsc_min_src_input_bpc(void); +int intel_dp_dsc_min_src_compressed_bpp(void); +int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state); + +int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector); +void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external); #endif /* __INTEL_DP_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index 0496061203fb..829a7c0fbe4f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -3,8 +3,9 @@ * Copyright © 2020-2021 Intel Corporation */ -#include "i915_drv.h" -#include "i915_reg.h" +#include <drm/drm_print.h> + +#include "i915_utils.h" #include "intel_de.h" #include "intel_display_types.h" #include "intel_dp.h" @@ -111,10 +112,9 @@ static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *i915 = to_i915(display->drm); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); - if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(i915)) { + if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(display)) { /* Workaround for non-ULT HSW */ switch (index) { case 0: return 63; @@ -177,12 +177,11 @@ static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, int send_bytes, u32 aux_clock_divider) { - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_display *display = to_intel_display(intel_dp); u32 timeout; /* Max timeout value on G4x-BDW: 1.6ms */ - if (IS_BROADWELL(i915)) + if (display->platform.broadwell) timeout = DP_AUX_CH_CTL_TIME_OUT_600us; else timeout = DP_AUX_CH_CTL_TIME_OUT_400us; @@ -786,7 +785,6 @@ void intel_dp_aux_fini(struct intel_dp *intel_dp) void intel_dp_aux_init(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *i915 = to_i915(display->drm); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &dig_port->base; enum aux_ch aux_ch = dig_port->aux_ch; @@ -801,10 +799,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp) } else if (DISPLAY_VER(display) >= 9) { intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; intel_dp->aux_ch_data_reg = skl_aux_data_reg; - } else if (HAS_PCH_SPLIT(i915)) { + } else if (HAS_PCH_SPLIT(display)) { intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; intel_dp->aux_ch_data_reg = ilk_aux_data_reg; - } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { + } else if (display->platform.valleyview || display->platform.cherryview) { intel_dp->aux_ch_ctl_reg = vlv_aux_ctl_reg; intel_dp->aux_ch_data_reg = vlv_aux_data_reg; } else { @@ -814,9 +812,9 @@ void intel_dp_aux_init(struct intel_dp *intel_dp) if (DISPLAY_VER(display) >= 9) intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; - else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) + else if (display->platform.broadwell || display->platform.haswell) intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; - else if (HAS_PCH_SPLIT(i915)) + else if (HAS_PCH_SPLIT(display)) intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; else intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; @@ -836,6 +834,8 @@ void intel_dp_aux_init(struct intel_dp *intel_dp) intel_dp->aux.transfer = intel_dp_aux_transfer; cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); + + intel_dp_dpcd_set_probe(intel_dp, true); } static enum aux_ch default_aux_ch(struct intel_encoder *encoder) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c index 20ab90acb351..5537136c367a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c @@ -36,7 +36,6 @@ #include <drm/drm_print.h> -#include "i915_utils.h" #include "intel_backlight.h" #include "intel_display_core.h" #include "intel_display_types.h" @@ -146,10 +145,10 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector) * ranges for such panels. */ if (display->params.enable_dpcd_backlight != INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL && - !(connector->base.hdr_sink_metadata.hdmi_type1.metadata_type & + !(connector->base.display_info.hdr_sink_metadata.hdmi_type1.metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1))) { drm_info(display->drm, - "[CONNECTOR:%d:%s] Panel is missing HDR static metadata. Possible support for Intel HDR backlight interface is not used. If your backlight controls don't work try booting with i915.enable_dpcd_backlight=%d. needs this, please file a _new_ bug report on drm/i915, see " FDO_BUG_URL " for details.\n", + "[CONNECTOR:%d:%s] Panel is missing HDR static metadata. Possible support for Intel HDR backlight interface is not used. If your backlight controls don't work try booting with i915.enable_dpcd_backlight=%d.\n", connector->base.base.id, connector->base.name, INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL); return false; diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c index cc312596fb77..7bd775fb65a0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c @@ -11,9 +11,9 @@ #include <drm/display/drm_hdcp_helper.h> #include <drm/drm_print.h> -#include "i915_reg.h" #include "intel_ddi.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dp_hdcp.h" diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 4c15dcb103aa..74497c9a0554 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -23,14 +23,17 @@ * */ +#include <linux/log2.h> +#include <linux/math.h> + #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_edid.h> #include <drm/drm_fixed.h> +#include <drm/drm_print.h> #include <drm/drm_probe_helper.h> -#include "i915_drv.h" -#include "i915_reg.h" +#include "i915_utils.h" #include "intel_atomic.h" #include "intel_audio.h" #include "intel_connector.h" @@ -38,6 +41,7 @@ #include "intel_ddi.h" #include "intel_de.h" #include "intel_display_driver.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dp_hdcp.h" @@ -51,6 +55,7 @@ #include "intel_link_bw.h" #include "intel_pfit.h" #include "intel_psr.h" +#include "intel_step.h" #include "intel_vdsc.h" #include "intel_vrr.h" #include "skl_scaler.h" @@ -133,6 +138,7 @@ static bool intel_dp_mst_inc_active_streams(struct intel_dp *intel_dp) return intel_dp->mst.active_streams++ == 0; } +/* TODO: return a bpp_x16 value */ static int intel_dp_mst_max_dpt_bpp(const struct intel_crtc_state *crtc_state, bool dsc) { @@ -239,24 +245,13 @@ static int intel_dp_mst_dsc_get_slice_count(const struct intel_connector *connec num_joined_pipes); } -static void intel_dp_mst_compute_min_hblank(struct intel_crtc_state *crtc_state, - int bpp_x16) +static void mst_stream_update_slots(const struct intel_crtc_state *crtc_state, + struct drm_dp_mst_topology_state *topology_state) { - struct intel_display *display = to_intel_display(crtc_state); - const struct drm_display_mode *adjusted_mode = - &crtc_state->hw.adjusted_mode; - int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8; - int hblank; - - if (DISPLAY_VER(display) < 20) - return; - - /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */ - hblank = DIV_ROUND_UP((DIV_ROUND_UP - (adjusted_mode->htotal - adjusted_mode->hdisplay, 4) * bpp_x16), - symbol_size); + u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ? + DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B; - crtc_state->min_hblank = hblank; + drm_dp_mst_update_slots(topology_state, link_coding_cap); } int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, @@ -271,7 +266,7 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, to_intel_connector(conn_state->connector); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - bool is_mst = intel_dp->is_mst; + bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); int bpp_x16, slots = -EINVAL; int dsc_slice_count = 0; int max_dpt_bpp_x16; @@ -281,6 +276,12 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, fxp_q4_to_frac(max_bpp_x16) || fxp_q4_to_frac(bpp_step_x16))); + if (!bpp_step_x16) { + /* Allow using zero step only to indicate single try for a given bpp. */ + drm_WARN_ON(display->drm, min_bpp_x16 != max_bpp_x16); + bpp_step_x16 = 1; + } + if (is_mst) { mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst.mgr); if (IS_ERR(mst_state)) @@ -288,6 +289,8 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock, crtc_state->lane_count); + + mst_stream_update_slots(crtc_state, mst_state); } if (dsc) { @@ -316,12 +319,20 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, } } + drm_WARN_ON(display->drm, min_bpp_x16 % bpp_step_x16 || max_bpp_x16 % bpp_step_x16); + for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) { int local_bw_overhead; int link_bpp_x16; drm_dbg_kms(display->drm, "Trying bpp " FXP_Q4_FMT "\n", FXP_Q4_ARGS(bpp_x16)); + if (dsc && !intel_dp_dsc_valid_compressed_bpp(intel_dp, bpp_x16)) { + /* SST must have validated the single bpp tried here already earlier. */ + drm_WARN_ON(display->drm, !is_mst); + continue; + } + link_bpp_x16 = dsc ? bpp_x16 : fxp_q4_from_int(intel_dp_output_bpp(crtc_state->output_format, fxp_q4_to_int(bpp_x16))); @@ -329,8 +340,6 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, false, dsc_slice_count, link_bpp_x16); - intel_dp_mst_compute_min_hblank(crtc_state, link_bpp_x16); - intel_dp_mst_compute_m_n(crtc_state, local_bw_overhead, link_bpp_x16, @@ -387,6 +396,10 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst.mgr, connector->mst.port, dfixed_trunc(pbn)); + + /* TODO: Check this already in drm_dp_atomic_find_time_slots(). */ + if (slots > mst_state->total_avail_slots) + slots = -EINVAL; } else { /* Same as above for remote_tu */ crtc_state->dp_m_n.tu = ALIGN(crtc_state->dp_m_n.tu, @@ -406,10 +419,6 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, break; } - - /* Allow using zero step to indicate one try */ - if (!bpp_step_x16) - break; } if (slots < 0) { @@ -457,7 +466,8 @@ static int mst_stream_dsc_compute_link_config(struct intel_dp *intel_dp, int num_bpc; u8 dsc_bpc[3] = {}; int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp; - int min_compressed_bpp, max_compressed_bpp; + int min_compressed_bpp_x16, max_compressed_bpp_x16; + int bpp_step_x16; max_bpp = limits->pipe.max_bpp; min_bpp = limits->pipe.min_bpp; @@ -482,46 +492,28 @@ static int mst_stream_dsc_compute_link_config(struct intel_dp *intel_dp, crtc_state->pipe_bpp = max_bpp; - max_compressed_bpp = fxp_q4_to_int(limits->link.max_bpp_x16); - min_compressed_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16); + min_compressed_bpp_x16 = limits->link.min_bpp_x16; + max_compressed_bpp_x16 = limits->link.max_bpp_x16; + + drm_dbg_kms(display->drm, + "DSC Sink supported compressed min bpp " FXP_Q4_FMT " compressed max bpp " FXP_Q4_FMT "\n", + FXP_Q4_ARGS(min_compressed_bpp_x16), FXP_Q4_ARGS(max_compressed_bpp_x16)); + + bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector); - drm_dbg_kms(display->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n", - min_compressed_bpp, max_compressed_bpp); + max_compressed_bpp_x16 = min(max_compressed_bpp_x16, fxp_q4_from_int(crtc_state->pipe_bpp) - bpp_step_x16); - /* Align compressed bpps according to our own constraints */ - max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(display, max_compressed_bpp, - crtc_state->pipe_bpp); - min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(display, min_compressed_bpp, - crtc_state->pipe_bpp); + drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16)); + min_compressed_bpp_x16 = round_up(min_compressed_bpp_x16, bpp_step_x16); + max_compressed_bpp_x16 = round_down(max_compressed_bpp_x16, bpp_step_x16); crtc_state->lane_count = limits->max_lane_count; crtc_state->port_clock = limits->max_rate; return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state, conn_state, - fxp_q4_from_int(min_compressed_bpp), - fxp_q4_from_int(max_compressed_bpp), - fxp_q4_from_int(1), true); -} - -static int mst_stream_update_slots(struct intel_dp *intel_dp, - struct intel_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - struct intel_display *display = to_intel_display(intel_dp); - struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst.mgr; - struct drm_dp_mst_topology_state *topology_state; - u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ? - DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B; - - topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr); - if (IS_ERR(topology_state)) { - drm_dbg_kms(display->drm, "slot update failed\n"); - return PTR_ERR(topology_state); - } - - drm_dp_mst_update_slots(topology_state, link_coding_cap); - - return 0; + min_compressed_bpp_x16, + max_compressed_bpp_x16, + bpp_step_x16, true); } static int mode_hblank_period_ns(const struct drm_display_mode *mode) @@ -619,12 +611,13 @@ adjust_limits_for_dsc_hblank_expansion_quirk(struct intel_dp *intel_dp, static bool mst_stream_compute_config_limits(struct intel_dp *intel_dp, - const struct intel_connector *connector, + struct intel_connector *connector, struct intel_crtc_state *crtc_state, bool dsc, struct link_config_limits *limits) { - if (!intel_dp_compute_config_limits(intel_dp, crtc_state, false, dsc, + if (!intel_dp_compute_config_limits(intel_dp, connector, + crtc_state, false, dsc, limits)) return false; @@ -728,10 +721,6 @@ static int mst_stream_compute_config(struct intel_encoder *encoder, if (ret) return ret; - ret = mst_stream_update_slots(intel_dp, pipe_config, conn_state); - if (ret) - return ret; - pipe_config->limited_color_range = intel_dp_limited_color_range(pipe_config, conn_state); @@ -739,6 +728,10 @@ static int mst_stream_compute_config(struct intel_encoder *encoder, pipe_config->lane_lat_optim_mask = bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); + ret = intel_dp_compute_min_hblank(pipe_config, conn_state); + if (ret) + return ret; + intel_vrr_compute_config(pipe_config, conn_state); intel_dp_audio_compute_config(encoder, pipe_config, conn_state); @@ -1021,12 +1014,10 @@ static void mst_stream_disable(struct intel_atomic_state *state, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { - struct intel_display *display = to_intel_display(state); struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); struct intel_dp *intel_dp = to_primary_dp(encoder); struct intel_connector *connector = to_intel_connector(old_conn_state->connector); - enum transcoder trans = old_crtc_state->cpu_transcoder; if (intel_dp_mst_active_streams(intel_dp) == 1) intel_dp->link.active = false; @@ -1034,9 +1025,6 @@ static void mst_stream_disable(struct intel_atomic_state *state, intel_hdcp_disable(intel_mst->connector); intel_dp_sink_disable_decompression(state, connector, old_crtc_state); - - if (DISPLAY_VER(display) >= 20) - intel_de_write(display, DP_MIN_HBLANK_CTL(trans), 0); } static void mst_stream_post_disable(struct intel_atomic_state *state, @@ -1305,7 +1293,7 @@ static void mst_stream_enable(struct intel_atomic_state *state, enum transcoder trans = pipe_config->cpu_transcoder; bool first_mst_stream = intel_dp_mst_active_streams(intel_dp) == 1; struct intel_crtc *pipe_crtc; - int ret, i, min_hblank; + int ret, i; drm_WARN_ON(display->drm, pipe_config->has_pch_encoder); @@ -1320,29 +1308,6 @@ static void mst_stream_enable(struct intel_atomic_state *state, TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); } - if (DISPLAY_VER(display) >= 20) { - /* - * adjust the BlankingStart/BlankingEnd framing control from - * the calculated value - */ - min_hblank = pipe_config->min_hblank - 2; - - /* Maximum value to be programmed is limited to 0x10 */ - min_hblank = min(0x10, min_hblank); - - /* - * Minimum hblank accepted for 128b/132b would be 5 and for - * 8b/10b would be 3 symbol count - */ - if (intel_dp_is_uhbr(pipe_config)) - min_hblank = max(min_hblank, 5); - else - min_hblank = max(min_hblank, 3); - - intel_de_write(display, DP_MIN_HBLANK_CTL(trans), - min_hblank); - } - enable_bs_jitter_was(pipe_config); intel_ddi_enable_transcoder_func(encoder, pipe_config); @@ -1371,8 +1336,6 @@ static void mst_stream_enable(struct intel_atomic_state *state, FECSTALL_DIS_DPTSTREAM_DPTTG, pipe_config->fec_enable ? FECSTALL_DIS_DPTSTREAM_DPTTG : 0); - intel_audio_sdp_split_update(pipe_config); - intel_enable_transcoder(pipe_config); for_each_pipe_crtc_modeset_enable(display, pipe_crtc, pipe_config, i) { diff --git a/drivers/gpu/drm/i915/display/intel_dp_test.c b/drivers/gpu/drm/i915/display/intel_dp_test.c index bd61f3c3ec91..6ed5012c5fac 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_test.c +++ b/drivers/gpu/drm/i915/display/intel_dp_test.c @@ -10,9 +10,9 @@ #include <drm/drm_print.h> #include <drm/drm_probe_helper.h> -#include "i915_reg.h" #include "intel_ddi.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dp_link_training.h" diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 429f89543789..3f77ad92c156 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -21,13 +21,15 @@ * DEALINGS IN THE SOFTWARE. */ +#include <drm/drm_print.h> + #include "bxt_dpio_phy_regs.h" -#include "i915_drv.h" -#include "i915_reg.h" +#include "i915_utils.h" #include "intel_ddi.h" #include "intel_ddi_buf_trans.h" #include "intel_de.h" #include "intel_display_power_well.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dpio_phy.h" @@ -222,9 +224,7 @@ static const struct bxt_dpio_phy_info glk_dpio_phy_info[] = { static const struct bxt_dpio_phy_info * bxt_get_phy_list(struct intel_display *display, int *count) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - - if (IS_GEMINILAKE(dev_priv)) { + if (display->platform.geminilake) { *count = ARRAY_SIZE(glk_dpio_phy_info); return glk_dpio_phy_info; } else { @@ -428,7 +428,7 @@ static void _bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy) * use 1ms due to occasional timeouts observed with that. */ if (intel_de_wait_fw(display, BXT_PORT_CL1CM_DW0(phy), - PHY_RESERVED | PHY_POWER_GOOD, PHY_POWER_GOOD, 1)) + PHY_RESERVED | PHY_POWER_GOOD, PHY_POWER_GOOD, 1, NULL)) drm_err(display->drm, "timeout during PHY%d power on\n", phy); @@ -717,53 +717,53 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, u32 deemph_reg_value, u32 margin_reg_value, bool uniq_trans_scale) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); u32 val; int i; - vlv_dpio_get(dev_priv); + vlv_dpio_get(display->drm); /* Clear calc init */ - val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW10(ch)); + val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW10(ch)); val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; - vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW10(ch), val); + vlv_dpio_write(display->drm, phy, VLV_PCS01_DW10(ch), val); if (crtc_state->lane_count > 2) { - val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW10(ch)); + val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW10(ch)); val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; - vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW10(ch), val); + vlv_dpio_write(display->drm, phy, VLV_PCS23_DW10(ch), val); } - val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW9(ch)); + val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW9(ch)); val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; - vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW9(ch), val); + vlv_dpio_write(display->drm, phy, VLV_PCS01_DW9(ch), val); if (crtc_state->lane_count > 2) { - val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW9(ch)); + val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW9(ch)); val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; - vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW9(ch), val); + vlv_dpio_write(display->drm, phy, VLV_PCS23_DW9(ch), val); } /* Program swing deemph */ for (i = 0; i < crtc_state->lane_count; i++) { - val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW4(ch, i)); + val = vlv_dpio_read(display->drm, phy, CHV_TX_DW4(ch, i)); val &= ~DPIO_SWING_DEEMPH9P5_MASK; val |= DPIO_SWING_DEEMPH9P5(deemph_reg_value); - vlv_dpio_write(dev_priv, phy, CHV_TX_DW4(ch, i), val); + vlv_dpio_write(display->drm, phy, CHV_TX_DW4(ch, i), val); } /* Program swing margin */ for (i = 0; i < crtc_state->lane_count; i++) { - val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW2(ch, i)); + val = vlv_dpio_read(display->drm, phy, CHV_TX_DW2(ch, i)); val &= ~DPIO_SWING_MARGIN000_MASK; val |= DPIO_SWING_MARGIN000(margin_reg_value); @@ -776,7 +776,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, val &= ~DPIO_UNIQ_TRANS_SCALE_MASK; val |= DPIO_UNIQ_TRANS_SCALE(0x9a); - vlv_dpio_write(dev_priv, phy, CHV_TX_DW2(ch, i), val); + vlv_dpio_write(display->drm, phy, CHV_TX_DW2(ch, i), val); } /* @@ -786,79 +786,89 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, * 27 for ch0 and ch1. */ for (i = 0; i < crtc_state->lane_count; i++) { - val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW3(ch, i)); + val = vlv_dpio_read(display->drm, phy, CHV_TX_DW3(ch, i)); if (uniq_trans_scale) val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; else val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; - vlv_dpio_write(dev_priv, phy, CHV_TX_DW3(ch, i), val); + vlv_dpio_write(display->drm, phy, CHV_TX_DW3(ch, i), val); } /* Start swing calculation */ - val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW10(ch)); + val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW10(ch)); val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; - vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW10(ch), val); + vlv_dpio_write(display->drm, phy, VLV_PCS01_DW10(ch), val); if (crtc_state->lane_count > 2) { - val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW10(ch)); + val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW10(ch)); val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; - vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW10(ch), val); + vlv_dpio_write(display->drm, phy, VLV_PCS23_DW10(ch), val); } - vlv_dpio_put(dev_priv); + vlv_dpio_put(display->drm); } -void chv_data_lane_soft_reset(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - bool reset) +static void __chv_data_lane_soft_reset(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + bool reset) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); u32 val; - val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW0(ch)); + val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW0(ch)); if (reset) val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); else val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; - vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW0(ch), val); + vlv_dpio_write(display->drm, phy, VLV_PCS01_DW0(ch), val); if (crtc_state->lane_count > 2) { - val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW0(ch)); + val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW0(ch)); if (reset) val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); else val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; - vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW0(ch), val); + vlv_dpio_write(display->drm, phy, VLV_PCS23_DW0(ch), val); } - val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW1(ch)); + val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW1(ch)); val |= CHV_PCS_REQ_SOFTRESET_EN; if (reset) val &= ~DPIO_PCS_CLK_SOFT_RESET; else val |= DPIO_PCS_CLK_SOFT_RESET; - vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW1(ch), val); + vlv_dpio_write(display->drm, phy, VLV_PCS01_DW1(ch), val); if (crtc_state->lane_count > 2) { - val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW1(ch)); + val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW1(ch)); val |= CHV_PCS_REQ_SOFTRESET_EN; if (reset) val &= ~DPIO_PCS_CLK_SOFT_RESET; else val |= DPIO_PCS_CLK_SOFT_RESET; - vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW1(ch), val); + vlv_dpio_write(display->drm, phy, VLV_PCS23_DW1(ch), val); } } +void chv_data_lane_soft_reset(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + bool reset) +{ + struct intel_display *display = to_intel_display(encoder); + + vlv_dpio_get(display->drm); + __chv_data_lane_soft_reset(encoder, crtc_state, reset); + vlv_dpio_put(display->drm); +} + void chv_phy_pre_pll_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); @@ -877,47 +887,47 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, chv_phy_powergate_lanes(encoder, true, lane_mask); - vlv_dpio_get(dev_priv); + vlv_dpio_get(display->drm); /* Assert data lane reset */ - chv_data_lane_soft_reset(encoder, crtc_state, true); + __chv_data_lane_soft_reset(encoder, crtc_state, true); /* program left/right clock distribution */ if (pipe != PIPE_B) { - val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0); + val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW5_CH0); val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); if (ch == DPIO_CH0) val |= CHV_BUFLEFTENA1_FORCE; if (ch == DPIO_CH1) val |= CHV_BUFRIGHTENA1_FORCE; - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val); + vlv_dpio_write(display->drm, phy, CHV_CMN_DW5_CH0, val); } else { - val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1); + val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW1_CH1); val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); if (ch == DPIO_CH0) val |= CHV_BUFLEFTENA2_FORCE; if (ch == DPIO_CH1) val |= CHV_BUFRIGHTENA2_FORCE; - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val); + vlv_dpio_write(display->drm, phy, CHV_CMN_DW1_CH1, val); } /* program clock channel usage */ - val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(ch)); + val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW8(ch)); val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; if (pipe == PIPE_B) val |= DPIO_PCS_USEDCLKCHANNEL; else val &= ~DPIO_PCS_USEDCLKCHANNEL; - vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW8(ch), val); + vlv_dpio_write(display->drm, phy, VLV_PCS01_DW8(ch), val); if (crtc_state->lane_count > 2) { - val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW8(ch)); + val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW8(ch)); val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; if (pipe == PIPE_B) val |= DPIO_PCS_USEDCLKCHANNEL; else val &= ~DPIO_PCS_USEDCLKCHANNEL; - vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW8(ch), val); + vlv_dpio_write(display->drm, phy, VLV_PCS23_DW8(ch), val); } /* @@ -925,38 +935,38 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, * matches the pipe, but here we need to * pick the CL based on the port. */ - val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW19(ch)); + val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW19(ch)); if (pipe == PIPE_B) val |= CHV_CMN_USEDCLKCHANNEL; else val &= ~CHV_CMN_USEDCLKCHANNEL; - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW19(ch), val); + vlv_dpio_write(display->drm, phy, CHV_CMN_DW19(ch), val); - vlv_dpio_put(dev_priv); + vlv_dpio_put(display->drm); } void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); int data, i, stagger; u32 val; - vlv_dpio_get(dev_priv); + vlv_dpio_get(display->drm); /* allow hardware to manage TX FIFO reset source */ - val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW11(ch)); + val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW11(ch)); val &= ~DPIO_LANEDESKEW_STRAP_OVRD; - vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW11(ch), val); + vlv_dpio_write(display->drm, phy, VLV_PCS01_DW11(ch), val); if (crtc_state->lane_count > 2) { - val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW11(ch)); + val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW11(ch)); val &= ~DPIO_LANEDESKEW_STRAP_OVRD; - vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW11(ch), val); + vlv_dpio_write(display->drm, phy, VLV_PCS23_DW11(ch), val); } /* Program Tx lane latency optimal setting*/ @@ -966,7 +976,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, data = 0; else data = (i == 1) ? 0 : DPIO_UPAR; - vlv_dpio_write(dev_priv, phy, CHV_TX_DW14(ch, i), data); + vlv_dpio_write(display->drm, phy, CHV_TX_DW14(ch, i), data); } /* Data lane stagger programming */ @@ -981,17 +991,17 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, else stagger = 0x2; - val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW11(ch)); + val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW11(ch)); val |= DPIO_TX2_STAGGER_MASK(0x1f); - vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW11(ch), val); + vlv_dpio_write(display->drm, phy, VLV_PCS01_DW11(ch), val); if (crtc_state->lane_count > 2) { - val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW11(ch)); + val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW11(ch)); val |= DPIO_TX2_STAGGER_MASK(0x1f); - vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW11(ch), val); + vlv_dpio_write(display->drm, phy, VLV_PCS23_DW11(ch), val); } - vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW12(ch), + vlv_dpio_write(display->drm, phy, VLV_PCS01_DW12(ch), DPIO_LANESTAGGER_STRAP(stagger) | DPIO_LANESTAGGER_STRAP_OVRD | DPIO_TX1_STAGGER_MASK(0x1f) | @@ -999,7 +1009,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, DPIO_TX2_STAGGER_MULT(0)); if (crtc_state->lane_count > 2) { - vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW12(ch), + vlv_dpio_write(display->drm, phy, VLV_PCS23_DW12(ch), DPIO_LANESTAGGER_STRAP(stagger) | DPIO_LANESTAGGER_STRAP_OVRD | DPIO_TX1_STAGGER_MASK(0x1f) | @@ -1008,9 +1018,9 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, } /* Deassert data lane reset */ - chv_data_lane_soft_reset(encoder, crtc_state, false); + __chv_data_lane_soft_reset(encoder, crtc_state, false); - vlv_dpio_put(dev_priv); + vlv_dpio_put(display->drm); } void chv_phy_release_cl2_override(struct intel_encoder *encoder) @@ -1027,25 +1037,25 @@ void chv_phy_release_cl2_override(struct intel_encoder *encoder) void chv_phy_post_pll_disable(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe; u32 val; - vlv_dpio_get(dev_priv); + vlv_dpio_get(display->drm); /* disable left/right clock distribution */ if (pipe != PIPE_B) { - val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0); + val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW5_CH0); val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val); + vlv_dpio_write(display->drm, phy, CHV_CMN_DW5_CH0, val); } else { - val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1); + val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW1_CH1); val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val); + vlv_dpio_write(display->drm, phy, CHV_CMN_DW1_CH1, val); } - vlv_dpio_put(dev_priv); + vlv_dpio_put(display->drm); /* * Leave the power down bit cleared for at least one @@ -1064,97 +1074,97 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder, u32 demph_reg_value, u32 preemph_reg_value, u32 uniqtranscale_reg_value, u32 tx3_demph) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); - vlv_dpio_get(dev_priv); + vlv_dpio_get(display->drm); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), 0x00000000); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW4_GRP(ch), demph_reg_value); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW2_GRP(ch), - uniqtranscale_reg_value); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW3_GRP(ch), 0x0C782040); + vlv_dpio_write(display->drm, phy, VLV_TX_DW5_GRP(ch), 0x00000000); + vlv_dpio_write(display->drm, phy, VLV_TX_DW4_GRP(ch), demph_reg_value); + vlv_dpio_write(display->drm, phy, VLV_TX_DW2_GRP(ch), + uniqtranscale_reg_value); + vlv_dpio_write(display->drm, phy, VLV_TX_DW3_GRP(ch), 0x0C782040); if (tx3_demph) - vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch, 3), tx3_demph); + vlv_dpio_write(display->drm, phy, VLV_TX_DW4(ch, 3), tx3_demph); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11_GRP(ch), 0x00030000); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN); + vlv_dpio_write(display->drm, phy, VLV_PCS_DW11_GRP(ch), 0x00030000); + vlv_dpio_write(display->drm, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value); + vlv_dpio_write(display->drm, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN); - vlv_dpio_put(dev_priv); + vlv_dpio_put(display->drm); } void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); /* Program Tx lane resets to default */ - vlv_dpio_get(dev_priv); + vlv_dpio_get(display->drm); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch), + vlv_dpio_write(display->drm, phy, VLV_PCS_DW0_GRP(ch), DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), + vlv_dpio_write(display->drm, phy, VLV_PCS_DW1_GRP(ch), DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | DPIO_PCS_CLK_DATAWIDTH_8_10 | DPIO_PCS_CLK_SOFT_RESET); /* Fix up inter-pair skew failure */ - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW11_GRP(ch), 0x00001500); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW14_GRP(ch), 0x40400000); + vlv_dpio_write(display->drm, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00); + vlv_dpio_write(display->drm, phy, VLV_TX_DW11_GRP(ch), 0x00001500); + vlv_dpio_write(display->drm, phy, VLV_TX_DW14_GRP(ch), 0x40400000); - vlv_dpio_put(dev_priv); + vlv_dpio_put(display->drm); } void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); enum pipe pipe = crtc->pipe; u32 val; - vlv_dpio_get(dev_priv); + vlv_dpio_get(display->drm); /* Enable clock channels for this port */ val = DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; if (pipe == PIPE_B) val |= DPIO_PCS_USEDCLKCHANNEL; val |= 0xc4; - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8_GRP(ch), val); + vlv_dpio_write(display->drm, phy, VLV_PCS_DW8_GRP(ch), val); /* Program lane clock */ - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14_GRP(ch), 0x00760018); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23_GRP(ch), 0x00400888); + vlv_dpio_write(display->drm, phy, VLV_PCS_DW14_GRP(ch), 0x00760018); + vlv_dpio_write(display->drm, phy, VLV_PCS_DW23_GRP(ch), 0x00400888); - vlv_dpio_put(dev_priv); + vlv_dpio_put(display->drm); } void vlv_phy_reset_lanes(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state) { + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); - vlv_dpio_get(dev_priv); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch), 0x00000000); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060); - vlv_dpio_put(dev_priv); + vlv_dpio_get(display->drm); + vlv_dpio_write(display->drm, phy, VLV_PCS_DW0_GRP(ch), 0x00000000); + vlv_dpio_write(display->drm, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060); + vlv_dpio_put(display->drm); } void vlv_wait_port_ready(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 0481b1365b85..f969c5399a51 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -6,13 +6,14 @@ #include <linux/kernel.h> #include <linux/string_helpers.h> -#include "i915_drv.h" -#include "i915_reg.h" +#include <drm/drm_print.h> + #include "intel_atomic.h" #include "intel_crtc.h" #include "intel_cx0_phy.h" #include "intel_de.h" #include "intel_display.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dpio_phy.h" #include "intel_dpll.h" @@ -24,11 +25,11 @@ #include "vlv_dpio_phy_regs.h" #include "vlv_sideband.h" -struct intel_dpll_funcs { +struct intel_dpll_global_funcs { int (*crtc_compute_clock)(struct intel_atomic_state *state, struct intel_crtc *crtc); - int (*crtc_get_shared_dpll)(struct intel_atomic_state *state, - struct intel_crtc *crtc); + int (*crtc_get_dpll)(struct intel_atomic_state *state, + struct intel_crtc *crtc); }; struct intel_limit { @@ -374,12 +375,11 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock) static int i9xx_pll_refclk(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; if ((hw_state->dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) return display->vbt.lvds_ssc_freq; - else if (HAS_PCH_SPLIT(i915)) + else if (HAS_PCH_SPLIT(display)) return 120000; else if (DISPLAY_VER(display) != 2) return 96000; @@ -514,8 +514,8 @@ void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state) void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; @@ -527,9 +527,9 @@ void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state) if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) return; - vlv_dpio_get(dev_priv); - tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(ch)); - vlv_dpio_put(dev_priv); + vlv_dpio_get(display->drm); + tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW3(ch)); + vlv_dpio_put(display->drm); clock.m1 = REG_FIELD_GET(DPIO_M1_DIV_MASK, tmp); clock.m2 = REG_FIELD_GET(DPIO_M2_DIV_MASK, tmp); @@ -542,8 +542,8 @@ void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state) void chv_crtc_clock_get(struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; @@ -555,13 +555,13 @@ void chv_crtc_clock_get(struct intel_crtc_state *crtc_state) if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) return; - vlv_dpio_get(dev_priv); - cmn_dw13 = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW13(ch)); - pll_dw0 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW0(ch)); - pll_dw1 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW1(ch)); - pll_dw2 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW2(ch)); - pll_dw3 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch)); - vlv_dpio_put(dev_priv); + vlv_dpio_get(display->drm); + cmn_dw13 = vlv_dpio_read(display->drm, phy, CHV_CMN_DW13(ch)); + pll_dw0 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW0(ch)); + pll_dw1 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW1(ch)); + pll_dw2 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW2(ch)); + pll_dw3 = vlv_dpio_read(display->drm, phy, CHV_PLL_DW3(ch)); + vlv_dpio_put(display->drm); clock.m1 = REG_FIELD_GET(DPIO_CHV_M1_DIV_MASK, pll_dw1) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; clock.m2 = REG_FIELD_GET(DPIO_CHV_M2_DIV_MASK, pll_dw0) << 22; @@ -1162,7 +1162,7 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state, intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) return 0; - ret = intel_compute_shared_dplls(state, crtc, encoder); + ret = intel_dpll_compute(state, crtc, encoder); if (ret) return ret; @@ -1177,8 +1177,8 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state, return 0; } -static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state, - struct intel_crtc *crtc) +static int hsw_crtc_get_dpll(struct intel_atomic_state *state, + struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = @@ -1190,7 +1190,7 @@ static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state, intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) return 0; - return intel_reserve_shared_dplls(state, crtc, encoder); + return intel_dpll_reserve(state, crtc, encoder); } static int dg2_crtc_compute_clock(struct intel_atomic_state *state, @@ -1224,7 +1224,7 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state, if (ret) return ret; - /* TODO: Do the readback via intel_compute_shared_dplls() */ + /* TODO: Do the readback via intel_dpll_compute() */ crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); @@ -1235,12 +1235,10 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state, static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && ((intel_panel_use_ssc(display) && display->vbt.lvds_ssc_freq == 100000) || - (HAS_PCH_IBX(i915) && intel_is_dual_link_lvds(display)))) + (HAS_PCH_IBX(display) && intel_is_dual_link_lvds(display)))) return 25; if (crtc_state->sdvo_tv_clock) @@ -1397,7 +1395,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state, ilk_compute_dpll(crtc_state, &crtc_state->dpll, &crtc_state->dpll); - ret = intel_compute_shared_dplls(state, crtc, NULL); + ret = intel_dpll_compute(state, crtc, NULL); if (ret) return ret; @@ -1407,8 +1405,8 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state, return ret; } -static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state, - struct intel_crtc *crtc) +static int ilk_crtc_get_dpll(struct intel_atomic_state *state, + struct intel_crtc *crtc) { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); @@ -1417,7 +1415,7 @@ static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state, if (!crtc_state->has_pch_encoder) return 0; - return intel_reserve_shared_dplls(state, crtc, NULL); + return intel_dpll_reserve(state, crtc, NULL); } static u32 vlv_dpll(const struct intel_crtc_state *crtc_state) @@ -1693,45 +1691,45 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state, return 0; } -static const struct intel_dpll_funcs mtl_dpll_funcs = { +static const struct intel_dpll_global_funcs mtl_dpll_funcs = { .crtc_compute_clock = mtl_crtc_compute_clock, }; -static const struct intel_dpll_funcs dg2_dpll_funcs = { +static const struct intel_dpll_global_funcs dg2_dpll_funcs = { .crtc_compute_clock = dg2_crtc_compute_clock, }; -static const struct intel_dpll_funcs hsw_dpll_funcs = { +static const struct intel_dpll_global_funcs hsw_dpll_funcs = { .crtc_compute_clock = hsw_crtc_compute_clock, - .crtc_get_shared_dpll = hsw_crtc_get_shared_dpll, + .crtc_get_dpll = hsw_crtc_get_dpll, }; -static const struct intel_dpll_funcs ilk_dpll_funcs = { +static const struct intel_dpll_global_funcs ilk_dpll_funcs = { .crtc_compute_clock = ilk_crtc_compute_clock, - .crtc_get_shared_dpll = ilk_crtc_get_shared_dpll, + .crtc_get_dpll = ilk_crtc_get_dpll, }; -static const struct intel_dpll_funcs chv_dpll_funcs = { +static const struct intel_dpll_global_funcs chv_dpll_funcs = { .crtc_compute_clock = chv_crtc_compute_clock, }; -static const struct intel_dpll_funcs vlv_dpll_funcs = { +static const struct intel_dpll_global_funcs vlv_dpll_funcs = { .crtc_compute_clock = vlv_crtc_compute_clock, }; -static const struct intel_dpll_funcs g4x_dpll_funcs = { +static const struct intel_dpll_global_funcs g4x_dpll_funcs = { .crtc_compute_clock = g4x_crtc_compute_clock, }; -static const struct intel_dpll_funcs pnv_dpll_funcs = { +static const struct intel_dpll_global_funcs pnv_dpll_funcs = { .crtc_compute_clock = pnv_crtc_compute_clock, }; -static const struct intel_dpll_funcs i9xx_dpll_funcs = { +static const struct intel_dpll_global_funcs i9xx_dpll_funcs = { .crtc_compute_clock = i9xx_crtc_compute_clock, }; -static const struct intel_dpll_funcs i8xx_dpll_funcs = { +static const struct intel_dpll_global_funcs i8xx_dpll_funcs = { .crtc_compute_clock = i8xx_crtc_compute_clock, }; @@ -1761,8 +1759,8 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, return 0; } -int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, - struct intel_crtc *crtc) +int intel_dpll_crtc_get_dpll(struct intel_atomic_state *state, + struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = @@ -1770,15 +1768,15 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, int ret; drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state)); - drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->shared_dpll); + drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->intel_dpll); - if (!crtc_state->hw.enable || crtc_state->shared_dpll) + if (!crtc_state->hw.enable || crtc_state->intel_dpll) return 0; - if (!display->funcs.dpll->crtc_get_shared_dpll) + if (!display->funcs.dpll->crtc_get_dpll) return 0; - ret = display->funcs.dpll->crtc_get_shared_dpll(state, crtc); + ret = display->funcs.dpll->crtc_get_dpll(state, crtc); if (ret) { drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n", crtc->base.base.id, crtc->base.name); @@ -1791,15 +1789,13 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, void intel_dpll_init_clock_hook(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - if (DISPLAY_VER(display) >= 14) display->funcs.dpll = &mtl_dpll_funcs; else if (display->platform.dg2) display->funcs.dpll = &dg2_dpll_funcs; else if (DISPLAY_VER(display) >= 9 || HAS_DDI(display)) display->funcs.dpll = &hsw_dpll_funcs; - else if (HAS_PCH_SPLIT(dev_priv)) + else if (HAS_PCH_SPLIT(display)) display->funcs.dpll = &ilk_dpll_funcs; else if (display->platform.cherryview) display->funcs.dpll = &chv_dpll_funcs; @@ -1876,45 +1872,43 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) static void vlv_pllb_recal_opamp(struct intel_display *display, enum dpio_phy phy, enum dpio_channel ch) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 tmp; /* * PLLB opamp always calibrates to max value of 0x3f, force enable it * and set it to a reasonable value instead. */ - tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch)); + tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW17(ch)); tmp &= 0xffffff00; tmp |= 0x00000030; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(ch), tmp); + vlv_dpio_write(display->drm, phy, VLV_PLL_DW17(ch), tmp); - tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11); + tmp = vlv_dpio_read(display->drm, phy, VLV_REF_DW11); tmp &= 0x00ffffff; tmp |= 0x8c000000; - vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp); + vlv_dpio_write(display->drm, phy, VLV_REF_DW11, tmp); - tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch)); + tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW17(ch)); tmp &= 0xffffff00; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(ch), tmp); + vlv_dpio_write(display->drm, phy, VLV_PLL_DW17(ch), tmp); - tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11); + tmp = vlv_dpio_read(display->drm, phy, VLV_REF_DW11); tmp &= 0x00ffffff; tmp |= 0xb0000000; - vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp); + vlv_dpio_write(display->drm, phy, VLV_REF_DW11, tmp); } static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct dpll *clock = &crtc_state->dpll; enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); enum pipe pipe = crtc->pipe; u32 tmp, coreclk; - vlv_dpio_get(dev_priv); + vlv_dpio_get(display->drm); /* See eDP HDMI DPIO driver vbios notes doc */ @@ -1923,15 +1917,15 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) vlv_pllb_recal_opamp(display, phy, ch); /* Set up Tx target for periodic Rcomp update */ - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x0100000f); + vlv_dpio_write(display->drm, phy, VLV_PCS_DW17_BCAST, 0x0100000f); /* Disable target IRef on PLL */ - tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(ch)); + tmp = vlv_dpio_read(display->drm, phy, VLV_PLL_DW16(ch)); tmp &= 0x00ffffff; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(ch), tmp); + vlv_dpio_write(display->drm, phy, VLV_PLL_DW16(ch), tmp); /* Disable fast lock */ - vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610); + vlv_dpio_write(display->drm, phy, VLV_CMN_DW0, 0x610); /* Set idtafcrecal before PLL is enabled */ tmp = DPIO_M1_DIV(clock->m1) | @@ -1947,48 +1941,42 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) * Note: don't use the DAC post divider as it seems unstable. */ tmp |= DPIO_S1_DIV(DPIO_S1_DIV_HDMIDP); - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp); + vlv_dpio_write(display->drm, phy, VLV_PLL_DW3(ch), tmp); tmp |= DPIO_ENABLE_CALIBRATION; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp); + vlv_dpio_write(display->drm, phy, VLV_PLL_DW3(ch), tmp); /* Set HBR and RBR LPF coefficients */ if (crtc_state->port_clock == 162000 || intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) || intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch), - 0x009f0003); + vlv_dpio_write(display->drm, phy, VLV_PLL_DW18(ch), 0x009f0003); else - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch), - 0x00d0000f); + vlv_dpio_write(display->drm, phy, VLV_PLL_DW18(ch), 0x00d0000f); if (intel_crtc_has_dp_encoder(crtc_state)) { /* Use SSC source */ if (pipe == PIPE_A) - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch), - 0x0df40000); + vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df40000); else - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch), - 0x0df70000); + vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df70000); } else { /* HDMI or VGA */ /* Use bend source */ if (pipe == PIPE_A) - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch), - 0x0df70000); + vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df70000); else - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch), - 0x0df40000); + vlv_dpio_write(display->drm, phy, VLV_PLL_DW5(ch), 0x0df40000); } - coreclk = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW7(ch)); + coreclk = vlv_dpio_read(display->drm, phy, VLV_PLL_DW7(ch)); coreclk = (coreclk & 0x0000ff00) | 0x01c00000; if (intel_crtc_has_dp_encoder(crtc_state)) coreclk |= 0x01000000; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW7(ch), coreclk); + vlv_dpio_write(display->drm, phy, VLV_PLL_DW7(ch), coreclk); - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW19(ch), 0x87871000); + vlv_dpio_write(display->drm, phy, VLV_PLL_DW19(ch), 0x87871000); - vlv_dpio_put(dev_priv); + vlv_dpio_put(display->drm); } static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state) @@ -2033,8 +2021,8 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state) static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct dpll *clock = &crtc_state->dpll; enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); @@ -2043,44 +2031,44 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) m2_frac = clock->m2 & 0x3fffff; - vlv_dpio_get(dev_priv); + vlv_dpio_get(display->drm); /* p1 and p2 divider */ - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(ch), + vlv_dpio_write(display->drm, phy, CHV_CMN_DW13(ch), DPIO_CHV_S1_DIV(5) | DPIO_CHV_P1_DIV(clock->p1) | DPIO_CHV_P2_DIV(clock->p2) | DPIO_CHV_K_DIV(1)); /* Feedback post-divider - m2 */ - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(ch), + vlv_dpio_write(display->drm, phy, CHV_PLL_DW0(ch), DPIO_CHV_M2_DIV(clock->m2 >> 22)); /* Feedback refclk divider - n and m1 */ - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(ch), + vlv_dpio_write(display->drm, phy, CHV_PLL_DW1(ch), DPIO_CHV_M1_DIV(DPIO_CHV_M1_DIV_BY_2) | DPIO_CHV_N_DIV(1)); /* M2 fraction division */ - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(ch), + vlv_dpio_write(display->drm, phy, CHV_PLL_DW2(ch), DPIO_CHV_M2_FRAC_DIV(m2_frac)); /* M2 fraction division enable */ - tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch)); + tmp = vlv_dpio_read(display->drm, phy, CHV_PLL_DW3(ch)); tmp &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); tmp |= DPIO_CHV_FEEDFWD_GAIN(2); if (m2_frac) tmp |= DPIO_CHV_FRAC_DIV_EN; - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(ch), tmp); + vlv_dpio_write(display->drm, phy, CHV_PLL_DW3(ch), tmp); /* Program digital lock detect threshold */ - tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(ch)); + tmp = vlv_dpio_read(display->drm, phy, CHV_PLL_DW9(ch)); tmp &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); tmp |= DPIO_CHV_INT_LOCK_THRESHOLD(0x5); if (!m2_frac) tmp |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(ch), tmp); + vlv_dpio_write(display->drm, phy, CHV_PLL_DW9(ch), tmp); /* Loop filter */ if (clock->vco == 5400000) { @@ -2105,40 +2093,39 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) DPIO_CHV_GAIN_CTRL(0x3); tribuf_calcntr = 0; } - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(ch), loopfilter); + vlv_dpio_write(display->drm, phy, CHV_PLL_DW6(ch), loopfilter); - tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(ch)); + tmp = vlv_dpio_read(display->drm, phy, CHV_PLL_DW8(ch)); tmp &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; tmp |= DPIO_CHV_TDC_TARGET_CNT(tribuf_calcntr); - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(ch), tmp); + vlv_dpio_write(display->drm, phy, CHV_PLL_DW8(ch), tmp); /* AFC Recal */ - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch), - vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch)) | + vlv_dpio_write(display->drm, phy, CHV_CMN_DW14(ch), + vlv_dpio_read(display->drm, phy, CHV_CMN_DW14(ch)) | DPIO_AFC_RECAL); - vlv_dpio_put(dev_priv); + vlv_dpio_put(display->drm); } static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); enum pipe pipe = crtc->pipe; u32 tmp; - vlv_dpio_get(dev_priv); + vlv_dpio_get(display->drm); /* Enable back the 10bit clock to display controller */ - tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch)); + tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW14(ch)); tmp |= DPIO_DCLKP_EN; - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch), tmp); + vlv_dpio_write(display->drm, phy, CHV_CMN_DW14(ch), tmp); - vlv_dpio_put(dev_priv); + vlv_dpio_put(display->drm); /* * Need to wait > 100ns between dclkp clock enable bit and PLL enable. @@ -2257,7 +2244,6 @@ void vlv_disable_pll(struct intel_display *display, enum pipe pipe) void chv_disable_pll(struct intel_display *display, enum pipe pipe) { - struct drm_i915_private *dev_priv = to_i915(display->drm); enum dpio_channel ch = vlv_pipe_to_channel(pipe); enum dpio_phy phy = vlv_pipe_to_phy(pipe); u32 val; @@ -2273,14 +2259,14 @@ void chv_disable_pll(struct intel_display *display, enum pipe pipe) intel_de_write(display, DPLL(display, pipe), val); intel_de_posting_read(display, DPLL(display, pipe)); - vlv_dpio_get(dev_priv); + vlv_dpio_get(display->drm); /* Disable 10bit clock to display controller */ - val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch)); + val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW14(ch)); val &= ~DPIO_DCLKP_EN; - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch), val); + vlv_dpio_write(display->drm, phy, CHV_CMN_DW14(ch), val); - vlv_dpio_put(dev_priv); + vlv_dpio_put(display->drm); } void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h index 280e90a57c87..3444a2dd3166 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.h +++ b/drivers/gpu/drm/i915/display/intel_dpll.h @@ -19,8 +19,8 @@ struct intel_dpll_hw_state; void intel_dpll_init_clock_hook(struct intel_display *display); int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, struct intel_crtc *crtc); -int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, - struct intel_crtc *crtc); +int intel_dpll_crtc_get_dpll(struct intel_atomic_state *state, + struct intel_crtc *crtc); int i9xx_calc_dpll_params(int refclk, struct dpll *clock); u32 i9xx_dpll_compute_fp(const struct dpll *dpll); void i9xx_dpll_get_hw_state(struct intel_crtc *crtc, diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 84df41086a89..33e0398120c8 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -24,11 +24,13 @@ #include <linux/math.h> #include <linux/string_helpers.h> +#include <drm/drm_print.h> + #include "bxt_dpio_phy_regs.h" -#include "i915_drv.h" -#include "i915_reg.h" +#include "i915_utils.h" #include "intel_cx0_phy.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dkl_phy.h" #include "intel_dkl_phy_regs.h" @@ -38,6 +40,7 @@ #include "intel_hti.h" #include "intel_mg_phy_regs.h" #include "intel_pch_refclk.h" +#include "intel_step.h" #include "intel_tc.h" /** @@ -49,34 +52,34 @@ * share a PLL if their configurations match. * * This file provides an abstraction over display PLLs. The function - * intel_shared_dpll_init() initializes the PLLs for the given platform. The + * intel_dpll_init() initializes the PLLs for the given platform. The * users of a PLL are tracked and that tracking is integrated with the atomic * modset interface. During an atomic operation, required PLLs can be reserved * for a given CRTC and encoder configuration by calling - * intel_reserve_shared_dplls() and previously reserved PLLs can be released - * with intel_release_shared_dplls(). + * intel_dpll_reserve() and previously reserved PLLs can be released + * with intel_dpll_release(). * Changes to the users are first staged in the atomic state, and then made - * effective by calling intel_shared_dpll_swap_state() during the atomic + * effective by calling intel_dpll_swap_state() during the atomic * commit phase. */ /* platform specific hooks for managing DPLLs */ -struct intel_shared_dpll_funcs { +struct intel_dpll_funcs { /* - * Hook for enabling the pll, called from intel_enable_shared_dpll() if + * Hook for enabling the pll, called from intel_enable_dpll() if * the pll is not already enabled. */ void (*enable)(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state); /* - * Hook for disabling the pll, called from intel_disable_shared_dpll() + * Hook for disabling the pll, called from intel_disable_dpll() * only when it is safe to disable the pll, i.e., there are no more * tracked users for it. */ void (*disable)(struct intel_display *display, - struct intel_shared_dpll *pll); + struct intel_dpll *pll); /* * Hook for reading the values currently programmed to the DPLL @@ -84,7 +87,7 @@ struct intel_shared_dpll_funcs { * verification after a mode set. */ bool (*get_hw_state)(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state); /* @@ -92,7 +95,7 @@ struct intel_shared_dpll_funcs { * in state. */ int (*get_freq)(struct intel_display *i915, - const struct intel_shared_dpll *pll, + const struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state); }; @@ -119,18 +122,18 @@ struct intel_dpll_mgr { static void intel_atomic_duplicate_dpll_state(struct intel_display *display, - struct intel_shared_dpll_state *shared_dpll) + struct intel_dpll_state *dpll_state) { - struct intel_shared_dpll *pll; + struct intel_dpll *pll; int i; - /* Copy shared dpll state */ - for_each_shared_dpll(display, pll, i) - shared_dpll[pll->index] = pll->state; + /* Copy dpll state */ + for_each_dpll(display, pll, i) + dpll_state[pll->index] = pll->state; } -static struct intel_shared_dpll_state * -intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s) +static struct intel_dpll_state * +intel_atomic_get_dpll_state(struct drm_atomic_state *s) { struct intel_atomic_state *state = to_intel_atomic_state(s); struct intel_display *display = to_intel_display(state); @@ -141,28 +144,28 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s) state->dpll_set = true; intel_atomic_duplicate_dpll_state(display, - state->shared_dpll); + state->dpll_state); } - return state->shared_dpll; + return state->dpll_state; } /** - * intel_get_shared_dpll_by_id - get a DPLL given its id + * intel_get_dpll_by_id - get a DPLL given its id * @display: intel_display device instance * @id: pll id * * Returns: * A pointer to the DPLL with @id */ -struct intel_shared_dpll * -intel_get_shared_dpll_by_id(struct intel_display *display, - enum intel_dpll_id id) +struct intel_dpll * +intel_get_dpll_by_id(struct intel_display *display, + enum intel_dpll_id id) { - struct intel_shared_dpll *pll; + struct intel_dpll *pll; int i; - for_each_shared_dpll(display, pll, i) { + for_each_dpll(display, pll, i) { if (pll->info->id == id) return pll; } @@ -172,9 +175,9 @@ intel_get_shared_dpll_by_id(struct intel_display *display, } /* For ILK+ */ -void assert_shared_dpll(struct intel_display *display, - struct intel_shared_dpll *pll, - bool state) +void assert_dpll(struct intel_display *display, + struct intel_dpll *pll, + bool state) { bool cur_state; struct intel_dpll_hw_state hw_state; @@ -202,7 +205,7 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port) static i915_reg_t intel_combo_pll_enable_reg(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll *pll) { if (display->platform.dg1) return DG1_DPLL_ENABLE(pll->info->id); @@ -215,7 +218,7 @@ intel_combo_pll_enable_reg(struct intel_display *display, static i915_reg_t intel_tc_pll_enable_reg(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll *pll) { const enum intel_dpll_id id = pll->info->id; enum tc_port tc_port = icl_pll_id_to_tc_port(id); @@ -227,7 +230,7 @@ intel_tc_pll_enable_reg(struct intel_display *display, } static void _intel_enable_shared_dpll(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll *pll) { if (pll->info->power_domain) pll->wakeref = intel_display_power_get(display, pll->info->power_domain); @@ -237,7 +240,7 @@ static void _intel_enable_shared_dpll(struct intel_display *display, } static void _intel_disable_shared_dpll(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll *pll) { pll->info->funcs->disable(display, pll); pll->on = false; @@ -247,16 +250,16 @@ static void _intel_disable_shared_dpll(struct intel_display *display, } /** - * intel_enable_shared_dpll - enable a CRTC's shared DPLL - * @crtc_state: CRTC, and its state, which has a shared DPLL + * intel_dpll_enable - enable a CRTC's DPLL + * @crtc_state: CRTC, and its state, which has a DPLL * - * Enable the shared DPLL used by @crtc. + * Enable DPLL used by @crtc. */ -void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state) +void intel_dpll_enable(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct intel_shared_dpll *pll = crtc_state->shared_dpll; + struct intel_dpll *pll = crtc_state->intel_dpll; unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state); unsigned int old_mask; @@ -279,7 +282,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state) if (old_mask) { drm_WARN_ON(display->drm, !pll->on); - assert_shared_dpll_enabled(display, pll); + assert_dpll_enabled(display, pll); goto out; } drm_WARN_ON(display->drm, pll->on); @@ -293,16 +296,16 @@ out: } /** - * intel_disable_shared_dpll - disable a CRTC's shared DPLL + * intel_dpll_disable - disable a CRTC's shared DPLL * @crtc_state: CRTC, and its state, which has a shared DPLL * - * Disable the shared DPLL used by @crtc. + * Disable DPLL used by @crtc. */ -void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) +void intel_dpll_disable(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct intel_shared_dpll *pll = crtc_state->shared_dpll; + struct intel_dpll *pll = crtc_state->intel_dpll; unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state); /* PCH only available on ILK+ */ @@ -323,7 +326,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) pll->info->name, pll->active_mask, pll->on, crtc->base.base.id, crtc->base.name); - assert_shared_dpll_enabled(display, pll); + assert_dpll_enabled(display, pll); drm_WARN_ON(display->drm, !pll->on); pll->active_mask &= ~pipe_mask; @@ -341,11 +344,11 @@ out: static unsigned long intel_dpll_mask_all(struct intel_display *display) { - struct intel_shared_dpll *pll; + struct intel_dpll *pll; unsigned long dpll_mask = 0; int i; - for_each_shared_dpll(display, pll, i) { + for_each_dpll(display, pll, i) { drm_WARN_ON(display->drm, dpll_mask & BIT(pll->info->id)); dpll_mask |= BIT(pll->info->id); @@ -354,44 +357,44 @@ intel_dpll_mask_all(struct intel_display *display) return dpll_mask; } -static struct intel_shared_dpll * -intel_find_shared_dpll(struct intel_atomic_state *state, - const struct intel_crtc *crtc, - const struct intel_dpll_hw_state *dpll_hw_state, - unsigned long dpll_mask) +static struct intel_dpll * +intel_find_dpll(struct intel_atomic_state *state, + const struct intel_crtc *crtc, + const struct intel_dpll_hw_state *dpll_hw_state, + unsigned long dpll_mask) { struct intel_display *display = to_intel_display(crtc); unsigned long dpll_mask_all = intel_dpll_mask_all(display); - struct intel_shared_dpll_state *shared_dpll; - struct intel_shared_dpll *unused_pll = NULL; + struct intel_dpll_state *dpll_state; + struct intel_dpll *unused_pll = NULL; enum intel_dpll_id id; - shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); + dpll_state = intel_atomic_get_dpll_state(&state->base); drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all); for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) { - struct intel_shared_dpll *pll; + struct intel_dpll *pll; - pll = intel_get_shared_dpll_by_id(display, id); + pll = intel_get_dpll_by_id(display, id); if (!pll) continue; /* Only want to check enabled timings first */ - if (shared_dpll[pll->index].pipe_mask == 0) { + if (dpll_state[pll->index].pipe_mask == 0) { if (!unused_pll) unused_pll = pll; continue; } if (memcmp(dpll_hw_state, - &shared_dpll[pll->index].hw_state, + &dpll_state[pll->index].hw_state, sizeof(*dpll_hw_state)) == 0) { drm_dbg_kms(display->drm, "[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n", crtc->base.base.id, crtc->base.name, pll->info->name, - shared_dpll[pll->index].pipe_mask, + dpll_state[pll->index].pipe_mask, pll->active_mask); return pll; } @@ -409,76 +412,76 @@ intel_find_shared_dpll(struct intel_atomic_state *state, } /** - * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC + * intel_dpll_crtc_get - Get a DPLL reference for a CRTC * @crtc: CRTC on which behalf the reference is taken * @pll: DPLL for which the reference is taken - * @shared_dpll_state: the DPLL atomic state in which the reference is tracked + * @dpll_state: the DPLL atomic state in which the reference is tracked * * Take a reference for @pll tracking the use of it by @crtc. */ static void -intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc, - const struct intel_shared_dpll *pll, - struct intel_shared_dpll_state *shared_dpll_state) +intel_dpll_crtc_get(const struct intel_crtc *crtc, + const struct intel_dpll *pll, + struct intel_dpll_state *dpll_state) { struct intel_display *display = to_intel_display(crtc); - drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0); + drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) != 0); - shared_dpll_state->pipe_mask |= BIT(crtc->pipe); + dpll_state->pipe_mask |= BIT(crtc->pipe); drm_dbg_kms(display->drm, "[CRTC:%d:%s] reserving %s\n", crtc->base.base.id, crtc->base.name, pll->info->name); } static void -intel_reference_shared_dpll(struct intel_atomic_state *state, - const struct intel_crtc *crtc, - const struct intel_shared_dpll *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +intel_reference_dpll(struct intel_atomic_state *state, + const struct intel_crtc *crtc, + const struct intel_dpll *pll, + const struct intel_dpll_hw_state *dpll_hw_state) { - struct intel_shared_dpll_state *shared_dpll; + struct intel_dpll_state *dpll_state; - shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); + dpll_state = intel_atomic_get_dpll_state(&state->base); - if (shared_dpll[pll->index].pipe_mask == 0) - shared_dpll[pll->index].hw_state = *dpll_hw_state; + if (dpll_state[pll->index].pipe_mask == 0) + dpll_state[pll->index].hw_state = *dpll_hw_state; - intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]); + intel_dpll_crtc_get(crtc, pll, &dpll_state[pll->index]); } /** - * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC + * intel_dpll_crtc_put - Drop a DPLL reference for a CRTC * @crtc: CRTC on which behalf the reference is dropped * @pll: DPLL for which the reference is dropped - * @shared_dpll_state: the DPLL atomic state in which the reference is tracked + * @dpll_state: the DPLL atomic state in which the reference is tracked * * Drop a reference for @pll tracking the end of use of it by @crtc. */ void -intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc, - const struct intel_shared_dpll *pll, - struct intel_shared_dpll_state *shared_dpll_state) +intel_dpll_crtc_put(const struct intel_crtc *crtc, + const struct intel_dpll *pll, + struct intel_dpll_state *dpll_state) { struct intel_display *display = to_intel_display(crtc); - drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0); + drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) == 0); - shared_dpll_state->pipe_mask &= ~BIT(crtc->pipe); + dpll_state->pipe_mask &= ~BIT(crtc->pipe); drm_dbg_kms(display->drm, "[CRTC:%d:%s] releasing %s\n", crtc->base.base.id, crtc->base.name, pll->info->name); } -static void intel_unreference_shared_dpll(struct intel_atomic_state *state, - const struct intel_crtc *crtc, - const struct intel_shared_dpll *pll) +static void intel_unreference_dpll(struct intel_atomic_state *state, + const struct intel_crtc *crtc, + const struct intel_dpll *pll) { - struct intel_shared_dpll_state *shared_dpll; + struct intel_dpll_state *dpll_state; - shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); + dpll_state = intel_atomic_get_dpll_state(&state->base); - intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]); + intel_dpll_crtc_put(crtc, pll, &dpll_state[pll->index]); } static void intel_put_dpll(struct intel_atomic_state *state, @@ -489,16 +492,16 @@ static void intel_put_dpll(struct intel_atomic_state *state, struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - new_crtc_state->shared_dpll = NULL; + new_crtc_state->intel_dpll = NULL; - if (!old_crtc_state->shared_dpll) + if (!old_crtc_state->intel_dpll) return; - intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll); + intel_unreference_dpll(state, crtc, old_crtc_state->intel_dpll); } /** - * intel_shared_dpll_swap_state - make atomic DPLL configuration effective + * intel_dpll_swap_state - make atomic DPLL configuration effective * @state: atomic state * * This is the dpll version of drm_atomic_helper_swap_state() since the @@ -508,22 +511,22 @@ static void intel_put_dpll(struct intel_atomic_state *state, * i.e. it also puts the current state into @state, even though there is no * need for that at this moment. */ -void intel_shared_dpll_swap_state(struct intel_atomic_state *state) +void intel_dpll_swap_state(struct intel_atomic_state *state) { struct intel_display *display = to_intel_display(state); - struct intel_shared_dpll_state *shared_dpll = state->shared_dpll; - struct intel_shared_dpll *pll; + struct intel_dpll_state *dpll_state = state->dpll_state; + struct intel_dpll *pll; int i; if (!state->dpll_set) return; - for_each_shared_dpll(display, pll, i) - swap(pll->state, shared_dpll[pll->index]); + for_each_dpll(display, pll, i) + swap(pll->state, dpll_state[pll->index]); } static bool ibx_pch_dpll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; @@ -559,7 +562,7 @@ static void ibx_assert_pch_refclk_enabled(struct intel_display *display) } static void ibx_pch_dpll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; @@ -588,7 +591,7 @@ static void ibx_pch_dpll_enable(struct intel_display *display, } static void ibx_pch_dpll_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll *pll) { const enum intel_dpll_id id = pll->info->id; @@ -609,36 +612,35 @@ static int ibx_get_dpll(struct intel_atomic_state *state, struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *i915 = to_i915(display->drm); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct intel_shared_dpll *pll; + struct intel_dpll *pll; enum intel_dpll_id id; - if (HAS_PCH_IBX(i915)) { + if (HAS_PCH_IBX(display)) { /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ id = (enum intel_dpll_id) crtc->pipe; - pll = intel_get_shared_dpll_by_id(display, id); + pll = intel_get_dpll_by_id(display, id); drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n", crtc->base.base.id, crtc->base.name, pll->info->name); } else { - pll = intel_find_shared_dpll(state, crtc, - &crtc_state->dpll_hw_state, - BIT(DPLL_ID_PCH_PLL_B) | - BIT(DPLL_ID_PCH_PLL_A)); + pll = intel_find_dpll(state, crtc, + &crtc_state->dpll_hw_state, + BIT(DPLL_ID_PCH_PLL_B) | + BIT(DPLL_ID_PCH_PLL_A)); } if (!pll) return -EINVAL; /* reference the pll */ - intel_reference_shared_dpll(state, crtc, - pll, &crtc_state->dpll_hw_state); + intel_reference_dpll(state, crtc, + pll, &crtc_state->dpll_hw_state); - crtc_state->shared_dpll = pll; + crtc_state->intel_dpll = pll; return 0; } @@ -668,7 +670,7 @@ static bool ibx_compare_hw_state(const struct intel_dpll_hw_state *_a, a->fp1 == b->fp1; } -static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = { +static const struct intel_dpll_funcs ibx_pch_dpll_funcs = { .enable = ibx_pch_dpll_enable, .disable = ibx_pch_dpll_disable, .get_hw_state = ibx_pch_dpll_get_hw_state, @@ -690,7 +692,7 @@ static const struct intel_dpll_mgr pch_pll_mgr = { }; static void hsw_ddi_wrpll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; @@ -702,7 +704,7 @@ static void hsw_ddi_wrpll_enable(struct intel_display *display, } static void hsw_ddi_spll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; @@ -713,7 +715,7 @@ static void hsw_ddi_spll_enable(struct intel_display *display, } static void hsw_ddi_wrpll_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll *pll) { const enum intel_dpll_id id = pll->info->id; @@ -729,7 +731,7 @@ static void hsw_ddi_wrpll_disable(struct intel_display *display, } static void hsw_ddi_spll_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll *pll) { enum intel_dpll_id id = pll->info->id; @@ -745,7 +747,7 @@ static void hsw_ddi_spll_disable(struct intel_display *display, } static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; @@ -767,7 +769,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display, } static bool hsw_ddi_spll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; @@ -994,7 +996,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */, } static int hsw_ddi_wrpll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; @@ -1057,14 +1059,14 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state, return 0; } -static struct intel_shared_dpll * +static struct intel_dpll * hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - return intel_find_shared_dpll(state, crtc, + return intel_find_dpll(state, crtc, &crtc_state->dpll_hw_state, BIT(DPLL_ID_WRPLL2) | BIT(DPLL_ID_WRPLL1)); @@ -1088,11 +1090,11 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state) } } -static struct intel_shared_dpll * +static struct intel_dpll * hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); - struct intel_shared_dpll *pll; + struct intel_dpll *pll; enum intel_dpll_id pll_id; int clock = crtc_state->port_clock; @@ -1111,7 +1113,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state) return NULL; } - pll = intel_get_shared_dpll_by_id(display, pll_id); + pll = intel_get_dpll_by_id(display, pll_id); if (!pll) return NULL; @@ -1120,7 +1122,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state) } static int hsw_ddi_lcpll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { int link_clock = 0; @@ -1160,19 +1162,19 @@ hsw_ddi_spll_compute_dpll(struct intel_atomic_state *state, return 0; } -static struct intel_shared_dpll * +static struct intel_dpll * hsw_ddi_spll_get_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state, + return intel_find_dpll(state, crtc, &crtc_state->dpll_hw_state, BIT(DPLL_ID_SPLL)); } static int hsw_ddi_spll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; @@ -1219,7 +1221,7 @@ static int hsw_get_dpll(struct intel_atomic_state *state, { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct intel_shared_dpll *pll = NULL; + struct intel_dpll *pll = NULL; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) pll = hsw_ddi_wrpll_get_dpll(state, crtc); @@ -1231,10 +1233,10 @@ static int hsw_get_dpll(struct intel_atomic_state *state, if (!pll) return -EINVAL; - intel_reference_shared_dpll(state, crtc, - pll, &crtc_state->dpll_hw_state); + intel_reference_dpll(state, crtc, + pll, &crtc_state->dpll_hw_state); - crtc_state->shared_dpll = pll; + crtc_state->intel_dpll = pll; return 0; } @@ -1268,14 +1270,14 @@ static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *_a, a->spll == b->spll; } -static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = { +static const struct intel_dpll_funcs hsw_ddi_wrpll_funcs = { .enable = hsw_ddi_wrpll_enable, .disable = hsw_ddi_wrpll_disable, .get_hw_state = hsw_ddi_wrpll_get_hw_state, .get_freq = hsw_ddi_wrpll_get_freq, }; -static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = { +static const struct intel_dpll_funcs hsw_ddi_spll_funcs = { .enable = hsw_ddi_spll_enable, .disable = hsw_ddi_spll_disable, .get_hw_state = hsw_ddi_spll_get_hw_state, @@ -1283,24 +1285,24 @@ static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = { }; static void hsw_ddi_lcpll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, const struct intel_dpll_hw_state *hw_state) { } static void hsw_ddi_lcpll_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll *pll) { } static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { return true; } -static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = { +static const struct intel_dpll_funcs hsw_ddi_lcpll_funcs = { .enable = hsw_ddi_lcpll_enable, .disable = hsw_ddi_lcpll_disable, .get_hw_state = hsw_ddi_lcpll_get_hw_state, @@ -1362,7 +1364,7 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = { }; static void skl_ddi_pll_write_ctrl1(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, const struct skl_dpll_hw_state *hw_state) { const enum intel_dpll_id id = pll->info->id; @@ -1376,7 +1378,7 @@ static void skl_ddi_pll_write_ctrl1(struct intel_display *display, } static void skl_ddi_pll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; @@ -1398,7 +1400,7 @@ static void skl_ddi_pll_enable(struct intel_display *display, } static void skl_ddi_dpll0_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; @@ -1407,7 +1409,7 @@ static void skl_ddi_dpll0_enable(struct intel_display *display, } static void skl_ddi_pll_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll *pll) { const struct skl_dpll_regs *regs = skl_dpll_regs; const enum intel_dpll_id id = pll->info->id; @@ -1418,12 +1420,12 @@ static void skl_ddi_pll_disable(struct intel_display *display, } static void skl_ddi_dpll0_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll *pll) { } static bool skl_ddi_pll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; @@ -1461,7 +1463,7 @@ out: } static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; @@ -1734,7 +1736,7 @@ skip_remaining_dividers: } static int skl_ddi_wrpll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; @@ -1882,7 +1884,7 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) } static int skl_ddi_lcpll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; @@ -1937,31 +1939,31 @@ static int skl_get_dpll(struct intel_atomic_state *state, { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct intel_shared_dpll *pll; + struct intel_dpll *pll; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) - pll = intel_find_shared_dpll(state, crtc, - &crtc_state->dpll_hw_state, - BIT(DPLL_ID_SKL_DPLL0)); + pll = intel_find_dpll(state, crtc, + &crtc_state->dpll_hw_state, + BIT(DPLL_ID_SKL_DPLL0)); else - pll = intel_find_shared_dpll(state, crtc, - &crtc_state->dpll_hw_state, - BIT(DPLL_ID_SKL_DPLL3) | - BIT(DPLL_ID_SKL_DPLL2) | - BIT(DPLL_ID_SKL_DPLL1)); + pll = intel_find_dpll(state, crtc, + &crtc_state->dpll_hw_state, + BIT(DPLL_ID_SKL_DPLL3) | + BIT(DPLL_ID_SKL_DPLL2) | + BIT(DPLL_ID_SKL_DPLL1)); if (!pll) return -EINVAL; - intel_reference_shared_dpll(state, crtc, - pll, &crtc_state->dpll_hw_state); + intel_reference_dpll(state, crtc, + pll, &crtc_state->dpll_hw_state); - crtc_state->shared_dpll = pll; + crtc_state->intel_dpll = pll; return 0; } static int skl_ddi_pll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; @@ -2002,14 +2004,14 @@ static bool skl_compare_hw_state(const struct intel_dpll_hw_state *_a, a->cfgcr2 == b->cfgcr2; } -static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = { +static const struct intel_dpll_funcs skl_ddi_pll_funcs = { .enable = skl_ddi_pll_enable, .disable = skl_ddi_pll_disable, .get_hw_state = skl_ddi_pll_get_hw_state, .get_freq = skl_ddi_pll_get_freq, }; -static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = { +static const struct intel_dpll_funcs skl_ddi_dpll0_funcs = { .enable = skl_ddi_dpll0_enable, .disable = skl_ddi_dpll0_disable, .get_hw_state = skl_ddi_dpll0_get_hw_state, @@ -2036,7 +2038,7 @@ static const struct intel_dpll_mgr skl_pll_mgr = { }; static void bxt_ddi_pll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; @@ -2139,7 +2141,7 @@ static void bxt_ddi_pll_enable(struct intel_display *display, } static void bxt_ddi_pll_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll *pll) { enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ @@ -2158,7 +2160,7 @@ static void bxt_ddi_pll_disable(struct intel_display *display, } static bool bxt_ddi_pll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; @@ -2358,7 +2360,7 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state, } static int bxt_ddi_pll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; @@ -2427,20 +2429,20 @@ static int bxt_get_dpll(struct intel_atomic_state *state, struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct intel_shared_dpll *pll; + struct intel_dpll *pll; enum intel_dpll_id id; /* 1:1 mapping between ports and PLLs */ id = (enum intel_dpll_id) encoder->port; - pll = intel_get_shared_dpll_by_id(display, id); + pll = intel_get_dpll_by_id(display, id); drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n", crtc->base.base.id, crtc->base.name, pll->info->name); - intel_reference_shared_dpll(state, crtc, - pll, &crtc_state->dpll_hw_state); + intel_reference_dpll(state, crtc, + pll, &crtc_state->dpll_hw_state); - crtc_state->shared_dpll = pll; + crtc_state->intel_dpll = pll; return 0; } @@ -2484,7 +2486,7 @@ static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *_a, a->pcsdw12 == b->pcsdw12; } -static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = { +static const struct intel_dpll_funcs bxt_ddi_pll_funcs = { .enable = bxt_ddi_pll_enable, .disable = bxt_ddi_pll_disable, .get_hw_state = bxt_ddi_pll_get_hw_state, @@ -2753,7 +2755,7 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, } static int icl_ddi_tbt_pll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { /* @@ -2824,7 +2826,7 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state, } static int icl_ddi_combo_pll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; @@ -3197,7 +3199,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, } static int icl_ddi_mg_pll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; @@ -3283,7 +3285,7 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; - crtc_state->shared_dpll = port_dpll->pll; + crtc_state->intel_dpll = port_dpll->pll; crtc_state->dpll_hw_state = port_dpll->hw_state; } @@ -3386,14 +3388,14 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state, /* Eliminate DPLLs from consideration if reserved by HTI */ dpll_mask &= ~intel_hti_dpll_mask(display); - port_dpll->pll = intel_find_shared_dpll(state, crtc, - &port_dpll->hw_state, - dpll_mask); + port_dpll->pll = intel_find_dpll(state, crtc, + &port_dpll->hw_state, + dpll_mask); if (!port_dpll->pll) return -EINVAL; - intel_reference_shared_dpll(state, crtc, - port_dpll->pll, &port_dpll->hw_state); + intel_reference_dpll(state, crtc, + port_dpll->pll, &port_dpll->hw_state); icl_update_active_dpll(state, crtc, encoder); @@ -3426,8 +3428,8 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state, return ret; /* this is mainly for the fastset check */ - if (old_crtc_state->shared_dpll && - old_crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL) + if (old_crtc_state->intel_dpll && + old_crtc_state->intel_dpll->info->id == DPLL_ID_ICL_TBTPLL) icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT); else icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY); @@ -3450,26 +3452,25 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state, int ret; port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; - port_dpll->pll = intel_find_shared_dpll(state, crtc, - &port_dpll->hw_state, - BIT(DPLL_ID_ICL_TBTPLL)); + port_dpll->pll = intel_find_dpll(state, crtc, + &port_dpll->hw_state, + BIT(DPLL_ID_ICL_TBTPLL)); if (!port_dpll->pll) return -EINVAL; - intel_reference_shared_dpll(state, crtc, - port_dpll->pll, &port_dpll->hw_state); - + intel_reference_dpll(state, crtc, + port_dpll->pll, &port_dpll->hw_state); port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; dpll_id = icl_tc_port_to_pll_id(intel_encoder_to_tc(encoder)); - port_dpll->pll = intel_find_shared_dpll(state, crtc, - &port_dpll->hw_state, - BIT(dpll_id)); + port_dpll->pll = intel_find_dpll(state, crtc, + &port_dpll->hw_state, + BIT(dpll_id)); if (!port_dpll->pll) { ret = -EINVAL; goto err_unreference_tbt_pll; } - intel_reference_shared_dpll(state, crtc, - port_dpll->pll, &port_dpll->hw_state); + intel_reference_dpll(state, crtc, + port_dpll->pll, &port_dpll->hw_state); icl_update_active_dpll(state, crtc, encoder); @@ -3477,7 +3478,7 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state, err_unreference_tbt_pll: port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; - intel_unreference_shared_dpll(state, crtc, port_dpll->pll); + intel_unreference_dpll(state, crtc, port_dpll->pll); return ret; } @@ -3519,7 +3520,7 @@ static void icl_put_dplls(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum icl_port_dpll_id id; - new_crtc_state->shared_dpll = NULL; + new_crtc_state->intel_dpll = NULL; for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) { const struct icl_port_dpll *old_port_dpll = @@ -3532,12 +3533,12 @@ static void icl_put_dplls(struct intel_atomic_state *state, if (!old_port_dpll->pll) continue; - intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll); + intel_unreference_dpll(state, crtc, old_port_dpll->pll); } } static bool mg_pll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; @@ -3604,7 +3605,7 @@ out: } static bool dkl_pll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; @@ -3676,7 +3677,7 @@ out: } static bool icl_pll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state, i915_reg_t enable_reg) { @@ -3737,7 +3738,7 @@ out: } static bool combo_pll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); @@ -3746,14 +3747,14 @@ static bool combo_pll_get_hw_state(struct intel_display *display, } static bool tbt_pll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE); } static void icl_dpll_write(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, const struct icl_dpll_hw_state *hw_state) { const enum intel_dpll_id id = pll->info->id; @@ -3795,7 +3796,7 @@ static void icl_dpll_write(struct intel_display *display, } static void icl_mg_pll_write(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, const struct icl_dpll_hw_state *hw_state) { enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id); @@ -3838,7 +3839,7 @@ static void icl_mg_pll_write(struct intel_display *display, } static void dkl_pll_write(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, const struct icl_dpll_hw_state *hw_state) { enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id); @@ -3903,7 +3904,7 @@ static void dkl_pll_write(struct intel_display *display, } static void icl_pll_power_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, i915_reg_t enable_reg) { intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE); @@ -3918,7 +3919,7 @@ static void icl_pll_power_enable(struct intel_display *display, } static void icl_pll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, i915_reg_t enable_reg) { intel_de_rmw(display, enable_reg, 0, PLL_ENABLE); @@ -3928,7 +3929,7 @@ static void icl_pll_enable(struct intel_display *display, drm_err(display->drm, "PLL %d not locked\n", pll->info->id); } -static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_shared_dpll *pll) +static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_dpll *pll) { u32 val; @@ -3953,7 +3954,7 @@ static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct inte } static void combo_pll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; @@ -3977,7 +3978,7 @@ static void combo_pll_enable(struct intel_display *display, } static void tbt_pll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; @@ -3998,7 +3999,7 @@ static void tbt_pll_enable(struct intel_display *display, } static void mg_pll_enable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; @@ -4023,7 +4024,7 @@ static void mg_pll_enable(struct intel_display *display, } static void icl_pll_disable(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, i915_reg_t enable_reg) { /* The first steps are done by intel_ddi_post_disable(). */ @@ -4054,7 +4055,7 @@ static void icl_pll_disable(struct intel_display *display, } static void combo_pll_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll *pll) { i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); @@ -4062,13 +4063,13 @@ static void combo_pll_disable(struct intel_display *display, } static void tbt_pll_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll *pll) { icl_pll_disable(display, pll, TBT_PLL_ENABLE); } static void mg_pll_disable(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll *pll) { i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll); @@ -4127,21 +4128,21 @@ static bool icl_compare_hw_state(const struct intel_dpll_hw_state *_a, a->mg_pll_tdc_coldst_bias == b->mg_pll_tdc_coldst_bias; } -static const struct intel_shared_dpll_funcs combo_pll_funcs = { +static const struct intel_dpll_funcs combo_pll_funcs = { .enable = combo_pll_enable, .disable = combo_pll_disable, .get_hw_state = combo_pll_get_hw_state, .get_freq = icl_ddi_combo_pll_get_freq, }; -static const struct intel_shared_dpll_funcs tbt_pll_funcs = { +static const struct intel_dpll_funcs tbt_pll_funcs = { .enable = tbt_pll_enable, .disable = tbt_pll_disable, .get_hw_state = tbt_pll_get_hw_state, .get_freq = icl_ddi_tbt_pll_get_freq, }; -static const struct intel_shared_dpll_funcs mg_pll_funcs = { +static const struct intel_dpll_funcs mg_pll_funcs = { .enable = mg_pll_enable, .disable = mg_pll_disable, .get_hw_state = mg_pll_get_hw_state, @@ -4189,7 +4190,7 @@ static const struct intel_dpll_mgr ehl_pll_mgr = { .compare_hw_state = icl_compare_hw_state, }; -static const struct intel_shared_dpll_funcs dkl_pll_funcs = { +static const struct intel_dpll_funcs dkl_pll_funcs = { .enable = mg_pll_enable, .disable = mg_pll_disable, .get_hw_state = dkl_pll_get_hw_state, @@ -4298,14 +4299,13 @@ static const struct intel_dpll_mgr adlp_pll_mgr = { }; /** - * intel_shared_dpll_init - Initialize shared DPLLs + * intel_dpll_init - Initialize DPLLs * @display: intel_display device * - * Initialize shared DPLLs for @display. + * Initialize DPLLs for @display. */ -void intel_shared_dpll_init(struct intel_display *display) +void intel_dpll_init(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); const struct intel_dpll_mgr *dpll_mgr = NULL; const struct dpll_info *dpll_info; int i; @@ -4335,7 +4335,7 @@ void intel_shared_dpll_init(struct intel_display *display) dpll_mgr = &skl_pll_mgr; else if (HAS_DDI(display)) dpll_mgr = &hsw_pll_mgr; - else if (HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915)) + else if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) dpll_mgr = &pch_pll_mgr; if (!dpll_mgr) @@ -4345,23 +4345,23 @@ void intel_shared_dpll_init(struct intel_display *display) for (i = 0; dpll_info[i].name; i++) { if (drm_WARN_ON(display->drm, - i >= ARRAY_SIZE(display->dpll.shared_dplls))) + i >= ARRAY_SIZE(display->dpll.dplls))) break; /* must fit into unsigned long bitmask on 32bit */ if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32)) break; - display->dpll.shared_dplls[i].info = &dpll_info[i]; - display->dpll.shared_dplls[i].index = i; + display->dpll.dplls[i].info = &dpll_info[i]; + display->dpll.dplls[i].index = i; } display->dpll.mgr = dpll_mgr; - display->dpll.num_shared_dpll = i; + display->dpll.num_dpll = i; } /** - * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination + * intel_dpll_compute - compute DPLL state CRTC and encoder combination * @state: atomic state * @crtc: CRTC to compute DPLLs for * @encoder: encoder @@ -4369,14 +4369,14 @@ void intel_shared_dpll_init(struct intel_display *display) * This function computes the DPLL state for the given CRTC and encoder. * * The new configuration in the atomic commit @state is made effective by - * calling intel_shared_dpll_swap_state(). + * calling intel_dpll_swap_state(). * * Returns: * 0 on success, negative error code on failure. */ -int intel_compute_shared_dplls(struct intel_atomic_state *state, - struct intel_crtc *crtc, - struct intel_encoder *encoder) +int intel_dpll_compute(struct intel_atomic_state *state, + struct intel_crtc *crtc, + struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(state); const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr; @@ -4388,7 +4388,7 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state, } /** - * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination + * intel_dpll_reserve - reserve DPLLs for CRTC and encoder combination * @state: atomic state * @crtc: CRTC to reserve DPLLs for * @encoder: encoder @@ -4398,18 +4398,18 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state, * state. * * The new configuration in the atomic commit @state is made effective by - * calling intel_shared_dpll_swap_state(). + * calling intel_dpll_swap_state(). * * The reserved DPLLs should be released by calling - * intel_release_shared_dplls(). + * intel_dpll_release(). * * Returns: * 0 if all required DPLLs were successfully reserved, * negative error code otherwise. */ -int intel_reserve_shared_dplls(struct intel_atomic_state *state, - struct intel_crtc *crtc, - struct intel_encoder *encoder) +int intel_dpll_reserve(struct intel_atomic_state *state, + struct intel_crtc *crtc, + struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(state); const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr; @@ -4421,18 +4421,18 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state, } /** - * intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state + * intel_dpll_release - end use of DPLLs by CRTC in atomic state * @state: atomic state * @crtc: crtc from which the DPLLs are to be released * - * This function releases all DPLLs reserved by intel_reserve_shared_dplls() + * This function releases all DPLLs reserved by intel_dpll_reserve() * from the current atomic commit @state and the old @crtc atomic state. * * The new configuration in the atomic commit @state is made effective by - * calling intel_shared_dpll_swap_state(). + * calling intel_dpll_swap_state(). */ -void intel_release_shared_dplls(struct intel_atomic_state *state, - struct intel_crtc *crtc) +void intel_dpll_release(struct intel_atomic_state *state, + struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr; @@ -4440,7 +4440,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state, /* * FIXME: this function is called for every platform having a * compute_clock hook, even though the platform doesn't yet support - * the shared DPLL framework and intel_reserve_shared_dplls() is not + * the DPLL framework and intel_dpll_reserve() is not * called on those. */ if (!dpll_mgr) @@ -4450,16 +4450,16 @@ void intel_release_shared_dplls(struct intel_atomic_state *state, } /** - * intel_update_active_dpll - update the active DPLL for a CRTC/encoder + * intel_dpll_update_active - update the active DPLL for a CRTC/encoder * @state: atomic state * @crtc: the CRTC for which to update the active DPLL * @encoder: encoder determining the type of port DPLL * * Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state, - * from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The + * from the port DPLLs reserved previously by intel_dpll_reserve(). The * DPLL selected will be based on the current mode of the encoder's port. */ -void intel_update_active_dpll(struct intel_atomic_state *state, +void intel_dpll_update_active(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { @@ -4481,7 +4481,7 @@ void intel_update_active_dpll(struct intel_atomic_state *state, * Return the output frequency corresponding to @pll's passed in @dpll_hw_state. */ int intel_dpll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq)) @@ -4499,14 +4499,14 @@ int intel_dpll_get_freq(struct intel_display *display, * Read out @pll's hardware state into @dpll_hw_state. */ bool intel_dpll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state); } static void readout_dpll_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll *pll) { struct intel_crtc *crtc; @@ -4520,8 +4520,8 @@ static void readout_dpll_hw_state(struct intel_display *display, struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); - if (crtc_state->hw.active && crtc_state->shared_dpll == pll) - intel_reference_shared_dpll_crtc(crtc, pll, &pll->state); + if (crtc_state->hw.active && crtc_state->intel_dpll == pll) + intel_dpll_crtc_get(crtc, pll, &pll->state); } pll->active_mask = pll->state.pipe_mask; @@ -4538,15 +4538,15 @@ void intel_dpll_update_ref_clks(struct intel_display *display) void intel_dpll_readout_hw_state(struct intel_display *display) { - struct intel_shared_dpll *pll; + struct intel_dpll *pll; int i; - for_each_shared_dpll(display, pll, i) + for_each_dpll(display, pll, i) readout_dpll_hw_state(display, pll); } static void sanitize_dpll_state(struct intel_display *display, - struct intel_shared_dpll *pll) + struct intel_dpll *pll) { if (!pll->on) return; @@ -4565,12 +4565,12 @@ static void sanitize_dpll_state(struct intel_display *display, void intel_dpll_sanitize_state(struct intel_display *display) { - struct intel_shared_dpll *pll; + struct intel_dpll *pll; int i; intel_cx0_pll_power_save_wa(display); - for_each_shared_dpll(display, pll, i) + for_each_dpll(display, pll, i) sanitize_dpll_state(display, pll); } @@ -4622,7 +4622,7 @@ bool intel_dpll_compare_hw_state(struct intel_display *display, static void verify_single_dpll_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, struct intel_crtc *crtc, const struct intel_crtc_state *new_crtc_state) { @@ -4675,15 +4675,15 @@ verify_single_dpll_state(struct intel_display *display, pll->info->name); } -static bool has_alt_port_dpll(const struct intel_shared_dpll *old_pll, - const struct intel_shared_dpll *new_pll) +static bool has_alt_port_dpll(const struct intel_dpll *old_pll, + const struct intel_dpll *new_pll) { return old_pll && new_pll && old_pll != new_pll && (old_pll->info->is_alt_port_dpll || new_pll->info->is_alt_port_dpll); } -void intel_shared_dpll_state_verify(struct intel_atomic_state *state, - struct intel_crtc *crtc) +void intel_dpll_state_verify(struct intel_atomic_state *state, + struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *old_crtc_state = @@ -4691,34 +4691,34 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state, const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - if (new_crtc_state->shared_dpll) - verify_single_dpll_state(display, new_crtc_state->shared_dpll, + if (new_crtc_state->intel_dpll) + verify_single_dpll_state(display, new_crtc_state->intel_dpll, crtc, new_crtc_state); - if (old_crtc_state->shared_dpll && - old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) { + if (old_crtc_state->intel_dpll && + old_crtc_state->intel_dpll != new_crtc_state->intel_dpll) { u8 pipe_mask = BIT(crtc->pipe); - struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; + struct intel_dpll *pll = old_crtc_state->intel_dpll; INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask, "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", pll->info->name, pipe_name(crtc->pipe), pll->active_mask); /* TC ports have both MG/TC and TBT PLL referenced simultaneously */ - INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->shared_dpll, - new_crtc_state->shared_dpll) && + INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->intel_dpll, + new_crtc_state->intel_dpll) && pll->state.pipe_mask & pipe_mask, "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n", pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask); } } -void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state) +void intel_dpll_verify_disabled(struct intel_atomic_state *state) { struct intel_display *display = to_intel_display(state); - struct intel_shared_dpll *pll; + struct intel_dpll *pll; int i; - for_each_shared_dpll(display, pll, i) + for_each_dpll(display, pll, i) verify_single_dpll_state(display, pll, NULL, NULL); } diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index caffb084830c..f131bdd1c975 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -30,18 +30,18 @@ #include "intel_display_power.h" #include "intel_wakeref.h" -#define for_each_shared_dpll(__display, __pll, __i) \ - for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \ - ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++) +#define for_each_dpll(__display, __pll, __i) \ + for ((__i) = 0; (__i) < (__display)->dpll.num_dpll && \ + ((__pll) = &(__display)->dpll.dplls[(__i)]) ; (__i)++) enum tc_port; struct drm_printer; struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; +struct intel_dpll_funcs; struct intel_encoder; struct intel_shared_dpll; -struct intel_shared_dpll_funcs; /** * enum intel_dpll_id - possible DPLL ids @@ -280,7 +280,7 @@ struct intel_dpll_hw_state { }; /** - * struct intel_shared_dpll_state - hold the DPLL atomic state + * struct intel_dpll_state - hold the DPLL atomic state * * This structure holds an atomic state for the DPLL, that can represent * either its current state (in struct &intel_shared_dpll) or a desired @@ -289,7 +289,7 @@ struct intel_dpll_hw_state { * * See also intel_reserve_shared_dplls() and intel_release_shared_dplls(). */ -struct intel_shared_dpll_state { +struct intel_dpll_state { /** * @pipe_mask: mask of pipes using this DPLL, active or not */ @@ -314,7 +314,7 @@ struct dpll_info { /** * @funcs: platform specific hooks */ - const struct intel_shared_dpll_funcs *funcs; + const struct intel_dpll_funcs *funcs; /** * @id: unique identifier for this DPLL @@ -344,16 +344,16 @@ struct dpll_info { }; /** - * struct intel_shared_dpll - display PLL with tracked state and users + * struct intel_dpll - display PLL with tracked state and users */ -struct intel_shared_dpll { +struct intel_dpll { /** * @state: * * Store the state for the pll, including its hw state * and CRTCs using it. */ - struct intel_shared_dpll_state state; + struct intel_dpll_state state; /** * @index: index for atomic state @@ -387,41 +387,41 @@ struct intel_shared_dpll { #define SKL_DPLL2 2 #define SKL_DPLL3 3 -/* shared dpll functions */ -struct intel_shared_dpll * -intel_get_shared_dpll_by_id(struct intel_display *display, - enum intel_dpll_id id); -void assert_shared_dpll(struct intel_display *display, - struct intel_shared_dpll *pll, - bool state); -#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) -#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) -int intel_compute_shared_dplls(struct intel_atomic_state *state, - struct intel_crtc *crtc, - struct intel_encoder *encoder); -int intel_reserve_shared_dplls(struct intel_atomic_state *state, - struct intel_crtc *crtc, - struct intel_encoder *encoder); -void intel_release_shared_dplls(struct intel_atomic_state *state, - struct intel_crtc *crtc); -void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc, - const struct intel_shared_dpll *pll, - struct intel_shared_dpll_state *shared_dpll_state); +/* dpll functions */ +struct intel_dpll * +intel_get_dpll_by_id(struct intel_display *display, + enum intel_dpll_id id); +void assert_dpll(struct intel_display *display, + struct intel_dpll *pll, + bool state); +#define assert_dpll_enabled(d, p) assert_dpll(d, p, true) +#define assert_dpll_disabled(d, p) assert_dpll(d, p, false) +int intel_dpll_compute(struct intel_atomic_state *state, + struct intel_crtc *crtc, + struct intel_encoder *encoder); +int intel_dpll_reserve(struct intel_atomic_state *state, + struct intel_crtc *crtc, + struct intel_encoder *encoder); +void intel_dpll_release(struct intel_atomic_state *state, + struct intel_crtc *crtc); +void intel_dpll_crtc_put(const struct intel_crtc *crtc, + const struct intel_dpll *pll, + struct intel_dpll_state *shared_dpll_state); void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, enum icl_port_dpll_id port_dpll_id); -void intel_update_active_dpll(struct intel_atomic_state *state, +void intel_dpll_update_active(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder); int intel_dpll_get_freq(struct intel_display *display, - const struct intel_shared_dpll *pll, + const struct intel_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state); bool intel_dpll_get_hw_state(struct intel_display *display, - struct intel_shared_dpll *pll, + struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state); -void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state); -void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state); -void intel_shared_dpll_swap_state(struct intel_atomic_state *state); -void intel_shared_dpll_init(struct intel_display *display); +void intel_dpll_enable(const struct intel_crtc_state *crtc_state); +void intel_dpll_disable(const struct intel_crtc_state *crtc_state); +void intel_dpll_swap_state(struct intel_atomic_state *state); +void intel_dpll_init(struct intel_display *display); void intel_dpll_update_ref_clks(struct intel_display *display); void intel_dpll_readout_hw_state(struct intel_display *display); void intel_dpll_sanitize_state(struct intel_display *display); @@ -435,8 +435,8 @@ bool intel_dpll_compare_hw_state(struct intel_display *display, enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port); bool intel_dpll_is_combophy(enum intel_dpll_id id); -void intel_shared_dpll_state_verify(struct intel_atomic_state *state, - struct intel_crtc *crtc); -void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state); +void intel_dpll_state_verify(struct intel_atomic_state *state, + struct intel_crtc *crtc); +void intel_dpll_verify_disabled(struct intel_atomic_state *state); #endif /* _INTEL_DPLL_MGR_H_ */ diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c b/drivers/gpu/drm/i915/display/intel_dpt.c index 43bd97e4f589..aea249e2699f 100644 --- a/drivers/gpu/drm/i915/display/intel_dpt.c +++ b/drivers/gpu/drm/i915/display/intel_dpt.c @@ -9,6 +9,7 @@ #include "gt/gen8_ppgtt.h" #include "i915_drv.h" +#include "intel_display_core.h" #include "intel_display_rpm.h" #include "intel_display_types.h" #include "intel_dpt.h" @@ -126,7 +127,7 @@ struct i915_vma *intel_dpt_pin_to_ggtt(struct i915_address_space *vm, unsigned int alignment) { struct drm_i915_private *i915 = vm->i915; - struct intel_display *display = &i915->display; + struct intel_display *display = i915->display; struct i915_dpt *dpt = i915_vm_to_dpt(vm); struct ref_tracker *wakeref; struct i915_vma *vma; diff --git a/drivers/gpu/drm/i915/display/intel_dpt_common.c b/drivers/gpu/drm/i915/display/intel_dpt_common.c index d2dede0a5229..5eb88d51dba1 100644 --- a/drivers/gpu/drm/i915/display/intel_dpt_common.c +++ b/drivers/gpu/drm/i915/display/intel_dpt_common.c @@ -3,18 +3,17 @@ * Copyright © 2023 Intel Corporation */ -#include "i915_drv.h" -#include "i915_reg.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dpt_common.h" #include "skl_universal_plane_regs.h" void intel_dpt_configure(struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); - if (DISPLAY_VER(i915) == 14) { + if (DISPLAY_VER(display) == 14) { enum pipe pipe = crtc->pipe; enum plane_id plane_id; @@ -22,15 +21,15 @@ void intel_dpt_configure(struct intel_crtc *crtc) if (plane_id == PLANE_CURSOR) continue; - intel_de_rmw(i915, PLANE_CHICKEN(pipe, plane_id), + intel_de_rmw(display, PLANE_CHICKEN(pipe, plane_id), PLANE_CHICKEN_DISABLE_DPT, - i915->display.params.enable_dpt ? 0 : + display->params.enable_dpt ? 0 : PLANE_CHICKEN_DISABLE_DPT); } - } else if (DISPLAY_VER(i915) == 13) { - intel_de_rmw(i915, CHICKEN_MISC_2, + } else if (DISPLAY_VER(display) == 13) { + intel_de_rmw(display, CHICKEN_MISC_2, CHICKEN_MISC_DISABLE_DPT, - i915->display.params.enable_dpt ? 0 : + display->params.enable_dpt ? 0 : CHICKEN_MISC_DISABLE_DPT); } } diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c index 05cd0f6e6d71..3fa94510458d 100644 --- a/drivers/gpu/drm/i915/display/intel_drrs.c +++ b/drivers/gpu/drm/i915/display/intel_drrs.c @@ -6,9 +6,9 @@ #include <linux/debugfs.h> #include "i915_drv.h" -#include "i915_reg.h" #include "intel_atomic.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_drrs.h" #include "intel_frontbuffer.h" diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 72fe390c5af2..53d8ae3a70e9 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -4,13 +4,13 @@ * */ +#include <drm/drm_print.h> #include <drm/drm_vblank.h> -#include "i915_drv.h" -#include "i915_irq.h" -#include "i915_reg.h" +#include "i915_utils.h" #include "intel_crtc.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_rpm.h" #include "intel_display_types.h" #include "intel_dsb.h" @@ -93,6 +93,10 @@ struct intel_dsb { /* see DSB_REG_VALUE_MASK */ #define DSB_OPCODE_POLL 0xA /* see DSB_REG_VALUE_MASK */ +#define DSB_OPCODE_GOSUB 0xC /* ptl+ */ +#define DSB_GOSUB_HEAD_SHIFT 26 +#define DSB_GOSUB_TAIL_SHIFT 0 +#define DSB_GOSUB_CONVERT_ADDR(x) ((x) >> 6) static bool pre_commit_is_vrr_active(struct intel_atomic_state *state, struct intel_crtc *crtc) @@ -204,6 +208,15 @@ static bool assert_dsb_has_room(struct intel_dsb *dsb) crtc->base.base.id, crtc->base.name, dsb->id); } +static bool assert_dsb_tail_is_aligned(struct intel_dsb *dsb) +{ + struct intel_crtc *crtc = dsb->crtc; + struct intel_display *display = to_intel_display(crtc->base.dev); + + return !drm_WARN_ON(display->drm, + !IS_ALIGNED(dsb->free_pos * 4, CACHELINE_BYTES)); +} + static void intel_dsb_dump(struct intel_dsb *dsb) { struct intel_crtc *crtc = dsb->crtc; @@ -228,13 +241,40 @@ static bool is_dsb_busy(struct intel_display *display, enum pipe pipe, return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY; } +unsigned int intel_dsb_size(struct intel_dsb *dsb) +{ + return dsb->free_pos * 4; +} + +unsigned int intel_dsb_head(struct intel_dsb *dsb) +{ + return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf); +} + +static unsigned int intel_dsb_tail(struct intel_dsb *dsb) +{ + return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + intel_dsb_size(dsb); +} + +static void intel_dsb_ins_align(struct intel_dsb *dsb) +{ + /* + * Every instruction should be 8 byte aligned. + * + * The only way to get unaligned free_pos is via + * intel_dsb_reg_write_indexed() which already + * makes sure the next dword is zeroed, so no need + * to clear it here. + */ + dsb->free_pos = ALIGN(dsb->free_pos, 2); +} + static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw) { if (!assert_dsb_has_room(dsb)) return; - /* Every instruction should be 8 byte aligned. */ - dsb->free_pos = ALIGN(dsb->free_pos, 2); + intel_dsb_ins_align(dsb); dsb->ins_start_offset = dsb->free_pos; dsb->ins[0] = ldw; @@ -492,6 +532,8 @@ static void intel_dsb_align_tail(struct intel_dsb *dsb) { u32 aligned_tail, tail; + intel_dsb_ins_align(dsb); + tail = dsb->free_pos * 4; aligned_tail = ALIGN(tail, CACHELINE_BYTES); @@ -502,20 +544,90 @@ static void intel_dsb_align_tail(struct intel_dsb *dsb) dsb->free_pos = aligned_tail / 4; } -void intel_dsb_finish(struct intel_dsb *dsb) +static void intel_dsb_gosub_align(struct intel_dsb *dsb) +{ + u32 aligned_tail, tail; + + intel_dsb_ins_align(dsb); + + tail = dsb->free_pos * 4; + aligned_tail = ALIGN(tail, CACHELINE_BYTES); + + /* + * Wa_16024917128 + * "Ensure GOSUB is not placed in cacheline QW slot 6 or 7 (numbered 0-7)" + */ + if (aligned_tail - tail <= 2 * 8) + intel_dsb_buffer_memset(&dsb->dsb_buf, dsb->free_pos, 0, + aligned_tail - tail); + + dsb->free_pos = aligned_tail / 4; +} + +void intel_dsb_gosub(struct intel_dsb *dsb, + struct intel_dsb *sub_dsb) { struct intel_crtc *crtc = dsb->crtc; + struct intel_display *display = to_intel_display(crtc->base.dev); + unsigned int head, tail; + u64 head_tail; + + if (drm_WARN_ON(display->drm, dsb->id != sub_dsb->id)) + return; + + if (!assert_dsb_tail_is_aligned(sub_dsb)) + return; + + intel_dsb_gosub_align(dsb); + + head = intel_dsb_head(sub_dsb); + tail = intel_dsb_tail(sub_dsb); /* - * DSB_FORCE_DEWAKE remains active even after DSB is - * disabled, so make sure to clear it (if set during - * intel_dsb_commit()). And clear DSB_ENABLE_DEWAKE as - * well for good measure. + * The GOSUB instruction has the following memory layout. + * + * +------------------------------------------------------------+ + * | Opcode | Rsvd | Head Ptr | Tail Ptr | + * | 0x0c | | | | + * +------------------------------------------------------------+ + * |<- 8bits->|<- 4bits ->|<-- 26bits -->|<-- 26bits -->| + * + * We have only 26 bits each to represent the head and tail + * pointers even though the addresses itself are of 32 bit. However, this + * is not a problem because the addresses are 64 bit aligned and therefore + * the last 6 bits are always Zero's. Therefore, we right shift the address + * by 6 before embedding it into the GOSUB instruction. */ - intel_dsb_reg_write(dsb, DSB_PMCTRL(crtc->pipe, dsb->id), 0); - intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(crtc->pipe, dsb->id), - DSB_FORCE_DEWAKE, 0); + head_tail = ((u64)(DSB_GOSUB_CONVERT_ADDR(head)) << DSB_GOSUB_HEAD_SHIFT) | + ((u64)(DSB_GOSUB_CONVERT_ADDR(tail)) << DSB_GOSUB_TAIL_SHIFT); + + intel_dsb_emit(dsb, lower_32_bits(head_tail), + (DSB_OPCODE_GOSUB << DSB_OPCODE_SHIFT) | + upper_32_bits(head_tail)); + + /* + * "NOTE: the instructions within the cacheline + * FOLLOWING the GOSUB instruction must be NOPs." + */ + intel_dsb_align_tail(dsb); +} + +void intel_dsb_gosub_finish(struct intel_dsb *dsb) +{ + intel_dsb_align_tail(dsb); + + /* + * Wa_16024917128 + * "Ensure that all subroutines called by GOSUB end with a cacheline of NOPs" + */ + intel_dsb_noop(dsb, 8); + + intel_dsb_buffer_flush_map(&dsb->dsb_buf); +} + +void intel_dsb_finish(struct intel_dsb *dsb) +{ intel_dsb_align_tail(dsb); intel_dsb_buffer_flush_map(&dsb->dsb_buf); @@ -538,6 +650,9 @@ static u32 dsb_error_int_status(struct intel_display *display) if (DISPLAY_VER(display) >= 14) errors |= DSB_ATS_FAULT_INT_STATUS; + if (DISPLAY_VER(display) >= 30) + errors |= DSB_GOSUB_INT_STATUS; + return errors; } @@ -552,17 +667,46 @@ static u32 dsb_error_int_en(struct intel_display *display) if (DISPLAY_VER(display) >= 14) errors |= DSB_ATS_FAULT_INT_EN; + /* + * Wa_16024917128 + * "Disable nested GOSUB interrupt (DSB_INTERRUPT bit 21)" + */ + if (0 && DISPLAY_VER(display) >= 30) + errors |= DSB_GOSUB_INT_EN; + return errors; } +/* + * FIXME calibrate these sensibly, ideally compute based on + * the number of regisetrs to be written. But that requires + * measuring the actual DSB execution speed on each platform + * (and the speed also depends on CDCLK and memory clock)... + */ +static int intel_dsb_noarm_exec_time_us(void) +{ + return 80; +} + +static int intel_dsb_arm_exec_time_us(void) +{ + return 20; +} + +int intel_dsb_exec_time_us(void) +{ + return intel_dsb_noarm_exec_time_us() + + intel_dsb_arm_exec_time_us(); +} + void intel_dsb_vblank_evade(struct intel_atomic_state *state, struct intel_dsb *dsb) { struct intel_crtc *crtc = dsb->crtc; const struct intel_crtc_state *crtc_state = intel_pre_commit_crtc_state(state, crtc); - /* FIXME calibrate sensibly */ - int latency = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 20); + int latency = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, + intel_dsb_arm_exec_time_us()); int start, end; /* @@ -604,13 +748,11 @@ static void _intel_dsb_chain(struct intel_atomic_state *state, struct intel_display *display = to_intel_display(state->base.dev); struct intel_crtc *crtc = dsb->crtc; enum pipe pipe = crtc->pipe; - u32 tail; if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id)) return; - tail = chained_dsb->free_pos * 4; - if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES))) + if (!assert_dsb_tail_is_aligned(chained_dsb)) return; intel_dsb_reg_write(dsb, DSB_CTRL(pipe, chained_dsb->id), @@ -630,13 +772,15 @@ static void _intel_dsb_chain(struct intel_atomic_state *state, intel_dsb_reg_write(dsb, DSB_PMCTRL(pipe, chained_dsb->id), DSB_ENABLE_DEWAKE | DSB_SCANLINE_FOR_DEWAKE(hw_dewake_scanline)); + } else { + intel_dsb_reg_write(dsb, DSB_PMCTRL(pipe, chained_dsb->id), 0); } intel_dsb_reg_write(dsb, DSB_HEAD(pipe, chained_dsb->id), - intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf)); + intel_dsb_head(chained_dsb)); intel_dsb_reg_write(dsb, DSB_TAIL(pipe, chained_dsb->id), - intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf) + tail); + intel_dsb_tail(chained_dsb)); if (ctrl & DSB_WAIT_FOR_VBLANK) { /* @@ -651,6 +795,13 @@ static void _intel_dsb_chain(struct intel_atomic_state *state, intel_dsb_wait_scanline_out(state, dsb, dsb_dewake_scanline_start(state, crtc), dsb_dewake_scanline_end(state, crtc)); + + /* + * DSB_FORCE_DEWAKE remains active even after DSB is + * disabled, so make sure to clear it. + */ + intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(crtc->pipe, dsb->id), + DSB_FORCE_DEWAKE, 0); } } @@ -675,16 +826,19 @@ void intel_dsb_wait_vblank_delay(struct intel_atomic_state *state, intel_dsb_wait_usec(dsb, usecs); } -static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, - int hw_dewake_scanline) +/** + * intel_dsb_commit() - Trigger workload execution of DSB. + * @dsb: DSB context + * + * This function is used to do actual write to hardware using DSB. + */ +void intel_dsb_commit(struct intel_dsb *dsb) { struct intel_crtc *crtc = dsb->crtc; struct intel_display *display = to_intel_display(crtc->base.dev); enum pipe pipe = crtc->pipe; - u32 tail; - tail = dsb->free_pos * 4; - if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES))) + if (!assert_dsb_tail_is_aligned(dsb)) return; if (is_dsb_busy(display, pipe, dsb->id)) { @@ -694,7 +848,7 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, } intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), - ctrl | DSB_ENABLE); + DSB_ENABLE); intel_de_write_fw(display, DSB_CHICKEN(pipe, dsb->id), dsb->chicken); @@ -703,45 +857,13 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, dsb_error_int_status(display) | DSB_PROG_INT_STATUS | dsb_error_int_en(display) | DSB_PROG_INT_EN); - intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id), - intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf)); - - if (hw_dewake_scanline >= 0) { - int diff, position; + intel_de_write_fw(display, DSB_PMCTRL(pipe, dsb->id), 0); - intel_de_write_fw(display, DSB_PMCTRL(pipe, dsb->id), - DSB_ENABLE_DEWAKE | - DSB_SCANLINE_FOR_DEWAKE(hw_dewake_scanline)); - - /* - * Force DEwake immediately if we're already past - * or close to racing past the target scanline. - */ - position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK; - - diff = hw_dewake_scanline - position; - intel_de_write_fw(display, DSB_PMCTRL_2(pipe, dsb->id), - (diff >= 0 && diff < 5 ? DSB_FORCE_DEWAKE : 0) | - DSB_BLOCK_DEWAKE_EXTENSION); - } + intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id), + intel_dsb_head(dsb)); intel_de_write_fw(display, DSB_TAIL(pipe, dsb->id), - intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + tail); -} - -/** - * intel_dsb_commit() - Trigger workload execution of DSB. - * @dsb: DSB context - * @wait_for_vblank: wait for vblank before executing - * - * This function is used to do actual write to hardware using DSB. - */ -void intel_dsb_commit(struct intel_dsb *dsb, - bool wait_for_vblank) -{ - _intel_dsb_commit(dsb, - wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0, - wait_for_vblank ? dsb->hw_dewake_scanline : -1); + intel_dsb_tail(dsb)); } void intel_dsb_wait(struct intel_dsb *dsb) @@ -894,4 +1016,7 @@ void intel_dsb_irq_handler(struct intel_display *display, if (errors & DSB_POLL_ERR_INT_STATUS) drm_err(display->drm, "[CRTC:%d:%s] DSB %d poll error\n", crtc->base.base.id, crtc->base.name, dsb_id); + if (errors & DSB_GOSUB_INT_STATUS) + drm_err(display->drm, "[CRTC:%d:%s] DSB %d GOSUB programming error\n", + crtc->base.base.id, crtc->base.name, dsb_id); } diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index e843c52bf97c..c8f4499916eb 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -26,12 +26,16 @@ enum intel_dsb_id { I915_MAX_DSBS, }; +unsigned int intel_dsb_size(struct intel_dsb *dsb); +unsigned int intel_dsb_head(struct intel_dsb *dsb); struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, struct intel_crtc *crtc, enum intel_dsb_id dsb_id, unsigned int max_cmds); void intel_dsb_finish(struct intel_dsb *dsb); +void intel_dsb_gosub_finish(struct intel_dsb *dsb); void intel_dsb_cleanup(struct intel_dsb *dsb); +int intel_dsb_exec_time_us(void); void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val); void intel_dsb_reg_write_indexed(struct intel_dsb *dsb, @@ -57,13 +61,14 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state, void intel_dsb_poll(struct intel_dsb *dsb, i915_reg_t reg, u32 mask, u32 val, int wait_us, int count); +void intel_dsb_gosub(struct intel_dsb *dsb, + struct intel_dsb *sub_dsb); void intel_dsb_chain(struct intel_atomic_state *state, struct intel_dsb *dsb, struct intel_dsb *chained_dsb, bool wait_for_vblank); -void intel_dsb_commit(struct intel_dsb *dsb, - bool wait_for_vblank); +void intel_dsb_commit(struct intel_dsb *dsb); void intel_dsb_wait(struct intel_dsb *dsb); void intel_dsb_irq_handler(struct intel_display *display, diff --git a/drivers/gpu/drm/i915/display/intel_dsb_regs.h b/drivers/gpu/drm/i915/display/intel_dsb_regs.h index cb6e0e5624a6..230104f36145 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dsb_regs.h @@ -51,11 +51,13 @@ #define DSB_RESET_SM_STATE_MASK REG_GENMASK(5, 4) #define DSB_RUN_SM_STATE_MASK REG_GENMASK(2, 0) #define DSB_INTERRUPT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28) +#define DSB_GOSUB_INT_EN REG_BIT(21) /* ptl+ */ #define DSB_ATS_FAULT_INT_EN REG_BIT(20) /* mtl+ */ #define DSB_GTT_FAULT_INT_EN REG_BIT(19) #define DSB_RSPTIMEOUT_INT_EN REG_BIT(18) #define DSB_POLL_ERR_INT_EN REG_BIT(17) #define DSB_PROG_INT_EN REG_BIT(16) +#define DSB_GOSUB_INT_STATUS REG_BIT(5) /* ptl+ */ #define DSB_ATS_FAULT_INT_STATUS REG_BIT(4) /* mtl+ */ #define DSB_GTT_FAULT_INT_STATUS REG_BIT(3) #define DSB_RSPTIMEOUT_INT_STATUS REG_BIT(2) diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c index 403151175a87..a8f012119165 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi.c +++ b/drivers/gpu/drm/i915/display/intel_dsi.c @@ -4,8 +4,9 @@ */ #include <drm/drm_mipi_dsi.h> +#include <drm/drm_print.h> -#include "i915_drv.h" +#include "intel_display_core.h" #include "intel_dsi.h" #include "intel_panel.h" @@ -116,14 +117,14 @@ struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, enum drm_panel_orientation intel_dsi_get_panel_orientation(struct intel_connector *connector) { - struct drm_i915_private *dev_priv = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); enum drm_panel_orientation orientation; orientation = connector->panel.vbt.dsi.orientation; if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN) return orientation; - orientation = dev_priv->display.vbt.orientation; + orientation = display->vbt.orientation; if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN) return orientation; diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c index 4e92504f5c14..e6a851d276f8 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c @@ -31,17 +31,16 @@ #include <linux/pinctrl/machine.h> #include <linux/slab.h> #include <linux/string_helpers.h> - #include <linux/unaligned.h> #include <drm/drm_crtc.h> #include <drm/drm_edid.h> - +#include <drm/drm_print.h> #include <video/mipi_display.h> -#include "i915_drv.h" -#include "i915_reg.h" +#include "i915_utils.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dsi.h" #include "intel_dsi_vbt.h" @@ -321,7 +320,6 @@ enum { static void icl_native_gpio_set_value(struct intel_display *display, int gpio, bool value) { - struct drm_i915_private *dev_priv = to_i915(display->drm); int index; if (drm_WARN_ON(display->drm, DISPLAY_VER(display) == 11 && gpio >= MIPI_RESET_2)) @@ -341,12 +339,12 @@ static void icl_native_gpio_set_value(struct intel_display *display, * The locking protects against concurrent SHOTPLUG_CTL_DDI * modifications in irq setup and handling. */ - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); intel_de_rmw(display, SHOTPLUG_CTL_DDI, SHOTPLUG_CTL_DDI_HPD_ENABLE(index) | SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index), value ? SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index) : 0); - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); break; case MIPI_AVDD_EN_1: case MIPI_AVDD_EN_2: diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c index b61520353c92..08b48e36aca6 100644 --- a/drivers/gpu/drm/i915/display/intel_dvo.c +++ b/drivers/gpu/drm/i915/display/intel_dvo.c @@ -34,11 +34,11 @@ #include <drm/drm_print.h> #include <drm/drm_probe_helper.h> -#include "i915_reg.h" #include "i915_utils.h" #include "intel_connector.h" #include "intel_de.h" #include "intel_display_driver.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dvo.h" #include "intel_dvo_dev.h" diff --git a/drivers/gpu/drm/i915/display/intel_encoder.c b/drivers/gpu/drm/i915/display/intel_encoder.c index 21d638535497..bad452ad979a 100644 --- a/drivers/gpu/drm/i915/display/intel_encoder.c +++ b/drivers/gpu/drm/i915/display/intel_encoder.c @@ -6,7 +6,7 @@ #include <linux/workqueue.h> #include "i915_drv.h" - +#include "intel_display_core.h" #include "intel_display_types.h" #include "intel_encoder.h" diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 2b0e0f220442..a5906cb4900c 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -14,6 +14,7 @@ #include "intel_atomic_plane.h" #include "intel_bo.h" #include "intel_display.h" +#include "intel_display_core.h" #include "intel_display_types.h" #include "intel_dpt.h" #include "intel_fb.h" @@ -560,11 +561,11 @@ static bool plane_has_modifier(struct intel_display *display, return false; if (md->modifier == I915_FORMAT_MOD_4_TILED_BMG_CCS && - (GRAPHICS_VER(i915) < 20 || !IS_DGFX(i915))) + (GRAPHICS_VER(i915) < 20 || !display->platform.dgfx)) return false; if (md->modifier == I915_FORMAT_MOD_4_TILED_LNL_CCS && - (GRAPHICS_VER(i915) < 20 || IS_DGFX(i915))) + (GRAPHICS_VER(i915) < 20 || display->platform.dgfx)) return false; return true; diff --git a/drivers/gpu/drm/i915/display/intel_fb_bo.c b/drivers/gpu/drm/i915/display/intel_fb_bo.c index 3d338a728354..b0e8b89f7ce8 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_bo.c +++ b/drivers/gpu/drm/i915/display/intel_fb_bo.c @@ -8,6 +8,7 @@ #include "gem/i915_gem_object.h" #include "i915_drv.h" +#include "intel_display_core.h" #include "intel_display_types.h" #include "intel_fb.h" #include "intel_fb_bo.h" diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index c648ab8a93d7..98a61a7b0b93 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -12,6 +12,7 @@ #include "i915_drv.h" #include "intel_atomic_plane.h" +#include "intel_display_core.h" #include "intel_display_rpm.h" #include "intel_display_types.h" #include "intel_dpt.h" diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index ce5b1e3f1c20..ec1ef8694c35 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -45,9 +45,10 @@ #include <drm/drm_fourcc.h> #include "gem/i915_gem_stolen.h" + #include "gt/intel_gt_types.h" + #include "i915_drv.h" -#include "i915_reg.h" #include "i915_utils.h" #include "i915_vgpu.h" #include "i915_vma.h" @@ -55,6 +56,7 @@ #include "intel_cdclk.h" #include "intel_de.h" #include "intel_display_device.h" +#include "intel_display_regs.h" #include "intel_display_rpm.h" #include "intel_display_trace.h" #include "intel_display_types.h" @@ -252,9 +254,12 @@ static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_s * Gen9 hw miscalculates cfb stride for linear as * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so * we always need to use the override there. + * + * wa_14022269668 For bmg, always program the FBC_STRIDE before fbc enable */ if (stride != stride_aligned || - (DISPLAY_VER(display) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR)) + (DISPLAY_VER(display) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR) || + display->platform.battlemage) return stride_aligned * 4 / 64; return 0; diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index 369f46286e95..2dc4029d71ed 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -47,9 +47,9 @@ #include <drm/drm_managed.h> #include <drm/drm_print.h> -#include "i915_drv.h" #include "i915_vma.h" #include "intel_bo.h" +#include "intel_display_core.h" #include "intel_display_rpm.h" #include "intel_display_types.h" #include "intel_fb.h" @@ -66,9 +66,9 @@ struct intel_fbdev { static struct intel_fbdev *to_intel_fbdev(struct drm_fb_helper *fb_helper) { - struct drm_i915_private *i915 = to_i915(fb_helper->client.dev); + struct intel_display *display = to_intel_display(fb_helper->client.dev); - return i915->display.fbdev.fbdev; + return display->fbdev.fbdev; } static struct intel_frontbuffer *to_frontbuffer(struct intel_fbdev *ifbdev) @@ -210,11 +210,9 @@ static const struct drm_fb_helper_funcs intel_fb_helper_funcs = { int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, struct drm_fb_helper_surface_size *sizes) { + struct intel_display *display = to_intel_display(helper->dev); struct intel_fbdev *ifbdev = to_intel_fbdev(helper); struct intel_framebuffer *fb = ifbdev->fb; - struct drm_device *dev = helper->dev; - struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_display *display = to_intel_display(dev); struct ref_tracker *wakeref; struct fb_info *info; struct i915_vma *vma; @@ -228,7 +226,7 @@ int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, if (fb && (sizes->fb_width > fb->base.width || sizes->fb_height > fb->base.height)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "BIOS fb too small (%dx%d), we require (%dx%d)," " releasing it\n", fb->base.width, fb->base.height, @@ -236,14 +234,14 @@ int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, drm_framebuffer_put(&fb->base); fb = NULL; } - if (!fb || drm_WARN_ON(dev, !intel_fb_bo(&fb->base))) { - drm_dbg_kms(&dev_priv->drm, + if (!fb || drm_WARN_ON(display->drm, !intel_fb_bo(&fb->base))) { + drm_dbg_kms(display->drm, "no BIOS fb, allocating a new one\n"); fb = intel_fbdev_fb_alloc(helper, sizes); if (IS_ERR(fb)) return PTR_ERR(fb); } else { - drm_dbg_kms(&dev_priv->drm, "re-using BIOS fb\n"); + drm_dbg_kms(display->drm, "re-using BIOS fb\n"); prealloc = true; sizes->fb_width = fb->base.width; sizes->fb_height = fb->base.height; @@ -267,7 +265,7 @@ int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, info = drm_fb_helper_alloc_info(helper); if (IS_ERR(info)) { - drm_err(&dev_priv->drm, "Failed to allocate fb_info (%pe)\n", info); + drm_err(display->drm, "Failed to allocate fb_info (%pe)\n", info); ret = PTR_ERR(info); goto out_unpin; } @@ -279,11 +277,11 @@ int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, obj = intel_fb_bo(&fb->base); - ret = intel_fbdev_fb_fill_info(dev_priv, info, obj, vma); + ret = intel_fbdev_fb_fill_info(display, info, obj, vma); if (ret) goto out_unpin; - drm_fb_helper_fill_info(info, dev->fb_helper, sizes); + drm_fb_helper_fill_info(info, display->drm->fb_helper, sizes); /* If the object is shmemfs backed, it will have given us zeroed pages. * If the object is stolen however, it will be full of whatever @@ -294,7 +292,7 @@ int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ - drm_dbg_kms(&dev_priv->drm, "allocated %dx%d fb: 0x%08x\n", + drm_dbg_kms(display->drm, "allocated %dx%d fb: 0x%08x\n", fb->base.width, fb->base.height, i915_ggtt_offset(vma)); ifbdev->fb = fb; @@ -322,16 +320,15 @@ out_unlock: * Note we only support a single fb shared across pipes for boot (mostly for * fbcon), so we just find the biggest and use that. */ -static bool intel_fbdev_init_bios(struct drm_device *dev, +static bool intel_fbdev_init_bios(struct intel_display *display, struct intel_fbdev *ifbdev) { - struct drm_i915_private *i915 = to_i915(dev); struct intel_framebuffer *fb = NULL; struct intel_crtc *crtc; unsigned int max_size = 0; /* Find the largest fb */ - for_each_intel_crtc(dev, crtc) { + for_each_intel_crtc(display->drm, crtc) { struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); struct intel_plane *plane = @@ -341,21 +338,21 @@ static bool intel_fbdev_init_bios(struct drm_device *dev, struct drm_gem_object *obj = intel_fb_bo(plane_state->uapi.fb); if (!crtc_state->uapi.active) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] not active, skipping\n", crtc->base.base.id, crtc->base.name); continue; } if (!obj) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[PLANE:%d:%s] no fb, skipping\n", plane->base.base.id, plane->base.name); continue; } if (obj->size > max_size) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "found possible fb from [PLANE:%d:%s]\n", plane->base.base.id, plane->base.name); fb = to_intel_framebuffer(plane_state->uapi.fb); @@ -364,13 +361,13 @@ static bool intel_fbdev_init_bios(struct drm_device *dev, } if (!fb) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "no active fbs found, not using BIOS config\n"); goto out; } /* Now make sure all the pipes will fit into it */ - for_each_intel_crtc(dev, crtc) { + for_each_intel_crtc(display->drm, crtc) { struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); struct intel_plane *plane = @@ -378,13 +375,13 @@ static bool intel_fbdev_init_bios(struct drm_device *dev, unsigned int cur_size; if (!crtc_state->uapi.active) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] not active, skipping\n", crtc->base.base.id, crtc->base.name); continue; } - drm_dbg_kms(&i915->drm, "checking [PLANE:%d:%s] for BIOS fb\n", + drm_dbg_kms(display->drm, "checking [PLANE:%d:%s] for BIOS fb\n", plane->base.base.id, plane->base.name); /* @@ -395,7 +392,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev, cur_size = crtc_state->uapi.adjusted_mode.crtc_hdisplay; cur_size = cur_size * fb->base.format->cpp[0]; if (fb->base.pitches[0] < cur_size) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "fb not wide enough for [PLANE:%d:%s] (%d vs %d)\n", plane->base.base.id, plane->base.name, cur_size, fb->base.pitches[0]); @@ -406,7 +403,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev, cur_size = crtc_state->uapi.adjusted_mode.crtc_vdisplay; cur_size = intel_fb_align_height(&fb->base, 0, cur_size); cur_size *= fb->base.pitches[0]; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] area: %dx%d, bpp: %d, size: %d\n", crtc->base.base.id, crtc->base.name, crtc_state->uapi.adjusted_mode.crtc_hdisplay, @@ -415,7 +412,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev, cur_size); if (cur_size > max_size) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "fb not big enough for [PLANE:%d:%s] (%d vs %d)\n", plane->base.base.id, plane->base.name, cur_size, max_size); @@ -423,14 +420,14 @@ static bool intel_fbdev_init_bios(struct drm_device *dev, break; } - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "fb big enough [PLANE:%d:%s] (%d >= %d)\n", plane->base.base.id, plane->base.name, max_size, cur_size); } if (!fb) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "BIOS fb not suitable for all pipes, not using\n"); goto out; } @@ -440,7 +437,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev, drm_framebuffer_get(&ifbdev->fb->base); /* Final pass to check if any active pipes don't have fbs */ - for_each_intel_crtc(dev, crtc) { + for_each_intel_crtc(display->drm, crtc) { struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); struct intel_plane *plane = @@ -451,13 +448,13 @@ static bool intel_fbdev_init_bios(struct drm_device *dev, if (!crtc_state->uapi.active) continue; - drm_WARN(dev, !plane_state->uapi.fb, + drm_WARN(display->drm, !plane_state->uapi.fb, "re-used BIOS config but lost an fb on [PLANE:%d:%s]\n", plane->base.base.id, plane->base.name); } - drm_dbg_kms(&i915->drm, "using BIOS fb for initial console\n"); + drm_dbg_kms(display->drm, "using BIOS fb for initial console\n"); return true; out: @@ -482,26 +479,25 @@ static unsigned int intel_fbdev_color_mode(const struct drm_format_info *info) } } -void intel_fbdev_setup(struct drm_i915_private *i915) +void intel_fbdev_setup(struct intel_display *display) { - struct drm_device *dev = &i915->drm; struct intel_fbdev *ifbdev; unsigned int preferred_bpp = 0; - if (!HAS_DISPLAY(i915)) + if (!HAS_DISPLAY(display)) return; - ifbdev = drmm_kzalloc(dev, sizeof(*ifbdev), GFP_KERNEL); + ifbdev = drmm_kzalloc(display->drm, sizeof(*ifbdev), GFP_KERNEL); if (!ifbdev) return; - i915->display.fbdev.fbdev = ifbdev; - if (intel_fbdev_init_bios(dev, ifbdev)) + display->fbdev.fbdev = ifbdev; + if (intel_fbdev_init_bios(display, ifbdev)) preferred_bpp = intel_fbdev_color_mode(ifbdev->fb->base.format); if (!preferred_bpp) preferred_bpp = 32; - drm_client_setup_with_color_mode(dev, preferred_bpp); + drm_client_setup_with_color_mode(display->drm, preferred_bpp); } struct intel_framebuffer *intel_fbdev_framebuffer(struct intel_fbdev *fbdev) diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.h b/drivers/gpu/drm/i915/display/intel_fbdev.h index 89bad3a2b01a..a15e3e222a0c 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.h +++ b/drivers/gpu/drm/i915/display/intel_fbdev.h @@ -10,7 +10,7 @@ struct drm_fb_helper; struct drm_fb_helper_surface_size; -struct drm_i915_private; +struct intel_display; struct intel_fbdev; struct intel_framebuffer; @@ -19,14 +19,14 @@ int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, struct drm_fb_helper_surface_size *sizes); #define INTEL_FBDEV_DRIVER_OPS \ .fbdev_probe = intel_fbdev_driver_fbdev_probe -void intel_fbdev_setup(struct drm_i915_private *dev_priv); +void intel_fbdev_setup(struct intel_display *display); struct intel_framebuffer *intel_fbdev_framebuffer(struct intel_fbdev *fbdev); struct i915_vma *intel_fbdev_vma_pointer(struct intel_fbdev *fbdev); #else #define INTEL_FBDEV_DRIVER_OPS \ .fbdev_probe = NULL -static inline void intel_fbdev_setup(struct drm_i915_private *dev_priv) +static inline void intel_fbdev_setup(struct intel_display *display) { } static inline struct intel_framebuffer *intel_fbdev_framebuffer(struct intel_fbdev *fbdev) diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c index 4991c35a2632..8db3af36b2f2 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c @@ -8,6 +8,7 @@ #include "gem/i915_gem_lmem.h" #include "i915_drv.h" +#include "intel_display_core.h" #include "intel_display_types.h" #include "intel_fb.h" #include "intel_fbdev_fb.h" @@ -15,9 +16,9 @@ struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper, struct drm_fb_helper_surface_size *sizes) { + struct intel_display *display = to_intel_display(helper->dev); + struct drm_i915_private *dev_priv = to_i915(display->drm); struct drm_framebuffer *fb; - struct drm_device *dev = helper->dev; - struct drm_i915_private *dev_priv = to_i915(dev); struct drm_mode_fb_cmd2 mode_cmd = {}; struct drm_i915_gem_object *obj; int size; @@ -50,14 +51,14 @@ struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper, * * Also skip stolen on MTL as Wa_22018444074 mitigation. */ - if (!(IS_METEORLAKE(dev_priv)) && size * 2 < dev_priv->dsm.usable_size) + if (!display->platform.meteorlake && size * 2 < dev_priv->dsm.usable_size) obj = i915_gem_object_create_stolen(dev_priv, size); if (IS_ERR(obj)) obj = i915_gem_object_create_shmem(dev_priv, size); } if (IS_ERR(obj)) { - drm_err(&dev_priv->drm, "failed to allocate framebuffer (%pe)\n", obj); + drm_err(display->drm, "failed to allocate framebuffer (%pe)\n", obj); return ERR_PTR(-ENOMEM); } @@ -67,9 +68,10 @@ struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper, return to_intel_framebuffer(fb); } -int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info *info, +int intel_fbdev_fb_fill_info(struct intel_display *display, struct fb_info *info, struct drm_gem_object *_obj, struct i915_vma *vma) { + struct drm_i915_private *i915 = to_i915(display->drm); struct drm_i915_gem_object *obj = to_intel_bo(_obj); struct i915_gem_ww_ctx ww; void __iomem *vaddr; @@ -101,7 +103,7 @@ int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info *info vaddr = i915_vma_pin_iomap(vma); if (IS_ERR(vaddr)) { - drm_err(&i915->drm, + drm_err(display->drm, "Failed to remap framebuffer into virtual memory (%pe)\n", vaddr); ret = PTR_ERR(vaddr); continue; diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.h b/drivers/gpu/drm/i915/display/intel_fbdev_fb.h index e502ae375fc0..cb7957272715 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fbdev_fb.h @@ -9,13 +9,13 @@ struct drm_fb_helper; struct drm_fb_helper_surface_size; struct drm_gem_object; -struct drm_i915_private; struct fb_info; struct i915_vma; +struct intel_display; struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper, struct drm_fb_helper_surface_size *sizes); -int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info *info, +int intel_fbdev_fb_fill_info(struct intel_display *display, struct fb_info *info, struct drm_gem_object *obj, struct i915_vma *vma); #endif diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index 40deee0769ae..8039a84671cc 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -6,15 +6,17 @@ #include <linux/string_helpers.h> #include <drm/drm_fixed.h> +#include <drm/drm_print.h> -#include "i915_drv.h" #include "i915_reg.h" +#include "i915_utils.h" #include "intel_atomic.h" #include "intel_crtc.h" #include "intel_ddi.h" #include "intel_de.h" -#include "intel_dp.h" +#include "intel_display_regs.h" #include "intel_display_types.h" +#include "intel_dp.h" #include "intel_fdi.h" #include "intel_fdi_regs.h" #include "intel_link_bw.h" @@ -464,7 +466,6 @@ static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_st void intel_fdi_normal_train(struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *dev_priv = to_i915(display->drm); enum pipe pipe = crtc->pipe; i915_reg_t reg; u32 temp; @@ -483,7 +484,7 @@ void intel_fdi_normal_train(struct intel_crtc *crtc) reg = FDI_RX_CTL(pipe); temp = intel_de_read(display, reg); - if (HAS_PCH_CPT(dev_priv)) { + if (HAS_PCH_CPT(display)) { temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp |= FDI_LINK_TRAIN_NORMAL_CPT; } else { @@ -607,7 +608,6 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *dev_priv = to_i915(display->drm); enum pipe pipe = crtc->pipe; i915_reg_t reg; u32 temp, i, retry; @@ -647,7 +647,7 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, reg = FDI_RX_CTL(pipe); temp = intel_de_read(display, reg); - if (HAS_PCH_CPT(dev_priv)) { + if (HAS_PCH_CPT(display)) { temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; } else { @@ -698,7 +698,7 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, reg = FDI_RX_CTL(pipe); temp = intel_de_read(display, reg); - if (HAS_PCH_CPT(dev_priv)) { + if (HAS_PCH_CPT(display)) { temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; } else { @@ -911,7 +911,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val); /* Configure Port Clock Select */ - drm_WARN_ON(display->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL); + drm_WARN_ON(display->drm, crtc_state->intel_dpll->info->id != DPLL_ID_SPLL); intel_ddi_enable_clock(encoder, crtc_state); /* Start the training iterating through available voltages and emphasis, @@ -1077,7 +1077,6 @@ void ilk_fdi_pll_disable(struct intel_crtc *crtc) void ilk_fdi_disable(struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; i915_reg_t reg; u32 temp; @@ -1096,7 +1095,7 @@ void ilk_fdi_disable(struct intel_crtc *crtc) udelay(100); /* Ironlake workaround, disable clock pointer after downing FDI */ - if (HAS_PCH_IBX(dev_priv)) + if (HAS_PCH_IBX(display)) intel_de_write(display, FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); @@ -1106,7 +1105,7 @@ void ilk_fdi_disable(struct intel_crtc *crtc) reg = FDI_RX_CTL(pipe); temp = intel_de_read(display, reg); - if (HAS_PCH_CPT(dev_priv)) { + if (HAS_PCH_CPT(display)) { temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; } else { diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c index 451cd26024f7..c2ce8461ac9e 100644 --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c @@ -25,10 +25,12 @@ * */ -#include "i915_drv.h" +#include <drm/drm_print.h> + #include "i915_reg.h" #include "intel_de.h" #include "intel_display_irq.h" +#include "intel_display_regs.h" #include "intel_display_trace.h" #include "intel_display_types.h" #include "intel_fbc.h" @@ -57,11 +59,10 @@ static bool ivb_can_enable_err_int(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_crtc *crtc; enum pipe pipe; - lockdep_assert_held(&dev_priv->irq_lock); + lockdep_assert_held(&display->irq.lock); for_each_pipe(display, pipe) { crtc = intel_crtc_for_pipe(display, pipe); @@ -75,11 +76,10 @@ static bool ivb_can_enable_err_int(struct intel_display *display) static bool cpt_can_enable_serr_int(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); enum pipe pipe; struct intel_crtc *crtc; - lockdep_assert_held(&dev_priv->irq_lock); + lockdep_assert_held(&display->irq.lock); for_each_pipe(display, pipe) { crtc = intel_crtc_for_pipe(display, pipe); @@ -94,11 +94,10 @@ static bool cpt_can_enable_serr_int(struct intel_display *display) static void i9xx_check_fifo_underruns(struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); i915_reg_t reg = PIPESTAT(display, crtc->pipe); u32 enable_mask; - lockdep_assert_held(&dev_priv->irq_lock); + lockdep_assert_held(&display->irq.lock); if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) return; @@ -115,10 +114,9 @@ static void i9xx_set_fifo_underrun_reporting(struct intel_display *display, enum pipe pipe, bool enable, bool old) { - struct drm_i915_private *dev_priv = to_i915(display->drm); i915_reg_t reg = PIPESTAT(display, pipe); - lockdep_assert_held(&dev_priv->irq_lock); + lockdep_assert_held(&display->irq.lock); if (enable) { u32 enable_mask = i915_pipestat_enable_mask(display, pipe); @@ -148,11 +146,10 @@ static void ilk_set_fifo_underrun_reporting(struct intel_display *display, static void ivb_check_fifo_underruns(struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; u32 err_int = intel_de_read(display, GEN7_ERR_INT); - lockdep_assert_held(&dev_priv->irq_lock); + lockdep_assert_held(&display->irq.lock); if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0) return; @@ -213,11 +210,10 @@ static void ibx_set_fifo_underrun_reporting(struct intel_display *display, static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pch_transcoder = crtc->pipe; u32 serr_int = intel_de_read(display, SERR_INT); - lockdep_assert_held(&dev_priv->irq_lock); + lockdep_assert_held(&display->irq.lock); if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0) return; @@ -258,11 +254,10 @@ static void cpt_set_fifo_underrun_reporting(struct intel_display *display, static bool __intel_set_cpu_fifo_underrun_reporting(struct intel_display *display, enum pipe pipe, bool enable) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); bool old; - lockdep_assert_held(&dev_priv->irq_lock); + lockdep_assert_held(&display->irq.lock); old = !crtc->cpu_fifo_underrun_disabled; crtc->cpu_fifo_underrun_disabled = !enable; @@ -298,13 +293,12 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct intel_display *displa bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display, enum pipe pipe, bool enable) { - struct drm_i915_private *dev_priv = to_i915(display->drm); unsigned long flags; bool ret; - spin_lock_irqsave(&dev_priv->irq_lock, flags); + spin_lock_irqsave(&display->irq.lock, flags); ret = __intel_set_cpu_fifo_underrun_reporting(display, pipe, enable); - spin_unlock_irqrestore(&dev_priv->irq_lock, flags); + spin_unlock_irqrestore(&display->irq.lock, flags); return ret; } @@ -327,7 +321,6 @@ bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display, enum pipe pch_transcoder, bool enable) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_crtc *crtc = intel_crtc_for_pipe(display, pch_transcoder); unsigned long flags; bool old; @@ -341,12 +334,12 @@ bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display, * crtc on LPT won't cause issues. */ - spin_lock_irqsave(&dev_priv->irq_lock, flags); + spin_lock_irqsave(&display->irq.lock, flags); old = !crtc->pch_fifo_underrun_disabled; crtc->pch_fifo_underrun_disabled = !enable; - if (HAS_PCH_IBX(dev_priv)) + if (HAS_PCH_IBX(display)) ibx_set_fifo_underrun_reporting(display, pch_transcoder, enable); @@ -355,7 +348,7 @@ bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display, pch_transcoder, enable, old); - spin_unlock_irqrestore(&dev_priv->irq_lock, flags); + spin_unlock_irqrestore(&display->irq.lock, flags); return old; } @@ -422,10 +415,9 @@ void intel_pch_fifo_underrun_irq_handler(struct intel_display *display, */ void intel_check_cpu_fifo_underruns(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_crtc *crtc; - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); for_each_intel_crtc(display->drm, crtc) { if (crtc->cpu_fifo_underrun_disabled) @@ -437,7 +429,7 @@ void intel_check_cpu_fifo_underruns(struct intel_display *display) ivb_check_fifo_underruns(crtc); } - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); } /** @@ -450,20 +442,19 @@ void intel_check_cpu_fifo_underruns(struct intel_display *display) */ void intel_check_pch_fifo_underruns(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_crtc *crtc; - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); for_each_intel_crtc(display->drm, crtc) { if (crtc->pch_fifo_underrun_disabled) continue; - if (HAS_PCH_CPT(dev_priv)) + if (HAS_PCH_CPT(display)) cpt_check_pch_fifo_underruns(crtc); } - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); } void intel_init_fifo_underrun_reporting(struct intel_display *display, diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c index ba2f88ca6117..43be5377ddc1 100644 --- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c +++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c @@ -58,7 +58,6 @@ #include <drm/drm_gem.h> #include "i915_active.h" -#include "i915_drv.h" #include "i915_vma.h" #include "intel_bo.h" #include "intel_display_trace.h" @@ -72,7 +71,7 @@ /** * frontbuffer_flush - flush frontbuffer - * @i915: i915 device + * @display: display device * @frontbuffer_bits: frontbuffer plane tracking bits * @origin: which operation caused the flush * @@ -82,16 +81,14 @@ * * Can be called without any locks held. */ -static void frontbuffer_flush(struct drm_i915_private *i915, +static void frontbuffer_flush(struct intel_display *display, unsigned int frontbuffer_bits, enum fb_op_origin origin) { - struct intel_display *display = &i915->display; - /* Delay flushing when rings are still busy.*/ - spin_lock(&i915->display.fb_tracking.lock); - frontbuffer_bits &= ~i915->display.fb_tracking.busy_bits; - spin_unlock(&i915->display.fb_tracking.lock); + spin_lock(&display->fb_tracking.lock); + frontbuffer_bits &= ~display->fb_tracking.busy_bits; + spin_unlock(&display->fb_tracking.lock); if (!frontbuffer_bits) return; @@ -107,7 +104,7 @@ static void frontbuffer_flush(struct drm_i915_private *i915, /** * intel_frontbuffer_flip_prepare - prepare asynchronous frontbuffer flip - * @i915: i915 device + * @display: display device * @frontbuffer_bits: frontbuffer plane tracking bits * * This function gets called after scheduling a flip on @obj. The actual @@ -117,19 +114,19 @@ static void frontbuffer_flush(struct drm_i915_private *i915, * * Can be called without any locks held. */ -void intel_frontbuffer_flip_prepare(struct drm_i915_private *i915, +void intel_frontbuffer_flip_prepare(struct intel_display *display, unsigned frontbuffer_bits) { - spin_lock(&i915->display.fb_tracking.lock); - i915->display.fb_tracking.flip_bits |= frontbuffer_bits; + spin_lock(&display->fb_tracking.lock); + display->fb_tracking.flip_bits |= frontbuffer_bits; /* Remove stale busy bits due to the old buffer. */ - i915->display.fb_tracking.busy_bits &= ~frontbuffer_bits; - spin_unlock(&i915->display.fb_tracking.lock); + display->fb_tracking.busy_bits &= ~frontbuffer_bits; + spin_unlock(&display->fb_tracking.lock); } /** * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flip - * @i915: i915 device + * @display: display device * @frontbuffer_bits: frontbuffer plane tracking bits * * This function gets called after the flip has been latched and will complete @@ -137,22 +134,22 @@ void intel_frontbuffer_flip_prepare(struct drm_i915_private *i915, * * Can be called without any locks held. */ -void intel_frontbuffer_flip_complete(struct drm_i915_private *i915, +void intel_frontbuffer_flip_complete(struct intel_display *display, unsigned frontbuffer_bits) { - spin_lock(&i915->display.fb_tracking.lock); + spin_lock(&display->fb_tracking.lock); /* Mask any cancelled flips. */ - frontbuffer_bits &= i915->display.fb_tracking.flip_bits; - i915->display.fb_tracking.flip_bits &= ~frontbuffer_bits; - spin_unlock(&i915->display.fb_tracking.lock); + frontbuffer_bits &= display->fb_tracking.flip_bits; + display->fb_tracking.flip_bits &= ~frontbuffer_bits; + spin_unlock(&display->fb_tracking.lock); if (frontbuffer_bits) - frontbuffer_flush(i915, frontbuffer_bits, ORIGIN_FLIP); + frontbuffer_flush(display, frontbuffer_bits, ORIGIN_FLIP); } /** * intel_frontbuffer_flip - synchronous frontbuffer flip - * @i915: i915 device + * @display: display device * @frontbuffer_bits: frontbuffer plane tracking bits * * This function gets called after scheduling a flip on @obj. This is for @@ -161,15 +158,15 @@ void intel_frontbuffer_flip_complete(struct drm_i915_private *i915, * * Can be called without any locks held. */ -void intel_frontbuffer_flip(struct drm_i915_private *i915, +void intel_frontbuffer_flip(struct intel_display *display, unsigned frontbuffer_bits) { - spin_lock(&i915->display.fb_tracking.lock); + spin_lock(&display->fb_tracking.lock); /* Remove stale busy bits due to the old buffer. */ - i915->display.fb_tracking.busy_bits &= ~frontbuffer_bits; - spin_unlock(&i915->display.fb_tracking.lock); + display->fb_tracking.busy_bits &= ~frontbuffer_bits; + spin_unlock(&display->fb_tracking.lock); - frontbuffer_flush(i915, frontbuffer_bits, ORIGIN_FLIP); + frontbuffer_flush(display, frontbuffer_bits, ORIGIN_FLIP); } void __intel_fb_invalidate(struct intel_frontbuffer *front, @@ -198,7 +195,6 @@ void __intel_fb_flush(struct intel_frontbuffer *front, unsigned int frontbuffer_bits) { struct intel_display *display = to_intel_display(front->obj->dev); - struct drm_i915_private *i915 = to_i915(display->drm); if (origin == ORIGIN_CS) { spin_lock(&display->fb_tracking.lock); @@ -209,7 +205,7 @@ void __intel_fb_flush(struct intel_frontbuffer *front, } if (frontbuffer_bits) - frontbuffer_flush(i915, frontbuffer_bits, origin); + frontbuffer_flush(display, frontbuffer_bits, origin); } static void intel_frontbuffer_flush_work(struct work_struct *work) @@ -280,7 +276,7 @@ static void frontbuffer_release(struct kref *ref) struct intel_frontbuffer * intel_frontbuffer_get(struct drm_gem_object *obj) { - struct drm_i915_private *i915 = to_i915(obj->dev); + struct intel_display *display = to_intel_display(obj->dev); struct intel_frontbuffer *front, *cur; front = intel_bo_get_frontbuffer(obj); @@ -300,9 +296,9 @@ intel_frontbuffer_get(struct drm_gem_object *obj) I915_ACTIVE_RETIRE_SLEEPS); INIT_WORK(&front->flush_work, intel_frontbuffer_flush_work); - spin_lock(&i915->display.fb_tracking.lock); + spin_lock(&display->fb_tracking.lock); cur = intel_bo_set_frontbuffer(obj, front); - spin_unlock(&i915->display.fb_tracking.lock); + spin_unlock(&display->fb_tracking.lock); if (cur != front) kfree(front); return cur; diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.h b/drivers/gpu/drm/i915/display/intel_frontbuffer.h index 6237780a9f68..2fee12eaf9b6 100644 --- a/drivers/gpu/drm/i915/display/intel_frontbuffer.h +++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.h @@ -31,7 +31,7 @@ #include "i915_active_types.h" struct drm_gem_object; -struct drm_i915_private; +struct intel_display; enum fb_op_origin { ORIGIN_CPU = 0, @@ -68,11 +68,11 @@ struct intel_frontbuffer { GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \ INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) -void intel_frontbuffer_flip_prepare(struct drm_i915_private *i915, +void intel_frontbuffer_flip_prepare(struct intel_display *display, unsigned frontbuffer_bits); -void intel_frontbuffer_flip_complete(struct drm_i915_private *i915, +void intel_frontbuffer_flip_complete(struct intel_display *display, unsigned frontbuffer_bits); -void intel_frontbuffer_flip(struct drm_i915_private *i915, +void intel_frontbuffer_flip(struct intel_display *display, unsigned frontbuffer_bits); void intel_frontbuffer_put(struct intel_frontbuffer *front); diff --git a/drivers/gpu/drm/i915/display/intel_global_state.c b/drivers/gpu/drm/i915/display/intel_global_state.c index 8a49e2bb37fa..000a898c9480 100644 --- a/drivers/gpu/drm/i915/display/intel_global_state.c +++ b/drivers/gpu/drm/i915/display/intel_global_state.c @@ -3,10 +3,13 @@ * Copyright © 2020 Intel Corporation */ +#include <linux/pci.h> #include <linux/string.h> -#include "i915_drv.h" +#include <drm/drm_print.h> + #include "intel_atomic.h" +#include "intel_display_core.h" #include "intel_display_types.h" #include "intel_global_state.h" diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index abf457e68ee9..0d73f32fe7f1 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -37,6 +37,7 @@ #include "i915_irq.h" #include "i915_reg.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_gmbus.h" #include "intel_gmbus_regs.h" @@ -152,32 +153,31 @@ static const struct gmbus_pin gmbus_pins_mtp[] = { static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display, unsigned int pin) { - struct drm_i915_private *i915 = to_i915(display->drm); const struct gmbus_pin *pins; size_t size; - if (INTEL_PCH_TYPE(i915) >= PCH_MTL) { + if (INTEL_PCH_TYPE(display) >= PCH_MTL) { pins = gmbus_pins_mtp; size = ARRAY_SIZE(gmbus_pins_mtp); - } else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) { + } else if (INTEL_PCH_TYPE(display) >= PCH_DG2) { pins = gmbus_pins_dg2; size = ARRAY_SIZE(gmbus_pins_dg2); - } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { + } else if (INTEL_PCH_TYPE(display) >= PCH_DG1) { pins = gmbus_pins_dg1; size = ARRAY_SIZE(gmbus_pins_dg1); - } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { + } else if (INTEL_PCH_TYPE(display) >= PCH_ICP) { pins = gmbus_pins_icp; size = ARRAY_SIZE(gmbus_pins_icp); - } else if (HAS_PCH_CNP(i915)) { + } else if (HAS_PCH_CNP(display)) { pins = gmbus_pins_cnp; size = ARRAY_SIZE(gmbus_pins_cnp); - } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { + } else if (display->platform.geminilake || display->platform.broxton) { pins = gmbus_pins_bxt; size = ARRAY_SIZE(gmbus_pins_bxt); } else if (DISPLAY_VER(display) == 9) { pins = gmbus_pins_skl; size = ARRAY_SIZE(gmbus_pins_skl); - } else if (IS_BROADWELL(i915)) { + } else if (display->platform.broadwell) { pins = gmbus_pins_bdw; size = ARRAY_SIZE(gmbus_pins_bdw); } else { @@ -240,11 +240,10 @@ static void bxt_gmbus_clock_gating(struct intel_display *display, static u32 get_reserved(struct intel_gmbus *bus) { struct intel_display *display = bus->display; - struct drm_i915_private *i915 = to_i915(display->drm); u32 reserved = 0; /* On most chips, these bits must be preserved in software. */ - if (!IS_I830(i915) && !IS_I845G(i915)) + if (!display->platform.i830 && !display->platform.i845g) reserved = intel_de_read_notrace(display, bus->gpio_reg) & (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE); @@ -314,11 +313,10 @@ intel_gpio_pre_xfer(struct i2c_adapter *adapter) { struct intel_gmbus *bus = to_intel_gmbus(adapter); struct intel_display *display = bus->display; - struct drm_i915_private *i915 = to_i915(display->drm); intel_gmbus_reset(display); - if (IS_PINEVIEW(i915)) + if (display->platform.pineview) pnv_gmbus_clock_gating(display, false); set_data(bus, 1); @@ -332,12 +330,11 @@ intel_gpio_post_xfer(struct i2c_adapter *adapter) { struct intel_gmbus *bus = to_intel_gmbus(adapter); struct intel_display *display = bus->display; - struct drm_i915_private *i915 = to_i915(display->drm); set_data(bus, 1); set_clock(bus, 1); - if (IS_PINEVIEW(i915)) + if (display->platform.pineview) pnv_gmbus_clock_gating(display, true); } @@ -418,7 +415,7 @@ gmbus_wait_idle(struct intel_display *display) add_wait_queue(&display->gmbus.wait_queue, &wait); intel_de_write_fw(display, GMBUS4(display), irq_enable); - ret = intel_de_wait_fw(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10); + ret = intel_de_wait_fw(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10, NULL); intel_de_write_fw(display, GMBUS4(display), 0); remove_wait_queue(&display->gmbus.wait_queue, &wait); @@ -630,14 +627,13 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, { struct intel_gmbus *bus = to_intel_gmbus(adapter); struct intel_display *display = bus->display; - struct drm_i915_private *i915 = to_i915(display->drm); int i = 0, inc, try = 0; int ret = 0; /* Display WA #0868: skl,bxt,kbl,cfl,glk */ - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) + if (display->platform.geminilake || display->platform.broxton) bxt_gmbus_clock_gating(display, false); - else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) + else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display)) pch_gmbus_clock_gating(display, false); retry: @@ -748,9 +744,9 @@ timeout: out: /* Display WA #0868: skl,bxt,kbl,cfl,glk */ - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) + if (display->platform.geminilake || display->platform.broxton) bxt_gmbus_clock_gating(display, true); - else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) + else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display)) pch_gmbus_clock_gating(display, true); return ret; @@ -873,12 +869,11 @@ static const struct i2c_lock_operations gmbus_lock_ops = { */ int intel_gmbus_setup(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); struct pci_dev *pdev = to_pci_dev(display->drm->dev); unsigned int pin; int ret; - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) + if (display->platform.valleyview || display->platform.cherryview) display->gmbus.mmio_base = VLV_DISPLAY_BASE; else if (!HAS_GMCH(display)) /* @@ -925,7 +920,7 @@ int intel_gmbus_setup(struct intel_display *display) bus->reg0 = pin | GMBUS_RATE_100KHZ; /* gmbus seems to be broken on i830 */ - if (IS_I830(i915)) + if (display->platform.i830) bus->force_bit = 1; intel_gpio_setup(bus, GPIO(display, gmbus_pin->gpio)); diff --git a/drivers/gpu/drm/i915/display/intel_gmbus_regs.h b/drivers/gpu/drm/i915/display/intel_gmbus_regs.h index 59bad1dda6d6..ab750562566b 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus_regs.h +++ b/drivers/gpu/drm/i915/display/intel_gmbus_regs.h @@ -6,7 +6,7 @@ #ifndef __INTEL_GMBUS_REGS_H__ #define __INTEL_GMBUS_REGS_H__ -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" #define __GMBUS_MMIO_BASE(__display) ((__display)->gmbus.mmio_base) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 411f17655f89..5235e4162555 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -22,15 +22,19 @@ #include "intel_de.h" #include "intel_display_power.h" #include "intel_display_power_well.h" +#include "intel_display_regs.h" #include "intel_display_rpm.h" #include "intel_display_types.h" #include "intel_dp_mst.h" #include "intel_hdcp.h" #include "intel_hdcp_gsc.h" +#include "intel_hdcp_gsc_message.h" #include "intel_hdcp_regs.h" #include "intel_hdcp_shim.h" #include "intel_pcode.h" +#define USE_HDCP_GSC(__display) (DISPLAY_VER(__display) >= 14) + #define KEY_LOAD_TRIES 5 #define HDCP2_LC_RETRY_CNT 3 @@ -250,8 +254,8 @@ static bool intel_hdcp2_prerequisite(struct intel_connector *connector) return false; /* If MTL+ make sure gsc is loaded and proxy is setup */ - if (intel_hdcp_gsc_cs_required(display)) { - if (!intel_hdcp_gsc_check_status(display)) + if (USE_HDCP_GSC(display)) { + if (!intel_hdcp_gsc_check_status(display->drm)) return false; } @@ -2339,7 +2343,7 @@ static int initialize_hdcp_port_data(struct intel_connector *connector, static bool is_hdcp2_supported(struct intel_display *display) { - if (intel_hdcp_gsc_cs_required(display)) + if (USE_HDCP_GSC(display)) return true; if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP)) @@ -2363,7 +2367,7 @@ void intel_hdcp_component_init(struct intel_display *display) display->hdcp.comp_added = true; mutex_unlock(&display->hdcp.hdcp_mutex); - if (intel_hdcp_gsc_cs_required(display)) + if (USE_HDCP_GSC(display)) ret = intel_hdcp_gsc_init(display); else ret = component_add_typed(display->drm->dev, &i915_hdcp_ops, @@ -2638,7 +2642,7 @@ void intel_hdcp_component_fini(struct intel_display *display) display->hdcp.comp_added = false; mutex_unlock(&display->hdcp.hdcp_mutex); - if (intel_hdcp_gsc_cs_required(display)) + if (USE_HDCP_GSC(display)) intel_hdcp_gsc_fini(display); else component_del(display->drm->dev, &i915_hdcp_ops); diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c index 55965844d829..6a22862d6be1 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c @@ -11,27 +11,22 @@ #include "i915_drv.h" #include "i915_utils.h" #include "intel_hdcp_gsc.h" -#include "intel_hdcp_gsc_message.h" -struct intel_hdcp_gsc_message { +struct intel_hdcp_gsc_context { + struct drm_i915_private *i915; struct i915_vma *vma; void *hdcp_cmd_in; void *hdcp_cmd_out; }; -bool intel_hdcp_gsc_cs_required(struct intel_display *display) +bool intel_hdcp_gsc_check_status(struct drm_device *drm) { - return DISPLAY_VER(display) >= 14; -} - -bool intel_hdcp_gsc_check_status(struct intel_display *display) -{ - struct drm_i915_private *i915 = to_i915(display->drm); + struct drm_i915_private *i915 = to_i915(drm); struct intel_gt *gt = i915->media_gt; struct intel_gsc_uc *gsc = gt ? >->uc.gsc : NULL; if (!gsc || !intel_uc_fw_is_running(&gsc->fw)) { - drm_dbg_kms(display->drm, + drm_dbg_kms(&i915->drm, "GSC components required for HDCP2.2 are not ready\n"); return false; } @@ -41,7 +36,7 @@ bool intel_hdcp_gsc_check_status(struct intel_display *display) /*This function helps allocate memory for the command that we will send to gsc cs */ static int intel_hdcp_gsc_initialize_message(struct drm_i915_private *i915, - struct intel_hdcp_gsc_message *hdcp_message) + struct intel_hdcp_gsc_context *gsc_context) { struct intel_gt *gt = i915->media_gt; struct drm_i915_gem_object *obj = NULL; @@ -78,9 +73,10 @@ static int intel_hdcp_gsc_initialize_message(struct drm_i915_private *i915, memset(cmd_in, 0, obj->base.size); - hdcp_message->hdcp_cmd_in = cmd_in; - hdcp_message->hdcp_cmd_out = cmd_out; - hdcp_message->vma = vma; + gsc_context->hdcp_cmd_in = cmd_in; + gsc_context->hdcp_cmd_out = cmd_out; + gsc_context->vma = vma; + gsc_context->i915 = i915; return 0; @@ -91,80 +87,37 @@ out_unpin: return err; } -static const struct i915_hdcp_ops gsc_hdcp_ops = { - .initiate_hdcp2_session = intel_hdcp_gsc_initiate_session, - .verify_receiver_cert_prepare_km = - intel_hdcp_gsc_verify_receiver_cert_prepare_km, - .verify_hprime = intel_hdcp_gsc_verify_hprime, - .store_pairing_info = intel_hdcp_gsc_store_pairing_info, - .initiate_locality_check = intel_hdcp_gsc_initiate_locality_check, - .verify_lprime = intel_hdcp_gsc_verify_lprime, - .get_session_key = intel_hdcp_gsc_get_session_key, - .repeater_check_flow_prepare_ack = - intel_hdcp_gsc_repeater_check_flow_prepare_ack, - .verify_mprime = intel_hdcp_gsc_verify_mprime, - .enable_hdcp_authentication = intel_hdcp_gsc_enable_authentication, - .close_hdcp_session = intel_hdcp_gsc_close_session, -}; - -static int intel_hdcp_gsc_hdcp2_init(struct intel_display *display) +struct intel_hdcp_gsc_context *intel_hdcp_gsc_context_alloc(struct drm_device *drm) { - struct drm_i915_private *i915 = to_i915(display->drm); - struct intel_hdcp_gsc_message *hdcp_message; + struct drm_i915_private *i915 = to_i915(drm); + struct intel_hdcp_gsc_context *gsc_context; int ret; - hdcp_message = kzalloc(sizeof(*hdcp_message), GFP_KERNEL); - - if (!hdcp_message) - return -ENOMEM; + gsc_context = kzalloc(sizeof(*gsc_context), GFP_KERNEL); + if (!gsc_context) + return ERR_PTR(-ENOMEM); /* * NOTE: No need to lock the comp mutex here as it is already * going to be taken before this function called */ - display->hdcp.hdcp_message = hdcp_message; - ret = intel_hdcp_gsc_initialize_message(i915, hdcp_message); - - if (ret) - drm_err(display->drm, "Could not initialize hdcp_message\n"); - - return ret; -} - -static void intel_hdcp_gsc_free_message(struct intel_display *display) -{ - struct intel_hdcp_gsc_message *hdcp_message = - display->hdcp.hdcp_message; + ret = intel_hdcp_gsc_initialize_message(i915, gsc_context); + if (ret) { + drm_err(&i915->drm, "Could not initialize gsc_context\n"); + kfree(gsc_context); + gsc_context = ERR_PTR(ret); + } - hdcp_message->hdcp_cmd_in = NULL; - hdcp_message->hdcp_cmd_out = NULL; - i915_vma_unpin_and_release(&hdcp_message->vma, I915_VMA_RELEASE_MAP); - kfree(hdcp_message); + return gsc_context; } -int intel_hdcp_gsc_init(struct intel_display *display) +void intel_hdcp_gsc_context_free(struct intel_hdcp_gsc_context *gsc_context) { - struct i915_hdcp_arbiter *data; - int ret; - - data = kzalloc(sizeof(struct i915_hdcp_arbiter), GFP_KERNEL); - if (!data) - return -ENOMEM; + if (!gsc_context) + return; - mutex_lock(&display->hdcp.hdcp_mutex); - display->hdcp.arbiter = data; - display->hdcp.arbiter->hdcp_dev = display->drm->dev; - display->hdcp.arbiter->ops = &gsc_hdcp_ops; - ret = intel_hdcp_gsc_hdcp2_init(display); - mutex_unlock(&display->hdcp.hdcp_mutex); - - return ret; -} - -void intel_hdcp_gsc_fini(struct intel_display *display) -{ - intel_hdcp_gsc_free_message(display); - kfree(display->hdcp.arbiter); + i915_vma_unpin_and_release(&gsc_context->vma, I915_VMA_RELEASE_MAP); + kfree(gsc_context); } static int intel_gsc_send_sync(struct drm_i915_private *i915, @@ -211,18 +164,18 @@ static int intel_gsc_send_sync(struct drm_i915_private *i915, /* * This function can now be used for sending requests and will also handle * receipt of reply messages hence no different function of message retrieval - * is required. We will initialize intel_hdcp_gsc_message structure then add + * is required. We will initialize intel_hdcp_gsc_context structure then add * gsc cs memory header as stated in specs after which the normal HDCP payload * will follow */ -ssize_t intel_hdcp_gsc_msg_send(struct drm_i915_private *i915, u8 *msg_in, - size_t msg_in_len, u8 *msg_out, - size_t msg_out_len) +ssize_t intel_hdcp_gsc_msg_send(struct intel_hdcp_gsc_context *gsc_context, + void *msg_in, size_t msg_in_len, + void *msg_out, size_t msg_out_len) { + struct drm_i915_private *i915 = gsc_context->i915; struct intel_gt *gt = i915->media_gt; struct intel_gsc_mtl_header *header_in, *header_out; const size_t max_msg_size = PAGE_SIZE - sizeof(*header_in); - struct intel_hdcp_gsc_message *hdcp_message; u64 addr_in, addr_out, host_session_id; u32 reply_size, msg_size_in, msg_size_out; int ret, tries = 0; @@ -235,10 +188,9 @@ ssize_t intel_hdcp_gsc_msg_send(struct drm_i915_private *i915, u8 *msg_in, msg_size_in = msg_in_len + sizeof(*header_in); msg_size_out = msg_out_len + sizeof(*header_out); - hdcp_message = i915->display.hdcp.hdcp_message; - header_in = hdcp_message->hdcp_cmd_in; - header_out = hdcp_message->hdcp_cmd_out; - addr_in = i915_ggtt_offset(hdcp_message->vma); + header_in = gsc_context->hdcp_cmd_in; + header_out = gsc_context->hdcp_cmd_out; + addr_in = i915_ggtt_offset(gsc_context->vma); addr_out = addr_in + PAGE_SIZE; memset(header_in, 0, msg_size_in); @@ -246,7 +198,7 @@ ssize_t intel_hdcp_gsc_msg_send(struct drm_i915_private *i915, u8 *msg_in, get_random_bytes(&host_session_id, sizeof(u64)); intel_gsc_uc_heci_cmd_emit_mtl_header(header_in, HECI_MEADDRESS_HDCP, msg_size_in, host_session_id); - memcpy(hdcp_message->hdcp_cmd_in + sizeof(*header_in), msg_in, msg_in_len); + memcpy(gsc_context->hdcp_cmd_in + sizeof(*header_in), msg_in, msg_in_len); /* * Keep sending request in case the pending bit is set no need to add @@ -280,7 +232,7 @@ ssize_t intel_hdcp_gsc_msg_send(struct drm_i915_private *i915, u8 *msg_in, reply_size, (u32)msg_out_len); } - memcpy(msg_out, hdcp_message->hdcp_cmd_out + sizeof(*header_out), msg_out_len); + memcpy(msg_out, gsc_context->hdcp_cmd_out + sizeof(*header_out), msg_out_len); err: return ret; diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h index 5695a5e4f609..9305c14aaffe 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h +++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h @@ -6,19 +6,17 @@ #ifndef __INTEL_HDCP_GSC_H__ #define __INTEL_HDCP_GSC_H__ -#include <linux/err.h> #include <linux/types.h> -struct drm_i915_private; -struct intel_display; -struct intel_hdcp_gsc_message; +struct drm_device; +struct intel_hdcp_gsc_context; -bool intel_hdcp_gsc_cs_required(struct intel_display *display); -ssize_t intel_hdcp_gsc_msg_send(struct drm_i915_private *i915, u8 *msg_in, - size_t msg_in_len, u8 *msg_out, - size_t msg_out_len); -int intel_hdcp_gsc_init(struct intel_display *display); -void intel_hdcp_gsc_fini(struct intel_display *display); -bool intel_hdcp_gsc_check_status(struct intel_display *display); +ssize_t intel_hdcp_gsc_msg_send(struct intel_hdcp_gsc_context *gsc_context, + void *msg_in, size_t msg_in_len, + void *msg_out, size_t msg_out_len); +bool intel_hdcp_gsc_check_status(struct drm_device *drm); + +struct intel_hdcp_gsc_context *intel_hdcp_gsc_context_alloc(struct drm_device *drm); +void intel_hdcp_gsc_context_free(struct intel_hdcp_gsc_context *gsc_context); #endif /* __INTEL_HDCP_GCS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c index 129104fa9b16..98967bb148e3 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c @@ -4,20 +4,23 @@ */ #include <linux/err.h> + +#include <drm/drm_print.h> #include <drm/intel/i915_hdcp_interface.h> -#include "i915_drv.h" +#include "intel_display_core.h" #include "intel_display_types.h" +#include "intel_hdcp_gsc.h" #include "intel_hdcp_gsc_message.h" -int +static int intel_hdcp_gsc_initiate_session(struct device *dev, struct hdcp_port_data *data, struct hdcp2_ake_init *ake_data) { struct wired_cmd_initiate_hdcp2_session_in session_init_in = {}; struct wired_cmd_initiate_hdcp2_session_out session_init_out = {}; + struct intel_hdcp_gsc_context *gsc_context; struct intel_display *display; - struct drm_i915_private *i915; ssize_t byte; if (!dev || !data || !ake_data) @@ -28,7 +31,7 @@ intel_hdcp_gsc_initiate_session(struct device *dev, struct hdcp_port_data *data, dev_err(dev, "DRM not initialized, aborting HDCP.\n"); return -ENODEV; } - i915 = to_i915(display->drm); + gsc_context = display->hdcp.gsc_context; session_init_in.header.api_version = HDCP_API_VERSION; session_init_in.header.command_id = WIRED_INITIATE_HDCP2_SESSION; @@ -41,9 +44,9 @@ intel_hdcp_gsc_initiate_session(struct device *dev, struct hdcp_port_data *data, session_init_in.port.attached_transcoder = (u8)data->hdcp_transcoder; session_init_in.protocol = data->protocol; - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&session_init_in, + byte = intel_hdcp_gsc_msg_send(gsc_context, &session_init_in, sizeof(session_init_in), - (u8 *)&session_init_out, + &session_init_out, sizeof(session_init_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); @@ -64,7 +67,7 @@ intel_hdcp_gsc_initiate_session(struct device *dev, struct hdcp_port_data *data, return 0; } -int +static int intel_hdcp_gsc_verify_receiver_cert_prepare_km(struct device *dev, struct hdcp_port_data *data, struct hdcp2_ake_send_cert *rx_cert, @@ -75,8 +78,8 @@ intel_hdcp_gsc_verify_receiver_cert_prepare_km(struct device *dev, { struct wired_cmd_verify_receiver_cert_in verify_rxcert_in = {}; struct wired_cmd_verify_receiver_cert_out verify_rxcert_out = {}; + struct intel_hdcp_gsc_context *gsc_context; struct intel_display *display; - struct drm_i915_private *i915; ssize_t byte; if (!dev || !data || !rx_cert || !km_stored || !ek_pub_km || !msg_sz) @@ -87,7 +90,7 @@ intel_hdcp_gsc_verify_receiver_cert_prepare_km(struct device *dev, dev_err(dev, "DRM not initialized, aborting HDCP.\n"); return -ENODEV; } - i915 = to_i915(display->drm); + gsc_context = display->hdcp.gsc_context; verify_rxcert_in.header.api_version = HDCP_API_VERSION; verify_rxcert_in.header.command_id = WIRED_VERIFY_RECEIVER_CERT; @@ -103,9 +106,9 @@ intel_hdcp_gsc_verify_receiver_cert_prepare_km(struct device *dev, memcpy(verify_rxcert_in.r_rx, &rx_cert->r_rx, HDCP_2_2_RRX_LEN); memcpy(verify_rxcert_in.rx_caps, rx_cert->rx_caps, HDCP_2_2_RXCAPS_LEN); - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&verify_rxcert_in, + byte = intel_hdcp_gsc_msg_send(gsc_context, &verify_rxcert_in, sizeof(verify_rxcert_in), - (u8 *)&verify_rxcert_out, + &verify_rxcert_out, sizeof(verify_rxcert_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed: %zd\n", byte); @@ -134,14 +137,14 @@ intel_hdcp_gsc_verify_receiver_cert_prepare_km(struct device *dev, return 0; } -int +static int intel_hdcp_gsc_verify_hprime(struct device *dev, struct hdcp_port_data *data, struct hdcp2_ake_send_hprime *rx_hprime) { struct wired_cmd_ake_send_hprime_in send_hprime_in = {}; struct wired_cmd_ake_send_hprime_out send_hprime_out = {}; + struct intel_hdcp_gsc_context *gsc_context; struct intel_display *display; - struct drm_i915_private *i915; ssize_t byte; if (!dev || !data || !rx_hprime) @@ -152,7 +155,7 @@ intel_hdcp_gsc_verify_hprime(struct device *dev, struct hdcp_port_data *data, dev_err(dev, "DRM not initialized, aborting HDCP.\n"); return -ENODEV; } - i915 = to_i915(display->drm); + gsc_context = display->hdcp.gsc_context; send_hprime_in.header.api_version = HDCP_API_VERSION; send_hprime_in.header.command_id = WIRED_AKE_SEND_HPRIME; @@ -166,9 +169,9 @@ intel_hdcp_gsc_verify_hprime(struct device *dev, struct hdcp_port_data *data, memcpy(send_hprime_in.h_prime, rx_hprime->h_prime, HDCP_2_2_H_PRIME_LEN); - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&send_hprime_in, + byte = intel_hdcp_gsc_msg_send(gsc_context, &send_hprime_in, sizeof(send_hprime_in), - (u8 *)&send_hprime_out, + &send_hprime_out, sizeof(send_hprime_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); @@ -184,14 +187,14 @@ intel_hdcp_gsc_verify_hprime(struct device *dev, struct hdcp_port_data *data, return 0; } -int +static int intel_hdcp_gsc_store_pairing_info(struct device *dev, struct hdcp_port_data *data, struct hdcp2_ake_send_pairing_info *pairing_info) { struct wired_cmd_ake_send_pairing_info_in pairing_info_in = {}; struct wired_cmd_ake_send_pairing_info_out pairing_info_out = {}; + struct intel_hdcp_gsc_context *gsc_context; struct intel_display *display; - struct drm_i915_private *i915; ssize_t byte; if (!dev || !data || !pairing_info) @@ -202,7 +205,7 @@ intel_hdcp_gsc_store_pairing_info(struct device *dev, struct hdcp_port_data *dat dev_err(dev, "DRM not initialized, aborting HDCP.\n"); return -ENODEV; } - i915 = to_i915(display->drm); + gsc_context = display->hdcp.gsc_context; pairing_info_in.header.api_version = HDCP_API_VERSION; pairing_info_in.header.command_id = WIRED_AKE_SEND_PAIRING_INFO; @@ -217,9 +220,9 @@ intel_hdcp_gsc_store_pairing_info(struct device *dev, struct hdcp_port_data *dat memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km, HDCP_2_2_E_KH_KM_LEN); - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&pairing_info_in, + byte = intel_hdcp_gsc_msg_send(gsc_context, &pairing_info_in, sizeof(pairing_info_in), - (u8 *)&pairing_info_out, + &pairing_info_out, sizeof(pairing_info_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); @@ -236,15 +239,15 @@ intel_hdcp_gsc_store_pairing_info(struct device *dev, struct hdcp_port_data *dat return 0; } -int +static int intel_hdcp_gsc_initiate_locality_check(struct device *dev, struct hdcp_port_data *data, struct hdcp2_lc_init *lc_init_data) { struct wired_cmd_init_locality_check_in lc_init_in = {}; struct wired_cmd_init_locality_check_out lc_init_out = {}; + struct intel_hdcp_gsc_context *gsc_context; struct intel_display *display; - struct drm_i915_private *i915; ssize_t byte; if (!dev || !data || !lc_init_data) @@ -255,7 +258,7 @@ intel_hdcp_gsc_initiate_locality_check(struct device *dev, dev_err(dev, "DRM not initialized, aborting HDCP.\n"); return -ENODEV; } - i915 = to_i915(display->drm); + gsc_context = display->hdcp.gsc_context; lc_init_in.header.api_version = HDCP_API_VERSION; lc_init_in.header.command_id = WIRED_INIT_LOCALITY_CHECK; @@ -266,8 +269,8 @@ intel_hdcp_gsc_initiate_locality_check(struct device *dev, lc_init_in.port.physical_port = (u8)data->hdcp_ddi; lc_init_in.port.attached_transcoder = (u8)data->hdcp_transcoder; - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&lc_init_in, sizeof(lc_init_in), - (u8 *)&lc_init_out, sizeof(lc_init_out)); + byte = intel_hdcp_gsc_msg_send(gsc_context, &lc_init_in, sizeof(lc_init_in), + &lc_init_out, sizeof(lc_init_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); return byte; @@ -285,14 +288,14 @@ intel_hdcp_gsc_initiate_locality_check(struct device *dev, return 0; } -int +static int intel_hdcp_gsc_verify_lprime(struct device *dev, struct hdcp_port_data *data, struct hdcp2_lc_send_lprime *rx_lprime) { struct wired_cmd_validate_locality_in verify_lprime_in = {}; struct wired_cmd_validate_locality_out verify_lprime_out = {}; + struct intel_hdcp_gsc_context *gsc_context; struct intel_display *display; - struct drm_i915_private *i915; ssize_t byte; if (!dev || !data || !rx_lprime) @@ -303,7 +306,7 @@ intel_hdcp_gsc_verify_lprime(struct device *dev, struct hdcp_port_data *data, dev_err(dev, "DRM not initialized, aborting HDCP.\n"); return -ENODEV; } - i915 = to_i915(display->drm); + gsc_context = display->hdcp.gsc_context; verify_lprime_in.header.api_version = HDCP_API_VERSION; verify_lprime_in.header.command_id = WIRED_VALIDATE_LOCALITY; @@ -318,9 +321,9 @@ intel_hdcp_gsc_verify_lprime(struct device *dev, struct hdcp_port_data *data, memcpy(verify_lprime_in.l_prime, rx_lprime->l_prime, HDCP_2_2_L_PRIME_LEN); - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&verify_lprime_in, + byte = intel_hdcp_gsc_msg_send(gsc_context, &verify_lprime_in, sizeof(verify_lprime_in), - (u8 *)&verify_lprime_out, + &verify_lprime_out, sizeof(verify_lprime_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); @@ -337,14 +340,15 @@ intel_hdcp_gsc_verify_lprime(struct device *dev, struct hdcp_port_data *data, return 0; } -int intel_hdcp_gsc_get_session_key(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_ske_send_eks *ske_data) +static int +intel_hdcp_gsc_get_session_key(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_ske_send_eks *ske_data) { struct wired_cmd_get_session_key_in get_skey_in = {}; struct wired_cmd_get_session_key_out get_skey_out = {}; + struct intel_hdcp_gsc_context *gsc_context; struct intel_display *display; - struct drm_i915_private *i915; ssize_t byte; if (!dev || !data || !ske_data) @@ -355,7 +359,7 @@ int intel_hdcp_gsc_get_session_key(struct device *dev, dev_err(dev, "DRM not initialized, aborting HDCP.\n"); return -ENODEV; } - i915 = to_i915(display->drm); + gsc_context = display->hdcp.gsc_context; get_skey_in.header.api_version = HDCP_API_VERSION; get_skey_in.header.command_id = WIRED_GET_SESSION_KEY; @@ -366,8 +370,8 @@ int intel_hdcp_gsc_get_session_key(struct device *dev, get_skey_in.port.physical_port = (u8)data->hdcp_ddi; get_skey_in.port.attached_transcoder = (u8)data->hdcp_transcoder; - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&get_skey_in, sizeof(get_skey_in), - (u8 *)&get_skey_out, sizeof(get_skey_out)); + byte = intel_hdcp_gsc_msg_send(gsc_context, &get_skey_in, sizeof(get_skey_in), + &get_skey_out, sizeof(get_skey_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); return byte; @@ -387,7 +391,7 @@ int intel_hdcp_gsc_get_session_key(struct device *dev, return 0; } -int +static int intel_hdcp_gsc_repeater_check_flow_prepare_ack(struct device *dev, struct hdcp_port_data *data, struct hdcp2_rep_send_receiverid_list @@ -397,8 +401,8 @@ intel_hdcp_gsc_repeater_check_flow_prepare_ack(struct device *dev, { struct wired_cmd_verify_repeater_in verify_repeater_in = {}; struct wired_cmd_verify_repeater_out verify_repeater_out = {}; + struct intel_hdcp_gsc_context *gsc_context; struct intel_display *display; - struct drm_i915_private *i915; ssize_t byte; if (!dev || !rep_topology || !rep_send_ack || !data) @@ -409,7 +413,7 @@ intel_hdcp_gsc_repeater_check_flow_prepare_ack(struct device *dev, dev_err(dev, "DRM not initialized, aborting HDCP.\n"); return -ENODEV; } - i915 = to_i915(display->drm); + gsc_context = display->hdcp.gsc_context; verify_repeater_in.header.api_version = HDCP_API_VERSION; verify_repeater_in.header.command_id = WIRED_VERIFY_REPEATER; @@ -430,9 +434,9 @@ intel_hdcp_gsc_repeater_check_flow_prepare_ack(struct device *dev, memcpy(verify_repeater_in.receiver_ids, rep_topology->receiver_ids, HDCP_2_2_RECEIVER_IDS_MAX_LEN); - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&verify_repeater_in, + byte = intel_hdcp_gsc_msg_send(gsc_context, &verify_repeater_in, sizeof(verify_repeater_in), - (u8 *)&verify_repeater_out, + &verify_repeater_out, sizeof(verify_repeater_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); @@ -453,14 +457,15 @@ intel_hdcp_gsc_repeater_check_flow_prepare_ack(struct device *dev, return 0; } -int intel_hdcp_gsc_verify_mprime(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_rep_stream_ready *stream_ready) +static int +intel_hdcp_gsc_verify_mprime(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_rep_stream_ready *stream_ready) { struct wired_cmd_repeater_auth_stream_req_in *verify_mprime_in; struct wired_cmd_repeater_auth_stream_req_out verify_mprime_out = {}; + struct intel_hdcp_gsc_context *gsc_context; struct intel_display *display; - struct drm_i915_private *i915; ssize_t byte; size_t cmd_size; @@ -472,7 +477,7 @@ int intel_hdcp_gsc_verify_mprime(struct device *dev, dev_err(dev, "DRM not initialized, aborting HDCP.\n"); return -ENODEV; } - i915 = to_i915(display->drm); + gsc_context = display->hdcp.gsc_context; cmd_size = struct_size(verify_mprime_in, streams, data->k); if (cmd_size == SIZE_MAX) @@ -499,8 +504,8 @@ int intel_hdcp_gsc_verify_mprime(struct device *dev, verify_mprime_in->k = cpu_to_be16(data->k); - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)verify_mprime_in, cmd_size, - (u8 *)&verify_mprime_out, + byte = intel_hdcp_gsc_msg_send(gsc_context, verify_mprime_in, cmd_size, + &verify_mprime_out, sizeof(verify_mprime_out)); kfree(verify_mprime_in); if (byte < 0) { @@ -518,13 +523,13 @@ int intel_hdcp_gsc_verify_mprime(struct device *dev, return 0; } -int intel_hdcp_gsc_enable_authentication(struct device *dev, - struct hdcp_port_data *data) +static int intel_hdcp_gsc_enable_authentication(struct device *dev, + struct hdcp_port_data *data) { struct wired_cmd_enable_auth_in enable_auth_in = {}; struct wired_cmd_enable_auth_out enable_auth_out = {}; + struct intel_hdcp_gsc_context *gsc_context; struct intel_display *display; - struct drm_i915_private *i915; ssize_t byte; if (!dev || !data) @@ -535,7 +540,7 @@ int intel_hdcp_gsc_enable_authentication(struct device *dev, dev_err(dev, "DRM not initialized, aborting HDCP.\n"); return -ENODEV; } - i915 = to_i915(display->drm); + gsc_context = display->hdcp.gsc_context; enable_auth_in.header.api_version = HDCP_API_VERSION; enable_auth_in.header.command_id = WIRED_ENABLE_AUTH; @@ -547,9 +552,9 @@ int intel_hdcp_gsc_enable_authentication(struct device *dev, enable_auth_in.port.attached_transcoder = (u8)data->hdcp_transcoder; enable_auth_in.stream_type = data->streams[0].stream_type; - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&enable_auth_in, + byte = intel_hdcp_gsc_msg_send(gsc_context, &enable_auth_in, sizeof(enable_auth_in), - (u8 *)&enable_auth_out, + &enable_auth_out, sizeof(enable_auth_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); @@ -565,13 +570,13 @@ int intel_hdcp_gsc_enable_authentication(struct device *dev, return 0; } -int +static int intel_hdcp_gsc_close_session(struct device *dev, struct hdcp_port_data *data) { struct wired_cmd_close_session_in session_close_in = {}; struct wired_cmd_close_session_out session_close_out = {}; + struct intel_hdcp_gsc_context *gsc_context; struct intel_display *display; - struct drm_i915_private *i915; ssize_t byte; if (!dev || !data) @@ -582,7 +587,7 @@ intel_hdcp_gsc_close_session(struct device *dev, struct hdcp_port_data *data) dev_err(dev, "DRM not initialized, aborting HDCP.\n"); return -ENODEV; } - i915 = to_i915(display->drm); + gsc_context = display->hdcp.gsc_context; session_close_in.header.api_version = HDCP_API_VERSION; session_close_in.header.command_id = WIRED_CLOSE_SESSION; @@ -594,9 +599,9 @@ intel_hdcp_gsc_close_session(struct device *dev, struct hdcp_port_data *data) session_close_in.port.physical_port = (u8)data->hdcp_ddi; session_close_in.port.attached_transcoder = (u8)data->hdcp_transcoder; - byte = intel_hdcp_gsc_msg_send(i915, (u8 *)&session_close_in, + byte = intel_hdcp_gsc_msg_send(gsc_context, &session_close_in, sizeof(session_close_in), - (u8 *)&session_close_out, + &session_close_out, sizeof(session_close_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); @@ -611,3 +616,57 @@ intel_hdcp_gsc_close_session(struct device *dev, struct hdcp_port_data *data) return 0; } + +static const struct i915_hdcp_ops gsc_hdcp_ops = { + .initiate_hdcp2_session = intel_hdcp_gsc_initiate_session, + .verify_receiver_cert_prepare_km = + intel_hdcp_gsc_verify_receiver_cert_prepare_km, + .verify_hprime = intel_hdcp_gsc_verify_hprime, + .store_pairing_info = intel_hdcp_gsc_store_pairing_info, + .initiate_locality_check = intel_hdcp_gsc_initiate_locality_check, + .verify_lprime = intel_hdcp_gsc_verify_lprime, + .get_session_key = intel_hdcp_gsc_get_session_key, + .repeater_check_flow_prepare_ack = + intel_hdcp_gsc_repeater_check_flow_prepare_ack, + .verify_mprime = intel_hdcp_gsc_verify_mprime, + .enable_hdcp_authentication = intel_hdcp_gsc_enable_authentication, + .close_hdcp_session = intel_hdcp_gsc_close_session, +}; + +int intel_hdcp_gsc_init(struct intel_display *display) +{ + struct intel_hdcp_gsc_context *gsc_context; + struct i915_hdcp_arbiter *arbiter; + int ret = 0; + + arbiter = kzalloc(sizeof(*arbiter), GFP_KERNEL); + if (!arbiter) + return -ENOMEM; + + mutex_lock(&display->hdcp.hdcp_mutex); + + gsc_context = intel_hdcp_gsc_context_alloc(display->drm); + if (IS_ERR(gsc_context)) { + ret = PTR_ERR(gsc_context); + kfree(arbiter); + goto out; + } + + display->hdcp.arbiter = arbiter; + display->hdcp.arbiter->hdcp_dev = display->drm->dev; + display->hdcp.arbiter->ops = &gsc_hdcp_ops; + display->hdcp.gsc_context = gsc_context; + +out: + mutex_unlock(&display->hdcp.hdcp_mutex); + + return ret; +} + +void intel_hdcp_gsc_fini(struct intel_display *display) +{ + intel_hdcp_gsc_context_free(display->hdcp.gsc_context); + display->hdcp.gsc_context = NULL; + kfree(display->hdcp.arbiter); + display->hdcp.arbiter = NULL; +} diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.h b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.h index 2d597f27e931..9f54157a4a3e 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.h +++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.h @@ -6,68 +6,9 @@ #ifndef __INTEL_HDCP_GSC_MESSAGE_H__ #define __INTEL_HDCP_GSC_MESSAGE_H__ -#include <linux/types.h> - -struct device; -struct drm_i915_private; -struct hdcp_port_data; -struct hdcp2_ake_init; -struct hdcp2_ake_send_cert; -struct hdcp2_ake_no_stored_km; -struct hdcp2_ake_send_hprime; -struct hdcp2_ake_send_pairing_info; -struct hdcp2_lc_init; -struct hdcp2_lc_send_lprime; -struct hdcp2_ske_send_eks; -struct hdcp2_rep_send_receiverid_list; -struct hdcp2_rep_send_ack; -struct hdcp2_rep_stream_ready; struct intel_display; -ssize_t intel_hdcp_gsc_msg_send(struct drm_i915_private *i915, u8 *msg_in, - size_t msg_in_len, u8 *msg_out, - size_t msg_out_len); -bool intel_hdcp_gsc_check_status(struct intel_display *display); -int -intel_hdcp_gsc_initiate_session(struct device *dev, struct hdcp_port_data *data, - struct hdcp2_ake_init *ake_data); -int -intel_hdcp_gsc_verify_receiver_cert_prepare_km(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_ake_send_cert *rx_cert, - bool *km_stored, - struct hdcp2_ake_no_stored_km - *ek_pub_km, - size_t *msg_sz); -int -intel_hdcp_gsc_verify_hprime(struct device *dev, struct hdcp_port_data *data, - struct hdcp2_ake_send_hprime *rx_hprime); -int -intel_hdcp_gsc_store_pairing_info(struct device *dev, struct hdcp_port_data *data, - struct hdcp2_ake_send_pairing_info *pairing_info); -int -intel_hdcp_gsc_initiate_locality_check(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_lc_init *lc_init_data); -int -intel_hdcp_gsc_verify_lprime(struct device *dev, struct hdcp_port_data *data, - struct hdcp2_lc_send_lprime *rx_lprime); -int intel_hdcp_gsc_get_session_key(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_ske_send_eks *ske_data); -int -intel_hdcp_gsc_repeater_check_flow_prepare_ack(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_rep_send_receiverid_list - *rep_topology, - struct hdcp2_rep_send_ack - *rep_send_ack); -int intel_hdcp_gsc_verify_mprime(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_rep_stream_ready *stream_ready); -int intel_hdcp_gsc_enable_authentication(struct device *dev, - struct hdcp_port_data *data); -int -intel_hdcp_gsc_close_session(struct device *dev, struct hdcp_port_data *data); +int intel_hdcp_gsc_init(struct intel_display *display); +void intel_hdcp_gsc_fini(struct intel_display *display); #endif /* __INTEL_HDCP_GSC_MESSAGE_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index f9fa17e1f584..9961ff259298 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -38,14 +38,13 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> #include <drm/drm_edid.h> +#include <drm/drm_print.h> #include <drm/drm_probe_helper.h> #include <drm/intel/intel_lpe_audio.h> - #include <media/cec-notifier.h> #include "g4x_hdmi.h" -#include "i915_drv.h" -#include "i915_reg.h" +#include "i915_utils.h" #include "intel_atomic.h" #include "intel_audio.h" #include "intel_connector.h" @@ -53,6 +52,7 @@ #include "intel_ddi.h" #include "intel_de.h" #include "intel_display_driver.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_gmbus.h" @@ -715,7 +715,7 @@ intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - struct drm_connector *connector = conn_state->connector; + struct intel_connector *connector = to_intel_connector(conn_state->connector); int ret; if (!crtc_state->has_infoframe) @@ -724,7 +724,7 @@ intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); - ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, + ret = drm_hdmi_avi_infoframe_from_display_mode(frame, &connector->base, adjusted_mode); if (ret) return false; @@ -743,7 +743,7 @@ intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { - drm_hdmi_avi_infoframe_quant_range(frame, connector, + drm_hdmi_avi_infoframe_quant_range(frame, &connector->base, adjusted_mode, crtc_state->limited_color_range ? HDMI_QUANTIZATION_RANGE_LIMITED : @@ -769,7 +769,7 @@ intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(crtc_state); struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; int ret; @@ -779,7 +779,7 @@ intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); - if (IS_DGFX(i915)) + if (display->platform.dgfx) ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx"); else ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); @@ -979,7 +979,6 @@ static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, const struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); i915_reg_t reg; @@ -989,9 +988,9 @@ static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, if (HAS_DDI(display)) reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); - else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + else if (display->platform.valleyview || display->platform.cherryview) reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); - else if (HAS_PCH_SPLIT(dev_priv)) + else if (HAS_PCH_SPLIT(display)) reg = TVIDEO_DIP_GCP(crtc->pipe); else return false; @@ -1005,7 +1004,6 @@ void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); i915_reg_t reg; @@ -1015,9 +1013,9 @@ void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, if (HAS_DDI(display)) reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); - else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + else if (display->platform.valleyview || display->platform.cherryview) reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); - else if (HAS_PCH_SPLIT(dev_priv)) + else if (HAS_PCH_SPLIT(display)) reg = TVIDEO_DIP_GCP(crtc->pipe); else return; @@ -1029,9 +1027,9 @@ static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); - if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) + if (display->platform.g4x || !crtc_state->has_infoframe) return; crtc_state->infoframes.enable |= @@ -1539,7 +1537,6 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, struct intel_display *display = to_intel_display(dig_port); struct intel_hdmi *hdmi = &dig_port->hdmi; struct intel_connector *connector = hdmi->attached_connector; - struct drm_i915_private *dev_priv = to_i915(connector->base.dev); int ret; if (!enable) @@ -1558,7 +1555,7 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, * WA: To fix incorrect positioning of the window of * opportunity and enc_en signalling in KABYLAKE. */ - if (IS_KABYLAKE(dev_priv) && enable) + if (display->platform.kabylake && enable) return kbl_repositioning_enc_en_signal(connector, cpu_transcoder); @@ -1570,7 +1567,6 @@ bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port, struct intel_connector *connector) { struct intel_display *display = to_intel_display(dig_port); - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); enum port port = dig_port->base.port; enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; int ret; @@ -1583,15 +1579,15 @@ bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port, if (ret) return false; - intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg); + intel_de_write(display, HDCP_RPRIME(display, cpu_transcoder, port), ri.reg); /* Wait for Ri prime match */ - if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & + if (wait_for((intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)) & (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) == (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n", - intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, - port))); + intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, + port))); return false; } return true; @@ -1814,14 +1810,13 @@ static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); int max_tmds_clock, vbt_max_tmds_clock; - if (DISPLAY_VER(display) >= 13 || IS_ALDERLAKE_S(dev_priv)) + if (DISPLAY_VER(display) >= 13 || display->platform.alderlake_s) max_tmds_clock = 600000; else if (DISPLAY_VER(display) >= 10) max_tmds_clock = 594000; - else if (DISPLAY_VER(display) >= 8 || IS_HASWELL(dev_priv)) + else if (DISPLAY_VER(display) >= 8 || display->platform.haswell) max_tmds_clock = 300000; else if (DISPLAY_VER(display) >= 5) max_tmds_clock = 225000; @@ -1880,7 +1875,6 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, bool has_hdmi_sink) { struct intel_display *display = to_intel_display(hdmi); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; if (clock < 25000) @@ -1890,16 +1884,16 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, return MODE_CLOCK_HIGH; /* GLK DPLL can't generate 446-480 MHz */ - if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000) + if (display->platform.geminilake && clock > 446666 && clock < 480000) return MODE_CLOCK_RANGE; /* BXT/GLK DPLL can't generate 223-240 MHz */ - if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && + if ((display->platform.geminilake || display->platform.broxton) && clock > 223333 && clock < 240000) return MODE_CLOCK_RANGE; /* CHV DPLL can't generate 216-240 MHz */ - if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) + if (display->platform.cherryview && clock > 216000 && clock < 240000) return MODE_CLOCK_RANGE; /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ @@ -1943,11 +1937,12 @@ static bool intel_hdmi_source_bpc_possible(struct intel_display *display, int bp } } -static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector, +static bool intel_hdmi_sink_bpc_possible(struct drm_connector *_connector, int bpc, bool has_hdmi_sink, enum intel_output_format sink_format) { - const struct drm_display_info *info = &connector->display_info; + struct intel_connector *connector = to_intel_connector(_connector); + const struct drm_display_info *info = &connector->base.display_info; const struct drm_hdmi_info *hdmi = &info->hdmi; switch (bpc) { @@ -1976,12 +1971,13 @@ static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector, } static enum drm_mode_status -intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock, +intel_hdmi_mode_clock_valid(struct drm_connector *_connector, int clock, bool has_hdmi_sink, enum intel_output_format sink_format) { - struct intel_display *display = to_intel_display(connector->dev); - struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); + struct intel_connector *connector = to_intel_connector(_connector); + struct intel_display *display = to_intel_display(connector); + struct intel_hdmi *hdmi = intel_attached_hdmi(connector); enum drm_mode_status status = MODE_OK; int bpc; @@ -1996,7 +1992,8 @@ intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock, if (!intel_hdmi_source_bpc_possible(display, bpc)) continue; - if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, sink_format)) + if (!intel_hdmi_sink_bpc_possible(&connector->base, bpc, has_hdmi_sink, + sink_format)) continue; status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink); @@ -2011,15 +2008,16 @@ intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock, } static enum drm_mode_status -intel_hdmi_mode_valid(struct drm_connector *connector, +intel_hdmi_mode_valid(struct drm_connector *_connector, const struct drm_display_mode *mode) { - struct intel_display *display = to_intel_display(connector->dev); - struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); + struct intel_connector *connector = to_intel_connector(_connector); + struct intel_display *display = to_intel_display(connector); + struct intel_hdmi *hdmi = intel_attached_hdmi(connector); enum drm_mode_status status; int clock = mode->clock; - int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq; - bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); + int max_dotclk = display->cdclk.max_dotclk_freq; + bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->base.state); bool ycbcr_420_only; enum intel_output_format sink_format; @@ -2048,22 +2046,23 @@ intel_hdmi_mode_valid(struct drm_connector *connector, if (clock > 600000) return MODE_CLOCK_HIGH; - ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode); + ycbcr_420_only = drm_mode_is_420_only(&connector->base.display_info, mode); if (ycbcr_420_only) sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; else sink_format = INTEL_OUTPUT_FORMAT_RGB; - status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); + status = intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format); if (status != MODE_OK) { if (ycbcr_420_only || - !connector->ycbcr_420_allowed || - !drm_mode_is_420_also(&connector->display_info, mode)) + !connector->base.ycbcr_420_allowed || + !drm_mode_is_420_also(&connector->base.display_info, mode)) return status; sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; - status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); + status = intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink, + sink_format); if (status != MODE_OK) return status; } @@ -2074,16 +2073,16 @@ intel_hdmi_mode_valid(struct drm_connector *connector, bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc, bool has_hdmi_sink) { - struct drm_atomic_state *state = crtc_state->uapi.state; - struct drm_connector_state *connector_state; - struct drm_connector *connector; + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); + struct intel_digital_connector_state *connector_state; + struct intel_connector *connector; int i; - for_each_new_connector_in_state(state, connector, connector_state, i) { - if (connector_state->crtc != crtc_state->uapi.crtc) + for_each_new_intel_connector_in_state(state, connector, connector_state, i) { + if (connector_state->base.crtc != crtc_state->uapi.crtc) continue; - if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, + if (!intel_hdmi_sink_bpc_possible(&connector->base, bpc, has_hdmi_sink, crtc_state->sink_format)) return false; } @@ -2211,7 +2210,7 @@ static bool intel_hdmi_has_audio(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { - struct drm_connector *connector = conn_state->connector; + struct intel_connector *connector = to_intel_connector(conn_state->connector); const struct intel_digital_connector_state *intel_conn_state = to_intel_digital_connector_state(conn_state); @@ -2219,7 +2218,7 @@ static bool intel_hdmi_has_audio(struct intel_encoder *encoder, return false; if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) - return connector->display_info.has_audio; + return connector->base.display_info.has_audio; else return intel_conn_state->force_audio == HDMI_AUDIO_ON; } @@ -2323,14 +2322,14 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder, { struct intel_display *display = to_intel_display(encoder); struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; - struct drm_connector *connector = conn_state->connector; - struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; + struct intel_connector *connector = to_intel_connector(conn_state->connector); + struct drm_scdc *scdc = &connector->base.display_info.hdmi.scdc; int ret; if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) return -EINVAL; - if (!connector->interlace_allowed && + if (!connector->base.interlace_allowed && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) return -EINVAL; @@ -2425,25 +2424,26 @@ void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder) } static void -intel_hdmi_unset_edid(struct drm_connector *connector) +intel_hdmi_unset_edid(struct drm_connector *_connector) { - struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); + struct intel_connector *connector = to_intel_connector(_connector); + struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; intel_hdmi->dp_dual_mode.max_tmds_clock = 0; - drm_edid_free(to_intel_connector(connector)->detect_edid); - to_intel_connector(connector)->detect_edid = NULL; + drm_edid_free(connector->detect_edid); + connector->detect_edid = NULL; } static void -intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector) +intel_hdmi_dp_dual_mode_detect(struct drm_connector *_connector) { - struct intel_display *display = to_intel_display(connector->dev); - struct drm_i915_private *dev_priv = to_i915(connector->dev); - struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); + struct intel_connector *connector = to_intel_connector(_connector); + struct intel_display *display = to_intel_display(connector); + struct intel_hdmi *hdmi = intel_attached_hdmi(connector); struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; - struct i2c_adapter *ddc = connector->ddc; + struct i2c_adapter *ddc = connector->base.ddc; enum drm_dp_dual_mode_type type; type = drm_dp_dual_mode_detect(display->drm, ddc); @@ -2458,7 +2458,7 @@ intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector) * if the port is a dual mode capable DP port. */ if (type == DRM_DP_DUAL_MODE_UNKNOWN) { - if (!connector->force && + if (!connector->base.force && intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { drm_dbg_kms(display->drm, "Assuming DP dual mode adaptor presence based on VBT\n"); @@ -2481,7 +2481,7 @@ intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector) hdmi->dp_dual_mode.max_tmds_clock); /* Older VBTs are often buggy and can't be trusted :( Play it safe. */ - if ((DISPLAY_VER(display) >= 8 || IS_HASWELL(dev_priv)) && + if ((DISPLAY_VER(display) >= 8 || display->platform.haswell) && !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { drm_dbg_kms(display->drm, "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n"); @@ -2490,34 +2490,35 @@ intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector) } static bool -intel_hdmi_set_edid(struct drm_connector *connector) +intel_hdmi_set_edid(struct drm_connector *_connector) { - struct intel_display *display = to_intel_display(connector->dev); - struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); - struct i2c_adapter *ddc = connector->ddc; + struct intel_connector *connector = to_intel_connector(_connector); + struct intel_display *display = to_intel_display(connector); + struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); + struct i2c_adapter *ddc = connector->base.ddc; intel_wakeref_t wakeref; const struct drm_edid *drm_edid; bool connected = false; wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); - drm_edid = drm_edid_read_ddc(connector, ddc); + drm_edid = drm_edid_read_ddc(&connector->base, ddc); if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) { drm_dbg_kms(display->drm, "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); intel_gmbus_force_bit(ddc, true); - drm_edid = drm_edid_read_ddc(connector, ddc); + drm_edid = drm_edid_read_ddc(&connector->base, ddc); intel_gmbus_force_bit(ddc, false); } /* Below we depend on display info having been updated */ - drm_edid_connector_update(connector, drm_edid); + drm_edid_connector_update(&connector->base, drm_edid); - to_intel_connector(connector)->detect_edid = drm_edid; + connector->detect_edid = drm_edid; if (drm_edid_is_digital(drm_edid)) { - intel_hdmi_dp_dual_mode_detect(connector); + intel_hdmi_dp_dual_mode_detect(&connector->base); connected = true; } @@ -2525,28 +2526,29 @@ intel_hdmi_set_edid(struct drm_connector *connector) intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); cec_notifier_set_phys_addr(intel_hdmi->cec_notifier, - connector->display_info.source_physical_address); + connector->base.display_info.source_physical_address); return connected; } static enum drm_connector_status -intel_hdmi_detect(struct drm_connector *connector, bool force) +intel_hdmi_detect(struct drm_connector *_connector, bool force) { - struct intel_display *display = to_intel_display(connector->dev); + struct intel_connector *connector = to_intel_connector(_connector); + struct intel_display *display = to_intel_display(connector); enum drm_connector_status status = connector_status_disconnected; - struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); + struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; intel_wakeref_t wakeref; drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", - connector->base.id, connector->name); + connector->base.base.id, connector->base.name); if (!intel_display_device_enabled(display)) return connector_status_disconnected; if (!intel_display_driver_check_access(display)) - return connector->status; + return connector->base.status; wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); @@ -2554,9 +2556,9 @@ intel_hdmi_detect(struct drm_connector *connector, bool force) !intel_digital_port_connected(encoder)) goto out; - intel_hdmi_unset_edid(connector); + intel_hdmi_unset_edid(&connector->base); - if (intel_hdmi_set_edid(connector)) + if (intel_hdmi_set_edid(&connector->base)) status = connector_status_connected; out: @@ -2569,49 +2571,54 @@ out: } static void -intel_hdmi_force(struct drm_connector *connector) +intel_hdmi_force(struct drm_connector *_connector) { - struct intel_display *display = to_intel_display(connector->dev); + struct intel_connector *connector = to_intel_connector(_connector); + struct intel_display *display = to_intel_display(connector); drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", - connector->base.id, connector->name); + connector->base.base.id, connector->base.name); if (!intel_display_driver_check_access(display)) return; - intel_hdmi_unset_edid(connector); + intel_hdmi_unset_edid(&connector->base); - if (connector->status != connector_status_connected) + if (connector->base.status != connector_status_connected) return; - intel_hdmi_set_edid(connector); + intel_hdmi_set_edid(&connector->base); } -static int intel_hdmi_get_modes(struct drm_connector *connector) +static int intel_hdmi_get_modes(struct drm_connector *_connector) { + struct intel_connector *connector = to_intel_connector(_connector); + /* drm_edid_connector_update() done in ->detect() or ->force() */ - return drm_edid_connector_add_modes(connector); + return drm_edid_connector_add_modes(&connector->base); } static int -intel_hdmi_connector_register(struct drm_connector *connector) +intel_hdmi_connector_register(struct drm_connector *_connector) { + struct intel_connector *connector = to_intel_connector(_connector); int ret; - ret = intel_connector_register(connector); + ret = intel_connector_register(&connector->base); if (ret) return ret; return ret; } -static void intel_hdmi_connector_unregister(struct drm_connector *connector) +static void intel_hdmi_connector_unregister(struct drm_connector *_connector) { - struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; + struct intel_connector *connector = to_intel_connector(_connector); + struct cec_notifier *n = intel_attached_hdmi(connector)->cec_notifier; cec_notifier_conn_unregister(n); - intel_connector_unregister(connector); + intel_connector_unregister(&connector->base); } static const struct drm_connector_funcs intel_hdmi_connector_funcs = { @@ -2627,15 +2634,16 @@ static const struct drm_connector_funcs intel_hdmi_connector_funcs = { .atomic_duplicate_state = intel_digital_connector_duplicate_state, }; -static int intel_hdmi_connector_atomic_check(struct drm_connector *connector, +static int intel_hdmi_connector_atomic_check(struct drm_connector *_connector, struct drm_atomic_state *state) { - struct intel_display *display = to_intel_display(connector->dev); + struct intel_connector *connector = to_intel_connector(_connector); + struct intel_display *display = to_intel_display(connector); if (HAS_DDI(display)) - return intel_digital_connector_atomic_check(connector, state); + return intel_digital_connector_atomic_check(&connector->base, state); else - return g4x_hdmi_connector_atomic_check(connector, state); + return g4x_hdmi_connector_atomic_check(&connector->base, state); } static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { @@ -2645,22 +2653,23 @@ static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs }; static void -intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) +intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *_connector) { + struct intel_connector *connector = to_intel_connector(_connector); struct intel_display *display = to_intel_display(intel_hdmi); - intel_attach_force_audio_property(connector); - intel_attach_broadcast_rgb_property(connector); - intel_attach_aspect_ratio_property(connector); + intel_attach_force_audio_property(&connector->base); + intel_attach_broadcast_rgb_property(&connector->base); + intel_attach_aspect_ratio_property(&connector->base); - intel_attach_hdmi_colorspace_property(connector); - drm_connector_attach_content_type_property(connector); + intel_attach_hdmi_colorspace_property(&connector->base); + drm_connector_attach_content_type_property(&connector->base); if (DISPLAY_VER(display) >= 10) - drm_connector_attach_hdr_output_metadata_property(connector); + drm_connector_attach_hdr_output_metadata_property(&connector->base); if (!HAS_GMCH(display)) - drm_connector_attach_max_bpc_property(connector, 8, 12); + drm_connector_attach_max_bpc_property(&connector->base, 8, 12); } /* @@ -2682,25 +2691,26 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *c * True on success, false on failure. */ bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, - struct drm_connector *connector, + struct drm_connector *_connector, bool high_tmds_clock_ratio, bool scrambling) { + struct intel_connector *connector = to_intel_connector(_connector); struct intel_display *display = to_intel_display(encoder); struct drm_scrambling *sink_scrambling = - &connector->display_info.hdmi.scdc.scrambling; + &connector->base.display_info.hdmi.scdc.scrambling; if (!sink_scrambling->supported) return true; drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", - connector->base.id, connector->name, + connector->base.base.id, connector->base.name, str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10); /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ - return drm_scdc_set_high_tmds_clock_ratio(connector, high_tmds_clock_ratio) && - drm_scdc_set_scrambling(connector, scrambling); + return drm_scdc_set_high_tmds_clock_ratio(&connector->base, high_tmds_clock_ratio) && + drm_scdc_set_scrambling(&connector->base, scrambling); } static u8 chv_encoder_to_ddc_pin(struct intel_encoder *encoder) @@ -2811,7 +2821,7 @@ static u8 mcc_encoder_to_ddc_pin(struct intel_encoder *encoder) static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); WARN_ON(encoder->port == PORT_C); @@ -2822,7 +2832,7 @@ static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder) * combo outputs. With CMP, the traditional DDI A-D pins are used for * all outputs. */ - if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C) + if (INTEL_PCH_TYPE(display) >= PCH_TGP && phy >= PHY_C) return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; return GMBUS_PIN_1_BXT + phy; @@ -2831,7 +2841,6 @@ static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder) static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_encoder_to_phy(encoder); drm_WARN_ON(display->drm, encoder->port == PORT_A); @@ -2842,7 +2851,7 @@ static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder) * combo outputs. With CMP, the traditional DDI A-D pins are used for * all outputs. */ - if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C) + if (INTEL_PCH_TYPE(display) >= PCH_TGP && phy >= PHY_C) return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; return GMBUS_PIN_1_BXT + phy; @@ -2895,27 +2904,26 @@ static u8 g4x_encoder_to_ddc_pin(struct intel_encoder *encoder) static u8 intel_hdmi_default_ddc_pin(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u8 ddc_pin; - if (IS_ALDERLAKE_S(dev_priv)) + if (display->platform.alderlake_s) ddc_pin = adls_encoder_to_ddc_pin(encoder); - else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) + else if (INTEL_PCH_TYPE(display) >= PCH_DG1) ddc_pin = dg1_encoder_to_ddc_pin(encoder); - else if (IS_ROCKETLAKE(dev_priv)) + else if (display->platform.rocketlake) ddc_pin = rkl_encoder_to_ddc_pin(encoder); - else if (DISPLAY_VER(display) == 9 && HAS_PCH_TGP(dev_priv)) + else if (DISPLAY_VER(display) == 9 && HAS_PCH_TGP(display)) ddc_pin = gen9bc_tgp_encoder_to_ddc_pin(encoder); - else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && - HAS_PCH_TGP(dev_priv)) + else if ((display->platform.jasperlake || display->platform.elkhartlake) && + HAS_PCH_TGP(display)) ddc_pin = mcc_encoder_to_ddc_pin(encoder); - else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) + else if (INTEL_PCH_TYPE(display) >= PCH_ICP) ddc_pin = icl_encoder_to_ddc_pin(encoder); - else if (HAS_PCH_CNP(dev_priv)) + else if (HAS_PCH_CNP(display)) ddc_pin = cnp_encoder_to_ddc_pin(encoder); - else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) + else if (display->platform.geminilake || display->platform.broxton) ddc_pin = bxt_encoder_to_ddc_pin(encoder); - else if (IS_CHERRYVIEW(dev_priv)) + else if (display->platform.cherryview) ddc_pin = chv_encoder_to_ddc_pin(encoder); else ddc_pin = g4x_encoder_to_ddc_pin(encoder); @@ -2989,15 +2997,13 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) void intel_infoframe_init(struct intel_digital_port *dig_port) { struct intel_display *display = to_intel_display(dig_port); - struct drm_i915_private *dev_priv = - to_i915(dig_port->base.base.dev); - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { + if (display->platform.valleyview || display->platform.cherryview) { dig_port->write_infoframe = vlv_write_infoframe; dig_port->read_infoframe = vlv_read_infoframe; dig_port->set_infoframes = vlv_set_infoframes; dig_port->infoframes_enabled = vlv_infoframes_enabled; - } else if (IS_G4X(dev_priv)) { + } else if (display->platform.g4x) { dig_port->write_infoframe = g4x_write_infoframe; dig_port->read_infoframe = g4x_read_infoframe; dig_port->set_infoframes = g4x_set_infoframes; @@ -3014,7 +3020,7 @@ void intel_infoframe_init(struct intel_digital_port *dig_port) dig_port->set_infoframes = hsw_set_infoframes; dig_port->infoframes_enabled = hsw_infoframes_enabled; } - } else if (HAS_PCH_IBX(dev_priv)) { + } else if (HAS_PCH_IBX(display)) { dig_port->write_infoframe = ibx_write_infoframe; dig_port->read_infoframe = ibx_read_infoframe; dig_port->set_infoframes = ibx_set_infoframes; diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c index 6885e5a09079..901fda434af1 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c @@ -30,8 +30,10 @@ #include "i915_irq.h" #include "intel_connector.h" #include "intel_display_power.h" +#include "intel_display_core.h" #include "intel_display_rpm.h" #include "intel_display_types.h" +#include "intel_dp.h" #include "intel_hdcp.h" #include "intel_hotplug.h" #include "intel_hotplug_irq.h" @@ -183,9 +185,7 @@ static bool intel_hpd_irq_storm_detect(struct intel_display *display, static bool detection_work_enabled(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - - lockdep_assert_held(&i915->irq_lock); + lockdep_assert_held(&display->irq.lock); return display->hotplug.detection_work_enabled; } @@ -195,7 +195,7 @@ mod_delayed_detection_work(struct intel_display *display, struct delayed_work *w { struct drm_i915_private *i915 = to_i915(display->drm); - lockdep_assert_held(&i915->irq_lock); + lockdep_assert_held(&display->irq.lock); if (!detection_work_enabled(display)) return false; @@ -208,7 +208,7 @@ queue_delayed_detection_work(struct intel_display *display, struct delayed_work { struct drm_i915_private *i915 = to_i915(display->drm); - lockdep_assert_held(&i915->irq_lock); + lockdep_assert_held(&display->irq.lock); if (!detection_work_enabled(display)) return false; @@ -221,7 +221,7 @@ queue_detection_work(struct intel_display *display, struct work_struct *work) { struct drm_i915_private *i915 = to_i915(display->drm); - lockdep_assert_held(&i915->irq_lock); + lockdep_assert_held(&display->irq.lock); if (!detection_work_enabled(display)) return false; @@ -232,12 +232,11 @@ queue_detection_work(struct intel_display *display, struct work_struct *work) static void intel_hpd_irq_storm_switch_to_polling(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct drm_connector_list_iter conn_iter; struct intel_connector *connector; bool hpd_disabled = false; - lockdep_assert_held(&dev_priv->irq_lock); + lockdep_assert_held(&display->irq.lock); drm_connector_list_iter_begin(display->drm, &conn_iter); for_each_intel_connector_iter(connector, &conn_iter) { @@ -276,7 +275,6 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work) { struct intel_display *display = container_of(work, typeof(*display), hotplug.reenable_work.work); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct drm_connector_list_iter conn_iter; struct intel_connector *connector; struct ref_tracker *wakeref; @@ -284,7 +282,7 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work) wakeref = intel_display_rpm_get(display); - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); drm_connector_list_iter_begin(display->drm, &conn_iter); for_each_intel_connector_iter(connector, &conn_iter) { @@ -308,7 +306,7 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work) intel_hpd_irq_setup(display); - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); intel_display_rpm_put(display, wakeref); } @@ -376,9 +374,7 @@ static bool hpd_pin_has_pulse(struct intel_display *display, enum hpd_pin pin) static bool hpd_pin_is_blocked(struct intel_display *display, enum hpd_pin pin) { - struct drm_i915_private *i915 = to_i915(display->drm); - - lockdep_assert_held(&i915->irq_lock); + lockdep_assert_held(&display->irq.lock); return display->hotplug.stats[pin].blocked_count; } @@ -400,14 +396,13 @@ static void i915_digport_work_func(struct work_struct *work) { struct intel_display *display = container_of(work, struct intel_display, hotplug.dig_port_work); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_hotplug *hotplug = &display->hotplug; u32 long_hpd_pin_mask, short_hpd_pin_mask; struct intel_encoder *encoder; u32 blocked_hpd_pin_mask; u32 old_bits = 0; - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); blocked_hpd_pin_mask = get_blocked_hpd_pin_mask(display); long_hpd_pin_mask = hotplug->long_hpd_pin_mask & ~blocked_hpd_pin_mask; @@ -415,7 +410,7 @@ static void i915_digport_work_func(struct work_struct *work) short_hpd_pin_mask = hotplug->short_hpd_pin_mask & ~blocked_hpd_pin_mask; hotplug->short_hpd_pin_mask &= ~short_hpd_pin_mask; - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); for_each_intel_encoder(display->drm, encoder) { struct intel_digital_port *dig_port; @@ -442,11 +437,11 @@ static void i915_digport_work_func(struct work_struct *work) } if (old_bits) { - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); display->hotplug.event_bits |= old_bits; queue_delayed_detection_work(display, &display->hotplug.hotplug_work, 0); - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); } } @@ -460,17 +455,16 @@ static void i915_digport_work_func(struct work_struct *work) void intel_hpd_trigger_irq(struct intel_digital_port *dig_port) { struct intel_display *display = to_intel_display(dig_port); - struct drm_i915_private *i915 = to_i915(display->drm); struct intel_hotplug *hotplug = &display->hotplug; struct intel_encoder *encoder = &dig_port->base; - spin_lock_irq(&i915->irq_lock); + spin_lock_irq(&display->irq.lock); hotplug->short_hpd_pin_mask |= BIT(encoder->hpd_pin); if (!hpd_pin_is_blocked(display, encoder->hpd_pin)) queue_work(hotplug->dp_wq, &hotplug->dig_port_work); - spin_unlock_irq(&i915->irq_lock); + spin_unlock_irq(&display->irq.lock); } /* @@ -480,7 +474,6 @@ static void i915_hotplug_work_func(struct work_struct *work) { struct intel_display *display = container_of(work, struct intel_display, hotplug.hotplug_work.work); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_hotplug *hotplug = &display->hotplug; struct drm_connector_list_iter conn_iter; struct intel_connector *connector; @@ -494,7 +487,7 @@ static void i915_hotplug_work_func(struct work_struct *work) mutex_lock(&display->drm->mode_config.mutex); drm_dbg_kms(display->drm, "running encoder hotplug functions\n"); - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); blocked_hpd_pin_mask = get_blocked_hpd_pin_mask(display); hpd_event_bits = hotplug->event_bits & ~blocked_hpd_pin_mask; @@ -505,7 +498,7 @@ static void i915_hotplug_work_func(struct work_struct *work) /* Enable polling for connectors which had HPD IRQ storms */ intel_hpd_irq_storm_switch_to_polling(display); - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); /* Skip calling encode hotplug handlers if ignore long HPD set*/ if (display->hotplug.ignore_long_hpd) { @@ -569,13 +562,13 @@ static void i915_hotplug_work_func(struct work_struct *work) /* Remove shared HPD pins that have changed */ retry &= ~changed; if (retry) { - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); display->hotplug.retry_bits |= retry; mod_delayed_detection_work(display, &display->hotplug.hotplug_work, msecs_to_jiffies(HPD_RETRY_DELAY)); - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); } } @@ -599,7 +592,6 @@ static void i915_hotplug_work_func(struct work_struct *work) void intel_hpd_irq_handler(struct intel_display *display, u32 pin_mask, u32 long_mask) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_encoder *encoder; bool storm_detected = false; bool queue_dig = false, queue_hp = false; @@ -610,7 +602,7 @@ void intel_hpd_irq_handler(struct intel_display *display, if (!pin_mask) return; - spin_lock(&dev_priv->irq_lock); + spin_lock(&display->irq.lock); /* * Determine whether ->hpd_pulse() exists for each pin, and @@ -711,7 +703,7 @@ void intel_hpd_irq_handler(struct intel_display *display, queue_delayed_detection_work(display, &display->hotplug.hotplug_work, 0); - spin_unlock(&dev_priv->irq_lock); + spin_unlock(&display->irq.lock); } /** @@ -730,7 +722,6 @@ void intel_hpd_irq_handler(struct intel_display *display, */ void intel_hpd_init(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); int i; if (!HAS_DISPLAY(display)) @@ -745,9 +736,9 @@ void intel_hpd_init(struct intel_display *display) * Interrupt setup is already guaranteed to be single-threaded, this is * just to make the assert_spin_locked checks happy. */ - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); intel_hpd_irq_setup(display); - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); } static void i915_hpd_poll_detect_connectors(struct intel_display *display) @@ -797,7 +788,6 @@ static void i915_hpd_poll_init_work(struct work_struct *work) { struct intel_display *display = container_of(work, typeof(*display), hotplug.poll_init_work); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct drm_connector_list_iter conn_iter; struct intel_connector *connector; intel_wakeref_t wakeref; @@ -820,7 +810,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work) cancel_work(&display->hotplug.poll_init_work); } - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); drm_connector_list_iter_begin(display->drm, &conn_iter); for_each_intel_connector_iter(connector, &conn_iter) { @@ -841,7 +831,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work) } drm_connector_list_iter_end(&conn_iter); - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); if (enabled) drm_kms_helper_poll_reschedule(display->drm); @@ -879,8 +869,6 @@ static void i915_hpd_poll_init_work(struct work_struct *work) */ void intel_hpd_poll_enable(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - if (!HAS_DISPLAY(display) || !intel_display_device_enabled(display)) return; @@ -892,10 +880,10 @@ void intel_hpd_poll_enable(struct intel_display *display) * As well, there's no issue if we race here since we always reschedule * this worker anyway */ - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); queue_detection_work(display, &display->hotplug.poll_init_work); - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); } /** @@ -919,17 +907,20 @@ void intel_hpd_poll_enable(struct intel_display *display) */ void intel_hpd_poll_disable(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); + struct intel_encoder *encoder; if (!HAS_DISPLAY(display)) return; + for_each_intel_dp(display->drm, encoder) + intel_dp_dpcd_set_probe(enc_to_intel_dp(encoder), true); + WRITE_ONCE(display->hotplug.poll_enabled, false); - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); queue_detection_work(display, &display->hotplug.poll_init_work); - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); } void intel_hpd_poll_fini(struct intel_display *display) @@ -981,12 +972,10 @@ static bool cancel_all_detection_work(struct intel_display *display) void intel_hpd_cancel_work(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - if (!HAS_DISPLAY(display)) return; - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); drm_WARN_ON(display->drm, get_blocked_hpd_pin_mask(display)); @@ -995,7 +984,7 @@ void intel_hpd_cancel_work(struct intel_display *display) display->hotplug.event_bits = 0; display->hotplug.retry_bits = 0; - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); cancel_work_sync(&display->hotplug.dig_port_work); @@ -1009,13 +998,12 @@ void intel_hpd_cancel_work(struct intel_display *display) static void queue_work_for_missed_irqs(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); struct intel_hotplug *hotplug = &display->hotplug; bool queue_hp_work = false; u32 blocked_hpd_pin_mask; enum hpd_pin pin; - lockdep_assert_held(&i915->irq_lock); + lockdep_assert_held(&display->irq.lock); blocked_hpd_pin_mask = get_blocked_hpd_pin_mask(display); if ((hotplug->event_bits | hotplug->retry_bits) & ~blocked_hpd_pin_mask) @@ -1043,10 +1031,9 @@ static void queue_work_for_missed_irqs(struct intel_display *display) static bool block_hpd_pin(struct intel_display *display, enum hpd_pin pin) { - struct drm_i915_private *i915 = to_i915(display->drm); struct intel_hotplug *hotplug = &display->hotplug; - lockdep_assert_held(&i915->irq_lock); + lockdep_assert_held(&display->irq.lock); hotplug->stats[pin].blocked_count++; @@ -1055,10 +1042,9 @@ static bool block_hpd_pin(struct intel_display *display, enum hpd_pin pin) static bool unblock_hpd_pin(struct intel_display *display, enum hpd_pin pin) { - struct drm_i915_private *i915 = to_i915(display->drm); struct intel_hotplug *hotplug = &display->hotplug; - lockdep_assert_held(&i915->irq_lock); + lockdep_assert_held(&display->irq.lock); if (drm_WARN_ON(display->drm, hotplug->stats[pin].blocked_count == 0)) return true; @@ -1095,19 +1081,18 @@ static bool unblock_hpd_pin(struct intel_display *display, enum hpd_pin pin) void intel_hpd_block(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *i915 = to_i915(display->drm); struct intel_hotplug *hotplug = &display->hotplug; bool do_flush = false; if (encoder->hpd_pin == HPD_NONE) return; - spin_lock_irq(&i915->irq_lock); + spin_lock_irq(&display->irq.lock); if (block_hpd_pin(display, encoder->hpd_pin)) do_flush = true; - spin_unlock_irq(&i915->irq_lock); + spin_unlock_irq(&display->irq.lock); if (do_flush && hpd_pin_has_pulse(display, encoder->hpd_pin)) flush_work(&hotplug->dig_port_work); @@ -1125,17 +1110,16 @@ void intel_hpd_block(struct intel_encoder *encoder) void intel_hpd_unblock(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *i915 = to_i915(display->drm); if (encoder->hpd_pin == HPD_NONE) return; - spin_lock_irq(&i915->irq_lock); + spin_lock_irq(&display->irq.lock); if (unblock_hpd_pin(display, encoder->hpd_pin)) queue_work_for_missed_irqs(display); - spin_unlock_irq(&i915->irq_lock); + spin_unlock_irq(&display->irq.lock); } /** @@ -1149,14 +1133,13 @@ void intel_hpd_unblock(struct intel_encoder *encoder) void intel_hpd_clear_and_unblock(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *i915 = to_i915(display->drm); struct intel_hotplug *hotplug = &display->hotplug; enum hpd_pin pin = encoder->hpd_pin; if (pin == HPD_NONE) return; - spin_lock_irq(&i915->irq_lock); + spin_lock_irq(&display->irq.lock); if (unblock_hpd_pin(display, pin)) { hotplug->event_bits &= ~BIT(pin); @@ -1165,39 +1148,34 @@ void intel_hpd_clear_and_unblock(struct intel_encoder *encoder) hotplug->long_hpd_pin_mask &= ~BIT(pin); } - spin_unlock_irq(&i915->irq_lock); + spin_unlock_irq(&display->irq.lock); } void intel_hpd_enable_detection_work(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - - spin_lock_irq(&i915->irq_lock); + spin_lock_irq(&display->irq.lock); display->hotplug.detection_work_enabled = true; queue_work_for_missed_irqs(display); - spin_unlock_irq(&i915->irq_lock); + spin_unlock_irq(&display->irq.lock); } void intel_hpd_disable_detection_work(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - - spin_lock_irq(&i915->irq_lock); + spin_lock_irq(&display->irq.lock); display->hotplug.detection_work_enabled = false; - spin_unlock_irq(&i915->irq_lock); + spin_unlock_irq(&display->irq.lock); cancel_all_detection_work(display); } bool intel_hpd_schedule_detection(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); unsigned long flags; bool ret; - spin_lock_irqsave(&i915->irq_lock, flags); + spin_lock_irqsave(&display->irq.lock, flags); ret = queue_delayed_detection_work(display, &display->hotplug.hotplug_work, 0); - spin_unlock_irqrestore(&i915->irq_lock, flags); + spin_unlock_irqrestore(&display->irq.lock, flags); return ret; } @@ -1228,7 +1206,6 @@ static ssize_t i915_hpd_storm_ctl_write(struct file *file, { struct seq_file *m = file->private_data; struct intel_display *display = m->private; - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_hotplug *hotplug = &display->hotplug; unsigned int new_threshold; int i; @@ -1260,12 +1237,12 @@ static ssize_t i915_hpd_storm_ctl_write(struct file *file, else drm_dbg_kms(display->drm, "Disabling HPD storm detection\n"); - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); hotplug->hpd_storm_threshold = new_threshold; /* Reset the HPD storm stats so we don't accidentally trigger a storm */ for_each_hpd_pin(i) hotplug->stats[i].count = 0; - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); /* Re-enable hpd immediately if we were in an irq storm */ flush_delayed_work(&display->hotplug.reenable_work); @@ -1310,7 +1287,6 @@ static ssize_t i915_hpd_short_storm_ctl_write(struct file *file, { struct seq_file *m = file->private_data; struct intel_display *display = m->private; - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_hotplug *hotplug = &display->hotplug; char *newline; char tmp[16]; @@ -1339,12 +1315,12 @@ static ssize_t i915_hpd_short_storm_ctl_write(struct file *file, drm_dbg_kms(display->drm, "%sabling HPD short storm detection\n", new_state ? "En" : "Dis"); - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); hotplug->hpd_short_storm_enabled = new_state; /* Reset the HPD storm stats so we don't accidentally trigger a storm */ for_each_hpd_pin(i) hotplug->stats[i].count = 0; - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); /* Re-enable hpd immediately if we were in an irq storm */ flush_delayed_work(&display->hotplug.reenable_work); diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c index 2463e61e7802..43aee70597bf 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c @@ -3,10 +3,13 @@ * Copyright © 2023 Intel Corporation */ -#include "i915_drv.h" +#include <drm/drm_print.h> + #include "i915_reg.h" +#include "i915_utils.h" #include "intel_de.h" #include "intel_display_irq.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dp_aux.h" #include "intel_gmbus.h" @@ -133,7 +136,6 @@ static const u32 hpd_mtp[HPD_NUM_PINS] = { static void intel_hpd_init_pins(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_hotplug *hpd = &display->hotplug; if (HAS_GMCH(display)) { @@ -160,33 +162,31 @@ static void intel_hpd_init_pins(struct intel_display *display) else hpd->hpd = hpd_ilk; - if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) && - (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))) + if ((INTEL_PCH_TYPE(display) < PCH_DG1) && + (!HAS_PCH_SPLIT(display) || HAS_PCH_NOP(display))) return; - if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL) + if (INTEL_PCH_TYPE(display) >= PCH_MTL) hpd->pch_hpd = hpd_mtp; - else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) + else if (INTEL_PCH_TYPE(display) >= PCH_DG1) hpd->pch_hpd = hpd_sde_dg1; - else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) + else if (INTEL_PCH_TYPE(display) >= PCH_ICP) hpd->pch_hpd = hpd_icp; - else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv)) + else if (HAS_PCH_CNP(display) || HAS_PCH_SPT(display)) hpd->pch_hpd = hpd_spt; - else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv)) + else if (HAS_PCH_LPT(display) || HAS_PCH_CPT(display)) hpd->pch_hpd = hpd_cpt; - else if (HAS_PCH_IBX(dev_priv)) + else if (HAS_PCH_IBX(display)) hpd->pch_hpd = hpd_ibx; else - MISSING_CASE(INTEL_PCH_TYPE(dev_priv)); + MISSING_CASE(INTEL_PCH_TYPE(display)); } /* For display hotplug interrupt */ void i915_hotplug_interrupt_update_locked(struct intel_display *display, u32 mask, u32 bits) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - - lockdep_assert_held(&dev_priv->irq_lock); + lockdep_assert_held(&display->irq.lock); drm_WARN_ON(display->drm, bits & ~mask); intel_de_rmw(display, PORT_HOTPLUG_EN(display), mask, bits); @@ -208,11 +208,9 @@ void i915_hotplug_interrupt_update(struct intel_display *display, u32 mask, u32 bits) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); i915_hotplug_interrupt_update_locked(display, mask, bits); - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); } static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val) @@ -557,7 +555,6 @@ void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir) void icp_irq_handler(struct intel_display *display, u32 pch_iir) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP; u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP; u32 pin_mask = 0, long_mask = 0; @@ -566,9 +563,9 @@ void icp_irq_handler(struct intel_display *display, u32 pch_iir) u32 dig_hotplug_reg; /* Locking due to DSI native GPIO sequences */ - spin_lock(&dev_priv->irq_lock); + spin_lock(&display->irq.lock); dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_DDI, 0, 0); - spin_unlock(&dev_priv->irq_lock); + spin_unlock(&display->irq.lock); intel_get_hpd_pins(display, &pin_mask, &long_mask, ddi_hotplug_trigger, dig_hotplug_reg, @@ -711,7 +708,7 @@ static u32 ibx_hotplug_mask(enum hpd_pin hpd_pin) static u32 ibx_hotplug_enables(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); switch (encoder->hpd_pin) { case HPD_PORT_A: @@ -719,7 +716,7 @@ static u32 ibx_hotplug_enables(struct intel_encoder *encoder) * When CPU and PCH are on the same package, port A * HPD must be enabled in both north and south. */ - return HAS_PCH_LPT_LP(i915) ? + return HAS_PCH_LPT_LP(display) ? PORTA_HOTPLUG_ENABLE : 0; case HPD_PORT_B: return PORTB_HOTPLUG_ENABLE | @@ -940,18 +937,17 @@ static void gen11_tbt_hpd_enable_detection(struct intel_encoder *encoder) static void gen11_hpd_enable_detection(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); gen11_tc_hpd_enable_detection(encoder); gen11_tbt_hpd_enable_detection(encoder); - if (INTEL_PCH_TYPE(i915) >= PCH_ICP) + if (INTEL_PCH_TYPE(display) >= PCH_ICP) icp_hpd_enable_detection(encoder); } static void gen11_hpd_irq_setup(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 hotplug_irqs, enabled_irqs; enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd); @@ -964,7 +960,7 @@ static void gen11_hpd_irq_setup(struct intel_display *display) gen11_tc_hpd_detection_setup(display); gen11_tbt_hpd_detection_setup(display); - if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) + if (INTEL_PCH_TYPE(display) >= PCH_ICP) icp_hpd_irq_setup(display); } @@ -1138,7 +1134,6 @@ static void xelpdp_hpd_enable_detection(struct intel_encoder *encoder) static void xelpdp_hpd_irq_setup(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); u32 hotplug_irqs, enabled_irqs; enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd); @@ -1150,9 +1145,9 @@ static void xelpdp_hpd_irq_setup(struct intel_display *display) xelpdp_pica_hpd_detection_setup(display); - if (INTEL_PCH_TYPE(i915) >= PCH_LNL) + if (INTEL_PCH_TYPE(display) >= PCH_LNL) xe2lpd_sde_hpd_irq_setup(display); - else if (INTEL_PCH_TYPE(i915) >= PCH_MTL) + else if (INTEL_PCH_TYPE(display) >= PCH_MTL) mtp_hpd_irq_setup(display); } @@ -1194,10 +1189,8 @@ static u32 spt_hotplug2_enables(struct intel_encoder *encoder) static void spt_hpd_detection_setup(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - /* Display WA #1179 WaHardHangonHotPlug: cnp */ - if (HAS_PCH_CNP(dev_priv)) { + if (HAS_PCH_CNP(display)) { intel_de_rmw(display, SOUTH_CHICKEN1, CHASSIS_CLK_REQ_DURATION_MASK, CHASSIS_CLK_REQ_DURATION(0xf)); } @@ -1215,10 +1208,9 @@ static void spt_hpd_detection_setup(struct intel_display *display) static void spt_hpd_enable_detection(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *i915 = to_i915(encoder->base.dev); /* Display WA #1179 WaHardHangonHotPlug: cnp */ - if (HAS_PCH_CNP(i915)) { + if (HAS_PCH_CNP(display)) { intel_de_rmw(display, SOUTH_CHICKEN1, CHASSIS_CLK_REQ_DURATION_MASK, CHASSIS_CLK_REQ_DURATION(0xf)); @@ -1235,10 +1227,9 @@ static void spt_hpd_enable_detection(struct intel_encoder *encoder) static void spt_hpd_irq_setup(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 hotplug_irqs, enabled_irqs; - if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) + if (INTEL_PCH_TYPE(display) >= PCH_CNP) intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); @@ -1402,10 +1393,9 @@ static void i915_hpd_enable_detection(struct intel_encoder *encoder) static void i915_hpd_irq_setup(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 hotplug_en; - lockdep_assert_held(&dev_priv->irq_lock); + lockdep_assert_held(&display->irq.lock); /* * Note HDMI and DP share hotplug bits. Enable bits are the same for all @@ -1474,8 +1464,6 @@ void intel_hpd_irq_setup(struct intel_display *display) void intel_hotplug_irq_init(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - intel_hpd_init_pins(display); intel_hpd_init_early(display); @@ -1484,9 +1472,9 @@ void intel_hotplug_irq_init(struct intel_display *display) if (HAS_HOTPLUG(display)) display->funcs.hotplug = &i915_hpd_funcs; } else { - if (HAS_PCH_DG2(i915)) + if (HAS_PCH_DG2(display)) display->funcs.hotplug = &icp_hpd_funcs; - else if (HAS_PCH_DG1(i915)) + else if (HAS_PCH_DG1(display)) display->funcs.hotplug = &dg1_hpd_funcs; else if (DISPLAY_VER(display) >= 14) display->funcs.hotplug = &xelpdp_hpd_funcs; @@ -1494,9 +1482,9 @@ void intel_hotplug_irq_init(struct intel_display *display) display->funcs.hotplug = &gen11_hpd_funcs; else if (display->platform.geminilake || display->platform.broxton) display->funcs.hotplug = &bxt_hpd_funcs; - else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) + else if (INTEL_PCH_TYPE(display) >= PCH_ICP) display->funcs.hotplug = &icp_hpd_funcs; - else if (INTEL_PCH_TYPE(i915) >= PCH_SPT) + else if (INTEL_PCH_TYPE(display) >= PCH_SPT) display->funcs.hotplug = &spt_hpd_funcs; else display->funcs.hotplug = &ilk_hpd_funcs; diff --git a/drivers/gpu/drm/i915/display/intel_hti_regs.h b/drivers/gpu/drm/i915/display/intel_hti_regs.h index e206f2837fc8..39c046bd351c 100644 --- a/drivers/gpu/drm/i915/display/intel_hti_regs.h +++ b/drivers/gpu/drm/i915/display/intel_hti_regs.h @@ -6,7 +6,7 @@ #ifndef __INTEL_HTI_REGS_H__ #define __INTEL_HTI_REGS_H__ -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" #define HDPORT_STATE _MMIO(0x45050) #define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12) diff --git a/drivers/gpu/drm/i915/display/intel_link_bw.c b/drivers/gpu/drm/i915/display/intel_link_bw.c index a10cd3992607..3caef7f9c7c4 100644 --- a/drivers/gpu/drm/i915/display/intel_link_bw.c +++ b/drivers/gpu/drm/i915/display/intel_link_bw.c @@ -3,6 +3,11 @@ * Copyright © 2023 Intel Corporation */ +#include <linux/ctype.h> +#include <linux/debugfs.h> +#include <linux/int_log.h> +#include <linux/math.h> + #include <drm/drm_fixed.h> #include <drm/drm_print.h> @@ -10,11 +15,33 @@ #include "intel_crtc.h" #include "intel_display_core.h" #include "intel_display_types.h" +#include "intel_dp.h" #include "intel_dp_mst.h" #include "intel_dp_tunnel.h" #include "intel_fdi.h" #include "intel_link_bw.h" +static int get_forced_link_bpp_x16(struct intel_atomic_state *state, + const struct intel_crtc *crtc) +{ + struct intel_digital_connector_state *conn_state; + struct intel_connector *connector; + int force_bpp_x16 = INT_MAX; + int i; + + for_each_new_intel_connector_in_state(state, connector, conn_state, i) { + if (conn_state->base.crtc != &crtc->base) + continue; + + if (!connector->link.force_bpp_x16) + continue; + + force_bpp_x16 = min(force_bpp_x16, connector->link.force_bpp_x16); + } + + return force_bpp_x16 < INT_MAX ? force_bpp_x16 : 0; +} + /** * intel_link_bw_init_limits - initialize BW limits * @state: Atomic state @@ -31,9 +58,10 @@ void intel_link_bw_init_limits(struct intel_atomic_state *state, limits->force_fec_pipes = 0; limits->bpp_limit_reached_pipes = 0; for_each_pipe(display, pipe) { + struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); const struct intel_crtc_state *crtc_state = - intel_atomic_get_new_crtc_state(state, - intel_crtc_for_pipe(display, pipe)); + intel_atomic_get_new_crtc_state(state, crtc); + int forced_bpp_x16 = get_forced_link_bpp_x16(state, crtc); if (state->base.duplicated && crtc_state) { limits->max_bpp_x16[pipe] = crtc_state->max_link_bpp_x16; @@ -42,15 +70,19 @@ void intel_link_bw_init_limits(struct intel_atomic_state *state, } else { limits->max_bpp_x16[pipe] = INT_MAX; } + + if (forced_bpp_x16) + limits->max_bpp_x16[pipe] = min(limits->max_bpp_x16[pipe], forced_bpp_x16); } } /** - * intel_link_bw_reduce_bpp - reduce maximum link bpp for a selected pipe + * __intel_link_bw_reduce_bpp - reduce maximum link bpp for a selected pipe * @state: atomic state * @limits: link BW limits * @pipe_mask: mask of pipes to select from * @reason: explanation of why bpp reduction is needed + * @reduce_forced_bpp: allow reducing bpps below their forced link bpp * * Select the pipe from @pipe_mask with the biggest link bpp value and set the * maximum of link bpp in @limits below this value. Modeset the selected pipe, @@ -64,10 +96,11 @@ void intel_link_bw_init_limits(struct intel_atomic_state *state, * - %-ENOSPC if no pipe can further reduce its link bpp * - Other negative error, if modesetting the selected pipe failed */ -int intel_link_bw_reduce_bpp(struct intel_atomic_state *state, - struct intel_link_bw_limits *limits, - u8 pipe_mask, - const char *reason) +static int __intel_link_bw_reduce_bpp(struct intel_atomic_state *state, + struct intel_link_bw_limits *limits, + u8 pipe_mask, + const char *reason, + bool reduce_forced_bpp) { struct intel_display *display = to_intel_display(state); enum pipe max_bpp_pipe = INVALID_PIPE; @@ -97,6 +130,10 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state *state, */ link_bpp_x16 = fxp_q4_from_int(crtc_state->pipe_bpp); + if (!reduce_forced_bpp && + link_bpp_x16 <= get_forced_link_bpp_x16(state, crtc)) + continue; + if (link_bpp_x16 > max_bpp_x16) { max_bpp_x16 = link_bpp_x16; max_bpp_pipe = crtc->pipe; @@ -112,6 +149,21 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state *state, BIT(max_bpp_pipe)); } +int intel_link_bw_reduce_bpp(struct intel_atomic_state *state, + struct intel_link_bw_limits *limits, + u8 pipe_mask, + const char *reason) +{ + int ret; + + /* Try to keep any forced link BPP. */ + ret = __intel_link_bw_reduce_bpp(state, limits, pipe_mask, reason, false); + if (ret == -ENOSPC) + ret = __intel_link_bw_reduce_bpp(state, limits, pipe_mask, reason, true); + + return ret; +} + /** * intel_link_bw_set_bpp_limit_for_pipe - set link bpp limit for a pipe to its minimum * @state: atomic state @@ -245,3 +297,176 @@ int intel_link_bw_atomic_check(struct intel_atomic_state *state, return -EAGAIN; } + +static int force_link_bpp_show(struct seq_file *m, void *data) +{ + struct intel_connector *connector = m->private; + + seq_printf(m, FXP_Q4_FMT "\n", FXP_Q4_ARGS(connector->link.force_bpp_x16)); + + return 0; +} + +static int str_to_fxp_q4_nonneg_int(const char *str, int *val_x16) +{ + unsigned int val; + int err; + + err = kstrtouint(str, 10, &val); + if (err) + return err; + + if (val > INT_MAX >> 4) + return -ERANGE; + + *val_x16 = fxp_q4_from_int(val); + + return 0; +} + +/* modifies str */ +static int str_to_fxp_q4_nonneg(char *str, int *val_x16) +{ + const char *int_str; + char *frac_str; + int frac_digits; + int frac_val; + int err; + + int_str = strim(str); + frac_str = strchr(int_str, '.'); + + if (frac_str) + *frac_str++ = '\0'; + + err = str_to_fxp_q4_nonneg_int(int_str, val_x16); + if (err) + return err; + + if (!frac_str) + return 0; + + /* prevent negative number/leading +- sign mark */ + if (!isdigit(*frac_str)) + return -EINVAL; + + err = str_to_fxp_q4_nonneg_int(frac_str, &frac_val); + if (err) + return err; + + frac_digits = strlen(frac_str); + if (frac_digits > intlog10(INT_MAX) >> 24 || + frac_val > INT_MAX - int_pow(10, frac_digits) / 2) + return -ERANGE; + + frac_val = DIV_ROUND_CLOSEST(frac_val, (int)int_pow(10, frac_digits)); + + if (*val_x16 > INT_MAX - frac_val) + return -ERANGE; + + *val_x16 += frac_val; + + return 0; +} + +static int user_str_to_fxp_q4_nonneg(const char __user *ubuf, size_t len, int *val_x16) +{ + char *kbuf; + int err; + + kbuf = memdup_user_nul(ubuf, len); + if (IS_ERR(kbuf)) + return PTR_ERR(kbuf); + + err = str_to_fxp_q4_nonneg(kbuf, val_x16); + + kfree(kbuf); + + return err; +} + +static bool connector_supports_dsc(struct intel_connector *connector) +{ + struct intel_display *display = to_intel_display(connector); + + switch (connector->base.connector_type) { + case DRM_MODE_CONNECTOR_eDP: + return intel_dp_has_dsc(connector); + case DRM_MODE_CONNECTOR_DisplayPort: + if (connector->mst.dp) + return HAS_DSC_MST(display); + + return HAS_DSC(display); + default: + return false; + } +} + +static ssize_t +force_link_bpp_write(struct file *file, const char __user *ubuf, size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct intel_connector *connector = m->private; + struct intel_display *display = to_intel_display(connector); + int min_bpp; + int bpp_x16; + int err; + + err = user_str_to_fxp_q4_nonneg(ubuf, len, &bpp_x16); + if (err) + return err; + + /* TODO: Make the non-DSC min_bpp value connector specific. */ + if (connector_supports_dsc(connector)) + min_bpp = intel_dp_dsc_min_src_compressed_bpp(); + else + min_bpp = intel_display_min_pipe_bpp(); + + if (bpp_x16 && + (bpp_x16 < fxp_q4_from_int(min_bpp) || + bpp_x16 > fxp_q4_from_int(intel_display_max_pipe_bpp(display)))) + return -EINVAL; + + err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); + if (err) + return err; + + connector->link.force_bpp_x16 = bpp_x16; + + drm_modeset_unlock(&display->drm->mode_config.connection_mutex); + + *offp += len; + + return len; +} +DEFINE_SHOW_STORE_ATTRIBUTE(force_link_bpp); + +void intel_link_bw_connector_debugfs_add(struct intel_connector *connector) +{ + struct intel_display *display = to_intel_display(connector); + struct dentry *root = connector->base.debugfs_entry; + + switch (connector->base.connector_type) { + case DRM_MODE_CONNECTOR_DisplayPort: + case DRM_MODE_CONNECTOR_eDP: + break; + case DRM_MODE_CONNECTOR_VGA: + case DRM_MODE_CONNECTOR_SVIDEO: + case DRM_MODE_CONNECTOR_LVDS: + case DRM_MODE_CONNECTOR_DVID: + if (HAS_FDI(display)) + break; + + return; + case DRM_MODE_CONNECTOR_HDMIA: + if (HAS_FDI(display) && !HAS_DDI(display)) + break; + + return; + default: + return; + } + + debugfs_create_file("intel_force_link_bpp", 0644, root, + connector, &force_link_bpp_fops); +} diff --git a/drivers/gpu/drm/i915/display/intel_link_bw.h b/drivers/gpu/drm/i915/display/intel_link_bw.h index e69049cf178f..b499042e62b1 100644 --- a/drivers/gpu/drm/i915/display/intel_link_bw.h +++ b/drivers/gpu/drm/i915/display/intel_link_bw.h @@ -11,6 +11,7 @@ #include "intel_display_limits.h" struct intel_atomic_state; +struct intel_connector; struct intel_crtc_state; struct intel_link_bw_limits { @@ -32,5 +33,6 @@ bool intel_link_bw_set_bpp_limit_for_pipe(struct intel_atomic_state *state, enum pipe pipe); int intel_link_bw_atomic_check(struct intel_atomic_state *state, struct intel_link_bw_limits *new_limits); +void intel_link_bw_connector_debugfs_add(struct intel_connector *connector); #endif diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c index 59551c8414c2..666148a14522 100644 --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c @@ -179,7 +179,7 @@ static int lpe_audio_irq_init(struct intel_display *display) handle_simple_irq, "hdmi_lpe_audio_irq_handler"); - return irq_set_chip_data(irq, dev_priv); + return 0; } static bool lpe_audio_detect(struct intel_display *display) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index f94b7eeae20f..abc4b562083d 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -29,9 +29,9 @@ #include <drm/drm_edid.h> #include <drm/drm_print.h> -#include "i915_reg.h" #include "i915_utils.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_hdmi.h" diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index 89d26913e253..7e48a235c99f 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -37,10 +37,9 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> #include <drm/drm_edid.h> +#include <drm/drm_print.h> #include <drm/drm_probe_helper.h> -#include "i915_drv.h" -#include "i915_reg.h" #include "intel_atomic.h" #include "intel_backlight.h" #include "intel_connector.h" @@ -87,13 +86,12 @@ static struct intel_lvds_encoder *to_lvds_encoder(struct intel_encoder *encoder) bool intel_lvds_port_enabled(struct intel_display *display, i915_reg_t lvds_reg, enum pipe *pipe) { - struct drm_i915_private *i915 = to_i915(display->drm); u32 val; val = intel_de_read(display, lvds_reg); /* asserts want to know the pipe even if the port is disabled */ - if (HAS_PCH_CPT(i915)) + if (HAS_PCH_CPT(display)) *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val); else *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val); @@ -243,15 +241,14 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state, { struct intel_display *display = to_intel_display(state); struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); - struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; enum pipe pipe = crtc->pipe; u32 temp; - if (HAS_PCH_SPLIT(i915)) { + if (HAS_PCH_SPLIT(display)) { assert_fdi_rx_pll_disabled(display, pipe); - assert_shared_dpll_disabled(display, crtc_state->shared_dpll); + assert_dpll_disabled(display, crtc_state->intel_dpll); } else { assert_pll_disabled(display, pipe); } @@ -261,7 +258,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state, temp = lvds_encoder->init_lvds_val; temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; - if (HAS_PCH_CPT(i915)) { + if (HAS_PCH_CPT(display)) { temp &= ~LVDS_PIPE_SEL_MASK_CPT; temp |= LVDS_PIPE_SEL_CPT(pipe); } else { @@ -421,7 +418,6 @@ static int intel_lvds_compute_config(struct intel_encoder *encoder, struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); struct intel_connector *connector = lvds_encoder->attached_connector; struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; @@ -435,7 +431,7 @@ static int intel_lvds_compute_config(struct intel_encoder *encoder, return -EINVAL; } - if (HAS_PCH_SPLIT(i915)) { + if (HAS_PCH_SPLIT(display)) { crtc_state->has_pch_encoder = true; if (!intel_fdi_compute_pipe_bpp(crtc_state)) return -EINVAL; @@ -798,7 +794,6 @@ bool intel_is_dual_link_lvds(struct intel_display *display) static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) { struct intel_display *display = to_intel_display(&lvds_encoder->base); - struct drm_i915_private *i915 = to_i915(lvds_encoder->base.base.dev); struct intel_connector *connector = lvds_encoder->attached_connector; const struct drm_display_mode *fixed_mode = intel_panel_preferred_fixed_mode(connector); @@ -822,7 +817,7 @@ static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) * register is uninitialized. */ val = intel_de_read(display, lvds_encoder->reg); - if (HAS_PCH_CPT(i915)) + if (HAS_PCH_CPT(display)) val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT); else val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK); @@ -846,7 +841,6 @@ static void intel_lvds_add_properties(struct drm_connector *connector) */ void intel_lvds_init(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); struct intel_lvds_encoder *lvds_encoder; struct intel_connector *connector; const struct drm_edid *drm_edid; @@ -868,14 +862,14 @@ void intel_lvds_init(struct intel_display *display) return; } - if (HAS_PCH_SPLIT(i915)) + if (HAS_PCH_SPLIT(display)) lvds_reg = PCH_LVDS; else lvds_reg = LVDS; lvds = intel_de_read(display, lvds_reg); - if (HAS_PCH_SPLIT(i915)) { + if (HAS_PCH_SPLIT(display)) { if ((lvds & LVDS_DETECTED) == 0) return; } @@ -915,7 +909,7 @@ void intel_lvds_init(struct intel_display *display) encoder->enable = intel_enable_lvds; encoder->pre_enable = intel_pre_enable_lvds; encoder->compute_config = intel_lvds_compute_config; - if (HAS_PCH_SPLIT(i915)) { + if (HAS_PCH_SPLIT(display)) { encoder->disable = pch_disable_lvds; encoder->post_disable = pch_post_disable_lvds; } else { diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index 9e963bce340f..05e1b309ba2c 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -6,11 +6,11 @@ * state. */ -#include <drm/drm_atomic_uapi.h> #include <drm/drm_atomic_state_helper.h> +#include <drm/drm_atomic_uapi.h> +#include <drm/drm_print.h> #include <drm/drm_vblank.h> -#include "i915_drv.h" #include "i915_reg.h" #include "i9xx_wm.h" #include "intel_atomic.h" @@ -23,6 +23,7 @@ #include "intel_de.h" #include "intel_display.h" #include "intel_display_power.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dmc.h" #include "intel_fifo_underrun.h" @@ -31,13 +32,14 @@ #include "intel_pmdemand.h" #include "intel_tc.h" #include "intel_vblank.h" +#include "intel_vga.h" #include "intel_wm.h" #include "skl_watermark.h" static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc, struct drm_modeset_acquire_ctx *ctx) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); struct intel_plane *plane; @@ -48,7 +50,7 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc, if (!crtc_state->hw.active) return; - for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { + for_each_intel_plane_on_crtc(display->drm, crtc, plane) { const struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state); @@ -56,9 +58,9 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc, intel_plane_disable_noatomic(crtc, plane); } - state = drm_atomic_state_alloc(&i915->drm); + state = drm_atomic_state_alloc(display->drm); if (!state) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "failed to disable [CRTC:%d:%s], out of memory", crtc->base.base.id, crtc->base.name); return; @@ -68,7 +70,7 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc, to_intel_atomic_state(state)->internal = true; /* Everything's already locked, -EDEADLK can't happen. */ - for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, + for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc, BIT(pipe) | intel_crtc_joiner_secondary_pipes(crtc_state)) { struct intel_crtc_state *temp_crtc_state = @@ -77,24 +79,24 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc, ret = drm_atomic_add_affected_connectors(state, &temp_crtc->base); - drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret); + drm_WARN_ON(display->drm, IS_ERR(temp_crtc_state) || ret); } - i915->display.funcs.display->crtc_disable(to_intel_atomic_state(state), crtc); + display->funcs.display->crtc_disable(to_intel_atomic_state(state), crtc); drm_atomic_state_put(state); - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", crtc->base.base.id, crtc->base.name); crtc->active = false; crtc->base.enabled = false; - if (crtc_state->shared_dpll) - intel_unreference_shared_dpll_crtc(crtc, - crtc_state->shared_dpll, - &crtc_state->shared_dpll->state); + if (crtc_state->intel_dpll) + intel_dpll_crtc_put(crtc, + crtc_state->intel_dpll, + &crtc_state->intel_dpll->state); } static void set_encoder_for_connector(struct intel_connector *connector, @@ -118,13 +120,12 @@ static void set_encoder_for_connector(struct intel_connector *connector, static void reset_encoder_connector_state(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_pmdemand_state *pmdemand_state = - to_intel_pmdemand_state(i915->display.pmdemand.obj.state); + to_intel_pmdemand_state(display->pmdemand.obj.state); struct intel_connector *connector; struct drm_connector_list_iter conn_iter; - drm_connector_list_iter_begin(&i915->drm, &conn_iter); + drm_connector_list_iter_begin(display->drm, &conn_iter); for_each_intel_connector_iter(connector, &conn_iter) { if (connector->base.encoder != &encoder->base) continue; @@ -143,10 +144,10 @@ static void reset_encoder_connector_state(struct intel_encoder *encoder) static void reset_crtc_encoder_state(struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_encoder *encoder; - for_each_encoder_on_crtc(&i915->drm, &crtc->base, encoder) { + for_each_encoder_on_crtc(display->drm, &crtc->base, encoder) { reset_encoder_connector_state(encoder); encoder->base.crtc = NULL; } @@ -183,13 +184,13 @@ static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc) * Return all the pipes using a transcoder in @transcoder_mask. * For joiner configs return only the joiner primary. */ -static u8 get_transcoder_pipes(struct drm_i915_private *i915, +static u8 get_transcoder_pipes(struct intel_display *display, u8 transcoder_mask) { struct intel_crtc *temp_crtc; u8 pipes = 0; - for_each_intel_crtc(&i915->drm, temp_crtc) { + for_each_intel_crtc(display->drm, temp_crtc) { struct intel_crtc_state *temp_crtc_state = to_intel_crtc_state(temp_crtc->base.state); @@ -214,7 +215,6 @@ static void get_portsync_pipes(struct intel_crtc *crtc, u8 *master_pipe_mask, u8 *slave_pipes_mask) { struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); struct intel_crtc *master_crtc; @@ -233,20 +233,20 @@ static void get_portsync_pipes(struct intel_crtc *crtc, else master_transcoder = crtc_state->master_transcoder; - *master_pipe_mask = get_transcoder_pipes(i915, BIT(master_transcoder)); - drm_WARN_ON(&i915->drm, !is_power_of_2(*master_pipe_mask)); + *master_pipe_mask = get_transcoder_pipes(display, BIT(master_transcoder)); + drm_WARN_ON(display->drm, !is_power_of_2(*master_pipe_mask)); master_crtc = intel_crtc_for_pipe(display, ffs(*master_pipe_mask) - 1); master_crtc_state = to_intel_crtc_state(master_crtc->base.state); - *slave_pipes_mask = get_transcoder_pipes(i915, master_crtc_state->sync_mode_slaves_mask); + *slave_pipes_mask = get_transcoder_pipes(display, master_crtc_state->sync_mode_slaves_mask); } -static u8 get_joiner_secondary_pipes(struct drm_i915_private *i915, u8 primary_pipes_mask) +static u8 get_joiner_secondary_pipes(struct intel_display *display, u8 primary_pipes_mask) { struct intel_crtc *primary_crtc; u8 pipes = 0; - for_each_intel_crtc_in_pipe_mask(&i915->drm, primary_crtc, primary_pipes_mask) { + for_each_intel_crtc_in_pipe_mask(display->drm, primary_crtc, primary_pipes_mask) { struct intel_crtc_state *primary_crtc_state = to_intel_crtc_state(primary_crtc->base.state); @@ -259,45 +259,45 @@ static u8 get_joiner_secondary_pipes(struct drm_i915_private *i915, u8 primary_p static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, struct drm_modeset_acquire_ctx *ctx) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); + struct intel_crtc *temp_crtc; u8 portsync_master_mask; u8 portsync_slaves_mask; u8 joiner_secondaries_mask; - struct intel_crtc *temp_crtc; /* TODO: Add support for MST */ get_portsync_pipes(crtc, &portsync_master_mask, &portsync_slaves_mask); - joiner_secondaries_mask = get_joiner_secondary_pipes(i915, + joiner_secondaries_mask = get_joiner_secondary_pipes(display, portsync_master_mask | portsync_slaves_mask); - drm_WARN_ON(&i915->drm, + drm_WARN_ON(display->drm, portsync_master_mask & portsync_slaves_mask || portsync_master_mask & joiner_secondaries_mask || portsync_slaves_mask & joiner_secondaries_mask); - for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, joiner_secondaries_mask) + for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc, joiner_secondaries_mask) intel_crtc_disable_noatomic_begin(temp_crtc, ctx); - for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, portsync_slaves_mask) + for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc, portsync_slaves_mask) intel_crtc_disable_noatomic_begin(temp_crtc, ctx); - for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, portsync_master_mask) + for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc, portsync_master_mask) intel_crtc_disable_noatomic_begin(temp_crtc, ctx); - for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, + for_each_intel_crtc_in_pipe_mask(display->drm, temp_crtc, joiner_secondaries_mask | portsync_slaves_mask | portsync_master_mask) intel_crtc_disable_noatomic_complete(temp_crtc); } -static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915) +static void intel_modeset_update_connector_atomic_state(struct intel_display *display) { struct intel_connector *connector; struct drm_connector_list_iter conn_iter; - drm_connector_list_iter_begin(&i915->drm, &conn_iter); + drm_connector_list_iter_begin(display->drm, &conn_iter); for_each_intel_connector_iter(connector, &conn_iter) { struct drm_connector_state *conn_state = connector->base.state; struct intel_encoder *encoder = @@ -319,7 +319,7 @@ static void intel_modeset_update_connector_atomic_state(struct drm_i915_private static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); if (intel_crtc_is_joiner_secondary(crtc_state)) return; @@ -332,7 +332,7 @@ static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; - if (DISPLAY_INFO(i915)->color.degamma_lut_size) { + if (DISPLAY_INFO(display)->color.degamma_lut_size) { /* assume 1:1 mapping */ drm_property_replace_blob(&crtc_state->hw.degamma_lut, crtc_state->pre_csc_lut); @@ -347,7 +347,7 @@ static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state * to gamma_lut as that is the only valid source of LUTs * in the uapi. */ - drm_WARN_ON(&i915->drm, crtc_state->post_csc_lut && + drm_WARN_ON(display->drm, crtc_state->post_csc_lut && crtc_state->pre_csc_lut); drm_property_replace_blob(&crtc_state->hw.degamma_lut, @@ -366,15 +366,14 @@ static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state } static void -intel_sanitize_plane_mapping(struct drm_i915_private *i915) +intel_sanitize_plane_mapping(struct intel_display *display) { - struct intel_display *display = &i915->display; struct intel_crtc *crtc; - if (DISPLAY_VER(i915) >= 4) + if (DISPLAY_VER(display) >= 4) return; - for_each_intel_crtc(&i915->drm, crtc) { + for_each_intel_crtc(display->drm, crtc) { struct intel_plane *plane = to_intel_plane(crtc->base.primary); struct intel_crtc *plane_crtc; @@ -386,7 +385,7 @@ intel_sanitize_plane_mapping(struct drm_i915_private *i915) if (pipe == crtc->pipe) continue; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", plane->base.base.id, plane->base.name); @@ -423,12 +422,12 @@ static bool intel_crtc_needs_link_reset(struct intel_crtc *crtc) static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct drm_connector_list_iter conn_iter; struct intel_connector *connector; struct intel_connector *found_connector = NULL; - drm_connector_list_iter_begin(&i915->drm, &conn_iter); + drm_connector_list_iter_begin(display->drm, &conn_iter); for_each_intel_connector_iter(connector, &conn_iter) { if (&encoder->base == connector->base.encoder) { found_connector = connector; @@ -466,7 +465,7 @@ static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state static bool intel_sanitize_crtc(struct intel_crtc *crtc, struct drm_modeset_acquire_ctx *ctx) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); bool needs_link_reset; @@ -474,7 +473,7 @@ static bool intel_sanitize_crtc(struct intel_crtc *crtc, struct intel_plane *plane; /* Disable everything but the primary plane */ - for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { + for_each_intel_plane_on_crtc(display->drm, crtc, plane) { const struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state); @@ -515,7 +514,7 @@ static bool intel_sanitize_crtc(struct intel_crtc *crtc, return true; } -static void intel_sanitize_all_crtcs(struct drm_i915_private *i915, +static void intel_sanitize_all_crtcs(struct intel_display *display, struct drm_modeset_acquire_ctx *ctx) { struct intel_crtc *crtc; @@ -530,7 +529,7 @@ static void intel_sanitize_all_crtcs(struct drm_i915_private *i915, for (;;) { u32 old_mask = crtcs_forced_off; - for_each_intel_crtc(&i915->drm, crtc) { + for_each_intel_crtc(display->drm, crtc) { u32 crtc_mask = drm_crtc_mask(&crtc->base); if (crtcs_forced_off & crtc_mask) @@ -543,7 +542,7 @@ static void intel_sanitize_all_crtcs(struct drm_i915_private *i915, break; } - for_each_intel_crtc(&i915->drm, crtc) { + for_each_intel_crtc(display->drm, crtc) { struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); @@ -553,7 +552,7 @@ static void intel_sanitize_all_crtcs(struct drm_i915_private *i915, static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); /* * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram @@ -565,22 +564,21 @@ static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) * without several WARNs, but for now let's take the easy * road. */ - return IS_SANDYBRIDGE(i915) && + return display->platform.sandybridge && crtc_state->hw.active && - crtc_state->shared_dpll && + crtc_state->intel_dpll && crtc_state->port_clock == 0; } static void intel_sanitize_encoder(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_connector *connector; struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); struct intel_crtc_state *crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL; struct intel_pmdemand_state *pmdemand_state = - to_intel_pmdemand_state(i915->display.pmdemand.obj.state); + to_intel_pmdemand_state(display->pmdemand.obj.state); /* * We need to check both for a crtc link (meaning that the encoder is @@ -591,7 +589,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) crtc_state->hw.active; if (crtc_state && has_bogus_dpll_config(crtc_state)) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "BIOS has misprogrammed the hardware. Disabling pipe %c\n", pipe_name(crtc->pipe)); has_active_crtc = false; @@ -599,7 +597,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) connector = intel_encoder_find_connector(encoder); if (connector && !has_active_crtc) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[ENCODER:%d:%s] has active connectors but no active pipe!\n", encoder->base.base.id, encoder->base.name); @@ -616,7 +614,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) if (crtc_state) { struct drm_encoder *best_encoder; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[ENCODER:%d:%s] manually disabled\n", encoder->base.base.id, encoder->base.name); @@ -650,18 +648,17 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) /* notify opregion of the sanitized encoder state */ intel_opregion_notify_encoder(encoder, connector && has_active_crtc); - if (HAS_DDI(i915)) + if (HAS_DDI(display)) intel_ddi_sanitize_encoder_pll_mapping(encoder); } /* FIXME read out full plane state for all planes */ -static void readout_plane_state(struct drm_i915_private *i915) +static void readout_plane_state(struct intel_display *display) { - struct intel_display *display = &i915->display; struct intel_plane *plane; struct intel_crtc *crtc; - for_each_intel_plane(&i915->drm, plane) { + for_each_intel_plane(display->drm, plane) { struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state); struct intel_crtc_state *crtc_state; @@ -675,13 +672,13 @@ static void readout_plane_state(struct drm_i915_private *i915) intel_set_plane_visible(crtc_state, plane_state, visible); - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", plane->base.base.id, plane->base.name, str_enabled_disabled(visible), pipe_name(pipe)); } - for_each_intel_crtc(&i915->drm, crtc) { + for_each_intel_crtc(display->drm, crtc) { struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); @@ -689,18 +686,17 @@ static void readout_plane_state(struct drm_i915_private *i915) } } -static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) +static void intel_modeset_readout_hw_state(struct intel_display *display) { - struct intel_display *display = &i915->display; struct intel_pmdemand_state *pmdemand_state = - to_intel_pmdemand_state(i915->display.pmdemand.obj.state); + to_intel_pmdemand_state(display->pmdemand.obj.state); enum pipe pipe; struct intel_crtc *crtc; struct intel_encoder *encoder; struct intel_connector *connector; struct drm_connector_list_iter conn_iter; - for_each_intel_crtc(&i915->drm, crtc) { + for_each_intel_crtc(display->drm, crtc) { struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); @@ -715,15 +711,15 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) crtc->base.enabled = crtc_state->hw.enable; crtc->active = crtc_state->hw.active; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] hw state readout: %s\n", crtc->base.base.id, crtc->base.name, str_enabled_disabled(crtc_state->hw.active)); } - readout_plane_state(i915); + readout_plane_state(display); - for_each_intel_encoder(&i915->drm, encoder) { + for_each_intel_encoder(display->drm, encoder) { struct intel_crtc_state *crtc_state = NULL; pipe = 0; @@ -742,7 +738,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) /* encoder should read be linked to joiner primary */ WARN_ON(intel_crtc_is_joiner_secondary(crtc_state)); - for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc, + for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc, intel_crtc_joiner_secondary_pipes(crtc_state)) { struct intel_crtc_state *secondary_crtc_state; @@ -765,7 +761,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) if (encoder->sync_state) encoder->sync_state(encoder, crtc_state); - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", encoder->base.base.id, encoder->base.name, str_enabled_disabled(encoder->base.crtc), @@ -774,7 +770,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) intel_dpll_readout_hw_state(display); - drm_connector_list_iter_begin(&i915->drm, &conn_iter); + drm_connector_list_iter_begin(display->drm, &conn_iter); for_each_intel_connector_iter(connector, &conn_iter) { struct intel_crtc_state *crtc_state = NULL; @@ -808,14 +804,14 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) if (connector->sync_state) connector->sync_state(connector, crtc_state); - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] hw state readout: %s\n", connector->base.base.id, connector->base.name, str_enabled_disabled(connector->base.encoder)); } drm_connector_list_iter_end(&conn_iter); - for_each_intel_crtc(&i915->drm, crtc) { + for_each_intel_crtc(display->drm, crtc) { struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); struct intel_plane *plane; @@ -838,7 +834,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) intel_crtc_copy_hw_to_uapi_state(crtc_state); } - for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { + for_each_intel_plane_on_crtc(display->drm, crtc, plane) { const struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state); @@ -854,14 +850,14 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) * use plane->min_cdclk() :( */ if (plane_state->uapi.visible && plane->min_cdclk) { - if (crtc_state->double_wide || DISPLAY_VER(i915) >= 10) + if (crtc_state->double_wide || DISPLAY_VER(display) >= 10) crtc_state->min_cdclk[plane->id] = DIV_ROUND_UP(crtc_state->pixel_rate, 2); else crtc_state->min_cdclk[plane->id] = crtc_state->pixel_rate; } - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[PLANE:%d:%s] min_cdclk %d kHz\n", plane->base.base.id, plane->base.name, crtc_state->min_cdclk[plane->id]); @@ -882,11 +878,11 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) } static void -get_encoder_power_domains(struct drm_i915_private *i915) +get_encoder_power_domains(struct intel_display *display) { struct intel_encoder *encoder; - for_each_intel_encoder(&i915->drm, encoder) { + for_each_intel_encoder(display->drm, encoder) { struct intel_crtc_state *crtc_state; if (!encoder->get_power_domains) @@ -904,47 +900,49 @@ get_encoder_power_domains(struct drm_i915_private *i915) } } -static void intel_early_display_was(struct drm_i915_private *i915) +static void intel_early_display_was(struct intel_display *display) { /* * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl * Also known as Wa_14010480278. */ - if (IS_DISPLAY_VER(i915, 10, 12)) - intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, DARBF_GATING_DIS); + if (IS_DISPLAY_VER(display, 10, 12)) + intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, DARBF_GATING_DIS); /* * WaRsPkgCStateDisplayPMReq:hsw * System hang if this isn't done before disabling all planes! */ - if (IS_HASWELL(i915)) - intel_de_rmw(i915, CHICKEN_PAR1_1, 0, FORCE_ARB_IDLE_PLANES); + if (display->platform.haswell) + intel_de_rmw(display, CHICKEN_PAR1_1, 0, FORCE_ARB_IDLE_PLANES); - if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) { + if (display->platform.kabylake || display->platform.coffeelake || + display->platform.cometlake) { /* Display WA #1142:kbl,cfl,cml */ - intel_de_rmw(i915, CHICKEN_PAR1_1, + intel_de_rmw(display, CHICKEN_PAR1_1, KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22); - intel_de_rmw(i915, CHICKEN_MISC_2, + intel_de_rmw(display, CHICKEN_MISC_2, KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14, KBL_ARB_FILL_SPARE_14); } } -void intel_modeset_setup_hw_state(struct drm_i915_private *i915, +void intel_modeset_setup_hw_state(struct intel_display *display, struct drm_modeset_acquire_ctx *ctx) { - struct intel_display *display = &i915->display; struct intel_encoder *encoder; struct intel_crtc *crtc; intel_wakeref_t wakeref; wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); - intel_early_display_was(i915); - intel_modeset_readout_hw_state(i915); + intel_early_display_was(display); + intel_vga_disable(display); + + intel_modeset_readout_hw_state(display); /* HW state is read out, now we need to sanitize this mess. */ - get_encoder_power_domains(i915); + get_encoder_power_domains(display); intel_pch_sanitize(display); @@ -954,7 +952,7 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915, * intel_sanitize_plane_mapping() may need to do vblank * waits, so we need vblank interrupts restored beforehand. */ - for_each_intel_crtc(&i915->drm, crtc) { + for_each_intel_crtc(display->drm, crtc) { struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); @@ -968,20 +966,20 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915, } } - intel_fbc_sanitize(&i915->display); + intel_fbc_sanitize(display); - intel_sanitize_plane_mapping(i915); + intel_sanitize_plane_mapping(display); - for_each_intel_encoder(&i915->drm, encoder) + for_each_intel_encoder(display->drm, encoder) intel_sanitize_encoder(encoder); /* * Sanitizing CRTCs needs their connector atomic state to be * up-to-date, so ensure that already here. */ - intel_modeset_update_connector_atomic_state(i915); + intel_modeset_update_connector_atomic_state(display); - intel_sanitize_all_crtcs(i915, ctx); + intel_sanitize_all_crtcs(display, ctx); intel_dpll_sanitize_state(display); @@ -990,13 +988,13 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915, intel_wm_get_hw_state(display); intel_wm_sanitize(display); - for_each_intel_crtc(&i915->drm, crtc) { + for_each_intel_crtc(display->drm, crtc) { struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); struct intel_power_domain_mask put_domains; intel_modeset_get_crtc_power_domains(crtc_state, &put_domains); - if (drm_WARN_ON(&i915->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM))) + if (drm_WARN_ON(display->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM))) intel_modeset_put_crtc_power_domains(crtc, &put_domains); } diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.h b/drivers/gpu/drm/i915/display/intel_modeset_setup.h index 3beff67b33d0..f5e6f3ae9572 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.h +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.h @@ -6,10 +6,10 @@ #ifndef __INTEL_MODESET_SETUP_H__ #define __INTEL_MODESET_SETUP_H__ -struct drm_i915_private; struct drm_modeset_acquire_ctx; +struct intel_display; -void intel_modeset_setup_hw_state(struct drm_i915_private *i915, +void intel_modeset_setup_hw_state(struct intel_display *display, struct drm_modeset_acquire_ctx *ctx); #endif /* __INTEL_MODESET_SETUP_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c index a008412fdd04..f2f6b9d9afa1 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c @@ -6,13 +6,14 @@ */ #include <drm/drm_atomic_state_helper.h> +#include <drm/drm_print.h> -#include "i915_drv.h" #include "intel_atomic.h" #include "intel_crtc.h" #include "intel_crtc_state_dump.h" #include "intel_cx0_phy.h" #include "intel_display.h" +#include "intel_display_core.h" #include "intel_display_types.h" #include "intel_fdi.h" #include "intel_modeset_verify.h" @@ -28,9 +29,8 @@ static void intel_connector_verify_state(const struct intel_crtc_state *crtc_sta { struct intel_connector *connector = to_intel_connector(conn_state->connector); struct intel_display *display = to_intel_display(connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", connector->base.base.id, connector->base.name); if (connector->get_hw_state(connector)) { @@ -91,7 +91,6 @@ verify_connector_state(struct intel_atomic_state *state, static void intel_pipe_config_sanity_check(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); if (crtc_state->has_pch_encoder) { int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(display, crtc_state), @@ -103,7 +102,7 @@ static void intel_pipe_config_sanity_check(const struct intel_crtc_state *crtc_s * Yell if the encoder disagrees. Allow for slight * rounding differences. */ - drm_WARN(&i915->drm, abs(fdi_dotclock - dotclock) > 1, + drm_WARN(display->drm, abs(fdi_dotclock - dotclock) > 1, "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", fdi_dotclock, dotclock); } @@ -113,17 +112,16 @@ static void verify_encoder_state(struct intel_atomic_state *state) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *i915 = to_i915(state->base.dev); struct intel_encoder *encoder; struct drm_connector *connector; const struct drm_connector_state *old_conn_state, *new_conn_state; int i; - for_each_intel_encoder(&i915->drm, encoder) { + for_each_intel_encoder(display->drm, encoder) { bool enabled = false, found = false; enum pipe pipe; - drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s]\n", + drm_dbg_kms(display->drm, "[ENCODER:%d:%s]\n", encoder->base.base.id, encoder->base.name); @@ -166,7 +164,6 @@ verify_crtc_state(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *i915 = to_i915(display->drm); const struct intel_crtc_state *sw_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct intel_crtc_state *hw_crtc_state; @@ -185,7 +182,7 @@ verify_crtc_state(struct intel_atomic_state *state, intel_crtc_get_pipe_config(hw_crtc_state); /* we keep both pipes enabled on 830 */ - if (IS_I830(i915) && hw_crtc_state->hw.active) + if (display->platform.i830 && hw_crtc_state->hw.active) hw_crtc_state->hw.active = sw_crtc_state->hw.active; INTEL_DISPLAY_STATE_WARN(display, @@ -246,7 +243,7 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state, intel_wm_state_verify(state, crtc); verify_connector_state(state, crtc); verify_crtc_state(state, crtc); - intel_shared_dpll_state_verify(state, crtc); + intel_dpll_state_verify(state, crtc); intel_mpllb_state_verify(state, crtc); intel_cx0pll_state_verify(state, crtc); } @@ -255,5 +252,5 @@ void intel_modeset_verify_disabled(struct intel_atomic_state *state) { verify_encoder_state(state); verify_connector_state(state, NULL); - intel_shared_dpll_verify_disabled(state); + intel_dpll_verify_disabled(state); } diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index 0eaa6cd6fe80..5535cb799431 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -35,6 +35,7 @@ #include "i915_drv.h" #include "intel_acpi.h" #include "intel_backlight.h" +#include "intel_display_core.h" #include "intel_display_types.h" #include "intel_opregion.h" #include "intel_pci_config.h" diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c index aff9a3455c1b..159a5f998ea0 100644 --- a/drivers/gpu/drm/i915/display/intel_overlay.c +++ b/drivers/gpu/drm/i915/display/intel_overlay.c @@ -31,6 +31,7 @@ #include "gem/i915_gem_internal.h" #include "gem/i915_gem_object_frontbuffer.h" #include "gem/i915_gem_pm.h" + #include "gt/intel_gpu_commands.h" #include "gt/intel_ring.h" @@ -38,6 +39,7 @@ #include "i915_reg.h" #include "intel_color_regs.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_frontbuffer.h" #include "intel_overlay.h" @@ -291,7 +293,6 @@ static void intel_overlay_flip_prepare(struct intel_overlay *overlay, struct i915_vma *vma) { struct intel_display *display = overlay->display; - struct drm_i915_private *i915 = to_i915(display->drm); enum pipe pipe = overlay->crtc->pipe; struct intel_frontbuffer *frontbuffer = NULL; @@ -307,7 +308,7 @@ static void intel_overlay_flip_prepare(struct intel_overlay *overlay, intel_frontbuffer_put(overlay->frontbuffer); overlay->frontbuffer = frontbuffer; - intel_frontbuffer_flip_prepare(i915, INTEL_FRONTBUFFER_OVERLAY(pipe)); + intel_frontbuffer_flip_prepare(display, INTEL_FRONTBUFFER_OVERLAY(pipe)); overlay->old_vma = overlay->vma; if (vma) @@ -359,14 +360,13 @@ static int intel_overlay_continue(struct intel_overlay *overlay, static void intel_overlay_release_old_vma(struct intel_overlay *overlay) { struct intel_display *display = overlay->display; - struct drm_i915_private *i915 = to_i915(display->drm); struct i915_vma *vma; vma = fetch_and_zero(&overlay->old_vma); if (drm_WARN_ON(display->drm, !vma)) return; - intel_frontbuffer_flip_complete(i915, INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); + intel_frontbuffer_flip_complete(display, INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); i915_vma_unpin(vma); i915_vma_put(vma); diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index f5c972880391..f956919dc648 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -462,3 +462,134 @@ void intel_panel_fini(struct intel_connector *connector) drm_mode_destroy(connector->base.dev, fixed_mode); } } + +/* + * If the panel was already enabled at probe, and we took over the state, the + * panel prepared state is out of sync, and the panel followers won't be + * notified. We need to call drm_panel_prepare() on enabled panels. + * + * It would be natural to handle this e.g. in the connector ->sync_state hook at + * intel_modeset_readout_hw_state(), but that's unfortunately too early. We + * don't have drm_connector::kdev at that time. For now, figure out the state at + * ->late_register, and sync there. + */ +static void intel_panel_sync_state(struct intel_connector *connector) +{ + struct intel_display *display = to_intel_display(connector); + struct drm_connector_state *conn_state; + struct intel_crtc *crtc; + int ret; + + ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL); + if (ret) + return; + + conn_state = connector->base.state; + + crtc = to_intel_crtc(conn_state->crtc); + if (crtc) { + struct intel_crtc_state *crtc_state; + + crtc_state = to_intel_crtc_state(crtc->base.state); + + if (crtc_state->hw.active) { + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Panel prepare\n", + connector->base.base.id, connector->base.name); + intel_panel_prepare(crtc_state, conn_state); + } + } + + drm_modeset_unlock(&display->drm->mode_config.connection_mutex); +} + +const struct drm_panel_funcs dummy_panel_funcs = { +}; + +int intel_panel_register(struct intel_connector *connector) +{ + struct intel_display *display = to_intel_display(connector); + struct intel_panel *panel = &connector->panel; + int ret; + + ret = intel_backlight_device_register(connector); + if (ret) + return ret; + + if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI) { + struct device *dev = connector->base.kdev; + struct drm_panel *base; + + /* Sanity check. */ + if (drm_WARN_ON(display->drm, !dev)) + goto out; + + /* + * We need drm_connector::kdev for allocating the panel, to make + * drm_panel_add_follower() lookups work. The kdev is + * initialized in drm_sysfs_connector_add(), just before the + * connector .late_register() hooks. So we can't allocate the + * panel at connector init time, and can't allocate struct + * intel_panel with a drm_panel sub-struct. For now, use + * __devm_drm_panel_alloc() directly. + * + * The lookups also depend on drm_connector::fwnode being set in + * intel_acpi_assign_connector_fwnodes(). However, if that's + * missing, it will gracefully lead to -EPROBE_DEFER in + * drm_panel_add_follower(). + */ + base = __devm_drm_panel_alloc(dev, sizeof(*base), 0, + &dummy_panel_funcs, + connector->base.connector_type); + if (IS_ERR(base)) { + ret = PTR_ERR(base); + goto err; + } + + panel->base = base; + + drm_panel_add(panel->base); + + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Registered panel device '%s', has fwnode: %s\n", + connector->base.base.id, connector->base.name, + dev_name(dev), str_yes_no(dev_fwnode(dev))); + + intel_panel_sync_state(connector); + } + +out: + return 0; + +err: + intel_backlight_device_unregister(connector); + + return ret; +} + +void intel_panel_unregister(struct intel_connector *connector) +{ + struct intel_panel *panel = &connector->panel; + + if (panel->base) + drm_panel_remove(panel->base); + + intel_backlight_device_unregister(connector); +} + +/* Notify followers, if any, about power being up. */ +void intel_panel_prepare(const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) +{ + struct intel_connector *connector = to_intel_connector(conn_state->connector); + struct intel_panel *panel = &connector->panel; + + drm_panel_prepare(panel->base); +} + +/* Notify followers, if any, about power going down. */ +void intel_panel_unprepare(const struct drm_connector_state *old_conn_state) +{ + struct intel_connector *connector = to_intel_connector(old_conn_state->connector); + struct intel_panel *panel = &connector->panel; + + drm_panel_unprepare(panel->base); +} diff --git a/drivers/gpu/drm/i915/display/intel_panel.h b/drivers/gpu/drm/i915/display/intel_panel.h index b60d12322e5d..56a6412cf0fb 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.h +++ b/drivers/gpu/drm/i915/display/intel_panel.h @@ -23,6 +23,8 @@ void intel_panel_init_alloc(struct intel_connector *connector); int intel_panel_init(struct intel_connector *connector, const struct drm_edid *fixed_edid); void intel_panel_fini(struct intel_connector *connector); +int intel_panel_register(struct intel_connector *connector); +void intel_panel_unregister(struct intel_connector *connector); enum drm_connector_status intel_panel_detect(struct drm_connector *connector, bool force); bool intel_panel_use_ssc(struct intel_display *display); @@ -51,4 +53,8 @@ void intel_panel_add_vbt_sdvo_fixed_mode(struct intel_connector *connector); void intel_panel_add_encoder_fixed_mode(struct intel_connector *connector, struct intel_encoder *encoder); +void intel_panel_prepare(const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state); +void intel_panel_unprepare(const struct drm_connector_state *old_conn_state); + #endif /* __INTEL_PANEL_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_pch.c b/drivers/gpu/drm/i915/display/intel_pch.c new file mode 100644 index 000000000000..469e8a3cfb49 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_pch.c @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Intel Corporation. + */ + +#include <drm/drm_print.h> + +#include "i915_utils.h" +#include "intel_display_core.h" +#include "intel_pch.h" + +#define INTEL_PCH_DEVICE_ID_MASK 0xff80 +#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 +#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 +#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 +#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 +#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 +#define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80 +#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80 +#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 +#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 +#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280 +#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300 +#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80 +#define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280 +#define INTEL_PCH_CMP2_DEVICE_ID_TYPE 0x0680 +#define INTEL_PCH_CMP_V_DEVICE_ID_TYPE 0xA380 +#define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480 +#define INTEL_PCH_ICP2_DEVICE_ID_TYPE 0x3880 +#define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00 +#define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080 +#define INTEL_PCH_TGP2_DEVICE_ID_TYPE 0x4380 +#define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80 +#define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80 +#define INTEL_PCH_ADP2_DEVICE_ID_TYPE 0x5180 +#define INTEL_PCH_ADP3_DEVICE_ID_TYPE 0x7A00 +#define INTEL_PCH_ADP4_DEVICE_ID_TYPE 0x5480 +#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 +#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 +#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ + +/* + * Check for platforms where the south display is on the same PCI device or SoC + * die as the north display. The PCH (if it even exists) is not involved in + * display. Return a fake PCH type for south display handling on these + * platforms, without actually detecting the PCH, and PCH_NONE otherwise. + */ +static enum intel_pch intel_pch_fake_for_south_display(struct intel_display *display) +{ + enum intel_pch pch_type = PCH_NONE; + + if (DISPLAY_VER(display) >= 20) + pch_type = PCH_LNL; + else if (display->platform.battlemage || display->platform.meteorlake) + pch_type = PCH_MTL; + else if (display->platform.dg2) + pch_type = PCH_DG2; + else if (display->platform.dg1) + pch_type = PCH_DG1; + + return pch_type; +} + +/* Map PCH device id to PCH type, or PCH_NONE if unknown. */ +static enum intel_pch +intel_pch_type(const struct intel_display *display, unsigned short id) +{ + switch (id) { + case INTEL_PCH_IBX_DEVICE_ID_TYPE: + drm_dbg_kms(display->drm, "Found Ibex Peak PCH\n"); + drm_WARN_ON(display->drm, DISPLAY_VER(display) != 5); + return PCH_IBX; + case INTEL_PCH_CPT_DEVICE_ID_TYPE: + drm_dbg_kms(display->drm, "Found CougarPoint PCH\n"); + drm_WARN_ON(display->drm, + DISPLAY_VER(display) != 6 && + !display->platform.ivybridge); + return PCH_CPT; + case INTEL_PCH_PPT_DEVICE_ID_TYPE: + drm_dbg_kms(display->drm, "Found PantherPoint PCH\n"); + drm_WARN_ON(display->drm, + DISPLAY_VER(display) != 6 && + !display->platform.ivybridge); + /* PPT is CPT compatible */ + return PCH_CPT; + case INTEL_PCH_LPT_DEVICE_ID_TYPE: + drm_dbg_kms(display->drm, "Found LynxPoint PCH\n"); + drm_WARN_ON(display->drm, + !display->platform.haswell && + !display->platform.broadwell); + drm_WARN_ON(display->drm, + display->platform.haswell_ult || + display->platform.broadwell_ult); + return PCH_LPT_H; + case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE: + drm_dbg_kms(display->drm, "Found LynxPoint LP PCH\n"); + drm_WARN_ON(display->drm, + !display->platform.haswell && + !display->platform.broadwell); + drm_WARN_ON(display->drm, + !display->platform.haswell_ult && + !display->platform.broadwell_ult); + return PCH_LPT_LP; + case INTEL_PCH_WPT_DEVICE_ID_TYPE: + drm_dbg_kms(display->drm, "Found WildcatPoint PCH\n"); + drm_WARN_ON(display->drm, + !display->platform.haswell && + !display->platform.broadwell); + drm_WARN_ON(display->drm, + display->platform.haswell_ult || + display->platform.broadwell_ult); + /* WPT is LPT compatible */ + return PCH_LPT_H; + case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE: + drm_dbg_kms(display->drm, "Found WildcatPoint LP PCH\n"); + drm_WARN_ON(display->drm, + !display->platform.haswell && + !display->platform.broadwell); + drm_WARN_ON(display->drm, + !display->platform.haswell_ult && + !display->platform.broadwell_ult); + /* WPT is LPT compatible */ + return PCH_LPT_LP; + case INTEL_PCH_SPT_DEVICE_ID_TYPE: + drm_dbg_kms(display->drm, "Found SunrisePoint PCH\n"); + drm_WARN_ON(display->drm, + !display->platform.skylake && + !display->platform.kabylake && + !display->platform.coffeelake); + return PCH_SPT; + case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE: + drm_dbg_kms(display->drm, "Found SunrisePoint LP PCH\n"); + drm_WARN_ON(display->drm, + !display->platform.skylake && + !display->platform.kabylake && + !display->platform.coffeelake && + !display->platform.cometlake); + return PCH_SPT; + case INTEL_PCH_KBP_DEVICE_ID_TYPE: + drm_dbg_kms(display->drm, "Found Kaby Lake PCH (KBP)\n"); + drm_WARN_ON(display->drm, + !display->platform.skylake && + !display->platform.kabylake && + !display->platform.coffeelake && + !display->platform.cometlake); + /* KBP is SPT compatible */ + return PCH_SPT; + case INTEL_PCH_CNP_DEVICE_ID_TYPE: + drm_dbg_kms(display->drm, "Found Cannon Lake PCH (CNP)\n"); + drm_WARN_ON(display->drm, + !display->platform.coffeelake && + !display->platform.cometlake); + return PCH_CNP; + case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE: + drm_dbg_kms(display->drm, + "Found Cannon Lake LP PCH (CNP-LP)\n"); + drm_WARN_ON(display->drm, + !display->platform.coffeelake && + !display->platform.cometlake); + return PCH_CNP; + case INTEL_PCH_CMP_DEVICE_ID_TYPE: + case INTEL_PCH_CMP2_DEVICE_ID_TYPE: + drm_dbg_kms(display->drm, "Found Comet Lake PCH (CMP)\n"); + drm_WARN_ON(display->drm, + !display->platform.coffeelake && + !display->platform.cometlake && + !display->platform.rocketlake); + /* CMP is CNP compatible */ + return PCH_CNP; + case INTEL_PCH_CMP_V_DEVICE_ID_TYPE: + drm_dbg_kms(display->drm, "Found Comet Lake V PCH (CMP-V)\n"); + drm_WARN_ON(display->drm, + !display->platform.coffeelake && + !display->platform.cometlake); + /* CMP-V is based on KBP, which is SPT compatible */ + return PCH_SPT; + case INTEL_PCH_ICP_DEVICE_ID_TYPE: + case INTEL_PCH_ICP2_DEVICE_ID_TYPE: + drm_dbg_kms(display->drm, "Found Ice Lake PCH\n"); + drm_WARN_ON(display->drm, !display->platform.icelake); + return PCH_ICP; + case INTEL_PCH_MCC_DEVICE_ID_TYPE: + drm_dbg_kms(display->drm, "Found Mule Creek Canyon PCH\n"); + drm_WARN_ON(display->drm, !(display->platform.jasperlake || + display->platform.elkhartlake)); + /* MCC is TGP compatible */ + return PCH_TGP; + case INTEL_PCH_TGP_DEVICE_ID_TYPE: + case INTEL_PCH_TGP2_DEVICE_ID_TYPE: + drm_dbg_kms(display->drm, "Found Tiger Lake LP PCH\n"); + drm_WARN_ON(display->drm, !display->platform.tigerlake && + !display->platform.rocketlake && + !display->platform.skylake && + !display->platform.kabylake && + !display->platform.coffeelake && + !display->platform.cometlake); + return PCH_TGP; + case INTEL_PCH_JSP_DEVICE_ID_TYPE: + drm_dbg_kms(display->drm, "Found Jasper Lake PCH\n"); + drm_WARN_ON(display->drm, !(display->platform.jasperlake || + display->platform.elkhartlake)); + /* JSP is ICP compatible */ + return PCH_ICP; + case INTEL_PCH_ADP_DEVICE_ID_TYPE: + case INTEL_PCH_ADP2_DEVICE_ID_TYPE: + case INTEL_PCH_ADP3_DEVICE_ID_TYPE: + case INTEL_PCH_ADP4_DEVICE_ID_TYPE: + drm_dbg_kms(display->drm, "Found Alder Lake PCH\n"); + drm_WARN_ON(display->drm, !display->platform.alderlake_s && + !display->platform.alderlake_p); + return PCH_ADP; + default: + return PCH_NONE; + } +} + +static bool intel_is_virt_pch(unsigned short id, + unsigned short svendor, unsigned short sdevice) +{ + return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE || + id == INTEL_PCH_P3X_DEVICE_ID_TYPE || + (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE && + svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET && + sdevice == PCI_SUBDEVICE_ID_QEMU)); +} + +static void +intel_virt_detect_pch(const struct intel_display *display, + unsigned short *pch_id, enum intel_pch *pch_type) +{ + unsigned short id = 0; + + /* + * In a virtualized passthrough environment we can be in a + * setup where the ISA bridge is not able to be passed through. + * In this case, a south bridge can be emulated and we have to + * make an educated guess as to which PCH is really there. + */ + + if (display->platform.alderlake_s || display->platform.alderlake_p) + id = INTEL_PCH_ADP_DEVICE_ID_TYPE; + else if (display->platform.tigerlake || display->platform.rocketlake) + id = INTEL_PCH_TGP_DEVICE_ID_TYPE; + else if (display->platform.jasperlake || display->platform.elkhartlake) + id = INTEL_PCH_MCC_DEVICE_ID_TYPE; + else if (display->platform.icelake) + id = INTEL_PCH_ICP_DEVICE_ID_TYPE; + else if (display->platform.coffeelake || + display->platform.cometlake) + id = INTEL_PCH_CNP_DEVICE_ID_TYPE; + else if (display->platform.kabylake || display->platform.skylake) + id = INTEL_PCH_SPT_DEVICE_ID_TYPE; + else if (display->platform.haswell_ult || + display->platform.broadwell_ult) + id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE; + else if (display->platform.haswell || display->platform.broadwell) + id = INTEL_PCH_LPT_DEVICE_ID_TYPE; + else if (DISPLAY_VER(display) == 6 || display->platform.ivybridge) + id = INTEL_PCH_CPT_DEVICE_ID_TYPE; + else if (DISPLAY_VER(display) == 5) + id = INTEL_PCH_IBX_DEVICE_ID_TYPE; + + if (id) + drm_dbg_kms(display->drm, "Assuming PCH ID %04x\n", id); + else + drm_dbg_kms(display->drm, "Assuming no PCH\n"); + + *pch_type = intel_pch_type(display, id); + + /* Sanity check virtual PCH id */ + if (drm_WARN_ON(display->drm, + id && *pch_type == PCH_NONE)) + id = 0; + + *pch_id = id; +} + +void intel_pch_detect(struct intel_display *display) +{ + struct pci_dev *pch = NULL; + unsigned short id; + enum intel_pch pch_type; + + pch_type = intel_pch_fake_for_south_display(display); + if (pch_type != PCH_NONE) { + display->pch_type = pch_type; + drm_dbg_kms(display->drm, + "PCH not involved in display, using fake PCH type %d for south display\n", + pch_type); + return; + } + + /* + * The reason to probe ISA bridge instead of Dev31:Fun0 is to + * make graphics device passthrough work easy for VMM, that only + * need to expose ISA bridge to let driver know the real hardware + * underneath. This is a requirement from virtualization team. + * + * In some virtualized environments (e.g. XEN), there is irrelevant + * ISA bridge in the system. To work reliably, we should scan through + * all the ISA bridge devices and check for the first match, instead + * of only checking the first one. + */ + while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { + if (pch->vendor != PCI_VENDOR_ID_INTEL) + continue; + + id = pch->device & INTEL_PCH_DEVICE_ID_MASK; + + pch_type = intel_pch_type(display, id); + if (pch_type != PCH_NONE) { + display->pch_type = pch_type; + break; + } else if (intel_is_virt_pch(id, pch->subsystem_vendor, + pch->subsystem_device)) { + intel_virt_detect_pch(display, &id, &pch_type); + display->pch_type = pch_type; + break; + } + } + + /* + * Use PCH_NOP (PCH but no South Display) for PCH platforms without + * display. + */ + if (pch && !HAS_DISPLAY(display)) { + drm_dbg_kms(display->drm, + "Display disabled, reverting to NOP PCH\n"); + display->pch_type = PCH_NOP; + } else if (!pch) { + if (i915_run_as_guest() && HAS_DISPLAY(display)) { + intel_virt_detect_pch(display, &id, &pch_type); + display->pch_type = pch_type; + } else { + drm_dbg_kms(display->drm, "No PCH found.\n"); + } + } + + pci_dev_put(pch); +} diff --git a/drivers/gpu/drm/i915/display/intel_pch.h b/drivers/gpu/drm/i915/display/intel_pch.h new file mode 100644 index 000000000000..cf4dab1b98bf --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_pch.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Intel Corporation. + */ + +#ifndef __INTEL_PCH__ +#define __INTEL_PCH__ + +#include "intel_display_conversion.h" + +struct intel_display; + +/* + * Sorted by south display engine compatibility. + * If the new PCH comes with a south display engine that is not + * inherited from the latest item, please do not add it to the + * end. Instead, add it right after its "parent" PCH. + */ +enum intel_pch { + PCH_NOP = -1, /* PCH without south display */ + PCH_NONE = 0, /* No PCH present */ + PCH_IBX, /* Ibexpeak PCH */ + PCH_CPT, /* Cougarpoint/Pantherpoint PCH */ + PCH_LPT_H, /* Lynxpoint/Wildcatpoint H PCH */ + PCH_LPT_LP, /* Lynxpoint/Wildcatpoint LP PCH */ + PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */ + PCH_CNP, /* Cannon/Comet Lake PCH */ + PCH_ICP, /* Ice Lake/Jasper Lake PCH */ + PCH_TGP, /* Tiger Lake/Mule Creek Canyon PCH */ + PCH_ADP, /* Alder Lake PCH */ + + /* Fake PCHs, functionality handled on the same PCI dev */ + PCH_DG1 = 1024, + PCH_DG2, + PCH_MTL, + PCH_LNL, +}; + +#define INTEL_PCH_TYPE(_display) (__to_intel_display(_display)->pch_type) +#define HAS_PCH_DG2(display) (INTEL_PCH_TYPE(display) == PCH_DG2) +#define HAS_PCH_ADP(display) (INTEL_PCH_TYPE(display) == PCH_ADP) +#define HAS_PCH_DG1(display) (INTEL_PCH_TYPE(display) == PCH_DG1) +#define HAS_PCH_TGP(display) (INTEL_PCH_TYPE(display) == PCH_TGP) +#define HAS_PCH_ICP(display) (INTEL_PCH_TYPE(display) == PCH_ICP) +#define HAS_PCH_CNP(display) (INTEL_PCH_TYPE(display) == PCH_CNP) +#define HAS_PCH_SPT(display) (INTEL_PCH_TYPE(display) == PCH_SPT) +#define HAS_PCH_LPT_H(display) (INTEL_PCH_TYPE(display) == PCH_LPT_H) +#define HAS_PCH_LPT_LP(display) (INTEL_PCH_TYPE(display) == PCH_LPT_LP) +#define HAS_PCH_LPT(display) (INTEL_PCH_TYPE(display) == PCH_LPT_H || \ + INTEL_PCH_TYPE(display) == PCH_LPT_LP) +#define HAS_PCH_CPT(display) (INTEL_PCH_TYPE(display) == PCH_CPT) +#define HAS_PCH_IBX(display) (INTEL_PCH_TYPE(display) == PCH_IBX) +#define HAS_PCH_NOP(display) (INTEL_PCH_TYPE(display) == PCH_NOP) +#define HAS_PCH_SPLIT(display) (INTEL_PCH_TYPE(display) != PCH_NONE) + +void intel_pch_detect(struct intel_display *display); + +#endif /* __INTEL_PCH__ */ diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index b909ed18a5b2..3456c794e0e7 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -3,12 +3,14 @@ * Copyright © 2021 Intel Corporation */ +#include <drm/drm_print.h> + #include "g4x_dp.h" -#include "i915_drv.h" #include "i915_reg.h" #include "intel_crt.h" #include "intel_crt_regs.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dpll.h" #include "intel_fdi.h" @@ -23,17 +25,15 @@ bool intel_has_pch_trancoder(struct intel_display *display, enum pipe pch_transcoder) { - struct drm_i915_private *i915 = to_i915(display->drm); - - return HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915) || - (HAS_PCH_LPT_H(i915) && pch_transcoder == PIPE_A); + return HAS_PCH_IBX(display) || HAS_PCH_CPT(display) || + (HAS_PCH_LPT_H(display) && pch_transcoder == PIPE_A); } enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); - if (HAS_PCH_LPT(i915)) + if (HAS_PCH_LPT(display)) return PIPE_A; else return crtc->pipe; @@ -43,7 +43,6 @@ static void assert_pch_dp_disabled(struct intel_display *display, enum pipe pipe, enum port port, i915_reg_t dp_reg) { - struct drm_i915_private *dev_priv = to_i915(display->drm); enum pipe port_pipe; bool state; @@ -54,7 +53,7 @@ static void assert_pch_dp_disabled(struct intel_display *display, port_name(port), pipe_name(pipe)); INTEL_DISPLAY_STATE_WARN(display, - HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, + HAS_PCH_IBX(display) && !state && port_pipe == PIPE_B, "IBX PCH DP %c still using transcoder B\n", port_name(port)); } @@ -63,7 +62,6 @@ static void assert_pch_hdmi_disabled(struct intel_display *display, enum pipe pipe, enum port port, i915_reg_t hdmi_reg) { - struct drm_i915_private *dev_priv = to_i915(display->drm); enum pipe port_pipe; bool state; @@ -74,7 +72,7 @@ static void assert_pch_hdmi_disabled(struct intel_display *display, port_name(port), pipe_name(pipe)); INTEL_DISPLAY_STATE_WARN(display, - HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, + HAS_PCH_IBX(display) && !state && port_pipe == PIPE_B, "IBX PCH HDMI %c still using transcoder B\n", port_name(port)); } @@ -249,19 +247,18 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; i915_reg_t reg; u32 val, pipeconf_val; /* Make sure PCH DPLL is enabled */ - assert_shared_dpll_enabled(display, crtc_state->shared_dpll); + assert_dpll_enabled(display, crtc_state->intel_dpll); /* FDI must be feeding us bits for PCH ports */ assert_fdi_tx_enabled(display, pipe); assert_fdi_rx_enabled(display, pipe); - if (HAS_PCH_CPT(dev_priv)) { + if (HAS_PCH_CPT(display)) { reg = TRANS_CHICKEN2(pipe); val = intel_de_read(display, reg); /* @@ -279,7 +276,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) val = intel_de_read(display, reg); pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe)); - if (HAS_PCH_IBX(dev_priv)) { + if (HAS_PCH_IBX(display)) { /* Configure frame start delay to match the CPU */ val &= ~TRANS_FRAME_START_DELAY_MASK; val |= TRANS_FRAME_START_DELAY(crtc_state->framestart_delay - 1); @@ -298,7 +295,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) val &= ~TRANS_INTERLACE_MASK; if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_ILK) == TRANSCONF_INTERLACE_IF_ID_ILK) { - if (HAS_PCH_IBX(dev_priv) && + if (HAS_PCH_IBX(display) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX; else @@ -316,7 +313,6 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) static void ilk_disable_pch_transcoder(struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; i915_reg_t reg; @@ -334,7 +330,7 @@ static void ilk_disable_pch_transcoder(struct intel_crtc *crtc) drm_err(display->drm, "failed to disable transcoder %c\n", pipe_name(pipe)); - if (HAS_PCH_CPT(dev_priv)) + if (HAS_PCH_CPT(display)) /* Workaround: Clear the timing override chicken bit again. */ intel_de_rmw(display, TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE, 0); @@ -366,7 +362,6 @@ void ilk_pch_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; @@ -381,14 +376,14 @@ void ilk_pch_enable(struct intel_atomic_state *state, * We need to program the right clock selection * before writing the pixel multiplier into the DPLL. */ - if (HAS_PCH_CPT(dev_priv)) { + if (HAS_PCH_CPT(display)) { u32 sel; temp = intel_de_read(display, PCH_DPLL_SEL); temp |= TRANS_DPLL_ENABLE(pipe); sel = TRANS_DPLLB_SEL(pipe); - if (crtc_state->shared_dpll == - intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B)) + if (crtc_state->intel_dpll == + intel_get_dpll_by_id(display, DPLL_ID_PCH_PLL_B)) temp |= sel; else temp &= ~sel; @@ -400,11 +395,11 @@ void ilk_pch_enable(struct intel_atomic_state *state, * transcoder, and we actually should do this to not upset any PCH * transcoder that already use the clock when we share it. * - * Note that enable_shared_dpll tries to do the right thing, but - * get_shared_dpll unconditionally resets the pll - we need that + * Note that dpll_enable tries to do the right thing, but + * get_dpll unconditionally resets the pll - we need that * to have the right LVDS enable sequence. */ - intel_enable_shared_dpll(crtc_state); + intel_dpll_enable(crtc_state); /* set transcoder timing, panel must allow it */ assert_pps_unlocked(display, pipe); @@ -417,7 +412,7 @@ void ilk_pch_enable(struct intel_atomic_state *state, intel_fdi_normal_train(crtc); /* For PCH DP, enable TRANS_DP_CTL */ - if (HAS_PCH_CPT(dev_priv) && + if (HAS_PCH_CPT(display) && intel_crtc_has_dp_encoder(crtc_state)) { const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; @@ -459,14 +454,13 @@ void ilk_pch_post_disable(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; ilk_disable_pch_transcoder(crtc); - if (HAS_PCH_CPT(dev_priv)) { + if (HAS_PCH_CPT(display)) { /* disable TRANS_DP_CTL */ intel_de_rmw(display, TRANS_DP_CTL(pipe), TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK, @@ -479,7 +473,7 @@ void ilk_pch_post_disable(struct intel_atomic_state *state, ilk_fdi_pll_disable(crtc); - intel_disable_shared_dpll(old_crtc_state); + intel_dpll_disable(old_crtc_state); } static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state) @@ -503,8 +497,7 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_shared_dpll *pll; + struct intel_dpll *pll; enum pipe pipe = crtc->pipe; enum intel_dpll_id pll_id; bool pll_active; @@ -522,7 +515,7 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state) intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, &crtc_state->fdi_m_n); - if (HAS_PCH_IBX(dev_priv)) { + if (HAS_PCH_IBX(display)) { /* * The pipe->pch transcoder and pch transcoder->pll * mapping is fixed. @@ -536,8 +529,8 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state) pll_id = DPLL_ID_PCH_PLL_A; } - crtc_state->shared_dpll = intel_get_shared_dpll_by_id(display, pll_id); - pll = crtc_state->shared_dpll; + crtc_state->intel_dpll = intel_get_dpll_by_id(display, pll_id); + pll = crtc_state->intel_dpll; pll_active = intel_dpll_get_hw_state(display, pll, &crtc_state->dpll_hw_state); @@ -646,8 +639,6 @@ void lpt_pch_get_config(struct intel_crtc_state *crtc_state) void intel_pch_sanitize(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - - if (HAS_PCH_IBX(i915)) + if (HAS_PCH_IBX(display)) ibx_sanitize_pch_ports(display); } diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c index 1307a478861a..d3c5255bf1a8 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c @@ -3,13 +3,17 @@ * Copyright © 2021 Intel Corporation */ -#include "i915_drv.h" +#include <drm/drm_print.h> + #include "i915_reg.h" +#include "i915_utils.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_panel.h" #include "intel_pch_refclk.h" #include "intel_sbi.h" +#include "intel_sbi_regs.h" static void lpt_fdi_reset_mphy(struct intel_display *display) { @@ -29,95 +33,93 @@ static void lpt_fdi_reset_mphy(struct intel_display *display) /* WaMPhyProgramming:hsw */ static void lpt_fdi_program_mphy(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 tmp; lpt_fdi_reset_mphy(display); - tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); + tmp = intel_sbi_read(display, 0x8008, SBI_MPHY); tmp &= ~(0xFF << 24); tmp |= (0x12 << 24); - intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); + intel_sbi_write(display, 0x8008, tmp, SBI_MPHY); - tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); + tmp = intel_sbi_read(display, 0x2008, SBI_MPHY); tmp |= (1 << 11); - intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); + intel_sbi_write(display, 0x2008, tmp, SBI_MPHY); - tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); + tmp = intel_sbi_read(display, 0x2108, SBI_MPHY); tmp |= (1 << 11); - intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); + intel_sbi_write(display, 0x2108, tmp, SBI_MPHY); - tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); + tmp = intel_sbi_read(display, 0x206C, SBI_MPHY); tmp |= (1 << 24) | (1 << 21) | (1 << 18); - intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); + intel_sbi_write(display, 0x206C, tmp, SBI_MPHY); - tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); + tmp = intel_sbi_read(display, 0x216C, SBI_MPHY); tmp |= (1 << 24) | (1 << 21) | (1 << 18); - intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); + intel_sbi_write(display, 0x216C, tmp, SBI_MPHY); - tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); + tmp = intel_sbi_read(display, 0x2080, SBI_MPHY); tmp &= ~(7 << 13); tmp |= (5 << 13); - intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); + intel_sbi_write(display, 0x2080, tmp, SBI_MPHY); - tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); + tmp = intel_sbi_read(display, 0x2180, SBI_MPHY); tmp &= ~(7 << 13); tmp |= (5 << 13); - intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); + intel_sbi_write(display, 0x2180, tmp, SBI_MPHY); - tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); + tmp = intel_sbi_read(display, 0x208C, SBI_MPHY); tmp &= ~0xFF; tmp |= 0x1C; - intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); + intel_sbi_write(display, 0x208C, tmp, SBI_MPHY); - tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); + tmp = intel_sbi_read(display, 0x218C, SBI_MPHY); tmp &= ~0xFF; tmp |= 0x1C; - intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); + intel_sbi_write(display, 0x218C, tmp, SBI_MPHY); - tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); + tmp = intel_sbi_read(display, 0x2098, SBI_MPHY); tmp &= ~(0xFF << 16); tmp |= (0x1C << 16); - intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); + intel_sbi_write(display, 0x2098, tmp, SBI_MPHY); - tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); + tmp = intel_sbi_read(display, 0x2198, SBI_MPHY); tmp &= ~(0xFF << 16); tmp |= (0x1C << 16); - intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); + intel_sbi_write(display, 0x2198, tmp, SBI_MPHY); - tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); + tmp = intel_sbi_read(display, 0x20C4, SBI_MPHY); tmp |= (1 << 27); - intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); + intel_sbi_write(display, 0x20C4, tmp, SBI_MPHY); - tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); + tmp = intel_sbi_read(display, 0x21C4, SBI_MPHY); tmp |= (1 << 27); - intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); + intel_sbi_write(display, 0x21C4, tmp, SBI_MPHY); - tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); + tmp = intel_sbi_read(display, 0x20EC, SBI_MPHY); tmp &= ~(0xF << 28); tmp |= (4 << 28); - intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); + intel_sbi_write(display, 0x20EC, tmp, SBI_MPHY); - tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); + tmp = intel_sbi_read(display, 0x21EC, SBI_MPHY); tmp &= ~(0xF << 28); tmp |= (4 << 28); - intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); + intel_sbi_write(display, 0x21EC, tmp, SBI_MPHY); } void lpt_disable_iclkip(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 temp; intel_de_write(display, PIXCLK_GATE, PIXCLK_GATE_GATE); - intel_sbi_lock(dev_priv); + intel_sbi_lock(display); - temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); + temp = intel_sbi_read(display, SBI_SSCCTL6, SBI_ICLK); temp |= SBI_SSCCTL_DISABLE; - intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); + intel_sbi_write(display, SBI_SSCCTL6, temp, SBI_ICLK); - intel_sbi_unlock(dev_priv); + intel_sbi_unlock(display); } struct iclkip_params { @@ -178,8 +180,6 @@ int lpt_iclkip(const struct intel_crtc_state *crtc_state) void lpt_program_iclkip(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); int clock = crtc_state->hw.adjusted_mode.crtc_clock; struct iclkip_params p; u32 temp; @@ -199,30 +199,30 @@ void lpt_program_iclkip(const struct intel_crtc_state *crtc_state) "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", clock, p.auxdiv, p.divsel, p.phasedir, p.phaseinc); - intel_sbi_lock(dev_priv); + intel_sbi_lock(display); /* Program SSCDIVINTPHASE6 */ - temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); + temp = intel_sbi_read(display, SBI_SSCDIVINTPHASE6, SBI_ICLK); temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; temp |= SBI_SSCDIVINTPHASE_DIVSEL(p.divsel); temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; temp |= SBI_SSCDIVINTPHASE_INCVAL(p.phaseinc); temp |= SBI_SSCDIVINTPHASE_DIR(p.phasedir); temp |= SBI_SSCDIVINTPHASE_PROPAGATE; - intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); + intel_sbi_write(display, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); /* Program SSCAUXDIV */ - temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); + temp = intel_sbi_read(display, SBI_SSCAUXDIV6, SBI_ICLK); temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); temp |= SBI_SSCAUXDIV_FINALDIV2SEL(p.auxdiv); - intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); + intel_sbi_write(display, SBI_SSCAUXDIV6, temp, SBI_ICLK); /* Enable modulator and associated divider */ - temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); + temp = intel_sbi_read(display, SBI_SSCCTL6, SBI_ICLK); temp &= ~SBI_SSCCTL_DISABLE; - intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); + intel_sbi_write(display, SBI_SSCCTL6, temp, SBI_ICLK); - intel_sbi_unlock(dev_priv); + intel_sbi_unlock(display); /* Wait for initialization time */ udelay(24); @@ -232,7 +232,6 @@ void lpt_program_iclkip(const struct intel_crtc_state *crtc_state) int lpt_get_iclkip(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct iclkip_params p; u32 temp; @@ -241,25 +240,25 @@ int lpt_get_iclkip(struct intel_display *display) iclkip_params_init(&p); - intel_sbi_lock(dev_priv); + intel_sbi_lock(display); - temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); + temp = intel_sbi_read(display, SBI_SSCCTL6, SBI_ICLK); if (temp & SBI_SSCCTL_DISABLE) { - intel_sbi_unlock(dev_priv); + intel_sbi_unlock(display); return 0; } - temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); + temp = intel_sbi_read(display, SBI_SSCDIVINTPHASE6, SBI_ICLK); p.divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; p.phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> SBI_SSCDIVINTPHASE_INCVAL_SHIFT; - temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); + temp = intel_sbi_read(display, SBI_SSCAUXDIV6, SBI_ICLK); p.auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; - intel_sbi_unlock(dev_priv); + intel_sbi_unlock(display); p.desired_divisor = (p.divsel + 2) * p.iclk_pi_range + p.phaseinc; @@ -275,67 +274,65 @@ int lpt_get_iclkip(struct intel_display *display) static void lpt_enable_clkout_dp(struct intel_display *display, bool with_spread, bool with_fdi) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 reg, tmp; if (drm_WARN(display->drm, with_fdi && !with_spread, "FDI requires downspread\n")) with_spread = true; - if (drm_WARN(display->drm, HAS_PCH_LPT_LP(dev_priv) && + if (drm_WARN(display->drm, HAS_PCH_LPT_LP(display) && with_fdi, "LP PCH doesn't have FDI\n")) with_fdi = false; - intel_sbi_lock(dev_priv); + intel_sbi_lock(display); - tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); + tmp = intel_sbi_read(display, SBI_SSCCTL, SBI_ICLK); tmp &= ~SBI_SSCCTL_DISABLE; tmp |= SBI_SSCCTL_PATHALT; - intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); + intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK); udelay(24); if (with_spread) { - tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); + tmp = intel_sbi_read(display, SBI_SSCCTL, SBI_ICLK); tmp &= ~SBI_SSCCTL_PATHALT; - intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); + intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK); if (with_fdi) lpt_fdi_program_mphy(display); } - reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; - tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); + reg = HAS_PCH_LPT_LP(display) ? SBI_GEN0 : SBI_DBUFF0; + tmp = intel_sbi_read(display, reg, SBI_ICLK); tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; - intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); + intel_sbi_write(display, reg, tmp, SBI_ICLK); - intel_sbi_unlock(dev_priv); + intel_sbi_unlock(display); } /* Sequence to disable CLKOUT_DP */ void lpt_disable_clkout_dp(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 reg, tmp; - intel_sbi_lock(dev_priv); + intel_sbi_lock(display); - reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; - tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); + reg = HAS_PCH_LPT_LP(display) ? SBI_GEN0 : SBI_DBUFF0; + tmp = intel_sbi_read(display, reg, SBI_ICLK); tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; - intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); + intel_sbi_write(display, reg, tmp, SBI_ICLK); - tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); + tmp = intel_sbi_read(display, SBI_SSCCTL, SBI_ICLK); if (!(tmp & SBI_SSCCTL_DISABLE)) { if (!(tmp & SBI_SSCCTL_PATHALT)) { tmp |= SBI_SSCCTL_PATHALT; - intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); + intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK); udelay(32); } tmp |= SBI_SSCCTL_DISABLE; - intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); + intel_sbi_write(display, SBI_SSCCTL, tmp, SBI_ICLK); } - intel_sbi_unlock(dev_priv); + intel_sbi_unlock(display); } #define BEND_IDX(steps) ((50 + (steps)) / 5) @@ -372,7 +369,6 @@ static const u16 sscdivintphase[] = { */ static void lpt_bend_clkout_dp(struct intel_display *display, int steps) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 tmp; int idx = BEND_IDX(steps); @@ -382,20 +378,20 @@ static void lpt_bend_clkout_dp(struct intel_display *display, int steps) if (drm_WARN_ON(display->drm, idx >= ARRAY_SIZE(sscdivintphase))) return; - intel_sbi_lock(dev_priv); + intel_sbi_lock(display); if (steps % 10 != 0) tmp = 0xAAAAAAAB; else tmp = 0x00000000; - intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); + intel_sbi_write(display, SBI_SSCDITHPHASE, tmp, SBI_ICLK); - tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); + tmp = intel_sbi_read(display, SBI_SSCDIVINTPHASE, SBI_ICLK); tmp &= 0xffff0000; tmp |= sscdivintphase[idx]; - intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); + intel_sbi_write(display, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); - intel_sbi_unlock(dev_priv); + intel_sbi_unlock(display); } #undef BEND_IDX @@ -498,9 +494,8 @@ static void lpt_init_pch_refclk(struct intel_display *display) static void ilk_init_pch_refclk(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_encoder *encoder; - struct intel_shared_dpll *pll; + struct intel_dpll *pll; int i; u32 val, final; bool has_lvds = false; @@ -527,7 +522,7 @@ static void ilk_init_pch_refclk(struct intel_display *display) } } - if (HAS_PCH_IBX(dev_priv)) { + if (HAS_PCH_IBX(display)) { has_ck505 = display->vbt.display_clock_mode; can_ssc = has_ck505; } else { @@ -536,7 +531,7 @@ static void ilk_init_pch_refclk(struct intel_display *display) } /* Check if any DPLLs are using the SSC source */ - for_each_shared_dpll(display, pll, i) { + for_each_dpll(display, pll, i) { u32 temp; temp = intel_de_read(display, PCH_DPLL(pll->info->id)); @@ -678,10 +673,8 @@ static void ilk_init_pch_refclk(struct intel_display *display) */ void intel_init_pch_refclk(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - - if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) + if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) ilk_init_pch_refclk(display); - else if (HAS_PCH_LPT(dev_priv)) + else if (HAS_PCH_LPT(display)) lpt_init_pch_refclk(display); } diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c index 3c3ecf288570..13541be4d6df 100644 --- a/drivers/gpu/drm/i915/display/intel_pfit.c +++ b/drivers/gpu/drm/i915/display/intel_pfit.c @@ -5,11 +5,11 @@ #include <drm/drm_print.h> -#include "i915_reg.h" #include "i915_utils.h" #include "intel_de.h" #include "intel_display_core.h" #include "intel_display_driver.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_lvds_regs.h" #include "intel_pfit.h" diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c index 6182f484b5bd..c2b4b2254190 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c @@ -30,10 +30,10 @@ #include "i915_drv.h" #include "i915_irq.h" -#include "i915_reg.h" #include "intel_atomic.h" #include "intel_de.h" #include "intel_display_irq.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_pipe_crc.h" #include "intel_pipe_crc_regs.h" diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c index b0c4892775ce..8800a657cd21 100644 --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c @@ -9,6 +9,7 @@ #include "intel_atomic_plane.h" #include "intel_crtc.h" #include "intel_display.h" +#include "intel_display_core.h" #include "intel_display_types.h" #include "intel_fb.h" #include "intel_frontbuffer.h" @@ -53,9 +54,11 @@ intel_reuse_initial_plane_obj(struct intel_crtc *this, } static enum intel_memory_type -initial_plane_memory_type(struct drm_i915_private *i915) +initial_plane_memory_type(struct intel_display *display) { - if (IS_DGFX(i915)) + struct drm_i915_private *i915 = to_i915(display->drm); + + if (display->platform.dgfx) return INTEL_MEMORY_LOCAL; else if (HAS_LMEMBAR_SMEM_STOLEN(i915)) return INTEL_MEMORY_STOLEN_LOCAL; @@ -75,7 +78,7 @@ initial_plane_phys(struct intel_display *display, dma_addr_t dma_addr; u32 base; - mem_type = initial_plane_memory_type(i915); + mem_type = initial_plane_memory_type(display); mem = intel_memory_region_by_type(i915, mem_type); if (!mem) { drm_dbg_kms(display->drm, diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c index d22b5469672d..93d5ee36fff1 100644 --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c @@ -7,12 +7,12 @@ #include <drm/drm_print.h> -#include "i915_reg.h" #include "i915_utils.h" #include "intel_atomic.h" #include "intel_bw.h" #include "intel_cdclk.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_trace.h" #include "intel_pmdemand.h" #include "intel_step.h" @@ -478,13 +478,34 @@ static bool intel_pmdemand_req_complete(struct intel_display *display) XELPDP_PMDEMAND_REQ_ENABLE); } -static void intel_pmdemand_wait(struct intel_display *display) +static void intel_pmdemand_poll(struct intel_display *display) { - if (!wait_event_timeout(display->pmdemand.waitqueue, - intel_pmdemand_req_complete(display), - msecs_to_jiffies_timeout(10))) + const unsigned int timeout_ms = 10; + u32 status; + int ret; + + ret = intel_de_wait_custom(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1), + XELPDP_PMDEMAND_REQ_ENABLE, 0, + 50, timeout_ms, &status); + + if (ret == -ETIMEDOUT) drm_err(display->drm, - "timed out waiting for Punit PM Demand Response\n"); + "timed out waiting for Punit PM Demand Response within %ums (status 0x%08x)\n", + timeout_ms, status); +} + +static void intel_pmdemand_wait(struct intel_display *display) +{ + /* Wa_14024400148 For lnl use polling method */ + if (DISPLAY_VER(display) == 20) { + intel_pmdemand_poll(display); + } else { + if (!wait_event_timeout(display->pmdemand.waitqueue, + intel_pmdemand_req_complete(display), + msecs_to_jiffies_timeout(10))) + drm_err(display->drm, + "timed out waiting for Punit PM Demand Response\n"); + } } /* Required to be programmed during Display Init Sequences. */ diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 4d4e2b9f5f2d..bff81fb5c316 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -10,6 +10,7 @@ #include "i915_reg.h" #include "intel_de.h" #include "intel_display_power_well.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dpio_phy.h" @@ -350,21 +351,19 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) static int intel_num_pps(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - if (display->platform.valleyview || display->platform.cherryview) return 2; if (display->platform.geminilake || display->platform.broxton) return 2; - if (INTEL_PCH_TYPE(i915) >= PCH_MTL) + if (INTEL_PCH_TYPE(display) >= PCH_MTL) return 2; - if (INTEL_PCH_TYPE(i915) >= PCH_DG1) + if (INTEL_PCH_TYPE(display) >= PCH_DG1) return 1; - if (INTEL_PCH_TYPE(i915) >= PCH_ICP) + if (INTEL_PCH_TYPE(display) >= PCH_ICP) return 2; return 1; @@ -373,11 +372,10 @@ static int intel_num_pps(struct intel_display *display) static bool intel_pps_is_valid(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *i915 = to_i915(display->drm); if (intel_dp->pps.pps_idx == 1 && - INTEL_PCH_TYPE(i915) >= PCH_ICP && - INTEL_PCH_TYPE(i915) <= PCH_ADP) + INTEL_PCH_TYPE(display) >= PCH_ICP && + INTEL_PCH_TYPE(display) <= PCH_ADP) return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT; return true; @@ -499,7 +497,6 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, struct pps_registers *regs) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); int pps_idx; memset(regs, 0, sizeof(*regs)); @@ -518,7 +515,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */ if (display->platform.geminilake || display->platform.broxton || - INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) + INTEL_PCH_TYPE(display) >= PCH_CNP) regs->pp_div = INVALID_MMIO_REG; else regs->pp_div = PP_DIVISOR(display, pps_idx); @@ -1591,7 +1588,6 @@ static void pps_init_delays(struct intel_dp *intel_dp) static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 pp_on, pp_off, port_sel = 0; int div = DISPLAY_RUNTIME_INFO(display)->rawclk_freq / 1000; struct pps_registers regs; @@ -1638,7 +1634,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd * power sequencer any more. */ if (display->platform.valleyview || display->platform.cherryview) { port_sel = PANEL_PORT_SELECT_VLV(port); - } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { + } else if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) { switch (port) { case PORT_A: port_sel = PANEL_PORT_SELECT_DPA; @@ -1791,9 +1787,7 @@ void intel_pps_unlock_regs_wa(struct intel_display *display) void intel_pps_setup(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - - if (HAS_PCH_SPLIT(i915) || display->platform.geminilake || display->platform.broxton) + if (HAS_PCH_SPLIT(display) || display->platform.geminilake || display->platform.broxton) display->pps.mmio_base = PCH_PPS_BASE; else if (display->platform.valleyview || display->platform.cherryview) display->pps.mmio_base = VLV_PPS_BASE; @@ -1836,7 +1830,6 @@ void intel_pps_connector_debugfs_add(struct intel_connector *connector) void assert_pps_unlocked(struct intel_display *display, enum pipe pipe) { - struct drm_i915_private *dev_priv = to_i915(display->drm); i915_reg_t pp_reg; u32 val; enum pipe panel_pipe = INVALID_PIPE; @@ -1845,7 +1838,7 @@ void assert_pps_unlocked(struct intel_display *display, enum pipe pipe) if (drm_WARN_ON(display->drm, HAS_DDI(display))) return; - if (HAS_PCH_SPLIT(dev_priv)) { + if (HAS_PCH_SPLIT(display)) { u32 port_sel; pp_reg = PP_CONTROL(display, 0); diff --git a/drivers/gpu/drm/i915/display/intel_pps_regs.h b/drivers/gpu/drm/i915/display/intel_pps_regs.h index 8f9dbfab9523..2f014d929d32 100644 --- a/drivers/gpu/drm/i915/display/intel_pps_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pps_regs.h @@ -6,7 +6,6 @@ #ifndef __INTEL_PPS_REGS_H__ #define __INTEL_PPS_REGS_H__ -#include "intel_display_conversion.h" #include "intel_display_reg_defs.h" /* Panel power sequencing */ @@ -14,11 +13,11 @@ #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) #define PCH_PPS_BASE 0xC7200 -#define _MMIO_PPS(dev_priv, pps_idx, reg) \ - _MMIO(__to_intel_display(dev_priv)->pps.mmio_base - PPS_BASE + (reg) + (pps_idx) * 0x100) +#define _MMIO_PPS(display, pps_idx, reg) \ + _MMIO((display)->pps.mmio_base - PPS_BASE + (reg) + (pps_idx) * 0x100) #define _PP_STATUS 0x61200 -#define PP_STATUS(dev_priv, pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_STATUS) +#define PP_STATUS(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_STATUS) #define PP_ON REG_BIT(31) /* * Indicates that all dependencies of the panel are on: @@ -45,7 +44,7 @@ #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf) #define _PP_CONTROL 0x61204 -#define PP_CONTROL(dev_priv, pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_CONTROL) +#define PP_CONTROL(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_CONTROL) #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16) #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd) #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) @@ -55,7 +54,7 @@ #define PANEL_POWER_ON REG_BIT(0) #define _PP_ON_DELAYS 0x61208 -#define PP_ON_DELAYS(dev_priv, pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_ON_DELAYS) +#define PP_ON_DELAYS(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_ON_DELAYS) #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30) #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0) #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1) @@ -66,12 +65,12 @@ #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0) #define _PP_OFF_DELAYS 0x6120C -#define PP_OFF_DELAYS(dev_priv, pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_OFF_DELAYS) +#define PP_OFF_DELAYS(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_OFF_DELAYS) #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16) #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0) #define _PP_DIVISOR 0x61210 -#define PP_DIVISOR(dev_priv, pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_DIVISOR) +#define PP_DIVISOR(display, pps_idx) _MMIO_PPS((display), (pps_idx), _PP_DIVISOR) #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8) #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index eef48c014112..8bee2f592ae7 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -26,6 +26,7 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_damage_helper.h> #include <drm/drm_debugfs.h> +#include <drm/drm_vblank.h> #include "i915_drv.h" #include "i915_reg.h" @@ -36,8 +37,10 @@ #include "intel_ddi.h" #include "intel_de.h" #include "intel_display_irq.h" +#include "intel_display_regs.h" #include "intel_display_rpm.h" #include "intel_display_types.h" +#include "intel_dmc.h" #include "intel_dp.h" #include "intel_dp_aux.h" #include "intel_frontbuffer.h" @@ -46,6 +49,7 @@ #include "intel_psr_regs.h" #include "intel_snps_phy.h" #include "intel_vblank.h" +#include "intel_vrr.h" #include "skl_universal_plane.h" /** @@ -513,7 +517,7 @@ static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp) if (intel_dp->psr.sink_panel_replay_su_support) drm_dp_dpcd_readb(&intel_dp->aux, - DP_PANEL_PANEL_REPLAY_CAPABILITY, + DP_PANEL_REPLAY_CAP_CAPABILITY, &su_capability); else su_capability = intel_dp->psr_dpcd[1]; @@ -525,7 +529,7 @@ static unsigned int intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp) { return intel_dp->psr.sink_panel_replay_su_support ? - DP_PANEL_PANEL_REPLAY_X_GRANULARITY : + DP_PANEL_REPLAY_CAP_X_GRANULARITY : DP_PSR2_SU_X_GRANULARITY; } @@ -533,7 +537,7 @@ static unsigned int intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp) { return intel_dp->psr.sink_panel_replay_su_support ? - DP_PANEL_PANEL_REPLAY_Y_GRANULARITY : + DP_PANEL_REPLAY_CAP_Y_GRANULARITY : DP_PSR2_SU_Y_GRANULARITY; } @@ -605,7 +609,8 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp) return; } - if (!(intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) { + if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & + DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) { drm_dbg_kms(display->drm, "Panel doesn't support early transport, eDP Panel Replay not possible\n"); return; @@ -614,7 +619,8 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp) intel_dp->psr.sink_panel_replay_support = true; - if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT) + if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & + DP_PANEL_REPLAY_SU_SUPPORT) intel_dp->psr.sink_panel_replay_su_support = true; drm_dbg_kms(display->drm, @@ -673,10 +679,12 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) { drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, sizeof(intel_dp->psr_dpcd)); - drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, - &intel_dp->pr_dpcd); - if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SUPPORT) + drm_dp_dpcd_read(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT, + &intel_dp->pr_dpcd, sizeof(intel_dp->pr_dpcd)); + + if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & + DP_PANEL_REPLAY_SUPPORT) _panel_replay_init_dpcd(intel_dp); if (intel_dp->psr_dpcd[0]) @@ -733,7 +741,8 @@ static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay return false; return panel_replay ? - intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT : + intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & + DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT : intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED && psr2_su_region_et_global_enabled(intel_dp); } @@ -794,31 +803,10 @@ static void _psr_enable_sink(struct intel_dp *intel_dp, drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); } -static void intel_psr_enable_sink_alpm(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state) -{ - u8 val; - - /* - * eDP Panel Replay uses always ALPM - * PSR2 uses ALPM but PSR1 doesn't - */ - if (!intel_dp_is_edp(intel_dp) || (!crtc_state->has_panel_replay && - !crtc_state->has_sel_update)) - return; - - val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE; - - if (crtc_state->has_panel_replay) - val |= DP_ALPM_MODE_AUX_LESS; - - drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val); -} - static void intel_psr_enable_sink(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { - intel_psr_enable_sink_alpm(intel_dp, crtc_state); + intel_alpm_enable_sink(intel_dp, crtc_state); crtc_state->has_panel_replay ? _panel_replay_enable_sink(intel_dp, crtc_state) : @@ -905,6 +893,18 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) return idle_frames; } +static bool is_dc5_dc6_blocked(struct intel_dp *intel_dp) +{ + struct intel_display *display = to_intel_display(intel_dp); + u32 current_dc_state = intel_display_power_get_current_dc_state(display); + struct drm_vblank_crtc *vblank = &display->drm->vblank[intel_dp->psr.pipe]; + + return (current_dc_state != DC_STATE_EN_UPTO_DC5 && + current_dc_state != DC_STATE_EN_UPTO_DC6) || + intel_dp->psr.active_non_psr_pipes || + READ_ONCE(vblank->enabled); +} + static void hsw_activate_psr1(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); @@ -933,6 +933,14 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp) intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder), ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val); + + /* Wa_16025596647 */ + if ((DISPLAY_VER(display) == 20 || + IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && + is_dc5_dc6_blocked(intel_dp)) + intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, + intel_dp->psr.pipe, + true); } static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) @@ -1014,8 +1022,16 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) enum transcoder cpu_transcoder = intel_dp->psr.transcoder; u32 val = EDP_PSR2_ENABLE; u32 psr_val = 0; + u8 idle_frames; - val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp)); + /* Wa_16025596647 */ + if ((DISPLAY_VER(display) == 20 || + IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && + is_dc5_dc6_blocked(intel_dp)) + idle_frames = 0; + else + idle_frames = psr_compute_idle_frames(intel_dp); + val |= EDP_PSR2_IDLE_FRAMES(idle_frames); if (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p) val |= EDP_SU_TRACK_ENABLE; @@ -1564,6 +1580,12 @@ static bool _psr_compute_config(struct intel_dp *intel_dp, if (!CAN_PSR(intel_dp)) return false; + /* + * Currently PSR doesn't work reliably with VRR enabled. + */ + if (crtc_state->vrr.enable) + return false; + entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, adjusted_mode); if (entry_setup_frames >= 0) { @@ -1649,6 +1671,9 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, { struct intel_display *display = to_intel_display(intel_dp); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); + struct intel_crtc *crtc; + u8 active_pipes = 0; if (!psr_global_enabled(intel_dp)) { drm_dbg_kms(display->drm, "PSR disabled by flag\n"); @@ -1678,12 +1703,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, return; } - /* - * Currently PSR/PR doesn't work reliably with VRR enabled. - */ - if (crtc_state->vrr.enable) - return; - crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp, crtc_state, conn_state); @@ -1702,6 +1721,24 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, drm_dbg_kms(display->drm, "PSR disabled to workaround PSR FSM hang issue\n"); } + + /* Rest is for Wa_16025596647 */ + if (DISPLAY_VER(display) != 20 && + !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) + return; + + /* Not needed by Panel Replay */ + if (crtc_state->has_panel_replay) + return; + + /* We ignore possible secondary PSR/Panel Replay capable eDP */ + for_each_intel_crtc(display->drm, crtc) + active_pipes |= crtc->active ? BIT(crtc->pipe) : 0; + + active_pipes = intel_calc_active_pipes(state, active_pipes); + + crtc_state->active_non_psr_pipes = active_pipes & + ~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe); } void intel_psr_get_config(struct intel_encoder *encoder, @@ -1893,9 +1930,6 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, intel_dp->psr.psr2_sel_fetch_enabled ? IGNORE_PSR2_HW_TRACKING : 0); - if (intel_dp_is_edp(intel_dp)) - intel_alpm_configure(intel_dp, crtc_state); - /* * Wa_16013835468 * Wa_14015648006 @@ -1930,6 +1964,14 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, intel_de_rmw(display, CLKGATE_DIS_MISC, 0, CLKGATE_DIS_MISC_DMASC_GATING_DIS); } + + /* Wa_16025596647 */ + if ((DISPLAY_VER(display) == 20 || + IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && + !intel_dp->psr.panel_replay_enabled) + intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true); + + intel_alpm_configure(intel_dp, crtc_state); } static bool psr_interrupt_error_check(struct intel_dp *intel_dp) @@ -1985,6 +2027,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, intel_dp->psr.psr2_sel_fetch_cff_enabled = false; intel_dp->psr.req_psr2_sdp_prior_scanline = crtc_state->req_psr2_sdp_prior_scanline; + intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes; if (!psr_interrupt_error_check(intel_dp)) return; @@ -1996,8 +2039,9 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, intel_dp->psr.sel_update_enabled ? "2" : "1"); /* - * Enabling here only for PSR. Panel Replay enable bit is already - * written at this point. See + * Enabling sink PSR/Panel Replay here only for PSR. Panel Replay enable + * bit is already written at this point. Sink ALPM is enabled here for + * PSR and Panel Replay. See * intel_psr_panel_replay_enable_sink. Modifiers/options: * - Selective Update * - Region Early Transport @@ -2060,6 +2104,12 @@ static void intel_psr_exit(struct intel_dp *intel_dp) drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE)); } else { + if (DISPLAY_VER(display) == 20 || + IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) + intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, + intel_dp->psr.pipe, + false); + val = intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder), EDP_PSR_ENABLE, 0); @@ -2133,16 +2183,8 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) if (intel_dp_is_edp(intel_dp)) intel_snps_phy_update_psr_power_state(&dp_to_dig_port(intel_dp)->base, false); - /* Panel Replay on eDP is always using ALPM aux less. */ - if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) { - intel_de_rmw(display, ALPM_CTL(display, cpu_transcoder), - ALPM_CTL_ALPM_ENABLE | - ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0); - - intel_de_rmw(display, - PORT_ALPM_CTL(cpu_transcoder), - PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0); - } + if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) + intel_alpm_disable(intel_dp); /* Disable PSR on Sink */ if (!intel_dp->psr.panel_replay_enabled) { @@ -2153,12 +2195,19 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) DP_RECEIVER_ALPM_CONFIG, 0); } + /* Wa_16025596647 */ + if ((DISPLAY_VER(display) == 20 || + IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && + !intel_dp->psr.panel_replay_enabled) + intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false); + intel_dp->psr.enabled = false; intel_dp->psr.panel_replay_enabled = false; intel_dp->psr.sel_update_enabled = false; intel_dp->psr.psr2_sel_fetch_enabled = false; intel_dp->psr.su_region_et_enabled = false; intel_dp->psr.psr2_sel_fetch_cff_enabled = false; + intel_dp->psr.active_non_psr_pipes = 0; } /** @@ -2254,17 +2303,20 @@ out: } /** - * intel_psr_needs_block_dc_vblank - Check if block dc entry is needed + * intel_psr_needs_vblank_notification - Check if PSR need vblank enable/disable + * notification. * @crtc_state: CRTC status * * We need to block DC6 entry in case of Panel Replay as enabling VBI doesn't * prevent it in case of Panel Replay. Panel Replay switches main link off on * DC entry. This means vblank interrupts are not fired and is a problem if - * user-space is polling for vblank events. + * user-space is polling for vblank events. Also Wa_16025596647 needs + * information when vblank is enabled/disabled. */ -bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state) +bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct intel_display *display = to_intel_display(crtc_state); struct intel_encoder *encoder; for_each_encoder_on_crtc(crtc->base.dev, &crtc->base, encoder) { @@ -2275,8 +2327,15 @@ bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state) intel_dp = enc_to_intel_dp(encoder); - if (intel_dp_is_edp(intel_dp) && - CAN_PANEL_REPLAY(intel_dp)) + if (!intel_dp_is_edp(intel_dp)) + continue; + + if (CAN_PANEL_REPLAY(intel_dp)) + return true; + + if ((DISPLAY_VER(display) == 20 || + IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && + CAN_PSR(intel_dp)) return true; } @@ -2304,6 +2363,53 @@ void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb, CURSURFLIVE(display, crtc->pipe), 0); } +/** + * intel_psr_min_vblank_delay - Minimum vblank delay needed by PSR + * @crtc_state: the crtc state + * + * Return minimum vblank delay needed by PSR. + */ +int intel_psr_min_vblank_delay(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + + if (!crtc_state->has_psr) + return 0; + + /* Wa_14015401596 */ + if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14)) + return 1; + + /* Rest is for SRD_STATUS needed on LunarLake and onwards */ + if (DISPLAY_VER(display) < 20) + return 0; + + /* + * Comment on SRD_STATUS register in Bspec for LunarLake and onwards: + * + * To deterministically capture the transition of the state machine + * going from SRDOFFACK to IDLE, the delayed V. Blank should be at least + * one line after the non-delayed V. Blank. + * + * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0 + * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[ VRR Vmax ] + * - TRANS_VTOTAL[ Vertical Active ]) + * + * SRD_STATUS is used only by PSR1 on PantherLake. + * SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake. + */ + + if (DISPLAY_VER(display) >= 30 && (crtc_state->has_panel_replay || + crtc_state->has_sel_update)) + return 0; + else if (DISPLAY_VER(display) < 30 && (crtc_state->has_sel_update || + intel_crtc_has_type(crtc_state, + INTEL_OUTPUT_EDP))) + return 0; + else + return 1; +} + static u32 man_trk_ctl_enable_bit_get(struct intel_display *display) { return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 0 : @@ -3398,29 +3504,14 @@ static int psr_get_status_and_error_status(struct intel_dp *intel_dp, static void psr_alpm_check(struct intel_dp *intel_dp) { - struct intel_display *display = to_intel_display(intel_dp); - struct drm_dp_aux *aux = &intel_dp->aux; struct intel_psr *psr = &intel_dp->psr; - u8 val; - int r; if (!psr->sel_update_enabled) return; - r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); - if (r != 1) { - drm_err(display->drm, "Error reading ALPM status\n"); - return; - } - - if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { + if (intel_alpm_get_error(intel_dp)) { intel_psr_disable_locked(intel_dp); psr->sink_not_reliable = true; - drm_dbg_kms(display->drm, - "ALPM lock timeout error, disabling PSR\n"); - - /* Clearing error */ - drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); } } @@ -3605,6 +3696,168 @@ void intel_psr_unlock(const struct intel_crtc_state *crtc_state) } } +/* Wa_16025596647 */ +static void intel_psr_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp) +{ + struct intel_display *display = to_intel_display(intel_dp); + bool dc5_dc6_blocked; + + if (!intel_dp->psr.active) + return; + + dc5_dc6_blocked = is_dc5_dc6_blocked(intel_dp); + + if (intel_dp->psr.sel_update_enabled) + psr2_program_idle_frames(intel_dp, dc5_dc6_blocked ? 0 : + psr_compute_idle_frames(intel_dp)); + else + intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, + intel_dp->psr.pipe, + dc5_dc6_blocked); +} + +static void psr_dc5_dc6_wa_work(struct work_struct *work) +{ + struct intel_display *display = container_of(work, typeof(*display), + psr_dc5_dc6_wa_work); + struct intel_encoder *encoder; + + for_each_intel_encoder_with_psr(display->drm, encoder) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + mutex_lock(&intel_dp->psr.lock); + + if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled) + intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); + + mutex_unlock(&intel_dp->psr.lock); + } +} + +/** + * intel_psr_notify_dc5_dc6 - Notify PSR about enable/disable dc5/dc6 + * @display: intel atomic state + * + * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to schedule + * psr_dc5_dc6_wa_work used for applying/removing the workaround. + */ +void intel_psr_notify_dc5_dc6(struct intel_display *display) +{ + if (DISPLAY_VER(display) != 20 && + !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) + return; + + schedule_work(&display->psr_dc5_dc6_wa_work); +} + +/** + * intel_psr_dc5_dc6_wa_init - Init work for underrun on idle PSR HW bug wa + * @display: intel atomic state + * + * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init + * psr_dc5_dc6_wa_work used for applying the workaround. + */ +void intel_psr_dc5_dc6_wa_init(struct intel_display *display) +{ + if (DISPLAY_VER(display) != 20 && + !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) + return; + + INIT_WORK(&display->psr_dc5_dc6_wa_work, psr_dc5_dc6_wa_work); +} + +/** + * intel_psr_notify_pipe_change - Notify PSR about enable/disable of a pipe + * @state: intel atomic state + * @crtc: intel crtc + * @enable: enable/disable + * + * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply + * remove the workaround when pipe is getting enabled/disabled + */ +void intel_psr_notify_pipe_change(struct intel_atomic_state *state, + struct intel_crtc *crtc, bool enable) +{ + struct intel_display *display = to_intel_display(state); + struct intel_encoder *encoder; + + if (DISPLAY_VER(display) != 20 && + !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) + return; + + for_each_intel_encoder_with_psr(display->drm, encoder) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + u8 active_non_psr_pipes; + + mutex_lock(&intel_dp->psr.lock); + + if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled) + goto unlock; + + active_non_psr_pipes = intel_dp->psr.active_non_psr_pipes; + + if (enable) + active_non_psr_pipes |= BIT(crtc->pipe); + else + active_non_psr_pipes &= ~BIT(crtc->pipe); + + if (active_non_psr_pipes == intel_dp->psr.active_non_psr_pipes) + goto unlock; + + if ((enable && intel_dp->psr.active_non_psr_pipes) || + (!enable && !intel_dp->psr.active_non_psr_pipes)) { + intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes; + goto unlock; + } + + intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes; + + intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); +unlock: + mutex_unlock(&intel_dp->psr.lock); + } +} + +/** + * intel_psr_notify_vblank_enable_disable - Notify PSR about enable/disable of vblank + * @display: intel display struct + * @enable: enable/disable + * + * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply + * remove the workaround when vblank is getting enabled/disabled + */ +void intel_psr_notify_vblank_enable_disable(struct intel_display *display, + bool enable) +{ + struct intel_encoder *encoder; + + for_each_intel_encoder_with_psr(display->drm, encoder) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + mutex_lock(&intel_dp->psr.lock); + if (intel_dp->psr.panel_replay_enabled) { + mutex_unlock(&intel_dp->psr.lock); + break; + } + + if (intel_dp->psr.enabled) + intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); + + mutex_unlock(&intel_dp->psr.lock); + return; + } + + /* + * NOTE: intel_display_power_set_target_dc_state is used + * only by PSR * code for DC3CO handling. DC3CO target + * state is currently disabled in * PSR code. If DC3CO + * is taken into use we need take that into account here + * as well. + */ + intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE : + DC_STATE_EN_UPTO_DC6); +} + static void psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) { @@ -3669,7 +3922,8 @@ static void intel_psr_sink_capability(struct intel_dp *intel_dp, seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support)); seq_printf(m, ", Panel Replay Selective Update = %s", str_yes_no(psr->sink_panel_replay_su_support)); - if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT) + if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & + DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT) seq_printf(m, " (Early Transport)"); seq_printf(m, "\n"); } @@ -3774,24 +4028,30 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) int frame; /* - * Reading all 3 registers before hand to minimize crossing a - * frame boundary between register reads + * PSR2_SU_STATUS register has been tied-off since DG2/ADL-P + * (it returns zeros only) and it has been removed on Xe2_LPD. */ - for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) { - val = intel_de_read(display, - PSR2_SU_STATUS(display, cpu_transcoder, frame)); - su_frames_val[frame / 3] = val; - } + if (DISPLAY_VER(display) < 13) { + /* + * Reading all 3 registers before hand to minimize crossing a + * frame boundary between register reads + */ + for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) { + val = intel_de_read(display, + PSR2_SU_STATUS(display, cpu_transcoder, frame)); + su_frames_val[frame / 3] = val; + } - seq_puts(m, "Frame:\tPSR2 SU blocks:\n"); + seq_puts(m, "Frame:\tPSR2 SU blocks:\n"); - for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) { - u32 su_blocks; + for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) { + u32 su_blocks; - su_blocks = su_frames_val[frame / 3] & - PSR2_SU_STATUS_MASK(frame); - su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame); - seq_printf(m, "%d\t%d\n", frame, su_blocks); + su_blocks = su_frames_val[frame / 3] & + PSR2_SU_STATUS_MASK(frame); + su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame); + seq_printf(m, "%d\t%d\n", frame, su_blocks); + } } seq_printf(m, "PSR2 selective fetch: %s\n", @@ -3977,3 +4237,19 @@ void intel_psr_connector_debugfs_add(struct intel_connector *connector) debugfs_create_file("i915_psr_status", 0444, root, connector, &i915_psr_status_fops); } + +bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) +{ + /* + * eDP Panel Replay uses always ALPM + * PSR2 uses ALPM but PSR1 doesn't + */ + return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update || + crtc_state->has_panel_replay); +} + +bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay; +} diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index a43a374cff55..0cf53184f13f 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -59,7 +59,13 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state); void intel_psr_pause(struct intel_dp *intel_dp); void intel_psr_resume(struct intel_dp *intel_dp); -bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state); +bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state); +void intel_psr_notify_pipe_change(struct intel_atomic_state *state, + struct intel_crtc *crtc, bool enable); +void intel_psr_notify_dc5_dc6(struct intel_display *display); +void intel_psr_dc5_dc6_wa_init(struct intel_display *display); +void intel_psr_notify_vblank_enable_disable(struct intel_display *display, + bool enable); bool intel_psr_link_ok(struct intel_dp *intel_dp); void intel_psr_lock(const struct intel_crtc_state *crtc_state); @@ -67,7 +73,11 @@ void intel_psr_unlock(const struct intel_crtc_state *crtc_state); void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb, struct intel_atomic_state *state, struct intel_crtc *crtc); +int intel_psr_min_vblank_delay(const struct intel_crtc_state *crtc_state); void intel_psr_connector_debugfs_add(struct intel_connector *connector); void intel_psr_debugfs_register(struct intel_display *display); +bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); +bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state); #endif /* __INTEL_PSR_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 795e6b9cc575..8afbf5a38335 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -266,6 +266,16 @@ #define _PIPE_SRCSZ_ERLY_TPT_B 0x71074 #define PIPE_SRCSZ_ERLY_TPT(pipe) _MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B) +#define _PR_ALPM_CTL_A 0x60948 +#define PR_ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PR_ALPM_CTL_A) +#define PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU BIT(6) +#define PR_ALPM_CTL_RFB_UPDATE_CONTROL BIT(5) +#define PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE BIT(4) +#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK REG_GENMASK(1, 0) +#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 0) +#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 1) +#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 2) + #define _ALPM_CTL_A 0x60950 #define ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A) #define ALPM_CTL_ALPM_ENABLE REG_BIT(31) @@ -325,8 +335,8 @@ #define PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK REG_GENMASK(20, 16) #define PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val) #define PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK REG_GENMASK(12, 8) -#define PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val) +#define PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK, val) #define PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK REG_GENMASK(4, 0) -#define PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val) +#define PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK, val) #endif /* __INTEL_PSR_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_sbi.c b/drivers/gpu/drm/i915/display/intel_sbi.c new file mode 100644 index 000000000000..dfcff924f0ed --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_sbi.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2013-2021 Intel Corporation + * + * LPT/WPT IOSF sideband. + */ + +#include <drm/drm_print.h> + +#include "intel_de.h" +#include "intel_display_core.h" +#include "intel_sbi.h" +#include "intel_sbi_regs.h" + +/* SBI access */ +static int intel_sbi_rw(struct intel_display *display, u16 reg, + enum intel_sbi_destination destination, + u32 *val, bool is_read) +{ + u32 cmd; + + lockdep_assert_held(&display->sbi.lock); + + if (intel_de_wait_fw(display, SBI_CTL_STAT, SBI_STATUS_MASK, SBI_STATUS_READY, 100, NULL)) { + drm_err(display->drm, "timeout waiting for SBI to become ready\n"); + return -EBUSY; + } + + intel_de_write_fw(display, SBI_ADDR, SBI_ADDR_VALUE(reg)); + intel_de_write_fw(display, SBI_DATA, is_read ? 0 : *val); + + if (destination == SBI_ICLK) + cmd = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD; + else + cmd = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD; + if (!is_read) + cmd |= SBI_CTL_OP_WR; + intel_de_write_fw(display, SBI_CTL_STAT, cmd | SBI_STATUS_BUSY); + + if (intel_de_wait_fw(display, SBI_CTL_STAT, SBI_STATUS_MASK, SBI_STATUS_READY, 100, &cmd)) { + drm_err(display->drm, "timeout waiting for SBI to complete read\n"); + return -ETIMEDOUT; + } + + if (cmd & SBI_RESPONSE_FAIL) { + drm_err(display->drm, "error during SBI read of reg %x\n", reg); + return -ENXIO; + } + + if (is_read) + *val = intel_de_read_fw(display, SBI_DATA); + + return 0; +} + +void intel_sbi_lock(struct intel_display *display) +{ + mutex_lock(&display->sbi.lock); +} + +void intel_sbi_unlock(struct intel_display *display) +{ + mutex_unlock(&display->sbi.lock); +} + +u32 intel_sbi_read(struct intel_display *display, u16 reg, + enum intel_sbi_destination destination) +{ + u32 result = 0; + + intel_sbi_rw(display, reg, destination, &result, true); + + return result; +} + +void intel_sbi_write(struct intel_display *display, u16 reg, u32 value, + enum intel_sbi_destination destination) +{ + intel_sbi_rw(display, reg, destination, &value, false); +} + +void intel_sbi_init(struct intel_display *display) +{ + mutex_init(&display->sbi.lock); +} + +void intel_sbi_fini(struct intel_display *display) +{ + mutex_destroy(&display->sbi.lock); +} diff --git a/drivers/gpu/drm/i915/display/intel_sbi.h b/drivers/gpu/drm/i915/display/intel_sbi.h new file mode 100644 index 000000000000..841f77a142a1 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_sbi.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2013-2021 Intel Corporation + */ + +#ifndef _INTEL_SBI_H_ +#define _INTEL_SBI_H_ + +#include <linux/types.h> + +struct intel_display; + +enum intel_sbi_destination { + SBI_ICLK, + SBI_MPHY, +}; + +void intel_sbi_init(struct intel_display *display); +void intel_sbi_fini(struct intel_display *display); +void intel_sbi_lock(struct intel_display *display); +void intel_sbi_unlock(struct intel_display *display); +u32 intel_sbi_read(struct intel_display *display, u16 reg, + enum intel_sbi_destination destination); +void intel_sbi_write(struct intel_display *display, u16 reg, u32 value, + enum intel_sbi_destination destination); + +#endif /* _INTEL_SBI_H_ */ diff --git a/drivers/gpu/drm/i915/display/intel_sbi_regs.h b/drivers/gpu/drm/i915/display/intel_sbi_regs.h new file mode 100644 index 000000000000..ec76652de02d --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_sbi_regs.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright © 2025 Intel Corporation */ + +#ifndef __INTEL_SBI_REGS_H__ +#define __INTEL_SBI_REGS_H__ + +#include "intel_display_reg_defs.h" + +/* + * Sideband Interface (SBI) is programmed indirectly, via SBI_ADDR, which + * contains the register offset; and SBI_DATA, which contains the payload. + */ +#define SBI_ADDR _MMIO(0xC6000) +#define SBI_ADDR_MASK REG_GENMASK(31, 16) +#define SBI_ADDR_VALUE(addr) REG_FIELD_PREP(SBI_ADDR_MASK, (addr)) + +#define SBI_DATA _MMIO(0xC6004) + +#define SBI_CTL_STAT _MMIO(0xC6008) +#define SBI_CTL_DEST_MASK REG_GENMASK(16, 16) +#define SBI_CTL_DEST_ICLK REG_FIELD_PREP(SBI_CTL_DEST_MASK, 0) +#define SBI_CTL_DEST_MPHY REG_FIELD_PREP(SBI_CTL_DEST_MASK, 1) +#define SBI_CTL_OP_MASK REG_GENMASK(15, 8) +#define SBI_CTL_OP_IORD REG_FIELD_PREP(SBI_CTL_OP_MASK, 2) +#define SBI_CTL_OP_IOWR REG_FIELD_PREP(SBI_CTL_OP_MASK, 3) +#define SBI_CTL_OP_CRRD REG_FIELD_PREP(SBI_CTL_OP_MASK, 6) +#define SBI_CTL_OP_CRWR REG_FIELD_PREP(SBI_CTL_OP_MASK, 7) +#define SBI_CTL_OP_WR REG_BIT(8) +#define SBI_RESPONSE_MASK REG_GENMASK(2, 1) +#define SBI_RESPONSE_FAIL REG_FIELD_PREP(SBI_RESPONSE_MASK, 1) +#define SBI_RESPONSE_SUCCESS REG_FIELD_PREP(SBI_RESPONSE_MASK, 0) +#define SBI_STATUS_MASK REG_GENMASK(0, 0) +#define SBI_STATUS_BUSY REG_FIELD_PREP(SBI_STATUS_MASK, 1) +#define SBI_STATUS_READY REG_FIELD_PREP(SBI_STATUS_MASK, 0) + +/* SBI offsets */ +#define SBI_SSCDIVINTPHASE 0x0200 + +#define SBI_SSCDIVINTPHASE6 0x0600 +#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 +#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) +#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) +#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 +#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) +#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) +#define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) +#define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) + +#define SBI_SSCDITHPHASE 0x0204 +#define SBI_SSCCTL 0x020c +#define SBI_SSCCTL6 0x060C +#define SBI_SSCCTL_PATHALT (1 << 3) +#define SBI_SSCCTL_DISABLE (1 << 0) + +#define SBI_SSCAUXDIV6 0x0610 +#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 +#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) +#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) + +#define SBI_DBUFF0 0x2a00 + +#define SBI_GEN0 0x1f00 +#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) + +#endif /* __INTEL_SBI_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c index 757b9ce7e3b1..87aff2754f69 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.c +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c @@ -36,16 +36,16 @@ #include <drm/drm_crtc.h> #include <drm/drm_edid.h> #include <drm/drm_eld.h> +#include <drm/drm_print.h> #include <drm/drm_probe_helper.h> -#include "i915_drv.h" -#include "i915_reg.h" #include "intel_atomic.h" #include "intel_audio.h" #include "intel_connector.h" #include "intel_crtc.h" #include "intel_de.h" #include "intel_display_driver.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_fdi.h" #include "intel_fifo_underrun.h" @@ -214,18 +214,17 @@ intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) { struct intel_display *display = to_intel_display(&intel_sdvo->base); - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 bval = val, cval = val; int i; - if (HAS_PCH_SPLIT(dev_priv)) { + if (HAS_PCH_SPLIT(display)) { intel_de_write(display, intel_sdvo->sdvo_reg, val); intel_de_posting_read(display, intel_sdvo->sdvo_reg); /* * HW workaround, need to write this twice for issue * that may result in first write getting masked. */ - if (HAS_PCH_IBX(dev_priv)) { + if (HAS_PCH_IBX(display)) { intel_de_write(display, intel_sdvo->sdvo_reg, val); intel_de_posting_read(display, intel_sdvo->sdvo_reg); } @@ -1360,14 +1359,13 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder, struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_sdvo *intel_sdvo = to_sdvo(encoder); struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(conn_state->connector); struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; struct drm_display_mode *mode = &pipe_config->hw.mode; - if (HAS_PCH_SPLIT(i915)) { + if (HAS_PCH_SPLIT(display)) { pipe_config->has_pch_encoder = true; if (!intel_fdi_compute_pipe_bpp(pipe_config)) return -EINVAL; @@ -1527,7 +1525,6 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(intel_encoder); - struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; const struct intel_sdvo_connector_state *sdvo_state = @@ -1634,7 +1631,7 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state, sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; } - if (HAS_PCH_CPT(dev_priv)) + if (HAS_PCH_CPT(display)) sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); else sdvox |= SDVO_PIPE_SEL(crtc->pipe); @@ -1670,13 +1667,12 @@ static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) bool intel_sdvo_port_enabled(struct intel_display *display, i915_reg_t sdvo_reg, enum pipe *pipe) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 val; val = intel_de_read(display, sdvo_reg); /* asserts want to know the pipe even if the port is disabled */ - if (HAS_PCH_CPT(dev_priv)) + if (HAS_PCH_CPT(display)) *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT; else if (display->platform.cherryview) *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV; @@ -1841,7 +1837,6 @@ static void intel_disable_sdvo(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_sdvo *intel_sdvo = to_sdvo(encoder); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); u32 temp; @@ -1861,7 +1856,7 @@ static void intel_disable_sdvo(struct intel_atomic_state *state, * to transcoder A after disabling it to allow the * matching DP port to be enabled on transcoder A. */ - if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { + if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B) { /* * We get CPU/PCH FIFO underruns on the other pipe when * doing the workaround. Sweep them under the rug. @@ -3367,9 +3362,7 @@ intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc, static bool is_sdvo_port_valid(struct intel_display *display, enum port port) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - - if (HAS_PCH_SPLIT(dev_priv)) + if (HAS_PCH_SPLIT(display)) return port == PORT_B; else return port == PORT_B || port == PORT_C; @@ -3384,7 +3377,6 @@ static bool assert_sdvo_port_valid(struct intel_display *display, enum port port bool intel_sdvo_init(struct intel_display *display, i915_reg_t sdvo_reg, enum port port) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_encoder *intel_encoder; struct intel_sdvo *intel_sdvo; int i; @@ -3427,7 +3419,7 @@ bool intel_sdvo_init(struct intel_display *display, } intel_encoder->compute_config = intel_sdvo_compute_config; - if (HAS_PCH_SPLIT(dev_priv)) { + if (HAS_PCH_SPLIT(display)) { intel_encoder->disable = pch_disable_sdvo; intel_encoder->post_disable = pch_post_disable_sdvo; } else { diff --git a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c index c6321dafef4f..74bb3bedf30f 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c +++ b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c @@ -41,12 +41,12 @@ static s64 interp(s64 x, s64 x1, s64 x2, s64 y1, s64 y2) { s64 dydx; - dydx = DIV_ROUND_UP_ULL((y2 - y1) * 100000, (x2 - x1)); + dydx = DIV64_U64_ROUND_UP((y2 - y1) * 100000, (x2 - x1)); - return (y1 + DIV_ROUND_UP_ULL(dydx * (x - x1), 100000)); + return (y1 + DIV64_U64_ROUND_UP(dydx * (x - x1), 100000)); } -static void get_ana_cp_int_prop(u32 vco_clk, +static void get_ana_cp_int_prop(u64 vco_clk, u32 refclk_postscalar, int mpll_ana_v2i, int c, int a, @@ -115,16 +115,16 @@ static void get_ana_cp_int_prop(u32 vco_clk, CURVE0_MULTIPLIER)); scaled_interpolated_sqrt = - int_sqrt(DIV_ROUND_UP_ULL(interpolated_product, vco_div_refclk_float) * + int_sqrt(DIV64_U64_ROUND_UP(interpolated_product, vco_div_refclk_float) * DIV_ROUND_DOWN_ULL(1000000000000ULL, 55)); /* Scale vco_div_refclk for ana_cp_int */ scaled_vco_div_refclk2 = DIV_ROUND_UP_ULL(vco_div_refclk_float, 1000000); - adjusted_vco_clk2 = 1460281 * DIV_ROUND_UP_ULL(scaled_interpolated_sqrt * + adjusted_vco_clk2 = 1460281 * DIV64_U64_ROUND_UP(scaled_interpolated_sqrt * scaled_vco_div_refclk2, curve_1_interpolated); - *ana_cp_prop = DIV_ROUND_UP_ULL(adjusted_vco_clk2, curve_2_scaled2); + *ana_cp_prop = DIV64_U64_ROUND_UP(adjusted_vco_clk2, curve_2_scaled2); *ana_cp_prop = max(1, min(*ana_cp_prop, 127)); } @@ -165,10 +165,10 @@ static void compute_hdmi_tmds_pll(u64 pixel_clock, u32 refclk, /* Select appropriate v2i point */ if (datarate <= INTEL_SNPS_PHY_HDMI_9999MHZ) { mpll_ana_v2i = 2; - tx_clk_div = ilog2(DIV_ROUND_DOWN_ULL(INTEL_SNPS_PHY_HDMI_9999MHZ, datarate)); + tx_clk_div = ilog2(div64_u64(INTEL_SNPS_PHY_HDMI_9999MHZ, datarate)); } else { mpll_ana_v2i = 3; - tx_clk_div = ilog2(DIV_ROUND_DOWN_ULL(INTEL_SNPS_PHY_HDMI_16GHZ, datarate)); + tx_clk_div = ilog2(div64_u64(INTEL_SNPS_PHY_HDMI_16GHZ, datarate)); } vco_clk = (datarate << tx_clk_div) >> 1; diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c index 2b53ac9f4935..b2dd69a11124 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c @@ -7,11 +7,11 @@ #include <drm/drm_print.h> -#include "i915_reg.h" #include "i915_utils.h" #include "intel_ddi.h" #include "intel_ddi_buf_trans.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_snps_hdmi_pll.h" #include "intel_snps_phy.h" diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 1ad6c8a94b3d..fd92e6b89b43 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -36,9 +36,10 @@ #include <drm/drm_blend.h> #include <drm/drm_color_mgmt.h> #include <drm/drm_fourcc.h> +#include <drm/drm_print.h> #include <drm/drm_rect.h> -#include "i915_drv.h" +#include "i915_utils.h" #include "i9xx_plane.h" #include "intel_atomic_plane.h" #include "intel_de.h" diff --git a/drivers/gpu/drm/i915/display/intel_sprite_uapi.c b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c index 1d0b84b464c1..4981cc34da05 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite_uapi.c +++ b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c @@ -3,21 +3,21 @@ * Copyright © 2023 Intel Corporation */ -#include "i915_drv.h" #include "intel_crtc.h" +#include "intel_display_core.h" #include "intel_display_types.h" #include "intel_sprite_uapi.h" -static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv) +static bool has_dst_key_in_primary_plane(struct intel_display *display) { - return DISPLAY_VER(dev_priv) >= 9; + return DISPLAY_VER(display) >= 9; } static void intel_plane_set_ckey(struct intel_plane_state *plane_state, const struct drm_intel_sprite_colorkey *set) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); struct drm_intel_sprite_colorkey *key = &plane_state->ckey; *key = *set; @@ -34,7 +34,7 @@ static void intel_plane_set_ckey(struct intel_plane_state *plane_state, * On SKL+ we want dst key enabled on * the primary and not on the sprite. */ - if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_PRIMARY && + if (DISPLAY_VER(display) >= 9 && plane->id != PLANE_PRIMARY && set->flags & I915_SET_COLORKEY_DESTINATION) key->flags = 0; } @@ -43,7 +43,6 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) { struct intel_display *display = to_intel_display(dev); - struct drm_i915_private *dev_priv = to_i915(dev); struct drm_intel_sprite_colorkey *set = data; struct drm_plane *plane; struct drm_plane_state *plane_state; @@ -61,7 +60,7 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) return -EINVAL; - if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && + if ((display->platform.valleyview || display->platform.cherryview) && set->flags & I915_SET_COLORKEY_DESTINATION) return -EINVAL; @@ -74,7 +73,7 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, * Also multiple planes can't do destination keying on the same * pipe simultaneously. */ - if (DISPLAY_VER(dev_priv) >= 9 && + if (DISPLAY_VER(display) >= 9 && to_intel_plane(plane)->id >= PLANE_3 && set->flags & I915_SET_COLORKEY_DESTINATION) return -EINVAL; @@ -99,7 +98,7 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, * On some platforms we have to configure * the dst colorkey on the primary plane. */ - if (!ret && has_dst_key_in_primary_plane(dev_priv)) { + if (!ret && has_dst_key_in_primary_plane(display)) { struct intel_crtc *crtc = intel_crtc_for_pipe(display, to_intel_plane(plane)->pipe); diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index c1014e74791f..3bc57579fe53 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -14,6 +14,7 @@ #include "intel_display.h" #include "intel_display_driver.h" #include "intel_display_power_map.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dkl_phy_regs.h" #include "intel_dp.h" diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c index 2e3f3f0207e8..e3ab49815a3c 100644 --- a/drivers/gpu/drm/i915/display/intel_tv.c +++ b/drivers/gpu/drm/i915/display/intel_tv.c @@ -33,15 +33,15 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> #include <drm/drm_edid.h> +#include <drm/drm_print.h> #include <drm/drm_probe_helper.h> -#include "i915_drv.h" -#include "i915_reg.h" #include "intel_connector.h" #include "intel_crtc.h" #include "intel_de.h" -#include "intel_display_irq.h" #include "intel_display_driver.h" +#include "intel_display_irq.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dpll.h" #include "intel_hotplug.h" @@ -1585,19 +1585,17 @@ intel_tv_detect_type(struct intel_tv *intel_tv, { struct intel_display *display = to_intel_display(connector->dev); struct intel_crtc *crtc = to_intel_crtc(connector->state->crtc); - struct drm_device *dev = connector->dev; - struct drm_i915_private *dev_priv = to_i915(dev); u32 tv_ctl, save_tv_ctl; u32 tv_dac, save_tv_dac; int type; /* Disable TV interrupts around load detect or we'll recurse */ if (connector->polled & DRM_CONNECTOR_POLL_HPD) { - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); i915_disable_pipestat(display, 0, PIPE_HOTPLUG_INTERRUPT_STATUS | PIPE_HOTPLUG_TV_INTERRUPT_STATUS); - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); } save_tv_dac = tv_dac = intel_de_read(display, TV_DAC); @@ -1668,11 +1666,11 @@ intel_tv_detect_type(struct intel_tv *intel_tv, /* Restore interrupt config */ if (connector->polled & DRM_CONNECTOR_POLL_HPD) { - spin_lock_irq(&dev_priv->irq_lock); + spin_lock_irq(&display->irq.lock); i915_enable_pipestat(display, 0, PIPE_HOTPLUG_INTERRUPT_STATUS | PIPE_HOTPLUG_TV_INTERRUPT_STATUS); - spin_unlock_irq(&dev_priv->irq_lock); + spin_unlock_irq(&display->irq.lock); } return type; diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index 139fa5deba80..70ba7aa26bf4 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -6,10 +6,10 @@ #include <drm/drm_vblank.h> #include "i915_drv.h" -#include "i915_reg.h" #include "intel_color.h" #include "intel_crtc.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_vblank.h" #include "intel_vrr.h" diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index e9b809568cd4..92c04811aa28 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -446,7 +446,7 @@ enum vbt_gmbus_ddi { * basically any of the fields to ensure the correct interpretation for the BDB * version in question. * - * When we copy the child device configs to dev_priv->display.vbt.child_dev, we + * When we copy the child device configs to display->vbt.child_dev, we * reserve space for the full structure below, and initialize the tail not * actually present in VBT to zeros. Accessing those fields is fine, as long as * the default zero is taken into account, again according to the BDB version. diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c index 684b5d1bc87c..6e125564db34 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.c +++ b/drivers/gpu/drm/i915/display/intel_vga.c @@ -4,15 +4,19 @@ */ #include <linux/delay.h> +#include <linux/pci.h> #include <linux/vgaarb.h> +#include <drm/drm_device.h> +#include <drm/drm_print.h> #include <video/vga.h> + #include "soc/intel_gmch.h" -#include "i915_drv.h" -#include "i915_reg.h" #include "intel_de.h" +#include "intel_display.h" #include "intel_vga.h" +#include "intel_vga_regs.h" static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display) { @@ -24,16 +28,42 @@ static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display) return VGACNTRL; } +static bool has_vga_pipe_sel(struct intel_display *display) +{ + if (display->platform.i845g || + display->platform.i865g) + return false; + + if (display->platform.valleyview || + display->platform.cherryview) + return true; + + return DISPLAY_VER(display) < 7; +} + /* Disable the VGA plane that we never use */ void intel_vga_disable(struct intel_display *display) { struct pci_dev *pdev = to_pci_dev(display->drm->dev); i915_reg_t vga_reg = intel_vga_cntrl_reg(display); + enum pipe pipe; + u32 tmp; u8 sr1; - if (intel_de_read(display, vga_reg) & VGA_DISP_DISABLE) + tmp = intel_de_read(display, vga_reg); + if (tmp & VGA_DISP_DISABLE) return; + if (display->platform.cherryview) + pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK_CHV, tmp); + else if (has_vga_pipe_sel(display)) + pipe = REG_FIELD_GET(VGA_PIPE_SEL_MASK, tmp); + else + pipe = PIPE_A; + + drm_dbg_kms(display->drm, "Disabling VGA plane on pipe %c\n", + pipe_name(pipe)); + /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); outb(0x01, VGA_SEQ_I); @@ -46,39 +76,6 @@ void intel_vga_disable(struct intel_display *display) intel_de_posting_read(display, vga_reg); } -void intel_vga_redisable_power_on(struct intel_display *display) -{ - i915_reg_t vga_reg = intel_vga_cntrl_reg(display); - - if (!(intel_de_read(display, vga_reg) & VGA_DISP_DISABLE)) { - drm_dbg_kms(display->drm, - "Something enabled VGA plane, disabling it\n"); - intel_vga_disable(display); - } -} - -void intel_vga_redisable(struct intel_display *display) -{ - intel_wakeref_t wakeref; - - /* - * This function can be called both from intel_modeset_setup_hw_state or - * at a very early point in our resume sequence, where the power well - * structures are not yet restored. Since this function is at a very - * paranoid "someone might have enabled VGA while we were not looking" - * level, just check if the power well is enabled instead of trying to - * follow the "don't touch the power well if we don't need it" policy - * the rest of the driver uses. - */ - wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_VGA); - if (!wakeref) - return; - - intel_vga_redisable_power_on(display); - - intel_display_power_put(display, POWER_DOMAIN_VGA, wakeref); -} - void intel_vga_reset_io_mem(struct intel_display *display) { struct pci_dev *pdev = to_pci_dev(display->drm->dev); diff --git a/drivers/gpu/drm/i915/display/intel_vga.h b/drivers/gpu/drm/i915/display/intel_vga.h index 824dfc32a199..16d699f3b641 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.h +++ b/drivers/gpu/drm/i915/display/intel_vga.h @@ -10,8 +10,6 @@ struct intel_display; void intel_vga_reset_io_mem(struct intel_display *display); void intel_vga_disable(struct intel_display *display); -void intel_vga_redisable(struct intel_display *display); -void intel_vga_redisable_power_on(struct intel_display *display); int intel_vga_register(struct intel_display *display); void intel_vga_unregister(struct intel_display *display); diff --git a/drivers/gpu/drm/i915/display/intel_vga_regs.h b/drivers/gpu/drm/i915/display/intel_vga_regs.h new file mode 100644 index 000000000000..cbacced1a69f --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_vga_regs.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2025 Intel Corporation + */ + +#ifndef __INTEL_VGA_REGS_H__ +#define __INTEL_VGA_REGS_H__ + +#include "intel_display_reg_defs.h" + +#define VGACNTRL _MMIO(0x71400) +#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) +#define CPU_VGACNTRL _MMIO(0x41000) +#define VGA_DISP_DISABLE REG_BIT(31) +#define VGA_2X_MODE REG_BIT(30) /* pre-ilk */ +#define VGA_PIPE_SEL_MASK REG_BIT(29) /* pre-ivb */ +#define VGA_PIPE_SEL(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK, (pipe)) +#define VGA_PIPE_SEL_MASK_CHV REG_GENMASK(29, 28) /* chv */ +#define VGA_PIPE_SEL_CHV(pipe) REG_FIELD_PREP(VGA_PIPE_SEL_MASK_CHV, (pipe)) +#define VGA_BORDER_ENABLE REG_BIT(26) +#define VGA_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ +#define VGA_CENTERING_ENABLE_MASK REG_GENMASK(25, 24) /* pre-ilk */ +#define VGA_PALETTE_READ_SEL REG_BIT(23) /* pre-ivb */ +#define VGA_PALETTE_A_WRITE_DISABLE REG_BIT(22) /* pre-ivb */ +#define VGA_PALETTE_B_WRITE_DISABLE REG_BIT(21) /* pre-ivb */ +#define VGA_LEGACY_8BIT_PALETTE_ENABLE REG_BIT(20) +#define VGA_PALETTE_BYPASS REG_BIT(19) +#define VGA_NINE_DOT_DISABLE REG_BIT(18) +#define VGA_PALETTE_READ_SEL_HI_CHV REG_BIT(15) /* chv */ +#define VGA_PALETTE_C_WRITE_DISABLE_CHV REG_BIT(14) /* chv */ +#define VGA_ACTIVE_THROTTLING_MASK REG_GENMASK(15, 12) /* ilk+ */ +#define VGA_BLANK_THROTTLING_MASK REG_GENMASK(11, 8) /* ilk+ */ +#define VGA_BLINK_DUTY_CYCLE_MASK REG_GENMASK(7, 6) +#define VGA_VSYNC_BLINK_RATE_MASK REG_GENMASK(5, 0) + +#endif /* __INTEL_VGA_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 633a66f6b73b..3eed37f271b0 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -6,8 +6,8 @@ #include <drm/drm_print.h> -#include "i915_reg.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_vrr.h" @@ -444,7 +444,10 @@ static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); - if (DISPLAY_VER(display) >= 13) + if (DISPLAY_VER(display) >= 14) + return VRR_CTL_FLIP_LINE_EN | + XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband); + else if (DISPLAY_VER(display) >= 13) return VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN | XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband); else @@ -573,6 +576,25 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display) return false; } +static +void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + /* + * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming + * double buffering point and transmission line for VRR packets for + * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON. + * Since currently we support VRR only for DP/eDP, so this is programmed + * to for Adaptive Sync SDP to Vsync start. + */ + if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20) + intel_de_write(display, + EMP_AS_SDP_TL(display, cpu_transcoder), + EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start)); +} + void intel_vrr_enable(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); @@ -592,6 +614,8 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) TRANS_PUSH_EN); if (!intel_vrr_always_use_vrr_tg(display)) { + intel_vrr_set_db_point_and_transmission_line(crtc_state); + if (crtc_state->cmrr.enable) { intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | @@ -643,6 +667,8 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state) intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN); + intel_vrr_set_db_point_and_transmission_line(crtc_state); + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); } diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h index 6ed0e0dc97e7..09cdd50d6187 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h @@ -108,6 +108,12 @@ #define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) #define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start)) +/* Common register for HDMI EMP and DP AS SDP */ +#define _EMP_AS_SDP_TL_A 0x60204 +#define EMP_AS_SDP_DB_TL_MASK REG_GENMASK(12, 0) +#define EMP_AS_SDP_TL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _EMP_AS_SDP_TL_A) +#define EMP_AS_SDP_DB_TL(db_transmit_line) REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, (db_transmit_line)) + /*CMRR Registers*/ #define _TRANS_CMRR_M_LO_A 0x604F0 diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index ee81220a7c88..d77798499c57 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -3,9 +3,11 @@ * Copyright © 2020 Intel Corporation */ -#include "i915_drv.h" -#include "i915_reg.h" +#include <drm/drm_print.h> + +#include "i915_utils.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_trace.h" #include "intel_display_types.h" #include "intel_fb.h" @@ -693,15 +695,14 @@ static void glk_program_nearest_filter_coefs(struct intel_display *display, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0); } -static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set) +static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter) { - if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) { + if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) return (PS_FILTER_PROGRAMMED | - PS_Y_VERT_FILTER_SELECT(set) | - PS_Y_HORZ_FILTER_SELECT(set) | - PS_UV_VERT_FILTER_SELECT(set) | - PS_UV_HORZ_FILTER_SELECT(set)); - } + PS_Y_VERT_FILTER_SELECT(0) | + PS_Y_HORZ_FILTER_SELECT(0) | + PS_UV_VERT_FILTER_SELECT(0) | + PS_UV_HORZ_FILTER_SELECT(0)); return PS_FILTER_MEDIUM; } @@ -759,7 +760,7 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state) id = scaler_state->scaler_id; ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode | - skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0); + skl_scaler_get_filter_select(crtc_state->hw.scaling_filter); trace_intel_pipe_scaler_update_arm(crtc, id, x, y, width, height); @@ -825,7 +826,7 @@ skl_program_plane_scaler(struct intel_dsb *dsb, } ps_ctrl = PS_SCALER_EN | PS_BINDING_PLANE(plane->id) | scaler->mode | - skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0); + skl_scaler_get_filter_select(plane_state->hw.scaling_filter); trace_intel_plane_scaler_update_arm(plane, scaler_id, crtc_x, crtc_y, crtc_w, crtc_h); diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 8739195aba69..2aa64482d44b 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -8,12 +8,14 @@ #include <drm/drm_damage_helper.h> #include <drm/drm_fourcc.h> +#include "pxp/intel_pxp.h" + #include "i915_drv.h" -#include "i915_reg.h" #include "intel_atomic_plane.h" #include "intel_bo.h" #include "intel_de.h" #include "intel_display_irq.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dpt.h" #include "intel_fb.h" @@ -25,7 +27,6 @@ #include "skl_universal_plane.h" #include "skl_universal_plane_regs.h" #include "skl_watermark.h" -#include "pxp/intel_pxp.h" static const u32 skl_plane_formats[] = { DRM_FORMAT_C8, @@ -601,7 +602,7 @@ static u32 tgl_plane_min_alignment(struct intel_plane *plane, * Figure out what's going on here... */ if (display->platform.alderlake_p && - intel_plane_can_async_flip(plane, fb->modifier)) + intel_plane_can_async_flip(plane, fb->format->format, fb->modifier)) return mult * 16 * 1024; switch (fb->modifier) { @@ -2666,6 +2667,7 @@ static const struct drm_plane_funcs skl_plane_funcs = { .atomic_duplicate_state = intel_plane_duplicate_state, .atomic_destroy_state = intel_plane_destroy_state, .format_mod_supported = skl_plane_format_mod_supported, + .format_mod_supported_async = intel_plane_format_mod_supported_async, }; static const struct drm_plane_funcs icl_plane_funcs = { @@ -2675,6 +2677,7 @@ static const struct drm_plane_funcs icl_plane_funcs = { .atomic_duplicate_state = intel_plane_duplicate_state, .atomic_destroy_state = intel_plane_destroy_state, .format_mod_supported = icl_plane_format_mod_supported, + .format_mod_supported_async = intel_plane_format_mod_supported_async, }; static const struct drm_plane_funcs tgl_plane_funcs = { @@ -2684,30 +2687,29 @@ static const struct drm_plane_funcs tgl_plane_funcs = { .atomic_duplicate_state = intel_plane_duplicate_state, .atomic_destroy_state = intel_plane_destroy_state, .format_mod_supported = tgl_plane_format_mod_supported, + .format_mod_supported_async = intel_plane_format_mod_supported_async, }; static void skl_plane_enable_flip_done(struct intel_plane *plane) { struct intel_display *display = to_intel_display(plane); - struct drm_i915_private *i915 = to_i915(plane->base.dev); enum pipe pipe = plane->pipe; - spin_lock_irq(&i915->irq_lock); + spin_lock_irq(&display->irq.lock); bdw_enable_pipe_irq(display, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id)); - spin_unlock_irq(&i915->irq_lock); + spin_unlock_irq(&display->irq.lock); } static void skl_plane_disable_flip_done(struct intel_plane *plane) { struct intel_display *display = to_intel_display(plane); - struct drm_i915_private *i915 = to_i915(plane->base.dev); enum pipe pipe = plane->pipe; - spin_lock_irq(&i915->irq_lock); + spin_lock_irq(&display->irq.lock); bdw_disable_pipe_irq(display, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id)); - spin_unlock_irq(&i915->irq_lock); + spin_unlock_irq(&display->irq.lock); } static bool skl_plane_has_rc_ccs(struct intel_display *display, diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 8080f777910a..2c2371574d6f 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -7,6 +7,8 @@ #include <drm/drm_blend.h> +#include "soc/intel_dram.h" + #include "i915_drv.h" #include "i915_reg.h" #include "i9xx_wm.h" @@ -19,6 +21,7 @@ #include "intel_de.h" #include "intel_display.h" #include "intel_display_power.h" +#include "intel_display_regs.h" #include "intel_display_rpm.h" #include "intel_display_types.h" #include "intel_fb.h" @@ -3184,8 +3187,6 @@ void skl_watermark_ipc_update(struct intel_display *display) static bool skl_watermark_ipc_can_enable(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - /* Display WA #0477 WaDisableIPC: skl */ if (display->platform.skylake) return false; @@ -3193,8 +3194,11 @@ static bool skl_watermark_ipc_can_enable(struct intel_display *display) /* Display WA #1141: SKL:all KBL:all CFL */ if (display->platform.kabylake || display->platform.coffeelake || - display->platform.cometlake) - return i915->dram_info.symmetric_memory; + display->platform.cometlake) { + const struct dram_info *dram_info = intel_dram_info(display->drm); + + return dram_info->symmetric_memory; + } return true; } @@ -3213,8 +3217,7 @@ static void adjust_wm_latency(struct intel_display *display, u16 wm[], int num_levels, int read_latency) { - struct drm_i915_private *i915 = to_i915(display->drm); - bool wm_lv_0_adjust_needed = i915->dram_info.wm_lv_0_adjust_needed; + const struct dram_info *dram_info = intel_dram_info(display->drm); int i, level; /* @@ -3250,7 +3253,7 @@ adjust_wm_latency(struct intel_display *display, * any underrun. If not able to get Dimm info assume 16GB dimm * to avoid any underrun. */ - if (wm_lv_0_adjust_needed) + if (!display->platform.dg2 && dram_info->wm_lv_0_adjust_needed) wm[0] += 1; } diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index 346737f15fa9..3433deb635ef 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -30,15 +30,17 @@ #include <drm/drm_crtc.h> #include <drm/drm_edid.h> #include <drm/drm_mipi_dsi.h> +#include <drm/drm_print.h> #include <drm/drm_probe_helper.h> -#include "i915_drv.h" #include "i915_reg.h" +#include "i915_utils.h" #include "intel_atomic.h" #include "intel_backlight.h" #include "intel_connector.h" #include "intel_crtc.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dsi.h" #include "intel_dsi_vbt.h" @@ -253,18 +255,16 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, static void band_gap_reset(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); + vlv_flisdsi_get(display->drm); - vlv_flisdsi_get(dev_priv); - - vlv_flisdsi_write(dev_priv, 0x08, 0x0001); - vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); - vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); + vlv_flisdsi_write(display->drm, 0x08, 0x0001); + vlv_flisdsi_write(display->drm, 0x0F, 0x0005); + vlv_flisdsi_write(display->drm, 0x0F, 0x0025); udelay(150); - vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); - vlv_flisdsi_write(dev_priv, 0x08, 0x0000); + vlv_flisdsi_write(display->drm, 0x0F, 0x0000); + vlv_flisdsi_write(display->drm, 0x08, 0x0000); - vlv_flisdsi_put(dev_priv); + vlv_flisdsi_put(display->drm); } static int intel_dsi_compute_config(struct intel_encoder *encoder, @@ -457,17 +457,16 @@ static void bxt_dsi_device_ready(struct intel_encoder *encoder) static void vlv_dsi_device_ready(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; drm_dbg_kms(display->drm, "\n"); - vlv_flisdsi_get(dev_priv); + vlv_flisdsi_get(display->drm); /* program rcomp for compliance, reduce from 50 ohms to 45 ohms * needed everytime after power gate */ - vlv_flisdsi_write(dev_priv, 0x04, 0x0004); - vlv_flisdsi_put(dev_priv); + vlv_flisdsi_write(display->drm, 0x04, 0x0004); + vlv_flisdsi_put(display->drm); /* bandgap reset is needed after everytime we do power gate */ band_gap_reset(display); @@ -1020,7 +1019,7 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, unsigned int lane_count = intel_dsi->lane_count; unsigned int bpp, fmt; enum port port; - u16 hactive, hfp, hsync, hbp, vfp, vsync; + u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; u16 hfp_sw, hsync_sw, hbp_sw; u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, crtc_hblank_start_sw, crtc_hblank_end_sw; @@ -1056,7 +1055,7 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, BXT_MIPI_TRANS_VACTIVE(port)); adjusted_mode->crtc_vtotal = intel_de_read(display, - BXT_MIPI_TRANS_VTOTAL(port)); + BXT_MIPI_TRANS_VTOTAL(port)) + 1; hactive = adjusted_mode->crtc_hdisplay; hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port)); @@ -1084,6 +1083,7 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, /* vertical values are in terms of lines */ vfp = intel_de_read(display, MIPI_VFP_COUNT(display, port)); + vbp = intel_de_read(display, MIPI_VBP_COUNT(display, port)); vsync = intel_de_read(display, MIPI_VSYNC_PADDING_COUNT(display, port)); adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; @@ -1092,6 +1092,8 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; + drm_WARN_ON(display->drm, adjusted_mode->crtc_vdisplay + + vfp + vsync + vbp != adjusted_mode->crtc_vtotal); adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; @@ -1260,7 +1262,7 @@ static void set_dsi_timings(struct intel_encoder *encoder, intel_de_write(display, BXT_MIPI_TRANS_VACTIVE(port), adjusted_mode->crtc_vdisplay); intel_de_write(display, BXT_MIPI_TRANS_VTOTAL(port), - adjusted_mode->crtc_vtotal); + adjusted_mode->crtc_vtotal - 1); } intel_de_write(display, MIPI_HACTIVE_AREA_COUNT(display, port), diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c index 7ce924a5ef90..d42b61e6f076 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c @@ -28,7 +28,9 @@ #include <linux/kernel.h> #include <linux/string_helpers.h> -#include "i915_drv.h" +#include <drm/drm_print.h> + +#include "i915_utils.h" #include "intel_de.h" #include "intel_display_types.h" #include "intel_dsi.h" @@ -214,15 +216,14 @@ void vlv_dsi_pll_enable(struct intel_encoder *encoder, const struct intel_crtc_state *config) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); drm_dbg_kms(display->drm, "\n"); - vlv_cck_get(dev_priv); + vlv_cck_get(display->drm); - vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); - vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div); - vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, + vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, 0); + vlv_cck_write(display->drm, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div); + vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN); /* wait at least 0.5 us after ungating before enabling VCO, @@ -230,16 +231,16 @@ void vlv_dsi_pll_enable(struct intel_encoder *encoder, */ usleep_range(10, 50); - vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl); + vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl); - if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & + if (wait_for(vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_LOCK, 20)) { - vlv_cck_put(dev_priv); + vlv_cck_put(display->drm); drm_err(display->drm, "DSI PLL lock failed\n"); return; } - vlv_cck_put(dev_priv); + vlv_cck_put(display->drm); drm_dbg_kms(display->drm, "DSI PLL locked\n"); } @@ -247,19 +248,18 @@ void vlv_dsi_pll_enable(struct intel_encoder *encoder, void vlv_dsi_pll_disable(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 tmp; drm_dbg_kms(display->drm, "\n"); - vlv_cck_get(dev_priv); + vlv_cck_get(display->drm); - tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); + tmp = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL); tmp &= ~DSI_PLL_VCO_EN; tmp |= DSI_PLL_LDO_GATE; - vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); + vlv_cck_write(display->drm, CCK_REG_DSI_PLL_CONTROL, tmp); - vlv_cck_put(dev_priv); + vlv_cck_put(display->drm); } bool bxt_dsi_pll_is_enabled(struct intel_display *display) @@ -323,15 +323,14 @@ u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, struct intel_crtc_state *config) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 pll_ctl, pll_div; drm_dbg_kms(display->drm, "\n"); - vlv_cck_get(dev_priv); - pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); - pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); - vlv_cck_put(dev_priv); + vlv_cck_get(display->drm); + pll_ctl = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL); + pll_div = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_DIVIDER); + vlv_cck_put(display->drm); config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK; config->dsi_pll.div = pll_div; @@ -592,12 +591,11 @@ void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) static void assert_dsi_pll(struct intel_display *display, bool state) { - struct drm_i915_private *i915 = to_i915(display->drm); bool cur_state; - vlv_cck_get(i915); - cur_state = vlv_cck_read(i915, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN; - vlv_cck_put(i915); + vlv_cck_get(display->drm); + cur_state = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN; + vlv_cck_put(display->drm); INTEL_DISPLAY_STATE_WARN(display, cur_state != state, "DSI PLL state assertion failure (expected %s, current %s)\n", diff --git a/drivers/gpu/drm/i915/display/vlv_sideband.c b/drivers/gpu/drm/i915/display/vlv_sideband.c new file mode 100644 index 000000000000..e18045f2b89d --- /dev/null +++ b/drivers/gpu/drm/i915/display/vlv_sideband.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: MIT +/* Copyright © 2025 Intel Corporation */ + +#include <drm/drm_print.h> + +#include "intel_display_core.h" +#include "intel_display_types.h" +#include "intel_dpio_phy.h" +#include "vlv_sideband.h" + +static enum vlv_iosf_sb_unit vlv_dpio_phy_to_unit(struct intel_display *display, + enum dpio_phy phy) +{ + /* + * IOSF_PORT_DPIO: VLV x2 PHY (DP/HDMI B and C), CHV x1 PHY (DP/HDMI D) + * IOSF_PORT_DPIO_2: CHV x2 PHY (DP/HDMI B and C) + */ + if (display->platform.cherryview) + return phy == DPIO_PHY0 ? VLV_IOSF_SB_DPIO_2 : VLV_IOSF_SB_DPIO; + else + return VLV_IOSF_SB_DPIO; +} + +u32 vlv_dpio_read(struct drm_device *drm, enum dpio_phy phy, int reg) +{ + struct intel_display *display = to_intel_display(drm); + enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(display, phy); + u32 val; + + val = vlv_iosf_sb_read(drm, unit, reg); + + /* + * FIXME: There might be some registers where all 1's is a valid value, + * so ideally we should check the register offset instead... + */ + drm_WARN(display->drm, val == 0xffffffff, + "DPIO PHY%d read reg 0x%x == 0x%x\n", + phy, reg, val); + + return val; +} + +void vlv_dpio_write(struct drm_device *drm, + enum dpio_phy phy, int reg, u32 val) +{ + struct intel_display *display = to_intel_display(drm); + enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(display, phy); + + vlv_iosf_sb_write(drm, unit, reg, val); +} diff --git a/drivers/gpu/drm/i915/display/vlv_sideband.h b/drivers/gpu/drm/i915/display/vlv_sideband.h new file mode 100644 index 000000000000..2c240d81fead --- /dev/null +++ b/drivers/gpu/drm/i915/display/vlv_sideband.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright © 2025 Intel Corporation */ + +#ifndef _VLV_SIDEBAND_H_ +#define _VLV_SIDEBAND_H_ + +#include <linux/bitops.h> +#include <linux/types.h> + +#include "vlv_iosf_sb.h" +#include "vlv_iosf_sb_reg.h" + +enum dpio_phy; +struct drm_device; + +static inline void vlv_bunit_get(struct drm_device *drm) +{ + vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_BUNIT)); +} + +static inline u32 vlv_bunit_read(struct drm_device *drm, u32 reg) +{ + return vlv_iosf_sb_read(drm, VLV_IOSF_SB_BUNIT, reg); +} + +static inline void vlv_bunit_write(struct drm_device *drm, u32 reg, u32 val) +{ + vlv_iosf_sb_write(drm, VLV_IOSF_SB_BUNIT, reg, val); +} + +static inline void vlv_bunit_put(struct drm_device *drm) +{ + vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_BUNIT)); +} + +static inline void vlv_cck_get(struct drm_device *drm) +{ + vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_CCK)); +} + +static inline u32 vlv_cck_read(struct drm_device *drm, u32 reg) +{ + return vlv_iosf_sb_read(drm, VLV_IOSF_SB_CCK, reg); +} + +static inline void vlv_cck_write(struct drm_device *drm, u32 reg, u32 val) +{ + vlv_iosf_sb_write(drm, VLV_IOSF_SB_CCK, reg, val); +} + +static inline void vlv_cck_put(struct drm_device *drm) +{ + vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_CCK)); +} + +static inline void vlv_ccu_get(struct drm_device *drm) +{ + vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_CCU)); +} + +static inline u32 vlv_ccu_read(struct drm_device *drm, u32 reg) +{ + return vlv_iosf_sb_read(drm, VLV_IOSF_SB_CCU, reg); +} + +static inline void vlv_ccu_write(struct drm_device *drm, u32 reg, u32 val) +{ + vlv_iosf_sb_write(drm, VLV_IOSF_SB_CCU, reg, val); +} + +static inline void vlv_ccu_put(struct drm_device *drm) +{ + vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_CCU)); +} + +static inline void vlv_dpio_get(struct drm_device *drm) +{ + vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_DPIO) | BIT(VLV_IOSF_SB_DPIO_2)); +} + +#ifdef I915 +u32 vlv_dpio_read(struct drm_device *drm, enum dpio_phy phy, int reg); +void vlv_dpio_write(struct drm_device *drm, + enum dpio_phy phy, int reg, u32 val); +#else +static inline u32 vlv_dpio_read(struct drm_device *drm, int phy, int reg) +{ + return 0; +} +static inline void vlv_dpio_write(struct drm_device *drm, + int phy, int reg, u32 val) +{ +} +#endif + +static inline void vlv_dpio_put(struct drm_device *drm) +{ + vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_DPIO) | BIT(VLV_IOSF_SB_DPIO_2)); +} + +static inline void vlv_flisdsi_get(struct drm_device *drm) +{ + vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_FLISDSI)); +} + +static inline u32 vlv_flisdsi_read(struct drm_device *drm, u32 reg) +{ + return vlv_iosf_sb_read(drm, VLV_IOSF_SB_FLISDSI, reg); +} + +static inline void vlv_flisdsi_write(struct drm_device *drm, u32 reg, u32 val) +{ + vlv_iosf_sb_write(drm, VLV_IOSF_SB_FLISDSI, reg, val); +} + +static inline void vlv_flisdsi_put(struct drm_device *drm) +{ + vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_FLISDSI)); +} + +static inline void vlv_nc_get(struct drm_device *drm) +{ + vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_NC)); +} + +static inline u32 vlv_nc_read(struct drm_device *drm, u8 addr) +{ + return vlv_iosf_sb_read(drm, VLV_IOSF_SB_NC, addr); +} + +static inline void vlv_nc_put(struct drm_device *drm) +{ + vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_NC)); +} + +static inline void vlv_punit_get(struct drm_device *drm) +{ + vlv_iosf_sb_get(drm, BIT(VLV_IOSF_SB_PUNIT)); +} + +static inline u32 vlv_punit_read(struct drm_device *drm, u32 addr) +{ + return vlv_iosf_sb_read(drm, VLV_IOSF_SB_PUNIT, addr); +} + +static inline int vlv_punit_write(struct drm_device *drm, u32 addr, u32 val) +{ + return vlv_iosf_sb_write(drm, VLV_IOSF_SB_PUNIT, addr, val); +} + +static inline void vlv_punit_put(struct drm_device *drm) +{ + vlv_iosf_sb_put(drm, BIT(VLV_IOSF_SB_PUNIT)); +} + +#endif /* _VLV_SIDEBAND_H_ */ |