diff options
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_vdsc.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_vdsc.c | 184 |
1 files changed, 162 insertions, 22 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 3a21c65ffa85..85749370508c 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -5,11 +5,13 @@ * Author: Gaurav K Singh <gaurav.k.singh@intel.com> * Manasi Navare <manasi.d.navare@intel.com> */ - +#include <linux/limits.h> #include "i915_drv.h" +#include "intel_de.h" #include "intel_display_types.h" #include "intel_dsi.h" #include "intel_vdsc.h" +#include "intel_qp_tables.h" enum ROW_INDEX_BPP { ROW_INDEX_6BPP = 0, @@ -372,12 +374,81 @@ static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state) return true; } +static void +calculate_rc_params(struct rc_parameters *rc, + struct drm_dsc_config *vdsc_cfg) +{ + int bpc = vdsc_cfg->bits_per_component; + int bpp = vdsc_cfg->bits_per_pixel >> 4; + int ofs_und6[] = { 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 }; + int ofs_und8[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; + int ofs_und12[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; + int ofs_und15[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 }; + int qp_bpc_modifier = (bpc - 8) * 2; + u32 res, buf_i, bpp_i; + + if (vdsc_cfg->slice_height >= 8) + rc->first_line_bpg_offset = + 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100); + else + rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1); + + /* Our hw supports only 444 modes as of today */ + if (bpp >= 12) + rc->initial_offset = 2048; + else if (bpp >= 10) + rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2); + else if (bpp >= 8) + rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2); + else + rc->initial_offset = 6144; + + /* initial_xmit_delay = rc_model_size/2/compression_bpp */ + rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp); + + rc->flatness_min_qp = 3 + qp_bpc_modifier; + rc->flatness_max_qp = 12 + qp_bpc_modifier; + + rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier; + rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier; + + bpp_i = (2 * (bpp - 6)); + for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) { + /* Read range_minqp and range_max_qp from qp tables */ + rc->rc_range_params[buf_i].range_min_qp = + intel_lookup_range_min_qp(bpc, buf_i, bpp_i); + rc->rc_range_params[buf_i].range_max_qp = + intel_lookup_range_max_qp(bpc, buf_i, bpp_i); + + /* Calculate range_bgp_offset */ + if (bpp <= 6) { + rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i]; + } else if (bpp <= 8) { + res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2); + rc->rc_range_params[buf_i].range_bpg_offset = + ofs_und6[buf_i] + res; + } else if (bpp <= 12) { + rc->rc_range_params[buf_i].range_bpg_offset = + ofs_und8[buf_i]; + } else if (bpp <= 15) { + res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3); + rc->rc_range_params[buf_i].range_bpg_offset = + ofs_und12[buf_i] + res; + } else { + rc->rc_range_params[buf_i].range_bpg_offset = + ofs_und15[buf_i]; + } + } +} + int intel_dsc_compute_params(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; u16 compressed_bpp = pipe_config->dsc.compressed_bpp; const struct rc_parameters *rc_params; + struct rc_parameters *rc = NULL; u8 i = 0; vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; @@ -412,9 +483,24 @@ int intel_dsc_compute_params(struct intel_encoder *encoder, vdsc_cfg->rc_buf_thresh[13] = 0x7D; } - rc_params = get_rc_params(compressed_bpp, vdsc_cfg->bits_per_component); - if (!rc_params) - return -EINVAL; + /* + * From XE_LPD onwards we supports compression bpps in steps of 1 + * upto uncompressed bpp-1, hence add calculations for all the rc + * parameters + */ + if (DISPLAY_VER(dev_priv) >= 13) { + rc = kmalloc(sizeof(*rc), GFP_KERNEL); + if (!rc) + return -ENOMEM; + + calculate_rc_params(rc, vdsc_cfg); + rc_params = rc; + } else { + rc_params = get_rc_params(compressed_bpp, + vdsc_cfg->bits_per_component); + if (!rc_params) + return -EINVAL; + } vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset; vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay; @@ -440,20 +526,20 @@ int intel_dsc_compute_params(struct intel_encoder *encoder, /* * BitsPerComponent value determines mux_word_size: - * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits - * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to - * 48 bits + * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to + * 48 bits otherwise 64 */ - if (vdsc_cfg->bits_per_component == 8 || - vdsc_cfg->bits_per_component == 10) + if (vdsc_cfg->bits_per_component <= 10) vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; - else if (vdsc_cfg->bits_per_component == 12) + else vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); + kfree(rc); + return 0; } @@ -469,13 +555,13 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state) * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases: * * - ICL eDP/DSI transcoder - * - Gen12+ (except RKL) pipe A + * - Display version 12 (except RKL) pipe A * * For any other pipe, VDSC/joining uses the power well associated with * the pipe in use. Hence another reference on the pipe power domain * will suffice. (Except no VDSC/joining on ICL pipe A.) */ - if (DISPLAY_VER(i915) >= 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A) + if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A) return POWER_DOMAIN_TRANSCODER_VDSC_PW2; else if (is_pipe_dsc(crtc_state)) return POWER_DOMAIN_PIPE(pipe); @@ -1020,6 +1106,43 @@ static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state) return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) : DSS_CTL2; } +static struct intel_crtc * +_get_crtc_for_pipe(struct drm_i915_private *i915, enum pipe pipe) +{ + if (!intel_pipe_valid(i915, pipe)) + return NULL; + + return intel_get_crtc_for_pipe(i915, pipe); +} + +struct intel_crtc * +intel_dsc_get_bigjoiner_secondary(const struct intel_crtc *primary_crtc) +{ + return _get_crtc_for_pipe(to_i915(primary_crtc->base.dev), primary_crtc->pipe + 1); +} + +static struct intel_crtc * +intel_dsc_get_bigjoiner_primary(const struct intel_crtc *secondary_crtc) +{ + return _get_crtc_for_pipe(to_i915(secondary_crtc->base.dev), secondary_crtc->pipe - 1); +} + +void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + u32 dss_ctl1_val = 0; + + if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) { + if (crtc_state->bigjoiner_slave) + dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE; + else + dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER; + + intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val); + } +} + void intel_dsc_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -1059,11 +1182,31 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - if (!old_crtc_state->dsc.compression_enable) - return; + /* Disable only if either of them is enabled */ + if (old_crtc_state->dsc.compression_enable || + old_crtc_state->bigjoiner) { + intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0); + intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0); + } +} + +void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + u32 dss_ctl1; - intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0); - intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0); + dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state)); + if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) { + crtc_state->bigjoiner = true; + crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_secondary(crtc); + drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc); + } else if (dss_ctl1 & UNCOMPRESSED_JOINER_SLAVE) { + crtc_state->bigjoiner = true; + crtc_state->bigjoiner_slave = true; + crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_primary(crtc); + drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc); + } } void intel_dsc_get_config(struct intel_crtc_state *crtc_state) @@ -1100,14 +1243,11 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) if (!(dss_ctl1 & MASTER_BIG_JOINER_ENABLE)) { crtc_state->bigjoiner_slave = true; - if (!WARN_ON(crtc->pipe == PIPE_A)) - crtc_state->bigjoiner_linked_crtc = - intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1); + crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_primary(crtc); } else { - if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1)) - crtc_state->bigjoiner_linked_crtc = - intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1); + crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_secondary(crtc); } + drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc); } /* FIXME: add more state readout as needed */ |