diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c index 31030f86be86..235548c0b41f 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -451,19 +451,16 @@ void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev) static void xgpu_ai_init_reg_access_mode(struct amdgpu_device *adev) { - uint32_t rlc_fw_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); - uint32_t sos_fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); - adev->virt.reg_access_mode = AMDGPU_VIRT_REG_ACCESS_LEGACY; - if (rlc_fw_ver >= 0x5d) - adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_RLC; + /* Enable L1 security reg access mode by defaul, as non-security VF + * will no longer be supported. + */ + adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_RLC; - if (sos_fw_ver >= 0x80455) - adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH; + adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH; - if (sos_fw_ver >= 0x8045b) - adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_SKIP_SEETING; + adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_SKIP_SEETING; } const struct amdgpu_virt_ops xgpu_ai_virt_ops = { |