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-rw-r--r--drivers/clk/Kconfig16
-rw-r--r--drivers/clk/Makefile2
-rw-r--r--drivers/clk/actions/owl-common.c6
-rw-r--r--drivers/clk/actions/owl-common.h2
-rw-r--r--drivers/clk/axs10x/pll_clock.c3
-rw-r--r--drivers/clk/baikal-t1/clk-ccu-div.c1
-rw-r--r--drivers/clk/bcm/clk-bcm2835.c2
-rw-r--r--drivers/clk/bcm/clk-bcm63xx-gate.c1
-rw-r--r--drivers/clk/bcm/clk-sr.c2
-rw-r--r--drivers/clk/clk-aspeed.c5
-rw-r--r--drivers/clk/clk-ast2600.c4
-rw-r--r--drivers/clk/clk-axm5516.c4
-rw-r--r--drivers/clk/clk-bm1880.c11
-rw-r--r--drivers/clk/clk-cdce925.c2
-rw-r--r--drivers/clk/clk-cs2000-cp.c2
-rw-r--r--drivers/clk/clk-en7523.c3
-rw-r--r--drivers/clk/clk-fsl-sai.c4
-rw-r--r--drivers/clk/clk-gemini.c6
-rw-r--r--drivers/clk/clk-gpio.c2
-rw-r--r--drivers/clk/clk-hsdk-pll.c5
-rw-r--r--drivers/clk/clk-k210.c1
-rw-r--r--drivers/clk/clk-lmk04832.c35
-rw-r--r--drivers/clk/clk-milbeaut.c3
-rw-r--r--drivers/clk/clk-oxnas.c251
-rw-r--r--drivers/clk/clk-palmas.c1
-rw-r--r--drivers/clk/clk-plldig.c2
-rw-r--r--drivers/clk/clk-qoriq.c2
-rw-r--r--drivers/clk/clk-scpi.c1
-rw-r--r--drivers/clk/clk-si5351.c2
-rw-r--r--drivers/clk/clk-sp7021.c3
-rw-r--r--drivers/clk/clk-versaclock3.c1143
-rw-r--r--drivers/clk/clk-versaclock5.c3
-rw-r--r--drivers/clk/clk-versaclock7.c3
-rw-r--r--drivers/clk/hisilicon/clk-hi3559a.c2
-rw-r--r--drivers/clk/hisilicon/clk-hi3620.c1
-rw-r--r--drivers/clk/hisilicon/clk-hi3660.c2
-rw-r--r--drivers/clk/hisilicon/clk-hi3670.c2
-rw-r--r--drivers/clk/hisilicon/clk-hi6220-stub.c2
-rw-r--r--drivers/clk/hisilicon/clk-hi6220.c3
-rw-r--r--drivers/clk/hisilicon/clk-hip04.c3
-rw-r--r--drivers/clk/hisilicon/clk.c2
-rw-r--r--drivers/clk/hisilicon/crg-hi3516cv300.c2
-rw-r--r--drivers/clk/hisilicon/crg-hi3798cv200.c2
-rw-r--r--drivers/clk/imx/Makefile3
-rw-r--r--drivers/clk/imx/clk-composite-8m.c12
-rw-r--r--drivers/clk/imx/clk-fracn-gppll.c1
-rw-r--r--drivers/clk/imx/clk-gpr-mux.c8
-rw-r--r--drivers/clk/imx/clk-imx25.c5
-rw-r--r--drivers/clk/imx/clk-imx8-acm.c476
-rw-r--r--drivers/clk/imx/clk-imx8mp.c5
-rw-r--r--drivers/clk/imx/clk-imx8qxp-lpcg.c6
-rw-r--r--drivers/clk/imx/clk-imx8qxp.c1
-rw-r--r--drivers/clk/imx/clk-imx8ulp.c4
-rw-r--r--drivers/clk/imx/clk-imx93.c4
-rw-r--r--drivers/clk/imx/clk-pll14xx.c13
-rw-r--r--drivers/clk/imx/clk-pllv4.c46
-rw-r--r--drivers/clk/imx/clk-scu.c2
-rw-r--r--drivers/clk/imx/clk.h1
-rw-r--r--drivers/clk/keystone/pll.c2
-rw-r--r--drivers/clk/keystone/sci-clk.c3
-rw-r--r--drivers/clk/mediatek/clk-mt2701-aud.c2
-rw-r--r--drivers/clk/mediatek/clk-mt2701-g3d.c4
-rw-r--r--drivers/clk/mediatek/clk-mt2701.c10
-rw-r--r--drivers/clk/mediatek/clk-mt2712.c4
-rw-r--r--drivers/clk/mediatek/clk-mt6765.c23
-rw-r--r--drivers/clk/mediatek/clk-mt6779-aud.c4
-rw-r--r--drivers/clk/mediatek/clk-mt6779.c2
-rw-r--r--drivers/clk/mediatek/clk-mt6797.c2
-rw-r--r--drivers/clk/mediatek/clk-mt7622-aud.c2
-rw-r--r--drivers/clk/mediatek/clk-mt7622-eth.c4
-rw-r--r--drivers/clk/mediatek/clk-mt7622-hif.c4
-rw-r--r--drivers/clk/mediatek/clk-mt7622.c4
-rw-r--r--drivers/clk/mediatek/clk-mt7629-eth.c2
-rw-r--r--drivers/clk/mediatek/clk-mt7629-hif.c4
-rw-r--r--drivers/clk/mediatek/clk-mt7629.c2
-rw-r--r--drivers/clk/mediatek/clk-mt7981-apmixed.c4
-rw-r--r--drivers/clk/mediatek/clk-mt7981-eth.c4
-rw-r--r--drivers/clk/mediatek/clk-mt7981-infracfg.c4
-rw-r--r--drivers/clk/mediatek/clk-mt7981-topckgen.c4
-rw-r--r--drivers/clk/mediatek/clk-mt7986-apmixed.c4
-rw-r--r--drivers/clk/mediatek/clk-mt7986-eth.c4
-rw-r--r--drivers/clk/mediatek/clk-mt7986-infracfg.c4
-rw-r--r--drivers/clk/mediatek/clk-mt7986-topckgen.c4
-rw-r--r--drivers/clk/mediatek/clk-mt8167-aud.c4
-rw-r--r--drivers/clk/mediatek/clk-mt8167-img.c4
-rw-r--r--drivers/clk/mediatek/clk-mt8167-mfgcfg.c4
-rw-r--r--drivers/clk/mediatek/clk-mt8167-mm.c4
-rw-r--r--drivers/clk/mediatek/clk-mt8167-vdec.c4
-rw-r--r--drivers/clk/mediatek/clk-mt8173-mm.c2
-rw-r--r--drivers/clk/mediatek/clk-mt8183.c4
-rw-r--r--drivers/clk/mediatek/clk-mt8188-apmixedsys.c2
-rw-r--r--drivers/clk/mediatek/clk-mt8188-topckgen.c2
-rw-r--r--drivers/clk/mediatek/clk-mt8192-cam.c2
-rw-r--r--drivers/clk/mediatek/clk-mt8192-img.c2
-rw-r--r--drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c2
-rw-r--r--drivers/clk/mediatek/clk-mt8192-ipe.c2
-rw-r--r--drivers/clk/mediatek/clk-mt8192-mdp.c2
-rw-r--r--drivers/clk/mediatek/clk-mt8192-mfg.c2
-rw-r--r--drivers/clk/mediatek/clk-mt8192-msdc.c2
-rw-r--r--drivers/clk/mediatek/clk-mt8192-scp_adsp.c2
-rw-r--r--drivers/clk/mediatek/clk-mt8192-vdec.c2
-rw-r--r--drivers/clk/mediatek/clk-mt8192-venc.c2
-rw-r--r--drivers/clk/mediatek/clk-mt8192.c4
-rw-r--r--drivers/clk/mediatek/clk-mt8195-apmixedsys.c2
-rw-r--r--drivers/clk/mediatek/clk-mt8195-topckgen.c2
-rw-r--r--drivers/clk/mediatek/clk-mt8365.c4
-rw-r--r--drivers/clk/mediatek/clk-mt8516-aud.c4
-rw-r--r--drivers/clk/meson/Kconfig9
-rw-r--r--drivers/clk/meson/Makefile1
-rw-r--r--drivers/clk/meson/a1-peripherals.c327
-rw-r--r--drivers/clk/meson/a1-peripherals.h67
-rw-r--r--drivers/clk/meson/a1-pll.c40
-rw-r--r--drivers/clk/meson/a1-pll.h19
-rw-r--r--drivers/clk/meson/axg-aoclk.c48
-rw-r--r--drivers/clk/meson/axg-aoclk.h18
-rw-r--r--drivers/clk/meson/axg-audio.c853
-rw-r--r--drivers/clk/meson/axg-audio.h75
-rw-r--r--drivers/clk/meson/axg.c287
-rw-r--r--drivers/clk/meson/axg.h63
-rw-r--r--drivers/clk/meson/g12a-aoclk.c72
-rw-r--r--drivers/clk/meson/g12a-aoclk.h32
-rw-r--r--drivers/clk/meson/g12a.c1491
-rw-r--r--drivers/clk/meson/g12a.h145
-rw-r--r--drivers/clk/meson/gxbb-aoclk.c14
-rw-r--r--drivers/clk/meson/gxbb-aoclk.h15
-rw-r--r--drivers/clk/meson/gxbb.c850
-rw-r--r--drivers/clk/meson/gxbb.h81
-rw-r--r--drivers/clk/meson/meson-aoclk.c11
-rw-r--r--drivers/clk/meson/meson-aoclk.h3
-rw-r--r--drivers/clk/meson/meson-clkc-utils.c25
-rw-r--r--drivers/clk/meson/meson-clkc-utils.h19
-rw-r--r--drivers/clk/meson/meson-eeclk.c11
-rw-r--r--drivers/clk/meson/meson-eeclk.h3
-rw-r--r--drivers/clk/meson/meson8b.c1318
-rw-r--r--drivers/clk/meson/meson8b.h117
-rw-r--r--drivers/clk/microchip/clk-pic32mzda.c2
-rw-r--r--drivers/clk/mmp/Makefile4
-rw-r--r--drivers/clk/mmp/clk-audio.c6
-rw-r--r--drivers/clk/mmp/clk-mmp2.c454
-rw-r--r--drivers/clk/mmp/clk-of-mmp2.c4
-rw-r--r--drivers/clk/mmp/clk-of-pxa168.c4
-rw-r--r--drivers/clk/mmp/clk-of-pxa1928.c7
-rw-r--r--drivers/clk/mmp/clk-of-pxa910.c4
-rw-r--r--drivers/clk/mmp/clk-pxa168.c354
-rw-r--r--drivers/clk/mmp/clk-pxa910.c325
-rw-r--r--drivers/clk/mvebu/ap-cpu-clk.c1
-rw-r--r--drivers/clk/mvebu/armada-37xx-periph.c5
-rw-r--r--drivers/clk/mvebu/armada-37xx-tbg.c4
-rw-r--r--drivers/clk/mvebu/cp110-system-controller.c2
-rw-r--r--drivers/clk/nuvoton/clk-ma35d1.c3
-rw-r--r--drivers/clk/qcom/Kconfig28
-rw-r--r--drivers/clk/qcom/Makefile2
-rw-r--r--drivers/clk/qcom/apss-ipq-pll.c2
-rw-r--r--drivers/clk/qcom/camcc-sc7180.c4
-rw-r--r--drivers/clk/qcom/camcc-sc7280.c2
-rw-r--r--drivers/clk/qcom/clk-cbf-8996.c10
-rw-r--r--drivers/clk/qcom/clk-cpu-8996.c2
-rw-r--r--drivers/clk/qcom/clk-rpm.c1
-rw-r--r--drivers/clk/qcom/clk-rpmh.c1
-rw-r--r--drivers/clk/qcom/clk-smd-rpm.c340
-rw-r--r--drivers/clk/qcom/clk-spmi-pmic-div.c2
-rw-r--r--drivers/clk/qcom/dispcc-qcm2290.c2
-rw-r--r--drivers/clk/qcom/dispcc-sc8280xp.c8
-rw-r--r--drivers/clk/qcom/dispcc-sm6115.c2
-rw-r--r--drivers/clk/qcom/dispcc-sm8450.c15
-rw-r--r--drivers/clk/qcom/dispcc-sm8550.c15
-rw-r--r--drivers/clk/qcom/gcc-apq8084.c1
-rw-r--r--drivers/clk/qcom/gcc-ipq4019.c7
-rw-r--r--drivers/clk/qcom/gcc-ipq5018.c3724
-rw-r--r--drivers/clk/qcom/gcc-ipq5332.c209
-rw-r--r--drivers/clk/qcom/gcc-ipq6018.c1
-rw-r--r--drivers/clk/qcom/gcc-ipq806x.c2
-rw-r--r--drivers/clk/qcom/gcc-ipq8074.c1
-rw-r--r--drivers/clk/qcom/gcc-ipq9574.c37
-rw-r--r--drivers/clk/qcom/gcc-mdm9607.c1
-rw-r--r--drivers/clk/qcom/gcc-mdm9615.c262
-rw-r--r--drivers/clk/qcom/gcc-msm8660.c1
-rw-r--r--drivers/clk/qcom/gcc-msm8909.c1
-rw-r--r--drivers/clk/qcom/gcc-msm8916.c1
-rw-r--r--drivers/clk/qcom/gcc-msm8917.c4
-rw-r--r--drivers/clk/qcom/gcc-msm8939.c1
-rw-r--r--drivers/clk/qcom/gcc-msm8953.c1
-rw-r--r--drivers/clk/qcom/gcc-msm8976.c2
-rw-r--r--drivers/clk/qcom/gcc-msm8994.c1
-rw-r--r--drivers/clk/qcom/gcc-msm8996.c1
-rw-r--r--drivers/clk/qcom/gcc-msm8998.c65
-rw-r--r--drivers/clk/qcom/gcc-qdu1000.c162
-rw-r--r--drivers/clk/qcom/gcc-sa8775p.c2
-rw-r--r--drivers/clk/qcom/gcc-sc7180.c3
-rw-r--r--drivers/clk/qcom/gcc-sc7280.c2
-rw-r--r--drivers/clk/qcom/gcc-sc8180x.c1
-rw-r--r--drivers/clk/qcom/gcc-sc8280xp.c147
-rw-r--r--drivers/clk/qcom/gcc-sdm660.c1
-rw-r--r--drivers/clk/qcom/gcc-sdm845.c1
-rw-r--r--drivers/clk/qcom/gcc-sdx65.c2
-rw-r--r--drivers/clk/qcom/gcc-sdx75.c3
-rw-r--r--drivers/clk/qcom/gcc-sm6115.c3
-rw-r--r--drivers/clk/qcom/gcc-sm6125.c1
-rw-r--r--drivers/clk/qcom/gcc-sm6350.c1
-rw-r--r--drivers/clk/qcom/gcc-sm6375.c3
-rw-r--r--drivers/clk/qcom/gcc-sm7150.c5
-rw-r--r--drivers/clk/qcom/gcc-sm8150.c1
-rw-r--r--drivers/clk/qcom/gcc-sm8250.c3
-rw-r--r--drivers/clk/qcom/gcc-sm8450.c7
-rw-r--r--drivers/clk/qcom/gcc-sm8550.c3
-rw-r--r--drivers/clk/qcom/gpucc-msm8998.c3
-rw-r--r--drivers/clk/qcom/gpucc-sa8775p.c4
-rw-r--r--drivers/clk/qcom/gpucc-sdm660.c1
-rw-r--r--drivers/clk/qcom/gpucc-sm6115.c3
-rw-r--r--drivers/clk/qcom/gpucc-sm6125.c3
-rw-r--r--drivers/clk/qcom/gpucc-sm6350.c18
-rw-r--r--drivers/clk/qcom/gpucc-sm6375.c3
-rw-r--r--drivers/clk/qcom/gpucc-sm8350.c2
-rw-r--r--drivers/clk/qcom/gpucc-sm8450.c3
-rw-r--r--drivers/clk/qcom/gpucc-sm8550.c3
-rw-r--r--drivers/clk/qcom/lcc-ipq806x.c1
-rw-r--r--drivers/clk/qcom/lcc-mdm9615.c572
-rw-r--r--drivers/clk/qcom/lcc-msm8960.c20
-rw-r--r--drivers/clk/qcom/lpass-gfm-sm8250.c2
-rw-r--r--drivers/clk/qcom/lpassaudiocc-sc7280.c3
-rw-r--r--drivers/clk/qcom/lpasscc-sc7280.c16
-rw-r--r--drivers/clk/qcom/lpasscc-sc8280xp.c4
-rw-r--r--drivers/clk/qcom/lpasscorecc-sc7180.c2
-rw-r--r--drivers/clk/qcom/lpasscorecc-sc7280.c3
-rw-r--r--drivers/clk/qcom/mmcc-msm8974.c12
-rw-r--r--drivers/clk/qcom/mmcc-msm8994.c1
-rw-r--r--drivers/clk/qcom/mmcc-msm8996.c1
-rw-r--r--drivers/clk/qcom/mmcc-msm8998.c36
-rw-r--r--drivers/clk/qcom/mss-sc7180.c13
-rw-r--r--drivers/clk/qcom/q6sstop-qcs404.c15
-rw-r--r--drivers/clk/qcom/reset.c3
-rw-r--r--drivers/clk/qcom/tcsrcc-sm8550.c3
-rw-r--r--drivers/clk/qcom/turingcc-qcs404.c13
-rw-r--r--drivers/clk/qcom/videocc-sm8350.c42
-rw-r--r--drivers/clk/qcom/videocc-sm8450.c3
-rw-r--r--drivers/clk/qcom/videocc-sm8550.c3
-rw-r--r--drivers/clk/ralink/clk-mt7621.c3
-rw-r--r--drivers/clk/renesas/clk-emev2.c3
-rw-r--r--drivers/clk/renesas/r8a774a1-cpg-mssr.c3
-rw-r--r--drivers/clk/renesas/r8a774b1-cpg-mssr.c3
-rw-r--r--drivers/clk/renesas/r8a774c0-cpg-mssr.c1
-rw-r--r--drivers/clk/renesas/r8a774e1-cpg-mssr.c4
-rw-r--r--drivers/clk/renesas/r8a7795-cpg-mssr.c3
-rw-r--r--drivers/clk/renesas/r8a7796-cpg-mssr.c3
-rw-r--r--drivers/clk/renesas/r8a77965-cpg-mssr.c3
-rw-r--r--drivers/clk/renesas/r8a77990-cpg-mssr.c1
-rw-r--r--drivers/clk/renesas/r8a77995-cpg-mssr.c1
-rw-r--r--drivers/clk/renesas/r9a07g043-cpg.c3
-rw-r--r--drivers/clk/renesas/r9a09g011-cpg.c15
-rw-r--r--drivers/clk/renesas/rcar-gen3-cpg.c35
-rw-r--r--drivers/clk/renesas/rcar-gen3-cpg.h1
-rw-r--r--drivers/clk/renesas/rcar-usb2-clock-sel.c1
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.c1
-rw-r--r--drivers/clk/renesas/rzg2l-cpg.c11
-rw-r--r--drivers/clk/rockchip/clk-rk3568.c5
-rw-r--r--drivers/clk/rockchip/clk-rv1126.c61
-rw-r--r--drivers/clk/samsung/clk-exynos-arm64.c3
-rw-r--r--drivers/clk/samsung/clk-exynos-audss.c3
-rw-r--r--drivers/clk/samsung/clk-exynos3250.c11
-rw-r--r--drivers/clk/samsung/clk-exynos4.c5
-rw-r--r--drivers/clk/samsung/clk-exynos4412-isp.c5
-rw-r--r--drivers/clk/samsung/clk-exynos5-subcmu.c2
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c5
-rw-r--r--drivers/clk/samsung/clk-exynos5260.c41
-rw-r--r--drivers/clk/samsung/clk-exynos5410.c5
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c5
-rw-r--r--drivers/clk/samsung/clk-exynos5433.c65
-rw-r--r--drivers/clk/samsung/clk-exynos7885.c15
-rw-r--r--drivers/clk/samsung/clk-exynos850.c36
-rw-r--r--drivers/clk/samsung/clk-exynosautov9.c31
-rw-r--r--drivers/clk/samsung/clk-fsd.c2
-rw-r--r--drivers/clk/sifive/sifive-prci.c2
-rw-r--r--drivers/clk/socfpga/clk-agilex.c7
-rw-r--r--drivers/clk/socfpga/clk-s10.c3
-rw-r--r--drivers/clk/spear/spear1310_clock.c1
-rw-r--r--drivers/clk/spear/spear1340_clock.c1
-rw-r--r--drivers/clk/spear/spear3xx_clock.c2
-rw-r--r--drivers/clk/sprd/common.c2
-rw-r--r--drivers/clk/sprd/sc9860-clk.c2
-rw-r--r--drivers/clk/sprd/ums512-clk.c2
-rw-r--r--drivers/clk/starfive/Kconfig33
-rw-r--r--drivers/clk/starfive/Makefile4
-rw-r--r--drivers/clk/starfive/clk-starfive-jh7100-audio.c1
-rw-r--r--drivers/clk/starfive/clk-starfive-jh7110-isp.c232
-rw-r--r--drivers/clk/starfive/clk-starfive-jh7110-pll.c507
-rw-r--r--drivers/clk/starfive/clk-starfive-jh7110-stg.c173
-rw-r--r--drivers/clk/starfive/clk-starfive-jh7110-sys.c66
-rw-r--r--drivers/clk/starfive/clk-starfive-jh7110-vout.c239
-rw-r--r--drivers/clk/starfive/clk-starfive-jh7110.h6
-rw-r--r--drivers/clk/starfive/clk-starfive-jh71x0.c10
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun4i-a10.c2
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun50i-a64.c41
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c2
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun6i-rtc.c2
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-de2.c2
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-h3.c2
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-r.c2
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-v3s.c2
-rw-r--r--drivers/clk/sunxi-ng/ccu_common.c12
-rw-r--r--drivers/clk/sunxi-ng/ccu_common.h6
-rw-r--r--drivers/clk/sunxi-ng/ccu_div.h30
-rw-r--r--drivers/clk/sunxi-ng/ccu_mmc_timing.c2
-rw-r--r--drivers/clk/sunxi-ng/ccu_mux.c15
-rw-r--r--drivers/clk/sunxi-ng/ccu_mux.h38
-rw-r--r--drivers/clk/sunxi-ng/ccu_nkm.c55
-rw-r--r--drivers/clk/sunxi-ng/ccu_nm.c13
-rw-r--r--drivers/clk/sunxi-ng/ccu_nm.h48
-rw-r--r--drivers/clk/sunxi/clk-sun6i-apb0-gates.c1
-rw-r--r--drivers/clk/sunxi/clk-sun9i-mmc.c11
-rw-r--r--drivers/clk/tegra/clk-device.c2
-rw-r--r--drivers/clk/tegra/clk-tegra124-dfll-fcpu.c2
-rw-r--r--drivers/clk/tegra/clk-tegra20.c1
-rw-r--r--drivers/clk/tegra/clk-tegra30.c1
-rw-r--r--drivers/clk/tegra/clk.c8
-rw-r--r--drivers/clk/ti/adpll.c8
-rw-r--r--drivers/clk/ti/clk.c4
-rw-r--r--drivers/clk/ti/clkctrl.c9
-rw-r--r--drivers/clk/uniphier/clk-uniphier-core.c1
-rw-r--r--drivers/clk/xilinx/xlnx_vcu.c2
-rw-r--r--drivers/clk/zynqmp/clkc.c3
320 files changed, 10989 insertions, 6457 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 6b3b424addab..c30099866174 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -360,13 +360,6 @@ config COMMON_CLK_PXA
help
Support for the Marvell PXA SoC.
-config COMMON_CLK_OXNAS
- bool "Clock driver for the OXNAS SoC Family"
- depends on ARCH_OXNAS || COMPILE_TEST
- select MFD_SYSCON
- help
- Support for the OXNAS SoC Family clocks.
-
config COMMON_CLK_RS9_PCIE
tristate "Clock driver for Renesas 9-series PCIe clock generators"
depends on I2C
@@ -385,6 +378,15 @@ config COMMON_CLK_SI521XX
This driver supports the SkyWorks Si521xx PCIe clock generator
models Si52144/Si52146/Si52147.
+config COMMON_CLK_VC3
+ tristate "Clock driver for Renesas VersaClock 3 devices"
+ depends on I2C
+ depends on OF
+ select REGMAP_I2C
+ help
+ This driver supports the Renesas VersaClock 3 programmable clock
+ generators.
+
config COMMON_CLK_VC5
tristate "Clock driver for IDT VersaClock 5,6 devices"
depends on I2C
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 7cb000549b61..18969cbd4bb1 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -52,7 +52,6 @@ obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
obj-$(CONFIG_ARCH_NPCM7XX) += clk-npcm7xx.o
obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
-obj-$(CONFIG_COMMON_CLK_OXNAS) += clk-oxnas.o
obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o
obj-$(CONFIG_CLK_LS1028A_PLLDIG) += clk-plldig.o
obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
@@ -76,6 +75,7 @@ obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_COMMON_CLK_RS9_PCIE) += clk-renesas-pcie.o
obj-$(CONFIG_COMMON_CLK_SI521XX) += clk-si521xx.o
+obj-$(CONFIG_COMMON_CLK_VC3) += clk-versaclock3.o
obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o
obj-$(CONFIG_COMMON_CLK_VC7) += clk-versaclock7.o
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/actions/owl-common.c b/drivers/clk/actions/owl-common.c
index 4de97cc7cb54..c62024b7c737 100644
--- a/drivers/clk/actions/owl-common.c
+++ b/drivers/clk/actions/owl-common.c
@@ -8,8 +8,6 @@
// Copyright (c) 2018 Linaro Ltd.
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
@@ -43,10 +41,8 @@ int owl_clk_regmap_init(struct platform_device *pdev,
{
void __iomem *base;
struct regmap *regmap;
- struct resource *res;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- base = devm_ioremap_resource(&pdev->dev, res);
+ base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
diff --git a/drivers/clk/actions/owl-common.h b/drivers/clk/actions/owl-common.h
index c000a431471e..8fb65f3e82d7 100644
--- a/drivers/clk/actions/owl-common.h
+++ b/drivers/clk/actions/owl-common.h
@@ -12,10 +12,10 @@
#define _OWL_COMMON_H_
#include <linux/clk-provider.h>
-#include <linux/of_platform.h>
#include <linux/regmap.h>
struct device_node;
+struct platform_device;
struct owl_clk_common {
struct regmap *regmap;
diff --git a/drivers/clk/axs10x/pll_clock.c b/drivers/clk/axs10x/pll_clock.c
index 242bf5d75bab..6c7a2b62b406 100644
--- a/drivers/clk/axs10x/pll_clock.c
+++ b/drivers/clk/axs10x/pll_clock.c
@@ -12,10 +12,9 @@
#include <linux/err.h>
#include <linux/device.h>
#include <linux/io.h>
+#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/slab.h>
-#include <linux/of.h>
/* PLL registers addresses */
#define PLL_REG_IDIV 0x0
diff --git a/drivers/clk/baikal-t1/clk-ccu-div.c b/drivers/clk/baikal-t1/clk-ccu-div.c
index 0e772e034812..84555a00f950 100644
--- a/drivers/clk/baikal-t1/clk-ccu-div.c
+++ b/drivers/clk/baikal-t1/clk-ccu-div.c
@@ -20,7 +20,6 @@
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/of_platform.h>
#include <linux/ioport.h>
#include <linux/regmap.h>
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 8dc476ef5bf9..fb04734afc80 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -32,7 +32,7 @@
#include <linux/io.h>
#include <linux/math.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <dt-bindings/clock/bcm2835.h>
diff --git a/drivers/clk/bcm/clk-bcm63xx-gate.c b/drivers/clk/bcm/clk-bcm63xx-gate.c
index 0769f98767da..36c7b302e396 100644
--- a/drivers/clk/bcm/clk-bcm63xx-gate.c
+++ b/drivers/clk/bcm/clk-bcm63xx-gate.c
@@ -3,7 +3,6 @@
#include <linux/clk-provider.h>
#include <linux/init.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/bcm3368-clock.h>
diff --git a/drivers/clk/bcm/clk-sr.c b/drivers/clk/bcm/clk-sr.c
index 5db021685d6d..3b2cf397b789 100644
--- a/drivers/clk/bcm/clk-sr.c
+++ b/drivers/clk/bcm/clk-sr.c
@@ -5,7 +5,7 @@
#include <linux/err.h>
#include <linux/clk-provider.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/bcm-sr.h>
diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
index 411ff5fb2c07..ff84191d0fe8 100644
--- a/drivers/clk/clk-aspeed.c
+++ b/drivers/clk/clk-aspeed.c
@@ -4,8 +4,8 @@
#define pr_fmt(fmt) "clk-aspeed: " fmt
#include <linux/mfd/syscon.h>
+#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
@@ -701,6 +701,7 @@ static void __init aspeed_cc_init(struct device_node *np)
GFP_KERNEL);
if (!aspeed_clk_data)
return;
+ aspeed_clk_data->num = ASPEED_NUM_CLKS;
/*
* This way all clocks fetched before the platform device probes,
@@ -732,8 +733,6 @@ static void __init aspeed_cc_init(struct device_node *np)
aspeed_ast2500_cc(map);
else
pr_err("unknown platform, failed to add clocks\n");
-
- aspeed_clk_data->num = ASPEED_NUM_CLKS;
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);
if (ret)
pr_err("failed to add DT provider: %d\n", ret);
diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
index a094a2601a37..909c3137c428 100644
--- a/drivers/clk/clk-ast2600.c
+++ b/drivers/clk/clk-ast2600.c
@@ -5,8 +5,8 @@
#define pr_fmt(fmt) "clk-ast2600: " fmt
#include <linux/mfd/syscon.h>
+#include <linux/mod_devicetable.h>
#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
@@ -839,6 +839,7 @@ static void __init aspeed_g6_cc_init(struct device_node *np)
ASPEED_G6_NUM_CLKS), GFP_KERNEL);
if (!aspeed_g6_clk_data)
return;
+ aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
/*
* This way all clocks fetched before the platform device probes,
@@ -860,7 +861,6 @@ static void __init aspeed_g6_cc_init(struct device_node *np)
}
aspeed_g6_cc(map);
- aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
if (ret)
pr_err("failed to add DT provider: %d\n", ret);
diff --git a/drivers/clk/clk-axm5516.c b/drivers/clk/clk-axm5516.c
index 1afcfdf2e6f9..4a3462ee8f3e 100644
--- a/drivers/clk/clk-axm5516.c
+++ b/drivers/clk/clk-axm5516.c
@@ -541,14 +541,12 @@ MODULE_DEVICE_TABLE(of, axmclk_match_table);
static int axmclk_probe(struct platform_device *pdev)
{
void __iomem *base;
- struct resource *res;
int i, ret;
struct device *dev = &pdev->dev;
struct regmap *regmap;
size_t num_clks;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- base = devm_ioremap_resource(dev, res);
+ base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
diff --git a/drivers/clk/clk-bm1880.c b/drivers/clk/clk-bm1880.c
index 2a19e50fff68..002f7360b1c6 100644
--- a/drivers/clk/clk-bm1880.c
+++ b/drivers/clk/clk-bm1880.c
@@ -7,10 +7,10 @@
*/
#include <linux/clk-provider.h>
+#include <linux/io.h>
#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
@@ -876,16 +876,13 @@ static int bm1880_clk_probe(struct platform_device *pdev)
struct bm1880_clock_data *clk_data;
void __iomem *pll_base, *sys_base;
struct device *dev = &pdev->dev;
- struct resource *res;
int num_clks, i;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- pll_base = devm_ioremap_resource(&pdev->dev, res);
+ pll_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pll_base))
return PTR_ERR(pll_base);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- sys_base = devm_ioremap_resource(&pdev->dev, res);
+ sys_base = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(sys_base))
return PTR_ERR(sys_base);
diff --git a/drivers/clk/clk-cdce925.c b/drivers/clk/clk-cdce925.c
index 96ac90364847..cdee4958f26d 100644
--- a/drivers/clk/clk-cdce925.c
+++ b/drivers/clk/clk-cdce925.c
@@ -834,7 +834,7 @@ MODULE_DEVICE_TABLE(of, clk_cdce925_of_match);
static struct i2c_driver cdce925_driver = {
.driver = {
.name = "cdce925",
- .of_match_table = of_match_ptr(clk_cdce925_of_match),
+ .of_match_table = clk_cdce925_of_match,
},
.probe = cdce925_probe,
.id_table = cdce925_id,
diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c
index b82fee6a3d6f..35cb93ad298a 100644
--- a/drivers/clk/clk-cs2000-cp.c
+++ b/drivers/clk/clk-cs2000-cp.c
@@ -9,7 +9,7 @@
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/i2c.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/module.h>
#include <linux/regmap.h>
diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
index 29f0126cbd05..7cde328495e2 100644
--- a/drivers/clk/clk-en7523.c
+++ b/drivers/clk/clk-en7523.c
@@ -2,9 +2,8 @@
#include <linux/delay.h>
#include <linux/clk-provider.h>
+#include <linux/io.h>
#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/en7523-clk.h>
diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c
index ee5baf993ff2..cba45e07562d 100644
--- a/drivers/clk/clk-fsl-sai.c
+++ b/drivers/clk/clk-fsl-sai.c
@@ -33,14 +33,12 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
struct clk_parent_data pdata = { .index = 0 };
void __iomem *base;
struct clk_hw *hw;
- struct resource *res;
sai_clk = devm_kzalloc(dev, sizeof(*sai_clk), GFP_KERNEL);
if (!sai_clk)
return -ENOMEM;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- base = devm_ioremap_resource(dev, res);
+ base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
diff --git a/drivers/clk/clk-gemini.c b/drivers/clk/clk-gemini.c
index a23fa6d47ef1..ba0ff01bf4dc 100644
--- a/drivers/clk/clk-gemini.c
+++ b/drivers/clk/clk-gemini.c
@@ -276,7 +276,6 @@ static int gemini_clk_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
unsigned int mult, div;
- struct resource *res;
u32 val;
int ret;
int i;
@@ -286,8 +285,7 @@ static int gemini_clk_probe(struct platform_device *pdev)
return -ENOMEM;
/* Remap the system controller for the exclusive register */
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- base = devm_ioremap_resource(dev, res);
+ base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
@@ -404,6 +402,7 @@ static void __init gemini_cc_init(struct device_node *np)
GFP_KERNEL);
if (!gemini_clk_data)
return;
+ gemini_clk_data->num = GEMINI_NUM_CLKS;
/*
* This way all clock fetched before the platform device probes,
@@ -457,7 +456,6 @@ static void __init gemini_cc_init(struct device_node *np)
gemini_clk_data->hws[GEMINI_CLK_APB] = hw;
/* Register the clocks to be accessed by the device tree */
- gemini_clk_data->num = GEMINI_NUM_CLKS;
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, gemini_clk_data);
}
CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init);
diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c
index 38755a241ab7..5b114043771d 100644
--- a/drivers/clk/clk-gpio.c
+++ b/drivers/clk/clk-gpio.c
@@ -15,8 +15,8 @@
#include <linux/gpio/consumer.h>
#include <linux/err.h>
#include <linux/device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
-#include <linux/of_device.h>
/**
* DOC: basic gpio gated clock which can be enabled and disabled
diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
index 33b48ea5ea3d..5d2a90addf1a 100644
--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -12,7 +12,6 @@
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
@@ -304,7 +303,6 @@ static const struct clk_ops hsdk_pll_ops = {
static int hsdk_pll_clk_probe(struct platform_device *pdev)
{
int ret;
- struct resource *mem;
const char *parent_name;
unsigned int num_parents;
struct hsdk_pll_clk *pll_clk;
@@ -315,8 +313,7 @@ static int hsdk_pll_clk_probe(struct platform_device *pdev)
if (!pll_clk)
return -ENOMEM;
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- pll_clk->regs = devm_ioremap_resource(dev, mem);
+ pll_clk->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pll_clk->regs))
return PTR_ERR(pll_clk->regs);
diff --git a/drivers/clk/clk-k210.c b/drivers/clk/clk-k210.c
index 870adac5cdee..7b7329a907ab 100644
--- a/drivers/clk/clk-k210.c
+++ b/drivers/clk/clk-k210.c
@@ -11,7 +11,6 @@
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_clk.h>
-#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/clk-provider.h>
#include <linux/bitfield.h>
diff --git a/drivers/clk/clk-lmk04832.c b/drivers/clk/clk-lmk04832.c
index e22ac93e0c2f..99b271c1278a 100644
--- a/drivers/clk/clk-lmk04832.c
+++ b/drivers/clk/clk-lmk04832.c
@@ -134,6 +134,11 @@
/* 0x14b - 0x152 Holdover */
/* 0x153 - 0x15f PLL1 Configuration */
+#define LMK04832_REG_PLL1_LD 0x15f
+#define LMK04832_BIT_PLL1_LD_MUX GENMASK(7, 3)
+#define LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK 0x07
+#define LMK04832_BIT_PLL1_LD_TYPE GENMASK(2, 0)
+#define LMK04832_VAL_PLL1_LD_TYPE_OUT_PP 0x03
/* 0x160 - 0x16e PLL2 Configuration */
#define LMK04832_REG_PLL2_R_MSB 0x160
@@ -206,6 +211,7 @@ enum lmk04832_rdbk_type {
RDBK_CLKIN_SEL0,
RDBK_CLKIN_SEL1,
RDBK_RESET,
+ RDBK_PLL1_LD,
};
struct lmk_dclk {
@@ -1297,6 +1303,7 @@ static int lmk04832_register_clkout(struct lmk04832 *lmk, const int num)
sprintf(dclk_name, "lmk-dclk%02d_%02d", num, num + 1);
init.name = dclk_name;
parent_names[0] = clk_hw_get_name(&lmk->vco);
+ init.parent_names = parent_names;
init.ops = &lmk04832_dclk_ops;
init.flags = CLK_SET_RATE_PARENT;
init.num_parents = 1;
@@ -1345,6 +1352,10 @@ static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin)
{
int reg;
int ret;
+ int val = FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX,
+ LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) |
+ FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE,
+ LMK04832_VAL_CLKIN_SEL_TYPE_OUT);
dev_info(lmk->dev, "setting up 4-wire mode\n");
ret = regmap_write(lmk->regmap, LMK04832_REG_RST3W,
@@ -1362,15 +1373,18 @@ static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin)
case RDBK_RESET:
reg = LMK04832_REG_CLKIN_RST;
break;
+ case RDBK_PLL1_LD:
+ reg = LMK04832_REG_PLL1_LD;
+ val = FIELD_PREP(LMK04832_BIT_PLL1_LD_MUX,
+ LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK) |
+ FIELD_PREP(LMK04832_BIT_PLL1_LD_TYPE,
+ LMK04832_VAL_PLL1_LD_TYPE_OUT_PP);
+ break;
default:
return -EINVAL;
}
- return regmap_write(lmk->regmap, reg,
- FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX,
- LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) |
- FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE,
- LMK04832_VAL_CLKIN_SEL_TYPE_OUT));
+ return regmap_write(lmk->regmap, reg, val);
}
static int lmk04832_probe(struct spi_device *spi)
@@ -1504,21 +1518,21 @@ static int lmk04832_probe(struct spi_device *spi)
ret = clk_set_rate(lmk->vco.clk, lmk->vco_rate);
if (ret) {
dev_err(lmk->dev, "failed to set VCO rate\n");
- goto err_disable_vco;
+ goto err_disable_oscin;
}
}
ret = lmk04832_register_sclk(lmk);
if (ret) {
dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n");
- goto err_disable_vco;
+ goto err_disable_oscin;
}
for (i = 0; i < info->num_channels; i++) {
ret = lmk04832_register_clkout(lmk, i);
if (ret) {
dev_err(lmk->dev, "failed to register clk %d\n", i);
- goto err_disable_vco;
+ goto err_disable_oscin;
}
}
@@ -1527,16 +1541,13 @@ static int lmk04832_probe(struct spi_device *spi)
lmk->clk_data);
if (ret) {
dev_err(lmk->dev, "failed to add provider (%d)\n", ret);
- goto err_disable_vco;
+ goto err_disable_oscin;
}
spi_set_drvdata(spi, lmk);
return 0;
-err_disable_vco:
- clk_disable_unprepare(lmk->vco.clk);
-
err_disable_oscin:
clk_disable_unprepare(lmk->oscin);
diff --git a/drivers/clk/clk-milbeaut.c b/drivers/clk/clk-milbeaut.c
index 050fd4fb588f..18c20aff45f7 100644
--- a/drivers/clk/clk-milbeaut.c
+++ b/drivers/clk/clk-milbeaut.c
@@ -618,6 +618,7 @@ static void __init m10v_cc_init(struct device_node *np)
if (!m10v_clk_data)
return;
+ m10v_clk_data->num = M10V_NUM_CLKS;
base = of_iomap(np, 0);
if (!base) {
@@ -654,8 +655,6 @@ static void __init m10v_cc_init(struct device_node *np)
base + CLKSEL(1), 0, 3, 0, rclk_table,
&m10v_crglock, NULL);
m10v_clk_data->hws[M10V_RCLK_ID] = hw;
-
- m10v_clk_data->num = M10V_NUM_CLKS;
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, m10v_clk_data);
}
CLK_OF_DECLARE_DRIVER(m10v_cc, "socionext,milbeaut-m10v-ccu", m10v_cc_init);
diff --git a/drivers/clk/clk-oxnas.c b/drivers/clk/clk-oxnas.c
deleted file mode 100644
index 584e293156ad..000000000000
--- a/drivers/clk/clk-oxnas.c
+++ /dev/null
@@ -1,251 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010 Broadcom
- * Copyright (C) 2012 Stephen Warren
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/stringify.h>
-#include <linux/regmap.h>
-#include <linux/mfd/syscon.h>
-
-#include <dt-bindings/clock/oxsemi,ox810se.h>
-#include <dt-bindings/clock/oxsemi,ox820.h>
-
-/* Standard regmap gate clocks */
-struct clk_oxnas_gate {
- struct clk_hw hw;
- unsigned int bit;
- struct regmap *regmap;
-};
-
-struct oxnas_stdclk_data {
- struct clk_hw_onecell_data *onecell_data;
- struct clk_oxnas_gate **gates;
- unsigned int ngates;
- struct clk_oxnas_pll **plls;
- unsigned int nplls;
-};
-
-/* Regmap offsets */
-#define CLK_STAT_REGOFFSET 0x24
-#define CLK_SET_REGOFFSET 0x2c
-#define CLK_CLR_REGOFFSET 0x30
-
-static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw)
-{
- return container_of(hw, struct clk_oxnas_gate, hw);
-}
-
-static int oxnas_clk_gate_is_enabled(struct clk_hw *hw)
-{
- struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
- int ret;
- unsigned int val;
-
- ret = regmap_read(std->regmap, CLK_STAT_REGOFFSET, &val);
- if (ret < 0)
- return ret;
-
- return val & BIT(std->bit);
-}
-
-static int oxnas_clk_gate_enable(struct clk_hw *hw)
-{
- struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
-
- regmap_write(std->regmap, CLK_SET_REGOFFSET, BIT(std->bit));
-
- return 0;
-}
-
-static void oxnas_clk_gate_disable(struct clk_hw *hw)
-{
- struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
-
- regmap_write(std->regmap, CLK_CLR_REGOFFSET, BIT(std->bit));
-}
-
-static const struct clk_ops oxnas_clk_gate_ops = {
- .enable = oxnas_clk_gate_enable,
- .disable = oxnas_clk_gate_disable,
- .is_enabled = oxnas_clk_gate_is_enabled,
-};
-
-static const char *const osc_parents[] = {
- "oscillator",
-};
-
-static const char *const eth_parents[] = {
- "gmacclk",
-};
-
-#define OXNAS_GATE(_name, _bit, _parents) \
-struct clk_oxnas_gate _name = { \
- .bit = (_bit), \
- .hw.init = &(struct clk_init_data) { \
- .name = #_name, \
- .ops = &oxnas_clk_gate_ops, \
- .parent_names = _parents, \
- .num_parents = ARRAY_SIZE(_parents), \
- .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
- }, \
-}
-
-static OXNAS_GATE(ox810se_leon, 0, osc_parents);
-static OXNAS_GATE(ox810se_dma_sgdma, 1, osc_parents);
-static OXNAS_GATE(ox810se_cipher, 2, osc_parents);
-static OXNAS_GATE(ox810se_sata, 4, osc_parents);
-static OXNAS_GATE(ox810se_audio, 5, osc_parents);
-static OXNAS_GATE(ox810se_usbmph, 6, osc_parents);
-static OXNAS_GATE(ox810se_etha, 7, eth_parents);
-static OXNAS_GATE(ox810se_pciea, 8, osc_parents);
-static OXNAS_GATE(ox810se_nand, 9, osc_parents);
-
-static struct clk_oxnas_gate *ox810se_gates[] = {
- &ox810se_leon,
- &ox810se_dma_sgdma,
- &ox810se_cipher,
- &ox810se_sata,
- &ox810se_audio,
- &ox810se_usbmph,
- &ox810se_etha,
- &ox810se_pciea,
- &ox810se_nand,
-};
-
-static OXNAS_GATE(ox820_leon, 0, osc_parents);
-static OXNAS_GATE(ox820_dma_sgdma, 1, osc_parents);
-static OXNAS_GATE(ox820_cipher, 2, osc_parents);
-static OXNAS_GATE(ox820_sd, 3, osc_parents);
-static OXNAS_GATE(ox820_sata, 4, osc_parents);
-static OXNAS_GATE(ox820_audio, 5, osc_parents);
-static OXNAS_GATE(ox820_usbmph, 6, osc_parents);
-static OXNAS_GATE(ox820_etha, 7, eth_parents);
-static OXNAS_GATE(ox820_pciea, 8, osc_parents);
-static OXNAS_GATE(ox820_nand, 9, osc_parents);
-static OXNAS_GATE(ox820_ethb, 10, eth_parents);
-static OXNAS_GATE(ox820_pcieb, 11, osc_parents);
-static OXNAS_GATE(ox820_ref600, 12, osc_parents);
-static OXNAS_GATE(ox820_usbdev, 13, osc_parents);
-
-static struct clk_oxnas_gate *ox820_gates[] = {
- &ox820_leon,
- &ox820_dma_sgdma,
- &ox820_cipher,
- &ox820_sd,
- &ox820_sata,
- &ox820_audio,
- &ox820_usbmph,
- &ox820_etha,
- &ox820_pciea,
- &ox820_nand,
- &ox820_etha,
- &ox820_pciea,
- &ox820_ref600,
- &ox820_usbdev,
-};
-
-static struct clk_hw_onecell_data ox810se_hw_onecell_data = {
- .hws = {
- [CLK_810_LEON] = &ox810se_leon.hw,
- [CLK_810_DMA_SGDMA] = &ox810se_dma_sgdma.hw,
- [CLK_810_CIPHER] = &ox810se_cipher.hw,
- [CLK_810_SATA] = &ox810se_sata.hw,
- [CLK_810_AUDIO] = &ox810se_audio.hw,
- [CLK_810_USBMPH] = &ox810se_usbmph.hw,
- [CLK_810_ETHA] = &ox810se_etha.hw,
- [CLK_810_PCIEA] = &ox810se_pciea.hw,
- [CLK_810_NAND] = &ox810se_nand.hw,
- },
- .num = ARRAY_SIZE(ox810se_gates),
-};
-
-static struct clk_hw_onecell_data ox820_hw_onecell_data = {
- .hws = {
- [CLK_820_LEON] = &ox820_leon.hw,
- [CLK_820_DMA_SGDMA] = &ox820_dma_sgdma.hw,
- [CLK_820_CIPHER] = &ox820_cipher.hw,
- [CLK_820_SD] = &ox820_sd.hw,
- [CLK_820_SATA] = &ox820_sata.hw,
- [CLK_820_AUDIO] = &ox820_audio.hw,
- [CLK_820_USBMPH] = &ox820_usbmph.hw,
- [CLK_820_ETHA] = &ox820_etha.hw,
- [CLK_820_PCIEA] = &ox820_pciea.hw,
- [CLK_820_NAND] = &ox820_nand.hw,
- [CLK_820_ETHB] = &ox820_ethb.hw,
- [CLK_820_PCIEB] = &ox820_pcieb.hw,
- [CLK_820_REF600] = &ox820_ref600.hw,
- [CLK_820_USBDEV] = &ox820_usbdev.hw,
- },
- .num = ARRAY_SIZE(ox820_gates),
-};
-
-static struct oxnas_stdclk_data ox810se_stdclk_data = {
- .onecell_data = &ox810se_hw_onecell_data,
- .gates = ox810se_gates,
- .ngates = ARRAY_SIZE(ox810se_gates),
-};
-
-static struct oxnas_stdclk_data ox820_stdclk_data = {
- .onecell_data = &ox820_hw_onecell_data,
- .gates = ox820_gates,
- .ngates = ARRAY_SIZE(ox820_gates),
-};
-
-static const struct of_device_id oxnas_stdclk_dt_ids[] = {
- { .compatible = "oxsemi,ox810se-stdclk", &ox810se_stdclk_data },
- { .compatible = "oxsemi,ox820-stdclk", &ox820_stdclk_data },
- { }
-};
-
-static int oxnas_stdclk_probe(struct platform_device *pdev)
-{
- struct device_node *np = pdev->dev.of_node, *parent_np;
- const struct oxnas_stdclk_data *data;
- struct regmap *regmap;
- int ret;
- int i;
-
- data = of_device_get_match_data(&pdev->dev);
-
- parent_np = of_get_parent(np);
- regmap = syscon_node_to_regmap(parent_np);
- of_node_put(parent_np);
- if (IS_ERR(regmap)) {
- dev_err(&pdev->dev, "failed to have parent regmap\n");
- return PTR_ERR(regmap);
- }
-
- for (i = 0 ; i < data->ngates ; ++i)
- data->gates[i]->regmap = regmap;
-
- for (i = 0; i < data->onecell_data->num; i++) {
- if (!data->onecell_data->hws[i])
- continue;
-
- ret = devm_clk_hw_register(&pdev->dev,
- data->onecell_data->hws[i]);
- if (ret)
- return ret;
- }
-
- return of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
- data->onecell_data);
-}
-
-static struct platform_driver oxnas_stdclk_driver = {
- .probe = oxnas_stdclk_probe,
- .driver = {
- .name = "oxnas-stdclk",
- .suppress_bind_attrs = true,
- .of_match_table = oxnas_stdclk_dt_ids,
- },
-};
-builtin_platform_driver(oxnas_stdclk_driver);
diff --git a/drivers/clk/clk-palmas.c b/drivers/clk/clk-palmas.c
index 74a241b1e1f4..5efb10776ae5 100644
--- a/drivers/clk/clk-palmas.c
+++ b/drivers/clk/clk-palmas.c
@@ -14,7 +14,6 @@
#include <linux/mfd/palmas.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
diff --git a/drivers/clk/clk-plldig.c b/drivers/clk/clk-plldig.c
index 25020164b89e..14357f3e4561 100644
--- a/drivers/clk/clk-plldig.c
+++ b/drivers/clk/clk-plldig.c
@@ -12,8 +12,6 @@
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/bitfield.h>
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index e3386fd98c5e..4dcde305944c 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -17,8 +17,8 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_address.h>
-#include <linux/of_platform.h>
#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/slab.h>
#define PLL_DIV1 0
diff --git a/drivers/clk/clk-scpi.c b/drivers/clk/clk-scpi.c
index 3fb4003453ee..108b697bd317 100644
--- a/drivers/clk/clk-scpi.c
+++ b/drivers/clk/clk-scpi.c
@@ -10,7 +10,6 @@
#include <linux/err.h>
#include <linux/of.h>
#include <linux/module.h>
-#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/scpi_protocol.h>
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index 31c3c8a71f12..00fb9b09e030 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -21,7 +21,7 @@
#include <linux/errno.h>
#include <linux/rational.h>
#include <linux/i2c.h>
-#include <linux/of_platform.h>
+#include <linux/of.h>
#include <linux/platform_data/si5351.h>
#include <linux/regmap.h>
#include <linux/slab.h>
diff --git a/drivers/clk/clk-sp7021.c b/drivers/clk/clk-sp7021.c
index 11d22043ddd7..01d3c4c7b0b2 100644
--- a/drivers/clk/clk-sp7021.c
+++ b/drivers/clk/clk-sp7021.c
@@ -621,6 +621,7 @@ static int sp7021_clk_probe(struct platform_device *pdev)
GFP_KERNEL);
if (!clk_data)
return -ENOMEM;
+ clk_data->num = CLK_MAX;
hws = clk_data->hws;
pd_ext.index = 0;
@@ -688,8 +689,6 @@ static int sp7021_clk_probe(struct platform_device *pdev)
return PTR_ERR(hws[i]);
}
- clk_data->num = CLK_MAX;
-
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
}
diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c
new file mode 100644
index 000000000000..7ab2447bd203
--- /dev/null
+++ b/drivers/clk/clk-versaclock3.c
@@ -0,0 +1,1143 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for Renesas Versaclock 3
+ *
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/i2c.h>
+#include <linux/limits.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+
+#define NUM_CONFIG_REGISTERS 37
+
+#define VC3_GENERAL_CTR 0x0
+#define VC3_GENERAL_CTR_DIV1_SRC_SEL BIT(3)
+#define VC3_GENERAL_CTR_PLL3_REFIN_SEL BIT(2)
+
+#define VC3_PLL3_M_DIVIDER 0x3
+#define VC3_PLL3_M_DIV1 BIT(7)
+#define VC3_PLL3_M_DIV2 BIT(6)
+#define VC3_PLL3_M_DIV(n) ((n) & GENMASK(5, 0))
+
+#define VC3_PLL3_N_DIVIDER 0x4
+#define VC3_PLL3_LOOP_FILTER_N_DIV_MSB 0x5
+
+#define VC3_PLL3_CHARGE_PUMP_CTRL 0x6
+#define VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL BIT(7)
+
+#define VC3_PLL1_CTRL_OUTDIV5 0x7
+#define VC3_PLL1_CTRL_OUTDIV5_PLL1_MDIV_DOUBLER BIT(7)
+
+#define VC3_PLL1_M_DIVIDER 0x8
+#define VC3_PLL1_M_DIV1 BIT(7)
+#define VC3_PLL1_M_DIV2 BIT(6)
+#define VC3_PLL1_M_DIV(n) ((n) & GENMASK(5, 0))
+
+#define VC3_PLL1_VCO_N_DIVIDER 0x9
+#define VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0x0a
+
+#define VC3_OUT_DIV1_DIV2_CTRL 0xf
+
+#define VC3_PLL2_FB_INT_DIV_MSB 0x10
+#define VC3_PLL2_FB_INT_DIV_LSB 0x11
+#define VC3_PLL2_FB_FRC_DIV_MSB 0x12
+#define VC3_PLL2_FB_FRC_DIV_LSB 0x13
+
+#define VC3_PLL2_M_DIVIDER 0x1a
+#define VC3_PLL2_MDIV_DOUBLER BIT(7)
+#define VC3_PLL2_M_DIV1 BIT(6)
+#define VC3_PLL2_M_DIV2 BIT(5)
+#define VC3_PLL2_M_DIV(n) ((n) & GENMASK(4, 0))
+
+#define VC3_OUT_DIV3_DIV4_CTRL 0x1b
+
+#define VC3_PLL_OP_CTRL 0x1c
+#define VC3_PLL_OP_CTRL_PLL2_REFIN_SEL 6
+
+#define VC3_OUTPUT_CTR 0x1d
+#define VC3_OUTPUT_CTR_DIV4_SRC_SEL BIT(3)
+
+#define VC3_SE2_CTRL_REG0 0x1f
+#define VC3_SE2_CTRL_REG0_SE2_CLK_SEL BIT(6)
+
+#define VC3_SE3_DIFF1_CTRL_REG 0x21
+#define VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL BIT(6)
+
+#define VC3_DIFF1_CTRL_REG 0x22
+#define VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL BIT(7)
+
+#define VC3_DIFF2_CTRL_REG 0x23
+#define VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL BIT(7)
+
+#define VC3_SE1_DIV4_CTRL 0x24
+#define VC3_SE1_DIV4_CTRL_SE1_CLK_SEL BIT(3)
+
+#define VC3_PLL1_VCO_MIN 300000000UL
+#define VC3_PLL1_VCO_MAX 600000000UL
+
+#define VC3_PLL2_VCO_MIN 400000000UL
+#define VC3_PLL2_VCO_MAX 1200000000UL
+
+#define VC3_PLL3_VCO_MIN 300000000UL
+#define VC3_PLL3_VCO_MAX 800000000UL
+
+#define VC3_2_POW_16 (U16_MAX + 1)
+#define VC3_DIV_MASK(width) ((1 << (width)) - 1)
+
+enum vc3_pfd_mux {
+ VC3_PFD2_MUX,
+ VC3_PFD3_MUX,
+};
+
+enum vc3_pfd {
+ VC3_PFD1,
+ VC3_PFD2,
+ VC3_PFD3,
+};
+
+enum vc3_pll {
+ VC3_PLL1,
+ VC3_PLL2,
+ VC3_PLL3,
+};
+
+enum vc3_div_mux {
+ VC3_DIV1_MUX,
+ VC3_DIV3_MUX,
+ VC3_DIV4_MUX,
+};
+
+enum vc3_div {
+ VC3_DIV1,
+ VC3_DIV2,
+ VC3_DIV3,
+ VC3_DIV4,
+ VC3_DIV5,
+};
+
+enum vc3_clk_mux {
+ VC3_DIFF2_MUX,
+ VC3_DIFF1_MUX,
+ VC3_SE3_MUX,
+ VC3_SE2_MUX,
+ VC3_SE1_MUX,
+};
+
+enum vc3_clk {
+ VC3_DIFF2,
+ VC3_DIFF1,
+ VC3_SE3,
+ VC3_SE2,
+ VC3_SE1,
+ VC3_REF,
+};
+
+struct vc3_clk_data {
+ u8 offs;
+ u8 bitmsk;
+};
+
+struct vc3_pfd_data {
+ u8 num;
+ u8 offs;
+ u8 mdiv1_bitmsk;
+ u8 mdiv2_bitmsk;
+};
+
+struct vc3_pll_data {
+ u8 num;
+ u8 int_div_msb_offs;
+ u8 int_div_lsb_offs;
+ unsigned long vco_min;
+ unsigned long vco_max;
+};
+
+struct vc3_div_data {
+ u8 offs;
+ const struct clk_div_table *table;
+ u8 shift;
+ u8 width;
+ u8 flags;
+};
+
+struct vc3_hw_data {
+ struct clk_hw hw;
+ struct regmap *regmap;
+ const void *data;
+
+ u32 div_int;
+ u32 div_frc;
+};
+
+static const struct clk_div_table div1_divs[] = {
+ { .val = 0, .div = 1, }, { .val = 1, .div = 4, },
+ { .val = 2, .div = 5, }, { .val = 3, .div = 6, },
+ { .val = 4, .div = 2, }, { .val = 5, .div = 8, },
+ { .val = 6, .div = 10, }, { .val = 7, .div = 12, },
+ { .val = 8, .div = 4, }, { .val = 9, .div = 16, },
+ { .val = 10, .div = 20, }, { .val = 11, .div = 24, },
+ { .val = 12, .div = 8, }, { .val = 13, .div = 32, },
+ { .val = 14, .div = 40, }, { .val = 15, .div = 48, },
+ {}
+};
+
+static const struct clk_div_table div245_divs[] = {
+ { .val = 0, .div = 1, }, { .val = 1, .div = 3, },
+ { .val = 2, .div = 5, }, { .val = 3, .div = 10, },
+ { .val = 4, .div = 2, }, { .val = 5, .div = 6, },
+ { .val = 6, .div = 10, }, { .val = 7, .div = 20, },
+ { .val = 8, .div = 4, }, { .val = 9, .div = 12, },
+ { .val = 10, .div = 20, }, { .val = 11, .div = 40, },
+ { .val = 12, .div = 5, }, { .val = 13, .div = 15, },
+ { .val = 14, .div = 25, }, { .val = 15, .div = 50, },
+ {}
+};
+
+static const struct clk_div_table div3_divs[] = {
+ { .val = 0, .div = 1, }, { .val = 1, .div = 3, },
+ { .val = 2, .div = 5, }, { .val = 3, .div = 10, },
+ { .val = 4, .div = 2, }, { .val = 5, .div = 6, },
+ { .val = 6, .div = 10, }, { .val = 7, .div = 20, },
+ { .val = 8, .div = 4, }, { .val = 9, .div = 12, },
+ { .val = 10, .div = 20, }, { .val = 11, .div = 40, },
+ { .val = 12, .div = 8, }, { .val = 13, .div = 24, },
+ { .val = 14, .div = 40, }, { .val = 15, .div = 80, },
+ {}
+};
+
+static struct clk_hw *clk_out[6];
+
+static unsigned char vc3_pfd_mux_get_parent(struct clk_hw *hw)
+{
+ struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_clk_data *pfd_mux = vc3->data;
+ u32 src;
+
+ regmap_read(vc3->regmap, pfd_mux->offs, &src);
+
+ return !!(src & pfd_mux->bitmsk);
+}
+
+static int vc3_pfd_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_clk_data *pfd_mux = vc3->data;
+
+ regmap_update_bits(vc3->regmap, pfd_mux->offs, pfd_mux->bitmsk,
+ index ? pfd_mux->bitmsk : 0);
+ return 0;
+}
+
+static const struct clk_ops vc3_pfd_mux_ops = {
+ .determine_rate = clk_hw_determine_rate_no_reparent,
+ .set_parent = vc3_pfd_mux_set_parent,
+ .get_parent = vc3_pfd_mux_get_parent,
+};
+
+static unsigned long vc3_pfd_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_pfd_data *pfd = vc3->data;
+ unsigned int prediv, premul;
+ unsigned long rate;
+ u8 mdiv;
+
+ regmap_read(vc3->regmap, pfd->offs, &prediv);
+ if (pfd->num == VC3_PFD1) {
+ /* The bypass_prediv is set, PLL fed from Ref_in directly. */
+ if (prediv & pfd->mdiv1_bitmsk) {
+ /* check doubler is set or not */
+ regmap_read(vc3->regmap, VC3_PLL1_CTRL_OUTDIV5, &premul);
+ if (premul & VC3_PLL1_CTRL_OUTDIV5_PLL1_MDIV_DOUBLER)
+ parent_rate *= 2;
+ return parent_rate;
+ }
+ mdiv = VC3_PLL1_M_DIV(prediv);
+ } else if (pfd->num == VC3_PFD2) {
+ /* The bypass_prediv is set, PLL fed from Ref_in directly. */
+ if (prediv & pfd->mdiv1_bitmsk) {
+ regmap_read(vc3->regmap, VC3_PLL2_M_DIVIDER, &premul);
+ /* check doubler is set or not */
+ if (premul & VC3_PLL2_MDIV_DOUBLER)
+ parent_rate *= 2;
+ return parent_rate;
+ }
+
+ mdiv = VC3_PLL2_M_DIV(prediv);
+ } else {
+ /* The bypass_prediv is set, PLL fed from Ref_in directly. */
+ if (prediv & pfd->mdiv1_bitmsk)
+ return parent_rate;
+
+ mdiv = VC3_PLL3_M_DIV(prediv);
+ }
+
+ if (prediv & pfd->mdiv2_bitmsk)
+ rate = parent_rate / 2;
+ else
+ rate = parent_rate / mdiv;
+
+ return rate;
+}
+
+static long vc3_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_pfd_data *pfd = vc3->data;
+ unsigned long idiv;
+
+ /* PLL cannot operate with input clock above 50 MHz. */
+ if (rate > 50000000)
+ return -EINVAL;
+
+ /* CLKIN within range of PLL input, feed directly to PLL. */
+ if (*parent_rate <= 50000000)
+ return *parent_rate;
+
+ idiv = DIV_ROUND_UP(*parent_rate, rate);
+ if (pfd->num == VC3_PFD1 || pfd->num == VC3_PFD3) {
+ if (idiv > 63)
+ return -EINVAL;
+ } else {
+ if (idiv > 31)
+ return -EINVAL;
+ }
+
+ return *parent_rate / idiv;
+}
+
+static int vc3_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_pfd_data *pfd = vc3->data;
+ unsigned long idiv;
+ u8 div;
+
+ /* CLKIN within range of PLL input, feed directly to PLL. */
+ if (parent_rate <= 50000000) {
+ regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv1_bitmsk,
+ pfd->mdiv1_bitmsk);
+ regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv2_bitmsk, 0);
+ return 0;
+ }
+
+ idiv = DIV_ROUND_UP(parent_rate, rate);
+ /* We have dedicated div-2 predivider. */
+ if (idiv == 2) {
+ regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv2_bitmsk,
+ pfd->mdiv2_bitmsk);
+ regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv1_bitmsk, 0);
+ } else {
+ if (pfd->num == VC3_PFD1)
+ div = VC3_PLL1_M_DIV(idiv);
+ else if (pfd->num == VC3_PFD2)
+ div = VC3_PLL2_M_DIV(idiv);
+ else
+ div = VC3_PLL3_M_DIV(idiv);
+
+ regmap_write(vc3->regmap, pfd->offs, div);
+ }
+
+ return 0;
+}
+
+static const struct clk_ops vc3_pfd_ops = {
+ .recalc_rate = vc3_pfd_recalc_rate,
+ .round_rate = vc3_pfd_round_rate,
+ .set_rate = vc3_pfd_set_rate,
+};
+
+static unsigned long vc3_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_pll_data *pll = vc3->data;
+ u32 div_int, div_frc, val;
+ unsigned long rate;
+
+ regmap_read(vc3->regmap, pll->int_div_msb_offs, &val);
+ div_int = (val & GENMASK(2, 0)) << 8;
+ regmap_read(vc3->regmap, pll->int_div_lsb_offs, &val);
+ div_int |= val;
+
+ if (pll->num == VC3_PLL2) {
+ regmap_read(vc3->regmap, VC3_PLL2_FB_FRC_DIV_MSB, &val);
+ div_frc = val << 8;
+ regmap_read(vc3->regmap, VC3_PLL2_FB_FRC_DIV_LSB, &val);
+ div_frc |= val;
+ rate = (parent_rate *
+ (div_int * VC3_2_POW_16 + div_frc) / VC3_2_POW_16);
+ } else {
+ rate = parent_rate * div_int;
+ }
+
+ return rate;
+}
+
+static long vc3_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_pll_data *pll = vc3->data;
+ u64 div_frc;
+
+ if (rate < pll->vco_min)
+ rate = pll->vco_min;
+ if (rate > pll->vco_max)
+ rate = pll->vco_max;
+
+ vc3->div_int = rate / *parent_rate;
+
+ if (pll->num == VC3_PLL2) {
+ if (vc3->div_int > 0x7ff)
+ rate = *parent_rate * 0x7ff;
+
+ /* Determine best fractional part, which is 16 bit wide */
+ div_frc = rate % *parent_rate;
+ div_frc *= BIT(16) - 1;
+ do_div(div_frc, *parent_rate);
+
+ vc3->div_frc = (u32)div_frc;
+ rate = (*parent_rate *
+ (vc3->div_int * VC3_2_POW_16 + div_frc) / VC3_2_POW_16);
+ } else {
+ rate = *parent_rate * vc3->div_int;
+ }
+
+ return rate;
+}
+
+static int vc3_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_pll_data *pll = vc3->data;
+ u32 val;
+
+ regmap_read(vc3->regmap, pll->int_div_msb_offs, &val);
+ val = (val & 0xf8) | ((vc3->div_int >> 8) & 0x7);
+ regmap_write(vc3->regmap, pll->int_div_msb_offs, val);
+ regmap_write(vc3->regmap, pll->int_div_lsb_offs, vc3->div_int & 0xff);
+
+ if (pll->num == VC3_PLL2) {
+ regmap_write(vc3->regmap, VC3_PLL2_FB_FRC_DIV_MSB,
+ vc3->div_frc >> 8);
+ regmap_write(vc3->regmap, VC3_PLL2_FB_FRC_DIV_LSB,
+ vc3->div_frc & 0xff);
+ }
+
+ return 0;
+}
+
+static const struct clk_ops vc3_pll_ops = {
+ .recalc_rate = vc3_pll_recalc_rate,
+ .round_rate = vc3_pll_round_rate,
+ .set_rate = vc3_pll_set_rate,
+};
+
+static unsigned char vc3_div_mux_get_parent(struct clk_hw *hw)
+{
+ struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_clk_data *div_mux = vc3->data;
+ u32 src;
+
+ regmap_read(vc3->regmap, div_mux->offs, &src);
+
+ return !!(src & div_mux->bitmsk);
+}
+
+static int vc3_div_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_clk_data *div_mux = vc3->data;
+
+ regmap_update_bits(vc3->regmap, div_mux->offs, div_mux->bitmsk,
+ index ? div_mux->bitmsk : 0);
+
+ return 0;
+}
+
+static const struct clk_ops vc3_div_mux_ops = {
+ .determine_rate = clk_hw_determine_rate_no_reparent,
+ .set_parent = vc3_div_mux_set_parent,
+ .get_parent = vc3_div_mux_get_parent,
+};
+
+static unsigned int vc3_get_div(const struct clk_div_table *table,
+ unsigned int val, unsigned long flag)
+{
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->val == val)
+ return clkt->div;
+
+ return 0;
+}
+
+static unsigned long vc3_div_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_div_data *div_data = vc3->data;
+ unsigned int val;
+
+ regmap_read(vc3->regmap, div_data->offs, &val);
+ val >>= div_data->shift;
+ val &= VC3_DIV_MASK(div_data->width);
+
+ return divider_recalc_rate(hw, parent_rate, val, div_data->table,
+ div_data->flags, div_data->width);
+}
+
+static long vc3_div_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_div_data *div_data = vc3->data;
+ unsigned int bestdiv;
+
+ /* if read only, just return current value */
+ if (div_data->flags & CLK_DIVIDER_READ_ONLY) {
+ regmap_read(vc3->regmap, div_data->offs, &bestdiv);
+ bestdiv >>= div_data->shift;
+ bestdiv &= VC3_DIV_MASK(div_data->width);
+ bestdiv = vc3_get_div(div_data->table, bestdiv, div_data->flags);
+ return DIV_ROUND_UP(*parent_rate, bestdiv);
+ }
+
+ return divider_round_rate(hw, rate, parent_rate, div_data->table,
+ div_data->width, div_data->flags);
+}
+
+static int vc3_div_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_div_data *div_data = vc3->data;
+ unsigned int value;
+
+ value = divider_get_val(rate, parent_rate, div_data->table,
+ div_data->width, div_data->flags);
+ regmap_update_bits(vc3->regmap, div_data->offs,
+ VC3_DIV_MASK(div_data->width) << div_data->shift,
+ value << div_data->shift);
+ return 0;
+}
+
+static const struct clk_ops vc3_div_ops = {
+ .recalc_rate = vc3_div_recalc_rate,
+ .round_rate = vc3_div_round_rate,
+ .set_rate = vc3_div_set_rate,
+};
+
+static int vc3_clk_mux_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ int ret;
+ int frc;
+
+ ret = clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT);
+ if (ret) {
+ /* The below check is equivalent to (best_parent_rate/rate) */
+ if (req->best_parent_rate >= req->rate) {
+ frc = DIV_ROUND_CLOSEST_ULL(req->best_parent_rate,
+ req->rate);
+ req->rate *= frc;
+ return clk_mux_determine_rate_flags(hw, req,
+ CLK_SET_RATE_PARENT);
+ }
+ ret = 0;
+ }
+
+ return ret;
+}
+
+static unsigned char vc3_clk_mux_get_parent(struct clk_hw *hw)
+{
+ struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_clk_data *clk_mux = vc3->data;
+ u32 val;
+
+ regmap_read(vc3->regmap, clk_mux->offs, &val);
+
+ return !!(val & clk_mux->bitmsk);
+}
+
+static int vc3_clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
+ const struct vc3_clk_data *clk_mux = vc3->data;
+
+ regmap_update_bits(vc3->regmap, clk_mux->offs,
+ clk_mux->bitmsk, index ? clk_mux->bitmsk : 0);
+ return 0;
+}
+
+static const struct clk_ops vc3_clk_mux_ops = {
+ .determine_rate = vc3_clk_mux_determine_rate,
+ .set_parent = vc3_clk_mux_set_parent,
+ .get_parent = vc3_clk_mux_get_parent,
+};
+
+static bool vc3_regmap_is_writeable(struct device *dev, unsigned int reg)
+{
+ return true;
+}
+
+static const struct regmap_config vc3_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .cache_type = REGCACHE_RBTREE,
+ .max_register = 0x24,
+ .writeable_reg = vc3_regmap_is_writeable,
+};
+
+static struct vc3_hw_data clk_div[5];
+
+static const struct clk_parent_data pfd_mux_parent_data[] = {
+ { .index = 0, },
+ { .hw = &clk_div[VC3_DIV2].hw }
+};
+
+static struct vc3_hw_data clk_pfd_mux[] = {
+ [VC3_PFD2_MUX] = {
+ .data = &(struct vc3_clk_data) {
+ .offs = VC3_PLL_OP_CTRL,
+ .bitmsk = BIT(VC3_PLL_OP_CTRL_PLL2_REFIN_SEL)
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pfd2_mux",
+ .ops = &vc3_pfd_mux_ops,
+ .parent_data = pfd_mux_parent_data,
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
+ }
+ },
+ [VC3_PFD3_MUX] = {
+ .data = &(struct vc3_clk_data) {
+ .offs = VC3_GENERAL_CTR,
+ .bitmsk = BIT(VC3_GENERAL_CTR_PLL3_REFIN_SEL)
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pfd3_mux",
+ .ops = &vc3_pfd_mux_ops,
+ .parent_data = pfd_mux_parent_data,
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
+ }
+ }
+};
+
+static struct vc3_hw_data clk_pfd[] = {
+ [VC3_PFD1] = {
+ .data = &(struct vc3_pfd_data) {
+ .num = VC3_PFD1,
+ .offs = VC3_PLL1_M_DIVIDER,
+ .mdiv1_bitmsk = VC3_PLL1_M_DIV1,
+ .mdiv2_bitmsk = VC3_PLL1_M_DIV2
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pfd1",
+ .ops = &vc3_pfd_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .index = 0
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT
+ }
+ },
+ [VC3_PFD2] = {
+ .data = &(struct vc3_pfd_data) {
+ .num = VC3_PFD2,
+ .offs = VC3_PLL2_M_DIVIDER,
+ .mdiv1_bitmsk = VC3_PLL2_M_DIV1,
+ .mdiv2_bitmsk = VC3_PLL2_M_DIV2
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pfd2",
+ .ops = &vc3_pfd_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &clk_pfd_mux[VC3_PFD2_MUX].hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT
+ }
+ },
+ [VC3_PFD3] = {
+ .data = &(struct vc3_pfd_data) {
+ .num = VC3_PFD3,
+ .offs = VC3_PLL3_M_DIVIDER,
+ .mdiv1_bitmsk = VC3_PLL3_M_DIV1,
+ .mdiv2_bitmsk = VC3_PLL3_M_DIV2
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pfd3",
+ .ops = &vc3_pfd_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &clk_pfd_mux[VC3_PFD3_MUX].hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT
+ }
+ }
+};
+
+static struct vc3_hw_data clk_pll[] = {
+ [VC3_PLL1] = {
+ .data = &(struct vc3_pll_data) {
+ .num = VC3_PLL1,
+ .int_div_msb_offs = VC3_PLL1_LOOP_FILTER_N_DIV_MSB,
+ .int_div_lsb_offs = VC3_PLL1_VCO_N_DIVIDER,
+ .vco_min = VC3_PLL1_VCO_MIN,
+ .vco_max = VC3_PLL1_VCO_MAX
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pll1",
+ .ops = &vc3_pll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &clk_pfd[VC3_PFD1].hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT
+ }
+ },
+ [VC3_PLL2] = {
+ .data = &(struct vc3_pll_data) {
+ .num = VC3_PLL2,
+ .int_div_msb_offs = VC3_PLL2_FB_INT_DIV_MSB,
+ .int_div_lsb_offs = VC3_PLL2_FB_INT_DIV_LSB,
+ .vco_min = VC3_PLL2_VCO_MIN,
+ .vco_max = VC3_PLL2_VCO_MAX
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pll2",
+ .ops = &vc3_pll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &clk_pfd[VC3_PFD2].hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT
+ }
+ },
+ [VC3_PLL3] = {
+ .data = &(struct vc3_pll_data) {
+ .num = VC3_PLL3,
+ .int_div_msb_offs = VC3_PLL3_LOOP_FILTER_N_DIV_MSB,
+ .int_div_lsb_offs = VC3_PLL3_N_DIVIDER,
+ .vco_min = VC3_PLL3_VCO_MIN,
+ .vco_max = VC3_PLL3_VCO_MAX
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "pll3",
+ .ops = &vc3_pll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &clk_pfd[VC3_PFD3].hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT
+ }
+ }
+};
+
+static const struct clk_parent_data div_mux_parent_data[][2] = {
+ [VC3_DIV1_MUX] = {
+ { .hw = &clk_pll[VC3_PLL1].hw },
+ { .index = 0 }
+ },
+ [VC3_DIV3_MUX] = {
+ { .hw = &clk_pll[VC3_PLL2].hw },
+ { .hw = &clk_pll[VC3_PLL3].hw }
+ },
+ [VC3_DIV4_MUX] = {
+ { .hw = &clk_pll[VC3_PLL2].hw },
+ { .index = 0 }
+ }
+};
+
+static struct vc3_hw_data clk_div_mux[] = {
+ [VC3_DIV1_MUX] = {
+ .data = &(struct vc3_clk_data) {
+ .offs = VC3_GENERAL_CTR,
+ .bitmsk = VC3_GENERAL_CTR_DIV1_SRC_SEL
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "div1_mux",
+ .ops = &vc3_div_mux_ops,
+ .parent_data = div_mux_parent_data[VC3_DIV1_MUX],
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
+ }
+ },
+ [VC3_DIV3_MUX] = {
+ .data = &(struct vc3_clk_data) {
+ .offs = VC3_PLL3_CHARGE_PUMP_CTRL,
+ .bitmsk = VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "div3_mux",
+ .ops = &vc3_div_mux_ops,
+ .parent_data = div_mux_parent_data[VC3_DIV3_MUX],
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
+ }
+ },
+ [VC3_DIV4_MUX] = {
+ .data = &(struct vc3_clk_data) {
+ .offs = VC3_OUTPUT_CTR,
+ .bitmsk = VC3_OUTPUT_CTR_DIV4_SRC_SEL
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "div4_mux",
+ .ops = &vc3_div_mux_ops,
+ .parent_data = div_mux_parent_data[VC3_DIV4_MUX],
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
+ }
+ }
+};
+
+static struct vc3_hw_data clk_div[] = {
+ [VC3_DIV1] = {
+ .data = &(struct vc3_div_data) {
+ .offs = VC3_OUT_DIV1_DIV2_CTRL,
+ .table = div1_divs,
+ .shift = 4,
+ .width = 4,
+ .flags = CLK_DIVIDER_READ_ONLY
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "div1",
+ .ops = &vc3_div_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &clk_div_mux[VC3_DIV1_MUX].hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT
+ }
+ },
+ [VC3_DIV2] = {
+ .data = &(struct vc3_div_data) {
+ .offs = VC3_OUT_DIV1_DIV2_CTRL,
+ .table = div245_divs,
+ .shift = 0,
+ .width = 4,
+ .flags = CLK_DIVIDER_READ_ONLY
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "div2",
+ .ops = &vc3_div_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &clk_pll[VC3_PLL1].hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT
+ }
+ },
+ [VC3_DIV3] = {
+ .data = &(struct vc3_div_data) {
+ .offs = VC3_OUT_DIV3_DIV4_CTRL,
+ .table = div3_divs,
+ .shift = 4,
+ .width = 4,
+ .flags = CLK_DIVIDER_READ_ONLY
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "div3",
+ .ops = &vc3_div_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &clk_div_mux[VC3_DIV3_MUX].hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT
+ }
+ },
+ [VC3_DIV4] = {
+ .data = &(struct vc3_div_data) {
+ .offs = VC3_OUT_DIV3_DIV4_CTRL,
+ .table = div245_divs,
+ .shift = 0,
+ .width = 4,
+ .flags = CLK_DIVIDER_READ_ONLY
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "div4",
+ .ops = &vc3_div_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &clk_div_mux[VC3_DIV4_MUX].hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT
+ }
+ },
+ [VC3_DIV5] = {
+ .data = &(struct vc3_div_data) {
+ .offs = VC3_PLL1_CTRL_OUTDIV5,
+ .table = div245_divs,
+ .shift = 0,
+ .width = 4,
+ .flags = CLK_DIVIDER_READ_ONLY
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "div5",
+ .ops = &vc3_div_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &clk_pll[VC3_PLL3].hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT
+ }
+ }
+};
+
+static struct vc3_hw_data clk_mux[] = {
+ [VC3_DIFF2_MUX] = {
+ .data = &(struct vc3_clk_data) {
+ .offs = VC3_DIFF2_CTRL_REG,
+ .bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "diff2_mux",
+ .ops = &vc3_clk_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &clk_div[VC3_DIV1].hw,
+ &clk_div[VC3_DIV3].hw
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT
+ }
+ },
+ [VC3_DIFF1_MUX] = {
+ .data = &(struct vc3_clk_data) {
+ .offs = VC3_DIFF1_CTRL_REG,
+ .bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "diff1_mux",
+ .ops = &vc3_clk_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &clk_div[VC3_DIV1].hw,
+ &clk_div[VC3_DIV3].hw
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT
+ }
+ },
+ [VC3_SE3_MUX] = {
+ .data = &(struct vc3_clk_data) {
+ .offs = VC3_SE3_DIFF1_CTRL_REG,
+ .bitmsk = VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "se3_mux",
+ .ops = &vc3_clk_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &clk_div[VC3_DIV2].hw,
+ &clk_div[VC3_DIV4].hw
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT
+ }
+ },
+ [VC3_SE2_MUX] = {
+ .data = &(struct vc3_clk_data) {
+ .offs = VC3_SE2_CTRL_REG0,
+ .bitmsk = VC3_SE2_CTRL_REG0_SE2_CLK_SEL
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "se2_mux",
+ .ops = &vc3_clk_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &clk_div[VC3_DIV5].hw,
+ &clk_div[VC3_DIV4].hw
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT
+ }
+ },
+ [VC3_SE1_MUX] = {
+ .data = &(struct vc3_clk_data) {
+ .offs = VC3_SE1_DIV4_CTRL,
+ .bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "se1_mux",
+ .ops = &vc3_clk_mux_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &clk_div[VC3_DIV5].hw,
+ &clk_div[VC3_DIV4].hw
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT
+ }
+ }
+};
+
+static struct clk_hw *vc3_of_clk_get(struct of_phandle_args *clkspec,
+ void *data)
+{
+ unsigned int idx = clkspec->args[0];
+ struct clk_hw **clkout_hw = data;
+
+ if (idx >= ARRAY_SIZE(clk_out)) {
+ pr_err("invalid clk index %u for provider %pOF\n", idx, clkspec->np);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return clkout_hw[idx];
+}
+
+static int vc3_probe(struct i2c_client *client)
+{
+ struct device *dev = &client->dev;
+ u8 settings[NUM_CONFIG_REGISTERS];
+ struct regmap *regmap;
+ const char *name;
+ int ret, i;
+
+ regmap = devm_regmap_init_i2c(client, &vc3_regmap_config);
+ if (IS_ERR(regmap))
+ return dev_err_probe(dev, PTR_ERR(regmap),
+ "failed to allocate register map\n");
+
+ ret = of_property_read_u8_array(dev->of_node, "renesas,settings",
+ settings, ARRAY_SIZE(settings));
+ if (!ret) {
+ /*
+ * A raw settings array was specified in the DT. Write the
+ * settings to the device immediately.
+ */
+ for (i = 0; i < NUM_CONFIG_REGISTERS; i++) {
+ ret = regmap_write(regmap, i, settings[i]);
+ if (ret) {
+ dev_err(dev, "error writing to chip (%i)\n", ret);
+ return ret;
+ }
+ }
+ } else if (ret == -EOVERFLOW) {
+ dev_err(&client->dev, "EOVERFLOW reg settings. ARRAY_SIZE: %zu\n",
+ ARRAY_SIZE(settings));
+ return ret;
+ }
+
+ /* Register pfd muxes */
+ for (i = 0; i < ARRAY_SIZE(clk_pfd_mux); i++) {
+ clk_pfd_mux[i].regmap = regmap;
+ ret = devm_clk_hw_register(dev, &clk_pfd_mux[i].hw);
+ if (ret)
+ return dev_err_probe(dev, ret, "%s failed\n",
+ clk_pfd_mux[i].hw.init->name);
+ }
+
+ /* Register pfd's */
+ for (i = 0; i < ARRAY_SIZE(clk_pfd); i++) {
+ clk_pfd[i].regmap = regmap;
+ ret = devm_clk_hw_register(dev, &clk_pfd[i].hw);
+ if (ret)
+ return dev_err_probe(dev, ret, "%s failed\n",
+ clk_pfd[i].hw.init->name);
+ }
+
+ /* Register pll's */
+ for (i = 0; i < ARRAY_SIZE(clk_pll); i++) {
+ clk_pll[i].regmap = regmap;
+ ret = devm_clk_hw_register(dev, &clk_pll[i].hw);
+ if (ret)
+ return dev_err_probe(dev, ret, "%s failed\n",
+ clk_pll[i].hw.init->name);
+ }
+
+ /* Register divider muxes */
+ for (i = 0; i < ARRAY_SIZE(clk_div_mux); i++) {
+ clk_div_mux[i].regmap = regmap;
+ ret = devm_clk_hw_register(dev, &clk_div_mux[i].hw);
+ if (ret)
+ return dev_err_probe(dev, ret, "%s failed\n",
+ clk_div_mux[i].hw.init->name);
+ }
+
+ /* Register dividers */
+ for (i = 0; i < ARRAY_SIZE(clk_div); i++) {
+ clk_div[i].regmap = regmap;
+ ret = devm_clk_hw_register(dev, &clk_div[i].hw);
+ if (ret)
+ return dev_err_probe(dev, ret, "%s failed\n",
+ clk_div[i].hw.init->name);
+ }
+
+ /* Register clk muxes */
+ for (i = 0; i < ARRAY_SIZE(clk_mux); i++) {
+ clk_mux[i].regmap = regmap;
+ ret = devm_clk_hw_register(dev, &clk_mux[i].hw);
+ if (ret)
+ return dev_err_probe(dev, ret, "%s failed\n",
+ clk_mux[i].hw.init->name);
+ }
+
+ /* Register clk outputs */
+ for (i = 0; i < ARRAY_SIZE(clk_out); i++) {
+ switch (i) {
+ case VC3_DIFF2:
+ name = "diff2";
+ break;
+ case VC3_DIFF1:
+ name = "diff1";
+ break;
+ case VC3_SE3:
+ name = "se3";
+ break;
+ case VC3_SE2:
+ name = "se2";
+ break;
+ case VC3_SE1:
+ name = "se1";
+ break;
+ case VC3_REF:
+ name = "ref";
+ break;
+ default:
+ return dev_err_probe(dev, -EINVAL, "invalid clk output %d\n", i);
+ }
+
+ if (i == VC3_REF)
+ clk_out[i] = devm_clk_hw_register_fixed_factor_index(dev,
+ name, 0, CLK_SET_RATE_PARENT, 1, 1);
+ else
+ clk_out[i] = devm_clk_hw_register_fixed_factor_parent_hw(dev,
+ name, &clk_mux[i].hw, CLK_SET_RATE_PARENT, 1, 1);
+
+ if (IS_ERR(clk_out[i]))
+ return PTR_ERR(clk_out[i]);
+ }
+
+ ret = devm_of_clk_add_hw_provider(dev, vc3_of_clk_get, clk_out);
+ if (ret)
+ return dev_err_probe(dev, ret, "unable to add clk provider\n");
+
+ return ret;
+}
+
+static const struct of_device_id dev_ids[] = {
+ { .compatible = "renesas,5p35023" },
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dev_ids);
+
+static struct i2c_driver vc3_driver = {
+ .driver = {
+ .name = "vc3",
+ .of_match_table = of_match_ptr(dev_ids),
+ },
+ .probe = vc3_probe,
+};
+module_i2c_driver(vc3_driver);
+
+MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
+MODULE_DESCRIPTION("Renesas VersaClock 3 driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
index 8bc54176f325..17cbb30d20ad 100644
--- a/drivers/clk/clk-versaclock5.c
+++ b/drivers/clk/clk-versaclock5.c
@@ -19,7 +19,6 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_platform.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/slab.h>
@@ -956,7 +955,7 @@ static int vc5_probe(struct i2c_client *client)
i2c_set_clientdata(client, vc5);
vc5->client = client;
- vc5->chip_info = device_get_match_data(&client->dev);
+ vc5->chip_info = i2c_get_match_data(client);
vc5->pin_xin = devm_clk_get(&client->dev, "xin");
if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
diff --git a/drivers/clk/clk-versaclock7.c b/drivers/clk/clk-versaclock7.c
index 9babb7913c1c..9ab35c1af0ff 100644
--- a/drivers/clk/clk-versaclock7.c
+++ b/drivers/clk/clk-versaclock7.c
@@ -14,7 +14,6 @@
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_platform.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/swab.h>
@@ -1109,7 +1108,7 @@ static int vc7_probe(struct i2c_client *client)
i2c_set_clientdata(client, vc7);
vc7->client = client;
- vc7->chip_info = device_get_match_data(&client->dev);
+ vc7->chip_info = i2c_get_match_data(client);
vc7->pin_xin = devm_clk_get(&client->dev, "xin");
if (PTR_ERR(vc7->pin_xin) == -EPROBE_DEFER) {
diff --git a/drivers/clk/hisilicon/clk-hi3559a.c b/drivers/clk/hisilicon/clk-hi3559a.c
index ce4028102bc2..ff4ca0edce06 100644
--- a/drivers/clk/hisilicon/clk-hi3559a.c
+++ b/drivers/clk/hisilicon/clk-hi3559a.c
@@ -9,7 +9,7 @@
#include <linux/clk-provider.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c
index a3d04c7c3da8..2d7186905abd 100644
--- a/drivers/clk/hisilicon/clk-hi3620.c
+++ b/drivers/clk/hisilicon/clk-hi3620.c
@@ -14,7 +14,6 @@
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/slab.h>
#include <dt-bindings/clock/hi3620-clock.h>
diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c
index 41f61726ab19..50f13dbb0e48 100644
--- a/drivers/clk/hisilicon/clk-hi3660.c
+++ b/drivers/clk/hisilicon/clk-hi3660.c
@@ -6,7 +6,7 @@
#include <dt-bindings/clock/hi3660-clock.h>
#include <linux/clk-provider.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk.h"
diff --git a/drivers/clk/hisilicon/clk-hi3670.c b/drivers/clk/hisilicon/clk-hi3670.c
index 4d05a71683a5..fa20ad144c8e 100644
--- a/drivers/clk/hisilicon/clk-hi3670.c
+++ b/drivers/clk/hisilicon/clk-hi3670.c
@@ -9,7 +9,7 @@
#include <dt-bindings/clock/hi3670-clock.h>
#include <linux/clk-provider.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk.h"
diff --git a/drivers/clk/hisilicon/clk-hi6220-stub.c b/drivers/clk/hisilicon/clk-hi6220-stub.c
index 4fdee4424d82..a8319795ed1c 100644
--- a/drivers/clk/hisilicon/clk-hi6220-stub.c
+++ b/drivers/clk/hisilicon/clk-hi6220-stub.c
@@ -14,7 +14,7 @@
#include <linux/mfd/syscon.h>
#include <linux/mailbox_client.h>
#include <linux/of.h>
-#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
/* Stub clocks id */
diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c
index e7cdf72d4b06..c9d5a88da053 100644
--- a/drivers/clk/hisilicon/clk-hi6220.c
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -11,9 +11,6 @@
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/slab.h>
#include <dt-bindings/clock/hi6220-clock.h>
diff --git a/drivers/clk/hisilicon/clk-hip04.c b/drivers/clk/hisilicon/clk-hip04.c
index 785b9faf3ea5..feb34e98af8c 100644
--- a/drivers/clk/hisilicon/clk-hip04.c
+++ b/drivers/clk/hisilicon/clk-hip04.c
@@ -11,9 +11,6 @@
#include <linux/kernel.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/slab.h>
#include <dt-bindings/clock/hip04-clock.h>
diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c
index 54d9fdc93599..09368fd32bef 100644
--- a/drivers/clk/hisilicon/clk.c
+++ b/drivers/clk/hisilicon/clk.c
@@ -16,7 +16,7 @@
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include <linux/slab.h>
#include "clk.h"
diff --git a/drivers/clk/hisilicon/crg-hi3516cv300.c b/drivers/clk/hisilicon/crg-hi3516cv300.c
index fe1bd3e3f988..e602e65fbc38 100644
--- a/drivers/clk/hisilicon/crg-hi3516cv300.c
+++ b/drivers/clk/hisilicon/crg-hi3516cv300.c
@@ -8,7 +8,7 @@
#include <dt-bindings/clock/hi3516cv300-clock.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk.h"
#include "crg.h"
diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c
index a0b16be1e25d..f651b197e45a 100644
--- a/drivers/clk/hisilicon/crg-hi3798cv200.c
+++ b/drivers/clk/hisilicon/crg-hi3798cv200.c
@@ -8,7 +8,7 @@
#include <dt-bindings/clock/histb-clock.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk.h"
#include "crg.h"
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index ae9d84ef046b..d4b8e10b1970 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -32,11 +32,12 @@ obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
obj-$(CONFIG_CLK_IMX93) += clk-imx93.o
-obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o
+obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o clk-imx-acm.o
clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \
clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o \
clk-imx8dxl-rsrc.o
clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o
+clk-imx-acm-$(CONFIG_CLK_IMX8QXP) = clk-imx8-acm.o
obj-$(CONFIG_CLK_IMX8ULP) += clk-imx8ulp.o
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 7a6e3ce97133..27a08c50ac1d 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -97,7 +97,7 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
int prediv_value;
int div_value;
int ret;
- u32 val;
+ u32 orig, val;
ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
&prediv_value, &div_value);
@@ -106,13 +106,15 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
spin_lock_irqsave(divider->lock, flags);
- val = readl(divider->reg);
- val &= ~((clk_div_mask(divider->width) << divider->shift) |
- (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
+ orig = readl(divider->reg);
+ val = orig & ~((clk_div_mask(divider->width) << divider->shift) |
+ (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
val |= (u32)(prediv_value - 1) << divider->shift;
val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
- writel(val, divider->reg);
+
+ if (val != orig)
+ writel(val, divider->reg);
spin_unlock_irqrestore(divider->lock, flags);
diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
index c54f9999da04..44462ab50e51 100644
--- a/drivers/clk/imx/clk-fracn-gppll.c
+++ b/drivers/clk/imx/clk-fracn-gppll.c
@@ -81,6 +81,7 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),
PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
+ PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8),
PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
diff --git a/drivers/clk/imx/clk-gpr-mux.c b/drivers/clk/imx/clk-gpr-mux.c
index 0b5a97698b47..0e14b61cba84 100644
--- a/drivers/clk/imx/clk-gpr-mux.c
+++ b/drivers/clk/imx/clk-gpr-mux.c
@@ -65,16 +65,10 @@ static int imx_clk_gpr_mux_set_parent(struct clk_hw *hw, u8 index)
return regmap_update_bits(priv->regmap, priv->reg, priv->mask, val);
}
-static int imx_clk_gpr_mux_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- return clk_mux_determine_rate_flags(hw, req, 0);
-}
-
static const struct clk_ops imx_clk_gpr_mux_ops = {
.get_parent = imx_clk_gpr_mux_get_parent,
.set_parent = imx_clk_gpr_mux_set_parent,
- .determine_rate = imx_clk_gpr_mux_determine_rate,
+ .determine_rate = __clk_mux_determine_rate,
};
struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible,
diff --git a/drivers/clk/imx/clk-imx25.c b/drivers/clk/imx/clk-imx25.c
index cc013b343e62..c566be848c2d 100644
--- a/drivers/clk/imx/clk-imx25.c
+++ b/drivers/clk/imx/clk-imx25.c
@@ -13,6 +13,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
+#include <soc/imx/revision.h>
#include "clk.h"
@@ -73,7 +74,7 @@ enum mx25_clks {
static struct clk *clk[clk_max];
-static int __init __mx25_clocks_init(void __iomem *ccm_base)
+static void __init __mx25_clocks_init(void __iomem *ccm_base)
{
BUG_ON(!ccm_base);
@@ -220,7 +221,7 @@ static int __init __mx25_clocks_init(void __iomem *ccm_base)
imx_register_uart_clocks();
- return 0;
+ imx_print_silicon_rev("i.MX25", mx25_revision());
}
static void __init mx25_clocks_init_dt(struct device_node *np)
diff --git a/drivers/clk/imx/clk-imx8-acm.c b/drivers/clk/imx/clk-imx8-acm.c
new file mode 100644
index 000000000000..1e82f72b75c6
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8-acm.c
@@ -0,0 +1,476 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2023 NXP
+//
+
+#include <dt-bindings/clock/imx8-clock.h>
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+
+#include "clk.h"
+
+/**
+ * struct clk_imx_acm_pm_domains - structure for multi power domain
+ * @pd_dev: power domain device
+ * @pd_dev_link: power domain device link
+ * @num_domains: power domain nummber
+ */
+struct clk_imx_acm_pm_domains {
+ struct device **pd_dev;
+ struct device_link **pd_dev_link;
+ int num_domains;
+};
+
+/**
+ * struct clk_imx8_acm_sel - for clock mux
+ * @name: clock name
+ * @clkid: clock id
+ * @parents: clock parents
+ * @num_parents: clock parents number
+ * @reg: register offset
+ * @shift: bit shift in register
+ * @width: bits width
+ */
+struct clk_imx8_acm_sel {
+ const char *name;
+ int clkid;
+ const struct clk_parent_data *parents; /* For mux */
+ int num_parents;
+ u32 reg;
+ u8 shift;
+ u8 width;
+};
+
+/**
+ * struct imx8_acm_soc_data - soc specific data
+ * @sels: pointer to struct clk_imx8_acm_sel
+ * @num_sels: numbers of items
+ */
+struct imx8_acm_soc_data {
+ struct clk_imx8_acm_sel *sels;
+ unsigned int num_sels;
+};
+
+/**
+ * struct imx8_acm_priv - private structure
+ * @dev_pm: multi power domain
+ * @soc_data: pointer to soc data
+ * @reg: base address of registers
+ * @regs: save registers for suspend
+ */
+struct imx8_acm_priv {
+ struct clk_imx_acm_pm_domains dev_pm;
+ const struct imx8_acm_soc_data *soc_data;
+ void __iomem *reg;
+ u32 regs[IMX_ADMA_ACM_CLK_END];
+};
+
+static const struct clk_parent_data imx8qm_aud_clk_sels[] = {
+ { .fw_name = "aud_rec_clk0_lpcg_clk" },
+ { .fw_name = "aud_rec_clk1_lpcg_clk" },
+ { .fw_name = "mlb_clk" },
+ { .fw_name = "hdmi_rx_mclk" },
+ { .fw_name = "ext_aud_mclk0" },
+ { .fw_name = "ext_aud_mclk1" },
+ { .fw_name = "esai0_rx_clk" },
+ { .fw_name = "esai0_rx_hf_clk" },
+ { .fw_name = "esai0_tx_clk" },
+ { .fw_name = "esai0_tx_hf_clk" },
+ { .fw_name = "esai1_rx_clk" },
+ { .fw_name = "esai1_rx_hf_clk" },
+ { .fw_name = "esai1_tx_clk" },
+ { .fw_name = "esai1_tx_hf_clk" },
+ { .fw_name = "spdif0_rx" },
+ { .fw_name = "spdif1_rx" },
+ { .fw_name = "sai0_rx_bclk" },
+ { .fw_name = "sai0_tx_bclk" },
+ { .fw_name = "sai1_rx_bclk" },
+ { .fw_name = "sai1_tx_bclk" },
+ { .fw_name = "sai2_rx_bclk" },
+ { .fw_name = "sai3_rx_bclk" },
+ { .fw_name = "sai4_rx_bclk" },
+};
+
+static const struct clk_parent_data imx8qm_mclk_out_sels[] = {
+ { .fw_name = "aud_rec_clk0_lpcg_clk" },
+ { .fw_name = "aud_rec_clk1_lpcg_clk" },
+ { .fw_name = "mlb_clk" },
+ { .fw_name = "hdmi_rx_mclk" },
+ { .fw_name = "spdif0_rx" },
+ { .fw_name = "spdif1_rx" },
+ { .fw_name = "sai4_rx_bclk" },
+ { .fw_name = "sai6_rx_bclk" },
+};
+
+static const struct clk_parent_data imx8qm_mclk_sels[] = {
+ { .fw_name = "aud_pll_div_clk0_lpcg_clk" },
+ { .fw_name = "aud_pll_div_clk1_lpcg_clk" },
+ { .fw_name = "acm_aud_clk0_sel" },
+ { .fw_name = "acm_aud_clk1_sel" },
+};
+
+static const struct clk_parent_data imx8qm_asrc_mux_clk_sels[] = {
+ { .fw_name = "sai4_rx_bclk" },
+ { .fw_name = "sai5_tx_bclk" },
+ { .index = -1 },
+ { .fw_name = "mlb_clk" },
+
+};
+
+static struct clk_imx8_acm_sel imx8qm_sels[] = {
+ { "acm_aud_clk0_sel", IMX_ADMA_ACM_AUD_CLK0_SEL, imx8qm_aud_clk_sels, ARRAY_SIZE(imx8qm_aud_clk_sels), 0x000000, 0, 5 },
+ { "acm_aud_clk1_sel", IMX_ADMA_ACM_AUD_CLK1_SEL, imx8qm_aud_clk_sels, ARRAY_SIZE(imx8qm_aud_clk_sels), 0x010000, 0, 5 },
+ { "acm_mclkout0_sel", IMX_ADMA_ACM_MCLKOUT0_SEL, imx8qm_mclk_out_sels, ARRAY_SIZE(imx8qm_mclk_out_sels), 0x020000, 0, 3 },
+ { "acm_mclkout1_sel", IMX_ADMA_ACM_MCLKOUT1_SEL, imx8qm_mclk_out_sels, ARRAY_SIZE(imx8qm_mclk_out_sels), 0x030000, 0, 3 },
+ { "acm_asrc0_mclk_sel", IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL, imx8qm_asrc_mux_clk_sels, ARRAY_SIZE(imx8qm_asrc_mux_clk_sels), 0x040000, 0, 2 },
+ { "acm_esai0_mclk_sel", IMX_ADMA_ACM_ESAI0_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x060000, 0, 2 },
+ { "acm_esai1_mclk_sel", IMX_ADMA_ACM_ESAI1_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x070000, 0, 2 },
+ { "acm_sai0_mclk_sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x0E0000, 0, 2 },
+ { "acm_sai1_mclk_sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x0F0000, 0, 2 },
+ { "acm_sai2_mclk_sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x100000, 0, 2 },
+ { "acm_sai3_mclk_sel", IMX_ADMA_ACM_SAI3_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x110000, 0, 2 },
+ { "acm_sai4_mclk_sel", IMX_ADMA_ACM_SAI4_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x120000, 0, 2 },
+ { "acm_sai5_mclk_sel", IMX_ADMA_ACM_SAI5_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x130000, 0, 2 },
+ { "acm_sai6_mclk_sel", IMX_ADMA_ACM_SAI6_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x140000, 0, 2 },
+ { "acm_sai7_mclk_sel", IMX_ADMA_ACM_SAI7_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x150000, 0, 2 },
+ { "acm_spdif0_mclk_sel", IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x1A0000, 0, 2 },
+ { "acm_spdif1_mclk_sel", IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x1B0000, 0, 2 },
+ { "acm_mqs_mclk_sel", IMX_ADMA_ACM_MQS_TX_CLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x1C0000, 0, 2 },
+};
+
+static const struct clk_parent_data imx8qxp_aud_clk_sels[] = {
+ { .fw_name = "aud_rec_clk0_lpcg_clk" },
+ { .fw_name = "aud_rec_clk1_lpcg_clk" },
+ { .fw_name = "ext_aud_mclk0" },
+ { .fw_name = "ext_aud_mclk1" },
+ { .fw_name = "esai0_rx_clk" },
+ { .fw_name = "esai0_rx_hf_clk" },
+ { .fw_name = "esai0_tx_clk" },
+ { .fw_name = "esai0_tx_hf_clk" },
+ { .fw_name = "spdif0_rx" },
+ { .fw_name = "sai0_rx_bclk" },
+ { .fw_name = "sai0_tx_bclk" },
+ { .fw_name = "sai1_rx_bclk" },
+ { .fw_name = "sai1_tx_bclk" },
+ { .fw_name = "sai2_rx_bclk" },
+ { .fw_name = "sai3_rx_bclk" },
+};
+
+static const struct clk_parent_data imx8qxp_mclk_out_sels[] = {
+ { .fw_name = "aud_rec_clk0_lpcg_clk" },
+ { .fw_name = "aud_rec_clk1_lpcg_clk" },
+ { .index = -1 },
+ { .index = -1 },
+ { .fw_name = "spdif0_rx" },
+ { .index = -1 },
+ { .index = -1 },
+ { .fw_name = "sai4_rx_bclk" },
+};
+
+static const struct clk_parent_data imx8qxp_mclk_sels[] = {
+ { .fw_name = "aud_pll_div_clk0_lpcg_clk" },
+ { .fw_name = "aud_pll_div_clk1_lpcg_clk" },
+ { .fw_name = "acm_aud_clk0_sel" },
+ { .fw_name = "acm_aud_clk1_sel" },
+};
+
+static struct clk_imx8_acm_sel imx8qxp_sels[] = {
+ { "acm_aud_clk0_sel", IMX_ADMA_ACM_AUD_CLK0_SEL, imx8qxp_aud_clk_sels, ARRAY_SIZE(imx8qxp_aud_clk_sels), 0x000000, 0, 5 },
+ { "acm_aud_clk1_sel", IMX_ADMA_ACM_AUD_CLK1_SEL, imx8qxp_aud_clk_sels, ARRAY_SIZE(imx8qxp_aud_clk_sels), 0x010000, 0, 5 },
+ { "acm_mclkout0_sel", IMX_ADMA_ACM_MCLKOUT0_SEL, imx8qxp_mclk_out_sels, ARRAY_SIZE(imx8qxp_mclk_out_sels), 0x020000, 0, 3 },
+ { "acm_mclkout1_sel", IMX_ADMA_ACM_MCLKOUT1_SEL, imx8qxp_mclk_out_sels, ARRAY_SIZE(imx8qxp_mclk_out_sels), 0x030000, 0, 3 },
+ { "acm_esai0_mclk_sel", IMX_ADMA_ACM_ESAI0_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x060000, 0, 2 },
+ { "acm_sai0_mclk_sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x0E0000, 0, 2 },
+ { "acm_sai1_mclk_sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x0F0000, 0, 2 },
+ { "acm_sai2_mclk_sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x100000, 0, 2 },
+ { "acm_sai3_mclk_sel", IMX_ADMA_ACM_SAI3_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x110000, 0, 2 },
+ { "acm_sai4_mclk_sel", IMX_ADMA_ACM_SAI4_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x140000, 0, 2 },
+ { "acm_sai5_mclk_sel", IMX_ADMA_ACM_SAI5_MCLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x150000, 0, 2 },
+ { "acm_spdif0_mclk_sel", IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x1A0000, 0, 2 },
+ { "acm_mqs_mclk_sel", IMX_ADMA_ACM_MQS_TX_CLK_SEL, imx8qxp_mclk_sels, ARRAY_SIZE(imx8qxp_mclk_sels), 0x1C0000, 0, 2 },
+};
+
+static const struct clk_parent_data imx8dxl_aud_clk_sels[] = {
+ { .fw_name = "aud_rec_clk0_lpcg_clk" },
+ { .fw_name = "aud_rec_clk1_lpcg_clk" },
+ { .fw_name = "ext_aud_mclk0" },
+ { .fw_name = "ext_aud_mclk1" },
+ { .index = -1 },
+ { .index = -1 },
+ { .index = -1 },
+ { .index = -1 },
+ { .fw_name = "spdif0_rx" },
+ { .fw_name = "sai0_rx_bclk" },
+ { .fw_name = "sai0_tx_bclk" },
+ { .fw_name = "sai1_rx_bclk" },
+ { .fw_name = "sai1_tx_bclk" },
+ { .fw_name = "sai2_rx_bclk" },
+ { .fw_name = "sai3_rx_bclk" },
+};
+
+static const struct clk_parent_data imx8dxl_mclk_out_sels[] = {
+ { .fw_name = "aud_rec_clk0_lpcg_clk" },
+ { .fw_name = "aud_rec_clk1_lpcg_clk" },
+ { .index = -1 },
+ { .index = -1 },
+ { .fw_name = "spdif0_rx" },
+ { .index = -1 },
+ { .index = -1 },
+ { .index = -1 },
+};
+
+static const struct clk_parent_data imx8dxl_mclk_sels[] = {
+ { .fw_name = "aud_pll_div_clk0_lpcg_clk" },
+ { .fw_name = "aud_pll_div_clk1_lpcg_clk" },
+ { .fw_name = "acm_aud_clk0_sel" },
+ { .fw_name = "acm_aud_clk1_sel" },
+};
+
+static struct clk_imx8_acm_sel imx8dxl_sels[] = {
+ { "acm_aud_clk0_sel", IMX_ADMA_ACM_AUD_CLK0_SEL, imx8dxl_aud_clk_sels, ARRAY_SIZE(imx8dxl_aud_clk_sels), 0x000000, 0, 5 },
+ { "acm_aud_clk1_sel", IMX_ADMA_ACM_AUD_CLK1_SEL, imx8dxl_aud_clk_sels, ARRAY_SIZE(imx8dxl_aud_clk_sels), 0x010000, 0, 5 },
+ { "acm_mclkout0_sel", IMX_ADMA_ACM_MCLKOUT0_SEL, imx8dxl_mclk_out_sels, ARRAY_SIZE(imx8dxl_mclk_out_sels), 0x020000, 0, 3 },
+ { "acm_mclkout1_sel", IMX_ADMA_ACM_MCLKOUT1_SEL, imx8dxl_mclk_out_sels, ARRAY_SIZE(imx8dxl_mclk_out_sels), 0x030000, 0, 3 },
+ { "acm_sai0_mclk_sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x0E0000, 0, 2 },
+ { "acm_sai1_mclk_sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x0F0000, 0, 2 },
+ { "acm_sai2_mclk_sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x100000, 0, 2 },
+ { "acm_sai3_mclk_sel", IMX_ADMA_ACM_SAI3_MCLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x110000, 0, 2 },
+ { "acm_spdif0_mclk_sel", IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x1A0000, 0, 2 },
+ { "acm_mqs_mclk_sel", IMX_ADMA_ACM_MQS_TX_CLK_SEL, imx8dxl_mclk_sels, ARRAY_SIZE(imx8dxl_mclk_sels), 0x1C0000, 0, 2 },
+};
+
+/**
+ * clk_imx_acm_attach_pm_domains: attach multi power domains
+ * @dev: device pointer
+ * @dev_pm: power domains for device
+ */
+static int clk_imx_acm_attach_pm_domains(struct device *dev,
+ struct clk_imx_acm_pm_domains *dev_pm)
+{
+ int ret;
+ int i;
+
+ dev_pm->num_domains = of_count_phandle_with_args(dev->of_node, "power-domains",
+ "#power-domain-cells");
+ if (dev_pm->num_domains <= 1)
+ return 0;
+
+ dev_pm->pd_dev = devm_kmalloc_array(dev, dev_pm->num_domains,
+ sizeof(*dev_pm->pd_dev),
+ GFP_KERNEL);
+ if (!dev_pm->pd_dev)
+ return -ENOMEM;
+
+ dev_pm->pd_dev_link = devm_kmalloc_array(dev,
+ dev_pm->num_domains,
+ sizeof(*dev_pm->pd_dev_link),
+ GFP_KERNEL);
+ if (!dev_pm->pd_dev_link)
+ return -ENOMEM;
+
+ for (i = 0; i < dev_pm->num_domains; i++) {
+ dev_pm->pd_dev[i] = dev_pm_domain_attach_by_id(dev, i);
+ if (IS_ERR(dev_pm->pd_dev[i]))
+ return PTR_ERR(dev_pm->pd_dev[i]);
+
+ dev_pm->pd_dev_link[i] = device_link_add(dev,
+ dev_pm->pd_dev[i],
+ DL_FLAG_STATELESS |
+ DL_FLAG_PM_RUNTIME |
+ DL_FLAG_RPM_ACTIVE);
+ if (IS_ERR(dev_pm->pd_dev_link[i])) {
+ dev_pm_domain_detach(dev_pm->pd_dev[i], false);
+ ret = PTR_ERR(dev_pm->pd_dev_link[i]);
+ goto detach_pm;
+ }
+ }
+ return 0;
+
+detach_pm:
+ while (--i >= 0) {
+ device_link_del(dev_pm->pd_dev_link[i]);
+ dev_pm_domain_detach(dev_pm->pd_dev[i], false);
+ }
+ return ret;
+}
+
+/**
+ * clk_imx_acm_detach_pm_domains: detach multi power domains
+ * @dev: deivice pointer
+ * @dev_pm: multi power domain for device
+ */
+static int clk_imx_acm_detach_pm_domains(struct device *dev,
+ struct clk_imx_acm_pm_domains *dev_pm)
+{
+ int i;
+
+ if (dev_pm->num_domains <= 1)
+ return 0;
+
+ for (i = 0; i < dev_pm->num_domains; i++) {
+ device_link_del(dev_pm->pd_dev_link[i]);
+ dev_pm_domain_detach(dev_pm->pd_dev[i], false);
+ }
+
+ return 0;
+}
+
+static int imx8_acm_clk_probe(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *clk_hw_data;
+ struct device *dev = &pdev->dev;
+ struct clk_imx8_acm_sel *sels;
+ struct imx8_acm_priv *priv;
+ struct clk_hw **hws;
+ void __iomem *base;
+ int ret;
+ int i;
+
+ base = devm_of_iomap(dev, dev->of_node, 0, NULL);
+ if (WARN_ON(IS_ERR(base)))
+ return PTR_ERR(base);
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->reg = base;
+ priv->soc_data = of_device_get_match_data(dev);
+ platform_set_drvdata(pdev, priv);
+
+ clk_hw_data = devm_kzalloc(&pdev->dev, struct_size(clk_hw_data, hws, IMX_ADMA_ACM_CLK_END),
+ GFP_KERNEL);
+ if (!clk_hw_data)
+ return -ENOMEM;
+
+ clk_hw_data->num = IMX_ADMA_ACM_CLK_END;
+ hws = clk_hw_data->hws;
+
+ ret = clk_imx_acm_attach_pm_domains(&pdev->dev, &priv->dev_pm);
+ if (ret)
+ return ret;
+
+ pm_runtime_enable(&pdev->dev);
+ pm_runtime_get_sync(&pdev->dev);
+
+ sels = priv->soc_data->sels;
+ for (i = 0; i < priv->soc_data->num_sels; i++) {
+ hws[sels[i].clkid] = devm_clk_hw_register_mux_parent_data_table(dev,
+ sels[i].name, sels[i].parents,
+ sels[i].num_parents, 0,
+ base + sels[i].reg,
+ sels[i].shift, sels[i].width,
+ 0, NULL, NULL);
+ if (IS_ERR(hws[sels[i].clkid])) {
+ pm_runtime_disable(&pdev->dev);
+ goto err_clk_register;
+ }
+ }
+
+ imx_check_clk_hws(hws, IMX_ADMA_ACM_CLK_END);
+
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_hw_data);
+ if (ret < 0) {
+ dev_err(dev, "failed to register hws for ACM\n");
+ pm_runtime_disable(&pdev->dev);
+ }
+
+err_clk_register:
+
+ pm_runtime_put_sync(&pdev->dev);
+
+ return ret;
+}
+
+static int imx8_acm_clk_remove(struct platform_device *pdev)
+{
+ struct imx8_acm_priv *priv = dev_get_drvdata(&pdev->dev);
+
+ pm_runtime_disable(&pdev->dev);
+
+ clk_imx_acm_detach_pm_domains(&pdev->dev, &priv->dev_pm);
+
+ return 0;
+}
+
+static const struct imx8_acm_soc_data imx8qm_acm_data = {
+ .sels = imx8qm_sels,
+ .num_sels = ARRAY_SIZE(imx8qm_sels),
+};
+
+static const struct imx8_acm_soc_data imx8qxp_acm_data = {
+ .sels = imx8qxp_sels,
+ .num_sels = ARRAY_SIZE(imx8qxp_sels),
+};
+
+static const struct imx8_acm_soc_data imx8dxl_acm_data = {
+ .sels = imx8dxl_sels,
+ .num_sels = ARRAY_SIZE(imx8dxl_sels),
+};
+
+static const struct of_device_id imx8_acm_match[] = {
+ { .compatible = "fsl,imx8qm-acm", .data = &imx8qm_acm_data },
+ { .compatible = "fsl,imx8qxp-acm", .data = &imx8qxp_acm_data },
+ { .compatible = "fsl,imx8dxl-acm", .data = &imx8dxl_acm_data },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx8_acm_match);
+
+static int __maybe_unused imx8_acm_runtime_suspend(struct device *dev)
+{
+ struct imx8_acm_priv *priv = dev_get_drvdata(dev);
+ struct clk_imx8_acm_sel *sels;
+ int i;
+
+ sels = priv->soc_data->sels;
+
+ for (i = 0; i < priv->soc_data->num_sels; i++)
+ priv->regs[i] = readl_relaxed(priv->reg + sels[i].reg);
+
+ return 0;
+}
+
+static int __maybe_unused imx8_acm_runtime_resume(struct device *dev)
+{
+ struct imx8_acm_priv *priv = dev_get_drvdata(dev);
+ struct clk_imx8_acm_sel *sels;
+ int i;
+
+ sels = priv->soc_data->sels;
+
+ for (i = 0; i < priv->soc_data->num_sels; i++)
+ writel_relaxed(priv->regs[i], priv->reg + sels[i].reg);
+
+ return 0;
+}
+
+static const struct dev_pm_ops imx8_acm_pm_ops = {
+ SET_RUNTIME_PM_OPS(imx8_acm_runtime_suspend,
+ imx8_acm_runtime_resume, NULL)
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+};
+
+static struct platform_driver imx8_acm_clk_driver = {
+ .driver = {
+ .name = "imx8-acm",
+ .of_match_table = imx8_acm_match,
+ .pm = &imx8_acm_pm_ops,
+ },
+ .probe = imx8_acm_clk_probe,
+ .remove = imx8_acm_clk_remove,
+};
+module_platform_driver(imx8_acm_clk_driver);
+
+MODULE_AUTHOR("Shengjiu Wang <shengjiu.wang@nxp.com>");
+MODULE_DESCRIPTION("Freescale i.MX8 Audio Clock Mux driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 1469249386dd..670aa2bab301 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -178,10 +178,6 @@ static const char * const imx8mp_sai3_sels[] = {"osc_24m", "audio_pll1_out", "au
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
"clk_ext3", "clk_ext4", };
-static const char * const imx8mp_sai4_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
- "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
- "clk_ext1", "clk_ext2", };
-
static const char * const imx8mp_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
"clk_ext2", "clk_ext3", };
@@ -567,7 +563,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_CLK_SAI1] = imx8m_clk_hw_composite("sai1", imx8mp_sai1_sels, ccm_base + 0xa580);
hws[IMX8MP_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mp_sai2_sels, ccm_base + 0xa600);
hws[IMX8MP_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mp_sai3_sels, ccm_base + 0xa680);
- hws[IMX8MP_CLK_SAI4] = imx8m_clk_hw_composite("sai4", imx8mp_sai4_sels, ccm_base + 0xa700);
hws[IMX8MP_CLK_SAI5] = imx8m_clk_hw_composite("sai5", imx8mp_sai5_sels, ccm_base + 0xa780);
hws[IMX8MP_CLK_SAI6] = imx8m_clk_hw_composite("sai6", imx8mp_sai6_sels, ccm_base + 0xa800);
hws[IMX8MP_CLK_ENET_QOS] = imx8m_clk_hw_composite("enet_qos", imx8mp_enet_qos_sels, ccm_base + 0xa880);
diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c
index 5e31a6a24b3a..d0ccaa040225 100644
--- a/drivers/clk/imx/clk-imx8qxp-lpcg.c
+++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c
@@ -9,8 +9,6 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
@@ -183,7 +181,6 @@ static int imx_lpcg_parse_clks_from_dt(struct platform_device *pdev,
unsigned int bit_offset[IMX_LPCG_MAX_CLKS];
struct clk_hw_onecell_data *clk_data;
struct clk_hw **clk_hws;
- struct resource *res;
void __iomem *base;
int count;
int idx;
@@ -193,8 +190,7 @@ static int imx_lpcg_parse_clks_from_dt(struct platform_device *pdev,
if (!of_device_is_compatible(np, "fsl,imx8qxp-lpcg"))
return -EINVAL;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- base = devm_ioremap_resource(&pdev->dev, res);
+ base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index 546a3703bfeb..cadcbb318f5c 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -9,7 +9,6 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
diff --git a/drivers/clk/imx/clk-imx8ulp.c b/drivers/clk/imx/clk-imx8ulp.c
index e308c88cb801..535b6364ca7e 100644
--- a/drivers/clk/imx/clk-imx8ulp.c
+++ b/drivers/clk/imx/clk-imx8ulp.c
@@ -7,7 +7,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
@@ -167,7 +167,7 @@ static int imx8ulp_clk_cgc1_init(struct platform_device *pdev)
clks[IMX8ULP_CLK_SPLL2_PRE_SEL] = imx_clk_hw_mux_flags("spll2_pre_sel", base + 0x510, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
clks[IMX8ULP_CLK_SPLL3_PRE_SEL] = imx_clk_hw_mux_flags("spll3_pre_sel", base + 0x610, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
- clks[IMX8ULP_CLK_SPLL2] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "spll2", "spll2_pre_sel", base + 0x500);
+ clks[IMX8ULP_CLK_SPLL2] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP_1GHZ, "spll2", "spll2_pre_sel", base + 0x500);
clks[IMX8ULP_CLK_SPLL3] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "spll3", "spll3_pre_sel", base + 0x600);
clks[IMX8ULP_CLK_SPLL3_VCODIV] = imx_clk_hw_divider("spll3_vcodiv", "spll3", base + 0x604, 0, 6);
diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c
index 44f435103c65..c6a9bc8ecc1f 100644
--- a/drivers/clk/imx/clk-imx93.c
+++ b/drivers/clk/imx/clk-imx93.c
@@ -32,6 +32,7 @@ static u32 share_count_sai1;
static u32 share_count_sai2;
static u32 share_count_sai3;
static u32 share_count_mub;
+static u32 share_count_pdm;
static const char * const a55_core_sels[] = {"a55_alt", "arm_pll"};
static const char *parent_names[MAX_SEL][4] = {
@@ -236,7 +237,8 @@ static const struct imx93_clk_ccgr {
{ IMX93_CLK_USB_CONTROLLER_GATE, "usb_controller", "hsio_root", 0x9a00, },
{ IMX93_CLK_USB_TEST_60M_GATE, "usb_test_60m", "hsio_usb_test_60m_root", 0x9a40, },
{ IMX93_CLK_HSIO_TROUT_24M_GATE, "hsio_trout_24m", "osc_24m", 0x9a80, },
- { IMX93_CLK_PDM_GATE, "pdm", "pdm_root", 0x9ac0, },
+ { IMX93_CLK_PDM_GATE, "pdm", "pdm_root", 0x9ac0, 0, &share_count_pdm},
+ { IMX93_CLK_PDM_IPG, "pdm_ipg_clk", "bus_aon_root", 0x9ac0, 0, &share_count_pdm},
{ IMX93_CLK_MQS1_GATE, "mqs1", "sai1_root", 0x9b00, },
{ IMX93_CLK_MQS2_GATE, "mqs2", "sai3_root", 0x9b40, },
{ IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, },
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index 7150c59bbfc9..0d58d85c375e 100644
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -64,8 +64,6 @@ static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
- PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
- PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
};
struct imx_pll14xx_clk imx_1443x_pll = {
@@ -139,11 +137,10 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat
/*
* Fractional PLL constrains:
*
- * a) 6MHz <= prate <= 25MHz
- * b) 1 <= p <= 63 (1 <= p <= 4 prate = 24MHz)
- * c) 64 <= m <= 1023
- * d) 0 <= s <= 6
- * e) -32768 <= k <= 32767
+ * a) 1 <= p <= 63
+ * b) 64 <= m <= 1023
+ * c) 0 <= s <= 6
+ * d) -32768 <= k <= 32767
*
* fvco = (m * 65536 + k) * prate / (p * 65536)
*/
@@ -186,7 +183,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat
}
/* Finally calculate best values */
- for (pdiv = 1; pdiv <= 7; pdiv++) {
+ for (pdiv = 1; pdiv <= 63; pdiv++) {
for (sdiv = 0; sdiv <= 6; sdiv++) {
/* calc mdiv = round(rate * pdiv * 2^sdiv) / prate) */
mdiv = DIV_ROUND_CLOSEST(rate * (pdiv << sdiv), prate);
diff --git a/drivers/clk/imx/clk-pllv4.c b/drivers/clk/imx/clk-pllv4.c
index 6e7e34571fc8..9b136c951762 100644
--- a/drivers/clk/imx/clk-pllv4.c
+++ b/drivers/clk/imx/clk-pllv4.c
@@ -44,11 +44,15 @@ struct clk_pllv4 {
u32 cfg_offset;
u32 num_offset;
u32 denom_offset;
+ bool use_mult_range;
};
/* Valid PLL MULT Table */
static const int pllv4_mult_table[] = {33, 27, 22, 20, 17, 16};
+/* Valid PLL MULT range, (max, min) */
+static const int pllv4_mult_range[] = {54, 27};
+
#define to_clk_pllv4(__hw) container_of(__hw, struct clk_pllv4, hw)
#define LOCK_TIMEOUT_US USEC_PER_MSEC
@@ -94,17 +98,30 @@ static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw,
static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
+ struct clk_pllv4 *pll = to_clk_pllv4(hw);
unsigned long parent_rate = *prate;
unsigned long round_rate, i;
u32 mfn, mfd = DEFAULT_MFD;
bool found = false;
u64 temp64;
-
- for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
- round_rate = parent_rate * pllv4_mult_table[i];
- if (rate >= round_rate) {
+ u32 mult;
+
+ if (pll->use_mult_range) {
+ temp64 = (u64)rate;
+ do_div(temp64, parent_rate);
+ mult = temp64;
+ if (mult >= pllv4_mult_range[1] &&
+ mult <= pllv4_mult_range[0]) {
+ round_rate = parent_rate * mult;
found = true;
- break;
+ }
+ } else {
+ for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
+ round_rate = parent_rate * pllv4_mult_table[i];
+ if (rate >= round_rate) {
+ found = true;
+ break;
+ }
}
}
@@ -138,14 +155,20 @@ static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate,
return round_rate + (u32)temp64;
}
-static bool clk_pllv4_is_valid_mult(unsigned int mult)
+static bool clk_pllv4_is_valid_mult(struct clk_pllv4 *pll, unsigned int mult)
{
int i;
/* check if mult is in valid MULT table */
- for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
- if (pllv4_mult_table[i] == mult)
+ if (pll->use_mult_range) {
+ if (mult >= pllv4_mult_range[1] &&
+ mult <= pllv4_mult_range[0])
return true;
+ } else {
+ for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
+ if (pllv4_mult_table[i] == mult)
+ return true;
+ }
}
return false;
@@ -160,7 +183,7 @@ static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate,
mult = rate / parent_rate;
- if (!clk_pllv4_is_valid_mult(mult))
+ if (!clk_pllv4_is_valid_mult(pll, mult))
return -EINVAL;
if (parent_rate <= MAX_MFD)
@@ -227,10 +250,13 @@ struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name,
pll->base = base;
- if (type == IMX_PLLV4_IMX8ULP) {
+ if (type == IMX_PLLV4_IMX8ULP ||
+ type == IMX_PLLV4_IMX8ULP_1GHZ) {
pll->cfg_offset = IMX8ULP_PLL_CFG_OFFSET;
pll->num_offset = IMX8ULP_PLL_NUM_OFFSET;
pll->denom_offset = IMX8ULP_PLL_DENOM_OFFSET;
+ if (type == IMX_PLLV4_IMX8ULP_1GHZ)
+ pll->use_mult_range = true;
} else {
pll->cfg_offset = PLL_CFG_OFFSET;
pll->num_offset = PLL_NUM_OFFSET;
diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c
index 85041e339515..cd83c52e9952 100644
--- a/drivers/clk/imx/clk-scu.c
+++ b/drivers/clk/imx/clk-scu.c
@@ -9,7 +9,7 @@
#include <linux/bsearch.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
-#include <linux/of_platform.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index af19d9f6aed0..adb7ad649a0d 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -45,6 +45,7 @@ enum imx_pll14xx_type {
enum imx_pllv4_type {
IMX_PLLV4_IMX7ULP,
IMX_PLLV4_IMX8ULP,
+ IMX_PLLV4_IMX8ULP_1GHZ,
};
enum imx_pfdv2_type {
diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c
index d59a7621bb20..ee5c72369334 100644
--- a/drivers/clk/keystone/pll.c
+++ b/drivers/clk/keystone/pll.c
@@ -209,7 +209,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)
}
clk = clk_register_pll(NULL, node->name, parent_name, pll_data);
- if (clk) {
+ if (!IS_ERR_OR_NULL(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
return;
}
diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
index 6c1df4f11536..35fe197dd303 100644
--- a/drivers/clk/keystone/sci-clk.c
+++ b/drivers/clk/keystone/sci-clk.c
@@ -9,8 +9,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/soc/ti/ti_sci_protocol.h>
diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c b/drivers/clk/mediatek/clk-mt2701-aud.c
index 3ce7e71196fd..27eecb6d3a53 100644
--- a/drivers/clk/mediatek/clk-mt2701-aud.c
+++ b/drivers/clk/mediatek/clk-mt2701-aud.c
@@ -7,7 +7,7 @@
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c
index e03ac76279ba..d25687f6c9b4 100644
--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
@@ -6,9 +6,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 4a154da8a543..c81f3e33ce56 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -5,9 +5,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-cpumux.h"
@@ -663,9 +661,8 @@ static int mtk_topckgen_init(struct platform_device *pdev)
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
struct device_node *node = pdev->dev.of_node;
- struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- base = devm_ioremap_resource(&pdev->dev, res);
+ base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
@@ -887,9 +884,8 @@ static int mtk_pericfg_init(struct platform_device *pdev)
void __iomem *base;
int r;
struct device_node *node = pdev->dev.of_node;
- struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- base = devm_ioremap_resource(&pdev->dev, res);
+ base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
index c4cc68c47af9..a8d12a1210fc 100644
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -7,9 +7,7 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/mfd/syscon.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-mt6765.c
index 0377e6dd3206..1f4c8d0c041a 100644
--- a/drivers/clk/mediatek/clk-mt6765.c
+++ b/drivers/clk/mediatek/clk-mt6765.c
@@ -9,7 +9,7 @@
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/mfd/syscon.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
@@ -731,13 +731,10 @@ static int clk_mt6765_apmixed_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
void __iomem *base;
- struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(base)) {
- pr_err("%s(): ioremap failed\n", __func__);
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
return PTR_ERR(base);
- }
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
@@ -766,13 +763,10 @@ static int clk_mt6765_top_probe(struct platform_device *pdev)
struct device_node *node = pdev->dev.of_node;
void __iomem *base;
struct clk_hw_onecell_data *clk_data;
- struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(base)) {
- pr_err("%s(): ioremap failed\n", __func__);
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
return PTR_ERR(base);
- }
clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
@@ -807,13 +801,10 @@ static int clk_mt6765_ifr_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
void __iomem *base;
- struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(base)) {
- pr_err("%s(): ioremap failed\n", __func__);
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
return PTR_ERR(base);
- }
clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
diff --git a/drivers/clk/mediatek/clk-mt6779-aud.c b/drivers/clk/mediatek/clk-mt6779-aud.c
index a97e1117d30b..66ae6421e27e 100644
--- a/drivers/clk/mediatek/clk-mt6779-aud.c
+++ b/drivers/clk/mediatek/clk-mt6779-aud.c
@@ -6,9 +6,7 @@
#include <linux/module.h>
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
index f33fbaee1404..3ee2f5a2319a 100644
--- a/drivers/clk/mediatek/clk-mt6779.c
+++ b/drivers/clk/mediatek/clk-mt6779.c
@@ -6,8 +6,6 @@
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c
index 4c87c0348e5f..2ebd25f0ce71 100644
--- a/drivers/clk/mediatek/clk-mt6797.c
+++ b/drivers/clk/mediatek/clk-mt6797.c
@@ -5,8 +5,6 @@
*/
#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/clk-mt7622-aud.c
index c3ce65ced902..42bade71e2f8 100644
--- a/drivers/clk/mediatek/clk-mt7622-aud.c
+++ b/drivers/clk/mediatek/clk-mt7622-aud.c
@@ -8,7 +8,7 @@
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c
index df81e445026a..62fdf127e77d 100644
--- a/drivers/clk/mediatek/clk-mt7622-eth.c
+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
@@ -6,9 +6,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c
index 9c738d730a7b..b4a520ce362c 100644
--- a/drivers/clk/mediatek/clk-mt7622-hif.c
+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
@@ -6,9 +6,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index fa5fb5891a09..27781a62a131 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -6,9 +6,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-cpumux.h"
diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c
index 1e1c77cc14ba..fe714debdc9e 100644
--- a/drivers/clk/mediatek/clk-mt7629-eth.c
+++ b/drivers/clk/mediatek/clk-mt7629-eth.c
@@ -7,8 +7,6 @@
#include <linux/clk-provider.h>
#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c
index ec3a71ebb766..dd1be946a8f0 100644
--- a/drivers/clk/mediatek/clk-mt7629-hif.c
+++ b/drivers/clk/mediatek/clk-mt7629-hif.c
@@ -6,9 +6,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
index 0893fbbb68cc..2882107d0f24 100644
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -8,8 +8,6 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-cpumux.h"
diff --git a/drivers/clk/mediatek/clk-mt7981-apmixed.c b/drivers/clk/mediatek/clk-mt7981-apmixed.c
index 875813d8b4a9..98739877f430 100644
--- a/drivers/clk/mediatek/clk-mt7981-apmixed.c
+++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c
@@ -8,9 +8,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
diff --git a/drivers/clk/mediatek/clk-mt7981-eth.c b/drivers/clk/mediatek/clk-mt7981-eth.c
index 6bc509a54e14..fb1a8c9242ef 100644
--- a/drivers/clk/mediatek/clk-mt7981-eth.c
+++ b/drivers/clk/mediatek/clk-mt7981-eth.c
@@ -8,9 +8,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt7981-infracfg.c b/drivers/clk/mediatek/clk-mt7981-infracfg.c
index 7e9d3d309151..18bf4e8be457 100644
--- a/drivers/clk/mediatek/clk-mt7981-infracfg.c
+++ b/drivers/clk/mediatek/clk-mt7981-infracfg.c
@@ -8,9 +8,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
diff --git a/drivers/clk/mediatek/clk-mt7981-topckgen.c b/drivers/clk/mediatek/clk-mt7981-topckgen.c
index 4740776e7aab..682f4ca9e89a 100644
--- a/drivers/clk/mediatek/clk-mt7981-topckgen.c
+++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c
@@ -8,9 +8,7 @@
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
diff --git a/drivers/clk/mediatek/clk-mt7986-apmixed.c b/drivers/clk/mediatek/clk-mt7986-apmixed.c
index 6767e9c43886..7f807fbdfcb9 100644
--- a/drivers/clk/mediatek/clk-mt7986-apmixed.c
+++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c
@@ -6,9 +6,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
diff --git a/drivers/clk/mediatek/clk-mt7986-eth.c b/drivers/clk/mediatek/clk-mt7986-eth.c
index 854e2c565041..7ab78e0f49a1 100644
--- a/drivers/clk/mediatek/clk-mt7986-eth.c
+++ b/drivers/clk/mediatek/clk-mt7986-eth.c
@@ -6,9 +6,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt7986-infracfg.c b/drivers/clk/mediatek/clk-mt7986-infracfg.c
index c576e9fb986c..cb8ab3e53abf 100644
--- a/drivers/clk/mediatek/clk-mt7986-infracfg.c
+++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c
@@ -6,9 +6,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
diff --git a/drivers/clk/mediatek/clk-mt7986-topckgen.c b/drivers/clk/mediatek/clk-mt7986-topckgen.c
index af151b016872..84bc24511504 100644
--- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
@@ -6,9 +6,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
diff --git a/drivers/clk/mediatek/clk-mt8167-aud.c b/drivers/clk/mediatek/clk-mt8167-aud.c
index b73058edf3d6..a5181f4eb34a 100644
--- a/drivers/clk/mediatek/clk-mt8167-aud.c
+++ b/drivers/clk/mediatek/clk-mt8167-aud.c
@@ -7,9 +7,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt8167-img.c b/drivers/clk/mediatek/clk-mt8167-img.c
index ba07d20f14b3..02fa52d8aabb 100644
--- a/drivers/clk/mediatek/clk-mt8167-img.c
+++ b/drivers/clk/mediatek/clk-mt8167-img.c
@@ -7,9 +7,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c b/drivers/clk/mediatek/clk-mt8167-mfgcfg.c
index 5f7dbaf97e96..a5b5ee7ac805 100644
--- a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c
+++ b/drivers/clk/mediatek/clk-mt8167-mfgcfg.c
@@ -7,9 +7,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt8167-mm.c b/drivers/clk/mediatek/clk-mt8167-mm.c
index 6472e76567a5..9b0c6b3343b9 100644
--- a/drivers/clk/mediatek/clk-mt8167-mm.c
+++ b/drivers/clk/mediatek/clk-mt8167-mm.c
@@ -7,9 +7,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt8167-vdec.c b/drivers/clk/mediatek/clk-mt8167-vdec.c
index 2f662b3f16a9..1e1e76743180 100644
--- a/drivers/clk/mediatek/clk-mt8167-vdec.c
+++ b/drivers/clk/mediatek/clk-mt8167-vdec.c
@@ -7,9 +7,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt8173-mm.c b/drivers/clk/mediatek/clk-mt8173-mm.c
index ffed6c5bfde2..fd903bee328f 100644
--- a/drivers/clk/mediatek/clk-mt8173-mm.c
+++ b/drivers/clk/mediatek/clk-mt8173-mm.c
@@ -5,7 +5,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index e31f94387d87..6e23461a0455 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -5,9 +5,7 @@
#include <linux/delay.h>
#include <linux/mfd/syscon.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
diff --git a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
index 3c1ace87796b..41ab4d6896a4 100644
--- a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
@@ -5,7 +5,7 @@
*/
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
diff --git a/drivers/clk/mediatek/clk-mt8188-topckgen.c b/drivers/clk/mediatek/clk-mt8188-topckgen.c
index d2eba2d6af8d..e330a4f9a0c3 100644
--- a/drivers/clk/mediatek/clk-mt8188-topckgen.c
+++ b/drivers/clk/mediatek/clk-mt8188-topckgen.c
@@ -5,7 +5,7 @@
*/
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
diff --git a/drivers/clk/mediatek/clk-mt8192-cam.c b/drivers/clk/mediatek/clk-mt8192-cam.c
index 7b9327eba924..a2c0142273a8 100644
--- a/drivers/clk/mediatek/clk-mt8192-cam.c
+++ b/drivers/clk/mediatek/clk-mt8192-cam.c
@@ -4,7 +4,7 @@
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include <linux/clk-provider.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt8192-img.c b/drivers/clk/mediatek/clk-mt8192-img.c
index 0208030c31a0..ee52b5b748e7 100644
--- a/drivers/clk/mediatek/clk-mt8192-img.c
+++ b/drivers/clk/mediatek/clk-mt8192-img.c
@@ -4,7 +4,7 @@
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include <linux/clk-provider.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c
index 275581f8c710..a97b6e8d97ac 100644
--- a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c
+++ b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c
@@ -4,7 +4,7 @@
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include <linux/clk-provider.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt8192-ipe.c b/drivers/clk/mediatek/clk-mt8192-ipe.c
index f3656c3b9573..56ce58ac01ad 100644
--- a/drivers/clk/mediatek/clk-mt8192-ipe.c
+++ b/drivers/clk/mediatek/clk-mt8192-ipe.c
@@ -4,7 +4,7 @@
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include <linux/clk-provider.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt8192-mdp.c b/drivers/clk/mediatek/clk-mt8192-mdp.c
index 5385ac95533a..bad2f3d439f5 100644
--- a/drivers/clk/mediatek/clk-mt8192-mdp.c
+++ b/drivers/clk/mediatek/clk-mt8192-mdp.c
@@ -4,7 +4,7 @@
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include <linux/clk-provider.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt8192-mfg.c b/drivers/clk/mediatek/clk-mt8192-mfg.c
index 0ac7045cf5d1..666b401e778c 100644
--- a/drivers/clk/mediatek/clk-mt8192-mfg.c
+++ b/drivers/clk/mediatek/clk-mt8192-mfg.c
@@ -4,7 +4,7 @@
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include <linux/clk-provider.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt8192-msdc.c b/drivers/clk/mediatek/clk-mt8192-msdc.c
index 9da647c5b8b3..52d6f0babf12 100644
--- a/drivers/clk/mediatek/clk-mt8192-msdc.c
+++ b/drivers/clk/mediatek/clk-mt8192-msdc.c
@@ -4,7 +4,7 @@
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include <linux/clk-provider.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt8192-scp_adsp.c b/drivers/clk/mediatek/clk-mt8192-scp_adsp.c
index 44091147c813..72c8a8722b11 100644
--- a/drivers/clk/mediatek/clk-mt8192-scp_adsp.c
+++ b/drivers/clk/mediatek/clk-mt8192-scp_adsp.c
@@ -4,7 +4,7 @@
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include <linux/clk-provider.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt8192-vdec.c b/drivers/clk/mediatek/clk-mt8192-vdec.c
index d82dee8317b2..cc514068bcdb 100644
--- a/drivers/clk/mediatek/clk-mt8192-vdec.c
+++ b/drivers/clk/mediatek/clk-mt8192-vdec.c
@@ -4,7 +4,7 @@
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include <linux/clk-provider.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt8192-venc.c b/drivers/clk/mediatek/clk-mt8192-venc.c
index b0ef242991e5..9f6fff2dd753 100644
--- a/drivers/clk/mediatek/clk-mt8192-venc.c
+++ b/drivers/clk/mediatek/clk-mt8192-venc.c
@@ -4,7 +4,7 @@
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include <linux/clk-provider.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c
index 462ec4465b50..e395c04632bc 100644
--- a/drivers/clk/mediatek/clk-mt8192.c
+++ b/drivers/clk/mediatek/clk-mt8192.c
@@ -6,9 +6,7 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/mfd/syscon.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
index 502a9dc1fdb8..44a4c85a67ef 100644
--- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
@@ -10,7 +10,7 @@
#include "clk-pllfh.h"
#include <dt-bindings/clock/mt8195-clk.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs apmixed_cg_regs = {
diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c
index 81daa24cadde..5c426a1c94c7 100644
--- a/drivers/clk/mediatek/clk-mt8195-topckgen.c
+++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c
@@ -8,7 +8,7 @@
#include "clk-mux.h"
#include <dt-bindings/clock/mt8195-clk.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
static DEFINE_SPINLOCK(mt8195_clk_lock);
diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c
index 1dca18f99134..ac45e4cc9bcd 100644
--- a/drivers/clk/mediatek/clk-mt8365.c
+++ b/drivers/clk/mediatek/clk-mt8365.c
@@ -10,9 +10,7 @@
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/mfd/syscon.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
diff --git a/drivers/clk/mediatek/clk-mt8516-aud.c b/drivers/clk/mediatek/clk-mt8516-aud.c
index d1e848e78fd5..53e1866fb8e2 100644
--- a/drivers/clk/mediatek/clk-mt8516-aud.c
+++ b/drivers/clk/mediatek/clk-mt8516-aud.c
@@ -7,9 +7,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 8ce846fdbe43..135da8f2d0b1 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -30,14 +30,19 @@ config COMMON_CLK_MESON_VID_PLL_DIV
tristate
select COMMON_CLK_MESON_REGMAP
+config COMMON_CLK_MESON_CLKC_UTILS
+ tristate
+
config COMMON_CLK_MESON_AO_CLKC
tristate
select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_CLKC_UTILS
select RESET_CONTROLLER
config COMMON_CLK_MESON_EE_CLKC
tristate
select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_CLKC_UTILS
config COMMON_CLK_MESON_CPU_DYNDIV
tristate
@@ -48,6 +53,7 @@ config COMMON_CLK_MESON8B
depends on ARM
default y
select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_CLKC_UTILS
select COMMON_CLK_MESON_MPLL
select COMMON_CLK_MESON_PLL
select MFD_SYSCON
@@ -94,6 +100,7 @@ config COMMON_CLK_AXG_AUDIO
select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_PHASE
select COMMON_CLK_MESON_SCLK_DIV
+ select COMMON_CLK_MESON_CLKC_UTILS
select REGMAP_MMIO
help
Support for the audio clock controller on AmLogic A113D devices,
@@ -103,6 +110,7 @@ config COMMON_CLK_A1_PLL
tristate "Amlogic A1 SoC PLL controller support"
depends on ARM64
select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_CLKC_UTILS
select COMMON_CLK_MESON_PLL
help
Support for the PLL clock controller on Amlogic A113L based
@@ -114,6 +122,7 @@ config COMMON_CLK_A1_PERIPHERALS
depends on ARM64
select COMMON_CLK_MESON_DUALDIV
select COMMON_CLK_MESON_REGMAP
+ select COMMON_CLK_MESON_CLKC_UTILS
help
Support for the Peripherals clock controller on Amlogic A113L based
device, A1 SoC Family. Say Y if you want A1 Peripherals clock
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index d5288662881d..cd961cc4f4db 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
# Amlogic clock drivers
+obj-$(CONFIG_COMMON_CLK_MESON_CLKC_UTILS) += meson-clkc-utils.o
obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peripherals.c
index 75dfae210fe5..e2a1f12f9175 100644
--- a/drivers/clk/meson/a1-peripherals.c
+++ b/drivers/clk/meson/a1-peripherals.c
@@ -8,11 +8,14 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "a1-peripherals.h"
#include "clk-dualdiv.h"
#include "clk-regmap.h"
+#include "meson-clkc-utils.h"
+
+#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
static struct clk_regmap xtal_in = {
.data = &(struct clk_regmap_gate_data){
@@ -1866,165 +1869,161 @@ static MESON_GATE(rom, AXI_CLK_EN, 11);
static MESON_GATE(prod_i2c, AXI_CLK_EN, 12);
/* Array of all clocks registered by this provider */
-static struct clk_hw_onecell_data a1_periphs_clks = {
- .hws = {
- [CLKID_XTAL_IN] = &xtal_in.hw,
- [CLKID_FIXPLL_IN] = &fixpll_in.hw,
- [CLKID_USB_PHY_IN] = &usb_phy_in.hw,
- [CLKID_USB_CTRL_IN] = &usb_ctrl_in.hw,
- [CLKID_HIFIPLL_IN] = &hifipll_in.hw,
- [CLKID_SYSPLL_IN] = &syspll_in.hw,
- [CLKID_DDS_IN] = &dds_in.hw,
- [CLKID_SYS] = &sys.hw,
- [CLKID_CLKTREE] = &clktree.hw,
- [CLKID_RESET_CTRL] = &reset_ctrl.hw,
- [CLKID_ANALOG_CTRL] = &analog_ctrl.hw,
- [CLKID_PWR_CTRL] = &pwr_ctrl.hw,
- [CLKID_PAD_CTRL] = &pad_ctrl.hw,
- [CLKID_SYS_CTRL] = &sys_ctrl.hw,
- [CLKID_TEMP_SENSOR] = &temp_sensor.hw,
- [CLKID_AM2AXI_DIV] = &am2axi_dev.hw,
- [CLKID_SPICC_B] = &spicc_b.hw,
- [CLKID_SPICC_A] = &spicc_a.hw,
- [CLKID_MSR] = &msr.hw,
- [CLKID_AUDIO] = &audio.hw,
- [CLKID_JTAG_CTRL] = &jtag_ctrl.hw,
- [CLKID_SARADC_EN] = &saradc_en.hw,
- [CLKID_PWM_EF] = &pwm_ef.hw,
- [CLKID_PWM_CD] = &pwm_cd.hw,
- [CLKID_PWM_AB] = &pwm_ab.hw,
- [CLKID_CEC] = &cec.hw,
- [CLKID_I2C_S] = &i2c_s.hw,
- [CLKID_IR_CTRL] = &ir_ctrl.hw,
- [CLKID_I2C_M_D] = &i2c_m_d.hw,
- [CLKID_I2C_M_C] = &i2c_m_c.hw,
- [CLKID_I2C_M_B] = &i2c_m_b.hw,
- [CLKID_I2C_M_A] = &i2c_m_a.hw,
- [CLKID_ACODEC] = &acodec.hw,
- [CLKID_OTP] = &otp.hw,
- [CLKID_SD_EMMC_A] = &sd_emmc_a.hw,
- [CLKID_USB_PHY] = &usb_phy.hw,
- [CLKID_USB_CTRL] = &usb_ctrl.hw,
- [CLKID_SYS_DSPB] = &sys_dspb.hw,
- [CLKID_SYS_DSPA] = &sys_dspa.hw,
- [CLKID_DMA] = &dma.hw,
- [CLKID_IRQ_CTRL] = &irq_ctrl.hw,
- [CLKID_NIC] = &nic.hw,
- [CLKID_GIC] = &gic.hw,
- [CLKID_UART_C] = &uart_c.hw,
- [CLKID_UART_B] = &uart_b.hw,
- [CLKID_UART_A] = &uart_a.hw,
- [CLKID_SYS_PSRAM] = &sys_psram.hw,
- [CLKID_RSA] = &rsa.hw,
- [CLKID_CORESIGHT] = &coresight.hw,
- [CLKID_AM2AXI_VAD] = &am2axi_vad.hw,
- [CLKID_AUDIO_VAD] = &audio_vad.hw,
- [CLKID_AXI_DMC] = &axi_dmc.hw,
- [CLKID_AXI_PSRAM] = &axi_psram.hw,
- [CLKID_RAMB] = &ramb.hw,
- [CLKID_RAMA] = &rama.hw,
- [CLKID_AXI_SPIFC] = &axi_spifc.hw,
- [CLKID_AXI_NIC] = &axi_nic.hw,
- [CLKID_AXI_DMA] = &axi_dma.hw,
- [CLKID_CPU_CTRL] = &cpu_ctrl.hw,
- [CLKID_ROM] = &rom.hw,
- [CLKID_PROC_I2C] = &prod_i2c.hw,
- [CLKID_DSPA_SEL] = &dspa_sel.hw,
- [CLKID_DSPB_SEL] = &dspb_sel.hw,
- [CLKID_DSPA_EN] = &dspa_en.hw,
- [CLKID_DSPA_EN_NIC] = &dspa_en_nic.hw,
- [CLKID_DSPB_EN] = &dspb_en.hw,
- [CLKID_DSPB_EN_NIC] = &dspb_en_nic.hw,
- [CLKID_RTC] = &rtc.hw,
- [CLKID_CECA_32K] = &ceca_32k_out.hw,
- [CLKID_CECB_32K] = &cecb_32k_out.hw,
- [CLKID_24M] = &clk_24m.hw,
- [CLKID_12M] = &clk_12m.hw,
- [CLKID_FCLK_DIV2_DIVN] = &fclk_div2_divn.hw,
- [CLKID_GEN] = &gen.hw,
- [CLKID_SARADC_SEL] = &saradc_sel.hw,
- [CLKID_SARADC] = &saradc.hw,
- [CLKID_PWM_A] = &pwm_a.hw,
- [CLKID_PWM_B] = &pwm_b.hw,
- [CLKID_PWM_C] = &pwm_c.hw,
- [CLKID_PWM_D] = &pwm_d.hw,
- [CLKID_PWM_E] = &pwm_e.hw,
- [CLKID_PWM_F] = &pwm_f.hw,
- [CLKID_SPICC] = &spicc.hw,
- [CLKID_TS] = &ts.hw,
- [CLKID_SPIFC] = &spifc.hw,
- [CLKID_USB_BUS] = &usb_bus.hw,
- [CLKID_SD_EMMC] = &sd_emmc.hw,
- [CLKID_PSRAM] = &psram.hw,
- [CLKID_DMC] = &dmc.hw,
- [CLKID_SYS_A_SEL] = &sys_a_sel.hw,
- [CLKID_SYS_A_DIV] = &sys_a_div.hw,
- [CLKID_SYS_A] = &sys_a.hw,
- [CLKID_SYS_B_SEL] = &sys_b_sel.hw,
- [CLKID_SYS_B_DIV] = &sys_b_div.hw,
- [CLKID_SYS_B] = &sys_b.hw,
- [CLKID_DSPA_A_SEL] = &dspa_a_sel.hw,
- [CLKID_DSPA_A_DIV] = &dspa_a_div.hw,
- [CLKID_DSPA_A] = &dspa_a.hw,
- [CLKID_DSPA_B_SEL] = &dspa_b_sel.hw,
- [CLKID_DSPA_B_DIV] = &dspa_b_div.hw,
- [CLKID_DSPA_B] = &dspa_b.hw,
- [CLKID_DSPB_A_SEL] = &dspb_a_sel.hw,
- [CLKID_DSPB_A_DIV] = &dspb_a_div.hw,
- [CLKID_DSPB_A] = &dspb_a.hw,
- [CLKID_DSPB_B_SEL] = &dspb_b_sel.hw,
- [CLKID_DSPB_B_DIV] = &dspb_b_div.hw,
- [CLKID_DSPB_B] = &dspb_b.hw,
- [CLKID_RTC_32K_IN] = &rtc_32k_in.hw,
- [CLKID_RTC_32K_DIV] = &rtc_32k_div.hw,
- [CLKID_RTC_32K_XTAL] = &rtc_32k_xtal.hw,
- [CLKID_RTC_32K_SEL] = &rtc_32k_sel.hw,
- [CLKID_CECB_32K_IN] = &cecb_32k_in.hw,
- [CLKID_CECB_32K_DIV] = &cecb_32k_div.hw,
- [CLKID_CECB_32K_SEL_PRE] = &cecb_32k_sel_pre.hw,
- [CLKID_CECB_32K_SEL] = &cecb_32k_sel.hw,
- [CLKID_CECA_32K_IN] = &ceca_32k_in.hw,
- [CLKID_CECA_32K_DIV] = &ceca_32k_div.hw,
- [CLKID_CECA_32K_SEL_PRE] = &ceca_32k_sel_pre.hw,
- [CLKID_CECA_32K_SEL] = &ceca_32k_sel.hw,
- [CLKID_DIV2_PRE] = &fclk_div2_divn_pre.hw,
- [CLKID_24M_DIV2] = &clk_24m_div2.hw,
- [CLKID_GEN_SEL] = &gen_sel.hw,
- [CLKID_GEN_DIV] = &gen_div.hw,
- [CLKID_SARADC_DIV] = &saradc_div.hw,
- [CLKID_PWM_A_SEL] = &pwm_a_sel.hw,
- [CLKID_PWM_A_DIV] = &pwm_a_div.hw,
- [CLKID_PWM_B_SEL] = &pwm_b_sel.hw,
- [CLKID_PWM_B_DIV] = &pwm_b_div.hw,
- [CLKID_PWM_C_SEL] = &pwm_c_sel.hw,
- [CLKID_PWM_C_DIV] = &pwm_c_div.hw,
- [CLKID_PWM_D_SEL] = &pwm_d_sel.hw,
- [CLKID_PWM_D_DIV] = &pwm_d_div.hw,
- [CLKID_PWM_E_SEL] = &pwm_e_sel.hw,
- [CLKID_PWM_E_DIV] = &pwm_e_div.hw,
- [CLKID_PWM_F_SEL] = &pwm_f_sel.hw,
- [CLKID_PWM_F_DIV] = &pwm_f_div.hw,
- [CLKID_SPICC_SEL] = &spicc_sel.hw,
- [CLKID_SPICC_DIV] = &spicc_div.hw,
- [CLKID_SPICC_SEL2] = &spicc_sel2.hw,
- [CLKID_TS_DIV] = &ts_div.hw,
- [CLKID_SPIFC_SEL] = &spifc_sel.hw,
- [CLKID_SPIFC_DIV] = &spifc_div.hw,
- [CLKID_SPIFC_SEL2] = &spifc_sel2.hw,
- [CLKID_USB_BUS_SEL] = &usb_bus_sel.hw,
- [CLKID_USB_BUS_DIV] = &usb_bus_div.hw,
- [CLKID_SD_EMMC_SEL] = &sd_emmc_sel.hw,
- [CLKID_SD_EMMC_DIV] = &sd_emmc_div.hw,
- [CLKID_SD_EMMC_SEL2] = &sd_emmc_sel2.hw,
- [CLKID_PSRAM_SEL] = &psram_sel.hw,
- [CLKID_PSRAM_DIV] = &psram_div.hw,
- [CLKID_PSRAM_SEL2] = &psram_sel2.hw,
- [CLKID_DMC_SEL] = &dmc_sel.hw,
- [CLKID_DMC_DIV] = &dmc_div.hw,
- [CLKID_DMC_SEL2] = &dmc_sel2.hw,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
+static struct clk_hw *a1_periphs_hw_clks[] = {
+ [CLKID_XTAL_IN] = &xtal_in.hw,
+ [CLKID_FIXPLL_IN] = &fixpll_in.hw,
+ [CLKID_USB_PHY_IN] = &usb_phy_in.hw,
+ [CLKID_USB_CTRL_IN] = &usb_ctrl_in.hw,
+ [CLKID_HIFIPLL_IN] = &hifipll_in.hw,
+ [CLKID_SYSPLL_IN] = &syspll_in.hw,
+ [CLKID_DDS_IN] = &dds_in.hw,
+ [CLKID_SYS] = &sys.hw,
+ [CLKID_CLKTREE] = &clktree.hw,
+ [CLKID_RESET_CTRL] = &reset_ctrl.hw,
+ [CLKID_ANALOG_CTRL] = &analog_ctrl.hw,
+ [CLKID_PWR_CTRL] = &pwr_ctrl.hw,
+ [CLKID_PAD_CTRL] = &pad_ctrl.hw,
+ [CLKID_SYS_CTRL] = &sys_ctrl.hw,
+ [CLKID_TEMP_SENSOR] = &temp_sensor.hw,
+ [CLKID_AM2AXI_DIV] = &am2axi_dev.hw,
+ [CLKID_SPICC_B] = &spicc_b.hw,
+ [CLKID_SPICC_A] = &spicc_a.hw,
+ [CLKID_MSR] = &msr.hw,
+ [CLKID_AUDIO] = &audio.hw,
+ [CLKID_JTAG_CTRL] = &jtag_ctrl.hw,
+ [CLKID_SARADC_EN] = &saradc_en.hw,
+ [CLKID_PWM_EF] = &pwm_ef.hw,
+ [CLKID_PWM_CD] = &pwm_cd.hw,
+ [CLKID_PWM_AB] = &pwm_ab.hw,
+ [CLKID_CEC] = &cec.hw,
+ [CLKID_I2C_S] = &i2c_s.hw,
+ [CLKID_IR_CTRL] = &ir_ctrl.hw,
+ [CLKID_I2C_M_D] = &i2c_m_d.hw,
+ [CLKID_I2C_M_C] = &i2c_m_c.hw,
+ [CLKID_I2C_M_B] = &i2c_m_b.hw,
+ [CLKID_I2C_M_A] = &i2c_m_a.hw,
+ [CLKID_ACODEC] = &acodec.hw,
+ [CLKID_OTP] = &otp.hw,
+ [CLKID_SD_EMMC_A] = &sd_emmc_a.hw,
+ [CLKID_USB_PHY] = &usb_phy.hw,
+ [CLKID_USB_CTRL] = &usb_ctrl.hw,
+ [CLKID_SYS_DSPB] = &sys_dspb.hw,
+ [CLKID_SYS_DSPA] = &sys_dspa.hw,
+ [CLKID_DMA] = &dma.hw,
+ [CLKID_IRQ_CTRL] = &irq_ctrl.hw,
+ [CLKID_NIC] = &nic.hw,
+ [CLKID_GIC] = &gic.hw,
+ [CLKID_UART_C] = &uart_c.hw,
+ [CLKID_UART_B] = &uart_b.hw,
+ [CLKID_UART_A] = &uart_a.hw,
+ [CLKID_SYS_PSRAM] = &sys_psram.hw,
+ [CLKID_RSA] = &rsa.hw,
+ [CLKID_CORESIGHT] = &coresight.hw,
+ [CLKID_AM2AXI_VAD] = &am2axi_vad.hw,
+ [CLKID_AUDIO_VAD] = &audio_vad.hw,
+ [CLKID_AXI_DMC] = &axi_dmc.hw,
+ [CLKID_AXI_PSRAM] = &axi_psram.hw,
+ [CLKID_RAMB] = &ramb.hw,
+ [CLKID_RAMA] = &rama.hw,
+ [CLKID_AXI_SPIFC] = &axi_spifc.hw,
+ [CLKID_AXI_NIC] = &axi_nic.hw,
+ [CLKID_AXI_DMA] = &axi_dma.hw,
+ [CLKID_CPU_CTRL] = &cpu_ctrl.hw,
+ [CLKID_ROM] = &rom.hw,
+ [CLKID_PROC_I2C] = &prod_i2c.hw,
+ [CLKID_DSPA_SEL] = &dspa_sel.hw,
+ [CLKID_DSPB_SEL] = &dspb_sel.hw,
+ [CLKID_DSPA_EN] = &dspa_en.hw,
+ [CLKID_DSPA_EN_NIC] = &dspa_en_nic.hw,
+ [CLKID_DSPB_EN] = &dspb_en.hw,
+ [CLKID_DSPB_EN_NIC] = &dspb_en_nic.hw,
+ [CLKID_RTC] = &rtc.hw,
+ [CLKID_CECA_32K] = &ceca_32k_out.hw,
+ [CLKID_CECB_32K] = &cecb_32k_out.hw,
+ [CLKID_24M] = &clk_24m.hw,
+ [CLKID_12M] = &clk_12m.hw,
+ [CLKID_FCLK_DIV2_DIVN] = &fclk_div2_divn.hw,
+ [CLKID_GEN] = &gen.hw,
+ [CLKID_SARADC_SEL] = &saradc_sel.hw,
+ [CLKID_SARADC] = &saradc.hw,
+ [CLKID_PWM_A] = &pwm_a.hw,
+ [CLKID_PWM_B] = &pwm_b.hw,
+ [CLKID_PWM_C] = &pwm_c.hw,
+ [CLKID_PWM_D] = &pwm_d.hw,
+ [CLKID_PWM_E] = &pwm_e.hw,
+ [CLKID_PWM_F] = &pwm_f.hw,
+ [CLKID_SPICC] = &spicc.hw,
+ [CLKID_TS] = &ts.hw,
+ [CLKID_SPIFC] = &spifc.hw,
+ [CLKID_USB_BUS] = &usb_bus.hw,
+ [CLKID_SD_EMMC] = &sd_emmc.hw,
+ [CLKID_PSRAM] = &psram.hw,
+ [CLKID_DMC] = &dmc.hw,
+ [CLKID_SYS_A_SEL] = &sys_a_sel.hw,
+ [CLKID_SYS_A_DIV] = &sys_a_div.hw,
+ [CLKID_SYS_A] = &sys_a.hw,
+ [CLKID_SYS_B_SEL] = &sys_b_sel.hw,
+ [CLKID_SYS_B_DIV] = &sys_b_div.hw,
+ [CLKID_SYS_B] = &sys_b.hw,
+ [CLKID_DSPA_A_SEL] = &dspa_a_sel.hw,
+ [CLKID_DSPA_A_DIV] = &dspa_a_div.hw,
+ [CLKID_DSPA_A] = &dspa_a.hw,
+ [CLKID_DSPA_B_SEL] = &dspa_b_sel.hw,
+ [CLKID_DSPA_B_DIV] = &dspa_b_div.hw,
+ [CLKID_DSPA_B] = &dspa_b.hw,
+ [CLKID_DSPB_A_SEL] = &dspb_a_sel.hw,
+ [CLKID_DSPB_A_DIV] = &dspb_a_div.hw,
+ [CLKID_DSPB_A] = &dspb_a.hw,
+ [CLKID_DSPB_B_SEL] = &dspb_b_sel.hw,
+ [CLKID_DSPB_B_DIV] = &dspb_b_div.hw,
+ [CLKID_DSPB_B] = &dspb_b.hw,
+ [CLKID_RTC_32K_IN] = &rtc_32k_in.hw,
+ [CLKID_RTC_32K_DIV] = &rtc_32k_div.hw,
+ [CLKID_RTC_32K_XTAL] = &rtc_32k_xtal.hw,
+ [CLKID_RTC_32K_SEL] = &rtc_32k_sel.hw,
+ [CLKID_CECB_32K_IN] = &cecb_32k_in.hw,
+ [CLKID_CECB_32K_DIV] = &cecb_32k_div.hw,
+ [CLKID_CECB_32K_SEL_PRE] = &cecb_32k_sel_pre.hw,
+ [CLKID_CECB_32K_SEL] = &cecb_32k_sel.hw,
+ [CLKID_CECA_32K_IN] = &ceca_32k_in.hw,
+ [CLKID_CECA_32K_DIV] = &ceca_32k_div.hw,
+ [CLKID_CECA_32K_SEL_PRE] = &ceca_32k_sel_pre.hw,
+ [CLKID_CECA_32K_SEL] = &ceca_32k_sel.hw,
+ [CLKID_DIV2_PRE] = &fclk_div2_divn_pre.hw,
+ [CLKID_24M_DIV2] = &clk_24m_div2.hw,
+ [CLKID_GEN_SEL] = &gen_sel.hw,
+ [CLKID_GEN_DIV] = &gen_div.hw,
+ [CLKID_SARADC_DIV] = &saradc_div.hw,
+ [CLKID_PWM_A_SEL] = &pwm_a_sel.hw,
+ [CLKID_PWM_A_DIV] = &pwm_a_div.hw,
+ [CLKID_PWM_B_SEL] = &pwm_b_sel.hw,
+ [CLKID_PWM_B_DIV] = &pwm_b_div.hw,
+ [CLKID_PWM_C_SEL] = &pwm_c_sel.hw,
+ [CLKID_PWM_C_DIV] = &pwm_c_div.hw,
+ [CLKID_PWM_D_SEL] = &pwm_d_sel.hw,
+ [CLKID_PWM_D_DIV] = &pwm_d_div.hw,
+ [CLKID_PWM_E_SEL] = &pwm_e_sel.hw,
+ [CLKID_PWM_E_DIV] = &pwm_e_div.hw,
+ [CLKID_PWM_F_SEL] = &pwm_f_sel.hw,
+ [CLKID_PWM_F_DIV] = &pwm_f_div.hw,
+ [CLKID_SPICC_SEL] = &spicc_sel.hw,
+ [CLKID_SPICC_DIV] = &spicc_div.hw,
+ [CLKID_SPICC_SEL2] = &spicc_sel2.hw,
+ [CLKID_TS_DIV] = &ts_div.hw,
+ [CLKID_SPIFC_SEL] = &spifc_sel.hw,
+ [CLKID_SPIFC_DIV] = &spifc_div.hw,
+ [CLKID_SPIFC_SEL2] = &spifc_sel2.hw,
+ [CLKID_USB_BUS_SEL] = &usb_bus_sel.hw,
+ [CLKID_USB_BUS_DIV] = &usb_bus_div.hw,
+ [CLKID_SD_EMMC_SEL] = &sd_emmc_sel.hw,
+ [CLKID_SD_EMMC_DIV] = &sd_emmc_div.hw,
+ [CLKID_SD_EMMC_SEL2] = &sd_emmc_sel2.hw,
+ [CLKID_PSRAM_SEL] = &psram_sel.hw,
+ [CLKID_PSRAM_DIV] = &psram_div.hw,
+ [CLKID_PSRAM_SEL2] = &psram_sel2.hw,
+ [CLKID_DMC_SEL] = &dmc_sel.hw,
+ [CLKID_DMC_DIV] = &dmc_div.hw,
+ [CLKID_DMC_SEL2] = &dmc_sel2.hw,
};
/* Convenience table to populate regmap in .probe */
@@ -2190,6 +2189,11 @@ static struct regmap_config a1_periphs_regmap_cfg = {
.reg_stride = 4,
};
+static struct meson_clk_hw_data a1_periphs_clks = {
+ .hws = a1_periphs_hw_clks,
+ .num = ARRAY_SIZE(a1_periphs_hw_clks),
+};
+
static int meson_a1_periphs_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -2219,8 +2223,7 @@ static int meson_a1_periphs_probe(struct platform_device *pdev)
clkid);
}
- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
- &a1_periphs_clks);
+ return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &a1_periphs_clks);
}
static const struct of_device_id a1_periphs_clkc_match_table[] = {
diff --git a/drivers/clk/meson/a1-peripherals.h b/drivers/clk/meson/a1-peripherals.h
index 526fc9ba5c9f..26de8530184a 100644
--- a/drivers/clk/meson/a1-peripherals.h
+++ b/drivers/clk/meson/a1-peripherals.h
@@ -43,71 +43,4 @@
#define PSRAM_CLK_CTRL 0xf4
#define DMC_CLK_CTRL 0xf8
-/* include the CLKIDs that have been made part of the DT binding */
-#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
-
-/*
- * CLKID index values for internal clocks
- *
- * These indices are entirely contrived and do not map onto the hardware.
- * It has now been decided to expose everything by default in the DT header:
- * include/dt-bindings/clock/a1-peripherals-clkc.h.
- * Only the clocks ids we don't want to expose, such as the internal muxes and
- * dividers of composite clocks, will remain defined here.
- */
-#define CLKID_XTAL_IN 0
-#define CLKID_DSPA_SEL 61
-#define CLKID_DSPB_SEL 62
-#define CLKID_SARADC_SEL 74
-#define CLKID_SYS_A_SEL 89
-#define CLKID_SYS_A_DIV 90
-#define CLKID_SYS_A 91
-#define CLKID_SYS_B_SEL 92
-#define CLKID_SYS_B_DIV 93
-#define CLKID_SYS_B 94
-#define CLKID_DSPA_A_DIV 96
-#define CLKID_DSPA_A 97
-#define CLKID_DSPA_B_DIV 99
-#define CLKID_DSPA_B 100
-#define CLKID_DSPB_A_DIV 102
-#define CLKID_DSPB_A 103
-#define CLKID_DSPB_B_DIV 105
-#define CLKID_DSPB_B 106
-#define CLKID_RTC_32K_IN 107
-#define CLKID_RTC_32K_DIV 108
-#define CLKID_RTC_32K_XTAL 109
-#define CLKID_RTC_32K_SEL 110
-#define CLKID_CECB_32K_IN 111
-#define CLKID_CECB_32K_DIV 112
-#define CLKID_CECA_32K_IN 115
-#define CLKID_CECA_32K_DIV 116
-#define CLKID_DIV2_PRE 119
-#define CLKID_24M_DIV2 120
-#define CLKID_GEN_DIV 122
-#define CLKID_SARADC_DIV 123
-#define CLKID_PWM_A_DIV 125
-#define CLKID_PWM_B_DIV 127
-#define CLKID_PWM_C_DIV 129
-#define CLKID_PWM_D_DIV 131
-#define CLKID_PWM_E_DIV 133
-#define CLKID_PWM_F_DIV 135
-#define CLKID_SPICC_SEL 136
-#define CLKID_SPICC_DIV 137
-#define CLKID_SPICC_SEL2 138
-#define CLKID_TS_DIV 139
-#define CLKID_SPIFC_SEL 140
-#define CLKID_SPIFC_DIV 141
-#define CLKID_SPIFC_SEL2 142
-#define CLKID_USB_BUS_SEL 143
-#define CLKID_USB_BUS_DIV 144
-#define CLKID_SD_EMMC_SEL 145
-#define CLKID_SD_EMMC_DIV 146
-#define CLKID_PSRAM_SEL 148
-#define CLKID_PSRAM_DIV 149
-#define CLKID_PSRAM_SEL2 150
-#define CLKID_DMC_SEL 151
-#define CLKID_DMC_DIV 152
-#define CLKID_DMC_SEL2 153
-#define NR_CLKS 154
-
#endif /* __A1_PERIPHERALS_H */
diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c
index bd2f1d1ec6e4..4325e8a6a3ef 100644
--- a/drivers/clk/meson/a1-pll.c
+++ b/drivers/clk/meson/a1-pll.c
@@ -8,10 +8,13 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "a1-pll.h"
#include "clk-regmap.h"
+#include "meson-clkc-utils.h"
+
+#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
static struct clk_regmap fixed_pll_dco = {
.data = &(struct meson_clk_pll_data){
@@ -268,22 +271,18 @@ static struct clk_regmap fclk_div7 = {
};
/* Array of all clocks registered by this provider */
-static struct clk_hw_onecell_data a1_pll_clks = {
- .hws = {
- [CLKID_FIXED_PLL_DCO] = &fixed_pll_dco.hw,
- [CLKID_FIXED_PLL] = &fixed_pll.hw,
- [CLKID_FCLK_DIV2_DIV] = &fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &fclk_div3_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &fclk_div7_div.hw,
- [CLKID_FCLK_DIV2] = &fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &fclk_div3.hw,
- [CLKID_FCLK_DIV5] = &fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &fclk_div7.hw,
- [CLKID_HIFI_PLL] = &hifi_pll.hw,
- [NR_PLL_CLKS] = NULL,
- },
- .num = NR_PLL_CLKS,
+static struct clk_hw *a1_pll_hw_clks[] = {
+ [CLKID_FIXED_PLL_DCO] = &fixed_pll_dco.hw,
+ [CLKID_FIXED_PLL] = &fixed_pll.hw,
+ [CLKID_FCLK_DIV2_DIV] = &fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &fclk_div3_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &fclk_div7_div.hw,
+ [CLKID_FCLK_DIV2] = &fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &fclk_div3.hw,
+ [CLKID_FCLK_DIV5] = &fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &fclk_div7.hw,
+ [CLKID_HIFI_PLL] = &hifi_pll.hw,
};
static struct clk_regmap *const a1_pll_regmaps[] = {
@@ -302,6 +301,11 @@ static struct regmap_config a1_pll_regmap_cfg = {
.reg_stride = 4,
};
+static struct meson_clk_hw_data a1_pll_clks = {
+ .hws = a1_pll_hw_clks,
+ .num = ARRAY_SIZE(a1_pll_hw_clks),
+};
+
static int meson_a1_pll_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -332,7 +336,7 @@ static int meson_a1_pll_probe(struct platform_device *pdev)
clkid);
}
- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+ return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get,
&a1_pll_clks);
}
diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h
index 29726651b056..4be17b2bf383 100644
--- a/drivers/clk/meson/a1-pll.h
+++ b/drivers/clk/meson/a1-pll.h
@@ -25,23 +25,4 @@
#define ANACTRL_HIFIPLL_CTRL4 0xd0
#define ANACTRL_HIFIPLL_STS 0xd4
-/* include the CLKIDs that have been made part of the DT binding */
-#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
-
-/*
- * CLKID index values for internal clocks
- *
- * These indices are entirely contrived and do not map onto the hardware.
- * It has now been decided to expose everything by default in the DT header:
- * include/dt-bindings/clock/a1-pll-clkc.h. Only the clocks ids we don't want
- * to expose, such as the internal muxes and dividers of composite clocks,
- * will remain defined here.
- */
-#define CLKID_FIXED_PLL_DCO 0
-#define CLKID_FCLK_DIV2_DIV 2
-#define CLKID_FCLK_DIV3_DIV 3
-#define CLKID_FCLK_DIV5_DIV 4
-#define CLKID_FCLK_DIV7_DIV 5
-#define NR_PLL_CLKS 11
-
#endif /* __A1_PLL_H */
diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
index af6db437bcd8..d80ab4728f7a 100644
--- a/drivers/clk/meson/axg-aoclk.c
+++ b/drivers/clk/meson/axg-aoclk.c
@@ -14,11 +14,13 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include "meson-aoclk.h"
-#include "axg-aoclk.h"
#include "clk-regmap.h"
#include "clk-dualdiv.h"
+#include <dt-bindings/clock/axg-aoclkc.h>
+#include <dt-bindings/reset/axg-aoclkc.h>
+
/*
* AO Configuration Clock registers offsets
* Register offsets from the data sheet must be multiplied by 4.
@@ -288,27 +290,24 @@ static struct clk_regmap *axg_aoclk_regmap[] = {
&axg_aoclk_saradc_gate,
};
-static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
- .hws = {
- [CLKID_AO_REMOTE] = &axg_aoclk_remote.hw,
- [CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master.hw,
- [CLKID_AO_I2C_SLAVE] = &axg_aoclk_i2c_slave.hw,
- [CLKID_AO_UART1] = &axg_aoclk_uart1.hw,
- [CLKID_AO_UART2] = &axg_aoclk_uart2.hw,
- [CLKID_AO_IR_BLASTER] = &axg_aoclk_ir_blaster.hw,
- [CLKID_AO_SAR_ADC] = &axg_aoclk_saradc.hw,
- [CLKID_AO_CLK81] = &axg_aoclk_clk81.hw,
- [CLKID_AO_SAR_ADC_SEL] = &axg_aoclk_saradc_mux.hw,
- [CLKID_AO_SAR_ADC_DIV] = &axg_aoclk_saradc_div.hw,
- [CLKID_AO_SAR_ADC_CLK] = &axg_aoclk_saradc_gate.hw,
- [CLKID_AO_CTS_OSCIN] = &axg_aoclk_cts_oscin.hw,
- [CLKID_AO_32K_PRE] = &axg_aoclk_32k_pre.hw,
- [CLKID_AO_32K_DIV] = &axg_aoclk_32k_div.hw,
- [CLKID_AO_32K_SEL] = &axg_aoclk_32k_sel.hw,
- [CLKID_AO_32K] = &axg_aoclk_32k.hw,
- [CLKID_AO_CTS_RTC_OSCIN] = &axg_aoclk_cts_rtc_oscin.hw,
- },
- .num = NR_CLKS,
+static struct clk_hw *axg_aoclk_hw_clks[] = {
+ [CLKID_AO_REMOTE] = &axg_aoclk_remote.hw,
+ [CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master.hw,
+ [CLKID_AO_I2C_SLAVE] = &axg_aoclk_i2c_slave.hw,
+ [CLKID_AO_UART1] = &axg_aoclk_uart1.hw,
+ [CLKID_AO_UART2] = &axg_aoclk_uart2.hw,
+ [CLKID_AO_IR_BLASTER] = &axg_aoclk_ir_blaster.hw,
+ [CLKID_AO_SAR_ADC] = &axg_aoclk_saradc.hw,
+ [CLKID_AO_CLK81] = &axg_aoclk_clk81.hw,
+ [CLKID_AO_SAR_ADC_SEL] = &axg_aoclk_saradc_mux.hw,
+ [CLKID_AO_SAR_ADC_DIV] = &axg_aoclk_saradc_div.hw,
+ [CLKID_AO_SAR_ADC_CLK] = &axg_aoclk_saradc_gate.hw,
+ [CLKID_AO_CTS_OSCIN] = &axg_aoclk_cts_oscin.hw,
+ [CLKID_AO_32K_PRE] = &axg_aoclk_32k_pre.hw,
+ [CLKID_AO_32K_DIV] = &axg_aoclk_32k_div.hw,
+ [CLKID_AO_32K_SEL] = &axg_aoclk_32k_sel.hw,
+ [CLKID_AO_32K] = &axg_aoclk_32k.hw,
+ [CLKID_AO_CTS_RTC_OSCIN] = &axg_aoclk_cts_rtc_oscin.hw,
};
static const struct meson_aoclk_data axg_aoclkc_data = {
@@ -317,7 +316,10 @@ static const struct meson_aoclk_data axg_aoclkc_data = {
.reset = axg_aoclk_reset,
.num_clks = ARRAY_SIZE(axg_aoclk_regmap),
.clks = axg_aoclk_regmap,
- .hw_data = &axg_aoclk_onecell_data,
+ .hw_clks = {
+ .hws = axg_aoclk_hw_clks,
+ .num = ARRAY_SIZE(axg_aoclk_hw_clks),
+ },
};
static const struct of_device_id axg_aoclkc_match_table[] = {
diff --git a/drivers/clk/meson/axg-aoclk.h b/drivers/clk/meson/axg-aoclk.h
deleted file mode 100644
index 3cc27e85170f..000000000000
--- a/drivers/clk/meson/axg-aoclk.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (c) 2017 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * Copyright (c) 2018 Amlogic, inc.
- * Author: Qiufang Dai <qiufang.dai@amlogic.com>
- */
-
-#ifndef __AXG_AOCLKC_H
-#define __AXG_AOCLKC_H
-
-#define NR_CLKS 17
-
-#include <dt-bindings/clock/axg-aoclkc.h>
-#include <dt-bindings/reset/axg-aoclkc.h>
-
-#endif /* __AXG_AOCLKC_H */
diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index 5016682e47c8..ac3482960903 100644
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@ -7,19 +7,22 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/init.h>
-#include <linux/of_device.h>
#include <linux/module.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
+#include "meson-clkc-utils.h"
#include "axg-audio.h"
#include "clk-regmap.h"
#include "clk-phase.h"
#include "sclk-div.h"
+#include <dt-bindings/clock/axg-audio-clkc.h>
+
#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \
.data = &(struct clk_regmap_gate_data){ \
.offset = (_reg), \
@@ -811,436 +814,424 @@ static struct clk_regmap sm1_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
* Array of all clocks provided by this provider
* The input clocks of the controller will be populated at runtime
*/
-static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
- .hws = {
- [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
- [AUD_CLKID_PDM] = &pdm.hw,
- [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
- [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
- [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
- [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
- [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
- [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
- [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
- [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
- [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
- [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
- [AUD_CLKID_TODDR_A] = &toddr_a.hw,
- [AUD_CLKID_TODDR_B] = &toddr_b.hw,
- [AUD_CLKID_TODDR_C] = &toddr_c.hw,
- [AUD_CLKID_LOOPBACK] = &loopback.hw,
- [AUD_CLKID_SPDIFIN] = &spdifin.hw,
- [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
- [AUD_CLKID_RESAMPLE] = &resample.hw,
- [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
- [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
- [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
- [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
- [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
- [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
- [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
- [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
- [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
- [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
- [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
- [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
- [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
- [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
- [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
- [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
- [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
- [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
- [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
- [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
- [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
- [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
- [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
- [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
- [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
- [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
- [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
- [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
- [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
- [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
- [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
- [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
- [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
- [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
- [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
- [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
- [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
- [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
- [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
- [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
- [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
- [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
- [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
- [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
- [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
- [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
- [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
- [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
- [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
- [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
- [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
- [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
- [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
- [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
- [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
- [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
- [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
- [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
- [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
- [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
- [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
- [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
- [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
- [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
- [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
- [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
- [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
- [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
- [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
- [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
- [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
- [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
- [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
- [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
- [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
- [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
- [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
- [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
- [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
- [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
- [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
- [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
- [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
- [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
- [AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw,
- [AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw,
- [AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw,
- [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
- [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
- [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
- [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
- [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
- [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
- [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
- [AUD_CLKID_TOP] = &axg_aud_top,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
+static struct clk_hw *axg_audio_hw_clks[] = {
+ [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
+ [AUD_CLKID_PDM] = &pdm.hw,
+ [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
+ [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
+ [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
+ [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
+ [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
+ [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
+ [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
+ [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
+ [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
+ [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
+ [AUD_CLKID_TODDR_A] = &toddr_a.hw,
+ [AUD_CLKID_TODDR_B] = &toddr_b.hw,
+ [AUD_CLKID_TODDR_C] = &toddr_c.hw,
+ [AUD_CLKID_LOOPBACK] = &loopback.hw,
+ [AUD_CLKID_SPDIFIN] = &spdifin.hw,
+ [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
+ [AUD_CLKID_RESAMPLE] = &resample.hw,
+ [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
+ [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
+ [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
+ [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
+ [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
+ [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
+ [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
+ [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
+ [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
+ [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
+ [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
+ [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
+ [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
+ [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
+ [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
+ [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
+ [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
+ [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
+ [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
+ [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
+ [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
+ [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
+ [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
+ [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
+ [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
+ [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
+ [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
+ [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
+ [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
+ [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
+ [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
+ [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
+ [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
+ [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
+ [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
+ [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
+ [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
+ [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
+ [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
+ [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
+ [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
+ [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
+ [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
+ [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
+ [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
+ [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
+ [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
+ [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
+ [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
+ [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
+ [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
+ [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
+ [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
+ [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
+ [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
+ [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
+ [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
+ [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
+ [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
+ [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
+ [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
+ [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
+ [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
+ [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
+ [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
+ [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
+ [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
+ [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
+ [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
+ [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw,
+ [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
+ [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
+ [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
+ [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
+ [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
+ [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
+ [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
+ [AUD_CLKID_TOP] = &axg_aud_top,
};
/*
* Array of all G12A clocks provided by this provider
* The input clocks of the controller will be populated at runtime
*/
-static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
- .hws = {
- [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
- [AUD_CLKID_PDM] = &pdm.hw,
- [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
- [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
- [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
- [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
- [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
- [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
- [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
- [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
- [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
- [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
- [AUD_CLKID_TODDR_A] = &toddr_a.hw,
- [AUD_CLKID_TODDR_B] = &toddr_b.hw,
- [AUD_CLKID_TODDR_C] = &toddr_c.hw,
- [AUD_CLKID_LOOPBACK] = &loopback.hw,
- [AUD_CLKID_SPDIFIN] = &spdifin.hw,
- [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
- [AUD_CLKID_RESAMPLE] = &resample.hw,
- [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
- [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
- [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
- [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
- [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
- [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
- [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
- [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
- [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
- [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
- [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
- [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
- [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
- [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
- [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
- [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
- [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
- [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
- [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
- [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
- [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
- [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
- [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
- [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
- [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
- [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
- [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
- [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
- [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
- [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
- [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
- [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
- [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
- [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
- [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
- [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
- [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
- [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
- [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
- [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
- [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
- [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
- [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
- [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
- [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
- [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
- [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
- [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
- [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
- [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
- [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
- [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
- [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
- [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
- [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
- [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
- [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
- [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
- [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
- [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
- [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
- [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
- [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
- [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
- [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
- [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
- [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
- [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
- [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
- [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
- [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
- [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
- [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
- [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
- [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
- [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
- [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
- [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
- [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
- [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
- [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
- [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
- [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
- [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
- [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
- [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
- [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
- [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
- [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
- [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
- [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
- [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
- [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
- [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
- [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
- [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
- [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
- [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
- [AUD_CLKID_TDM_MCLK_PAD0] = &g12a_tdm_mclk_pad_0.hw,
- [AUD_CLKID_TDM_MCLK_PAD1] = &g12a_tdm_mclk_pad_1.hw,
- [AUD_CLKID_TDM_LRCLK_PAD0] = &g12a_tdm_lrclk_pad_0.hw,
- [AUD_CLKID_TDM_LRCLK_PAD1] = &g12a_tdm_lrclk_pad_1.hw,
- [AUD_CLKID_TDM_LRCLK_PAD2] = &g12a_tdm_lrclk_pad_2.hw,
- [AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw,
- [AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw,
- [AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw,
- [AUD_CLKID_TOP] = &axg_aud_top,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
+static struct clk_hw *g12a_audio_hw_clks[] = {
+ [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
+ [AUD_CLKID_PDM] = &pdm.hw,
+ [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
+ [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
+ [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
+ [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
+ [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
+ [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
+ [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
+ [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
+ [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
+ [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
+ [AUD_CLKID_TODDR_A] = &toddr_a.hw,
+ [AUD_CLKID_TODDR_B] = &toddr_b.hw,
+ [AUD_CLKID_TODDR_C] = &toddr_c.hw,
+ [AUD_CLKID_LOOPBACK] = &loopback.hw,
+ [AUD_CLKID_SPDIFIN] = &spdifin.hw,
+ [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
+ [AUD_CLKID_RESAMPLE] = &resample.hw,
+ [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
+ [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
+ [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
+ [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
+ [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
+ [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
+ [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
+ [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
+ [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
+ [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
+ [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
+ [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
+ [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
+ [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
+ [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
+ [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
+ [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
+ [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
+ [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
+ [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
+ [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
+ [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
+ [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
+ [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
+ [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
+ [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
+ [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
+ [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
+ [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
+ [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
+ [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
+ [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
+ [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
+ [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
+ [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
+ [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
+ [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
+ [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
+ [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
+ [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
+ [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
+ [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
+ [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
+ [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
+ [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
+ [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
+ [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
+ [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
+ [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
+ [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
+ [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
+ [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
+ [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
+ [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
+ [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
+ [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
+ [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
+ [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
+ [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
+ [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
+ [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
+ [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
+ [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
+ [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
+ [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
+ [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
+ [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
+ [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
+ [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
+ [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
+ [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
+ [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
+ [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
+ [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
+ [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
+ [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
+ [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
+ [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
+ [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
+ [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
+ [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
+ [AUD_CLKID_TDM_MCLK_PAD0] = &g12a_tdm_mclk_pad_0.hw,
+ [AUD_CLKID_TDM_MCLK_PAD1] = &g12a_tdm_mclk_pad_1.hw,
+ [AUD_CLKID_TDM_LRCLK_PAD0] = &g12a_tdm_lrclk_pad_0.hw,
+ [AUD_CLKID_TDM_LRCLK_PAD1] = &g12a_tdm_lrclk_pad_1.hw,
+ [AUD_CLKID_TDM_LRCLK_PAD2] = &g12a_tdm_lrclk_pad_2.hw,
+ [AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw,
+ [AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw,
+ [AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw,
+ [AUD_CLKID_TOP] = &axg_aud_top,
};
/*
* Array of all SM1 clocks provided by this provider
* The input clocks of the controller will be populated at runtime
*/
-static struct clk_hw_onecell_data sm1_audio_hw_onecell_data = {
- .hws = {
- [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
- [AUD_CLKID_PDM] = &pdm.hw,
- [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
- [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
- [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
- [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
- [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
- [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
- [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
- [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
- [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
- [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
- [AUD_CLKID_TODDR_A] = &toddr_a.hw,
- [AUD_CLKID_TODDR_B] = &toddr_b.hw,
- [AUD_CLKID_TODDR_C] = &toddr_c.hw,
- [AUD_CLKID_LOOPBACK] = &loopback.hw,
- [AUD_CLKID_SPDIFIN] = &spdifin.hw,
- [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
- [AUD_CLKID_RESAMPLE] = &resample.hw,
- [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
- [AUD_CLKID_MST_A_MCLK_SEL] = &sm1_mst_a_mclk_sel.hw,
- [AUD_CLKID_MST_B_MCLK_SEL] = &sm1_mst_b_mclk_sel.hw,
- [AUD_CLKID_MST_C_MCLK_SEL] = &sm1_mst_c_mclk_sel.hw,
- [AUD_CLKID_MST_D_MCLK_SEL] = &sm1_mst_d_mclk_sel.hw,
- [AUD_CLKID_MST_E_MCLK_SEL] = &sm1_mst_e_mclk_sel.hw,
- [AUD_CLKID_MST_F_MCLK_SEL] = &sm1_mst_f_mclk_sel.hw,
- [AUD_CLKID_MST_A_MCLK_DIV] = &sm1_mst_a_mclk_div.hw,
- [AUD_CLKID_MST_B_MCLK_DIV] = &sm1_mst_b_mclk_div.hw,
- [AUD_CLKID_MST_C_MCLK_DIV] = &sm1_mst_c_mclk_div.hw,
- [AUD_CLKID_MST_D_MCLK_DIV] = &sm1_mst_d_mclk_div.hw,
- [AUD_CLKID_MST_E_MCLK_DIV] = &sm1_mst_e_mclk_div.hw,
- [AUD_CLKID_MST_F_MCLK_DIV] = &sm1_mst_f_mclk_div.hw,
- [AUD_CLKID_MST_A_MCLK] = &sm1_mst_a_mclk.hw,
- [AUD_CLKID_MST_B_MCLK] = &sm1_mst_b_mclk.hw,
- [AUD_CLKID_MST_C_MCLK] = &sm1_mst_c_mclk.hw,
- [AUD_CLKID_MST_D_MCLK] = &sm1_mst_d_mclk.hw,
- [AUD_CLKID_MST_E_MCLK] = &sm1_mst_e_mclk.hw,
- [AUD_CLKID_MST_F_MCLK] = &sm1_mst_f_mclk.hw,
- [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
- [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
- [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
- [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
- [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
- [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
- [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
- [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
- [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
- [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
- [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
- [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
- [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
- [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
- [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
- [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
- [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
- [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
- [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
- [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
- [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
- [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
- [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
- [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
- [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
- [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
- [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
- [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
- [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
- [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
- [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
- [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
- [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
- [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
- [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
- [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
- [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
- [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
- [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
- [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
- [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
- [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
- [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
- [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
- [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
- [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
- [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
- [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
- [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
- [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
- [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
- [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
- [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
- [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
- [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
- [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
- [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
- [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
- [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
- [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
- [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
- [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
- [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
- [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
- [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
- [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
- [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
- [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
- [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
- [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
- [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
- [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
- [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
- [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
- [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
- [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
- [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
- [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
- [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
- [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
- [AUD_CLKID_TDM_MCLK_PAD0] = &sm1_tdm_mclk_pad_0.hw,
- [AUD_CLKID_TDM_MCLK_PAD1] = &sm1_tdm_mclk_pad_1.hw,
- [AUD_CLKID_TDM_LRCLK_PAD0] = &sm1_tdm_lrclk_pad_0.hw,
- [AUD_CLKID_TDM_LRCLK_PAD1] = &sm1_tdm_lrclk_pad_1.hw,
- [AUD_CLKID_TDM_LRCLK_PAD2] = &sm1_tdm_lrclk_pad_2.hw,
- [AUD_CLKID_TDM_SCLK_PAD0] = &sm1_tdm_sclk_pad_0.hw,
- [AUD_CLKID_TDM_SCLK_PAD1] = &sm1_tdm_sclk_pad_1.hw,
- [AUD_CLKID_TDM_SCLK_PAD2] = &sm1_tdm_sclk_pad_2.hw,
- [AUD_CLKID_TOP] = &sm1_aud_top.hw,
- [AUD_CLKID_TORAM] = &toram.hw,
- [AUD_CLKID_EQDRC] = &eqdrc.hw,
- [AUD_CLKID_RESAMPLE_B] = &resample_b.hw,
- [AUD_CLKID_TOVAD] = &tovad.hw,
- [AUD_CLKID_LOCKER] = &locker.hw,
- [AUD_CLKID_SPDIFIN_LB] = &spdifin_lb.hw,
- [AUD_CLKID_FRDDR_D] = &frddr_d.hw,
- [AUD_CLKID_TODDR_D] = &toddr_d.hw,
- [AUD_CLKID_LOOPBACK_B] = &loopback_b.hw,
- [AUD_CLKID_CLK81_EN] = &sm1_clk81_en.hw,
- [AUD_CLKID_SYSCLK_A_DIV] = &sm1_sysclk_a_div.hw,
- [AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw,
- [AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw,
- [AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
+static struct clk_hw *sm1_audio_hw_clks[] = {
+ [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
+ [AUD_CLKID_PDM] = &pdm.hw,
+ [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
+ [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
+ [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
+ [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
+ [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
+ [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
+ [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
+ [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
+ [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
+ [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
+ [AUD_CLKID_TODDR_A] = &toddr_a.hw,
+ [AUD_CLKID_TODDR_B] = &toddr_b.hw,
+ [AUD_CLKID_TODDR_C] = &toddr_c.hw,
+ [AUD_CLKID_LOOPBACK] = &loopback.hw,
+ [AUD_CLKID_SPDIFIN] = &spdifin.hw,
+ [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
+ [AUD_CLKID_RESAMPLE] = &resample.hw,
+ [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
+ [AUD_CLKID_MST_A_MCLK_SEL] = &sm1_mst_a_mclk_sel.hw,
+ [AUD_CLKID_MST_B_MCLK_SEL] = &sm1_mst_b_mclk_sel.hw,
+ [AUD_CLKID_MST_C_MCLK_SEL] = &sm1_mst_c_mclk_sel.hw,
+ [AUD_CLKID_MST_D_MCLK_SEL] = &sm1_mst_d_mclk_sel.hw,
+ [AUD_CLKID_MST_E_MCLK_SEL] = &sm1_mst_e_mclk_sel.hw,
+ [AUD_CLKID_MST_F_MCLK_SEL] = &sm1_mst_f_mclk_sel.hw,
+ [AUD_CLKID_MST_A_MCLK_DIV] = &sm1_mst_a_mclk_div.hw,
+ [AUD_CLKID_MST_B_MCLK_DIV] = &sm1_mst_b_mclk_div.hw,
+ [AUD_CLKID_MST_C_MCLK_DIV] = &sm1_mst_c_mclk_div.hw,
+ [AUD_CLKID_MST_D_MCLK_DIV] = &sm1_mst_d_mclk_div.hw,
+ [AUD_CLKID_MST_E_MCLK_DIV] = &sm1_mst_e_mclk_div.hw,
+ [AUD_CLKID_MST_F_MCLK_DIV] = &sm1_mst_f_mclk_div.hw,
+ [AUD_CLKID_MST_A_MCLK] = &sm1_mst_a_mclk.hw,
+ [AUD_CLKID_MST_B_MCLK] = &sm1_mst_b_mclk.hw,
+ [AUD_CLKID_MST_C_MCLK] = &sm1_mst_c_mclk.hw,
+ [AUD_CLKID_MST_D_MCLK] = &sm1_mst_d_mclk.hw,
+ [AUD_CLKID_MST_E_MCLK] = &sm1_mst_e_mclk.hw,
+ [AUD_CLKID_MST_F_MCLK] = &sm1_mst_f_mclk.hw,
+ [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
+ [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
+ [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
+ [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
+ [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
+ [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
+ [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
+ [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
+ [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
+ [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
+ [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
+ [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
+ [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
+ [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
+ [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
+ [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
+ [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
+ [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
+ [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
+ [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
+ [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
+ [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
+ [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
+ [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
+ [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
+ [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
+ [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
+ [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
+ [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
+ [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
+ [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
+ [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
+ [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
+ [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
+ [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
+ [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
+ [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
+ [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
+ [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
+ [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
+ [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
+ [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
+ [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
+ [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
+ [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
+ [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
+ [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
+ [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
+ [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
+ [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
+ [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
+ [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
+ [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
+ [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
+ [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
+ [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
+ [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
+ [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
+ [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
+ [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
+ [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
+ [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
+ [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
+ [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
+ [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
+ [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
+ [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
+ [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
+ [AUD_CLKID_TDM_MCLK_PAD0] = &sm1_tdm_mclk_pad_0.hw,
+ [AUD_CLKID_TDM_MCLK_PAD1] = &sm1_tdm_mclk_pad_1.hw,
+ [AUD_CLKID_TDM_LRCLK_PAD0] = &sm1_tdm_lrclk_pad_0.hw,
+ [AUD_CLKID_TDM_LRCLK_PAD1] = &sm1_tdm_lrclk_pad_1.hw,
+ [AUD_CLKID_TDM_LRCLK_PAD2] = &sm1_tdm_lrclk_pad_2.hw,
+ [AUD_CLKID_TDM_SCLK_PAD0] = &sm1_tdm_sclk_pad_0.hw,
+ [AUD_CLKID_TDM_SCLK_PAD1] = &sm1_tdm_sclk_pad_1.hw,
+ [AUD_CLKID_TDM_SCLK_PAD2] = &sm1_tdm_sclk_pad_2.hw,
+ [AUD_CLKID_TOP] = &sm1_aud_top.hw,
+ [AUD_CLKID_TORAM] = &toram.hw,
+ [AUD_CLKID_EQDRC] = &eqdrc.hw,
+ [AUD_CLKID_RESAMPLE_B] = &resample_b.hw,
+ [AUD_CLKID_TOVAD] = &tovad.hw,
+ [AUD_CLKID_LOCKER] = &locker.hw,
+ [AUD_CLKID_SPDIFIN_LB] = &spdifin_lb.hw,
+ [AUD_CLKID_FRDDR_D] = &frddr_d.hw,
+ [AUD_CLKID_TODDR_D] = &toddr_d.hw,
+ [AUD_CLKID_LOOPBACK_B] = &loopback_b.hw,
+ [AUD_CLKID_CLK81_EN] = &sm1_clk81_en.hw,
+ [AUD_CLKID_SYSCLK_A_DIV] = &sm1_sysclk_a_div.hw,
+ [AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw,
+ [AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw,
+ [AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw,
};
@@ -1745,7 +1736,7 @@ static const struct regmap_config axg_audio_regmap_cfg = {
struct audioclk_data {
struct clk_regmap *const *regmap_clks;
unsigned int regmap_clk_num;
- struct clk_hw_onecell_data *hw_onecell_data;
+ struct meson_clk_hw_data hw_clks;
unsigned int reset_offset;
unsigned int reset_num;
};
@@ -1791,10 +1782,10 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
data->regmap_clks[i]->map = map;
/* Take care to skip the registered input clocks */
- for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) {
+ for (i = AUD_CLKID_DDR_ARB; i < data->hw_clks.num; i++) {
const char *name;
- hw = data->hw_onecell_data->hws[i];
+ hw = data->hw_clks.hws[i];
/* array might be sparse */
if (!hw)
continue;
@@ -1808,8 +1799,7 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
}
}
- ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
- data->hw_onecell_data);
+ ret = devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
if (ret)
return ret;
@@ -1834,13 +1824,19 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
static const struct audioclk_data axg_audioclk_data = {
.regmap_clks = axg_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
- .hw_onecell_data = &axg_audio_hw_onecell_data,
+ .hw_clks = {
+ .hws = axg_audio_hw_clks,
+ .num = ARRAY_SIZE(axg_audio_hw_clks),
+ },
};
static const struct audioclk_data g12a_audioclk_data = {
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
- .hw_onecell_data = &g12a_audio_hw_onecell_data,
+ .hw_clks = {
+ .hws = g12a_audio_hw_clks,
+ .num = ARRAY_SIZE(g12a_audio_hw_clks),
+ },
.reset_offset = AUDIO_SW_RESET,
.reset_num = 26,
};
@@ -1848,7 +1844,10 @@ static const struct audioclk_data g12a_audioclk_data = {
static const struct audioclk_data sm1_audioclk_data = {
.regmap_clks = sm1_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps),
- .hw_onecell_data = &sm1_audio_hw_onecell_data,
+ .hw_clks = {
+ .hws = sm1_audio_hw_clks,
+ .num = ARRAY_SIZE(sm1_audio_hw_clks),
+ },
.reset_offset = AUDIO_SM1_SW_RESET0,
.reset_num = 39,
};
diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h
index fd65a7d0704b..01a3da19933e 100644
--- a/drivers/clk/meson/axg-audio.h
+++ b/drivers/clk/meson/axg-audio.h
@@ -64,80 +64,5 @@
#define AUDIO_SM1_SW_RESET1 0x02C
#define AUDIO_CLK81_CTRL 0x030
#define AUDIO_CLK81_EN 0x034
-/*
- * CLKID index values
- * These indices are entirely contrived and do not map onto the hardware.
- */
-
-#define AUD_CLKID_MST_A_MCLK_SEL 59
-#define AUD_CLKID_MST_B_MCLK_SEL 60
-#define AUD_CLKID_MST_C_MCLK_SEL 61
-#define AUD_CLKID_MST_D_MCLK_SEL 62
-#define AUD_CLKID_MST_E_MCLK_SEL 63
-#define AUD_CLKID_MST_F_MCLK_SEL 64
-#define AUD_CLKID_MST_A_MCLK_DIV 65
-#define AUD_CLKID_MST_B_MCLK_DIV 66
-#define AUD_CLKID_MST_C_MCLK_DIV 67
-#define AUD_CLKID_MST_D_MCLK_DIV 68
-#define AUD_CLKID_MST_E_MCLK_DIV 69
-#define AUD_CLKID_MST_F_MCLK_DIV 70
-#define AUD_CLKID_SPDIFOUT_CLK_SEL 71
-#define AUD_CLKID_SPDIFOUT_CLK_DIV 72
-#define AUD_CLKID_SPDIFIN_CLK_SEL 73
-#define AUD_CLKID_SPDIFIN_CLK_DIV 74
-#define AUD_CLKID_PDM_DCLK_SEL 75
-#define AUD_CLKID_PDM_DCLK_DIV 76
-#define AUD_CLKID_PDM_SYSCLK_SEL 77
-#define AUD_CLKID_PDM_SYSCLK_DIV 78
-#define AUD_CLKID_MST_A_SCLK_PRE_EN 92
-#define AUD_CLKID_MST_B_SCLK_PRE_EN 93
-#define AUD_CLKID_MST_C_SCLK_PRE_EN 94
-#define AUD_CLKID_MST_D_SCLK_PRE_EN 95
-#define AUD_CLKID_MST_E_SCLK_PRE_EN 96
-#define AUD_CLKID_MST_F_SCLK_PRE_EN 97
-#define AUD_CLKID_MST_A_SCLK_DIV 98
-#define AUD_CLKID_MST_B_SCLK_DIV 99
-#define AUD_CLKID_MST_C_SCLK_DIV 100
-#define AUD_CLKID_MST_D_SCLK_DIV 101
-#define AUD_CLKID_MST_E_SCLK_DIV 102
-#define AUD_CLKID_MST_F_SCLK_DIV 103
-#define AUD_CLKID_MST_A_SCLK_POST_EN 104
-#define AUD_CLKID_MST_B_SCLK_POST_EN 105
-#define AUD_CLKID_MST_C_SCLK_POST_EN 106
-#define AUD_CLKID_MST_D_SCLK_POST_EN 107
-#define AUD_CLKID_MST_E_SCLK_POST_EN 108
-#define AUD_CLKID_MST_F_SCLK_POST_EN 109
-#define AUD_CLKID_MST_A_LRCLK_DIV 110
-#define AUD_CLKID_MST_B_LRCLK_DIV 111
-#define AUD_CLKID_MST_C_LRCLK_DIV 112
-#define AUD_CLKID_MST_D_LRCLK_DIV 113
-#define AUD_CLKID_MST_E_LRCLK_DIV 114
-#define AUD_CLKID_MST_F_LRCLK_DIV 115
-#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 137
-#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 138
-#define AUD_CLKID_TDMIN_C_SCLK_PRE_EN 139
-#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 140
-#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 141
-#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 142
-#define AUD_CLKID_TDMOUT_C_SCLK_PRE_EN 143
-#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 144
-#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 145
-#define AUD_CLKID_TDMIN_C_SCLK_POST_EN 146
-#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 147
-#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148
-#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149
-#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150
-#define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153
-#define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154
-#define AUD_CLKID_CLK81_EN 173
-#define AUD_CLKID_SYSCLK_A_DIV 174
-#define AUD_CLKID_SYSCLK_B_DIV 175
-#define AUD_CLKID_SYSCLK_A_EN 176
-#define AUD_CLKID_SYSCLK_B_EN 177
-
-/* include the CLKIDs which are part of the DT bindings */
-#include <dt-bindings/clock/axg-audio-clkc.h>
-
-#define NR_CLKS 178
#endif /*__AXG_AUDIO_CLKC_H */
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 2ad3801398dc..c12f81dfa674 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -11,7 +11,7 @@
#include <linux/clk-provider.h>
#include <linux/init.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/module.h>
@@ -21,6 +21,8 @@
#include "axg.h"
#include "meson-eeclk.h"
+#include <dt-bindings/clock/axg-clkc.h>
+
static DEFINE_SPINLOCK(meson_clk_lock);
static struct clk_regmap axg_fixed_pll_dco = {
@@ -1890,147 +1892,143 @@ static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
/* Array of all clocks provided by this provider */
-static struct clk_hw_onecell_data axg_hw_onecell_data = {
- .hws = {
- [CLKID_SYS_PLL] = &axg_sys_pll.hw,
- [CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
- [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
- [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
- [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
- [CLKID_GP0_PLL] = &axg_gp0_pll.hw,
- [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
- [CLKID_CLK81] = &axg_clk81.hw,
- [CLKID_MPLL0] = &axg_mpll0.hw,
- [CLKID_MPLL1] = &axg_mpll1.hw,
- [CLKID_MPLL2] = &axg_mpll2.hw,
- [CLKID_MPLL3] = &axg_mpll3.hw,
- [CLKID_DDR] = &axg_ddr.hw,
- [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
- [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
- [CLKID_ISA] = &axg_isa.hw,
- [CLKID_PL301] = &axg_pl301.hw,
- [CLKID_PERIPHS] = &axg_periphs.hw,
- [CLKID_SPICC0] = &axg_spicc_0.hw,
- [CLKID_I2C] = &axg_i2c.hw,
- [CLKID_RNG0] = &axg_rng0.hw,
- [CLKID_UART0] = &axg_uart0.hw,
- [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
- [CLKID_SPICC1] = &axg_spicc_1.hw,
- [CLKID_PCIE_A] = &axg_pcie_a.hw,
- [CLKID_PCIE_B] = &axg_pcie_b.hw,
- [CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
- [CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
- [CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
- [CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
- [CLKID_DMA] = &axg_dma.hw,
- [CLKID_SPI] = &axg_spi.hw,
- [CLKID_AUDIO] = &axg_audio.hw,
- [CLKID_ETH] = &axg_eth_core.hw,
- [CLKID_UART1] = &axg_uart1.hw,
- [CLKID_G2D] = &axg_g2d.hw,
- [CLKID_USB0] = &axg_usb0.hw,
- [CLKID_USB1] = &axg_usb1.hw,
- [CLKID_RESET] = &axg_reset.hw,
- [CLKID_USB] = &axg_usb_general.hw,
- [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
- [CLKID_EFUSE] = &axg_efuse.hw,
- [CLKID_BOOT_ROM] = &axg_boot_rom.hw,
- [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
- [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
- [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
- [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
- [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
- [CLKID_VPU_INTR] = &axg_vpu_intr.hw,
- [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
- [CLKID_GIC] = &axg_gic.hw,
- [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
- [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
- [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
- [CLKID_AO_IFACE] = &axg_ao_iface.hw,
- [CLKID_AO_I2C] = &axg_ao_i2c.hw,
- [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
- [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
- [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
- [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
- [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
- [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
- [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,
- [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
- [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
- [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
- [CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
- [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
- [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw,
- [CLKID_PCIE_PLL] = &axg_pcie_pll.hw,
- [CLKID_PCIE_MUX] = &axg_pcie_mux.hw,
- [CLKID_PCIE_REF] = &axg_pcie_ref.hw,
- [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
- [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
- [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
- [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
- [CLKID_GEN_CLK] = &axg_gen_clk.hw,
- [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw,
- [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw,
- [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw,
- [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
- [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
- [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
- [CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw,
- [CLKID_VPU_0_SEL] = &axg_vpu_0_sel.hw,
- [CLKID_VPU_0] = &axg_vpu_0.hw,
- [CLKID_VPU_1_DIV] = &axg_vpu_1_div.hw,
- [CLKID_VPU_1_SEL] = &axg_vpu_1_sel.hw,
- [CLKID_VPU_1] = &axg_vpu_1.hw,
- [CLKID_VPU] = &axg_vpu.hw,
- [CLKID_VAPB_0_DIV] = &axg_vapb_0_div.hw,
- [CLKID_VAPB_0_SEL] = &axg_vapb_0_sel.hw,
- [CLKID_VAPB_0] = &axg_vapb_0.hw,
- [CLKID_VAPB_1_DIV] = &axg_vapb_1_div.hw,
- [CLKID_VAPB_1_SEL] = &axg_vapb_1_sel.hw,
- [CLKID_VAPB_1] = &axg_vapb_1.hw,
- [CLKID_VAPB_SEL] = &axg_vapb_sel.hw,
- [CLKID_VAPB] = &axg_vapb.hw,
- [CLKID_VCLK] = &axg_vclk.hw,
- [CLKID_VCLK2] = &axg_vclk2.hw,
- [CLKID_VCLK_SEL] = &axg_vclk_sel.hw,
- [CLKID_VCLK2_SEL] = &axg_vclk2_sel.hw,
- [CLKID_VCLK_INPUT] = &axg_vclk_input.hw,
- [CLKID_VCLK2_INPUT] = &axg_vclk2_input.hw,
- [CLKID_VCLK_DIV] = &axg_vclk_div.hw,
- [CLKID_VCLK2_DIV] = &axg_vclk2_div.hw,
- [CLKID_VCLK_DIV2_EN] = &axg_vclk_div2_en.hw,
- [CLKID_VCLK_DIV4_EN] = &axg_vclk_div4_en.hw,
- [CLKID_VCLK_DIV6_EN] = &axg_vclk_div6_en.hw,
- [CLKID_VCLK_DIV12_EN] = &axg_vclk_div12_en.hw,
- [CLKID_VCLK2_DIV2_EN] = &axg_vclk2_div2_en.hw,
- [CLKID_VCLK2_DIV4_EN] = &axg_vclk2_div4_en.hw,
- [CLKID_VCLK2_DIV6_EN] = &axg_vclk2_div6_en.hw,
- [CLKID_VCLK2_DIV12_EN] = &axg_vclk2_div12_en.hw,
- [CLKID_VCLK_DIV1] = &axg_vclk_div1.hw,
- [CLKID_VCLK_DIV2] = &axg_vclk_div2.hw,
- [CLKID_VCLK_DIV4] = &axg_vclk_div4.hw,
- [CLKID_VCLK_DIV6] = &axg_vclk_div6.hw,
- [CLKID_VCLK_DIV12] = &axg_vclk_div12.hw,
- [CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw,
- [CLKID_VCLK2_DIV2] = &axg_vclk2_div2.hw,
- [CLKID_VCLK2_DIV4] = &axg_vclk2_div4.hw,
- [CLKID_VCLK2_DIV6] = &axg_vclk2_div6.hw,
- [CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw,
- [CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw,
- [CLKID_CTS_ENCL] = &axg_cts_encl.hw,
- [CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw,
- [CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw,
- [CLKID_VDIN_MEAS] = &axg_vdin_meas.hw,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
+static struct clk_hw *axg_hw_clks[] = {
+ [CLKID_SYS_PLL] = &axg_sys_pll.hw,
+ [CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
+ [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
+ [CLKID_GP0_PLL] = &axg_gp0_pll.hw,
+ [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &axg_clk81.hw,
+ [CLKID_MPLL0] = &axg_mpll0.hw,
+ [CLKID_MPLL1] = &axg_mpll1.hw,
+ [CLKID_MPLL2] = &axg_mpll2.hw,
+ [CLKID_MPLL3] = &axg_mpll3.hw,
+ [CLKID_DDR] = &axg_ddr.hw,
+ [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
+ [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
+ [CLKID_ISA] = &axg_isa.hw,
+ [CLKID_PL301] = &axg_pl301.hw,
+ [CLKID_PERIPHS] = &axg_periphs.hw,
+ [CLKID_SPICC0] = &axg_spicc_0.hw,
+ [CLKID_I2C] = &axg_i2c.hw,
+ [CLKID_RNG0] = &axg_rng0.hw,
+ [CLKID_UART0] = &axg_uart0.hw,
+ [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
+ [CLKID_SPICC1] = &axg_spicc_1.hw,
+ [CLKID_PCIE_A] = &axg_pcie_a.hw,
+ [CLKID_PCIE_B] = &axg_pcie_b.hw,
+ [CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
+ [CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
+ [CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
+ [CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
+ [CLKID_DMA] = &axg_dma.hw,
+ [CLKID_SPI] = &axg_spi.hw,
+ [CLKID_AUDIO] = &axg_audio.hw,
+ [CLKID_ETH] = &axg_eth_core.hw,
+ [CLKID_UART1] = &axg_uart1.hw,
+ [CLKID_G2D] = &axg_g2d.hw,
+ [CLKID_USB0] = &axg_usb0.hw,
+ [CLKID_USB1] = &axg_usb1.hw,
+ [CLKID_RESET] = &axg_reset.hw,
+ [CLKID_USB] = &axg_usb_general.hw,
+ [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
+ [CLKID_EFUSE] = &axg_efuse.hw,
+ [CLKID_BOOT_ROM] = &axg_boot_rom.hw,
+ [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
+ [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
+ [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
+ [CLKID_VPU_INTR] = &axg_vpu_intr.hw,
+ [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
+ [CLKID_GIC] = &axg_gic.hw,
+ [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
+ [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
+ [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
+ [CLKID_AO_IFACE] = &axg_ao_iface.hw,
+ [CLKID_AO_I2C] = &axg_ao_i2c.hw,
+ [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
+ [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
+ [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
+ [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
+ [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
+ [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
+ [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,
+ [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
+ [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
+ [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
+ [CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
+ [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
+ [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw,
+ [CLKID_PCIE_PLL] = &axg_pcie_pll.hw,
+ [CLKID_PCIE_MUX] = &axg_pcie_mux.hw,
+ [CLKID_PCIE_REF] = &axg_pcie_ref.hw,
+ [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
+ [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
+ [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
+ [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
+ [CLKID_GEN_CLK] = &axg_gen_clk.hw,
+ [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw,
+ [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw,
+ [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw,
+ [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
+ [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
+ [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
+ [CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw,
+ [CLKID_VPU_0_SEL] = &axg_vpu_0_sel.hw,
+ [CLKID_VPU_0] = &axg_vpu_0.hw,
+ [CLKID_VPU_1_DIV] = &axg_vpu_1_div.hw,
+ [CLKID_VPU_1_SEL] = &axg_vpu_1_sel.hw,
+ [CLKID_VPU_1] = &axg_vpu_1.hw,
+ [CLKID_VPU] = &axg_vpu.hw,
+ [CLKID_VAPB_0_DIV] = &axg_vapb_0_div.hw,
+ [CLKID_VAPB_0_SEL] = &axg_vapb_0_sel.hw,
+ [CLKID_VAPB_0] = &axg_vapb_0.hw,
+ [CLKID_VAPB_1_DIV] = &axg_vapb_1_div.hw,
+ [CLKID_VAPB_1_SEL] = &axg_vapb_1_sel.hw,
+ [CLKID_VAPB_1] = &axg_vapb_1.hw,
+ [CLKID_VAPB_SEL] = &axg_vapb_sel.hw,
+ [CLKID_VAPB] = &axg_vapb.hw,
+ [CLKID_VCLK] = &axg_vclk.hw,
+ [CLKID_VCLK2] = &axg_vclk2.hw,
+ [CLKID_VCLK_SEL] = &axg_vclk_sel.hw,
+ [CLKID_VCLK2_SEL] = &axg_vclk2_sel.hw,
+ [CLKID_VCLK_INPUT] = &axg_vclk_input.hw,
+ [CLKID_VCLK2_INPUT] = &axg_vclk2_input.hw,
+ [CLKID_VCLK_DIV] = &axg_vclk_div.hw,
+ [CLKID_VCLK2_DIV] = &axg_vclk2_div.hw,
+ [CLKID_VCLK_DIV2_EN] = &axg_vclk_div2_en.hw,
+ [CLKID_VCLK_DIV4_EN] = &axg_vclk_div4_en.hw,
+ [CLKID_VCLK_DIV6_EN] = &axg_vclk_div6_en.hw,
+ [CLKID_VCLK_DIV12_EN] = &axg_vclk_div12_en.hw,
+ [CLKID_VCLK2_DIV2_EN] = &axg_vclk2_div2_en.hw,
+ [CLKID_VCLK2_DIV4_EN] = &axg_vclk2_div4_en.hw,
+ [CLKID_VCLK2_DIV6_EN] = &axg_vclk2_div6_en.hw,
+ [CLKID_VCLK2_DIV12_EN] = &axg_vclk2_div12_en.hw,
+ [CLKID_VCLK_DIV1] = &axg_vclk_div1.hw,
+ [CLKID_VCLK_DIV2] = &axg_vclk_div2.hw,
+ [CLKID_VCLK_DIV4] = &axg_vclk_div4.hw,
+ [CLKID_VCLK_DIV6] = &axg_vclk_div6.hw,
+ [CLKID_VCLK_DIV12] = &axg_vclk_div12.hw,
+ [CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw,
+ [CLKID_VCLK2_DIV2] = &axg_vclk2_div2.hw,
+ [CLKID_VCLK2_DIV4] = &axg_vclk2_div4.hw,
+ [CLKID_VCLK2_DIV6] = &axg_vclk2_div6.hw,
+ [CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw,
+ [CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw,
+ [CLKID_CTS_ENCL] = &axg_cts_encl.hw,
+ [CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw,
+ [CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw,
+ [CLKID_VDIN_MEAS] = &axg_vdin_meas.hw,
};
/* Convenience table to populate regmap in .probe */
@@ -2163,7 +2161,10 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
static const struct meson_eeclkc_data axg_clkc_data = {
.regmap_clks = axg_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
- .hw_onecell_data = &axg_hw_onecell_data,
+ .hw_clks = {
+ .hws = axg_hw_clks,
+ .num = ARRAY_SIZE(axg_hw_clks),
+ },
};
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
index 23ea87964af2..624d8d3ce7c4 100644
--- a/drivers/clk/meson/axg.h
+++ b/drivers/clk/meson/axg.h
@@ -102,67 +102,4 @@
#define HHI_DPLL_TOP_I 0x318
#define HHI_DPLL_TOP2_I 0x31C
-/*
- * CLKID index values
- *
- * These indices are entirely contrived and do not map onto the hardware.
- * It has now been decided to expose everything by default in the DT header:
- * include/dt-bindings/clock/axg-clkc.h. Only the clocks ids we don't want
- * to expose, such as the internal muxes and dividers of composite clocks,
- * will remain defined here.
- */
-#define CLKID_MPEG_SEL 8
-#define CLKID_MPEG_DIV 9
-#define CLKID_SD_EMMC_B_CLK0_SEL 61
-#define CLKID_SD_EMMC_B_CLK0_DIV 62
-#define CLKID_SD_EMMC_C_CLK0_SEL 63
-#define CLKID_SD_EMMC_C_CLK0_DIV 64
-#define CLKID_MPLL0_DIV 65
-#define CLKID_MPLL1_DIV 66
-#define CLKID_MPLL2_DIV 67
-#define CLKID_MPLL3_DIV 68
-#define CLKID_MPLL_PREDIV 70
-#define CLKID_FCLK_DIV2_DIV 71
-#define CLKID_FCLK_DIV3_DIV 72
-#define CLKID_FCLK_DIV4_DIV 73
-#define CLKID_FCLK_DIV5_DIV 74
-#define CLKID_FCLK_DIV7_DIV 75
-#define CLKID_PCIE_PLL 76
-#define CLKID_PCIE_MUX 77
-#define CLKID_PCIE_REF 78
-#define CLKID_GEN_CLK_SEL 82
-#define CLKID_GEN_CLK_DIV 83
-#define CLKID_SYS_PLL_DCO 85
-#define CLKID_FIXED_PLL_DCO 86
-#define CLKID_GP0_PLL_DCO 87
-#define CLKID_HIFI_PLL_DCO 88
-#define CLKID_PCIE_PLL_DCO 89
-#define CLKID_PCIE_PLL_OD 90
-#define CLKID_VPU_0_DIV 91
-#define CLKID_VPU_1_DIV 94
-#define CLKID_VAPB_0_DIV 98
-#define CLKID_VAPB_1_DIV 101
-#define CLKID_VCLK_SEL 108
-#define CLKID_VCLK2_SEL 109
-#define CLKID_VCLK_INPUT 110
-#define CLKID_VCLK2_INPUT 111
-#define CLKID_VCLK_DIV 112
-#define CLKID_VCLK2_DIV 113
-#define CLKID_VCLK_DIV2_EN 114
-#define CLKID_VCLK_DIV4_EN 115
-#define CLKID_VCLK_DIV6_EN 116
-#define CLKID_VCLK_DIV12_EN 117
-#define CLKID_VCLK2_DIV2_EN 118
-#define CLKID_VCLK2_DIV4_EN 119
-#define CLKID_VCLK2_DIV6_EN 120
-#define CLKID_VCLK2_DIV12_EN 121
-#define CLKID_CTS_ENCL_SEL 132
-#define CLKID_VDIN_MEAS_SEL 134
-#define CLKID_VDIN_MEAS_DIV 135
-
-#define NR_CLKS 137
-
-/* include the CLKIDs that have been made part of the DT binding */
-#include <dt-bindings/clock/axg-clkc.h>
-
#endif /* __AXG_H */
diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c
index b52990e574d2..c6b1d55cd7c8 100644
--- a/drivers/clk/meson/g12a-aoclk.c
+++ b/drivers/clk/meson/g12a-aoclk.c
@@ -14,11 +14,13 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include "meson-aoclk.h"
-#include "g12a-aoclk.h"
#include "clk-regmap.h"
#include "clk-dualdiv.h"
+#include <dt-bindings/clock/g12a-aoclkc.h>
+#include <dt-bindings/reset/g12a-aoclkc.h>
+
/*
* AO Configuration Clock registers offsets
* Register offsets from the data sheet must be multiplied by 4.
@@ -411,39 +413,36 @@ static struct clk_regmap *g12a_aoclk_regmap[] = {
&g12a_aoclk_saradc_gate,
};
-static const struct clk_hw_onecell_data g12a_aoclk_onecell_data = {
- .hws = {
- [CLKID_AO_AHB] = &g12a_aoclk_ahb.hw,
- [CLKID_AO_IR_IN] = &g12a_aoclk_ir_in.hw,
- [CLKID_AO_I2C_M0] = &g12a_aoclk_i2c_m0.hw,
- [CLKID_AO_I2C_S0] = &g12a_aoclk_i2c_s0.hw,
- [CLKID_AO_UART] = &g12a_aoclk_uart.hw,
- [CLKID_AO_PROD_I2C] = &g12a_aoclk_prod_i2c.hw,
- [CLKID_AO_UART2] = &g12a_aoclk_uart2.hw,
- [CLKID_AO_IR_OUT] = &g12a_aoclk_ir_out.hw,
- [CLKID_AO_SAR_ADC] = &g12a_aoclk_saradc.hw,
- [CLKID_AO_MAILBOX] = &g12a_aoclk_mailbox.hw,
- [CLKID_AO_M3] = &g12a_aoclk_m3.hw,
- [CLKID_AO_AHB_SRAM] = &g12a_aoclk_ahb_sram.hw,
- [CLKID_AO_RTI] = &g12a_aoclk_rti.hw,
- [CLKID_AO_M4_FCLK] = &g12a_aoclk_m4_fclk.hw,
- [CLKID_AO_M4_HCLK] = &g12a_aoclk_m4_hclk.hw,
- [CLKID_AO_CLK81] = &g12a_aoclk_clk81.hw,
- [CLKID_AO_SAR_ADC_SEL] = &g12a_aoclk_saradc_mux.hw,
- [CLKID_AO_SAR_ADC_DIV] = &g12a_aoclk_saradc_div.hw,
- [CLKID_AO_SAR_ADC_CLK] = &g12a_aoclk_saradc_gate.hw,
- [CLKID_AO_CTS_OSCIN] = &g12a_aoclk_cts_oscin.hw,
- [CLKID_AO_32K_PRE] = &g12a_aoclk_32k_by_oscin_pre.hw,
- [CLKID_AO_32K_DIV] = &g12a_aoclk_32k_by_oscin_div.hw,
- [CLKID_AO_32K_SEL] = &g12a_aoclk_32k_by_oscin_sel.hw,
- [CLKID_AO_32K] = &g12a_aoclk_32k_by_oscin.hw,
- [CLKID_AO_CEC_PRE] = &g12a_aoclk_cec_pre.hw,
- [CLKID_AO_CEC_DIV] = &g12a_aoclk_cec_div.hw,
- [CLKID_AO_CEC_SEL] = &g12a_aoclk_cec_sel.hw,
- [CLKID_AO_CEC] = &g12a_aoclk_cec.hw,
- [CLKID_AO_CTS_RTC_OSCIN] = &g12a_aoclk_cts_rtc_oscin.hw,
- },
- .num = NR_CLKS,
+static struct clk_hw *g12a_aoclk_hw_clks[] = {
+ [CLKID_AO_AHB] = &g12a_aoclk_ahb.hw,
+ [CLKID_AO_IR_IN] = &g12a_aoclk_ir_in.hw,
+ [CLKID_AO_I2C_M0] = &g12a_aoclk_i2c_m0.hw,
+ [CLKID_AO_I2C_S0] = &g12a_aoclk_i2c_s0.hw,
+ [CLKID_AO_UART] = &g12a_aoclk_uart.hw,
+ [CLKID_AO_PROD_I2C] = &g12a_aoclk_prod_i2c.hw,
+ [CLKID_AO_UART2] = &g12a_aoclk_uart2.hw,
+ [CLKID_AO_IR_OUT] = &g12a_aoclk_ir_out.hw,
+ [CLKID_AO_SAR_ADC] = &g12a_aoclk_saradc.hw,
+ [CLKID_AO_MAILBOX] = &g12a_aoclk_mailbox.hw,
+ [CLKID_AO_M3] = &g12a_aoclk_m3.hw,
+ [CLKID_AO_AHB_SRAM] = &g12a_aoclk_ahb_sram.hw,
+ [CLKID_AO_RTI] = &g12a_aoclk_rti.hw,
+ [CLKID_AO_M4_FCLK] = &g12a_aoclk_m4_fclk.hw,
+ [CLKID_AO_M4_HCLK] = &g12a_aoclk_m4_hclk.hw,
+ [CLKID_AO_CLK81] = &g12a_aoclk_clk81.hw,
+ [CLKID_AO_SAR_ADC_SEL] = &g12a_aoclk_saradc_mux.hw,
+ [CLKID_AO_SAR_ADC_DIV] = &g12a_aoclk_saradc_div.hw,
+ [CLKID_AO_SAR_ADC_CLK] = &g12a_aoclk_saradc_gate.hw,
+ [CLKID_AO_CTS_OSCIN] = &g12a_aoclk_cts_oscin.hw,
+ [CLKID_AO_32K_PRE] = &g12a_aoclk_32k_by_oscin_pre.hw,
+ [CLKID_AO_32K_DIV] = &g12a_aoclk_32k_by_oscin_div.hw,
+ [CLKID_AO_32K_SEL] = &g12a_aoclk_32k_by_oscin_sel.hw,
+ [CLKID_AO_32K] = &g12a_aoclk_32k_by_oscin.hw,
+ [CLKID_AO_CEC_PRE] = &g12a_aoclk_cec_pre.hw,
+ [CLKID_AO_CEC_DIV] = &g12a_aoclk_cec_div.hw,
+ [CLKID_AO_CEC_SEL] = &g12a_aoclk_cec_sel.hw,
+ [CLKID_AO_CEC] = &g12a_aoclk_cec.hw,
+ [CLKID_AO_CTS_RTC_OSCIN] = &g12a_aoclk_cts_rtc_oscin.hw,
};
static const struct meson_aoclk_data g12a_aoclkc_data = {
@@ -452,7 +451,10 @@ static const struct meson_aoclk_data g12a_aoclkc_data = {
.reset = g12a_aoclk_reset,
.num_clks = ARRAY_SIZE(g12a_aoclk_regmap),
.clks = g12a_aoclk_regmap,
- .hw_data = &g12a_aoclk_onecell_data,
+ .hw_clks = {
+ .hws = g12a_aoclk_hw_clks,
+ .num = ARRAY_SIZE(g12a_aoclk_hw_clks),
+ },
};
static const struct of_device_id g12a_aoclkc_match_table[] = {
diff --git a/drivers/clk/meson/g12a-aoclk.h b/drivers/clk/meson/g12a-aoclk.h
deleted file mode 100644
index a67c8a7cd7c4..000000000000
--- a/drivers/clk/meson/g12a-aoclk.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef __G12A_AOCLKC_H
-#define __G12A_AOCLKC_H
-
-/*
- * CLKID index values
- *
- * These indices are entirely contrived and do not map onto the hardware.
- * It has now been decided to expose everything by default in the DT header:
- * include/dt-bindings/clock/g12a-aoclkc.h. Only the clocks ids we don't want
- * to expose, such as the internal muxes and dividers of composite clocks,
- * will remain defined here.
- */
-#define CLKID_AO_SAR_ADC_DIV 17
-#define CLKID_AO_32K_PRE 20
-#define CLKID_AO_32K_DIV 21
-#define CLKID_AO_32K_SEL 22
-#define CLKID_AO_CEC_PRE 24
-#define CLKID_AO_CEC_DIV 25
-#define CLKID_AO_CEC_SEL 26
-
-#define NR_CLKS 29
-
-#include <dt-bindings/clock/g12a-aoclkc.h>
-#include <dt-bindings/reset/g12a-aoclkc.h>
-
-#endif /* __G12A_AOCLKC_H */
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 310accf94830..f373a8d48b1d 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -12,7 +12,7 @@
#include <linux/clk-provider.h>
#include <linux/init.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/module.h>
@@ -25,6 +25,8 @@
#include "meson-eeclk.h"
#include "g12a.h"
+#include <dt-bindings/clock/g12a-clkc.h>
+
static DEFINE_SPINLOCK(meson_clk_lock);
static struct clk_regmap g12a_fixed_pll_dco = {
@@ -4244,746 +4246,734 @@ static MESON_GATE_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3);
static MESON_GATE_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4);
/* Array of all clocks provided by this provider */
-static struct clk_hw_onecell_data g12a_hw_onecell_data = {
- .hws = {
- [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
- [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
- [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
- [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
- [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
- [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
- [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
- [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
- [CLKID_CLK81] = &g12a_clk81.hw,
- [CLKID_MPLL0] = &g12a_mpll0.hw,
- [CLKID_MPLL1] = &g12a_mpll1.hw,
- [CLKID_MPLL2] = &g12a_mpll2.hw,
- [CLKID_MPLL3] = &g12a_mpll3.hw,
- [CLKID_DDR] = &g12a_ddr.hw,
- [CLKID_DOS] = &g12a_dos.hw,
- [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
- [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
- [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
- [CLKID_ISA] = &g12a_isa.hw,
- [CLKID_PL301] = &g12a_pl301.hw,
- [CLKID_PERIPHS] = &g12a_periphs.hw,
- [CLKID_SPICC0] = &g12a_spicc_0.hw,
- [CLKID_I2C] = &g12a_i2c.hw,
- [CLKID_SANA] = &g12a_sana.hw,
- [CLKID_SD] = &g12a_sd.hw,
- [CLKID_RNG0] = &g12a_rng0.hw,
- [CLKID_UART0] = &g12a_uart0.hw,
- [CLKID_SPICC1] = &g12a_spicc_1.hw,
- [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
- [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
- [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
- [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
- [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
- [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
- [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
- [CLKID_AUDIO] = &g12a_audio.hw,
- [CLKID_ETH] = &g12a_eth_core.hw,
- [CLKID_DEMUX] = &g12a_demux.hw,
- [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
- [CLKID_ADC] = &g12a_adc.hw,
- [CLKID_UART1] = &g12a_uart1.hw,
- [CLKID_G2D] = &g12a_g2d.hw,
- [CLKID_RESET] = &g12a_reset.hw,
- [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
- [CLKID_PARSER] = &g12a_parser.hw,
- [CLKID_USB] = &g12a_usb_general.hw,
- [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
- [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
- [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
- [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
- [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
- [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
- [CLKID_BT656] = &g12a_bt656.hw,
- [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
- [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
- [CLKID_UART2] = &g12a_uart2.hw,
- [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
- [CLKID_GIC] = &g12a_gic.hw,
- [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
- [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
- [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
- [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
- [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
- [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
- [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
- [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
- [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
- [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
- [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
- [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
- [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
- [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
- [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
- [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
- [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
- [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
- [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
- [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
- [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
- [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
- [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
- [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
- [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
- [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
- [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
- [CLKID_IEC958] = &g12a_iec958_gate.hw,
- [CLKID_ENC480P] = &g12a_enc480p.hw,
- [CLKID_RNG1] = &g12a_rng1.hw,
- [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
- [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
- [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
- [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
- [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
- [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
- [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
- [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
- [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
- [CLKID_DMA] = &g12a_dma.hw,
- [CLKID_EFUSE] = &g12a_efuse.hw,
- [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
- [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
- [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
- [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
- [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
- [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
- [CLKID_VPU_0] = &g12a_vpu_0.hw,
- [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
- [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
- [CLKID_VPU_1] = &g12a_vpu_1.hw,
- [CLKID_VPU] = &g12a_vpu.hw,
- [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
- [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
- [CLKID_VAPB_0] = &g12a_vapb_0.hw,
- [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
- [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
- [CLKID_VAPB_1] = &g12a_vapb_1.hw,
- [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
- [CLKID_VAPB] = &g12a_vapb.hw,
- [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
- [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
- [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
- [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
- [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
- [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
- [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
- [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
- [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
- [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
- [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
- [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
- [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
- [CLKID_VCLK] = &g12a_vclk.hw,
- [CLKID_VCLK2] = &g12a_vclk2.hw,
- [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
- [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
- [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
- [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
- [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
- [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
- [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
- [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
- [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
- [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
- [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
- [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
- [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
- [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
- [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
- [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
- [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
- [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
- [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
- [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
- [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
- [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
- [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
- [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
- [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
- [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
- [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
- [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
- [CLKID_HDMI] = &g12a_hdmi.hw,
- [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
- [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
- [CLKID_MALI_0] = &g12a_mali_0.hw,
- [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
- [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
- [CLKID_MALI_1] = &g12a_mali_1.hw,
- [CLKID_MALI] = &g12a_mali.hw,
- [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
- [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
- [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
- [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
- [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
- [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
- [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
- [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
- [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
- [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
- [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
- [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
- [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
- [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
- [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
- [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
- [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
- [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
- [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
- [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
- [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
- [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
- [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
- [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
- [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
- [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
- [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
- [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
- [CLKID_VDEC_1] = &g12a_vdec_1.hw,
- [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
- [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
- [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
- [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
- [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
- [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
- [CLKID_TS_DIV] = &g12a_ts_div.hw,
- [CLKID_TS] = &g12a_ts.hw,
- [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
- [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
- [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
- [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
- [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
- [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
- [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
- [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
- [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
-};
-
-static struct clk_hw_onecell_data g12b_hw_onecell_data = {
- .hws = {
- [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
- [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
- [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
- [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
- [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
- [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
- [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
- [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
- [CLKID_CLK81] = &g12a_clk81.hw,
- [CLKID_MPLL0] = &g12a_mpll0.hw,
- [CLKID_MPLL1] = &g12a_mpll1.hw,
- [CLKID_MPLL2] = &g12a_mpll2.hw,
- [CLKID_MPLL3] = &g12a_mpll3.hw,
- [CLKID_DDR] = &g12a_ddr.hw,
- [CLKID_DOS] = &g12a_dos.hw,
- [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
- [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
- [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
- [CLKID_ISA] = &g12a_isa.hw,
- [CLKID_PL301] = &g12a_pl301.hw,
- [CLKID_PERIPHS] = &g12a_periphs.hw,
- [CLKID_SPICC0] = &g12a_spicc_0.hw,
- [CLKID_I2C] = &g12a_i2c.hw,
- [CLKID_SANA] = &g12a_sana.hw,
- [CLKID_SD] = &g12a_sd.hw,
- [CLKID_RNG0] = &g12a_rng0.hw,
- [CLKID_UART0] = &g12a_uart0.hw,
- [CLKID_SPICC1] = &g12a_spicc_1.hw,
- [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
- [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
- [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
- [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
- [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
- [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
- [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
- [CLKID_AUDIO] = &g12a_audio.hw,
- [CLKID_ETH] = &g12a_eth_core.hw,
- [CLKID_DEMUX] = &g12a_demux.hw,
- [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
- [CLKID_ADC] = &g12a_adc.hw,
- [CLKID_UART1] = &g12a_uart1.hw,
- [CLKID_G2D] = &g12a_g2d.hw,
- [CLKID_RESET] = &g12a_reset.hw,
- [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
- [CLKID_PARSER] = &g12a_parser.hw,
- [CLKID_USB] = &g12a_usb_general.hw,
- [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
- [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
- [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
- [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
- [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
- [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
- [CLKID_BT656] = &g12a_bt656.hw,
- [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
- [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
- [CLKID_UART2] = &g12a_uart2.hw,
- [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
- [CLKID_GIC] = &g12a_gic.hw,
- [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
- [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
- [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
- [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
- [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
- [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
- [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
- [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
- [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
- [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
- [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
- [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
- [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
- [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
- [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
- [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
- [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
- [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
- [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
- [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
- [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
- [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
- [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
- [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
- [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
- [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
- [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
- [CLKID_IEC958] = &g12a_iec958_gate.hw,
- [CLKID_ENC480P] = &g12a_enc480p.hw,
- [CLKID_RNG1] = &g12a_rng1.hw,
- [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
- [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
- [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
- [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
- [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
- [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
- [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
- [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
- [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
- [CLKID_DMA] = &g12a_dma.hw,
- [CLKID_EFUSE] = &g12a_efuse.hw,
- [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
- [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
- [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
- [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
- [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
- [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
- [CLKID_VPU_0] = &g12a_vpu_0.hw,
- [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
- [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
- [CLKID_VPU_1] = &g12a_vpu_1.hw,
- [CLKID_VPU] = &g12a_vpu.hw,
- [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
- [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
- [CLKID_VAPB_0] = &g12a_vapb_0.hw,
- [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
- [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
- [CLKID_VAPB_1] = &g12a_vapb_1.hw,
- [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
- [CLKID_VAPB] = &g12a_vapb.hw,
- [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
- [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
- [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
- [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
- [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
- [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
- [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
- [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
- [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
- [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
- [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
- [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
- [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
- [CLKID_VCLK] = &g12a_vclk.hw,
- [CLKID_VCLK2] = &g12a_vclk2.hw,
- [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
- [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
- [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
- [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
- [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
- [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
- [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
- [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
- [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
- [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
- [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
- [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
- [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
- [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
- [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
- [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
- [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
- [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
- [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
- [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
- [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
- [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
- [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
- [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
- [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
- [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
- [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
- [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
- [CLKID_HDMI] = &g12a_hdmi.hw,
- [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
- [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
- [CLKID_MALI_0] = &g12a_mali_0.hw,
- [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
- [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
- [CLKID_MALI_1] = &g12a_mali_1.hw,
- [CLKID_MALI] = &g12a_mali.hw,
- [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
- [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
- [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
- [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
- [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
- [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
- [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
- [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
- [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
- [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
- [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
- [CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
- [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
- [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
- [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
- [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
- [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
- [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
- [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
- [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
- [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
- [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
- [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
- [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
- [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
- [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
- [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
- [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
- [CLKID_VDEC_1] = &g12a_vdec_1.hw,
- [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
- [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
- [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
- [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
- [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
- [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
- [CLKID_TS_DIV] = &g12a_ts_div.hw,
- [CLKID_TS] = &g12a_ts.hw,
- [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,
- [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
- [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
- [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
- [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw,
- [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw,
- [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw,
- [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw,
- [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw,
- [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw,
- [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
- [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
- [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
- [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,
- [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,
- [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,
- [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,
- [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,
- [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,
- [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,
- [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,
- [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,
- [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,
- [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,
- [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,
- [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,
- [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
- [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
- [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
- [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
- [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
- [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
- [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
- [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
- [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
- [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
- [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
- [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
- [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
- [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
- [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
- [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
- [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
- [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
-};
-
-static struct clk_hw_onecell_data sm1_hw_onecell_data = {
- .hws = {
- [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
- [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
- [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
- [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
- [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
- [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
- [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
- [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
- [CLKID_CLK81] = &g12a_clk81.hw,
- [CLKID_MPLL0] = &g12a_mpll0.hw,
- [CLKID_MPLL1] = &g12a_mpll1.hw,
- [CLKID_MPLL2] = &g12a_mpll2.hw,
- [CLKID_MPLL3] = &g12a_mpll3.hw,
- [CLKID_DDR] = &g12a_ddr.hw,
- [CLKID_DOS] = &g12a_dos.hw,
- [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
- [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
- [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
- [CLKID_ISA] = &g12a_isa.hw,
- [CLKID_PL301] = &g12a_pl301.hw,
- [CLKID_PERIPHS] = &g12a_periphs.hw,
- [CLKID_SPICC0] = &g12a_spicc_0.hw,
- [CLKID_I2C] = &g12a_i2c.hw,
- [CLKID_SANA] = &g12a_sana.hw,
- [CLKID_SD] = &g12a_sd.hw,
- [CLKID_RNG0] = &g12a_rng0.hw,
- [CLKID_UART0] = &g12a_uart0.hw,
- [CLKID_SPICC1] = &g12a_spicc_1.hw,
- [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
- [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
- [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
- [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
- [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
- [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
- [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
- [CLKID_AUDIO] = &g12a_audio.hw,
- [CLKID_ETH] = &g12a_eth_core.hw,
- [CLKID_DEMUX] = &g12a_demux.hw,
- [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
- [CLKID_ADC] = &g12a_adc.hw,
- [CLKID_UART1] = &g12a_uart1.hw,
- [CLKID_G2D] = &g12a_g2d.hw,
- [CLKID_RESET] = &g12a_reset.hw,
- [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
- [CLKID_PARSER] = &g12a_parser.hw,
- [CLKID_USB] = &g12a_usb_general.hw,
- [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
- [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
- [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
- [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
- [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
- [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
- [CLKID_BT656] = &g12a_bt656.hw,
- [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
- [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
- [CLKID_UART2] = &g12a_uart2.hw,
- [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
- [CLKID_GIC] = &g12a_gic.hw,
- [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
- [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
- [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
- [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
- [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
- [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
- [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
- [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
- [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
- [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
- [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
- [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
- [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
- [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
- [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
- [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
- [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
- [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
- [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
- [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
- [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
- [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
- [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
- [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
- [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
- [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
- [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
- [CLKID_IEC958] = &g12a_iec958_gate.hw,
- [CLKID_ENC480P] = &g12a_enc480p.hw,
- [CLKID_RNG1] = &g12a_rng1.hw,
- [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
- [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
- [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
- [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
- [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
- [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
- [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
- [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
- [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
- [CLKID_DMA] = &g12a_dma.hw,
- [CLKID_EFUSE] = &g12a_efuse.hw,
- [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
- [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
- [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
- [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
- [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
- [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
- [CLKID_VPU_0] = &g12a_vpu_0.hw,
- [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
- [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
- [CLKID_VPU_1] = &g12a_vpu_1.hw,
- [CLKID_VPU] = &g12a_vpu.hw,
- [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
- [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
- [CLKID_VAPB_0] = &g12a_vapb_0.hw,
- [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
- [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
- [CLKID_VAPB_1] = &g12a_vapb_1.hw,
- [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
- [CLKID_VAPB] = &g12a_vapb.hw,
- [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
- [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
- [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
- [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
- [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
- [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
- [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
- [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
- [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
- [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
- [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
- [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
- [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
- [CLKID_VCLK] = &g12a_vclk.hw,
- [CLKID_VCLK2] = &g12a_vclk2.hw,
- [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
- [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
- [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
- [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
- [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
- [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
- [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
- [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
- [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
- [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
- [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
- [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
- [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
- [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
- [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
- [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
- [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
- [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
- [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
- [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
- [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
- [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
- [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
- [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
- [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
- [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
- [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
- [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
- [CLKID_HDMI] = &g12a_hdmi.hw,
- [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
- [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
- [CLKID_MALI_0] = &g12a_mali_0.hw,
- [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
- [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
- [CLKID_MALI_1] = &g12a_mali_1.hw,
- [CLKID_MALI] = &g12a_mali.hw,
- [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
- [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
- [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
- [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
- [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
- [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
- [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
- [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
- [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
- [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
- [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
- [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
- [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
- [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
- [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
- [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
- [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
- [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
- [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
- [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
- [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
- [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
- [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
- [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
- [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
- [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
- [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
- [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
- [CLKID_VDEC_1] = &g12a_vdec_1.hw,
- [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
- [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
- [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
- [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
- [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
- [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
- [CLKID_TS_DIV] = &g12a_ts_div.hw,
- [CLKID_TS] = &g12a_ts.hw,
- [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
- [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
- [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
- [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
- [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
- [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
- [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
- [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
- [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
- [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
- [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
- [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
- [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
- [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
- [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
- [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
- [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
- [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
- [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
- [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
- [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
- [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
- [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
- [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
- [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
- [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
- [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
- [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
- [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
+static struct clk_hw *g12a_hw_clks[] = {
+ [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
+ [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
+ [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
+ [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
+ [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
+ [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &g12a_clk81.hw,
+ [CLKID_MPLL0] = &g12a_mpll0.hw,
+ [CLKID_MPLL1] = &g12a_mpll1.hw,
+ [CLKID_MPLL2] = &g12a_mpll2.hw,
+ [CLKID_MPLL3] = &g12a_mpll3.hw,
+ [CLKID_DDR] = &g12a_ddr.hw,
+ [CLKID_DOS] = &g12a_dos.hw,
+ [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
+ [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
+ [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
+ [CLKID_ISA] = &g12a_isa.hw,
+ [CLKID_PL301] = &g12a_pl301.hw,
+ [CLKID_PERIPHS] = &g12a_periphs.hw,
+ [CLKID_SPICC0] = &g12a_spicc_0.hw,
+ [CLKID_I2C] = &g12a_i2c.hw,
+ [CLKID_SANA] = &g12a_sana.hw,
+ [CLKID_SD] = &g12a_sd.hw,
+ [CLKID_RNG0] = &g12a_rng0.hw,
+ [CLKID_UART0] = &g12a_uart0.hw,
+ [CLKID_SPICC1] = &g12a_spicc_1.hw,
+ [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
+ [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
+ [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
+ [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
+ [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
+ [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
+ [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
+ [CLKID_AUDIO] = &g12a_audio.hw,
+ [CLKID_ETH] = &g12a_eth_core.hw,
+ [CLKID_DEMUX] = &g12a_demux.hw,
+ [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
+ [CLKID_ADC] = &g12a_adc.hw,
+ [CLKID_UART1] = &g12a_uart1.hw,
+ [CLKID_G2D] = &g12a_g2d.hw,
+ [CLKID_RESET] = &g12a_reset.hw,
+ [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
+ [CLKID_PARSER] = &g12a_parser.hw,
+ [CLKID_USB] = &g12a_usb_general.hw,
+ [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
+ [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
+ [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
+ [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
+ [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
+ [CLKID_BT656] = &g12a_bt656.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
+ [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
+ [CLKID_UART2] = &g12a_uart2.hw,
+ [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
+ [CLKID_GIC] = &g12a_gic.hw,
+ [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
+ [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
+ [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
+ [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
+ [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
+ [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
+ [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
+ [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
+ [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
+ [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
+ [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
+ [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
+ [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
+ [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
+ [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
+ [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
+ [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
+ [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
+ [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
+ [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
+ [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
+ [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
+ [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
+ [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
+ [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
+ [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
+ [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
+ [CLKID_IEC958] = &g12a_iec958_gate.hw,
+ [CLKID_ENC480P] = &g12a_enc480p.hw,
+ [CLKID_RNG1] = &g12a_rng1.hw,
+ [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
+ [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
+ [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
+ [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
+ [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
+ [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
+ [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
+ [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
+ [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
+ [CLKID_DMA] = &g12a_dma.hw,
+ [CLKID_EFUSE] = &g12a_efuse.hw,
+ [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
+ [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
+ [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
+ [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
+ [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
+ [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
+ [CLKID_VPU_0] = &g12a_vpu_0.hw,
+ [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
+ [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
+ [CLKID_VPU_1] = &g12a_vpu_1.hw,
+ [CLKID_VPU] = &g12a_vpu.hw,
+ [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
+ [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
+ [CLKID_VAPB_0] = &g12a_vapb_0.hw,
+ [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
+ [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
+ [CLKID_VAPB_1] = &g12a_vapb_1.hw,
+ [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
+ [CLKID_VAPB] = &g12a_vapb.hw,
+ [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
+ [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
+ [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
+ [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
+ [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
+ [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
+ [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
+ [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
+ [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
+ [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
+ [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
+ [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
+ [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
+ [CLKID_VCLK] = &g12a_vclk.hw,
+ [CLKID_VCLK2] = &g12a_vclk2.hw,
+ [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
+ [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
+ [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
+ [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
+ [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
+ [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
+ [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
+ [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
+ [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
+ [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
+ [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
+ [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
+ [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
+ [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
+ [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
+ [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
+ [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
+ [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
+ [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
+ [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
+ [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
+ [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
+ [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
+ [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
+ [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
+ [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
+ [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
+ [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
+ [CLKID_HDMI] = &g12a_hdmi.hw,
+ [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
+ [CLKID_MALI_0] = &g12a_mali_0.hw,
+ [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
+ [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
+ [CLKID_MALI_1] = &g12a_mali_1.hw,
+ [CLKID_MALI] = &g12a_mali.hw,
+ [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
+ [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
+ [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
+ [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
+ [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
+ [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
+ [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
+ [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
+ [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
+ [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
+ [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
+ [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
+ [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
+ [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
+ [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
+ [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
+ [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
+ [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
+ [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
+ [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
+ [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
+ [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
+ [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
+ [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
+ [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
+ [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
+ [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
+ [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
+ [CLKID_VDEC_1] = &g12a_vdec_1.hw,
+ [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
+ [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
+ [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
+ [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
+ [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
+ [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
+ [CLKID_TS_DIV] = &g12a_ts_div.hw,
+ [CLKID_TS] = &g12a_ts.hw,
+ [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
+ [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
+ [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
+ [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
+ [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
+ [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
+ [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
+ [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
+ [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
+};
+
+static struct clk_hw *g12b_hw_clks[] = {
+ [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
+ [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
+ [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
+ [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
+ [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
+ [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &g12a_clk81.hw,
+ [CLKID_MPLL0] = &g12a_mpll0.hw,
+ [CLKID_MPLL1] = &g12a_mpll1.hw,
+ [CLKID_MPLL2] = &g12a_mpll2.hw,
+ [CLKID_MPLL3] = &g12a_mpll3.hw,
+ [CLKID_DDR] = &g12a_ddr.hw,
+ [CLKID_DOS] = &g12a_dos.hw,
+ [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
+ [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
+ [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
+ [CLKID_ISA] = &g12a_isa.hw,
+ [CLKID_PL301] = &g12a_pl301.hw,
+ [CLKID_PERIPHS] = &g12a_periphs.hw,
+ [CLKID_SPICC0] = &g12a_spicc_0.hw,
+ [CLKID_I2C] = &g12a_i2c.hw,
+ [CLKID_SANA] = &g12a_sana.hw,
+ [CLKID_SD] = &g12a_sd.hw,
+ [CLKID_RNG0] = &g12a_rng0.hw,
+ [CLKID_UART0] = &g12a_uart0.hw,
+ [CLKID_SPICC1] = &g12a_spicc_1.hw,
+ [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
+ [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
+ [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
+ [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
+ [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
+ [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
+ [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
+ [CLKID_AUDIO] = &g12a_audio.hw,
+ [CLKID_ETH] = &g12a_eth_core.hw,
+ [CLKID_DEMUX] = &g12a_demux.hw,
+ [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
+ [CLKID_ADC] = &g12a_adc.hw,
+ [CLKID_UART1] = &g12a_uart1.hw,
+ [CLKID_G2D] = &g12a_g2d.hw,
+ [CLKID_RESET] = &g12a_reset.hw,
+ [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
+ [CLKID_PARSER] = &g12a_parser.hw,
+ [CLKID_USB] = &g12a_usb_general.hw,
+ [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
+ [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
+ [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
+ [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
+ [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
+ [CLKID_BT656] = &g12a_bt656.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
+ [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
+ [CLKID_UART2] = &g12a_uart2.hw,
+ [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
+ [CLKID_GIC] = &g12a_gic.hw,
+ [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
+ [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
+ [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
+ [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
+ [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
+ [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
+ [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
+ [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
+ [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
+ [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
+ [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
+ [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
+ [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
+ [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
+ [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
+ [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
+ [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
+ [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
+ [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
+ [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
+ [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
+ [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
+ [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
+ [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
+ [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
+ [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
+ [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
+ [CLKID_IEC958] = &g12a_iec958_gate.hw,
+ [CLKID_ENC480P] = &g12a_enc480p.hw,
+ [CLKID_RNG1] = &g12a_rng1.hw,
+ [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
+ [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
+ [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
+ [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
+ [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
+ [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
+ [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
+ [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
+ [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
+ [CLKID_DMA] = &g12a_dma.hw,
+ [CLKID_EFUSE] = &g12a_efuse.hw,
+ [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
+ [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
+ [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
+ [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
+ [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
+ [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
+ [CLKID_VPU_0] = &g12a_vpu_0.hw,
+ [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
+ [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
+ [CLKID_VPU_1] = &g12a_vpu_1.hw,
+ [CLKID_VPU] = &g12a_vpu.hw,
+ [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
+ [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
+ [CLKID_VAPB_0] = &g12a_vapb_0.hw,
+ [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
+ [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
+ [CLKID_VAPB_1] = &g12a_vapb_1.hw,
+ [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
+ [CLKID_VAPB] = &g12a_vapb.hw,
+ [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
+ [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
+ [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
+ [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
+ [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
+ [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
+ [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
+ [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
+ [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
+ [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
+ [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
+ [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
+ [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
+ [CLKID_VCLK] = &g12a_vclk.hw,
+ [CLKID_VCLK2] = &g12a_vclk2.hw,
+ [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
+ [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
+ [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
+ [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
+ [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
+ [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
+ [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
+ [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
+ [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
+ [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
+ [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
+ [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
+ [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
+ [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
+ [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
+ [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
+ [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
+ [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
+ [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
+ [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
+ [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
+ [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
+ [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
+ [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
+ [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
+ [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
+ [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
+ [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
+ [CLKID_HDMI] = &g12a_hdmi.hw,
+ [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
+ [CLKID_MALI_0] = &g12a_mali_0.hw,
+ [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
+ [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
+ [CLKID_MALI_1] = &g12a_mali_1.hw,
+ [CLKID_MALI] = &g12a_mali.hw,
+ [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
+ [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
+ [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
+ [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
+ [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
+ [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
+ [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
+ [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
+ [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
+ [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
+ [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
+ [CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
+ [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
+ [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
+ [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
+ [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
+ [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
+ [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
+ [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
+ [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
+ [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
+ [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
+ [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
+ [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
+ [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
+ [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
+ [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
+ [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
+ [CLKID_VDEC_1] = &g12a_vdec_1.hw,
+ [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
+ [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
+ [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
+ [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
+ [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
+ [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
+ [CLKID_TS_DIV] = &g12a_ts_div.hw,
+ [CLKID_TS] = &g12a_ts.hw,
+ [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,
+ [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
+ [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
+ [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
+ [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw,
+ [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw,
+ [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw,
+ [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw,
+ [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw,
+ [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw,
+ [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
+ [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
+ [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
+ [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,
+ [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,
+ [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,
+ [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,
+ [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,
+ [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,
+ [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,
+ [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,
+ [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,
+ [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,
+ [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,
+ [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,
+ [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,
+ [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
+ [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
+ [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
+ [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
+ [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
+ [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
+ [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
+ [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
+ [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
+ [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
+ [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
+ [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
+ [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
+ [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
+ [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
+ [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
+ [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
+ [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
+};
+
+static struct clk_hw *sm1_hw_clks[] = {
+ [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
+ [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
+ [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
+ [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
+ [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
+ [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &g12a_clk81.hw,
+ [CLKID_MPLL0] = &g12a_mpll0.hw,
+ [CLKID_MPLL1] = &g12a_mpll1.hw,
+ [CLKID_MPLL2] = &g12a_mpll2.hw,
+ [CLKID_MPLL3] = &g12a_mpll3.hw,
+ [CLKID_DDR] = &g12a_ddr.hw,
+ [CLKID_DOS] = &g12a_dos.hw,
+ [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
+ [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
+ [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
+ [CLKID_ISA] = &g12a_isa.hw,
+ [CLKID_PL301] = &g12a_pl301.hw,
+ [CLKID_PERIPHS] = &g12a_periphs.hw,
+ [CLKID_SPICC0] = &g12a_spicc_0.hw,
+ [CLKID_I2C] = &g12a_i2c.hw,
+ [CLKID_SANA] = &g12a_sana.hw,
+ [CLKID_SD] = &g12a_sd.hw,
+ [CLKID_RNG0] = &g12a_rng0.hw,
+ [CLKID_UART0] = &g12a_uart0.hw,
+ [CLKID_SPICC1] = &g12a_spicc_1.hw,
+ [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
+ [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
+ [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
+ [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
+ [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
+ [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
+ [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
+ [CLKID_AUDIO] = &g12a_audio.hw,
+ [CLKID_ETH] = &g12a_eth_core.hw,
+ [CLKID_DEMUX] = &g12a_demux.hw,
+ [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
+ [CLKID_ADC] = &g12a_adc.hw,
+ [CLKID_UART1] = &g12a_uart1.hw,
+ [CLKID_G2D] = &g12a_g2d.hw,
+ [CLKID_RESET] = &g12a_reset.hw,
+ [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
+ [CLKID_PARSER] = &g12a_parser.hw,
+ [CLKID_USB] = &g12a_usb_general.hw,
+ [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
+ [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
+ [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
+ [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
+ [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
+ [CLKID_BT656] = &g12a_bt656.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
+ [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
+ [CLKID_UART2] = &g12a_uart2.hw,
+ [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
+ [CLKID_GIC] = &g12a_gic.hw,
+ [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
+ [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
+ [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
+ [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
+ [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
+ [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
+ [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
+ [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
+ [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
+ [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
+ [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
+ [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
+ [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
+ [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
+ [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
+ [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
+ [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
+ [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
+ [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
+ [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
+ [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
+ [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
+ [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
+ [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
+ [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
+ [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
+ [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
+ [CLKID_IEC958] = &g12a_iec958_gate.hw,
+ [CLKID_ENC480P] = &g12a_enc480p.hw,
+ [CLKID_RNG1] = &g12a_rng1.hw,
+ [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
+ [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
+ [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
+ [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
+ [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
+ [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
+ [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
+ [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
+ [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
+ [CLKID_DMA] = &g12a_dma.hw,
+ [CLKID_EFUSE] = &g12a_efuse.hw,
+ [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
+ [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
+ [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
+ [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
+ [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
+ [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
+ [CLKID_VPU_0] = &g12a_vpu_0.hw,
+ [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
+ [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
+ [CLKID_VPU_1] = &g12a_vpu_1.hw,
+ [CLKID_VPU] = &g12a_vpu.hw,
+ [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
+ [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
+ [CLKID_VAPB_0] = &g12a_vapb_0.hw,
+ [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
+ [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
+ [CLKID_VAPB_1] = &g12a_vapb_1.hw,
+ [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
+ [CLKID_VAPB] = &g12a_vapb.hw,
+ [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
+ [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
+ [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
+ [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
+ [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
+ [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
+ [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
+ [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
+ [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
+ [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
+ [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
+ [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
+ [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
+ [CLKID_VCLK] = &g12a_vclk.hw,
+ [CLKID_VCLK2] = &g12a_vclk2.hw,
+ [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
+ [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
+ [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
+ [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
+ [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
+ [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
+ [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
+ [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
+ [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
+ [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
+ [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
+ [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
+ [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
+ [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
+ [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
+ [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
+ [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
+ [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
+ [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
+ [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
+ [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
+ [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
+ [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
+ [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
+ [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
+ [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
+ [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
+ [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
+ [CLKID_HDMI] = &g12a_hdmi.hw,
+ [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
+ [CLKID_MALI_0] = &g12a_mali_0.hw,
+ [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
+ [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
+ [CLKID_MALI_1] = &g12a_mali_1.hw,
+ [CLKID_MALI] = &g12a_mali.hw,
+ [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
+ [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
+ [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
+ [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
+ [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
+ [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
+ [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
+ [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
+ [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
+ [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
+ [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
+ [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
+ [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
+ [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
+ [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
+ [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
+ [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
+ [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
+ [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
+ [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
+ [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
+ [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
+ [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
+ [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
+ [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
+ [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
+ [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
+ [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
+ [CLKID_VDEC_1] = &g12a_vdec_1.hw,
+ [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
+ [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
+ [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
+ [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
+ [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
+ [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
+ [CLKID_TS_DIV] = &g12a_ts_div.hw,
+ [CLKID_TS] = &g12a_ts.hw,
+ [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
+ [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
+ [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
+ [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
+ [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
+ [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
+ [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
+ [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
+ [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
+ [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
+ [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
+ [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
+ [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
+ [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
+ [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
+ [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
+ [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
+ [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
+ [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
+ [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
+ [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
+ [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
+ [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
+ [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
+ [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
+ [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
+ [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
+ [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
+ [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
};
/* Convenience table to populate regmap in .probe */
@@ -5274,7 +5264,7 @@ static int meson_g12a_dvfs_setup_common(struct device *dev,
static int meson_g12b_dvfs_setup(struct platform_device *pdev)
{
- struct clk_hw **hws = g12b_hw_onecell_data.hws;
+ struct clk_hw **hws = g12b_hw_clks;
struct device *dev = &pdev->dev;
struct clk *notifier_clk;
struct clk_hw *xtal;
@@ -5351,7 +5341,7 @@ static int meson_g12b_dvfs_setup(struct platform_device *pdev)
static int meson_g12a_dvfs_setup(struct platform_device *pdev)
{
- struct clk_hw **hws = g12a_hw_onecell_data.hws;
+ struct clk_hw **hws = g12a_hw_clks;
struct device *dev = &pdev->dev;
struct clk *notifier_clk;
int ret;
@@ -5413,7 +5403,10 @@ static const struct meson_g12a_data g12a_clkc_data = {
.eeclkc_data = {
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
- .hw_onecell_data = &g12a_hw_onecell_data,
+ .hw_clks = {
+ .hws = g12a_hw_clks,
+ .num = ARRAY_SIZE(g12a_hw_clks),
+ },
.init_regs = g12a_init_regs,
.init_count = ARRAY_SIZE(g12a_init_regs),
},
@@ -5424,7 +5417,10 @@ static const struct meson_g12a_data g12b_clkc_data = {
.eeclkc_data = {
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
- .hw_onecell_data = &g12b_hw_onecell_data,
+ .hw_clks = {
+ .hws = g12b_hw_clks,
+ .num = ARRAY_SIZE(g12b_hw_clks),
+ },
},
.dvfs_setup = meson_g12b_dvfs_setup,
};
@@ -5433,7 +5429,10 @@ static const struct meson_g12a_data sm1_clkc_data = {
.eeclkc_data = {
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
- .hw_onecell_data = &sm1_hw_onecell_data,
+ .hw_clks = {
+ .hws = sm1_hw_clks,
+ .num = ARRAY_SIZE(sm1_hw_clks),
+ },
},
.dvfs_setup = meson_g12a_dvfs_setup,
};
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index a97613df38b3..f11ee3c59849 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -126,149 +126,4 @@
#define HHI_SYS1_PLL_CNTL5 0x394
#define HHI_SYS1_PLL_CNTL6 0x398
-/*
- * CLKID index values
- *
- * These indices are entirely contrived and do not map onto the hardware.
- * It has now been decided to expose everything by default in the DT header:
- * include/dt-bindings/clock/g12a-clkc.h. Only the clocks ids we don't want
- * to expose, such as the internal muxes and dividers of composite clocks,
- * will remain defined here.
- */
-#define CLKID_MPEG_SEL 8
-#define CLKID_MPEG_DIV 9
-#define CLKID_SD_EMMC_A_CLK0_SEL 63
-#define CLKID_SD_EMMC_A_CLK0_DIV 64
-#define CLKID_SD_EMMC_B_CLK0_SEL 65
-#define CLKID_SD_EMMC_B_CLK0_DIV 66
-#define CLKID_SD_EMMC_C_CLK0_SEL 67
-#define CLKID_SD_EMMC_C_CLK0_DIV 68
-#define CLKID_MPLL0_DIV 69
-#define CLKID_MPLL1_DIV 70
-#define CLKID_MPLL2_DIV 71
-#define CLKID_MPLL3_DIV 72
-#define CLKID_MPLL_PREDIV 73
-#define CLKID_FCLK_DIV2_DIV 75
-#define CLKID_FCLK_DIV3_DIV 76
-#define CLKID_FCLK_DIV4_DIV 77
-#define CLKID_FCLK_DIV5_DIV 78
-#define CLKID_FCLK_DIV7_DIV 79
-#define CLKID_FCLK_DIV2P5_DIV 100
-#define CLKID_FIXED_PLL_DCO 101
-#define CLKID_SYS_PLL_DCO 102
-#define CLKID_GP0_PLL_DCO 103
-#define CLKID_HIFI_PLL_DCO 104
-#define CLKID_VPU_0_DIV 111
-#define CLKID_VPU_1_DIV 114
-#define CLKID_VAPB_0_DIV 118
-#define CLKID_VAPB_1_DIV 121
-#define CLKID_HDMI_PLL_DCO 125
-#define CLKID_HDMI_PLL_OD 126
-#define CLKID_HDMI_PLL_OD2 127
-#define CLKID_VID_PLL_SEL 130
-#define CLKID_VID_PLL_DIV 131
-#define CLKID_VCLK_SEL 132
-#define CLKID_VCLK2_SEL 133
-#define CLKID_VCLK_INPUT 134
-#define CLKID_VCLK2_INPUT 135
-#define CLKID_VCLK_DIV 136
-#define CLKID_VCLK2_DIV 137
-#define CLKID_VCLK_DIV2_EN 140
-#define CLKID_VCLK_DIV4_EN 141
-#define CLKID_VCLK_DIV6_EN 142
-#define CLKID_VCLK_DIV12_EN 143
-#define CLKID_VCLK2_DIV2_EN 144
-#define CLKID_VCLK2_DIV4_EN 145
-#define CLKID_VCLK2_DIV6_EN 146
-#define CLKID_VCLK2_DIV12_EN 147
-#define CLKID_CTS_ENCI_SEL 158
-#define CLKID_CTS_ENCP_SEL 159
-#define CLKID_CTS_VDAC_SEL 160
-#define CLKID_HDMI_TX_SEL 161
-#define CLKID_HDMI_SEL 166
-#define CLKID_HDMI_DIV 167
-#define CLKID_MALI_0_DIV 170
-#define CLKID_MALI_1_DIV 173
-#define CLKID_MPLL_50M_DIV 176
-#define CLKID_SYS_PLL_DIV16_EN 178
-#define CLKID_SYS_PLL_DIV16 179
-#define CLKID_CPU_CLK_DYN0_SEL 180
-#define CLKID_CPU_CLK_DYN0_DIV 181
-#define CLKID_CPU_CLK_DYN0 182
-#define CLKID_CPU_CLK_DYN1_SEL 183
-#define CLKID_CPU_CLK_DYN1_DIV 184
-#define CLKID_CPU_CLK_DYN1 185
-#define CLKID_CPU_CLK_DYN 186
-#define CLKID_CPU_CLK_DIV16_EN 188
-#define CLKID_CPU_CLK_DIV16 189
-#define CLKID_CPU_CLK_APB_DIV 190
-#define CLKID_CPU_CLK_APB 191
-#define CLKID_CPU_CLK_ATB_DIV 192
-#define CLKID_CPU_CLK_ATB 193
-#define CLKID_CPU_CLK_AXI_DIV 194
-#define CLKID_CPU_CLK_AXI 195
-#define CLKID_CPU_CLK_TRACE_DIV 196
-#define CLKID_CPU_CLK_TRACE 197
-#define CLKID_PCIE_PLL_DCO 198
-#define CLKID_PCIE_PLL_DCO_DIV2 199
-#define CLKID_PCIE_PLL_OD 200
-#define CLKID_VDEC_1_SEL 202
-#define CLKID_VDEC_1_DIV 203
-#define CLKID_VDEC_HEVC_SEL 205
-#define CLKID_VDEC_HEVC_DIV 206
-#define CLKID_VDEC_HEVCF_SEL 208
-#define CLKID_VDEC_HEVCF_DIV 209
-#define CLKID_TS_DIV 211
-#define CLKID_SYS1_PLL_DCO 213
-#define CLKID_SYS1_PLL 214
-#define CLKID_SYS1_PLL_DIV16_EN 215
-#define CLKID_SYS1_PLL_DIV16 216
-#define CLKID_CPUB_CLK_DYN0_SEL 217
-#define CLKID_CPUB_CLK_DYN0_DIV 218
-#define CLKID_CPUB_CLK_DYN0 219
-#define CLKID_CPUB_CLK_DYN1_SEL 220
-#define CLKID_CPUB_CLK_DYN1_DIV 221
-#define CLKID_CPUB_CLK_DYN1 222
-#define CLKID_CPUB_CLK_DYN 223
-#define CLKID_CPUB_CLK_DIV16_EN 225
-#define CLKID_CPUB_CLK_DIV16 226
-#define CLKID_CPUB_CLK_DIV2 227
-#define CLKID_CPUB_CLK_DIV3 228
-#define CLKID_CPUB_CLK_DIV4 229
-#define CLKID_CPUB_CLK_DIV5 230
-#define CLKID_CPUB_CLK_DIV6 231
-#define CLKID_CPUB_CLK_DIV7 232
-#define CLKID_CPUB_CLK_DIV8 233
-#define CLKID_CPUB_CLK_APB_SEL 234
-#define CLKID_CPUB_CLK_APB 235
-#define CLKID_CPUB_CLK_ATB_SEL 236
-#define CLKID_CPUB_CLK_ATB 237
-#define CLKID_CPUB_CLK_AXI_SEL 238
-#define CLKID_CPUB_CLK_AXI 239
-#define CLKID_CPUB_CLK_TRACE_SEL 240
-#define CLKID_CPUB_CLK_TRACE 241
-#define CLKID_GP1_PLL_DCO 242
-#define CLKID_DSU_CLK_DYN0_SEL 244
-#define CLKID_DSU_CLK_DYN0_DIV 245
-#define CLKID_DSU_CLK_DYN0 246
-#define CLKID_DSU_CLK_DYN1_SEL 247
-#define CLKID_DSU_CLK_DYN1_DIV 248
-#define CLKID_DSU_CLK_DYN1 249
-#define CLKID_DSU_CLK_DYN 250
-#define CLKID_DSU_CLK_FINAL 251
-#define CLKID_SPICC0_SCLK_SEL 256
-#define CLKID_SPICC0_SCLK_DIV 257
-#define CLKID_SPICC1_SCLK_SEL 259
-#define CLKID_SPICC1_SCLK_DIV 260
-#define CLKID_NNA_AXI_CLK_SEL 262
-#define CLKID_NNA_AXI_CLK_DIV 263
-#define CLKID_NNA_CORE_CLK_SEL 265
-#define CLKID_NNA_CORE_CLK_DIV 266
-#define CLKID_MIPI_DSI_PXCLK_DIV 268
-
-#define NR_CLKS 271
-
-/* include the CLKIDs that have been made part of the DT binding */
-#include <dt-bindings/clock/g12a-clkc.h>
-
#endif /* __G12A_H */
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index fce95cf89836..4aec1740ac34 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -7,11 +7,13 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include "meson-aoclk.h"
-#include "gxbb-aoclk.h"
#include "clk-regmap.h"
#include "clk-dualdiv.h"
+#include <dt-bindings/clock/gxbb-aoclkc.h>
+#include <dt-bindings/reset/gxbb-aoclkc.h>
+
/* AO Configuration Clock registers offsets */
#define AO_RTI_PWR_CNTL_REG1 0x0c
#define AO_RTI_PWR_CNTL_REG0 0x10
@@ -252,8 +254,7 @@ static struct clk_regmap *gxbb_aoclk[] = {
&ao_cts_cec,
};
-static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
- .hws = {
+static struct clk_hw *gxbb_aoclk_hw_clks[] = {
[CLKID_AO_REMOTE] = &remote_ao.hw,
[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
[CLKID_AO_I2C_SLAVE] = &i2c_slave_ao.hw,
@@ -268,8 +269,6 @@ static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
[CLKID_AO_32K] = &ao_32k.hw,
[CLKID_AO_CTS_RTC_OSCIN] = &ao_cts_rtc_oscin.hw,
[CLKID_AO_CLK81] = &ao_clk81.hw,
- },
- .num = NR_CLKS,
};
static const struct meson_aoclk_data gxbb_aoclkc_data = {
@@ -278,7 +277,10 @@ static const struct meson_aoclk_data gxbb_aoclkc_data = {
.reset = gxbb_aoclk_reset,
.num_clks = ARRAY_SIZE(gxbb_aoclk),
.clks = gxbb_aoclk,
- .hw_data = &gxbb_aoclk_onecell_data,
+ .hw_clks = {
+ .hws = gxbb_aoclk_hw_clks,
+ .num = ARRAY_SIZE(gxbb_aoclk_hw_clks),
+ },
};
static const struct of_device_id gxbb_aoclkc_match_table[] = {
diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
deleted file mode 100644
index 1db16f9b37d4..000000000000
--- a/drivers/clk/meson/gxbb-aoclk.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2017 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef __GXBB_AOCLKC_H
-#define __GXBB_AOCLKC_H
-
-#define NR_CLKS 14
-
-#include <dt-bindings/clock/gxbb-aoclkc.h>
-#include <dt-bindings/reset/gxbb-aoclkc.h>
-
-#endif /* __GXBB_AOCLKC_H */
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 608e0e8ca49a..1b1279d94781 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -6,7 +6,7 @@
#include <linux/clk-provider.h>
#include <linux/init.h>
-#include <linux/of_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/module.h>
@@ -17,6 +17,8 @@
#include "meson-eeclk.h"
#include "vid-pll-div.h"
+#include <dt-bindings/clock/gxbb-clkc.h>
+
static DEFINE_SPINLOCK(meson_clk_lock);
static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
@@ -2728,428 +2730,420 @@ static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);
/* Array of all clocks provided by this provider */
-static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
- .hws = {
- [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
- [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
- [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
- [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
- [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
- [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
- [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
- [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
- [CLKID_CLK81] = &gxbb_clk81.hw,
- [CLKID_MPLL0] = &gxbb_mpll0.hw,
- [CLKID_MPLL1] = &gxbb_mpll1.hw,
- [CLKID_MPLL2] = &gxbb_mpll2.hw,
- [CLKID_DDR] = &gxbb_ddr.hw,
- [CLKID_DOS] = &gxbb_dos.hw,
- [CLKID_ISA] = &gxbb_isa.hw,
- [CLKID_PL301] = &gxbb_pl301.hw,
- [CLKID_PERIPHS] = &gxbb_periphs.hw,
- [CLKID_SPICC] = &gxbb_spicc.hw,
- [CLKID_I2C] = &gxbb_i2c.hw,
- [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
- [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
- [CLKID_RNG0] = &gxbb_rng0.hw,
- [CLKID_UART0] = &gxbb_uart0.hw,
- [CLKID_SDHC] = &gxbb_sdhc.hw,
- [CLKID_STREAM] = &gxbb_stream.hw,
- [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
- [CLKID_SDIO] = &gxbb_sdio.hw,
- [CLKID_ABUF] = &gxbb_abuf.hw,
- [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
- [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
- [CLKID_SPI] = &gxbb_spi.hw,
- [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
- [CLKID_ETH] = &gxbb_eth.hw,
- [CLKID_DEMUX] = &gxbb_demux.hw,
- [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
- [CLKID_IEC958] = &gxbb_iec958.hw,
- [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
- [CLKID_AMCLK] = &gxbb_amclk.hw,
- [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
- [CLKID_MIXER] = &gxbb_mixer.hw,
- [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
- [CLKID_ADC] = &gxbb_adc.hw,
- [CLKID_BLKMV] = &gxbb_blkmv.hw,
- [CLKID_AIU] = &gxbb_aiu.hw,
- [CLKID_UART1] = &gxbb_uart1.hw,
- [CLKID_G2D] = &gxbb_g2d.hw,
- [CLKID_USB0] = &gxbb_usb0.hw,
- [CLKID_USB1] = &gxbb_usb1.hw,
- [CLKID_RESET] = &gxbb_reset.hw,
- [CLKID_NAND] = &gxbb_nand.hw,
- [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
- [CLKID_USB] = &gxbb_usb.hw,
- [CLKID_VDIN1] = &gxbb_vdin1.hw,
- [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
- [CLKID_EFUSE] = &gxbb_efuse.hw,
- [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
- [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
- [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
- [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
- [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
- [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
- [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
- [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
- [CLKID_DVIN] = &gxbb_dvin.hw,
- [CLKID_UART2] = &gxbb_uart2.hw,
- [CLKID_SANA] = &gxbb_sana.hw,
- [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
- [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
- [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
- [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
- [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
- [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
- [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
- [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
- [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
- [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
- [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
- [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
- [CLKID_ENC480P] = &gxbb_enc480p.hw,
- [CLKID_RNG1] = &gxbb_rng1.hw,
- [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
- [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
- [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
- [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
- [CLKID_EDP] = &gxbb_edp.hw,
- [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
- [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
- [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
- [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
- [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
- [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
- [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
- [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
- [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
- [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
- [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
- [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
- [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
- [CLKID_MALI_0] = &gxbb_mali_0.hw,
- [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
- [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
- [CLKID_MALI_1] = &gxbb_mali_1.hw,
- [CLKID_MALI] = &gxbb_mali.hw,
- [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
- [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
- [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
- [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
- [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
- [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
- [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
- [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
- [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
- [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
- [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
- [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
- [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
- [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
- [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
- [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
- [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
- [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
- [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
- [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
- [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
- [CLKID_VPU_0] = &gxbb_vpu_0.hw,
- [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
- [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
- [CLKID_VPU_1] = &gxbb_vpu_1.hw,
- [CLKID_VPU] = &gxbb_vpu.hw,
- [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
- [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
- [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
- [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
- [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
- [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
- [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
- [CLKID_VAPB] = &gxbb_vapb.hw,
- [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw,
- [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
- [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
- [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
- [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
- [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
- [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
- [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
- [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
- [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
- [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
- [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
- [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
- [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
- [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
- [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
- [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,
- [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw,
- [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw,
- [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
- [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw,
- [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
- [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
- [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
- [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
- [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
- [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
- [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
- [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
- [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
- [CLKID_VCLK] = &gxbb_vclk.hw,
- [CLKID_VCLK2] = &gxbb_vclk2.hw,
- [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
- [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
- [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
- [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
- [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
- [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
- [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
- [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
- [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
- [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
- [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
- [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
- [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
- [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
- [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
- [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
- [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
- [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
- [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
- [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
- [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
- [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
- [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
- [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
- [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
- [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
- [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
- [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
- [CLKID_HDMI] = &gxbb_hdmi.hw,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
-};
-
-static struct clk_hw_onecell_data gxl_hw_onecell_data = {
- .hws = {
- [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
- [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw,
- [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
- [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
- [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
- [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
- [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
- [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
- [CLKID_CLK81] = &gxbb_clk81.hw,
- [CLKID_MPLL0] = &gxbb_mpll0.hw,
- [CLKID_MPLL1] = &gxbb_mpll1.hw,
- [CLKID_MPLL2] = &gxbb_mpll2.hw,
- [CLKID_DDR] = &gxbb_ddr.hw,
- [CLKID_DOS] = &gxbb_dos.hw,
- [CLKID_ISA] = &gxbb_isa.hw,
- [CLKID_PL301] = &gxbb_pl301.hw,
- [CLKID_PERIPHS] = &gxbb_periphs.hw,
- [CLKID_SPICC] = &gxbb_spicc.hw,
- [CLKID_I2C] = &gxbb_i2c.hw,
- [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
- [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
- [CLKID_RNG0] = &gxbb_rng0.hw,
- [CLKID_UART0] = &gxbb_uart0.hw,
- [CLKID_SDHC] = &gxbb_sdhc.hw,
- [CLKID_STREAM] = &gxbb_stream.hw,
- [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
- [CLKID_SDIO] = &gxbb_sdio.hw,
- [CLKID_ABUF] = &gxbb_abuf.hw,
- [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
- [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
- [CLKID_SPI] = &gxbb_spi.hw,
- [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
- [CLKID_ETH] = &gxbb_eth.hw,
- [CLKID_DEMUX] = &gxbb_demux.hw,
- [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
- [CLKID_IEC958] = &gxbb_iec958.hw,
- [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
- [CLKID_AMCLK] = &gxbb_amclk.hw,
- [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
- [CLKID_MIXER] = &gxbb_mixer.hw,
- [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
- [CLKID_ADC] = &gxbb_adc.hw,
- [CLKID_BLKMV] = &gxbb_blkmv.hw,
- [CLKID_AIU] = &gxbb_aiu.hw,
- [CLKID_UART1] = &gxbb_uart1.hw,
- [CLKID_G2D] = &gxbb_g2d.hw,
- [CLKID_USB0] = &gxbb_usb0.hw,
- [CLKID_USB1] = &gxbb_usb1.hw,
- [CLKID_RESET] = &gxbb_reset.hw,
- [CLKID_NAND] = &gxbb_nand.hw,
- [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
- [CLKID_USB] = &gxbb_usb.hw,
- [CLKID_VDIN1] = &gxbb_vdin1.hw,
- [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
- [CLKID_EFUSE] = &gxbb_efuse.hw,
- [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
- [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
- [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
- [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
- [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
- [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
- [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
- [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
- [CLKID_DVIN] = &gxbb_dvin.hw,
- [CLKID_UART2] = &gxbb_uart2.hw,
- [CLKID_SANA] = &gxbb_sana.hw,
- [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
- [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
- [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
- [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
- [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
- [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
- [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
- [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
- [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
- [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
- [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
- [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
- [CLKID_ENC480P] = &gxbb_enc480p.hw,
- [CLKID_RNG1] = &gxbb_rng1.hw,
- [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
- [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
- [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
- [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
- [CLKID_EDP] = &gxbb_edp.hw,
- [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
- [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
- [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
- [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
- [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
- [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
- [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
- [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
- [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
- [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
- [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
- [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
- [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
- [CLKID_MALI_0] = &gxbb_mali_0.hw,
- [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
- [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
- [CLKID_MALI_1] = &gxbb_mali_1.hw,
- [CLKID_MALI] = &gxbb_mali.hw,
- [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
- [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
- [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
- [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
- [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
- [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
- [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
- [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
- [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
- [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
- [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
- [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
- [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
- [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
- [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
- [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
- [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
- [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
- [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
- [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
- [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
- [CLKID_VPU_0] = &gxbb_vpu_0.hw,
- [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
- [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
- [CLKID_VPU_1] = &gxbb_vpu_1.hw,
- [CLKID_VPU] = &gxbb_vpu.hw,
- [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
- [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
- [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
- [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
- [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
- [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
- [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
- [CLKID_VAPB] = &gxbb_vapb.hw,
- [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw,
- [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
- [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
- [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
- [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
- [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
- [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
- [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
- [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
- [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
- [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
- [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
- [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
- [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
- [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
- [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw,
- [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw,
- [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw,
- [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
- [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw,
- [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
- [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
- [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
- [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
- [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
- [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
- [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
- [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
- [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
- [CLKID_VCLK] = &gxbb_vclk.hw,
- [CLKID_VCLK2] = &gxbb_vclk2.hw,
- [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
- [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
- [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
- [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
- [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
- [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
- [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
- [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
- [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
- [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
- [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
- [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
- [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
- [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
- [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
- [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
- [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
- [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
- [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
- [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
- [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
- [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
- [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
- [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
- [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
- [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
- [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
- [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
- [CLKID_HDMI] = &gxbb_hdmi.hw,
- [CLKID_ACODEC] = &gxl_acodec.hw,
- [NR_CLKS] = NULL,
- },
- .num = NR_CLKS,
+static struct clk_hw *gxbb_hw_clks[] = {
+ [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
+ [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
+ [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
+ [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
+ [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
+ [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &gxbb_clk81.hw,
+ [CLKID_MPLL0] = &gxbb_mpll0.hw,
+ [CLKID_MPLL1] = &gxbb_mpll1.hw,
+ [CLKID_MPLL2] = &gxbb_mpll2.hw,
+ [CLKID_DDR] = &gxbb_ddr.hw,
+ [CLKID_DOS] = &gxbb_dos.hw,
+ [CLKID_ISA] = &gxbb_isa.hw,
+ [CLKID_PL301] = &gxbb_pl301.hw,
+ [CLKID_PERIPHS] = &gxbb_periphs.hw,
+ [CLKID_SPICC] = &gxbb_spicc.hw,
+ [CLKID_I2C] = &gxbb_i2c.hw,
+ [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
+ [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
+ [CLKID_RNG0] = &gxbb_rng0.hw,
+ [CLKID_UART0] = &gxbb_uart0.hw,
+ [CLKID_SDHC] = &gxbb_sdhc.hw,
+ [CLKID_STREAM] = &gxbb_stream.hw,
+ [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
+ [CLKID_SDIO] = &gxbb_sdio.hw,
+ [CLKID_ABUF] = &gxbb_abuf.hw,
+ [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
+ [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
+ [CLKID_SPI] = &gxbb_spi.hw,
+ [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
+ [CLKID_ETH] = &gxbb_eth.hw,
+ [CLKID_DEMUX] = &gxbb_demux.hw,
+ [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
+ [CLKID_IEC958] = &gxbb_iec958.hw,
+ [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
+ [CLKID_AMCLK] = &gxbb_amclk.hw,
+ [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
+ [CLKID_MIXER] = &gxbb_mixer.hw,
+ [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
+ [CLKID_ADC] = &gxbb_adc.hw,
+ [CLKID_BLKMV] = &gxbb_blkmv.hw,
+ [CLKID_AIU] = &gxbb_aiu.hw,
+ [CLKID_UART1] = &gxbb_uart1.hw,
+ [CLKID_G2D] = &gxbb_g2d.hw,
+ [CLKID_USB0] = &gxbb_usb0.hw,
+ [CLKID_USB1] = &gxbb_usb1.hw,
+ [CLKID_RESET] = &gxbb_reset.hw,
+ [CLKID_NAND] = &gxbb_nand.hw,
+ [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
+ [CLKID_USB] = &gxbb_usb.hw,
+ [CLKID_VDIN1] = &gxbb_vdin1.hw,
+ [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
+ [CLKID_EFUSE] = &gxbb_efuse.hw,
+ [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
+ [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
+ [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
+ [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
+ [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
+ [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
+ [CLKID_DVIN] = &gxbb_dvin.hw,
+ [CLKID_UART2] = &gxbb_uart2.hw,
+ [CLKID_SANA] = &gxbb_sana.hw,
+ [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
+ [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
+ [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
+ [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
+ [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
+ [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
+ [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
+ [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
+ [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
+ [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
+ [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
+ [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
+ [CLKID_ENC480P] = &gxbb_enc480p.hw,
+ [CLKID_RNG1] = &gxbb_rng1.hw,
+ [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
+ [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
+ [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
+ [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
+ [CLKID_EDP] = &gxbb_edp.hw,
+ [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
+ [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
+ [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
+ [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
+ [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
+ [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
+ [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
+ [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
+ [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
+ [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
+ [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
+ [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
+ [CLKID_MALI_0] = &gxbb_mali_0.hw,
+ [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
+ [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
+ [CLKID_MALI_1] = &gxbb_mali_1.hw,
+ [CLKID_MALI] = &gxbb_mali.hw,
+ [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
+ [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
+ [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
+ [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
+ [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
+ [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
+ [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
+ [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
+ [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
+ [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
+ [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
+ [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
+ [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
+ [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
+ [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
+ [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
+ [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
+ [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
+ [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
+ [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
+ [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
+ [CLKID_VPU_0] = &gxbb_vpu_0.hw,
+ [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
+ [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
+ [CLKID_VPU_1] = &gxbb_vpu_1.hw,
+ [CLKID_VPU] = &gxbb_vpu.hw,
+ [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
+ [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
+ [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
+ [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
+ [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
+ [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
+ [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
+ [CLKID_VAPB] = &gxbb_vapb.hw,
+ [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw,
+ [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
+ [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
+ [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
+ [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
+ [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
+ [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
+ [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
+ [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
+ [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
+ [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
+ [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
+ [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
+ [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
+ [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
+ [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
+ [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,
+ [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw,
+ [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw,
+ [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
+ [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw,
+ [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
+ [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
+ [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
+ [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
+ [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
+ [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
+ [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
+ [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
+ [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
+ [CLKID_VCLK] = &gxbb_vclk.hw,
+ [CLKID_VCLK2] = &gxbb_vclk2.hw,
+ [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
+ [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
+ [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
+ [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
+ [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
+ [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
+ [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
+ [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
+ [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
+ [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
+ [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
+ [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
+ [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
+ [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
+ [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
+ [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
+ [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
+ [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
+ [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
+ [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
+ [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
+ [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
+ [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
+ [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
+ [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
+ [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
+ [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
+ [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
+ [CLKID_HDMI] = &gxbb_hdmi.hw,
+};
+
+static struct clk_hw *gxl_hw_clks[] = {
+ [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
+ [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw,
+ [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
+ [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
+ [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
+ [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &gxbb_clk81.hw,
+ [CLKID_MPLL0] = &gxbb_mpll0.hw,
+ [CLKID_MPLL1] = &gxbb_mpll1.hw,
+ [CLKID_MPLL2] = &gxbb_mpll2.hw,
+ [CLKID_DDR] = &gxbb_ddr.hw,
+ [CLKID_DOS] = &gxbb_dos.hw,
+ [CLKID_ISA] = &gxbb_isa.hw,
+ [CLKID_PL301] = &gxbb_pl301.hw,
+ [CLKID_PERIPHS] = &gxbb_periphs.hw,
+ [CLKID_SPICC] = &gxbb_spicc.hw,
+ [CLKID_I2C] = &gxbb_i2c.hw,
+ [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
+ [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
+ [CLKID_RNG0] = &gxbb_rng0.hw,
+ [CLKID_UART0] = &gxbb_uart0.hw,
+ [CLKID_SDHC] = &gxbb_sdhc.hw,
+ [CLKID_STREAM] = &gxbb_stream.hw,
+ [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
+ [CLKID_SDIO] = &gxbb_sdio.hw,
+ [CLKID_ABUF] = &gxbb_abuf.hw,
+ [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
+ [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
+ [CLKID_SPI] = &gxbb_spi.hw,
+ [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
+ [CLKID_ETH] = &gxbb_eth.hw,
+ [CLKID_DEMUX] = &gxbb_demux.hw,
+ [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
+ [CLKID_IEC958] = &gxbb_iec958.hw,
+ [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
+ [CLKID_AMCLK] = &gxbb_amclk.hw,
+ [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
+ [CLKID_MIXER] = &gxbb_mixer.hw,
+ [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
+ [CLKID_ADC] = &gxbb_adc.hw,
+ [CLKID_BLKMV] = &gxbb_blkmv.hw,
+ [CLKID_AIU] = &gxbb_aiu.hw,
+ [CLKID_UART1] = &gxbb_uart1.hw,
+ [CLKID_G2D] = &gxbb_g2d.hw,
+ [CLKID_USB0] = &gxbb_usb0.hw,
+ [CLKID_USB1] = &gxbb_usb1.hw,
+ [CLKID_RESET] = &gxbb_reset.hw,
+ [CLKID_NAND] = &gxbb_nand.hw,
+ [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
+ [CLKID_USB] = &gxbb_usb.hw,
+ [CLKID_VDIN1] = &gxbb_vdin1.hw,
+ [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
+ [CLKID_EFUSE] = &gxbb_efuse.hw,
+ [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
+ [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
+ [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
+ [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
+ [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
+ [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
+ [CLKID_DVIN] = &gxbb_dvin.hw,
+ [CLKID_UART2] = &gxbb_uart2.hw,
+ [CLKID_SANA] = &gxbb_sana.hw,
+ [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
+ [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
+ [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
+ [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
+ [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
+ [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
+ [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
+ [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
+ [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
+ [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
+ [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
+ [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
+ [CLKID_ENC480P] = &gxbb_enc480p.hw,
+ [CLKID_RNG1] = &gxbb_rng1.hw,
+ [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
+ [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
+ [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
+ [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
+ [CLKID_EDP] = &gxbb_edp.hw,
+ [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
+ [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
+ [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
+ [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
+ [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
+ [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
+ [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
+ [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
+ [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
+ [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
+ [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
+ [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
+ [CLKID_MALI_0] = &gxbb_mali_0.hw,
+ [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
+ [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
+ [CLKID_MALI_1] = &gxbb_mali_1.hw,
+ [CLKID_MALI] = &gxbb_mali.hw,
+ [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
+ [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
+ [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
+ [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
+ [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
+ [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
+ [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
+ [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
+ [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
+ [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
+ [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
+ [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
+ [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
+ [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
+ [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
+ [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
+ [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
+ [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
+ [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
+ [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
+ [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
+ [CLKID_VPU_0] = &gxbb_vpu_0.hw,
+ [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
+ [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
+ [CLKID_VPU_1] = &gxbb_vpu_1.hw,
+ [CLKID_VPU] = &gxbb_vpu.hw,
+ [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
+ [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
+ [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
+ [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
+ [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
+ [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
+ [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
+ [CLKID_VAPB] = &gxbb_vapb.hw,
+ [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw,
+ [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
+ [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
+ [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
+ [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
+ [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
+ [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
+ [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
+ [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
+ [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
+ [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
+ [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
+ [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
+ [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
+ [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
+ [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw,
+ [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw,
+ [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw,
+ [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
+ [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw,
+ [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
+ [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
+ [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
+ [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
+ [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
+ [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
+ [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
+ [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
+ [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
+ [CLKID_VCLK] = &gxbb_vclk.hw,
+ [CLKID_VCLK2] = &gxbb_vclk2.hw,
+ [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
+ [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
+ [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
+ [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
+ [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
+ [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
+ [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
+ [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
+ [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
+ [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
+ [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
+ [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
+ [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
+ [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
+ [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
+ [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
+ [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
+ [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
+ [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
+ [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
+ [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
+ [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
+ [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
+ [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
+ [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
+ [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
+ [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
+ [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
+ [CLKID_HDMI] = &gxbb_hdmi.hw,
+ [CLKID_ACODEC] = &gxl_acodec.hw,
};
static struct clk_regmap *const gxbb_clk_regmaps[] = {
@@ -3544,13 +3538,19 @@ static struct clk_regmap *const gxl_clk_regmaps[] = {
static const struct meson_eeclkc_data gxbb_clkc_data = {
.regmap_clks = gxbb_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps),
- .hw_onecell_data = &gxbb_hw_onecell_data,
+ .hw_clks = {
+ .hws = gxbb_hw_clks,
+ .num = ARRAY_SIZE(gxbb_hw_clks),
+ },
};
static const struct meson_eeclkc_data gxl_clkc_data = {
.regmap_clks = gxl_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps),
- .hw_onecell_data = &gxl_hw_onecell_data,
+ .hw_clks = {
+ .hws = gxl_hw_clks,
+ .num = ARRAY_SIZE(gxl_hw_clks),
+ },
};
static const struct of_device_id clkc_match_table[] = {
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 1ee8cb7e2f5a..ba5f39a8d746 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -112,85 +112,4 @@
#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */
#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */
-/*
- * CLKID index values
- *
- * These indices are entirely contrived and do not map onto the hardware.
- * It has now been decided to expose everything by default in the DT header:
- * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
- * to expose, such as the internal muxes and dividers of composite clocks,
- * will remain defined here.
- */
-/* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */
-#define CLKID_MPEG_SEL 10
-#define CLKID_MPEG_DIV 11
-#define CLKID_SAR_ADC_DIV 99
-#define CLKID_MALI_0_DIV 101
-#define CLKID_MALI_1_DIV 104
-#define CLKID_CTS_AMCLK_SEL 108
-#define CLKID_CTS_AMCLK_DIV 109
-#define CLKID_CTS_MCLK_I958_SEL 111
-#define CLKID_CTS_MCLK_I958_DIV 112
-#define CLKID_32K_CLK_SEL 115
-#define CLKID_32K_CLK_DIV 116
-#define CLKID_SD_EMMC_A_CLK0_SEL 117
-#define CLKID_SD_EMMC_A_CLK0_DIV 118
-#define CLKID_SD_EMMC_B_CLK0_SEL 120
-#define CLKID_SD_EMMC_B_CLK0_DIV 121
-#define CLKID_SD_EMMC_C_CLK0_SEL 123
-#define CLKID_SD_EMMC_C_CLK0_DIV 124
-#define CLKID_VPU_0_DIV 127
-#define CLKID_VPU_1_DIV 130
-#define CLKID_VAPB_0_DIV 134
-#define CLKID_VAPB_1_DIV 137
-#define CLKID_HDMI_PLL_PRE_MULT 141
-#define CLKID_MPLL0_DIV 142
-#define CLKID_MPLL1_DIV 143
-#define CLKID_MPLL2_DIV 144
-#define CLKID_MPLL_PREDIV 145
-#define CLKID_FCLK_DIV2_DIV 146
-#define CLKID_FCLK_DIV3_DIV 147
-#define CLKID_FCLK_DIV4_DIV 148
-#define CLKID_FCLK_DIV5_DIV 149
-#define CLKID_FCLK_DIV7_DIV 150
-#define CLKID_VDEC_1_SEL 151
-#define CLKID_VDEC_1_DIV 152
-#define CLKID_VDEC_HEVC_SEL 154
-#define CLKID_VDEC_HEVC_DIV 155
-#define CLKID_GEN_CLK_SEL 157
-#define CLKID_GEN_CLK_DIV 158
-#define CLKID_FIXED_PLL_DCO 160
-#define CLKID_HDMI_PLL_DCO 161
-#define CLKID_HDMI_PLL_OD 162
-#define CLKID_HDMI_PLL_OD2 163
-#define CLKID_SYS_PLL_DCO 164
-#define CLKID_GP0_PLL_DCO 165
-#define CLKID_VID_PLL_SEL 167
-#define CLKID_VID_PLL_DIV 168
-#define CLKID_VCLK_SEL 169
-#define CLKID_VCLK2_SEL 170
-#define CLKID_VCLK_INPUT 171
-#define CLKID_VCLK2_INPUT 172
-#define CLKID_VCLK_DIV 173
-#define CLKID_VCLK2_DIV 174
-#define CLKID_VCLK_DIV2_EN 177
-#define CLKID_VCLK_DIV4_EN 178
-#define CLKID_VCLK_DIV6_EN 179
-#define CLKID_VCLK_DIV12_EN 180
-#define CLKID_VCLK2_DIV2_EN 181
-#define CLKID_VCLK2_DIV4_EN 182
-#define CLKID_VCLK2_DIV6_EN 183
-#define CLKID_VCLK2_DIV12_EN 184
-#define CLKID_CTS_ENCI_SEL 195
-#define CLKID_CTS_ENCP_SEL 196
-#define CLKID_CTS_VDAC_SEL 197
-#define CLKID_HDMI_TX_SEL 198
-#define CLKID_HDMI_SEL 203
-#define CLKID_HDMI_DIV 204
-
-#define NR_CLKS 207
-
-/* include the CLKIDs that have been made part of the DT binding */
-#include <dt-bindings/clock/gxbb-clkc.h>
-
#endif /* __GXBB_H */
diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
index 434cd8f9de82..bf466fef263c 100644
--- a/drivers/clk/meson/meson-aoclk.c
+++ b/drivers/clk/meson/meson-aoclk.c
@@ -13,7 +13,7 @@
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/mfd/syscon.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/module.h>
#include <linux/slab.h>
@@ -75,19 +75,18 @@ int meson_aoclkc_probe(struct platform_device *pdev)
data->clks[clkid]->map = regmap;
/* Register all clks */
- for (clkid = 0; clkid < data->hw_data->num; clkid++) {
- if (!data->hw_data->hws[clkid])
+ for (clkid = 0; clkid < data->hw_clks.num; clkid++) {
+ if (!data->hw_clks.hws[clkid])
continue;
- ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
+ ret = devm_clk_hw_register(dev, data->hw_clks.hws[clkid]);
if (ret) {
dev_err(dev, "Clock registration failed\n");
return ret;
}
}
- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
- (void *) data->hw_data);
+ return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
}
EXPORT_SYMBOL_GPL(meson_aoclkc_probe);
MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aoclk.h
index 605b43855a69..308be3e4814a 100644
--- a/drivers/clk/meson/meson-aoclk.h
+++ b/drivers/clk/meson/meson-aoclk.h
@@ -17,6 +17,7 @@
#include <linux/reset-controller.h>
#include "clk-regmap.h"
+#include "meson-clkc-utils.h"
struct meson_aoclk_data {
const unsigned int reset_reg;
@@ -24,7 +25,7 @@ struct meson_aoclk_data {
const unsigned int *reset;
const int num_clks;
struct clk_regmap **clks;
- const struct clk_hw_onecell_data *hw_data;
+ struct meson_clk_hw_data hw_clks;
};
struct meson_aoclk_reset_controller {
diff --git a/drivers/clk/meson/meson-clkc-utils.c b/drivers/clk/meson/meson-clkc-utils.c
new file mode 100644
index 000000000000..7370644e8092
--- /dev/null
+++ b/drivers/clk/meson/meson-clkc-utils.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
+ */
+
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include "meson-clkc-utils.h"
+
+struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data)
+{
+ const struct meson_clk_hw_data *data = clk_hw_data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx >= data->num) {
+ pr_err("%s: invalid index %u\n", __func__, idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return data->hws[idx];
+}
+EXPORT_SYMBOL_GPL(meson_clk_hw_get);
+
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/meson/meson-clkc-utils.h b/drivers/clk/meson/meson-clkc-utils.h
new file mode 100644
index 000000000000..fe6f40728949
--- /dev/null
+++ b/drivers/clk/meson/meson-clkc-utils.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
+ */
+
+#ifndef __MESON_CLKC_UTILS_H__
+#define __MESON_CLKC_UTILS_H__
+
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+
+struct meson_clk_hw_data {
+ struct clk_hw **hws;
+ unsigned int num;
+};
+
+struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data);
+
+#endif
diff --git a/drivers/clk/meson/meson-eeclk.c b/drivers/clk/meson/meson-eeclk.c
index 0e5e6b57eb20..845ca8bfa346 100644
--- a/drivers/clk/meson/meson-eeclk.c
+++ b/drivers/clk/meson/meson-eeclk.c
@@ -5,7 +5,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
@@ -43,20 +43,19 @@ int meson_eeclkc_probe(struct platform_device *pdev)
for (i = 0; i < data->regmap_clk_num; i++)
data->regmap_clks[i]->map = map;
- for (i = 0; i < data->hw_onecell_data->num; i++) {
+ for (i = 0; i < data->hw_clks.num; i++) {
/* array might be sparse */
- if (!data->hw_onecell_data->hws[i])
+ if (!data->hw_clks.hws[i])
continue;
- ret = devm_clk_hw_register(dev, data->hw_onecell_data->hws[i]);
+ ret = devm_clk_hw_register(dev, data->hw_clks.hws[i]);
if (ret) {
dev_err(dev, "Clock registration failed\n");
return ret;
}
}
- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
- data->hw_onecell_data);
+ return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
}
EXPORT_SYMBOL_GPL(meson_eeclkc_probe);
MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/meson/meson-eeclk.h b/drivers/clk/meson/meson-eeclk.h
index 77316207bde1..37a48b75c660 100644
--- a/drivers/clk/meson/meson-eeclk.h
+++ b/drivers/clk/meson/meson-eeclk.h
@@ -9,6 +9,7 @@
#include <linux/clk-provider.h>
#include "clk-regmap.h"
+#include "meson-clkc-utils.h"
struct platform_device;
@@ -17,7 +18,7 @@ struct meson_eeclkc_data {
unsigned int regmap_clk_num;
const struct reg_sequence *init_regs;
unsigned int init_count;
- struct clk_hw_onecell_data *hw_onecell_data;
+ struct meson_clk_hw_data hw_clks;
};
int meson_eeclkc_probe(struct platform_device *pdev);
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 827e78fb16a8..b7417ac262d3 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -18,9 +18,13 @@
#include "meson8b.h"
#include "clk-regmap.h"
+#include "meson-clkc-utils.h"
#include "clk-pll.h"
#include "clk-mpll.h"
+#include <dt-bindings/clock/meson8b-clkc.h>
+#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
+
static DEFINE_SPINLOCK(meson_clk_lock);
struct meson8b_clk_reset {
@@ -2772,652 +2776,640 @@ static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
-static struct clk_hw_onecell_data meson8_hw_onecell_data = {
- .hws = {
- [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
- [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
- [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
- [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
- [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
- [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
- [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
- [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
- [CLKID_CLK81] = &meson8b_clk81.hw,
- [CLKID_DDR] = &meson8b_ddr.hw,
- [CLKID_DOS] = &meson8b_dos.hw,
- [CLKID_ISA] = &meson8b_isa.hw,
- [CLKID_PL301] = &meson8b_pl301.hw,
- [CLKID_PERIPHS] = &meson8b_periphs.hw,
- [CLKID_SPICC] = &meson8b_spicc.hw,
- [CLKID_I2C] = &meson8b_i2c.hw,
- [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
- [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
- [CLKID_RNG0] = &meson8b_rng0.hw,
- [CLKID_UART0] = &meson8b_uart0.hw,
- [CLKID_SDHC] = &meson8b_sdhc.hw,
- [CLKID_STREAM] = &meson8b_stream.hw,
- [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
- [CLKID_SDIO] = &meson8b_sdio.hw,
- [CLKID_ABUF] = &meson8b_abuf.hw,
- [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
- [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
- [CLKID_SPI] = &meson8b_spi.hw,
- [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
- [CLKID_ETH] = &meson8b_eth.hw,
- [CLKID_DEMUX] = &meson8b_demux.hw,
- [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
- [CLKID_IEC958] = &meson8b_iec958.hw,
- [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
- [CLKID_AMCLK] = &meson8b_amclk.hw,
- [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
- [CLKID_MIXER] = &meson8b_mixer.hw,
- [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
- [CLKID_ADC] = &meson8b_adc.hw,
- [CLKID_BLKMV] = &meson8b_blkmv.hw,
- [CLKID_AIU] = &meson8b_aiu.hw,
- [CLKID_UART1] = &meson8b_uart1.hw,
- [CLKID_G2D] = &meson8b_g2d.hw,
- [CLKID_USB0] = &meson8b_usb0.hw,
- [CLKID_USB1] = &meson8b_usb1.hw,
- [CLKID_RESET] = &meson8b_reset.hw,
- [CLKID_NAND] = &meson8b_nand.hw,
- [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
- [CLKID_USB] = &meson8b_usb.hw,
- [CLKID_VDIN1] = &meson8b_vdin1.hw,
- [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
- [CLKID_EFUSE] = &meson8b_efuse.hw,
- [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
- [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
- [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
- [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
- [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
- [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
- [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
- [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
- [CLKID_DVIN] = &meson8b_dvin.hw,
- [CLKID_UART2] = &meson8b_uart2.hw,
- [CLKID_SANA] = &meson8b_sana.hw,
- [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
- [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
- [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
- [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
- [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
- [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
- [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
- [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
- [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
- [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
- [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
- [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
- [CLKID_ENC480P] = &meson8b_enc480p.hw,
- [CLKID_RNG1] = &meson8b_rng1.hw,
- [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
- [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
- [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
- [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
- [CLKID_EDP] = &meson8b_edp.hw,
- [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
- [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
- [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
- [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
- [CLKID_MPLL0] = &meson8b_mpll0.hw,
- [CLKID_MPLL1] = &meson8b_mpll1.hw,
- [CLKID_MPLL2] = &meson8b_mpll2.hw,
- [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
- [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
- [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
- [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
- [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
- [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
- [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
- [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
- [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
- [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
- [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
- [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
- [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
- [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
- [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
- [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
- [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
- [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
- [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
- [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
- [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
- [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
- [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
- [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
- [CLKID_APB] = &meson8b_apb_clk_gate.hw,
- [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
- [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
- [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
- [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
- [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
- [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
- [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
- [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
- [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
- [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
- [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
- [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
- [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
- [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
- [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
- [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
- [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
- [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
- [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
- [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
- [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
- [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
- [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
- [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
- [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
- [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
- [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
- [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
- [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
- [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
- [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
- [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
- [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
- [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
- [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
- [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
- [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
- [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
- [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
- [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
- [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
- [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
- [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
- [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
- [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
- [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
- [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
- [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
- [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
- [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
- [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
- [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
- [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
- [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
- [CLKID_MALI] = &meson8b_mali_0.hw,
- [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
- [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
- [CLKID_VPU] = &meson8b_vpu_0.hw,
- [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
- [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
- [CLKID_VDEC_1] = &meson8b_vdec_1_1.hw,
- [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
- [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
- [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
- [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
- [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
- [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
- [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
- [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
- [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
- [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
- [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
- [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
- [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
- [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
- [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
- [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
- [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
- [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
- [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
- [CLK_NR_CLKS] = NULL,
- },
- .num = CLK_NR_CLKS,
-};
-
-static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
- .hws = {
- [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
- [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
- [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
- [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
- [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
- [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
- [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
- [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
- [CLKID_CLK81] = &meson8b_clk81.hw,
- [CLKID_DDR] = &meson8b_ddr.hw,
- [CLKID_DOS] = &meson8b_dos.hw,
- [CLKID_ISA] = &meson8b_isa.hw,
- [CLKID_PL301] = &meson8b_pl301.hw,
- [CLKID_PERIPHS] = &meson8b_periphs.hw,
- [CLKID_SPICC] = &meson8b_spicc.hw,
- [CLKID_I2C] = &meson8b_i2c.hw,
- [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
- [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
- [CLKID_RNG0] = &meson8b_rng0.hw,
- [CLKID_UART0] = &meson8b_uart0.hw,
- [CLKID_SDHC] = &meson8b_sdhc.hw,
- [CLKID_STREAM] = &meson8b_stream.hw,
- [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
- [CLKID_SDIO] = &meson8b_sdio.hw,
- [CLKID_ABUF] = &meson8b_abuf.hw,
- [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
- [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
- [CLKID_SPI] = &meson8b_spi.hw,
- [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
- [CLKID_ETH] = &meson8b_eth.hw,
- [CLKID_DEMUX] = &meson8b_demux.hw,
- [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
- [CLKID_IEC958] = &meson8b_iec958.hw,
- [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
- [CLKID_AMCLK] = &meson8b_amclk.hw,
- [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
- [CLKID_MIXER] = &meson8b_mixer.hw,
- [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
- [CLKID_ADC] = &meson8b_adc.hw,
- [CLKID_BLKMV] = &meson8b_blkmv.hw,
- [CLKID_AIU] = &meson8b_aiu.hw,
- [CLKID_UART1] = &meson8b_uart1.hw,
- [CLKID_G2D] = &meson8b_g2d.hw,
- [CLKID_USB0] = &meson8b_usb0.hw,
- [CLKID_USB1] = &meson8b_usb1.hw,
- [CLKID_RESET] = &meson8b_reset.hw,
- [CLKID_NAND] = &meson8b_nand.hw,
- [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
- [CLKID_USB] = &meson8b_usb.hw,
- [CLKID_VDIN1] = &meson8b_vdin1.hw,
- [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
- [CLKID_EFUSE] = &meson8b_efuse.hw,
- [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
- [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
- [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
- [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
- [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
- [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
- [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
- [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
- [CLKID_DVIN] = &meson8b_dvin.hw,
- [CLKID_UART2] = &meson8b_uart2.hw,
- [CLKID_SANA] = &meson8b_sana.hw,
- [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
- [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
- [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
- [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
- [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
- [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
- [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
- [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
- [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
- [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
- [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
- [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
- [CLKID_ENC480P] = &meson8b_enc480p.hw,
- [CLKID_RNG1] = &meson8b_rng1.hw,
- [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
- [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
- [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
- [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
- [CLKID_EDP] = &meson8b_edp.hw,
- [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
- [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
- [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
- [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
- [CLKID_MPLL0] = &meson8b_mpll0.hw,
- [CLKID_MPLL1] = &meson8b_mpll1.hw,
- [CLKID_MPLL2] = &meson8b_mpll2.hw,
- [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
- [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
- [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
- [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
- [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
- [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
- [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
- [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
- [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
- [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
- [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
- [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
- [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
- [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
- [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
- [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
- [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
- [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
- [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
- [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
- [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
- [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
- [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
- [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
- [CLKID_APB] = &meson8b_apb_clk_gate.hw,
- [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
- [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
- [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
- [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
- [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
- [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
- [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
- [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
- [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
- [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
- [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
- [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
- [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
- [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
- [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
- [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
- [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
- [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
- [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
- [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
- [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
- [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
- [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
- [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
- [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
- [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
- [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
- [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
- [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
- [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
- [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
- [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
- [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
- [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
- [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
- [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
- [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
- [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
- [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
- [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
- [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
- [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
- [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
- [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
- [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
- [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
- [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
- [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
- [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
- [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
- [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
- [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
- [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
- [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
- [CLKID_MALI_0] = &meson8b_mali_0.hw,
- [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
- [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
- [CLKID_MALI_1] = &meson8b_mali_1.hw,
- [CLKID_MALI] = &meson8b_mali.hw,
- [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
- [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
- [CLKID_VPU_0] = &meson8b_vpu_0.hw,
- [CLKID_VPU_1_SEL] = &meson8b_vpu_1_sel.hw,
- [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
- [CLKID_VPU_1] = &meson8b_vpu_1.hw,
- [CLKID_VPU] = &meson8b_vpu.hw,
- [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
- [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
- [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
- [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
- [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
- [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
- [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
- [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
- [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
- [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
- [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
- [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
- [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
- [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
- [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
- [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
- [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
- [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
- [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
- [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
- [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
- [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
- [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
- [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
- [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
- [CLK_NR_CLKS] = NULL,
- },
- .num = CLK_NR_CLKS,
-};
-
-static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
- .hws = {
- [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
- [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
- [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
- [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
- [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
- [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
- [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
- [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
- [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
- [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
- [CLKID_CLK81] = &meson8b_clk81.hw,
- [CLKID_DDR] = &meson8b_ddr.hw,
- [CLKID_DOS] = &meson8b_dos.hw,
- [CLKID_ISA] = &meson8b_isa.hw,
- [CLKID_PL301] = &meson8b_pl301.hw,
- [CLKID_PERIPHS] = &meson8b_periphs.hw,
- [CLKID_SPICC] = &meson8b_spicc.hw,
- [CLKID_I2C] = &meson8b_i2c.hw,
- [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
- [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
- [CLKID_RNG0] = &meson8b_rng0.hw,
- [CLKID_UART0] = &meson8b_uart0.hw,
- [CLKID_SDHC] = &meson8b_sdhc.hw,
- [CLKID_STREAM] = &meson8b_stream.hw,
- [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
- [CLKID_SDIO] = &meson8b_sdio.hw,
- [CLKID_ABUF] = &meson8b_abuf.hw,
- [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
- [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
- [CLKID_SPI] = &meson8b_spi.hw,
- [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
- [CLKID_ETH] = &meson8b_eth.hw,
- [CLKID_DEMUX] = &meson8b_demux.hw,
- [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
- [CLKID_IEC958] = &meson8b_iec958.hw,
- [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
- [CLKID_AMCLK] = &meson8b_amclk.hw,
- [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
- [CLKID_MIXER] = &meson8b_mixer.hw,
- [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
- [CLKID_ADC] = &meson8b_adc.hw,
- [CLKID_BLKMV] = &meson8b_blkmv.hw,
- [CLKID_AIU] = &meson8b_aiu.hw,
- [CLKID_UART1] = &meson8b_uart1.hw,
- [CLKID_G2D] = &meson8b_g2d.hw,
- [CLKID_USB0] = &meson8b_usb0.hw,
- [CLKID_USB1] = &meson8b_usb1.hw,
- [CLKID_RESET] = &meson8b_reset.hw,
- [CLKID_NAND] = &meson8b_nand.hw,
- [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
- [CLKID_USB] = &meson8b_usb.hw,
- [CLKID_VDIN1] = &meson8b_vdin1.hw,
- [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
- [CLKID_EFUSE] = &meson8b_efuse.hw,
- [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
- [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
- [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
- [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
- [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
- [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
- [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
- [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
- [CLKID_DVIN] = &meson8b_dvin.hw,
- [CLKID_UART2] = &meson8b_uart2.hw,
- [CLKID_SANA] = &meson8b_sana.hw,
- [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
- [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
- [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
- [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
- [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
- [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
- [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
- [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
- [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
- [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
- [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
- [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
- [CLKID_ENC480P] = &meson8b_enc480p.hw,
- [CLKID_RNG1] = &meson8b_rng1.hw,
- [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
- [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
- [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
- [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
- [CLKID_EDP] = &meson8b_edp.hw,
- [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
- [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
- [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
- [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
- [CLKID_MPLL0] = &meson8b_mpll0.hw,
- [CLKID_MPLL1] = &meson8b_mpll1.hw,
- [CLKID_MPLL2] = &meson8b_mpll2.hw,
- [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
- [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
- [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
- [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
- [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
- [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
- [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
- [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
- [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
- [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
- [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
- [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
- [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
- [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
- [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
- [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
- [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
- [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
- [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
- [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
- [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
- [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
- [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
- [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
- [CLKID_APB] = &meson8b_apb_clk_gate.hw,
- [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
- [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
- [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
- [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
- [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
- [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
- [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
- [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
- [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
- [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
- [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
- [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
- [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
- [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
- [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
- [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
- [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
- [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
- [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
- [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
- [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
- [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
- [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
- [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
- [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
- [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
- [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
- [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
- [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
- [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
- [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
- [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
- [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
- [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
- [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
- [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
- [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
- [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
- [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
- [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
- [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
- [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
- [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
- [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
- [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
- [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
- [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
- [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
- [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
- [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
- [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
- [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
- [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
- [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
- [CLKID_MALI_0] = &meson8b_mali_0.hw,
- [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
- [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
- [CLKID_MALI_1] = &meson8b_mali_1.hw,
- [CLKID_MALI] = &meson8b_mali.hw,
- [CLKID_GP_PLL_DCO] = &meson8m2_gp_pll_dco.hw,
- [CLKID_GP_PLL] = &meson8m2_gp_pll.hw,
- [CLKID_VPU_0_SEL] = &meson8m2_vpu_0_sel.hw,
- [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
- [CLKID_VPU_0] = &meson8b_vpu_0.hw,
- [CLKID_VPU_1_SEL] = &meson8m2_vpu_1_sel.hw,
- [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
- [CLKID_VPU_1] = &meson8b_vpu_1.hw,
- [CLKID_VPU] = &meson8b_vpu.hw,
- [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
- [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
- [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
- [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
- [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
- [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
- [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
- [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
- [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
- [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
- [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
- [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
- [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
- [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
- [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
- [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
- [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
- [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
- [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
- [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
- [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
- [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
- [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
- [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
- [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
- [CLK_NR_CLKS] = NULL,
- },
- .num = CLK_NR_CLKS,
+static struct clk_hw *meson8_hw_clks[] = {
+ [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
+ [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
+ [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
+ [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
+ [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
+ [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &meson8b_clk81.hw,
+ [CLKID_DDR] = &meson8b_ddr.hw,
+ [CLKID_DOS] = &meson8b_dos.hw,
+ [CLKID_ISA] = &meson8b_isa.hw,
+ [CLKID_PL301] = &meson8b_pl301.hw,
+ [CLKID_PERIPHS] = &meson8b_periphs.hw,
+ [CLKID_SPICC] = &meson8b_spicc.hw,
+ [CLKID_I2C] = &meson8b_i2c.hw,
+ [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
+ [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
+ [CLKID_RNG0] = &meson8b_rng0.hw,
+ [CLKID_UART0] = &meson8b_uart0.hw,
+ [CLKID_SDHC] = &meson8b_sdhc.hw,
+ [CLKID_STREAM] = &meson8b_stream.hw,
+ [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
+ [CLKID_SDIO] = &meson8b_sdio.hw,
+ [CLKID_ABUF] = &meson8b_abuf.hw,
+ [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
+ [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
+ [CLKID_SPI] = &meson8b_spi.hw,
+ [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
+ [CLKID_ETH] = &meson8b_eth.hw,
+ [CLKID_DEMUX] = &meson8b_demux.hw,
+ [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
+ [CLKID_IEC958] = &meson8b_iec958.hw,
+ [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
+ [CLKID_AMCLK] = &meson8b_amclk.hw,
+ [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
+ [CLKID_MIXER] = &meson8b_mixer.hw,
+ [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
+ [CLKID_ADC] = &meson8b_adc.hw,
+ [CLKID_BLKMV] = &meson8b_blkmv.hw,
+ [CLKID_AIU] = &meson8b_aiu.hw,
+ [CLKID_UART1] = &meson8b_uart1.hw,
+ [CLKID_G2D] = &meson8b_g2d.hw,
+ [CLKID_USB0] = &meson8b_usb0.hw,
+ [CLKID_USB1] = &meson8b_usb1.hw,
+ [CLKID_RESET] = &meson8b_reset.hw,
+ [CLKID_NAND] = &meson8b_nand.hw,
+ [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
+ [CLKID_USB] = &meson8b_usb.hw,
+ [CLKID_VDIN1] = &meson8b_vdin1.hw,
+ [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
+ [CLKID_EFUSE] = &meson8b_efuse.hw,
+ [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
+ [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
+ [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
+ [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
+ [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
+ [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
+ [CLKID_DVIN] = &meson8b_dvin.hw,
+ [CLKID_UART2] = &meson8b_uart2.hw,
+ [CLKID_SANA] = &meson8b_sana.hw,
+ [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
+ [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
+ [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
+ [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
+ [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
+ [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
+ [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
+ [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
+ [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
+ [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
+ [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
+ [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
+ [CLKID_ENC480P] = &meson8b_enc480p.hw,
+ [CLKID_RNG1] = &meson8b_rng1.hw,
+ [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
+ [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
+ [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
+ [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
+ [CLKID_EDP] = &meson8b_edp.hw,
+ [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
+ [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
+ [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
+ [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
+ [CLKID_MPLL0] = &meson8b_mpll0.hw,
+ [CLKID_MPLL1] = &meson8b_mpll1.hw,
+ [CLKID_MPLL2] = &meson8b_mpll2.hw,
+ [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
+ [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
+ [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
+ [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
+ [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
+ [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
+ [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
+ [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
+ [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
+ [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
+ [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
+ [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
+ [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
+ [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
+ [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
+ [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
+ [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
+ [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
+ [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
+ [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
+ [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
+ [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
+ [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
+ [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
+ [CLKID_APB] = &meson8b_apb_clk_gate.hw,
+ [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
+ [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
+ [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
+ [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
+ [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
+ [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
+ [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
+ [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
+ [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
+ [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
+ [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
+ [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
+ [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
+ [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
+ [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
+ [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
+ [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
+ [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
+ [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
+ [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
+ [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
+ [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
+ [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
+ [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
+ [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
+ [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
+ [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
+ [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
+ [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
+ [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
+ [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
+ [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
+ [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
+ [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
+ [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
+ [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
+ [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
+ [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
+ [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
+ [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
+ [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
+ [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
+ [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
+ [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
+ [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
+ [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
+ [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
+ [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
+ [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
+ [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
+ [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
+ [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
+ [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
+ [CLKID_MALI] = &meson8b_mali_0.hw,
+ [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
+ [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
+ [CLKID_VPU] = &meson8b_vpu_0.hw,
+ [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
+ [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
+ [CLKID_VDEC_1] = &meson8b_vdec_1_1.hw,
+ [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
+ [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
+ [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
+ [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
+ [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
+ [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
+ [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
+ [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
+ [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
+ [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
+ [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
+ [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
+ [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
+ [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
+ [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
+ [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
+ [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
+ [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
+ [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
+};
+
+static struct clk_hw *meson8b_hw_clks[] = {
+ [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
+ [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
+ [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
+ [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
+ [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
+ [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &meson8b_clk81.hw,
+ [CLKID_DDR] = &meson8b_ddr.hw,
+ [CLKID_DOS] = &meson8b_dos.hw,
+ [CLKID_ISA] = &meson8b_isa.hw,
+ [CLKID_PL301] = &meson8b_pl301.hw,
+ [CLKID_PERIPHS] = &meson8b_periphs.hw,
+ [CLKID_SPICC] = &meson8b_spicc.hw,
+ [CLKID_I2C] = &meson8b_i2c.hw,
+ [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
+ [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
+ [CLKID_RNG0] = &meson8b_rng0.hw,
+ [CLKID_UART0] = &meson8b_uart0.hw,
+ [CLKID_SDHC] = &meson8b_sdhc.hw,
+ [CLKID_STREAM] = &meson8b_stream.hw,
+ [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
+ [CLKID_SDIO] = &meson8b_sdio.hw,
+ [CLKID_ABUF] = &meson8b_abuf.hw,
+ [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
+ [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
+ [CLKID_SPI] = &meson8b_spi.hw,
+ [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
+ [CLKID_ETH] = &meson8b_eth.hw,
+ [CLKID_DEMUX] = &meson8b_demux.hw,
+ [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
+ [CLKID_IEC958] = &meson8b_iec958.hw,
+ [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
+ [CLKID_AMCLK] = &meson8b_amclk.hw,
+ [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
+ [CLKID_MIXER] = &meson8b_mixer.hw,
+ [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
+ [CLKID_ADC] = &meson8b_adc.hw,
+ [CLKID_BLKMV] = &meson8b_blkmv.hw,
+ [CLKID_AIU] = &meson8b_aiu.hw,
+ [CLKID_UART1] = &meson8b_uart1.hw,
+ [CLKID_G2D] = &meson8b_g2d.hw,
+ [CLKID_USB0] = &meson8b_usb0.hw,
+ [CLKID_USB1] = &meson8b_usb1.hw,
+ [CLKID_RESET] = &meson8b_reset.hw,
+ [CLKID_NAND] = &meson8b_nand.hw,
+ [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
+ [CLKID_USB] = &meson8b_usb.hw,
+ [CLKID_VDIN1] = &meson8b_vdin1.hw,
+ [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
+ [CLKID_EFUSE] = &meson8b_efuse.hw,
+ [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
+ [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
+ [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
+ [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
+ [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
+ [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
+ [CLKID_DVIN] = &meson8b_dvin.hw,
+ [CLKID_UART2] = &meson8b_uart2.hw,
+ [CLKID_SANA] = &meson8b_sana.hw,
+ [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
+ [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
+ [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
+ [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
+ [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
+ [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
+ [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
+ [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
+ [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
+ [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
+ [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
+ [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
+ [CLKID_ENC480P] = &meson8b_enc480p.hw,
+ [CLKID_RNG1] = &meson8b_rng1.hw,
+ [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
+ [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
+ [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
+ [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
+ [CLKID_EDP] = &meson8b_edp.hw,
+ [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
+ [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
+ [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
+ [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
+ [CLKID_MPLL0] = &meson8b_mpll0.hw,
+ [CLKID_MPLL1] = &meson8b_mpll1.hw,
+ [CLKID_MPLL2] = &meson8b_mpll2.hw,
+ [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
+ [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
+ [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
+ [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
+ [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
+ [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
+ [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
+ [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
+ [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
+ [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
+ [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
+ [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
+ [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
+ [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
+ [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
+ [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
+ [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
+ [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
+ [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
+ [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
+ [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
+ [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
+ [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
+ [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
+ [CLKID_APB] = &meson8b_apb_clk_gate.hw,
+ [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
+ [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
+ [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
+ [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
+ [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
+ [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
+ [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
+ [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
+ [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
+ [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
+ [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
+ [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
+ [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
+ [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
+ [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
+ [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
+ [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
+ [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
+ [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
+ [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
+ [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
+ [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
+ [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
+ [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
+ [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
+ [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
+ [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
+ [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
+ [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
+ [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
+ [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
+ [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
+ [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
+ [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
+ [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
+ [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
+ [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
+ [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
+ [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
+ [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
+ [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
+ [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
+ [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
+ [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
+ [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
+ [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
+ [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
+ [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
+ [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
+ [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
+ [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
+ [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
+ [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
+ [CLKID_MALI_0] = &meson8b_mali_0.hw,
+ [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
+ [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
+ [CLKID_MALI_1] = &meson8b_mali_1.hw,
+ [CLKID_MALI] = &meson8b_mali.hw,
+ [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
+ [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
+ [CLKID_VPU_0] = &meson8b_vpu_0.hw,
+ [CLKID_VPU_1_SEL] = &meson8b_vpu_1_sel.hw,
+ [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
+ [CLKID_VPU_1] = &meson8b_vpu_1.hw,
+ [CLKID_VPU] = &meson8b_vpu.hw,
+ [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
+ [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
+ [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
+ [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
+ [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
+ [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
+ [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
+ [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
+ [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
+ [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
+ [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
+ [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
+ [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
+ [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
+ [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
+ [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
+ [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
+ [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
+ [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
+ [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
+ [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
+ [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
+ [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
+ [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
+ [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
+};
+
+static struct clk_hw *meson8m2_hw_clks[] = {
+ [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
+ [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
+ [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
+ [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
+ [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
+ [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
+ [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
+ [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
+ [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
+ [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
+ [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
+ [CLKID_CLK81] = &meson8b_clk81.hw,
+ [CLKID_DDR] = &meson8b_ddr.hw,
+ [CLKID_DOS] = &meson8b_dos.hw,
+ [CLKID_ISA] = &meson8b_isa.hw,
+ [CLKID_PL301] = &meson8b_pl301.hw,
+ [CLKID_PERIPHS] = &meson8b_periphs.hw,
+ [CLKID_SPICC] = &meson8b_spicc.hw,
+ [CLKID_I2C] = &meson8b_i2c.hw,
+ [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
+ [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
+ [CLKID_RNG0] = &meson8b_rng0.hw,
+ [CLKID_UART0] = &meson8b_uart0.hw,
+ [CLKID_SDHC] = &meson8b_sdhc.hw,
+ [CLKID_STREAM] = &meson8b_stream.hw,
+ [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
+ [CLKID_SDIO] = &meson8b_sdio.hw,
+ [CLKID_ABUF] = &meson8b_abuf.hw,
+ [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
+ [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
+ [CLKID_SPI] = &meson8b_spi.hw,
+ [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
+ [CLKID_ETH] = &meson8b_eth.hw,
+ [CLKID_DEMUX] = &meson8b_demux.hw,
+ [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
+ [CLKID_IEC958] = &meson8b_iec958.hw,
+ [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
+ [CLKID_AMCLK] = &meson8b_amclk.hw,
+ [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
+ [CLKID_MIXER] = &meson8b_mixer.hw,
+ [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
+ [CLKID_ADC] = &meson8b_adc.hw,
+ [CLKID_BLKMV] = &meson8b_blkmv.hw,
+ [CLKID_AIU] = &meson8b_aiu.hw,
+ [CLKID_UART1] = &meson8b_uart1.hw,
+ [CLKID_G2D] = &meson8b_g2d.hw,
+ [CLKID_USB0] = &meson8b_usb0.hw,
+ [CLKID_USB1] = &meson8b_usb1.hw,
+ [CLKID_RESET] = &meson8b_reset.hw,
+ [CLKID_NAND] = &meson8b_nand.hw,
+ [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
+ [CLKID_USB] = &meson8b_usb.hw,
+ [CLKID_VDIN1] = &meson8b_vdin1.hw,
+ [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
+ [CLKID_EFUSE] = &meson8b_efuse.hw,
+ [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
+ [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
+ [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
+ [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
+ [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
+ [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
+ [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
+ [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
+ [CLKID_DVIN] = &meson8b_dvin.hw,
+ [CLKID_UART2] = &meson8b_uart2.hw,
+ [CLKID_SANA] = &meson8b_sana.hw,
+ [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
+ [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
+ [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
+ [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
+ [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
+ [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
+ [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
+ [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
+ [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
+ [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
+ [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
+ [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
+ [CLKID_ENC480P] = &meson8b_enc480p.hw,
+ [CLKID_RNG1] = &meson8b_rng1.hw,
+ [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
+ [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
+ [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
+ [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
+ [CLKID_EDP] = &meson8b_edp.hw,
+ [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
+ [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
+ [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
+ [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
+ [CLKID_MPLL0] = &meson8b_mpll0.hw,
+ [CLKID_MPLL1] = &meson8b_mpll1.hw,
+ [CLKID_MPLL2] = &meson8b_mpll2.hw,
+ [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
+ [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
+ [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
+ [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
+ [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
+ [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
+ [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
+ [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
+ [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
+ [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
+ [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
+ [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
+ [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
+ [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
+ [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
+ [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
+ [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
+ [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
+ [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
+ [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
+ [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
+ [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
+ [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
+ [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
+ [CLKID_APB] = &meson8b_apb_clk_gate.hw,
+ [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
+ [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
+ [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
+ [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
+ [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
+ [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
+ [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
+ [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
+ [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
+ [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
+ [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
+ [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
+ [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
+ [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
+ [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
+ [CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
+ [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
+ [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
+ [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
+ [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
+ [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
+ [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
+ [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
+ [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
+ [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
+ [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
+ [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
+ [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
+ [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
+ [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
+ [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
+ [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
+ [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
+ [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
+ [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
+ [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
+ [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
+ [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
+ [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
+ [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
+ [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
+ [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
+ [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
+ [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
+ [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
+ [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
+ [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
+ [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
+ [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
+ [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
+ [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
+ [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
+ [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
+ [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
+ [CLKID_MALI_0] = &meson8b_mali_0.hw,
+ [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
+ [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
+ [CLKID_MALI_1] = &meson8b_mali_1.hw,
+ [CLKID_MALI] = &meson8b_mali.hw,
+ [CLKID_GP_PLL_DCO] = &meson8m2_gp_pll_dco.hw,
+ [CLKID_GP_PLL] = &meson8m2_gp_pll.hw,
+ [CLKID_VPU_0_SEL] = &meson8m2_vpu_0_sel.hw,
+ [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
+ [CLKID_VPU_0] = &meson8b_vpu_0.hw,
+ [CLKID_VPU_1_SEL] = &meson8m2_vpu_1_sel.hw,
+ [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
+ [CLKID_VPU_1] = &meson8b_vpu_1.hw,
+ [CLKID_VPU] = &meson8b_vpu.hw,
+ [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
+ [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
+ [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
+ [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
+ [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
+ [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
+ [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
+ [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
+ [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
+ [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
+ [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
+ [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
+ [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
+ [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
+ [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
+ [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
+ [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
+ [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
+ [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
+ [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
+ [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
+ [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
+ [CLKID_CTS_I958] = &meson8b_cts_i958.hw,
+ [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw,
+ [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
};
static struct clk_regmap *const meson8b_clk_regmaps[] = {
@@ -3788,8 +3780,23 @@ static struct meson8b_nb_data meson8b_cpu_nb_data = {
.nb.notifier_call = meson8b_cpu_clk_notifier_cb,
};
+static struct meson_clk_hw_data meson8_clks = {
+ .hws = meson8_hw_clks,
+ .num = ARRAY_SIZE(meson8_hw_clks),
+};
+
+static struct meson_clk_hw_data meson8b_clks = {
+ .hws = meson8b_hw_clks,
+ .num = ARRAY_SIZE(meson8b_hw_clks),
+};
+
+static struct meson_clk_hw_data meson8m2_clks = {
+ .hws = meson8m2_hw_clks,
+ .num = ARRAY_SIZE(meson8m2_hw_clks),
+};
+
static void __init meson8b_clkc_init_common(struct device_node *np,
- struct clk_hw_onecell_data *clk_hw_onecell_data)
+ struct meson_clk_hw_data *hw_clks)
{
struct meson8b_clk_reset *rstc;
struct device_node *parent_np;
@@ -3830,17 +3837,17 @@ static void __init meson8b_clkc_init_common(struct device_node *np,
* register all clks and start with the first used ID (which is
* CLKID_PLL_FIXED)
*/
- for (i = CLKID_PLL_FIXED; i < CLK_NR_CLKS; i++) {
+ for (i = CLKID_PLL_FIXED; i < hw_clks->num; i++) {
/* array might be sparse */
- if (!clk_hw_onecell_data->hws[i])
+ if (!hw_clks->hws[i])
continue;
- ret = of_clk_hw_register(np, clk_hw_onecell_data->hws[i]);
+ ret = of_clk_hw_register(np, hw_clks->hws[i]);
if (ret)
return;
}
- meson8b_cpu_nb_data.cpu_clk = clk_hw_onecell_data->hws[CLKID_CPUCLK];
+ meson8b_cpu_nb_data.cpu_clk = hw_clks->hws[CLKID_CPUCLK];
/*
* FIXME we shouldn't program the muxes in notifier handlers. The
@@ -3856,25 +3863,24 @@ static void __init meson8b_clkc_init_common(struct device_node *np,
return;
}
- ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
- clk_hw_onecell_data);
+ ret = of_clk_add_hw_provider(np, meson_clk_hw_get, hw_clks);
if (ret)
pr_err("%s: failed to register clock provider\n", __func__);
}
static void __init meson8_clkc_init(struct device_node *np)
{
- return meson8b_clkc_init_common(np, &meson8_hw_onecell_data);
+ return meson8b_clkc_init_common(np, &meson8_clks);
}
static void __init meson8b_clkc_init(struct device_node *np)
{
- return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data);
+ return meson8b_clkc_init_common(np, &meson8b_clks);
}
static void __init meson8m2_clkc_init(struct device_node *np)
{
- return meson8b_clkc_init_common(np, &meson8m2_hw_onecell_data);
+ return meson8b_clkc_init_common(np, &meson8m2_clks);
}
CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index ce62ed47cbfc..a5b6e67eeefb 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -77,121 +77,4 @@
#define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */
#define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */
-/*
- * CLKID index values
- *
- * These indices are entirely contrived and do not map onto the hardware.
- * It has now been decided to expose everything by default in the DT header:
- * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
- * to expose, such as the internal muxes and dividers of composite clocks,
- * will remain defined here.
- */
-
-#define CLKID_MPLL0_DIV 96
-#define CLKID_MPLL1_DIV 97
-#define CLKID_MPLL2_DIV 98
-#define CLKID_CPU_IN_SEL 99
-#define CLKID_CPU_IN_DIV2 100
-#define CLKID_CPU_IN_DIV3 101
-#define CLKID_CPU_SCALE_DIV 102
-#define CLKID_CPU_SCALE_OUT_SEL 103
-#define CLKID_MPLL_PREDIV 104
-#define CLKID_FCLK_DIV2_DIV 105
-#define CLKID_FCLK_DIV3_DIV 106
-#define CLKID_FCLK_DIV4_DIV 107
-#define CLKID_FCLK_DIV5_DIV 108
-#define CLKID_FCLK_DIV7_DIV 109
-#define CLKID_NAND_SEL 110
-#define CLKID_NAND_DIV 111
-#define CLKID_PLL_FIXED_DCO 113
-#define CLKID_HDMI_PLL_DCO 114
-#define CLKID_PLL_SYS_DCO 115
-#define CLKID_CPU_CLK_DIV2 116
-#define CLKID_CPU_CLK_DIV3 117
-#define CLKID_CPU_CLK_DIV4 118
-#define CLKID_CPU_CLK_DIV5 119
-#define CLKID_CPU_CLK_DIV6 120
-#define CLKID_CPU_CLK_DIV7 121
-#define CLKID_CPU_CLK_DIV8 122
-#define CLKID_APB_SEL 123
-#define CLKID_PERIPH_SEL 125
-#define CLKID_AXI_SEL 127
-#define CLKID_L2_DRAM_SEL 129
-#define CLKID_HDMI_PLL_LVDS_OUT 131
-#define CLKID_VID_PLL_IN_SEL 133
-#define CLKID_VID_PLL_IN_EN 134
-#define CLKID_VID_PLL_PRE_DIV 135
-#define CLKID_VID_PLL_POST_DIV 136
-#define CLKID_VCLK_IN_EN 139
-#define CLKID_VCLK_DIV1 140
-#define CLKID_VCLK_DIV2_DIV 141
-#define CLKID_VCLK_DIV2 142
-#define CLKID_VCLK_DIV4_DIV 143
-#define CLKID_VCLK_DIV4 144
-#define CLKID_VCLK_DIV6_DIV 145
-#define CLKID_VCLK_DIV6 146
-#define CLKID_VCLK_DIV12_DIV 147
-#define CLKID_VCLK_DIV12 148
-#define CLKID_VCLK2_IN_EN 150
-#define CLKID_VCLK2_DIV1 151
-#define CLKID_VCLK2_DIV2_DIV 152
-#define CLKID_VCLK2_DIV2 153
-#define CLKID_VCLK2_DIV4_DIV 154
-#define CLKID_VCLK2_DIV4 155
-#define CLKID_VCLK2_DIV6_DIV 156
-#define CLKID_VCLK2_DIV6 157
-#define CLKID_VCLK2_DIV12_DIV 158
-#define CLKID_VCLK2_DIV12 159
-#define CLKID_CTS_ENCT_SEL 160
-#define CLKID_CTS_ENCP_SEL 162
-#define CLKID_CTS_ENCI_SEL 164
-#define CLKID_HDMI_TX_PIXEL_SEL 166
-#define CLKID_CTS_ENCL_SEL 168
-#define CLKID_CTS_VDAC0_SEL 170
-#define CLKID_HDMI_SYS_SEL 172
-#define CLKID_HDMI_SYS_DIV 173
-#define CLKID_MALI_0_SEL 175
-#define CLKID_MALI_0_DIV 176
-#define CLKID_MALI_0 177
-#define CLKID_MALI_1_SEL 178
-#define CLKID_MALI_1_DIV 179
-#define CLKID_MALI_1 180
-#define CLKID_GP_PLL_DCO 181
-#define CLKID_GP_PLL 182
-#define CLKID_VPU_0_SEL 183
-#define CLKID_VPU_0_DIV 184
-#define CLKID_VPU_0 185
-#define CLKID_VPU_1_SEL 186
-#define CLKID_VPU_1_DIV 187
-#define CLKID_VPU_1 189
-#define CLKID_VDEC_1_SEL 191
-#define CLKID_VDEC_1_1_DIV 192
-#define CLKID_VDEC_1_1 193
-#define CLKID_VDEC_1_2_DIV 194
-#define CLKID_VDEC_1_2 195
-#define CLKID_VDEC_HCODEC_SEL 197
-#define CLKID_VDEC_HCODEC_DIV 198
-#define CLKID_VDEC_2_SEL 200
-#define CLKID_VDEC_2_DIV 201
-#define CLKID_VDEC_HEVC_SEL 203
-#define CLKID_VDEC_HEVC_DIV 204
-#define CLKID_VDEC_HEVC_EN 205
-#define CLKID_CTS_AMCLK_SEL 207
-#define CLKID_CTS_AMCLK_DIV 208
-#define CLKID_CTS_MCLK_I958_SEL 210
-#define CLKID_CTS_MCLK_I958_DIV 211
-#define CLKID_VCLK_EN 214
-#define CLKID_VCLK2_EN 215
-#define CLKID_VID_PLL_LVDS_EN 216
-#define CLKID_HDMI_PLL_DCO_IN 217
-
-#define CLK_NR_CLKS 218
-
-/*
- * include the CLKID and RESETID that have
- * been made part of the stable DT binding
- */
-#include <dt-bindings/clock/meson8b-clkc.h>
-#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
-
#endif /* __MESON8B_H */
diff --git a/drivers/clk/microchip/clk-pic32mzda.c b/drivers/clk/microchip/clk-pic32mzda.c
index eabfc4931fe9..27599829ea40 100644
--- a/drivers/clk/microchip/clk-pic32mzda.c
+++ b/drivers/clk/microchip/clk-pic32mzda.c
@@ -9,8 +9,8 @@
#include <linux/clkdev.h>
#include <linux/io.h>
#include <linux/module.h>
+#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <asm/traps.h>
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index cbcc2f8430a2..441bf83080a1 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -11,8 +11,4 @@ obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o clk-pll.o pwr-island.o
obj-$(CONFIG_COMMON_CLK_MMP2_AUDIO) += clk-audio.o
-obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
-obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
-obj-$(CONFIG_CPU_MMP2) += clk-mmp2.o
-
obj-y += clk-of-pxa1928.o
diff --git a/drivers/clk/mmp/clk-audio.c b/drivers/clk/mmp/clk-audio.c
index 6fb1aa9487b5..ae521aaf8cdc 100644
--- a/drivers/clk/mmp/clk-audio.c
+++ b/drivers/clk/mmp/clk-audio.c
@@ -55,6 +55,8 @@
#define SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN_MASK (0x7ff << 0)
#define SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(x) ((x) << 0)
+#define CLK_AUDIO_NR_CLKS 3
+
struct mmp2_audio_clk {
void __iomem *mmio_base;
@@ -336,7 +338,7 @@ static int register_clocks(struct mmp2_audio_clk *priv, struct device *dev)
priv->clk_data.hws[MMP2_CLK_AUDIO_SYSCLK] = &priv->sysclk_gate.hw;
priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA0] = &priv->sspa0_gate.hw;
priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA1] = &priv->sspa1_gate.hw;
- priv->clk_data.num = MMP2_CLK_AUDIO_NR_CLKS;
+ priv->clk_data.num = CLK_AUDIO_NR_CLKS;
return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
&priv->clk_data);
@@ -349,7 +351,7 @@ static int mmp2_audio_clk_probe(struct platform_device *pdev)
priv = devm_kzalloc(&pdev->dev,
struct_size(priv, clk_data.hws,
- MMP2_CLK_AUDIO_NR_CLKS),
+ CLK_AUDIO_NR_CLKS),
GFP_KERNEL);
if (!priv)
return -ENOMEM;
diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c
deleted file mode 100644
index aabacfa10158..000000000000
--- a/drivers/clk/mmp/clk-mmp2.c
+++ /dev/null
@@ -1,454 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * mmp2 clock framework source file
- *
- * Copyright (C) 2012 Marvell
- * Chao Xie <xiechao.mail@gmail.com>
- */
-
-#include <linux/clk.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/clk/mmp.h>
-
-#include "clk.h"
-
-#define APBC_RTC 0x0
-#define APBC_TWSI0 0x4
-#define APBC_TWSI1 0x8
-#define APBC_TWSI2 0xc
-#define APBC_TWSI3 0x10
-#define APBC_TWSI4 0x7c
-#define APBC_TWSI5 0x80
-#define APBC_KPC 0x18
-#define APBC_UART0 0x2c
-#define APBC_UART1 0x30
-#define APBC_UART2 0x34
-#define APBC_UART3 0x88
-#define APBC_GPIO 0x38
-#define APBC_PWM0 0x3c
-#define APBC_PWM1 0x40
-#define APBC_PWM2 0x44
-#define APBC_PWM3 0x48
-#define APBC_SSP0 0x50
-#define APBC_SSP1 0x54
-#define APBC_SSP2 0x58
-#define APBC_SSP3 0x5c
-#define APMU_SDH0 0x54
-#define APMU_SDH1 0x58
-#define APMU_SDH2 0xe8
-#define APMU_SDH3 0xec
-#define APMU_USB 0x5c
-#define APMU_DISP0 0x4c
-#define APMU_DISP1 0x110
-#define APMU_CCIC0 0x50
-#define APMU_CCIC1 0xf4
-#define MPMU_UART_PLL 0x14
-
-static DEFINE_SPINLOCK(clk_lock);
-
-static struct mmp_clk_factor_masks uart_factor_masks = {
- .factor = 2,
- .num_mask = 0x1fff,
- .den_mask = 0x1fff,
- .num_shift = 16,
- .den_shift = 0,
-};
-
-static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
- {.num = 8125, .den = 1536}, /*14.745MHZ */
- {.num = 3521, .den = 689}, /*19.23MHZ */
-};
-
-static const char *uart_parent[] = {"uart_pll", "vctcxo"};
-static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
-static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
-static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
-static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"};
-
-void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
- phys_addr_t apbc_phys)
-{
- struct clk *clk;
- struct clk *vctcxo;
- void __iomem *mpmu_base;
- void __iomem *apmu_base;
- void __iomem *apbc_base;
-
- mpmu_base = ioremap(mpmu_phys, SZ_4K);
- if (!mpmu_base) {
- pr_err("error to ioremap MPMU base\n");
- return;
- }
-
- apmu_base = ioremap(apmu_phys, SZ_4K);
- if (!apmu_base) {
- pr_err("error to ioremap APMU base\n");
- return;
- }
-
- apbc_base = ioremap(apbc_phys, SZ_4K);
- if (!apbc_base) {
- pr_err("error to ioremap APBC base\n");
- return;
- }
-
- clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
- clk_register_clkdev(clk, "clk32", NULL);
-
- vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
- clk_register_clkdev(vctcxo, "vctcxo", NULL);
-
- clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 800000000);
- clk_register_clkdev(clk, "pll1", NULL);
-
- clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, 0, 480000000);
- clk_register_clkdev(clk, "usb_pll", NULL);
-
- clk = clk_register_fixed_rate(NULL, "pll2", NULL, 0, 960000000);
- clk_register_clkdev(clk, "pll2", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_2", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_4", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_8", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_16", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4",
- CLK_SET_RATE_PARENT, 1, 5);
- clk_register_clkdev(clk, "pll1_20", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1",
- CLK_SET_RATE_PARENT, 1, 3);
- clk_register_clkdev(clk, "pll1_3", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_6", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_12", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll2_2", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll2_4", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll2_8", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll2_16", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2",
- CLK_SET_RATE_PARENT, 1, 3);
- clk_register_clkdev(clk, "pll2_3", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll2_6", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll2_12", NULL);
-
- clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "vctcxo_2", NULL);
-
- clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "vctcxo_4", NULL);
-
- clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
- mpmu_base + MPMU_UART_PLL,
- &uart_factor_masks, uart_factor_tbl,
- ARRAY_SIZE(uart_factor_tbl), &clk_lock);
- clk_set_rate(clk, 14745600);
- clk_register_clkdev(clk, "uart_pll", NULL);
-
- clk = mmp_clk_register_apbc("twsi0", "vctcxo",
- apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
-
- clk = mmp_clk_register_apbc("twsi1", "vctcxo",
- apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
-
- clk = mmp_clk_register_apbc("twsi2", "vctcxo",
- apbc_base + APBC_TWSI2, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2");
-
- clk = mmp_clk_register_apbc("twsi3", "vctcxo",
- apbc_base + APBC_TWSI3, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3");
-
- clk = mmp_clk_register_apbc("twsi4", "vctcxo",
- apbc_base + APBC_TWSI4, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4");
-
- clk = mmp_clk_register_apbc("twsi5", "vctcxo",
- apbc_base + APBC_TWSI5, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5");
-
- clk = mmp_clk_register_apbc("gpio", "vctcxo",
- apbc_base + APBC_GPIO, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp2-gpio");
-
- clk = mmp_clk_register_apbc("kpc", "clk32",
- apbc_base + APBC_KPC, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa27x-keypad");
-
- clk = mmp_clk_register_apbc("rtc", "clk32",
- apbc_base + APBC_RTC, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp-rtc");
-
- clk = mmp_clk_register_apbc("pwm0", "vctcxo",
- apbc_base + APBC_PWM0, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp2-pwm.0");
-
- clk = mmp_clk_register_apbc("pwm1", "vctcxo",
- apbc_base + APBC_PWM1, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp2-pwm.1");
-
- clk = mmp_clk_register_apbc("pwm2", "vctcxo",
- apbc_base + APBC_PWM2, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp2-pwm.2");
-
- clk = mmp_clk_register_apbc("pwm3", "vctcxo",
- apbc_base + APBC_PWM3, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
-
- clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
- ARRAY_SIZE(uart_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
- clk_set_parent(clk, vctcxo);
- clk_register_clkdev(clk, "uart_mux.0", NULL);
-
- clk = mmp_clk_register_apbc("uart0", "uart0_mux",
- apbc_base + APBC_UART0, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
-
- clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
- ARRAY_SIZE(uart_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
- clk_set_parent(clk, vctcxo);
- clk_register_clkdev(clk, "uart_mux.1", NULL);
-
- clk = mmp_clk_register_apbc("uart1", "uart1_mux",
- apbc_base + APBC_UART1, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
-
- clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
- ARRAY_SIZE(uart_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
- clk_set_parent(clk, vctcxo);
- clk_register_clkdev(clk, "uart_mux.2", NULL);
-
- clk = mmp_clk_register_apbc("uart2", "uart2_mux",
- apbc_base + APBC_UART2, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
-
- clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
- ARRAY_SIZE(uart_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
- clk_set_parent(clk, vctcxo);
- clk_register_clkdev(clk, "uart_mux.3", NULL);
-
- clk = mmp_clk_register_apbc("uart3", "uart3_mux",
- apbc_base + APBC_UART3, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
-
- clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
- ARRAY_SIZE(ssp_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
- clk_register_clkdev(clk, "uart_mux.0", NULL);
-
- clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
- apbc_base + APBC_SSP0, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp-ssp.0");
-
- clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
- ARRAY_SIZE(ssp_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
- clk_register_clkdev(clk, "ssp_mux.1", NULL);
-
- clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
- apbc_base + APBC_SSP1, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp-ssp.1");
-
- clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
- ARRAY_SIZE(ssp_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
- clk_register_clkdev(clk, "ssp_mux.2", NULL);
-
- clk = mmp_clk_register_apbc("ssp2", "ssp2_mux",
- apbc_base + APBC_SSP2, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp-ssp.2");
-
- clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
- ARRAY_SIZE(ssp_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
- clk_register_clkdev(clk, "ssp_mux.3", NULL);
-
- clk = mmp_clk_register_apbc("ssp3", "ssp3_mux",
- apbc_base + APBC_SSP3, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp-ssp.3");
-
- clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
- ARRAY_SIZE(sdh_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
- clk_register_clkdev(clk, "sdh_mux", NULL);
-
- clk = clk_register_divider(NULL, "sdh_div", "sdh_mux",
- CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0,
- 10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
- clk_register_clkdev(clk, "sdh_div", NULL);
-
- clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,
- 0x1b, &clk_lock);
- clk_register_clkdev(clk, NULL, "sdhci-pxav3.0");
-
- clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,
- 0x1b, &clk_lock);
- clk_register_clkdev(clk, NULL, "sdhci-pxav3.1");
-
- clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,
- 0x1b, &clk_lock);
- clk_register_clkdev(clk, NULL, "sdhci-pxav3.2");
-
- clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,
- 0x1b, &clk_lock);
- clk_register_clkdev(clk, NULL, "sdhci-pxav3.3");
-
- clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
- 0x9, &clk_lock);
- clk_register_clkdev(clk, "usb_clk", NULL);
-
- clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
- ARRAY_SIZE(disp_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
- clk_register_clkdev(clk, "disp_mux.0", NULL);
-
- clk = clk_register_divider(NULL, "disp0_div", "disp0_mux",
- CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0,
- 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
- clk_register_clkdev(clk, "disp_div.0", NULL);
-
- clk = mmp_clk_register_apmu("disp0", "disp0_div",
- apmu_base + APMU_DISP0, 0x1b, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp-disp.0");
-
- clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
- apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);
- clk_register_clkdev(clk, "disp_sphy_div.0", NULL);
-
- clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div",
- apmu_base + APMU_DISP0, 0x1024, &clk_lock);
- clk_register_clkdev(clk, "disp_sphy.0", NULL);
-
- clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
- ARRAY_SIZE(disp_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
- clk_register_clkdev(clk, "disp_mux.1", NULL);
-
- clk = clk_register_divider(NULL, "disp1_div", "disp1_mux",
- CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,
- 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
- clk_register_clkdev(clk, "disp_div.1", NULL);
-
- clk = mmp_clk_register_apmu("disp1", "disp1_div",
- apmu_base + APMU_DISP1, 0x1b, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp-disp.1");
-
- clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo",
- apmu_base + APMU_CCIC0, 0x1800, &clk_lock);
- clk_register_clkdev(clk, "ccic_arbiter", NULL);
-
- clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
- ARRAY_SIZE(ccic_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
- clk_register_clkdev(clk, "ccic_mux.0", NULL);
-
- clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
- CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
- 17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
- clk_register_clkdev(clk, "ccic_div.0", NULL);
-
- clk = mmp_clk_register_apmu("ccic0", "ccic0_div",
- apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
- clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
-
- clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div",
- apmu_base + APMU_CCIC0, 0x24, &clk_lock);
- clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
-
- clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
- CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
- 10, 5, 0, &clk_lock);
- clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0");
-
- clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
- apmu_base + APMU_CCIC0, 0x300, &clk_lock);
- clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
-
- clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
- ARRAY_SIZE(ccic_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
- clk_register_clkdev(clk, "ccic_mux.1", NULL);
-
- clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
- CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
- 16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
- clk_register_clkdev(clk, "ccic_div.1", NULL);
-
- clk = mmp_clk_register_apmu("ccic1", "ccic1_div",
- apmu_base + APMU_CCIC1, 0x1b, &clk_lock);
- clk_register_clkdev(clk, "fnclk", "mmp-ccic.1");
-
- clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div",
- apmu_base + APMU_CCIC1, 0x24, &clk_lock);
- clk_register_clkdev(clk, "phyclk", "mmp-ccic.1");
-
- clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
- CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
- 10, 5, 0, &clk_lock);
- clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1");
-
- clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div",
- apmu_base + APMU_CCIC1, 0x300, &clk_lock);
- clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1");
-}
diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
index bcf60f43aa13..eaad36ee323d 100644
--- a/drivers/clk/mmp/clk-of-mmp2.c
+++ b/drivers/clk/mmp/clk-of-mmp2.c
@@ -78,6 +78,8 @@
#define MPMU_PLL_DIFF_CTRL 0x68
#define MPMU_PLL2_CTRL1 0x414
+#define NR_CLKS 200
+
enum mmp2_clk_model {
CLK_MODEL_MMP2,
CLK_MODEL_MMP3,
@@ -543,7 +545,7 @@ static void __init mmp2_clk_init(struct device_node *np)
mmp2_pm_domain_init(np, pxa_unit);
- mmp_clk_init(np, &pxa_unit->unit, MMP2_NR_CLKS);
+ mmp_clk_init(np, &pxa_unit->unit, NR_CLKS);
mmp2_main_clk_init(pxa_unit);
diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c
index 130d1a723879..fb0df64cf053 100644
--- a/drivers/clk/mmp/clk-of-pxa168.c
+++ b/drivers/clk/mmp/clk-of-pxa168.c
@@ -62,6 +62,8 @@
#define APMU_EPD 0x104
#define MPMU_UART_PLL 0x14
+#define NR_CLKS 200
+
struct pxa168_clk_unit {
struct mmp_clk_unit unit;
void __iomem *mpmu_base;
@@ -321,7 +323,7 @@ static void __init pxa168_clk_init(struct device_node *np)
return;
}
- mmp_clk_init(np, &pxa_unit->unit, PXA168_NR_CLKS);
+ mmp_clk_init(np, &pxa_unit->unit, NR_CLKS);
pxa168_pll_init(pxa_unit);
diff --git a/drivers/clk/mmp/clk-of-pxa1928.c b/drivers/clk/mmp/clk-of-pxa1928.c
index 2508a0d795f8..9def4b5f10e9 100644
--- a/drivers/clk/mmp/clk-of-pxa1928.c
+++ b/drivers/clk/mmp/clk-of-pxa1928.c
@@ -22,6 +22,9 @@
#define MPMU_UART_PLL 0x14
+#define APBC_NR_CLKS 48
+#define APMU_NR_CLKS 96
+
struct pxa1928_clk_unit {
struct mmp_clk_unit unit;
void __iomem *mpmu_base;
@@ -235,7 +238,7 @@ static void __init pxa1928_apmu_clk_init(struct device_node *np)
return;
}
- mmp_clk_init(np, &pxa_unit->unit, PXA1928_APMU_NR_CLKS);
+ mmp_clk_init(np, &pxa_unit->unit, APMU_NR_CLKS);
pxa1928_axi_periph_clk_init(pxa_unit);
}
@@ -256,7 +259,7 @@ static void __init pxa1928_apbc_clk_init(struct device_node *np)
return;
}
- mmp_clk_init(np, &pxa_unit->unit, PXA1928_APBC_NR_CLKS);
+ mmp_clk_init(np, &pxa_unit->unit, APBC_NR_CLKS);
pxa1928_apb_periph_clk_init(pxa_unit);
pxa1928_clk_reset_init(np, pxa_unit);
diff --git a/drivers/clk/mmp/clk-of-pxa910.c b/drivers/clk/mmp/clk-of-pxa910.c
index 4d15bac987eb..7a38c424782e 100644
--- a/drivers/clk/mmp/clk-of-pxa910.c
+++ b/drivers/clk/mmp/clk-of-pxa910.c
@@ -44,6 +44,8 @@
#define APMU_DFC 0x60
#define MPMU_UART_PLL 0x14
+#define NR_CLKS 200
+
struct pxa910_clk_unit {
struct mmp_clk_unit unit;
void __iomem *mpmu_base;
@@ -296,7 +298,7 @@ static void __init pxa910_clk_init(struct device_node *np)
goto unmap_apbc_region;
}
- mmp_clk_init(np, &pxa_unit->unit, PXA910_NR_CLKS);
+ mmp_clk_init(np, &pxa_unit->unit, NR_CLKS);
pxa910_pll_init(pxa_unit);
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
deleted file mode 100644
index 8a9b8fb3a465..000000000000
--- a/drivers/clk/mmp/clk-pxa168.c
+++ /dev/null
@@ -1,354 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * pxa168 clock framework source file
- *
- * Copyright (C) 2012 Marvell
- * Chao Xie <xiechao.mail@gmail.com>
- */
-
-#include <linux/clk.h>
-#include <linux/clk/mmp.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-
-#include "clk.h"
-
-#define APBC_RTC 0x28
-#define APBC_TWSI0 0x2c
-#define APBC_KPC 0x30
-#define APBC_UART0 0x0
-#define APBC_UART1 0x4
-#define APBC_GPIO 0x8
-#define APBC_PWM0 0xc
-#define APBC_PWM1 0x10
-#define APBC_PWM2 0x14
-#define APBC_PWM3 0x18
-#define APBC_SSP0 0x81c
-#define APBC_SSP1 0x820
-#define APBC_SSP2 0x84c
-#define APBC_SSP3 0x858
-#define APBC_SSP4 0x85c
-#define APBC_TWSI1 0x6c
-#define APBC_UART2 0x70
-#define APMU_SDH0 0x54
-#define APMU_SDH1 0x58
-#define APMU_USB 0x5c
-#define APMU_DISP0 0x4c
-#define APMU_CCIC0 0x50
-#define APMU_DFC 0x60
-#define MPMU_UART_PLL 0x14
-
-static DEFINE_SPINLOCK(clk_lock);
-
-static struct mmp_clk_factor_masks uart_factor_masks = {
- .factor = 2,
- .num_mask = 0x1fff,
- .den_mask = 0x1fff,
- .num_shift = 16,
- .den_shift = 0,
-};
-
-static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
- {.num = 8125, .den = 1536}, /*14.745MHZ */
-};
-
-static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
-static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
-static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
-static const char *disp_parent[] = {"pll1_2", "pll1_12"};
-static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
-static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
-
-void __init pxa168_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
- phys_addr_t apbc_phys)
-{
- struct clk *clk;
- struct clk *uart_pll;
- void __iomem *mpmu_base;
- void __iomem *apmu_base;
- void __iomem *apbc_base;
-
- mpmu_base = ioremap(mpmu_phys, SZ_4K);
- if (!mpmu_base) {
- pr_err("error to ioremap MPMU base\n");
- return;
- }
-
- apmu_base = ioremap(apmu_phys, SZ_4K);
- if (!apmu_base) {
- pr_err("error to ioremap APMU base\n");
- return;
- }
-
- apbc_base = ioremap(apbc_phys, SZ_4K);
- if (!apbc_base) {
- pr_err("error to ioremap APBC base\n");
- return;
- }
-
- clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
- clk_register_clkdev(clk, "clk32", NULL);
-
- clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
- clk_register_clkdev(clk, "vctcxo", NULL);
-
- clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000);
- clk_register_clkdev(clk, "pll1", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_2", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_4", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_8", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_16", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
- CLK_SET_RATE_PARENT, 1, 3);
- clk_register_clkdev(clk, "pll1_6", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_12", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_24", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_48", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_96", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
- CLK_SET_RATE_PARENT, 1, 13);
- clk_register_clkdev(clk, "pll1_13", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
- CLK_SET_RATE_PARENT, 2, 3);
- clk_register_clkdev(clk, "pll1_13_1_5", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
- CLK_SET_RATE_PARENT, 2, 3);
- clk_register_clkdev(clk, "pll1_2_1_5", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
- CLK_SET_RATE_PARENT, 3, 16);
- clk_register_clkdev(clk, "pll1_3_16", NULL);
-
- uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
- mpmu_base + MPMU_UART_PLL,
- &uart_factor_masks, uart_factor_tbl,
- ARRAY_SIZE(uart_factor_tbl), &clk_lock);
- clk_set_rate(uart_pll, 14745600);
- clk_register_clkdev(uart_pll, "uart_pll", NULL);
-
- clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
- apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
-
- clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
- apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
-
- clk = mmp_clk_register_apbc("gpio", "vctcxo",
- apbc_base + APBC_GPIO, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp-gpio");
-
- clk = mmp_clk_register_apbc("kpc", "clk32",
- apbc_base + APBC_KPC, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa27x-keypad");
-
- clk = mmp_clk_register_apbc("rtc", "clk32",
- apbc_base + APBC_RTC, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "sa1100-rtc");
-
- clk = mmp_clk_register_apbc("pwm0", "pll1_48",
- apbc_base + APBC_PWM0, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa168-pwm.0");
-
- clk = mmp_clk_register_apbc("pwm1", "pll1_48",
- apbc_base + APBC_PWM1, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa168-pwm.1");
-
- clk = mmp_clk_register_apbc("pwm2", "pll1_48",
- apbc_base + APBC_PWM2, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa168-pwm.2");
-
- clk = mmp_clk_register_apbc("pwm3", "pll1_48",
- apbc_base + APBC_PWM3, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa168-pwm.3");
-
- clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
- ARRAY_SIZE(uart_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
- clk_set_parent(clk, uart_pll);
- clk_register_clkdev(clk, "uart_mux.0", NULL);
-
- clk = mmp_clk_register_apbc("uart0", "uart0_mux",
- apbc_base + APBC_UART0, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
-
- clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
- ARRAY_SIZE(uart_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
- clk_set_parent(clk, uart_pll);
- clk_register_clkdev(clk, "uart_mux.1", NULL);
-
- clk = mmp_clk_register_apbc("uart1", "uart1_mux",
- apbc_base + APBC_UART1, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
-
- clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
- ARRAY_SIZE(uart_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
- clk_set_parent(clk, uart_pll);
- clk_register_clkdev(clk, "uart_mux.2", NULL);
-
- clk = mmp_clk_register_apbc("uart2", "uart2_mux",
- apbc_base + APBC_UART2, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
-
- clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
- ARRAY_SIZE(ssp_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
- clk_register_clkdev(clk, "uart_mux.0", NULL);
-
- clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0,
- 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp-ssp.0");
-
- clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
- ARRAY_SIZE(ssp_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
- clk_register_clkdev(clk, "ssp_mux.1", NULL);
-
- clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1,
- 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp-ssp.1");
-
- clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
- ARRAY_SIZE(ssp_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
- clk_register_clkdev(clk, "ssp_mux.2", NULL);
-
- clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2,
- 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp-ssp.2");
-
- clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
- ARRAY_SIZE(ssp_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
- clk_register_clkdev(clk, "ssp_mux.3", NULL);
-
- clk = mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3,
- 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp-ssp.3");
-
- clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent,
- ARRAY_SIZE(ssp_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);
- clk_register_clkdev(clk, "ssp_mux.4", NULL);
-
- clk = mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4,
- 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp-ssp.4");
-
- clk = mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC,
- 0x19b, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
-
- clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
- ARRAY_SIZE(sdh_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
- clk_register_clkdev(clk, "sdh0_mux", NULL);
-
- clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0,
- 0x1b, &clk_lock);
- clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
-
- clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
- ARRAY_SIZE(sdh_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
- clk_register_clkdev(clk, "sdh1_mux", NULL);
-
- clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1,
- 0x1b, &clk_lock);
- clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
-
- clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
- 0x9, &clk_lock);
- clk_register_clkdev(clk, "usb_clk", NULL);
-
- clk = mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB,
- 0x12, &clk_lock);
- clk_register_clkdev(clk, "sph_clk", NULL);
-
- clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
- ARRAY_SIZE(disp_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
- clk_register_clkdev(clk, "disp_mux.0", NULL);
-
- clk = mmp_clk_register_apmu("disp0", "disp0_mux",
- apmu_base + APMU_DISP0, 0x1b, &clk_lock);
- clk_register_clkdev(clk, "fnclk", "mmp-disp.0");
-
- clk = mmp_clk_register_apmu("disp0_hclk", "disp0_mux",
- apmu_base + APMU_DISP0, 0x24, &clk_lock);
- clk_register_clkdev(clk, "hclk", "mmp-disp.0");
-
- clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
- ARRAY_SIZE(ccic_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
- clk_register_clkdev(clk, "ccic_mux.0", NULL);
-
- clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
- apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
- clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
-
- clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
- ARRAY_SIZE(ccic_phy_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
- clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
-
- clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
- apmu_base + APMU_CCIC0, 0x24, &clk_lock);
- clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
-
- clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
- CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
- 10, 5, 0, &clk_lock);
- clk_register_clkdev(clk, "sphyclk_div", NULL);
-
- clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
- apmu_base + APMU_CCIC0, 0x300, &clk_lock);
- clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
-}
diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c
deleted file mode 100644
index 9fcd76316d7e..000000000000
--- a/drivers/clk/mmp/clk-pxa910.c
+++ /dev/null
@@ -1,325 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * pxa910 clock framework source file
- *
- * Copyright (C) 2012 Marvell
- * Chao Xie <xiechao.mail@gmail.com>
- */
-
-#include <linux/clk.h>
-#include <linux/clk/mmp.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-
-#include "clk.h"
-
-#define APBC_RTC 0x28
-#define APBC_TWSI0 0x2c
-#define APBC_KPC 0x18
-#define APBC_UART0 0x0
-#define APBC_UART1 0x4
-#define APBC_GPIO 0x8
-#define APBC_PWM0 0xc
-#define APBC_PWM1 0x10
-#define APBC_PWM2 0x14
-#define APBC_PWM3 0x18
-#define APBC_SSP0 0x1c
-#define APBC_SSP1 0x20
-#define APBC_SSP2 0x4c
-#define APBCP_TWSI1 0x28
-#define APBCP_UART2 0x1c
-#define APMU_SDH0 0x54
-#define APMU_SDH1 0x58
-#define APMU_USB 0x5c
-#define APMU_DISP0 0x4c
-#define APMU_CCIC0 0x50
-#define APMU_DFC 0x60
-#define MPMU_UART_PLL 0x14
-
-static DEFINE_SPINLOCK(clk_lock);
-
-static struct mmp_clk_factor_masks uart_factor_masks = {
- .factor = 2,
- .num_mask = 0x1fff,
- .den_mask = 0x1fff,
- .num_shift = 16,
- .den_shift = 0,
-};
-
-static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
- {.num = 8125, .den = 1536}, /*14.745MHZ */
-};
-
-static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
-static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
-static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
-static const char *disp_parent[] = {"pll1_2", "pll1_12"};
-static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
-static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
-
-void __init pxa910_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
- phys_addr_t apbc_phys, phys_addr_t apbcp_phys)
-{
- struct clk *clk;
- struct clk *uart_pll;
- void __iomem *mpmu_base;
- void __iomem *apmu_base;
- void __iomem *apbcp_base;
- void __iomem *apbc_base;
-
- mpmu_base = ioremap(mpmu_phys, SZ_4K);
- if (!mpmu_base) {
- pr_err("error to ioremap MPMU base\n");
- return;
- }
-
- apmu_base = ioremap(apmu_phys, SZ_4K);
- if (!apmu_base) {
- pr_err("error to ioremap APMU base\n");
- return;
- }
-
- apbcp_base = ioremap(apbcp_phys, SZ_4K);
- if (!apbcp_base) {
- pr_err("error to ioremap APBC extension base\n");
- return;
- }
-
- apbc_base = ioremap(apbc_phys, SZ_4K);
- if (!apbc_base) {
- pr_err("error to ioremap APBC base\n");
- return;
- }
-
- clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
- clk_register_clkdev(clk, "clk32", NULL);
-
- clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
- clk_register_clkdev(clk, "vctcxo", NULL);
-
- clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000);
- clk_register_clkdev(clk, "pll1", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_2", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_4", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_8", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_16", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
- CLK_SET_RATE_PARENT, 1, 3);
- clk_register_clkdev(clk, "pll1_6", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_12", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_24", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_48", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
- CLK_SET_RATE_PARENT, 1, 2);
- clk_register_clkdev(clk, "pll1_96", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
- CLK_SET_RATE_PARENT, 1, 13);
- clk_register_clkdev(clk, "pll1_13", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
- CLK_SET_RATE_PARENT, 2, 3);
- clk_register_clkdev(clk, "pll1_13_1_5", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
- CLK_SET_RATE_PARENT, 2, 3);
- clk_register_clkdev(clk, "pll1_2_1_5", NULL);
-
- clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
- CLK_SET_RATE_PARENT, 3, 16);
- clk_register_clkdev(clk, "pll1_3_16", NULL);
-
- uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
- mpmu_base + MPMU_UART_PLL,
- &uart_factor_masks, uart_factor_tbl,
- ARRAY_SIZE(uart_factor_tbl), &clk_lock);
- clk_set_rate(uart_pll, 14745600);
- clk_register_clkdev(uart_pll, "uart_pll", NULL);
-
- clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
- apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
-
- clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
- apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
-
- clk = mmp_clk_register_apbc("gpio", "vctcxo",
- apbc_base + APBC_GPIO, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp-gpio");
-
- clk = mmp_clk_register_apbc("kpc", "clk32",
- apbc_base + APBC_KPC, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa27x-keypad");
-
- clk = mmp_clk_register_apbc("rtc", "clk32",
- apbc_base + APBC_RTC, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "sa1100-rtc");
-
- clk = mmp_clk_register_apbc("pwm0", "pll1_48",
- apbc_base + APBC_PWM0, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa910-pwm.0");
-
- clk = mmp_clk_register_apbc("pwm1", "pll1_48",
- apbc_base + APBC_PWM1, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa910-pwm.1");
-
- clk = mmp_clk_register_apbc("pwm2", "pll1_48",
- apbc_base + APBC_PWM2, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa910-pwm.2");
-
- clk = mmp_clk_register_apbc("pwm3", "pll1_48",
- apbc_base + APBC_PWM3, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa910-pwm.3");
-
- clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
- ARRAY_SIZE(uart_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
- clk_set_parent(clk, uart_pll);
- clk_register_clkdev(clk, "uart_mux.0", NULL);
-
- clk = mmp_clk_register_apbc("uart0", "uart0_mux",
- apbc_base + APBC_UART0, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
-
- clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
- ARRAY_SIZE(uart_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
- clk_set_parent(clk, uart_pll);
- clk_register_clkdev(clk, "uart_mux.1", NULL);
-
- clk = mmp_clk_register_apbc("uart1", "uart1_mux",
- apbc_base + APBC_UART1, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
-
- clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
- ARRAY_SIZE(uart_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
- clk_set_parent(clk, uart_pll);
- clk_register_clkdev(clk, "uart_mux.2", NULL);
-
- clk = mmp_clk_register_apbc("uart2", "uart2_mux",
- apbcp_base + APBCP_UART2, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
-
- clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
- ARRAY_SIZE(ssp_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
- clk_register_clkdev(clk, "uart_mux.0", NULL);
-
- clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
- apbc_base + APBC_SSP0, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp-ssp.0");
-
- clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
- ARRAY_SIZE(ssp_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
- clk_register_clkdev(clk, "ssp_mux.1", NULL);
-
- clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
- apbc_base + APBC_SSP1, 10, 0, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp-ssp.1");
-
- clk = mmp_clk_register_apmu("dfc", "pll1_4",
- apmu_base + APMU_DFC, 0x19b, &clk_lock);
- clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
-
- clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
- ARRAY_SIZE(sdh_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
- clk_register_clkdev(clk, "sdh0_mux", NULL);
-
- clk = mmp_clk_register_apmu("sdh0", "sdh_mux",
- apmu_base + APMU_SDH0, 0x1b, &clk_lock);
- clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
-
- clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
- ARRAY_SIZE(sdh_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
- clk_register_clkdev(clk, "sdh1_mux", NULL);
-
- clk = mmp_clk_register_apmu("sdh1", "sdh1_mux",
- apmu_base + APMU_SDH1, 0x1b, &clk_lock);
- clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
-
- clk = mmp_clk_register_apmu("usb", "usb_pll",
- apmu_base + APMU_USB, 0x9, &clk_lock);
- clk_register_clkdev(clk, "usb_clk", NULL);
-
- clk = mmp_clk_register_apmu("sph", "usb_pll",
- apmu_base + APMU_USB, 0x12, &clk_lock);
- clk_register_clkdev(clk, "sph_clk", NULL);
-
- clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
- ARRAY_SIZE(disp_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
- clk_register_clkdev(clk, "disp_mux.0", NULL);
-
- clk = mmp_clk_register_apmu("disp0", "disp0_mux",
- apmu_base + APMU_DISP0, 0x1b, &clk_lock);
- clk_register_clkdev(clk, NULL, "mmp-disp.0");
-
- clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
- ARRAY_SIZE(ccic_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
- clk_register_clkdev(clk, "ccic_mux.0", NULL);
-
- clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
- apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
- clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
-
- clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
- ARRAY_SIZE(ccic_phy_parent),
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
- apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
- clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
-
- clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
- apmu_base + APMU_CCIC0, 0x24, &clk_lock);
- clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
-
- clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
- CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
- 10, 5, 0, &clk_lock);
- clk_register_clkdev(clk, "sphyclk_div", NULL);
-
- clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
- apmu_base + APMU_CCIC0, 0x300, &clk_lock);
- clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
-}
diff --git a/drivers/clk/mvebu/ap-cpu-clk.c b/drivers/clk/mvebu/ap-cpu-clk.c
index d8a7a4c90d54..677cc3514849 100644
--- a/drivers/clk/mvebu/ap-cpu-clk.c
+++ b/drivers/clk/mvebu/ap-cpu-clk.c
@@ -15,7 +15,6 @@
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "armada_ap_cp_helper.h"
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
index 3ae6078f6ff7..8701a58a5804 100644
--- a/drivers/clk/mvebu/armada-37xx-periph.c
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
@@ -21,7 +21,6 @@
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
@@ -733,7 +732,6 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
const struct clk_periph_data *data;
struct device *dev = &pdev->dev;
int num_periph = 0, i, ret;
- struct resource *res;
data = of_device_get_match_data(dev);
if (!data)
@@ -754,8 +752,7 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
return -ENOMEM;
driver_data->hw_data->num = num_periph;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- driver_data->reg = devm_ioremap_resource(dev, res);
+ driver_data->reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(driver_data->reg))
return PTR_ERR(driver_data->reg);
diff --git a/drivers/clk/mvebu/armada-37xx-tbg.c b/drivers/clk/mvebu/armada-37xx-tbg.c
index eccc1aeefbaf..e94c336e0f1c 100644
--- a/drivers/clk/mvebu/armada-37xx-tbg.c
+++ b/drivers/clk/mvebu/armada-37xx-tbg.c
@@ -84,7 +84,6 @@ static int armada_3700_tbg_clock_probe(struct platform_device *pdev)
struct clk_hw_onecell_data *hw_tbg_data;
struct device *dev = &pdev->dev;
const char *parent_name;
- struct resource *res;
struct clk *parent;
void __iomem *reg;
int i;
@@ -105,8 +104,7 @@ static int armada_3700_tbg_clock_probe(struct platform_device *pdev)
parent_name = __clk_get_name(parent);
clk_put(parent);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- reg = devm_ioremap_resource(dev, res);
+ reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
diff --git a/drivers/clk/mvebu/cp110-system-controller.c b/drivers/clk/mvebu/cp110-system-controller.c
index 84c8900542e4..03c59bf22106 100644
--- a/drivers/clk/mvebu/cp110-system-controller.c
+++ b/drivers/clk/mvebu/cp110-system-controller.c
@@ -240,9 +240,9 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
GFP_KERNEL);
if (!cp110_clk_data)
return -ENOMEM;
+ cp110_clk_data->num = CP110_CLK_NUM;
cp110_clks = cp110_clk_data->hws;
- cp110_clk_data->num = CP110_CLK_NUM;
/* Register the PLL0 which is the root of the hw tree */
pll0_name = ap_cp_unique_name(dev, syscon_node, "pll0");
diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma35d1.c
index f1fe7edd21b5..9f65d0623517 100644
--- a/drivers/clk/nuvoton/clk-ma35d1.c
+++ b/drivers/clk/nuvoton/clk-ma35d1.c
@@ -460,7 +460,6 @@ static int ma35d1_clocks_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *clk_node = pdev->dev.of_node;
- struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
void __iomem *clk_base;
static struct clk_hw **hws;
static struct clk_hw_onecell_data *ma35d1_hw_data;
@@ -476,7 +475,7 @@ static int ma35d1_clocks_probe(struct platform_device *pdev)
ma35d1_hw_data->num = CLK_MAX_IDX;
hws = ma35d1_hw_data->hws;
- clk_base = devm_ioremap_resource(dev, res);
+ clk_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(clk_base))
return PTR_ERR(clk_base);
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 263e55d75e3f..865db5202e4c 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -145,6 +145,14 @@ config IPQ_GCC_4019
Say Y if you want to use peripheral devices such as UART, SPI,
i2c, USB, SD/eMMC, etc.
+config IPQ_GCC_5018
+ tristate "IPQ5018 Global Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ help
+ Support for global clock controller on ipq5018 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2c, USB, SD/eMMC, etc.
+
config IPQ_GCC_5332
tristate "IPQ5332 Global Clock Controller"
depends on ARM64 || COMPILE_TEST
@@ -247,11 +255,11 @@ config MSM_GCC_8960
i2c, USB, SD/eMMC, SATA, PCIe, etc.
config MSM_LCC_8960
- tristate "APQ8064/MSM8960 LPASS Clock Controller"
+ tristate "APQ8064/MSM8960/MDM9650 LPASS Clock Controller"
depends on ARM || COMPILE_TEST
- select MSM_GCC_8960
help
- Support for the LPASS clock controller on apq8064/msm8960 devices.
+ Support for the LPASS clock controller on apq8064/msm8960/mdm9650
+ devices.
Say Y if you want to use audio devices such as i2s, pcm,
SLIMBus, etc.
@@ -271,15 +279,6 @@ config MDM_GCC_9615
Say Y if you want to use peripheral devices such as UART, SPI,
i2c, USB, SD/eMMC, etc.
-config MDM_LCC_9615
- tristate "MDM9615 LPASS Clock Controller"
- depends on ARM || COMPILE_TEST
- select MDM_GCC_9615
- help
- Support for the LPASS clock controller on mdm9615 devices.
- Say Y if you want to use audio devices such as i2s, pcm,
- SLIMBus, etc.
-
config MSM_MMCC_8960
tristate "MSM8960 Multimedia Clock Controller"
depends on ARM || COMPILE_TEST
@@ -987,6 +986,7 @@ config SM_GPUCC_8350
config SM_GPUCC_8450
tristate "SM8450 Graphics Clock Controller"
+ depends on ARM64 || COMPILE_TEST
select SM_GCC_8450
help
Support for the graphics clock controller on SM8450 devices.
@@ -995,6 +995,7 @@ config SM_GPUCC_8450
config SM_GPUCC_8550
tristate "SM8550 Graphics Clock Controller"
+ depends on ARM64 || COMPILE_TEST
select SM_GCC_8550
help
Support for the graphics clock controller on SM8550 devices.
@@ -1031,6 +1032,7 @@ config SM_VIDEOCC_8250
config SM_VIDEOCC_8350
tristate "SM8350 Video Clock Controller"
+ depends on ARM64 || COMPILE_TEST
select SM_GCC_8350
select QCOM_GDSC
help
@@ -1040,6 +1042,7 @@ config SM_VIDEOCC_8350
config SM_VIDEOCC_8550
tristate "SM8550 Video Clock Controller"
+ depends on ARM64 || COMPILE_TEST
select SM_GCC_8550
select QCOM_GDSC
help
@@ -1088,6 +1091,7 @@ config CLK_GFM_LPASS_SM8250
config SM_VIDEOCC_8450
tristate "SM8450 Video Clock Controller"
+ depends on ARM64 || COMPILE_TEST
select SM_GCC_8450
select QCOM_GDSC
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index e6e294274c35..4790c8cca426 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
+obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o
obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o
obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
@@ -32,7 +33,6 @@ obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
-obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o
obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
obj-$(CONFIG_MSM_GCC_8909) += gcc-msm8909.o
obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o
diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
index ce28d882ee78..e170331858cc 100644
--- a/drivers/clk/qcom/apss-ipq-pll.c
+++ b/drivers/clk/qcom/apss-ipq-pll.c
@@ -2,7 +2,7 @@
// Copyright (c) 2018, The Linux Foundation. All rights reserved.
#include <linux/clk-provider.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c
index 8a4ba7a19ed1..0a9a6df3ddac 100644
--- a/drivers/clk/qcom/camcc-sc7180.c
+++ b/drivers/clk/qcom/camcc-sc7180.c
@@ -7,7 +7,7 @@
#include <linux/err.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
@@ -1664,7 +1664,7 @@ static int cam_cc_sc7180_probe(struct platform_device *pdev)
return ret;
}
- ret = pm_runtime_get(&pdev->dev);
+ ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
diff --git a/drivers/clk/qcom/camcc-sc7280.c b/drivers/clk/qcom/camcc-sc7280.c
index 4396fddba7a6..49f046ea857c 100644
--- a/drivers/clk/qcom/camcc-sc7280.c
+++ b/drivers/clk/qcom/camcc-sc7280.c
@@ -7,8 +7,8 @@
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/of_device.h>
#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,camcc-sc7280.h>
diff --git a/drivers/clk/qcom/clk-cbf-8996.c b/drivers/clk/qcom/clk-cbf-8996.c
index 1e23b734abb3..53f205a3f183 100644
--- a/drivers/clk/qcom/clk-cbf-8996.c
+++ b/drivers/clk/qcom/clk-cbf-8996.c
@@ -52,7 +52,7 @@ static const u8 cbf_pll_regs[PLL_OFF_MAX_REGS] = {
[PLL_OFF_STATUS] = 0x28,
};
-static const struct alpha_pll_config cbfpll_config = {
+static struct alpha_pll_config cbfpll_config = {
.l = 72,
.config_ctl_val = 0x200d4828,
.config_ctl_hi_val = 0x006,
@@ -141,7 +141,7 @@ static int clk_cbf_8996_mux_determine_rate(struct clk_hw *hw,
{
struct clk_hw *parent;
- if (req->rate < (DIV_THRESHOLD / 2))
+ if (req->rate < (DIV_THRESHOLD / cbf_pll_postdiv.div))
return -EINVAL;
if (req->rate < DIV_THRESHOLD)
@@ -312,6 +312,11 @@ static int qcom_msm8996_cbf_probe(struct platform_device *pdev)
/* Switch CBF to use the primary PLL */
regmap_update_bits(regmap, CBF_MUX_OFFSET, CBF_MUX_PARENT_MASK, 0x1);
+ if (of_device_is_compatible(dev->of_node, "qcom,msm8996pro-cbf")) {
+ cbfpll_config.post_div_val = 0x3 << 8;
+ cbf_pll_postdiv.div = 4;
+ }
+
for (i = 0; i < ARRAY_SIZE(cbf_msm8996_hw_clks); i++) {
ret = devm_clk_hw_register(dev, cbf_msm8996_hw_clks[i]);
if (ret)
@@ -342,6 +347,7 @@ static int qcom_msm8996_cbf_remove(struct platform_device *pdev)
static const struct of_device_id qcom_msm8996_cbf_match_table[] = {
{ .compatible = "qcom,msm8996-cbf" },
+ { .compatible = "qcom,msm8996pro-cbf" },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, qcom_msm8996_cbf_match_table);
diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
index 592c7c3cdeb7..72689448a653 100644
--- a/drivers/clk/qcom/clk-cpu-8996.c
+++ b/drivers/clk/qcom/clk-cpu-8996.c
@@ -590,6 +590,7 @@ static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
data = devm_kzalloc(dev, struct_size(data, hws, 2), GFP_KERNEL);
if (!data)
return -ENOMEM;
+ data->num = 2;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
@@ -605,7 +606,6 @@ static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
data->hws[0] = &pwrcl_pmux.clkr.hw;
data->hws[1] = &perfcl_pmux.clkr.hw;
- data->num = 2;
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data);
}
diff --git a/drivers/clk/qcom/clk-rpm.c b/drivers/clk/qcom/clk-rpm.c
index cac623e27b0e..745026ef4d9c 100644
--- a/drivers/clk/qcom/clk-rpm.c
+++ b/drivers/clk/qcom/clk-rpm.c
@@ -13,7 +13,6 @@
#include <linux/mutex.h>
#include <linux/mfd/qcom_rpm.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <dt-bindings/mfd/qcom-rpm.h>
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 86572570bc54..4c5b552b47b6 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -8,7 +8,6 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <soc/qcom/cmd-db.h>
#include <soc/qcom/rpmh.h>
diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
index e4de74b68797..0191fc0dd7da 100644
--- a/drivers/clk/qcom/clk-smd-rpm.c
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -12,21 +12,13 @@
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/soc/qcom/smd-rpm.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
-#define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773
-#define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370
-#define QCOM_RPM_SMD_KEY_RATE 0x007a484b
-#define QCOM_RPM_SMD_KEY_ENABLE 0x62616e45
-#define QCOM_RPM_SMD_KEY_STATE 0x54415453
-#define QCOM_RPM_SCALING_ENABLE_ID 0x2
-
#define __DEFINE_CLK_SMD_RPM_PREFIX(_prefix, _name, _active, \
- type, r_id, key) \
+ type, r_id, key, ao_rate, ao_flags) \
static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \
static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \
.rpm_res_type = (type), \
@@ -50,7 +42,7 @@
.active_only = true, \
.rpm_key = (key), \
.peer = &clk_smd_rpm_##_prefix##_name, \
- .rate = INT_MAX, \
+ .rate = (ao_rate), \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_smd_rpm_ops, \
.name = #_active, \
@@ -59,12 +51,14 @@
.name = "xo_board", \
}, \
.num_parents = 1, \
+ .flags = (ao_flags), \
}, \
}
-#define __DEFINE_CLK_SMD_RPM(_name, _active, type, r_id, key) \
+#define __DEFINE_CLK_SMD_RPM(_name, _active, type, r_id, key,\
+ ao_rate, ao_flags) \
__DEFINE_CLK_SMD_RPM_PREFIX(/* empty */, _name, _active, \
- type, r_id, key)
+ type, r_id, key, ao_rate, ao_flags)
#define __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, _name, _active,\
type, r_id, r, key, ao_flags) \
@@ -112,17 +106,22 @@
#define DEFINE_CLK_SMD_RPM(_name, type, r_id) \
__DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \
- type, r_id, QCOM_RPM_SMD_KEY_RATE)
+ type, r_id, QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0)
#define DEFINE_CLK_SMD_RPM_BUS(_name, r_id) \
__DEFINE_CLK_SMD_RPM_PREFIX(bus_##r_id##_, \
_name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \
- QCOM_RPM_SMD_KEY_RATE)
+ QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0)
+
+#define DEFINE_CLK_SMD_RPM_BUS_A(_name, r_id, ao_rate, ao_flags) \
+ __DEFINE_CLK_SMD_RPM_PREFIX(bus_##r_id##_, \
+ _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \
+ QCOM_RPM_SMD_KEY_RATE, ao_rate, ao_flags)
#define DEFINE_CLK_SMD_RPM_CLK_SRC(_name, type, r_id) \
__DEFINE_CLK_SMD_RPM( \
_name##_clk_src, _name##_a_clk_src, \
- type, r_id, QCOM_RPM_SMD_KEY_RATE)
+ type, r_id, QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0)
#define DEFINE_CLK_SMD_RPM_BRANCH(_name, type, r_id, r) \
__DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \
@@ -136,7 +135,7 @@
#define DEFINE_CLK_SMD_RPM_QDSS(_name, type, r_id) \
__DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \
- type, r_id, QCOM_RPM_SMD_KEY_STATE)
+ type, r_id, QCOM_RPM_SMD_KEY_STATE, INT_MAX, 0)
#define DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r) \
__DEFINE_CLK_SMD_RPM_BRANCH(_name, _name##_a, \
@@ -171,21 +170,23 @@ struct clk_smd_rpm {
unsigned long rate;
};
-struct clk_smd_rpm_req {
- __le32 key;
- __le32 nbytes;
- __le32 value;
-};
-
struct rpm_smd_clk_desc {
struct clk_smd_rpm **clks;
size_t num_clks;
+
+ /*
+ * Interconnect clocks are managed by the icc framework, this driver
+ * only kickstarts them so that they don't get gated between
+ * clk_smd_rpm_enable_scaling() and interconnect driver initialization.
+ */
+ const struct clk_smd_rpm ** const icc_clks;
+ size_t num_icc_clks;
bool scaling_before_handover;
};
static DEFINE_MUTEX(rpm_smd_clk_lock);
-static int clk_smd_rpm_handoff(struct clk_smd_rpm *r)
+static int clk_smd_rpm_handoff(const struct clk_smd_rpm *r)
{
int ret;
struct clk_smd_rpm_req req = {
@@ -454,7 +455,7 @@ DEFINE_CLK_SMD_RPM_BRANCH(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2, 1000);
DEFINE_CLK_SMD_RPM(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1);
DEFINE_CLK_SMD_RPM(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2);
-DEFINE_CLK_SMD_RPM_BUS(pcnoc, 0);
+DEFINE_CLK_SMD_RPM_BUS_A(pcnoc, 0, 19200000, CLK_IS_CRITICAL);
DEFINE_CLK_SMD_RPM_BUS(snoc, 1);
DEFINE_CLK_SMD_RPM_BUS(sysmmnoc, 2);
DEFINE_CLK_SMD_RPM_BUS(cnoc, 2);
@@ -511,13 +512,69 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk1, 11, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk2, 12, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk3, 13, 19200000);
+static const struct clk_smd_rpm *bimc_pcnoc_icc_clks[] = {
+ &clk_smd_rpm_bimc_clk,
+ &clk_smd_rpm_bus_0_pcnoc_clk,
+};
+
+static const struct clk_smd_rpm *bimc_pcnoc_snoc_icc_clks[] = {
+ &clk_smd_rpm_bimc_clk,
+ &clk_smd_rpm_bus_0_pcnoc_clk,
+ &clk_smd_rpm_bus_1_snoc_clk,
+};
+
+static const struct clk_smd_rpm *bimc_pcnoc_snoc_smmnoc_icc_clks[] = {
+ &clk_smd_rpm_bimc_clk,
+ &clk_smd_rpm_bus_0_pcnoc_clk,
+ &clk_smd_rpm_bus_1_snoc_clk,
+ &clk_smd_rpm_bus_2_sysmmnoc_clk,
+};
+
+static const struct clk_smd_rpm *bimc_pcnoc_snoc_cnoc_ocmem_icc_clks[] = {
+ &clk_smd_rpm_bimc_clk,
+ &clk_smd_rpm_bus_0_pcnoc_clk,
+ &clk_smd_rpm_bus_1_snoc_clk,
+ &clk_smd_rpm_bus_2_cnoc_clk,
+ &clk_smd_rpm_ocmemgx_clk,
+};
+
+static const struct clk_smd_rpm *msm8996_icc_clks[] = {
+ &clk_smd_rpm_bimc_clk,
+ &clk_smd_rpm_branch_aggre1_noc_clk,
+ &clk_smd_rpm_branch_aggre2_noc_clk,
+ &clk_smd_rpm_bus_0_pcnoc_clk,
+ &clk_smd_rpm_bus_1_snoc_clk,
+ &clk_smd_rpm_bus_2_cnoc_clk,
+ &clk_smd_rpm_mmssnoc_axi_rpm_clk,
+};
+
+static const struct clk_smd_rpm *msm8998_icc_clks[] = {
+ &clk_smd_rpm_aggre1_noc_clk,
+ &clk_smd_rpm_aggre2_noc_clk,
+ &clk_smd_rpm_bimc_clk,
+ &clk_smd_rpm_bus_1_snoc_clk,
+ &clk_smd_rpm_bus_2_cnoc_clk,
+ &clk_smd_rpm_mmssnoc_axi_rpm_clk,
+};
+
+static const struct clk_smd_rpm *sdm660_icc_clks[] = {
+ &clk_smd_rpm_aggre2_noc_clk,
+ &clk_smd_rpm_bimc_clk,
+ &clk_smd_rpm_bus_1_snoc_clk,
+ &clk_smd_rpm_bus_2_cnoc_clk,
+ &clk_smd_rpm_mmssnoc_axi_rpm_clk,
+};
+
+static const struct clk_smd_rpm *sm_qnoc_icc_clks[] = {
+ &clk_smd_rpm_bimc_clk,
+ &clk_smd_rpm_bus_1_cnoc_clk,
+ &clk_smd_rpm_mmnrt_clk,
+ &clk_smd_rpm_mmrt_clk,
+ &clk_smd_rpm_qup_clk,
+ &clk_smd_rpm_bus_2_snoc_clk,
+};
+
static struct clk_smd_rpm *msm8909_clks[] = {
- [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
- [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
- [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
- [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
- [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
- [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
[RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk,
[RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
@@ -543,15 +600,11 @@ static struct clk_smd_rpm *msm8909_clks[] = {
static const struct rpm_smd_clk_desc rpm_clk_msm8909 = {
.clks = msm8909_clks,
.num_clks = ARRAY_SIZE(msm8909_clks),
+ .icc_clks = bimc_pcnoc_snoc_icc_clks,
+ .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),
};
static struct clk_smd_rpm *msm8916_clks[] = {
- [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
- [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
- [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
- [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
- [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
- [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
@@ -575,21 +628,15 @@ static struct clk_smd_rpm *msm8916_clks[] = {
static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
.clks = msm8916_clks,
.num_clks = ARRAY_SIZE(msm8916_clks),
+ .icc_clks = bimc_pcnoc_snoc_icc_clks,
+ .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),
};
static struct clk_smd_rpm *msm8917_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
- [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
- [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
- [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
- [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
- [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
- [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
[RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk,
[RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk,
- [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk,
- [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
@@ -609,19 +656,13 @@ static struct clk_smd_rpm *msm8917_clks[] = {
static const struct rpm_smd_clk_desc rpm_clk_msm8917 = {
.clks = msm8917_clks,
.num_clks = ARRAY_SIZE(msm8917_clks),
+ .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
+ .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
};
static struct clk_smd_rpm *msm8936_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
- [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
- [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
- [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
- [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
- [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
- [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
- [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk,
- [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
@@ -645,25 +686,17 @@ static struct clk_smd_rpm *msm8936_clks[] = {
static const struct rpm_smd_clk_desc rpm_clk_msm8936 = {
.clks = msm8936_clks,
.num_clks = ARRAY_SIZE(msm8936_clks),
+ .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
+ .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
};
static struct clk_smd_rpm *msm8974_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
- [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
- [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
- [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
- [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
- [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
- [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
[RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk,
[RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk,
- [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
[RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src,
[RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src,
- [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
- [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk,
- [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_CXO_D0] = &clk_smd_rpm_cxo_d0,
@@ -697,20 +730,14 @@ static struct clk_smd_rpm *msm8974_clks[] = {
static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
.clks = msm8974_clks,
.num_clks = ARRAY_SIZE(msm8974_clks),
+ .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,
+ .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),
.scaling_before_handover = true,
};
static struct clk_smd_rpm *msm8976_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
- [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
- [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
- [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
- [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
- [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
- [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
- [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk,
- [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
@@ -731,24 +758,15 @@ static struct clk_smd_rpm *msm8976_clks[] = {
static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
.clks = msm8976_clks,
- .num_clks = ARRAY_SIZE(msm8976_clks),
+ .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
+ .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
};
static struct clk_smd_rpm *msm8992_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
- [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
- [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
- [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk,
- [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk,
- [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
- [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
- [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
- [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
[RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src,
[RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src,
- [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
- [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
[RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
@@ -790,23 +808,15 @@ static struct clk_smd_rpm *msm8992_clks[] = {
static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {
.clks = msm8992_clks,
.num_clks = ARRAY_SIZE(msm8992_clks),
+ .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,
+ .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),
};
static struct clk_smd_rpm *msm8994_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
- [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
- [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
- [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk,
- [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk,
- [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
- [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
- [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
- [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
[RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src,
[RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src,
- [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
- [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
[RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
@@ -850,29 +860,17 @@ static struct clk_smd_rpm *msm8994_clks[] = {
static const struct rpm_smd_clk_desc rpm_clk_msm8994 = {
.clks = msm8994_clks,
.num_clks = ARRAY_SIZE(msm8994_clks),
+ .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,
+ .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),
};
static struct clk_smd_rpm *msm8996_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
- [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
- [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
- [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
- [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
- [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
- [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
- [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
- [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
- [RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk,
- [RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk,
[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
- [RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_branch_aggre1_noc_clk,
- [RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_branch_aggre1_noc_a_clk,
- [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_branch_aggre2_noc_clk,
- [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_branch_aggre2_noc_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
@@ -904,6 +902,8 @@ static struct clk_smd_rpm *msm8996_clks[] = {
static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
.clks = msm8996_clks,
.num_clks = ARRAY_SIZE(msm8996_clks),
+ .icc_clks = msm8996_icc_clks,
+ .num_icc_clks = ARRAY_SIZE(msm8996_icc_clks),
};
static struct clk_smd_rpm *qcs404_clks[] = {
@@ -932,19 +932,15 @@ static struct clk_smd_rpm *qcs404_clks[] = {
static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
.clks = qcs404_clks,
.num_clks = ARRAY_SIZE(qcs404_clks),
+ .icc_clks = bimc_pcnoc_snoc_icc_clks,
+ .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),
};
static struct clk_smd_rpm *msm8998_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
- [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
- [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
[RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
[RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
- [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
- [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
- [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
- [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
[RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,
@@ -967,12 +963,6 @@ static struct clk_smd_rpm *msm8998_clks[] = {
[RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin,
[RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin,
[RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin,
- [RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk,
- [RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk,
- [RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_aggre1_noc_clk,
- [RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_aggre1_noc_a_clk,
- [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk,
- [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
@@ -992,27 +982,19 @@ static struct clk_smd_rpm *msm8998_clks[] = {
static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
.clks = msm8998_clks,
.num_clks = ARRAY_SIZE(msm8998_clks),
+ .icc_clks = msm8998_icc_clks,
+ .num_icc_clks = ARRAY_SIZE(msm8998_icc_clks),
};
static struct clk_smd_rpm *sdm660_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
- [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
- [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
- [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk,
- [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk,
[RPM_SMD_CNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
[RPM_SMD_CNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
- [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
- [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
- [RPM_SMD_MMSSNOC_AXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk,
- [RPM_SMD_MMSSNOC_AXI_CLK_A] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk,
[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
- [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk,
- [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
@@ -1038,15 +1020,13 @@ static struct clk_smd_rpm *sdm660_clks[] = {
static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
.clks = sdm660_clks,
.num_clks = ARRAY_SIZE(sdm660_clks),
+ .icc_clks = sdm660_icc_clks,
+ .num_icc_clks = ARRAY_SIZE(sdm660_icc_clks),
};
static struct clk_smd_rpm *mdm9607_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
- [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
- [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
- [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
- [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
[RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk,
[RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
@@ -1060,21 +1040,15 @@ static struct clk_smd_rpm *mdm9607_clks[] = {
static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = {
.clks = mdm9607_clks,
.num_clks = ARRAY_SIZE(mdm9607_clks),
+ .icc_clks = bimc_pcnoc_icc_clks,
+ .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_icc_clks),
};
static struct clk_smd_rpm *msm8953_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
- [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
- [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
- [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
- [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
- [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
- [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
- [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk,
- [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
@@ -1096,23 +1070,19 @@ static struct clk_smd_rpm *msm8953_clks[] = {
static const struct rpm_smd_clk_desc rpm_clk_msm8953 = {
.clks = msm8953_clks,
.num_clks = ARRAY_SIZE(msm8953_clks),
+ .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,
+ .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),
};
static struct clk_smd_rpm *sm6125_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
- [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk,
- [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk,
- [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
- [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
- [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk,
- [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk,
[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
@@ -1123,12 +1093,6 @@ static struct clk_smd_rpm *sm6125_clks[] = {
[RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,
[RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3,
[RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a,
- [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk,
- [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk,
- [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk,
- [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk,
- [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk,
- [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk,
[RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
[RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
[RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
@@ -1138,34 +1102,24 @@ static struct clk_smd_rpm *sm6125_clks[] = {
static const struct rpm_smd_clk_desc rpm_clk_sm6125 = {
.clks = sm6125_clks,
.num_clks = ARRAY_SIZE(sm6125_clks),
+ .icc_clks = sm_qnoc_icc_clks,
+ .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
};
/* SM6115 */
static struct clk_smd_rpm *sm6115_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
- [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk,
- [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk,
- [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
- [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
[RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,
[RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,
[RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
- [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk,
- [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk,
[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
[RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,
[RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,
- [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk,
- [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk,
- [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk,
- [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk,
- [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk,
- [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk,
[RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
[RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
[RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
@@ -1179,27 +1133,17 @@ static struct clk_smd_rpm *sm6115_clks[] = {
static const struct rpm_smd_clk_desc rpm_clk_sm6115 = {
.clks = sm6115_clks,
.num_clks = ARRAY_SIZE(sm6115_clks),
+ .icc_clks = sm_qnoc_icc_clks,
+ .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
};
static struct clk_smd_rpm *sm6375_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
- [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk,
- [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk,
- [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
- [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
- [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk,
- [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk,
[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
- [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk,
- [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk,
- [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk,
- [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk,
- [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk,
- [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk,
[RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
[RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
[RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
@@ -1216,31 +1160,21 @@ static struct clk_smd_rpm *sm6375_clks[] = {
static const struct rpm_smd_clk_desc rpm_clk_sm6375 = {
.clks = sm6375_clks,
.num_clks = ARRAY_SIZE(sm6375_clks),
+ .icc_clks = sm_qnoc_icc_clks,
+ .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
};
static struct clk_smd_rpm *qcm2290_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
- [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk,
- [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk,
- [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
- [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,
[RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2,
[RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,
[RPM_SMD_RF_CLK3] = &clk_smd_rpm_38m4_rf_clk3,
[RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_38m4_rf_clk3_a,
- [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk,
- [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk,
[RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,
[RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,
- [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk,
- [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk,
- [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk,
- [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk,
- [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk,
- [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk,
[RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,
[RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,
[RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,
@@ -1262,6 +1196,8 @@ static struct clk_smd_rpm *qcm2290_clks[] = {
static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = {
.clks = qcm2290_clks,
.num_clks = ARRAY_SIZE(qcm2290_clks),
+ .icc_clks = sm_qnoc_icc_clks,
+ .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)
};
static const struct of_device_id rpm_smd_clk_match_table[] = {
@@ -1302,12 +1238,20 @@ static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec,
return desc->clks[idx] ? &desc->clks[idx]->hw : ERR_PTR(-ENOENT);
}
+static void rpm_smd_unregister_icc(void *data)
+{
+ struct platform_device *icc_pdev = data;
+
+ platform_device_unregister(icc_pdev);
+}
+
static int rpm_smd_clk_probe(struct platform_device *pdev)
{
int ret;
size_t num_clks, i;
struct clk_smd_rpm **rpm_smd_clks;
const struct rpm_smd_clk_desc *desc;
+ struct platform_device *icc_pdev;
rpmcc_smd_rpm = dev_get_drvdata(pdev->dev.parent);
if (!rpmcc_smd_rpm) {
@@ -1337,6 +1281,15 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
goto err;
}
+ for (i = 0; i < desc->num_icc_clks; i++) {
+ if (!desc->icc_clks[i])
+ continue;
+
+ ret = clk_smd_rpm_handoff(desc->icc_clks[i]);
+ if (ret)
+ goto err;
+ }
+
if (!desc->scaling_before_handover) {
ret = clk_smd_rpm_enable_scaling();
if (ret)
@@ -1357,6 +1310,19 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
if (ret)
goto err;
+ icc_pdev = platform_device_register_data(pdev->dev.parent,
+ "icc_smd_rpm", -1, NULL, 0);
+ if (IS_ERR(icc_pdev)) {
+ dev_err(&pdev->dev, "Failed to register icc_smd_rpm device: %pE\n",
+ icc_pdev);
+ /* No need to unregister clocks because of this */
+ } else {
+ ret = devm_add_action_or_reset(&pdev->dev, rpm_smd_unregister_icc,
+ icc_pdev);
+ if (ret)
+ goto err;
+ }
+
return 0;
err:
dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret);
diff --git a/drivers/clk/qcom/clk-spmi-pmic-div.c b/drivers/clk/qcom/clk-spmi-pmic-div.c
index f846be285f51..f394031eb0e5 100644
--- a/drivers/clk/qcom/clk-spmi-pmic-div.c
+++ b/drivers/clk/qcom/clk-spmi-pmic-div.c
@@ -177,7 +177,7 @@ static const struct clk_ops clk_spmi_pmic_div_ops = {
struct spmi_pmic_div_clk_cc {
int nclks;
- struct clkdiv clks[];
+ struct clkdiv clks[] __counted_by(nclks);
};
static struct clk_hw *
diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
index 44dd5cfcc150..9206f0eed446 100644
--- a/drivers/clk/qcom/dispcc-qcm2290.c
+++ b/drivers/clk/qcom/dispcc-qcm2290.c
@@ -7,8 +7,8 @@
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/of_device.h>
#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
diff --git a/drivers/clk/qcom/dispcc-sc8280xp.c b/drivers/clk/qcom/dispcc-sc8280xp.c
index 167470beb369..30f636b9f0ec 100644
--- a/drivers/clk/qcom/dispcc-sc8280xp.c
+++ b/drivers/clk/qcom/dispcc-sc8280xp.c
@@ -3057,7 +3057,7 @@ static struct gdsc disp0_mdss_gdsc = {
.name = "disp0_mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
- .flags = HW_CTRL,
+ .flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct gdsc disp1_mdss_gdsc = {
@@ -3069,7 +3069,7 @@ static struct gdsc disp1_mdss_gdsc = {
.name = "disp1_mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
- .flags = HW_CTRL,
+ .flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct gdsc disp0_mdss_int2_gdsc = {
@@ -3081,7 +3081,7 @@ static struct gdsc disp0_mdss_int2_gdsc = {
.name = "disp0_mdss_int2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
- .flags = HW_CTRL,
+ .flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct gdsc disp1_mdss_int2_gdsc = {
@@ -3093,7 +3093,7 @@ static struct gdsc disp1_mdss_int2_gdsc = {
.name = "disp1_mdss_int2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
- .flags = HW_CTRL,
+ .flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct gdsc *disp0_cc_sc8280xp_gdscs[] = {
diff --git a/drivers/clk/qcom/dispcc-sm6115.c b/drivers/clk/qcom/dispcc-sm6115.c
index 1937edf23f21..1fab43f08e73 100644
--- a/drivers/clk/qcom/dispcc-sm6115.c
+++ b/drivers/clk/qcom/dispcc-sm6115.c
@@ -8,8 +8,8 @@
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/of_device.h>
#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm6115-dispcc.h>
diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c
index adbfd30bfc96..2c4aecd75186 100644
--- a/drivers/clk/qcom/dispcc-sm8450.c
+++ b/drivers/clk/qcom/dispcc-sm8450.c
@@ -9,8 +9,8 @@
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/of_device.h>
#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/pm_runtime.h>
@@ -1776,8 +1776,10 @@ static int disp_cc_sm8450_probe(struct platform_device *pdev)
return ret;
regmap = qcom_cc_map(pdev, &disp_cc_sm8450_desc);
- if (IS_ERR(regmap))
- return PTR_ERR(regmap);
+ if (IS_ERR(regmap)) {
+ ret = PTR_ERR(regmap);
+ goto err_put_rpm;
+ }
clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
@@ -1792,9 +1794,16 @@ static int disp_cc_sm8450_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0xe05c, BIT(0), BIT(0));
ret = qcom_cc_really_probe(pdev, &disp_cc_sm8450_desc, regmap);
+ if (ret)
+ goto err_put_rpm;
pm_runtime_put(&pdev->dev);
+ return 0;
+
+err_put_rpm:
+ pm_runtime_put_sync(&pdev->dev);
+
return ret;
}
diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c
index 1e5a11081860..aefa19f3c2c5 100644
--- a/drivers/clk/qcom/dispcc-sm8550.c
+++ b/drivers/clk/qcom/dispcc-sm8550.c
@@ -9,8 +9,8 @@
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/of_device.h>
#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/pm_runtime.h>
@@ -1761,8 +1761,10 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev)
return ret;
regmap = qcom_cc_map(pdev, &disp_cc_sm8550_desc);
- if (IS_ERR(regmap))
- return PTR_ERR(regmap);
+ if (IS_ERR(regmap)) {
+ ret = PTR_ERR(regmap);
+ goto err_put_rpm;
+ }
clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
@@ -1777,9 +1779,16 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0));
ret = qcom_cc_really_probe(pdev, &disp_cc_sm8550_desc, regmap);
+ if (ret)
+ goto err_put_rpm;
pm_runtime_put(&pdev->dev);
+ return 0;
+
+err_put_rpm:
+ pm_runtime_put_sync(&pdev->dev);
+
return ret;
}
diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
index 7085d2ccae49..c7ca93ef0d53 100644
--- a/drivers/clk/qcom/gcc-apq8084.c
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -9,7 +9,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 5657e29464ad..d38628b52268 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -8,7 +8,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
@@ -1686,6 +1685,12 @@ static const struct qcom_reset_map gcc_ipq4019_resets[] = {
[GCC_TCSR_BCR] = {0x22000, 0},
[GCC_MPM_BCR] = {0x24000, 0},
[GCC_SPDM_BCR] = {0x25000, 0},
+ [ESS_MAC1_ARES] = {0x1200C, 0},
+ [ESS_MAC2_ARES] = {0x1200C, 1},
+ [ESS_MAC3_ARES] = {0x1200C, 2},
+ [ESS_MAC4_ARES] = {0x1200C, 3},
+ [ESS_MAC5_ARES] = {0x1200C, 4},
+ [ESS_PSGMII_ARES] = {0x1200C, 5},
};
static const struct regmap_config gcc_ipq4019_regmap_config = {
diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c
new file mode 100644
index 000000000000..19dc2b71cacf
--- /dev/null
+++ b/drivers/clk/qcom/gcc-ipq5018.c
@@ -0,0 +1,3724 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (c) 2023, The Linux Foundation. All rights reserved.
+ */
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
+#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "clk-regmap-phy-mux.h"
+#include "reset.h"
+
+/* Need to match the order of clocks in DT binding */
+enum {
+ DT_XO,
+ DT_SLEEP_CLK,
+ DT_PCIE20_PHY0_PIPE_CLK,
+ DT_PCIE20_PHY1_PIPE_CLK,
+ DT_USB3_PHY0_CC_PIPE_CLK,
+ DT_GEPHY_RX_CLK,
+ DT_GEPHY_TX_CLK,
+ DT_UNIPHY_RX_CLK,
+ DT_UNIPHY_TX_CLK,
+};
+
+enum {
+ P_XO,
+ P_CORE_PI_SLEEP_CLK,
+ P_PCIE20_PHY0_PIPE,
+ P_PCIE20_PHY1_PIPE,
+ P_USB3PHY_0_PIPE,
+ P_GEPHY_RX,
+ P_GEPHY_TX,
+ P_UNIPHY_RX,
+ P_UNIPHY_TX,
+ P_GPLL0,
+ P_GPLL0_DIV2,
+ P_GPLL2,
+ P_GPLL4,
+ P_UBI32_PLL,
+};
+
+static const struct clk_parent_data gcc_xo_data[] = {
+ { .index = DT_XO },
+};
+
+static const struct clk_parent_data gcc_sleep_clk_data[] = {
+ { .index = DT_SLEEP_CLK },
+};
+
+static struct clk_alpha_pll gpll0_main = {
+ .offset = 0x21000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gpll0_main",
+ .parent_data = gcc_xo_data,
+ .num_parents = ARRAY_SIZE(gcc_xo_data),
+ .ops = &clk_alpha_pll_stromer_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll gpll2_main = {
+ .offset = 0x4a000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(2),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gpll2_main",
+ .parent_data = gcc_xo_data,
+ .num_parents = ARRAY_SIZE(gcc_xo_data),
+ .ops = &clk_alpha_pll_stromer_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll gpll4_main = {
+ .offset = 0x24000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(5),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gpll4_main",
+ .parent_data = gcc_xo_data,
+ .num_parents = ARRAY_SIZE(gcc_xo_data),
+ .ops = &clk_alpha_pll_stromer_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll ubi32_pll_main = {
+ .offset = 0x25000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(6),
+ .hw.init = &(struct clk_init_data) {
+ .name = "ubi32_pll_main",
+ .parent_data = gcc_xo_data,
+ .num_parents = ARRAY_SIZE(gcc_xo_data),
+ .ops = &clk_alpha_pll_stromer_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll0 = {
+ .offset = 0x21000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gpll0",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gpll0_main.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll2 = {
+ .offset = 0x4a000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gpll2",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gpll2_main.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll4 = {
+ .offset = 0x24000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gpll4",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gpll4_main.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_alpha_pll_postdiv ubi32_pll = {
+ .offset = 0x25000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "ubi32_pll",
+ .parent_hws = (const struct clk_hw *[]) {
+ &ubi32_pll_main.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_fixed_factor gpll0_out_main_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data) {
+ .name = "gpll0_out_main_div2",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gpll0_main.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0_out_main_div2.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0_out_main_div2.hw },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0_DIV2, 2 },
+ { P_GPLL0, 1 },
+};
+
+static const struct clk_parent_data gcc_xo_ubi32_gpll0[] = {
+ { .index = DT_XO },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_ubi32_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_UBI32_PLL, 1 },
+ { P_GPLL0, 2 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll2.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL2, 2 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll2.clkr.hw },
+ { .hw = &gpll4.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL2, 2 },
+ { P_GPLL4, 3 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll4.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL4, 2 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 2 },
+ { P_CORE_PI_SLEEP_CLK, 6 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0_out_main_div2.hw },
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_DIV2, 4 },
+ { P_CORE_PI_SLEEP_CLK, 6 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll2.clkr.hw },
+ { .hw = &gpll0_out_main_div2.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL2, 2 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = {
+ { .index = DT_XO },
+ { .hw = &gpll4.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0_out_main_div2.hw },
+};
+
+static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1[] = {
+ { P_XO, 0 },
+ { P_GPLL4, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2[] = {
+ { P_XO, 0 },
+ { P_GPLL4, 1 },
+ { P_GPLL0, 3 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static const struct clk_parent_data gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0[] = {
+ { .index = DT_XO },
+ { .index = DT_GEPHY_RX_CLK },
+ { .index = DT_GEPHY_TX_CLK },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GEPHY_RX, 1 },
+ { P_GEPHY_TX, 2 },
+ { P_UBI32_PLL, 3 },
+ { P_GPLL0, 4 },
+};
+
+static const struct clk_parent_data gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0[] = {
+ { .index = DT_XO },
+ { .index = DT_GEPHY_TX_CLK },
+ { .index = DT_GEPHY_RX_CLK },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GEPHY_TX, 1 },
+ { P_GEPHY_RX, 2 },
+ { P_UBI32_PLL, 3 },
+ { P_GPLL0, 4 },
+};
+
+static const struct clk_parent_data gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = {
+ { .index = DT_XO },
+ { .index = DT_UNIPHY_RX_CLK },
+ { .index = DT_UNIPHY_TX_CLK },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY_RX, 1 },
+ { P_UNIPHY_TX, 2 },
+ { P_UBI32_PLL, 3 },
+ { P_GPLL0, 4 },
+};
+
+static const struct clk_parent_data gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0[] = {
+ { .index = DT_XO },
+ { .index = DT_UNIPHY_TX_CLK },
+ { .index = DT_UNIPHY_RX_CLK },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY_TX, 1 },
+ { P_UNIPHY_RX, 2 },
+ { P_UBI32_PLL, 3 },
+ { P_GPLL0, 4 },
+};
+
+static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
+ { .index = DT_PCIE20_PHY0_PIPE_CLK },
+ { .index = DT_XO },
+};
+
+static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
+ { P_PCIE20_PHY0_PIPE, 0 },
+ { P_XO, 2 },
+};
+
+static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
+ { .index = DT_PCIE20_PHY1_PIPE_CLK },
+ { .index = DT_XO },
+};
+
+static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
+ { P_PCIE20_PHY1_PIPE, 0 },
+ { P_XO, 2 },
+};
+
+static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
+ { .index = DT_USB3_PHY0_CC_PIPE_CLK },
+ { .index = DT_XO },
+};
+
+static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
+ { P_USB3PHY_0_PIPE, 0 },
+ { P_XO, 2 },
+};
+
+static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(100000000, P_GPLL0, 8, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 adss_pwm_clk_src = {
+ .cmd_rcgr = 0x1f008,
+ .freq_tbl = ftbl_adss_pwm_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "adss_pwm_clk_src",
+ .parent_data = gcc_xo_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
+ F(50000000, P_GPLL0, 16, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x0200c,
+ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "blsp1_qup1_i2c_apps_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x03000,
+ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "blsp1_qup2_i2c_apps_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x04000,
+ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "blsp1_qup3_i2c_apps_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 2, 5),
+ F(4800000, P_XO, 5, 0, 0),
+ F(9600000, P_XO, 2, 4, 5),
+ F(16000000, P_GPLL0, 10, 1, 5),
+ F(24000000, P_XO, 1, 0, 0),
+ F(50000000, P_GPLL0, 16, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
+ .cmd_rcgr = 0x02024,
+ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "blsp1_qup1_spi_apps_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
+ .cmd_rcgr = 0x03014,
+ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "blsp1_qup2_spi_apps_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
+ .cmd_rcgr = 0x04014,
+ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "blsp1_qup3_spi_apps_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
+ F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
+ F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
+ F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
+ F(24000000, P_XO, 1, 0, 0),
+ F(25000000, P_GPLL0, 16, 1, 2),
+ F(40000000, P_GPLL0, 1, 1, 20),
+ F(46400000, P_GPLL0, 1, 29, 500),
+ F(48000000, P_GPLL0, 1, 3, 50),
+ F(51200000, P_GPLL0, 1, 8, 125),
+ F(56000000, P_GPLL0, 1, 7, 100),
+ F(58982400, P_GPLL0, 1, 1152, 15625),
+ F(60000000, P_GPLL0, 1, 3, 40),
+ F(64000000, P_GPLL0, 10, 4, 5),
+ { }
+};
+
+static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
+ .cmd_rcgr = 0x02044,
+ .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "blsp1_uart1_apps_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
+ .cmd_rcgr = 0x03034,
+ .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "blsp1_uart2_apps_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_crypto_clk_src[] = {
+ F(160000000, P_GPLL0, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 crypto_clk_src = {
+ .cmd_rcgr = 0x16004,
+ .freq_tbl = ftbl_crypto_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "crypto_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gmac0_tx_clk_src[] = {
+ F(2500000, P_GEPHY_TX, 5, 0, 0),
+ F(24000000, P_XO, 1, 0, 0),
+ F(25000000, P_GEPHY_TX, 5, 0, 0),
+ F(125000000, P_GEPHY_TX, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gmac0_rx_clk_src = {
+ .cmd_rcgr = 0x68020,
+ .parent_map = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map,
+ .hid_width = 5,
+ .freq_tbl = ftbl_gmac0_tx_clk_src,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gmac0_rx_clk_src",
+ .parent_data = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div gmac0_rx_div_clk_src = {
+ .reg = 0x68420,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data) {
+ .name = "gmac0_rx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac0_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 gmac0_tx_clk_src = {
+ .cmd_rcgr = 0x68028,
+ .parent_map = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map,
+ .hid_width = 5,
+ .freq_tbl = ftbl_gmac0_tx_clk_src,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gmac0_tx_clk_src",
+ .parent_data = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div gmac0_tx_div_clk_src = {
+ .reg = 0x68424,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data) {
+ .name = "gmac0_tx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac0_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_gmac1_rx_clk_src[] = {
+ F(2500000, P_UNIPHY_RX, 12.5, 0, 0),
+ F(24000000, P_XO, 1, 0, 0),
+ F(25000000, P_UNIPHY_RX, 2.5, 0, 0),
+ F(125000000, P_UNIPHY_RX, 2.5, 0, 0),
+ F(125000000, P_UNIPHY_RX, 1, 0, 0),
+ F(312500000, P_UNIPHY_RX, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gmac1_rx_clk_src = {
+ .cmd_rcgr = 0x68030,
+ .parent_map = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map,
+ .hid_width = 5,
+ .freq_tbl = ftbl_gmac1_rx_clk_src,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gmac1_rx_clk_src",
+ .parent_data = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div gmac1_rx_div_clk_src = {
+ .reg = 0x68430,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data) {
+ .name = "gmac1_rx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac1_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_gmac1_tx_clk_src[] = {
+ F(2500000, P_UNIPHY_TX, 12.5, 0, 0),
+ F(24000000, P_XO, 1, 0, 0),
+ F(25000000, P_UNIPHY_TX, 2.5, 0, 0),
+ F(125000000, P_UNIPHY_TX, 2.5, 0, 0),
+ F(125000000, P_UNIPHY_TX, 1, 0, 0),
+ F(312500000, P_UNIPHY_TX, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gmac1_tx_clk_src = {
+ .cmd_rcgr = 0x68038,
+ .parent_map = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map,
+ .hid_width = 5,
+ .freq_tbl = ftbl_gmac1_tx_clk_src,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gmac1_tx_clk_src",
+ .parent_data = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div gmac1_tx_div_clk_src = {
+ .reg = 0x68434,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data) {
+ .name = "gmac1_tx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac1_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_gmac_clk_src[] = {
+ F(240000000, P_GPLL4, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gmac_clk_src = {
+ .cmd_rcgr = 0x68080,
+ .parent_map = gcc_xo_gpll0_gpll4_map,
+ .hid_width = 5,
+ .freq_tbl = ftbl_gmac_clk_src,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gmac_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gp_clk_src[] = {
+ F(200000000, P_GPLL0, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gp1_clk_src = {
+ .cmd_rcgr = 0x08004,
+ .freq_tbl = ftbl_gp_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gp1_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gp2_clk_src = {
+ .cmd_rcgr = 0x09004,
+ .freq_tbl = ftbl_gp_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gp2_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gp3_clk_src = {
+ .cmd_rcgr = 0x0a004,
+ .freq_tbl = ftbl_gp_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "gp3_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {
+ F(133333334, P_GPLL0, 6, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 lpass_axim_clk_src = {
+ .cmd_rcgr = 0x2e028,
+ .freq_tbl = ftbl_lpass_axim_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "lpass_axim_clk_src",
+ .parent_data = gcc_xo_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_lpass_sway_clk_src[] = {
+ F(66666667, P_GPLL0, 12, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 lpass_sway_clk_src = {
+ .cmd_rcgr = 0x2e040,
+ .freq_tbl = ftbl_lpass_sway_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "lpass_sway_clk_src",
+ .parent_data = gcc_xo_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_pcie0_aux_clk_src[] = {
+ F(2000000, P_XO, 12, 0, 0),
+};
+
+static struct clk_rcg2 pcie0_aux_clk_src = {
+ .cmd_rcgr = 0x75020,
+ .freq_tbl = ftbl_pcie0_aux_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "pcie0_aux_clk_src",
+ .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_pcie0_axi_clk_src[] = {
+ F(240000000, P_GPLL4, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 pcie0_axi_clk_src = {
+ .cmd_rcgr = 0x75050,
+ .freq_tbl = ftbl_pcie0_axi_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll4_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "pcie0_axi_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 pcie1_aux_clk_src = {
+ .cmd_rcgr = 0x76020,
+ .freq_tbl = ftbl_pcie0_aux_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "pcie1_aux_clk_src",
+ .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 pcie1_axi_clk_src = {
+ .cmd_rcgr = 0x76050,
+ .freq_tbl = ftbl_gp_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "pcie1_axi_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_mux pcie0_pipe_clk_src = {
+ .reg = 0x7501c,
+ .shift = 8,
+ .width = 2,
+ .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
+ .clkr = {
+ .hw.init = &(struct clk_init_data) {
+ .name = "pcie0_pipe_clk_src",
+ .parent_data = gcc_pcie20_phy0_pipe_clk_xo,
+ .num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_regmap_mux pcie1_pipe_clk_src = {
+ .reg = 0x7601c,
+ .shift = 8,
+ .width = 2,
+ .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map, .clkr = {
+ .hw.init = &(struct clk_init_data) {
+ .name = "pcie1_pipe_clk_src",
+ .parent_data = gcc_pcie20_phy1_pipe_clk_xo,
+ .num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
+ F(100000000, P_GPLL0, 8, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
+ .cmd_rcgr = 0x27000,
+ .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "pcnoc_bfdcd_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_fixed_factor pcnoc_clk_src = {
+ .mult = 1,
+ .div = 1,
+ .hw.init = &(struct clk_init_data) {
+ .name = "pcnoc_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
+ F(240000000, P_GPLL4, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 qdss_at_clk_src = {
+ .cmd_rcgr = 0x2900c,
+ .freq_tbl = ftbl_qdss_at_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "qdss_at_clk_src",
+ .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
+ F(200000000, P_GPLL0, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 qdss_stm_clk_src = {
+ .cmd_rcgr = 0x2902c,
+ .freq_tbl = ftbl_qdss_stm_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "qdss_stm_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
+ F(266666667, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 qdss_traceclkin_clk_src = {
+ .cmd_rcgr = 0x29048,
+ .freq_tbl = ftbl_qdss_traceclkin_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "qdss_traceclkin_clk_src",
+ .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
+ F(600000000, P_GPLL4, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 qdss_tsctr_clk_src = {
+ .cmd_rcgr = 0x29064,
+ .freq_tbl = ftbl_qdss_tsctr_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "qdss_tsctr_clk_src",
+ .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data) {
+ .name = "qdss_tsctr_div2_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_tsctr_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_fixed_factor qdss_dap_sync_clk_src = {
+ .mult = 1,
+ .div = 4,
+ .hw.init = &(struct clk_init_data) {
+ .name = "qdss_dap_sync_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_tsctr_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_fixed_factor eud_at_clk_src = {
+ .mult = 1,
+ .div = 6,
+ .hw.init = &(struct clk_init_data) {
+ .name = "eud_at_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_at_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(100000000, P_GPLL0, 8, 0, 0),
+ F(200000000, P_GPLL0, 4, 0, 0),
+ F(320000000, P_GPLL0, 2.5, 0, 0),
+};
+
+static struct clk_rcg2 qpic_io_macro_clk_src = {
+ .cmd_rcgr = 0x57010,
+ .freq_tbl = ftbl_qpic_io_macro_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "qpic_io_macro_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
+ F(143713, P_XO, 1, 1, 167),
+ F(400000, P_XO, 1, 1, 60),
+ F(24000000, P_XO, 1, 0, 0),
+ F(48000000, P_GPLL2, 12, 1, 2),
+ F(96000000, P_GPLL2, 12, 0, 0),
+ F(177777778, P_GPLL0, 1, 2, 9),
+ F(192000000, P_GPLL2, 6, 0, 0),
+ F(200000000, P_GPLL0, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc1_apps_clk_src = {
+ .cmd_rcgr = 0x42004,
+ .freq_tbl = ftbl_sdcc1_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "sdcc1_apps_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
+ .ops = &clk_rcg2_floor_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
+ F(266666667, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 system_noc_bfdcd_clk_src = {
+ .cmd_rcgr = 0x26004,
+ .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "system_noc_bfdcd_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_fixed_factor system_noc_clk_src = {
+ .mult = 1,
+ .div = 1,
+ .hw.init = &(struct clk_init_data) {
+ .name = "system_noc_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &system_noc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
+ F(400000000, P_GPLL0, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ubi0_axi_clk_src = {
+ .cmd_rcgr = 0x68088,
+ .freq_tbl = ftbl_apss_axi_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll2_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "ubi0_axi_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct freq_tbl ftbl_ubi0_core_clk_src[] = {
+ F(850000000, P_UBI32_PLL, 1, 0, 0),
+ F(1000000000, P_UBI32_PLL, 1, 0, 0),
+};
+
+static struct clk_rcg2 ubi0_core_clk_src = {
+ .cmd_rcgr = 0x68100,
+ .freq_tbl = ftbl_ubi0_core_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_ubi32_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "ubi0_core_clk_src",
+ .parent_data = gcc_xo_ubi32_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_ubi32_gpll0),
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_rcg2 usb0_aux_clk_src = {
+ .cmd_rcgr = 0x3e05c,
+ .freq_tbl = ftbl_pcie0_aux_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "usb0_aux_clk_src",
+ .parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb0_lfps_clk_src[] = {
+ F(25000000, P_GPLL0, 16, 1, 2),
+ { }
+};
+
+static struct clk_rcg2 usb0_lfps_clk_src = {
+ .cmd_rcgr = 0x3e090,
+ .freq_tbl = ftbl_usb0_lfps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "usb0_lfps_clk_src",
+ .parent_data = gcc_xo_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 usb0_master_clk_src = {
+ .cmd_rcgr = 0x3e00c,
+ .freq_tbl = ftbl_gp_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "usb0_master_clk_src",
+ .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = {
+ F(60000000, P_GPLL4, 10, 1, 2),
+ { }
+};
+
+static struct clk_rcg2 usb0_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x3e020,
+ .freq_tbl = ftbl_usb0_mock_utmi_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "usb0_mock_utmi_clk_src",
+ .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_mux usb0_pipe_clk_src = {
+ .reg = 0x3e048,
+ .shift = 8,
+ .width = 2,
+ .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
+ .clkr = {
+ .hw.init = &(struct clk_init_data) {
+ .name = "usb0_pipe_clk_src",
+ .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
+ .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
+ F(400000000, P_GPLL0, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 q6_axi_clk_src = {
+ .cmd_rcgr = 0x59120,
+ .freq_tbl = ftbl_q6_axi_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll2_gpll4_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "q6_axi_clk_src",
+ .parent_data = gcc_xo_gpll0_gpll2_gpll4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
+ F(133333333, P_GPLL0, 6, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 wcss_ahb_clk_src = {
+ .cmd_rcgr = 0x59020,
+ .freq_tbl = ftbl_wcss_ahb_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "wcss_ahb_clk_src",
+ .parent_data = gcc_xo_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch gcc_sleep_clk_src = {
+ .halt_reg = 0x30000,
+ .clkr = {
+ .enable_reg = 0x30000,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_sleep_clk_src",
+ .parent_data = gcc_sleep_clk_data,
+ .num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_xo_clk_src = {
+ .halt_reg = 0x30018,
+ .clkr = {
+ .enable_reg = 0x30018,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_xo_clk_src",
+ .parent_data = gcc_xo_data,
+ .num_parents = ARRAY_SIZE(gcc_xo_data),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_xo_clk = {
+ .halt_reg = 0x30030,
+ .clkr = {
+ .enable_reg = 0x30030,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_xo_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_adss_pwm_clk = {
+ .halt_reg = 0x1f020,
+ .clkr = {
+ .enable_reg = 0x1f020,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_adss_pwm_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &adss_pwm_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_ahb_clk = {
+ .halt_reg = 0x01008,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x0b004,
+ .enable_mask = BIT(10),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_blsp1_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
+ .halt_reg = 0x02008,
+ .clkr = {
+ .enable_reg = 0x02008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_blsp1_qup1_i2c_apps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
+ .halt_reg = 0x02004,
+ .clkr = {
+ .enable_reg = 0x02004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_blsp1_qup1_spi_apps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &blsp1_qup1_spi_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
+ .halt_reg = 0x03010,
+ .clkr = {
+ .enable_reg = 0x03010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_blsp1_qup2_i2c_apps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
+ .halt_reg = 0x0300c,
+ .clkr = {
+ .enable_reg = 0x0300c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_blsp1_qup2_spi_apps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &blsp1_qup2_spi_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
+ .halt_reg = 0x04010,
+ .clkr = {
+ .enable_reg = 0x04010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_blsp1_qup3_i2c_apps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
+ .halt_reg = 0x0400c,
+ .clkr = {
+ .enable_reg = 0x0400c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_blsp1_qup3_spi_apps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &blsp1_qup3_spi_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart1_apps_clk = {
+ .halt_reg = 0x0203c,
+ .clkr = {
+ .enable_reg = 0x0203c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_blsp1_uart1_apps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &blsp1_uart1_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart2_apps_clk = {
+ .halt_reg = 0x0302c,
+ .clkr = {
+ .enable_reg = 0x0302c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_blsp1_uart2_apps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &blsp1_uart2_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_btss_lpo_clk = {
+ .halt_reg = 0x1c004,
+ .clkr = {
+ .enable_reg = 0x1c004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_btss_lpo_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cmn_blk_ahb_clk = {
+ .halt_reg = 0x56308,
+ .clkr = {
+ .enable_reg = 0x56308,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_cmn_blk_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cmn_blk_sys_clk = {
+ .halt_reg = 0x5630c,
+ .clkr = {
+ .enable_reg = 0x5630c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_cmn_blk_sys_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_crypto_ahb_clk = {
+ .halt_reg = 0x16024,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x0b004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_crypto_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_crypto_axi_clk = {
+ .halt_reg = 0x16020,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x0b004,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_crypto_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_crypto_clk = {
+ .halt_reg = 0x1601c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x0b004,
+ .enable_mask = BIT(2),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_crypto_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &crypto_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_dcc_clk = {
+ .halt_reg = 0x77004,
+ .clkr = {
+ .enable_reg = 0x77004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_dcc_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gephy_rx_clk = {
+ .halt_reg = 0x56010,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x56010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gephy_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac0_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_branch gcc_gephy_tx_clk = {
+ .halt_reg = 0x56014,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x56014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gephy_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac0_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac0_cfg_clk = {
+ .halt_reg = 0x68304,
+ .clkr = {
+ .enable_reg = 0x68304,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac0_cfg_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac0_ptp_clk = {
+ .halt_reg = 0x68300,
+ .clkr = {
+ .enable_reg = 0x68300,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac0_ptp_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac0_rx_clk = {
+ .halt_reg = 0x68240,
+ .clkr = {
+ .enable_reg = 0x68240,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac0_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac0_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac0_sys_clk = {
+ .halt_reg = 0x68190,
+ .halt_check = BRANCH_HALT_DELAY,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x683190,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac0_sys_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac0_tx_clk = {
+ .halt_reg = 0x68244,
+ .clkr = {
+ .enable_reg = 0x68244,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac0_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac0_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac1_cfg_clk = {
+ .halt_reg = 0x68324,
+ .clkr = {
+ .enable_reg = 0x68324,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac1_cfg_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac1_ptp_clk = {
+ .halt_reg = 0x68320,
+ .clkr = {
+ .enable_reg = 0x68320,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac1_ptp_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac1_rx_clk = {
+ .halt_reg = 0x68248,
+ .clkr = {
+ .enable_reg = 0x68248,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac1_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac1_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac1_sys_clk = {
+ .halt_reg = 0x68310,
+ .clkr = {
+ .enable_reg = 0x68310,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac1_sys_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gmac1_tx_clk = {
+ .halt_reg = 0x6824c,
+ .clkr = {
+ .enable_reg = 0x6824c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gmac1_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac1_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+ .halt_reg = 0x08000,
+ .clkr = {
+ .enable_reg = 0x08000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gp1_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gp1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+ .halt_reg = 0x09000,
+ .clkr = {
+ .enable_reg = 0x09000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gp2_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gp2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp3_clk = {
+ .halt_reg = 0x0a000,
+ .clkr = {
+ .enable_reg = 0x0a000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_gp3_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gp3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_lpass_core_axim_clk = {
+ .halt_reg = 0x2e048,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x2e048,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_lpass_core_axim_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &lpass_axim_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_lpass_sway_clk = {
+ .halt_reg = 0x2e04c,
+ .clkr = {
+ .enable_reg = 0x2e04c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_lpass_sway_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &lpass_sway_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mdio0_ahb_clk = {
+ .halt_reg = 0x58004,
+ .clkr = {
+ .enable_reg = 0x58004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_mdioi0_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mdio1_ahb_clk = {
+ .halt_reg = 0x58014,
+ .clkr = {
+ .enable_reg = 0x58014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_mdio1_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_ahb_clk = {
+ .halt_reg = 0x75010,
+ .clkr = {
+ .enable_reg = 0x75010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie0_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_aux_clk = {
+ .halt_reg = 0x75014,
+ .clkr = {
+ .enable_reg = 0x75014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie0_aux_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie0_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_axi_m_clk = {
+ .halt_reg = 0x75008,
+ .clkr = {
+ .enable_reg = 0x75008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie0_axi_m_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie0_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
+ .halt_reg = 0x75048,
+ .clkr = {
+ .enable_reg = 0x75048,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie0_axi_s_bridge_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie0_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_axi_s_clk = {
+ .halt_reg = 0x7500c,
+ .clkr = {
+ .enable_reg = 0x7500c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie0_axi_s_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie0_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_pipe_clk = {
+ .halt_reg = 0x75018,
+ .halt_check = BRANCH_HALT_DELAY,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x75018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie0_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie0_pipe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_ahb_clk = {
+ .halt_reg = 0x76010,
+ .clkr = {
+ .enable_reg = 0x76010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie1_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_aux_clk = {
+ .halt_reg = 0x76014,
+ .clkr = {
+ .enable_reg = 0x76014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie1_aux_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie1_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_axi_m_clk = {
+ .halt_reg = 0x76008,
+ .clkr = {
+ .enable_reg = 0x76008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie1_axi_m_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie1_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {
+ .halt_reg = 0x76048,
+ .clkr = {
+ .enable_reg = 0x76048,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie1_axi_s_bridge_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie1_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_axi_s_clk = {
+ .halt_reg = 0x7600c,
+ .clkr = {
+ .enable_reg = 0x7600c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie1_axi_s_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie1_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_pipe_clk = {
+ .halt_reg = 8,
+ .halt_check = BRANCH_HALT_DELAY,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x76018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie1_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie1_pipe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+ .halt_reg = 0x13004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x0b004,
+ .enable_mask = BIT(8),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_prng_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6_ahb_clk = {
+ .halt_reg = 0x59138,
+ .clkr = {
+ .enable_reg = 0x59138,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_q6_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &wcss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6_ahb_s_clk = {
+ .halt_reg = 0x5914c,
+ .clkr = {
+ .enable_reg = 0x5914c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_q6_ahb_s_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &wcss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6_axim_clk = {
+ .halt_reg = 0x5913c,
+ .clkr = {
+ .enable_reg = 0x5913c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_q6_axim_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &q6_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6_axim2_clk = {
+ .halt_reg = 0x59150,
+ .clkr = {
+ .enable_reg = 0x59150,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_q6_axim2_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &q6_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6_axis_clk = {
+ .halt_reg = 0x59154,
+ .clkr = {
+ .enable_reg = 0x59154,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_q6_axis_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &system_noc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6_tsctr_1to2_clk = {
+ .halt_reg = 0x59148,
+ .clkr = {
+ .enable_reg = 0x59148,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_q6_tsctr_1to2_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_tsctr_div2_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6ss_atbm_clk = {
+ .halt_reg = 0x59144,
+ .clkr = {
+ .enable_reg = 0x59144,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_q6ss_atbm_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_at_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6ss_pclkdbg_clk = {
+ .halt_reg = 0x59140,
+ .clkr = {
+ .enable_reg = 0x59140,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_q6ss_pclkdbg_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_dap_sync_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6ss_trig_clk = {
+ .halt_reg = 0x59128,
+ .clkr = {
+ .enable_reg = 0x59128,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_q6ss_trig_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_dap_sync_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_at_clk = {
+ .halt_reg = 0x29024,
+ .clkr = {
+ .enable_reg = 0x29024,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qdss_at_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_at_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_dap_clk = {
+ .halt_reg = 0x29084,
+ .clkr = {
+ .enable_reg = 0x29084,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qdss_dap_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_tsctr_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_cfg_ahb_clk = {
+ .halt_reg = 0x29008,
+ .clkr = {
+ .enable_reg = 0x29008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qdss_cfg_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_dap_ahb_clk = {
+ .halt_reg = 0x29004,
+ .clkr = {
+ .enable_reg = 0x29004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qdss_dap_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_etr_usb_clk = {
+ .halt_reg = 0x29028,
+ .clkr = {
+ .enable_reg = 0x29028,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qdss_etr_usb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &system_noc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_eud_at_clk = {
+ .halt_reg = 0x29020,
+ .clkr = {
+ .enable_reg = 0x29020,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qdss_eud_at_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &eud_at_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_stm_clk = {
+ .halt_reg = 0x29044,
+ .clkr = {
+ .enable_reg = 0x29044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qdss_stm_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_stm_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_traceclkin_clk = {
+ .halt_reg = 0x29060,
+ .clkr = {
+ .enable_reg = 0x29060,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qdss_traceclkin_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_traceclkin_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_tsctr_div8_clk = {
+ .halt_reg = 0x2908c,
+ .clkr = {
+ .enable_reg = 0x2908c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qdss_tsctr_div8_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_tsctr_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qpic_ahb_clk = {
+ .halt_reg = 0x57024,
+ .clkr = {
+ .enable_reg = 0x57024,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qpic_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qpic_clk = {
+ .halt_reg = 0x57020,
+ .clkr = {
+ .enable_reg = 0x57020,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qpic_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qpic_io_macro_clk = {
+ .halt_reg = 0x5701c,
+ .clkr = {
+ .enable_reg = 0x5701c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_qpic_io_macro_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qpic_io_macro_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ahb_clk = {
+ .halt_reg = 0x4201c,
+ .clkr = {
+ .enable_reg = 0x4201c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_sdcc1_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_apps_clk = {
+ .halt_reg = 0x42018,
+ .clkr = {
+ .enable_reg = 0x42018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_sdcc1_apps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &sdcc1_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_gmac0_ahb_clk = {
+ .halt_reg = 0x260a0,
+ .clkr = {
+ .enable_reg = 0x260a0,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_snoc_gmac0_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_gmac0_axi_clk = {
+ .halt_reg = 0x26084,
+ .clkr = {
+ .enable_reg = 0x26084,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_snoc_gmac0_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_gmac1_ahb_clk = {
+ .halt_reg = 0x260a4,
+ .clkr = {
+ .enable_reg = 0x260a4,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_snoc_gmac1_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_gmac1_axi_clk = {
+ .halt_reg = 0x26088,
+ .clkr = {
+ .enable_reg = 0x26088,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_snoc_gmac1_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_lpass_axim_clk = {
+ .halt_reg = 0x26074,
+ .clkr = {
+ .enable_reg = 0x26074,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_snoc_lpass_axim_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &lpass_axim_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_lpass_sway_clk = {
+ .halt_reg = 0x26078,
+ .clkr = {
+ .enable_reg = 0x26078,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_snoc_lpass_sway_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &lpass_sway_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_ubi0_axi_clk = {
+ .halt_reg = 0x26094,
+ .clkr = {
+ .enable_reg = 0x26094,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_snoc_ubi0_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &ubi0_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
+ .halt_reg = 0x26048,
+ .clkr = {
+ .enable_reg = 0x26048,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_sys_noc_pcie0_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie0_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
+ .halt_reg = 0x2604c,
+ .clkr = {
+ .enable_reg = 0x2604c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_sys_noc_pcie1_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie1_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {
+ .halt_reg = 0x26024,
+ .clkr = {
+ .enable_reg = 0x26024,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_sys_noc_qdss_stm_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_stm_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
+ .halt_reg = 0x26040,
+ .clkr = {
+ .enable_reg = 0x26040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_sys_noc_usb0_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &usb0_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
+ .halt_reg = 0x26034,
+ .clkr = {
+ .enable_reg = 0x26034,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_sys_noc_wcss_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &wcss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_axi_clk = {
+ .halt_reg = 0x68200,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x68200,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_ubi0_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &ubi0_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_cfg_clk = {
+ .halt_reg = 0x68160,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x68160,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_ubi0_cfg_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_dbg_clk = {
+ .halt_reg = 0x68214,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x68214,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_ubi0_dbg_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_tsctr_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_core_clk = {
+ .halt_reg = 0x68210,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x68210,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_ubi0_core_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &ubi0_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_nc_axi_clk = {
+ .halt_reg = 0x68204,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x68204,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_ubi0_nc_axi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &system_noc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_utcm_clk = {
+ .halt_reg = 0x68208,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x68208,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_ubi0_utcm_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &system_noc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy_ahb_clk = {
+ .halt_reg = 0x56108,
+ .clkr = {
+ .enable_reg = 0x56108,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_uniphy_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy_rx_clk = {
+ .halt_reg = 0x56110,
+ .clkr = {
+ .enable_reg = 0x56110,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_uniphy_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac1_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy_tx_clk = {
+ .halt_reg = 0x56114,
+ .clkr = {
+ .enable_reg = 0x56114,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_uniphy_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gmac1_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy_sys_clk = {
+ .halt_reg = 0x5610c,
+ .clkr = {
+ .enable_reg = 0x5610c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_uniphy_sys_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_aux_clk = {
+ .halt_reg = 0x3e044,
+ .clkr = {
+ .enable_reg = 0x3e044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_usb0_aux_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &usb0_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_eud_at_clk = {
+ .halt_reg = 0x3e04c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x3e04c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_usb0_eud_at_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &eud_at_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_lfps_clk = {
+ .halt_reg = 0x3e050,
+ .clkr = {
+ .enable_reg = 0x3e050,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_usb0_lfps_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &usb0_lfps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_master_clk = {
+ .halt_reg = 0x3e000,
+ .clkr = {
+ .enable_reg = 0x3e000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_usb0_master_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &usb0_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_mock_utmi_clk = {
+ .halt_reg = 0x3e008,
+ .clkr = {
+ .enable_reg = 0x3e008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_usb0_mock_utmi_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &usb0_mock_utmi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
+ .halt_reg = 0x3e080,
+ .clkr = {
+ .enable_reg = 0x3e080,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_usb0_phy_cfg_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcnoc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_sleep_clk = {
+ .halt_reg = 0x3e004,
+ .clkr = {
+ .enable_reg = 0x3e004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_usb0_sleep_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_sleep_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_pipe_clk = {
+ .halt_reg = 0x3e040,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x3e040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_usb0_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &usb0_pipe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_acmt_clk = {
+ .halt_reg = 0x59064,
+ .clkr = {
+ .enable_reg = 0x59064,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_acmt_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &wcss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_ahb_s_clk = {
+ .halt_reg = 0x59034,
+ .clkr = {
+ .enable_reg = 0x59034,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_ahb_s_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &wcss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_axi_m_clk = {
+ .halt_reg = 0x5903c,
+ .clkr = {
+ .enable_reg = 0x5903c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_axi_m_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &system_noc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_axi_s_clk = {
+ .halt_reg = 0x59068,
+ .clkr = {
+ .enable_reg = 0x59068,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wi_s_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &system_noc_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = {
+ .halt_reg = 0x59050,
+ .clkr = {
+ .enable_reg = 0x59050,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_dbg_ifc_apb_bdg_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_dap_sync_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
+ .halt_reg = 0x59040,
+ .clkr = {
+ .enable_reg = 0x59040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_dbg_ifc_apb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_dap_sync_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = {
+ .halt_reg = 0x59054,
+ .clkr = {
+ .enable_reg = 0x59054,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_dbg_ifc_atb_bdg_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_at_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
+ .halt_reg = 0x59044,
+ .clkr = {
+ .enable_reg = 0x59044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_dbg_ifc_atb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_at_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_dapbus_bdg_clk = {
+ .halt_reg = 0x59060,
+ .clkr = {
+ .enable_reg = 0x59060,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_dbg_ifc_dapbus_bdg_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_dap_sync_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {
+ .halt_reg = 0x5905c,
+ .clkr = {
+ .enable_reg = 0x5905c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_dbg_ifc_dapbus_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_dap_sync_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = {
+ .halt_reg = 0x59058,
+ .clkr = {
+ .enable_reg = 0x59058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_dbg_ifc_nts_bdg_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_tsctr_div2_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
+ .halt_reg = 0x59048,
+ .clkr = {
+ .enable_reg = 0x59048,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_dbg_ifc_nts_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &qdss_tsctr_div2_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_ecahb_clk = {
+ .halt_reg = 0x59038,
+ .clkr = {
+ .enable_reg = 0x59038,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_wcss_ecahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &wcss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_hw *gcc_ipq5018_hws[] = {
+ &gpll0_out_main_div2.hw,
+ &pcnoc_clk_src.hw,
+ &system_noc_clk_src.hw,
+ &qdss_dap_sync_clk_src.hw,
+ &qdss_tsctr_div2_clk_src.hw,
+ &eud_at_clk_src.hw,
+};
+
+static const struct alpha_pll_config ubi32_pll_config = {
+ .l = 0x29,
+ .alpha = 0xaaaaaaaa,
+ .alpha_hi = 0xaa,
+ .config_ctl_val = 0x4001075b,
+ .main_output_mask = BIT(0),
+ .aux_output_mask = BIT(1),
+ .alpha_en_mask = BIT(24),
+ .vco_val = 0x1,
+ .vco_mask = GENMASK(21, 20),
+ .test_ctl_val = 0x0,
+ .test_ctl_hi_val = 0x0,
+};
+
+static struct clk_regmap *gcc_ipq5018_clks[] = {
+ [GPLL0_MAIN] = &gpll0_main.clkr,
+ [GPLL0] = &gpll0.clkr,
+ [GPLL2_MAIN] = &gpll2_main.clkr,
+ [GPLL2] = &gpll2.clkr,
+ [GPLL4_MAIN] = &gpll4_main.clkr,
+ [GPLL4] = &gpll4.clkr,
+ [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
+ [UBI32_PLL] = &ubi32_pll.clkr,
+ [ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
+ [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
+ [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
+ [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
+ [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
+ [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
+ [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
+ [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
+ [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
+ [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
+ [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
+ [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
+ [GCC_BTSS_LPO_CLK] = &gcc_btss_lpo_clk.clkr,
+ [GCC_CMN_BLK_AHB_CLK] = &gcc_cmn_blk_ahb_clk.clkr,
+ [GCC_CMN_BLK_SYS_CLK] = &gcc_cmn_blk_sys_clk.clkr,
+ [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
+ [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
+ [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
+ [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
+ [GCC_GEPHY_RX_CLK] = &gcc_gephy_rx_clk.clkr,
+ [GCC_GEPHY_TX_CLK] = &gcc_gephy_tx_clk.clkr,
+ [GCC_GMAC0_CFG_CLK] = &gcc_gmac0_cfg_clk.clkr,
+ [GCC_GMAC0_PTP_CLK] = &gcc_gmac0_ptp_clk.clkr,
+ [GCC_GMAC0_RX_CLK] = &gcc_gmac0_rx_clk.clkr,
+ [GCC_GMAC0_SYS_CLK] = &gcc_gmac0_sys_clk.clkr,
+ [GCC_GMAC0_TX_CLK] = &gcc_gmac0_tx_clk.clkr,
+ [GCC_GMAC1_CFG_CLK] = &gcc_gmac1_cfg_clk.clkr,
+ [GCC_GMAC1_PTP_CLK] = &gcc_gmac1_ptp_clk.clkr,
+ [GCC_GMAC1_RX_CLK] = &gcc_gmac1_rx_clk.clkr,
+ [GCC_GMAC1_SYS_CLK] = &gcc_gmac1_sys_clk.clkr,
+ [GCC_GMAC1_TX_CLK] = &gcc_gmac1_tx_clk.clkr,
+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+ [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+ [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
+ [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
+ [GCC_MDIO0_AHB_CLK] = &gcc_mdio0_ahb_clk.clkr,
+ [GCC_MDIO1_AHB_CLK] = &gcc_mdio1_ahb_clk.clkr,
+ [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
+ [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
+ [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
+ [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
+ [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
+ [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
+ [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
+ [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
+ [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
+ [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
+ [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+ [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
+ [GCC_Q6_AXIM2_CLK] = &gcc_q6_axim2_clk.clkr,
+ [GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr,
+ [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
+ [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
+ [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
+ [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
+ [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
+ [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
+ [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
+ [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
+ [GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
+ [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
+ [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
+ [GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
+ [GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,
+ [GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,
+ [GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,
+ [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
+ [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
+ [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
+ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
+ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
+ [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
+ [GCC_SNOC_GMAC0_AHB_CLK] = &gcc_snoc_gmac0_ahb_clk.clkr,
+ [GCC_SNOC_GMAC0_AXI_CLK] = &gcc_snoc_gmac0_axi_clk.clkr,
+ [GCC_SNOC_GMAC1_AHB_CLK] = &gcc_snoc_gmac1_ahb_clk.clkr,
+ [GCC_SNOC_GMAC1_AXI_CLK] = &gcc_snoc_gmac1_axi_clk.clkr,
+ [GCC_SNOC_LPASS_AXIM_CLK] = &gcc_snoc_lpass_axim_clk.clkr,
+ [GCC_SNOC_LPASS_SWAY_CLK] = &gcc_snoc_lpass_sway_clk.clkr,
+ [GCC_SNOC_UBI0_AXI_CLK] = &gcc_snoc_ubi0_axi_clk.clkr,
+ [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
+ [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
+ [GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,
+ [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
+ [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
+ [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
+ [GCC_UBI0_CFG_CLK] = &gcc_ubi0_cfg_clk.clkr,
+ [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
+ [GCC_UBI0_DBG_CLK] = &gcc_ubi0_dbg_clk.clkr,
+ [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
+ [GCC_UBI0_UTCM_CLK] = &gcc_ubi0_utcm_clk.clkr,
+ [GCC_UNIPHY_AHB_CLK] = &gcc_uniphy_ahb_clk.clkr,
+ [GCC_UNIPHY_RX_CLK] = &gcc_uniphy_rx_clk.clkr,
+ [GCC_UNIPHY_SYS_CLK] = &gcc_uniphy_sys_clk.clkr,
+ [GCC_UNIPHY_TX_CLK] = &gcc_uniphy_tx_clk.clkr,
+ [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
+ [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
+ [GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr,
+ [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
+ [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
+ [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
+ [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
+ [GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,
+ [GCC_WCSS_AHB_S_CLK] = &gcc_wcss_ahb_s_clk.clkr,
+ [GCC_WCSS_AXI_M_CLK] = &gcc_wcss_axi_m_clk.clkr,
+ [GCC_WCSS_AXI_S_CLK] = &gcc_wcss_axi_s_clk.clkr,
+ [GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr,
+ [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
+ [GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr,
+ [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
+ [GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK] = &gcc_wcss_dbg_ifc_dapbus_bdg_clk.clkr,
+ [GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,
+ [GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr,
+ [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
+ [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
+ [GCC_XO_CLK] = &gcc_xo_clk.clkr,
+ [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
+ [GMAC0_RX_CLK_SRC] = &gmac0_rx_clk_src.clkr,
+ [GMAC0_RX_DIV_CLK_SRC] = &gmac0_rx_div_clk_src.clkr,
+ [GMAC0_TX_CLK_SRC] = &gmac0_tx_clk_src.clkr,
+ [GMAC0_TX_DIV_CLK_SRC] = &gmac0_tx_div_clk_src.clkr,
+ [GMAC1_RX_CLK_SRC] = &gmac1_rx_clk_src.clkr,
+ [GMAC1_RX_DIV_CLK_SRC] = &gmac1_rx_div_clk_src.clkr,
+ [GMAC1_TX_CLK_SRC] = &gmac1_tx_clk_src.clkr,
+ [GMAC1_TX_DIV_CLK_SRC] = &gmac1_tx_div_clk_src.clkr,
+ [GMAC_CLK_SRC] = &gmac_clk_src.clkr,
+ [GP1_CLK_SRC] = &gp1_clk_src.clkr,
+ [GP2_CLK_SRC] = &gp2_clk_src.clkr,
+ [GP3_CLK_SRC] = &gp3_clk_src.clkr,
+ [LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,
+ [LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,
+ [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
+ [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
+ [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
+ [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
+ [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
+ [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
+ [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
+ [QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
+ [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
+ [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
+ [QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,
+ [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
+ [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
+ [UBI0_AXI_CLK_SRC] = &ubi0_axi_clk_src.clkr,
+ [UBI0_CORE_CLK_SRC] = &ubi0_core_clk_src.clkr,
+ [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
+ [USB0_LFPS_CLK_SRC] = &usb0_lfps_clk_src.clkr,
+ [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
+ [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
+ [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
+ [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
+ [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
+ [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
+ [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
+ [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
+ [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
+};
+
+static const struct qcom_reset_map gcc_ipq5018_resets[] = {
+ [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
+ [GCC_BLSP1_BCR] = { 0x01000, 0 },
+ [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
+ [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
+ [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
+ [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
+ [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
+ [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
+ [GCC_BTSS_BCR] = { 0x1c000, 0 },
+ [GCC_CMN_BLK_BCR] = { 0x56300, 0 },
+ [GCC_CMN_LDO_BCR] = { 0x33000, 0 },
+ [GCC_CE_BCR] = { 0x33014, 0 },
+ [GCC_CRYPTO_BCR] = { 0x16000, 0 },
+ [GCC_DCC_BCR] = { 0x77000, 0 },
+ [GCC_DCD_BCR] = { 0x2a000, 0 },
+ [GCC_DDRSS_BCR] = { 0x1e000, 0 },
+ [GCC_EDPD_BCR] = { 0x3a000, 0 },
+ [GCC_GEPHY_BCR] = { 0x56000, 0 },
+ [GCC_GEPHY_MDC_SW_ARES] = { 0x56004, 0 },
+ [GCC_GEPHY_DSP_HW_ARES] = { 0x56004, 1 },
+ [GCC_GEPHY_RX_ARES] = { 0x56004, 2 },
+ [GCC_GEPHY_TX_ARES] = { 0x56004, 3 },
+ [GCC_GMAC0_BCR] = { 0x19000, 0 },
+ [GCC_GMAC0_CFG_ARES] = { 0x68428, 0 },
+ [GCC_GMAC0_SYS_ARES] = { 0x68428, 1 },
+ [GCC_GMAC1_BCR] = { 0x19100, 0 },
+ [GCC_GMAC1_CFG_ARES] = { 0x68438, 0 },
+ [GCC_GMAC1_SYS_ARES] = { 0x68438, 1 },
+ [GCC_IMEM_BCR] = { 0x0e000, 0 },
+ [GCC_LPASS_BCR] = { 0x2e000, 0 },
+ [GCC_MDIO0_BCR] = { 0x58000, 0 },
+ [GCC_MDIO1_BCR] = { 0x58010, 0 },
+ [GCC_MPM_BCR] = { 0x2c000, 0 },
+ [GCC_PCIE0_BCR] = { 0x75004, 0 },
+ [GCC_PCIE0_LINK_DOWN_BCR] = { 0x750a8, 0 },
+ [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
+ [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
+ [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
+ [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
+ [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
+ [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
+ [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
+ [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
+ [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
+ [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
+ [GCC_PCIE1_BCR] = { 0x76004, 0 },
+ [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
+ [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
+ [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
+ [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
+ [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
+ [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
+ [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
+ [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
+ [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
+ [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
+ [GCC_PCIE1_AXI_SLAVE_STICKY_ARES] = { 0x76040, 7 },
+ [GCC_PCNOC_BCR] = { 0x27018, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT10_BCR] = { 0x48050, 0 },
+ [GCC_PCNOC_BUS_TIMEOUT11_BCR] = { 0x48058, 0 },
+ [GCC_PRNG_BCR] = { 0x13000, 0 },
+ [GCC_Q6SS_DBG_ARES] = { 0x59110, 0 },
+ [GCC_Q6_AHB_S_ARES] = { 0x59110, 1 },
+ [GCC_Q6_AHB_ARES] = { 0x59110, 2 },
+ [GCC_Q6_AXIM2_ARES] = { 0x59110, 3 },
+ [GCC_Q6_AXIM_ARES] = { 0x59110, 4 },
+ [GCC_Q6_AXIS_ARES] = { 0x59158, 0 },
+ [GCC_QDSS_BCR] = { 0x29000, 0 },
+ [GCC_QPIC_BCR] = { 0x57018, 0 },
+ [GCC_QUSB2_0_PHY_BCR] = { 0x41030, 0 },
+ [GCC_SDCC1_BCR] = { 0x42000, 0 },
+ [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
+ [GCC_SPDM_BCR] = { 0x2f000, 0 },
+ [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
+ [GCC_TCSR_BCR] = { 0x28000, 0 },
+ [GCC_TLMM_BCR] = { 0x34000, 0 },
+ [GCC_UBI0_AXI_ARES] = { 0x680},
+ [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
+ [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
+ [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
+ [GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
+ [GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
+ [GCC_UBI32_BCR] = { 0x19064, 0 },
+ [GCC_UNIPHY_BCR] = { 0x56100, 0 },
+ [GCC_UNIPHY_AHB_ARES] = { 0x56104, 0 },
+ [GCC_UNIPHY_SYS_ARES] = { 0x56104, 1 },
+ [GCC_UNIPHY_RX_ARES] = { 0x56104, 4 },
+ [GCC_UNIPHY_TX_ARES] = { 0x56104, 5 },
+ [GCC_UNIPHY_SOFT_RESET] = {0x56104, 0 },
+ [GCC_USB0_BCR] = { 0x3e070, 0 },
+ [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
+ [GCC_WCSS_BCR] = { 0x18000, 0 },
+ [GCC_WCSS_DBG_ARES] = { 0x59008, 0 },
+ [GCC_WCSS_ECAHB_ARES] = { 0x59008, 1 },
+ [GCC_WCSS_ACMT_ARES] = { 0x59008, 2 },
+ [GCC_WCSS_DBG_BDG_ARES] = { 0x59008, 3 },
+ [GCC_WCSS_AHB_S_ARES] = { 0x59008, 4 },
+ [GCC_WCSS_AXI_M_ARES] = { 0x59008, 5 },
+ [GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 },
+ [GCC_WCSS_Q6_BCR] = { 0x18004, 0 },
+ [GCC_WCSSAON_RESET] = { 0x59010, 0},
+ [GCC_GEPHY_MISC_ARES] = { 0x56004, 0 },
+};
+
+static const struct of_device_id gcc_ipq5018_match_table[] = {
+ { .compatible = "qcom,gcc-ipq5018" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, gcc_ipq5018_match_table);
+
+static const struct regmap_config gcc_ipq5018_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x7fffc,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc gcc_ipq5018_desc = {
+ .config = &gcc_ipq5018_regmap_config,
+ .clks = gcc_ipq5018_clks,
+ .num_clks = ARRAY_SIZE(gcc_ipq5018_clks),
+ .resets = gcc_ipq5018_resets,
+ .num_resets = ARRAY_SIZE(gcc_ipq5018_resets),
+ .clk_hws = gcc_ipq5018_hws,
+ .num_clk_hws = ARRAY_SIZE(gcc_ipq5018_hws),
+};
+
+static int gcc_ipq5018_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+ struct qcom_cc_desc ipq5018_desc = gcc_ipq5018_desc;
+
+ regmap = qcom_cc_map(pdev, &ipq5018_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
+
+ return qcom_cc_really_probe(pdev, &ipq5018_desc, regmap);
+}
+
+static struct platform_driver gcc_ipq5018_driver = {
+ .probe = gcc_ipq5018_probe,
+ .driver = {
+ .name = "qcom,gcc-ipq5018",
+ .of_match_table = gcc_ipq5018_match_table,
+ },
+};
+
+static int __init gcc_ipq5018_init(void)
+{
+ return platform_driver_register(&gcc_ipq5018_driver);
+}
+core_initcall(gcc_ipq5018_init);
+
+static void __exit gcc_ipq5018_exit(void)
+{
+ platform_driver_unregister(&gcc_ipq5018_driver);
+}
+module_exit(gcc_ipq5018_exit);
+
+MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ5018 Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index a75ab88ed14c..b02026f8549b 100644
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -4,8 +4,9 @@
*/
#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
@@ -226,36 +227,18 @@ static const struct clk_parent_data gcc_parent_data_4[] = {
static const struct parent_map gcc_parent_map_5[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
- { P_GPLL2_OUT_AUX, 2 },
- { P_GPLL4_OUT_AUX, 3 },
- { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
- { P_GPLL0_OUT_AUX, 5 },
-};
-
-static const struct clk_parent_data gcc_parent_data_5[] = {
- { .index = DT_XO },
- { .hw = &gpll0.clkr.hw },
- { .hw = &gpll2.clkr.hw },
- { .hw = &gpll4.clkr.hw },
- { .hw = &gpll0_div2.hw },
- { .hw = &gpll0.clkr.hw },
-};
-
-static const struct parent_map gcc_parent_map_6[] = {
- { P_XO, 0 },
- { P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_AUX, 2 },
{ P_SLEEP_CLK, 6 },
};
-static const struct clk_parent_data gcc_parent_data_6[] = {
+static const struct clk_parent_data gcc_parent_data_5[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0.clkr.hw },
{ .index = DT_SLEEP_CLK },
};
-static const struct parent_map gcc_parent_map_7[] = {
+static const struct parent_map gcc_parent_map_6[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL2_OUT_AUX, 2 },
@@ -263,7 +246,7 @@ static const struct parent_map gcc_parent_map_7[] = {
{ P_SLEEP_CLK, 6 },
};
-static const struct clk_parent_data gcc_parent_data_7[] = {
+static const struct clk_parent_data gcc_parent_data_6[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
@@ -271,74 +254,74 @@ static const struct clk_parent_data gcc_parent_data_7[] = {
{ .index = DT_SLEEP_CLK },
};
-static const struct parent_map gcc_parent_map_8[] = {
+static const struct parent_map gcc_parent_map_7[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL2_OUT_AUX, 2 },
};
-static const struct clk_parent_data gcc_parent_data_8[] = {
+static const struct clk_parent_data gcc_parent_data_7[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
};
-static const struct parent_map gcc_parent_map_9[] = {
+static const struct parent_map gcc_parent_map_8[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL2_OUT_MAIN, 2 },
{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
};
-static const struct clk_parent_data gcc_parent_data_9[] = {
+static const struct clk_parent_data gcc_parent_data_8[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll0_div2.hw },
};
-static const struct parent_map gcc_parent_map_10[] = {
+static const struct parent_map gcc_parent_map_9[] = {
{ P_SLEEP_CLK, 6 },
};
-static const struct clk_parent_data gcc_parent_data_10[] = {
+static const struct clk_parent_data gcc_parent_data_9[] = {
{ .index = DT_SLEEP_CLK },
};
-static const struct parent_map gcc_parent_map_11[] = {
+static const struct parent_map gcc_parent_map_10[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL4_OUT_MAIN, 2 },
{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 3 },
};
-static const struct clk_parent_data gcc_parent_data_11[] = {
+static const struct clk_parent_data gcc_parent_data_10[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0_div2.hw },
};
-static const struct parent_map gcc_parent_map_12[] = {
+static const struct parent_map gcc_parent_map_11[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_AUX, 2 },
{ P_SLEEP_CLK, 6 },
};
-static const struct clk_parent_data gcc_parent_data_12[] = {
+static const struct clk_parent_data gcc_parent_data_11[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .index = DT_SLEEP_CLK },
};
-static const struct parent_map gcc_parent_map_13[] = {
+static const struct parent_map gcc_parent_map_12[] = {
{ P_XO, 0 },
{ P_GPLL4_OUT_AUX, 1 },
{ P_GPLL0_OUT_MAIN, 3 },
{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
};
-static const struct clk_parent_data gcc_parent_data_13[] = {
+static const struct clk_parent_data gcc_parent_data_12[] = {
{ .index = DT_XO },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0.clkr.hw },
@@ -371,20 +354,6 @@ static const struct freq_tbl ftbl_gcc_apss_axi_clk_src[] = {
{ }
};
-static struct clk_rcg2 gcc_apss_axi_clk_src = {
- .cmd_rcgr = 0x24004,
- .mnd_width = 0,
- .hid_width = 5,
- .parent_map = gcc_parent_map_5,
- .freq_tbl = ftbl_gcc_apss_axi_clk_src,
- .clkr.hw.init = &(const struct clk_init_data) {
- .name = "gcc_apss_axi_clk_src",
- .parent_data = gcc_parent_data_5,
- .num_parents = ARRAY_SIZE(gcc_parent_data_5),
- .ops = &clk_rcg2_ops,
- },
-};
-
static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = {
F(960000, P_XO, 1, 1, 25),
F(4800000, P_XO, 5, 0, 0),
@@ -733,12 +702,12 @@ static struct clk_rcg2 gcc_pcie_aux_clk_src = {
.cmd_rcgr = 0x28004,
.mnd_width = 16,
.hid_width = 5,
- .parent_map = gcc_parent_map_6,
+ .parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_pcie_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_aux_clk_src",
- .parent_data = gcc_parent_data_6,
- .num_parents = ARRAY_SIZE(gcc_parent_data_6),
+ .parent_data = gcc_parent_data_5,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_ops,
},
};
@@ -810,12 +779,12 @@ static struct clk_rcg2 gcc_q6_axim_clk_src = {
.cmd_rcgr = 0x25004,
.mnd_width = 0,
.hid_width = 5,
- .parent_map = gcc_parent_map_7,
+ .parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_apss_axi_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_q6_axim_clk_src",
- .parent_data = gcc_parent_data_7,
- .num_parents = ARRAY_SIZE(gcc_parent_data_7),
+ .parent_data = gcc_parent_data_6,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_ops,
},
};
@@ -931,12 +900,12 @@ static struct clk_rcg2 gcc_qpic_io_macro_clk_src = {
.cmd_rcgr = 0x32004,
.mnd_width = 0,
.hid_width = 5,
- .parent_map = gcc_parent_map_8,
+ .parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_qpic_io_macro_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_qpic_io_macro_clk_src",
- .parent_data = gcc_parent_data_8,
- .num_parents = ARRAY_SIZE(gcc_parent_data_8),
+ .parent_data = gcc_parent_data_7,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_7),
.ops = &clk_rcg2_ops,
},
};
@@ -957,12 +926,12 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.cmd_rcgr = 0x33004,
.mnd_width = 8,
.hid_width = 5,
- .parent_map = gcc_parent_map_9,
+ .parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc1_apps_clk_src",
- .parent_data = gcc_parent_data_9,
- .num_parents = ARRAY_SIZE(gcc_parent_data_9),
+ .parent_data = gcc_parent_data_8,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_rcg2_floor_ops,
},
};
@@ -976,12 +945,12 @@ static struct clk_rcg2 gcc_sleep_clk_src = {
.cmd_rcgr = 0x3400c,
.mnd_width = 0,
.hid_width = 5,
- .parent_map = gcc_parent_map_10,
+ .parent_map = gcc_parent_map_9,
.freq_tbl = ftbl_gcc_sleep_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_sleep_clk_src",
- .parent_data = gcc_parent_data_10,
- .num_parents = ARRAY_SIZE(gcc_parent_data_10),
+ .parent_data = gcc_parent_data_9,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_9),
.ops = &clk_rcg2_ops,
},
};
@@ -998,12 +967,12 @@ static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x2e004,
.mnd_width = 0,
.hid_width = 5,
- .parent_map = gcc_parent_map_11,
+ .parent_map = gcc_parent_map_10,
.freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_system_noc_bfdcd_clk_src",
- .parent_data = gcc_parent_data_11,
- .num_parents = ARRAY_SIZE(gcc_parent_data_11),
+ .parent_data = gcc_parent_data_10,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_10),
.ops = &clk_rcg2_ops,
},
};
@@ -1039,12 +1008,12 @@ static struct clk_rcg2 gcc_usb0_aux_clk_src = {
.cmd_rcgr = 0x2c018,
.mnd_width = 16,
.hid_width = 5,
- .parent_map = gcc_parent_map_12,
+ .parent_map = gcc_parent_map_11,
.freq_tbl = ftbl_gcc_pcie_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_aux_clk_src",
- .parent_data = gcc_parent_data_12,
- .num_parents = ARRAY_SIZE(gcc_parent_data_12),
+ .parent_data = gcc_parent_data_11,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_11),
.ops = &clk_rcg2_ops,
},
};
@@ -1091,12 +1060,12 @@ static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = {
.cmd_rcgr = 0x2c02c,
.mnd_width = 8,
.hid_width = 5,
- .parent_map = gcc_parent_map_13,
+ .parent_map = gcc_parent_map_12,
.freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_mock_utmi_clk_src",
- .parent_data = gcc_parent_data_13,
- .num_parents = ARRAY_SIZE(gcc_parent_data_13),
+ .parent_data = gcc_parent_data_12,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_12),
.ops = &clk_rcg2_ops,
},
};
@@ -1635,42 +1604,6 @@ static struct clk_branch gcc_mdio_slave_ahb_clk = {
},
};
-static struct clk_branch gcc_mem_noc_q6_axi_clk = {
- .halt_reg = 0x19010,
- .halt_check = BRANCH_HALT,
- .clkr = {
- .enable_reg = 0x19010,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "gcc_mem_noc_q6_axi_clk",
- .parent_hws = (const struct clk_hw*[]) {
- &gcc_q6_axim_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch gcc_mem_noc_ts_clk = {
- .halt_reg = 0x19028,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0x19028,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "gcc_mem_noc_ts_clk",
- .parent_hws = (const struct clk_hw*[]) {
- &gcc_qdss_tsctr_div8_clk_src.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_nss_ts_clk = {
.halt_reg = 0x17018,
.halt_check = BRANCH_HALT_VOTED,
@@ -3339,42 +3272,6 @@ static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
},
};
-static struct clk_branch gcc_mem_noc_ahb_clk = {
- .halt_reg = 0x1900c,
- .halt_check = BRANCH_HALT,
- .clkr = {
- .enable_reg = 0x1900c,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "gcc_mem_noc_ahb_clk",
- .parent_hws = (const struct clk_hw*[]) {
- &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch gcc_mem_noc_apss_axi_clk = {
- .halt_reg = 0x1901c,
- .halt_check = BRANCH_HALT_VOTED,
- .clkr = {
- .enable_reg = 0xb004,
- .enable_mask = BIT(6),
- .hw.init = &(const struct clk_init_data) {
- .name = "gcc_mem_noc_apss_axi_clk",
- .parent_hws = (const struct clk_hw*[]) {
- &gcc_apss_axi_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_regmap_div gcc_snoc_qosgen_extref_div_clk_src = {
.reg = 0x2e010,
.shift = 0,
@@ -3390,24 +3287,6 @@ static struct clk_regmap_div gcc_snoc_qosgen_extref_div_clk_src = {
},
};
-static struct clk_branch gcc_mem_noc_qosgen_extref_clk = {
- .halt_reg = 0x19024,
- .halt_check = BRANCH_HALT,
- .clkr = {
- .enable_reg = 0x19024,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "gcc_mem_noc_qosgen_extref_clk",
- .parent_hws = (const struct clk_hw*[]) {
- &gcc_snoc_qosgen_extref_div_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_regmap *gcc_ipq5332_clocks[] = {
[GPLL0_MAIN] = &gpll0_main.clkr,
[GPLL0] = &gpll0.clkr,
@@ -3418,7 +3297,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
[GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr,
[GCC_AHB_CLK] = &gcc_ahb_clk.clkr,
- [GCC_APSS_AXI_CLK_SRC] = &gcc_apss_axi_clk_src.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
@@ -3451,8 +3329,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
[GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr,
[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
[GCC_MDIO_SLAVE_AHB_CLK] = &gcc_mdio_slave_ahb_clk.clkr,
- [GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr,
- [GCC_MEM_NOC_TS_CLK] = &gcc_mem_noc_ts_clk.clkr,
[GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
[GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr,
[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
@@ -3573,10 +3449,7 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
[GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
[GCC_IM_SLEEP_CLK] = &gcc_im_sleep_clk.clkr,
[GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
- [GCC_MEM_NOC_AHB_CLK] = &gcc_mem_noc_ahb_clk.clkr,
- [GCC_MEM_NOC_APSS_AXI_CLK] = &gcc_mem_noc_apss_axi_clk.clkr,
[GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC] = &gcc_snoc_qosgen_extref_div_clk_src.clkr,
- [GCC_MEM_NOC_QOSGEN_EXTREF_CLK] = &gcc_mem_noc_qosgen_extref_clk.clkr,
[GCC_PCIE3X2_PIPE_CLK_SRC] = &gcc_pcie3x2_pipe_clk_src.clkr,
[GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr,
[GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr,
diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
index 86b43175b042..6120fbbc5de0 100644
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -8,7 +8,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 6447f3e81b55..974d01fd4381 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -9,7 +9,7 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
+#include <linux/of_platform.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index 6541d98c0348..63ac2ced76bb 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -8,7 +8,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 6914f962c893..8f430367299e 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -2004,6 +2004,41 @@ static struct clk_regmap_mux usb0_pipe_clk_src = {
},
};
+static struct clk_branch gcc_usb0_pipe_clk = {
+ .halt_reg = 0x2c054,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x2c054,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb0_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &usb0_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_sleep_clk = {
+ .halt_reg = 0x2c058,
+ .clkr = {
+ .enable_reg = 0x2c058,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb0_sleep_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_sleep_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
F(144000, P_XO, 16, 12, 125),
F(400000, P_XO, 12, 1, 5),
@@ -4003,6 +4038,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
+ [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
+ [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
diff --git a/drivers/clk/qcom/gcc-mdm9607.c b/drivers/clk/qcom/gcc-mdm9607.c
index 4c9078e99bb3..fb290e73ce94 100644
--- a/drivers/clk/qcom/gcc-mdm9607.c
+++ b/drivers/clk/qcom/gcc-mdm9607.c
@@ -9,7 +9,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
index 8bed02a748ab..aec7c4a1d3de 100644
--- a/drivers/clk/qcom/gcc-mdm9615.c
+++ b/drivers/clk/qcom/gcc-mdm9615.c
@@ -11,7 +11,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
@@ -26,15 +25,23 @@
#include "clk-branch.h"
#include "reset.h"
-static struct clk_fixed_factor cxo = {
- .mult = 1,
- .div = 1,
- .hw.init = &(struct clk_init_data){
- .name = "cxo",
- .parent_names = (const char *[]){ "cxo_board" },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- },
+enum {
+ DT_CXO,
+ DT_PLL4,
+};
+
+enum {
+ P_CXO,
+ P_PLL8,
+ P_PLL14,
+};
+
+static const struct parent_map gcc_cxo_map[] = {
+ { P_CXO, 0 },
+};
+
+static const struct clk_parent_data gcc_cxo[] = {
+ { .index = DT_CXO, .name = "cxo_board" },
};
static struct clk_pll pll0 = {
@@ -47,8 +54,8 @@ static struct clk_pll pll0 = {
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll0",
- .parent_names = (const char *[]){ "cxo" },
- .num_parents = 1,
+ .parent_data = gcc_cxo,
+ .num_parents = ARRAY_SIZE(gcc_cxo),
.ops = &clk_pll_ops,
},
};
@@ -58,7 +65,9 @@ static struct clk_regmap pll0_vote = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "pll0_vote",
- .parent_names = (const char *[]){ "pll8" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &pll0.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@@ -69,7 +78,9 @@ static struct clk_regmap pll4_vote = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pll4_vote",
- .parent_names = (const char *[]){ "pll4" },
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_PLL4, .name = "pll4",
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@@ -85,8 +96,8 @@ static struct clk_pll pll8 = {
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll8",
- .parent_names = (const char *[]){ "cxo" },
- .num_parents = 1,
+ .parent_data = gcc_cxo,
+ .num_parents = ARRAY_SIZE(gcc_cxo),
.ops = &clk_pll_ops,
},
};
@@ -96,7 +107,9 @@ static struct clk_regmap pll8_vote = {
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "pll8_vote",
- .parent_names = (const char *[]){ "pll8" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &pll8.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@@ -112,8 +125,8 @@ static struct clk_pll pll14 = {
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll14",
- .parent_names = (const char *[]){ "cxo" },
- .num_parents = 1,
+ .parent_data = gcc_cxo,
+ .num_parents = ARRAY_SIZE(gcc_cxo),
.ops = &clk_pll_ops,
},
};
@@ -123,26 +136,22 @@ static struct clk_regmap pll14_vote = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "pll14_vote",
- .parent_names = (const char *[]){ "pll14" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &pll14.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
-enum {
- P_CXO,
- P_PLL8,
- P_PLL14,
-};
-
static const struct parent_map gcc_cxo_pll8_map[] = {
{ P_CXO, 0 },
{ P_PLL8, 3 }
};
-static const char * const gcc_cxo_pll8[] = {
- "cxo",
- "pll8_vote",
+static const struct clk_parent_data gcc_cxo_pll8[] = {
+ { .index = DT_CXO, .name = "cxo_board" },
+ { .hw = &pll8_vote.hw },
};
static const struct parent_map gcc_cxo_pll14_map[] = {
@@ -150,17 +159,9 @@ static const struct parent_map gcc_cxo_pll14_map[] = {
{ P_PLL14, 4 }
};
-static const char * const gcc_cxo_pll14[] = {
- "cxo",
- "pll14_vote",
-};
-
-static const struct parent_map gcc_cxo_map[] = {
- { P_CXO, 0 },
-};
-
-static const char * const gcc_cxo[] = {
- "cxo",
+static const struct clk_parent_data gcc_cxo_pll14[] = {
+ { .index = DT_CXO, .name = "cxo_board" },
+ { .hw = &pll14_vote.hw },
};
static struct freq_tbl clk_tbl_gsbi_uart[] = {
@@ -206,8 +207,8 @@ static struct clk_rcg gsbi1_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_src",
- .parent_names = gcc_cxo_pll8,
- .num_parents = 2,
+ .parent_data = gcc_cxo_pll8,
+ .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -222,8 +223,8 @@ static struct clk_branch gsbi1_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_clk",
- .parent_names = (const char *[]){
- "gsbi1_uart_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gsbi1_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -257,8 +258,8 @@ static struct clk_rcg gsbi2_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_src",
- .parent_names = gcc_cxo_pll8,
- .num_parents = 2,
+ .parent_data = gcc_cxo_pll8,
+ .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -273,8 +274,8 @@ static struct clk_branch gsbi2_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_clk",
- .parent_names = (const char *[]){
- "gsbi2_uart_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gsbi2_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -308,8 +309,8 @@ static struct clk_rcg gsbi3_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_uart_src",
- .parent_names = gcc_cxo_pll8,
- .num_parents = 2,
+ .parent_data = gcc_cxo_pll8,
+ .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -324,8 +325,8 @@ static struct clk_branch gsbi3_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_uart_clk",
- .parent_names = (const char *[]){
- "gsbi3_uart_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gsbi3_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -359,8 +360,8 @@ static struct clk_rcg gsbi4_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_src",
- .parent_names = gcc_cxo_pll8,
- .num_parents = 2,
+ .parent_data = gcc_cxo_pll8,
+ .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -375,8 +376,8 @@ static struct clk_branch gsbi4_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_clk",
- .parent_names = (const char *[]){
- "gsbi4_uart_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gsbi4_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -410,8 +411,8 @@ static struct clk_rcg gsbi5_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_src",
- .parent_names = gcc_cxo_pll8,
- .num_parents = 2,
+ .parent_data = gcc_cxo_pll8,
+ .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -426,8 +427,8 @@ static struct clk_branch gsbi5_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_clk",
- .parent_names = (const char *[]){
- "gsbi5_uart_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gsbi5_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -473,8 +474,8 @@ static struct clk_rcg gsbi1_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_src",
- .parent_names = gcc_cxo_pll8,
- .num_parents = 2,
+ .parent_data = gcc_cxo_pll8,
+ .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -489,7 +490,9 @@ static struct clk_branch gsbi1_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_clk",
- .parent_names = (const char *[]){ "gsbi1_qup_src" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &gsbi1_qup_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -522,8 +525,8 @@ static struct clk_rcg gsbi2_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_src",
- .parent_names = gcc_cxo_pll8,
- .num_parents = 2,
+ .parent_data = gcc_cxo_pll8,
+ .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -538,7 +541,9 @@ static struct clk_branch gsbi2_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_clk",
- .parent_names = (const char *[]){ "gsbi2_qup_src" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &gsbi2_qup_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -571,8 +576,8 @@ static struct clk_rcg gsbi3_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_qup_src",
- .parent_names = gcc_cxo_pll8,
- .num_parents = 2,
+ .parent_data = gcc_cxo_pll8,
+ .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -587,7 +592,9 @@ static struct clk_branch gsbi3_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_qup_clk",
- .parent_names = (const char *[]){ "gsbi3_qup_src" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &gsbi3_qup_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -620,8 +627,8 @@ static struct clk_rcg gsbi4_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_src",
- .parent_names = gcc_cxo_pll8,
- .num_parents = 2,
+ .parent_data = gcc_cxo_pll8,
+ .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -636,7 +643,9 @@ static struct clk_branch gsbi4_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_clk",
- .parent_names = (const char *[]){ "gsbi4_qup_src" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &gsbi4_qup_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -669,8 +678,8 @@ static struct clk_rcg gsbi5_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_src",
- .parent_names = gcc_cxo_pll8,
- .num_parents = 2,
+ .parent_data = gcc_cxo_pll8,
+ .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -685,7 +694,9 @@ static struct clk_branch gsbi5_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_clk",
- .parent_names = (const char *[]){ "gsbi5_qup_src" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &gsbi5_qup_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -724,8 +735,8 @@ static struct clk_rcg gp0_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp0_src",
- .parent_names = gcc_cxo,
- .num_parents = 1,
+ .parent_data = gcc_cxo,
+ .num_parents = ARRAY_SIZE(gcc_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -740,7 +751,9 @@ static struct clk_branch gp0_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp0_clk",
- .parent_names = (const char *[]){ "gp0_src" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &gp0_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -773,8 +786,8 @@ static struct clk_rcg gp1_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp1_src",
- .parent_names = gcc_cxo,
- .num_parents = 1,
+ .parent_data = gcc_cxo,
+ .num_parents = ARRAY_SIZE(gcc_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -789,7 +802,9 @@ static struct clk_branch gp1_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp1_clk",
- .parent_names = (const char *[]){ "gp1_src" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &gp1_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -822,8 +837,8 @@ static struct clk_rcg gp2_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp2_src",
- .parent_names = gcc_cxo,
- .num_parents = 1,
+ .parent_data = gcc_cxo,
+ .num_parents = ARRAY_SIZE(gcc_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -838,7 +853,9 @@ static struct clk_branch gp2_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp2_clk",
- .parent_names = (const char *[]){ "gp2_src" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &gp2_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -874,8 +891,8 @@ static struct clk_rcg prng_src = {
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "prng_src",
- .parent_names = gcc_cxo_pll8,
- .num_parents = 2,
+ .parent_data = gcc_cxo_pll8,
+ .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
},
},
@@ -890,7 +907,9 @@ static struct clk_branch prng_clk = {
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "prng_clk",
- .parent_names = (const char *[]){ "prng_src" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &prng_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
},
@@ -936,8 +955,8 @@ static struct clk_rcg sdc1_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc1_src",
- .parent_names = gcc_cxo_pll8,
- .num_parents = 2,
+ .parent_data = gcc_cxo_pll8,
+ .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -951,7 +970,9 @@ static struct clk_branch sdc1_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc1_clk",
- .parent_names = (const char *[]){ "sdc1_src" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &sdc1_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -984,8 +1005,8 @@ static struct clk_rcg sdc2_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc2_src",
- .parent_names = gcc_cxo_pll8,
- .num_parents = 2,
+ .parent_data = gcc_cxo_pll8,
+ .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -999,7 +1020,9 @@ static struct clk_branch sdc2_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc2_clk",
- .parent_names = (const char *[]){ "sdc2_src" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &sdc2_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1037,8 +1060,8 @@ static struct clk_rcg usb_hs1_xcvr_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_src",
- .parent_names = gcc_cxo_pll8,
- .num_parents = 2,
+ .parent_data = gcc_cxo_pll8,
+ .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1053,7 +1076,9 @@ static struct clk_branch usb_hs1_xcvr_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_clk",
- .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &usb_hs1_xcvr_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1086,8 +1111,8 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hsic_xcvr_fs_src",
- .parent_names = gcc_cxo_pll8,
- .num_parents = 2,
+ .parent_data = gcc_cxo_pll8,
+ .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1102,8 +1127,9 @@ static struct clk_branch usb_hsic_xcvr_fs_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_hsic_xcvr_fs_clk",
- .parent_names =
- (const char *[]){ "usb_hsic_xcvr_fs_src" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &usb_hsic_xcvr_fs_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1141,8 +1167,8 @@ static struct clk_rcg usb_hs1_system_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_system_src",
- .parent_names = gcc_cxo_pll8,
- .num_parents = 2,
+ .parent_data = gcc_cxo_pll8,
+ .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1156,8 +1182,9 @@ static struct clk_branch usb_hs1_system_clk = {
.enable_reg = 0x36a4,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
- .parent_names =
- (const char *[]){ "usb_hs1_system_src" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &usb_hs1_system_src.clkr.hw,
+ },
.num_parents = 1,
.name = "usb_hs1_system_clk",
.ops = &clk_branch_ops,
@@ -1196,8 +1223,8 @@ static struct clk_rcg usb_hsic_system_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hsic_system_src",
- .parent_names = gcc_cxo_pll8,
- .num_parents = 2,
+ .parent_data = gcc_cxo_pll8,
+ .num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1211,8 +1238,9 @@ static struct clk_branch usb_hsic_system_clk = {
.enable_reg = 0x2b58,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
- .parent_names =
- (const char *[]){ "usb_hsic_system_src" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &usb_hsic_system_src.clkr.hw,
+ },
.num_parents = 1,
.name = "usb_hsic_system_clk",
.ops = &clk_branch_ops,
@@ -1251,8 +1279,8 @@ static struct clk_rcg usb_hsic_hsic_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hsic_hsic_src",
- .parent_names = gcc_cxo_pll14,
- .num_parents = 2,
+ .parent_data = gcc_cxo_pll14,
+ .num_parents = ARRAY_SIZE(gcc_cxo_pll14),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1265,7 +1293,9 @@ static struct clk_branch usb_hsic_hsic_clk = {
.enable_reg = 0x2b50,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
- .parent_names = (const char *[]){ "usb_hsic_hsic_src" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &usb_hsic_hsic_src.clkr.hw,
+ },
.num_parents = 1,
.name = "usb_hsic_hsic_clk",
.ops = &clk_branch_ops,
@@ -1281,8 +1311,8 @@ static struct clk_branch usb_hsic_hsio_cal_clk = {
.enable_reg = 0x2b48,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
- .parent_names = (const char *[]){ "cxo" },
- .num_parents = 1,
+ .parent_data = gcc_cxo,
+ .num_parents = ARRAY_SIZE(gcc_cxo),
.name = "usb_hsic_hsio_cal_clk",
.ops = &clk_branch_ops,
},
@@ -1581,10 +1611,6 @@ static struct clk_branch ebi2_aon_clk = {
},
};
-static struct clk_hw *gcc_mdm9615_hws[] = {
- &cxo.hw,
-};
-
static struct clk_regmap *gcc_mdm9615_clks[] = {
[PLL0] = &pll0.clkr,
[PLL0_VOTE] = &pll0_vote,
@@ -1694,8 +1720,6 @@ static const struct qcom_cc_desc gcc_mdm9615_desc = {
.num_clks = ARRAY_SIZE(gcc_mdm9615_clks),
.resets = gcc_mdm9615_resets,
.num_resets = ARRAY_SIZE(gcc_mdm9615_resets),
- .clk_hws = gcc_mdm9615_hws,
- .num_clk_hws = ARRAY_SIZE(gcc_mdm9615_hws),
};
static const struct of_device_id gcc_mdm9615_match_table[] = {
diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c
index a9eb6a9ac445..67870c899ab9 100644
--- a/drivers/clk/qcom/gcc-msm8660.c
+++ b/drivers/clk/qcom/gcc-msm8660.c
@@ -9,7 +9,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
diff --git a/drivers/clk/qcom/gcc-msm8909.c b/drivers/clk/qcom/gcc-msm8909.c
index 2a00b11ce2cd..cc36e81bca7d 100644
--- a/drivers/clk/qcom/gcc-msm8909.c
+++ b/drivers/clk/qcom/gcc-msm8909.c
@@ -14,7 +14,6 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index 0c8fe19387a7..9c7c6b23ce32 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -9,7 +9,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
diff --git a/drivers/clk/qcom/gcc-msm8917.c b/drivers/clk/qcom/gcc-msm8917.c
index a4c33a2ce61c..f2dd132e2fb1 100644
--- a/drivers/clk/qcom/gcc-msm8917.c
+++ b/drivers/clk/qcom/gcc-msm8917.c
@@ -18,7 +18,6 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
@@ -64,7 +63,7 @@ static struct clk_alpha_pll gpll0_sleep_clk_src = {
.index = DT_XO,
},
.num_parents = 1,
- .ops = &clk_alpha_pll_ops,
+ .ops = &clk_branch_simple_ops,
},
},
};
@@ -3042,6 +3041,7 @@ static struct gdsc cpp_gdsc = {
static struct clk_regmap *gcc_msm8917_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL0_EARLY] = &gpll0_early.clkr,
+ [GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
[GPLL3] = &gpll3.clkr,
[GPLL3_EARLY] = &gpll3_early.clkr,
[GPLL4] = &gpll4.clkr,
diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c
index 7f8969a77974..b45f97c07eeb 100644
--- a/drivers/clk/qcom/gcc-msm8939.c
+++ b/drivers/clk/qcom/gcc-msm8939.c
@@ -9,7 +9,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
diff --git a/drivers/clk/qcom/gcc-msm8953.c b/drivers/clk/qcom/gcc-msm8953.c
index 8aafa6591e84..3e5a8cb14d4d 100644
--- a/drivers/clk/qcom/gcc-msm8953.c
+++ b/drivers/clk/qcom/gcc-msm8953.c
@@ -7,7 +7,6 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
diff --git a/drivers/clk/qcom/gcc-msm8976.c b/drivers/clk/qcom/gcc-msm8976.c
index 8beb923c0e19..f60a8171972b 100644
--- a/drivers/clk/qcom/gcc-msm8976.c
+++ b/drivers/clk/qcom/gcc-msm8976.c
@@ -15,8 +15,8 @@
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/of_device.h>
#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-msm8976.h>
diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
index 0f52c48e89d8..80170a805c3b 100644
--- a/drivers/clk/qcom/gcc-msm8994.c
+++ b/drivers/clk/qcom/gcc-msm8994.c
@@ -9,7 +9,6 @@
#include <linux/ctype.h>
#include <linux/io.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/regmap.h>
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index 5e44d1bcca9e..14dcc3f03668 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -9,7 +9,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index be024f8093c5..cad7f1c7789c 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -9,7 +9,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
@@ -25,6 +24,9 @@
#include "reset.h"
#include "gdsc.h"
+#define GCC_MMSS_MISC 0x0902C
+#define GCC_GPU_MISC 0x71028
+
static struct pll_vco fabia_vco[] = {
{ 250000000, 2000000000, 0 },
{ 125000000, 1000000000, 1 },
@@ -1367,6 +1369,22 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
},
};
+static struct clk_branch gcc_mmss_gpll0_div_clk = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_gpll0_div_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gpll0_out_main.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_mmss_gpll0_clk = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
@@ -1395,6 +1413,38 @@ static struct clk_branch gcc_mss_gpll0_div_clk_src = {
},
};
+static struct clk_branch gcc_gpu_gpll0_div_clk = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(3),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_gpll0_div_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gpll0_out_main.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_gpll0_clk = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_gpll0_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gpll0_out_main.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT_VOTED,
@@ -2061,7 +2111,7 @@ static struct clk_branch gcc_gp3_clk = {
static struct clk_branch gcc_bimc_gfx_clk = {
.halt_reg = 0x46040,
- .halt_check = BRANCH_HALT,
+ .halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x46040,
.enable_mask = BIT(0),
@@ -2074,7 +2124,7 @@ static struct clk_branch gcc_bimc_gfx_clk = {
static struct clk_branch gcc_gpu_bimc_gfx_clk = {
.halt_reg = 0x71010,
- .halt_check = BRANCH_HALT,
+ .halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x71010,
.enable_mask = BIT(0),
@@ -2100,7 +2150,7 @@ static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {
static struct clk_branch gcc_gpu_cfg_ahb_clk = {
.halt_reg = 0x71004,
- .halt_check = BRANCH_HALT,
+ .halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x71004,
.enable_mask = BIT(0),
@@ -3080,6 +3130,9 @@ static struct clk_regmap *gcc_msm8998_clocks[] = {
[AGGRE2_SNOC_NORTH_AXI] = &aggre2_snoc_north_axi_clk.clkr,
[SSC_XO] = &ssc_xo_clk.clkr,
[SSC_CNOC_AHBS_CLK] = &ssc_cnoc_ahbs_clk.clkr,
+ [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
+ [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
+ [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
};
static struct gdsc *gcc_msm8998_gdscs[] = {
@@ -3235,6 +3288,10 @@ static int gcc_msm8998_probe(struct platform_device *pdev)
if (ret)
return ret;
+ /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
+ regmap_write(regmap, GCC_MMSS_MISC, 0x10003);
+ regmap_write(regmap, GCC_GPU_MISC, 0x10003);
+
return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap);
}
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
index 5051769ad90c..9f42d2601464 100644
--- a/drivers/clk/qcom/gcc-qdu1000.c
+++ b/drivers/clk/qcom/gcc-qdu1000.c
@@ -1,11 +1,12 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,qdu1000-gcc.h>
@@ -17,6 +18,7 @@
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
+#include "gdsc.h"
#include "reset.h"
enum {
@@ -370,16 +372,6 @@ static const struct clk_parent_data gcc_parent_data_6[] = {
{ .index = DT_TCXO_IDX },
};
-static const struct parent_map gcc_parent_map_7[] = {
- { P_PCIE_0_PIPE_CLK, 0 },
- { P_BI_TCXO, 2 },
-};
-
-static const struct clk_parent_data gcc_parent_data_7[] = {
- { .index = DT_PCIE_0_PIPE_CLK_IDX },
- { .index = DT_TCXO_IDX },
-};
-
static const struct parent_map gcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
@@ -439,16 +431,15 @@ static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = {
},
};
-static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
+static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
.reg = 0x9d064,
- .shift = 0,
- .width = 2,
- .parent_map = gcc_parent_map_7,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_pipe_clk_src",
- .parent_data = gcc_parent_data_7,
- .num_parents = ARRAY_SIZE(gcc_parent_data_7),
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_PCIE_0_PIPE_CLK_IDX,
+ },
+ .num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
@@ -485,7 +476,7 @@ static struct clk_rcg2 gcc_aggre_noc_ecpri_dma_clk_src = {
.name = "gcc_aggre_noc_ecpri_dma_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -505,7 +496,7 @@ static struct clk_rcg2 gcc_aggre_noc_ecpri_gsi_clk_src = {
.name = "gcc_aggre_noc_ecpri_gsi_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -524,7 +515,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = {
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -538,7 +529,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = {
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -552,7 +543,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -571,7 +562,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
.name = "gcc_pcie_0_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -591,7 +582,7 @@ static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
.name = "gcc_pcie_0_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -610,7 +601,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -632,7 +623,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
@@ -648,7 +639,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
@@ -664,7 +655,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
@@ -680,7 +671,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
@@ -696,7 +687,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
@@ -717,7 +708,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
@@ -733,7 +724,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
@@ -749,7 +740,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
@@ -765,7 +756,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
@@ -781,7 +772,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
@@ -797,7 +788,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
@@ -813,7 +804,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
@@ -829,7 +820,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
@@ -845,7 +836,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
@@ -861,7 +852,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
.name = "gcc_qupv3_wrap1_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
@@ -877,7 +868,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
.name = "gcc_qupv3_wrap1_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
@@ -913,7 +904,7 @@ static struct clk_rcg2 gcc_sdcc5_apps_clk_src = {
.name = "gcc_sdcc5_apps_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
@@ -932,7 +923,7 @@ static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = {
.name = "gcc_sdcc5_ice_core_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
@@ -946,7 +937,7 @@ static struct clk_rcg2 gcc_sm_bus_xo_clk_src = {
.name = "gcc_sm_bus_xo_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -965,7 +956,7 @@ static struct clk_rcg2 gcc_tsc_clk_src = {
.name = "gcc_tsc_clk_src",
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -985,7 +976,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -999,7 +990,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -1013,7 +1004,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -1142,6 +1133,26 @@ static struct clk_branch gcc_ddrss_ecpri_dma_clk = {
},
};
+static struct clk_branch gcc_ddrss_ecpri_gsi_clk = {
+ .halt_reg = 0x54298,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x54298,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x54298,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ddrss_ecpri_gsi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_aon_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_ecpri_ahb_clk = {
.halt_reg = 0x3a008,
.halt_check = BRANCH_HALT_VOTED,
@@ -1458,14 +1469,13 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
static struct clk_branch gcc_pcie_0_clkref_en = {
.halt_reg = 0x9c004,
- .halt_bit = 31,
- .halt_check = BRANCH_HALT_ENABLE,
+ .halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9c004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_clkref_en",
- .ops = &clk_branch_ops,
+ .ops = &clk_branch2_ops,
},
},
};
@@ -2285,14 +2295,13 @@ static struct clk_branch gcc_tsc_etu_clk = {
static struct clk_branch gcc_usb2_clkref_en = {
.halt_reg = 0x9c008,
- .halt_bit = 31,
- .halt_check = BRANCH_HALT_ENABLE,
+ .halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9c008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb2_clkref_en",
- .ops = &clk_branch_ops,
+ .ops = &clk_branch2_ops,
},
},
};
@@ -2402,6 +2411,39 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
},
};
+static struct gdsc pcie_0_gdsc = {
+ .gdscr = 0x9d004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "gcc_pcie_0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc pcie_0_phy_gdsc = {
+ .gdscr = 0x7c004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0x2,
+ .pd = {
+ .name = "gcc_pcie_0_phy_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc usb30_prim_gdsc = {
+ .gdscr = 0x49004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "gcc_usb30_prim_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
static struct clk_regmap *gcc_qdu1000_clocks[] = {
[GCC_AGGRE_NOC_ECPRI_DMA_CLK] = &gcc_aggre_noc_ecpri_dma_clk.clkr,
[GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] = &gcc_aggre_noc_ecpri_dma_clk_src.clkr,
@@ -2534,6 +2576,14 @@ static struct clk_regmap *gcc_qdu1000_clocks[] = {
[GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr,
[GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr,
[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
+ [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr,
+ [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr,
+};
+
+static struct gdsc *gcc_qdu1000_gdscs[] = {
+ [PCIE_0_GDSC] = &pcie_0_gdsc,
+ [PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc,
+ [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
};
static const struct qcom_reset_map gcc_qdu1000_resets[] = {
@@ -2597,6 +2647,8 @@ static const struct qcom_cc_desc gcc_qdu1000_desc = {
.num_clks = ARRAY_SIZE(gcc_qdu1000_clocks),
.resets = gcc_qdu1000_resets,
.num_resets = ARRAY_SIZE(gcc_qdu1000_resets),
+ .gdscs = gcc_qdu1000_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_qdu1000_gdscs),
};
static const struct of_device_id gcc_qdu1000_match_table[] = {
diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c
index bb94ff367abd..8171d23c96e6 100644
--- a/drivers/clk/qcom/gcc-sa8775p.c
+++ b/drivers/clk/qcom/gcc-sa8775p.c
@@ -9,8 +9,8 @@
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/of_device.h>
#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
index cef3c77564cf..a3406aadbd17 100644
--- a/drivers/clk/qcom/gcc-sc7180.c
+++ b/drivers/clk/qcom/gcc-sc7180.c
@@ -8,7 +8,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
@@ -651,6 +651,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
+ .flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_floor_ops,
},
};
diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c
index 1dc804154031..2b661df5de26 100644
--- a/drivers/clk/qcom/gcc-sc7280.c
+++ b/drivers/clk/qcom/gcc-sc7280.c
@@ -6,8 +6,8 @@
#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/of_device.h>
#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c
index c41b9f010585..ae2147381559 100644
--- a/drivers/clk/qcom/gcc-sc8180x.c
+++ b/drivers/clk/qcom/gcc-sc8180x.c
@@ -10,7 +10,6 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c
index b90c71637814..bfb77931e868 100644
--- a/drivers/clk/qcom/gcc-sc8280xp.c
+++ b/drivers/clk/qcom/gcc-sc8280xp.c
@@ -8,9 +8,9 @@
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
@@ -6761,7 +6761,7 @@ static struct gdsc pcie_0_tunnel_gdsc = {
.name = "pcie_0_tunnel_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
- .flags = VOTABLE,
+ .flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc pcie_1_tunnel_gdsc = {
@@ -6772,7 +6772,7 @@ static struct gdsc pcie_1_tunnel_gdsc = {
.name = "pcie_1_tunnel_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
- .flags = VOTABLE,
+ .flags = VOTABLE | RETAIN_FF_ENABLE,
};
/*
@@ -6786,8 +6786,8 @@ static struct gdsc pcie_2a_gdsc = {
.pd = {
.name = "pcie_2a_gdsc",
},
- .pwrsts = PWRSTS_OFF_ON,
- .flags = VOTABLE | ALWAYS_ON,
+ .pwrsts = PWRSTS_RET_ON,
+ .flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc pcie_2b_gdsc = {
@@ -6797,8 +6797,8 @@ static struct gdsc pcie_2b_gdsc = {
.pd = {
.name = "pcie_2b_gdsc",
},
- .pwrsts = PWRSTS_OFF_ON,
- .flags = VOTABLE | ALWAYS_ON,
+ .pwrsts = PWRSTS_RET_ON,
+ .flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc pcie_3a_gdsc = {
@@ -6808,8 +6808,8 @@ static struct gdsc pcie_3a_gdsc = {
.pd = {
.name = "pcie_3a_gdsc",
},
- .pwrsts = PWRSTS_OFF_ON,
- .flags = VOTABLE | ALWAYS_ON,
+ .pwrsts = PWRSTS_RET_ON,
+ .flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc pcie_3b_gdsc = {
@@ -6819,8 +6819,8 @@ static struct gdsc pcie_3b_gdsc = {
.pd = {
.name = "pcie_3b_gdsc",
},
- .pwrsts = PWRSTS_OFF_ON,
- .flags = VOTABLE | ALWAYS_ON,
+ .pwrsts = PWRSTS_RET_ON,
+ .flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc pcie_4_gdsc = {
@@ -6830,8 +6830,8 @@ static struct gdsc pcie_4_gdsc = {
.pd = {
.name = "pcie_4_gdsc",
},
- .pwrsts = PWRSTS_OFF_ON,
- .flags = VOTABLE | ALWAYS_ON,
+ .pwrsts = PWRSTS_RET_ON,
+ .flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc ufs_card_gdsc = {
@@ -6840,6 +6840,7 @@ static struct gdsc ufs_card_gdsc = {
.name = "ufs_card_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
+ .flags = RETAIN_FF_ENABLE,
};
static struct gdsc ufs_phy_gdsc = {
@@ -6848,6 +6849,7 @@ static struct gdsc ufs_phy_gdsc = {
.name = "ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
+ .flags = RETAIN_FF_ENABLE,
};
static struct gdsc usb30_mp_gdsc = {
@@ -6856,6 +6858,7 @@ static struct gdsc usb30_mp_gdsc = {
.name = "usb30_mp_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
+ .flags = RETAIN_FF_ENABLE,
};
static struct gdsc usb30_prim_gdsc = {
@@ -6864,6 +6867,7 @@ static struct gdsc usb30_prim_gdsc = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
+ .flags = RETAIN_FF_ENABLE,
};
static struct gdsc usb30_sec_gdsc = {
@@ -6872,6 +6876,7 @@ static struct gdsc usb30_sec_gdsc = {
.name = "usb30_sec_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
+ .flags = RETAIN_FF_ENABLE,
};
static struct gdsc emac_0_gdsc = {
@@ -6880,6 +6885,7 @@ static struct gdsc emac_0_gdsc = {
.name = "emac_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
+ .flags = RETAIN_FF_ENABLE,
};
static struct gdsc emac_1_gdsc = {
@@ -6888,6 +6894,97 @@ static struct gdsc emac_1_gdsc = {
.name = "emac_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
+ .flags = RETAIN_FF_ENABLE,
+};
+
+static struct gdsc usb4_1_gdsc = {
+ .gdscr = 0xb8004,
+ .pd = {
+ .name = "usb4_1_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = RETAIN_FF_ENABLE,
+};
+
+static struct gdsc usb4_gdsc = {
+ .gdscr = 0x2a004,
+ .pd = {
+ .name = "usb4_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = RETAIN_FF_ENABLE,
+};
+
+static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
+ .gdscr = 0x7d050,
+ .pd = {
+ .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
+ .gdscr = 0x7d058,
+ .pd = {
+ .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = {
+ .gdscr = 0x7d054,
+ .pd = {
+ .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = {
+ .gdscr = 0x7d06c,
+ .pd = {
+ .name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
+ .gdscr = 0x7d05c,
+ .pd = {
+ .name = "hlos1_vote_turing_mmu_tbu0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
+ .gdscr = 0x7d060,
+ .pd = {
+ .name = "hlos1_vote_turing_mmu_tbu1_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc hlos1_vote_turing_mmu_tbu2_gdsc = {
+ .gdscr = 0x7d0a0,
+ .pd = {
+ .name = "hlos1_vote_turing_mmu_tbu2_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc hlos1_vote_turing_mmu_tbu3_gdsc = {
+ .gdscr = 0x7d0a4,
+ .pd = {
+ .name = "hlos1_vote_turing_mmu_tbu3_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
};
static struct clk_regmap *gcc_sc8280xp_clocks[] = {
@@ -7370,6 +7467,16 @@ static struct gdsc *gcc_sc8280xp_gdscs[] = {
[USB30_SEC_GDSC] = &usb30_sec_gdsc,
[EMAC_0_GDSC] = &emac_0_gdsc,
[EMAC_1_GDSC] = &emac_1_gdsc,
+ [USB4_1_GDSC] = &usb4_1_gdsc,
+ [USB4_GDSC] = &usb4_gdsc,
+ [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
+ [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
+ [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc,
+ [HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc,
+ [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
+ [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
+ [HLOS1_VOTE_TURING_MMU_TBU2_GDSC] = &hlos1_vote_turing_mmu_tbu2_gdsc,
+ [HLOS1_VOTE_TURING_MMU_TBU3_GDSC] = &hlos1_vote_turing_mmu_tbu3_gdsc,
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
@@ -7432,8 +7539,8 @@ static int gcc_sc8280xp_probe(struct platform_device *pdev)
regmap = qcom_cc_map(pdev, &gcc_sc8280xp_desc);
if (IS_ERR(regmap)) {
- pm_runtime_put(&pdev->dev);
- return PTR_ERR(regmap);
+ ret = PTR_ERR(regmap);
+ goto err_put_rpm;
}
/*
@@ -7454,11 +7561,19 @@ static int gcc_sc8280xp_probe(struct platform_device *pdev)
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
- return ret;
+ goto err_put_rpm;
ret = qcom_cc_really_probe(pdev, &gcc_sc8280xp_desc, regmap);
+ if (ret)
+ goto err_put_rpm;
+
pm_runtime_put(&pdev->dev);
+ return 0;
+
+err_put_rpm:
+ pm_runtime_put_sync(&pdev->dev);
+
return ret;
}
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
index 6afce8e42ede..c4fe70871b6d 100644
--- a/drivers/clk/qcom/gcc-sdm660.c
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -10,7 +10,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index 6af08e0ca847..725cd52d2398 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -9,7 +9,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
diff --git a/drivers/clk/qcom/gcc-sdx65.c b/drivers/clk/qcom/gcc-sdx65.c
index b0c17043551d..ffddbed5a6db 100644
--- a/drivers/clk/qcom/gcc-sdx65.c
+++ b/drivers/clk/qcom/gcc-sdx65.c
@@ -7,8 +7,8 @@
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/of_device.h>
#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-sdx65.h>
diff --git a/drivers/clk/qcom/gcc-sdx75.c b/drivers/clk/qcom/gcc-sdx75.c
index b6772abdcec5..573af17bd24c 100644
--- a/drivers/clk/qcom/gcc-sdx75.c
+++ b/drivers/clk/qcom/gcc-sdx75.c
@@ -4,8 +4,9 @@
*/
#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sdx75-gcc.h>
diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c
index 033e308ff865..13e521cd4259 100644
--- a/drivers/clk/qcom/gcc-sm6115.c
+++ b/drivers/clk/qcom/gcc-sm6115.c
@@ -6,7 +6,8 @@
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
diff --git a/drivers/clk/qcom/gcc-sm6125.c b/drivers/clk/qcom/gcc-sm6125.c
index 40ad062d1bf7..da554efee2ce 100644
--- a/drivers/clk/qcom/gcc-sm6125.c
+++ b/drivers/clk/qcom/gcc-sm6125.c
@@ -8,7 +8,6 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
diff --git a/drivers/clk/qcom/gcc-sm6350.c b/drivers/clk/qcom/gcc-sm6350.c
index 9b4e4bb05963..cf4a7b6e0b23 100644
--- a/drivers/clk/qcom/gcc-sm6350.c
+++ b/drivers/clk/qcom/gcc-sm6350.c
@@ -641,6 +641,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
+ .flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_floor_ops,
},
};
diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c
index 417a0fd242ec..3dd15d765b22 100644
--- a/drivers/clk/qcom/gcc-sm6375.c
+++ b/drivers/clk/qcom/gcc-sm6375.c
@@ -6,7 +6,8 @@
#include <linux/clk-provider.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm6375-gcc.h>
diff --git a/drivers/clk/qcom/gcc-sm7150.c b/drivers/clk/qcom/gcc-sm7150.c
index 6b628178f62c..d9983bb27475 100644
--- a/drivers/clk/qcom/gcc-sm7150.c
+++ b/drivers/clk/qcom/gcc-sm7150.c
@@ -8,9 +8,9 @@
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm7150-gcc.h>
@@ -739,6 +739,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_floor_ops,
+ .flags = CLK_OPS_PARENT_ENABLE,
},
};
diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
index 70b067f3618c..41ab210875fb 100644
--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -7,7 +7,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
diff --git a/drivers/clk/qcom/gcc-sm8250.c b/drivers/clk/qcom/gcc-sm8250.c
index b6cf4bc88d4d..c6c5261264f1 100644
--- a/drivers/clk/qcom/gcc-sm8250.c
+++ b/drivers/clk/qcom/gcc-sm8250.c
@@ -7,8 +7,8 @@
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/of_device.h>
#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
@@ -721,6 +721,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
+ .flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_floor_ops,
},
};
diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c
index 75635d40a12d..563542982551 100644
--- a/drivers/clk/qcom/gcc-sm8450.c
+++ b/drivers/clk/qcom/gcc-sm8450.c
@@ -6,7 +6,8 @@
#include <linux/clk-provider.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
@@ -935,7 +936,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.flags = CLK_SET_RATE_PARENT,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
@@ -958,7 +959,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c
index 277cd4f020ff..586126c4dd90 100644
--- a/drivers/clk/qcom/gcc-sm8550.c
+++ b/drivers/clk/qcom/gcc-sm8550.c
@@ -7,7 +7,8 @@
#include <linux/clk-provider.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
diff --git a/drivers/clk/qcom/gpucc-msm8998.c b/drivers/clk/qcom/gpucc-msm8998.c
index f929e0f2333f..9a4fdff719ec 100644
--- a/drivers/clk/qcom/gpucc-msm8998.c
+++ b/drivers/clk/qcom/gpucc-msm8998.c
@@ -9,7 +9,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
@@ -98,7 +97,7 @@ static const struct parent_map gpu_xo_gpll0_map[] = {
static const struct clk_parent_data gpu_xo_gpll0[] = {
{ .hw = &gpucc_cxo_clk.clkr.hw },
- { .fw_name = "gpll0" },
+ { .fw_name = "gpll0", .name = "gcc_gpu_gpll0_clk" },
};
static const struct parent_map gpu_xo_gpupll0_map[] = {
diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c
index 18d23be8d435..26ecfa63be19 100644
--- a/drivers/clk/qcom/gpucc-sa8775p.c
+++ b/drivers/clk/qcom/gpucc-sa8775p.c
@@ -7,9 +7,9 @@
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/of_device.h>
-#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c
index d6b38a0b063d..459f123a6720 100644
--- a/drivers/clk/qcom/gpucc-sdm660.c
+++ b/drivers/clk/qcom/gpucc-sdm660.c
@@ -13,7 +13,6 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gpucc-sdm660.h>
diff --git a/drivers/clk/qcom/gpucc-sm6115.c b/drivers/clk/qcom/gpucc-sm6115.c
index c84727e8352d..fb71c21c9a89 100644
--- a/drivers/clk/qcom/gpucc-sm6115.c
+++ b/drivers/clk/qcom/gpucc-sm6115.c
@@ -5,8 +5,9 @@
*/
#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm6115-gpucc.h>
diff --git a/drivers/clk/qcom/gpucc-sm6125.c b/drivers/clk/qcom/gpucc-sm6125.c
index d4f1296a48ef..61959ba02f9a 100644
--- a/drivers/clk/qcom/gpucc-sm6125.c
+++ b/drivers/clk/qcom/gpucc-sm6125.c
@@ -5,8 +5,9 @@
*/
#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm6125-gpucc.h>
diff --git a/drivers/clk/qcom/gpucc-sm6350.c b/drivers/clk/qcom/gpucc-sm6350.c
index ef15185a99c3..0bcbba2a2943 100644
--- a/drivers/clk/qcom/gpucc-sm6350.c
+++ b/drivers/clk/qcom/gpucc-sm6350.c
@@ -25,6 +25,12 @@
#define CX_GMU_CBCR_WAKE_SHIFT 8
enum {
+ DT_BI_TCXO,
+ DT_GPLL0_OUT_MAIN,
+ DT_GPLL0_OUT_MAIN_DIV,
+};
+
+enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
@@ -61,6 +67,7 @@ static struct clk_alpha_pll gpu_cc_pll0 = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll0",
.parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO,
.fw_name = "bi_tcxo",
},
.num_parents = 1,
@@ -104,6 +111,7 @@ static struct clk_alpha_pll gpu_cc_pll1 = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO,
.fw_name = "bi_tcxo",
},
.num_parents = 1,
@@ -121,11 +129,11 @@ static const struct parent_map gpu_cc_parent_map_0[] = {
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
- { .fw_name = "bi_tcxo" },
+ { .index = DT_BI_TCXO, .fw_name = "bi_tcxo" },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
- { .fw_name = "gcc_gpu_gpll0_clk" },
- { .fw_name = "gcc_gpu_gpll0_div_clk" },
+ { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk_src" },
+ { .index = DT_GPLL0_OUT_MAIN_DIV, .fw_name = "gcc_gpu_gpll0_div_clk_src" },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
@@ -138,12 +146,12 @@ static const struct parent_map gpu_cc_parent_map_1[] = {
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
- { .fw_name = "bi_tcxo" },
+ { .index = DT_BI_TCXO, .fw_name = "bi_tcxo" },
{ .hw = &crc_div.hw },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
- { .fw_name = "gcc_gpu_gpll0_clk" },
+ { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk_src" },
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
diff --git a/drivers/clk/qcom/gpucc-sm6375.c b/drivers/clk/qcom/gpucc-sm6375.c
index 2d863dc3d83b..da24276a018e 100644
--- a/drivers/clk/qcom/gpucc-sm6375.c
+++ b/drivers/clk/qcom/gpucc-sm6375.c
@@ -5,8 +5,9 @@
*/
#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm8350.c
index 5367ce654ac9..8dc54dff983f 100644
--- a/drivers/clk/qcom/gpucc-sm8350.c
+++ b/drivers/clk/qcom/gpucc-sm8350.c
@@ -8,8 +8,8 @@
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/of_device.h>
#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gpucc-sm8350.h>
diff --git a/drivers/clk/qcom/gpucc-sm8450.c b/drivers/clk/qcom/gpucc-sm8450.c
index 16c0381b3087..1c4769b646b0 100644
--- a/drivers/clk/qcom/gpucc-sm8450.c
+++ b/drivers/clk/qcom/gpucc-sm8450.c
@@ -4,8 +4,9 @@
*/
#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8450-gpucc.h>
diff --git a/drivers/clk/qcom/gpucc-sm8550.c b/drivers/clk/qcom/gpucc-sm8550.c
index 8a2e3522af51..775e0b931923 100644
--- a/drivers/clk/qcom/gpucc-sm8550.c
+++ b/drivers/clk/qcom/gpucc-sm8550.c
@@ -4,8 +4,9 @@
*/
#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8550-gpucc.h>
diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c
index 81a44a9a9abc..fa8cda63cf20 100644
--- a/drivers/clk/qcom/lcc-ipq806x.c
+++ b/drivers/clk/qcom/lcc-ipq806x.c
@@ -9,7 +9,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
diff --git a/drivers/clk/qcom/lcc-mdm9615.c b/drivers/clk/qcom/lcc-mdm9615.c
deleted file mode 100644
index 8d243e880d95..000000000000
--- a/drivers/clk/qcom/lcc-mdm9615.c
+++ /dev/null
@@ -1,572 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2014, The Linux Foundation. All rights reserved.
- * Copyright (c) BayLibre, SAS.
- * Author : Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/bitops.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/clk-provider.h>
-#include <linux/regmap.h>
-
-#include <dt-bindings/clock/qcom,lcc-mdm9615.h>
-
-#include "common.h"
-#include "clk-regmap.h"
-#include "clk-pll.h"
-#include "clk-rcg.h"
-#include "clk-branch.h"
-#include "clk-regmap-divider.h"
-#include "clk-regmap-mux.h"
-
-static struct clk_pll pll4 = {
- .l_reg = 0x4,
- .m_reg = 0x8,
- .n_reg = 0xc,
- .config_reg = 0x14,
- .mode_reg = 0x0,
- .status_reg = 0x18,
- .status_bit = 16,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pll4",
- .parent_names = (const char *[]){ "cxo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-enum {
- P_CXO,
- P_PLL4,
-};
-
-static const struct parent_map lcc_cxo_pll4_map[] = {
- { P_CXO, 0 },
- { P_PLL4, 2 }
-};
-
-static const char * const lcc_cxo_pll4[] = {
- "cxo",
- "pll4_vote",
-};
-
-static struct freq_tbl clk_tbl_aif_osr_492[] = {
- { 512000, P_PLL4, 4, 1, 240 },
- { 768000, P_PLL4, 4, 1, 160 },
- { 1024000, P_PLL4, 4, 1, 120 },
- { 1536000, P_PLL4, 4, 1, 80 },
- { 2048000, P_PLL4, 4, 1, 60 },
- { 3072000, P_PLL4, 4, 1, 40 },
- { 4096000, P_PLL4, 4, 1, 30 },
- { 6144000, P_PLL4, 4, 1, 20 },
- { 8192000, P_PLL4, 4, 1, 15 },
- { 12288000, P_PLL4, 4, 1, 10 },
- { 24576000, P_PLL4, 4, 1, 5 },
- { 27000000, P_CXO, 1, 0, 0 },
- { }
-};
-
-static struct freq_tbl clk_tbl_aif_osr_393[] = {
- { 512000, P_PLL4, 4, 1, 192 },
- { 768000, P_PLL4, 4, 1, 128 },
- { 1024000, P_PLL4, 4, 1, 96 },
- { 1536000, P_PLL4, 4, 1, 64 },
- { 2048000, P_PLL4, 4, 1, 48 },
- { 3072000, P_PLL4, 4, 1, 32 },
- { 4096000, P_PLL4, 4, 1, 24 },
- { 6144000, P_PLL4, 4, 1, 16 },
- { 8192000, P_PLL4, 4, 1, 12 },
- { 12288000, P_PLL4, 4, 1, 8 },
- { 24576000, P_PLL4, 4, 1, 4 },
- { 27000000, P_CXO, 1, 0, 0 },
- { }
-};
-
-static struct clk_rcg mi2s_osr_src = {
- .ns_reg = 0x48,
- .md_reg = 0x4c,
- .mn = {
- .mnctr_en_bit = 8,
- .mnctr_reset_bit = 7,
- .mnctr_mode_shift = 5,
- .n_val_shift = 24,
- .m_val_shift = 8,
- .width = 8,
- },
- .p = {
- .pre_div_shift = 3,
- .pre_div_width = 2,
- },
- .s = {
- .src_sel_shift = 0,
- .parent_map = lcc_cxo_pll4_map,
- },
- .freq_tbl = clk_tbl_aif_osr_393,
- .clkr = {
- .enable_reg = 0x48,
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "mi2s_osr_src",
- .parent_names = lcc_cxo_pll4,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
- },
- },
-};
-
-static const char * const lcc_mi2s_parents[] = {
- "mi2s_osr_src",
-};
-
-static struct clk_branch mi2s_osr_clk = {
- .halt_reg = 0x50,
- .halt_bit = 1,
- .halt_check = BRANCH_HALT_ENABLE,
- .clkr = {
- .enable_reg = 0x48,
- .enable_mask = BIT(17),
- .hw.init = &(struct clk_init_data){
- .name = "mi2s_osr_clk",
- .parent_names = lcc_mi2s_parents,
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
- },
-};
-
-static struct clk_regmap_div mi2s_div_clk = {
- .reg = 0x48,
- .shift = 10,
- .width = 4,
- .clkr = {
- .enable_reg = 0x48,
- .enable_mask = BIT(15),
- .hw.init = &(struct clk_init_data){
- .name = "mi2s_div_clk",
- .parent_names = lcc_mi2s_parents,
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- },
- },
-};
-
-static struct clk_branch mi2s_bit_div_clk = {
- .halt_reg = 0x50,
- .halt_bit = 0,
- .halt_check = BRANCH_HALT_ENABLE,
- .clkr = {
- .enable_reg = 0x48,
- .enable_mask = BIT(15),
- .hw.init = &(struct clk_init_data){
- .name = "mi2s_bit_div_clk",
- .parent_names = (const char *[]){ "mi2s_div_clk" },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
- },
-};
-
-static struct clk_regmap_mux mi2s_bit_clk = {
- .reg = 0x48,
- .shift = 14,
- .width = 1,
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "mi2s_bit_clk",
- .parent_names = (const char *[]){
- "mi2s_bit_div_clk",
- "mi2s_codec_clk",
- },
- .num_parents = 2,
- .ops = &clk_regmap_mux_closest_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
- },
-};
-
-#define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr) \
-static struct clk_rcg prefix##_osr_src = { \
- .ns_reg = _ns, \
- .md_reg = _md, \
- .mn = { \
- .mnctr_en_bit = 8, \
- .mnctr_reset_bit = 7, \
- .mnctr_mode_shift = 5, \
- .n_val_shift = 24, \
- .m_val_shift = 8, \
- .width = 8, \
- }, \
- .p = { \
- .pre_div_shift = 3, \
- .pre_div_width = 2, \
- }, \
- .s = { \
- .src_sel_shift = 0, \
- .parent_map = lcc_cxo_pll4_map, \
- }, \
- .freq_tbl = clk_tbl_aif_osr_393, \
- .clkr = { \
- .enable_reg = _ns, \
- .enable_mask = BIT(9), \
- .hw.init = &(struct clk_init_data){ \
- .name = #prefix "_osr_src", \
- .parent_names = lcc_cxo_pll4, \
- .num_parents = 2, \
- .ops = &clk_rcg_ops, \
- .flags = CLK_SET_RATE_GATE, \
- }, \
- }, \
-}; \
- \
-static const char * const lcc_##prefix##_parents[] = { \
- #prefix "_osr_src", \
-}; \
- \
-static struct clk_branch prefix##_osr_clk = { \
- .halt_reg = hr, \
- .halt_bit = 1, \
- .halt_check = BRANCH_HALT_ENABLE, \
- .clkr = { \
- .enable_reg = _ns, \
- .enable_mask = BIT(21), \
- .hw.init = &(struct clk_init_data){ \
- .name = #prefix "_osr_clk", \
- .parent_names = lcc_##prefix##_parents, \
- .num_parents = 1, \
- .ops = &clk_branch_ops, \
- .flags = CLK_SET_RATE_PARENT, \
- }, \
- }, \
-}; \
- \
-static struct clk_regmap_div prefix##_div_clk = { \
- .reg = _ns, \
- .shift = 10, \
- .width = 8, \
- .clkr = { \
- .hw.init = &(struct clk_init_data){ \
- .name = #prefix "_div_clk", \
- .parent_names = lcc_##prefix##_parents, \
- .num_parents = 1, \
- .ops = &clk_regmap_div_ops, \
- }, \
- }, \
-}; \
- \
-static struct clk_branch prefix##_bit_div_clk = { \
- .halt_reg = hr, \
- .halt_bit = 0, \
- .halt_check = BRANCH_HALT_ENABLE, \
- .clkr = { \
- .enable_reg = _ns, \
- .enable_mask = BIT(19), \
- .hw.init = &(struct clk_init_data){ \
- .name = #prefix "_bit_div_clk", \
- .parent_names = (const char *[]){ \
- #prefix "_div_clk" \
- }, \
- .num_parents = 1, \
- .ops = &clk_branch_ops, \
- .flags = CLK_SET_RATE_PARENT, \
- }, \
- }, \
-}; \
- \
-static struct clk_regmap_mux prefix##_bit_clk = { \
- .reg = _ns, \
- .shift = 18, \
- .width = 1, \
- .clkr = { \
- .hw.init = &(struct clk_init_data){ \
- .name = #prefix "_bit_clk", \
- .parent_names = (const char *[]){ \
- #prefix "_bit_div_clk", \
- #prefix "_codec_clk", \
- }, \
- .num_parents = 2, \
- .ops = &clk_regmap_mux_closest_ops, \
- .flags = CLK_SET_RATE_PARENT, \
- }, \
- }, \
-}
-
-CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68);
-CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80);
-CLK_AIF_OSR_DIV(codec_i2s_spkr, 0x6c, 0x70, 0x74);
-CLK_AIF_OSR_DIV(spare_i2s_spkr, 0x84, 0x88, 0x8c);
-
-static struct freq_tbl clk_tbl_pcm_492[] = {
- { 256000, P_PLL4, 4, 1, 480 },
- { 512000, P_PLL4, 4, 1, 240 },
- { 768000, P_PLL4, 4, 1, 160 },
- { 1024000, P_PLL4, 4, 1, 120 },
- { 1536000, P_PLL4, 4, 1, 80 },
- { 2048000, P_PLL4, 4, 1, 60 },
- { 3072000, P_PLL4, 4, 1, 40 },
- { 4096000, P_PLL4, 4, 1, 30 },
- { 6144000, P_PLL4, 4, 1, 20 },
- { 8192000, P_PLL4, 4, 1, 15 },
- { 12288000, P_PLL4, 4, 1, 10 },
- { 24576000, P_PLL4, 4, 1, 5 },
- { 27000000, P_CXO, 1, 0, 0 },
- { }
-};
-
-static struct freq_tbl clk_tbl_pcm_393[] = {
- { 256000, P_PLL4, 4, 1, 384 },
- { 512000, P_PLL4, 4, 1, 192 },
- { 768000, P_PLL4, 4, 1, 128 },
- { 1024000, P_PLL4, 4, 1, 96 },
- { 1536000, P_PLL4, 4, 1, 64 },
- { 2048000, P_PLL4, 4, 1, 48 },
- { 3072000, P_PLL4, 4, 1, 32 },
- { 4096000, P_PLL4, 4, 1, 24 },
- { 6144000, P_PLL4, 4, 1, 16 },
- { 8192000, P_PLL4, 4, 1, 12 },
- { 12288000, P_PLL4, 4, 1, 8 },
- { 24576000, P_PLL4, 4, 1, 4 },
- { 27000000, P_CXO, 1, 0, 0 },
- { }
-};
-
-static struct clk_rcg pcm_src = {
- .ns_reg = 0x54,
- .md_reg = 0x58,
- .mn = {
- .mnctr_en_bit = 8,
- .mnctr_reset_bit = 7,
- .mnctr_mode_shift = 5,
- .n_val_shift = 16,
- .m_val_shift = 16,
- .width = 16,
- },
- .p = {
- .pre_div_shift = 3,
- .pre_div_width = 2,
- },
- .s = {
- .src_sel_shift = 0,
- .parent_map = lcc_cxo_pll4_map,
- },
- .freq_tbl = clk_tbl_pcm_393,
- .clkr = {
- .enable_reg = 0x54,
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "pcm_src",
- .parent_names = lcc_cxo_pll4,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
- },
- },
-};
-
-static struct clk_branch pcm_clk_out = {
- .halt_reg = 0x5c,
- .halt_bit = 0,
- .halt_check = BRANCH_HALT_ENABLE,
- .clkr = {
- .enable_reg = 0x54,
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "pcm_clk_out",
- .parent_names = (const char *[]){ "pcm_src" },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
- },
-};
-
-static struct clk_regmap_mux pcm_clk = {
- .reg = 0x54,
- .shift = 10,
- .width = 1,
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "pcm_clk",
- .parent_names = (const char *[]){
- "pcm_clk_out",
- "pcm_codec_clk",
- },
- .num_parents = 2,
- .ops = &clk_regmap_mux_closest_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
- },
-};
-
-static struct clk_rcg slimbus_src = {
- .ns_reg = 0xcc,
- .md_reg = 0xd0,
- .mn = {
- .mnctr_en_bit = 8,
- .mnctr_reset_bit = 7,
- .mnctr_mode_shift = 5,
- .n_val_shift = 24,
- .m_val_shift = 8,
- .width = 8,
- },
- .p = {
- .pre_div_shift = 3,
- .pre_div_width = 2,
- },
- .s = {
- .src_sel_shift = 0,
- .parent_map = lcc_cxo_pll4_map,
- },
- .freq_tbl = clk_tbl_aif_osr_393,
- .clkr = {
- .enable_reg = 0xcc,
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "slimbus_src",
- .parent_names = lcc_cxo_pll4,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
- },
- },
-};
-
-static const char * const lcc_slimbus_parents[] = {
- "slimbus_src",
-};
-
-static struct clk_branch audio_slimbus_clk = {
- .halt_reg = 0xd4,
- .halt_bit = 0,
- .halt_check = BRANCH_HALT_ENABLE,
- .clkr = {
- .enable_reg = 0xcc,
- .enable_mask = BIT(10),
- .hw.init = &(struct clk_init_data){
- .name = "audio_slimbus_clk",
- .parent_names = lcc_slimbus_parents,
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
- },
-};
-
-static struct clk_branch sps_slimbus_clk = {
- .halt_reg = 0xd4,
- .halt_bit = 1,
- .halt_check = BRANCH_HALT_ENABLE,
- .clkr = {
- .enable_reg = 0xcc,
- .enable_mask = BIT(12),
- .hw.init = &(struct clk_init_data){
- .name = "sps_slimbus_clk",
- .parent_names = lcc_slimbus_parents,
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
- },
-};
-
-static struct clk_regmap *lcc_mdm9615_clks[] = {
- [PLL4] = &pll4.clkr,
- [MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
- [MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
- [MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
- [MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
- [MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
- [PCM_SRC] = &pcm_src.clkr,
- [PCM_CLK_OUT] = &pcm_clk_out.clkr,
- [PCM_CLK] = &pcm_clk.clkr,
- [SLIMBUS_SRC] = &slimbus_src.clkr,
- [AUDIO_SLIMBUS_CLK] = &audio_slimbus_clk.clkr,
- [SPS_SLIMBUS_CLK] = &sps_slimbus_clk.clkr,
- [CODEC_I2S_MIC_OSR_SRC] = &codec_i2s_mic_osr_src.clkr,
- [CODEC_I2S_MIC_OSR_CLK] = &codec_i2s_mic_osr_clk.clkr,
- [CODEC_I2S_MIC_DIV_CLK] = &codec_i2s_mic_div_clk.clkr,
- [CODEC_I2S_MIC_BIT_DIV_CLK] = &codec_i2s_mic_bit_div_clk.clkr,
- [CODEC_I2S_MIC_BIT_CLK] = &codec_i2s_mic_bit_clk.clkr,
- [SPARE_I2S_MIC_OSR_SRC] = &spare_i2s_mic_osr_src.clkr,
- [SPARE_I2S_MIC_OSR_CLK] = &spare_i2s_mic_osr_clk.clkr,
- [SPARE_I2S_MIC_DIV_CLK] = &spare_i2s_mic_div_clk.clkr,
- [SPARE_I2S_MIC_BIT_DIV_CLK] = &spare_i2s_mic_bit_div_clk.clkr,
- [SPARE_I2S_MIC_BIT_CLK] = &spare_i2s_mic_bit_clk.clkr,
- [CODEC_I2S_SPKR_OSR_SRC] = &codec_i2s_spkr_osr_src.clkr,
- [CODEC_I2S_SPKR_OSR_CLK] = &codec_i2s_spkr_osr_clk.clkr,
- [CODEC_I2S_SPKR_DIV_CLK] = &codec_i2s_spkr_div_clk.clkr,
- [CODEC_I2S_SPKR_BIT_DIV_CLK] = &codec_i2s_spkr_bit_div_clk.clkr,
- [CODEC_I2S_SPKR_BIT_CLK] = &codec_i2s_spkr_bit_clk.clkr,
- [SPARE_I2S_SPKR_OSR_SRC] = &spare_i2s_spkr_osr_src.clkr,
- [SPARE_I2S_SPKR_OSR_CLK] = &spare_i2s_spkr_osr_clk.clkr,
- [SPARE_I2S_SPKR_DIV_CLK] = &spare_i2s_spkr_div_clk.clkr,
- [SPARE_I2S_SPKR_BIT_DIV_CLK] = &spare_i2s_spkr_bit_div_clk.clkr,
- [SPARE_I2S_SPKR_BIT_CLK] = &spare_i2s_spkr_bit_clk.clkr,
-};
-
-static const struct regmap_config lcc_mdm9615_regmap_config = {
- .reg_bits = 32,
- .reg_stride = 4,
- .val_bits = 32,
- .max_register = 0xfc,
- .fast_io = true,
-};
-
-static const struct qcom_cc_desc lcc_mdm9615_desc = {
- .config = &lcc_mdm9615_regmap_config,
- .clks = lcc_mdm9615_clks,
- .num_clks = ARRAY_SIZE(lcc_mdm9615_clks),
-};
-
-static const struct of_device_id lcc_mdm9615_match_table[] = {
- { .compatible = "qcom,lcc-mdm9615" },
- { }
-};
-MODULE_DEVICE_TABLE(of, lcc_mdm9615_match_table);
-
-static int lcc_mdm9615_probe(struct platform_device *pdev)
-{
- u32 val;
- struct regmap *regmap;
-
- regmap = qcom_cc_map(pdev, &lcc_mdm9615_desc);
- if (IS_ERR(regmap))
- return PTR_ERR(regmap);
-
- /* Use the correct frequency plan depending on speed of PLL4 */
- regmap_read(regmap, 0x4, &val);
- if (val == 0x12) {
- slimbus_src.freq_tbl = clk_tbl_aif_osr_492;
- mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492;
- codec_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
- spare_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
- codec_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
- spare_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
- pcm_src.freq_tbl = clk_tbl_pcm_492;
- }
- /* Enable PLL4 source on the LPASS Primary PLL Mux */
- regmap_write(regmap, 0xc4, 0x1);
-
- return qcom_cc_really_probe(pdev, &lcc_mdm9615_desc, regmap);
-}
-
-static struct platform_driver lcc_mdm9615_driver = {
- .probe = lcc_mdm9615_probe,
- .driver = {
- .name = "lcc-mdm9615",
- .of_match_table = lcc_mdm9615_match_table,
- },
-};
-module_platform_driver(lcc_mdm9615_driver);
-
-MODULE_DESCRIPTION("QCOM LCC MDM9615 Driver");
-MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("platform:lcc-mdm9615");
diff --git a/drivers/clk/qcom/lcc-msm8960.c b/drivers/clk/qcom/lcc-msm8960.c
index 3926184cc91b..e725e7b9c456 100644
--- a/drivers/clk/qcom/lcc-msm8960.c
+++ b/drivers/clk/qcom/lcc-msm8960.c
@@ -9,7 +9,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
@@ -23,6 +22,10 @@
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
+static struct clk_parent_data pxo_parent_data = {
+ .fw_name = "pxo", .name = "pxo_board",
+};
+
static struct clk_pll pll4 = {
.l_reg = 0x4,
.m_reg = 0x8,
@@ -33,9 +36,7 @@ static struct clk_pll pll4 = {
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll4",
- .parent_data = (const struct clk_parent_data[]){
- { .fw_name = "pxo", .name = "pxo_board" },
- },
+ .parent_data = &pxo_parent_data,
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -51,7 +52,7 @@ static const struct parent_map lcc_pxo_pll4_map[] = {
{ P_PLL4, 2 }
};
-static const struct clk_parent_data lcc_pxo_pll4[] = {
+static struct clk_parent_data lcc_pxo_pll4[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .fw_name = "pll4_vote", .name = "pll4_vote" },
};
@@ -444,6 +445,7 @@ static const struct qcom_cc_desc lcc_msm8960_desc = {
static const struct of_device_id lcc_msm8960_match_table[] = {
{ .compatible = "qcom,lcc-msm8960" },
{ .compatible = "qcom,lcc-apq8064" },
+ { .compatible = "qcom,lcc-mdm9615" },
{ }
};
MODULE_DEVICE_TABLE(of, lcc_msm8960_match_table);
@@ -453,6 +455,14 @@ static int lcc_msm8960_probe(struct platform_device *pdev)
u32 val;
struct regmap *regmap;
+ /* patch for the cxo <-> pxo difference */
+ if (of_device_is_compatible(pdev->dev.of_node, "qcom,lcc-mdm9615")) {
+ pxo_parent_data.fw_name = "cxo";
+ pxo_parent_data.name = "cxo_board";
+ lcc_pxo_pll4[0].fw_name = "cxo";
+ lcc_pxo_pll4[0].name = "cxo_board";
+ }
+
regmap = qcom_cc_map(pdev, &lcc_msm8960_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
diff --git a/drivers/clk/qcom/lpass-gfm-sm8250.c b/drivers/clk/qcom/lpass-gfm-sm8250.c
index 96f476f24eb2..8a1ee52cbcc3 100644
--- a/drivers/clk/qcom/lpass-gfm-sm8250.c
+++ b/drivers/clk/qcom/lpass-gfm-sm8250.c
@@ -15,8 +15,8 @@
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
-#include <linux/of_device.h>
#include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
#include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c
index 134eb1529ede..c43d0b1af7f7 100644
--- a/drivers/clk/qcom/lpassaudiocc-sc7280.c
+++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c
@@ -7,7 +7,8 @@
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-sc7280.c
index 0df2b29e95e3..e6b815aec46a 100644
--- a/drivers/clk/qcom/lpasscc-sc7280.c
+++ b/drivers/clk/qcom/lpasscc-sc7280.c
@@ -118,9 +118,13 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev)
ret = pm_clk_add(&pdev->dev, "iface");
if (ret < 0) {
dev_err(&pdev->dev, "failed to acquire iface clock\n");
- goto destroy_pm_clk;
+ goto err_destroy_pm_clk;
}
+ ret = pm_runtime_resume_and_get(&pdev->dev);
+ if (ret)
+ goto err_destroy_pm_clk;
+
if (!of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) {
lpass_regmap_config.name = "qdsp6ss";
lpass_regmap_config.max_register = 0x3f;
@@ -128,7 +132,7 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev)
ret = qcom_cc_probe_by_index(pdev, 0, desc);
if (ret)
- goto destroy_pm_clk;
+ goto err_put_rpm;
}
lpass_regmap_config.name = "top_cc";
@@ -137,11 +141,15 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev)
ret = qcom_cc_probe_by_index(pdev, 1, desc);
if (ret)
- goto destroy_pm_clk;
+ goto err_put_rpm;
+
+ pm_runtime_put(&pdev->dev);
return 0;
-destroy_pm_clk:
+err_put_rpm:
+ pm_runtime_put_sync(&pdev->dev);
+err_destroy_pm_clk:
pm_clk_destroy(&pdev->dev);
return ret;
diff --git a/drivers/clk/qcom/lpasscc-sc8280xp.c b/drivers/clk/qcom/lpasscc-sc8280xp.c
index 43b37ce397cf..3693e47d548e 100644
--- a/drivers/clk/qcom/lpasscc-sc8280xp.c
+++ b/drivers/clk/qcom/lpasscc-sc8280xp.c
@@ -6,8 +6,10 @@
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c b/drivers/clk/qcom/lpasscorecc-sc7180.c
index 010867dcc2ef..9051fd567112 100644
--- a/drivers/clk/qcom/lpasscorecc-sc7180.c
+++ b/drivers/clk/qcom/lpasscorecc-sc7180.c
@@ -6,7 +6,7 @@
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
diff --git a/drivers/clk/qcom/lpasscorecc-sc7280.c b/drivers/clk/qcom/lpasscorecc-sc7280.c
index 6ad19b06b1ce..a2f1e6ad6da4 100644
--- a/drivers/clk/qcom/lpasscorecc-sc7280.c
+++ b/drivers/clk/qcom/lpasscorecc-sc7280.c
@@ -6,7 +6,8 @@
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index 82f6bad144a9..1f3bd302fe6e 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -9,7 +9,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
@@ -2426,6 +2425,16 @@ static struct gdsc oxilicx_gdsc = {
.pwrsts = PWRSTS_OFF_ON,
};
+static struct gdsc oxili_cx_gdsc_msm8226 = {
+ .gdscr = 0x4034,
+ .cxcs = (unsigned int []){ 0x4028 },
+ .cxc_count = 1,
+ .pd = {
+ .name = "oxili_cx",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
static struct clk_regmap *mmcc_msm8226_clocks[] = {
[MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
[MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
@@ -2515,6 +2524,7 @@ static struct gdsc *mmcc_msm8226_gdscs[] = {
[MDSS_GDSC] = &mdss_gdsc,
[CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
[CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
+ [OXILICX_GDSC] = &oxili_cx_gdsc_msm8226,
};
static const struct regmap_config mmcc_msm8226_regmap_config = {
diff --git a/drivers/clk/qcom/mmcc-msm8994.c b/drivers/clk/qcom/mmcc-msm8994.c
index 89c5f5fa7d9a..3229ff77372f 100644
--- a/drivers/clk/qcom/mmcc-msm8994.c
+++ b/drivers/clk/qcom/mmcc-msm8994.c
@@ -9,7 +9,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
index 80330dab4d81..d3f2dc798567 100644
--- a/drivers/clk/qcom/mmcc-msm8996.c
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -9,7 +9,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
diff --git a/drivers/clk/qcom/mmcc-msm8998.c b/drivers/clk/qcom/mmcc-msm8998.c
index 4490594bde69..a023c4374be9 100644
--- a/drivers/clk/qcom/mmcc-msm8998.c
+++ b/drivers/clk/qcom/mmcc-msm8998.c
@@ -9,7 +9,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
@@ -46,19 +45,6 @@ enum {
P_DPLINK,
};
-static struct clk_fixed_factor gpll0_div = {
- .mult = 1,
- .div = 2,
- .hw.init = &(struct clk_init_data){
- .name = "mmss_gpll0_div",
- .parent_data = &(const struct clk_parent_data){
- .fw_name = "gpll0"
- },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- },
-};
-
static const struct clk_div_table post_div_table_fabia_even[] = {
{ 0x0, 1 },
{ 0x1, 2 },
@@ -354,7 +340,7 @@ static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = {
{ .fw_name = "xo" },
{ .fw_name = "gpll0" },
- { .hw = &gpll0_div.hw },
+ { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
};
static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
@@ -368,7 +354,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = {
{ .fw_name = "xo" },
{ .hw = &mmpll0_out_even.clkr.hw },
{ .fw_name = "gpll0" },
- { .hw = &gpll0_div.hw },
+ { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
};
static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
@@ -384,7 +370,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
{ .hw = &mmpll0_out_even.clkr.hw },
{ .hw = &mmpll1_out_even.clkr.hw },
{ .fw_name = "gpll0" },
- { .hw = &gpll0_div.hw },
+ { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
};
static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
@@ -400,7 +386,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
{ .hw = &mmpll0_out_even.clkr.hw },
{ .hw = &mmpll5_out_even.clkr.hw },
{ .fw_name = "gpll0" },
- { .hw = &gpll0_div.hw },
+ { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
};
static const struct parent_map mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map[] = {
@@ -418,7 +404,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div
{ .hw = &mmpll3_out_even.clkr.hw },
{ .hw = &mmpll6_out_even.clkr.hw },
{ .fw_name = "gpll0" },
- { .hw = &gpll0_div.hw },
+ { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
};
static const struct parent_map mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
@@ -436,7 +422,7 @@ static const struct clk_parent_data mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_di
{ .hw = &mmpll7_out_even.clkr.hw },
{ .hw = &mmpll10_out_even.clkr.hw },
{ .fw_name = "gpll0" },
- { .hw = &gpll0_div.hw },
+ { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
};
static const struct parent_map mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
@@ -454,7 +440,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_di
{ .hw = &mmpll7_out_even.clkr.hw },
{ .hw = &mmpll10_out_even.clkr.hw },
{ .fw_name = "gpll0" },
- { .hw = &gpll0_div.hw },
+ { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
};
static const struct parent_map mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
@@ -474,7 +460,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_g
{ .hw = &mmpll7_out_even.clkr.hw },
{ .hw = &mmpll10_out_even.clkr.hw },
{ .fw_name = "gpll0" },
- { .hw = &gpll0_div.hw },
+ { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
};
static struct clk_rcg2 byte0_clk_src = {
@@ -2544,10 +2530,6 @@ static struct clk_branch vmem_ahb_clk = {
},
};
-static struct clk_hw *mmcc_msm8998_hws[] = {
- &gpll0_div.hw,
-};
-
static struct gdsc video_top_gdsc = {
.gdscr = 0x1024,
.pd = {
@@ -2855,8 +2837,6 @@ static const struct qcom_cc_desc mmcc_msm8998_desc = {
.num_resets = ARRAY_SIZE(mmcc_msm8998_resets),
.gdscs = mmcc_msm8998_gdscs,
.num_gdscs = ARRAY_SIZE(mmcc_msm8998_gdscs),
- .clk_hws = mmcc_msm8998_hws,
- .num_clk_hws = ARRAY_SIZE(mmcc_msm8998_hws),
};
static const struct of_device_id mmcc_msm8998_match_table[] = {
diff --git a/drivers/clk/qcom/mss-sc7180.c b/drivers/clk/qcom/mss-sc7180.c
index 5a1407440662..d106bc65470e 100644
--- a/drivers/clk/qcom/mss-sc7180.c
+++ b/drivers/clk/qcom/mss-sc7180.c
@@ -87,11 +87,22 @@ static int mss_sc7180_probe(struct platform_device *pdev)
return ret;
}
+ ret = pm_runtime_resume_and_get(&pdev->dev);
+ if (ret)
+ return ret;
+
ret = qcom_cc_probe(pdev, &mss_sc7180_desc);
if (ret < 0)
- return ret;
+ goto err_put_rpm;
+
+ pm_runtime_put(&pdev->dev);
return 0;
+
+err_put_rpm:
+ pm_runtime_put_sync(&pdev->dev);
+
+ return ret;
}
static const struct dev_pm_ops mss_sc7180_pm_ops = {
diff --git a/drivers/clk/qcom/q6sstop-qcs404.c b/drivers/clk/qcom/q6sstop-qcs404.c
index 780074e05841..26e2d63614ac 100644
--- a/drivers/clk/qcom/q6sstop-qcs404.c
+++ b/drivers/clk/qcom/q6sstop-qcs404.c
@@ -174,21 +174,32 @@ static int q6sstopcc_qcs404_probe(struct platform_device *pdev)
return ret;
}
+ ret = pm_runtime_resume_and_get(&pdev->dev);
+ if (ret)
+ return ret;
+
q6sstop_regmap_config.name = "q6sstop_tcsr";
desc = &tcsr_qcs404_desc;
ret = qcom_cc_probe_by_index(pdev, 1, desc);
if (ret)
- return ret;
+ goto err_put_rpm;
q6sstop_regmap_config.name = "q6sstop_cc";
desc = &q6sstop_qcs404_desc;
ret = qcom_cc_probe_by_index(pdev, 0, desc);
if (ret)
- return ret;
+ goto err_put_rpm;
+
+ pm_runtime_put(&pdev->dev);
return 0;
+
+err_put_rpm:
+ pm_runtime_put_sync(&pdev->dev);
+
+ return ret;
}
static const struct dev_pm_ops q6sstopcc_pm_ops = {
diff --git a/drivers/clk/qcom/reset.c b/drivers/clk/qcom/reset.c
index 0e914ec7aeae..e45e32804d2c 100644
--- a/drivers/clk/qcom/reset.c
+++ b/drivers/clk/qcom/reset.c
@@ -16,7 +16,8 @@ static int qcom_reset(struct reset_controller_dev *rcdev, unsigned long id)
struct qcom_reset_controller *rst = to_qcom_reset_controller(rcdev);
rcdev->ops->assert(rcdev, id);
- udelay(rst->reset_map[id].udelay ?: 1); /* use 1 us as default */
+ fsleep(rst->reset_map[id].udelay ?: 1); /* use 1 us as default */
+
rcdev->ops->deassert(rcdev, id);
return 0;
}
diff --git a/drivers/clk/qcom/tcsrcc-sm8550.c b/drivers/clk/qcom/tcsrcc-sm8550.c
index 2c67ee71c196..552a3eb1fd91 100644
--- a/drivers/clk/qcom/tcsrcc-sm8550.c
+++ b/drivers/clk/qcom/tcsrcc-sm8550.c
@@ -7,7 +7,8 @@
#include <linux/clk-provider.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8550-tcsr.h>
diff --git a/drivers/clk/qcom/turingcc-qcs404.c b/drivers/clk/qcom/turingcc-qcs404.c
index 43184459228f..2cd288d6c3e4 100644
--- a/drivers/clk/qcom/turingcc-qcs404.c
+++ b/drivers/clk/qcom/turingcc-qcs404.c
@@ -125,11 +125,22 @@ static int turingcc_probe(struct platform_device *pdev)
return ret;
}
+ ret = pm_runtime_resume_and_get(&pdev->dev);
+ if (ret)
+ return ret;
+
ret = qcom_cc_probe(pdev, &turingcc_desc);
if (ret < 0)
- return ret;
+ goto err_put_rpm;
+
+ pm_runtime_put(&pdev->dev);
return 0;
+
+err_put_rpm:
+ pm_runtime_put_sync(&pdev->dev);
+
+ return ret;
}
static const struct dev_pm_ops turingcc_pm_ops = {
diff --git a/drivers/clk/qcom/videocc-sm8350.c b/drivers/clk/qcom/videocc-sm8350.c
index b148877fc73d..7246f3c99492 100644
--- a/drivers/clk/qcom/videocc-sm8350.c
+++ b/drivers/clk/qcom/videocc-sm8350.c
@@ -41,6 +41,10 @@ static const struct pll_vco lucid_5lpe_vco[] = {
{ 249600000, 1750000000, 0 },
};
+static const struct pll_vco lucid_5lpe_vco_8280xp[] = {
+ { 249600000, 1800000000, 0 },
+};
+
static const struct alpha_pll_config video_pll0_config = {
.l = 0x25,
.alpha = 0x8000,
@@ -159,6 +163,16 @@ static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
{ }
};
+static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_8280xp[] = {
+ F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
+ F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
+ F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
+ F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
+ F(1599000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
+ F(1680000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
+ { }
+};
+
static struct clk_rcg2 video_cc_mvs0_clk_src = {
.cmd_rcgr = 0xb94,
.mnd_width = 0,
@@ -181,6 +195,15 @@ static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
{ }
};
+static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_8280xp[] = {
+ F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
+ F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
+ F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
+ F(1600000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
+ F(1800000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
+ { }
+};
+
static struct clk_rcg2 video_cc_mvs1_clk_src = {
.cmd_rcgr = 0xbb4,
.mnd_width = 0,
@@ -499,6 +522,7 @@ static struct qcom_cc_desc video_cc_sm8350_desc = {
static int video_cc_sm8350_probe(struct platform_device *pdev)
{
+ u32 video_cc_xo_clk_cbcr = 0xeec;
struct regmap *regmap;
int ret;
@@ -510,6 +534,21 @@ static int video_cc_sm8350_probe(struct platform_device *pdev)
if (ret)
return ret;
+ if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8280xp-videocc")) {
+ video_cc_sleep_clk_src.cmd_rcgr = 0xf38;
+ video_cc_sleep_clk.halt_reg = 0xf58;
+ video_cc_sleep_clk.clkr.enable_reg = 0xf58;
+ video_cc_xo_clk_src.cmd_rcgr = 0xf14;
+ video_cc_xo_clk_cbcr = 0xf34;
+
+ video_pll0.vco_table = video_pll1.vco_table = lucid_5lpe_vco_8280xp;
+ /* No change, but assign it for completeness */
+ video_pll0.num_vco = video_pll1.num_vco = ARRAY_SIZE(lucid_5lpe_vco_8280xp);
+
+ video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_8280xp;
+ video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_8280xp;
+ }
+
regmap = qcom_cc_map(pdev, &video_cc_sm8350_desc);
if (IS_ERR(regmap)) {
pm_runtime_put(&pdev->dev);
@@ -525,7 +564,7 @@ static int video_cc_sm8350_probe(struct platform_device *pdev)
* video_cc_xo_clk
*/
regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0));
- regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0));
+ regmap_update_bits(regmap, video_cc_xo_clk_cbcr, BIT(0), BIT(0));
ret = qcom_cc_really_probe(pdev, &video_cc_sm8350_desc, regmap);
pm_runtime_put(&pdev->dev);
@@ -534,6 +573,7 @@ static int video_cc_sm8350_probe(struct platform_device *pdev)
}
static const struct of_device_id video_cc_sm8350_match_table[] = {
+ { .compatible = "qcom,sc8280xp-videocc" },
{ .compatible = "qcom,sm8350-videocc" },
{ }
};
diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c
index 7d0029b8b799..16a61146e619 100644
--- a/drivers/clk/qcom/videocc-sm8450.c
+++ b/drivers/clk/qcom/videocc-sm8450.c
@@ -4,8 +4,9 @@
*/
#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c
index e2400fe23e60..3bb136ec31b1 100644
--- a/drivers/clk/qcom/videocc-sm8550.c
+++ b/drivers/clk/qcom/videocc-sm8550.c
@@ -4,8 +4,9 @@
*/
#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c
index d95a33293b0a..92d14350c4b3 100644
--- a/drivers/clk/ralink/clk-mt7621.c
+++ b/drivers/clk/ralink/clk-mt7621.c
@@ -521,6 +521,7 @@ static int mt7621_clk_probe(struct platform_device *pdev)
GFP_KERNEL);
if (!clk_data)
return -ENOMEM;
+ clk_data->num = count;
for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++)
clk_data->hws[i] = mt7621_clk_early[i];
@@ -537,8 +538,6 @@ static int mt7621_clk_probe(struct platform_device *pdev)
goto unreg_clk_fixed;
}
- clk_data->num = count;
-
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
if (ret) {
dev_err(dev, "Couldn't add clk hw provider\n");
diff --git a/drivers/clk/renesas/clk-emev2.c b/drivers/clk/renesas/clk-emev2.c
index 7807b30a5bbb..37c6f9be5e5b 100644
--- a/drivers/clk/renesas/clk-emev2.c
+++ b/drivers/clk/renesas/clk-emev2.c
@@ -6,7 +6,6 @@
* Copyright (C) 2012 Magnus Damm
*/
#include <linux/clk-provider.h>
-#include <linux/clkdev.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
@@ -74,7 +73,6 @@ static void __init emev2_smu_clkdiv_init(struct device_node *np)
clk = clk_register_divider(NULL, np->name, parent_name, 0,
smu_base + reg[0], reg[1], 8, 0, &lock);
of_clk_add_provider(np, of_clk_src_simple_get, clk);
- clk_register_clkdev(clk, np->full_name, NULL);
pr_debug("## %s %pOFn %p\n", __func__, np, clk);
}
CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv",
@@ -92,7 +90,6 @@ static void __init emev2_smu_gclk_init(struct device_node *np)
clk = clk_register_gate(NULL, np->name, parent_name, 0,
smu_base + reg[0], reg[1], 0, &lock);
of_clk_add_provider(np, of_clk_src_simple_get, clk);
- clk_register_clkdev(clk, np->full_name, NULL);
pr_debug("## %s %pOFn %p\n", __func__, np, clk);
}
CLK_OF_DECLARE(emev2_smu_gclk, "renesas,emev2-smu-gclk", emev2_smu_gclk_init);
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index ad03c09ebc1f..aba043f999eb 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
+ DEF_GEN3_Z("zg", R8A774A1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -123,6 +124,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
};
static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
+ DEF_MOD("3dge", 112, R8A774A1_CLK_ZG),
DEF_MOD("tmu4", 121, R8A774A1_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A774A1_CLK_S3D2),
DEF_MOD("tmu2", 123, R8A774A1_CLK_S3D2),
@@ -213,6 +215,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
DEF_MOD("rpc-if", 917, R8A774A1_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6),
+ DEF_MOD("adg", 922, R8A774A1_CLK_S0D4),
DEF_MOD("iic-pmic", 926, R8A774A1_CLK_CP),
DEF_MOD("i2c4", 927, R8A774A1_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A774A1_CLK_S0D6),
diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
index ab087b02ef90..a3244e76f779 100644
--- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
@@ -73,6 +73,7 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A774B1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
+ DEF_GEN3_Z("zg", R8A774B1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
DEF_FIXED("ztr", R8A774B1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A774B1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A774B1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -120,6 +121,7 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
};
static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
+ DEF_MOD("3dge", 112, R8A774B1_CLK_ZG),
DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2),
DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2),
@@ -209,6 +211,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6),
+ DEF_MOD("adg", 922, R8A774B1_CLK_S0D4),
DEF_MOD("iic-pmic", 926, R8A774B1_CLK_CP),
DEF_MOD("i2c4", 927, R8A774B1_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A774B1_CLK_S0D6),
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index c9c8fde0f0a6..870f8c55eb28 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -211,6 +211,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
DEF_MOD("rpc-if", 917, R8A774C0_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2),
DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2),
+ DEF_MOD("adg", 922, R8A774C0_CLK_ZA2),
DEF_MOD("iic-pmic", 926, R8A774C0_CLK_CP),
DEF_MOD("i2c4", 927, R8A774C0_CLK_S3D2),
DEF_MOD("i2c3", 928, R8A774C0_CLK_S3D2),
diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
index a790061db877..7158464c80d8 100644
--- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
@@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = {
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A774E1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
+ DEF_GEN3_Z("zg", R8A774E1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
DEF_FIXED("ztr", R8A774E1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A774E1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A774E1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -124,6 +125,7 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = {
};
static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = {
+ DEF_MOD("3dge", 112, R8A774E1_CLK_ZG),
DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1),
DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A774E1_CLK_S0D6),
@@ -221,7 +223,7 @@ static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = {
DEF_MOD("rpc-if", 917, R8A774E1_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774E1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774E1_CLK_S0D6),
- DEF_MOD("adg", 922, R8A774E1_CLK_S0D1),
+ DEF_MOD("adg", 922, R8A774E1_CLK_S0D4),
DEF_MOD("iic-pmic", 926, R8A774E1_CLK_CP),
DEF_MOD("i2c4", 927, R8A774E1_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A774E1_CLK_S0D6),
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index 7a585a777d38..ad20b3301ef6 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -79,6 +79,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
+ DEF_GEN3_Z("zg", R8A7795_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -128,6 +129,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
};
static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
+ DEF_MOD("3dge", 112, R8A7795_CLK_ZG),
DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A7795_CLK_S0D6),
@@ -251,6 +253,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
DEF_MOD("rpc-if", 917, R8A7795_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
+ DEF_MOD("adg", 922, R8A7795_CLK_S0D4),
DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6),
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index c4969318508e..e5f9e3e74229 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -81,6 +81,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
+ DEF_GEN3_Z("zg", R8A7796_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -130,6 +131,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
};
static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
+ DEF_MOD("3dge", 112, R8A7796_CLK_ZG),
DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A7796_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A7796_CLK_S3D2),
@@ -236,6 +238,7 @@ static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
DEF_MOD("rpc-if", 917, R8A7796_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
+ DEF_MOD("adg", 922, R8A7796_CLK_S0D4),
DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A7796_CLK_S0D6),
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index 78f6e530848e..219e41abb5df 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
+ DEF_GEN3_Z("zg", R8A77965_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -125,6 +126,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
};
static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
+ DEF_MOD("3dge", 112, R8A77965_CLK_ZG),
DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A77965_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A77965_CLK_S3D2),
@@ -236,6 +238,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
DEF_MOD("rpc-if", 917, R8A77965_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A77965_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A77965_CLK_S0D6),
+ DEF_MOD("adg", 922, R8A77965_CLK_S0D4),
DEF_MOD("i2c-dvfs", 926, R8A77965_CLK_CP),
DEF_MOD("i2c4", 927, R8A77965_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A77965_CLK_S0D6),
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index b666d099365e..b2f82c594925 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -224,6 +224,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
DEF_MOD("rpc-if", 917, R8A77990_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2),
DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2),
+ DEF_MOD("adg", 922, R8A77990_CLK_ZA2),
DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP),
DEF_MOD("i2c4", 927, R8A77990_CLK_S3D2),
DEF_MOD("i2c3", 928, R8A77990_CLK_S3D2),
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index 3a73f6f911dd..162fa86c81ff 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -181,6 +181,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
DEF_MOD("rpc-if", 917, R8A77995_CLK_RPCD2),
+ DEF_MOD("adg", 922, R8A77995_CLK_ZA2),
DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 99f72bf590fa..1a7a6d60aca4 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -154,6 +154,8 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0x534, 1),
DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0,
0x534, 2),
+ DEF_MOD("mtu_x_mck", R9A07G043_MTU_X_MCK_MTU3, R9A07G043_CLK_P0,
+ 0x538, 0),
DEF_MOD("wdt0_pclk", R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0,
0x548, 0),
DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,
@@ -264,6 +266,7 @@ static struct rzg2l_reset r9a07g043_resets[] = {
DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0),
DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
+ DEF_RST(R9A07G043_MTU_X_PRESET_MTU3, 0x838, 0),
DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),
DEF_RST(R9A07G043_SPI_RST, 0x850, 0),
DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c
index 3d06baf5061d..dda9f29dff33 100644
--- a/drivers/clk/renesas/r9a09g011-cpg.c
+++ b/drivers/clk/renesas/r9a09g011-cpg.c
@@ -28,6 +28,8 @@
#define DIV_W DDIV_PACK(0x328, 0, 3)
#define SEL_B SEL_PLL_PACK(0x214, 0, 1)
+#define SEL_CSI0 SEL_PLL_PACK(0x330, 0, 1)
+#define SEL_CSI4 SEL_PLL_PACK(0x330, 4, 1)
#define SEL_D SEL_PLL_PACK(0x214, 1, 1)
#define SEL_E SEL_PLL_PACK(0x214, 2, 1)
#define SEL_SDI SEL_PLL_PACK(0x300, 0, 1)
@@ -58,6 +60,8 @@ enum clk_ids {
CLK_DIV_W,
CLK_SEL_B,
CLK_SEL_B_D2,
+ CLK_SEL_CSI0,
+ CLK_SEL_CSI4,
CLK_SEL_D,
CLK_SEL_E,
CLK_SEL_SDI,
@@ -108,6 +112,7 @@ static const struct clk_div_table dtable_divw[] = {
/* Mux clock tables */
static const char * const sel_b[] = { ".main", ".divb" };
+static const char * const sel_csi[] = { ".main_24", ".main" };
static const char * const sel_d[] = { ".main", ".divd" };
static const char * const sel_e[] = { ".main", ".dive" };
static const char * const sel_w[] = { ".main", ".divw" };
@@ -139,6 +144,8 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
DEF_MUX_RO(".seld", CLK_SEL_D, SEL_D, sel_d),
DEF_MUX_RO(".sele", CLK_SEL_E, SEL_E, sel_e),
DEF_MUX(".selsdi", CLK_SEL_SDI, SEL_SDI, sel_sdi),
+ DEF_MUX(".selcsi0", CLK_SEL_CSI0, SEL_CSI0, sel_csi),
+ DEF_MUX(".selcsi4", CLK_SEL_CSI4, SEL_CSI4, sel_csi),
DEF_MUX(".selw0", CLK_SEL_W0, SEL_W0, sel_w),
DEF_FIXED(".selb_d2", CLK_SEL_B_D2, CLK_SEL_B, 1, 2),
@@ -196,8 +203,12 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
DEF_MOD("pwm12_clk", R9A09G011_PWM12_CLK, CLK_MAIN, 0x434, 8),
DEF_MOD("pwm13_clk", R9A09G011_PWM13_CLK, CLK_MAIN, 0x434, 9),
DEF_MOD("pwm14_clk", R9A09G011_PWM14_CLK, CLK_MAIN, 0x434, 10),
+ DEF_MOD("cperi_grpg", R9A09G011_CPERI_GRPG_PCLK, CLK_SEL_E, 0x438, 0),
+ DEF_MOD("cperi_grph", R9A09G011_CPERI_GRPH_PCLK, CLK_SEL_E, 0x438, 1),
DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4),
DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5),
+ DEF_MOD("csi0_clk", R9A09G011_CSI0_CLK, CLK_SEL_CSI0, 0x438, 8),
+ DEF_MOD("csi4_clk", R9A09G011_CSI4_CLK, CLK_SEL_CSI4, 0x438, 12),
DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0),
};
@@ -215,6 +226,8 @@ static const struct rzg2l_reset r9a09g011_resets[] = {
DEF_RST(R9A09G011_TIM_GPB_PRESETN, 0x614, 1),
DEF_RST(R9A09G011_TIM_GPC_PRESETN, 0x614, 2),
DEF_RST_MON(R9A09G011_PWM_GPF_PRESETN, 0x614, 5, 23),
+ DEF_RST_MON(R9A09G011_CSI_GPG_PRESETN, 0x614, 6, 22),
+ DEF_RST_MON(R9A09G011_CSI_GPH_PRESETN, 0x614, 7, 23),
DEF_RST(R9A09G011_IIC_GPA_PRESETN, 0x614, 8),
DEF_RST(R9A09G011_IIC_GPB_PRESETN, 0x614, 9),
DEF_RST_MON(R9A09G011_WDT0_PRESETN, 0x614, 12, 19),
@@ -225,6 +238,8 @@ static const unsigned int r9a09g011_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A09G011_CPERI_GRPB_PCLK,
MOD_CLK_BASE + R9A09G011_CPERI_GRPC_PCLK,
MOD_CLK_BASE + R9A09G011_CPERI_GRPF_PCLK,
+ MOD_CLK_BASE + R9A09G011_CPERI_GRPG_PCLK,
+ MOD_CLK_BASE + R9A09G011_CPERI_GRPH_PCLK,
MOD_CLK_BASE + R9A09G011_GIC_CLK,
MOD_CLK_BASE + R9A09G011_SYC_CNT_CLK,
MOD_CLK_BASE + R9A09G011_URT_PCLK,
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index b3ef62fa612e..d0129a650941 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -264,11 +264,13 @@ static const struct clk_ops cpg_z_clk_ops = {
.set_rate = cpg_z_clk_set_rate,
};
-static struct clk * __init cpg_z_clk_register(const char *name,
+static struct clk * __init __cpg_z_clk_register(const char *name,
const char *parent_name,
void __iomem *reg,
unsigned int div,
- unsigned int offset)
+ unsigned int offset,
+ unsigned int fcr,
+ unsigned int flags)
{
struct clk_init_data init = {};
struct cpg_z_clk *zclk;
@@ -280,11 +282,11 @@ static struct clk * __init cpg_z_clk_register(const char *name,
init.name = name;
init.ops = &cpg_z_clk_ops;
- init.flags = CLK_SET_RATE_PARENT;
+ init.flags = flags;
init.parent_names = &parent_name;
init.num_parents = 1;
- zclk->reg = reg + CPG_FRQCRC;
+ zclk->reg = reg + fcr;
zclk->kick_reg = reg + CPG_FRQCRB;
zclk->hw.init = &init;
zclk->mask = GENMASK(offset + 4, offset);
@@ -301,6 +303,27 @@ static struct clk * __init cpg_z_clk_register(const char *name,
return clk;
}
+static struct clk * __init cpg_z_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *reg,
+ unsigned int div,
+ unsigned int offset)
+{
+ return __cpg_z_clk_register(name, parent_name, reg, div, offset,
+ CPG_FRQCRC, CLK_SET_RATE_PARENT);
+}
+
+static struct clk * __init cpg_zg_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *reg,
+ unsigned int div,
+ unsigned int offset)
+{
+ return __cpg_z_clk_register(name, parent_name, reg, div, offset,
+ CPG_FRQCRB, 0);
+
+}
+
static const struct clk_div_table cpg_rpcsrc_div_table[] = {
{ 2, 5 }, { 3, 6 }, { 0, 0 },
};
@@ -438,6 +461,10 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
return cpg_z_clk_register(core->name, __clk_get_name(parent),
base, core->div, core->offset);
+ case CLK_TYPE_GEN3_ZG:
+ return cpg_zg_clk_register(core->name, __clk_get_name(parent),
+ base, core->div, core->offset);
+
case CLK_TYPE_GEN3_OSC:
/*
* Clock combining OSC EXTAL predivider and a fixed divider
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 9028bf4295ce..bfdc649bdf12 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -22,6 +22,7 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_R,
CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
CLK_TYPE_GEN3_Z,
+ CLK_TYPE_GEN3_ZG,
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
CLK_TYPE_GEN3_RPCSRC,
diff --git a/drivers/clk/renesas/rcar-usb2-clock-sel.c b/drivers/clk/renesas/rcar-usb2-clock-sel.c
index 17c110978e33..de4896cf5f40 100644
--- a/drivers/clk/renesas/rcar-usb2-clock-sel.c
+++ b/drivers/clk/renesas/rcar-usb2-clock-sel.c
@@ -15,7 +15,6 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 2772499d2016..cb80d1bf6c7c 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -21,7 +21,6 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_domain.h>
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index bc623515ad84..47f488387f33 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -20,8 +20,7 @@
#include <linux/iopoll.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_domain.h>
@@ -182,12 +181,6 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core,
return clk_hw->clk;
}
-static int rzg2l_cpg_sd_clk_mux_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST);
-}
-
static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
{
struct sd_hw_data *hwdata = to_sd_hw_data(hw);
@@ -250,7 +243,7 @@ static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw)
}
static const struct clk_ops rzg2l_cpg_sd_clk_mux_ops = {
- .determine_rate = rzg2l_cpg_sd_clk_mux_determine_rate,
+ .determine_rate = __clk_mux_determine_rate_closest,
.set_parent = rzg2l_cpg_sd_clk_mux_set_parent,
.get_parent = rzg2l_cpg_sd_clk_mux_get_parent,
};
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index f85902e2590c..16dabe2b9c47 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -7,8 +7,8 @@
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/of_address.h>
+#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rk3568-cru.h>
#include "clk.h"
@@ -79,9 +79,10 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0),
+ RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
- RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
+ RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
{ /* sentinel */ },
};
diff --git a/drivers/clk/rockchip/clk-rv1126.c b/drivers/clk/rockchip/clk-rv1126.c
index c18790f5d05b..fc19c5522490 100644
--- a/drivers/clk/rockchip/clk-rv1126.c
+++ b/drivers/clk/rockchip/clk-rv1126.c
@@ -8,7 +8,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rockchip,rv1126-cru.h>
#include "clk.h"
@@ -175,6 +175,7 @@ PNAME(mux_i2s2_p) = { "mclk_i2s2_div", "mclk_i2s2_fracdiv", "i2s2_mclkin", "xi
PNAME(mux_i2s2_out2io_p) = { "mclk_i2s2", "xin12m" };
PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
PNAME(mux_audpwm_p) = { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" };
+PNAME(mux_dclk_vop_p) = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
PNAME(mux_usb480m_gpll_p) = { "usb480m", "gpll" };
PNAME(clk_gmac_src_m0_p) = { "clk_gmac_div", "clk_gmac_rgmii_m0" };
PNAME(clk_gmac_src_m1_p) = { "clk_gmac_div", "clk_gmac_rgmii_m1" };
@@ -259,6 +260,10 @@ static struct rockchip_clk_branch rv1126_audpwm_fracmux __initdata =
MUX(SCLK_AUDPWM_MUX, "mclk_audpwm_mux", mux_audpwm_p, CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(36), 8, 2, MFLAGS);
+static struct rockchip_clk_branch rv1126_dclk_vop_fracmux __initdata =
+ MUX(DCLK_VOP_MUX, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(47), 10, 2, MFLAGS);
+
static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = {
/*
* Clock-Architecture Diagram 2
@@ -715,6 +720,49 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
RV1126_CLKGATE_CON(11), 1, GFLAGS),
/*
+ * Clock-Architecture Diagram 9
+ */
+ /* PD_VO */
+ COMPOSITE(ACLK_PDVO, "aclk_pdvo", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(14), 0, GFLAGS),
+ COMPOSITE_NOMUX(HCLK_PDVO, "hclk_pdvo", "aclk_pdvo", 0,
+ RV1126_CLKSEL_CON(45), 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(14), 1, GFLAGS),
+ COMPOSITE_NOMUX(PCLK_PDVO, "pclk_pdvo", "aclk_pdvo", 0,
+ RV1126_CLKSEL_CON(46), 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(14), 2, GFLAGS),
+ GATE(ACLK_RGA, "aclk_rga", "aclk_pdvo", 0,
+ RV1126_CLKGATE_CON(14), 6, GFLAGS),
+ GATE(HCLK_RGA, "hclk_rga", "hclk_pdvo", 0,
+ RV1126_CLKGATE_CON(14), 7, GFLAGS),
+ COMPOSITE(CLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(14), 8, GFLAGS),
+ GATE(ACLK_VOP, "aclk_vop", "aclk_pdvo", 0,
+ RV1126_CLKGATE_CON(14), 9, GFLAGS),
+ GATE(HCLK_VOP, "hclk_vop", "hclk_pdvo", 0,
+ RV1126_CLKGATE_CON(14), 10, GFLAGS),
+ COMPOSITE(DCLK_VOP_DIV, "dclk_vop_div", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(47), 8, 1, MFLAGS, 0, 8, DFLAGS,
+ RV1126_CLKGATE_CON(14), 11, GFLAGS),
+ COMPOSITE_FRACMUX(DCLK_VOP_FRACDIV, "dclk_vop_fracdiv", "dclk_vop_div",
+ CLK_SET_RATE_PARENT, RV1126_CLKSEL_CON(48), 0,
+ RV1126_CLKGATE_CON(14), 12, GFLAGS,
+ &rv1126_dclk_vop_fracmux),
+ GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
+ RV1126_CLKGATE_CON(14), 13, GFLAGS),
+ GATE(PCLK_DSIHOST, "pclk_dsihost", "pclk_pdvo", 0,
+ RV1126_CLKGATE_CON(14), 14, GFLAGS),
+ GATE(ACLK_IEP, "aclk_iep", "aclk_pdvo", 0,
+ RV1126_CLKGATE_CON(12), 7, GFLAGS),
+ GATE(HCLK_IEP, "hclk_iep", "hclk_pdvo", 0,
+ RV1126_CLKGATE_CON(12), 8, GFLAGS),
+ COMPOSITE(CLK_IEP_CORE, "clk_iep_core", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(54), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(12), 9, GFLAGS),
+
+ /*
* Clock-Architecture Diagram 12
*/
/* PD_PHP */
@@ -906,6 +954,17 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
RV1126_CLKGATE_CON(9), 3, GFLAGS),
/*
+ * Clock-Architecture Diagram 9
+ */
+ /* PD_VO */
+ GATE(0, "aclk_pdvo_niu", "aclk_pdvo", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(14), 3, GFLAGS),
+ GATE(0, "hclk_pdvo_niu", "hclk_pdvo", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(14), 4, GFLAGS),
+ GATE(0, "pclk_pdvo_niu", "pclk_pdvo", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(14), 5, GFLAGS),
+
+ /*
* Clock-Architecture Diagram 12
*/
/* PD_PHP */
diff --git a/drivers/clk/samsung/clk-exynos-arm64.c b/drivers/clk/samsung/clk-exynos-arm64.c
index 7d8937caf22a..6fb7194df7ab 100644
--- a/drivers/clk/samsung/clk-exynos-arm64.c
+++ b/drivers/clk/samsung/clk-exynos-arm64.c
@@ -10,7 +10,8 @@
*/
#include <linux/clk.h>
#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index 7626dff41f6f..e44b172d7255 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -10,8 +10,7 @@
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index 6cc65ccf867c..a02461667664 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -100,6 +100,11 @@
#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR_MAIN (CLK_SCLK_MMC2 + 1)
+#define CLKS_NR_DMC (CLK_DIV_DMCD + 1)
+#define CLKS_NR_ISP (CLK_SCLK_MPWM_ISP + 1)
+
static const unsigned long exynos3250_cmu_clk_regs[] __initconst = {
SRC_LEFTBUS,
DIV_LEFTBUS,
@@ -807,7 +812,7 @@ static const struct samsung_cmu_info cmu_info __initconst = {
.nr_fixed_factor_clks = ARRAY_SIZE(fixed_factor_clks),
.cpu_clks = exynos3250_cpu_clks,
.nr_cpu_clks = ARRAY_SIZE(exynos3250_cpu_clks),
- .nr_clk_ids = CLK_NR_CLKS,
+ .nr_clk_ids = CLKS_NR_MAIN,
.clk_regs = exynos3250_cmu_clk_regs,
.nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs),
};
@@ -923,7 +928,7 @@ static const struct samsung_cmu_info dmc_cmu_info __initconst = {
.nr_mux_clks = ARRAY_SIZE(dmc_mux_clks),
.div_clks = dmc_div_clks,
.nr_div_clks = ARRAY_SIZE(dmc_div_clks),
- .nr_clk_ids = NR_CLKS_DMC,
+ .nr_clk_ids = CLKS_NR_DMC,
.clk_regs = exynos3250_cmu_dmc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs),
};
@@ -1067,7 +1072,7 @@ static const struct samsung_cmu_info isp_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(isp_div_clks),
.gate_clks = isp_gate_clks,
.nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
- .nr_clk_ids = NR_CLKS_ISP,
+ .nr_clk_ids = CLKS_NR_ISP,
};
static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev)
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 43207257a9cc..4ec41221e68f 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -135,6 +135,9 @@
#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR (CLK_DIV_CORE2 + 1)
+
/* the exynos4 soc type */
enum exynos4_soc {
EXYNOS4210,
@@ -1275,7 +1278,7 @@ static void __init exynos4_clk_init(struct device_node *np,
if (!reg_base)
panic("%s: failed to map registers\n", __func__);
- ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS);
+ ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
hws = ctx->clk_data.hws;
samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
diff --git a/drivers/clk/samsung/clk-exynos4412-isp.c b/drivers/clk/samsung/clk-exynos4412-isp.c
index 1470c15e95da..a70c2b06a61a 100644
--- a/drivers/clk/samsung/clk-exynos4412-isp.c
+++ b/drivers/clk/samsung/clk-exynos4412-isp.c
@@ -22,6 +22,9 @@
#define E4X12_GATE_ISP0 0x0800
#define E4X12_GATE_ISP1 0x0804
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR_ISP (CLK_ISP_DIV_MCUISP1 + 1)
+
/*
* Support for CMU save/restore across system suspends
*/
@@ -121,7 +124,7 @@ static int __init exynos4x12_isp_clk_probe(struct platform_device *pdev)
if (!exynos4x12_save_isp)
return -ENOMEM;
- ctx = samsung_clk_init(dev, reg_base, CLK_NR_ISP_CLKS);
+ ctx = samsung_clk_init(dev, reg_base, CLKS_NR_ISP);
platform_set_drvdata(pdev, ctx);
diff --git a/drivers/clk/samsung/clk-exynos5-subcmu.c b/drivers/clk/samsung/clk-exynos5-subcmu.c
index 96d74bc250e5..373129847301 100644
--- a/drivers/clk/samsung/clk-exynos5-subcmu.c
+++ b/drivers/clk/samsung/clk-exynos5-subcmu.c
@@ -5,7 +5,7 @@
// Common Clock Framework support for Exynos5 power-domain dependent clocks
#include <linux/io.h>
-#include <linux/of_platform.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 92fb09922f28..8ebe6155d8b7 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -100,6 +100,9 @@
#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR (CLK_MOUT_VPLLSRC + 1)
+
/* list of PLLs to be registered */
enum exynos5250_plls {
apll, mpll, cpll, epll, vpll, gpll, bpll,
@@ -797,7 +800,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
panic("%s: unable to determine soc\n", __func__);
}
- ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS);
+ ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
hws = ctx->clk_data.hws;
samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c
index e05d7323669a..16da6ef5ca0c 100644
--- a/drivers/clk/samsung/clk-exynos5260.c
+++ b/drivers/clk/samsung/clk-exynos5260.c
@@ -15,6 +15,21 @@
#include <dt-bindings/clock/exynos5260-clk.h>
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR_TOP (PHYCLK_USBDRD30_UDRD30_PHYCLOCK + 1)
+#define CLKS_NR_EGL (EGL_DOUT_EGL1 + 1)
+#define CLKS_NR_KFC (KFC_DOUT_KFC1 + 1)
+#define CLKS_NR_MIF (MIF_SCLK_LPDDR3PHY_WRAP_U0 + 1)
+#define CLKS_NR_G3D (G3D_CLK_G3D + 1)
+#define CLKS_NR_AUD (AUD_SCLK_I2S + 1)
+#define CLKS_NR_MFC (MFC_CLK_SMMU2_MFCM0 + 1)
+#define CLKS_NR_GSCL (GSCL_SCLK_CSIS0_WRAP + 1)
+#define CLKS_NR_FSYS (FSYS_PHYCLK_USBHOST20 + 1)
+#define CLKS_NR_PERI (PERI_SCLK_PCM1 + 1)
+#define CLKS_NR_DISP (DISP_MOUT_HDMI_PHY_PIXEL_USER + 1)
+#define CLKS_NR_G2D (G2D_CLK_SMMU3_G2D + 1)
+#define CLKS_NR_ISP (ISP_SCLK_UART_EXT + 1)
+
/*
* Applicable for all 2550 Type PLLS for Exynos5260, listed below
* DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
@@ -135,7 +150,7 @@ static const struct samsung_cmu_info aud_cmu __initconst = {
.nr_div_clks = ARRAY_SIZE(aud_div_clks),
.gate_clks = aud_gate_clks,
.nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
- .nr_clk_ids = AUD_NR_CLK,
+ .nr_clk_ids = CLKS_NR_AUD,
.clk_regs = aud_clk_regs,
.nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
};
@@ -325,7 +340,7 @@ static const struct samsung_cmu_info disp_cmu __initconst = {
.nr_div_clks = ARRAY_SIZE(disp_div_clks),
.gate_clks = disp_gate_clks,
.nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
- .nr_clk_ids = DISP_NR_CLK,
+ .nr_clk_ids = CLKS_NR_DISP,
.clk_regs = disp_clk_regs,
.nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
};
@@ -389,7 +404,7 @@ static const struct samsung_cmu_info egl_cmu __initconst = {
.nr_mux_clks = ARRAY_SIZE(egl_mux_clks),
.div_clks = egl_div_clks,
.nr_div_clks = ARRAY_SIZE(egl_div_clks),
- .nr_clk_ids = EGL_NR_CLK,
+ .nr_clk_ids = CLKS_NR_EGL,
.clk_regs = egl_clk_regs,
.nr_clk_regs = ARRAY_SIZE(egl_clk_regs),
};
@@ -489,7 +504,7 @@ static const struct samsung_cmu_info fsys_cmu __initconst = {
.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
.gate_clks = fsys_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
- .nr_clk_ids = FSYS_NR_CLK,
+ .nr_clk_ids = CLKS_NR_FSYS,
.clk_regs = fsys_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
};
@@ -580,7 +595,7 @@ static const struct samsung_cmu_info g2d_cmu __initconst = {
.nr_div_clks = ARRAY_SIZE(g2d_div_clks),
.gate_clks = g2d_gate_clks,
.nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
- .nr_clk_ids = G2D_NR_CLK,
+ .nr_clk_ids = CLKS_NR_G2D,
.clk_regs = g2d_clk_regs,
.nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
};
@@ -643,7 +658,7 @@ static const struct samsung_cmu_info g3d_cmu __initconst = {
.nr_div_clks = ARRAY_SIZE(g3d_div_clks),
.gate_clks = g3d_gate_clks,
.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
- .nr_clk_ids = G3D_NR_CLK,
+ .nr_clk_ids = CLKS_NR_G3D,
.clk_regs = g3d_clk_regs,
.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
};
@@ -776,7 +791,7 @@ static const struct samsung_cmu_info gscl_cmu __initconst = {
.nr_div_clks = ARRAY_SIZE(gscl_div_clks),
.gate_clks = gscl_gate_clks,
.nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
- .nr_clk_ids = GSCL_NR_CLK,
+ .nr_clk_ids = CLKS_NR_GSCL,
.clk_regs = gscl_clk_regs,
.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
};
@@ -895,7 +910,7 @@ static const struct samsung_cmu_info isp_cmu __initconst = {
.nr_div_clks = ARRAY_SIZE(isp_div_clks),
.gate_clks = isp_gate_clks,
.nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
- .nr_clk_ids = ISP_NR_CLK,
+ .nr_clk_ids = CLKS_NR_ISP,
.clk_regs = isp_clk_regs,
.nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
};
@@ -959,7 +974,7 @@ static const struct samsung_cmu_info kfc_cmu __initconst = {
.nr_mux_clks = ARRAY_SIZE(kfc_mux_clks),
.div_clks = kfc_div_clks,
.nr_div_clks = ARRAY_SIZE(kfc_div_clks),
- .nr_clk_ids = KFC_NR_CLK,
+ .nr_clk_ids = CLKS_NR_KFC,
.clk_regs = kfc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(kfc_clk_regs),
};
@@ -1015,7 +1030,7 @@ static const struct samsung_cmu_info mfc_cmu __initconst = {
.nr_div_clks = ARRAY_SIZE(mfc_div_clks),
.gate_clks = mfc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
- .nr_clk_ids = MFC_NR_CLK,
+ .nr_clk_ids = CLKS_NR_MFC,
.clk_regs = mfc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
};
@@ -1164,7 +1179,7 @@ static const struct samsung_cmu_info mif_cmu __initconst = {
.nr_div_clks = ARRAY_SIZE(mif_div_clks),
.gate_clks = mif_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
- .nr_clk_ids = MIF_NR_CLK,
+ .nr_clk_ids = CLKS_NR_MIF,
.clk_regs = mif_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
};
@@ -1370,7 +1385,7 @@ static const struct samsung_cmu_info peri_cmu __initconst = {
.nr_div_clks = ARRAY_SIZE(peri_div_clks),
.gate_clks = peri_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
- .nr_clk_ids = PERI_NR_CLK,
+ .nr_clk_ids = CLKS_NR_PERI,
.clk_regs = peri_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
};
@@ -1826,7 +1841,7 @@ static const struct samsung_cmu_info top_cmu __initconst = {
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
.fixed_clks = fixed_rate_clks,
.nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks),
- .nr_clk_ids = TOP_NR_CLK,
+ .nr_clk_ids = CLKS_NR_TOP,
.clk_regs = top_clk_regs,
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
};
diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index d67d67a519a4..2654077211e7 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -56,6 +56,9 @@
#define SRC_KFC 0x28200
#define DIV_KFC0 0x28500
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR 512
+
/* list of PLLs */
enum exynos5410_plls {
apll, cpll, epll, mpll,
@@ -260,7 +263,7 @@ static const struct samsung_cmu_info cmu __initconst = {
.nr_div_clks = ARRAY_SIZE(exynos5410_div_clks),
.gate_clks = exynos5410_gate_clks,
.nr_gate_clks = ARRAY_SIZE(exynos5410_gate_clks),
- .nr_clk_ids = CLK_NR_CLKS,
+ .nr_clk_ids = CLKS_NR,
};
/* register exynos5410 clocks */
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 1e0cbf762408..199843f12ae5 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -139,6 +139,9 @@
#define SRC_KFC 0x28200
#define DIV_KFC0 0x28500
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR (CLK_DOUT_PCLK_DREX1 + 1)
+
/* Exynos5x SoC type */
enum exynos5x_soc {
EXYNOS5420,
@@ -1587,7 +1590,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
exynos5x_soc = soc;
- ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS);
+ ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
hws = ctx->clk_data.hws;
samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index ed43233649ae..6bfc5d0cd924 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -21,6 +21,29 @@
#include "clk-exynos-arm64.h"
#include "clk-pll.h"
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR_TOP (CLK_SCLK_HDMI_SPDIF_DISP + 1)
+#define CLKS_NR_CPIF (CLK_SCLK_UFS_MPHY + 1)
+#define CLKS_NR_MIF (CLK_SCLK_BUS_PLL_ATLAS + 1)
+#define CLKS_NR_PERIC (CLK_DIV_SCLK_SC_IN + 1)
+#define CLKS_NR_PERIS (CLK_SCLK_OTP_CON + 1)
+#define CLKS_NR_FSYS (CLK_PCIE + 1)
+#define CLKS_NR_G2D (CLK_PCLK_SMMU_G2D + 1)
+#define CLKS_NR_DISP (CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY + 1)
+#define CLKS_NR_AUD (CLK_SCLK_AUD_I2S + 1)
+#define CLKS_NR_BUSX (CLK_ACLK_BUS2RTND_400 + 1)
+#define CLKS_NR_G3D (CLK_SCLK_HPM_G3D + 1)
+#define CLKS_NR_GSCL (CLK_PCLK_SMMU_GSCL2 + 1)
+#define CLKS_NR_APOLLO (CLK_SCLK_APOLLO + 1)
+#define CLKS_NR_ATLAS (CLK_SCLK_ATLAS + 1)
+#define CLKS_NR_MSCL (CLK_SCLK_JPEG + 1)
+#define CLKS_NR_MFC (CLK_PCLK_SMMU_MFC_0 + 1)
+#define CLKS_NR_HEVC (CLK_PCLK_SMMU_HEVC_0 + 1)
+#define CLKS_NR_ISP (CLK_SCLK_PIXELASYNCM_ISPC + 1)
+#define CLKS_NR_CAM0 (CLK_SCLK_PIXELASYNCS_LITE_C_INIT + 1)
+#define CLKS_NR_CAM1 (CLK_SCLK_ISP_CA5 + 1)
+#define CLKS_NR_IMEM (CLK_PCLK_SLIMSSS + 1)
+
/*
* Register offset definitions for CMU_TOP
*/
@@ -798,7 +821,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
.nr_fixed_clks = ARRAY_SIZE(top_fixed_clks),
.fixed_factor_clks = top_fixed_factor_clks,
.nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
- .nr_clk_ids = TOP_NR_CLK,
+ .nr_clk_ids = CLKS_NR_TOP,
.clk_regs = top_clk_regs,
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
.suspend_regs = top_suspend_regs,
@@ -877,7 +900,7 @@ static const struct samsung_cmu_info cpif_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(cpif_div_clks),
.gate_clks = cpif_gate_clks,
.nr_gate_clks = ARRAY_SIZE(cpif_gate_clks),
- .nr_clk_ids = CPIF_NR_CLK,
+ .nr_clk_ids = CLKS_NR_CPIF,
.clk_regs = cpif_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
.suspend_regs = cpif_suspend_regs,
@@ -1531,7 +1554,7 @@ static const struct samsung_cmu_info mif_cmu_info __initconst = {
.nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
.fixed_factor_clks = mif_fixed_factor_clks,
.nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks),
- .nr_clk_ids = MIF_NR_CLK,
+ .nr_clk_ids = CLKS_NR_MIF,
.clk_regs = mif_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
};
@@ -1730,7 +1753,7 @@ static const struct samsung_cmu_info peric_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(peric_div_clks),
.gate_clks = peric_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
- .nr_clk_ids = PERIC_NR_CLK,
+ .nr_clk_ids = CLKS_NR_PERIC,
.clk_regs = peric_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
.suspend_regs = peric_suspend_regs,
@@ -1924,7 +1947,7 @@ static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
static const struct samsung_cmu_info peris_cmu_info __initconst = {
.gate_clks = peris_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
- .nr_clk_ids = PERIS_NR_CLK,
+ .nr_clk_ids = CLKS_NR_PERIS,
.clk_regs = peris_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
};
@@ -2336,7 +2359,7 @@ static const struct samsung_cmu_info fsys_cmu_info __initconst = {
.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
.fixed_clks = fsys_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks),
- .nr_clk_ids = FSYS_NR_CLK,
+ .nr_clk_ids = CLKS_NR_FSYS,
.clk_regs = fsys_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
.suspend_regs = fsys_suspend_regs,
@@ -2459,7 +2482,7 @@ static const struct samsung_cmu_info g2d_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(g2d_div_clks),
.gate_clks = g2d_gate_clks,
.nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
- .nr_clk_ids = G2D_NR_CLK,
+ .nr_clk_ids = CLKS_NR_G2D,
.clk_regs = g2d_clk_regs,
.nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
.suspend_regs = g2d_suspend_regs,
@@ -2887,7 +2910,7 @@ static const struct samsung_cmu_info disp_cmu_info __initconst = {
.nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks),
.fixed_factor_clks = disp_fixed_factor_clks,
.nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks),
- .nr_clk_ids = DISP_NR_CLK,
+ .nr_clk_ids = CLKS_NR_DISP,
.clk_regs = disp_clk_regs,
.nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
.suspend_regs = disp_suspend_regs,
@@ -3057,7 +3080,7 @@ static const struct samsung_cmu_info aud_cmu_info __initconst = {
.nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
.fixed_clks = aud_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
- .nr_clk_ids = AUD_NR_CLK,
+ .nr_clk_ids = CLKS_NR_AUD,
.clk_regs = aud_clk_regs,
.nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
.suspend_regs = aud_suspend_regs,
@@ -3189,7 +3212,7 @@ static const struct samsung_gate_clock bus2_gate_clks[] __initconst = {
.nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \
.gate_clks = bus##id##_gate_clks, \
.nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \
- .nr_clk_ids = BUSx_NR_CLK
+ .nr_clk_ids = CLKS_NR_BUSX
static const struct samsung_cmu_info bus0_cmu_info __initconst = {
CMU_BUS_INFO_CLKS(0),
@@ -3340,7 +3363,7 @@ static const struct samsung_cmu_info g3d_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(g3d_div_clks),
.gate_clks = g3d_gate_clks,
.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
- .nr_clk_ids = G3D_NR_CLK,
+ .nr_clk_ids = CLKS_NR_G3D,
.clk_regs = g3d_clk_regs,
.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
.suspend_regs = g3d_suspend_regs,
@@ -3483,7 +3506,7 @@ static const struct samsung_cmu_info gscl_cmu_info __initconst = {
.nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
.gate_clks = gscl_gate_clks,
.nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
- .nr_clk_ids = GSCL_NR_CLK,
+ .nr_clk_ids = CLKS_NR_GSCL,
.clk_regs = gscl_clk_regs,
.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
.suspend_regs = gscl_suspend_regs,
@@ -3693,7 +3716,7 @@ static const struct samsung_cmu_info apollo_cmu_info __initconst = {
.nr_gate_clks = ARRAY_SIZE(apollo_gate_clks),
.cpu_clks = apollo_cpu_clks,
.nr_cpu_clks = ARRAY_SIZE(apollo_cpu_clks),
- .nr_clk_ids = APOLLO_NR_CLK,
+ .nr_clk_ids = CLKS_NR_APOLLO,
.clk_regs = apollo_clk_regs,
.nr_clk_regs = ARRAY_SIZE(apollo_clk_regs),
};
@@ -3938,7 +3961,7 @@ static const struct samsung_cmu_info atlas_cmu_info __initconst = {
.nr_gate_clks = ARRAY_SIZE(atlas_gate_clks),
.cpu_clks = atlas_cpu_clks,
.nr_cpu_clks = ARRAY_SIZE(atlas_cpu_clks),
- .nr_clk_ids = ATLAS_NR_CLK,
+ .nr_clk_ids = CLKS_NR_ATLAS,
.clk_regs = atlas_clk_regs,
.nr_clk_regs = ARRAY_SIZE(atlas_clk_regs),
};
@@ -4112,7 +4135,7 @@ static const struct samsung_cmu_info mscl_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(mscl_div_clks),
.gate_clks = mscl_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
- .nr_clk_ids = MSCL_NR_CLK,
+ .nr_clk_ids = CLKS_NR_MSCL,
.clk_regs = mscl_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
.suspend_regs = mscl_suspend_regs,
@@ -4220,7 +4243,7 @@ static const struct samsung_cmu_info mfc_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(mfc_div_clks),
.gate_clks = mfc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
- .nr_clk_ids = MFC_NR_CLK,
+ .nr_clk_ids = CLKS_NR_MFC,
.clk_regs = mfc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
.suspend_regs = mfc_suspend_regs,
@@ -4330,7 +4353,7 @@ static const struct samsung_cmu_info hevc_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(hevc_div_clks),
.gate_clks = hevc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(hevc_gate_clks),
- .nr_clk_ids = HEVC_NR_CLK,
+ .nr_clk_ids = CLKS_NR_HEVC,
.clk_regs = hevc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(hevc_clk_regs),
.suspend_regs = hevc_suspend_regs,
@@ -4583,7 +4606,7 @@ static const struct samsung_cmu_info isp_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(isp_div_clks),
.gate_clks = isp_gate_clks,
.nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
- .nr_clk_ids = ISP_NR_CLK,
+ .nr_clk_ids = CLKS_NR_ISP,
.clk_regs = isp_clk_regs,
.nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
.suspend_regs = isp_suspend_regs,
@@ -5065,7 +5088,7 @@ static const struct samsung_cmu_info cam0_cmu_info __initconst = {
.nr_gate_clks = ARRAY_SIZE(cam0_gate_clks),
.fixed_clks = cam0_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks),
- .nr_clk_ids = CAM0_NR_CLK,
+ .nr_clk_ids = CLKS_NR_CAM0,
.clk_regs = cam0_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cam0_clk_regs),
.suspend_regs = cam0_suspend_regs,
@@ -5440,7 +5463,7 @@ static const struct samsung_cmu_info cam1_cmu_info __initconst = {
.nr_gate_clks = ARRAY_SIZE(cam1_gate_clks),
.fixed_clks = cam1_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks),
- .nr_clk_ids = CAM1_NR_CLK,
+ .nr_clk_ids = CLKS_NR_CAM1,
.clk_regs = cam1_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cam1_clk_regs),
.suspend_regs = cam1_suspend_regs,
@@ -5472,7 +5495,7 @@ static const struct samsung_gate_clock imem_gate_clks[] __initconst = {
static const struct samsung_cmu_info imem_cmu_info __initconst = {
.gate_clks = imem_gate_clks,
.nr_gate_clks = ARRAY_SIZE(imem_gate_clks),
- .nr_clk_ids = IMEM_NR_CLK,
+ .nr_clk_ids = CLKS_NR_IMEM,
.clk_regs = imem_clk_regs,
.nr_clk_regs = ARRAY_SIZE(imem_clk_regs),
.clk_name = "aclk_imem_200",
diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c
index 0d2a950ed184..f7d7427a558b 100644
--- a/drivers/clk/samsung/clk-exynos7885.c
+++ b/drivers/clk/samsung/clk-exynos7885.c
@@ -9,7 +9,6 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/exynos7885.h>
@@ -17,6 +16,12 @@
#include "clk.h"
#include "clk-exynos-arm64.h"
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR_TOP (CLK_GOUT_FSYS_USB30DRD + 1)
+#define CLKS_NR_CORE (CLK_GOUT_TREX_P_CORE_PCLK_P_CORE + 1)
+#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
+#define CLKS_NR_FSYS (CLK_GOUT_MMC_SDIO_SDCLKIN + 1)
+
/* ---- CMU_TOP ------------------------------------------------------------- */
/* Register Offset definitions for CMU_TOP (0x12060000) */
@@ -334,7 +339,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(top_div_clks),
.gate_clks = top_gate_clks,
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
- .nr_clk_ids = TOP_NR_CLK,
+ .nr_clk_ids = CLKS_NR_TOP,
.clk_regs = top_clk_regs,
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
};
@@ -553,7 +558,7 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = {
.nr_mux_clks = ARRAY_SIZE(peri_mux_clks),
.gate_clks = peri_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
- .nr_clk_ids = PERI_NR_CLK,
+ .nr_clk_ids = CLKS_NR_PERI,
.clk_regs = peri_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
.clk_name = "dout_peri_bus",
@@ -662,7 +667,7 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(core_div_clks),
.gate_clks = core_gate_clks,
.nr_gate_clks = ARRAY_SIZE(core_gate_clks),
- .nr_clk_ids = CORE_NR_CLK,
+ .nr_clk_ids = CLKS_NR_CORE,
.clk_regs = core_clk_regs,
.nr_clk_regs = ARRAY_SIZE(core_clk_regs),
.clk_name = "dout_core_bus",
@@ -744,7 +749,7 @@ static const struct samsung_cmu_info fsys_cmu_info __initconst = {
.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
.gate_clks = fsys_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
- .nr_clk_ids = FSYS_NR_CLK,
+ .nr_clk_ids = CLKS_NR_FSYS,
.clk_regs = fsys_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
.clk_name = "dout_fsys_bus",
diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
index 98b23af7324d..bdc1eef7d6e5 100644
--- a/drivers/clk/samsung/clk-exynos850.c
+++ b/drivers/clk/samsung/clk-exynos850.c
@@ -9,7 +9,6 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/exynos850.h>
@@ -17,6 +16,19 @@
#include "clk.h"
#include "clk-exynos-arm64.h"
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR_TOP (CLK_DOUT_G3D_SWITCH + 1)
+#define CLKS_NR_APM (CLK_GOUT_SYSREG_APM_PCLK + 1)
+#define CLKS_NR_AUD (CLK_GOUT_AUD_CMU_AUD_PCLK + 1)
+#define CLKS_NR_CMGP (CLK_GOUT_SYSREG_CMGP_PCLK + 1)
+#define CLKS_NR_G3D (CLK_GOUT_G3D_SYSREG_PCLK + 1)
+#define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1)
+#define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1)
+#define CLKS_NR_MFCMSCL (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1)
+#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
+#define CLKS_NR_CORE (CLK_GOUT_SYSREG_CORE_PCLK + 1)
+#define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_PCLK + 1)
+
/* ---- CMU_TOP ------------------------------------------------------------- */
/* Register Offset definitions for CMU_TOP (0x120e0000) */
@@ -486,7 +498,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(top_div_clks),
.gate_clks = top_gate_clks,
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
- .nr_clk_ids = TOP_NR_CLK,
+ .nr_clk_ids = CLKS_NR_TOP,
.clk_regs = top_clk_regs,
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
};
@@ -626,7 +638,7 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
.nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
.fixed_clks = apm_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
- .nr_clk_ids = APM_NR_CLK,
+ .nr_clk_ids = CLKS_NR_APM,
.clk_regs = apm_clk_regs,
.nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
.clk_name = "dout_clkcmu_apm_bus",
@@ -909,7 +921,7 @@ static const struct samsung_cmu_info aud_cmu_info __initconst = {
.nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
.fixed_clks = aud_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
- .nr_clk_ids = AUD_NR_CLK,
+ .nr_clk_ids = CLKS_NR_AUD,
.clk_regs = aud_clk_regs,
.nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
.clk_name = "dout_aud",
@@ -1012,7 +1024,7 @@ static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
.nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks),
.fixed_clks = cmgp_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks),
- .nr_clk_ids = CMGP_NR_CLK,
+ .nr_clk_ids = CLKS_NR_CMGP,
.clk_regs = cmgp_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs),
.clk_name = "gout_clkcmu_cmgp_bus",
@@ -1108,7 +1120,7 @@ static const struct samsung_cmu_info g3d_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(g3d_div_clks),
.gate_clks = g3d_gate_clks,
.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
- .nr_clk_ids = G3D_NR_CLK,
+ .nr_clk_ids = CLKS_NR_G3D,
.clk_regs = g3d_clk_regs,
.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
.clk_name = "dout_g3d_switch",
@@ -1210,7 +1222,7 @@ static const struct samsung_cmu_info hsi_cmu_info __initconst = {
.nr_mux_clks = ARRAY_SIZE(hsi_mux_clks),
.gate_clks = hsi_gate_clks,
.nr_gate_clks = ARRAY_SIZE(hsi_gate_clks),
- .nr_clk_ids = HSI_NR_CLK,
+ .nr_clk_ids = CLKS_NR_HSI,
.clk_regs = hsi_clk_regs,
.nr_clk_regs = ARRAY_SIZE(hsi_clk_regs),
.clk_name = "dout_hsi_bus",
@@ -1342,7 +1354,7 @@ static const struct samsung_cmu_info is_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(is_div_clks),
.gate_clks = is_gate_clks,
.nr_gate_clks = ARRAY_SIZE(is_gate_clks),
- .nr_clk_ids = IS_NR_CLK,
+ .nr_clk_ids = CLKS_NR_IS,
.clk_regs = is_clk_regs,
.nr_clk_regs = ARRAY_SIZE(is_clk_regs),
.clk_name = "dout_is_bus",
@@ -1451,7 +1463,7 @@ static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks),
.gate_clks = mfcmscl_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks),
- .nr_clk_ids = MFCMSCL_NR_CLK,
+ .nr_clk_ids = CLKS_NR_MFCMSCL,
.clk_regs = mfcmscl_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs),
.clk_name = "dout_mfcmscl_mfc",
@@ -1626,7 +1638,7 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(peri_div_clks),
.gate_clks = peri_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
- .nr_clk_ids = PERI_NR_CLK,
+ .nr_clk_ids = CLKS_NR_PERI,
.clk_regs = peri_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
.clk_name = "dout_peri_bus",
@@ -1733,7 +1745,7 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(core_div_clks),
.gate_clks = core_gate_clks,
.nr_gate_clks = ARRAY_SIZE(core_gate_clks),
- .nr_clk_ids = CORE_NR_CLK,
+ .nr_clk_ids = CLKS_NR_CORE,
.clk_regs = core_clk_regs,
.nr_clk_regs = ARRAY_SIZE(core_clk_regs),
.clk_name = "dout_core_bus",
@@ -1807,7 +1819,7 @@ static const struct samsung_cmu_info dpu_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(dpu_div_clks),
.gate_clks = dpu_gate_clks,
.nr_gate_clks = ARRAY_SIZE(dpu_gate_clks),
- .nr_clk_ids = DPU_NR_CLK,
+ .nr_clk_ids = CLKS_NR_DPU,
.clk_regs = dpu_clk_regs,
.nr_clk_regs = ARRAY_SIZE(dpu_clk_regs),
.clk_name = "dout_dpu",
diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
index 7b16320bba66..e9c06eb93e66 100644
--- a/drivers/clk/samsung/clk-exynosautov9.c
+++ b/drivers/clk/samsung/clk-exynosautov9.c
@@ -9,8 +9,6 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/samsung,exynosautov9.h>
@@ -18,6 +16,17 @@
#include "clk.h"
#include "clk-exynos-arm64.h"
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR_TOP (GOUT_CLKCMU_PERIS_BUS + 1)
+#define CLKS_NR_BUSMC (CLK_GOUT_BUSMC_SPDMA_PCLK + 1)
+#define CLKS_NR_CORE (CLK_GOUT_CORE_CMU_CORE_PCLK + 1)
+#define CLKS_NR_FSYS0 (CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK + 1)
+#define CLKS_NR_FSYS1 (CLK_GOUT_FSYS1_USB30_1_ACLK + 1)
+#define CLKS_NR_FSYS2 (CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO + 1)
+#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_PCLK_11 + 1)
+#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_PCLK_11 + 1)
+#define CLKS_NR_PERIS (CLK_GOUT_WDT_CLUSTER1 + 1)
+
/* ---- CMU_TOP ------------------------------------------------------------ */
/* Register Offset definitions for CMU_TOP (0x1b240000) */
@@ -943,7 +952,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
.nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
.gate_clks = top_gate_clks,
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
- .nr_clk_ids = TOP_NR_CLK,
+ .nr_clk_ids = CLKS_NR_TOP,
.clk_regs = top_clk_regs,
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
};
@@ -1003,7 +1012,7 @@ static const struct samsung_cmu_info busmc_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(busmc_div_clks),
.gate_clks = busmc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(busmc_gate_clks),
- .nr_clk_ids = BUSMC_NR_CLK,
+ .nr_clk_ids = CLKS_NR_BUSMC,
.clk_regs = busmc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(busmc_clk_regs),
.clk_name = "dout_clkcmu_busmc_bus",
@@ -1061,7 +1070,7 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(core_div_clks),
.gate_clks = core_gate_clks,
.nr_gate_clks = ARRAY_SIZE(core_gate_clks),
- .nr_clk_ids = CORE_NR_CLK,
+ .nr_clk_ids = CLKS_NR_CORE,
.clk_regs = core_clk_regs,
.nr_clk_regs = ARRAY_SIZE(core_clk_regs),
.clk_name = "dout_clkcmu_core_bus",
@@ -1301,7 +1310,7 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
.nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
.gate_clks = fsys0_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
- .nr_clk_ids = FSYS0_NR_CLK,
+ .nr_clk_ids = CLKS_NR_FSYS0,
.clk_regs = fsys0_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
.clk_name = "dout_clkcmu_fsys0_bus",
@@ -1428,7 +1437,7 @@ static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
.gate_clks = fsys1_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
- .nr_clk_ids = FSYS1_NR_CLK,
+ .nr_clk_ids = CLKS_NR_FSYS1,
.clk_regs = fsys1_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
.clk_name = "dout_clkcmu_fsys1_bus",
@@ -1495,7 +1504,7 @@ static const struct samsung_cmu_info fsys2_cmu_info __initconst = {
.nr_mux_clks = ARRAY_SIZE(fsys2_mux_clks),
.gate_clks = fsys2_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys2_gate_clks),
- .nr_clk_ids = FSYS2_NR_CLK,
+ .nr_clk_ids = CLKS_NR_FSYS2,
.clk_regs = fsys2_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys2_clk_regs),
.clk_name = "dout_clkcmu_fsys2_bus",
@@ -1750,7 +1759,7 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(peric0_div_clks),
.gate_clks = peric0_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
- .nr_clk_ids = PERIC0_NR_CLK,
+ .nr_clk_ids = CLKS_NR_PERIC0,
.clk_regs = peric0_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
.clk_name = "dout_clkcmu_peric0_bus",
@@ -2005,7 +2014,7 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(peric1_div_clks),
.gate_clks = peric1_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
- .nr_clk_ids = PERIC1_NR_CLK,
+ .nr_clk_ids = CLKS_NR_PERIC1,
.clk_regs = peric1_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
.clk_name = "dout_clkcmu_peric1_bus",
@@ -2052,7 +2061,7 @@ static const struct samsung_cmu_info peris_cmu_info __initconst = {
.nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
.gate_clks = peris_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
- .nr_clk_ids = PERIS_NR_CLK,
+ .nr_clk_ids = CLKS_NR_PERIS,
.clk_regs = peris_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
.clk_name = "dout_clkcmu_peris_bus",
diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
index 5d009c70e97d..6f984cfcd33c 100644
--- a/drivers/clk/samsung/clk-fsd.c
+++ b/drivers/clk/samsung/clk-fsd.c
@@ -13,8 +13,6 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/fsd-clk.h>
diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c
index e317f3454e93..af81eb835bc2 100644
--- a/drivers/clk/sifive/sifive-prci.c
+++ b/drivers/clk/sifive/sifive-prci.c
@@ -7,7 +7,7 @@
#include <linux/clkdev.h>
#include <linux/delay.h>
#include <linux/io.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include "sifive-prci.h"
#include "fu540-prci.h"
#include "fu740-prci.h"
diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
index 74d21bd82710..6b65a74aefa6 100644
--- a/drivers/clk/socfpga/clk-agilex.c
+++ b/drivers/clk/socfpga/clk-agilex.c
@@ -4,8 +4,7 @@
*/
#include <linux/slab.h>
#include <linux/clk-provider.h>
-#include <linux/of_device.h>
-#include <linux/of_address.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/agilex-clock.h>
@@ -458,12 +457,10 @@ static int agilex_clkmgr_init(struct platform_device *pdev)
struct device_node *np = pdev->dev.of_node;
struct device *dev = &pdev->dev;
struct stratix10_clock_data *clk_data;
- struct resource *res;
void __iomem *base;
int i, num_clks;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- base = devm_ioremap_resource(dev, res);
+ base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
index 9b2e0275fbf7..3752bd9c103c 100644
--- a/drivers/clk/socfpga/clk-s10.c
+++ b/drivers/clk/socfpga/clk-s10.c
@@ -4,8 +4,7 @@
*/
#include <linux/slab.h>
#include <linux/clk-provider.h>
-#include <linux/of_device.h>
-#include <linux/of_address.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/stratix10-clock.h>
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 9d5959a4251a..0847f5452489 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -12,7 +12,6 @@
#include <linux/clk/spear.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <linux/of_platform.h>
#include <linux/spinlock_types.h>
#include "clk.h"
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index 8b51229d0471..361d344bfaf0 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -12,7 +12,6 @@
#include <linux/clk/spear.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <linux/of_platform.h>
#include <linux/spinlock_types.h>
#include "clk.h"
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
index ba8791303156..6c0af99b0578 100644
--- a/drivers/clk/spear/spear3xx_clock.c
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -11,7 +11,7 @@
#include <linux/clk/spear.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <linux/of_platform.h>
+#include <linux/of.h>
#include <linux/spinlock_types.h>
#include "clk.h"
diff --git a/drivers/clk/sprd/common.c b/drivers/clk/sprd/common.c
index 16142fbb7a47..762f0961f17f 100644
--- a/drivers/clk/sprd/common.c
+++ b/drivers/clk/sprd/common.c
@@ -8,7 +8,7 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_address.h>
-#include <linux/of_platform.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "common.h"
diff --git a/drivers/clk/sprd/sc9860-clk.c b/drivers/clk/sprd/sc9860-clk.c
index f76305b4bc8d..cc5ed2dd8267 100644
--- a/drivers/clk/sprd/sc9860-clk.c
+++ b/drivers/clk/sprd/sc9860-clk.c
@@ -9,7 +9,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
diff --git a/drivers/clk/sprd/ums512-clk.c b/drivers/clk/sprd/ums512-clk.c
index fc25bdd85e4e..8f4441dd572b 100644
--- a/drivers/clk/sprd/ums512-clk.c
+++ b/drivers/clk/sprd/ums512-clk.c
@@ -9,8 +9,8 @@
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/io.h>
+#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 5d2333106f13..bd29358ffeec 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -21,12 +21,21 @@ config CLK_STARFIVE_JH7100_AUDIO
Say Y or M here to support the audio clocks on the StarFive JH7100
SoC.
+config CLK_STARFIVE_JH7110_PLL
+ bool "StarFive JH7110 PLL clock support"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the PLL clock controller on the
+ StarFive JH7110 SoC.
+
config CLK_STARFIVE_JH7110_SYS
bool "StarFive JH7110 system clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
select AUXILIARY_BUS
select CLK_STARFIVE_JH71X0
select RESET_STARFIVE_JH7110 if RESET_CONTROLLER
+ select CLK_STARFIVE_JH7110_PLL
default ARCH_STARFIVE
help
Say yes here to support the system clock controller on the
@@ -39,3 +48,27 @@ config CLK_STARFIVE_JH7110_AON
help
Say yes here to support the always-on clock controller on the
StarFive JH7110 SoC.
+
+config CLK_STARFIVE_JH7110_STG
+ tristate "StarFive JH7110 System-Top-Group clock support"
+ depends on CLK_STARFIVE_JH7110_SYS
+ default m if ARCH_STARFIVE
+ help
+ Say yes here to support the System-Top-Group clock controller
+ on the StarFive JH7110 SoC.
+
+config CLK_STARFIVE_JH7110_ISP
+ tristate "StarFive JH7110 Image-Signal-Process clock support"
+ depends on CLK_STARFIVE_JH7110_SYS && JH71XX_PMU
+ default m if ARCH_STARFIVE
+ help
+ Say yes here to support the Image-Signal-Process clock controller
+ on the StarFive JH7110 SoC.
+
+config CLK_STARFIVE_JH7110_VOUT
+ tristate "StarFive JH7110 Video-Output clock support"
+ depends on CLK_STARFIVE_JH7110_SYS && JH71XX_PMU
+ default m if ARCH_STARFIVE
+ help
+ Say yes here to support the Video-Output clock controller
+ on the StarFive JH7110 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index f3df7d957b1e..199ac0f37a2f 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -4,5 +4,9 @@ obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk-starfive-jh71x0.o
obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
+obj-$(CONFIG_CLK_STARFIVE_JH7110_PLL) += clk-starfive-jh7110-pll.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
+obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
+obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
+obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
index 02aefb7264f8..ee4bda14a40e 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
@@ -11,7 +11,6 @@
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/starfive-jh7100-audio.h>
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-isp.c b/drivers/clk/starfive/clk-starfive-jh7110-isp.c
new file mode 100644
index 000000000000..ce034ed28532
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh7110-isp.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 Image-Signal-Process Clock Driver
+ *
+ * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+
+#include "clk-starfive-jh7110.h"
+
+/* external clocks */
+#define JH7110_ISPCLK_ISP_TOP_CORE (JH7110_ISPCLK_END + 0)
+#define JH7110_ISPCLK_ISP_TOP_AXI (JH7110_ISPCLK_END + 1)
+#define JH7110_ISPCLK_NOC_BUS_ISP_AXI (JH7110_ISPCLK_END + 2)
+#define JH7110_ISPCLK_DVP_CLK (JH7110_ISPCLK_END + 3)
+#define JH7110_ISPCLK_EXT_END (JH7110_ISPCLK_END + 4)
+
+static struct clk_bulk_data jh7110_isp_top_clks[] = {
+ { .id = "isp_top_core" },
+ { .id = "isp_top_axi" }
+};
+
+static const struct jh71x0_clk_data jh7110_ispclk_data[] = {
+ /* syscon */
+ JH71X0__DIV(JH7110_ISPCLK_DOM4_APB_FUNC, "dom4_apb_func", 15,
+ JH7110_ISPCLK_ISP_TOP_AXI),
+ JH71X0__DIV(JH7110_ISPCLK_MIPI_RX0_PXL, "mipi_rx0_pxl", 8,
+ JH7110_ISPCLK_ISP_TOP_CORE),
+ JH71X0__INV(JH7110_ISPCLK_DVP_INV, "dvp_inv", JH7110_ISPCLK_DVP_CLK),
+ /* vin */
+ JH71X0__DIV(JH7110_ISPCLK_M31DPHY_CFG_IN, "m31dphy_cfg_in", 16,
+ JH7110_ISPCLK_ISP_TOP_CORE),
+ JH71X0__DIV(JH7110_ISPCLK_M31DPHY_REF_IN, "m31dphy_ref_in", 16,
+ JH7110_ISPCLK_ISP_TOP_CORE),
+ JH71X0__DIV(JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0, "m31dphy_tx_esc_lan0", 60,
+ JH7110_ISPCLK_ISP_TOP_CORE),
+ JH71X0_GATE(JH7110_ISPCLK_VIN_APB, "vin_apb", 0,
+ JH7110_ISPCLK_DOM4_APB_FUNC),
+ JH71X0__DIV(JH7110_ISPCLK_VIN_SYS, "vin_sys", 8, JH7110_ISPCLK_ISP_TOP_CORE),
+ JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF0, "vin_pixel_if0", 0,
+ JH7110_ISPCLK_MIPI_RX0_PXL),
+ JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF1, "vin_pixel_if1", 0,
+ JH7110_ISPCLK_MIPI_RX0_PXL),
+ JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF2, "vin_pixel_if2", 0,
+ JH7110_ISPCLK_MIPI_RX0_PXL),
+ JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", 0,
+ JH7110_ISPCLK_MIPI_RX0_PXL),
+ JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 2,
+ JH7110_ISPCLK_MIPI_RX0_PXL,
+ JH7110_ISPCLK_DVP_INV),
+ /* ispv2_top_wrapper */
+ JH71X0_GMUX(JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C, "ispv2_top_wrapper_c", 0, 2,
+ JH7110_ISPCLK_MIPI_RX0_PXL,
+ JH7110_ISPCLK_DVP_INV),
+};
+
+static inline int jh7110_isp_top_rst_init(struct jh71x0_clk_priv *priv)
+{
+ struct reset_control *top_rsts;
+
+ /* The resets should be shared and other ISP modules will use its. */
+ top_rsts = devm_reset_control_array_get_shared(priv->dev);
+ if (IS_ERR(top_rsts))
+ return dev_err_probe(priv->dev, PTR_ERR(top_rsts),
+ "failed to get top resets\n");
+
+ return reset_control_deassert(top_rsts);
+}
+
+static struct clk_hw *jh7110_ispclk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct jh71x0_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < JH7110_ISPCLK_END)
+ return &priv->reg[idx].hw;
+
+ return ERR_PTR(-EINVAL);
+}
+
+#ifdef CONFIG_PM
+static int jh7110_ispcrg_suspend(struct device *dev)
+{
+ struct jh7110_top_sysclk *top = dev_get_drvdata(dev);
+
+ clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);
+
+ return 0;
+}
+
+static int jh7110_ispcrg_resume(struct device *dev)
+{
+ struct jh7110_top_sysclk *top = dev_get_drvdata(dev);
+
+ return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks);
+}
+
+static const struct dev_pm_ops jh7110_ispcrg_pm_ops = {
+ RUNTIME_PM_OPS(jh7110_ispcrg_suspend, jh7110_ispcrg_resume, NULL)
+};
+#endif
+
+static int jh7110_ispcrg_probe(struct platform_device *pdev)
+{
+ struct jh71x0_clk_priv *priv;
+ struct jh7110_top_sysclk *top;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JH7110_ISPCLK_END),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL);
+ if (!top)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ top->top_clks = jh7110_isp_top_clks;
+ top->top_clks_num = ARRAY_SIZE(jh7110_isp_top_clks);
+ ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks);
+ if (ret)
+ return dev_err_probe(priv->dev, ret, "failed to get main clocks\n");
+ dev_set_drvdata(priv->dev, top);
+
+ /* enable power domain and clocks */
+ pm_runtime_enable(priv->dev);
+ ret = pm_runtime_get_sync(priv->dev);
+ if (ret < 0)
+ return dev_err_probe(priv->dev, ret, "failed to turn on power\n");
+
+ ret = jh7110_isp_top_rst_init(priv);
+ if (ret)
+ goto err_exit;
+
+ for (idx = 0; idx < JH7110_ISPCLK_END; idx++) {
+ u32 max = jh7110_ispclk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh7110_ispclk_data[idx].name,
+ .ops = starfive_jh71x0_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
+ .flags = jh7110_ispclk_data[idx].flags,
+ };
+ struct jh71x0_clk *clk = &priv->reg[idx];
+ unsigned int i;
+ const char *fw_name[JH7110_ISPCLK_EXT_END - JH7110_ISPCLK_END] = {
+ "isp_top_core",
+ "isp_top_axi",
+ "noc_bus_isp_axi",
+ "dvp_clk"
+ };
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh7110_ispclk_data[idx].parents[i];
+
+ if (pidx < JH7110_ISPCLK_END)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else
+ parents[i].fw_name = fw_name[pidx - JH7110_ISPCLK_END];
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & JH71X0_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ goto err_exit;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_ispclk_get, priv);
+ if (ret)
+ goto err_exit;
+
+ ret = jh7110_reset_controller_register(priv, "rst-isp", 3);
+ if (ret)
+ goto err_exit;
+
+ return 0;
+
+err_exit:
+ pm_runtime_put_sync(priv->dev);
+ pm_runtime_disable(priv->dev);
+ return ret;
+}
+
+static int jh7110_ispcrg_remove(struct platform_device *pdev)
+{
+ pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+static const struct of_device_id jh7110_ispcrg_match[] = {
+ { .compatible = "starfive,jh7110-ispcrg" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jh7110_ispcrg_match);
+
+static struct platform_driver jh7110_ispcrg_driver = {
+ .probe = jh7110_ispcrg_probe,
+ .remove = jh7110_ispcrg_remove,
+ .driver = {
+ .name = "clk-starfive-jh7110-isp",
+ .of_match_table = jh7110_ispcrg_match,
+ .pm = pm_ptr(&jh7110_ispcrg_pm_ops),
+ },
+};
+module_platform_driver(jh7110_ispcrg_driver);
+
+MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JH7110 Image-Signal-Process clock driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-pll.c b/drivers/clk/starfive/clk-starfive-jh7110-pll.c
new file mode 100644
index 000000000000..3598390e8fd0
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh7110-pll.c
@@ -0,0 +1,507 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 PLL Clock Generator Driver
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Copyright (C) 2023 Emil Renner Berthing <emil.renner.berthing@canonical.com>
+ *
+ * This driver is about to register JH7110 PLL clock generator and support ops.
+ * The JH7110 have three PLL clock, PLL0, PLL1 and PLL2.
+ * Each PLL clocks work in integer mode or fraction mode by some dividers,
+ * and the configuration registers and dividers are set in several syscon registers.
+ * The formula for calculating frequency is:
+ * Fvco = Fref * (NI + NF) / M / Q1
+ * Fref: OSC source clock rate
+ * NI: integer frequency dividing ratio of feedback divider, set by fbdiv[11:0].
+ * NF: fractional frequency dividing ratio, set by frac[23:0]. NF = frac[23:0] / 2^24 = 0 ~ 0.999.
+ * M: frequency dividing ratio of pre-divider, set by prediv[5:0].
+ * Q1: frequency dividing ratio of post divider, set by 2^postdiv1[1:0], eg. 1, 2, 4 or 8.
+ */
+
+#include <linux/bits.h>
+#include <linux/clk-provider.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+
+/* this driver expects a 24MHz input frequency from the oscillator */
+#define JH7110_PLL_OSC_RATE 24000000UL
+
+#define JH7110_PLL0_PD_OFFSET 0x18
+#define JH7110_PLL0_DACPD_SHIFT 24
+#define JH7110_PLL0_DACPD_MASK BIT(24)
+#define JH7110_PLL0_DSMPD_SHIFT 25
+#define JH7110_PLL0_DSMPD_MASK BIT(25)
+#define JH7110_PLL0_FBDIV_OFFSET 0x1c
+#define JH7110_PLL0_FBDIV_SHIFT 0
+#define JH7110_PLL0_FBDIV_MASK GENMASK(11, 0)
+#define JH7110_PLL0_FRAC_OFFSET 0x20
+#define JH7110_PLL0_PREDIV_OFFSET 0x24
+
+#define JH7110_PLL1_PD_OFFSET 0x24
+#define JH7110_PLL1_DACPD_SHIFT 15
+#define JH7110_PLL1_DACPD_MASK BIT(15)
+#define JH7110_PLL1_DSMPD_SHIFT 16
+#define JH7110_PLL1_DSMPD_MASK BIT(16)
+#define JH7110_PLL1_FBDIV_OFFSET 0x24
+#define JH7110_PLL1_FBDIV_SHIFT 17
+#define JH7110_PLL1_FBDIV_MASK GENMASK(28, 17)
+#define JH7110_PLL1_FRAC_OFFSET 0x28
+#define JH7110_PLL1_PREDIV_OFFSET 0x2c
+
+#define JH7110_PLL2_PD_OFFSET 0x2c
+#define JH7110_PLL2_DACPD_SHIFT 15
+#define JH7110_PLL2_DACPD_MASK BIT(15)
+#define JH7110_PLL2_DSMPD_SHIFT 16
+#define JH7110_PLL2_DSMPD_MASK BIT(16)
+#define JH7110_PLL2_FBDIV_OFFSET 0x2c
+#define JH7110_PLL2_FBDIV_SHIFT 17
+#define JH7110_PLL2_FBDIV_MASK GENMASK(28, 17)
+#define JH7110_PLL2_FRAC_OFFSET 0x30
+#define JH7110_PLL2_PREDIV_OFFSET 0x34
+
+#define JH7110_PLL_FRAC_SHIFT 0
+#define JH7110_PLL_FRAC_MASK GENMASK(23, 0)
+#define JH7110_PLL_POSTDIV1_SHIFT 28
+#define JH7110_PLL_POSTDIV1_MASK GENMASK(29, 28)
+#define JH7110_PLL_PREDIV_SHIFT 0
+#define JH7110_PLL_PREDIV_MASK GENMASK(5, 0)
+
+enum jh7110_pll_mode {
+ JH7110_PLL_MODE_FRACTION,
+ JH7110_PLL_MODE_INTEGER,
+};
+
+struct jh7110_pll_preset {
+ unsigned long freq;
+ u32 frac; /* frac value should be decimals multiplied by 2^24 */
+ unsigned fbdiv : 12; /* fbdiv value should be 8 to 4095 */
+ unsigned prediv : 6;
+ unsigned postdiv1 : 2;
+ unsigned mode : 1;
+};
+
+struct jh7110_pll_info {
+ char *name;
+ const struct jh7110_pll_preset *presets;
+ unsigned int npresets;
+ struct {
+ unsigned int pd;
+ unsigned int fbdiv;
+ unsigned int frac;
+ unsigned int prediv;
+ } offsets;
+ struct {
+ u32 dacpd;
+ u32 dsmpd;
+ u32 fbdiv;
+ } masks;
+ struct {
+ char dacpd;
+ char dsmpd;
+ char fbdiv;
+ } shifts;
+};
+
+#define _JH7110_PLL(_idx, _name, _presets) \
+ [_idx] = { \
+ .name = _name, \
+ .presets = _presets, \
+ .npresets = ARRAY_SIZE(_presets), \
+ .offsets = { \
+ .pd = JH7110_PLL##_idx##_PD_OFFSET, \
+ .fbdiv = JH7110_PLL##_idx##_FBDIV_OFFSET, \
+ .frac = JH7110_PLL##_idx##_FRAC_OFFSET, \
+ .prediv = JH7110_PLL##_idx##_PREDIV_OFFSET, \
+ }, \
+ .masks = { \
+ .dacpd = JH7110_PLL##_idx##_DACPD_MASK, \
+ .dsmpd = JH7110_PLL##_idx##_DSMPD_MASK, \
+ .fbdiv = JH7110_PLL##_idx##_FBDIV_MASK, \
+ }, \
+ .shifts = { \
+ .dacpd = JH7110_PLL##_idx##_DACPD_SHIFT, \
+ .dsmpd = JH7110_PLL##_idx##_DSMPD_SHIFT, \
+ .fbdiv = JH7110_PLL##_idx##_FBDIV_SHIFT, \
+ }, \
+ }
+#define JH7110_PLL(idx, name, presets) _JH7110_PLL(idx, name, presets)
+
+struct jh7110_pll_data {
+ struct clk_hw hw;
+ unsigned int idx;
+};
+
+struct jh7110_pll_priv {
+ struct device *dev;
+ struct regmap *regmap;
+ struct jh7110_pll_data pll[JH7110_PLLCLK_END];
+};
+
+struct jh7110_pll_regvals {
+ u32 dacpd;
+ u32 dsmpd;
+ u32 fbdiv;
+ u32 frac;
+ u32 postdiv1;
+ u32 prediv;
+};
+
+/*
+ * Because the pll frequency is relatively fixed,
+ * it cannot be set arbitrarily, so it needs a specific configuration.
+ * PLL0 frequency should be multiple of 125MHz (USB frequency).
+ */
+static const struct jh7110_pll_preset jh7110_pll0_presets[] = {
+ {
+ .freq = 375000000,
+ .fbdiv = 125,
+ .prediv = 8,
+ .postdiv1 = 0,
+ .mode = JH7110_PLL_MODE_INTEGER,
+ }, {
+ .freq = 500000000,
+ .fbdiv = 125,
+ .prediv = 6,
+ .postdiv1 = 0,
+ .mode = JH7110_PLL_MODE_INTEGER,
+ }, {
+ .freq = 625000000,
+ .fbdiv = 625,
+ .prediv = 24,
+ .postdiv1 = 0,
+ .mode = JH7110_PLL_MODE_INTEGER,
+ }, {
+ .freq = 750000000,
+ .fbdiv = 125,
+ .prediv = 4,
+ .postdiv1 = 0,
+ .mode = JH7110_PLL_MODE_INTEGER,
+ }, {
+ .freq = 875000000,
+ .fbdiv = 875,
+ .prediv = 24,
+ .postdiv1 = 0,
+ .mode = JH7110_PLL_MODE_INTEGER,
+ }, {
+ .freq = 1000000000,
+ .fbdiv = 125,
+ .prediv = 3,
+ .postdiv1 = 0,
+ .mode = JH7110_PLL_MODE_INTEGER,
+ }, {
+ .freq = 1250000000,
+ .fbdiv = 625,
+ .prediv = 12,
+ .postdiv1 = 0,
+ .mode = JH7110_PLL_MODE_INTEGER,
+ }, {
+ .freq = 1375000000,
+ .fbdiv = 1375,
+ .prediv = 24,
+ .postdiv1 = 0,
+ .mode = JH7110_PLL_MODE_INTEGER,
+ }, {
+ .freq = 1500000000,
+ .fbdiv = 125,
+ .prediv = 2,
+ .postdiv1 = 0,
+ .mode = JH7110_PLL_MODE_INTEGER,
+ },
+};
+
+static const struct jh7110_pll_preset jh7110_pll1_presets[] = {
+ {
+ .freq = 1066000000,
+ .fbdiv = 533,
+ .prediv = 12,
+ .postdiv1 = 0,
+ .mode = JH7110_PLL_MODE_INTEGER,
+ }, {
+ .freq = 1200000000,
+ .fbdiv = 50,
+ .prediv = 1,
+ .postdiv1 = 0,
+ .mode = JH7110_PLL_MODE_INTEGER,
+ }, {
+ .freq = 1400000000,
+ .fbdiv = 350,
+ .prediv = 6,
+ .postdiv1 = 0,
+ .mode = JH7110_PLL_MODE_INTEGER,
+ }, {
+ .freq = 1600000000,
+ .fbdiv = 200,
+ .prediv = 3,
+ .postdiv1 = 0,
+ .mode = JH7110_PLL_MODE_INTEGER,
+ },
+};
+
+static const struct jh7110_pll_preset jh7110_pll2_presets[] = {
+ {
+ .freq = 1188000000,
+ .fbdiv = 99,
+ .prediv = 2,
+ .postdiv1 = 0,
+ .mode = JH7110_PLL_MODE_INTEGER,
+ }, {
+ .freq = 1228800000,
+ .fbdiv = 256,
+ .prediv = 5,
+ .postdiv1 = 0,
+ .mode = JH7110_PLL_MODE_INTEGER,
+ },
+};
+
+static const struct jh7110_pll_info jh7110_plls[JH7110_PLLCLK_END] = {
+ JH7110_PLL(JH7110_PLLCLK_PLL0_OUT, "pll0_out", jh7110_pll0_presets),
+ JH7110_PLL(JH7110_PLLCLK_PLL1_OUT, "pll1_out", jh7110_pll1_presets),
+ JH7110_PLL(JH7110_PLLCLK_PLL2_OUT, "pll2_out", jh7110_pll2_presets),
+};
+
+static struct jh7110_pll_data *jh7110_pll_data_from(struct clk_hw *hw)
+{
+ return container_of(hw, struct jh7110_pll_data, hw);
+}
+
+static struct jh7110_pll_priv *jh7110_pll_priv_from(struct jh7110_pll_data *pll)
+{
+ return container_of(pll, struct jh7110_pll_priv, pll[pll->idx]);
+}
+
+static void jh7110_pll_regvals_get(struct regmap *regmap,
+ const struct jh7110_pll_info *info,
+ struct jh7110_pll_regvals *ret)
+{
+ u32 val;
+
+ regmap_read(regmap, info->offsets.pd, &val);
+ ret->dacpd = (val & info->masks.dacpd) >> info->shifts.dacpd;
+ ret->dsmpd = (val & info->masks.dsmpd) >> info->shifts.dsmpd;
+
+ regmap_read(regmap, info->offsets.fbdiv, &val);
+ ret->fbdiv = (val & info->masks.fbdiv) >> info->shifts.fbdiv;
+
+ regmap_read(regmap, info->offsets.frac, &val);
+ ret->frac = (val & JH7110_PLL_FRAC_MASK) >> JH7110_PLL_FRAC_SHIFT;
+ ret->postdiv1 = (val & JH7110_PLL_POSTDIV1_MASK) >> JH7110_PLL_POSTDIV1_SHIFT;
+
+ regmap_read(regmap, info->offsets.prediv, &val);
+ ret->prediv = (val & JH7110_PLL_PREDIV_MASK) >> JH7110_PLL_PREDIV_SHIFT;
+}
+
+static unsigned long jh7110_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
+ struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll);
+ struct jh7110_pll_regvals val;
+ unsigned long rate;
+
+ jh7110_pll_regvals_get(priv->regmap, &jh7110_plls[pll->idx], &val);
+
+ /*
+ * dacpd = dsmpd = 0: fraction mode
+ * dacpd = dsmpd = 1: integer mode, frac value ignored
+ *
+ * rate = parent * (fbdiv + frac/2^24) / prediv / 2^postdiv1
+ * = (parent * fbdiv + parent * frac / 2^24) / (prediv * 2^postdiv1)
+ */
+ if (val.dacpd == 0 && val.dsmpd == 0)
+ rate = parent_rate * val.frac / (1UL << 24);
+ else if (val.dacpd == 1 && val.dsmpd == 1)
+ rate = 0;
+ else
+ return 0;
+
+ rate += parent_rate * val.fbdiv;
+ rate /= val.prediv << val.postdiv1;
+
+ return rate;
+}
+
+static int jh7110_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
+{
+ struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
+ const struct jh7110_pll_info *info = &jh7110_plls[pll->idx];
+ const struct jh7110_pll_preset *selected = &info->presets[0];
+ unsigned int idx;
+
+ /* if the parent rate doesn't match our expectations the presets won't work */
+ if (req->best_parent_rate != JH7110_PLL_OSC_RATE) {
+ req->rate = jh7110_pll_recalc_rate(hw, req->best_parent_rate);
+ return 0;
+ }
+
+ /* find highest rate lower or equal to the requested rate */
+ for (idx = 1; idx < info->npresets; idx++) {
+ const struct jh7110_pll_preset *val = &info->presets[idx];
+
+ if (req->rate < val->freq)
+ break;
+
+ selected = val;
+ }
+
+ req->rate = selected->freq;
+ return 0;
+}
+
+static int jh7110_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
+ struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll);
+ const struct jh7110_pll_info *info = &jh7110_plls[pll->idx];
+ const struct jh7110_pll_preset *val;
+ unsigned int idx;
+
+ /* if the parent rate doesn't match our expectations the presets won't work */
+ if (parent_rate != JH7110_PLL_OSC_RATE)
+ return -EINVAL;
+
+ for (idx = 0, val = &info->presets[0]; idx < info->npresets; idx++, val++) {
+ if (val->freq == rate)
+ goto found;
+ }
+ return -EINVAL;
+
+found:
+ if (val->mode == JH7110_PLL_MODE_FRACTION)
+ regmap_update_bits(priv->regmap, info->offsets.frac, JH7110_PLL_FRAC_MASK,
+ val->frac << JH7110_PLL_FRAC_SHIFT);
+
+ regmap_update_bits(priv->regmap, info->offsets.pd, info->masks.dacpd,
+ (u32)val->mode << info->shifts.dacpd);
+ regmap_update_bits(priv->regmap, info->offsets.pd, info->masks.dsmpd,
+ (u32)val->mode << info->shifts.dsmpd);
+ regmap_update_bits(priv->regmap, info->offsets.prediv, JH7110_PLL_PREDIV_MASK,
+ (u32)val->prediv << JH7110_PLL_PREDIV_SHIFT);
+ regmap_update_bits(priv->regmap, info->offsets.fbdiv, info->masks.fbdiv,
+ val->fbdiv << info->shifts.fbdiv);
+ regmap_update_bits(priv->regmap, info->offsets.frac, JH7110_PLL_POSTDIV1_MASK,
+ (u32)val->postdiv1 << JH7110_PLL_POSTDIV1_SHIFT);
+
+ return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static int jh7110_pll_registers_read(struct seq_file *s, void *unused)
+{
+ struct jh7110_pll_data *pll = s->private;
+ struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll);
+ struct jh7110_pll_regvals val;
+
+ jh7110_pll_regvals_get(priv->regmap, &jh7110_plls[pll->idx], &val);
+
+ seq_printf(s, "fbdiv=%u\n"
+ "frac=%u\n"
+ "prediv=%u\n"
+ "postdiv1=%u\n"
+ "dacpd=%u\n"
+ "dsmpd=%u\n",
+ val.fbdiv, val.frac, val.prediv, val.postdiv1,
+ val.dacpd, val.dsmpd);
+
+ return 0;
+}
+
+static int jh7110_pll_registers_open(struct inode *inode, struct file *f)
+{
+ return single_open(f, jh7110_pll_registers_read, inode->i_private);
+}
+
+static const struct file_operations jh7110_pll_registers_ops = {
+ .owner = THIS_MODULE,
+ .open = jh7110_pll_registers_open,
+ .release = single_release,
+ .read = seq_read,
+ .llseek = seq_lseek
+};
+
+static void jh7110_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
+{
+ struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
+
+ debugfs_create_file("registers", 0400, dentry, pll,
+ &jh7110_pll_registers_ops);
+}
+#else
+#define jh7110_pll_debug_init NULL
+#endif
+
+static const struct clk_ops jh7110_pll_ops = {
+ .recalc_rate = jh7110_pll_recalc_rate,
+ .determine_rate = jh7110_pll_determine_rate,
+ .set_rate = jh7110_pll_set_rate,
+ .debug_init = jh7110_pll_debug_init,
+};
+
+static struct clk_hw *jh7110_pll_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct jh7110_pll_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < JH7110_PLLCLK_END)
+ return &priv->pll[idx].hw;
+
+ return ERR_PTR(-EINVAL);
+}
+
+static int jh7110_pll_probe(struct platform_device *pdev)
+{
+ struct jh7110_pll_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = &pdev->dev;
+ priv->regmap = syscon_node_to_regmap(priv->dev->of_node->parent);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ for (idx = 0; idx < JH7110_PLLCLK_END; idx++) {
+ struct clk_parent_data parents = {
+ .index = 0,
+ };
+ struct clk_init_data init = {
+ .name = jh7110_plls[idx].name,
+ .ops = &jh7110_pll_ops,
+ .parent_data = &parents,
+ .num_parents = 1,
+ .flags = 0,
+ };
+ struct jh7110_pll_data *pll = &priv->pll[idx];
+
+ pll->hw.init = &init;
+ pll->idx = idx;
+
+ ret = devm_clk_hw_register(&pdev->dev, &pll->hw);
+ if (ret)
+ return ret;
+ }
+
+ return devm_of_clk_add_hw_provider(&pdev->dev, jh7110_pll_get, priv);
+}
+
+static const struct of_device_id jh7110_pll_match[] = {
+ { .compatible = "starfive,jh7110-pll" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jh7110_pll_match);
+
+static struct platform_driver jh7110_pll_driver = {
+ .driver = {
+ .name = "clk-starfive-jh7110-pll",
+ .of_match_table = jh7110_pll_match,
+ },
+};
+builtin_platform_driver_probe(jh7110_pll_driver, jh7110_pll_probe);
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-stg.c b/drivers/clk/starfive/clk-starfive-jh7110-stg.c
new file mode 100644
index 000000000000..dafcb7190592
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh7110-stg.c
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 System-Top-Group Clock Driver
+ *
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+
+#include "clk-starfive-jh7110.h"
+
+/* external clocks */
+#define JH7110_STGCLK_OSC (JH7110_STGCLK_END + 0)
+#define JH7110_STGCLK_HIFI4_CORE (JH7110_STGCLK_END + 1)
+#define JH7110_STGCLK_STG_AXIAHB (JH7110_STGCLK_END + 2)
+#define JH7110_STGCLK_USB_125M (JH7110_STGCLK_END + 3)
+#define JH7110_STGCLK_CPU_BUS (JH7110_STGCLK_END + 4)
+#define JH7110_STGCLK_HIFI4_AXI (JH7110_STGCLK_END + 5)
+#define JH7110_STGCLK_NOCSTG_BUS (JH7110_STGCLK_END + 6)
+#define JH7110_STGCLK_APB_BUS (JH7110_STGCLK_END + 7)
+#define JH7110_STGCLK_EXT_END (JH7110_STGCLK_END + 8)
+
+static const struct jh71x0_clk_data jh7110_stgclk_data[] = {
+ /* hifi4 */
+ JH71X0_GATE(JH7110_STGCLK_HIFI4_CLK_CORE, "hifi4_clk_core", 0,
+ JH7110_STGCLK_HIFI4_CORE),
+ /* usb */
+ JH71X0_GATE(JH7110_STGCLK_USB0_APB, "usb0_apb", 0, JH7110_STGCLK_APB_BUS),
+ JH71X0_GATE(JH7110_STGCLK_USB0_UTMI_APB, "usb0_utmi_apb", 0, JH7110_STGCLK_APB_BUS),
+ JH71X0_GATE(JH7110_STGCLK_USB0_AXI, "usb0_axi", 0, JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GDIV(JH7110_STGCLK_USB0_LPM, "usb0_lpm", 0, 2, JH7110_STGCLK_OSC),
+ JH71X0_GDIV(JH7110_STGCLK_USB0_STB, "usb0_stb", 0, 4, JH7110_STGCLK_OSC),
+ JH71X0_GATE(JH7110_STGCLK_USB0_APP_125, "usb0_app_125", 0, JH7110_STGCLK_USB_125M),
+ JH71X0__DIV(JH7110_STGCLK_USB0_REFCLK, "usb0_refclk", 2, JH7110_STGCLK_OSC),
+ /* pci-e */
+ JH71X0_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", 0,
+ JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_STGCLK_PCIE0_APB, "pcie0_apb", 0, JH7110_STGCLK_APB_BUS),
+ JH71X0_GATE(JH7110_STGCLK_PCIE0_TL, "pcie0_tl", 0, JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_STGCLK_PCIE1_AXI_MST0, "pcie1_axi_mst0", 0,
+ JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_STGCLK_PCIE1_APB, "pcie1_apb", 0, JH7110_STGCLK_APB_BUS),
+ JH71X0_GATE(JH7110_STGCLK_PCIE1_TL, "pcie1_tl", 0, JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", CLK_IS_CRITICAL,
+ JH7110_STGCLK_STG_AXIAHB),
+ /* security */
+ JH71X0_GATE(JH7110_STGCLK_SEC_AHB, "sec_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_STGCLK_SEC_MISC_AHB, "sec_misc_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
+ /* stg mtrx */
+ JH71X0_GATE(JH7110_STGCLK_GRP0_MAIN, "mtrx_grp0_main", CLK_IS_CRITICAL,
+ JH7110_STGCLK_CPU_BUS),
+ JH71X0_GATE(JH7110_STGCLK_GRP0_BUS, "mtrx_grp0_bus", CLK_IS_CRITICAL,
+ JH7110_STGCLK_NOCSTG_BUS),
+ JH71X0_GATE(JH7110_STGCLK_GRP0_STG, "mtrx_grp0_stg", CLK_IS_CRITICAL,
+ JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_STGCLK_GRP1_MAIN, "mtrx_grp1_main", CLK_IS_CRITICAL,
+ JH7110_STGCLK_CPU_BUS),
+ JH71X0_GATE(JH7110_STGCLK_GRP1_BUS, "mtrx_grp1_bus", CLK_IS_CRITICAL,
+ JH7110_STGCLK_NOCSTG_BUS),
+ JH71X0_GATE(JH7110_STGCLK_GRP1_STG, "mtrx_grp1_stg", CLK_IS_CRITICAL,
+ JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_STGCLK_GRP1_HIFI, "mtrx_grp1_hifi", CLK_IS_CRITICAL,
+ JH7110_STGCLK_HIFI4_AXI),
+ /* e24_rvpi */
+ JH71X0_GDIV(JH7110_STGCLK_E2_RTC, "e2_rtc", 0, 24, JH7110_STGCLK_OSC),
+ JH71X0_GATE(JH7110_STGCLK_E2_CORE, "e2_core", 0, JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_STGCLK_E2_DBG, "e2_dbg", 0, JH7110_STGCLK_STG_AXIAHB),
+ /* dw_sgdma1p */
+ JH71X0_GATE(JH7110_STGCLK_DMA1P_AXI, "dma1p_axi", 0, JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_STGCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
+};
+
+static struct clk_hw *jh7110_stgclk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct jh71x0_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < JH7110_STGCLK_END)
+ return &priv->reg[idx].hw;
+
+ return ERR_PTR(-EINVAL);
+}
+
+static int jh7110_stgcrg_probe(struct platform_device *pdev)
+{
+ struct jh71x0_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7110_STGCLK_END),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ for (idx = 0; idx < JH7110_STGCLK_END; idx++) {
+ u32 max = jh7110_stgclk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh7110_stgclk_data[idx].name,
+ .ops = starfive_jh71x0_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
+ .flags = jh7110_stgclk_data[idx].flags,
+ };
+ struct jh71x0_clk *clk = &priv->reg[idx];
+ const char *fw_name[JH7110_STGCLK_EXT_END - JH7110_STGCLK_END] = {
+ "osc",
+ "hifi4_core",
+ "stg_axiahb",
+ "usb_125m",
+ "cpu_bus",
+ "hifi4_axi",
+ "nocstg_bus",
+ "apb_bus"
+ };
+ unsigned int i;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh7110_stgclk_data[idx].parents[i];
+
+ if (pidx < JH7110_STGCLK_END)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx < JH7110_STGCLK_EXT_END)
+ parents[i].fw_name = fw_name[pidx - JH7110_STGCLK_END];
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & JH71X0_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_stgclk_get, priv);
+ if (ret)
+ return ret;
+
+ return jh7110_reset_controller_register(priv, "rst-stg", 2);
+}
+
+static const struct of_device_id jh7110_stgcrg_match[] = {
+ { .compatible = "starfive,jh7110-stgcrg" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jh7110_stgcrg_match);
+
+static struct platform_driver jh7110_stgcrg_driver = {
+ .probe = jh7110_stgcrg_probe,
+ .driver = {
+ .name = "clk-starfive-jh7110-stg",
+ .of_match_table = jh7110_stgcrg_match,
+ },
+};
+module_platform_driver(jh7110_stgcrg_driver);
+
+MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
+MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
+MODULE_DESCRIPTION("StarFive JH7110 System-Top-Group clock driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index e6031345ef05..3884eff9fe93 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -7,6 +7,7 @@
*/
#include <linux/auxiliary_bus.h>
+#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/init.h>
#include <linux/io.h>
@@ -389,6 +390,7 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
struct jh71x0_clk_priv *priv;
unsigned int idx;
int ret;
+ struct clk *pllclk;
priv = devm_kzalloc(&pdev->dev,
struct_size(priv, reg, JH7110_SYSCLK_END),
@@ -402,28 +404,42 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
- /*
- * These PLL clocks are not actually fixed factor clocks and can be
- * controlled by the syscon registers of JH7110. They will be dropped
- * and registered in the PLL clock driver instead.
- */
- /* 24MHz -> 1000.0MHz */
- priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
- "osc", 0, 125, 3);
- if (IS_ERR(priv->pll[0]))
- return PTR_ERR(priv->pll[0]);
-
- /* 24MHz -> 1066.0MHz */
- priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
- "osc", 0, 533, 12);
- if (IS_ERR(priv->pll[1]))
- return PTR_ERR(priv->pll[1]);
-
- /* 24MHz -> 1188.0MHz */
- priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
- "osc", 0, 99, 2);
- if (IS_ERR(priv->pll[2]))
- return PTR_ERR(priv->pll[2]);
+ /* Use fixed factor clocks if can not get the PLL clocks from DTS */
+ pllclk = clk_get(priv->dev, "pll0_out");
+ if (IS_ERR(pllclk)) {
+ /* 24MHz -> 1000.0MHz */
+ priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
+ "osc", 0, 125, 3);
+ if (IS_ERR(priv->pll[0]))
+ return PTR_ERR(priv->pll[0]);
+ } else {
+ clk_put(pllclk);
+ priv->pll[0] = NULL;
+ }
+
+ pllclk = clk_get(priv->dev, "pll1_out");
+ if (IS_ERR(pllclk)) {
+ /* 24MHz -> 1066.0MHz */
+ priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
+ "osc", 0, 533, 12);
+ if (IS_ERR(priv->pll[1]))
+ return PTR_ERR(priv->pll[1]);
+ } else {
+ clk_put(pllclk);
+ priv->pll[1] = NULL;
+ }
+
+ pllclk = clk_get(priv->dev, "pll2_out");
+ if (IS_ERR(pllclk)) {
+ /* 24MHz -> 1188.0MHz */
+ priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
+ "osc", 0, 99, 2);
+ if (IS_ERR(priv->pll[2]))
+ return PTR_ERR(priv->pll[2]);
+ } else {
+ clk_put(pllclk);
+ priv->pll[2] = NULL;
+ }
for (idx = 0; idx < JH7110_SYSCLK_END; idx++) {
u32 max = jh7110_sysclk_data[idx].max;
@@ -462,6 +478,12 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
parents[i].fw_name = "tdm_ext";
else if (pidx == JH7110_SYSCLK_MCLK_EXT)
parents[i].fw_name = "mclk_ext";
+ else if (pidx == JH7110_SYSCLK_PLL0_OUT && !priv->pll[0])
+ parents[i].fw_name = "pll0_out";
+ else if (pidx == JH7110_SYSCLK_PLL1_OUT && !priv->pll[1])
+ parents[i].fw_name = "pll1_out";
+ else if (pidx == JH7110_SYSCLK_PLL2_OUT && !priv->pll[2])
+ parents[i].fw_name = "pll2_out";
else
parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT];
}
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
new file mode 100644
index 000000000000..10cc1ec43925
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 Video-Output Clock Driver
+ *
+ * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+
+#include "clk-starfive-jh7110.h"
+
+/* external clocks */
+#define JH7110_VOUTCLK_VOUT_SRC (JH7110_VOUTCLK_END + 0)
+#define JH7110_VOUTCLK_VOUT_TOP_AHB (JH7110_VOUTCLK_END + 1)
+#define JH7110_VOUTCLK_VOUT_TOP_AXI (JH7110_VOUTCLK_END + 2)
+#define JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK (JH7110_VOUTCLK_END + 3)
+#define JH7110_VOUTCLK_I2STX0_BCLK (JH7110_VOUTCLK_END + 4)
+#define JH7110_VOUTCLK_HDMITX0_PIXELCLK (JH7110_VOUTCLK_END + 5)
+#define JH7110_VOUTCLK_EXT_END (JH7110_VOUTCLK_END + 6)
+
+static struct clk_bulk_data jh7110_vout_top_clks[] = {
+ { .id = "vout_src" },
+ { .id = "vout_top_ahb" }
+};
+
+static const struct jh71x0_clk_data jh7110_voutclk_data[] = {
+ /* divider */
+ JH71X0__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB),
+ JH71X0__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC),
+ JH71X0__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC),
+ JH71X0__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB),
+ /* dc8200 */
+ JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
+ JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
+ JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB),
+ JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2,
+ JH7110_VOUTCLK_DC8200_PIX,
+ JH7110_VOUTCLK_HDMITX0_PIXELCLK),
+ JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2,
+ JH7110_VOUTCLK_DC8200_PIX,
+ JH7110_VOUTCLK_HDMITX0_PIXELCLK),
+ /* LCD */
+ JH71X0_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2,
+ JH7110_VOUTCLK_DC8200_PIX0,
+ JH7110_VOUTCLK_DC8200_PIX1),
+ /* dsiTx */
+ JH71X0_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS),
+ JH71X0_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS),
+ JH71X0_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2,
+ JH7110_VOUTCLK_DC8200_PIX,
+ JH7110_VOUTCLK_HDMITX0_PIXELCLK),
+ JH71X0_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC),
+ /* mipitx DPHY */
+ JH71X0_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0,
+ JH7110_VOUTCLK_TX_ESC),
+ /* hdmi */
+ JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0,
+ JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK),
+ JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0,
+ JH7110_VOUTCLK_I2STX0_BCLK),
+ JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB),
+};
+
+static int jh7110_vout_top_rst_init(struct jh71x0_clk_priv *priv)
+{
+ struct reset_control *top_rst;
+
+ /* The reset should be shared and other Vout modules will use its. */
+ top_rst = devm_reset_control_get_shared(priv->dev, NULL);
+ if (IS_ERR(top_rst))
+ return dev_err_probe(priv->dev, PTR_ERR(top_rst), "failed to get top reset\n");
+
+ return reset_control_deassert(top_rst);
+}
+
+static struct clk_hw *jh7110_voutclk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct jh71x0_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < JH7110_VOUTCLK_END)
+ return &priv->reg[idx].hw;
+
+ return ERR_PTR(-EINVAL);
+}
+
+#ifdef CONFIG_PM
+static int jh7110_voutcrg_suspend(struct device *dev)
+{
+ struct jh7110_top_sysclk *top = dev_get_drvdata(dev);
+
+ clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);
+
+ return 0;
+}
+
+static int jh7110_voutcrg_resume(struct device *dev)
+{
+ struct jh7110_top_sysclk *top = dev_get_drvdata(dev);
+
+ return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks);
+}
+
+static const struct dev_pm_ops jh7110_voutcrg_pm_ops = {
+ RUNTIME_PM_OPS(jh7110_voutcrg_suspend, jh7110_voutcrg_resume, NULL)
+};
+#endif
+
+static int jh7110_voutcrg_probe(struct platform_device *pdev)
+{
+ struct jh71x0_clk_priv *priv;
+ struct jh7110_top_sysclk *top;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JH7110_VOUTCLK_END),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL);
+ if (!top)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ top->top_clks = jh7110_vout_top_clks;
+ top->top_clks_num = ARRAY_SIZE(jh7110_vout_top_clks);
+ ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks);
+ if (ret)
+ return dev_err_probe(priv->dev, ret, "failed to get top clocks\n");
+ dev_set_drvdata(priv->dev, top);
+
+ /* enable power domain and clocks */
+ pm_runtime_enable(priv->dev);
+ ret = pm_runtime_get_sync(priv->dev);
+ if (ret < 0)
+ return dev_err_probe(priv->dev, ret, "failed to turn on power\n");
+
+ ret = jh7110_vout_top_rst_init(priv);
+ if (ret)
+ goto err_exit;
+
+ for (idx = 0; idx < JH7110_VOUTCLK_END; idx++) {
+ u32 max = jh7110_voutclk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh7110_voutclk_data[idx].name,
+ .ops = starfive_jh71x0_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
+ .flags = jh7110_voutclk_data[idx].flags,
+ };
+ struct jh71x0_clk *clk = &priv->reg[idx];
+ unsigned int i;
+ const char *fw_name[JH7110_VOUTCLK_EXT_END - JH7110_VOUTCLK_END] = {
+ "vout_src",
+ "vout_top_ahb",
+ "vout_top_axi",
+ "vout_top_hdmitx0_mclk",
+ "i2stx0_bclk",
+ "hdmitx0_pixelclk"
+ };
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh7110_voutclk_data[idx].parents[i];
+
+ if (pidx < JH7110_VOUTCLK_END)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx < JH7110_VOUTCLK_EXT_END)
+ parents[i].fw_name = fw_name[pidx - JH7110_VOUTCLK_END];
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & JH71X0_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ goto err_exit;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_voutclk_get, priv);
+ if (ret)
+ goto err_exit;
+
+ ret = jh7110_reset_controller_register(priv, "rst-vo", 4);
+ if (ret)
+ goto err_exit;
+
+ return 0;
+
+err_exit:
+ pm_runtime_put_sync(priv->dev);
+ pm_runtime_disable(priv->dev);
+ return ret;
+}
+
+static int jh7110_voutcrg_remove(struct platform_device *pdev)
+{
+ pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+static const struct of_device_id jh7110_voutcrg_match[] = {
+ { .compatible = "starfive,jh7110-voutcrg" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jh7110_voutcrg_match);
+
+static struct platform_driver jh7110_voutcrg_driver = {
+ .probe = jh7110_voutcrg_probe,
+ .remove = jh7110_voutcrg_remove,
+ .driver = {
+ .name = "clk-starfive-jh7110-vout",
+ .of_match_table = jh7110_voutcrg_match,
+ .pm = pm_ptr(&jh7110_voutcrg_pm_ops),
+ },
+};
+module_platform_driver(jh7110_voutcrg_driver);
+
+MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JH7110 Video-Output clock driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/starfive/clk-starfive-jh7110.h b/drivers/clk/starfive/clk-starfive-jh7110.h
index f29682b8d400..0659adae4d76 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110.h
+++ b/drivers/clk/starfive/clk-starfive-jh7110.h
@@ -4,6 +4,12 @@
#include "clk-starfive-jh71x0.h"
+/* top clocks of ISP/VOUT domain from JH7110 SYSCRG */
+struct jh7110_top_sysclk {
+ struct clk_bulk_data *top_clks;
+ int top_clks_num;
+};
+
int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
const char *adev_name,
u32 adev_id);
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-jh71x0.c
index b372083d11c3..aebc99264a0b 100644
--- a/drivers/clk/starfive/clk-starfive-jh71x0.c
+++ b/drivers/clk/starfive/clk-starfive-jh71x0.c
@@ -174,12 +174,6 @@ static int jh71x0_clk_set_parent(struct clk_hw *hw, u8 index)
return 0;
}
-static int jh71x0_clk_mux_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- return clk_mux_determine_rate_flags(hw, req, 0);
-}
-
static int jh71x0_clk_get_phase(struct clk_hw *hw)
{
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
@@ -261,7 +255,7 @@ static const struct clk_ops jh71x0_clk_gdiv_ops = {
};
static const struct clk_ops jh71x0_clk_mux_ops = {
- .determine_rate = jh71x0_clk_mux_determine_rate,
+ .determine_rate = __clk_mux_determine_rate,
.set_parent = jh71x0_clk_set_parent,
.get_parent = jh71x0_clk_get_parent,
.debug_init = jh71x0_clk_debug_init,
@@ -271,7 +265,7 @@ static const struct clk_ops jh71x0_clk_gmux_ops = {
.enable = jh71x0_clk_enable,
.disable = jh71x0_clk_disable,
.is_enabled = jh71x0_clk_is_enabled,
- .determine_rate = jh71x0_clk_mux_determine_rate,
+ .determine_rate = __clk_mux_determine_rate,
.set_parent = jh71x0_clk_set_parent,
.get_parent = jh71x0_clk_get_parent,
.debug_init = jh71x0_clk_debug_init,
diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
index c19828f1aa0f..451ebb7c99a3 100644
--- a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
+++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
@@ -8,7 +8,7 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index eb36f8f77d55..8951ffc14ff5 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -68,7 +68,7 @@ static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST(pll_video0_clk, "pll-video0",
"osc24M", 0x010,
192000000, /* Minimum rate */
1008000000, /* Maximum rate */
@@ -179,7 +179,9 @@ static struct ccu_nkm pll_mipi_clk = {
.common = {
.reg = 0x040,
.hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
- &ccu_nkm_ops, CLK_SET_RATE_UNGATE),
+ &ccu_nkm_ops,
+ CLK_SET_RATE_UNGATE | CLK_SET_RATE_PARENT),
+ .features = CCU_FEATURE_CLOSEST_RATE,
},
};
@@ -536,25 +538,18 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
static const u8 tcon0_table[] = { 0, 2, };
-static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
- tcon0_table, 0x118, 24, 3, BIT(31),
- CLK_SET_RATE_PARENT |
- CLK_SET_RATE_NO_REPARENT);
+static SUNXI_CCU_MUX_TABLE_WITH_GATE_CLOSEST(tcon0_clk, "tcon0", tcon0_parents,
+ tcon0_table, 0x118, 24, 3, BIT(31),
+ CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
static const u8 tcon1_table[] = { 0, 2, };
-static struct ccu_div tcon1_clk = {
- .enable = BIT(31),
- .div = _SUNXI_CCU_DIV(0, 4),
- .mux = _SUNXI_CCU_MUX_TABLE(24, 2, tcon1_table),
- .common = {
- .reg = 0x11c,
- .hw.init = CLK_HW_INIT_PARENTS("tcon1",
- tcon1_parents,
- &ccu_div_ops,
- CLK_SET_RATE_PARENT),
- },
-};
+static SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(tcon1_clk, "tcon1", tcon1_parents,
+ tcon1_table, 0x11c,
+ 0, 4, /* M */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ CLK_SET_RATE_PARENT);
static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
@@ -584,8 +579,8 @@ static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
0x144, BIT(31), 0);
static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
-static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
- 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M_WITH_MUX_GATE_CLOSEST(hdmi_clk, "hdmi", hdmi_parents,
+ 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
0x154, BIT(31), 0);
@@ -597,9 +592,9 @@ static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
static const u8 dsi_dphy_table[] = { 0, 2, };
-static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
- dsi_dphy_parents, dsi_dphy_table,
- 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(dsi_dphy_clk, "dsi-dphy",
+ dsi_dphy_parents, dsi_dphy_table,
+ 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index 001582ea71ba..02b28cfc5525 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -5,7 +5,7 @@
#include <linux/clk-provider.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
index d65398497d5f..fdc8ccc586c9 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
@@ -5,8 +5,10 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
+#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
+#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/clk/sunxi-ng.h>
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index b70b312e7483..6a043a0a9dd6 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -6,7 +6,7 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index bfebe8dbbe65..74274c17efb3 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -6,7 +6,7 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
index 4221649b311f..4890a976b1a0 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
@@ -5,7 +5,7 @@
#include <linux/clk-provider.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index fbb3529f0d3e..f3ce8664b288 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -9,7 +9,7 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-ng/ccu_common.c
index 8d28a7a079d0..8babce55302f 100644
--- a/drivers/clk/sunxi-ng/ccu_common.c
+++ b/drivers/clk/sunxi-ng/ccu_common.c
@@ -39,6 +39,18 @@ void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock)
}
EXPORT_SYMBOL_NS_GPL(ccu_helper_wait_for_lock, SUNXI_CCU);
+bool ccu_is_better_rate(struct ccu_common *common,
+ unsigned long target_rate,
+ unsigned long current_rate,
+ unsigned long best_rate)
+{
+ if (common->features & CCU_FEATURE_CLOSEST_RATE)
+ return abs(current_rate - target_rate) < abs(best_rate - target_rate);
+
+ return current_rate <= target_rate && current_rate > best_rate;
+}
+EXPORT_SYMBOL_NS_GPL(ccu_is_better_rate, SUNXI_CCU);
+
/*
* This clock notifier is called when the frequency of a PLL clock is
* changed. In common PLL designs, changes to the dividers take effect
diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h
index fbf16c6b896d..942a72c09437 100644
--- a/drivers/clk/sunxi-ng/ccu_common.h
+++ b/drivers/clk/sunxi-ng/ccu_common.h
@@ -18,6 +18,7 @@
#define CCU_FEATURE_MMC_TIMING_SWITCH BIT(6)
#define CCU_FEATURE_SIGMA_DELTA_MOD BIT(7)
#define CCU_FEATURE_KEY_FIELD BIT(8)
+#define CCU_FEATURE_CLOSEST_RATE BIT(9)
/* MMC timing mode switch bit */
#define CCU_MMC_NEW_TIMING_MODE BIT(30)
@@ -52,6 +53,11 @@ struct sunxi_ccu_desc {
void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock);
+bool ccu_is_better_rate(struct ccu_common *common,
+ unsigned long target_rate,
+ unsigned long current_rate,
+ unsigned long best_rate);
+
struct ccu_pll_nb {
struct notifier_block clk_nb;
struct ccu_common *common;
diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h
index 948e2b0c0c3b..90d49ee8e0cc 100644
--- a/drivers/clk/sunxi-ng/ccu_div.h
+++ b/drivers/clk/sunxi-ng/ccu_div.h
@@ -143,6 +143,26 @@ struct ccu_div {
}, \
}
+#define SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(_struct, _name, \
+ _parents, _table, \
+ _reg, \
+ _mshift, _mwidth, \
+ _muxshift, _muxwidth, \
+ _gate, _flags) \
+ struct ccu_div _struct = { \
+ .enable = _gate, \
+ .div = _SUNXI_CCU_DIV_FLAGS(_mshift, _mwidth, CLK_DIVIDER_ROUND_CLOSEST), \
+ .mux = _SUNXI_CCU_MUX_TABLE(_muxshift, _muxwidth, _table), \
+ .common = { \
+ .reg = _reg, \
+ .hw.init = CLK_HW_INIT_PARENTS(_name, \
+ _parents, \
+ &ccu_div_ops, \
+ _flags), \
+ .features = CCU_FEATURE_CLOSEST_RATE, \
+ }, \
+ }
+
#define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
_mshift, _mwidth, _muxshift, _muxwidth, \
_gate, _flags) \
@@ -152,6 +172,16 @@ struct ccu_div {
_muxshift, _muxwidth, \
_gate, _flags)
+#define SUNXI_CCU_M_WITH_MUX_GATE_CLOSEST(_struct, _name, _parents, \
+ _reg, _mshift, _mwidth, \
+ _muxshift, _muxwidth, \
+ _gate, _flags) \
+ SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(_struct, _name, \
+ _parents, NULL, \
+ _reg, _mshift, _mwidth, \
+ _muxshift, _muxwidth, \
+ _gate, _flags)
+
#define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \
_mshift, _mwidth, _muxshift, _muxwidth, \
_flags) \
diff --git a/drivers/clk/sunxi-ng/ccu_mmc_timing.c b/drivers/clk/sunxi-ng/ccu_mmc_timing.c
index 23a8d44e2449..78919d7843be 100644
--- a/drivers/clk/sunxi-ng/ccu_mmc_timing.c
+++ b/drivers/clk/sunxi-ng/ccu_mmc_timing.c
@@ -43,7 +43,7 @@ int sunxi_ccu_set_mmc_timing_mode(struct clk *clk, bool new_mode)
EXPORT_SYMBOL_GPL(sunxi_ccu_set_mmc_timing_mode);
/**
- * sunxi_ccu_set_mmc_timing_mode: Get the current MMC clock timing mode
+ * sunxi_ccu_get_mmc_timing_mode: Get the current MMC clock timing mode
* @clk: clock to query
*
* Return: %0 if the clock is in old timing mode, > %0 if it is in
diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index 1d557e323169..5edc63b46651 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -139,7 +139,7 @@ int ccu_mux_helper_determine_rate(struct ccu_common *common,
goto out;
}
- if ((req->rate - tmp_rate) < (req->rate - best_rate)) {
+ if (ccu_is_better_rate(common, req->rate, tmp_rate, best_rate)) {
best_rate = tmp_rate;
best_parent_rate = parent_rate;
best_parent = parent;
@@ -242,6 +242,17 @@ static int ccu_mux_set_parent(struct clk_hw *hw, u8 index)
return ccu_mux_helper_set_parent(&cm->common, &cm->mux, index);
}
+static int ccu_mux_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ struct ccu_mux *cm = hw_to_ccu_mux(hw);
+
+ if (cm->common.features & CCU_FEATURE_CLOSEST_RATE)
+ return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST);
+
+ return clk_mux_determine_rate_flags(hw, req, 0);
+}
+
static unsigned long ccu_mux_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@@ -259,7 +270,7 @@ const struct clk_ops ccu_mux_ops = {
.get_parent = ccu_mux_get_parent,
.set_parent = ccu_mux_set_parent,
- .determine_rate = __clk_mux_determine_rate,
+ .determine_rate = ccu_mux_determine_rate,
.recalc_rate = ccu_mux_recalc_rate,
};
EXPORT_SYMBOL_NS_GPL(ccu_mux_ops, SUNXI_CCU);
diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h
index 2c1811a445b0..eb1172ebbd94 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.h
+++ b/drivers/clk/sunxi-ng/ccu_mux.h
@@ -46,20 +46,36 @@ struct ccu_mux {
struct ccu_common common;
};
+#define SUNXI_CCU_MUX_TABLE_WITH_GATE_FEAT(_struct, _name, _parents, _table, \
+ _reg, _shift, _width, _gate, \
+ _flags, _features) \
+ struct ccu_mux _struct = { \
+ .enable = _gate, \
+ .mux = _SUNXI_CCU_MUX_TABLE(_shift, _width, _table), \
+ .common = { \
+ .reg = _reg, \
+ .hw.init = CLK_HW_INIT_PARENTS(_name, \
+ _parents, \
+ &ccu_mux_ops, \
+ _flags), \
+ .features = _features, \
+ } \
+ }
+
+#define SUNXI_CCU_MUX_TABLE_WITH_GATE_CLOSEST(_struct, _name, _parents, \
+ _table, _reg, _shift, \
+ _width, _gate, _flags) \
+ SUNXI_CCU_MUX_TABLE_WITH_GATE_FEAT(_struct, _name, _parents, \
+ _table, _reg, _shift, \
+ _width, _gate, _flags, \
+ CCU_FEATURE_CLOSEST_RATE)
+
#define SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, _table, \
_reg, _shift, _width, _gate, \
_flags) \
- struct ccu_mux _struct = { \
- .enable = _gate, \
- .mux = _SUNXI_CCU_MUX_TABLE(_shift, _width, _table), \
- .common = { \
- .reg = _reg, \
- .hw.init = CLK_HW_INIT_PARENTS(_name, \
- _parents, \
- &ccu_mux_ops, \
- _flags), \
- } \
- }
+ SUNXI_CCU_MUX_TABLE_WITH_GATE_FEAT(_struct, _name, _parents, \
+ _table, _reg, _shift, \
+ _width, _gate, _flags, 0)
#define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \
_shift, _width, _gate, _flags) \
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
index a0978a50edae..eed64547ad42 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.c
+++ b/drivers/clk/sunxi-ng/ccu_nkm.c
@@ -16,8 +16,47 @@ struct _ccu_nkm {
unsigned long m, min_m, max_m;
};
+static unsigned long ccu_nkm_find_best_with_parent_adj(struct ccu_common *common,
+ struct clk_hw *parent_hw,
+ unsigned long *parent, unsigned long rate,
+ struct _ccu_nkm *nkm)
+{
+ unsigned long best_rate = 0, best_parent_rate = *parent, tmp_parent = *parent;
+ unsigned long best_n = 0, best_k = 0, best_m = 0;
+ unsigned long _n, _k, _m;
+
+ for (_k = nkm->min_k; _k <= nkm->max_k; _k++) {
+ for (_n = nkm->min_n; _n <= nkm->max_n; _n++) {
+ for (_m = nkm->min_m; _m <= nkm->max_m; _m++) {
+ unsigned long tmp_rate;
+
+ tmp_parent = clk_hw_round_rate(parent_hw, rate * _m / (_n * _k));
+
+ tmp_rate = tmp_parent * _n * _k / _m;
+
+ if (ccu_is_better_rate(common, rate, tmp_rate, best_rate) ||
+ (tmp_parent == *parent && tmp_rate == best_rate)) {
+ best_rate = tmp_rate;
+ best_parent_rate = tmp_parent;
+ best_n = _n;
+ best_k = _k;
+ best_m = _m;
+ }
+ }
+ }
+ }
+
+ nkm->n = best_n;
+ nkm->k = best_k;
+ nkm->m = best_m;
+
+ *parent = best_parent_rate;
+
+ return best_rate;
+}
+
static unsigned long ccu_nkm_find_best(unsigned long parent, unsigned long rate,
- struct _ccu_nkm *nkm)
+ struct _ccu_nkm *nkm, struct ccu_common *common)
{
unsigned long best_rate = 0;
unsigned long best_n = 0, best_k = 0, best_m = 0;
@@ -30,9 +69,7 @@ static unsigned long ccu_nkm_find_best(unsigned long parent, unsigned long rate,
tmp_rate = parent * _n * _k / _m;
- if (tmp_rate > rate)
- continue;
- if ((rate - tmp_rate) < (rate - best_rate)) {
+ if (ccu_is_better_rate(common, rate, tmp_rate, best_rate)) {
best_rate = tmp_rate;
best_n = _n;
best_k = _k;
@@ -106,7 +143,7 @@ static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw,
}
static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
- struct clk_hw *hw,
+ struct clk_hw *parent_hw,
unsigned long *parent_rate,
unsigned long rate,
void *data)
@@ -124,7 +161,11 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate *= nkm->fixed_post_div;
- rate = ccu_nkm_find_best(*parent_rate, rate, &_nkm);
+ if (!clk_hw_can_set_rate_parent(&nkm->common.hw))
+ rate = ccu_nkm_find_best(*parent_rate, rate, &_nkm, &nkm->common);
+ else
+ rate = ccu_nkm_find_best_with_parent_adj(&nkm->common, parent_hw, parent_rate, rate,
+ &_nkm);
if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nkm->fixed_post_div;
@@ -159,7 +200,7 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate,
_nkm.min_m = 1;
_nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
- ccu_nkm_find_best(parent_rate, rate, &_nkm);
+ ccu_nkm_find_best(parent_rate, rate, &_nkm, &nkm->common);
spin_lock_irqsave(nkm->common.lock, flags);
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
index c1fd11542c45..ffac3deb89d6 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.c
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
@@ -27,8 +27,8 @@ static unsigned long ccu_nm_calc_rate(unsigned long parent,
return rate;
}
-static unsigned long ccu_nm_find_best(unsigned long parent, unsigned long rate,
- struct _ccu_nm *nm)
+static unsigned long ccu_nm_find_best(struct ccu_common *common, unsigned long parent,
+ unsigned long rate, struct _ccu_nm *nm)
{
unsigned long best_rate = 0;
unsigned long best_n = 0, best_m = 0;
@@ -39,10 +39,7 @@ static unsigned long ccu_nm_find_best(unsigned long parent, unsigned long rate,
unsigned long tmp_rate = ccu_nm_calc_rate(parent,
_n, _m);
- if (tmp_rate > rate)
- continue;
-
- if ((rate - tmp_rate) < (rate - best_rate)) {
+ if (ccu_is_better_rate(common, rate, tmp_rate, best_rate)) {
best_rate = tmp_rate;
best_n = _n;
best_m = _m;
@@ -159,7 +156,7 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
_nm.min_m = 1;
_nm.max_m = nm->m.max ?: 1 << nm->m.width;
- rate = ccu_nm_find_best(*parent_rate, rate, &_nm);
+ rate = ccu_nm_find_best(&nm->common, *parent_rate, rate, &_nm);
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nm->fixed_post_div;
@@ -210,7 +207,7 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
&_nm.m, &_nm.n);
} else {
ccu_sdm_helper_disable(&nm->common, &nm->sdm);
- ccu_nm_find_best(parent_rate, rate, &_nm);
+ ccu_nm_find_best(&nm->common, parent_rate, rate, &_nm);
}
spin_lock_irqsave(nm->common.lock, flags);
diff --git a/drivers/clk/sunxi-ng/ccu_nm.h b/drivers/clk/sunxi-ng/ccu_nm.h
index 2904e67f05a8..93c11693574f 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.h
+++ b/drivers/clk/sunxi-ng/ccu_nm.h
@@ -108,7 +108,7 @@ struct ccu_nm {
}, \
}
-#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(_struct, _name, \
+#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_FEAT(_struct, _name, \
_parent, _reg, \
_min_rate, _max_rate, \
_nshift, _nwidth, \
@@ -116,7 +116,8 @@ struct ccu_nm {
_frac_en, _frac_sel, \
_frac_rate_0, \
_frac_rate_1, \
- _gate, _lock, _flags) \
+ _gate, _lock, _flags, \
+ _features) \
struct ccu_nm _struct = { \
.enable = _gate, \
.lock = _lock, \
@@ -129,7 +130,7 @@ struct ccu_nm {
.max_rate = _max_rate, \
.common = { \
.reg = _reg, \
- .features = CCU_FEATURE_FRACTIONAL, \
+ .features = _features, \
.hw.init = CLK_HW_INIT(_name, \
_parent, \
&ccu_nm_ops, \
@@ -137,6 +138,47 @@ struct ccu_nm {
}, \
}
+#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(_struct, _name, \
+ _parent, _reg, \
+ _min_rate, _max_rate, \
+ _nshift, _nwidth, \
+ _mshift, _mwidth, \
+ _frac_en, _frac_sel, \
+ _frac_rate_0, \
+ _frac_rate_1, \
+ _gate, _lock, _flags) \
+ SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_FEAT(_struct, _name, \
+ _parent, _reg, \
+ _min_rate, _max_rate, \
+ _nshift, _nwidth, \
+ _mshift, _mwidth, \
+ _frac_en, _frac_sel, \
+ _frac_rate_0, \
+ _frac_rate_1, \
+ _gate, _lock, _flags, \
+ CCU_FEATURE_FRACTIONAL)
+
+#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST(_struct, _name, \
+ _parent, _reg, \
+ _min_rate, _max_rate, \
+ _nshift, _nwidth, \
+ _mshift, _mwidth, \
+ _frac_en, _frac_sel, \
+ _frac_rate_0, \
+ _frac_rate_1, \
+ _gate, _lock, _flags) \
+ SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_FEAT(_struct, _name, \
+ _parent, _reg, \
+ _min_rate, _max_rate, \
+ _nshift, _nwidth, \
+ _mshift, _mwidth, \
+ _frac_en, _frac_sel, \
+ _frac_rate_0, \
+ _frac_rate_1, \
+ _gate, _lock, _flags, \
+ CCU_FEATURE_FRACTIONAL |\
+ CCU_FEATURE_CLOSEST_RATE)
+
#define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \
_nshift, _nwidth, \
_mshift, _mwidth, \
diff --git a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
index e4cf1180b088..b0a93b4fb051 100644
--- a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
+++ b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
@@ -10,7 +10,6 @@
#include <linux/clk-provider.h>
#include <linux/init.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#define SUN6I_APB0_GATES_MAX_SIZE 32
diff --git a/drivers/clk/sunxi/clk-sun9i-mmc.c b/drivers/clk/sunxi/clk-sun9i-mmc.c
index 636bcf2439ef..91074017c04f 100644
--- a/drivers/clk/sunxi/clk-sun9i-mmc.c
+++ b/drivers/clk/sunxi/clk-sun9i-mmc.c
@@ -11,7 +11,6 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/reset.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
@@ -108,15 +107,13 @@ static int sun9i_a80_mmc_config_clk_probe(struct platform_device *pdev)
spin_lock_init(&data->lock);
- r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!r)
- return -EINVAL;
- /* one clock/reset pair per word */
- count = DIV_ROUND_UP((resource_size(r)), SUN9I_MMC_WIDTH);
- data->membase = devm_ioremap_resource(&pdev->dev, r);
+ data->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
if (IS_ERR(data->membase))
return PTR_ERR(data->membase);
+ /* one clock/reset pair per word */
+ count = DIV_ROUND_UP((resource_size(r)), SUN9I_MMC_WIDTH);
+
clk_data = &data->clk_data;
clk_data->clk_num = count;
clk_data->clks = devm_kcalloc(&pdev->dev, count, sizeof(struct clk *),
diff --git a/drivers/clk/tegra/clk-device.c b/drivers/clk/tegra/clk-device.c
index c58beaf8afbc..8c8e2b853a99 100644
--- a/drivers/clk/tegra/clk-device.c
+++ b/drivers/clk/tegra/clk-device.c
@@ -2,8 +2,8 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
#include <linux/mutex.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_opp.h>
diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
index 2a164e565c86..a9be4b56b2b7 100644
--- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
+++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
@@ -12,7 +12,7 @@
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/init.h>
-#include <linux/of_device.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <soc/tegra/fuse.h>
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index dcacc5064d33..2c58ce25af75 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -9,7 +9,6 @@
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/clk/tegra.h>
#include <linux/delay.h>
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 60f1534711f1..82a8cb9545eb 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -10,7 +10,6 @@
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/clk/tegra.h>
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index 26bda45813c0..19037346f522 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -9,12 +9,12 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of.h>
-#include <linux/of_device.h>
+#include <linux/of_platform.h>
#include <linux/clk/tegra.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset-controller.h>
-#include <linux/string.h>
+#include <linux/string_helpers.h>
#include <soc/tegra/fuse.h>
@@ -384,12 +384,10 @@ static struct device_node *tegra_clk_get_of_node(struct clk_hw *hw)
struct device_node *np;
char *node_name;
- node_name = kstrdup(hw->init->name, GFP_KERNEL);
+ node_name = kstrdup_and_replace(hw->init->name, '_', '-', GFP_KERNEL);
if (!node_name)
return NULL;
- strreplace(node_name, '_', '-');
-
for_each_child_of_node(tegra_car_np, np) {
if (!strcmp(np->name, node_name))
break;
diff --git a/drivers/clk/ti/adpll.c b/drivers/clk/ti/adpll.c
index 6ecbba4342c5..ff42ea75cb43 100644
--- a/drivers/clk/ti/adpll.c
+++ b/drivers/clk/ti/adpll.c
@@ -881,14 +881,10 @@ static int ti_adpll_probe(struct platform_device *pdev)
dev_set_drvdata(d->dev, d);
spin_lock_init(&d->lock);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res)
- return -ENODEV;
- d->pa = res->start;
-
- d->iobase = devm_ioremap_resource(dev, res);
+ d->iobase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(d->iobase))
return PTR_ERR(d->iobase);
+ d->pa = res->start;
err = ti_adpll_init_registers(d);
if (err)
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index 3d636938a739..1862958ab412 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -16,6 +16,7 @@
#include <linux/of_address.h>
#include <linux/list.h>
#include <linux/regmap.h>
+#include <linux/string_helpers.h>
#include <linux/memblock.h>
#include <linux/device.h>
@@ -123,10 +124,9 @@ static struct device_node *ti_find_clock_provider(struct device_node *from,
const char *n;
char *tmp;
- tmp = kstrdup(name, GFP_KERNEL);
+ tmp = kstrdup_and_replace(name, '-', '_', GFP_KERNEL);
if (!tmp)
return NULL;
- strreplace(tmp, '-', '_');
/* Node named "clock" with "clock-output-names" */
for_each_of_allnodes_from(from, np) {
diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c
index 8c40f10280b7..607e34d8e289 100644
--- a/drivers/clk/ti/clkctrl.c
+++ b/drivers/clk/ti/clkctrl.c
@@ -13,6 +13,7 @@
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include <linux/delay.h>
+#include <linux/string_helpers.h>
#include <linux/timekeeping.h>
#include "clock.h"
@@ -473,11 +474,11 @@ static const char * __init clkctrl_get_name(struct device_node *np)
const int prefix_len = 11;
const char *compat;
const char *output;
+ const char *end;
char *name;
if (!of_property_read_string_index(np, "clock-output-names", 0,
&output)) {
- const char *end;
int len;
len = strlen(output);
@@ -491,13 +492,13 @@ static const char * __init clkctrl_get_name(struct device_node *np)
of_property_for_each_string(np, "compatible", prop, compat) {
if (!strncmp("ti,clkctrl-", compat, prefix_len)) {
+ end = compat + prefix_len;
/* Two letter minimum name length for l3, l4 etc */
- if (strnlen(compat + prefix_len, 16) < 2)
+ if (strnlen(end, 16) < 2)
continue;
- name = kasprintf(GFP_KERNEL, "%s", compat + prefix_len);
+ name = kstrdup_and_replace(end, '-', '_', GFP_KERNEL);
if (!name)
continue;
- strreplace(name, '-', '_');
return name;
}
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index a61213311d6c..37b495e68107 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -8,7 +8,6 @@
#include <linux/init.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-uniphier.h"
diff --git a/drivers/clk/xilinx/xlnx_vcu.c b/drivers/clk/xilinx/xlnx_vcu.c
index 0786f15ebbe8..60a3ed7c7263 100644
--- a/drivers/clk/xilinx/xlnx_vcu.c
+++ b/drivers/clk/xilinx/xlnx_vcu.c
@@ -15,7 +15,7 @@
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/xlnx-vcu.h>
#include <linux/module.h>
-#include <linux/of_platform.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
index 5636ff1ce552..a91d98e238c2 100644
--- a/drivers/clk/zynqmp/clkc.c
+++ b/drivers/clk/zynqmp/clkc.c
@@ -11,7 +11,8 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
-#include <linux/of_platform.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/string.h>