diff options
Diffstat (limited to 'drivers/clk/qcom/gcc-sm7150.c')
| -rw-r--r-- | drivers/clk/qcom/gcc-sm7150.c | 394 |
1 files changed, 197 insertions, 197 deletions
diff --git a/drivers/clk/qcom/gcc-sm7150.c b/drivers/clk/qcom/gcc-sm7150.c index 44b49f7cd178..7eabaf0e1b57 100644 --- a/drivers/clk/qcom/gcc-sm7150.c +++ b/drivers/clk/qcom/gcc-sm7150.c @@ -44,9 +44,9 @@ static struct clk_alpha_pll gpll0 = { .clkr = { .enable_reg = 0x52000, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gpll0", - .parent_data = &(const struct clk_parent_data){ + .parent_data = &(const struct clk_parent_data) { .index = DT_BI_TCXO, }, .num_parents = 1, @@ -70,9 +70,9 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = { .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), .width = 4, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gpll0_out_even", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gpll0.clkr.hw, }, .num_parents = 1, @@ -83,9 +83,9 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = { static struct clk_fixed_factor gcc_pll0_main_div_cdiv = { .mult = 1, .div = 2, - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pll0_main_div_cdiv", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gpll0.clkr.hw, }, .num_parents = 1, @@ -99,9 +99,9 @@ static struct clk_alpha_pll gpll6 = { .clkr = { .enable_reg = 0x52000, .enable_mask = BIT(6), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gpll6", - .parent_data = &(const struct clk_parent_data){ + .parent_data = &(const struct clk_parent_data) { .index = DT_BI_TCXO, }, .num_parents = 1, @@ -116,9 +116,9 @@ static struct clk_alpha_pll gpll7 = { .clkr = { .enable_reg = 0x52000, .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gpll7", - .parent_data = &(const struct clk_parent_data){ + .parent_data = &(const struct clk_parent_data) { .index = DT_BI_TCXO, }, .num_parents = 1, @@ -252,7 +252,7 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_cpuss_ahb_clk_src", .parent_data = gcc_parent_data_0_ao, .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao), @@ -272,7 +272,7 @@ static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_2, .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_cpuss_rbcpr_clk_src", .parent_data = gcc_parent_data_2_ao, .num_parents = ARRAY_SIZE(gcc_parent_data_2_ao), @@ -295,7 +295,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_gp1_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), @@ -309,7 +309,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_gp2_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), @@ -323,7 +323,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_1, .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_gp3_clk_src", .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), @@ -343,7 +343,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_3, .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_aux_clk_src", .parent_data = gcc_parent_data_3, .num_parents = ARRAY_SIZE(gcc_parent_data_3), @@ -363,7 +363,7 @@ static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_phy_refgen_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), @@ -383,7 +383,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_pdm2_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_pdm2_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), @@ -687,7 +687,7 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_5, .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc1_apps_clk_src", .parent_data = gcc_parent_data_5, .num_parents = ARRAY_SIZE(gcc_parent_data_5), @@ -709,7 +709,7 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc1_ice_core_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), @@ -734,7 +734,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_6, .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc2_apps_clk_src", .parent_data = gcc_parent_data_6, .num_parents = ARRAY_SIZE(gcc_parent_data_6), @@ -760,7 +760,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc4_apps_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), @@ -779,7 +779,7 @@ static struct clk_rcg2 gcc_tsif_ref_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_7, .freq_tbl = ftbl_gcc_tsif_ref_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_tsif_ref_clk_src", .parent_data = gcc_parent_data_7, .num_parents = ARRAY_SIZE(gcc_parent_data_7), @@ -802,7 +802,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_axi_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), @@ -824,7 +824,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_ice_core_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), @@ -838,7 +838,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_4, .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_phy_aux_clk_src", .parent_data = gcc_parent_data_4, .num_parents = ARRAY_SIZE(gcc_parent_data_4), @@ -859,7 +859,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_unipro_core_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), @@ -881,7 +881,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_usb30_prim_master_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), @@ -903,7 +903,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_usb30_prim_mock_utmi_clk_src", .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), @@ -922,7 +922,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_3, .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_usb3_prim_phy_aux_clk_src", .parent_data = gcc_parent_data_3, .num_parents = ARRAY_SIZE(gcc_parent_data_3), @@ -936,7 +936,7 @@ static struct clk_rcg2 gcc_vs_ctrl_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_2, .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_vs_ctrl_clk_src", .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), @@ -957,7 +957,7 @@ static struct clk_rcg2 gcc_vsensor_clk_src = { .hid_width = 5, .parent_map = gcc_parent_map_8, .freq_tbl = ftbl_gcc_vsensor_clk_src, - .clkr.hw.init = &(struct clk_init_data){ + .clkr.hw.init = &(const struct clk_init_data) { .name = "gcc_vsensor_clk_src", .parent_data = gcc_parent_data_8, .num_parents = ARRAY_SIZE(gcc_parent_data_8), @@ -971,7 +971,7 @@ static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { .clkr = { .enable_reg = 0x2800c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_aggre_noc_pcie_tbu_clk", .ops = &clk_branch2_ops, }, @@ -986,9 +986,9 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { .clkr = { .enable_reg = 0x82024, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_aggre_ufs_phy_axi_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents = 1, @@ -1006,9 +1006,9 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { .clkr = { .enable_reg = 0x82024, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_aggre_ufs_phy_axi_clk.clkr.hw, }, .num_parents = 1, @@ -1024,9 +1024,9 @@ static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { .clkr = { .enable_reg = 0x8201c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_aggre_usb3_prim_axi_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, @@ -1042,9 +1042,9 @@ static struct clk_branch gcc_apc_vs_clk = { .clkr = { .enable_reg = 0x7a050, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_apc_vs_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_vsensor_clk_src.clkr.hw, }, .num_parents = 1, @@ -1062,7 +1062,7 @@ static struct clk_branch gcc_boot_rom_ahb_clk = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_boot_rom_ahb_clk", .ops = &clk_branch2_ops, }, @@ -1075,7 +1075,7 @@ static struct clk_branch gcc_camera_hf_axi_clk = { .clkr = { .enable_reg = 0xb020, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_camera_hf_axi_clk", .ops = &clk_branch2_ops, }, @@ -1088,7 +1088,7 @@ static struct clk_branch gcc_camera_sf_axi_clk = { .clkr = { .enable_reg = 0xb06c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_camera_sf_axi_clk", .ops = &clk_branch2_ops, }, @@ -1103,7 +1103,7 @@ static struct clk_branch gcc_ce1_ahb_clk = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(3), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ce1_ahb_clk", .ops = &clk_branch2_ops, }, @@ -1116,7 +1116,7 @@ static struct clk_branch gcc_ce1_axi_clk = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ce1_axi_clk", .ops = &clk_branch2_ops, }, @@ -1129,7 +1129,7 @@ static struct clk_branch gcc_ce1_clk = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(5), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ce1_clk", .ops = &clk_branch2_ops, }, @@ -1142,9 +1142,9 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { .clkr = { .enable_reg = 0x502c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_cfg_noc_usb3_prim_axi_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, @@ -1160,9 +1160,9 @@ static struct clk_branch gcc_cpuss_ahb_clk = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_cpuss_ahb_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_cpuss_ahb_clk_src.clkr.hw, }, .num_parents = 1, @@ -1178,9 +1178,9 @@ static struct clk_branch gcc_cpuss_rbcpr_clk = { .clkr = { .enable_reg = 0x48008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_cpuss_rbcpr_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_cpuss_rbcpr_clk_src.clkr.hw, }, .num_parents = 1, @@ -1196,7 +1196,7 @@ static struct clk_branch gcc_ddrss_gpu_axi_clk = { .clkr = { .enable_reg = 0x4452c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ddrss_gpu_axi_clk", .ops = &clk_branch2_ops, }, @@ -1209,9 +1209,9 @@ static struct clk_branch gcc_disp_gpll0_clk_src = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(18), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_disp_gpll0_clk_src", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gpll0.clkr.hw, }, .num_parents = 1, @@ -1225,9 +1225,9 @@ static struct clk_branch gcc_disp_gpll0_div_clk_src = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(19), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_disp_gpll0_div_clk_src", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_pll0_main_div_cdiv.hw, }, .num_parents = 1, @@ -1242,7 +1242,7 @@ static struct clk_branch gcc_disp_hf_axi_clk = { .clkr = { .enable_reg = 0xb024, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_disp_hf_axi_clk", .ops = &clk_branch2_ops, }, @@ -1255,7 +1255,7 @@ static struct clk_branch gcc_disp_sf_axi_clk = { .clkr = { .enable_reg = 0xb070, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_disp_sf_axi_clk", .ops = &clk_branch2_ops, }, @@ -1269,9 +1269,9 @@ static struct clk_branch gcc_gp1_clk = { .clkr = { .enable_reg = 0x64000, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_gp1_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_gp1_clk_src.clkr.hw, }, .num_parents = 1, @@ -1287,9 +1287,9 @@ static struct clk_branch gcc_gp2_clk = { .clkr = { .enable_reg = 0x65000, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_gp2_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_gp2_clk_src.clkr.hw, }, .num_parents = 1, @@ -1305,9 +1305,9 @@ static struct clk_branch gcc_gp3_clk = { .clkr = { .enable_reg = 0x66000, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_gp3_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_gp3_clk_src.clkr.hw, }, .num_parents = 1, @@ -1322,9 +1322,9 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_gpu_gpll0_clk_src", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gpll0.clkr.hw, }, .num_parents = 1, @@ -1338,9 +1338,9 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(16), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_gpu_gpll0_div_clk_src", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_pll0_main_div_cdiv.hw, }, .num_parents = 1, @@ -1355,7 +1355,7 @@ static struct clk_branch gcc_gpu_memnoc_gfx_clk = { .clkr = { .enable_reg = 0x7100c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_gpu_memnoc_gfx_clk", .ops = &clk_branch2_ops, }, @@ -1368,7 +1368,7 @@ static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { .clkr = { .enable_reg = 0x71018, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_gpu_snoc_dvm_gfx_clk", .ops = &clk_branch2_ops, }, @@ -1381,9 +1381,9 @@ static struct clk_branch gcc_gpu_vs_clk = { .clkr = { .enable_reg = 0x7a04c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_gpu_vs_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_vsensor_clk_src.clkr.hw, }, .num_parents = 1, @@ -1399,7 +1399,7 @@ static struct clk_branch gcc_npu_axi_clk = { .clkr = { .enable_reg = 0x4d008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_npu_axi_clk", .ops = &clk_branch2_ops, }, @@ -1414,7 +1414,7 @@ static struct clk_branch gcc_npu_cfg_ahb_clk = { .clkr = { .enable_reg = 0x4d004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_npu_cfg_ahb_clk", .flags = CLK_IS_CRITICAL, .ops = &clk_branch2_ops, @@ -1427,9 +1427,9 @@ static struct clk_branch gcc_npu_gpll0_clk_src = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(25), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_npu_gpll0_clk_src", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gpll0.clkr.hw, }, .num_parents = 1, @@ -1443,9 +1443,9 @@ static struct clk_branch gcc_npu_gpll0_div_clk_src = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(26), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_npu_gpll0_div_clk_src", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_pll0_main_div_cdiv.hw, }, .num_parents = 1, @@ -1461,9 +1461,9 @@ static struct clk_branch gcc_pcie_0_aux_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(3), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_aux_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_pcie_0_aux_clk_src.clkr.hw, }, .num_parents = 1, @@ -1481,7 +1481,7 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(2), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_cfg_ahb_clk", .ops = &clk_branch2_ops, }, @@ -1494,7 +1494,7 @@ static struct clk_branch gcc_pcie_0_clkref_clk = { .clkr = { .enable_reg = 0x8c008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_clkref_clk", .ops = &clk_branch2_ops, }, @@ -1507,7 +1507,7 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_mstr_axi_clk", .ops = &clk_branch2_ops, }, @@ -1520,7 +1520,7 @@ static struct clk_branch gcc_pcie_0_pipe_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_pipe_clk", .ops = &clk_branch2_ops, }, @@ -1535,7 +1535,7 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_slv_axi_clk", .ops = &clk_branch2_ops, }, @@ -1548,7 +1548,7 @@ static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(5), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_slv_q2a_axi_clk", .ops = &clk_branch2_ops, }, @@ -1561,9 +1561,9 @@ static struct clk_branch gcc_pcie_phy_aux_clk = { .clkr = { .enable_reg = 0x6f004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_phy_aux_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_pcie_0_aux_clk_src.clkr.hw, }, .num_parents = 1, @@ -1579,9 +1579,9 @@ static struct clk_branch gcc_pcie_phy_refgen_clk = { .clkr = { .enable_reg = 0x6f02c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_phy_refgen_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_pcie_phy_refgen_clk_src.clkr.hw, }, .num_parents = 1, @@ -1597,9 +1597,9 @@ static struct clk_branch gcc_pdm2_clk = { .clkr = { .enable_reg = 0x3300c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pdm2_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_pdm2_clk_src.clkr.hw, }, .num_parents = 1, @@ -1617,7 +1617,7 @@ static struct clk_branch gcc_pdm_ahb_clk = { .clkr = { .enable_reg = 0x33004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pdm_ahb_clk", .ops = &clk_branch2_ops, }, @@ -1630,7 +1630,7 @@ static struct clk_branch gcc_pdm_xo4_clk = { .clkr = { .enable_reg = 0x33008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_pdm_xo4_clk", .ops = &clk_branch2_ops, }, @@ -1645,7 +1645,7 @@ static struct clk_branch gcc_prng_ahb_clk = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(13), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_prng_ahb_clk", .ops = &clk_branch2_ops, }, @@ -1658,7 +1658,7 @@ static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_core_2x_clk", .ops = &clk_branch2_ops, }, @@ -1671,7 +1671,7 @@ static struct clk_branch gcc_qupv3_wrap0_core_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(8), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_core_clk", .ops = &clk_branch2_ops, }, @@ -1684,9 +1684,9 @@ static struct clk_branch gcc_qupv3_wrap0_s0_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_s0_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, }, .num_parents = 1, @@ -1702,9 +1702,9 @@ static struct clk_branch gcc_qupv3_wrap0_s1_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_s1_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, }, .num_parents = 1, @@ -1720,9 +1720,9 @@ static struct clk_branch gcc_qupv3_wrap0_s2_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(12), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_s2_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, }, .num_parents = 1, @@ -1738,9 +1738,9 @@ static struct clk_branch gcc_qupv3_wrap0_s3_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(13), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_s3_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, }, .num_parents = 1, @@ -1756,9 +1756,9 @@ static struct clk_branch gcc_qupv3_wrap0_s4_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(14), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_s4_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, }, .num_parents = 1, @@ -1774,9 +1774,9 @@ static struct clk_branch gcc_qupv3_wrap0_s5_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_s5_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, }, .num_parents = 1, @@ -1792,9 +1792,9 @@ static struct clk_branch gcc_qupv3_wrap0_s6_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(16), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_s6_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, }, .num_parents = 1, @@ -1810,9 +1810,9 @@ static struct clk_branch gcc_qupv3_wrap0_s7_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(17), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap0_s7_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, }, .num_parents = 1, @@ -1828,7 +1828,7 @@ static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(18), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_core_2x_clk", .ops = &clk_branch2_ops, }, @@ -1841,7 +1841,7 @@ static struct clk_branch gcc_qupv3_wrap1_core_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(19), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_core_clk", .ops = &clk_branch2_ops, }, @@ -1854,9 +1854,9 @@ static struct clk_branch gcc_qupv3_wrap1_s0_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(22), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_s0_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, }, .num_parents = 1, @@ -1872,9 +1872,9 @@ static struct clk_branch gcc_qupv3_wrap1_s1_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(23), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_s1_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, }, .num_parents = 1, @@ -1890,9 +1890,9 @@ static struct clk_branch gcc_qupv3_wrap1_s2_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(24), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_s2_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, }, .num_parents = 1, @@ -1908,9 +1908,9 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(25), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_s3_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, }, .num_parents = 1, @@ -1926,9 +1926,9 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(26), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_s4_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, }, .num_parents = 1, @@ -1944,9 +1944,9 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(27), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_s5_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, }, .num_parents = 1, @@ -1962,9 +1962,9 @@ static struct clk_branch gcc_qupv3_wrap1_s6_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(28), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_s6_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, }, .num_parents = 1, @@ -1980,9 +1980,9 @@ static struct clk_branch gcc_qupv3_wrap1_s7_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(29), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap1_s7_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, }, .num_parents = 1, @@ -1998,7 +1998,7 @@ static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(6), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap_0_m_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2013,7 +2013,7 @@ static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap_0_s_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2026,7 +2026,7 @@ static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(20), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap_1_m_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2041,7 +2041,7 @@ static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_qupv3_wrap_1_s_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2054,7 +2054,7 @@ static struct clk_branch gcc_sdcc1_ahb_clk = { .clkr = { .enable_reg = 0x12008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc1_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2067,9 +2067,9 @@ static struct clk_branch gcc_sdcc1_apps_clk = { .clkr = { .enable_reg = 0x1200c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc1_apps_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_sdcc1_apps_clk_src.clkr.hw, }, .num_parents = 1, @@ -2085,9 +2085,9 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = { .clkr = { .enable_reg = 0x12040, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc1_ice_core_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_sdcc1_ice_core_clk_src.clkr.hw, }, .num_parents = 1, @@ -2103,7 +2103,7 @@ static struct clk_branch gcc_sdcc2_ahb_clk = { .clkr = { .enable_reg = 0x14008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc2_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2116,9 +2116,9 @@ static struct clk_branch gcc_sdcc2_apps_clk = { .clkr = { .enable_reg = 0x14004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc2_apps_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_sdcc2_apps_clk_src.clkr.hw, }, .num_parents = 1, @@ -2134,7 +2134,7 @@ static struct clk_branch gcc_sdcc4_ahb_clk = { .clkr = { .enable_reg = 0x16008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc4_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2147,9 +2147,9 @@ static struct clk_branch gcc_sdcc4_apps_clk = { .clkr = { .enable_reg = 0x16004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_sdcc4_apps_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_sdcc4_apps_clk_src.clkr.hw, }, .num_parents = 1, @@ -2165,9 +2165,9 @@ static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_sys_noc_cpuss_ahb_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_cpuss_ahb_clk_src.clkr.hw, }, .num_parents = 1, @@ -2183,7 +2183,7 @@ static struct clk_branch gcc_tsif_ahb_clk = { .clkr = { .enable_reg = 0x36004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_tsif_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2196,7 +2196,7 @@ static struct clk_branch gcc_tsif_inactivity_timers_clk = { .clkr = { .enable_reg = 0x3600c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_tsif_inactivity_timers_clk", .ops = &clk_branch2_ops, }, @@ -2209,9 +2209,9 @@ static struct clk_branch gcc_tsif_ref_clk = { .clkr = { .enable_reg = 0x36008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_tsif_ref_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_tsif_ref_clk_src.clkr.hw, }, .num_parents = 1, @@ -2227,7 +2227,7 @@ static struct clk_branch gcc_ufs_mem_clkref_clk = { .clkr = { .enable_reg = 0x8c000, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_mem_clkref_clk", .ops = &clk_branch2_ops, }, @@ -2242,7 +2242,7 @@ static struct clk_branch gcc_ufs_phy_ahb_clk = { .clkr = { .enable_reg = 0x77014, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2257,9 +2257,9 @@ static struct clk_branch gcc_ufs_phy_axi_clk = { .clkr = { .enable_reg = 0x77038, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_axi_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents = 1, @@ -2277,9 +2277,9 @@ static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { .clkr = { .enable_reg = 0x77038, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_axi_hw_ctl_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_ufs_phy_axi_clk.clkr.hw, }, .num_parents = 1, @@ -2297,9 +2297,9 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = { .clkr = { .enable_reg = 0x77090, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_ice_core_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_ufs_phy_ice_core_clk_src.clkr.hw, }, .num_parents = 1, @@ -2317,9 +2317,9 @@ static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { .clkr = { .enable_reg = 0x77090, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_ufs_phy_ice_core_clk.clkr.hw, }, .num_parents = 1, @@ -2337,9 +2337,9 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = { .clkr = { .enable_reg = 0x77094, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_phy_aux_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, @@ -2357,9 +2357,9 @@ static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { .clkr = { .enable_reg = 0x77094, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_ufs_phy_phy_aux_clk.clkr.hw, }, .num_parents = 1, @@ -2375,7 +2375,7 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { .clkr = { .enable_reg = 0x7701c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_rx_symbol_0_clk", .ops = &clk_branch2_ops, }, @@ -2388,7 +2388,7 @@ static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { .clkr = { .enable_reg = 0x77018, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_tx_symbol_0_clk", .ops = &clk_branch2_ops, }, @@ -2403,9 +2403,9 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = { .clkr = { .enable_reg = 0x7708c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_unipro_core_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, }, .num_parents = 1, @@ -2423,9 +2423,9 @@ static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { .clkr = { .enable_reg = 0x7708c, .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_ufs_phy_unipro_core_clk.clkr.hw, }, .num_parents = 1, @@ -2441,9 +2441,9 @@ static struct clk_branch gcc_usb30_prim_master_clk = { .clkr = { .enable_reg = 0xf010, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb30_prim_master_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, @@ -2459,9 +2459,9 @@ static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { .clkr = { .enable_reg = 0xf018, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb30_prim_mock_utmi_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, }, .num_parents = 1, @@ -2477,7 +2477,7 @@ static struct clk_branch gcc_usb30_prim_sleep_clk = { .clkr = { .enable_reg = 0xf014, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb30_prim_sleep_clk", .ops = &clk_branch2_ops, }, @@ -2490,7 +2490,7 @@ static struct clk_branch gcc_usb3_prim_clkref_clk = { .clkr = { .enable_reg = 0x8c010, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb3_prim_clkref_clk", .ops = &clk_branch2_ops, }, @@ -2503,9 +2503,9 @@ static struct clk_branch gcc_usb3_prim_phy_aux_clk = { .clkr = { .enable_reg = 0xf050, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb3_prim_phy_aux_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, @@ -2521,9 +2521,9 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { .clkr = { .enable_reg = 0xf054, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb3_prim_phy_com_aux_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, @@ -2538,7 +2538,7 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { .clkr = { .enable_reg = 0xf058, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb3_prim_phy_pipe_clk", .ops = &clk_branch2_ops, }, @@ -2553,7 +2553,7 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { .clkr = { .enable_reg = 0x6a004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_usb_phy_cfg_ahb2phy_clk", .ops = &clk_branch2_ops, }, @@ -2566,9 +2566,9 @@ static struct clk_branch gcc_vdda_vs_clk = { .clkr = { .enable_reg = 0x7a00c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_vdda_vs_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_vsensor_clk_src.clkr.hw, }, .num_parents = 1, @@ -2584,9 +2584,9 @@ static struct clk_branch gcc_vddcx_vs_clk = { .clkr = { .enable_reg = 0x7a004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_vddcx_vs_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_vsensor_clk_src.clkr.hw, }, .num_parents = 1, @@ -2602,9 +2602,9 @@ static struct clk_branch gcc_vddmx_vs_clk = { .clkr = { .enable_reg = 0x7a008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_vddmx_vs_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_vsensor_clk_src.clkr.hw, }, .num_parents = 1, @@ -2621,7 +2621,7 @@ static struct clk_branch gcc_video_axi_clk = { .clkr = { .enable_reg = 0xb01c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_video_axi_clk", .ops = &clk_branch2_ops, }, @@ -2636,7 +2636,7 @@ static struct clk_branch gcc_vs_ctrl_ahb_clk = { .clkr = { .enable_reg = 0x7a014, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_vs_ctrl_ahb_clk", .ops = &clk_branch2_ops, }, @@ -2649,9 +2649,9 @@ static struct clk_branch gcc_vs_ctrl_clk = { .clkr = { .enable_reg = 0x7a010, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "gcc_vs_ctrl_clk", - .parent_hws = (const struct clk_hw*[]){ + .parent_hws = (const struct clk_hw*[]) { &gcc_vs_ctrl_clk_src.clkr.hw, }, .num_parents = 1, @@ -3017,7 +3017,7 @@ static int gcc_sm7150_probe(struct platform_device *pdev) if (ret) return ret; - return qcom_cc_really_probe(pdev, &gcc_sm7150_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sm7150_desc, regmap); } static struct platform_driver gcc_sm7150_driver = { |