diff options
Diffstat (limited to 'drivers/clk/qcom/camcc-sc7180.c')
| -rw-r--r-- | drivers/clk/qcom/camcc-sc7180.c | 221 |
1 files changed, 104 insertions, 117 deletions
diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c index ce73ee9037cb..e2b4804695f3 100644 --- a/drivers/clk/qcom/camcc-sc7180.c +++ b/drivers/clk/qcom/camcc-sc7180.c @@ -29,7 +29,6 @@ enum { P_CAM_CC_PLL2_OUT_AUX, P_CAM_CC_PLL2_OUT_EARLY, P_CAM_CC_PLL3_OUT_MAIN, - P_CORE_BI_PLL_TEST_SE, }; static const struct pll_vco agera_vco[] = { @@ -127,7 +126,9 @@ static struct clk_fixed_factor cam_cc_pll2_out_early = { .div = 2, .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll2_out_early", - .parent_names = (const char *[]){ "cam_cc_pll2" }, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll2.clkr.hw, + }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, @@ -147,8 +148,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll2_out_aux", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_pll2.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll2.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -187,26 +188,22 @@ static const struct parent_map cam_cc_parent_map_0[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL1_OUT_EVEN, 2 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_0[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll1.clkr.hw }, { .hw = &cam_cc_pll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map cam_cc_parent_map_1[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL2_OUT_AUX, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_1[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll2_out_aux.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map cam_cc_parent_map_2[] = { @@ -214,7 +211,6 @@ static const struct parent_map cam_cc_parent_map_2[] = { { P_CAM_CC_PLL2_OUT_EARLY, 4 }, { P_CAM_CC_PLL3_OUT_MAIN, 5 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_2[] = { @@ -222,7 +218,6 @@ static const struct clk_parent_data cam_cc_parent_data_2[] = { { .hw = &cam_cc_pll2_out_early.hw }, { .hw = &cam_cc_pll3.clkr.hw }, { .hw = &cam_cc_pll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map cam_cc_parent_map_3[] = { @@ -231,7 +226,6 @@ static const struct parent_map cam_cc_parent_map_3[] = { { P_CAM_CC_PLL2_OUT_EARLY, 4 }, { P_CAM_CC_PLL3_OUT_MAIN, 5 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_3[] = { @@ -240,33 +234,28 @@ static const struct clk_parent_data cam_cc_parent_data_3[] = { { .hw = &cam_cc_pll2_out_early.hw }, { .hw = &cam_cc_pll3.clkr.hw }, { .hw = &cam_cc_pll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map cam_cc_parent_map_4[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL3_OUT_MAIN, 5 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_4[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll3.clkr.hw }, { .hw = &cam_cc_pll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map cam_cc_parent_map_5[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_5[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map cam_cc_parent_map_6[] = { @@ -274,7 +263,6 @@ static const struct parent_map cam_cc_parent_map_6[] = { { P_CAM_CC_PLL1_OUT_EVEN, 2 }, { P_CAM_CC_PLL3_OUT_MAIN, 5 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_6[] = { @@ -282,7 +270,6 @@ static const struct clk_parent_data cam_cc_parent_data_6[] = { { .hw = &cam_cc_pll1.clkr.hw }, { .hw = &cam_cc_pll3.clkr.hw }, { .hw = &cam_cc_pll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { @@ -303,7 +290,7 @@ static struct clk_rcg2 cam_cc_bps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_clk_src", .parent_data = cam_cc_parent_data_2, - .num_parents = 5, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), .ops = &clk_rcg2_shared_ops, }, }; @@ -324,7 +311,7 @@ static struct clk_rcg2 cam_cc_cci_0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_0_clk_src", .parent_data = cam_cc_parent_data_5, - .num_parents = 3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), .ops = &clk_rcg2_shared_ops, }, }; @@ -338,7 +325,7 @@ static struct clk_rcg2 cam_cc_cci_1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_1_clk_src", .parent_data = cam_cc_parent_data_5, - .num_parents = 3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), .ops = &clk_rcg2_shared_ops, }, }; @@ -359,7 +346,7 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cphy_rx_clk_src", .parent_data = cam_cc_parent_data_3, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -378,7 +365,7 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi0phytimer_clk_src", .parent_data = cam_cc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -392,7 +379,7 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi1phytimer_clk_src", .parent_data = cam_cc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -406,7 +393,7 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi2phytimer_clk_src", .parent_data = cam_cc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -420,7 +407,7 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi3phytimer_clk_src", .parent_data = cam_cc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -442,7 +429,7 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_fast_ahb_clk_src", .parent_data = cam_cc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -465,7 +452,7 @@ static struct clk_rcg2 cam_cc_icp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_icp_clk_src", .parent_data = cam_cc_parent_data_2, - .num_parents = 5, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), .ops = &clk_rcg2_shared_ops, }, }; @@ -487,7 +474,7 @@ static struct clk_rcg2 cam_cc_ife_0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_clk_src", .parent_data = cam_cc_parent_data_4, - .num_parents = 4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), .ops = &clk_rcg2_shared_ops, }, }; @@ -509,7 +496,7 @@ static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_csid_clk_src", .parent_data = cam_cc_parent_data_3, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -523,7 +510,7 @@ static struct clk_rcg2 cam_cc_ife_1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_clk_src", .parent_data = cam_cc_parent_data_4, - .num_parents = 4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), .ops = &clk_rcg2_shared_ops, }, }; @@ -537,7 +524,7 @@ static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_csid_clk_src", .parent_data = cam_cc_parent_data_3, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -551,7 +538,7 @@ static struct clk_rcg2 cam_cc_ife_lite_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_clk_src", .parent_data = cam_cc_parent_data_4, - .num_parents = 4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -566,7 +553,7 @@ static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_csid_clk_src", .parent_data = cam_cc_parent_data_3, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -589,7 +576,7 @@ static struct clk_rcg2 cam_cc_ipe_0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_clk_src", .parent_data = cam_cc_parent_data_2, - .num_parents = 5, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), .ops = &clk_rcg2_shared_ops, }, }; @@ -612,7 +599,7 @@ static struct clk_rcg2 cam_cc_jpeg_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_jpeg_clk_src", .parent_data = cam_cc_parent_data_2, - .num_parents = 5, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), .ops = &clk_rcg2_shared_ops, }, }; @@ -634,7 +621,7 @@ static struct clk_rcg2 cam_cc_lrme_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_lrme_clk_src", .parent_data = cam_cc_parent_data_6, - .num_parents = 5, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), .ops = &clk_rcg2_shared_ops, }, }; @@ -655,7 +642,7 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk0_clk_src", .parent_data = cam_cc_parent_data_1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .ops = &clk_rcg2_shared_ops, }, }; @@ -669,7 +656,7 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk1_clk_src", .parent_data = cam_cc_parent_data_1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .ops = &clk_rcg2_shared_ops, }, }; @@ -683,7 +670,7 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk2_clk_src", .parent_data = cam_cc_parent_data_1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .ops = &clk_rcg2_shared_ops, }, }; @@ -697,7 +684,7 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk3_clk_src", .parent_data = cam_cc_parent_data_1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .ops = &clk_rcg2_shared_ops, }, }; @@ -711,7 +698,7 @@ static struct clk_rcg2 cam_cc_mclk4_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk4_clk_src", .parent_data = cam_cc_parent_data_1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .ops = &clk_rcg2_shared_ops, }, }; @@ -730,7 +717,7 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_slow_ahb_clk_src", .parent_data = cam_cc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, .ops = &clk_rcg2_shared_ops, }, @@ -744,8 +731,8 @@ static struct clk_branch cam_cc_bps_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -762,8 +749,8 @@ static struct clk_branch cam_cc_bps_areg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_areg_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -793,8 +780,8 @@ static struct clk_branch cam_cc_bps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_bps_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_bps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -824,8 +811,8 @@ static struct clk_branch cam_cc_cci_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cci_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cci_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -842,8 +829,8 @@ static struct clk_branch cam_cc_cci_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cci_1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cci_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -860,8 +847,8 @@ static struct clk_branch cam_cc_core_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_core_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -878,8 +865,8 @@ static struct clk_branch cam_cc_cpas_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cpas_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -896,8 +883,8 @@ static struct clk_branch cam_cc_csi0phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi0phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_csi0phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi0phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -914,8 +901,8 @@ static struct clk_branch cam_cc_csi1phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi1phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_csi1phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi1phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -932,8 +919,8 @@ static struct clk_branch cam_cc_csi2phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi2phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_csi2phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi2phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -950,8 +937,8 @@ static struct clk_branch cam_cc_csi3phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi3phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_csi3phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi3phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -968,8 +955,8 @@ static struct clk_branch cam_cc_csiphy0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -986,8 +973,8 @@ static struct clk_branch cam_cc_csiphy1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1004,8 +991,8 @@ static struct clk_branch cam_cc_csiphy2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1022,8 +1009,8 @@ static struct clk_branch cam_cc_csiphy3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1040,8 +1027,8 @@ static struct clk_branch cam_cc_icp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_icp_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_icp_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_icp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1071,8 +1058,8 @@ static struct clk_branch cam_cc_ife_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1089,8 +1076,8 @@ static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_cphy_rx_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1107,8 +1094,8 @@ static struct clk_branch cam_cc_ife_0_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_csid_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_0_csid_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1125,8 +1112,8 @@ static struct clk_branch cam_cc_ife_0_dsp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_dsp_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1156,8 +1143,8 @@ static struct clk_branch cam_cc_ife_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1174,8 +1161,8 @@ static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_cphy_rx_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1192,8 +1179,8 @@ static struct clk_branch cam_cc_ife_1_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_csid_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_1_csid_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1210,8 +1197,8 @@ static struct clk_branch cam_cc_ife_1_dsp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_dsp_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1228,8 +1215,8 @@ static struct clk_branch cam_cc_ife_lite_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_lite_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_lite_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1246,8 +1233,8 @@ static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_cphy_rx_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1264,8 +1251,8 @@ static struct clk_branch cam_cc_ife_lite_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_csid_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_lite_csid_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_lite_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1282,8 +1269,8 @@ static struct clk_branch cam_cc_ipe_0_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1300,8 +1287,8 @@ static struct clk_branch cam_cc_ipe_0_areg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_areg_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1331,8 +1318,8 @@ static struct clk_branch cam_cc_ipe_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ipe_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ipe_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1349,8 +1336,8 @@ static struct clk_branch cam_cc_jpeg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_jpeg_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_jpeg_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_jpeg_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1367,8 +1354,8 @@ static struct clk_branch cam_cc_lrme_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_lrme_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_lrme_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_lrme_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1385,8 +1372,8 @@ static struct clk_branch cam_cc_mclk0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1403,8 +1390,8 @@ static struct clk_branch cam_cc_mclk1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1421,8 +1408,8 @@ static struct clk_branch cam_cc_mclk2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1439,8 +1426,8 @@ static struct clk_branch cam_cc_mclk3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1457,8 +1444,8 @@ static struct clk_branch cam_cc_mclk4_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk4_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk4_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, |