diff options
Diffstat (limited to 'arch')
78 files changed, 3170 insertions, 404 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 573be57d3d28..6f6d13f91e4c 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -212,7 +212,7 @@ config MACH_SMDKV310 select EXYNOS_DEV_SYSMMU select EXYNOS4_DEV_AHCI select SAMSUNG_DEV_KEYPAD - select EXYNOS4_DEV_DMA + select EXYNOS_DEV_DMA select SAMSUNG_DEV_PWM select EXYNOS4_DEV_USB_OHCI select EXYNOS4_SETUP_FIMD0 @@ -264,7 +264,7 @@ config MACH_UNIVERSAL_C210 select S5P_DEV_ONENAND select S5P_DEV_TV select EXYNOS_DEV_SYSMMU - select EXYNOS4_DEV_DMA + select EXYNOS_DEV_DMA select EXYNOS_DEV_DRM select EXYNOS4_SETUP_FIMD0 select EXYNOS4_SETUP_I2C1 @@ -303,7 +303,7 @@ config MACH_NURI select S5P_DEV_MFC select S5P_DEV_USB_EHCI select S5P_SETUP_MIPIPHY - select EXYNOS4_DEV_DMA + select EXYNOS_DEV_DMA select EXYNOS_DEV_DRM select EXYNOS4_SETUP_FIMC select EXYNOS4_SETUP_FIMD0 @@ -341,7 +341,7 @@ config MACH_ORIGEN select SAMSUNG_DEV_PWM select EXYNOS_DEV_DRM select EXYNOS_DEV_SYSMMU - select EXYNOS4_DEV_DMA + select EXYNOS_DEV_DMA select EXYNOS4_DEV_USB_OHCI select EXYNOS4_SETUP_FIMD0 select EXYNOS4_SETUP_SDHCI diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 17dc66a085a5..e1a17ac7b3b4 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -152,13 +152,14 @@ enum mx6q_clks { ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg, - ssi2_ipg, ssi3_ipg, clk_max + ssi2_ipg, ssi3_ipg, rom, + clk_max }; static struct clk *clk[clk_max]; static enum mx6q_clks const clks_init_on[] __initconst = { - mmdc_ch0_axi, mmdc_ch1_axi, + mmdc_ch0_axi, rom, }; int __init mx6q_clocks_init(void) @@ -364,6 +365,7 @@ int __init mx6q_clocks_init(void) clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28); clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); + clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4); clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c index 64c65bcb2d67..aa81593db1af 100644 --- a/arch/arm/mach-omap1/timer.c +++ b/arch/arm/mach-omap1/timer.c @@ -140,7 +140,8 @@ static int __init omap1_dm_timer_init(void) } pdata->set_timer_src = omap1_dm_timer_set_src; - pdata->needs_manual_reset = 1; + pdata->timer_capability = OMAP_TIMER_ALWON | + OMAP_TIMER_NEEDS_RESET; ret = platform_device_add_data(pdev, pdata, sizeof(*pdata)); if (ret) { diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 9ba1c406a465..54ad3a4b612c 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -90,6 +90,7 @@ obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o +obj-$(CONFIG_SOC_AM33XX) += prcm.o prm33xx.o cm33xx.o # OMAP voltage domains voltagedomain-common := voltage.o vc.o vp.o @@ -99,6 +100,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o +obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o # OMAP powerdomain framework powerdomain-common += powerdomain.o powerdomain-common.o @@ -113,6 +115,8 @@ obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o +obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o +obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o # PRCM clockdomain control clockdomain-common += clockdomain.o @@ -128,6 +132,8 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o +obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o +obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o # Clock framework obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index 70a81f900bb5..53c39d239d6e 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -97,11 +97,6 @@ __init board_onenand_init(struct mtd_partition *onenand_parts, gpmc_onenand_init(&board_onenand_data); } -#else -void -__init board_onenand_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs) -{ -} #endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */ #if defined(CONFIG_MTD_NAND_OMAP2) || \ diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 202934657867..2f2abfb82d84 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -112,6 +112,24 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") MACHINE_END #endif +#ifdef CONFIG_SOC_AM33XX +static const char *am33xx_boards_compat[] __initdata = { + "ti,am33xx", + NULL, +}; + +DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)") + .reserve = omap_reserve, + .map_io = am33xx_map_io, + .init_early = am33xx_init_early, + .init_irq = omap_init_irq, + .handle_irq = omap3_intc_handle_irq, + .init_machine = omap_generic_init, + .timer = &omap3_am33xx_timer, + .dt_compat = am33xx_boards_compat, +MACHINE_END +#endif + #ifdef CONFIG_ARCH_OMAP4 static const char *omap4_boards_compat[] __initdata = { "ti,omap4", diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 7e39015357b1..002745181ad6 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -1897,42 +1897,9 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "pka_ick", &pka_ick, CK_242X), CLK(NULL, "usb_fck", &usb_fck, CK_242X), CLK("musb-hdrc", "fck", &osc_ck, CK_242X), - CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.4", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.5", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.6", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.7", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.8", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.9", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.10", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.11", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.12", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.1", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.2", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.3", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.4", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.5", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.6", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.7", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.8", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.9", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.10", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.11", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.12", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.1", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.2", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.3", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.4", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.5", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.6", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.7", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.8", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.9", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.10", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.11", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.12", "alt_ck", &alt_ck, CK_243X), + CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X), + CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X), + CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X), }; /* diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 90a08c3b12ac..cacabb070e22 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -1990,42 +1990,9 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), - CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.4", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.5", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.6", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.7", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.8", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.9", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.10", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.11", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.12", "32k_ck", &func_32k_ck, CK_243X), - CLK("omap_timer.1", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.2", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.3", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.4", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.5", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.6", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.7", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.8", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.9", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.10", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.11", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.12", "sys_ck", &sys_ck, CK_243X), - CLK("omap_timer.1", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.2", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.3", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.4", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.5", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.6", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.7", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.8", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.9", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.10", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.11", "alt_ck", &alt_ck, CK_243X), - CLK("omap_timer.12", "alt_ck", &alt_ck, CK_243X), + CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X), + CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X), + CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X), }; /* diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index ff422bee804a..71a1d3383807 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3472,30 +3472,8 @@ static struct omap_clk omap3xxx_clks[] = { CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX), CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), - CLK("omap_timer.1", "32k_ck", &omap_32k_fck, CK_3XXX), - CLK("omap_timer.2", "32k_ck", &omap_32k_fck, CK_3XXX), - CLK("omap_timer.3", "32k_ck", &omap_32k_fck, CK_3XXX), - CLK("omap_timer.4", "32k_ck", &omap_32k_fck, CK_3XXX), - CLK("omap_timer.5", "32k_ck", &omap_32k_fck, CK_3XXX), - CLK("omap_timer.6", "32k_ck", &omap_32k_fck, CK_3XXX), - CLK("omap_timer.7", "32k_ck", &omap_32k_fck, CK_3XXX), - CLK("omap_timer.8", "32k_ck", &omap_32k_fck, CK_3XXX), - CLK("omap_timer.9", "32k_ck", &omap_32k_fck, CK_3XXX), - CLK("omap_timer.10", "32k_ck", &omap_32k_fck, CK_3XXX), - CLK("omap_timer.11", "32k_ck", &omap_32k_fck, CK_3XXX), - CLK("omap_timer.12", "32k_ck", &omap_32k_fck, CK_3XXX), - CLK("omap_timer.1", "sys_ck", &sys_ck, CK_3XXX), - CLK("omap_timer.2", "sys_ck", &sys_ck, CK_3XXX), - CLK("omap_timer.3", "sys_ck", &sys_ck, CK_3XXX), - CLK("omap_timer.4", "sys_ck", &sys_ck, CK_3XXX), - CLK("omap_timer.5", "sys_ck", &sys_ck, CK_3XXX), - CLK("omap_timer.6", "sys_ck", &sys_ck, CK_3XXX), - CLK("omap_timer.7", "sys_ck", &sys_ck, CK_3XXX), - CLK("omap_timer.8", "sys_ck", &sys_ck, CK_3XXX), - CLK("omap_timer.9", "sys_ck", &sys_ck, CK_3XXX), - CLK("omap_timer.10", "sys_ck", &sys_ck, CK_3XXX), - CLK("omap_timer.11", "sys_ck", &sys_ck, CK_3XXX), - CLK("omap_timer.12", "sys_ck", &sys_ck, CK_3XXX), + CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX), + CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX), }; diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index e2b701e164f6..de53b7014b80 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -3385,28 +3385,18 @@ static struct omap_clk omap44xx_clks[] = { CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X), CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X), CLK("omap_wdt", "ick", &dummy_ck, CK_443X), - CLK("omap_timer.1", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.2", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.3", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.4", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.5", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.6", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.7", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.8", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.9", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.10", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.11", "32k_ck", &sys_32k_ck, CK_443X), - CLK("omap_timer.1", "sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.2", "sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.3", "sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.4", "sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.9", "sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.10", "sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.11", "sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.5", "sys_ck", &syc_clk_div_ck, CK_443X), - CLK("omap_timer.6", "sys_ck", &syc_clk_div_ck, CK_443X), - CLK("omap_timer.7", "sys_ck", &syc_clk_div_ck, CK_443X), - CLK("omap_timer.8", "sys_ck", &syc_clk_div_ck, CK_443X), + CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X), + CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X), }; int __init omap4xxx_clk_init(void) @@ -3417,9 +3407,12 @@ int __init omap4xxx_clk_init(void) if (cpu_is_omap443x()) { cpu_mask = RATE_IN_4430; cpu_clkflg = CK_443X; - } else if (cpu_is_omap446x()) { + } else if (cpu_is_omap446x() || cpu_is_omap447x()) { cpu_mask = RATE_IN_4460 | RATE_IN_4430; cpu_clkflg = CK_446X | CK_443X; + + if (cpu_is_omap447x()) + pr_warn("WARNING: OMAP4470 clock data incomplete!\n"); } else { return 0; } diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 349dcbb6fecb..0a8c7b67858c 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -195,6 +195,7 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh); extern void __init omap242x_clockdomains_init(void); extern void __init omap243x_clockdomains_init(void); extern void __init omap3xxx_clockdomains_init(void); +extern void __init am33xx_clockdomains_init(void); extern void __init omap44xx_clockdomains_init(void); extern void _clkdm_add_autodeps(struct clockdomain *clkdm); extern void _clkdm_del_autodeps(struct clockdomain *clkdm); @@ -202,6 +203,7 @@ extern void _clkdm_del_autodeps(struct clockdomain *clkdm); extern struct clkdm_ops omap2_clkdm_operations; extern struct clkdm_ops omap3_clkdm_operations; extern struct clkdm_ops omap4_clkdm_operations; +extern struct clkdm_ops am33xx_clkdm_operations; extern struct clkdm_dep gfx_24xx_wkdeps[]; extern struct clkdm_dep dsp_24xx_wkdeps[]; diff --git a/arch/arm/mach-omap2/clockdomain33xx.c b/arch/arm/mach-omap2/clockdomain33xx.c new file mode 100644 index 000000000000..aca6388fad76 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomain33xx.c @@ -0,0 +1,74 @@ +/* + * AM33XX clockdomain control + * + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * Vaibhav Hiremath <hvaibhav@ti.com> + * + * Derived from mach-omap2/clockdomain44xx.c written by Rajendra Nayak + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> + +#include "clockdomain.h" +#include "cm33xx.h" + + +static int am33xx_clkdm_sleep(struct clockdomain *clkdm) +{ + am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs); + return 0; +} + +static int am33xx_clkdm_wakeup(struct clockdomain *clkdm) +{ + am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs); + return 0; +} + +static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm) +{ + am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); +} + +static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm) +{ + am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); +} + +static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm) +{ + if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) + return am33xx_clkdm_wakeup(clkdm); + + return 0; +} + +static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm) +{ + bool hwsup = false; + + hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); + + if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) + am33xx_clkdm_sleep(clkdm); + + return 0; +} + +struct clkdm_ops am33xx_clkdm_operations = { + .clkdm_sleep = am33xx_clkdm_sleep, + .clkdm_wakeup = am33xx_clkdm_wakeup, + .clkdm_allow_idle = am33xx_clkdm_allow_idle, + .clkdm_deny_idle = am33xx_clkdm_deny_idle, + .clkdm_clk_enable = am33xx_clkdm_clk_enable, + .clkdm_clk_disable = am33xx_clkdm_clk_disable, +}; diff --git a/arch/arm/mach-omap2/clockdomains33xx_data.c b/arch/arm/mach-omap2/clockdomains33xx_data.c new file mode 100644 index 000000000000..32c90fd9eba2 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomains33xx_data.c @@ -0,0 +1,196 @@ +/* + * AM33XX Clock Domain data. + * + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * Vaibhav Hiremath <hvaibhav@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/io.h> + +#include "clockdomain.h" +#include "cm.h" +#include "cm33xx.h" +#include "cm-regbits-33xx.h" + +static struct clockdomain l4ls_am33xx_clkdm = { + .name = "l4ls_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain l3s_am33xx_clkdm = { + .name = "l3s_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain l4fw_am33xx_clkdm = { + .name = "l4fw_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain l3_am33xx_clkdm = { + .name = "l3_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain l4hs_am33xx_clkdm = { + .name = "l4hs_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain ocpwp_l3_am33xx_clkdm = { + .name = "ocpwp_l3_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain pruss_ocp_am33xx_clkdm = { + .name = "pruss_ocp_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain cpsw_125mhz_am33xx_clkdm = { + .name = "cpsw_125mhz_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain lcdc_am33xx_clkdm = { + .name = "lcdc_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain clk_24mhz_am33xx_clkdm = { + .name = "clk_24mhz_clkdm", + .pwrdm = { .name = "per_pwrdm" }, + .cm_inst = AM33XX_CM_PER_MOD, + .clkdm_offs = AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain l4_wkup_am33xx_clkdm = { + .name = "l4_wkup_clkdm", + .pwrdm = { .name = "wkup_pwrdm" }, + .cm_inst = AM33XX_CM_WKUP_MOD, + .clkdm_offs = AM33XX_CM_WKUP_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain l3_aon_am33xx_clkdm = { + .name = "l3_aon_clkdm", + .pwrdm = { .name = "wkup_pwrdm" }, + .cm_inst = AM33XX_CM_WKUP_MOD, + .clkdm_offs = AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain l4_wkup_aon_am33xx_clkdm = { + .name = "l4_wkup_aon_clkdm", + .pwrdm = { .name = "wkup_pwrdm" }, + .cm_inst = AM33XX_CM_WKUP_MOD, + .clkdm_offs = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain mpu_am33xx_clkdm = { + .name = "mpu_clkdm", + .pwrdm = { .name = "mpu_pwrdm" }, + .cm_inst = AM33XX_CM_MPU_MOD, + .clkdm_offs = AM33XX_CM_MPU_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain l4_rtc_am33xx_clkdm = { + .name = "l4_rtc_clkdm", + .pwrdm = { .name = "rtc_pwrdm" }, + .cm_inst = AM33XX_CM_RTC_MOD, + .clkdm_offs = AM33XX_CM_RTC_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain gfx_l3_am33xx_clkdm = { + .name = "gfx_l3_clkdm", + .pwrdm = { .name = "gfx_pwrdm" }, + .cm_inst = AM33XX_CM_GFX_MOD, + .clkdm_offs = AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = { + .name = "gfx_l4ls_gfx_clkdm", + .pwrdm = { .name = "gfx_pwrdm" }, + .cm_inst = AM33XX_CM_GFX_MOD, + .clkdm_offs = AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain l4_cefuse_am33xx_clkdm = { + .name = "l4_cefuse_clkdm", + .pwrdm = { .name = "cefuse_pwrdm" }, + .cm_inst = AM33XX_CM_CEFUSE_MOD, + .clkdm_offs = AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET, + .flags = CLKDM_CAN_SWSUP, +}; + +static struct clockdomain *clockdomains_am33xx[] __initdata = { + &l4ls_am33xx_clkdm, + &l3s_am33xx_clkdm, + &l4fw_am33xx_clkdm, + &l3_am33xx_clkdm, + &l4hs_am33xx_clkdm, + &ocpwp_l3_am33xx_clkdm, + &pruss_ocp_am33xx_clkdm, + &cpsw_125mhz_am33xx_clkdm, + &lcdc_am33xx_clkdm, + &clk_24mhz_am33xx_clkdm, + &l4_wkup_am33xx_clkdm, + &l3_aon_am33xx_clkdm, + &l4_wkup_aon_am33xx_clkdm, + &mpu_am33xx_clkdm, + &l4_rtc_am33xx_clkdm, + &gfx_l3_am33xx_clkdm, + &gfx_l4ls_gfx_am33xx_clkdm, + &l4_cefuse_am33xx_clkdm, + NULL, +}; + +void __init am33xx_clockdomains_init(void) +{ + clkdm_register_platform_funcs(&am33xx_clkdm_operations); + clkdm_register_clkdms(clockdomains_am33xx); + clkdm_complete_init(); +} diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h new file mode 100644 index 000000000000..532027ee3d8d --- /dev/null +++ b/arch/arm/mach-omap2/cm-regbits-33xx.h @@ -0,0 +1,687 @@ +/* + * AM33XX Power Management register bits + * + * This file is automatically generated from the AM33XX hardware databases. + * Vaibhav Hiremath <hvaibhav@ti.com> + * + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H +#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H + +/* + * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP, + * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER + */ +#define AM33XX_AUTO_DPLL_MODE_SHIFT 0 +#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0) + +/* Used by CM_WKUP_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14 +#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16) + +/* Used by CM_PER_L4LS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11 +#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11) + +/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4) + +/* Used by CM_PER_CPSW_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4) + +/* Used by CM_PER_L4HS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4) + +/* Used by CM_PER_L4HS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5 +#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5) + +/* Used by CM_PER_L4HS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6 +#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6) + +/* Used by CM_PER_L3_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6 +#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6) + +/* Used by CM_CEFUSE_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 +#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) + +/* Used by CM_L3_AON_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2 +#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2) + +/* Used by CM_L3_AON_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4 +#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4) + +/* Used by CM_PER_L3_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2 +#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2) + +/* Used by CM_GFX_L3_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9 +#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9) + +/* Used by CM_GFX_L3_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8) + +/* Used by CM_WKUP_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8) + +/* Used by CM_PER_L4LS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19 +#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19) + +/* Used by CM_PER_L4LS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20 +#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20) + +/* Used by CM_PER_L4LS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21 +#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21) + +/* Used by CM_PER_L4LS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22 +#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22) + +/* Used by CM_PER_L4LS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26 +#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26) + +/* Used by CM_PER_L4LS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18 +#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18) + +/* Used by CM_WKUP_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11 +#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11) + +/* Used by CM_PER_L4LS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24 +#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24) + +/* Used by CM_PER_PRUSS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5 +#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5) + +/* Used by CM_PER_PRUSS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4) + +/* Used by CM_PER_PRUSS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6 +#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6) + +/* Used by CM_PER_L3S_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3 +#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3) + +/* Used by CM_L3_AON_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3 +#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3) + +/* Used by CM_PER_L3_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4) + +/* Used by CM_PER_L4FW_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8) + +/* Used by CM_PER_L4HS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3 +#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3) + +/* Used by CM_PER_L4LS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8) + +/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */ +#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8) + +/* Used by CM_CEFUSE_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) + +/* Used by CM_RTC_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8 +#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8) + +/* Used by CM_L4_WKUP_AON_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2 +#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2) + +/* Used by CM_WKUP_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2 +#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2) + +/* Used by CM_PER_L4LS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17 +#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17) + +/* Used by CM_PER_LCDC_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4) + +/* Used by CM_PER_LCDC_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5 +#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5) + +/* Used by CM_PER_L3_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7 +#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7) + +/* Used by CM_PER_L3_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3 +#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3) + +/* Used by CM_MPU_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2 +#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2) + +/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4) + +/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5 +#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5) + +/* Used by CM_RTC_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9 +#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9) + +/* Used by CM_PER_L4LS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25 +#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25) + +/* Used by CM_WKUP_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3 +#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3) + +/* Used by CM_WKUP_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10 +#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10) + +/* Used by CM_WKUP_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13 +#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13) + +/* Used by CM_PER_L4LS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14 +#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14) + +/* Used by CM_PER_L4LS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15 +#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15) + +/* Used by CM_PER_L4LS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16 +#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16) + +/* Used by CM_PER_L4LS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27 +#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27) + +/* Used by CM_PER_L4LS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28 +#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28) + +/* Used by CM_PER_L4LS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13 +#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13) + +/* Used by CM_WKUP_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12 +#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12) + +/* Used by CM_PER_L4LS_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10 +#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10) + +/* Used by CM_WKUP_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9 +#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9) + +/* Used by CM_WKUP_CLKSTCTRL */ +#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4 +#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4) + +/* Used by CLKSEL_GFX_FCLK */ +#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0 +#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0) + +/* Used by CM_CLKOUT_CTRL */ +#define AM33XX_CLKOUT2DIV_SHIFT 3 +#define AM33XX_CLKOUT2DIV_MASK (0x05 << 3) + +/* Used by CM_CLKOUT_CTRL */ +#define AM33XX_CLKOUT2EN_SHIFT 7 +#define AM33XX_CLKOUT2EN_MASK (1 << 7) + +/* Used by CM_CLKOUT_CTRL */ +#define AM33XX_CLKOUT2SOURCE_SHIFT 0 +#define AM33XX_CLKOUT2SOURCE_MASK (0x02 << 0) + +/* + * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK, + * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK, + * CLKSEL_TIMER7_CLK + */ +#define AM33XX_CLKSEL_SHIFT 0 +#define AM33XX_CLKSEL_MASK (0x01 << 0) + +/* + * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK, + * CM_CPTS_RFT_CLKSEL + */ +#define AM33XX_CLKSEL_0_0_SHIFT 0 +#define AM33XX_CLKSEL_0_0_MASK (1 << 0) + +#define AM33XX_CLKSEL_0_1_SHIFT 0 +#define AM33XX_CLKSEL_0_1_MASK (3 << 0) + +/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */ +#define AM33XX_CLKSEL_0_2_SHIFT 0 +#define AM33XX_CLKSEL_0_2_MASK (7 << 0) + +/* Used by CLKSEL_GFX_FCLK */ +#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1 +#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) + +/* + * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL, + * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL, + * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL, + * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL, + * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL, + * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL + */ +#define AM33XX_CLKTRCTRL_SHIFT 0 +#define AM33XX_CLKTRCTRL_MASK (0x3 << 0) + +/* + * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR, + * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU, + * CM_SSC_DELTAMSTEP_DPLL_PER + */ +#define AM33XX_DELTAMSTEP_SHIFT 0 +#define AM33XX_DELTAMSTEP_MASK (0x19 << 0) + +/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */ +#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23 +#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23) + +/* Used by CM_CLKDCOLDO_DPLL_PER */ +#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 +#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) + +/* Used by CM_CLKDCOLDO_DPLL_PER */ +#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12 +#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12) + +/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ +#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0 +#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0) + +/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */ +#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0 +#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x06 << 0) + +/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ +#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5 +#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) + +/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */ +#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7 +#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7) + +/* + * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU, + * CM_DIV_M2_DPLL_PER + */ +#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 +#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) + +/* + * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, + * CM_CLKSEL_DPLL_MPU + */ +#define AM33XX_DPLL_DIV_SHIFT 0 +#define AM33XX_DPLL_DIV_MASK (0x7f << 0) + +#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) + +/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */ +#define AM33XX_DPLL_DIV_0_7_SHIFT 0 +#define AM33XX_DPLL_DIV_0_7_MASK (0x07 << 0) + +/* + * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, + * CM_CLKMODE_DPLL_MPU + */ +#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) + +/* + * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER + */ +#define AM33XX_DPLL_EN_SHIFT 0 +#define AM33XX_DPLL_EN_MASK (0x7 << 0) + +/* + * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, + * CM_CLKMODE_DPLL_MPU + */ +#define AM33XX_DPLL_LPMODE_EN_SHIFT 10 +#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10) + +/* + * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, + * CM_CLKSEL_DPLL_MPU + */ +#define AM33XX_DPLL_MULT_SHIFT 8 +#define AM33XX_DPLL_MULT_MASK (0x7ff << 8) + +/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */ +#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8 +#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) + +/* + * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, + * CM_CLKMODE_DPLL_MPU + */ +#define AM33XX_DPLL_REGM4XEN_SHIFT 11 +#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11) + +/* Used by CM_CLKSEL_DPLL_PERIPH */ +#define AM33XX_DPLL_SD_DIV_SHIFT 24 +#define AM33XX_DPLL_SD_DIV_MASK (24, 31) + +/* + * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER + */ +#define AM33XX_DPLL_SSC_ACK_SHIFT 13 +#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13) + +/* + * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER + */ +#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 +#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) + +/* + * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER + */ +#define AM33XX_DPLL_SSC_EN_SHIFT 12 +#define AM33XX_DPLL_SSC_EN_MASK (1 << 12) + +/* Used by CM_DIV_M4_DPLL_CORE */ +#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 +#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) + +/* Used by CM_DIV_M4_DPLL_CORE */ +#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 +#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) + +/* Used by CM_DIV_M4_DPLL_CORE */ +#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 +#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) + +/* Used by CM_DIV_M4_DPLL_CORE */ +#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 +#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) + +/* Used by CM_DIV_M5_DPLL_CORE */ +#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 +#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) + +/* Used by CM_DIV_M5_DPLL_CORE */ +#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 +#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) + +/* Used by CM_DIV_M5_DPLL_CORE */ +#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 +#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) + +/* Used by CM_DIV_M5_DPLL_CORE */ +#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 +#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) + +/* Used by CM_DIV_M6_DPLL_CORE */ +#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 +#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x04 << 0) + +/* Used by CM_DIV_M6_DPLL_CORE */ +#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 +#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) + +/* Used by CM_DIV_M6_DPLL_CORE */ +#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 +#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) + +/* Used by CM_DIV_M6_DPLL_CORE */ +#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 +#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) + +/* + * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, + * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, + * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL, + * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL, + * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL, + * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL, + * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL, + * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL, + * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL, + * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL, + * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL, + * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL, + * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL, + * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL, + * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, + * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL, + * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL, + * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL, + * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL, + * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL, + * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL, + * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, + * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL, + * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL, + * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL, + * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL, + * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL, + * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL, + * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL, + * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL, + * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL + */ +#define AM33XX_IDLEST_SHIFT 16 +#define AM33XX_IDLEST_MASK (0x3 << 16) +#define AM33XX_IDLEST_VAL 0x3 + +/* Used by CM_MAC_CLKSEL */ +#define AM33XX_MII_CLK_SEL_SHIFT 2 +#define AM33XX_MII_CLK_SEL_MASK (1 << 2) + +/* + * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, + * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU, + * CM_SSC_MODFREQDIV_DPLL_PER + */ +#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8 +#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x10 << 8) + +/* + * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, + * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU, + * CM_SSC_MODFREQDIV_DPLL_PER + */ +#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0 +#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x06 << 0) + +/* + * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, + * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, + * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL, + * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL, + * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL, + * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL, + * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL, + * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL, + * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL, + * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL, + * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL, + * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL, + * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL, + * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL, + * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, + * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL, + * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL, + * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL, + * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL, + * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL, + * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL, + * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, + * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL, + * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL, + * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL, + * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL, + * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL, + * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL, + * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL, + * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, + * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, + * CM_CEFUSE_CEFUSE_CLKCTRL + */ +#define AM33XX_MODULEMODE_SHIFT 0 +#define AM33XX_MODULEMODE_MASK (0x3 << 0) + +/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ +#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 +#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30) + +/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ +#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 +#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19) + +/* Used by CM_WKUP_GPIO0_CLKCTRL */ +#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18) + +/* Used by CM_PER_GPIO1_CLKCTRL */ +#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18) + +/* Used by CM_PER_GPIO2_CLKCTRL */ +#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18) + +/* Used by CM_PER_GPIO3_CLKCTRL */ +#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18) + +/* Used by CM_PER_GPIO4_CLKCTRL */ +#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18) + +/* Used by CM_PER_GPIO5_CLKCTRL */ +#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18) + +/* Used by CM_PER_GPIO6_CLKCTRL */ +#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18 +#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18) + +/* + * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL, + * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL, + * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, + * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, + * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL, + * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL + */ +#define AM33XX_STBYST_SHIFT 18 +#define AM33XX_STBYST_MASK (1 << 18) + +/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ +#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 +#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x29 << 27) + +/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ +#define AM33XX_STM_PMD_CLKSEL_SHIFT 22 +#define AM33XX_STM_PMD_CLKSEL_MASK (0x23 << 22) + +/* + * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, + * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER + */ +#define AM33XX_ST_DPLL_CLK_SHIFT 0 +#define AM33XX_ST_DPLL_CLK_MASK (1 << 0) + +/* Used by CM_CLKDCOLDO_DPLL_PER */ +#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 +#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8) + +/* + * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU, + * CM_DIV_M2_DPLL_PER + */ +#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9 +#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9) + +/* Used by CM_DIV_M4_DPLL_CORE */ +#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9 +#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) + +/* Used by CM_DIV_M5_DPLL_CORE */ +#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9 +#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) + +/* Used by CM_DIV_M6_DPLL_CORE */ +#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9 +#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) + +/* + * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, + * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER + */ +#define AM33XX_ST_MN_BYPASS_SHIFT 8 +#define AM33XX_ST_MN_BYPASS_MASK (1 << 8) + +/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ +#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 +#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x26 << 24) + +/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ +#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 +#define AM33XX_TRC_PMD_CLKSEL_MASK (0x21 << 20) + +/* Used by CONTROL_SEC_CLK_CTRL */ +#define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4) +#endif diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c new file mode 100644 index 000000000000..13f56eafef03 --- /dev/null +++ b/arch/arm/mach-omap2/cm33xx.c @@ -0,0 +1,313 @@ +/* + * AM33XX CM functions + * + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * Vaibhav Hiremath <hvaibhav@ti.com> + * + * Reference taken from from OMAP4 cminst44xx.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/io.h> + +#include <plat/common.h> + +#include "cm.h" +#include "cm33xx.h" +#include "cm-regbits-34xx.h" +#include "cm-regbits-33xx.h" +#include "prm33xx.h" + +/* + * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: + * + * 0x0 func: Module is fully functional, including OCP + * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep + * abortion + * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if + * using separate functional clock + * 0x3 disabled: Module is disabled and cannot be accessed + * + */ +#define CLKCTRL_IDLEST_FUNCTIONAL 0x0 +#define CLKCTRL_IDLEST_INTRANSITION 0x1 +#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 +#define CLKCTRL_IDLEST_DISABLED 0x3 + +/* Private functions */ + +/* Read a register in a CM instance */ +static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx) +{ + return __raw_readl(cm_base + inst + idx); +} + +/* Write into a register in a CM */ +static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx) +{ + __raw_writel(val, cm_base + inst + idx); +} + +/* Read-modify-write a register in CM */ +static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) +{ + u32 v; + + v = am33xx_cm_read_reg(inst, idx); + v &= ~mask; + v |= bits; + am33xx_cm_write_reg(v, inst, idx); + + return v; +} + +static inline u32 am33xx_cm_set_reg_bits(u32 bits, s16 inst, s16 idx) +{ + return am33xx_cm_rmw_reg_bits(bits, bits, inst, idx); +} + +static inline u32 am33xx_cm_clear_reg_bits(u32 bits, s16 inst, s16 idx) +{ + return am33xx_cm_rmw_reg_bits(bits, 0x0, inst, idx); +} + +static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask) +{ + u32 v; + + v = am33xx_cm_read_reg(inst, idx); + v &= mask; + v >>= __ffs(mask); + + return v; +} + +/** + * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) + * + * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to + * bit 0. + */ +static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs) +{ + u32 v = am33xx_cm_read_reg(inst, clkctrl_offs); + v &= AM33XX_IDLEST_MASK; + v >>= AM33XX_IDLEST_SHIFT; + return v; +} + +/** + * _is_module_ready - can module registers be accessed without causing an abort? + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) + * + * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either + * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise. + */ +static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs) +{ + u32 v; + + v = _clkctrl_idlest(inst, cdoffs, clkctrl_offs); + + return (v == CLKCTRL_IDLEST_FUNCTIONAL || + v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false; +} + +/** + * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield + * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted) + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * + * @c must be the unshifted value for CLKTRCTRL - i.e., this function + * will handle the shift itself. + */ +static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs) +{ + u32 v; + + v = am33xx_cm_read_reg(inst, cdoffs); + v &= ~AM33XX_CLKTRCTRL_MASK; + v |= c << AM33XX_CLKTRCTRL_SHIFT; + am33xx_cm_write_reg(v, inst, cdoffs); +} + +/* Public functions */ + +/** + * am33xx_cm_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode? + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * + * Returns true if the clockdomain referred to by (@inst, @cdoffs) + * is in hardware-supervised idle mode, or 0 otherwise. + */ +bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs) +{ + u32 v; + + v = am33xx_cm_read_reg(inst, cdoffs); + v &= AM33XX_CLKTRCTRL_MASK; + v >>= AM33XX_CLKTRCTRL_SHIFT; + + return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false; +} + +/** + * am33xx_cm_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * + * Put a clockdomain referred to by (@inst, @cdoffs) into + * hardware-supervised idle mode. No return value. + */ +void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs) +{ + _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs); +} + +/** + * am33xx_cm_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * + * Put a clockdomain referred to by (@inst, @cdoffs) into + * software-supervised idle mode, i.e., controlled manually by the + * Linux OMAP clockdomain code. No return value. + */ +void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs) +{ + _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs); +} + +/** + * am33xx_cm_clkdm_force_sleep - try to put a clockdomain into idle + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * + * Put a clockdomain referred to by (@inst, @cdoffs) into idle + * No return value. + */ +void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs) +{ + _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs); +} + +/** + * am33xx_cm_clkdm_force_wakeup - try to take a clockdomain out of idle + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * + * Take a clockdomain referred to by (@inst, @cdoffs) out of idle, + * waking it up. No return value. + */ +void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs) +{ + _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs); +} + +/* + * + */ + +/** + * am33xx_cm_wait_module_ready - wait for a module to be in 'func' state + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) + * + * Wait for the module IDLEST to be functional. If the idle state is in any + * the non functional state (trans, idle or disabled), module and thus the + * sysconfig cannot be accessed and will probably lead to an "imprecise + * external abort" + */ +int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs) +{ + int i = 0; + + if (!clkctrl_offs) + return 0; + + omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs), + MAX_MODULE_READY_TIME, i); + + return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; +} + +/** + * am33xx_cm_wait_module_idle - wait for a module to be in 'disabled' + * state + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) + * + * Wait for the module IDLEST to be disabled. Some PRCM transition, + * like reset assertion or parent clock de-activation must wait the + * module to be fully disabled. + */ +int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs) +{ + int i = 0; + + if (!clkctrl_offs) + return 0; + + omap_test_timeout((_clkctrl_idlest(inst, cdoffs, clkctrl_offs) == + CLKCTRL_IDLEST_DISABLED), + MAX_MODULE_READY_TIME, i); + + return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; +} + +/** + * am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL + * @mode: Module mode (SW or HW) + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) + * + * No return value. + */ +void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs) +{ + u32 v; + + v = am33xx_cm_read_reg(inst, clkctrl_offs); + v &= ~AM33XX_MODULEMODE_MASK; + v |= mode << AM33XX_MODULEMODE_SHIFT; + am33xx_cm_write_reg(v, inst, clkctrl_offs); +} + +/** + * am33xx_cm_module_disable - Disable the module inside CLKCTRL + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) + * + * No return value. + */ +void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs) +{ + u32 v; + + v = am33xx_cm_read_reg(inst, clkctrl_offs); + v &= ~AM33XX_MODULEMODE_MASK; + am33xx_cm_write_reg(v, inst, clkctrl_offs); +} diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h new file mode 100644 index 000000000000..5fa0b62e1a79 --- /dev/null +++ b/arch/arm/mach-omap2/cm33xx.h @@ -0,0 +1,420 @@ +/* + * AM33XX CM offset macros + * + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * Vaibhav Hiremath <hvaibhav@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H +#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H + +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/io.h> + +#include "common.h" + +#include "cm.h" +#include "cm-regbits-33xx.h" +#include "cm33xx.h" + +/* CM base address */ +#define AM33XX_CM_BASE 0x44e00000 + +#define AM33XX_CM_REGADDR(inst, reg) \ + AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg)) + +/* CM instances */ +#define AM33XX_CM_PER_MOD 0x0000 +#define AM33XX_CM_WKUP_MOD 0x0400 +#define AM33XX_CM_DPLL_MOD 0x0500 +#define AM33XX_CM_MPU_MOD 0x0600 +#define AM33XX_CM_DEVICE_MOD 0x0700 +#define AM33XX_CM_RTC_MOD 0x0800 +#define AM33XX_CM_GFX_MOD 0x0900 +#define AM33XX_CM_CEFUSE_MOD 0x0A00 + +/* CM */ + +/* CM.PER_CM register offsets */ +#define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000 +#define AM33XX_CM_PER_L4LS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000) +#define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET 0x0004 +#define AM33XX_CM_PER_L3S_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004) +#define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET 0x0008 +#define AM33XX_CM_PER_L4FW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008) +#define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET 0x000c +#define AM33XX_CM_PER_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c) +#define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0014 +#define AM33XX_CM_PER_CPGMAC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014) +#define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET 0x0018 +#define AM33XX_CM_PER_LCDC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018) +#define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET 0x001c +#define AM33XX_CM_PER_USB0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c) +#define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET 0x0020 +#define AM33XX_CM_PER_MLB_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020) +#define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0024 +#define AM33XX_CM_PER_TPTC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024) +#define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0028 +#define AM33XX_CM_PER_EMIF_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028) +#define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x002c +#define AM33XX_CM_PER_OCMCRAM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c) +#define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0030 +#define AM33XX_CM_PER_GPMC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030) +#define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0034 +#define AM33XX_CM_PER_MCASP0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034) +#define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET 0x0038 +#define AM33XX_CM_PER_UART5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038) +#define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x003c +#define AM33XX_CM_PER_MMC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c) +#define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0040 +#define AM33XX_CM_PER_ELM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040) +#define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x0044 +#define AM33XX_CM_PER_I2C2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044) +#define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x0048 +#define AM33XX_CM_PER_I2C1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048) +#define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x004c +#define AM33XX_CM_PER_SPI0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c) +#define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0050 +#define AM33XX_CM_PER_SPI1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050) +#define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0054 +#define AM33XX_CM_PER_SPI2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054) +#define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0058 +#define AM33XX_CM_PER_SPI3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058) +#define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0060 +#define AM33XX_CM_PER_L4LS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060) +#define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET 0x0064 +#define AM33XX_CM_PER_L4FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064) +#define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0068 +#define AM33XX_CM_PER_MCASP1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068) +#define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET 0x006c +#define AM33XX_CM_PER_UART1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c) +#define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0070 +#define AM33XX_CM_PER_UART2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070) +#define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0074 +#define AM33XX_CM_PER_UART3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074) +#define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0078 +#define AM33XX_CM_PER_UART4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078) +#define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x007c +#define AM33XX_CM_PER_TIMER7_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c) +#define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0080 +#define AM33XX_CM_PER_TIMER2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080) +#define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0084 +#define AM33XX_CM_PER_TIMER3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084) +#define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0088 +#define AM33XX_CM_PER_TIMER4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088) +#define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET 0x008c +#define AM33XX_CM_PER_MCASP2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c) +#define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET 0x0090 +#define AM33XX_CM_PER_RNG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090) +#define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0094 +#define AM33XX_CM_PER_AES0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094) +#define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET 0x0098 +#define AM33XX_CM_PER_AES1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098) +#define AM33XX_CM_PER_DES_CLKCTRL_OFFSET 0x009c +#define AM33XX_CM_PER_DES_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c) +#define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x00a0 +#define AM33XX_CM_PER_SHA0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0) +#define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET 0x00a4 +#define AM33XX_CM_PER_PKA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4) +#define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET 0x00a8 +#define AM33XX_CM_PER_GPIO6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8) +#define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x00ac +#define AM33XX_CM_PER_GPIO1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac) +#define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x00b0 +#define AM33XX_CM_PER_GPIO2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0) +#define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x00b4 +#define AM33XX_CM_PER_GPIO3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4) +#define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x00b8 +#define AM33XX_CM_PER_GPIO4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8) +#define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x00bc +#define AM33XX_CM_PER_TPCC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc) +#define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x00c0 +#define AM33XX_CM_PER_DCAN0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0) +#define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x00c4 +#define AM33XX_CM_PER_DCAN1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4) +#define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x00cc +#define AM33XX_CM_PER_EPWMSS1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc) +#define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET 0x00d0 +#define AM33XX_CM_PER_EMIF_FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0) +#define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x00d4 +#define AM33XX_CM_PER_EPWMSS0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4) +#define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x00d8 +#define AM33XX_CM_PER_EPWMSS2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8) +#define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x00dc +#define AM33XX_CM_PER_L3_INSTR_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc) +#define AM33XX_CM_PER_L3_CLKCTRL_OFFSET 0x00e0 +#define AM33XX_CM_PER_L3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0) +#define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET 0x00e4 +#define AM33XX_CM_PER_IEEE5000_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4) +#define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x00e8 +#define AM33XX_CM_PER_PRUSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8) +#define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x00ec +#define AM33XX_CM_PER_TIMER5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec) +#define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x00f0 +#define AM33XX_CM_PER_TIMER6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0) +#define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x00f4 +#define AM33XX_CM_PER_MMC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4) +#define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x00f8 +#define AM33XX_CM_PER_MMC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8) +#define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x00fc +#define AM33XX_CM_PER_TPTC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc) +#define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0100 +#define AM33XX_CM_PER_TPTC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100) +#define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0104 +#define AM33XX_CM_PER_GPIO5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104) +#define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x010c +#define AM33XX_CM_PER_SPINLOCK_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c) +#define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x0110 +#define AM33XX_CM_PER_MAILBOX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110) +#define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET 0x011c +#define AM33XX_CM_PER_L4HS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c) +#define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x0120 +#define AM33XX_CM_PER_L4HS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120) +#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET 0x0124 +#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124) +#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET 0x0128 +#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128) +#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET 0x012c +#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c) +#define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET 0x0130 +#define AM33XX_CM_PER_OCPWP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130) +#define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET 0x0134 +#define AM33XX_CM_PER_MAILBOX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134) +#define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET 0x0140 +#define AM33XX_CM_PER_PRUSS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140) +#define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET 0x0144 +#define AM33XX_CM_PER_CPSW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144) +#define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET 0x0148 +#define AM33XX_CM_PER_LCDC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148) +#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET 0x014c +#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c) +#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET 0x0150 +#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150) + +/* CM.WKUP_CM register offsets */ +#define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET 0x0000 +#define AM33XX_CM_WKUP_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000) +#define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0004 +#define AM33XX_CM_WKUP_CONTROL_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004) +#define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0008 +#define AM33XX_CM_WKUP_GPIO0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008) +#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x000c +#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c) +#define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET 0x0010 +#define AM33XX_CM_WKUP_TIMER0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010) +#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET 0x0014 +#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014) +#define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET 0x0018 +#define AM33XX_CM_L3_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018) +#define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x001c +#define AM33XX_CM_AUTOIDLE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c) +#define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0020 +#define AM33XX_CM_IDLEST_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020) +#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0024 +#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024) +#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x0028 +#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028) +#define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x002c +#define AM33XX_CM_CLKSEL_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c) +#define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0030 +#define AM33XX_CM_AUTOIDLE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030) +#define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0034 +#define AM33XX_CM_IDLEST_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034) +#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x0038 +#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038) +#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x003c +#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c) +#define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x0040 +#define AM33XX_CM_CLKSEL_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040) +#define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET 0x0044 +#define AM33XX_CM_AUTOIDLE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044) +#define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET 0x0048 +#define AM33XX_CM_IDLEST_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048) +#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET 0x004c +#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c) +#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET 0x0050 +#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050) +#define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET 0x0054 +#define AM33XX_CM_CLKSEL_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054) +#define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0058 +#define AM33XX_CM_AUTOIDLE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058) +#define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET 0x005c +#define AM33XX_CM_IDLEST_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c) +#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0060 +#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060) +#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x0064 +#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064) +#define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x0068 +#define AM33XX_CM_CLKSEL_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068) +#define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x006c +#define AM33XX_CM_AUTOIDLE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c) +#define AM33XX_CM_IDLEST_DPLL_PER_OFFSET 0x0070 +#define AM33XX_CM_IDLEST_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070) +#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0074 +#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074) +#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0078 +#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078) +#define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET 0x007c +#define AM33XX_CM_CLKDCOLDO_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c) +#define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET 0x0080 +#define AM33XX_CM_DIV_M4_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080) +#define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET 0x0084 +#define AM33XX_CM_DIV_M5_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084) +#define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0088 +#define AM33XX_CM_CLKMODE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088) +#define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET 0x008c +#define AM33XX_CM_CLKMODE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c) +#define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0090 +#define AM33XX_CM_CLKMODE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090) +#define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0094 +#define AM33XX_CM_CLKMODE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094) +#define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET 0x0098 +#define AM33XX_CM_CLKMODE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098) +#define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET 0x009c +#define AM33XX_CM_CLKSEL_DPLL_PERIPH AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c) +#define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x00a0 +#define AM33XX_CM_DIV_M2_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0) +#define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET 0x00a4 +#define AM33XX_CM_DIV_M2_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4) +#define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x00a8 +#define AM33XX_CM_DIV_M2_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8) +#define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET 0x00ac +#define AM33XX_CM_DIV_M2_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac) +#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x00b0 +#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0) +#define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x00b4 +#define AM33XX_CM_WKUP_UART0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4) +#define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x00b8 +#define AM33XX_CM_WKUP_I2C0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8) +#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x00bc +#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc) +#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x00c0 +#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0) +#define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x00c4 +#define AM33XX_CM_WKUP_TIMER1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4) +#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x00c8 +#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8) +#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET 0x00cc +#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc) +#define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET 0x00d0 +#define AM33XX_CM_WKUP_WDT0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0) +#define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x00d4 +#define AM33XX_CM_WKUP_WDT1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4) +#define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET 0x00d8 +#define AM33XX_CM_DIV_M6_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8) + +/* CM.DPLL_CM register offsets */ +#define AM33XX_CLKSEL_TIMER7_CLK_OFFSET 0x0004 +#define AM33XX_CLKSEL_TIMER7_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004) +#define AM33XX_CLKSEL_TIMER2_CLK_OFFSET 0x0008 +#define AM33XX_CLKSEL_TIMER2_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008) +#define AM33XX_CLKSEL_TIMER3_CLK_OFFSET 0x000c +#define AM33XX_CLKSEL_TIMER3_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c) +#define AM33XX_CLKSEL_TIMER4_CLK_OFFSET 0x0010 +#define AM33XX_CLKSEL_TIMER4_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010) +#define AM33XX_CM_MAC_CLKSEL_OFFSET 0x0014 +#define AM33XX_CM_MAC_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014) +#define AM33XX_CLKSEL_TIMER5_CLK_OFFSET 0x0018 +#define AM33XX_CLKSEL_TIMER5_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018) +#define AM33XX_CLKSEL_TIMER6_CLK_OFFSET 0x001c +#define AM33XX_CLKSEL_TIMER6_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c) +#define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET 0x0020 +#define AM33XX_CM_CPTS_RFT_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020) +#define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET 0x0028 +#define AM33XX_CLKSEL_TIMER1MS_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028) +#define AM33XX_CLKSEL_GFX_FCLK_OFFSET 0x002c +#define AM33XX_CLKSEL_GFX_FCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c) +#define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET 0x0030 +#define AM33XX_CLKSEL_PRUSS_OCP_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030) +#define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET 0x0034 +#define AM33XX_CLKSEL_LCDC_PIXEL_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034) +#define AM33XX_CLKSEL_WDT1_CLK_OFFSET 0x0038 +#define AM33XX_CLKSEL_WDT1_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038) +#define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET 0x003c +#define AM33XX_CLKSEL_GPIO0_DBCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c) + +/* CM.MPU_CM register offsets */ +#define AM33XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000 +#define AM33XX_CM_MPU_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000) +#define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0004 +#define AM33XX_CM_MPU_MPU_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004) + +/* CM.DEVICE_CM register offsets */ +#define AM33XX_CM_CLKOUT_CTRL_OFFSET 0x0000 +#define AM33XX_CM_CLKOUT_CTRL AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000) + +/* CM.RTC_CM register offsets */ +#define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0000 +#define AM33XX_CM_RTC_RTC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000) +#define AM33XX_CM_RTC_CLKSTCTRL_OFFSET 0x0004 +#define AM33XX_CM_RTC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004) + +/* CM.GFX_CM register offsets */ +#define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET 0x0000 +#define AM33XX_CM_GFX_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000) +#define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0004 +#define AM33XX_CM_GFX_GFX_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004) +#define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET 0x0008 +#define AM33XX_CM_GFX_BITBLT_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008) +#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET 0x000c +#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1 AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c) +#define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET 0x0010 +#define AM33XX_CM_GFX_MMUCFG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010) +#define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET 0x0014 +#define AM33XX_CM_GFX_MMUDATA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014) + +/* CM.CEFUSE_CM register offsets */ +#define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 +#define AM33XX_CM_CEFUSE_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000) +#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 +#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020) + + +extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs); +extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs); +extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs); +extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs); +extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs); + +#ifdef CONFIG_SOC_AM33XX +extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, + u16 clkctrl_offs); +extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, + u16 clkctrl_offs); +extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs, + u16 clkctrl_offs); +extern int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, + u16 clkctrl_offs); +#else +static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, + u16 clkctrl_offs) +{ + return 0; +} +static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, + u16 clkctrl_offs) +{ +} +static inline void am33xx_cm_module_disable(u16 inst, s16 cdoffs, + u16 clkctrl_offs) +{ +} +static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, + u16 clkctrl_offs) +{ + return 0; +} +#endif + +#endif diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index be9dfd1abe60..5d99c1b2cb48 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -120,6 +120,7 @@ extern void omap2_init_common_infrastructure(void); extern struct sys_timer omap2_timer; extern struct sys_timer omap3_timer; extern struct sys_timer omap3_secure_timer; +extern struct sys_timer omap3_am33xx_timer; extern struct sys_timer omap4_timer; void omap2420_init_early(void); @@ -128,8 +129,10 @@ void omap3430_init_early(void); void omap35xx_init_early(void); void omap3630_init_early(void); void omap3_init_early(void); /* Do not use this one */ +void am33xx_init_early(void); void am35xx_init_early(void); void ti81xx_init_early(void); +void am33xx_init_early(void); void omap4430_init_early(void); void omap3_init_late(void); /* Do not use this one */ void omap4430_init_late(void); diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index fcc98f822d9d..5baf305386e9 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -21,6 +21,8 @@ #include <mach/ctrl_module_pad_core_44xx.h> #include <mach/ctrl_module_pad_wkup_44xx.h> +#include <plat/am33xx.h> + #ifndef __ASSEMBLY__ #define OMAP242X_CTRL_REGADDR(reg) \ OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) @@ -28,6 +30,8 @@ OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) #define OMAP343X_CTRL_REGADDR(reg) \ OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) +#define AM33XX_CTRL_REGADDR(reg) \ + AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) #else #define OMAP242X_CTRL_REGADDR(reg) \ OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) @@ -35,6 +39,8 @@ OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) #define OMAP343X_CTRL_REGADDR(reg) \ OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) +#define AM33XX_CTRL_REGADDR(reg) \ + AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) #endif /* __ASSEMBLY__ */ /* @@ -312,15 +318,15 @@ OMAP343X_SCRATCHPAD + reg) /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ -#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 -#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 -#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 -#define AM35XX_HECC_VBUSP_CLK_SHIFT 3 -#define AM35XX_USBOTG_FCLK_SHIFT 8 -#define AM35XX_CPGMAC_FCLK_SHIFT 9 -#define AM35XX_VPFE_FCLK_SHIFT 10 - -/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/ +#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 +#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 +#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 +#define AM35XX_HECC_VBUSP_CLK_SHIFT 3 +#define AM35XX_USBOTG_FCLK_SHIFT 8 +#define AM35XX_CPGMAC_FCLK_SHIFT 9 +#define AM35XX_VPFE_FCLK_SHIFT 10 + +/* AM35XX CONTROL_LVL_INTR_CLEAR bits */ #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) #define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) #define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) @@ -330,21 +336,22 @@ #define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) #define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) -/*AM35XX CONTROL_IP_SW_RESET bits*/ +/* AM35XX CONTROL_IP_SW_RESET bits */ #define AM35XX_USBOTGSS_SW_RST BIT(0) #define AM35XX_CPGMACSS_SW_RST BIT(1) #define AM35XX_VPFE_VBUSP_SW_RST BIT(2) #define AM35XX_HECC_SW_RST BIT(3) #define AM35XX_VPFE_PCLK_SW_RST BIT(4) -/* - * CONTROL AM33XX STATUS register - */ +/* AM33XX CONTROL_STATUS register */ #define AM33XX_CONTROL_STATUS 0x040 +#define AM33XX_CONTROL_SEC_CLK_CTRL 0x1bc -/* - * CONTROL OMAP STATUS register to identify OMAP3 features - */ +/* AM33XX CONTROL_STATUS bitfields (partial) */ +#define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22 +#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) + +/* CONTROL OMAP STATUS register to identify OMAP3 features */ #define OMAP3_CONTROL_OMAP_STATUS 0x044c #define OMAP3_SGX_SHIFT 13 diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index cdfc2a1f0e75..d7f844a99a7b 100644 --- a/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S @@ -72,6 +72,8 @@ omap_uart_lsr: .word 0 beq 82f @ configure UART2 cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different beq 83f @ configure UART3 + cmp \rp, #AM33XXUART1 @ AM33XX UART offsets different + beq 84f @ configure UART1 cmp \rp, #ZOOM_UART @ only on zoom2/3 beq 95f @ configure ZOOM_UART @@ -100,7 +102,9 @@ omap_uart_lsr: .word 0 b 98f 83: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE) b 98f - +84: ldr \rp, =AM33XX_UART1_BASE + and \rp, \rp, #0x00ffffff + b 97f 95: ldr \rp, =ZOOM_UART_BASE str \rp, [\tmp, #0] @ omap_uart_phys ldr \rp, =ZOOM_UART_VIRT @@ -109,6 +113,17 @@ omap_uart_lsr: .word 0 str \rp, [\tmp, #8] @ omap_uart_lsr b 10b + /* AM33XX: Store both phys and virt address for the uart */ +97: add \rp, \rp, #0x44000000 @ phys base + str \rp, [\tmp, #0] @ omap_uart_phys + sub \rp, \rp, #0x44000000 @ phys base + add \rp, \rp, #0xf9000000 @ virt base + str \rp, [\tmp, #4] @ omap_uart_virt + mov \rp, #(UART_LSR << OMAP_PORT_SHIFT) + str \rp, [\tmp, #8] @ omap_uart_lsr + + b 10b + /* Store both phys and virt address for the uart */ 98: add \rp, \rp, #0x48000000 @ phys base str \rp, [\tmp, #0] @ omap_uart_phys diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 8d014ba04abc..cb6c11cd8df9 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -477,6 +477,19 @@ void __init ti81xx_init_late(void) } #endif +#ifdef CONFIG_SOC_AM33XX +void __init am33xx_init_early(void) +{ + omap2_set_globals_am33xx(); + omap3xxx_check_revision(); + ti81xx_check_features(); + omap_common_init_early(); + am33xx_voltagedomains_init(); + am33xx_powerdomains_init(); + am33xx_clockdomains_init(); +} +#endif + #ifdef CONFIG_ARCH_OMAP4 void __init omap4430_init_early(void) { diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 6038a8c84b74..d5b34febd82d 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -280,7 +280,7 @@ int __init omap_intc_of_init(struct device_node *node, return 0; } -#ifdef CONFIG_ARCH_OMAP3 +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; void omap_intc_save_context(void) diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index 83eafd96ecaa..afad69c6ba6e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -68,7 +68,6 @@ static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = { struct omap_hwmod_class omap2xxx_timer_hwmod_class = { .name = "timer", .sysc = &omap2xxx_timer_sysc, - .rev = OMAP_TIMER_IP_VERSION_1, }; /* @@ -257,7 +256,6 @@ struct omap_hwmod omap2xxx_timer2_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, .class = &omap2xxx_timer_hwmod_class, }; @@ -276,7 +274,6 @@ struct omap_hwmod omap2xxx_timer3_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, .class = &omap2xxx_timer_hwmod_class, }; @@ -295,7 +292,6 @@ struct omap_hwmod omap2xxx_timer4_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, .class = &omap2xxx_timer_hwmod_class, }; @@ -314,7 +310,6 @@ struct omap_hwmod omap2xxx_timer5_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, .class = &omap2xxx_timer_hwmod_class, }; @@ -333,7 +328,6 @@ struct omap_hwmod omap2xxx_timer6_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, .class = &omap2xxx_timer_hwmod_class, }; @@ -352,7 +346,6 @@ struct omap_hwmod omap2xxx_timer7_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, .class = &omap2xxx_timer_hwmod_class, }; @@ -371,7 +364,6 @@ struct omap_hwmod omap2xxx_timer8_hwmod = { .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, .class = &omap2xxx_timer_hwmod_class, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 8379b8d7244a..6491e057d9ce 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -129,7 +129,6 @@ static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { .name = "timer", .sysc = &omap3xxx_timer_1ms_sysc, - .rev = OMAP_TIMER_IP_VERSION_1, }; static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { @@ -145,12 +144,11 @@ static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { .name = "timer", .sysc = &omap3xxx_timer_sysc, - .rev = OMAP_TIMER_IP_VERSION_1, }; /* secure timers dev attribute */ static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { - .timer_capability = OMAP_TIMER_SECURE, + .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE, }; /* always-on timers dev attribute */ @@ -195,7 +193,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, .class = &omap3xxx_timer_1ms_hwmod_class, }; @@ -213,7 +210,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, .class = &omap3xxx_timer_hwmod_class, }; @@ -231,7 +227,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, .class = &omap3xxx_timer_hwmod_class, }; @@ -249,7 +244,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, .class = &omap3xxx_timer_hwmod_class, }; @@ -267,7 +261,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, .class = &omap3xxx_timer_hwmod_class, }; @@ -285,7 +278,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = { .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, }, }, - .dev_attr = &capability_alwon_dev_attr, .class = &omap3xxx_timer_hwmod_class, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index d055b4725679..1b1d04141c3d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -2944,7 +2944,6 @@ static struct omap_hwmod omap44xx_timer2_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &capability_alwon_dev_attr, }; /* timer3 */ @@ -2966,7 +2965,6 @@ static struct omap_hwmod omap44xx_timer3_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &capability_alwon_dev_attr, }; /* timer4 */ @@ -2988,7 +2986,6 @@ static struct omap_hwmod omap44xx_timer4_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &capability_alwon_dev_attr, }; /* timer5 */ @@ -3010,7 +3007,6 @@ static struct omap_hwmod omap44xx_timer5_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &capability_alwon_dev_attr, }; /* timer6 */ @@ -3033,7 +3029,6 @@ static struct omap_hwmod omap44xx_timer6_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &capability_alwon_dev_attr, }; /* timer7 */ @@ -3055,7 +3050,6 @@ static struct omap_hwmod omap44xx_timer7_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .dev_attr = &capability_alwon_dev_attr, }; /* timer8 */ diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index 8f88d65c46ea..a8a95184243d 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -67,9 +67,9 @@ /* * Maximum number of clockdomains that can be associated with a powerdomain. - * CORE powerdomain on OMAP4 is the worst case + * PER powerdomain on AM33XX is the worst case */ -#define PWRDM_MAX_CLKDMS 9 +#define PWRDM_MAX_CLKDMS 11 /* XXX A completely arbitrary number. What is reasonable here? */ #define PWRDM_TRANSITION_BAILOUT 100000 @@ -92,6 +92,15 @@ struct powerdomain; * @pwrdm_clkdms: Clockdomains in this powerdomain * @node: list_head linking all powerdomains * @voltdm_node: list_head linking all powerdomains in a voltagedomain + * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs + * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs + * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield + * in @pwrstctrl_offs + * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs + * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs + * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs + * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield + * in @pwrstctrl_offs * @state: * @state_counter: * @timer: @@ -121,6 +130,14 @@ struct powerdomain { unsigned ret_logic_off_counter; unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; + const u8 pwrstctrl_offs; + const u8 pwrstst_offs; + const u32 logicretstate_mask; + const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS]; + const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS]; + const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS]; + const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS]; + #ifdef CONFIG_PM_DEBUG s64 timer; s64 state_timer[PWRDM_MAX_PWRSTS]; @@ -222,10 +239,12 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm); extern void omap242x_powerdomains_init(void); extern void omap243x_powerdomains_init(void); extern void omap3xxx_powerdomains_init(void); +extern void am33xx_powerdomains_init(void); extern void omap44xx_powerdomains_init(void); extern struct pwrdm_ops omap2_pwrdm_operations; extern struct pwrdm_ops omap3_pwrdm_operations; +extern struct pwrdm_ops am33xx_pwrdm_operations; extern struct pwrdm_ops omap4_pwrdm_operations; /* Common Internal functions used across OMAP rev's */ diff --git a/arch/arm/mach-omap2/powerdomain33xx.c b/arch/arm/mach-omap2/powerdomain33xx.c new file mode 100644 index 000000000000..67c5663899b6 --- /dev/null +++ b/arch/arm/mach-omap2/powerdomain33xx.c @@ -0,0 +1,229 @@ +/* + * AM33XX Powerdomain control + * + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * Derived from mach-omap2/powerdomain44xx.c written by Rajendra Nayak + * <rnayak@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/io.h> +#include <linux/errno.h> +#include <linux/delay.h> + +#include <plat/prcm.h> + +#include "powerdomain.h" +#include "prm33xx.h" +#include "prm-regbits-33xx.h" + + +static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) +{ + am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK, + (pwrst << OMAP_POWERSTATE_SHIFT), + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + return 0; +} + +static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + v &= OMAP_POWERSTATE_MASK; + v >>= OMAP_POWERSTATE_SHIFT; + + return v; +} + +static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); + v &= OMAP_POWERSTATEST_MASK; + v >>= OMAP_POWERSTATEST_SHIFT; + + return v; +} + +static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); + v &= AM33XX_LASTPOWERSTATEENTERED_MASK; + v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT; + + return v; +} + +static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) +{ + am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK, + (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT), + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + return 0; +} + +static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) +{ + am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK, + AM33XX_LASTPOWERSTATEENTERED_MASK, + pwrdm->prcm_offs, pwrdm->pwrstst_offs); + return 0; +} + +static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) +{ + u32 m; + + m = pwrdm->logicretstate_mask; + if (!m) + return -EINVAL; + + am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + + return 0; +} + +static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); + v &= AM33XX_LOGICSTATEST_MASK; + v >>= AM33XX_LOGICSTATEST_SHIFT; + + return v; +} + +static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm) +{ + u32 v, m; + + m = pwrdm->logicretstate_mask; + if (!m) + return -EINVAL; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + v &= m; + v >>= __ffs(m); + + return v; +} + +static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, + u8 pwrst) +{ + u32 m; + + m = pwrdm->mem_on_mask[bank]; + if (!m) + return -EINVAL; + + am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + + return 0; +} + +static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, + u8 pwrst) +{ + u32 m; + + m = pwrdm->mem_ret_mask[bank]; + if (!m) + return -EINVAL; + + am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + + return 0; +} + +static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) +{ + u32 m, v; + + m = pwrdm->mem_pwrst_mask[bank]; + if (!m) + return -EINVAL; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); + v &= m; + v >>= __ffs(m); + + return v; +} + +static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) +{ + u32 m, v; + + m = pwrdm->mem_retst_mask[bank]; + if (!m) + return -EINVAL; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + v &= m; + v >>= __ffs(m); + + return v; +} + +static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm) +{ + u32 c = 0; + + /* + * REVISIT: pwrdm_wait_transition() may be better implemented + * via a callback and a periodic timer check -- how long do we expect + * powerdomain transitions to take? + */ + + /* XXX Is this udelay() value meaningful? */ + while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs) + & OMAP_INTRANSITION_MASK) && + (c++ < PWRDM_TRANSITION_BAILOUT)) + udelay(1); + + if (c > PWRDM_TRANSITION_BAILOUT) { + pr_err("powerdomain: %s: waited too long to complete transition\n", + pwrdm->name); + return -EAGAIN; + } + + pr_debug("powerdomain: completed transition in %d loops\n", c); + + return 0; +} + +struct pwrdm_ops am33xx_pwrdm_operations = { + .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst, + .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst, + .pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst, + .pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst, + .pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst, + .pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst, + .pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst, + .pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst, + .pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange, + .pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst, + .pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst, + .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst, + .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst, + .pwrdm_wait_transition = am33xx_pwrdm_wait_transition, +}; diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c b/arch/arm/mach-omap2/powerdomains33xx_data.c new file mode 100644 index 000000000000..869adb82569e --- /dev/null +++ b/arch/arm/mach-omap2/powerdomains33xx_data.c @@ -0,0 +1,185 @@ +/* + * AM33XX Power domain data + * + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/init.h> + +#include "powerdomain.h" +#include "prcm-common.h" +#include "prm-regbits-33xx.h" +#include "prm33xx.h" + +static struct powerdomain gfx_33xx_pwrdm = { + .name = "gfx_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = AM33XX_PRM_GFX_MOD, + .pwrstctrl_offs = AM33XX_PM_GFX_PWRSTCTRL_OFFSET, + .pwrstst_offs = AM33XX_PM_GFX_PWRSTST_OFFSET, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, + .banks = 1, + .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK, + .mem_on_mask = { + [0] = AM33XX_GFX_MEM_ONSTATE_MASK, /* gfx_mem */ + }, + .mem_ret_mask = { + [0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */ + }, + .mem_pwrst_mask = { + [0] = AM33XX_GFX_MEM_STATEST_MASK, /* gfx_mem */ + }, + .mem_retst_mask = { + [0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */ + }, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* gfx_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_ON, /* gfx_mem */ + }, +}; + +static struct powerdomain rtc_33xx_pwrdm = { + .name = "rtc_pwrdm", + .voltdm = { .name = "rtc" }, + .prcm_offs = AM33XX_PRM_RTC_MOD, + .pwrstctrl_offs = AM33XX_PM_RTC_PWRSTCTRL_OFFSET, + .pwrstst_offs = AM33XX_PM_RTC_PWRSTST_OFFSET, + .pwrsts = PWRSTS_ON, + .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK, +}; + +static struct powerdomain wkup_33xx_pwrdm = { + .name = "wkup_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = AM33XX_PRM_WKUP_MOD, + .pwrstctrl_offs = AM33XX_PM_WKUP_PWRSTCTRL_OFFSET, + .pwrstst_offs = AM33XX_PM_WKUP_PWRSTST_OFFSET, + .pwrsts = PWRSTS_ON, + .logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK, +}; + +static struct powerdomain per_33xx_pwrdm = { + .name = "per_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = AM33XX_PRM_PER_MOD, + .pwrstctrl_offs = AM33XX_PM_PER_PWRSTCTRL_OFFSET, + .pwrstst_offs = AM33XX_PM_PER_PWRSTST_OFFSET, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, + .banks = 3, + .logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK, + .mem_on_mask = { + [0] = AM33XX_PRUSS_MEM_ONSTATE_MASK, /* pruss_mem */ + [1] = AM33XX_PER_MEM_ONSTATE_MASK, /* per_mem */ + [2] = AM33XX_RAM_MEM_ONSTATE_MASK, /* ram_mem */ + }, + .mem_ret_mask = { + [0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */ + [1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */ + [2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */ + }, + .mem_pwrst_mask = { + [0] = AM33XX_PRUSS_MEM_STATEST_MASK, /* pruss_mem */ + [1] = AM33XX_PER_MEM_STATEST_MASK, /* per_mem */ + [2] = AM33XX_RAM_MEM_STATEST_MASK, /* ram_mem */ + }, + .mem_retst_mask = { + [0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */ + [1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */ + [2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */ + }, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* pruss_mem */ + [1] = PWRSTS_OFF_RET, /* per_mem */ + [2] = PWRSTS_OFF_RET, /* ram_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_ON, /* pruss_mem */ + [1] = PWRSTS_ON, /* per_mem */ + [2] = PWRSTS_ON, /* ram_mem */ + }, +}; + +static struct powerdomain mpu_33xx_pwrdm = { + .name = "mpu_pwrdm", + .voltdm = { .name = "mpu" }, + .prcm_offs = AM33XX_PRM_MPU_MOD, + .pwrstctrl_offs = AM33XX_PM_MPU_PWRSTCTRL_OFFSET, + .pwrstst_offs = AM33XX_PM_MPU_PWRSTST_OFFSET, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, + .banks = 3, + .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK, + .mem_on_mask = { + [0] = AM33XX_MPU_L1_ONSTATE_MASK, /* mpu_l1 */ + [1] = AM33XX_MPU_L2_ONSTATE_MASK, /* mpu_l2 */ + [2] = AM33XX_MPU_RAM_ONSTATE_MASK, /* mpu_ram */ + }, + .mem_ret_mask = { + [0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */ + [1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */ + [2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */ + }, + .mem_pwrst_mask = { + [0] = AM33XX_MPU_L1_STATEST_MASK, /* mpu_l1 */ + [1] = AM33XX_MPU_L2_STATEST_MASK, /* mpu_l2 */ + [2] = AM33XX_MPU_RAM_STATEST_MASK, /* mpu_ram */ + }, + .mem_retst_mask = { + [0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */ + [1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */ + [2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */ + }, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* mpu_l1 */ + [1] = PWRSTS_OFF_RET, /* mpu_l2 */ + [2] = PWRSTS_OFF_RET, /* mpu_ram */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_ON, /* mpu_l1 */ + [1] = PWRSTS_ON, /* mpu_l2 */ + [2] = PWRSTS_ON, /* mpu_ram */ + }, +}; + +static struct powerdomain cefuse_33xx_pwrdm = { + .name = "cefuse_pwrdm", + .voltdm = { .name = "core" }, + .prcm_offs = AM33XX_PRM_CEFUSE_MOD, + .pwrstctrl_offs = AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET, + .pwrstst_offs = AM33XX_PM_CEFUSE_PWRSTST_OFFSET, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct powerdomain *powerdomains_am33xx[] __initdata = { + &gfx_33xx_pwrdm, + &rtc_33xx_pwrdm, + &wkup_33xx_pwrdm, + &per_33xx_pwrdm, + &mpu_33xx_pwrdm, + &cefuse_33xx_pwrdm, + NULL, +}; + +void __init am33xx_powerdomains_init(void) +{ + pwrdm_register_platform_funcs(&am33xx_pwrdm_operations); + pwrdm_register_pwrdms(powerdomains_am33xx); + pwrdm_complete_init(); +} diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h new file mode 100644 index 000000000000..0221b5c20e87 --- /dev/null +++ b/arch/arm/mach-omap2/prm-regbits-33xx.h @@ -0,0 +1,357 @@ +/* + * AM33XX PRM_XXX register bits + * + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H +#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H + +#include "prm.h" + +/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ +#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT 1 +#define AM33XX_ABBOFF_ACT_EXPORT_MASK (1 << 1) + +/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ +#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT 2 +#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) + +/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ +#define AM33XX_AIPOFF_SHIFT 8 +#define AM33XX_AIPOFF_MASK (1 << 8) + +/* Used by PM_WKUP_PWRSTST */ +#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT 17 +#define AM33XX_DEBUGSS_MEM_STATEST_MASK (0x3 << 17) + +/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ +#define AM33XX_DISABLE_RTA_EXPORT_SHIFT 0 +#define AM33XX_DISABLE_RTA_EXPORT_MASK (1 << 0) + +/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ +#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT 12 +#define AM33XX_DPLL_CORE_RECAL_EN_MASK (1 << 12) + +/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ +#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT 12 +#define AM33XX_DPLL_CORE_RECAL_ST_MASK (1 << 12) + +/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ +#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT 14 +#define AM33XX_DPLL_DDR_RECAL_EN_MASK (1 << 14) + +/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ +#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT 14 +#define AM33XX_DPLL_DDR_RECAL_ST_MASK (1 << 14) + +/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ +#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT 15 +#define AM33XX_DPLL_DISP_RECAL_EN_MASK (1 << 15) + +/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ +#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT 13 +#define AM33XX_DPLL_DISP_RECAL_ST_MASK (1 << 13) + +/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ +#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT 11 +#define AM33XX_DPLL_MPU_RECAL_EN_MASK (1 << 11) + +/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ +#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT 11 +#define AM33XX_DPLL_MPU_RECAL_ST_MASK (1 << 11) + +/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ +#define AM33XX_DPLL_PER_RECAL_EN_SHIFT 13 +#define AM33XX_DPLL_PER_RECAL_EN_MASK (1 << 13) + +/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ +#define AM33XX_DPLL_PER_RECAL_ST_SHIFT 15 +#define AM33XX_DPLL_PER_RECAL_ST_MASK (1 << 15) + +/* Used by RM_WKUP_RSTST */ +#define AM33XX_EMULATION_M3_RST_SHIFT 6 +#define AM33XX_EMULATION_M3_RST_MASK (1 << 6) + +/* Used by RM_MPU_RSTST */ +#define AM33XX_EMULATION_MPU_RST_SHIFT 5 +#define AM33XX_EMULATION_MPU_RST_MASK (1 << 5) + +/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ +#define AM33XX_ENFUNC1_EXPORT_SHIFT 3 +#define AM33XX_ENFUNC1_EXPORT_MASK (1 << 3) + +/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ +#define AM33XX_ENFUNC3_EXPORT_SHIFT 5 +#define AM33XX_ENFUNC3_EXPORT_MASK (1 << 5) + +/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ +#define AM33XX_ENFUNC4_SHIFT 6 +#define AM33XX_ENFUNC4_MASK (1 << 6) + +/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ +#define AM33XX_ENFUNC5_SHIFT 7 +#define AM33XX_ENFUNC5_MASK (1 << 7) + +/* Used by PRM_RSTST */ +#define AM33XX_EXTERNAL_WARM_RST_SHIFT 5 +#define AM33XX_EXTERNAL_WARM_RST_MASK (1 << 5) + +/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ +#define AM33XX_FORCEWKUP_EN_SHIFT 10 +#define AM33XX_FORCEWKUP_EN_MASK (1 << 10) + +/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ +#define AM33XX_FORCEWKUP_ST_SHIFT 10 +#define AM33XX_FORCEWKUP_ST_MASK (1 << 10) + +/* Used by PM_GFX_PWRSTCTRL */ +#define AM33XX_GFX_MEM_ONSTATE_SHIFT 17 +#define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17) + +/* Used by PM_GFX_PWRSTCTRL */ +#define AM33XX_GFX_MEM_RETSTATE_SHIFT 6 +#define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6) + +/* Used by PM_GFX_PWRSTST */ +#define AM33XX_GFX_MEM_STATEST_SHIFT 4 +#define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4) + +/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */ +#define AM33XX_GFX_RST_SHIFT 0 +#define AM33XX_GFX_RST_MASK (1 << 0) + +/* Used by PRM_RSTST */ +#define AM33XX_GLOBAL_COLD_RST_SHIFT 0 +#define AM33XX_GLOBAL_COLD_RST_MASK (1 << 0) + +/* Used by PRM_RSTST */ +#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT 1 +#define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) + +/* Used by RM_WKUP_RSTST */ +#define AM33XX_ICECRUSHER_M3_RST_SHIFT 7 +#define AM33XX_ICECRUSHER_M3_RST_MASK (1 << 7) + +/* Used by RM_MPU_RSTST */ +#define AM33XX_ICECRUSHER_MPU_RST_SHIFT 6 +#define AM33XX_ICECRUSHER_MPU_RST_MASK (1 << 6) + +/* Used by PRM_RSTST */ +#define AM33XX_ICEPICK_RST_SHIFT 9 +#define AM33XX_ICEPICK_RST_MASK (1 << 9) + +/* Used by RM_PER_RSTCTRL */ +#define AM33XX_PRUSS_LRST_SHIFT 1 +#define AM33XX_PRUSS_LRST_MASK (1 << 1) + +/* Used by PM_PER_PWRSTCTRL */ +#define AM33XX_PRUSS_MEM_ONSTATE_SHIFT 5 +#define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5) + +/* Used by PM_PER_PWRSTCTRL */ +#define AM33XX_PRUSS_MEM_RETSTATE_SHIFT 7 +#define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7) + +/* Used by PM_PER_PWRSTST */ +#define AM33XX_PRUSS_MEM_STATEST_SHIFT 23 +#define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23) + +/* + * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST, + * PM_WKUP_PWRSTST, PM_RTC_PWRSTST + */ +#define AM33XX_INTRANSITION_SHIFT 20 +#define AM33XX_INTRANSITION_MASK (1 << 20) + +/* Used by PM_CEFUSE_PWRSTST */ +#define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24 +#define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) + +/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */ +#define AM33XX_LOGICRETSTATE_SHIFT 2 +#define AM33XX_LOGICRETSTATE_MASK (1 << 2) + +/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */ +#define AM33XX_LOGICRETSTATE_3_3_SHIFT 3 +#define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3) + +/* + * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST, + * PM_WKUP_PWRSTST, PM_RTC_PWRSTST + */ +#define AM33XX_LOGICSTATEST_SHIFT 2 +#define AM33XX_LOGICSTATEST_MASK (1 << 2) + +/* + * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL, + * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL + */ +#define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4 +#define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4) + +/* Used by PM_MPU_PWRSTCTRL */ +#define AM33XX_MPU_L1_ONSTATE_SHIFT 18 +#define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18) + +/* Used by PM_MPU_PWRSTCTRL */ +#define AM33XX_MPU_L1_RETSTATE_SHIFT 22 +#define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22) + +/* Used by PM_MPU_PWRSTST */ +#define AM33XX_MPU_L1_STATEST_SHIFT 6 +#define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6) + +/* Used by PM_MPU_PWRSTCTRL */ +#define AM33XX_MPU_L2_ONSTATE_SHIFT 20 +#define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20) + +/* Used by PM_MPU_PWRSTCTRL */ +#define AM33XX_MPU_L2_RETSTATE_SHIFT 23 +#define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23) + +/* Used by PM_MPU_PWRSTST */ +#define AM33XX_MPU_L2_STATEST_SHIFT 8 +#define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8) + +/* Used by PM_MPU_PWRSTCTRL */ +#define AM33XX_MPU_RAM_ONSTATE_SHIFT 16 +#define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16) + +/* Used by PM_MPU_PWRSTCTRL */ +#define AM33XX_MPU_RAM_RETSTATE_SHIFT 24 +#define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24) + +/* Used by PM_MPU_PWRSTST */ +#define AM33XX_MPU_RAM_STATEST_SHIFT 4 +#define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4) + +/* Used by PRM_RSTST */ +#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT 2 +#define AM33XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2) + +/* Used by PRM_SRAM_COUNT */ +#define AM33XX_PCHARGECNT_VALUE_SHIFT 0 +#define AM33XX_PCHARGECNT_VALUE_MASK (0x3f << 0) + +/* Used by RM_PER_RSTCTRL */ +#define AM33XX_PCI_LRST_SHIFT 0 +#define AM33XX_PCI_LRST_MASK (1 << 0) + +/* Renamed from PCI_LRST Used by RM_PER_RSTST */ +#define AM33XX_PCI_LRST_5_5_SHIFT 5 +#define AM33XX_PCI_LRST_5_5_MASK (1 << 5) + +/* Used by PM_PER_PWRSTCTRL */ +#define AM33XX_PER_MEM_ONSTATE_SHIFT 25 +#define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25) + +/* Used by PM_PER_PWRSTCTRL */ +#define AM33XX_PER_MEM_RETSTATE_SHIFT 29 +#define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29) + +/* Used by PM_PER_PWRSTST */ +#define AM33XX_PER_MEM_STATEST_SHIFT 17 +#define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17) + +/* + * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL, + * PM_MPU_PWRSTCTRL + */ +#define AM33XX_POWERSTATE_SHIFT 0 +#define AM33XX_POWERSTATE_MASK (0x3 << 0) + +/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */ +#define AM33XX_POWERSTATEST_SHIFT 0 +#define AM33XX_POWERSTATEST_MASK (0x3 << 0) + +/* Used by PM_PER_PWRSTCTRL */ +#define AM33XX_RAM_MEM_ONSTATE_SHIFT 30 +#define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30) + +/* Used by PM_PER_PWRSTCTRL */ +#define AM33XX_RAM_MEM_RETSTATE_SHIFT 27 +#define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27) + +/* Used by PM_PER_PWRSTST */ +#define AM33XX_RAM_MEM_STATEST_SHIFT 21 +#define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21) + +/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ +#define AM33XX_RETMODE_ENABLE_SHIFT 0 +#define AM33XX_RETMODE_ENABLE_MASK (1 << 0) + +/* Used by REVISION_PRM */ +#define AM33XX_REV_SHIFT 0 +#define AM33XX_REV_MASK (0xff << 0) + +/* Used by PRM_RSTTIME */ +#define AM33XX_RSTTIME1_SHIFT 0 +#define AM33XX_RSTTIME1_MASK (0xff << 0) + +/* Used by PRM_RSTTIME */ +#define AM33XX_RSTTIME2_SHIFT 8 +#define AM33XX_RSTTIME2_MASK (0x1f << 8) + +/* Used by PRM_RSTCTRL */ +#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT 1 +#define AM33XX_RST_GLOBAL_COLD_SW_MASK (1 << 1) + +/* Used by PRM_RSTCTRL */ +#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT 0 +#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) + +/* Used by PRM_SRAM_COUNT */ +#define AM33XX_SLPCNT_VALUE_SHIFT 16 +#define AM33XX_SLPCNT_VALUE_MASK (0xff << 16) + +/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ +#define AM33XX_SRAMLDO_STATUS_SHIFT 8 +#define AM33XX_SRAMLDO_STATUS_MASK (1 << 8) + +/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ +#define AM33XX_SRAM_IN_TRANSITION_SHIFT 9 +#define AM33XX_SRAM_IN_TRANSITION_MASK (1 << 9) + +/* Used by PRM_SRAM_COUNT */ +#define AM33XX_STARTUP_COUNT_SHIFT 24 +#define AM33XX_STARTUP_COUNT_MASK (0xff << 24) + +/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ +#define AM33XX_TRANSITION_EN_SHIFT 8 +#define AM33XX_TRANSITION_EN_MASK (1 << 8) + +/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ +#define AM33XX_TRANSITION_ST_SHIFT 8 +#define AM33XX_TRANSITION_ST_MASK (1 << 8) + +/* Used by PRM_SRAM_COUNT */ +#define AM33XX_VSETUPCNT_VALUE_SHIFT 8 +#define AM33XX_VSETUPCNT_VALUE_MASK (0xff << 8) + +/* Used by PRM_RSTST */ +#define AM33XX_WDT0_RST_SHIFT 3 +#define AM33XX_WDT0_RST_MASK (1 << 3) + +/* Used by PRM_RSTST */ +#define AM33XX_WDT1_RST_SHIFT 4 +#define AM33XX_WDT1_RST_MASK (1 << 4) + +/* Used by RM_WKUP_RSTCTRL */ +#define AM33XX_WKUP_M3_LRST_SHIFT 3 +#define AM33XX_WKUP_M3_LRST_MASK (1 << 3) + +/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */ +#define AM33XX_WKUP_M3_LRST_5_5_SHIFT 5 +#define AM33XX_WKUP_M3_LRST_5_5_MASK (1 << 5) + +#endif diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c new file mode 100644 index 000000000000..e7dbb6cf1255 --- /dev/null +++ b/arch/arm/mach-omap2/prm33xx.c @@ -0,0 +1,135 @@ +/* + * AM33XX PRM functions + * + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/io.h> + +#include <plat/common.h> + +#include "common.h" +#include "prm33xx.h" +#include "prm-regbits-33xx.h" + +/* Read a register in a PRM instance */ +u32 am33xx_prm_read_reg(s16 inst, u16 idx) +{ + return __raw_readl(prm_base + inst + idx); +} + +/* Write into a register in a PRM instance */ +void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx) +{ + __raw_writel(val, prm_base + inst + idx); +} + +/* Read-modify-write a register in PRM. Caller must lock */ +u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) +{ + u32 v; + + v = am33xx_prm_read_reg(inst, idx); + v &= ~mask; + v |= bits; + am33xx_prm_write_reg(v, inst, idx); + + return v; +} + +/** + * am33xx_prm_is_hardreset_asserted - read the HW reset line state of + * submodules contained in the hwmod module + * @shift: register bit shift corresponding to the reset line to check + * @inst: CM instance register offset (*_INST macro) + * @rstctrl_offs: RM_RSTCTRL register address offset for this module + * + * Returns 1 if the (sub)module hardreset line is currently asserted, + * 0 if the (sub)module hardreset line is not currently asserted, or + * -EINVAL upon parameter error. + */ +int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs) +{ + u32 v; + + v = am33xx_prm_read_reg(inst, rstctrl_offs); + v &= 1 << shift; + v >>= shift; + + return v; +} + +/** + * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule + * @shift: register bit shift corresponding to the reset line to assert + * @inst: CM instance register offset (*_INST macro) + * @rstctrl_reg: RM_RSTCTRL register address for this module + * + * Some IPs like dsp, ipu or iva contain processors that require an HW + * reset line to be asserted / deasserted in order to fully enable the + * IP. These modules may have multiple hard-reset lines that reset + * different 'submodules' inside the IP block. This function will + * place the submodule into reset. Returns 0 upon success or -EINVAL + * upon an argument error. + */ +int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs) +{ + u32 mask = 1 << shift; + + am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs); + + return 0; +} + +/** + * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and + * wait + * @shift: register bit shift corresponding to the reset line to deassert + * @inst: CM instance register offset (*_INST macro) + * @rstctrl_reg: RM_RSTCTRL register address for this module + * @rstst_reg: RM_RSTST register address for this module + * + * Some IPs like dsp, ipu or iva contain processors that require an HW + * reset line to be asserted / deasserted in order to fully enable the + * IP. These modules may have multiple hard-reset lines that reset + * different 'submodules' inside the IP block. This function will + * take the submodule out of reset and wait until the PRCM indicates + * that the reset has completed before returning. Returns 0 upon success or + * -EINVAL upon an argument error, -EEXIST if the submodule was already out + * of reset, or -EBUSY if the submodule did not exit reset promptly. + */ +int am33xx_prm_deassert_hardreset(u8 shift, s16 inst, + u16 rstctrl_offs, u16 rstst_offs) +{ + int c; + u32 mask = 1 << shift; + + /* Check the current status to avoid de-asserting the line twice */ + if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0) + return -EEXIST; + + /* Clear the reset status by writing 1 to the status bit */ + am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs); + /* de-assert the reset control line */ + am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs); + /* wait the status to be set */ + + omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst, + rstst_offs), + MAX_MODULE_HARDRESET_WAIT, c); + + return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; +} diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h new file mode 100644 index 000000000000..3f25c563a821 --- /dev/null +++ b/arch/arm/mach-omap2/prm33xx.h @@ -0,0 +1,129 @@ +/* + * AM33XX PRM instance offset macros + * + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H +#define __ARCH_ARM_MACH_OMAP2_PRM33XX_H + +#include "prcm-common.h" +#include "prm.h" + +#define AM33XX_PRM_BASE 0x44E00000 + +#define AM33XX_PRM_REGADDR(inst, reg) \ + AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg)) + + +/* PRM instances */ +#define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00 +#define AM33XX_PRM_PER_MOD 0x0C00 +#define AM33XX_PRM_WKUP_MOD 0x0D00 +#define AM33XX_PRM_MPU_MOD 0x0E00 +#define AM33XX_PRM_DEVICE_MOD 0x0F00 +#define AM33XX_PRM_RTC_MOD 0x1000 +#define AM33XX_PRM_GFX_MOD 0x1100 +#define AM33XX_PRM_CEFUSE_MOD 0x1200 + +/* PRM */ + +/* PRM.OCP_SOCKET_PRM register offsets */ +#define AM33XX_REVISION_PRM_OFFSET 0x0000 +#define AM33XX_REVISION_PRM AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000) +#define AM33XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004 +#define AM33XX_PRM_IRQSTATUS_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004) +#define AM33XX_PRM_IRQENABLE_MPU_OFFSET 0x0008 +#define AM33XX_PRM_IRQENABLE_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008) +#define AM33XX_PRM_IRQSTATUS_M3_OFFSET 0x000c +#define AM33XX_PRM_IRQSTATUS_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c) +#define AM33XX_PRM_IRQENABLE_M3_OFFSET 0x0010 +#define AM33XX_PRM_IRQENABLE_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010) + +/* PRM.PER_PRM register offsets */ +#define AM33XX_RM_PER_RSTCTRL_OFFSET 0x0000 +#define AM33XX_RM_PER_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000) +#define AM33XX_RM_PER_RSTST_OFFSET 0x0004 +#define AM33XX_RM_PER_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004) +#define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008 +#define AM33XX_PM_PER_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008) +#define AM33XX_PM_PER_PWRSTCTRL_OFFSET 0x000c +#define AM33XX_PM_PER_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c) + +/* PRM.WKUP_PRM register offsets */ +#define AM33XX_RM_WKUP_RSTCTRL_OFFSET 0x0000 +#define AM33XX_RM_WKUP_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000) +#define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET 0x0004 +#define AM33XX_PM_WKUP_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004) +#define AM33XX_PM_WKUP_PWRSTST_OFFSET 0x0008 +#define AM33XX_PM_WKUP_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008) +#define AM33XX_RM_WKUP_RSTST_OFFSET 0x000c +#define AM33XX_RM_WKUP_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c) + +/* PRM.MPU_PRM register offsets */ +#define AM33XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 +#define AM33XX_PM_MPU_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000) +#define AM33XX_PM_MPU_PWRSTST_OFFSET 0x0004 +#define AM33XX_PM_MPU_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004) +#define AM33XX_RM_MPU_RSTST_OFFSET 0x0008 +#define AM33XX_RM_MPU_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008) + +/* PRM.DEVICE_PRM register offsets */ +#define AM33XX_PRM_RSTCTRL_OFFSET 0x0000 +#define AM33XX_PRM_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000) +#define AM33XX_PRM_RSTTIME_OFFSET 0x0004 +#define AM33XX_PRM_RSTTIME AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004) +#define AM33XX_PRM_RSTST_OFFSET 0x0008 +#define AM33XX_PRM_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008) +#define AM33XX_PRM_SRAM_COUNT_OFFSET 0x000c +#define AM33XX_PRM_SRAM_COUNT AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c) +#define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x0010 +#define AM33XX_PRM_LDO_SRAM_CORE_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010) +#define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x0014 +#define AM33XX_PRM_LDO_SRAM_CORE_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014) +#define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x0018 +#define AM33XX_PRM_LDO_SRAM_MPU_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018) +#define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x001c +#define AM33XX_PRM_LDO_SRAM_MPU_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c) + +/* PRM.RTC_PRM register offsets */ +#define AM33XX_PM_RTC_PWRSTCTRL_OFFSET 0x0000 +#define AM33XX_PM_RTC_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0000) +#define AM33XX_PM_RTC_PWRSTST_OFFSET 0x0004 +#define AM33XX_PM_RTC_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0004) + +/* PRM.GFX_PRM register offsets */ +#define AM33XX_PM_GFX_PWRSTCTRL_OFFSET 0x0000 +#define AM33XX_PM_GFX_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000) +#define AM33XX_RM_GFX_RSTCTRL_OFFSET 0x0004 +#define AM33XX_RM_GFX_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004) +#define AM33XX_PM_GFX_PWRSTST_OFFSET 0x0010 +#define AM33XX_PM_GFX_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010) +#define AM33XX_RM_GFX_RSTST_OFFSET 0x0014 +#define AM33XX_RM_GFX_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014) + +/* PRM.CEFUSE_PRM register offsets */ +#define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000 +#define AM33XX_PM_CEFUSE_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0000) +#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004 +#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004) + +extern u32 am33xx_prm_read_reg(s16 inst, u16 idx); +extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx); +extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); +extern void am33xx_prm_global_warm_sw_reset(void); +extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, + u16 rstctrl_offs); +extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs); +extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst, + u16 rstctrl_offs, u16 rstst_offs); +#endif diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 840929bd9dae..b5b5d92acd9d 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -69,11 +69,6 @@ #define OMAP3_SECURE_TIMER 1 #endif -/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ -#define MAX_GPTIMER_ID 12 - -static u32 sys_timer_reserved; - /* Clockevent code */ static struct omap_dm_timer clkev; @@ -180,7 +175,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, omap_hwmod_enable(oh); - sys_timer_reserved |= (1 << (gptimer_id - 1)); + if (omap_dm_timer_reserve_systimer(gptimer_id)) + return -ENODEV; if (gptimer_id != 12) { struct clk *src; @@ -368,6 +364,11 @@ OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE, OMAP_SYS_TIMER(3_secure) #endif +#ifdef CONFIG_SOC_AM33XX +OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE) +OMAP_SYS_TIMER(3_am33xx) +#endif + #ifdef CONFIG_ARCH_OMAP4 #ifdef CONFIG_LOCAL_TIMERS static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, @@ -394,66 +395,6 @@ OMAP_SYS_TIMER(4) #endif /** - * omap2_dm_timer_set_src - change the timer input clock source - * @pdev: timer platform device pointer - * @source: array index of parent clock source - */ -static int omap2_dm_timer_set_src(struct platform_device *pdev, int source) -{ - int ret; - struct dmtimer_platform_data *pdata = pdev->dev.platform_data; - struct clk *fclk, *parent; - char *parent_name = NULL; - - fclk = clk_get(&pdev->dev, "fck"); - if (IS_ERR_OR_NULL(fclk)) { - dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n", - __func__, __LINE__); - return -EINVAL; - } - - switch (source) { - case OMAP_TIMER_SRC_SYS_CLK: - parent_name = "sys_ck"; - break; - - case OMAP_TIMER_SRC_32_KHZ: - parent_name = "32k_ck"; - break; - - case OMAP_TIMER_SRC_EXT_CLK: - if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) { - parent_name = "alt_ck"; - break; - } - dev_err(&pdev->dev, "%s: %d: invalid clk src.\n", - __func__, __LINE__); - clk_put(fclk); - return -EINVAL; - } - - parent = clk_get(&pdev->dev, parent_name); - if (IS_ERR_OR_NULL(parent)) { - dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n", - __func__, __LINE__, parent_name); - clk_put(fclk); - return -EINVAL; - } - - ret = clk_set_parent(fclk, parent); - if (IS_ERR_VALUE(ret)) { - dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n", - __func__, parent_name); - ret = -EINVAL; - } - - clk_put(parent); - clk_put(fclk); - - return ret; -} - -/** * omap_timer_init - build and register timer device with an * associated timer hwmod * @oh: timer hwmod pointer to be used to build timer device @@ -473,7 +414,6 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) struct dmtimer_platform_data *pdata; struct platform_device *pdev; struct omap_timer_capability_dev_attr *timer_dev_attr; - struct powerdomain *pwrdm; pr_debug("%s: %s\n", __func__, oh->name); @@ -501,18 +441,9 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) */ sscanf(oh->name, "timer%2d", &id); - pdata->set_timer_src = omap2_dm_timer_set_src; - pdata->timer_ip_version = oh->class->rev; + if (timer_dev_attr) + pdata->timer_capability = timer_dev_attr->timer_capability; - /* Mark clocksource and clockevent timers as reserved */ - if ((sys_timer_reserved >> (id - 1)) & 0x1) - pdata->reserved = 1; - - pwrdm = omap_hwmod_get_pwrdm(oh); - pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm); -#ifdef CONFIG_PM - pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; -#endif pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), NULL, 0, 0); diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h index 16a1b092cf36..a7c43c1042be 100644 --- a/arch/arm/mach-omap2/voltage.h +++ b/arch/arm/mach-omap2/voltage.h @@ -156,6 +156,7 @@ int omap_voltage_late_init(void); extern void omap2xxx_voltagedomains_init(void); extern void omap3xxx_voltagedomains_init(void); +extern void am33xx_voltagedomains_init(void); extern void omap44xx_voltagedomains_init(void); struct voltagedomain *voltdm_lookup(const char *name); diff --git a/arch/arm/mach-omap2/voltagedomains33xx_data.c b/arch/arm/mach-omap2/voltagedomains33xx_data.c new file mode 100644 index 000000000000..965458dc0cb9 --- /dev/null +++ b/arch/arm/mach-omap2/voltagedomains33xx_data.c @@ -0,0 +1,43 @@ +/* + * AM33XX voltage domain data + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/init.h> + +#include "voltage.h" + +static struct voltagedomain am33xx_voltdm_mpu = { + .name = "mpu", +}; + +static struct voltagedomain am33xx_voltdm_core = { + .name = "core", +}; + +static struct voltagedomain am33xx_voltdm_rtc = { + .name = "rtc", +}; + +static struct voltagedomain *voltagedomains_am33xx[] __initdata = { + &am33xx_voltdm_mpu, + &am33xx_voltdm_core, + &am33xx_voltdm_rtc, + NULL, +}; + +void __init am33xx_voltagedomains_init(void) +{ + voltdm_init(voltagedomains_am33xx); +} diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index 9e37026ef9dd..9bd135531d76 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -779,6 +779,7 @@ DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva") .init_irq = r8a7740_init_irq, .handle_irq = shmobile_handle_irq_intc, .init_machine = eva_init, + .init_late = shmobile_init_late, .timer = &shmobile_timer, .dt_compat = eva_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c index 7bc5e7d39f9b..6a33cf393428 100644 --- a/arch/arm/mach-shmobile/board-kzm9d.c +++ b/arch/arm/mach-shmobile/board-kzm9d.c @@ -80,6 +80,7 @@ DT_MACHINE_START(KZM9D_DT, "kzm9d") .init_irq = emev2_init_irq, .handle_irq = gic_handle_irq, .init_machine = kzm9d_add_standard_devices, + .init_late = shmobile_init_late, .timer = &shmobile_timer, .dt_compat = kzm9d_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index d8e33b682832..c0ae815e7beb 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c @@ -455,6 +455,7 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g") .init_irq = sh73a0_init_irq, .handle_irq = gic_handle_irq, .init_machine = kzm_init, + .init_late = shmobile_init_late, .timer = &shmobile_timer, .dt_compat = kzm9g_boards_compat_dt, MACHINE_END diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index b577f7c44678..150122a44630 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c @@ -1512,6 +1512,9 @@ static void __init mackerel_init(void) gpio_request(GPIO_FN_SDHID0_1, NULL); gpio_request(GPIO_FN_SDHID0_0, NULL); + /* SDHI0 PORT172 card-detect IRQ26 */ + gpio_request(GPIO_FN_IRQ26_172, NULL); + #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) /* enable SDHI1 */ gpio_request(GPIO_FN_SDHICMD1, NULL); diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index 472d1f5361e5..3946c4ba2aa8 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -475,9 +475,9 @@ static struct clk *late_main_clks[] = { enum { MSTP001, MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100, - MSTP219, + MSTP219, MSTP218, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, - MSTP331, MSTP329, MSTP325, MSTP323, MSTP318, + MSTP331, MSTP329, MSTP325, MSTP323, MSTP314, MSTP313, MSTP312, MSTP311, MSTP303, MSTP302, MSTP301, MSTP300, MSTP411, MSTP410, MSTP403, @@ -497,6 +497,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */ [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */ + [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */ [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */ [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */ [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */ @@ -508,7 +509,6 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */ [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */ [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */ - [MSTP318] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* SY-DMAC */ [MSTP314] = MSTP(&div6_clks[DIV6_SDHI0], SMSTPCR3, 14, 0), /* SDHI0 */ [MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */ [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */ @@ -552,6 +552,7 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */ CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */ CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */ + CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* SY-DMAC */ CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */ CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */ CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ @@ -563,7 +564,6 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */ CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */ CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */ - CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP318]), /* SY-DMAC */ CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */ diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c index 550b23df4fd4..f04fad4ec4fb 100644 --- a/arch/arm/mach-shmobile/intc-r8a7779.c +++ b/arch/arm/mach-shmobile/intc-r8a7779.c @@ -35,6 +35,9 @@ #define INT2SMSKCR3 0xfe7822ac #define INT2SMSKCR4 0xfe7822b0 +#define INT2NTSR0 0xfe700060 +#define INT2NTSR1 0xfe700064 + static int r8a7779_set_wake(struct irq_data *data, unsigned int on) { return 0; /* always allow wakeup */ @@ -49,6 +52,10 @@ void __init r8a7779_init_irq(void) gic_init(0, 29, gic_dist_base, gic_cpu_base); gic_arch_extn.irq_set_wake = r8a7779_set_wake; + /* route all interrupts to ARM */ + __raw_writel(0xffffffff, INT2NTSR0); + __raw_writel(0x3fffffff, INT2NTSR1); + /* unmask all known interrupts in INTCS2 */ __raw_writel(0xfffffff0, INT2SMSKCR0); __raw_writel(0xfff7ffff, INT2SMSKCR1); diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c index bacdd667e3b1..e859fcdb3d58 100644 --- a/arch/arm/mach-shmobile/platsmp.c +++ b/arch/arm/mach-shmobile/platsmp.c @@ -25,7 +25,12 @@ #define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2() || \ of_machine_is_compatible("renesas,sh73a0")) #define is_r8a7779() machine_is_marzen() + +#ifdef CONFIG_ARCH_EMEV2 #define is_emev2() of_machine_is_compatible("renesas,emev2") +#else +#define is_emev2() (0) +#endif static unsigned int __init shmobile_smp_get_core_count(void) { diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 6a4bd582c028..fafce9ce8218 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -484,7 +484,7 @@ static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = { }, }; -#define SH7372_CHCLR 0x220 +#define SH7372_CHCLR (0x220 - 0x20) static const struct sh_dmae_channel sh7372_dmae_channels[] = { { diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index d766e4256b74..4044abcf6f9d 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -1067,7 +1067,7 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, gfp_t return NULL; while (count) { - int j, order = __ffs(count); + int j, order = __fls(count); pages[i] = alloc_pages(gfp | __GFP_NOWARN, order); while (!pages[i] && order) diff --git a/arch/arm/plat-mxc/include/mach/mx2_cam.h b/arch/arm/plat-mxc/include/mach/mx2_cam.h index 7ded6f1f74bc..3c080a32dbf5 100644 --- a/arch/arm/plat-mxc/include/mach/mx2_cam.h +++ b/arch/arm/plat-mxc/include/mach/mx2_cam.h @@ -23,6 +23,7 @@ #ifndef __MACH_MX2_CAM_H_ #define __MACH_MX2_CAM_H_ +#define MX2_CAMERA_SWAP16 (1 << 0) #define MX2_CAMERA_EXT_VSYNC (1 << 1) #define MX2_CAMERA_CCIR (1 << 2) #define MX2_CAMERA_CCIR_INTERLACE (1 << 3) @@ -30,6 +31,7 @@ #define MX2_CAMERA_GATED_CLOCK (1 << 5) #define MX2_CAMERA_INV_DATA (1 << 6) #define MX2_CAMERA_PCLK_SAMPLE_RISING (1 << 7) +#define MX2_CAMERA_PACK_DIR_MSB (1 << 8) /** * struct mx2_camera_platform_data - optional platform data for mx2_camera diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 3b0cfeb33d05..54ed4e6e429e 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -42,9 +42,11 @@ #include <linux/pm_runtime.h> #include <plat/dmtimer.h> +#include <plat/omap-pm.h> #include <mach/hardware.h> +static u32 omap_reserved_systimers; static LIST_HEAD(omap_timer_list); static DEFINE_SPINLOCK(dm_timer_lock); @@ -133,17 +135,22 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer) int omap_dm_timer_prepare(struct omap_dm_timer *timer) { - struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data; int ret; - timer->fclk = clk_get(&timer->pdev->dev, "fck"); - if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) { - timer->fclk = NULL; - dev_err(&timer->pdev->dev, ": No fclk handle.\n"); - return -EINVAL; + /* + * FIXME: OMAP1 devices do not use the clock framework for dmtimers so + * do not call clk_get() for these devices. + */ + if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { + timer->fclk = clk_get(&timer->pdev->dev, "fck"); + if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) { + timer->fclk = NULL; + dev_err(&timer->pdev->dev, ": No fclk handle.\n"); + return -EINVAL; + } } - if (pdata->needs_manual_reset) + if (timer->capability & OMAP_TIMER_NEEDS_RESET) omap_dm_timer_reset(timer); ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); @@ -152,6 +159,21 @@ int omap_dm_timer_prepare(struct omap_dm_timer *timer) return ret; } +static inline u32 omap_dm_timer_reserved_systimer(int id) +{ + return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; +} + +int omap_dm_timer_reserve_systimer(int id) +{ + if (omap_dm_timer_reserved_systimer(id)) + return -ENODEV; + + omap_reserved_systimers |= (1 << (id - 1)); + + return 0; +} + struct omap_dm_timer *omap_dm_timer_request(void) { struct omap_dm_timer *timer = NULL, *t; @@ -325,10 +347,9 @@ int omap_dm_timer_start(struct omap_dm_timer *timer) omap_dm_timer_enable(timer); - if (timer->loses_context) { - u32 ctx_loss_cnt_after = - timer->get_context_loss_count(&timer->pdev->dev); - if (ctx_loss_cnt_after != timer->ctx_loss_count) + if (!(timer->capability & OMAP_TIMER_ALWON)) { + if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) != + timer->ctx_loss_count) omap_timer_restore_context(timer); } @@ -347,20 +368,18 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_start); int omap_dm_timer_stop(struct omap_dm_timer *timer) { unsigned long rate = 0; - struct dmtimer_platform_data *pdata; if (unlikely(!timer)) return -EINVAL; - pdata = timer->pdev->dev.platform_data; - if (!pdata->needs_manual_reset) + if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) rate = clk_get_rate(timer->fclk); __omap_dm_timer_stop(timer, timer->posted, rate); - if (timer->loses_context && timer->get_context_loss_count) + if (!(timer->capability & OMAP_TIMER_ALWON)) timer->ctx_loss_count = - timer->get_context_loss_count(&timer->pdev->dev); + omap_pm_get_dev_context_loss_count(&timer->pdev->dev); /* * Since the register values are computed and written within @@ -378,6 +397,8 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_stop); int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) { int ret; + char *parent_name = NULL; + struct clk *fclk, *parent; struct dmtimer_platform_data *pdata; if (unlikely(!timer)) @@ -388,7 +409,49 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) if (source < 0 || source >= 3) return -EINVAL; - ret = pdata->set_timer_src(timer->pdev, source); + /* + * FIXME: Used for OMAP1 devices only because they do not currently + * use the clock framework to set the parent clock. To be removed + * once OMAP1 migrated to using clock framework for dmtimers + */ + if (pdata->set_timer_src) + return pdata->set_timer_src(timer->pdev, source); + + fclk = clk_get(&timer->pdev->dev, "fck"); + if (IS_ERR_OR_NULL(fclk)) { + pr_err("%s: fck not found\n", __func__); + return -EINVAL; + } + + switch (source) { + case OMAP_TIMER_SRC_SYS_CLK: + parent_name = "timer_sys_ck"; + break; + + case OMAP_TIMER_SRC_32_KHZ: + parent_name = "timer_32k_ck"; + break; + + case OMAP_TIMER_SRC_EXT_CLK: + parent_name = "timer_ext_ck"; + break; + } + + parent = clk_get(&timer->pdev->dev, parent_name); + if (IS_ERR_OR_NULL(parent)) { + pr_err("%s: %s not found\n", __func__, parent_name); + ret = -EINVAL; + goto out; + } + + ret = clk_set_parent(fclk, parent); + if (IS_ERR_VALUE(ret)) + pr_err("%s: failed to set %s as parent\n", __func__, + parent_name); + + clk_put(parent); +out: + clk_put(fclk); return ret; } @@ -431,10 +494,9 @@ int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, omap_dm_timer_enable(timer); - if (timer->loses_context) { - u32 ctx_loss_cnt_after = - timer->get_context_loss_count(&timer->pdev->dev); - if (ctx_loss_cnt_after != timer->ctx_loss_count) + if (!(timer->capability & OMAP_TIMER_ALWON)) { + if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) != + timer->ctx_loss_count) omap_timer_restore_context(timer); } @@ -674,13 +736,12 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev) timer->id = pdev->id; timer->irq = irq->start; - timer->reserved = pdata->reserved; + timer->reserved = omap_dm_timer_reserved_systimer(timer->id); timer->pdev = pdev; - timer->loses_context = pdata->loses_context; - timer->get_context_loss_count = pdata->get_context_loss_count; + timer->capability = pdata->timer_capability; /* Skip pm_runtime_enable for OMAP1 */ - if (!pdata->needs_manual_reset) { + if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { pm_runtime_enable(&pdev->dev); pm_runtime_irq_safe(&pdev->dev); } diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 5da73562e486..19e7fa577bd0 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -55,23 +55,17 @@ #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 -/* - * IP revision identifier so that Highlander IP - * in OMAP4 can be distinguished. - */ -#define OMAP_TIMER_IP_VERSION_1 0x1 - /* timer capabilities used in hwmod database */ #define OMAP_TIMER_SECURE 0x80000000 #define OMAP_TIMER_ALWON 0x40000000 #define OMAP_TIMER_HAS_PWM 0x20000000 +#define OMAP_TIMER_NEEDS_RESET 0x10000000 struct omap_timer_capability_dev_attr { u32 timer_capability; }; struct omap_dm_timer; -struct clk; struct timer_regs { u32 tidr; @@ -96,16 +90,12 @@ struct timer_regs { }; struct dmtimer_platform_data { + /* set_timer_src - Only used for OMAP1 devices */ int (*set_timer_src)(struct platform_device *pdev, int source); - int timer_ip_version; - u32 needs_manual_reset:1; - bool reserved; - - bool loses_context; - - int (*get_context_loss_count)(struct device *dev); + u32 timer_capability; }; +int omap_dm_timer_reserve_systimer(int id); struct omap_dm_timer *omap_dm_timer_request(void); struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id); int omap_dm_timer_free(struct omap_dm_timer *timer); @@ -272,13 +262,11 @@ struct omap_dm_timer { unsigned reserved:1; unsigned posted:1; struct timer_regs context; - bool loses_context; int ctx_loss_count; int revision; + u32 capability; struct platform_device *pdev; struct list_head node; - - int (*get_context_loss_count)(struct device *dev); }; int omap_dm_timer_prepare(struct omap_dm_timer *timer); diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index b073e5f2b190..28e2d250c2fd 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h @@ -60,6 +60,9 @@ /* AM3505/3517 UART4 */ #define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */ +/* AM33XX serial port */ +#define AM33XX_UART1_BASE 0x44E09000 + /* External port on Zoom2/3 */ #define ZOOM_UART_BASE 0x10000000 #define ZOOM_UART_VIRT 0xfa400000 @@ -93,6 +96,7 @@ #define TI81XXUART1 81 #define TI81XXUART2 82 #define TI81XXUART3 83 +#define AM33XXUART1 84 #define ZOOM_UART 95 /* Only on zoom2/3 */ /* This is only used by 8250.c for omap1510 */ diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index cc3f11ba7a99..ac4323390213 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -103,6 +103,10 @@ static inline void flush(void) _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ TI81XXUART##p) +#define DEBUG_LL_AM33XX(p, mach) \ + _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ + AM33XXUART##p) + static inline void __arch_decomp_setup(unsigned long arch_id) { int port = 0; @@ -183,6 +187,8 @@ static inline void __arch_decomp_setup(unsigned long arch_id) /* TI8148 base boards using UART1 */ DEBUG_LL_TI81XX(1, ti8148evm); + /* AM33XX base boards using UART1 */ + DEBUG_LL_AM33XX(1, am335xevm); } while (0); } diff --git a/arch/arm/plat-samsung/include/plat/map-s3c.h b/arch/arm/plat-samsung/include/plat/map-s3c.h index 7d048759b772..c0c70a895ca8 100644 --- a/arch/arm/plat-samsung/include/plat/map-s3c.h +++ b/arch/arm/plat-samsung/include/plat/map-s3c.h @@ -22,7 +22,7 @@ #define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG #define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000) -#define S3C2412_VA_EBI S3C_ADDR_CPU(0x00010000) +#define S3C2412_VA_EBI S3C_ADDR_CPU(0x00100000) #define S3C2410_PA_UART (0x50000000) #define S3C24XX_PA_UART S3C2410_PA_UART diff --git a/arch/arm/plat-samsung/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h index f19aff19205c..bc4db9b04e36 100644 --- a/arch/arm/plat-samsung/include/plat/watchdog-reset.h +++ b/arch/arm/plat-samsung/include/plat/watchdog-reset.h @@ -25,7 +25,7 @@ static inline void arch_wdt_reset(void) __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ - if (s3c2410_wdtclk) + if (!IS_ERR(s3c2410_wdtclk)) clk_enable(s3c2410_wdtclk); /* put initial values into count and data */ diff --git a/arch/m68k/platform/coldfire/clk.c b/arch/m68k/platform/coldfire/clk.c index 9f1260c5e2ad..44da406897e5 100644 --- a/arch/m68k/platform/coldfire/clk.c +++ b/arch/m68k/platform/coldfire/clk.c @@ -42,4 +42,11 @@ unsigned long clk_get_rate(struct clk *clk) return MCF_CLK; } EXPORT_SYMBOL(clk_get_rate); + +struct clk *devm_clk_get(struct device *dev, const char *id) +{ + return NULL; +} +EXPORT_SYMBOL(devm_clk_get); + /***************************************************************************/ diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h index 32b394f3b854..6eb75b80488c 100644 --- a/arch/powerpc/include/asm/hw_irq.h +++ b/arch/powerpc/include/asm/hw_irq.h @@ -103,6 +103,11 @@ static inline void hard_irq_disable(void) /* include/linux/interrupt.h needs hard_irq_disable to be a macro */ #define hard_irq_disable hard_irq_disable +static inline bool lazy_irq_pending(void) +{ + return !!(get_paca()->irq_happened & ~PACA_IRQ_HARD_DIS); +} + /* * This is called by asynchronous interrupts to conditionally * re-enable hard interrupts when soft-disabled after having diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index ed1718feb9d9..5971c85df136 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -558,27 +558,54 @@ _GLOBAL(ret_from_except_lite) mtmsrd r10,1 /* Update machine state */ #endif /* CONFIG_PPC_BOOK3E */ -#ifdef CONFIG_PREEMPT clrrdi r9,r1,THREAD_SHIFT /* current_thread_info() */ - li r0,_TIF_NEED_RESCHED /* bits to check */ ld r3,_MSR(r1) ld r4,TI_FLAGS(r9) - /* Move MSR_PR bit in r3 to _TIF_SIGPENDING position in r0 */ - rlwimi r0,r3,32+TIF_SIGPENDING-MSR_PR_LG,_TIF_SIGPENDING - and. r0,r4,r0 /* check NEED_RESCHED and maybe SIGPENDING */ - bne do_work - -#else /* !CONFIG_PREEMPT */ - ld r3,_MSR(r1) /* Returning to user mode? */ andi. r3,r3,MSR_PR - beq restore /* if not, just restore regs and return */ + beq resume_kernel /* Check current_thread_info()->flags */ + andi. r0,r4,_TIF_USER_WORK_MASK + beq restore + + andi. r0,r4,_TIF_NEED_RESCHED + beq 1f + bl .restore_interrupts + bl .schedule + b .ret_from_except_lite + +1: bl .save_nvgprs + bl .restore_interrupts + addi r3,r1,STACK_FRAME_OVERHEAD + bl .do_notify_resume + b .ret_from_except + +resume_kernel: +#ifdef CONFIG_PREEMPT + /* Check if we need to preempt */ + andi. r0,r4,_TIF_NEED_RESCHED + beq+ restore + /* Check that preempt_count() == 0 and interrupts are enabled */ + lwz r8,TI_PREEMPT(r9) + cmpwi cr1,r8,0 + ld r0,SOFTE(r1) + cmpdi r0,0 + crandc eq,cr1*4+eq,eq + bne restore + + /* + * Here we are preempting the current task. We want to make + * sure we are soft-disabled first + */ + SOFT_DISABLE_INTS(r3,r4) +1: bl .preempt_schedule_irq + + /* Re-test flags and eventually loop */ clrrdi r9,r1,THREAD_SHIFT ld r4,TI_FLAGS(r9) - andi. r0,r4,_TIF_USER_WORK_MASK - bne do_work -#endif /* !CONFIG_PREEMPT */ + andi. r0,r4,_TIF_NEED_RESCHED + bne 1b +#endif /* CONFIG_PREEMPT */ .globl fast_exc_return_irq fast_exc_return_irq: @@ -759,50 +786,6 @@ restore_check_irq_replay: #endif /* CONFIG_PPC_BOOK3E */ 1: b .ret_from_except /* What else to do here ? */ - - -3: -do_work: -#ifdef CONFIG_PREEMPT - andi. r0,r3,MSR_PR /* Returning to user mode? */ - bne user_work - /* Check that preempt_count() == 0 and interrupts are enabled */ - lwz r8,TI_PREEMPT(r9) - cmpwi cr1,r8,0 - ld r0,SOFTE(r1) - cmpdi r0,0 - crandc eq,cr1*4+eq,eq - bne restore - - /* - * Here we are preempting the current task. We want to make - * sure we are soft-disabled first - */ - SOFT_DISABLE_INTS(r3,r4) -1: bl .preempt_schedule_irq - - /* Re-test flags and eventually loop */ - clrrdi r9,r1,THREAD_SHIFT - ld r4,TI_FLAGS(r9) - andi. r0,r4,_TIF_NEED_RESCHED - bne 1b - b restore - -user_work: -#endif /* CONFIG_PREEMPT */ - - andi. r0,r4,_TIF_NEED_RESCHED - beq 1f - bl .restore_interrupts - bl .schedule - b .ret_from_except_lite - -1: bl .save_nvgprs - bl .restore_interrupts - addi r3,r1,STACK_FRAME_OVERHEAD - bl .do_notify_resume - b .ret_from_except - unrecov_restore: addi r3,r1,STACK_FRAME_OVERHEAD bl .unrecoverable_exception diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index 7835a5e1ea5f..1b415027ec0e 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c @@ -277,7 +277,7 @@ EXPORT_SYMBOL(arch_local_irq_restore); * NOTE: This is called with interrupts hard disabled but not marked * as such in paca->irq_happened, so we need to resync this. */ -void restore_interrupts(void) +void notrace restore_interrupts(void) { if (irqs_disabled()) { local_paca->irq_happened |= PACA_IRQ_HARD_DIS; diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c index 1b488e5305c5..0794a3017b1b 100644 --- a/arch/powerpc/kernel/prom_init.c +++ b/arch/powerpc/kernel/prom_init.c @@ -1312,7 +1312,7 @@ static struct opal_secondary_data { extern char opal_secondary_entry; -static void prom_query_opal(void) +static void __init prom_query_opal(void) { long rc; @@ -1436,7 +1436,7 @@ static void __init prom_opal_hold_cpus(void) prom_debug("prom_opal_hold_cpus: end...\n"); } -static void prom_opal_takeover(void) +static void __init prom_opal_takeover(void) { struct opal_secondary_data *data = &RELOC(opal_secondary_data); struct opal_takeover_args *args = &data->args; diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c index b6edbb3b4a54..6e8f677f5646 100644 --- a/arch/powerpc/mm/numa.c +++ b/arch/powerpc/mm/numa.c @@ -635,7 +635,7 @@ static inline int __init read_usm_ranges(const u32 **usm) */ static void __init parse_drconf_memory(struct device_node *memory) { - const u32 *dm, *usm; + const u32 *uninitialized_var(dm), *usm; unsigned int n, rc, ranges, is_kexec_kdump = 0; unsigned long lmb_size, base, size, sz; int nid; diff --git a/arch/powerpc/net/bpf_jit_64.S b/arch/powerpc/net/bpf_jit_64.S index 55ba3855a97f..7d3a3b5619a2 100644 --- a/arch/powerpc/net/bpf_jit_64.S +++ b/arch/powerpc/net/bpf_jit_64.S @@ -105,6 +105,7 @@ sk_load_byte_msh_positive_offset: mr r4, r_addr; \ li r6, SIZE; \ bl skb_copy_bits; \ + nop; \ /* R3 = 0 on success */ \ addi r1, r1, BPF_PPC_SLOWPATH_FRAME; \ ld r0, 16(r1); \ @@ -156,6 +157,7 @@ bpf_slow_path_byte_msh: mr r4, r_addr; \ li r5, SIZE; \ bl bpf_internal_load_pointer_neg_helper; \ + nop; \ /* R3 != 0 on success */ \ addi r1, r1, BPF_PPC_SLOWPATH_FRAME; \ ld r0, 16(r1); \ diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c index 0915b1ad66ce..2d311c0caf8e 100644 --- a/arch/powerpc/platforms/pseries/iommu.c +++ b/arch/powerpc/platforms/pseries/iommu.c @@ -106,7 +106,7 @@ static int tce_build_pSeries(struct iommu_table *tbl, long index, tcep++; } - if (tbl->it_type == TCE_PCI_SWINV_CREATE) + if (tbl->it_type & TCE_PCI_SWINV_CREATE) tce_invalidate_pSeries_sw(tbl, tces, tcep - 1); return 0; } @@ -121,7 +121,7 @@ static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages) while (npages--) *(tcep++) = 0; - if (tbl->it_type == TCE_PCI_SWINV_FREE) + if (tbl->it_type & TCE_PCI_SWINV_FREE) tce_invalidate_pSeries_sw(tbl, tces, tcep - 1); } diff --git a/arch/powerpc/platforms/pseries/processor_idle.c b/arch/powerpc/platforms/pseries/processor_idle.c index 41a34bc4a9a2..e61483e8e960 100644 --- a/arch/powerpc/platforms/pseries/processor_idle.c +++ b/arch/powerpc/platforms/pseries/processor_idle.c @@ -106,7 +106,7 @@ static void check_and_cede_processor(void) * we first hard disable then check. */ hard_irq_disable(); - if (get_paca()->irq_happened == 0) + if (!lazy_irq_pending()) cede_processor(); } diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c index 158c9176e42a..43a179ce9afc 100644 --- a/arch/sh/boards/mach-kfr2r09/setup.c +++ b/arch/sh/boards/mach-kfr2r09/setup.c @@ -201,8 +201,8 @@ static struct resource kfr2r09_usb0_gadget_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = evtirq(0xa20), - .end = evtirq(0xa20), + .start = evt2irq(0xa20), + .end = evt2irq(0xa20), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, }, }; diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index c045142f7338..9e702f2f8045 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -239,7 +239,7 @@ static int __init pcie_clk_init(struct sh7786_pcie_port *port) clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR); clk->enable_bit = BITS_CKE; - ret = sh_clk_mstp32_register(clk, 1); + ret = sh_clk_mstp_register(clk, 1); if (unlikely(ret < 0)) goto err_phy; diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c index ea01a72f1b94..53638e231cd0 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c @@ -283,7 +283,7 @@ int __init arch_clk_init(void) ret = sh_clk_div6_register(div6_clks, DIV6_NR); if (!ret) - ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c index 7ac07b4f75de..22e485d1990b 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c @@ -276,7 +276,7 @@ int __init arch_clk_init(void) ret = sh_clk_div6_register(div6_clks, DIV6_NR); if (!ret) - ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c index 8e1f97010c0d..c4cb740e4d10 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c @@ -261,7 +261,7 @@ int __init arch_clk_init(void) ret = sh_clk_div6_register(div6_clks, DIV6_NR); if (!ret) - ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR); + ret = sh_clk_mstp_register(mstp_clks, HWBLK_NR); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c index 35f75cf0c7e5..37c41c7747a3 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c @@ -311,7 +311,7 @@ int __init arch_clk_init(void) ret = sh_clk_div6_register(div6_clks, DIV6_NR); if (!ret) - ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR); + ret = sh_clk_mstp_register(mstp_clks, HWBLK_NR); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c index 2a87901673fe..c87e78f73234 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c @@ -375,7 +375,7 @@ int __init arch_clk_init(void) ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR); if (!ret) - ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR); + ret = sh_clk_mstp_register(mstp_clks, HWBLK_NR); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7734.c b/arch/sh/kernel/cpu/sh4a/clock-sh7734.c index 1697642c1f73..deb683abacf0 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7734.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7734.c @@ -260,7 +260,7 @@ int __init arch_clk_init(void) &div4_table); if (!ret) - ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c index 04ab5aeaf920..e84a43229b9c 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c @@ -148,7 +148,7 @@ int __init arch_clk_init(void) ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), &div4_table); if (!ret) - ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c index ab1c58f2d101..1c83788db76a 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c @@ -175,7 +175,7 @@ int __init arch_clk_init(void) ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), &div4_table); if (!ret) - ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c index 491709483e10..8bba6f159023 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c @@ -194,7 +194,7 @@ int __init arch_clk_init(void) ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), &div4_table); if (!ret) - ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); return ret; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c index 0f11b392bf46..a9422dab0ce7 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c @@ -149,7 +149,7 @@ int __init arch_clk_init(void) ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), &div4_table); if (!ret) - ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); + ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); return ret; } diff --git a/arch/x86/ia32/ia32_signal.c b/arch/x86/ia32/ia32_signal.c index daeca56211e3..673ac9b63d6b 100644 --- a/arch/x86/ia32/ia32_signal.c +++ b/arch/x86/ia32/ia32_signal.c @@ -38,7 +38,7 @@ int copy_siginfo_to_user32(compat_siginfo_t __user *to, siginfo_t *from) { int err = 0; - bool ia32 = is_ia32_task(); + bool ia32 = test_thread_flag(TIF_IA32); if (!access_ok(VERIFY_WRITE, to, sizeof(compat_siginfo_t))) return -EFAULT; diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 340ee49961a6..f91e80f4f180 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -176,7 +176,7 @@ #define X86_FEATURE_XSAVEOPT (7*32+ 4) /* Optimized Xsave */ #define X86_FEATURE_PLN (7*32+ 5) /* Intel Power Limit Notification */ #define X86_FEATURE_PTS (7*32+ 6) /* Intel Package Thermal Status */ -#define X86_FEATURE_DTS (7*32+ 7) /* Digital Thermal Sensor */ +#define X86_FEATURE_DTHERM (7*32+ 7) /* Digital Thermal Sensor */ #define X86_FEATURE_HW_PSTATE (7*32+ 8) /* AMD HW-PState */ /* Virtualization flags: Linux defined, word 8 */ diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index 8afb69319815..b2297e58c6ed 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -422,12 +422,14 @@ acpi_parse_int_src_ovr(struct acpi_subtable_header * header, return 0; } - if (intsrc->source_irq == 0 && intsrc->global_irq == 2) { + if (intsrc->source_irq == 0) { if (acpi_skip_timer_override) { - printk(PREFIX "BIOS IRQ0 pin2 override ignored.\n"); + printk(PREFIX "BIOS IRQ0 override ignored.\n"); return 0; } - if (acpi_fix_pin2_polarity && (intsrc->inti_flags & ACPI_MADT_POLARITY_MASK)) { + + if ((intsrc->global_irq == 2) && acpi_fix_pin2_polarity + && (intsrc->inti_flags & ACPI_MADT_POLARITY_MASK)) { intsrc->inti_flags &= ~ACPI_MADT_POLARITY_MASK; printk(PREFIX "BIOS IRQ0 pin2 override: forcing polarity to high active.\n"); } @@ -1334,17 +1336,12 @@ static int __init dmi_disable_acpi(const struct dmi_system_id *d) } /* - * Force ignoring BIOS IRQ0 pin2 override + * Force ignoring BIOS IRQ0 override */ static int __init dmi_ignore_irq0_timer_override(const struct dmi_system_id *d) { - /* - * The ati_ixp4x0_rev() early PCI quirk should have set - * the acpi_skip_timer_override flag already: - */ if (!acpi_skip_timer_override) { - WARN(1, KERN_ERR "ati_ixp4x0 quirk not complete.\n"); - pr_notice("%s detected: Ignoring BIOS IRQ0 pin2 override\n", + pr_notice("%s detected: Ignoring BIOS IRQ0 override\n", d->ident); acpi_skip_timer_override = 1; } @@ -1438,7 +1435,7 @@ static struct dmi_system_id __initdata acpi_dmi_table_late[] = { * is enabled. This input is incorrectly designated the * ISA IRQ 0 via an interrupt source override even though * it is wired to the output of the master 8259A and INTIN0 - * is not connected at all. Force ignoring BIOS IRQ0 pin2 + * is not connected at all. Force ignoring BIOS IRQ0 * override in that cases. */ { @@ -1473,6 +1470,14 @@ static struct dmi_system_id __initdata acpi_dmi_table_late[] = { DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6715b"), }, }, + { + .callback = dmi_ignore_irq0_timer_override, + .ident = "FUJITSU SIEMENS", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU SIEMENS"), + DMI_MATCH(DMI_PRODUCT_NAME, "AMILO PRO V2030"), + }, + }, {} }; diff --git a/arch/x86/kernel/cpu/mkcapflags.pl b/arch/x86/kernel/cpu/mkcapflags.pl index dfea390e1608..c7b3fe2d72e0 100644 --- a/arch/x86/kernel/cpu/mkcapflags.pl +++ b/arch/x86/kernel/cpu/mkcapflags.pl @@ -1,4 +1,4 @@ -#!/usr/bin/perl +#!/usr/bin/perl -w # # Generate the x86_cap_flags[] array from include/asm-x86/cpufeature.h # @@ -11,22 +11,35 @@ open(OUT, "> $out\0") or die "$0: cannot create: $out: $!\n"; print OUT "#include <asm/cpufeature.h>\n\n"; print OUT "const char * const x86_cap_flags[NCAPINTS*32] = {\n"; +%features = (); +$err = 0; + while (defined($line = <IN>)) { if ($line =~ /^\s*\#\s*define\s+(X86_FEATURE_(\S+))\s+(.*)$/) { $macro = $1; - $feature = $2; + $feature = "\L$2"; $tail = $3; if ($tail =~ /\/\*\s*\"([^"]*)\".*\*\//) { - $feature = $1; + $feature = "\L$1"; } - if ($feature ne '') { - printf OUT "\t%-32s = \"%s\",\n", - "[$macro]", "\L$feature"; + next if ($feature eq ''); + + if ($features{$feature}++) { + print STDERR "$in: duplicate feature name: $feature\n"; + $err++; } + printf OUT "\t%-32s = \"%s\",\n", "[$macro]", $feature; } } print OUT "};\n"; close(IN); close(OUT); + +if ($err) { + unlink($out); + exit(1); +} + +exit(0); diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index addf9e82a7f2..ee8e9abc859f 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -31,7 +31,7 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c) const struct cpuid_bit *cb; static const struct cpuid_bit __cpuinitconst cpuid_bits[] = { - { X86_FEATURE_DTS, CR_EAX, 0, 0x00000006, 0 }, + { X86_FEATURE_DTHERM, CR_EAX, 0, 0x00000006, 0 }, { X86_FEATURE_IDA, CR_EAX, 1, 0x00000006, 0 }, { X86_FEATURE_ARAT, CR_EAX, 2, 0x00000006, 0 }, { X86_FEATURE_PLN, CR_EAX, 4, 0x00000006, 0 }, diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c index 8bfb6146f753..3f61904365cf 100644 --- a/arch/x86/kernel/kgdb.c +++ b/arch/x86/kernel/kgdb.c @@ -444,12 +444,12 @@ void kgdb_roundup_cpus(unsigned long flags) /** * kgdb_arch_handle_exception - Handle architecture specific GDB packets. - * @vector: The error vector of the exception that happened. + * @e_vector: The error vector of the exception that happened. * @signo: The signal number of the exception that happened. * @err_code: The error code of the exception that happened. - * @remcom_in_buffer: The buffer of the packet we have read. - * @remcom_out_buffer: The buffer of %BUFMAX bytes to write a packet into. - * @regs: The &struct pt_regs of the current process. + * @remcomInBuffer: The buffer of the packet we have read. + * @remcomOutBuffer: The buffer of %BUFMAX bytes to write a packet into. + * @linux_regs: The &struct pt_regs of the current process. * * This function MUST handle the 'c' and 's' command packets, * as well packets to set / remove a hardware breakpoint, if used. diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index 25b48edb847c..5de92f1abd76 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c @@ -451,6 +451,14 @@ static struct dmi_system_id __initdata reboot_dmi_table[] = { DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 990"), }, }, + { /* Handle problems with rebooting on the Precision M6600. */ + .callback = set_pci_reboot, + .ident = "Dell OptiPlex 990", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "Precision M6600"), + }, + }, { } }; diff --git a/arch/x86/lib/csum-wrappers_64.c b/arch/x86/lib/csum-wrappers_64.c index 459b58a8a15c..25b7ae8d058a 100644 --- a/arch/x86/lib/csum-wrappers_64.c +++ b/arch/x86/lib/csum-wrappers_64.c @@ -115,7 +115,7 @@ EXPORT_SYMBOL(csum_partial_copy_to_user); * @src: source address * @dst: destination address * @len: number of bytes to be copied. - * @isum: initial sum that is added into the result (32bit unfolded) + * @sum: initial sum that is added into the result (32bit unfolded) * * Returns an 32bit unfolded checksum of the buffer. */ |