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-rw-r--r--arch/s390/pci/Makefile6
-rw-r--r--arch/s390/pci/pci.c1103
-rw-r--r--arch/s390/pci/pci_clp.c324
-rw-r--r--arch/s390/pci/pci_dma.c506
-rw-r--r--arch/s390/pci/pci_event.c93
-rw-r--r--arch/s390/pci/pci_msi.c141
-rw-r--r--arch/s390/pci/pci_sysfs.c86
7 files changed, 2259 insertions, 0 deletions
diff --git a/arch/s390/pci/Makefile b/arch/s390/pci/Makefile
new file mode 100644
index 000000000000..ab0827b6bc4b
--- /dev/null
+++ b/arch/s390/pci/Makefile
@@ -0,0 +1,6 @@
+#
+# Makefile for the s390 PCI subsystem.
+#
+
+obj-$(CONFIG_PCI) += pci.o pci_dma.o pci_clp.o pci_msi.o \
+ pci_sysfs.o pci_event.o
diff --git a/arch/s390/pci/pci.c b/arch/s390/pci/pci.c
new file mode 100644
index 000000000000..7ed38e5e3028
--- /dev/null
+++ b/arch/s390/pci/pci.c
@@ -0,0 +1,1103 @@
+/*
+ * Copyright IBM Corp. 2012
+ *
+ * Author(s):
+ * Jan Glauber <jang@linux.vnet.ibm.com>
+ *
+ * The System z PCI code is a rewrite from a prototype by
+ * the following people (Kudoz!):
+ * Alexander Schmidt
+ * Christoph Raisch
+ * Hannes Hering
+ * Hoang-Nam Nguyen
+ * Jan-Bernd Themann
+ * Stefan Roscher
+ * Thomas Klein
+ */
+
+#define COMPONENT "zPCI"
+#define pr_fmt(fmt) COMPONENT ": " fmt
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/export.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/kernel_stat.h>
+#include <linux/seq_file.h>
+#include <linux/pci.h>
+#include <linux/msi.h>
+
+#include <asm/isc.h>
+#include <asm/airq.h>
+#include <asm/facility.h>
+#include <asm/pci_insn.h>
+#include <asm/pci_clp.h>
+#include <asm/pci_dma.h>
+
+#define DEBUG /* enable pr_debug */
+
+#define SIC_IRQ_MODE_ALL 0
+#define SIC_IRQ_MODE_SINGLE 1
+
+#define ZPCI_NR_DMA_SPACES 1
+#define ZPCI_MSI_VEC_BITS 6
+#define ZPCI_NR_DEVICES CONFIG_PCI_NR_FUNCTIONS
+
+/* list of all detected zpci devices */
+LIST_HEAD(zpci_list);
+EXPORT_SYMBOL_GPL(zpci_list);
+DEFINE_MUTEX(zpci_list_lock);
+EXPORT_SYMBOL_GPL(zpci_list_lock);
+
+struct pci_hp_callback_ops hotplug_ops;
+EXPORT_SYMBOL_GPL(hotplug_ops);
+
+static DECLARE_BITMAP(zpci_domain, ZPCI_NR_DEVICES);
+static DEFINE_SPINLOCK(zpci_domain_lock);
+
+struct callback {
+ irq_handler_t handler;
+ void *data;
+};
+
+struct zdev_irq_map {
+ unsigned long aibv; /* AI bit vector */
+ int msi_vecs; /* consecutive MSI-vectors used */
+ int __unused;
+ struct callback cb[ZPCI_NR_MSI_VECS]; /* callback handler array */
+ spinlock_t lock; /* protect callbacks against de-reg */
+};
+
+struct intr_bucket {
+ /* amap of adapters, one bit per dev, corresponds to one irq nr */
+ unsigned long *alloc;
+ /* AI summary bit, global page for all devices */
+ unsigned long *aisb;
+ /* pointer to aibv and callback data in zdev */
+ struct zdev_irq_map *imap[ZPCI_NR_DEVICES];
+ /* protects the whole bucket struct */
+ spinlock_t lock;
+};
+
+static struct intr_bucket *bucket;
+
+/* Adapter local summary indicator */
+static u8 *zpci_irq_si;
+
+static atomic_t irq_retries = ATOMIC_INIT(0);
+
+/* I/O Map */
+static DEFINE_SPINLOCK(zpci_iomap_lock);
+static DECLARE_BITMAP(zpci_iomap, ZPCI_IOMAP_MAX_ENTRIES);
+struct zpci_iomap_entry *zpci_iomap_start;
+EXPORT_SYMBOL_GPL(zpci_iomap_start);
+
+/* highest irq summary bit */
+static int __read_mostly aisb_max;
+
+static struct kmem_cache *zdev_irq_cache;
+
+static inline int irq_to_msi_nr(unsigned int irq)
+{
+ return irq & ZPCI_MSI_MASK;
+}
+
+static inline int irq_to_dev_nr(unsigned int irq)
+{
+ return irq >> ZPCI_MSI_VEC_BITS;
+}
+
+static inline struct zdev_irq_map *get_imap(unsigned int irq)
+{
+ return bucket->imap[irq_to_dev_nr(irq)];
+}
+
+struct zpci_dev *get_zdev(struct pci_dev *pdev)
+{
+ return (struct zpci_dev *) pdev->sysdata;
+}
+
+struct zpci_dev *get_zdev_by_fid(u32 fid)
+{
+ struct zpci_dev *tmp, *zdev = NULL;
+
+ mutex_lock(&zpci_list_lock);
+ list_for_each_entry(tmp, &zpci_list, entry) {
+ if (tmp->fid == fid) {
+ zdev = tmp;
+ break;
+ }
+ }
+ mutex_unlock(&zpci_list_lock);
+ return zdev;
+}
+
+bool zpci_fid_present(u32 fid)
+{
+ return (get_zdev_by_fid(fid) != NULL) ? true : false;
+}
+
+static struct zpci_dev *get_zdev_by_bus(struct pci_bus *bus)
+{
+ return (bus && bus->sysdata) ? (struct zpci_dev *) bus->sysdata : NULL;
+}
+
+int pci_domain_nr(struct pci_bus *bus)
+{
+ return ((struct zpci_dev *) bus->sysdata)->domain;
+}
+EXPORT_SYMBOL_GPL(pci_domain_nr);
+
+int pci_proc_domain(struct pci_bus *bus)
+{
+ return pci_domain_nr(bus);
+}
+EXPORT_SYMBOL_GPL(pci_proc_domain);
+
+/* Store PCI function information block */
+static int zpci_store_fib(struct zpci_dev *zdev, u8 *fc)
+{
+ struct zpci_fib *fib;
+ u8 status, cc;
+
+ fib = (void *) get_zeroed_page(GFP_KERNEL);
+ if (!fib)
+ return -ENOMEM;
+
+ do {
+ cc = __stpcifc(zdev->fh, 0, fib, &status);
+ if (cc == 2) {
+ msleep(ZPCI_INSN_BUSY_DELAY);
+ memset(fib, 0, PAGE_SIZE);
+ }
+ } while (cc == 2);
+
+ if (cc)
+ pr_err_once("%s: cc: %u status: %u\n",
+ __func__, cc, status);
+
+ /* Return PCI function controls */
+ *fc = fib->fc;
+
+ free_page((unsigned long) fib);
+ return (cc) ? -EIO : 0;
+}
+
+/* Modify PCI: Register adapter interruptions */
+static int zpci_register_airq(struct zpci_dev *zdev, unsigned int aisb,
+ u64 aibv)
+{
+ u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_REG_INT);
+ struct zpci_fib *fib;
+ int rc;
+
+ fib = (void *) get_zeroed_page(GFP_KERNEL);
+ if (!fib)
+ return -ENOMEM;
+
+ fib->isc = PCI_ISC;
+ fib->noi = zdev->irq_map->msi_vecs;
+ fib->sum = 1; /* enable summary notifications */
+ fib->aibv = aibv;
+ fib->aibvo = 0; /* every function has its own page */
+ fib->aisb = (u64) bucket->aisb + aisb / 8;
+ fib->aisbo = aisb & ZPCI_MSI_MASK;
+
+ rc = mpcifc_instr(req, fib);
+ pr_debug("%s mpcifc returned noi: %d\n", __func__, fib->noi);
+
+ free_page((unsigned long) fib);
+ return rc;
+}
+
+struct mod_pci_args {
+ u64 base;
+ u64 limit;
+ u64 iota;
+};
+
+static int mod_pci(struct zpci_dev *zdev, int fn, u8 dmaas, struct mod_pci_args *args)
+{
+ u64 req = ZPCI_CREATE_REQ(zdev->fh, dmaas, fn);
+ struct zpci_fib *fib;
+ int rc;
+
+ /* The FIB must be available even if it's not used */
+ fib = (void *) get_zeroed_page(GFP_KERNEL);
+ if (!fib)
+ return -ENOMEM;
+
+ fib->pba = args->base;
+ fib->pal = args->limit;
+ fib->iota = args->iota;
+
+ rc = mpcifc_instr(req, fib);
+ free_page((unsigned long) fib);
+ return rc;
+}
+
+/* Modify PCI: Register I/O address translation parameters */
+int zpci_register_ioat(struct zpci_dev *zdev, u8 dmaas,
+ u64 base, u64 limit, u64 iota)
+{
+ struct mod_pci_args args = { base, limit, iota };
+
+ WARN_ON_ONCE(iota & 0x3fff);
+ args.iota |= ZPCI_IOTA_RTTO_FLAG;
+ return mod_pci(zdev, ZPCI_MOD_FC_REG_IOAT, dmaas, &args);
+}
+
+/* Modify PCI: Unregister I/O address translation parameters */
+int zpci_unregister_ioat(struct zpci_dev *zdev, u8 dmaas)
+{
+ struct mod_pci_args args = { 0, 0, 0 };
+
+ return mod_pci(zdev, ZPCI_MOD_FC_DEREG_IOAT, dmaas, &args);
+}
+
+/* Modify PCI: Unregister adapter interruptions */
+static int zpci_unregister_airq(struct zpci_dev *zdev)
+{
+ struct mod_pci_args args = { 0, 0, 0 };
+
+ return mod_pci(zdev, ZPCI_MOD_FC_DEREG_INT, 0, &args);
+}
+
+#define ZPCI_PCIAS_CFGSPC 15
+
+static int zpci_cfg_load(struct zpci_dev *zdev, int offset, u32 *val, u8 len)
+{
+ u64 req = ZPCI_CREATE_REQ(zdev->fh, ZPCI_PCIAS_CFGSPC, len);
+ u64 data;
+ int rc;
+
+ rc = pcilg_instr(&data, req, offset);
+ data = data << ((8 - len) * 8);
+ data = le64_to_cpu(data);
+ if (!rc)
+ *val = (u32) data;
+ else
+ *val = 0xffffffff;
+ return rc;
+}
+
+static int zpci_cfg_store(struct zpci_dev *zdev, int offset, u32 val, u8 len)
+{
+ u64 req = ZPCI_CREATE_REQ(zdev->fh, ZPCI_PCIAS_CFGSPC, len);
+ u64 data = val;
+ int rc;
+
+ data = cpu_to_le64(data);
+ data = data >> ((8 - len) * 8);
+ rc = pcistg_instr(data, req, offset);
+ return rc;
+}
+
+void synchronize_irq(unsigned int irq)
+{
+ /*
+ * Not needed, the handler is protected by a lock and IRQs that occur
+ * after the handler is deleted are just NOPs.
+ */
+}
+EXPORT_SYMBOL_GPL(synchronize_irq);
+
+void enable_irq(unsigned int irq)
+{
+ struct msi_desc *msi = irq_get_msi_desc(irq);
+
+ zpci_msi_set_mask_bits(msi, 1, 0);
+}
+EXPORT_SYMBOL_GPL(enable_irq);
+
+void disable_irq(unsigned int irq)
+{
+ struct msi_desc *msi = irq_get_msi_desc(irq);
+
+ zpci_msi_set_mask_bits(msi, 1, 1);
+}
+EXPORT_SYMBOL_GPL(disable_irq);
+
+void disable_irq_nosync(unsigned int irq)
+{
+ disable_irq(irq);
+}
+EXPORT_SYMBOL_GPL(disable_irq_nosync);
+
+unsigned long probe_irq_on(void)
+{
+ return 0;
+}
+EXPORT_SYMBOL_GPL(probe_irq_on);
+
+int probe_irq_off(unsigned long val)
+{
+ return 0;
+}
+EXPORT_SYMBOL_GPL(probe_irq_off);
+
+unsigned int probe_irq_mask(unsigned long val)
+{
+ return val;
+}
+EXPORT_SYMBOL_GPL(probe_irq_mask);
+
+void __devinit pcibios_fixup_bus(struct pci_bus *bus)
+{
+}
+
+resource_size_t pcibios_align_resource(void *data, const struct resource *res,
+ resource_size_t size,
+ resource_size_t align)
+{
+ return 0;
+}
+
+/* combine single writes by using store-block insn */
+void __iowrite64_copy(void __iomem *to, const void *from, size_t count)
+{
+ zpci_memcpy_toio(to, from, count);
+}
+
+/* Create a virtual mapping cookie for a PCI BAR */
+void __iomem *pci_iomap(struct pci_dev *pdev, int bar, unsigned long max)
+{
+ struct zpci_dev *zdev = get_zdev(pdev);
+ u64 addr;
+ int idx;
+
+ if ((bar & 7) != bar)
+ return NULL;
+
+ idx = zdev->bars[bar].map_idx;
+ spin_lock(&zpci_iomap_lock);
+ zpci_iomap_start[idx].fh = zdev->fh;
+ zpci_iomap_start[idx].bar = bar;
+ spin_unlock(&zpci_iomap_lock);
+
+ addr = ZPCI_IOMAP_ADDR_BASE | ((u64) idx << 48);
+ return (void __iomem *) addr;
+}
+EXPORT_SYMBOL_GPL(pci_iomap);
+
+void pci_iounmap(struct pci_dev *pdev, void __iomem *addr)
+{
+ unsigned int idx;
+
+ idx = (((__force u64) addr) & ~ZPCI_IOMAP_ADDR_BASE) >> 48;
+ spin_lock(&zpci_iomap_lock);
+ zpci_iomap_start[idx].fh = 0;
+ zpci_iomap_start[idx].bar = 0;
+ spin_unlock(&zpci_iomap_lock);
+}
+EXPORT_SYMBOL_GPL(pci_iounmap);
+
+static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, u32 *val)
+{
+ struct zpci_dev *zdev = get_zdev_by_bus(bus);
+
+ if (!zdev || devfn != ZPCI_DEVFN)
+ return 0;
+ return zpci_cfg_load(zdev, where, val, size);
+}
+
+static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, u32 val)
+{
+ struct zpci_dev *zdev = get_zdev_by_bus(bus);
+
+ if (!zdev || devfn != ZPCI_DEVFN)
+ return 0;
+ return zpci_cfg_store(zdev, where, val, size);
+}
+
+static struct pci_ops pci_root_ops = {
+ .read = pci_read,
+ .write = pci_write,
+};
+
+/* store the last handled bit to implement fair scheduling of devices */
+static DEFINE_PER_CPU(unsigned long, next_sbit);
+
+static void zpci_irq_handler(void *dont, void *need)
+{
+ unsigned long sbit, mbit, last = 0, start = __get_cpu_var(next_sbit);
+ int rescan = 0, max = aisb_max;
+ struct zdev_irq_map *imap;
+
+ kstat_cpu(smp_processor_id()).irqs[IOINT_PCI]++;
+ sbit = start;
+
+scan:
+ /* find summary_bit */
+ for_each_set_bit_left_cont(sbit, bucket->aisb, max) {
+ clear_bit(63 - (sbit & 63), bucket->aisb + (sbit >> 6));
+ last = sbit;
+
+ /* find vector bit */
+ imap = bucket->imap[sbit];
+ for_each_set_bit_left(mbit, &imap->aibv, imap->msi_vecs) {
+ kstat_cpu(smp_processor_id()).irqs[IOINT_MSI]++;
+ clear_bit(63 - mbit, &imap->aibv);
+
+ spin_lock(&imap->lock);
+ if (imap->cb[mbit].handler)
+ imap->cb[mbit].handler(mbit,
+ imap->cb[mbit].data);
+ spin_unlock(&imap->lock);
+ }
+ }
+
+ if (rescan)
+ goto out;
+
+ /* scan the skipped bits */
+ if (start > 0) {
+ sbit = 0;
+ max = start;
+ start = 0;
+ goto scan;
+ }
+
+ /* enable interrupts again */
+ sic_instr(SIC_IRQ_MODE_SINGLE, NULL, PCI_ISC);
+
+ /* check again to not lose initiative */
+ rmb();
+ max = aisb_max;
+ sbit = find_first_bit_left(bucket->aisb, max);
+ if (sbit != max) {
+ atomic_inc(&irq_retries);
+ rescan++;
+ goto scan;
+ }
+out:
+ /* store next device bit to scan */
+ __get_cpu_var(next_sbit) = (++last >= aisb_max) ? 0 : last;
+}
+
+/* msi_vecs - number of requested interrupts, 0 place function to error state */
+static int zpci_setup_msi(struct pci_dev *pdev, int msi_vecs)
+{
+ struct zpci_dev *zdev = get_zdev(pdev);
+ unsigned int aisb, msi_nr;
+ struct msi_desc *msi;
+ int rc;
+
+ /* store the number of used MSI vectors */
+ zdev->irq_map->msi_vecs = min(msi_vecs, ZPCI_NR_MSI_VECS);
+
+ spin_lock(&bucket->lock);
+ aisb = find_first_zero_bit(bucket->alloc, PAGE_SIZE);
+ /* alloc map exhausted? */
+ if (aisb == PAGE_SIZE) {
+ spin_unlock(&bucket->lock);
+ return -EIO;
+ }
+ set_bit(aisb, bucket->alloc);
+ spin_unlock(&bucket->lock);
+
+ zdev->aisb = aisb;
+ if (aisb + 1 > aisb_max)
+ aisb_max = aisb + 1;
+
+ /* wire up IRQ shortcut pointer */
+ bucket->imap[zdev->aisb] = zdev->irq_map;
+ pr_debug("%s: imap[%u] linked to %p\n", __func__, zdev->aisb, zdev->irq_map);
+
+ /* TODO: irq number 0 wont be found if we return less than requested MSIs.
+ * ignore it for now and fix in common code.
+ */
+ msi_nr = aisb << ZPCI_MSI_VEC_BITS;
+
+ list_for_each_entry(msi, &pdev->msi_list, list) {
+ rc = zpci_setup_msi_irq(zdev, msi, msi_nr,
+ aisb << ZPCI_MSI_VEC_BITS);
+ if (rc)
+ return rc;
+ msi_nr++;
+ }
+
+ rc = zpci_register_airq(zdev, aisb, (u64) &zdev->irq_map->aibv);
+ if (rc) {
+ clear_bit(aisb, bucket->alloc);
+ dev_err(&pdev->dev, "register MSI failed with: %d\n", rc);
+ return rc;
+ }
+ return (zdev->irq_map->msi_vecs == msi_vecs) ?
+ 0 : zdev->irq_map->msi_vecs;
+}
+
+static void zpci_teardown_msi(struct pci_dev *pdev)
+{
+ struct zpci_dev *zdev = get_zdev(pdev);
+ struct msi_desc *msi;
+ int aisb, rc;
+
+ rc = zpci_unregister_airq(zdev);
+ if (rc) {
+ dev_err(&pdev->dev, "deregister MSI failed with: %d\n", rc);
+ return;
+ }
+
+ msi = list_first_entry(&pdev->msi_list, struct msi_desc, list);
+ aisb = irq_to_dev_nr(msi->irq);
+
+ list_for_each_entry(msi, &pdev->msi_list, list)
+ zpci_teardown_msi_irq(zdev, msi);
+
+ clear_bit(aisb, bucket->alloc);
+ if (aisb + 1 == aisb_max)
+ aisb_max--;
+}
+
+int arch_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
+{
+ pr_debug("%s: requesting %d MSI-X interrupts...", __func__, nvec);
+ if (type != PCI_CAP_ID_MSIX && type != PCI_CAP_ID_MSI)
+ return -EINVAL;
+ return zpci_setup_msi(pdev, nvec);
+}
+
+void arch_teardown_msi_irqs(struct pci_dev *pdev)
+{
+ pr_info("%s: on pdev: %p\n", __func__, pdev);
+ zpci_teardown_msi(pdev);
+}
+
+static void zpci_map_resources(struct zpci_dev *zdev)
+{
+ struct pci_dev *pdev = zdev->pdev;
+ resource_size_t len;
+ int i;
+
+ for (i = 0; i < PCI_BAR_COUNT; i++) {
+ len = pci_resource_len(pdev, i);
+ if (!len)
+ continue;
+ pdev->resource[i].start = (resource_size_t) pci_iomap(pdev, i, 0);
+ pdev->resource[i].end = pdev->resource[i].start + len - 1;
+ pr_debug("BAR%i: -> start: %Lx end: %Lx\n",
+ i, pdev->resource[i].start, pdev->resource[i].end);
+ }
+};
+
+static void zpci_unmap_resources(struct pci_dev *pdev)
+{
+ resource_size_t len;
+ int i;
+
+ for (i = 0; i < PCI_BAR_COUNT; i++) {
+ len = pci_resource_len(pdev, i);
+ if (!len)
+ continue;
+ pci_iounmap(pdev, (void *) pdev->resource[i].start);
+ }
+};
+
+struct zpci_dev *zpci_alloc_device(void)
+{
+ struct zpci_dev *zdev;
+
+ /* Alloc memory for our private pci device data */
+ zdev = kzalloc(sizeof(*zdev), GFP_KERNEL);
+ if (!zdev)
+ return ERR_PTR(-ENOMEM);
+
+ /* Alloc aibv & callback space */
+ zdev->irq_map = kmem_cache_zalloc(zdev_irq_cache, GFP_KERNEL);
+ if (!zdev->irq_map)
+ goto error;
+ WARN_ON((u64) zdev->irq_map & 0xff);
+ return zdev;
+
+error:
+ kfree(zdev);
+ return ERR_PTR(-ENOMEM);
+}
+
+void zpci_free_device(struct zpci_dev *zdev)
+{
+ kmem_cache_free(zdev_irq_cache, zdev->irq_map);
+ kfree(zdev);
+}
+
+/* Called on removal of pci_dev, leaves zpci and bus device */
+static void zpci_remove_device(struct pci_dev *pdev)
+{
+ struct zpci_dev *zdev = get_zdev(pdev);
+
+ dev_info(&pdev->dev, "Removing device %u\n", zdev->domain);
+ zdev->state = ZPCI_FN_STATE_CONFIGURED;
+ zpci_dma_exit_device(zdev);
+ zpci_sysfs_remove_device(&pdev->dev);
+ zpci_unmap_resources(pdev);
+ list_del(&zdev->entry); /* can be called from init */
+ zdev->pdev = NULL;
+}
+
+static void zpci_scan_devices(void)
+{
+ struct zpci_dev *zdev;
+
+ mutex_lock(&zpci_list_lock);
+ list_for_each_entry(zdev, &zpci_list, entry)
+ if (zdev->state == ZPCI_FN_STATE_CONFIGURED)
+ zpci_scan_device(zdev);
+ mutex_unlock(&zpci_list_lock);
+}
+
+/*
+ * Too late for any s390 specific setup, since interrupts must be set up
+ * already which requires DMA setup too and the pci scan will access the
+ * config space, which only works if the function handle is enabled.
+ */
+int pcibios_enable_device(struct pci_dev *pdev, int mask)
+{
+ struct resource *res;
+ u16 cmd;
+ int i;
+
+ pci_read_config_word(pdev, PCI_COMMAND, &cmd);
+
+ for (i = 0; i < PCI_BAR_COUNT; i++) {
+ res = &pdev->resource[i];
+
+ if (res->flags & IORESOURCE_IO)
+ return -EINVAL;
+
+ if (res->flags & IORESOURCE_MEM)
+ cmd |= PCI_COMMAND_MEMORY;
+ }
+ pci_write_config_word(pdev, PCI_COMMAND, cmd);
+ return 0;
+}
+
+void pcibios_disable_device(struct pci_dev *pdev)
+{
+ zpci_remove_device(pdev);
+ pdev->sysdata = NULL;
+}
+
+int pcibios_add_platform_entries(struct pci_dev *pdev)
+{
+ return zpci_sysfs_add_device(&pdev->dev);
+}
+
+int zpci_request_irq(unsigned int irq, irq_handler_t handler, void *data)
+{
+ int msi_nr = irq_to_msi_nr(irq);
+ struct zdev_irq_map *imap;
+ struct msi_desc *msi;
+
+ msi = irq_get_msi_desc(irq);
+ if (!msi)
+ return -EIO;
+
+ imap = get_imap(irq);
+ spin_lock_init(&imap->lock);
+
+ pr_debug("%s: register handler for IRQ:MSI %d:%d\n", __func__, irq >> 6, msi_nr);
+ imap->cb[msi_nr].handler = handler;
+ imap->cb[msi_nr].data = data;
+
+ /*
+ * The generic MSI code returns with the interrupt disabled on the
+ * card, using the MSI mask bits. Firmware doesn't appear to unmask
+ * at that level, so we do it here by hand.
+ */
+ zpci_msi_set_mask_bits(msi, 1, 0);
+ return 0;
+}
+
+void zpci_free_irq(unsigned int irq)
+{
+ struct zdev_irq_map *imap = get_imap(irq);
+ int msi_nr = irq_to_msi_nr(irq);
+ unsigned long flags;
+
+ pr_debug("%s: for irq: %d\n", __func__, irq);
+
+ spin_lock_irqsave(&imap->lock, flags);
+ imap->cb[msi_nr].handler = NULL;
+ imap->cb[msi_nr].data = NULL;
+ spin_unlock_irqrestore(&imap->lock, flags);
+}
+
+int request_irq(unsigned int irq, irq_handler_t handler,
+ unsigned long irqflags, const char *devname, void *dev_id)
+{
+ pr_debug("%s: irq: %d handler: %p flags: %lx dev: %s\n",
+ __func__, irq, handler, irqflags, devname);
+
+ return zpci_request_irq(irq, handler, dev_id);
+}
+EXPORT_SYMBOL_GPL(request_irq);
+
+void free_irq(unsigned int irq, void *dev_id)
+{
+ zpci_free_irq(irq);
+}
+EXPORT_SYMBOL_GPL(free_irq);
+
+static int __init zpci_irq_init(void)
+{
+ int cpu, rc;
+
+ bucket = kzalloc(sizeof(*bucket), GFP_KERNEL);
+ if (!bucket)
+ return -ENOMEM;
+
+ bucket->aisb = (unsigned long *) get_zeroed_page(GFP_KERNEL);
+ if (!bucket->aisb) {
+ rc = -ENOMEM;
+ goto out_aisb;
+ }
+
+ bucket->alloc = (unsigned long *) get_zeroed_page(GFP_KERNEL);
+ if (!bucket->alloc) {
+ rc = -ENOMEM;
+ goto out_alloc;
+ }
+
+ isc_register(PCI_ISC);
+ zpci_irq_si = s390_register_adapter_interrupt(&zpci_irq_handler, NULL, PCI_ISC);
+ if (IS_ERR(zpci_irq_si)) {
+ rc = PTR_ERR(zpci_irq_si);
+ zpci_irq_si = NULL;
+ goto out_ai;
+ }
+
+ for_each_online_cpu(cpu)
+ per_cpu(next_sbit, cpu) = 0;
+
+ spin_lock_init(&bucket->lock);
+ /* set summary to 1 to be called every time for the ISC */
+ *zpci_irq_si = 1;
+ sic_instr(SIC_IRQ_MODE_SINGLE, NULL, PCI_ISC);
+ return 0;
+
+out_ai:
+ isc_unregister(PCI_ISC);
+ free_page((unsigned long) bucket->alloc);
+out_alloc:
+ free_page((unsigned long) bucket->aisb);
+out_aisb:
+ kfree(bucket);
+ return rc;
+}
+
+static void zpci_irq_exit(void)
+{
+ free_page((unsigned long) bucket->alloc);
+ free_page((unsigned long) bucket->aisb);
+ s390_unregister_adapter_interrupt(zpci_irq_si, PCI_ISC);
+ isc_unregister(PCI_ISC);
+ kfree(bucket);
+}
+
+static struct resource *zpci_alloc_bus_resource(unsigned long start, unsigned long size,
+ unsigned long flags, int domain)
+{
+ struct resource *r;
+ char *name;
+ int rc;
+
+ r = kzalloc(sizeof(*r), GFP_KERNEL);
+ if (!r)
+ return ERR_PTR(-ENOMEM);
+ r->start = start;
+ r->end = r->start + size - 1;
+ r->flags = flags;
+ r->parent = &iomem_resource;
+ name = kmalloc(18, GFP_KERNEL);
+ if (!name) {
+ kfree(r);
+ return ERR_PTR(-ENOMEM);
+ }
+ sprintf(name, "PCI Bus: %04x:%02x", domain, ZPCI_BUS_NR);
+ r->name = name;
+
+ rc = request_resource(&iomem_resource, r);
+ if (rc)
+ pr_debug("request resource %pR failed\n", r);
+ return r;
+}
+
+static int zpci_alloc_iomap(struct zpci_dev *zdev)
+{
+ int entry;
+
+ spin_lock(&zpci_iomap_lock);
+ entry = find_first_zero_bit(zpci_iomap, ZPCI_IOMAP_MAX_ENTRIES);
+ if (entry == ZPCI_IOMAP_MAX_ENTRIES) {
+ spin_unlock(&zpci_iomap_lock);
+ return -ENOSPC;
+ }
+ set_bit(entry, zpci_iomap);
+ spin_unlock(&zpci_iomap_lock);
+ return entry;
+}
+
+static void zpci_free_iomap(struct zpci_dev *zdev, int entry)
+{
+ spin_lock(&zpci_iomap_lock);
+ memset(&zpci_iomap_start[entry], 0, sizeof(struct zpci_iomap_entry));
+ clear_bit(entry, zpci_iomap);
+ spin_unlock(&zpci_iomap_lock);
+}
+
+static int zpci_create_device_bus(struct zpci_dev *zdev)
+{
+ struct resource *res;
+ LIST_HEAD(resources);
+ int i;
+
+ /* allocate mapping entry for each used bar */
+ for (i = 0; i < PCI_BAR_COUNT; i++) {
+ unsigned long addr, size, flags;
+ int entry;
+
+ if (!zdev->bars[i].size)
+ continue;
+ entry = zpci_alloc_iomap(zdev);
+ if (entry < 0)
+ return entry;
+ zdev->bars[i].map_idx = entry;
+
+ /* only MMIO is supported */
+ flags = IORESOURCE_MEM;
+ if (zdev->bars[i].val & 8)
+ flags |= IORESOURCE_PREFETCH;
+ if (zdev->bars[i].val & 4)
+ flags |= IORESOURCE_MEM_64;
+
+ addr = ZPCI_IOMAP_ADDR_BASE + ((u64) entry << 48);
+
+ size = 1UL << zdev->bars[i].size;
+
+ res = zpci_alloc_bus_resource(addr, size, flags, zdev->domain);
+ if (IS_ERR(res)) {
+ zpci_free_iomap(zdev, entry);
+ return PTR_ERR(res);
+ }
+ pci_add_resource(&resources, res);
+ }
+
+ zdev->bus = pci_create_root_bus(NULL, ZPCI_BUS_NR, &pci_root_ops,
+ zdev, &resources);
+ if (!zdev->bus)
+ return -EIO;
+
+ zdev->bus->max_bus_speed = zdev->max_bus_speed;
+ return 0;
+}
+
+static int zpci_alloc_domain(struct zpci_dev *zdev)
+{
+ spin_lock(&zpci_domain_lock);
+ zdev->domain = find_first_zero_bit(zpci_domain, ZPCI_NR_DEVICES);
+ if (zdev->domain == ZPCI_NR_DEVICES) {
+ spin_unlock(&zpci_domain_lock);
+ return -ENOSPC;
+ }
+ set_bit(zdev->domain, zpci_domain);
+ spin_unlock(&zpci_domain_lock);
+ return 0;
+}
+
+static void zpci_free_domain(struct zpci_dev *zdev)
+{
+ spin_lock(&zpci_domain_lock);
+ clear_bit(zdev->domain, zpci_domain);
+ spin_unlock(&zpci_domain_lock);
+}
+
+int zpci_enable_device(struct zpci_dev *zdev)
+{
+ int rc;
+
+ rc = clp_enable_fh(zdev, ZPCI_NR_DMA_SPACES);
+ if (rc)
+ goto out;
+ pr_info("Enabled fh: 0x%x fid: 0x%x\n", zdev->fh, zdev->fid);
+
+ rc = zpci_dma_init_device(zdev);
+ if (rc)
+ goto out_dma;
+ return 0;
+
+out_dma:
+ clp_disable_fh(zdev);
+out:
+ return rc;
+}
+EXPORT_SYMBOL_GPL(zpci_enable_device);
+
+int zpci_create_device(struct zpci_dev *zdev)
+{
+ int rc;
+
+ rc = zpci_alloc_domain(zdev);
+ if (rc)
+ goto out;
+
+ rc = zpci_create_device_bus(zdev);
+ if (rc)
+ goto out_bus;
+
+ mutex_lock(&zpci_list_lock);
+ list_add_tail(&zdev->entry, &zpci_list);
+ if (hotplug_ops.create_slot)
+ hotplug_ops.create_slot(zdev);
+ mutex_unlock(&zpci_list_lock);
+
+ if (zdev->state == ZPCI_FN_STATE_STANDBY)
+ return 0;
+
+ rc = zpci_enable_device(zdev);
+ if (rc)
+ goto out_start;
+ return 0;
+
+out_start:
+ mutex_lock(&zpci_list_lock);
+ list_del(&zdev->entry);
+ if (hotplug_ops.remove_slot)
+ hotplug_ops.remove_slot(zdev);
+ mutex_unlock(&zpci_list_lock);
+out_bus:
+ zpci_free_domain(zdev);
+out:
+ return rc;
+}
+
+void zpci_stop_device(struct zpci_dev *zdev)
+{
+ zpci_dma_exit_device(zdev);
+ /*
+ * Note: SCLP disables fh via set-pci-fn so don't
+ * do that here.
+ */
+}
+EXPORT_SYMBOL_GPL(zpci_stop_device);
+
+int zpci_scan_device(struct zpci_dev *zdev)
+{
+ zdev->pdev = pci_scan_single_device(zdev->bus, ZPCI_DEVFN);
+ if (!zdev->pdev) {
+ pr_err("pci_scan_single_device failed for fid: 0x%x\n",
+ zdev->fid);
+ goto out;
+ }
+
+ zpci_map_resources(zdev);
+ pci_bus_add_devices(zdev->bus);
+
+ /* now that pdev was added to the bus mark it as used */
+ zdev->state = ZPCI_FN_STATE_ONLINE;
+ return 0;
+
+out:
+ zpci_dma_exit_device(zdev);
+ clp_disable_fh(zdev);
+ return -EIO;
+}
+EXPORT_SYMBOL_GPL(zpci_scan_device);
+
+static inline int barsize(u8 size)
+{
+ return (size) ? (1 << size) >> 10 : 0;
+}
+
+static int zpci_mem_init(void)
+{
+ zdev_irq_cache = kmem_cache_create("PCI_IRQ_cache", sizeof(struct zdev_irq_map),
+ L1_CACHE_BYTES, SLAB_HWCACHE_ALIGN, NULL);
+ if (!zdev_irq_cache)
+ goto error_zdev;
+
+ /* TODO: use realloc */
+ zpci_iomap_start = kzalloc(ZPCI_IOMAP_MAX_ENTRIES * sizeof(*zpci_iomap_start),
+ GFP_KERNEL);
+ if (!zpci_iomap_start)
+ goto error_iomap;
+ return 0;
+
+error_iomap:
+ kmem_cache_destroy(zdev_irq_cache);
+error_zdev:
+ return -ENOMEM;
+}
+
+static void zpci_mem_exit(void)
+{
+ kfree(zpci_iomap_start);
+ kmem_cache_destroy(zdev_irq_cache);
+}
+
+unsigned int pci_probe = 1;
+EXPORT_SYMBOL_GPL(pci_probe);
+
+char * __init pcibios_setup(char *str)
+{
+ if (!strcmp(str, "off")) {
+ pci_probe = 0;
+ return NULL;
+ }
+ return str;
+}
+
+static int __init pci_base_init(void)
+{
+ int rc;
+
+ if (!pci_probe)
+ return 0;
+
+ if (!test_facility(2) || !test_facility(69)
+ || !test_facility(71) || !test_facility(72))
+ return 0;
+
+ pr_info("Probing PCI hardware: PCI:%d SID:%d AEN:%d\n",
+ test_facility(69), test_facility(70),
+ test_facility(71));
+
+ rc = zpci_mem_init();
+ if (rc)
+ goto out_mem;
+
+ rc = zpci_msihash_init();
+ if (rc)
+ goto out_hash;
+
+ rc = zpci_irq_init();
+ if (rc)
+ goto out_irq;
+
+ rc = zpci_dma_init();
+ if (rc)
+ goto out_dma;
+
+ rc = clp_find_pci_devices();
+ if (rc)
+ goto out_find;
+
+ zpci_scan_devices();
+ return 0;
+
+out_find:
+ zpci_dma_exit();
+out_dma:
+ zpci_irq_exit();
+out_irq:
+ zpci_msihash_exit();
+out_hash:
+ zpci_mem_exit();
+out_mem:
+ return rc;
+}
+subsys_initcall(pci_base_init);
diff --git a/arch/s390/pci/pci_clp.c b/arch/s390/pci/pci_clp.c
new file mode 100644
index 000000000000..7f4ce8d874a4
--- /dev/null
+++ b/arch/s390/pci/pci_clp.c
@@ -0,0 +1,324 @@
+/*
+ * Copyright IBM Corp. 2012
+ *
+ * Author(s):
+ * Jan Glauber <jang@linux.vnet.ibm.com>
+ */
+
+#define COMPONENT "zPCI"
+#define pr_fmt(fmt) COMPONENT ": " fmt
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <asm/pci_clp.h>
+
+/*
+ * Call Logical Processor
+ * Retry logic is handled by the caller.
+ */
+static inline u8 clp_instr(void *req)
+{
+ u64 ilpm;
+ u8 cc;
+
+ asm volatile (
+ " .insn rrf,0xb9a00000,%[ilpm],%[req],0x0,0x2\n"
+ " ipm %[cc]\n"
+ " srl %[cc],28\n"
+ : [cc] "=d" (cc), [ilpm] "=d" (ilpm)
+ : [req] "a" (req)
+ : "cc", "memory");
+ return cc;
+}
+
+static void *clp_alloc_block(void)
+{
+ struct page *page = alloc_pages(GFP_KERNEL, get_order(CLP_BLK_SIZE));
+ return (page) ? page_address(page) : NULL;
+}
+
+static void clp_free_block(void *ptr)
+{
+ free_pages((unsigned long) ptr, get_order(CLP_BLK_SIZE));
+}
+
+static void clp_store_query_pci_fngrp(struct zpci_dev *zdev,
+ struct clp_rsp_query_pci_grp *response)
+{
+ zdev->tlb_refresh = response->refresh;
+ zdev->dma_mask = response->dasm;
+ zdev->msi_addr = response->msia;
+
+ pr_debug("Supported number of MSI vectors: %u\n", response->noi);
+ switch (response->version) {
+ case 1:
+ zdev->max_bus_speed = PCIE_SPEED_5_0GT;
+ break;
+ default:
+ zdev->max_bus_speed = PCI_SPEED_UNKNOWN;
+ break;
+ }
+}
+
+static int clp_query_pci_fngrp(struct zpci_dev *zdev, u8 pfgid)
+{
+ struct clp_req_rsp_query_pci_grp *rrb;
+ int rc;
+
+ rrb = clp_alloc_block();
+ if (!rrb)
+ return -ENOMEM;
+
+ memset(rrb, 0, sizeof(*rrb));
+ rrb->request.hdr.len = sizeof(rrb->request);
+ rrb->request.hdr.cmd = CLP_QUERY_PCI_FNGRP;
+ rrb->response.hdr.len = sizeof(rrb->response);
+ rrb->request.pfgid = pfgid;
+
+ rc = clp_instr(rrb);
+ if (!rc && rrb->response.hdr.rsp == CLP_RC_OK)
+ clp_store_query_pci_fngrp(zdev, &rrb->response);
+ else {
+ pr_err("Query PCI FNGRP failed with response: %x cc: %d\n",
+ rrb->response.hdr.rsp, rc);
+ rc = -EIO;
+ }
+ clp_free_block(rrb);
+ return rc;
+}
+
+static int clp_store_query_pci_fn(struct zpci_dev *zdev,
+ struct clp_rsp_query_pci *response)
+{
+ int i;
+
+ for (i = 0; i < PCI_BAR_COUNT; i++) {
+ zdev->bars[i].val = le32_to_cpu(response->bar[i]);
+ zdev->bars[i].size = response->bar_size[i];
+ }
+ zdev->start_dma = response->sdma;
+ zdev->end_dma = response->edma;
+ zdev->pchid = response->pchid;
+ zdev->pfgid = response->pfgid;
+ return 0;
+}
+
+static int clp_query_pci_fn(struct zpci_dev *zdev, u32 fh)
+{
+ struct clp_req_rsp_query_pci *rrb;
+ int rc;
+
+ rrb = clp_alloc_block();
+ if (!rrb)
+ return -ENOMEM;
+
+ memset(rrb, 0, sizeof(*rrb));
+ rrb->request.hdr.len = sizeof(rrb->request);
+ rrb->request.hdr.cmd = CLP_QUERY_PCI_FN;
+ rrb->response.hdr.len = sizeof(rrb->response);
+ rrb->request.fh = fh;
+
+ rc = clp_instr(rrb);
+ if (!rc && rrb->response.hdr.rsp == CLP_RC_OK) {
+ rc = clp_store_query_pci_fn(zdev, &rrb->response);
+ if (rc)
+ goto out;
+ if (rrb->response.pfgid)
+ rc = clp_query_pci_fngrp(zdev, rrb->response.pfgid);
+ } else {
+ pr_err("Query PCI failed with response: %x cc: %d\n",
+ rrb->response.hdr.rsp, rc);
+ rc = -EIO;
+ }
+out:
+ clp_free_block(rrb);
+ return rc;
+}
+
+int clp_add_pci_device(u32 fid, u32 fh, int configured)
+{
+ struct zpci_dev *zdev;
+ int rc;
+
+ zdev = zpci_alloc_device();
+ if (IS_ERR(zdev))
+ return PTR_ERR(zdev);
+
+ zdev->fh = fh;
+ zdev->fid = fid;
+
+ /* Query function properties and update zdev */
+ rc = clp_query_pci_fn(zdev, fh);
+ if (rc)
+ goto error;
+
+ if (configured)
+ zdev->state = ZPCI_FN_STATE_CONFIGURED;
+ else
+ zdev->state = ZPCI_FN_STATE_STANDBY;
+
+ rc = zpci_create_device(zdev);
+ if (rc)
+ goto error;
+ return 0;
+
+error:
+ zpci_free_device(zdev);
+ return rc;
+}
+
+/*
+ * Enable/Disable a given PCI function defined by its function handle.
+ */
+static int clp_set_pci_fn(u32 *fh, u8 nr_dma_as, u8 command)
+{
+ struct clp_req_rsp_set_pci *rrb;
+ int rc, retries = 1000;
+
+ rrb = clp_alloc_block();
+ if (!rrb)
+ return -ENOMEM;
+
+ do {
+ memset(rrb, 0, sizeof(*rrb));
+ rrb->request.hdr.len = sizeof(rrb->request);
+ rrb->request.hdr.cmd = CLP_SET_PCI_FN;
+ rrb->response.hdr.len = sizeof(rrb->response);
+ rrb->request.fh = *fh;
+ rrb->request.oc = command;
+ rrb->request.ndas = nr_dma_as;
+
+ rc = clp_instr(rrb);
+ if (rrb->response.hdr.rsp == CLP_RC_SETPCIFN_BUSY) {
+ retries--;
+ if (retries < 0)
+ break;
+ msleep(1);
+ }
+ } while (rrb->response.hdr.rsp == CLP_RC_SETPCIFN_BUSY);
+
+ if (!rc && rrb->response.hdr.rsp == CLP_RC_OK)
+ *fh = rrb->response.fh;
+ else {
+ pr_err("Set PCI FN failed with response: %x cc: %d\n",
+ rrb->response.hdr.rsp, rc);
+ rc = -EIO;
+ }
+ clp_free_block(rrb);
+ return rc;
+}
+
+int clp_enable_fh(struct zpci_dev *zdev, u8 nr_dma_as)
+{
+ u32 fh = zdev->fh;
+ int rc;
+
+ rc = clp_set_pci_fn(&fh, nr_dma_as, CLP_SET_ENABLE_PCI_FN);
+ if (!rc)
+ /* Success -> store enabled handle in zdev */
+ zdev->fh = fh;
+ return rc;
+}
+
+int clp_disable_fh(struct zpci_dev *zdev)
+{
+ u32 fh = zdev->fh;
+ int rc;
+
+ if (!zdev_enabled(zdev))
+ return 0;
+
+ dev_info(&zdev->pdev->dev, "disabling fn handle: 0x%x\n", fh);
+ rc = clp_set_pci_fn(&fh, 0, CLP_SET_DISABLE_PCI_FN);
+ if (!rc)
+ /* Success -> store disabled handle in zdev */
+ zdev->fh = fh;
+ else
+ dev_err(&zdev->pdev->dev,
+ "Failed to disable fn handle: 0x%x\n", fh);
+ return rc;
+}
+
+static void clp_check_pcifn_entry(struct clp_fh_list_entry *entry)
+{
+ int present, rc;
+
+ if (!entry->vendor_id)
+ return;
+
+ /* TODO: be a little bit more scalable */
+ present = zpci_fid_present(entry->fid);
+
+ if (present)
+ pr_debug("%s: device %x already present\n", __func__, entry->fid);
+
+ /* skip already used functions */
+ if (present && entry->config_state)
+ return;
+
+ /* aev 306: function moved to stand-by state */
+ if (present && !entry->config_state) {
+ /*
+ * The handle is already disabled, that means no iota/irq freeing via
+ * the firmware interfaces anymore. Need to free resources manually
+ * (DMA memory, debug, sysfs)...
+ */
+ zpci_stop_device(get_zdev_by_fid(entry->fid));
+ return;
+ }
+
+ rc = clp_add_pci_device(entry->fid, entry->fh, entry->config_state);
+ if (rc)
+ pr_err("Failed to add fid: 0x%x\n", entry->fid);
+}
+
+int clp_find_pci_devices(void)
+{
+ struct clp_req_rsp_list_pci *rrb;
+ u64 resume_token = 0;
+ int entries, i, rc;
+
+ rrb = clp_alloc_block();
+ if (!rrb)
+ return -ENOMEM;
+
+ do {
+ memset(rrb, 0, sizeof(*rrb));
+ rrb->request.hdr.len = sizeof(rrb->request);
+ rrb->request.hdr.cmd = CLP_LIST_PCI;
+ /* store as many entries as possible */
+ rrb->response.hdr.len = CLP_BLK_SIZE - LIST_PCI_HDR_LEN;
+ rrb->request.resume_token = resume_token;
+
+ /* Get PCI function handle list */
+ rc = clp_instr(rrb);
+ if (rc || rrb->response.hdr.rsp != CLP_RC_OK) {
+ pr_err("List PCI failed with response: 0x%x cc: %d\n",
+ rrb->response.hdr.rsp, rc);
+ rc = -EIO;
+ goto out;
+ }
+
+ WARN_ON_ONCE(rrb->response.entry_size !=
+ sizeof(struct clp_fh_list_entry));
+
+ entries = (rrb->response.hdr.len - LIST_PCI_HDR_LEN) /
+ rrb->response.entry_size;
+ pr_info("Detected number of PCI functions: %u\n", entries);
+
+ /* Store the returned resume token as input for the next call */
+ resume_token = rrb->response.resume_token;
+
+ for (i = 0; i < entries; i++)
+ clp_check_pcifn_entry(&rrb->response.fh_list[i]);
+ } while (resume_token);
+
+ pr_debug("Maximum number of supported PCI functions: %u\n",
+ rrb->response.max_fn);
+out:
+ clp_free_block(rrb);
+ return rc;
+}
diff --git a/arch/s390/pci/pci_dma.c b/arch/s390/pci/pci_dma.c
new file mode 100644
index 000000000000..c64b4b294b0a
--- /dev/null
+++ b/arch/s390/pci/pci_dma.c
@@ -0,0 +1,506 @@
+/*
+ * Copyright IBM Corp. 2012
+ *
+ * Author(s):
+ * Jan Glauber <jang@linux.vnet.ibm.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/export.h>
+#include <linux/iommu-helper.h>
+#include <linux/dma-mapping.h>
+#include <linux/pci.h>
+#include <asm/pci_dma.h>
+
+static enum zpci_ioat_dtype zpci_ioat_dt = ZPCI_IOTA_RTTO;
+
+static struct kmem_cache *dma_region_table_cache;
+static struct kmem_cache *dma_page_table_cache;
+
+static unsigned long *dma_alloc_cpu_table(void)
+{
+ unsigned long *table, *entry;
+
+ table = kmem_cache_alloc(dma_region_table_cache, GFP_ATOMIC);
+ if (!table)
+ return NULL;
+
+ for (entry = table; entry < table + ZPCI_TABLE_ENTRIES; entry++)
+ *entry = ZPCI_TABLE_INVALID | ZPCI_TABLE_PROTECTED;
+ return table;
+}
+
+static void dma_free_cpu_table(void *table)
+{
+ kmem_cache_free(dma_region_table_cache, table);
+}
+
+static unsigned long *dma_alloc_page_table(void)
+{
+ unsigned long *table, *entry;
+
+ table = kmem_cache_alloc(dma_page_table_cache, GFP_ATOMIC);
+ if (!table)
+ return NULL;
+
+ for (entry = table; entry < table + ZPCI_PT_ENTRIES; entry++)
+ *entry = ZPCI_PTE_INVALID | ZPCI_TABLE_PROTECTED;
+ return table;
+}
+
+static void dma_free_page_table(void *table)
+{
+ kmem_cache_free(dma_page_table_cache, table);
+}
+
+static unsigned long *dma_get_seg_table_origin(unsigned long *entry)
+{
+ unsigned long *sto;
+
+ if (reg_entry_isvalid(*entry))
+ sto = get_rt_sto(*entry);
+ else {
+ sto = dma_alloc_cpu_table();
+ if (!sto)
+ return NULL;
+
+ set_rt_sto(entry, sto);
+ validate_rt_entry(entry);
+ entry_clr_protected(entry);
+ }
+ return sto;
+}
+
+static unsigned long *dma_get_page_table_origin(unsigned long *entry)
+{
+ unsigned long *pto;
+
+ if (reg_entry_isvalid(*entry))
+ pto = get_st_pto(*entry);
+ else {
+ pto = dma_alloc_page_table();
+ if (!pto)
+ return NULL;
+ set_st_pto(entry, pto);
+ validate_st_entry(entry);
+ entry_clr_protected(entry);
+ }
+ return pto;
+}
+
+static unsigned long *dma_walk_cpu_trans(unsigned long *rto, dma_addr_t dma_addr)
+{
+ unsigned long *sto, *pto;
+ unsigned int rtx, sx, px;
+
+ rtx = calc_rtx(dma_addr);
+ sto = dma_get_seg_table_origin(&rto[rtx]);
+ if (!sto)
+ return NULL;
+
+ sx = calc_sx(dma_addr);
+ pto = dma_get_page_table_origin(&sto[sx]);
+ if (!pto)
+ return NULL;
+
+ px = calc_px(dma_addr);
+ return &pto[px];
+}
+
+static void dma_update_cpu_trans(struct zpci_dev *zdev, void *page_addr,
+ dma_addr_t dma_addr, int flags)
+{
+ unsigned long *entry;
+
+ entry = dma_walk_cpu_trans(zdev->dma_table, dma_addr);
+ if (!entry) {
+ WARN_ON_ONCE(1);
+ return;
+ }
+
+ if (flags & ZPCI_PTE_INVALID) {
+ invalidate_pt_entry(entry);
+ return;
+ } else {
+ set_pt_pfaa(entry, page_addr);
+ validate_pt_entry(entry);
+ }
+
+ if (flags & ZPCI_TABLE_PROTECTED)
+ entry_set_protected(entry);
+ else
+ entry_clr_protected(entry);
+}
+
+static int dma_update_trans(struct zpci_dev *zdev, unsigned long pa,
+ dma_addr_t dma_addr, size_t size, int flags)
+{
+ unsigned int nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
+ u8 *page_addr = (u8 *) (pa & PAGE_MASK);
+ dma_addr_t start_dma_addr = dma_addr;
+ unsigned long irq_flags;
+ int i, rc = 0;
+
+ if (!nr_pages)
+ return -EINVAL;
+
+ spin_lock_irqsave(&zdev->dma_table_lock, irq_flags);
+ if (!zdev->dma_table) {
+ dev_err(&zdev->pdev->dev, "Missing DMA table\n");
+ goto no_refresh;
+ }
+
+ for (i = 0; i < nr_pages; i++) {
+ dma_update_cpu_trans(zdev, page_addr, dma_addr, flags);
+ page_addr += PAGE_SIZE;
+ dma_addr += PAGE_SIZE;
+ }
+
+ /*
+ * rpcit is not required to establish new translations when previously
+ * invalid translation-table entries are validated, however it is
+ * required when altering previously valid entries.
+ */
+ if (!zdev->tlb_refresh &&
+ ((flags & ZPCI_PTE_VALID_MASK) == ZPCI_PTE_VALID))
+ /*
+ * TODO: also need to check that the old entry is indeed INVALID
+ * and not only for one page but for the whole range...
+ * -> now we WARN_ON in that case but with lazy unmap that
+ * needs to be redone!
+ */
+ goto no_refresh;
+ rc = rpcit_instr((u64) zdev->fh << 32, start_dma_addr,
+ nr_pages * PAGE_SIZE);
+
+no_refresh:
+ spin_unlock_irqrestore(&zdev->dma_table_lock, irq_flags);
+ return rc;
+}
+
+static void dma_free_seg_table(unsigned long entry)
+{
+ unsigned long *sto = get_rt_sto(entry);
+ int sx;
+
+ for (sx = 0; sx < ZPCI_TABLE_ENTRIES; sx++)
+ if (reg_entry_isvalid(sto[sx]))
+ dma_free_page_table(get_st_pto(sto[sx]));
+
+ dma_free_cpu_table(sto);
+}
+
+static void dma_cleanup_tables(struct zpci_dev *zdev)
+{
+ unsigned long *table;
+ int rtx;
+
+ if (!zdev || !zdev->dma_table)
+ return;
+
+ table = zdev->dma_table;
+ for (rtx = 0; rtx < ZPCI_TABLE_ENTRIES; rtx++)
+ if (reg_entry_isvalid(table[rtx]))
+ dma_free_seg_table(table[rtx]);
+
+ dma_free_cpu_table(table);
+ zdev->dma_table = NULL;
+}
+
+static unsigned long __dma_alloc_iommu(struct zpci_dev *zdev, unsigned long start,
+ int size)
+{
+ unsigned long boundary_size = 0x1000000;
+
+ return iommu_area_alloc(zdev->iommu_bitmap, zdev->iommu_pages,
+ start, size, 0, boundary_size, 0);
+}
+
+static unsigned long dma_alloc_iommu(struct zpci_dev *zdev, int size)
+{
+ unsigned long offset, flags;
+
+ spin_lock_irqsave(&zdev->iommu_bitmap_lock, flags);
+ offset = __dma_alloc_iommu(zdev, zdev->next_bit, size);
+ if (offset == -1)
+ offset = __dma_alloc_iommu(zdev, 0, size);
+
+ if (offset != -1) {
+ zdev->next_bit = offset + size;
+ if (zdev->next_bit >= zdev->iommu_pages)
+ zdev->next_bit = 0;
+ }
+ spin_unlock_irqrestore(&zdev->iommu_bitmap_lock, flags);
+ return offset;
+}
+
+static void dma_free_iommu(struct zpci_dev *zdev, unsigned long offset, int size)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&zdev->iommu_bitmap_lock, flags);
+ if (!zdev->iommu_bitmap)
+ goto out;
+ bitmap_clear(zdev->iommu_bitmap, offset, size);
+ if (offset >= zdev->next_bit)
+ zdev->next_bit = offset + size;
+out:
+ spin_unlock_irqrestore(&zdev->iommu_bitmap_lock, flags);
+}
+
+int dma_set_mask(struct device *dev, u64 mask)
+{
+ if (!dev->dma_mask || !dma_supported(dev, mask))
+ return -EIO;
+
+ *dev->dma_mask = mask;
+ return 0;
+}
+EXPORT_SYMBOL_GPL(dma_set_mask);
+
+static dma_addr_t s390_dma_map_pages(struct device *dev, struct page *page,
+ unsigned long offset, size_t size,
+ enum dma_data_direction direction,
+ struct dma_attrs *attrs)
+{
+ struct zpci_dev *zdev = get_zdev(container_of(dev, struct pci_dev, dev));
+ unsigned long nr_pages, iommu_page_index;
+ unsigned long pa = page_to_phys(page) + offset;
+ int flags = ZPCI_PTE_VALID;
+ dma_addr_t dma_addr;
+
+ WARN_ON_ONCE(offset > PAGE_SIZE);
+
+ /* This rounds up number of pages based on size and offset */
+ nr_pages = iommu_num_pages(pa, size, PAGE_SIZE);
+ iommu_page_index = dma_alloc_iommu(zdev, nr_pages);
+ if (iommu_page_index == -1)
+ goto out_err;
+
+ /* Use rounded up size */
+ size = nr_pages * PAGE_SIZE;
+
+ dma_addr = zdev->start_dma + iommu_page_index * PAGE_SIZE;
+ if (dma_addr + size > zdev->end_dma) {
+ dev_err(dev, "(dma_addr: 0x%16.16LX + size: 0x%16.16lx) > end_dma: 0x%16.16Lx\n",
+ dma_addr, size, zdev->end_dma);
+ goto out_free;
+ }
+
+ if (direction == DMA_NONE || direction == DMA_TO_DEVICE)
+ flags |= ZPCI_TABLE_PROTECTED;
+
+ if (!dma_update_trans(zdev, pa, dma_addr, size, flags))
+ return dma_addr + offset;
+
+out_free:
+ dma_free_iommu(zdev, iommu_page_index, nr_pages);
+out_err:
+ dev_err(dev, "Failed to map addr: %lx\n", pa);
+ return DMA_ERROR_CODE;
+}
+
+static void s390_dma_unmap_pages(struct device *dev, dma_addr_t dma_addr,
+ size_t size, enum dma_data_direction direction,
+ struct dma_attrs *attrs)
+{
+ struct zpci_dev *zdev = get_zdev(container_of(dev, struct pci_dev, dev));
+ unsigned long iommu_page_index;
+ int npages;
+
+ npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
+ dma_addr = dma_addr & PAGE_MASK;
+ if (dma_update_trans(zdev, 0, dma_addr, npages * PAGE_SIZE,
+ ZPCI_TABLE_PROTECTED | ZPCI_PTE_INVALID))
+ dev_err(dev, "Failed to unmap addr: %Lx\n", dma_addr);
+
+ iommu_page_index = (dma_addr - zdev->start_dma) >> PAGE_SHIFT;
+ dma_free_iommu(zdev, iommu_page_index, npages);
+}
+
+static void *s390_dma_alloc(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t flag,
+ struct dma_attrs *attrs)
+{
+ struct page *page;
+ unsigned long pa;
+ dma_addr_t map;
+
+ size = PAGE_ALIGN(size);
+ page = alloc_pages(flag, get_order(size));
+ if (!page)
+ return NULL;
+ pa = page_to_phys(page);
+ memset((void *) pa, 0, size);
+
+ map = s390_dma_map_pages(dev, page, pa % PAGE_SIZE,
+ size, DMA_BIDIRECTIONAL, NULL);
+ if (dma_mapping_error(dev, map)) {
+ free_pages(pa, get_order(size));
+ return NULL;
+ }
+
+ if (dma_handle)
+ *dma_handle = map;
+ return (void *) pa;
+}
+
+static void s390_dma_free(struct device *dev, size_t size,
+ void *pa, dma_addr_t dma_handle,
+ struct dma_attrs *attrs)
+{
+ s390_dma_unmap_pages(dev, dma_handle, PAGE_ALIGN(size),
+ DMA_BIDIRECTIONAL, NULL);
+ free_pages((unsigned long) pa, get_order(size));
+}
+
+static int s390_dma_map_sg(struct device *dev, struct scatterlist *sg,
+ int nr_elements, enum dma_data_direction dir,
+ struct dma_attrs *attrs)
+{
+ int mapped_elements = 0;
+ struct scatterlist *s;
+ int i;
+
+ for_each_sg(sg, s, nr_elements, i) {
+ struct page *page = sg_page(s);
+ s->dma_address = s390_dma_map_pages(dev, page, s->offset,
+ s->length, dir, NULL);
+ if (!dma_mapping_error(dev, s->dma_address)) {
+ s->dma_length = s->length;
+ mapped_elements++;
+ } else
+ goto unmap;
+ }
+out:
+ return mapped_elements;
+
+unmap:
+ for_each_sg(sg, s, mapped_elements, i) {
+ if (s->dma_address)
+ s390_dma_unmap_pages(dev, s->dma_address, s->dma_length,
+ dir, NULL);
+ s->dma_address = 0;
+ s->dma_length = 0;
+ }
+ mapped_elements = 0;
+ goto out;
+}
+
+static void s390_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+ int nr_elements, enum dma_data_direction dir,
+ struct dma_attrs *attrs)
+{
+ struct scatterlist *s;
+ int i;
+
+ for_each_sg(sg, s, nr_elements, i) {
+ s390_dma_unmap_pages(dev, s->dma_address, s->dma_length, dir, NULL);
+ s->dma_address = 0;
+ s->dma_length = 0;
+ }
+}
+
+int zpci_dma_init_device(struct zpci_dev *zdev)
+{
+ unsigned int bitmap_order;
+ int rc;
+
+ spin_lock_init(&zdev->iommu_bitmap_lock);
+ spin_lock_init(&zdev->dma_table_lock);
+
+ zdev->dma_table = dma_alloc_cpu_table();
+ if (!zdev->dma_table) {
+ rc = -ENOMEM;
+ goto out_clean;
+ }
+
+ zdev->iommu_size = (unsigned long) high_memory - PAGE_OFFSET;
+ zdev->iommu_pages = zdev->iommu_size >> PAGE_SHIFT;
+ bitmap_order = get_order(zdev->iommu_pages / 8);
+ pr_info("iommu_size: 0x%lx iommu_pages: 0x%lx bitmap_order: %i\n",
+ zdev->iommu_size, zdev->iommu_pages, bitmap_order);
+
+ zdev->iommu_bitmap = (void *) __get_free_pages(GFP_KERNEL | __GFP_ZERO,
+ bitmap_order);
+ if (!zdev->iommu_bitmap) {
+ rc = -ENOMEM;
+ goto out_reg;
+ }
+
+ rc = zpci_register_ioat(zdev,
+ 0,
+ zdev->start_dma + PAGE_OFFSET,
+ zdev->start_dma + zdev->iommu_size - 1,
+ (u64) zdev->dma_table);
+ if (rc)
+ goto out_reg;
+ return 0;
+
+out_reg:
+ dma_free_cpu_table(zdev->dma_table);
+out_clean:
+ return rc;
+}
+
+void zpci_dma_exit_device(struct zpci_dev *zdev)
+{
+ zpci_unregister_ioat(zdev, 0);
+ dma_cleanup_tables(zdev);
+ free_pages((unsigned long) zdev->iommu_bitmap,
+ get_order(zdev->iommu_pages / 8));
+ zdev->iommu_bitmap = NULL;
+ zdev->next_bit = 0;
+}
+
+static int __init dma_alloc_cpu_table_caches(void)
+{
+ dma_region_table_cache = kmem_cache_create("PCI_DMA_region_tables",
+ ZPCI_TABLE_SIZE, ZPCI_TABLE_ALIGN,
+ 0, NULL);
+ if (!dma_region_table_cache)
+ return -ENOMEM;
+
+ dma_page_table_cache = kmem_cache_create("PCI_DMA_page_tables",
+ ZPCI_PT_SIZE, ZPCI_PT_ALIGN,
+ 0, NULL);
+ if (!dma_page_table_cache) {
+ kmem_cache_destroy(dma_region_table_cache);
+ return -ENOMEM;
+ }
+ return 0;
+}
+
+int __init zpci_dma_init(void)
+{
+ return dma_alloc_cpu_table_caches();
+}
+
+void zpci_dma_exit(void)
+{
+ kmem_cache_destroy(dma_page_table_cache);
+ kmem_cache_destroy(dma_region_table_cache);
+}
+
+#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
+
+static int __init dma_debug_do_init(void)
+{
+ dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
+ return 0;
+}
+fs_initcall(dma_debug_do_init);
+
+struct dma_map_ops s390_dma_ops = {
+ .alloc = s390_dma_alloc,
+ .free = s390_dma_free,
+ .map_sg = s390_dma_map_sg,
+ .unmap_sg = s390_dma_unmap_sg,
+ .map_page = s390_dma_map_pages,
+ .unmap_page = s390_dma_unmap_pages,
+ /* if we support direct DMA this must be conditional */
+ .is_phys = 0,
+ /* dma_supported is unconditionally true without a callback */
+};
+EXPORT_SYMBOL_GPL(s390_dma_ops);
diff --git a/arch/s390/pci/pci_event.c b/arch/s390/pci/pci_event.c
new file mode 100644
index 000000000000..dbed8cd3370c
--- /dev/null
+++ b/arch/s390/pci/pci_event.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright IBM Corp. 2012
+ *
+ * Author(s):
+ * Jan Glauber <jang@linux.vnet.ibm.com>
+ */
+
+#define COMPONENT "zPCI"
+#define pr_fmt(fmt) COMPONENT ": " fmt
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+
+/* Content Code Description for PCI Function Error */
+struct zpci_ccdf_err {
+ u32 reserved1;
+ u32 fh; /* function handle */
+ u32 fid; /* function id */
+ u32 ett : 4; /* expected table type */
+ u32 mvn : 12; /* MSI vector number */
+ u32 dmaas : 8; /* DMA address space */
+ u32 : 6;
+ u32 q : 1; /* event qualifier */
+ u32 rw : 1; /* read/write */
+ u64 faddr; /* failing address */
+ u32 reserved3;
+ u16 reserved4;
+ u16 pec; /* PCI event code */
+} __packed;
+
+/* Content Code Description for PCI Function Availability */
+struct zpci_ccdf_avail {
+ u32 reserved1;
+ u32 fh; /* function handle */
+ u32 fid; /* function id */
+ u32 reserved2;
+ u32 reserved3;
+ u32 reserved4;
+ u32 reserved5;
+ u16 reserved6;
+ u16 pec; /* PCI event code */
+} __packed;
+
+static void zpci_event_log_err(struct zpci_ccdf_err *ccdf)
+{
+ struct zpci_dev *zdev = get_zdev_by_fid(ccdf->fid);
+
+ dev_err(&zdev->pdev->dev, "event code: 0x%x\n", ccdf->pec);
+}
+
+static void zpci_event_log_avail(struct zpci_ccdf_avail *ccdf)
+{
+ struct zpci_dev *zdev = get_zdev_by_fid(ccdf->fid);
+
+ pr_err("%s%s: availability event: fh: 0x%x fid: 0x%x event code: 0x%x reason:",
+ (zdev) ? dev_driver_string(&zdev->pdev->dev) : "?",
+ (zdev) ? dev_name(&zdev->pdev->dev) : "?",
+ ccdf->fh, ccdf->fid, ccdf->pec);
+ print_hex_dump(KERN_CONT, "ccdf", DUMP_PREFIX_OFFSET,
+ 16, 1, ccdf, sizeof(*ccdf), false);
+
+ switch (ccdf->pec) {
+ case 0x0301:
+ zpci_enable_device(zdev);
+ break;
+ case 0x0302:
+ clp_add_pci_device(ccdf->fid, ccdf->fh, 0);
+ break;
+ case 0x0306:
+ clp_find_pci_devices();
+ break;
+ default:
+ break;
+ }
+}
+
+void zpci_event_error(void *data)
+{
+ struct zpci_ccdf_err *ccdf = data;
+ struct zpci_dev *zdev;
+
+ zpci_event_log_err(ccdf);
+ zdev = get_zdev_by_fid(ccdf->fid);
+ if (!zdev) {
+ pr_err("Error event for unknown fid: %x", ccdf->fid);
+ return;
+ }
+}
+
+void zpci_event_availability(void *data)
+{
+ zpci_event_log_avail(data);
+}
diff --git a/arch/s390/pci/pci_msi.c b/arch/s390/pci/pci_msi.c
new file mode 100644
index 000000000000..90fd3482b9e2
--- /dev/null
+++ b/arch/s390/pci/pci_msi.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright IBM Corp. 2012
+ *
+ * Author(s):
+ * Jan Glauber <jang@linux.vnet.ibm.com>
+ */
+
+#define COMPONENT "zPCI"
+#define pr_fmt(fmt) COMPONENT ": " fmt
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/rculist.h>
+#include <linux/hash.h>
+#include <linux/pci.h>
+#include <linux/msi.h>
+#include <asm/hw_irq.h>
+
+/* mapping of irq numbers to msi_desc */
+static struct hlist_head *msi_hash;
+static unsigned int msihash_shift = 6;
+#define msi_hashfn(nr) hash_long(nr, msihash_shift)
+
+static DEFINE_SPINLOCK(msi_map_lock);
+
+struct msi_desc *__irq_get_msi_desc(unsigned int irq)
+{
+ struct hlist_node *entry;
+ struct msi_map *map;
+
+ hlist_for_each_entry_rcu(map, entry,
+ &msi_hash[msi_hashfn(irq)], msi_chain)
+ if (map->irq == irq)
+ return map->msi;
+ return NULL;
+}
+
+int zpci_msi_set_mask_bits(struct msi_desc *msi, u32 mask, u32 flag)
+{
+ if (msi->msi_attrib.is_msix) {
+ int offset = msi->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
+ PCI_MSIX_ENTRY_VECTOR_CTRL;
+ msi->masked = readl(msi->mask_base + offset);
+ writel(flag, msi->mask_base + offset);
+ } else {
+ if (msi->msi_attrib.maskbit) {
+ int pos;
+ u32 mask_bits;
+
+ pos = (long) msi->mask_base;
+ pci_read_config_dword(msi->dev, pos, &mask_bits);
+ mask_bits &= ~(mask);
+ mask_bits |= flag & mask;
+ pci_write_config_dword(msi->dev, pos, mask_bits);
+ } else {
+ return 0;
+ }
+ }
+
+ msi->msi_attrib.maskbit = !!flag;
+ return 1;
+}
+
+int zpci_setup_msi_irq(struct zpci_dev *zdev, struct msi_desc *msi,
+ unsigned int nr, int offset)
+{
+ struct msi_map *map;
+ struct msi_msg msg;
+ int rc;
+
+ map = kmalloc(sizeof(*map), GFP_KERNEL);
+ if (map == NULL)
+ return -ENOMEM;
+
+ map->irq = nr;
+ map->msi = msi;
+ zdev->msi_map[nr & ZPCI_MSI_MASK] = map;
+
+ pr_debug("%s hashing irq: %u to bucket nr: %llu\n",
+ __func__, nr, msi_hashfn(nr));
+ hlist_add_head_rcu(&map->msi_chain, &msi_hash[msi_hashfn(nr)]);
+
+ spin_lock(&msi_map_lock);
+ rc = irq_set_msi_desc(nr, msi);
+ if (rc) {
+ spin_unlock(&msi_map_lock);
+ hlist_del_rcu(&map->msi_chain);
+ kfree(map);
+ zdev->msi_map[nr & ZPCI_MSI_MASK] = NULL;
+ return rc;
+ }
+ spin_unlock(&msi_map_lock);
+
+ msg.data = nr - offset;
+ msg.address_lo = zdev->msi_addr & 0xffffffff;
+ msg.address_hi = zdev->msi_addr >> 32;
+ write_msi_msg(nr, &msg);
+ return 0;
+}
+
+void zpci_teardown_msi_irq(struct zpci_dev *zdev, struct msi_desc *msi)
+{
+ int irq = msi->irq & ZPCI_MSI_MASK;
+ struct msi_map *map;
+
+ msi->msg.address_lo = 0;
+ msi->msg.address_hi = 0;
+ msi->msg.data = 0;
+ msi->irq = 0;
+ zpci_msi_set_mask_bits(msi, 1, 1);
+
+ spin_lock(&msi_map_lock);
+ map = zdev->msi_map[irq];
+ hlist_del_rcu(&map->msi_chain);
+ kfree(map);
+ zdev->msi_map[irq] = NULL;
+ spin_unlock(&msi_map_lock);
+}
+
+/*
+ * The msi hash table has 256 entries which is good for 4..20
+ * devices (a typical device allocates 10 + CPUs MSI's). Maybe make
+ * the hash table size adjustable later.
+ */
+int __init zpci_msihash_init(void)
+{
+ unsigned int i;
+
+ msi_hash = kmalloc(256 * sizeof(*msi_hash), GFP_KERNEL);
+ if (!msi_hash)
+ return -ENOMEM;
+
+ for (i = 0; i < (1U << msihash_shift); i++)
+ INIT_HLIST_HEAD(&msi_hash[i]);
+ return 0;
+}
+
+void __init zpci_msihash_exit(void)
+{
+ kfree(msi_hash);
+}
diff --git a/arch/s390/pci/pci_sysfs.c b/arch/s390/pci/pci_sysfs.c
new file mode 100644
index 000000000000..a42cce69d0a0
--- /dev/null
+++ b/arch/s390/pci/pci_sysfs.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright IBM Corp. 2012
+ *
+ * Author(s):
+ * Jan Glauber <jang@linux.vnet.ibm.com>
+ */
+
+#define COMPONENT "zPCI"
+#define pr_fmt(fmt) COMPONENT ": " fmt
+
+#include <linux/kernel.h>
+#include <linux/stat.h>
+#include <linux/pci.h>
+
+static ssize_t show_fid(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct zpci_dev *zdev = get_zdev(container_of(dev, struct pci_dev, dev));
+
+ sprintf(buf, "0x%08x\n", zdev->fid);
+ return strlen(buf);
+}
+static DEVICE_ATTR(function_id, S_IRUGO, show_fid, NULL);
+
+static ssize_t show_fh(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct zpci_dev *zdev = get_zdev(container_of(dev, struct pci_dev, dev));
+
+ sprintf(buf, "0x%08x\n", zdev->fh);
+ return strlen(buf);
+}
+static DEVICE_ATTR(function_handle, S_IRUGO, show_fh, NULL);
+
+static ssize_t show_pchid(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct zpci_dev *zdev = get_zdev(container_of(dev, struct pci_dev, dev));
+
+ sprintf(buf, "0x%04x\n", zdev->pchid);
+ return strlen(buf);
+}
+static DEVICE_ATTR(pchid, S_IRUGO, show_pchid, NULL);
+
+static ssize_t show_pfgid(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct zpci_dev *zdev = get_zdev(container_of(dev, struct pci_dev, dev));
+
+ sprintf(buf, "0x%02x\n", zdev->pfgid);
+ return strlen(buf);
+}
+static DEVICE_ATTR(pfgid, S_IRUGO, show_pfgid, NULL);
+
+static struct device_attribute *zpci_dev_attrs[] = {
+ &dev_attr_function_id,
+ &dev_attr_function_handle,
+ &dev_attr_pchid,
+ &dev_attr_pfgid,
+ NULL,
+};
+
+int zpci_sysfs_add_device(struct device *dev)
+{
+ int i, rc = 0;
+
+ for (i = 0; zpci_dev_attrs[i]; i++) {
+ rc = device_create_file(dev, zpci_dev_attrs[i]);
+ if (rc)
+ goto error;
+ }
+ return 0;
+
+error:
+ while (--i >= 0)
+ device_remove_file(dev, zpci_dev_attrs[i]);
+ return rc;
+}
+
+void zpci_sysfs_remove_device(struct device *dev)
+{
+ int i;
+
+ for (i = 0; zpci_dev_attrs[i]; i++)
+ device_remove_file(dev, zpci_dev_attrs[i]);
+}
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-30 22:12:45 +0300