diff options
Diffstat (limited to 'arch/powerpc/boot')
| -rw-r--r-- | arch/powerpc/boot/dts/pcm030.dts | 363 |
1 files changed, 363 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts new file mode 100644 index 000000000000..7c1bb952360c --- /dev/null +++ b/arch/powerpc/boot/dts/pcm030.dts @@ -0,0 +1,363 @@ +/* + * phyCORE-MPC5200B-tiny (pcm030) board Device Tree Source + * + * Copyright 2006 Pengutronix + * Sascha Hauer <s.hauer@pengutronix.de> + * Copyright 2007 Pengutronix + * Juergen Beisert <j.beisert@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + model = "phytec,pcm030"; + compatible = "phytec,pcm030"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,5200@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <0x4000>; /* L1, 16K */ + i-cache-size = <0x4000>; /* L1, 16K */ + timebase-frequency = <0>; /* From Bootloader */ + bus-frequency = <0>; /* From Bootloader */ + clock-frequency = <0>; /* From Bootloader */ + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x04000000>; /* 64MB */ + }; + + soc5200@f0000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc5200b-immr"; + ranges = <0x0 0xf0000000 0x0000c000>; + bus-frequency = <0>; /* From bootloader */ + system-frequency = <0>; /* From bootloader */ + + cdm@200 { + compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; + reg = <0x200 0x38>; + }; + + mpc5200_pic: interrupt-controller@500 { + /* 5200 interrupts are encoded into two levels; */ + interrupt-controller; + #interrupt-cells = <3>; + device_type = "interrupt-controller"; + compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; + reg = <0x500 0x80>; + }; + + timer@600 { /* General Purpose Timer */ + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; + cell-index = <0>; + reg = <0x600 0x10>; + interrupts = <0x1 0x9 0x0>; + interrupt-parent = <&mpc5200_pic>; + fsl,has-wdt; + }; + + timer@610 { /* General Purpose Timer */ + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; + cell-index = <1>; + reg = <0x610 0x10>; + interrupts = <0x1 0xa 0x0>; + interrupt-parent = <&mpc5200_pic>; + }; + + gpt2: timer@620 { /* General Purpose Timer in GPIO mode */ + compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; + cell-index = <2>; + reg = <0x620 0x10>; + interrupts = <0x1 0xb 0x0>; + interrupt-parent = <&mpc5200_pic>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpt3: timer@630 { /* General Purpose Timer in GPIO mode */ + compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; + cell-index = <3>; + reg = <0x630 0x10>; + interrupts = <0x1 0xc 0x0>; + interrupt-parent = <&mpc5200_pic>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpt4: timer@640 { /* General Purpose Timer in GPIO mode */ + compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; + cell-index = <4>; + reg = <0x640 0x10>; + interrupts = <0x1 0xd 0x0>; + interrupt-parent = <&mpc5200_pic>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpt5: timer@650 { /* General Purpose Timer in GPIO mode */ + compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; + cell-index = <5>; + reg = <0x650 0x10>; + interrupts = <0x1 0xe 0x0>; + interrupt-parent = <&mpc5200_pic>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpt6: timer@660 { /* General Purpose Timer in GPIO mode */ + compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; + cell-index = <6>; + reg = <0x660 0x10>; + interrupts = <0x1 0xf 0x0>; + interrupt-parent = <&mpc5200_pic>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpt7: timer@670 { /* General Purpose Timer in GPIO mode */ + compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; + cell-index = <7>; + reg = <0x670 0x10>; + interrupts = <0x1 0x10 0x0>; + interrupt-parent = <&mpc5200_pic>; + gpio-controller; + #gpio-cells = <2>; + }; + + rtc@800 { // Real time clock + compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; + device_type = "rtc"; + reg = <0x800 0x100>; + interrupts = <0x1 0x5 0x0 0x1 0x6 0x0>; + interrupt-parent = <&mpc5200_pic>; + }; + + can@900 { + compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; + cell-index = <0>; + interrupts = <0x2 0x11 0x0>; + interrupt-parent = <&mpc5200_pic>; + reg = <0x900 0x80>; + }; + + can@980 { + compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; + cell-index = <1>; + interrupts = <0x2 0x12 0x0>; + interrupt-parent = <&mpc5200_pic>; + reg = <0x980 0x80>; + }; + + gpio_simple: gpio@b00 { + compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; + reg = <0xb00 0x40>; + interrupts = <0x1 0x7 0x0>; + interrupt-parent = <&mpc5200_pic>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio_wkup: gpio-wkup@c00 { + compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; + reg = <0xc00 0x40>; + interrupts = <0x1 0x8 0x0 0x0 0x3 0x0>; + interrupt-parent = <&mpc5200_pic>; + gpio-controller; + #gpio-cells = <2>; + }; + + spi@f00 { + compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; + reg = <0xf00 0x20>; + interrupts = <0x2 0xd 0x0 0x2 0xe 0x0>; + interrupt-parent = <&mpc5200_pic>; + }; + + usb@1000 { + compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; + reg = <0x1000 0xff>; + interrupts = <0x2 0x6 0x0>; + interrupt-parent = <&mpc5200_pic>; + }; + + dma-controller@1200 { + device_type = "dma-controller"; + compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; + reg = <0x1200 0x80>; + interrupts = <0x3 0x0 0x0 0x3 0x1 0x0 0x3 0x2 0x0 0x3 0x3 0x0 + 0x3 0x4 0x0 0x3 0x5 0x0 0x3 0x6 0x0 0x3 0x7 0x0 + 0x3 0x8 0x0 0x3 0x9 0x0 0x3 0xa 0x0 0x3 0xb 0x0 + 0x3 0xc 0x0 0x3 0xd 0x0 0x3 0xe 0x0 0x3 0xf 0x0>; + interrupt-parent = <&mpc5200_pic>; + }; + + xlb@1f00 { + compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; + reg = <0x1f00 0x100>; + }; + + ac97@2000 { /* PSC1 in ac97 mode */ + device_type = "sound"; + compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97"; + cell-index = <0>; + reg = <0x2000 0x100>; + interrupts = <0x2 0x2 0x0>; + interrupt-parent = <&mpc5200_pic>; + }; + + /* PSC2 port is used by CAN1/2 */ + + serial@2400 { /* PSC3 in UART mode */ + device_type = "serial"; + compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; + port-number = <0>; + cell-index = <2>; + reg = <0x2400 0x100>; + interrupts = <0x2 0x3 0x0>; + interrupt-parent = <&mpc5200_pic>; + }; + + /* PSC4 is ??? */ + + /* PSC5 is ??? */ + + serial@2c00 { /* PSC6 in UART mode */ + device_type = "serial"; + compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; + port-number = <1>; + cell-index = <5>; + reg = <0x2c00 0x100>; + interrupts = <0x2 0x4 0x0>; + interrupt-parent = <&mpc5200_pic>; + }; + + ethernet@3000 { + device_type = "network"; + compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; + reg = <0x3000 0x400>; + local-mac-address = [00 00 00 00 00 00]; + interrupts = <0x2 0x5 0x0>; + interrupt-parent = <&mpc5200_pic>; + phy-handle = <&phy0>; + }; + + mdio@3000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio"; + reg = <0x3000 0x400>; /* fec range, since we need to setup fec interrupts */ + interrupts = <0x2 0x5 0x0>; /* these are for "mii command finished", not link changes & co. */ + interrupt-parent = <&mpc5200_pic>; + + phy0:ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <0x0>; + }; + }; + + ata@3a00 { + device_type = "ata"; + compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; + reg = <0x3a00 0x100>; + interrupts = <0x2 0x7 0x0>; + interrupt-parent = <&mpc5200_pic>; + }; + + i2c@3d00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; + cell-index = <0>; + reg = <0x3d00 0x40>; + interrupts = <0x2 0xf 0x0>; + interrupt-parent = <&mpc5200_pic>; + fsl5200-clocking; + }; + + i2c@3d40 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; + cell-index = <1>; + reg = <0x3d40 0x40>; + interrupts = <0x2 0x10 0x0>; + interrupt-parent = <&mpc5200_pic>; + fsl5200-clocking; + rtc@51 { + device_type = "rtc"; + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + /* FIXME: EEPROM */ + }; + + sram@8000 { + compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram"; + reg = <0x8000 0x4000>; + }; + + /* This is only an example device to show the usage of gpios. It maps all available + * gpios to the "gpio-provider" device. + */ + gpio { + compatible = "gpio-provider"; + + /* mpc52xx exp.con patchfield */ + gpios = <&gpio_wkup 0 0 /* GPIO_WKUP_7 11d jp13-3 */ + &gpio_wkup 1 0 /* GPIO_WKUP_6 14c */ + &gpio_wkup 6 0 /* PSC2_4 43c x5-11 */ + &gpio_simple 2 0 /* IRDA_1 24c x7-6 set GPS_PORT_CONFIG[IRDA] = 0 */ + &gpio_simple 3 0 /* IRDA_0 x8-5 set GPS_PORT_CONFIG[IRDA] = 0 */ + &gpt2 0 0 /* timer2 12d x4-4 */ + &gpt3 0 0 /* timer3 13d x6-4 */ + &gpt4 0 0 /* timer4 61c x2-16 */ + &gpt5 0 0 /* timer5 44c x7-11 */ + &gpt6 0 0 /* timer6 60c x8-15 */ + &gpt7 0 0 /* timer7 36a x17-9 */ + >; + }; + }; + + pci@f0000d00 { + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; + reg = <0xf0000d00 0x100>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = <0xc000 0x0 0x0 0x1 &mpc5200_pic 0x0 0x0 0x3 /* 1st slot */ + 0xc000 0x0 0x0 0x2 &mpc5200_pic 0x1 0x1 0x3 + 0xc000 0x0 0x0 0x3 &mpc5200_pic 0x1 0x2 0x3 + 0xc000 0x0 0x0 0x4 &mpc5200_pic 0x1 0x3 0x3 + + 0xc800 0x0 0x0 0x1 &mpc5200_pic 0x1 0x1 0x3 /* 2nd slot */ + 0xc800 0x0 0x0 0x2 &mpc5200_pic 0x1 0x2 0x3 + 0xc800 0x0 0x0 0x3 &mpc5200_pic 0x1 0x3 0x3 + 0xc800 0x0 0x0 0x4 &mpc5200_pic 0x0 0x0 0x3>; + clock-frequency = <0>; // From boot loader + interrupts = <0x2 0x8 0x0 0x2 0x9 0x0 0x2 0xa 0x0>; + interrupt-parent = <&mpc5200_pic>; + bus-range = <0 0>; + ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000 + 0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 + 0x01000000 0x0 0x00000000 0xb0000000 0x0 0x01000000>; + }; +}; |