diff options
Diffstat (limited to 'arch/parisc/kernel/pci.c')
| -rw-r--r-- | arch/parisc/kernel/pci.c | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/arch/parisc/kernel/pci.c b/arch/parisc/kernel/pci.c index 64f2764a8cef..0903c6abd7a4 100644 --- a/arch/parisc/kernel/pci.c +++ b/arch/parisc/kernel/pci.c @@ -170,23 +170,31 @@ void pcibios_set_master(struct pci_dev *dev) (0x80 << 8) | pci_cache_line_size); } - -void __init pcibios_init_bus(struct pci_bus *bus) +/* + * pcibios_init_bridge() initializes cache line and default latency + * for pci controllers and pci-pci bridges + */ +void __init pcibios_init_bridge(struct pci_dev *dev) { - struct pci_dev *dev = bus->self; - unsigned short bridge_ctl; + unsigned short bridge_ctl, bridge_ctl_new; /* We deal only with pci controllers and pci-pci bridges. */ if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) return; /* PCI-PCI bridge - set the cache line and default latency - (32) for primary and secondary buses. */ + * (32) for primary and secondary buses. + */ pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32); pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl); - bridge_ctl |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; - pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl); + + bridge_ctl_new = bridge_ctl | PCI_BRIDGE_CTL_PARITY | + PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_MASTER_ABORT; + dev_info(&dev->dev, "Changing bridge control from 0x%08x to 0x%08x\n", + bridge_ctl, bridge_ctl_new); + + pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl_new); } /* |