diff options
Diffstat (limited to 'arch/mips/include/asm')
47 files changed, 3583 insertions, 497 deletions
diff --git a/arch/mips/include/asm/asm-offsets.h b/arch/mips/include/asm/asm-offsets.h new file mode 100644 index 000000000000..d370ee36a182 --- /dev/null +++ b/arch/mips/include/asm/asm-offsets.h @@ -0,0 +1 @@ +#include <generated/asm-offsets.h> diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h index f5dfaf6a1606..09eee09780f2 100644 --- a/arch/mips/include/asm/bootinfo.h +++ b/arch/mips/include/asm/bootinfo.h @@ -67,9 +67,9 @@ #define MACH_LEMOTE_ML2F7 3 #define MACH_LEMOTE_YL2F89 4 #define MACH_DEXXON_GDIUM2F10 5 -#define MACH_LOONGSON_END 6 - -#define CL_SIZE COMMAND_LINE_SIZE +#define MACH_LEMOTE_NAS 6 +#define MACH_LEMOTE_LL2F 7 +#define MACH_LOONGSON_END 8 extern char *system_type; const char *get_system_type(void); @@ -107,7 +107,7 @@ extern void free_init_pages(const char *what, /* * Initial kernel command line, usually setup by prom_init() */ -extern char arcs_cmdline[CL_SIZE]; +extern char arcs_cmdline[COMMAND_LINE_SIZE]; /* * Registers a0, a1, a3 and a4 as passed to the kernel entry by firmware diff --git a/arch/mips/include/asm/clock.h b/arch/mips/include/asm/clock.h new file mode 100644 index 000000000000..83894aa7932c --- /dev/null +++ b/arch/mips/include/asm/clock.h @@ -0,0 +1,64 @@ +#ifndef __ASM_MIPS_CLOCK_H +#define __ASM_MIPS_CLOCK_H + +#include <linux/kref.h> +#include <linux/list.h> +#include <linux/seq_file.h> +#include <linux/clk.h> + +extern void (*cpu_wait) (void); + +struct clk; + +struct clk_ops { + void (*init) (struct clk *clk); + void (*enable) (struct clk *clk); + void (*disable) (struct clk *clk); + void (*recalc) (struct clk *clk); + int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id); + long (*round_rate) (struct clk *clk, unsigned long rate); +}; + +struct clk { + struct list_head node; + const char *name; + int id; + struct module *owner; + + struct clk *parent; + struct clk_ops *ops; + + struct kref kref; + + unsigned long rate; + unsigned long flags; +}; + +#define CLK_ALWAYS_ENABLED (1 << 0) +#define CLK_RATE_PROPAGATES (1 << 1) + +/* Should be defined by processor-specific code */ +void arch_init_clk_ops(struct clk_ops **, int type); + +int clk_init(void); + +int __clk_enable(struct clk *); +void __clk_disable(struct clk *); + +void clk_recalc_rate(struct clk *); + +int clk_register(struct clk *); +void clk_unregister(struct clk *); + +/* the exported API, in addition to clk_set_rate */ +/** + * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter + * @clk: clock source + * @rate: desired clock rate in Hz + * @algo_id: algorithm id to be passed down to ops->set_rate + * + * Returns success (0) or negative errno. + */ +int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id); + +#endif /* __ASM_MIPS_CLOCK_H */ diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h new file mode 100644 index 000000000000..6b04c98b7fad --- /dev/null +++ b/arch/mips/include/asm/cop2.h @@ -0,0 +1,23 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2009 Wind River Systems, + * written by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_COP2_H +#define __ASM_COP2_H + +enum cu2_ops { + CU2_EXCEPTION, + CU2_LWC2_OP, + CU2_LDC2_OP, + CU2_SWC2_OP, + CU2_SDC2_OP, +}; + +extern int register_cu2_notifier(struct notifier_block *nb); +extern int cu2_notifier_call_chain(unsigned long val, void *v); + +#endif /* __ASM_COP2_H */ diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 4b96d1a36056..cf373a95fe4a 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -154,6 +154,8 @@ #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ #define PRID_REV_VR4130 0x0080 #define PRID_REV_34K_V1_0_2 0x0022 +#define PRID_REV_LOONGSON2E 0x0002 +#define PRID_REV_LOONGSON2F 0x0003 /* * Older processors used to encode processor version and revision in two diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h index 7990694cda22..7a6a35dbe529 100644 --- a/arch/mips/include/asm/elf.h +++ b/arch/mips/include/asm/elf.h @@ -326,7 +326,6 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); #define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \ dump_task_fpu(tsk, elf_fpregs) -#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE PAGE_SIZE /* This yields a mask that user programs can use to figure out what diff --git a/arch/mips/include/asm/fcntl.h b/arch/mips/include/asm/fcntl.h index 7c6681aa2ab8..e482fe90fe88 100644 --- a/arch/mips/include/asm/fcntl.h +++ b/arch/mips/include/asm/fcntl.h @@ -19,7 +19,7 @@ #define FASYNC 0x1000 /* fcntl, for BSD compatibility */ #define O_LARGEFILE 0x2000 /* allow large file opens */ /* - * Before Linux 2.6.32 only O_DSYNC semantics were implemented, but using + * Before Linux 2.6.33 only O_DSYNC semantics were implemented, but using * the O_SYNC flag. We continue to use the existing numerical value * for O_DSYNC semantics now, but using the correct symbolic name for it. * This new value is used to request true Posix O_SYNC semantics. It is diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h index 8a3ef247659a..7fcef8ef3fab 100644 --- a/arch/mips/include/asm/fpu.h +++ b/arch/mips/include/asm/fpu.h @@ -28,15 +28,7 @@ struct sigcontext; struct sigcontext32; -extern asmlinkage int (*save_fp_context)(struct sigcontext __user *sc); -extern asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc); - -extern asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); -extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); - extern void fpu_emulator_init_fpu(void); -extern int fpu_emulator_save_context(struct sigcontext __user *sc); -extern int fpu_emulator_restore_context(struct sigcontext __user *sc); extern void _init_fpu(void); extern void _save_fp(struct task_struct *); extern void _restore_fp(struct task_struct *); diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h index e5189572956c..aecada6f6117 100644 --- a/arch/mips/include/asm/fpu_emulator.h +++ b/arch/mips/include/asm/fpu_emulator.h @@ -25,17 +25,27 @@ #include <asm/break.h> #include <asm/inst.h> +#include <asm/local.h> + +#ifdef CONFIG_DEBUG_FS struct mips_fpu_emulator_stats { - unsigned int emulated; - unsigned int loads; - unsigned int stores; - unsigned int cp1ops; - unsigned int cp1xops; - unsigned int errors; + local_t emulated; + local_t loads; + local_t stores; + local_t cp1ops; + local_t cp1xops; + local_t errors; }; -extern struct mips_fpu_emulator_stats fpuemustats; +DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats); + +#define MIPS_FPU_EMU_INC_STATS(M) \ + cpu_local_wrap(__local_inc(&__get_cpu_var(fpuemustats).M)) + +#else +#define MIPS_FPU_EMU_INC_STATS(M) do { } while (0) +#endif /* CONFIG_DEBUG_FS */ extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc); diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h index 40a8c178f10d..3986cd8704f3 100644 --- a/arch/mips/include/asm/ftrace.h +++ b/arch/mips/include/asm/ftrace.h @@ -1 +1,90 @@ -/* empty */ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive for + * more details. + * + * Copyright (C) 2009 DSLab, Lanzhou University, China + * Author: Wu Zhangjin <wuzj@lemote.com> + */ + +#ifndef _ASM_MIPS_FTRACE_H +#define _ASM_MIPS_FTRACE_H + +#ifdef CONFIG_FUNCTION_TRACER + +#define MCOUNT_ADDR ((unsigned long)(_mcount)) +#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */ + +#ifndef __ASSEMBLY__ +extern void _mcount(void); +#define mcount _mcount + +#define safe_load(load, src, dst, error) \ +do { \ + asm volatile ( \ + "1: " load " %[" STR(dst) "], 0(%[" STR(src) "])\n"\ + " li %[" STR(error) "], 0\n" \ + "2:\n" \ + \ + ".section .fixup, \"ax\"\n" \ + "3: li %[" STR(error) "], 1\n" \ + " j 2b\n" \ + ".previous\n" \ + \ + ".section\t__ex_table,\"a\"\n\t" \ + STR(PTR) "\t1b, 3b\n\t" \ + ".previous\n" \ + \ + : [dst] "=&r" (dst), [error] "=r" (error)\ + : [src] "r" (src) \ + : "memory" \ + ); \ +} while (0) + +#define safe_store(store, src, dst, error) \ +do { \ + asm volatile ( \ + "1: " store " %[" STR(src) "], 0(%[" STR(dst) "])\n"\ + " li %[" STR(error) "], 0\n" \ + "2:\n" \ + \ + ".section .fixup, \"ax\"\n" \ + "3: li %[" STR(error) "], 1\n" \ + " j 2b\n" \ + ".previous\n" \ + \ + ".section\t__ex_table,\"a\"\n\t"\ + STR(PTR) "\t1b, 3b\n\t" \ + ".previous\n" \ + \ + : [error] "=r" (error) \ + : [dst] "r" (dst), [src] "r" (src)\ + : "memory" \ + ); \ +} while (0) + +#define safe_load_code(dst, src, error) \ + safe_load(STR(lw), src, dst, error) +#define safe_store_code(src, dst, error) \ + safe_store(STR(sw), src, dst, error) + +#define safe_load_stack(dst, src, error) \ + safe_load(STR(PTR_L), src, dst, error) + +#define safe_store_stack(src, dst, error) \ + safe_store(STR(PTR_S), src, dst, error) + + +#ifdef CONFIG_DYNAMIC_FTRACE +static inline unsigned long ftrace_call_adjust(unsigned long addr) +{ + return addr; +} + +struct dyn_arch_ftrace { +}; + +#endif /* CONFIG_DYNAMIC_FTRACE */ +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_FUNCTION_TRACER */ +#endif /* _ASM_MIPS_FTRACE_H */ diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h index 09b08d05ff72..06960364c96b 100644 --- a/arch/mips/include/asm/irq.h +++ b/arch/mips/include/asm/irq.h @@ -113,36 +113,11 @@ do { \ #endif -/* - * do_IRQ handles all normal device IRQ's (the special - * SMP cross-CPU interrupts have their own specific - * handlers). - * - * Ideally there should be away to get this into kernel/irq/handle.c to - * avoid the overhead of a call for just a tiny function ... - */ -#define do_IRQ(irq) \ -do { \ - irq_enter(); \ - __DO_IRQ_SMTC_HOOK(irq); \ - generic_handle_irq(irq); \ - irq_exit(); \ -} while (0) +extern void do_IRQ(unsigned int irq); #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF -/* - * To avoid inefficient and in some cases pathological re-checking of - * IRQ affinity, we have this variant that skips the affinity check. - */ - -#define do_IRQ_no_affinity(irq) \ -do { \ - irq_enter(); \ - __NO_AFFINITY_IRQ_SMTC_HOOK(irq); \ - generic_handle_irq(irq); \ - irq_exit(); \ -} while (0) +extern void do_IRQ_no_affinity(unsigned int irq); #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ diff --git a/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h b/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h deleted file mode 100644 index 107104c3cd12..000000000000 --- a/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com> - * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H - -/* - * Basler eXcite has an RM9122 processor. - */ -#define cpu_has_watch 1 -#define cpu_has_mips16 0 -#define cpu_has_divec 0 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_prefetch 1 -#define cpu_has_mcheck 0 -#define cpu_has_ejtag 0 - -#define cpu_has_llsc 1 -#define cpu_has_vtag_icache 0 -#define cpu_has_dc_aliases 0 -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_dsp 0 -#define cpu_icache_snoops_remote_store 0 -#define cpu_has_mipsmt 0 -#define cpu_has_userlocal 0 - -#define cpu_has_nofpuex 0 -#define cpu_has_64bits 1 - -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#define cpu_has_inclusive_pcaches 0 - -#define cpu_dcache_line_size() 32 -#define cpu_icache_line_size() 32 -#define cpu_scache_line_size() 32 - -#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-excite/excite.h b/arch/mips/include/asm/mach-excite/excite.h deleted file mode 100644 index 4c29ba44992c..000000000000 --- a/arch/mips/include/asm/mach-excite/excite.h +++ /dev/null @@ -1,154 +0,0 @@ -#ifndef __EXCITE_H__ -#define __EXCITE_H__ - -#include <linux/init.h> -#include <asm/addrspace.h> -#include <asm/types.h> - -#define EXCITE_CPU_EXT_CLOCK 100000000 - -#if !defined(__ASSEMBLY__) -void __init excite_kgdb_init(void); -void excite_procfs_init(void); -extern unsigned long memsize; -extern char modetty[]; -extern u32 unit_id; -#endif - -/* Base name for XICAP devices */ -#define XICAP_NAME "xicap_gpi" - -/* OCD register offsets */ -#define LKB0 0x0038 -#define LKB5 0x0128 -#define LKM5 0x012C -#define LKB7 0x0138 -#define LKM7 0x013c -#define LKB8 0x0140 -#define LKM8 0x0144 -#define LKB9 0x0148 -#define LKM9 0x014c -#define LKB10 0x0150 -#define LKM10 0x0154 -#define LKB11 0x0158 -#define LKM11 0x015c -#define LKB12 0x0160 -#define LKM12 0x0164 -#define LKB13 0x0168 -#define LKM13 0x016c -#define LDP0 0x0200 -#define LDP1 0x0210 -#define LDP2 0x0220 -#define LDP3 0x0230 -#define INTPIN0 0x0A40 -#define INTPIN1 0x0A44 -#define INTPIN2 0x0A48 -#define INTPIN3 0x0A4C -#define INTPIN4 0x0A50 -#define INTPIN5 0x0A54 -#define INTPIN6 0x0A58 -#define INTPIN7 0x0A5C - - - - -/* TITAN register offsets */ -#define CPRR 0x0004 -#define CPDSR 0x0008 -#define CPTC0R 0x000c -#define CPTC1R 0x0010 -#define CPCFG0 0x0020 -#define CPCFG1 0x0024 -#define CPDST0A 0x0028 -#define CPDST0B 0x002c -#define CPDST1A 0x0030 -#define CPDST1B 0x0034 -#define CPXDSTA 0x0038 -#define CPXDSTB 0x003c -#define CPXCISRA 0x0048 -#define CPXCISRB 0x004c -#define CPGIG0ER 0x0050 -#define CPGIG1ER 0x0054 -#define CPGRWL 0x0068 -#define CPURSLMT 0x00f8 -#define UACFG 0x0200 -#define UAINTS 0x0204 -#define SDRXFCIE 0x4828 -#define SDTXFCIE 0x4928 -#define INTP0Status0 0x1B00 -#define INTP0Mask0 0x1B04 -#define INTP0Set0 0x1B08 -#define INTP0Clear0 0x1B0C -#define GXCFG 0x5000 -#define GXDMADRPFX 0x5018 -#define GXDMA_DESCADR 0x501c -#define GXCH0TDESSTRT 0x5054 - -/* IRQ definitions */ -#define NMICONFIG 0xac0 -#define TITAN_MSGINT 0xc4 -#define TITAN_IRQ ((TITAN_MSGINT / 0x20) + 2) -#define FPGA0_MSGINT 0x5a -#define FPGA0_IRQ ((FPGA0_MSGINT / 0x20) + 2) -#define FPGA1_MSGINT 0x7b -#define FPGA1_IRQ ((FPGA1_MSGINT / 0x20) + 2) -#define PHY_MSGINT 0x9c -#define PHY_IRQ ((PHY_MSGINT / 0x20) + 2) - -#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE) -/* Pre-release units used interrupt pin #9 */ -#define USB_IRQ 11 -#else -/* Re-designed units use interrupt pin #1 */ -#define USB_MSGINT 0x39 -#define USB_IRQ ((USB_MSGINT / 0x20) + 2) -#endif -#define TIMER_IRQ 12 - - -/* Device address ranges */ -#define EXCITE_OFFS_OCD 0x1fffc000 -#define EXCITE_SIZE_OCD (16 * 1024) -#define EXCITE_PHYS_OCD CPHYSADDR(EXCITE_OFFS_OCD) -#define EXCITE_ADDR_OCD CKSEG1ADDR(EXCITE_OFFS_OCD) - -#define EXCITE_OFFS_SCRAM 0x1fffa000 -#define EXCITE_SIZE_SCRAM (8 << 10) -#define EXCITE_PHYS_SCRAM CPHYSADDR(EXCITE_OFFS_SCRAM) -#define EXCITE_ADDR_SCRAM CKSEG1ADDR(EXCITE_OFFS_SCRAM) - -#define EXCITE_OFFS_PCI_IO 0x1fff8000 -#define EXCITE_SIZE_PCI_IO (8 << 10) -#define EXCITE_PHYS_PCI_IO CPHYSADDR(EXCITE_OFFS_PCI_IO) -#define EXCITE_ADDR_PCI_IO CKSEG1ADDR(EXCITE_OFFS_PCI_IO) - -#define EXCITE_OFFS_TITAN 0x1fff0000 -#define EXCITE_SIZE_TITAN (32 << 10) -#define EXCITE_PHYS_TITAN CPHYSADDR(EXCITE_OFFS_TITAN) -#define EXCITE_ADDR_TITAN CKSEG1ADDR(EXCITE_OFFS_TITAN) - -#define EXCITE_OFFS_PCI_MEM 0x1ffe0000 -#define EXCITE_SIZE_PCI_MEM (64 << 10) -#define EXCITE_PHYS_PCI_MEM CPHYSADDR(EXCITE_OFFS_PCI_MEM) -#define EXCITE_ADDR_PCI_MEM CKSEG1ADDR(EXCITE_OFFS_PCI_MEM) - -#define EXCITE_OFFS_FPGA 0x1ffdc000 -#define EXCITE_SIZE_FPGA (16 << 10) -#define EXCITE_PHYS_FPGA CPHYSADDR(EXCITE_OFFS_FPGA) -#define EXCITE_ADDR_FPGA CKSEG1ADDR(EXCITE_OFFS_FPGA) - -#define EXCITE_OFFS_NAND 0x1ffd8000 -#define EXCITE_SIZE_NAND (16 << 10) -#define EXCITE_PHYS_NAND CPHYSADDR(EXCITE_OFFS_NAND) -#define EXCITE_ADDR_NAND CKSEG1ADDR(EXCITE_OFFS_NAND) - -#define EXCITE_OFFS_BOOTROM 0x1f000000 -#define EXCITE_SIZE_BOOTROM (8 << 20) -#define EXCITE_PHYS_BOOTROM CPHYSADDR(EXCITE_OFFS_BOOTROM) -#define EXCITE_ADDR_BOOTROM CKSEG1ADDR(EXCITE_OFFS_BOOTROM) - -/* FPGA address offsets */ -#define EXCITE_FPGA_DPR 0x0104 /* dual-ported ram */ -#define EXCITE_FPGA_SYSCTL 0x0200 /* system control register block */ - -#endif /* __EXCITE_H__ */ diff --git a/arch/mips/include/asm/mach-excite/excite_fpga.h b/arch/mips/include/asm/mach-excite/excite_fpga.h deleted file mode 100644 index 0a1ef69bece7..000000000000 --- a/arch/mips/include/asm/mach-excite/excite_fpga.h +++ /dev/null @@ -1,80 +0,0 @@ -#ifndef EXCITE_FPGA_H_INCLUDED -#define EXCITE_FPGA_H_INCLUDED - - -/** - * Address alignment of the individual FPGA bytes. - * The address arrangement of the individual bytes of the FPGA is two - * byte aligned at the embedded MK2 platform. - */ -#ifdef EXCITE_CCI_FPGA_MK2 -typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2))); -#else -typedef unsigned char excite_cci_fpga_align_t; -#endif - - -/** - * Size of Dual Ported RAM. - */ -#define EXCITE_DPR_SIZE 263 - - -/** - * Size of Reserved Status Fields in Dual Ported RAM. - */ -#define EXCITE_DPR_STATUS_SIZE 7 - - - -/** - * FPGA. - * Hardware register layout of the FPGA interface. The FPGA must accessed - * byte wise solely. - * @see EXCITE_CCI_DPR_MK2 - */ -typedef struct excite_fpga { - - /** - * Dual Ported RAM. - */ - excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE]; - - /** - * Status. - */ - excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE]; - -#ifdef EXCITE_CCI_FPGA_MK2 - /** - * RM9000 Interrupt. - * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite. - */ - excite_cci_fpga_align_t rm9k_int; -#else - /** - * MK2 Interrupt. - * Write access initiates interrupt at the ARM processor of the MK2. - */ - excite_cci_fpga_align_t mk2_int; - - excite_cci_fpga_align_t gap[0x1000-0x10f]; - - /** - * IRQ Source/Acknowledge. - */ - excite_cci_fpga_align_t rm9k_irq_src; - - /** - * IRQ Mask. - * Set bits enable the related interrupt. - */ - excite_cci_fpga_align_t rm9k_irq_mask; -#endif - - -} excite_fpga; - - - -#endif /* ndef EXCITE_FPGA_H_INCLUDED */ diff --git a/arch/mips/include/asm/mach-excite/excite_nandflash.h b/arch/mips/include/asm/mach-excite/excite_nandflash.h deleted file mode 100644 index c4cf6140622e..000000000000 --- a/arch/mips/include/asm/mach-excite/excite_nandflash.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __EXCITE_NANDFLASH_H__ -#define __EXCITE_NANDFLASH_H__ - -/* Resource names */ -#define EXCITE_NANDFLASH_RESOURCE_REGS "excite_nandflash_regs" - -#endif /* __EXCITE_NANDFLASH_H__ */ diff --git a/arch/mips/include/asm/mach-excite/rm9k_eth.h b/arch/mips/include/asm/mach-excite/rm9k_eth.h deleted file mode 100644 index 94705a46f72e..000000000000 --- a/arch/mips/include/asm/mach-excite/rm9k_eth.h +++ /dev/null @@ -1,23 +0,0 @@ -#if !defined(__RM9K_ETH_H__) -#define __RM9K_ETH_H__ - -#define RM9K_GE_NAME "rm9k_ge" - -/* Resource names */ -#define RM9K_GE_RESOURCE_MAC "rm9k_ge_mac" -#define RM9K_GE_RESOURCE_MSTAT "rm9k_ge_mstat" -#define RM9K_GE_RESOURCE_PKTPROC "rm9k_ge_pktproc" -#define RM9K_GE_RESOURCE_XDMA "rm9k_ge_xdma" -#define RM9K_GE_RESOURCE_FIFO_RX "rm9k_ge_fifo_rx" -#define RM9K_GE_RESOURCE_FIFO_TX "rm9k_ge_fifo_tx" -#define RM9K_GE_RESOURCE_FIFOMEM_RX "rm9k_ge_fifo_memory_rx" -#define RM9K_GE_RESOURCE_FIFOMEM_TX "rm9k_ge_fifo_memory_tx" -#define RM9K_GE_RESOURCE_PHY "rm9k_ge_phy" -#define RM9K_GE_RESOURCE_DMADESC_RX "rm9k_ge_dmadesc_rx" -#define RM9K_GE_RESOURCE_DMADESC_TX "rm9k_ge_dmadesc_tx" -#define RM9K_GE_RESOURCE_IRQ_MAIN "rm9k_ge_irq_main" -#define RM9K_GE_RESOURCE_IRQ_PHY "rm9k_ge_irq_phy" -#define RM9K_GE_RESOURCE_GPI_SLICE "rm9k_ge_gpi_slice" -#define RM9K_GE_RESOURCE_MDIO_CHANNEL "rm9k_ge_mdio_channel" - -#endif /* !defined(__RM9K_ETH_H__) */ diff --git a/arch/mips/include/asm/mach-excite/rm9k_wdt.h b/arch/mips/include/asm/mach-excite/rm9k_wdt.h deleted file mode 100644 index 3fa3c08d2da7..000000000000 --- a/arch/mips/include/asm/mach-excite/rm9k_wdt.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef __RM9K_WDT_H__ -#define __RM9K_WDT_H__ - -/* Device name */ -#define WDT_NAME "wdt_gpi" - -/* Resource names */ -#define WDT_RESOURCE_REGS "excite_watchdog_regs" -#define WDT_RESOURCE_IRQ "excite_watchdog_irq" -#define WDT_RESOURCE_COUNTER "excite_watchdog_counter" - -#endif /* __RM9K_WDT_H__ */ diff --git a/arch/mips/include/asm/mach-excite/rm9k_xicap.h b/arch/mips/include/asm/mach-excite/rm9k_xicap.h deleted file mode 100644 index 009577734a8d..000000000000 --- a/arch/mips/include/asm/mach-excite/rm9k_xicap.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef __EXCITE_XICAP_H__ -#define __EXCITE_XICAP_H__ - - -/* Resource names */ -#define XICAP_RESOURCE_FIFO_RX "xicap_fifo_rx" -#define XICAP_RESOURCE_FIFO_TX "xicap_fifo_tx" -#define XICAP_RESOURCE_XDMA "xicap_xdma" -#define XICAP_RESOURCE_DMADESC "xicap_dmadesc" -#define XICAP_RESOURCE_PKTPROC "xicap_pktproc" -#define XICAP_RESOURCE_IRQ "xicap_irq" -#define XICAP_RESOURCE_GPI_SLICE "xicap_gpi_slice" -#define XICAP_RESOURCE_FIFO_BLK "xicap_fifo_blocks" -#define XICAP_RESOURCE_PKT_STREAM "xicap_pkt_stream" - -#endif /* __EXCITE_XICAP_H__ */ diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h index 09a59bcc1b07..1b1a7d1632b9 100644 --- a/arch/mips/include/asm/mach-ip27/topology.h +++ b/arch/mips/include/asm/mach-ip27/topology.h @@ -24,7 +24,9 @@ extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS]; #define cpu_to_node(cpu) (sn_cpu_info[(cpu)].p_nodeid) #define parent_node(node) (node) -#define cpumask_of_node(node) (&hub_data(node)->h_cpus) +#define cpumask_of_node(node) ((node) == -1 ? \ + cpu_all_mask : \ + &hub_data(node)->h_cpus) struct pci_bus; extern int pcibus_to_node(struct pci_bus *); diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h new file mode 100644 index 000000000000..021f77ca59ec --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h @@ -0,0 +1,305 @@ +/* + * The header file of cs5536 sourth bridge. + * + * Copyright (C) 2007 Lemote, Inc. + * Author : jlliu <liujl@lemote.com> + */ + +#ifndef _CS5536_H +#define _CS5536_H + +#include <linux/types.h> + +extern void _rdmsr(u32 msr, u32 *hi, u32 *lo); +extern void _wrmsr(u32 msr, u32 hi, u32 lo); + +/* + * MSR module base + */ +#define CS5536_SB_MSR_BASE (0x00000000) +#define CS5536_GLIU_MSR_BASE (0x10000000) +#define CS5536_ILLEGAL_MSR_BASE (0x20000000) +#define CS5536_USB_MSR_BASE (0x40000000) +#define CS5536_IDE_MSR_BASE (0x60000000) +#define CS5536_DIVIL_MSR_BASE (0x80000000) +#define CS5536_ACC_MSR_BASE (0xa0000000) +#define CS5536_UNUSED_MSR_BASE (0xc0000000) +#define CS5536_GLCP_MSR_BASE (0xe0000000) + +#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset)) +#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset)) +#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset)) +#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset)) +#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset)) +#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset)) +#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset)) +#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset)) +#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset)) + +/* + * BAR SPACE OF VIRTUAL PCI : + * range for pci probe use, length is the actual size. + */ +/* IO space for all DIVIL modules */ +#define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */ +#define CS5536_IRQ_LENGTH 0x20 /* THE REGS ACTUAL LENGTH */ +#define CS5536_SMB_RANGE 0xfffffff8 +#define CS5536_SMB_LENGTH 0x08 +#define CS5536_GPIO_RANGE 0xffffff00 +#define CS5536_GPIO_LENGTH 0x100 +#define CS5536_MFGPT_RANGE 0xffffffc0 +#define CS5536_MFGPT_LENGTH 0x40 +#define CS5536_ACPI_RANGE 0xffffffe0 +#define CS5536_ACPI_LENGTH 0x20 +#define CS5536_PMS_RANGE 0xffffff80 +#define CS5536_PMS_LENGTH 0x80 +/* IO space for IDE */ +#define CS5536_IDE_RANGE 0xfffffff0 +#define CS5536_IDE_LENGTH 0x10 +/* IO space for ACC */ +#define CS5536_ACC_RANGE 0xffffff80 +#define CS5536_ACC_LENGTH 0x80 +/* MEM space for ALL USB modules */ +#define CS5536_OHCI_RANGE 0xfffff000 +#define CS5536_OHCI_LENGTH 0x1000 +#define CS5536_EHCI_RANGE 0xfffff000 +#define CS5536_EHCI_LENGTH 0x1000 + +/* + * PCI MSR ACCESS + */ +#define PCI_MSR_CTRL 0xF0 +#define PCI_MSR_ADDR 0xF4 +#define PCI_MSR_DATA_LO 0xF8 +#define PCI_MSR_DATA_HI 0xFC + +/**************** MSR *****************************/ + +/* + * GLIU STANDARD MSR + */ +#define GLIU_CAP 0x00 +#define GLIU_CONFIG 0x01 +#define GLIU_SMI 0x02 +#define GLIU_ERROR 0x03 +#define GLIU_PM 0x04 +#define GLIU_DIAG 0x05 + +/* + * GLIU SPEC. MSR + */ +#define GLIU_P2D_BM0 0x20 +#define GLIU_P2D_BM1 0x21 +#define GLIU_P2D_BM2 0x22 +#define GLIU_P2D_BMK0 0x23 +#define GLIU_P2D_BMK1 0x24 +#define GLIU_P2D_BM3 0x25 +#define GLIU_P2D_BM4 0x26 +#define GLIU_COH 0x80 +#define GLIU_PAE 0x81 +#define GLIU_ARB 0x82 +#define GLIU_ASMI 0x83 +#define GLIU_AERR 0x84 +#define GLIU_DEBUG 0x85 +#define GLIU_PHY_CAP 0x86 +#define GLIU_NOUT_RESP 0x87 +#define GLIU_NOUT_WDATA 0x88 +#define GLIU_WHOAMI 0x8B +#define GLIU_SLV_DIS 0x8C +#define GLIU_IOD_BM0 0xE0 +#define GLIU_IOD_BM1 0xE1 +#define GLIU_IOD_BM2 0xE2 +#define GLIU_IOD_BM3 0xE3 +#define GLIU_IOD_BM4 0xE4 +#define GLIU_IOD_BM5 0xE5 +#define GLIU_IOD_BM6 0xE6 +#define GLIU_IOD_BM7 0xE7 +#define GLIU_IOD_BM8 0xE8 +#define GLIU_IOD_BM9 0xE9 +#define GLIU_IOD_SC0 0xEA +#define GLIU_IOD_SC1 0xEB +#define GLIU_IOD_SC2 0xEC +#define GLIU_IOD_SC3 0xED +#define GLIU_IOD_SC4 0xEE +#define GLIU_IOD_SC5 0xEF +#define GLIU_IOD_SC6 0xF0 +#define GLIU_IOD_SC7 0xF1 + +/* + * SB STANDARD + */ +#define SB_CAP 0x00 +#define SB_CONFIG 0x01 +#define SB_SMI 0x02 +#define SB_ERROR 0x03 +#define SB_MAR_ERR_EN 0x00000001 +#define SB_TAR_ERR_EN 0x00000002 +#define SB_RSVD_BIT1 0x00000004 +#define SB_EXCEP_ERR_EN 0x00000008 +#define SB_SYSE_ERR_EN 0x00000010 +#define SB_PARE_ERR_EN 0x00000020 +#define SB_TAS_ERR_EN 0x00000040 +#define SB_MAR_ERR_FLAG 0x00010000 +#define SB_TAR_ERR_FLAG 0x00020000 +#define SB_RSVD_BIT2 0x00040000 +#define SB_EXCEP_ERR_FLAG 0x00080000 +#define SB_SYSE_ERR_FLAG 0x00100000 +#define SB_PARE_ERR_FLAG 0x00200000 +#define SB_TAS_ERR_FLAG 0x00400000 +#define SB_PM 0x04 +#define SB_DIAG 0x05 + +/* + * SB SPEC. + */ +#define SB_CTRL 0x10 +#define SB_R0 0x20 +#define SB_R1 0x21 +#define SB_R2 0x22 +#define SB_R3 0x23 +#define SB_R4 0x24 +#define SB_R5 0x25 +#define SB_R6 0x26 +#define SB_R7 0x27 +#define SB_R8 0x28 +#define SB_R9 0x29 +#define SB_R10 0x2A +#define SB_R11 0x2B +#define SB_R12 0x2C +#define SB_R13 0x2D +#define SB_R14 0x2E +#define SB_R15 0x2F + +/* + * GLCP STANDARD + */ +#define GLCP_CAP 0x00 +#define GLCP_CONFIG 0x01 +#define GLCP_SMI 0x02 +#define GLCP_ERROR 0x03 +#define GLCP_PM 0x04 +#define GLCP_DIAG 0x05 + +/* + * GLCP SPEC. + */ +#define GLCP_CLK_DIS_DELAY 0x08 +#define GLCP_PM_CLK_DISABLE 0x09 +#define GLCP_GLB_PM 0x0B +#define GLCP_DBG_OUT 0x0C +#define GLCP_RSVD1 0x0D +#define GLCP_SOFT_COM 0x0E +#define SOFT_BAR_SMB_FLAG 0x00000001 +#define SOFT_BAR_GPIO_FLAG 0x00000002 +#define SOFT_BAR_MFGPT_FLAG 0x00000004 +#define SOFT_BAR_IRQ_FLAG 0x00000008 +#define SOFT_BAR_PMS_FLAG 0x00000010 +#define SOFT_BAR_ACPI_FLAG 0x00000020 +#define SOFT_BAR_IDE_FLAG 0x00000400 +#define SOFT_BAR_ACC_FLAG 0x00000800 +#define SOFT_BAR_OHCI_FLAG 0x00001000 +#define SOFT_BAR_EHCI_FLAG 0x00002000 +#define GLCP_RSVD2 0x0F +#define GLCP_CLK_OFF 0x10 +#define GLCP_CLK_ACTIVE 0x11 +#define GLCP_CLK_DISABLE 0x12 +#define GLCP_CLK4ACK 0x13 +#define GLCP_SYS_RST 0x14 +#define GLCP_RSVD3 0x15 +#define GLCP_DBG_CLK_CTRL 0x16 +#define GLCP_CHIP_REV_ID 0x17 + +/* PIC */ +#define PIC_YSEL_LOW 0x20 +#define PIC_YSEL_LOW_USB_SHIFT 8 +#define PIC_YSEL_LOW_ACC_SHIFT 16 +#define PIC_YSEL_LOW_FLASH_SHIFT 24 +#define PIC_YSEL_HIGH 0x21 +#define PIC_ZSEL_LOW 0x22 +#define PIC_ZSEL_HIGH 0x23 +#define PIC_IRQM_PRIM 0x24 +#define PIC_IRQM_LPC 0x25 +#define PIC_XIRR_STS_LOW 0x26 +#define PIC_XIRR_STS_HIGH 0x27 +#define PCI_SHDW 0x34 + +/* + * DIVIL STANDARD + */ +#define DIVIL_CAP 0x00 +#define DIVIL_CONFIG 0x01 +#define DIVIL_SMI 0x02 +#define DIVIL_ERROR 0x03 +#define DIVIL_PM 0x04 +#define DIVIL_DIAG 0x05 + +/* + * DIVIL SPEC. + */ +#define DIVIL_LBAR_IRQ 0x08 +#define DIVIL_LBAR_KEL 0x09 +#define DIVIL_LBAR_SMB 0x0B +#define DIVIL_LBAR_GPIO 0x0C +#define DIVIL_LBAR_MFGPT 0x0D +#define DIVIL_LBAR_ACPI 0x0E +#define DIVIL_LBAR_PMS 0x0F +#define DIVIL_LEG_IO 0x14 +#define DIVIL_BALL_OPTS 0x15 +#define DIVIL_SOFT_IRQ 0x16 +#define DIVIL_SOFT_RESET 0x17 + +/* MFGPT */ +#define MFGPT_IRQ 0x28 + +/* + * IDE STANDARD + */ +#define IDE_CAP 0x00 +#define IDE_CONFIG 0x01 +#define IDE_SMI 0x02 +#define IDE_ERROR 0x03 +#define IDE_PM 0x04 +#define IDE_DIAG 0x05 + +/* + * IDE SPEC. + */ +#define IDE_IO_BAR 0x08 +#define IDE_CFG 0x10 +#define IDE_DTC 0x12 +#define IDE_CAST 0x13 +#define IDE_ETC 0x14 +#define IDE_INTERNAL_PM 0x15 + +/* + * ACC STANDARD + */ +#define ACC_CAP 0x00 +#define ACC_CONFIG 0x01 +#define ACC_SMI 0x02 +#define ACC_ERROR 0x03 +#define ACC_PM 0x04 +#define ACC_DIAG 0x05 + +/* + * USB STANDARD + */ +#define USB_CAP 0x00 +#define USB_CONFIG 0x01 +#define USB_SMI 0x02 +#define USB_ERROR 0x03 +#define USB_PM 0x04 +#define USB_DIAG 0x05 + +/* + * USB SPEC. + */ +#define USB_OHCI 0x08 +#define USB_EHCI 0x09 + +/****************** NATIVE ***************************/ +/* GPIO : I/O SPACE; REG : 32BITS */ +#define GPIOL_OUT_VAL 0x00 +#define GPIOL_OUT_EN 0x04 + +#endif /* _CS5536_H */ diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h new file mode 100644 index 000000000000..4b493d6772c2 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h @@ -0,0 +1,35 @@ +/* + * cs5536 mfgpt header file + */ + +#ifndef _CS5536_MFGPT_H +#define _CS5536_MFGPT_H + +#include <cs5536/cs5536.h> +#include <cs5536/cs5536_pci.h> + +#ifdef CONFIG_CS5536_MFGPT +extern void setup_mfgpt0_timer(void); +extern void disable_mfgpt0_counter(void); +extern void enable_mfgpt0_counter(void); +#else +static inline void __maybe_unused setup_mfgpt0_timer(void) +{ +} +static inline void __maybe_unused disable_mfgpt0_counter(void) +{ +} +static inline void __maybe_unused enable_mfgpt0_counter(void) +{ +} +#endif + +#define MFGPT_TICK_RATE 14318000 +#define COMPARE ((MFGPT_TICK_RATE + HZ/2) / HZ) + +#define MFGPT_BASE mfgpt_base +#define MFGPT0_CMP2 (MFGPT_BASE + 2) +#define MFGPT0_CNT (MFGPT_BASE + 4) +#define MFGPT0_SETUP (MFGPT_BASE + 6) + +#endif /*!_CS5536_MFGPT_H */ diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h new file mode 100644 index 000000000000..0dca9c89ee7c --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h @@ -0,0 +1,153 @@ +/* + * the definition file of cs5536 Virtual Support Module(VSM). + * pci configuration space can be accessed through the VSM, so + * there is no need of the MSR read/write now, except the spec. + * MSR registers which are not implemented yet. + * + * Copyright (C) 2007 Lemote Inc. + * Author : jlliu, liujl@lemote.com + */ + +#ifndef _CS5536_PCI_H +#define _CS5536_PCI_H + +#include <linux/types.h> +#include <linux/pci_regs.h> + +extern void cs5536_pci_conf_write4(int function, int reg, u32 value); +extern u32 cs5536_pci_conf_read4(int function, int reg); + +#define CS5536_ACC_INTR 9 +#define CS5536_IDE_INTR 14 +#define CS5536_USB_INTR 11 +#define CS5536_MFGPT_INTR 5 +#define CS5536_UART1_INTR 4 +#define CS5536_UART2_INTR 3 + +/************** PCI BUS DEVICE FUNCTION ***************/ + +/* + * PCI bus device function + */ +#define PCI_BUS_CS5536 0 +#define PCI_IDSEL_CS5536 14 + +/********** STANDARD PCI-2.2 EXPANSION ****************/ + +/* + * PCI configuration space + * we have to virtualize the PCI configure space head, so we should + * define the necessary IDs and some others. + */ + +/* CONFIG of PCI VENDOR ID*/ +#define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \ + (((mod_dev_id) << 16) | (sys_vendor_id)) + +/* VENDOR ID */ +#define CS5536_VENDOR_ID 0x1022 + +/* DEVICE ID */ +#define CS5536_ISA_DEVICE_ID 0x2090 +#define CS5536_IDE_DEVICE_ID 0x209a +#define CS5536_ACC_DEVICE_ID 0x2093 +#define CS5536_OHCI_DEVICE_ID 0x2094 +#define CS5536_EHCI_DEVICE_ID 0x2095 + +/* CLASS CODE : CLASS SUB-CLASS INTERFACE */ +#define CS5536_ISA_CLASS_CODE 0x060100 +#define CS5536_IDE_CLASS_CODE 0x010180 +#define CS5536_ACC_CLASS_CODE 0x040100 +#define CS5536_OHCI_CLASS_CODE 0x0C0310 +#define CS5536_EHCI_CLASS_CODE 0x0C0320 + +/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */ + +#define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer) \ + ((PCI_NONE_BIST << 24) | ((header_type) << 16) \ + | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE); + +#define PCI_NONE_BIST 0x00 /* RO not implemented yet. */ +#define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */ +#define PCI_NORMAL_HEADER_TYPE 0x00 +#define PCI_NORMAL_LATENCY_TIMER 0x00 +#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */ + +/* BAR */ +#define PCI_BAR0_REG 0x10 +#define PCI_BAR1_REG 0x14 +#define PCI_BAR2_REG 0x18 +#define PCI_BAR3_REG 0x1c +#define PCI_BAR4_REG 0x20 +#define PCI_BAR5_REG 0x24 +#define PCI_BAR_COUNT 6 +#define PCI_BAR_RANGE_MASK 0xFFFFFFFF + +/* CARDBUS CIS POINTER */ +#define PCI_CARDBUS_CIS_POINTER 0x00000000 + +/* SUBSYSTEM VENDOR ID */ +#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID + +/* SUBSYSTEM ID */ +#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID +#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID +#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID +#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID +#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID + +/* EXPANSION ROM BAR */ +#define PCI_EXPANSION_ROM_BAR 0x00000000 + +/* CAPABILITIES POINTER */ +#define PCI_CAPLIST_POINTER 0x00000000 +#define PCI_CAPLIST_USB_POINTER 0x40 +/* INTERRUPT */ + +#define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \ + ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \ + ((pin) << 8) | (mod_intr)) + +#define PCI_MAX_LATENCY 0x40 +#define PCI_MIN_GRANT 0x00 +#define PCI_DEFAULT_PIN 0x01 + +/*********** EXPANSION PCI REG ************************/ + +/* + * ISA EXPANSION + */ +#define PCI_UART1_INT_REG 0x50 +#define PCI_UART2_INT_REG 0x54 +#define PCI_ISA_FIXUP_REG 0x58 + +/* + * IDE EXPANSION + */ +#define PCI_IDE_CFG_REG 0x40 +#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF +#define PCI_IDE_DTC_REG 0x48 +#define PCI_IDE_CAST_REG 0x4C +#define PCI_IDE_ETC_REG 0x50 +#define PCI_IDE_PM_REG 0x54 +#define PCI_IDE_INT_REG 0x60 + +/* + * ACC EXPANSION + */ +#define PCI_ACC_INT_REG 0x50 + +/* + * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI + */ +#define PCI_OHCI_PM_REG 0x40 +#define PCI_OHCI_INT_REG 0x50 + +/* + * EHCI EXPANSION + */ +#define PCI_EHCI_LEGSMIEN_REG 0x50 +#define PCI_EHCI_LEGSMISTS_REG 0x54 +#define PCI_EHCI_FLADJ_REG 0x60 + +#endif /* _CS5536_PCI_H_ */ diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h new file mode 100644 index 000000000000..6305bea7e18e --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h @@ -0,0 +1,31 @@ +/* + * the read/write interfaces for Virtual Support Module(VSM) + * + * Copyright (C) 2009 Lemote, Inc. + * Author: Wu Zhangjin <wuzj@lemote.com> + */ + +#ifndef _CS5536_VSM_H +#define _CS5536_VSM_H + +#include <linux/types.h> + +typedef void (*cs5536_pci_vsm_write)(int reg, u32 value); +typedef u32 (*cs5536_pci_vsm_read)(int reg); + +#define DECLARE_CS5536_MODULE(name) \ +extern void pci_##name##_write_reg(int reg, u32 value); \ +extern u32 pci_##name##_read_reg(int reg); + +/* ide module */ +DECLARE_CS5536_MODULE(ide) +/* acc module */ +DECLARE_CS5536_MODULE(acc) +/* ohci module */ +DECLARE_CS5536_MODULE(ohci) +/* isa module */ +DECLARE_CS5536_MODULE(isa) +/* ehci module */ +DECLARE_CS5536_MODULE(ehci) + +#endif /* _CS5536_VSM_H */ diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h index 71a6851ba833..981c75f91a7d 100644 --- a/arch/mips/include/asm/mach-loongson/dma-coherence.h +++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h @@ -28,7 +28,11 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, static inline unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) { +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) + return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff); +#else return dma_addr & 0x7fffffff; +#endif } static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index da70bcf2304e..ee8bc8376972 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology + * Copyright (C) 2009 Lemote, Inc. * Author: Wu Zhangjin <wuzj@lemote.com> * * This program is free software; you can redistribute it and/or modify it @@ -15,9 +15,6 @@ #include <linux/io.h> #include <linux/init.h> -/* there is an internal bonito64-compatiable northbridge in loongson2e/2f */ -#include <asm/mips-boards/bonito64.h> - /* loongson internal northbridge initialization */ extern void bonito_irq_init(void); @@ -32,7 +29,19 @@ extern unsigned long memsize, highmemsize; /* loongson-specific command line, env and memory initialization */ extern void __init prom_init_memory(void); extern void __init prom_init_cmdline(void); +extern void __init prom_init_machtype(void); extern void __init prom_init_env(void); +#ifdef CONFIG_LOONGSON_UART_BASE +extern unsigned long _loongson_uart_base, loongson_uart_base; +extern void prom_init_loongson_uart_base(void); +#endif + +static inline void prom_init_uart_base(void) +{ +#ifdef CONFIG_LOONGSON_UART_BASE + prom_init_loongson_uart_base(); +#endif +} /* irq operation functions */ extern void bonito_irqdispatch(void); @@ -40,25 +49,276 @@ extern void __init bonito_irq_init(void); extern void __init set_irq_trigger_mode(void); extern void __init mach_init_irq(void); extern void mach_irq_dispatch(unsigned int pending); +extern int mach_i8259_irq(void); + +/* We need this in some places... */ +#define delay() ({ \ + int x; \ + for (x = 0; x < 100000; x++) \ + __asm__ __volatile__(""); \ +}) + +#define LOONGSON_REG(x) \ + (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x))) + +#define LOONGSON_IRQ_BASE 32 +#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */ + +#define LOONGSON_FLASH_BASE 0x1c000000 +#define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */ +#define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1) + +#define LOONGSON_LIO0_BASE 0x1e000000 +#define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */ +#define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1) + +#define LOONGSON_BOOT_BASE 0x1fc00000 +#define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */ +#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1) +#define LOONGSON_REG_BASE 0x1fe00000 +#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */ +#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1) + +#define LOONGSON_LIO1_BASE 0x1ff00000 +#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */ +#define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1) + +#define LOONGSON_PCILO0_BASE 0x10000000 +#define LOONGSON_PCILO1_BASE 0x14000000 +#define LOONGSON_PCILO2_BASE 0x18000000 +#define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE +#define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */ +#define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1) + +#define LOONGSON_PCICFG_BASE 0x1fe80000 +#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */ +#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1) +#define LOONGSON_PCIIO_BASE 0x1fd00000 +#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */ +#define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1) + +/* Loongson Register Bases */ + +#define LOONGSON_PCICONFIGBASE 0x00 +#define LOONGSON_REGBASE 0x100 /* PCI Configuration Registers */ -#define LOONGSON_PCI_ISR4C BONITO_PCI_REG(0x4c) + +#define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x)) +#define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00) +#define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04) +#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08) +#define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c) +#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10) +#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14) +#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18) +#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c) +#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20) +#define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30) +#define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c) + +#define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c) + +#define LOONGSON_PCICMD_PERR_CLR 0x80000000 +#define LOONGSON_PCICMD_SERR_CLR 0x40000000 +#define LOONGSON_PCICMD_MABORT_CLR 0x20000000 +#define LOONGSON_PCICMD_MTABORT_CLR 0x10000000 +#define LOONGSON_PCICMD_TABORT_CLR 0x08000000 +#define LOONGSON_PCICMD_MPERR_CLR 0x01000000 +#define LOONGSON_PCICMD_PERRRESPEN 0x00000040 +#define LOONGSON_PCICMD_ASTEPEN 0x00000080 +#define LOONGSON_PCICMD_SERREN 0x00000100 +#define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00 +#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8 + +/* Loongson h/w Configuration */ + +#define LOONGSON_GENCFG_OFFSET 0x4 +#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET) + +#define LOONGSON_GENCFG_DEBUGMODE 0x00000001 +#define LOONGSON_GENCFG_SNOOPEN 0x00000002 +#define LOONGSON_GENCFG_CPUSELFRESET 0x00000004 + +#define LOONGSON_GENCFG_FORCE_IRQA 0x00000008 +#define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010 +#define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020 +#define LOONGSON_GENCFG_BYTESWAP 0x00000040 + +#define LOONGSON_GENCFG_UNCACHED 0x00000080 +#define LOONGSON_GENCFG_PREFETCHEN 0x00000100 +#define LOONGSON_GENCFG_WBEHINDEN 0x00000200 +#define LOONGSON_GENCFG_CACHEALG 0x00000c00 +#define LOONGSON_GENCFG_CACHEALG_SHIFT 10 +#define LOONGSON_GENCFG_PCIQUEUE 0x00001000 +#define LOONGSON_GENCFG_CACHESTOP 0x00002000 +#define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000 +#define LOONGSON_GENCFG_BUSERREN 0x00008000 +#define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000 +#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000 + +/* PCI address map control */ + +#define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10) +#define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14) +#define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18) + +/* GPIO Regs - r/w */ + +#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c) +#define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20) + +/* ICU Configuration Regs - r/w */ + +#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24) +#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28) +#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c) + +/* ICU Enable Regs - IntEn & IntISR are r/o. */ + +#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30) +#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34) +#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38) +#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c) + +/* ICU */ +#define LOONGSON_ICU_MBOXES 0x0000000f +#define LOONGSON_ICU_MBOXES_SHIFT 0 +#define LOONGSON_ICU_DMARDY 0x00000010 +#define LOONGSON_ICU_DMAEMPTY 0x00000020 +#define LOONGSON_ICU_COPYRDY 0x00000040 +#define LOONGSON_ICU_COPYEMPTY 0x00000080 +#define LOONGSON_ICU_COPYERR 0x00000100 +#define LOONGSON_ICU_PCIIRQ 0x00000200 +#define LOONGSON_ICU_MASTERERR 0x00000400 +#define LOONGSON_ICU_SYSTEMERR 0x00000800 +#define LOONGSON_ICU_DRAMPERR 0x00001000 +#define LOONGSON_ICU_RETRYERR 0x00002000 +#define LOONGSON_ICU_GPIOS 0x01ff0000 +#define LOONGSON_ICU_GPIOS_SHIFT 16 +#define LOONGSON_ICU_GPINS 0x7e000000 +#define LOONGSON_ICU_GPINS_SHIFT 25 +#define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N))) +#define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N))) +#define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N))) + +/* PCI prefetch window base & mask */ + +#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40) +#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44) +#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48) +#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c) /* PCI_Hit*_Sel_* */ -#define LOONGSON_PCI_HIT0_SEL_L BONITO(BONITO_REGBASE + 0x50) -#define LOONGSON_PCI_HIT0_SEL_H BONITO(BONITO_REGBASE + 0x54) -#define LOONGSON_PCI_HIT1_SEL_L BONITO(BONITO_REGBASE + 0x58) -#define LOONGSON_PCI_HIT1_SEL_H BONITO(BONITO_REGBASE + 0x5c) -#define LOONGSON_PCI_HIT2_SEL_L BONITO(BONITO_REGBASE + 0x60) -#define LOONGSON_PCI_HIT2_SEL_H BONITO(BONITO_REGBASE + 0x64) +#define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50) +#define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54) +#define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58) +#define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c) +#define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60) +#define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64) /* PXArb Config & Status */ -#define LOONGSON_PXARB_CFG BONITO(BONITO_REGBASE + 0x68) -#define LOONGSON_PXARB_STATUS BONITO(BONITO_REGBASE + 0x6c) +#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68) +#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c) + +/* pcimap */ + +#define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f +#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0 +#define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0 +#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6 +#define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000 +#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12 +#define LOONGSON_PCIMAP_PCIMAP_2 0x00040000 +#define LOONGSON_PCIMAP_WIN(WIN, ADDR) \ + ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) + +#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ +#include <linux/cpufreq.h> +extern void loongson2_cpu_wait(void); +extern struct cpufreq_frequency_table loongson2_clockmod_table[]; + +/* Chip Config */ +#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80) +#endif + +/* + * address windows configuration module + * + * loongson2e do not have this module + */ +#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG + +/* address window config module base address */ +#define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul +#define LOONGSON_ADDRWINCFG_SIZE 0x180 + +extern unsigned long _loongson_addrwincfg_base; +#define LOONGSON_ADDRWINCFG(offset) \ + (*(volatile u64 *)(_loongson_addrwincfg_base + (offset))) + +#define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00) +#define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08) +#define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10) +#define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18) + +#define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20) +#define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28) +#define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30) +#define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38) + +#define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40) +#define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48) +#define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50) +#define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58) + +#define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60) +#define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68) +#define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70) +#define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78) + +#define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80) +#define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88) +#define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90) +#define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98) + +#define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0) +#define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8) +#define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0) +#define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8) + +#define ADDRWIN_WIN0 0 +#define ADDRWIN_WIN1 1 +#define ADDRWIN_WIN2 2 +#define ADDRWIN_WIN3 3 + +#define ADDRWIN_MAP_DST_DDR 0 +#define ADDRWIN_MAP_DST_PCI 1 +#define ADDRWIN_MAP_DST_LIO 1 + +/* + * s: CPU, PCIDMA + * d: DDR, PCI, LIO + * win: 0, 1, 2, 3 + * src: map source + * dst: map destination + * size: ~mask + 1 + */ +#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\ + s##_WIN##w##_BASE = (src); \ + s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \ + s##_WIN##w##_MASK = ~(size-1); \ +} while (0) + +#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \ + LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size) +#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \ + LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size) +#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \ + LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size) -/* loongson2-specific perf counter IRQ */ -#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) +#endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */ #endif /* __ASM_MACH_LOONGSON_LOONGSON_H */ diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h index 206ea2067916..acf8359cb135 100644 --- a/arch/mips/include/asm/mach-loongson/machine.h +++ b/arch/mips/include/asm/mach-loongson/machine.h @@ -13,10 +13,15 @@ #ifdef CONFIG_LEMOTE_FULOONG2E -#define LOONGSON_UART_BASE (BONITO_PCIIO_BASE + 0x3f8) - #define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E #endif +/* use fuloong2f as the default machine of LEMOTE_MACH2F */ +#ifdef CONFIG_LEMOTE_MACH2F + +#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2F + +#endif + #endif /* __ASM_MACH_LOONGSON_MACHINE_H */ diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h index bd7b3cba7e35..e9960f341b96 100644 --- a/arch/mips/include/asm/mach-loongson/mem.h +++ b/arch/mips/include/asm/mach-loongson/mem.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology + * Copyright (C) 2009 Lemote, Inc. * Author: Wu Zhangjin <wuzj@lemote.com> * * This program is free software; you can redistribute it and/or modify it @@ -12,19 +12,30 @@ #define __ASM_MACH_LOONGSON_MEM_H /* - * On Lemote Loongson 2e + * high memory space * - * the high memory space starts from 512M. - * the peripheral registers reside between 0x1000:0000 and 0x2000:0000. + * in loongson2e, starts from 512M + * in loongson2f, starts from 2G 256M */ +#ifdef CONFIG_CPU_LOONGSON2E +#define LOONGSON_HIGHMEM_START 0x20000000 +#else +#define LOONGSON_HIGHMEM_START 0x90000000 +#endif -#ifdef CONFIG_LEMOTE_FULOONG2E - -#define LOONGSON_HIGHMEM_START 0x20000000 +/* + * the peripheral registers(MMIO): + * + * On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000. + * On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000. + */ #define LOONGSON_MMIO_MEM_START 0x10000000 -#define LOONGSON_MMIO_MEM_END 0x20000000 +#ifdef CONFIG_CPU_LOONGSON2E +#define LOONGSON_MMIO_MEM_END 0x20000000 +#else +#define LOONGSON_MMIO_MEM_END 0x80000000 #endif #endif /* __ASM_MACH_LOONGSON_MEM_H */ diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h index f1663ca81da0..a199a4f6de4e 100644 --- a/arch/mips/include/asm/mach-loongson/pci.h +++ b/arch/mips/include/asm/mach-loongson/pci.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org> + * Copyright (c) 2009 Wu Zhangjin <wuzj@lemote.com> * * This program is free software; you can redistribute it * and/or modify it under the terms of the GNU General @@ -22,16 +23,39 @@ #ifndef __ASM_MACH_LOONGSON_PCI_H_ #define __ASM_MACH_LOONGSON_PCI_H_ -extern struct pci_ops bonito64_pci_ops; +extern struct pci_ops loongson_pci_ops; -#ifdef CONFIG_LEMOTE_FULOONG2E +/* this is an offset from mips_io_port_base */ +#define LOONGSON_PCI_IO_START 0x00004000UL + +#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG + +/* + * we use address window2 to map cpu address space to pci space + * window2: cpu [1G, 2G] -> pci [1G, 2G] + * why not use window 0 & 1? because they are used by cpu when booting. + * window0: cpu [0, 256M] -> ddr [0, 256M] + * window1: cpu [256M, 512M] -> pci [256M, 512M] + */ + +/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */ +#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */ +#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC + +#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST +#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */ + +#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \ + LOONGSON_PCI_MEM_START + 1) + +#else /* loongson2f/32bit & loongson2e */ /* this pci memory space is mapped by pcimap in pci.c */ -#define LOONGSON_PCI_MEM_START BONITO_PCILO1_BASE -#define LOONGSON_PCI_MEM_END (BONITO_PCILO1_BASE + 0x04000000 * 2) +#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE +#define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2) /* this is an offset from mips_io_port_base */ #define LOONGSON_PCI_IO_START 0x00004000UL -#endif +#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */ #endif /* !__ASM_MACH_LOONGSON_PCI_H_ */ diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h new file mode 100644 index 000000000000..bcad43a93ebf --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/asic.h @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ASM_MACH_POWERTV_ASIC_H +#define _ASM_MACH_POWERTV_ASIC_H + +#include <linux/ioport.h> +#include <asm/mach-powertv/asic_regs.h> + +#define DVR_CAPABLE (1<<0) +#define PCIE_CAPABLE (1<<1) +#define FFS_CAPABLE (1<<2) +#define DISPLAY_CAPABLE (1<<3) + +/* Platform Family types + * For compitability, the new value must be added in the end */ +enum family_type { + FAMILY_8500, + FAMILY_8500RNG, + FAMILY_4500, + FAMILY_1500, + FAMILY_8600, + FAMILY_4600, + FAMILY_4600VZA, + FAMILY_8600VZB, + FAMILY_1500VZE, + FAMILY_1500VZF, + FAMILIES +}; + +/* Register maps for each ASIC */ +extern const struct register_map calliope_register_map; +extern const struct register_map cronus_register_map; +extern const struct register_map zeus_register_map; + +extern struct resource dvr_cronus_resources[]; +extern struct resource dvr_zeus_resources[]; +extern struct resource non_dvr_calliope_resources[]; +extern struct resource non_dvr_cronus_resources[]; +extern struct resource non_dvr_cronuslite_resources[]; +extern struct resource non_dvr_vz_calliope_resources[]; +extern struct resource non_dvr_vze_calliope_resources[]; +extern struct resource non_dvr_vzf_calliope_resources[]; +extern struct resource non_dvr_zeus_resources[]; + +extern void powertv_platform_init(void); +extern void platform_alloc_bootmem(void); +extern enum asic_type platform_get_asic(void); +extern enum family_type platform_get_family(void); +extern int platform_supports_dvr(void); +extern int platform_supports_ffs(void); +extern int platform_supports_pcie(void); +extern int platform_supports_display(void); +extern void configure_platform(void); +extern void platform_configure_usb_ehci(void); +extern void platform_unconfigure_usb_ehci(void); +extern void platform_configure_usb_ohci(void); +extern void platform_unconfigure_usb_ohci(void); + +/* Platform Resources */ +#define ASIC_RESOURCE_GET_EXISTS 1 +extern struct resource *asic_resource_get(const char *name); +extern void platform_release_memory(void *baddr, int size); + +/* Reboot Cause */ +extern void set_reboot_cause(char code, unsigned int data, unsigned int data2); +extern void set_locked_reboot_cause(char code, unsigned int data, + unsigned int data2); + +enum sys_reboot_type { + sys_unknown_reboot = 0x00, /* Unknown reboot cause */ + sys_davic_change = 0x01, /* Reboot due to change in DAVIC + * mode */ + sys_user_reboot = 0x02, /* Reboot initiated by user */ + sys_system_reboot = 0x03, /* Reboot initiated by OS */ + sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */ + sys_silent_reboot = 0x05, /* Silent reboot */ + sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */ + sys_power_up_reboot = 0x07, /* Power on bootup. Older + * drivers may report as + * userReboot. */ + sys_code_change = 0x08, /* Reboot to take code change. + * Older drivers may report as + * userReboot. */ + sys_hardware_reset = 0x09, /* HW watchdog or front-panel + * reset button reset. Older + * drivers may report as + * userReboot. */ + sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */ +}; + +#endif /* _ASM_MACH_POWERTV_ASIC_H */ diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h new file mode 100644 index 000000000000..9a65c93782f9 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/asic_regs.h @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ASM_MACH_POWERTV_ASIC_H_ +#define __ASM_MACH_POWERTV_ASIC_H_ +#include <linux/io.h> + +/* ASIC types */ +enum asic_type { + ASIC_UNKNOWN, + ASIC_ZEUS, + ASIC_CALLIOPE, + ASIC_CRONUS, + ASIC_CRONUSLITE, + ASICS +}; + +/* hardcoded values read from Chip Version registers */ +#define CRONUS_10 0x0B4C1C20 +#define CRONUS_11 0x0B4C1C21 +#define CRONUSLITE_10 0x0B4C1C40 + +#define NAND_FLASH_BASE 0x03000000 +#define ZEUS_IO_BASE 0x09000000 +#define CALLIOPE_IO_BASE 0x08000000 +#define CRONUS_IO_BASE 0x09000000 +#define ASIC_IO_SIZE 0x01000000 + +/* Definitions for backward compatibility */ +#define UART1_INTSTAT uart1_intstat +#define UART1_INTEN uart1_inten +#define UART1_CONFIG1 uart1_config1 +#define UART1_CONFIG2 uart1_config2 +#define UART1_DIVISORHI uart1_divisorhi +#define UART1_DIVISORLO uart1_divisorlo +#define UART1_DATA uart1_data +#define UART1_STATUS uart1_status + +/* ASIC register enumeration */ +struct register_map { + u32 eic_slow0_strt_add; + u32 eic_cfg_bits; + u32 eic_ready_status; + + u32 chipver3; + u32 chipver2; + u32 chipver1; + u32 chipver0; + + u32 uart1_intstat; + u32 uart1_inten; + u32 uart1_config1; + u32 uart1_config2; + u32 uart1_divisorhi; + u32 uart1_divisorlo; + u32 uart1_data; + u32 uart1_status; + + u32 int_stat_3; + u32 int_stat_2; + u32 int_stat_1; + u32 int_stat_0; + u32 int_config; + u32 int_int_scan; + u32 ien_int_3; + u32 ien_int_2; + u32 ien_int_1; + u32 ien_int_0; + u32 int_level_3_3; + u32 int_level_3_2; + u32 int_level_3_1; + u32 int_level_3_0; + u32 int_level_2_3; + u32 int_level_2_2; + u32 int_level_2_1; + u32 int_level_2_0; + u32 int_level_1_3; + u32 int_level_1_2; + u32 int_level_1_1; + u32 int_level_1_0; + u32 int_level_0_3; + u32 int_level_0_2; + u32 int_level_0_1; + u32 int_level_0_0; + u32 int_docsis_en; + + u32 mips_pll_setup; + u32 usb_fs; + u32 test_bus; + u32 crt_spare; + u32 usb2_ohci_int_mask; + u32 usb2_strap; + u32 ehci_hcapbase; + u32 ohci_hc_revision; + u32 bcm1_bs_lmi_steer; + u32 usb2_control; + u32 usb2_stbus_obc; + u32 usb2_stbus_mess_size; + u32 usb2_stbus_chunk_size; + + u32 pcie_regs; + u32 tim_ch; + u32 tim_cl; + u32 gpio_dout; + u32 gpio_din; + u32 gpio_dir; + u32 watchdog; + u32 front_panel; + + u32 register_maps; +}; + +extern enum asic_type asic; +extern const struct register_map *register_map; +extern unsigned long asic_phy_base; /* Physical address of ASIC */ +extern unsigned long asic_base; /* Virtual address of ASIC */ + +/* + * Macros to interface to registers through their ioremapped address + * asic_reg_offset Returns the offset of a given register from the start + * of the ASIC address space + * asic_reg_phys_addr Returns the physical address of the given register + * asic_reg_addr Returns the iomapped virtual address of the given + * register. + */ +#define asic_reg_offset(x) (register_map->x) +#define asic_reg_phys_addr(x) (asic_phy_base + asic_reg_offset(x)) +#define asic_reg_addr(x) \ + ((unsigned int *) (asic_base + asic_reg_offset(x))) + +/* + * The asic_reg macro is gone. It should be replaced by either asic_read or + * asic_write, as appropriate. + */ + +#define asic_read(x) readl(asic_reg_addr(x)) +#define asic_write(v, x) writel(v, asic_reg_addr(x)) + +extern void asic_irq_init(void); +#endif diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h new file mode 100644 index 000000000000..5b8d5ebeb838 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h @@ -0,0 +1,119 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Version from mach-generic modified to support PowerTV port + * Portions Copyright (C) 2009 Cisco Systems, Inc. + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> + * + */ + +#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H +#define __ASM_MACH_POWERTV_DMA_COHERENCE_H + +#include <linux/sched.h> +#include <linux/version.h> +#include <linux/device.h> +#include <asm/mach-powertv/asic.h> + +static inline bool is_kseg2(void *addr) +{ + return (unsigned long)addr >= KSEG2; +} + +static inline unsigned long virt_to_phys_from_pte(void *addr) +{ + pgd_t *pgd; + pud_t *pud; + pmd_t *pmd; + pte_t *ptep, pte; + + unsigned long virt_addr = (unsigned long)addr; + unsigned long phys_addr = 0UL; + + /* get the page global directory. */ + pgd = pgd_offset_k(virt_addr); + + if (!pgd_none(*pgd)) { + /* get the page upper directory */ + pud = pud_offset(pgd, virt_addr); + if (!pud_none(*pud)) { + /* get the page middle directory */ + pmd = pmd_offset(pud, virt_addr); + if (!pmd_none(*pmd)) { + /* get a pointer to the page table entry */ + ptep = pte_offset(pmd, virt_addr); + pte = *ptep; + /* check for a valid page */ + if (pte_present(pte)) { + /* get the physical address the page is + * refering to */ + phys_addr = (unsigned long) + page_to_phys(pte_page(pte)); + /* add the offset within the page */ + phys_addr |= (virt_addr & ~PAGE_MASK); + } + } + } + } + + return phys_addr; +} + +static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, + size_t size) +{ + if (is_kseg2(addr)) + return phys_to_bus(virt_to_phys_from_pte(addr)); + else + return phys_to_bus(virt_to_phys(addr)); +} + +static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, + struct page *page) +{ + return phys_to_bus(page_to_phys(page)); +} + +static inline unsigned long plat_dma_addr_to_phys(struct device *dev, + dma_addr_t dma_addr) +{ + return bus_to_phys(dma_addr); +} + +static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, + size_t size, enum dma_data_direction direction) +{ +} + +static inline int plat_dma_supported(struct device *dev, u64 mask) +{ + /* + * we fall back to GFP_DMA when the mask isn't all 1s, + * so we can't guarantee allocations that must be + * within a tighter range than GFP_DMA.. + */ + if (mask < DMA_BIT_MASK(24)) + return 0; + + return 1; +} + +static inline void plat_extra_sync_for_device(struct device *dev) +{ + return; +} + +static inline int plat_dma_mapping_error(struct device *dev, + dma_addr_t dma_addr) +{ + return 0; +} + +static inline int plat_device_is_coherent(struct device *dev) +{ + return 0; +} + +#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */ diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h new file mode 100644 index 000000000000..629a57413657 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/interrupts.h @@ -0,0 +1,254 @@ +/* + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_ +#define _ASM_MACH_POWERTV_INTERRUPTS_H_ + +/* + * Defines for all of the interrupt lines + */ + +/* Definitions for backward compatibility */ +#define kIrq_Uart1 irq_uart1 + +#define ibase 0 + +/*------------- Register: int_stat_3 */ +/* 126 unused (bit 31) */ +#define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */ +#define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */ +#define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */ +#define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */ +#define irq_fdma_gp (ibase+122) /* FDMA GP Output */ +#define irq_mips_pic (ibase+121) /* MIPS Performance Counter + * Interrupt */ +#define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */ +#define irq_memory_protect (ibase+119) /* Memory Protection Interrupt + * -- Ored by glue logic inside + * SPARC ILC (see + * INT_MEM_PROT_STAT, below, + * for individual interrupts) + */ +/* 118 unused (bit 22) */ +#define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by + * glue logic inside SPARC ILC + * (see INT_SBAG_STAT, below, + * for individual interrupts) */ +#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */ +#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */ +/* 114 unused (bit 18) */ +#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt -- + * Ored by glue logic inside + * SPARC ILC (see + * INT_MAILBOX_STAT, below, for + * individual interrupts) */ +#define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */ +#define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */ +#define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse + * Status 3 */ +#define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse + * Status 3 */ +#define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0 + * Interrupt */ +#define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1 + * Interrupt */ +#define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE + * Interrupt */ +#define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0 + * Interrupt */ +#define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1 + * Interrupt */ +#define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE + * Interrupt */ +#define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */ +#define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA + * Interrupt */ +#define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */ +#define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */ +#define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */ +#define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */ +#define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */ +#define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */ +/*------------- Register: int_stat_2 */ +#define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */ +#define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */ +#define irq_timer2 (ibase+93) /* Programmable Timer + * Interrupt 2 */ +#define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */ +#define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */ +#define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */ +#define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */ +#define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */ +#define irq_afe1 (ibase+88) /* AFE 1 Interrupt */ +#define irq_sata (ibase+87) /* SATA 1 Interrupt */ +#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */ +#define irq_dtcp (ibase+86) /* DTCP Interrupt */ +#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */ +/* 84 unused (bit 20) */ +/* 83 unused (bit 19) */ +/* 82 unused (bit 18) */ +#define irq_sata2 (ibase+81) /* SATA2 Interrupt */ +#define irq_uart2 (ibase+80) /* UART2 Interrupt */ +#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1 + * Host module) */ +#define irq_pod (ibase+78) /* POD Interrupt */ +#define irq_slave_usb (ibase+77) /* Slave USB */ +#define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */ +#define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */ +#define irq_afe2 (ibase+74) /* AFE 2 Interrupt */ +#define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */ +#define irq_asc2 (ibase+72) /* ASC #2 Interrupt */ +#define irq_asc1 (ibase+71) /* ASC #1 Interrupt */ +#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */ +#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */ +#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */ +/* 67 unused (bit 03) */ +/* 66 unused (bit 02) */ +/* 65 unused (bit 01) */ +/* 64 unused (bit 00) */ +/*------------- Register: int_stat_1 */ +/* 63 unused (bit 31) */ +/* 62 unused (bit 30) */ +/* 61 unused (bit 29) */ +/* 60 unused (bit 28) */ +/* 59 unused (bit 27) */ +/* 58 unused (bit 26) */ +/* 57 unused (bit 25) */ +/* 56 unused (bit 24) */ +#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory + * Interrupt */ +#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit + * Interrupt */ +#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit + * Interrupt */ +#define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error + * Interrupt */ +#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive + * Interrupt */ +#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive + * Interrupt */ +#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error + * Interrupt */ +#define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play + * Interrupt */ +#define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error + * Interrupt */ +#define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High + * (Chans 63-32) */ +#define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low + * (Chans 31-0) */ +#define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High + * (Chans 63-32) */ +#define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low + * (Chans 31-0) */ +#define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error + * Interrupt */ +#define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */ +#define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready + * Interrupt */ +#define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */ +#define irq_gpio3 (ibase+38) /* GP I/O IRQ 3 - From GP I/O + * Module */ +#define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O + * Module (ABE_intN) */ +#define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or + * Discontinuity 1 */ +#define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or + * Discontinuity 2 */ +#define irq_parse_peierr (ibase+34) /* PID Parser Error Detect + * (PEI) */ +#define irq_parse_cont_err (ibase+33) /* PID Parser continuity error + * detect */ +#define irq_ds1framer (ibase+32) /* DS1 Framer Interrupt */ +/*------------- Register: int_stat_0 */ +#define irq_gpio1 (ibase+31) /* GP I/O IRQ 1 - From GP I/O + * Module */ +#define irq_gpio0 (ibase+30) /* GP I/O IRQ 0 - From GP I/O + * Module */ +#define irq_qpsk_out_aloha (ibase+29) /* QPSK Output Slotted Aloha + * (chan 3) Transmission + * Completed OK */ +#define irq_qpsk_out_tdma (ibase+28) /* QPSK Output TDMA (chan 2) + * Transmission Completed OK */ +#define irq_qpsk_out_reserve (ibase+27) /* QPSK Output Reservation + * (chan 1) Transmission + * Completed OK */ +#define irq_qpsk_out_aloha_err (ibase+26) /* QPSK Output Slotted Aloha + * (chan 3)Transmission + * completed with Errors. */ +#define irq_qpsk_out_tdma_err (ibase+25) /* QPSK Output TDMA (chan 2) + * Transmission completed with + * Errors. */ +#define irq_qpsk_out_rsrv_err (ibase+24) /* QPSK Output Reservation + * (chan 1) Transmission + * completed with Errors */ +#define irq_aloha_fail (ibase+23) /* Unsuccessful Resend of Aloha + * for N times. Aloha retry + * timeout for channel 3. */ +#define irq_timer1 (ibase+22) /* Programmable Timer + * Interrupt */ +#define irq_keyboard (ibase+21) /* Keyboard Module Interrupt */ +#define irq_i2c (ibase+20) /* I2C Module Interrupt */ +#define irq_spi (ibase+19) /* SPI Module Interrupt */ +#define irq_irblaster (ibase+18) /* IR Blaster Interrupt */ +#define irq_splice_detect (ibase+17) /* PID Key Change Interrupt or + * Splice Detect Interrupt */ +#define irq_se_micro (ibase+16) /* Secure Micro I/F Module + * Interrupt */ +#define irq_uart1 (ibase+15) /* UART Interrupt */ +#define irq_irrecv (ibase+14) /* IR Receiver Interrupt */ +#define irq_host_int1 (ibase+13) /* Host-to-Host Interrupt 1 */ +#define irq_host_int0 (ibase+12) /* Host-to-Host Interrupt 0 */ +#define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */ +#define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error + * Interrupt */ +/* 9 unused (bit 09) */ +/* 8 unused (bit 08) */ +#define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error + * Interrupt */ +#define irq_psilength_err (ibase+6) /* QAM PSI Length Error + * Interrupt */ +#define irq_esfforward (ibase+5) /* ESF Interrupt Mark From + * Forward Path Reference - + * every 3ms when forward Mbits + * and forward slot control + * bytes are updated. */ +#define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from + * Reverse Path Reference - + * delayed from forward mark by + * the ranging delay plus a + * fixed amount. When reverse + * Mbits and reverse slot + * control bytes are updated. + * Occurs every 3ms for 3.0M and + * 1.554 M upstream rates and + * every 6 ms for 256K upstream + * rate. */ +#define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on + * Channel 1. */ +#define irq_reservation (ibase+2) /* Partial (or Incremental) + * Reservation Message Completed + * or Slotted aloha verify for + * channel 1. */ +#define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify + * Interrupt or Reservation + * increment completed for + * channel 3. */ +#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */ +#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */ + diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h new file mode 100644 index 000000000000..e6276d5146e8 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/ioremap.h @@ -0,0 +1,90 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Portions Copyright (C) Cisco Systems, Inc. + */ +#ifndef __ASM_MACH_POWERTV_IOREMAP_H +#define __ASM_MACH_POWERTV_IOREMAP_H + +#include <linux/types.h> + +#define LOW_MEM_BOUNDARY_PHYS 0x20000000 +#define LOW_MEM_BOUNDARY_MASK (~(LOW_MEM_BOUNDARY_PHYS - 1)) + +/* + * The bus addresses are different than the physical addresses that + * the processor sees by an offset. This offset varies by ASIC + * version. Define a variable to hold the offset and some macros to + * make the conversion simpler. */ +extern unsigned long phys_to_bus_offset; + +#ifdef CONFIG_HIGHMEM +#define MEM_GAP_PHYS 0x60000000 +/* + * TODO: We will use the hard code for conversion between physical and + * bus until the bootloader releases their device tree to us. + */ +#define phys_to_bus(x) (((x) < LOW_MEM_BOUNDARY_PHYS) ? \ + ((x) + phys_to_bus_offset) : (x)) +#define bus_to_phys(x) (((x) < MEM_GAP_PHYS_ADDR) ? \ + ((x) - phys_to_bus_offset) : (x)) +#else +#define phys_to_bus(x) ((x) + phys_to_bus_offset) +#define bus_to_phys(x) ((x) - phys_to_bus_offset) +#endif + +/* + * Determine whether the address we are given is for an ASIC device + * Params: addr Address to check + * Returns: Zero if the address is not for ASIC devices, non-zero + * if it is. + */ +static inline int asic_is_device_addr(phys_t addr) +{ + return !((phys_t)addr & (phys_t) LOW_MEM_BOUNDARY_MASK); +} + +/* + * Determine whether the address we are given is external RAM mappable + * into KSEG1. + * Params: addr Address to check + * Returns: Zero if the address is not for external RAM and + */ +static inline int asic_is_lowmem_ram_addr(phys_t addr) +{ + /* + * The RAM always starts at the following address in the processor's + * physical address space + */ + static const phys_t phys_ram_base = 0x10000000; + phys_t bus_ram_base; + + bus_ram_base = phys_to_bus_offset + phys_ram_base; + + return addr >= bus_ram_base && + addr < (bus_ram_base + (LOW_MEM_BOUNDARY_PHYS - phys_ram_base)); +} + +/* + * Allow physical addresses to be fixed up to help peripherals located + * outside the low 32-bit range -- generic pass-through version. + */ +static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) +{ + return phys_addr; +} + +static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, + unsigned long flags) +{ + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return 0; +} +#endif /* __ASM_MACH_POWERTV_IOREMAP_H */ diff --git a/arch/mips/include/asm/mach-powertv/irq.h b/arch/mips/include/asm/mach-powertv/irq.h new file mode 100644 index 000000000000..4bd5d0c61a91 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/irq.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ASM_MACH_POWERTV_IRQ_H +#define _ASM_MACH_POWERTV_IRQ_H +#include <asm/mach-powertv/interrupts.h> + +#define MIPS_CPU_IRQ_BASE ibase +#define NR_IRQS 127 +#endif diff --git a/arch/mips/include/asm/mach-powertv/powertv-clock.h b/arch/mips/include/asm/mach-powertv/powertv-clock.h new file mode 100644 index 000000000000..6f3e9a0fcf8c --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/powertv-clock.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* + * Local definitions for the powertv PCI code + */ + +#ifndef _POWERTV_PCI_POWERTV_PCI_H_ +#define _POWERTV_PCI_POWERTV_PCI_H_ +extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); +extern int asic_pcie_init(void); +extern int asic_pcie_init(void); + +extern int log_level; +#endif diff --git a/arch/mips/include/asm/mach-excite/war.h b/arch/mips/include/asm/mach-powertv/war.h index 1f82180c1598..7ac05ecc512b 100644 --- a/arch/mips/include/asm/mach-excite/war.h +++ b/arch/mips/include/asm/mach-powertv/war.h @@ -3,10 +3,13 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * + * This version for the PowerTV platform copied from the Malta version. + * * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + * Portions copyright (C) 2009 Cisco Systems, Inc. */ -#ifndef __ASM_MIPS_MACH_EXCITE_WAR_H -#define __ASM_MIPS_MACH_EXCITE_WAR_H +#ifndef __ASM_MACH_POWERTV_WAR_H +#define __ASM_MACH_POWERTV_WAR_H #define R4600_V1_INDEX_ICACHEOP_WAR 0 #define R4600_V1_HIT_CACHEOP_WAR 0 @@ -14,12 +17,12 @@ #define R5432_CP0_INTERRUPT_WAR 0 #define BCM1250_M3_WAR 0 #define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 1 +#define MIPS_CACHE_SYNC_WAR 1 #define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 1 -#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 #define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 -#endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */ +#endif /* __ASM_MACH_POWERTV_WAR_H */ diff --git a/arch/mips/include/asm/mips-boards/bonito64.h b/arch/mips/include/asm/mips-boards/bonito64.h index a576ce044c3c..d14e2adc4be5 100644 --- a/arch/mips/include/asm/mips-boards/bonito64.h +++ b/arch/mips/include/asm/mips-boards/bonito64.h @@ -26,11 +26,6 @@ /* offsets from base register */ #define BONITO(x) (x) -#elif defined(CONFIG_LEMOTE_FULOONG2E) - -#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x))) -#define BONITO_IRQ_BASE 32 - #else /* diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index 6083db586500..145bb81ccaa5 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -24,6 +24,33 @@ #endif /* SMTC */ #include <asm-generic/mm_hooks.h> +#ifdef CONFIG_MIPS_PGD_C0_CONTEXT + +#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ + tlbmiss_handler_setup_pgd((unsigned long)(pgd)) + +static inline void tlbmiss_handler_setup_pgd(unsigned long pgd) +{ + /* Check for swapper_pg_dir and convert to physical address. */ + if ((pgd & CKSEG3) == CKSEG0) + pgd = CPHYSADDR(pgd); + write_c0_context(pgd << 11); +} + +#define TLBMISS_HANDLER_SETUP() \ + do { \ + TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ + write_c0_xcontext((unsigned long) smp_processor_id() << 51); \ + } while (0) + + +static inline unsigned long get_current_pgd(void) +{ + return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL); +} + +#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ + /* * For the fast tlb miss handlers, we keep a per cpu array of pointers * to the current pgd for each processor. Also, the proc. id is stuffed @@ -46,7 +73,7 @@ extern unsigned long pgd_current[]; back_to_back_c0_hazard(); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) #endif - +#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) #define ASID_INC 0x40 diff --git a/arch/mips/include/asm/octeon/cvmx-agl-defs.h b/arch/mips/include/asm/octeon/cvmx-agl-defs.h new file mode 100644 index 000000000000..ec94b9ab7be1 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-agl-defs.h @@ -0,0 +1,1194 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_AGL_DEFS_H__ +#define __CVMX_AGL_DEFS_H__ + +#define CVMX_AGL_GMX_BAD_REG \ + CVMX_ADD_IO_SEG(0x00011800E0000518ull) +#define CVMX_AGL_GMX_BIST \ + CVMX_ADD_IO_SEG(0x00011800E0000400ull) +#define CVMX_AGL_GMX_DRV_CTL \ + CVMX_ADD_IO_SEG(0x00011800E00007F0ull) +#define CVMX_AGL_GMX_INF_MODE \ + CVMX_ADD_IO_SEG(0x00011800E00007F8ull) +#define CVMX_AGL_GMX_PRTX_CFG(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000010ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000180ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000188ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000190ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000198ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) \ + CVMX_ADD_IO_SEG(0x00011800E00001A0ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) \ + CVMX_ADD_IO_SEG(0x00011800E00001A8ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000108ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000100ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_DECISION(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000040ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000020ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000018ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000030ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000028ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_IFG(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000058ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_INT_EN(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000008ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_INT_REG(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000000ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_JABBER(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000038ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000068ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000050ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000088ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000098ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) \ + CVMX_ADD_IO_SEG(0x00011800E00000A8ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) \ + CVMX_ADD_IO_SEG(0x00011800E00000B8ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000080ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) \ + CVMX_ADD_IO_SEG(0x00011800E00000C0ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000090ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) \ + CVMX_ADD_IO_SEG(0x00011800E00000A0ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) \ + CVMX_ADD_IO_SEG(0x00011800E00000B0ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000048ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_RX_BP_DROPX(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000420ull + (((offset) & 1) * 8)) +#define CVMX_AGL_GMX_RX_BP_OFFX(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000460ull + (((offset) & 1) * 8)) +#define CVMX_AGL_GMX_RX_BP_ONX(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000440ull + (((offset) & 1) * 8)) +#define CVMX_AGL_GMX_RX_PRT_INFO \ + CVMX_ADD_IO_SEG(0x00011800E00004E8ull) +#define CVMX_AGL_GMX_RX_TX_STATUS \ + CVMX_ADD_IO_SEG(0x00011800E00007E8ull) +#define CVMX_AGL_GMX_SMACX(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000230ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_STAT_BP \ + CVMX_ADD_IO_SEG(0x00011800E0000520ull) +#define CVMX_AGL_GMX_TXX_APPEND(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000218ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TXX_CTL(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000270ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000240ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000248ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000238ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000258ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000260ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000250ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TXX_STAT0(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000280ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TXX_STAT1(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000288ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TXX_STAT2(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000290ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TXX_STAT3(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000298ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TXX_STAT4(offset) \ + CVMX_ADD_IO_SEG(0x00011800E00002A0ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TXX_STAT5(offset) \ + CVMX_ADD_IO_SEG(0x00011800E00002A8ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TXX_STAT6(offset) \ + CVMX_ADD_IO_SEG(0x00011800E00002B0ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TXX_STAT7(offset) \ + CVMX_ADD_IO_SEG(0x00011800E00002B8ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TXX_STAT8(offset) \ + CVMX_ADD_IO_SEG(0x00011800E00002C0ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TXX_STAT9(offset) \ + CVMX_ADD_IO_SEG(0x00011800E00002C8ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000268ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TXX_THRESH(offset) \ + CVMX_ADD_IO_SEG(0x00011800E0000210ull + (((offset) & 1) * 2048)) +#define CVMX_AGL_GMX_TX_BP \ + CVMX_ADD_IO_SEG(0x00011800E00004D0ull) +#define CVMX_AGL_GMX_TX_COL_ATTEMPT \ + CVMX_ADD_IO_SEG(0x00011800E0000498ull) +#define CVMX_AGL_GMX_TX_IFG \ + CVMX_ADD_IO_SEG(0x00011800E0000488ull) +#define CVMX_AGL_GMX_TX_INT_EN \ + CVMX_ADD_IO_SEG(0x00011800E0000508ull) +#define CVMX_AGL_GMX_TX_INT_REG \ + CVMX_ADD_IO_SEG(0x00011800E0000500ull) +#define CVMX_AGL_GMX_TX_JAM \ + CVMX_ADD_IO_SEG(0x00011800E0000490ull) +#define CVMX_AGL_GMX_TX_LFSR \ + CVMX_ADD_IO_SEG(0x00011800E00004F8ull) +#define CVMX_AGL_GMX_TX_OVR_BP \ + CVMX_ADD_IO_SEG(0x00011800E00004C8ull) +#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC \ + CVMX_ADD_IO_SEG(0x00011800E00004A0ull) +#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE \ + CVMX_ADD_IO_SEG(0x00011800E00004A8ull) + +union cvmx_agl_gmx_bad_reg { + uint64_t u64; + struct cvmx_agl_gmx_bad_reg_s { + uint64_t reserved_38_63:26; + uint64_t txpsh1:1; + uint64_t txpop1:1; + uint64_t ovrflw1:1; + uint64_t txpsh:1; + uint64_t txpop:1; + uint64_t ovrflw:1; + uint64_t reserved_27_31:5; + uint64_t statovr:1; + uint64_t reserved_23_25:3; + uint64_t loststat:1; + uint64_t reserved_4_21:18; + uint64_t out_ovr:2; + uint64_t reserved_0_1:2; + } s; + struct cvmx_agl_gmx_bad_reg_s cn52xx; + struct cvmx_agl_gmx_bad_reg_s cn52xxp1; + struct cvmx_agl_gmx_bad_reg_cn56xx { + uint64_t reserved_35_63:29; + uint64_t txpsh:1; + uint64_t txpop:1; + uint64_t ovrflw:1; + uint64_t reserved_27_31:5; + uint64_t statovr:1; + uint64_t reserved_23_25:3; + uint64_t loststat:1; + uint64_t reserved_3_21:19; + uint64_t out_ovr:1; + uint64_t reserved_0_1:2; + } cn56xx; + struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1; +}; + +union cvmx_agl_gmx_bist { + uint64_t u64; + struct cvmx_agl_gmx_bist_s { + uint64_t reserved_10_63:54; + uint64_t status:10; + } s; + struct cvmx_agl_gmx_bist_s cn52xx; + struct cvmx_agl_gmx_bist_s cn52xxp1; + struct cvmx_agl_gmx_bist_s cn56xx; + struct cvmx_agl_gmx_bist_s cn56xxp1; +}; + +union cvmx_agl_gmx_drv_ctl { + uint64_t u64; + struct cvmx_agl_gmx_drv_ctl_s { + uint64_t reserved_49_63:15; + uint64_t byp_en1:1; + uint64_t reserved_45_47:3; + uint64_t pctl1:5; + uint64_t reserved_37_39:3; + uint64_t nctl1:5; + uint64_t reserved_17_31:15; + uint64_t byp_en:1; + uint64_t reserved_13_15:3; + uint64_t pctl:5; + uint64_t reserved_5_7:3; + uint64_t nctl:5; + } s; + struct cvmx_agl_gmx_drv_ctl_s cn52xx; + struct cvmx_agl_gmx_drv_ctl_s cn52xxp1; + struct cvmx_agl_gmx_drv_ctl_cn56xx { + uint64_t reserved_17_63:47; + uint64_t byp_en:1; + uint64_t reserved_13_15:3; + uint64_t pctl:5; + uint64_t reserved_5_7:3; + uint64_t nctl:5; + } cn56xx; + struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1; +}; + +union cvmx_agl_gmx_inf_mode { + uint64_t u64; + struct cvmx_agl_gmx_inf_mode_s { + uint64_t reserved_2_63:62; + uint64_t en:1; + uint64_t reserved_0_0:1; + } s; + struct cvmx_agl_gmx_inf_mode_s cn52xx; + struct cvmx_agl_gmx_inf_mode_s cn52xxp1; + struct cvmx_agl_gmx_inf_mode_s cn56xx; + struct cvmx_agl_gmx_inf_mode_s cn56xxp1; +}; + +union cvmx_agl_gmx_prtx_cfg { + uint64_t u64; + struct cvmx_agl_gmx_prtx_cfg_s { + uint64_t reserved_6_63:58; + uint64_t tx_en:1; + uint64_t rx_en:1; + uint64_t slottime:1; + uint64_t duplex:1; + uint64_t speed:1; + uint64_t en:1; + } s; + struct cvmx_agl_gmx_prtx_cfg_s cn52xx; + struct cvmx_agl_gmx_prtx_cfg_s cn52xxp1; + struct cvmx_agl_gmx_prtx_cfg_s cn56xx; + struct cvmx_agl_gmx_prtx_cfg_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_adr_cam0 { + uint64_t u64; + struct cvmx_agl_gmx_rxx_adr_cam0_s { + uint64_t adr:64; + } s; + struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx; + struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1; + struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx; + struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_adr_cam1 { + uint64_t u64; + struct cvmx_agl_gmx_rxx_adr_cam1_s { + uint64_t adr:64; + } s; + struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx; + struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1; + struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx; + struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_adr_cam2 { + uint64_t u64; + struct cvmx_agl_gmx_rxx_adr_cam2_s { + uint64_t adr:64; + } s; + struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx; + struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1; + struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx; + struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_adr_cam3 { + uint64_t u64; + struct cvmx_agl_gmx_rxx_adr_cam3_s { + uint64_t adr:64; + } s; + struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx; + struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1; + struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx; + struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_adr_cam4 { + uint64_t u64; + struct cvmx_agl_gmx_rxx_adr_cam4_s { + uint64_t adr:64; + } s; + struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx; + struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1; + struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx; + struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_adr_cam5 { + uint64_t u64; + struct cvmx_agl_gmx_rxx_adr_cam5_s { + uint64_t adr:64; + } s; + struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx; + struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1; + struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx; + struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_adr_cam_en { + uint64_t u64; + struct cvmx_agl_gmx_rxx_adr_cam_en_s { + uint64_t reserved_8_63:56; + uint64_t en:8; + } s; + struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx; + struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1; + struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx; + struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_adr_ctl { + uint64_t u64; + struct cvmx_agl_gmx_rxx_adr_ctl_s { + uint64_t reserved_4_63:60; + uint64_t cam_mode:1; + uint64_t mcst:2; + uint64_t bcst:1; + } s; + struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx; + struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1; + struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx; + struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_decision { + uint64_t u64; + struct cvmx_agl_gmx_rxx_decision_s { + uint64_t reserved_5_63:59; + uint64_t cnt:5; + } s; + struct cvmx_agl_gmx_rxx_decision_s cn52xx; + struct cvmx_agl_gmx_rxx_decision_s cn52xxp1; + struct cvmx_agl_gmx_rxx_decision_s cn56xx; + struct cvmx_agl_gmx_rxx_decision_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_frm_chk { + uint64_t u64; + struct cvmx_agl_gmx_rxx_frm_chk_s { + uint64_t reserved_9_63:55; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t lenerr:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t maxerr:1; + uint64_t reserved_1_1:1; + uint64_t minerr:1; + } s; + struct cvmx_agl_gmx_rxx_frm_chk_s cn52xx; + struct cvmx_agl_gmx_rxx_frm_chk_s cn52xxp1; + struct cvmx_agl_gmx_rxx_frm_chk_s cn56xx; + struct cvmx_agl_gmx_rxx_frm_chk_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_frm_ctl { + uint64_t u64; + struct cvmx_agl_gmx_rxx_frm_ctl_s { + uint64_t reserved_10_63:54; + uint64_t pre_align:1; + uint64_t pad_len:1; + uint64_t vlan_len:1; + uint64_t pre_free:1; + uint64_t ctl_smac:1; + uint64_t ctl_mcst:1; + uint64_t ctl_bck:1; + uint64_t ctl_drp:1; + uint64_t pre_strp:1; + uint64_t pre_chk:1; + } s; + struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xx; + struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xxp1; + struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xx; + struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_frm_max { + uint64_t u64; + struct cvmx_agl_gmx_rxx_frm_max_s { + uint64_t reserved_16_63:48; + uint64_t len:16; + } s; + struct cvmx_agl_gmx_rxx_frm_max_s cn52xx; + struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1; + struct cvmx_agl_gmx_rxx_frm_max_s cn56xx; + struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_frm_min { + uint64_t u64; + struct cvmx_agl_gmx_rxx_frm_min_s { + uint64_t reserved_16_63:48; + uint64_t len:16; + } s; + struct cvmx_agl_gmx_rxx_frm_min_s cn52xx; + struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1; + struct cvmx_agl_gmx_rxx_frm_min_s cn56xx; + struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_ifg { + uint64_t u64; + struct cvmx_agl_gmx_rxx_ifg_s { + uint64_t reserved_4_63:60; + uint64_t ifg:4; + } s; + struct cvmx_agl_gmx_rxx_ifg_s cn52xx; + struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1; + struct cvmx_agl_gmx_rxx_ifg_s cn56xx; + struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_int_en { + uint64_t u64; + struct cvmx_agl_gmx_rxx_int_en_s { + uint64_t reserved_20_63:44; + uint64_t pause_drp:1; + uint64_t reserved_16_18:3; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t reserved_9_9:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t lenerr:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t maxerr:1; + uint64_t reserved_1_1:1; + uint64_t minerr:1; + } s; + struct cvmx_agl_gmx_rxx_int_en_s cn52xx; + struct cvmx_agl_gmx_rxx_int_en_s cn52xxp1; + struct cvmx_agl_gmx_rxx_int_en_s cn56xx; + struct cvmx_agl_gmx_rxx_int_en_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_int_reg { + uint64_t u64; + struct cvmx_agl_gmx_rxx_int_reg_s { + uint64_t reserved_20_63:44; + uint64_t pause_drp:1; + uint64_t reserved_16_18:3; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t reserved_9_9:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t lenerr:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t maxerr:1; + uint64_t reserved_1_1:1; + uint64_t minerr:1; + } s; + struct cvmx_agl_gmx_rxx_int_reg_s cn52xx; + struct cvmx_agl_gmx_rxx_int_reg_s cn52xxp1; + struct cvmx_agl_gmx_rxx_int_reg_s cn56xx; + struct cvmx_agl_gmx_rxx_int_reg_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_jabber { + uint64_t u64; + struct cvmx_agl_gmx_rxx_jabber_s { + uint64_t reserved_16_63:48; + uint64_t cnt:16; + } s; + struct cvmx_agl_gmx_rxx_jabber_s cn52xx; + struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1; + struct cvmx_agl_gmx_rxx_jabber_s cn56xx; + struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_pause_drop_time { + uint64_t u64; + struct cvmx_agl_gmx_rxx_pause_drop_time_s { + uint64_t reserved_16_63:48; + uint64_t status:16; + } s; + struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx; + struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1; + struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx; + struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_stats_ctl { + uint64_t u64; + struct cvmx_agl_gmx_rxx_stats_ctl_s { + uint64_t reserved_1_63:63; + uint64_t rd_clr:1; + } s; + struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx; + struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1; + struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx; + struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_stats_octs { + uint64_t u64; + struct cvmx_agl_gmx_rxx_stats_octs_s { + uint64_t reserved_48_63:16; + uint64_t cnt:48; + } s; + struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx; + struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx; + struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_stats_octs_ctl { + uint64_t u64; + struct cvmx_agl_gmx_rxx_stats_octs_ctl_s { + uint64_t reserved_48_63:16; + uint64_t cnt:48; + } s; + struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx; + struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx; + struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_stats_octs_dmac { + uint64_t u64; + struct cvmx_agl_gmx_rxx_stats_octs_dmac_s { + uint64_t reserved_48_63:16; + uint64_t cnt:48; + } s; + struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx; + struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx; + struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_stats_octs_drp { + uint64_t u64; + struct cvmx_agl_gmx_rxx_stats_octs_drp_s { + uint64_t reserved_48_63:16; + uint64_t cnt:48; + } s; + struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx; + struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1; + struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx; + struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_stats_pkts { + uint64_t u64; + struct cvmx_agl_gmx_rxx_stats_pkts_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx; + struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx; + struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_stats_pkts_bad { + uint64_t u64; + struct cvmx_agl_gmx_rxx_stats_pkts_bad_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx; + struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx; + struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_stats_pkts_ctl { + uint64_t u64; + struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx; + struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx; + struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_stats_pkts_dmac { + uint64_t u64; + struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx; + struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx; + struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_stats_pkts_drp { + uint64_t u64; + struct cvmx_agl_gmx_rxx_stats_pkts_drp_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx; + struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1; + struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx; + struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1; +}; + +union cvmx_agl_gmx_rxx_udd_skp { + uint64_t u64; + struct cvmx_agl_gmx_rxx_udd_skp_s { + uint64_t reserved_9_63:55; + uint64_t fcssel:1; + uint64_t reserved_7_7:1; + uint64_t len:7; + } s; + struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx; + struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1; + struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx; + struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1; +}; + +union cvmx_agl_gmx_rx_bp_dropx { + uint64_t u64; + struct cvmx_agl_gmx_rx_bp_dropx_s { + uint64_t reserved_6_63:58; + uint64_t mark:6; + } s; + struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx; + struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1; + struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx; + struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1; +}; + +union cvmx_agl_gmx_rx_bp_offx { + uint64_t u64; + struct cvmx_agl_gmx_rx_bp_offx_s { + uint64_t reserved_6_63:58; + uint64_t mark:6; + } s; + struct cvmx_agl_gmx_rx_bp_offx_s cn52xx; + struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1; + struct cvmx_agl_gmx_rx_bp_offx_s cn56xx; + struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1; +}; + +union cvmx_agl_gmx_rx_bp_onx { + uint64_t u64; + struct cvmx_agl_gmx_rx_bp_onx_s { + uint64_t reserved_9_63:55; + uint64_t mark:9; + } s; + struct cvmx_agl_gmx_rx_bp_onx_s cn52xx; + struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1; + struct cvmx_agl_gmx_rx_bp_onx_s cn56xx; + struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1; +}; + +union cvmx_agl_gmx_rx_prt_info { + uint64_t u64; + struct cvmx_agl_gmx_rx_prt_info_s { + uint64_t reserved_18_63:46; + uint64_t drop:2; + uint64_t reserved_2_15:14; + uint64_t commit:2; + } s; + struct cvmx_agl_gmx_rx_prt_info_s cn52xx; + struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1; + struct cvmx_agl_gmx_rx_prt_info_cn56xx { + uint64_t reserved_17_63:47; + uint64_t drop:1; + uint64_t reserved_1_15:15; + uint64_t commit:1; + } cn56xx; + struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1; +}; + +union cvmx_agl_gmx_rx_tx_status { + uint64_t u64; + struct cvmx_agl_gmx_rx_tx_status_s { + uint64_t reserved_6_63:58; + uint64_t tx:2; + uint64_t reserved_2_3:2; + uint64_t rx:2; + } s; + struct cvmx_agl_gmx_rx_tx_status_s cn52xx; + struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1; + struct cvmx_agl_gmx_rx_tx_status_cn56xx { + uint64_t reserved_5_63:59; + uint64_t tx:1; + uint64_t reserved_1_3:3; + uint64_t rx:1; + } cn56xx; + struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1; +}; + +union cvmx_agl_gmx_smacx { + uint64_t u64; + struct cvmx_agl_gmx_smacx_s { + uint64_t reserved_48_63:16; + uint64_t smac:48; + } s; + struct cvmx_agl_gmx_smacx_s cn52xx; + struct cvmx_agl_gmx_smacx_s cn52xxp1; + struct cvmx_agl_gmx_smacx_s cn56xx; + struct cvmx_agl_gmx_smacx_s cn56xxp1; +}; + +union cvmx_agl_gmx_stat_bp { + uint64_t u64; + struct cvmx_agl_gmx_stat_bp_s { + uint64_t reserved_17_63:47; + uint64_t bp:1; + uint64_t cnt:16; + } s; + struct cvmx_agl_gmx_stat_bp_s cn52xx; + struct cvmx_agl_gmx_stat_bp_s cn52xxp1; + struct cvmx_agl_gmx_stat_bp_s cn56xx; + struct cvmx_agl_gmx_stat_bp_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_append { + uint64_t u64; + struct cvmx_agl_gmx_txx_append_s { + uint64_t reserved_4_63:60; + uint64_t force_fcs:1; + uint64_t fcs:1; + uint64_t pad:1; + uint64_t preamble:1; + } s; + struct cvmx_agl_gmx_txx_append_s cn52xx; + struct cvmx_agl_gmx_txx_append_s cn52xxp1; + struct cvmx_agl_gmx_txx_append_s cn56xx; + struct cvmx_agl_gmx_txx_append_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_ctl { + uint64_t u64; + struct cvmx_agl_gmx_txx_ctl_s { + uint64_t reserved_2_63:62; + uint64_t xsdef_en:1; + uint64_t xscol_en:1; + } s; + struct cvmx_agl_gmx_txx_ctl_s cn52xx; + struct cvmx_agl_gmx_txx_ctl_s cn52xxp1; + struct cvmx_agl_gmx_txx_ctl_s cn56xx; + struct cvmx_agl_gmx_txx_ctl_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_min_pkt { + uint64_t u64; + struct cvmx_agl_gmx_txx_min_pkt_s { + uint64_t reserved_8_63:56; + uint64_t min_size:8; + } s; + struct cvmx_agl_gmx_txx_min_pkt_s cn52xx; + struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1; + struct cvmx_agl_gmx_txx_min_pkt_s cn56xx; + struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_pause_pkt_interval { + uint64_t u64; + struct cvmx_agl_gmx_txx_pause_pkt_interval_s { + uint64_t reserved_16_63:48; + uint64_t interval:16; + } s; + struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx; + struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1; + struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx; + struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_pause_pkt_time { + uint64_t u64; + struct cvmx_agl_gmx_txx_pause_pkt_time_s { + uint64_t reserved_16_63:48; + uint64_t time:16; + } s; + struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx; + struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1; + struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx; + struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_pause_togo { + uint64_t u64; + struct cvmx_agl_gmx_txx_pause_togo_s { + uint64_t reserved_16_63:48; + uint64_t time:16; + } s; + struct cvmx_agl_gmx_txx_pause_togo_s cn52xx; + struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1; + struct cvmx_agl_gmx_txx_pause_togo_s cn56xx; + struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_pause_zero { + uint64_t u64; + struct cvmx_agl_gmx_txx_pause_zero_s { + uint64_t reserved_1_63:63; + uint64_t send:1; + } s; + struct cvmx_agl_gmx_txx_pause_zero_s cn52xx; + struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1; + struct cvmx_agl_gmx_txx_pause_zero_s cn56xx; + struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_soft_pause { + uint64_t u64; + struct cvmx_agl_gmx_txx_soft_pause_s { + uint64_t reserved_16_63:48; + uint64_t time:16; + } s; + struct cvmx_agl_gmx_txx_soft_pause_s cn52xx; + struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1; + struct cvmx_agl_gmx_txx_soft_pause_s cn56xx; + struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_stat0 { + uint64_t u64; + struct cvmx_agl_gmx_txx_stat0_s { + uint64_t xsdef:32; + uint64_t xscol:32; + } s; + struct cvmx_agl_gmx_txx_stat0_s cn52xx; + struct cvmx_agl_gmx_txx_stat0_s cn52xxp1; + struct cvmx_agl_gmx_txx_stat0_s cn56xx; + struct cvmx_agl_gmx_txx_stat0_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_stat1 { + uint64_t u64; + struct cvmx_agl_gmx_txx_stat1_s { + uint64_t scol:32; + uint64_t mcol:32; + } s; + struct cvmx_agl_gmx_txx_stat1_s cn52xx; + struct cvmx_agl_gmx_txx_stat1_s cn52xxp1; + struct cvmx_agl_gmx_txx_stat1_s cn56xx; + struct cvmx_agl_gmx_txx_stat1_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_stat2 { + uint64_t u64; + struct cvmx_agl_gmx_txx_stat2_s { + uint64_t reserved_48_63:16; + uint64_t octs:48; + } s; + struct cvmx_agl_gmx_txx_stat2_s cn52xx; + struct cvmx_agl_gmx_txx_stat2_s cn52xxp1; + struct cvmx_agl_gmx_txx_stat2_s cn56xx; + struct cvmx_agl_gmx_txx_stat2_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_stat3 { + uint64_t u64; + struct cvmx_agl_gmx_txx_stat3_s { + uint64_t reserved_32_63:32; + uint64_t pkts:32; + } s; + struct cvmx_agl_gmx_txx_stat3_s cn52xx; + struct cvmx_agl_gmx_txx_stat3_s cn52xxp1; + struct cvmx_agl_gmx_txx_stat3_s cn56xx; + struct cvmx_agl_gmx_txx_stat3_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_stat4 { + uint64_t u64; + struct cvmx_agl_gmx_txx_stat4_s { + uint64_t hist1:32; + uint64_t hist0:32; + } s; + struct cvmx_agl_gmx_txx_stat4_s cn52xx; + struct cvmx_agl_gmx_txx_stat4_s cn52xxp1; + struct cvmx_agl_gmx_txx_stat4_s cn56xx; + struct cvmx_agl_gmx_txx_stat4_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_stat5 { + uint64_t u64; + struct cvmx_agl_gmx_txx_stat5_s { + uint64_t hist3:32; + uint64_t hist2:32; + } s; + struct cvmx_agl_gmx_txx_stat5_s cn52xx; + struct cvmx_agl_gmx_txx_stat5_s cn52xxp1; + struct cvmx_agl_gmx_txx_stat5_s cn56xx; + struct cvmx_agl_gmx_txx_stat5_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_stat6 { + uint64_t u64; + struct cvmx_agl_gmx_txx_stat6_s { + uint64_t hist5:32; + uint64_t hist4:32; + } s; + struct cvmx_agl_gmx_txx_stat6_s cn52xx; + struct cvmx_agl_gmx_txx_stat6_s cn52xxp1; + struct cvmx_agl_gmx_txx_stat6_s cn56xx; + struct cvmx_agl_gmx_txx_stat6_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_stat7 { + uint64_t u64; + struct cvmx_agl_gmx_txx_stat7_s { + uint64_t hist7:32; + uint64_t hist6:32; + } s; + struct cvmx_agl_gmx_txx_stat7_s cn52xx; + struct cvmx_agl_gmx_txx_stat7_s cn52xxp1; + struct cvmx_agl_gmx_txx_stat7_s cn56xx; + struct cvmx_agl_gmx_txx_stat7_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_stat8 { + uint64_t u64; + struct cvmx_agl_gmx_txx_stat8_s { + uint64_t mcst:32; + uint64_t bcst:32; + } s; + struct cvmx_agl_gmx_txx_stat8_s cn52xx; + struct cvmx_agl_gmx_txx_stat8_s cn52xxp1; + struct cvmx_agl_gmx_txx_stat8_s cn56xx; + struct cvmx_agl_gmx_txx_stat8_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_stat9 { + uint64_t u64; + struct cvmx_agl_gmx_txx_stat9_s { + uint64_t undflw:32; + uint64_t ctl:32; + } s; + struct cvmx_agl_gmx_txx_stat9_s cn52xx; + struct cvmx_agl_gmx_txx_stat9_s cn52xxp1; + struct cvmx_agl_gmx_txx_stat9_s cn56xx; + struct cvmx_agl_gmx_txx_stat9_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_stats_ctl { + uint64_t u64; + struct cvmx_agl_gmx_txx_stats_ctl_s { + uint64_t reserved_1_63:63; + uint64_t rd_clr:1; + } s; + struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx; + struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1; + struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx; + struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1; +}; + +union cvmx_agl_gmx_txx_thresh { + uint64_t u64; + struct cvmx_agl_gmx_txx_thresh_s { + uint64_t reserved_6_63:58; + uint64_t cnt:6; + } s; + struct cvmx_agl_gmx_txx_thresh_s cn52xx; + struct cvmx_agl_gmx_txx_thresh_s cn52xxp1; + struct cvmx_agl_gmx_txx_thresh_s cn56xx; + struct cvmx_agl_gmx_txx_thresh_s cn56xxp1; +}; + +union cvmx_agl_gmx_tx_bp { + uint64_t u64; + struct cvmx_agl_gmx_tx_bp_s { + uint64_t reserved_2_63:62; + uint64_t bp:2; + } s; + struct cvmx_agl_gmx_tx_bp_s cn52xx; + struct cvmx_agl_gmx_tx_bp_s cn52xxp1; + struct cvmx_agl_gmx_tx_bp_cn56xx { + uint64_t reserved_1_63:63; + uint64_t bp:1; + } cn56xx; + struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1; +}; + +union cvmx_agl_gmx_tx_col_attempt { + uint64_t u64; + struct cvmx_agl_gmx_tx_col_attempt_s { + uint64_t reserved_5_63:59; + uint64_t limit:5; + } s; + struct cvmx_agl_gmx_tx_col_attempt_s cn52xx; + struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1; + struct cvmx_agl_gmx_tx_col_attempt_s cn56xx; + struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1; +}; + +union cvmx_agl_gmx_tx_ifg { + uint64_t u64; + struct cvmx_agl_gmx_tx_ifg_s { + uint64_t reserved_8_63:56; + uint64_t ifg2:4; + uint64_t ifg1:4; + } s; + struct cvmx_agl_gmx_tx_ifg_s cn52xx; + struct cvmx_agl_gmx_tx_ifg_s cn52xxp1; + struct cvmx_agl_gmx_tx_ifg_s cn56xx; + struct cvmx_agl_gmx_tx_ifg_s cn56xxp1; +}; + +union cvmx_agl_gmx_tx_int_en { + uint64_t u64; + struct cvmx_agl_gmx_tx_int_en_s { + uint64_t reserved_18_63:46; + uint64_t late_col:2; + uint64_t reserved_14_15:2; + uint64_t xsdef:2; + uint64_t reserved_10_11:2; + uint64_t xscol:2; + uint64_t reserved_4_7:4; + uint64_t undflw:2; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; + } s; + struct cvmx_agl_gmx_tx_int_en_s cn52xx; + struct cvmx_agl_gmx_tx_int_en_s cn52xxp1; + struct cvmx_agl_gmx_tx_int_en_cn56xx { + uint64_t reserved_17_63:47; + uint64_t late_col:1; + uint64_t reserved_13_15:3; + uint64_t xsdef:1; + uint64_t reserved_9_11:3; + uint64_t xscol:1; + uint64_t reserved_3_7:5; + uint64_t undflw:1; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; + } cn56xx; + struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1; +}; + +union cvmx_agl_gmx_tx_int_reg { + uint64_t u64; + struct cvmx_agl_gmx_tx_int_reg_s { + uint64_t reserved_18_63:46; + uint64_t late_col:2; + uint64_t reserved_14_15:2; + uint64_t xsdef:2; + uint64_t reserved_10_11:2; + uint64_t xscol:2; + uint64_t reserved_4_7:4; + uint64_t undflw:2; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; + } s; + struct cvmx_agl_gmx_tx_int_reg_s cn52xx; + struct cvmx_agl_gmx_tx_int_reg_s cn52xxp1; + struct cvmx_agl_gmx_tx_int_reg_cn56xx { + uint64_t reserved_17_63:47; + uint64_t late_col:1; + uint64_t reserved_13_15:3; + uint64_t xsdef:1; + uint64_t reserved_9_11:3; + uint64_t xscol:1; + uint64_t reserved_3_7:5; + uint64_t undflw:1; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; + } cn56xx; + struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1; +}; + +union cvmx_agl_gmx_tx_jam { + uint64_t u64; + struct cvmx_agl_gmx_tx_jam_s { + uint64_t reserved_8_63:56; + uint64_t jam:8; + } s; + struct cvmx_agl_gmx_tx_jam_s cn52xx; + struct cvmx_agl_gmx_tx_jam_s cn52xxp1; + struct cvmx_agl_gmx_tx_jam_s cn56xx; + struct cvmx_agl_gmx_tx_jam_s cn56xxp1; +}; + +union cvmx_agl_gmx_tx_lfsr { + uint64_t u64; + struct cvmx_agl_gmx_tx_lfsr_s { + uint64_t reserved_16_63:48; + uint64_t lfsr:16; + } s; + struct cvmx_agl_gmx_tx_lfsr_s cn52xx; + struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1; + struct cvmx_agl_gmx_tx_lfsr_s cn56xx; + struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1; +}; + +union cvmx_agl_gmx_tx_ovr_bp { + uint64_t u64; + struct cvmx_agl_gmx_tx_ovr_bp_s { + uint64_t reserved_10_63:54; + uint64_t en:2; + uint64_t reserved_6_7:2; + uint64_t bp:2; + uint64_t reserved_2_3:2; + uint64_t ign_full:2; + } s; + struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx; + struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1; + struct cvmx_agl_gmx_tx_ovr_bp_cn56xx { + uint64_t reserved_9_63:55; + uint64_t en:1; + uint64_t reserved_5_7:3; + uint64_t bp:1; + uint64_t reserved_1_3:3; + uint64_t ign_full:1; + } cn56xx; + struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1; +}; + +union cvmx_agl_gmx_tx_pause_pkt_dmac { + uint64_t u64; + struct cvmx_agl_gmx_tx_pause_pkt_dmac_s { + uint64_t reserved_48_63:16; + uint64_t dmac:48; + } s; + struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx; + struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1; + struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx; + struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1; +}; + +union cvmx_agl_gmx_tx_pause_pkt_type { + uint64_t u64; + struct cvmx_agl_gmx_tx_pause_pkt_type_s { + uint64_t reserved_16_63:48; + uint64_t type:16; + } s; + struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx; + struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1; + struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx; + struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h new file mode 100644 index 000000000000..dab6dca492f9 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h @@ -0,0 +1,248 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_MIXX_DEFS_H__ +#define __CVMX_MIXX_DEFS_H__ + +#define CVMX_MIXX_BIST(offset) \ + CVMX_ADD_IO_SEG(0x0001070000100078ull + (((offset) & 1) * 2048)) +#define CVMX_MIXX_CTL(offset) \ + CVMX_ADD_IO_SEG(0x0001070000100020ull + (((offset) & 1) * 2048)) +#define CVMX_MIXX_INTENA(offset) \ + CVMX_ADD_IO_SEG(0x0001070000100050ull + (((offset) & 1) * 2048)) +#define CVMX_MIXX_IRCNT(offset) \ + CVMX_ADD_IO_SEG(0x0001070000100030ull + (((offset) & 1) * 2048)) +#define CVMX_MIXX_IRHWM(offset) \ + CVMX_ADD_IO_SEG(0x0001070000100028ull + (((offset) & 1) * 2048)) +#define CVMX_MIXX_IRING1(offset) \ + CVMX_ADD_IO_SEG(0x0001070000100010ull + (((offset) & 1) * 2048)) +#define CVMX_MIXX_IRING2(offset) \ + CVMX_ADD_IO_SEG(0x0001070000100018ull + (((offset) & 1) * 2048)) +#define CVMX_MIXX_ISR(offset) \ + CVMX_ADD_IO_SEG(0x0001070000100048ull + (((offset) & 1) * 2048)) +#define CVMX_MIXX_ORCNT(offset) \ + CVMX_ADD_IO_SEG(0x0001070000100040ull + (((offset) & 1) * 2048)) +#define CVMX_MIXX_ORHWM(offset) \ + CVMX_ADD_IO_SEG(0x0001070000100038ull + (((offset) & 1) * 2048)) +#define CVMX_MIXX_ORING1(offset) \ + CVMX_ADD_IO_SEG(0x0001070000100000ull + (((offset) & 1) * 2048)) +#define CVMX_MIXX_ORING2(offset) \ + CVMX_ADD_IO_SEG(0x0001070000100008ull + (((offset) & 1) * 2048)) +#define CVMX_MIXX_REMCNT(offset) \ + CVMX_ADD_IO_SEG(0x0001070000100058ull + (((offset) & 1) * 2048)) + +union cvmx_mixx_bist { + uint64_t u64; + struct cvmx_mixx_bist_s { + uint64_t reserved_4_63:60; + uint64_t mrqdat:1; + uint64_t ipfdat:1; + uint64_t irfdat:1; + uint64_t orfdat:1; + } s; + struct cvmx_mixx_bist_s cn52xx; + struct cvmx_mixx_bist_s cn52xxp1; + struct cvmx_mixx_bist_s cn56xx; + struct cvmx_mixx_bist_s cn56xxp1; +}; + +union cvmx_mixx_ctl { + uint64_t u64; + struct cvmx_mixx_ctl_s { + uint64_t reserved_8_63:56; + uint64_t crc_strip:1; + uint64_t busy:1; + uint64_t en:1; + uint64_t reset:1; + uint64_t lendian:1; + uint64_t nbtarb:1; + uint64_t mrq_hwm:2; + } s; + struct cvmx_mixx_ctl_s cn52xx; + struct cvmx_mixx_ctl_s cn52xxp1; + struct cvmx_mixx_ctl_s cn56xx; + struct cvmx_mixx_ctl_s cn56xxp1; +}; + +union cvmx_mixx_intena { + uint64_t u64; + struct cvmx_mixx_intena_s { + uint64_t reserved_7_63:57; + uint64_t orunena:1; + uint64_t irunena:1; + uint64_t data_drpena:1; + uint64_t ithena:1; + uint64_t othena:1; + uint64_t ivfena:1; + uint64_t ovfena:1; + } s; + struct cvmx_mixx_intena_s cn52xx; + struct cvmx_mixx_intena_s cn52xxp1; + struct cvmx_mixx_intena_s cn56xx; + struct cvmx_mixx_intena_s cn56xxp1; +}; + +union cvmx_mixx_ircnt { + uint64_t u64; + struct cvmx_mixx_ircnt_s { + uint64_t reserved_20_63:44; + uint64_t ircnt:20; + } s; + struct cvmx_mixx_ircnt_s cn52xx; + struct cvmx_mixx_ircnt_s cn52xxp1; + struct cvmx_mixx_ircnt_s cn56xx; + struct cvmx_mixx_ircnt_s cn56xxp1; +}; + +union cvmx_mixx_irhwm { + uint64_t u64; + struct cvmx_mixx_irhwm_s { + uint64_t reserved_40_63:24; + uint64_t ibplwm:20; + uint64_t irhwm:20; + } s; + struct cvmx_mixx_irhwm_s cn52xx; + struct cvmx_mixx_irhwm_s cn52xxp1; + struct cvmx_mixx_irhwm_s cn56xx; + struct cvmx_mixx_irhwm_s cn56xxp1; +}; + +union cvmx_mixx_iring1 { + uint64_t u64; + struct cvmx_mixx_iring1_s { + uint64_t reserved_60_63:4; + uint64_t isize:20; + uint64_t reserved_36_39:4; + uint64_t ibase:33; + uint64_t reserved_0_2:3; + } s; + struct cvmx_mixx_iring1_s cn52xx; + struct cvmx_mixx_iring1_s cn52xxp1; + struct cvmx_mixx_iring1_s cn56xx; + struct cvmx_mixx_iring1_s cn56xxp1; +}; + +union cvmx_mixx_iring2 { + uint64_t u64; + struct cvmx_mixx_iring2_s { + uint64_t reserved_52_63:12; + uint64_t itlptr:20; + uint64_t reserved_20_31:12; + uint64_t idbell:20; + } s; + struct cvmx_mixx_iring2_s cn52xx; + struct cvmx_mixx_iring2_s cn52xxp1; + struct cvmx_mixx_iring2_s cn56xx; + struct cvmx_mixx_iring2_s cn56xxp1; +}; + +union cvmx_mixx_isr { + uint64_t u64; + struct cvmx_mixx_isr_s { + uint64_t reserved_7_63:57; + uint64_t orun:1; + uint64_t irun:1; + uint64_t data_drp:1; + uint64_t irthresh:1; + uint64_t orthresh:1; + uint64_t idblovf:1; + uint64_t odblovf:1; + } s; + struct cvmx_mixx_isr_s cn52xx; + struct cvmx_mixx_isr_s cn52xxp1; + struct cvmx_mixx_isr_s cn56xx; + struct cvmx_mixx_isr_s cn56xxp1; +}; + +union cvmx_mixx_orcnt { + uint64_t u64; + struct cvmx_mixx_orcnt_s { + uint64_t reserved_20_63:44; + uint64_t orcnt:20; + } s; + struct cvmx_mixx_orcnt_s cn52xx; + struct cvmx_mixx_orcnt_s cn52xxp1; + struct cvmx_mixx_orcnt_s cn56xx; + struct cvmx_mixx_orcnt_s cn56xxp1; +}; + +union cvmx_mixx_orhwm { + uint64_t u64; + struct cvmx_mixx_orhwm_s { + uint64_t reserved_20_63:44; + uint64_t orhwm:20; + } s; + struct cvmx_mixx_orhwm_s cn52xx; + struct cvmx_mixx_orhwm_s cn52xxp1; + struct cvmx_mixx_orhwm_s cn56xx; + struct cvmx_mixx_orhwm_s cn56xxp1; +}; + +union cvmx_mixx_oring1 { + uint64_t u64; + struct cvmx_mixx_oring1_s { + uint64_t reserved_60_63:4; + uint64_t osize:20; + uint64_t reserved_36_39:4; + uint64_t obase:33; + uint64_t reserved_0_2:3; + } s; + struct cvmx_mixx_oring1_s cn52xx; + struct cvmx_mixx_oring1_s cn52xxp1; + struct cvmx_mixx_oring1_s cn56xx; + struct cvmx_mixx_oring1_s cn56xxp1; +}; + +union cvmx_mixx_oring2 { + uint64_t u64; + struct cvmx_mixx_oring2_s { + uint64_t reserved_52_63:12; + uint64_t otlptr:20; + uint64_t reserved_20_31:12; + uint64_t odbell:20; + } s; + struct cvmx_mixx_oring2_s cn52xx; + struct cvmx_mixx_oring2_s cn52xxp1; + struct cvmx_mixx_oring2_s cn56xx; + struct cvmx_mixx_oring2_s cn56xxp1; +}; + +union cvmx_mixx_remcnt { + uint64_t u64; + struct cvmx_mixx_remcnt_s { + uint64_t reserved_52_63:12; + uint64_t iremcnt:20; + uint64_t reserved_20_31:12; + uint64_t oremcnt:20; + } s; + struct cvmx_mixx_remcnt_s cn52xx; + struct cvmx_mixx_remcnt_s cn52xxp1; + struct cvmx_mixx_remcnt_s cn56xx; + struct cvmx_mixx_remcnt_s cn56xxp1; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-smix-defs.h b/arch/mips/include/asm/octeon/cvmx-smix-defs.h new file mode 100644 index 000000000000..9ae45fcbe3e3 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-smix-defs.h @@ -0,0 +1,178 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_SMIX_DEFS_H__ +#define __CVMX_SMIX_DEFS_H__ + +#define CVMX_SMIX_CLK(offset) \ + CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256)) +#define CVMX_SMIX_CMD(offset) \ + CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256)) +#define CVMX_SMIX_EN(offset) \ + CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256)) +#define CVMX_SMIX_RD_DAT(offset) \ + CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256)) +#define CVMX_SMIX_WR_DAT(offset) \ + CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256)) + +union cvmx_smix_clk { + uint64_t u64; + struct cvmx_smix_clk_s { + uint64_t reserved_25_63:39; + uint64_t mode:1; + uint64_t reserved_21_23:3; + uint64_t sample_hi:5; + uint64_t sample_mode:1; + uint64_t reserved_14_14:1; + uint64_t clk_idle:1; + uint64_t preamble:1; + uint64_t sample:4; + uint64_t phase:8; + } s; + struct cvmx_smix_clk_cn30xx { + uint64_t reserved_21_63:43; + uint64_t sample_hi:5; + uint64_t reserved_14_15:2; + uint64_t clk_idle:1; + uint64_t preamble:1; + uint64_t sample:4; + uint64_t phase:8; + } cn30xx; + struct cvmx_smix_clk_cn30xx cn31xx; + struct cvmx_smix_clk_cn30xx cn38xx; + struct cvmx_smix_clk_cn30xx cn38xxp2; + struct cvmx_smix_clk_cn50xx { + uint64_t reserved_25_63:39; + uint64_t mode:1; + uint64_t reserved_21_23:3; + uint64_t sample_hi:5; + uint64_t reserved_14_15:2; + uint64_t clk_idle:1; + uint64_t preamble:1; + uint64_t sample:4; + uint64_t phase:8; + } cn50xx; + struct cvmx_smix_clk_s cn52xx; + struct cvmx_smix_clk_cn50xx cn52xxp1; + struct cvmx_smix_clk_s cn56xx; + struct cvmx_smix_clk_cn50xx cn56xxp1; + struct cvmx_smix_clk_cn30xx cn58xx; + struct cvmx_smix_clk_cn30xx cn58xxp1; +}; + +union cvmx_smix_cmd { + uint64_t u64; + struct cvmx_smix_cmd_s { + uint64_t reserved_18_63:46; + uint64_t phy_op:2; + uint64_t reserved_13_15:3; + uint64_t phy_adr:5; + uint64_t reserved_5_7:3; + uint64_t reg_adr:5; + } s; + struct cvmx_smix_cmd_cn30xx { + uint64_t reserved_17_63:47; + uint64_t phy_op:1; + uint64_t reserved_13_15:3; + uint64_t phy_adr:5; + uint64_t reserved_5_7:3; + uint64_t reg_adr:5; + } cn30xx; + struct cvmx_smix_cmd_cn30xx cn31xx; + struct cvmx_smix_cmd_cn30xx cn38xx; + struct cvmx_smix_cmd_cn30xx cn38xxp2; + struct cvmx_smix_cmd_s cn50xx; + struct cvmx_smix_cmd_s cn52xx; + struct cvmx_smix_cmd_s cn52xxp1; + struct cvmx_smix_cmd_s cn56xx; + struct cvmx_smix_cmd_s cn56xxp1; + struct cvmx_smix_cmd_cn30xx cn58xx; + struct cvmx_smix_cmd_cn30xx cn58xxp1; +}; + +union cvmx_smix_en { + uint64_t u64; + struct cvmx_smix_en_s { + uint64_t reserved_1_63:63; + uint64_t en:1; + } s; + struct cvmx_smix_en_s cn30xx; + struct cvmx_smix_en_s cn31xx; + struct cvmx_smix_en_s cn38xx; + struct cvmx_smix_en_s cn38xxp2; + struct cvmx_smix_en_s cn50xx; + struct cvmx_smix_en_s cn52xx; + struct cvmx_smix_en_s cn52xxp1; + struct cvmx_smix_en_s cn56xx; + struct cvmx_smix_en_s cn56xxp1; + struct cvmx_smix_en_s cn58xx; + struct cvmx_smix_en_s cn58xxp1; +}; + +union cvmx_smix_rd_dat { + uint64_t u64; + struct cvmx_smix_rd_dat_s { + uint64_t reserved_18_63:46; + uint64_t pending:1; + uint64_t val:1; + uint64_t dat:16; + } s; + struct cvmx_smix_rd_dat_s cn30xx; + struct cvmx_smix_rd_dat_s cn31xx; + struct cvmx_smix_rd_dat_s cn38xx; + struct cvmx_smix_rd_dat_s cn38xxp2; + struct cvmx_smix_rd_dat_s cn50xx; + struct cvmx_smix_rd_dat_s cn52xx; + struct cvmx_smix_rd_dat_s cn52xxp1; + struct cvmx_smix_rd_dat_s cn56xx; + struct cvmx_smix_rd_dat_s cn56xxp1; + struct cvmx_smix_rd_dat_s cn58xx; + struct cvmx_smix_rd_dat_s cn58xxp1; +}; + +union cvmx_smix_wr_dat { + uint64_t u64; + struct cvmx_smix_wr_dat_s { + uint64_t reserved_18_63:46; + uint64_t pending:1; + uint64_t val:1; + uint64_t dat:16; + } s; + struct cvmx_smix_wr_dat_s cn30xx; + struct cvmx_smix_wr_dat_s cn31xx; + struct cvmx_smix_wr_dat_s cn38xx; + struct cvmx_smix_wr_dat_s cn38xxp2; + struct cvmx_smix_wr_dat_s cn50xx; + struct cvmx_smix_wr_dat_s cn52xx; + struct cvmx_smix_wr_dat_s cn52xxp1; + struct cvmx_smix_wr_dat_s cn56xx; + struct cvmx_smix_wr_dat_s cn56xxp1; + struct cvmx_smix_wr_dat_s cn58xx; + struct cvmx_smix_wr_dat_s cn58xxp1; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index cac9b1a206fc..4d0a8c61fc3e 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h @@ -47,6 +47,7 @@ struct octeon_cop2_state; extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state); extern void octeon_crypto_disable(struct octeon_cop2_state *state, unsigned long flags); +extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task); extern void octeon_init_cvmcount(void); diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index d6eb6134abec..1854336e56a2 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -390,6 +390,19 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma, #include <asm-generic/pgtable.h> /* + * uncached accelerated TLB map for video memory access + */ +#ifdef CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED +#define __HAVE_PHYS_MEM_ACCESS_PROT + +struct file; +pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, + unsigned long size, pgprot_t vma_prot); +int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, + unsigned long size, pgprot_t *vma_prot); +#endif + +/* * We provide our own get_unmapped area to cope with the virtual aliasing * constraints placed on us by the cache architecture. */ diff --git a/arch/mips/include/asm/sgialib.h b/arch/mips/include/asm/sgialib.h index bfce5c786f1c..63741ca1e422 100644 --- a/arch/mips/include/asm/sgialib.h +++ b/arch/mips/include/asm/sgialib.h @@ -85,8 +85,7 @@ extern void prom_identify_arch(void); extern PCHAR ArcGetEnvironmentVariable(PCHAR name); extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value); -/* ARCS command line acquisition and parsing. */ -extern char *prom_getcmdline(void); +/* ARCS command line parsing. */ extern void prom_init_cmdline(void); /* Acquiring info about the current time, etc. */ diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h index 5b60a09a0f08..21ef9efbde43 100644 --- a/arch/mips/include/asm/spinlock.h +++ b/arch/mips/include/asm/spinlock.h @@ -34,33 +34,33 @@ * becomes equal to the the initial value of the tail. */ -static inline int __raw_spin_is_locked(raw_spinlock_t *lock) +static inline int arch_spin_is_locked(arch_spinlock_t *lock) { unsigned int counters = ACCESS_ONCE(lock->lock); return ((counters >> 14) ^ counters) & 0x1fff; } -#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) -#define __raw_spin_unlock_wait(x) \ - while (__raw_spin_is_locked(x)) { cpu_relax(); } +#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock) +#define arch_spin_unlock_wait(x) \ + while (arch_spin_is_locked(x)) { cpu_relax(); } -static inline int __raw_spin_is_contended(raw_spinlock_t *lock) +static inline int arch_spin_is_contended(arch_spinlock_t *lock) { unsigned int counters = ACCESS_ONCE(lock->lock); return (((counters >> 14) - counters) & 0x1fff) > 1; } -#define __raw_spin_is_contended __raw_spin_is_contended +#define arch_spin_is_contended arch_spin_is_contended -static inline void __raw_spin_lock(raw_spinlock_t *lock) +static inline void arch_spin_lock(arch_spinlock_t *lock) { int my_ticket; int tmp; if (R10000_LLSC_WAR) { __asm__ __volatile__ ( - " .set push # __raw_spin_lock \n" + " .set push # arch_spin_lock \n" " .set noreorder \n" " \n" "1: ll %[ticket], %[ticket_ptr] \n" @@ -94,7 +94,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock) [my_ticket] "=&r" (my_ticket)); } else { __asm__ __volatile__ ( - " .set push # __raw_spin_lock \n" + " .set push # arch_spin_lock \n" " .set noreorder \n" " \n" " ll %[ticket], %[ticket_ptr] \n" @@ -134,7 +134,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock) smp_llsc_mb(); } -static inline void __raw_spin_unlock(raw_spinlock_t *lock) +static inline void arch_spin_unlock(arch_spinlock_t *lock) { int tmp; @@ -142,7 +142,7 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock) if (R10000_LLSC_WAR) { __asm__ __volatile__ ( - " # __raw_spin_unlock \n" + " # arch_spin_unlock \n" "1: ll %[ticket], %[ticket_ptr] \n" " addiu %[ticket], %[ticket], 1 \n" " ori %[ticket], %[ticket], 0x2000 \n" @@ -153,7 +153,7 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock) [ticket] "=&r" (tmp)); } else { __asm__ __volatile__ ( - " .set push # __raw_spin_unlock \n" + " .set push # arch_spin_unlock \n" " .set noreorder \n" " \n" " ll %[ticket], %[ticket_ptr] \n" @@ -174,13 +174,13 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock) } } -static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock) +static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock) { int tmp, tmp2, tmp3; if (R10000_LLSC_WAR) { __asm__ __volatile__ ( - " .set push # __raw_spin_trylock \n" + " .set push # arch_spin_trylock \n" " .set noreorder \n" " \n" "1: ll %[ticket], %[ticket_ptr] \n" @@ -204,7 +204,7 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock) [now_serving] "=&r" (tmp3)); } else { __asm__ __volatile__ ( - " .set push # __raw_spin_trylock \n" + " .set push # arch_spin_trylock \n" " .set noreorder \n" " \n" " ll %[ticket], %[ticket_ptr] \n" @@ -248,21 +248,21 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock) * read_can_lock - would read_trylock() succeed? * @lock: the rwlock in question. */ -#define __raw_read_can_lock(rw) ((rw)->lock >= 0) +#define arch_read_can_lock(rw) ((rw)->lock >= 0) /* * write_can_lock - would write_trylock() succeed? * @lock: the rwlock in question. */ -#define __raw_write_can_lock(rw) (!(rw)->lock) +#define arch_write_can_lock(rw) (!(rw)->lock) -static inline void __raw_read_lock(raw_rwlock_t *rw) +static inline void arch_read_lock(arch_rwlock_t *rw) { unsigned int tmp; if (R10000_LLSC_WAR) { __asm__ __volatile__( - " .set noreorder # __raw_read_lock \n" + " .set noreorder # arch_read_lock \n" "1: ll %1, %2 \n" " bltz %1, 1b \n" " addu %1, 1 \n" @@ -275,7 +275,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw) : "memory"); } else { __asm__ __volatile__( - " .set noreorder # __raw_read_lock \n" + " .set noreorder # arch_read_lock \n" "1: ll %1, %2 \n" " bltz %1, 2f \n" " addu %1, 1 \n" @@ -301,7 +301,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw) /* Note the use of sub, not subu which will make the kernel die with an overflow exception if we ever try to unlock an rwlock that is already unlocked or is being held by a writer. */ -static inline void __raw_read_unlock(raw_rwlock_t *rw) +static inline void arch_read_unlock(arch_rwlock_t *rw) { unsigned int tmp; @@ -309,7 +309,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw) if (R10000_LLSC_WAR) { __asm__ __volatile__( - "1: ll %1, %2 # __raw_read_unlock \n" + "1: ll %1, %2 # arch_read_unlock \n" " sub %1, 1 \n" " sc %1, %0 \n" " beqzl %1, 1b \n" @@ -318,7 +318,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw) : "memory"); } else { __asm__ __volatile__( - " .set noreorder # __raw_read_unlock \n" + " .set noreorder # arch_read_unlock \n" "1: ll %1, %2 \n" " sub %1, 1 \n" " sc %1, %0 \n" @@ -335,13 +335,13 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw) } } -static inline void __raw_write_lock(raw_rwlock_t *rw) +static inline void arch_write_lock(arch_rwlock_t *rw) { unsigned int tmp; if (R10000_LLSC_WAR) { __asm__ __volatile__( - " .set noreorder # __raw_write_lock \n" + " .set noreorder # arch_write_lock \n" "1: ll %1, %2 \n" " bnez %1, 1b \n" " lui %1, 0x8000 \n" @@ -354,7 +354,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw) : "memory"); } else { __asm__ __volatile__( - " .set noreorder # __raw_write_lock \n" + " .set noreorder # arch_write_lock \n" "1: ll %1, %2 \n" " bnez %1, 2f \n" " lui %1, 0x8000 \n" @@ -377,26 +377,26 @@ static inline void __raw_write_lock(raw_rwlock_t *rw) smp_llsc_mb(); } -static inline void __raw_write_unlock(raw_rwlock_t *rw) +static inline void arch_write_unlock(arch_rwlock_t *rw) { smp_mb(); __asm__ __volatile__( - " # __raw_write_unlock \n" + " # arch_write_unlock \n" " sw $0, %0 \n" : "=m" (rw->lock) : "m" (rw->lock) : "memory"); } -static inline int __raw_read_trylock(raw_rwlock_t *rw) +static inline int arch_read_trylock(arch_rwlock_t *rw) { unsigned int tmp; int ret; if (R10000_LLSC_WAR) { __asm__ __volatile__( - " .set noreorder # __raw_read_trylock \n" + " .set noreorder # arch_read_trylock \n" " li %2, 0 \n" "1: ll %1, %3 \n" " bltz %1, 2f \n" @@ -413,7 +413,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw) : "memory"); } else { __asm__ __volatile__( - " .set noreorder # __raw_read_trylock \n" + " .set noreorder # arch_read_trylock \n" " li %2, 0 \n" "1: ll %1, %3 \n" " bltz %1, 2f \n" @@ -433,14 +433,14 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw) return ret; } -static inline int __raw_write_trylock(raw_rwlock_t *rw) +static inline int arch_write_trylock(arch_rwlock_t *rw) { unsigned int tmp; int ret; if (R10000_LLSC_WAR) { __asm__ __volatile__( - " .set noreorder # __raw_write_trylock \n" + " .set noreorder # arch_write_trylock \n" " li %2, 0 \n" "1: ll %1, %3 \n" " bnez %1, 2f \n" @@ -457,7 +457,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw) : "memory"); } else { __asm__ __volatile__( - " .set noreorder # __raw_write_trylock \n" + " .set noreorder # arch_write_trylock \n" " li %2, 0 \n" "1: ll %1, %3 \n" " bnez %1, 2f \n" @@ -480,11 +480,11 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw) return ret; } -#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock) -#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock) +#define arch_read_lock_flags(lock, flags) arch_read_lock(lock) +#define arch_write_lock_flags(lock, flags) arch_write_lock(lock) -#define _raw_spin_relax(lock) cpu_relax() -#define _raw_read_relax(lock) cpu_relax() -#define _raw_write_relax(lock) cpu_relax() +#define arch_spin_relax(lock) cpu_relax() +#define arch_read_relax(lock) cpu_relax() +#define arch_write_relax(lock) cpu_relax() #endif /* _ASM_SPINLOCK_H */ diff --git a/arch/mips/include/asm/spinlock_types.h b/arch/mips/include/asm/spinlock_types.h index adeedaa116c1..ee197c2f9c98 100644 --- a/arch/mips/include/asm/spinlock_types.h +++ b/arch/mips/include/asm/spinlock_types.h @@ -12,14 +12,14 @@ typedef struct { * bits 15..28: ticket */ unsigned int lock; -} raw_spinlock_t; +} arch_spinlock_t; -#define __RAW_SPIN_LOCK_UNLOCKED { 0 } +#define __ARCH_SPIN_LOCK_UNLOCKED { 0 } typedef struct { volatile unsigned int lock; -} raw_rwlock_t; +} arch_rwlock_t; -#define __RAW_RW_LOCK_UNLOCKED { 0 } +#define __ARCH_RW_LOCK_UNLOCKED { 0 } #endif diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index db0fa7b5aeaf..3b6da3330e32 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -51,9 +51,6 @@ LONG_S v1, PT_ACX(sp) #else mfhi v1 - LONG_S v1, PT_HI(sp) - mflo v1 - LONG_S v1, PT_LO(sp) #endif #ifdef CONFIG_32BIT LONG_S $8, PT_R8(sp) @@ -62,10 +59,17 @@ LONG_S $10, PT_R10(sp) LONG_S $11, PT_R11(sp) LONG_S $12, PT_R12(sp) +#ifndef CONFIG_CPU_HAS_SMARTMIPS + LONG_S v1, PT_HI(sp) + mflo v1 +#endif LONG_S $13, PT_R13(sp) LONG_S $14, PT_R14(sp) LONG_S $15, PT_R15(sp) LONG_S $24, PT_R24(sp) +#ifndef CONFIG_CPU_HAS_SMARTMIPS + LONG_S v1, PT_LO(sp) +#endif .endm .macro SAVE_STATIC @@ -83,15 +87,19 @@ #ifdef CONFIG_SMP #ifdef CONFIG_MIPS_MT_SMTC #define PTEBASE_SHIFT 19 /* TCBIND */ +#define CPU_ID_REG CP0_TCBIND +#define CPU_ID_MFC0 mfc0 +#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT) +#define PTEBASE_SHIFT 48 /* XCONTEXT */ +#define CPU_ID_REG CP0_XCONTEXT +#define CPU_ID_MFC0 MFC0 #else #define PTEBASE_SHIFT 23 /* CONTEXT */ +#define CPU_ID_REG CP0_CONTEXT +#define CPU_ID_MFC0 MFC0 #endif .macro get_saved_sp /* SMP variation */ -#ifdef CONFIG_MIPS_MT_SMTC - mfc0 k0, CP0_TCBIND -#else - MFC0 k0, CP0_CONTEXT -#endif + CPU_ID_MFC0 k0, CPU_ID_REG #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) lui k1, %hi(kernelsp) #else @@ -107,11 +115,7 @@ .endm .macro set_saved_sp stackp temp temp2 -#ifdef CONFIG_MIPS_MT_SMTC - mfc0 \temp, CP0_TCBIND -#else - MFC0 \temp, CP0_CONTEXT -#endif + CPU_ID_MFC0 \temp, CPU_ID_REG LONG_SRL \temp, PTEBASE_SHIFT LONG_S \stackp, kernelsp(\temp) .endm @@ -166,7 +170,6 @@ LONG_S $0, PT_R0(sp) mfc0 v1, CP0_STATUS LONG_S $2, PT_R2(sp) - LONG_S v1, PT_STATUS(sp) #ifdef CONFIG_MIPS_MT_SMTC /* * Ideally, these instructions would be shuffled in @@ -178,20 +181,21 @@ LONG_S v1, PT_TCSTATUS(sp) #endif /* CONFIG_MIPS_MT_SMTC */ LONG_S $4, PT_R4(sp) - mfc0 v1, CP0_CAUSE LONG_S $5, PT_R5(sp) - LONG_S v1, PT_CAUSE(sp) + LONG_S v1, PT_STATUS(sp) + mfc0 v1, CP0_CAUSE LONG_S $6, PT_R6(sp) - MFC0 v1, CP0_EPC LONG_S $7, PT_R7(sp) + LONG_S v1, PT_CAUSE(sp) + MFC0 v1, CP0_EPC #ifdef CONFIG_64BIT LONG_S $8, PT_R8(sp) LONG_S $9, PT_R9(sp) #endif - LONG_S v1, PT_EPC(sp) LONG_S $25, PT_R25(sp) LONG_S $28, PT_R28(sp) LONG_S $31, PT_R31(sp) + LONG_S v1, PT_EPC(sp) ori $28, sp, _THREAD_MASK xori $28, _THREAD_MASK #ifdef CONFIG_CPU_CAVIUM_OCTEON |