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-rw-r--r--arch/mips/include/asm/txx9/jmr3927.h14
-rw-r--r--arch/mips/include/asm/txx9/rbtx4927.h6
-rw-r--r--arch/mips/include/asm/txx9/rbtx4938.h20
-rw-r--r--arch/mips/include/asm/txx9/rbtx4939.h14
-rw-r--r--arch/mips/include/asm/txx9/smsc_fdc37m81x.h54
-rw-r--r--arch/mips/include/asm/txx9/tx3927.h16
-rw-r--r--arch/mips/include/asm/txx9/tx4927.h18
-rw-r--r--arch/mips/include/asm/txx9/tx4927pcic.h6
-rw-r--r--arch/mips/include/asm/txx9/tx4938.h32
-rw-r--r--arch/mips/include/asm/txx9/tx4939.h50
10 files changed, 115 insertions, 115 deletions
diff --git a/arch/mips/include/asm/txx9/jmr3927.h b/arch/mips/include/asm/txx9/jmr3927.h
index 8808d7f82da0..aab959dc30ba 100644
--- a/arch/mips/include/asm/txx9/jmr3927.h
+++ b/arch/mips/include/asm/txx9/jmr3927.h
@@ -40,7 +40,7 @@
#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO)
#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000)
-#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000)
+#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000)
#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000)
#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000)
#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000)
@@ -115,9 +115,9 @@
#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */
#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */
-#define JMR3927_IRQ_IRC TXX9_IRQ_BASE
-#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
-#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
+#define JMR3927_IRQ_IRC TXX9_IRQ_BASE
+#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
+#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0)
#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1)
@@ -127,11 +127,11 @@
#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5)
#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0)
#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1)
-#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))
+#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))
#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA)
#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO)
#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI)
-#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))
+#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))
#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
@@ -147,7 +147,7 @@
#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3
/* Clocks */
-#define JMR3927_CORECLK 132710400 /* 132.7MHz */
+#define JMR3927_CORECLK 132710400 /* 132.7MHz */
/*
* TX3927 Pin Configuration:
diff --git a/arch/mips/include/asm/txx9/rbtx4927.h b/arch/mips/include/asm/txx9/rbtx4927.h
index b2adab3d1acc..4060ad26ca99 100644
--- a/arch/mips/include/asm/txx9/rbtx4927.h
+++ b/arch/mips/include/asm/txx9/rbtx4927.h
@@ -1,6 +1,6 @@
/*
* Author: MontaVista Software, Inc.
- * source@mvista.com
+ * source@mvista.com
*
* Copyright 2001-2002 MontaVista Software Inc.
*
@@ -38,7 +38,7 @@
#define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
#define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
#define RBTX4927_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
-#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
+#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
#define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002)
#define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006)
#define RBTX4927_BRAMRTC_BASE (IO_BASE + TXX9_CE(2) + 0x00010000)
@@ -50,7 +50,7 @@
#define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR)
#define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR)
#define rbtx4927_softint_addr ((__u8 __iomem *)RBTX4927_SOFTINT_ADDR)
-#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR)
+#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR)
#define rbtx4927_softresetlock_addr \
((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR)
#define rbtx4927_pcireset_addr ((__u8 __iomem *)RBTX4927_PCIRESET_ADDR)
diff --git a/arch/mips/include/asm/txx9/rbtx4938.h b/arch/mips/include/asm/txx9/rbtx4938.h
index 9f0441a28126..9c969dd3c6eb 100644
--- a/arch/mips/include/asm/txx9/rbtx4938.h
+++ b/arch/mips/include/asm/txx9/rbtx4938.h
@@ -36,7 +36,7 @@
#define RBTX4938_SPICS_ADDR (IO_BASE + TXX9_CE(2) + 0x00005002)
#define RBTX4938_SFPWR_ADDR (IO_BASE + TXX9_CE(2) + 0x00005008)
#define RBTX4938_SFVOL_ADDR (IO_BASE + TXX9_CE(2) + 0x0000500a)
-#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000)
+#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000)
#define RBTX4938_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x00007002)
#define RBTX4938_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007004)
#define RBTX4938_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000)
@@ -78,7 +78,7 @@
#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR)
#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR)
#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR)
-#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)
+#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)
#define rbtx4938_softresetlock_addr \
((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR)
#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR)
@@ -94,7 +94,7 @@
/* These are the virtual IRQ numbers, we divide all IRQ's into
* 'spaces', the 'space' determines where and how to enable/disable
- * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new
+ * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new
* IRQ hardware is supported.
*/
#define RBTX4938_NR_IRQ_IOC 8
@@ -103,18 +103,18 @@
#define RBTX4938_IRQ_IOC (TXX9_IRQ_BASE + TX4938_NUM_IR)
#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
-#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
-#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
-#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
-#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
+#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
+#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
+#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
+#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n))
#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
-#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
+#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
-#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
-#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
+#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
+#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
diff --git a/arch/mips/include/asm/txx9/rbtx4939.h b/arch/mips/include/asm/txx9/rbtx4939.h
index e517899794a8..6157bfd90848 100644
--- a/arch/mips/include/asm/txx9/rbtx4939.h
+++ b/arch/mips/include/asm/txx9/rbtx4939.h
@@ -17,7 +17,7 @@
/* Address map */
#define RBTX4939_IOC_REG_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
-#define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
+#define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
#define RBTX4939_IOC_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000002)
#define RBTX4939_CONFIG1_ADDR (IO_BASE + TXX9_CE(1) + 0x00000004)
#define RBTX4939_CONFIG2_ADDR (IO_BASE + TXX9_CE(1) + 0x00000006)
@@ -46,9 +46,9 @@
#define RBTX4939_VPSIN_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500c)
#define RBTX4939_7SEG_ADDR(s, ch) \
(IO_BASE + TXX9_CE(1) + 0x00006000 + (s) * 16 + ((ch) & 3) * 2)
-#define RBTX4939_SOFTRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00007000)
+#define RBTX4939_SOFTRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00007000)
#define RBTX4939_RESETEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00007002)
-#define RBTX4939_RESETSTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00007004)
+#define RBTX4939_RESETSTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00007004)
#define RBTX4939_ETHER_BASE (IO_BASE + TXX9_CE(1) + 0x00020000)
/* Ethernet port address */
@@ -77,11 +77,11 @@
#define RBTX4939_PE2_CIR 0x08
#define RBTX4939_PE2_SPI 0x10
#define RBTX4939_PE2_GPIO 0x20
-#define RBTX4939_PE3_VP 0x01
+#define RBTX4939_PE3_VP 0x01
#define RBTX4939_PE3_VP_P 0x02
#define RBTX4939_PE3_VP_S 0x04
-#define rbtx4939_board_rev_addr ((u8 __iomem *)RBTX4939_BOARD_REV_ADDR)
+#define rbtx4939_board_rev_addr ((u8 __iomem *)RBTX4939_BOARD_REV_ADDR)
#define rbtx4939_ioc_rev_addr ((u8 __iomem *)RBTX4939_IOC_REV_ADDR)
#define rbtx4939_config1_addr ((u8 __iomem *)RBTX4939_CONFIG1_ADDR)
#define rbtx4939_config2_addr ((u8 __iomem *)RBTX4939_CONFIG2_ADDR)
@@ -110,9 +110,9 @@
#define rbtx4939_vpsin_addr ((u8 __iomem *)RBTX4939_VPSIN_ADDR)
#define rbtx4939_7seg_addr(s, ch) \
((u8 __iomem *)RBTX4939_7SEG_ADDR(s, ch))
-#define rbtx4939_softreset_addr ((u8 __iomem *)RBTX4939_SOFTRESET_ADDR)
+#define rbtx4939_softreset_addr ((u8 __iomem *)RBTX4939_SOFTRESET_ADDR)
#define rbtx4939_reseten_addr ((u8 __iomem *)RBTX4939_RESETEN_ADDR)
-#define rbtx4939_resetstat_addr ((u8 __iomem *)RBTX4939_RESETSTAT_ADDR)
+#define rbtx4939_resetstat_addr ((u8 __iomem *)RBTX4939_RESETSTAT_ADDR)
/*
* IRQ mappings
diff --git a/arch/mips/include/asm/txx9/smsc_fdc37m81x.h b/arch/mips/include/asm/txx9/smsc_fdc37m81x.h
index d1d6332b4ca6..926d08f18463 100644
--- a/arch/mips/include/asm/txx9/smsc_fdc37m81x.h
+++ b/arch/mips/include/asm/txx9/smsc_fdc37m81x.h
@@ -18,43 +18,43 @@
/* Common Registers */
#define SMSC_FDC37M81X_CONFIG_INDEX 0x00
#define SMSC_FDC37M81X_CONFIG_DATA 0x01
-#define SMSC_FDC37M81X_CONF 0x02
-#define SMSC_FDC37M81X_INDEX 0x03
-#define SMSC_FDC37M81X_DNUM 0x07
-#define SMSC_FDC37M81X_DID 0x20
-#define SMSC_FDC37M81X_DREV 0x21
-#define SMSC_FDC37M81X_PCNT 0x22
-#define SMSC_FDC37M81X_PMGT 0x23
-#define SMSC_FDC37M81X_OSC 0x24
-#define SMSC_FDC37M81X_CONFPA0 0x26
-#define SMSC_FDC37M81X_CONFPA1 0x27
-#define SMSC_FDC37M81X_TEST4 0x2B
-#define SMSC_FDC37M81X_TEST5 0x2C
-#define SMSC_FDC37M81X_TEST1 0x2D
-#define SMSC_FDC37M81X_TEST2 0x2E
-#define SMSC_FDC37M81X_TEST3 0x2F
+#define SMSC_FDC37M81X_CONF 0x02
+#define SMSC_FDC37M81X_INDEX 0x03
+#define SMSC_FDC37M81X_DNUM 0x07
+#define SMSC_FDC37M81X_DID 0x20
+#define SMSC_FDC37M81X_DREV 0x21
+#define SMSC_FDC37M81X_PCNT 0x22
+#define SMSC_FDC37M81X_PMGT 0x23
+#define SMSC_FDC37M81X_OSC 0x24
+#define SMSC_FDC37M81X_CONFPA0 0x26
+#define SMSC_FDC37M81X_CONFPA1 0x27
+#define SMSC_FDC37M81X_TEST4 0x2B
+#define SMSC_FDC37M81X_TEST5 0x2C
+#define SMSC_FDC37M81X_TEST1 0x2D
+#define SMSC_FDC37M81X_TEST2 0x2E
+#define SMSC_FDC37M81X_TEST3 0x2F
/* Logical device numbers */
-#define SMSC_FDC37M81X_FDD 0x00
-#define SMSC_FDC37M81X_PARALLEL 0x03
-#define SMSC_FDC37M81X_SERIAL1 0x04
-#define SMSC_FDC37M81X_SERIAL2 0x05
-#define SMSC_FDC37M81X_KBD 0x07
-#define SMSC_FDC37M81X_AUXIO 0x08
-#define SMSC_FDC37M81X_NONE 0xff
+#define SMSC_FDC37M81X_FDD 0x00
+#define SMSC_FDC37M81X_PARALLEL 0x03
+#define SMSC_FDC37M81X_SERIAL1 0x04
+#define SMSC_FDC37M81X_SERIAL2 0x05
+#define SMSC_FDC37M81X_KBD 0x07
+#define SMSC_FDC37M81X_AUXIO 0x08
+#define SMSC_FDC37M81X_NONE 0xff
/* Logical device Config Registers */
-#define SMSC_FDC37M81X_ACTIVE 0x30
+#define SMSC_FDC37M81X_ACTIVE 0x30
#define SMSC_FDC37M81X_BASEADDR0 0x60
#define SMSC_FDC37M81X_BASEADDR1 0x61
-#define SMSC_FDC37M81X_INT 0x70
-#define SMSC_FDC37M81X_INT2 0x72
-#define SMSC_FDC37M81X_LDCR_F0 0xF0
+#define SMSC_FDC37M81X_INT 0x70
+#define SMSC_FDC37M81X_INT2 0x72
+#define SMSC_FDC37M81X_LDCR_F0 0xF0
/* Chip Config Values */
#define SMSC_FDC37M81X_CONFIG_ENTER 0x55
#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa
-#define SMSC_FDC37M81X_CHIP_ID 0x4d
+#define SMSC_FDC37M81X_CHIP_ID 0x4d
unsigned long smsc_fdc37m81x_init(unsigned long port);
diff --git a/arch/mips/include/asm/txx9/tx3927.h b/arch/mips/include/asm/txx9/tx3927.h
index dc30c8d42061..149fab4f8327 100644
--- a/arch/mips/include/asm/txx9/tx3927.h
+++ b/arch/mips/include/asm/txx9/tx3927.h
@@ -8,8 +8,8 @@
#ifndef __ASM_TXX9_TX3927_H
#define __ASM_TXX9_TX3927_H
-#define TX3927_REG_BASE 0xfffe0000UL
-#define TX3927_REG_SIZE 0x00010000
+#define TX3927_REG_BASE 0xfffe0000UL
+#define TX3927_REG_SIZE 0x00010000
#define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000)
#define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000)
#define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000)
@@ -191,8 +191,8 @@ struct tx3927_ccfg_reg {
#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2)
#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4)
#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5)
-#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
-#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
+#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
+#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
#define TX3927_DMA_CCR_MEMIO 0x00000002
#define TX3927_DMA_CCR_ONEAD 0x00000001
@@ -250,7 +250,7 @@ struct tx3927_ccfg_reg {
/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
/* bits for PBAPMC */
-#define TX3927_PCIC_PBAPMC_RPBA 0x00000004
+#define TX3927_PCIC_PBAPMC_RPBA 0x00000004
#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002
#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001
@@ -282,7 +282,7 @@ struct tx3927_ccfg_reg {
#define TX3927_CCFG_TLBOFF 0x00020000
#define TX3927_CCFG_BEOW 0x00010000
#define TX3927_CCFG_WR 0x00008000
-#define TX3927_CCFG_TOE 0x00004000
+#define TX3927_CCFG_TOE 0x00004000
#define TX3927_CCFG_PCIXARB 0x00002000
#define TX3927_CCFG_PCI3 0x00001000
#define TX3927_CCFG_PSNP 0x00000800
@@ -301,8 +301,8 @@ struct tx3927_ccfg_reg {
#define TX3927_PCFG_SELALL 0x0003ffff
#define TX3927_PCFG_SELCS 0x00020000
#define TX3927_PCFG_SELDSF 0x00010000
-#define TX3927_PCFG_SELSIOC_ALL 0x0000c000
-#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
+#define TX3927_PCFG_SELSIOC_ALL 0x0000c000
+#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
#define TX3927_PCFG_SELSIO_ALL 0x00003000
#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch))
#define TX3927_PCFG_SELTMR_ALL 0x00000e00
diff --git a/arch/mips/include/asm/txx9/tx4927.h b/arch/mips/include/asm/txx9/tx4927.h
index 18c98c52afdb..284eea752d55 100644
--- a/arch/mips/include/asm/txx9/tx4927.h
+++ b/arch/mips/include/asm/txx9/tx4927.h
@@ -1,6 +1,6 @@
/*
* Author: MontaVista Software, Inc.
- * source@mvista.com
+ * source@mvista.com
*
* Copyright 2001-2006 MontaVista Software Inc.
*
@@ -33,11 +33,11 @@
#include <asm/txx9/tx4927pcic.h>
#ifdef CONFIG_64BIT
-#define TX4927_REG_BASE 0xffffffffff1f0000UL
+#define TX4927_REG_BASE 0xffffffffff1f0000UL
#else
-#define TX4927_REG_BASE 0xff1f0000UL
+#define TX4927_REG_BASE 0xff1f0000UL
#endif
-#define TX4927_REG_SIZE 0x00010000
+#define TX4927_REG_SIZE 0x00010000
#define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)
#define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)
@@ -118,10 +118,10 @@ struct tx4927_ccfg_reg {
#define TX4927_CCFG_DIVMODE_2 (0x4 << 17)
#define TX4927_CCFG_DIVMODE_3 (0x5 << 17)
#define TX4927_CCFG_DIVMODE_4 (0x6 << 17)
-#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
+#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
#define TX4927_CCFG_BEOW 0x00010000
#define TX4927_CCFG_WR 0x00008000
-#define TX4927_CCFG_TOE 0x00004000
+#define TX4927_CCFG_TOE 0x00004000
#define TX4927_CCFG_PCIARB 0x00002000
#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
@@ -136,10 +136,10 @@ struct tx4927_ccfg_reg {
/* PCFG : Pin Configuration */
#define TX4927_PCFG_SDCLKDLY_MASK 0x30000000
-#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
+#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
#define TX4927_PCFG_SYSCLKEN 0x08000000
-#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
-#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
+#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
+#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
#define TX4927_PCFG_SEL2 0x00000200
diff --git a/arch/mips/include/asm/txx9/tx4927pcic.h b/arch/mips/include/asm/txx9/tx4927pcic.h
index c470b8a5fe57..9eab2698caec 100644
--- a/arch/mips/include/asm/txx9/tx4927pcic.h
+++ b/arch/mips/include/asm/txx9/tx4927pcic.h
@@ -93,7 +93,7 @@ struct tx4927_pcic_reg {
/* bits for PBACFG */
#define TX4927_PCIC_PBACFG_FIXPA 0x00000008
-#define TX4927_PCIC_PBACFG_RPBA 0x00000004
+#define TX4927_PCIC_PBACFG_RPBA 0x00000004
#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
@@ -165,7 +165,7 @@ struct tx4927_pcic_reg {
#define TX4927_PCIC_PDMCFG_CHNEN 0x00000080
#define TX4927_PCIC_PDMCFG_XFRACT 0x00000040
#define TX4927_PCIC_PDMCFG_BSWAP 0x00000020
-#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
+#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
#define TX4927_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000
#define TX4927_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004
#define TX4927_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008
@@ -174,7 +174,7 @@ struct tx4927_pcic_reg {
/* bits for PDMSTS */
#define TX4927_PCIC_PDMSTS_REQCNT_MASK 0x3f000000
-#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
+#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
#define TX4927_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000
#define TX4927_PCIC_PDMSTS_FIFORP_MASK 0x00030000
#define TX4927_PCIC_PDMSTS_ERRINT 0x00000800
diff --git a/arch/mips/include/asm/txx9/tx4938.h b/arch/mips/include/asm/txx9/tx4938.h
index 8a178f186f7d..6ca767ee6467 100644
--- a/arch/mips/include/asm/txx9/tx4938.h
+++ b/arch/mips/include/asm/txx9/tx4938.h
@@ -16,11 +16,11 @@
#include <asm/txx9/tx4927.h>
#ifdef CONFIG_64BIT
-#define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */
+#define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */
#else
-#define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */
+#define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */
#endif
-#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
+#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
#define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000)
@@ -72,16 +72,16 @@ struct tx4938_ccfg_reg {
#define TX4938_NUM_IR_DMA 4
#define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
#define TX4938_IR_PIO 14
-#define TX4938_IR_PDMAC 15
+#define TX4938_IR_PDMAC 15
#define TX4938_IR_PCIC 16
#define TX4938_NUM_IR_TMR 3
#define TX4938_IR_TMR(n) (17 + (n))
-#define TX4938_IR_NDFMC 21
+#define TX4938_IR_NDFMC 21
#define TX4938_IR_PCIERR 22
#define TX4938_IR_PCIPME 23
#define TX4938_IR_ACLC 24
#define TX4938_IR_ACLCPME 25
-#define TX4938_IR_PCIC1 26
+#define TX4938_IR_PCIC1 26
#define TX4938_IR_SPI 31
#define TX4938_NUM_IR 32
/* multiplex */
@@ -105,10 +105,10 @@ struct tx4938_ccfg_reg {
#define TX4938_CCFG_PCI1_66 0x00200000
#define TX4938_CCFG_DIVMODE_MASK 0x001e0000
#define TX4938_CCFG_DIVMODE_2 (0x4 << 17)
-#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
+#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
#define TX4938_CCFG_DIVMODE_3 (0x5 << 17)
#define TX4938_CCFG_DIVMODE_4 (0x6 << 17)
-#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
+#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
#define TX4938_CCFG_DIVMODE_8 (0x0 << 17)
#define TX4938_CCFG_DIVMODE_10 (0xb << 17)
#define TX4938_CCFG_DIVMODE_12 (0x1 << 17)
@@ -116,7 +116,7 @@ struct tx4938_ccfg_reg {
#define TX4938_CCFG_DIVMODE_18 (0x9 << 17)
#define TX4938_CCFG_BEOW 0x00010000
#define TX4938_CCFG_WR 0x00008000
-#define TX4938_CCFG_TOE 0x00004000
+#define TX4938_CCFG_TOE 0x00004000
#define TX4938_CCFG_PCIARB 0x00002000
#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00
#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10)
@@ -141,10 +141,10 @@ struct tx4938_ccfg_reg {
#define TX4938_PCFG_SPI_SEL 0x0800000000000000ULL
#define TX4938_PCFG_NDF_SEL 0x0400000000000000ULL
#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000
-#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
+#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
#define TX4938_PCFG_SYSCLKEN 0x08000000
-#define TX4938_PCFG_SDCLKEN_ALL 0x07800000
-#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
+#define TX4938_PCFG_SDCLKEN_ALL 0x07800000
+#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
#define TX4938_PCFG_PCICLKEN_ALL 0x003f0000
#define TX4938_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
#define TX4938_PCFG_SEL2 0x00000200
@@ -230,8 +230,8 @@ struct tx4938_ccfg_reg {
#define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3)
#define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4)
#define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5)
-#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
-#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
+#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
+#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
#define TX4938_DMA_CCR_MEMIO 0x00000002
#define TX4938_DMA_CCR_SNGAD 0x00000001
@@ -263,9 +263,9 @@ struct tx4938_ccfg_reg {
#define TX4938_REV_PCODE() \
((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
-#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
+#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits)
-#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
+#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
#define TX4938_SDRAMC_CR(ch) TX4927_SDRAMC_CR(ch)
#define TX4938_SDRAMC_BA(ch) TX4927_SDRAMC_BA(ch)
diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h
index d4f342cd5939..6d667087f2aa 100644
--- a/arch/mips/include/asm/txx9/tx4939.h
+++ b/arch/mips/include/asm/txx9/tx4939.h
@@ -14,11 +14,11 @@
#include <asm/txx9/tx4938.h>
#ifdef CONFIG_64BIT
-#define TX4939_REG_BASE 0xffffffffff1f0000UL /* == TX4938_REG_BASE */
+#define TX4939_REG_BASE 0xffffffffff1f0000UL /* == TX4938_REG_BASE */
#else
-#define TX4939_REG_BASE 0xff1f0000UL /* == TX4938_REG_BASE */
+#define TX4939_REG_BASE 0xff1f0000UL /* == TX4938_REG_BASE */
#endif
-#define TX4939_REG_SIZE 0x00010000 /* == TX4938_REG_SIZE */
+#define TX4939_REG_SIZE 0x00010000 /* == TX4938_REG_SIZE */
#define TX4939_ATA_REG(ch) (TX4939_REG_BASE + 0x3000 + (ch) * 0x1000)
#define TX4939_NDFMC_REG (TX4939_REG_BASE + 0x5000)
@@ -189,14 +189,14 @@ struct tx4939_vpc_desc {
#define TX4939_IR_INT(n) (3 + (n))
#define TX4939_NUM_IR_ETH 2
#define TX4939_IR_ETH(n) ((n) ? 43 : 6)
-#define TX4939_IR_VIDEO 7
+#define TX4939_IR_VIDEO 7
#define TX4939_IR_CIR 8
#define TX4939_NUM_IR_SIO 4
#define TX4939_IR_SIO(n) ((n) ? 43 + (n) : 9) /* 9,44-46 */
#define TX4939_NUM_IR_DMA 4
#define TX4939_IR_DMA(ch, n) (((ch) ? 22 : 10) + (n)) /* 10-13,22-25 */
#define TX4939_IR_IRC 14
-#define TX4939_IR_PDMAC 15
+#define TX4939_IR_PDMAC 15
#define TX4939_NUM_IR_TMR 6
#define TX4939_IR_TMR(n) (((n) >= 3 ? 45 : 16) + (n)) /* 16-18,48-50 */
#define TX4939_NUM_IR_ATA 2
@@ -210,10 +210,10 @@ struct tx4939_vpc_desc {
#define TX4939_IR_I2C 33
#define TX4939_IR_SPI 34
#define TX4939_IR_PCIC 35
-#define TX4939_IR_PCIC1 36
+#define TX4939_IR_PCIC1 36
#define TX4939_IR_PCIERR 37
#define TX4939_IR_PCIPME 38
-#define TX4939_IR_NDFMC 39
+#define TX4939_IR_NDFMC 39
#define TX4939_IR_ACLCPME 40
#define TX4939_IR_RTC 41
#define TX4939_IR_RND 42
@@ -239,7 +239,7 @@ struct tx4939_vpc_desc {
#define TX4939_CCFG_PCI66 0x00800000
#define TX4939_CCFG_PCIMODE 0x00400000
#define TX4939_CCFG_SSCG 0x00100000
-#define TX4939_CCFG_MULCLK_MASK 0x000e0000
+#define TX4939_CCFG_MULCLK_MASK 0x000e0000
#define TX4939_CCFG_MULCLK_8 (0x7 << 17)
#define TX4939_CCFG_MULCLK_9 (0x0 << 17)
#define TX4939_CCFG_MULCLK_10 (0x1 << 17)
@@ -250,7 +250,7 @@ struct tx4939_vpc_desc {
#define TX4939_CCFG_MULCLK_15 (0x6 << 17)
#define TX4939_CCFG_BEOW 0x00010000
#define TX4939_CCFG_WR 0x00008000
-#define TX4939_CCFG_TOE 0x00004000
+#define TX4939_CCFG_TOE 0x00004000
#define TX4939_CCFG_PCIARB 0x00002000
#define TX4939_CCFG_YDIVMODE_MASK 0x00001c00
#define TX4939_CCFG_YDIVMODE_2 (0x0 << 10)
@@ -275,7 +275,7 @@ struct tx4939_vpc_desc {
#define TX4939_PCFG_I2CMODE 0x1000000000000000ULL
#define TX4939_PCFG_I2SMODE_MASK 0x0c00000000000000ULL
#define TX4939_PCFG_I2SMODE_GPIO 0x0c00000000000000ULL
-#define TX4939_PCFG_I2SMODE_I2S 0x0800000000000000ULL
+#define TX4939_PCFG_I2SMODE_I2S 0x0800000000000000ULL
#define TX4939_PCFG_I2SMODE_I2S_ALT 0x0400000000000000ULL
#define TX4939_PCFG_I2SMODE_ACLC 0x0000000000000000ULL
#define TX4939_PCFG_SIO3MODE 0x0200000000000000ULL
@@ -392,15 +392,15 @@ struct tx4939_vpc_desc {
/*
* CRYPTO
*/
-#define TX4939_CRYPTO_CSR_SAESO 0x08000000
-#define TX4939_CRYPTO_CSR_SAESI 0x04000000
-#define TX4939_CRYPTO_CSR_SDESO 0x02000000
-#define TX4939_CRYPTO_CSR_SDESI 0x01000000
+#define TX4939_CRYPTO_CSR_SAESO 0x08000000
+#define TX4939_CRYPTO_CSR_SAESI 0x04000000
+#define TX4939_CRYPTO_CSR_SDESO 0x02000000
+#define TX4939_CRYPTO_CSR_SDESI 0x01000000
#define TX4939_CRYPTO_CSR_INDXBST_MASK 0x00700000
#define TX4939_CRYPTO_CSR_INDXBST(n) ((n) << 20)
-#define TX4939_CRYPTO_CSR_TOINT 0x00080000
-#define TX4939_CRYPTO_CSR_DCINT 0x00040000
-#define TX4939_CRYPTO_CSR_GBINT 0x00010000
+#define TX4939_CRYPTO_CSR_TOINT 0x00080000
+#define TX4939_CRYPTO_CSR_DCINT 0x00040000
+#define TX4939_CRYPTO_CSR_GBINT 0x00010000
#define TX4939_CRYPTO_CSR_INDXAST_MASK 0x0000e000
#define TX4939_CRYPTO_CSR_INDXAST(n) ((n) << 13)
#define TX4939_CRYPTO_CSR_CSWAP_MASK 0x00001800
@@ -418,7 +418,7 @@ struct tx4939_vpc_desc {
#define TX4939_CRYPTO_CSR_PDINT_END 0x00000040
#define TX4939_CRYPTO_CSR_PDINT_NEXT 0x00000080
#define TX4939_CRYPTO_CSR_PDINT_NONE 0x000000c0
-#define TX4939_CRYPTO_CSR_GINTE 0x00000008
+#define TX4939_CRYPTO_CSR_GINTE 0x00000008
#define TX4939_CRYPTO_CSR_RSTD 0x00000004
#define TX4939_CRYPTO_CSR_RSTC 0x00000002
#define TX4939_CRYPTO_CSR_ENCR 0x00000001
@@ -442,7 +442,7 @@ struct tx4939_vpc_desc {
#define TX4939_CRYPTO_DESC_START 0x00000200
#define TX4939_CRYPTO_DESC_END 0x00000100
#define TX4939_CRYPTO_DESC_XOR 0x00000010
-#define TX4939_CRYPTO_DESC_LAST 0x00000008
+#define TX4939_CRYPTO_DESC_LAST 0x00000008
#define TX4939_CRYPTO_DESC_ERR_MASK 0x00000006
#define TX4939_CRYPTO_DESC_ERR_NONE 0x00000000
#define TX4939_CRYPTO_DESC_ERR_TOUT 0x00000002
@@ -457,7 +457,7 @@ struct tx4939_vpc_desc {
#define TX4939_CRYPTO_NR_SET 6
-#define TX4939_CRYPTO_RCSR_INTE 0x00000008
+#define TX4939_CRYPTO_RCSR_INTE 0x00000008
#define TX4939_CRYPTO_RCSR_RST 0x00000004
#define TX4939_CRYPTO_RCSR_FIN 0x00000002
#define TX4939_CRYPTO_RCSR_ST 0x00000001
@@ -480,8 +480,8 @@ struct tx4939_vpc_desc {
#define TX4939_VPC_CTRLA_PDINT_ALL 0x00000000
#define TX4939_VPC_CTRLA_PDINT_NEXT 0x00000010
#define TX4939_VPC_CTRLA_PDINT_NONE 0x00000030
-#define TX4939_VPC_CTRLA_VDVLDP 0x00000008
-#define TX4939_VPC_CTRLA_VDMODE 0x00000004
+#define TX4939_VPC_CTRLA_VDVLDP 0x00000008
+#define TX4939_VPC_CTRLA_VDMODE 0x00000004
#define TX4939_VPC_CTRLA_VDFOR 0x00000002
#define TX4939_VPC_CTRLA_ENVPC 0x00000001
@@ -512,9 +512,9 @@ struct tx4939_vpc_desc {
((__u32)((__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_BCFG_MASK) \
>> 32))
-#define tx4939_ccfg_clear(bits) tx4938_ccfg_clear(bits)
+#define tx4939_ccfg_clear(bits) tx4938_ccfg_clear(bits)
#define tx4939_ccfg_set(bits) tx4938_ccfg_set(bits)
-#define tx4939_ccfg_change(change, new) tx4938_ccfg_change(change, new)
+#define tx4939_ccfg_change(change, new) tx4938_ccfg_change(change, new)
#define TX4939_EBUSC_CR(ch) TX4927_EBUSC_CR(ch)
#define TX4939_EBUSC_BA(ch) TX4927_EBUSC_BA(ch)
@@ -522,7 +522,7 @@ struct tx4939_vpc_desc {
#define TX4939_EBUSC_WIDTH(ch) \
(16 >> ((__u32)(TX4939_EBUSC_CR(ch) >> 20) & 0x1))
-/* SCLK0 = MSTCLK * 429/19 * 16/245 / 2 (14.745MHz for MST 20MHz) */
+/* SCLK0 = MSTCLK * 429/19 * 16/245 / 2 (14.745MHz for MST 20MHz) */
#define TX4939_SCLK0(mst) \
((((mst) + 245/2) / 245UL * 429 * 16 + 19) / 19 / 2)
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-02 16:39:03 +0300