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-rw-r--r--arch/m68k/Kconfig41
-rw-r--r--arch/m68k/Makefile1
-rw-r--r--arch/m68k/amiga/chipram.c4
-rw-r--r--arch/m68k/bvme6000/config.c4
-rw-r--r--arch/m68k/emu/Makefile9
-rw-r--r--arch/m68k/emu/natfeat.c78
-rw-r--r--arch/m68k/emu/nfblock.c195
-rw-r--r--arch/m68k/emu/nfcon.c162
-rw-r--r--arch/m68k/emu/nfeth.c270
-rw-r--r--arch/m68k/include/asm/coldfire.h42
-rw-r--r--arch/m68k/include/asm/m5206sim.h23
-rw-r--r--arch/m68k/include/asm/m520xsim.h50
-rw-r--r--arch/m68k/include/asm/m523xsim.h52
-rw-r--r--arch/m68k/include/asm/m5249sim.h30
-rw-r--r--arch/m68k/include/asm/m5272sim.h8
-rw-r--r--arch/m68k/include/asm/m527xsim.h68
-rw-r--r--arch/m68k/include/asm/m528xsim.h44
-rw-r--r--arch/m68k/include/asm/m5307sim.h25
-rw-r--r--arch/m68k/include/asm/m532xsim.h9
-rw-r--r--arch/m68k/include/asm/m5407sim.h25
-rw-r--r--arch/m68k/include/asm/m54xxsim.h14
-rw-r--r--arch/m68k/include/asm/mcfdma.h23
-rw-r--r--arch/m68k/include/asm/mcfpit.h16
-rw-r--r--arch/m68k/include/asm/mcftimer.h23
-rw-r--r--arch/m68k/include/asm/natfeat.h22
-rw-r--r--arch/m68k/include/asm/processor.h2
-rw-r--r--arch/m68k/kernel/setup.c5
-rw-r--r--arch/m68k/kernel/signal.c24
-rw-r--r--arch/m68k/kernel/time.c4
-rw-r--r--arch/m68k/kernel/traps.c20
-rw-r--r--arch/m68k/math-emu/Makefile4
-rw-r--r--arch/m68k/mm/fault.c16
-rw-r--r--arch/m68k/mvme147/config.c4
-rw-r--r--arch/m68k/mvme16x/config.c4
-rw-r--r--arch/m68k/sun3/sun3ints.c2
35 files changed, 1107 insertions, 216 deletions
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index bc9271b85759..525174d41679 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -18,11 +18,9 @@ config RWSEM_XCHGADD_ALGORITHM
config ARCH_HAS_ILOG2_U32
bool
- default n
config ARCH_HAS_ILOG2_U64
bool
- default n
config GENERIC_HWEIGHT
bool
@@ -242,6 +240,37 @@ config SUN3
If you don't want to compile a kernel exclusively for a Sun 3, say N.
+config NATFEAT
+ bool "ARAnyM emulator support"
+ depends on ATARI
+ help
+ This option enables support for ARAnyM native features, such as
+ access to a disk image as /dev/hda.
+
+config NFBLOCK
+ tristate "NatFeat block device support"
+ depends on BLOCK && NATFEAT
+ help
+ Say Y to include support for the ARAnyM NatFeat block device
+ which allows direct access to the hard drives without using
+ the hardware emulation.
+
+config NFCON
+ tristate "NatFeat console driver"
+ depends on NATFEAT
+ help
+ Say Y to include support for the ARAnyM NatFeat console driver
+ which allows the console output to be redirected to the stderr
+ output of ARAnyM.
+
+config NFETH
+ tristate "NatFeat Ethernet support"
+ depends on NET_ETHERNET && NATFEAT
+ help
+ Say Y to include support for the ARAnyM NatFeat network device
+ which will emulate a regular ethernet device while presenting an
+ ethertap device to the host system.
+
comment "Processor type"
config M68020
@@ -554,14 +583,6 @@ config MVME147_SCC
This is the driver for the serial ports on the Motorola MVME147
boards. Everyone using one of these boards should say Y here.
-config SERIAL167
- bool "CD2401 support for MVME166/7 serial ports"
- depends on MVME16x
- help
- This is the driver for the serial ports on the Motorola MVME166,
- 167, and 172 boards. Everyone using one of these boards should say
- Y here.
-
config MVME162_SCC
bool "SCC support for MVME162 serial ports"
depends on MVME16x && BROKEN
diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
index b06a7e3cbcd6..b793163abc61 100644
--- a/arch/m68k/Makefile
+++ b/arch/m68k/Makefile
@@ -76,6 +76,7 @@ core-$(CONFIG_MVME16x) += arch/m68k/mvme16x/
core-$(CONFIG_BVME6000) += arch/m68k/bvme6000/
core-$(CONFIG_SUN3X) += arch/m68k/sun3x/ arch/m68k/sun3/
core-$(CONFIG_SUN3) += arch/m68k/sun3/ arch/m68k/sun3/prom/
+core-$(CONFIG_NATFEAT) += arch/m68k/emu/
core-$(CONFIG_M68040) += arch/m68k/fpsp040/
core-$(CONFIG_M68060) += arch/m68k/ifpsp060/
core-$(CONFIG_M68KFPU_EMU) += arch/m68k/math-emu/
diff --git a/arch/m68k/amiga/chipram.c b/arch/m68k/amiga/chipram.c
index 61df1d33c050..dd0447db1c90 100644
--- a/arch/m68k/amiga/chipram.c
+++ b/arch/m68k/amiga/chipram.c
@@ -33,10 +33,6 @@ void __init amiga_chip_init(void)
if (!AMIGAHW_PRESENT(CHIP_RAM))
return;
- /*
- * Remove the first 4 pages where PPC exception handlers will be located
- */
- amiga_chip_size -= 0x4000;
chipram_res.end = amiga_chip_size-1;
request_resource(&iomem_resource, &chipram_res);
diff --git a/arch/m68k/bvme6000/config.c b/arch/m68k/bvme6000/config.c
index 9fe6fefb5e14..1edd95095cb4 100644
--- a/arch/m68k/bvme6000/config.c
+++ b/arch/m68k/bvme6000/config.c
@@ -45,8 +45,8 @@ extern int bvme6000_set_clock_mmss (unsigned long);
extern void bvme6000_reset (void);
void bvme6000_set_vectors (void);
-/* Save tick handler routine pointer, will point to do_timer() in
- * kernel/sched.c, called via bvme6000_process_int() */
+/* Save tick handler routine pointer, will point to xtime_update() in
+ * kernel/timer/timekeeping.c, called via bvme6000_process_int() */
static irq_handler_t tick_handler;
diff --git a/arch/m68k/emu/Makefile b/arch/m68k/emu/Makefile
new file mode 100644
index 000000000000..7dc201080308
--- /dev/null
+++ b/arch/m68k/emu/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for Linux arch/m68k/emu source directory
+#
+
+obj-y += natfeat.o
+
+obj-$(CONFIG_NFBLOCK) += nfblock.o
+obj-$(CONFIG_NFCON) += nfcon.o
+obj-$(CONFIG_NFETH) += nfeth.o
diff --git a/arch/m68k/emu/natfeat.c b/arch/m68k/emu/natfeat.c
new file mode 100644
index 000000000000..2291a7d69d49
--- /dev/null
+++ b/arch/m68k/emu/natfeat.c
@@ -0,0 +1,78 @@
+/*
+ * natfeat.c - ARAnyM hardware support via Native Features (natfeats)
+ *
+ * Copyright (c) 2005 Petr Stehlik of ARAnyM dev team
+ *
+ * Reworked for Linux by Roman Zippel <zippel@linux-m68k.org>
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL), incorporated herein by reference.
+ */
+
+#include <linux/types.h>
+#include <linux/console.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <asm/machdep.h>
+#include <asm/natfeat.h>
+
+asm("\n"
+" .global nf_get_id,nf_call\n"
+"nf_get_id:\n"
+" .short 0x7300\n"
+" rts\n"
+"nf_call:\n"
+" .short 0x7301\n"
+" rts\n"
+"1: moveq.l #0,%d0\n"
+" rts\n"
+" .section __ex_table,\"a\"\n"
+" .long nf_get_id,1b\n"
+" .long nf_call,1b\n"
+" .previous");
+EXPORT_SYMBOL_GPL(nf_get_id);
+EXPORT_SYMBOL_GPL(nf_call);
+
+void nfprint(const char *fmt, ...)
+{
+ static char buf[256];
+ va_list ap;
+ int n;
+
+ va_start(ap, fmt);
+ n = vsnprintf(buf, 256, fmt, ap);
+ nf_call(nf_get_id("NF_STDERR"), buf);
+ va_end(ap);
+}
+
+static void nf_poweroff(void)
+{
+ long id = nf_get_id("NF_SHUTDOWN");
+
+ if (id)
+ nf_call(id);
+}
+
+void nf_init(void)
+{
+ unsigned long id, version;
+ char buf[256];
+
+ id = nf_get_id("NF_VERSION");
+ if (!id)
+ return;
+ version = nf_call(id);
+
+ id = nf_get_id("NF_NAME");
+ if (!id)
+ return;
+ nf_call(id, buf, 256);
+ buf[255] = 0;
+
+ pr_info("NatFeats found (%s, %lu.%lu)\n", buf, version >> 16,
+ version & 0xffff);
+
+ mach_power_off = nf_poweroff;
+}
diff --git a/arch/m68k/emu/nfblock.c b/arch/m68k/emu/nfblock.c
new file mode 100644
index 000000000000..48e50f8c1c7e
--- /dev/null
+++ b/arch/m68k/emu/nfblock.c
@@ -0,0 +1,195 @@
+/*
+ * ARAnyM block device driver
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/genhd.h>
+#include <linux/blkdev.h>
+#include <linux/hdreg.h>
+#include <linux/slab.h>
+
+#include <asm/natfeat.h>
+
+static long nfhd_id;
+
+enum {
+ /* emulation entry points */
+ NFHD_READ_WRITE = 10,
+ NFHD_GET_CAPACITY = 14,
+
+ /* skip ACSI devices */
+ NFHD_DEV_OFFSET = 8,
+};
+
+static inline s32 nfhd_read_write(u32 major, u32 minor, u32 rwflag, u32 recno,
+ u32 count, u32 buf)
+{
+ return nf_call(nfhd_id + NFHD_READ_WRITE, major, minor, rwflag, recno,
+ count, buf);
+}
+
+static inline s32 nfhd_get_capacity(u32 major, u32 minor, u32 *blocks,
+ u32 *blocksize)
+{
+ return nf_call(nfhd_id + NFHD_GET_CAPACITY, major, minor, blocks,
+ blocksize);
+}
+
+static LIST_HEAD(nfhd_list);
+
+static int major_num;
+module_param(major_num, int, 0);
+
+struct nfhd_device {
+ struct list_head list;
+ int id;
+ u32 blocks, bsize;
+ int bshift;
+ struct request_queue *queue;
+ struct gendisk *disk;
+};
+
+static int nfhd_make_request(struct request_queue *queue, struct bio *bio)
+{
+ struct nfhd_device *dev = queue->queuedata;
+ struct bio_vec *bvec;
+ int i, dir, len, shift;
+ sector_t sec = bio->bi_sector;
+
+ dir = bio_data_dir(bio);
+ shift = dev->bshift;
+ bio_for_each_segment(bvec, bio, i) {
+ len = bvec->bv_len;
+ len >>= 9;
+ nfhd_read_write(dev->id, 0, dir, sec >> shift, len >> shift,
+ bvec_to_phys(bvec));
+ sec += len;
+ }
+ bio_endio(bio, 0);
+ return 0;
+}
+
+static int nfhd_getgeo(struct block_device *bdev, struct hd_geometry *geo)
+{
+ struct nfhd_device *dev = bdev->bd_disk->private_data;
+
+ geo->cylinders = dev->blocks >> (6 - dev->bshift);
+ geo->heads = 4;
+ geo->sectors = 16;
+
+ return 0;
+}
+
+static const struct block_device_operations nfhd_ops = {
+ .owner = THIS_MODULE,
+ .getgeo = nfhd_getgeo,
+};
+
+static int __init nfhd_init_one(int id, u32 blocks, u32 bsize)
+{
+ struct nfhd_device *dev;
+ int dev_id = id - NFHD_DEV_OFFSET;
+
+ pr_info("nfhd%u: found device with %u blocks (%u bytes)\n", dev_id,
+ blocks, bsize);
+
+ if (bsize < 512 || (bsize & (bsize - 1))) {
+ pr_warn("nfhd%u: invalid block size\n", dev_id);
+ return -EINVAL;
+ }
+
+ dev = kmalloc(sizeof(struct nfhd_device), GFP_KERNEL);
+ if (!dev)
+ goto out;
+
+ dev->id = id;
+ dev->blocks = blocks;
+ dev->bsize = bsize;
+ dev->bshift = ffs(bsize) - 10;
+
+ dev->queue = blk_alloc_queue(GFP_KERNEL);
+ if (dev->queue == NULL)
+ goto free_dev;
+
+ dev->queue->queuedata = dev;
+ blk_queue_make_request(dev->queue, nfhd_make_request);
+ blk_queue_logical_block_size(dev->queue, bsize);
+
+ dev->disk = alloc_disk(16);
+ if (!dev->disk)
+ goto free_queue;
+
+ dev->disk->major = major_num;
+ dev->disk->first_minor = dev_id * 16;
+ dev->disk->fops = &nfhd_ops;
+ dev->disk->private_data = dev;
+ sprintf(dev->disk->disk_name, "nfhd%u", dev_id);
+ set_capacity(dev->disk, (sector_t)blocks * (bsize / 512));
+ dev->disk->queue = dev->queue;
+
+ add_disk(dev->disk);
+
+ list_add_tail(&dev->list, &nfhd_list);
+
+ return 0;
+
+free_queue:
+ blk_cleanup_queue(dev->queue);
+free_dev:
+ kfree(dev);
+out:
+ return -ENOMEM;
+}
+
+static int __init nfhd_init(void)
+{
+ u32 blocks, bsize;
+ int i;
+
+ nfhd_id = nf_get_id("XHDI");
+ if (!nfhd_id)
+ return -ENODEV;
+
+ major_num = register_blkdev(major_num, "nfhd");
+ if (major_num <= 0) {
+ pr_warn("nfhd: unable to get major number\n");
+ return major_num;
+ }
+
+ for (i = NFHD_DEV_OFFSET; i < 24; i++) {
+ if (nfhd_get_capacity(i, 0, &blocks, &bsize))
+ continue;
+ nfhd_init_one(i, blocks, bsize);
+ }
+
+ return 0;
+}
+
+static void __exit nfhd_exit(void)
+{
+ struct nfhd_device *dev, *next;
+
+ list_for_each_entry_safe(dev, next, &nfhd_list, list) {
+ list_del(&dev->list);
+ del_gendisk(dev->disk);
+ put_disk(dev->disk);
+ blk_cleanup_queue(dev->queue);
+ kfree(dev);
+ }
+ unregister_blkdev(major_num, "nfhd");
+}
+
+module_init(nfhd_init);
+module_exit(nfhd_exit);
+
+MODULE_LICENSE("GPL");
diff --git a/arch/m68k/emu/nfcon.c b/arch/m68k/emu/nfcon.c
new file mode 100644
index 000000000000..ab20dc0ff63b
--- /dev/null
+++ b/arch/m68k/emu/nfcon.c
@@ -0,0 +1,162 @@
+/*
+ * ARAnyM console driver
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/tty.h>
+#include <linux/tty_driver.h>
+#include <linux/tty_flip.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/uaccess.h>
+
+#include <asm/natfeat.h>
+
+static int stderr_id;
+static struct tty_driver *nfcon_tty_driver;
+
+static void nfputs(const char *str, unsigned int count)
+{
+ char buf[68];
+
+ buf[64] = 0;
+ while (count > 64) {
+ memcpy(buf, str, 64);
+ nf_call(stderr_id, buf);
+ str += 64;
+ count -= 64;
+ }
+ memcpy(buf, str, count);
+ buf[count] = 0;
+ nf_call(stderr_id, buf);
+}
+
+static void nfcon_write(struct console *con, const char *str,
+ unsigned int count)
+{
+ nfputs(str, count);
+}
+
+static struct tty_driver *nfcon_device(struct console *con, int *index)
+{
+ *index = 0;
+ return (con->flags & CON_ENABLED) ? nfcon_tty_driver : NULL;
+}
+
+static struct console nf_console = {
+ .name = "nfcon",
+ .write = nfcon_write,
+ .device = nfcon_device,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+};
+
+
+static int nfcon_tty_open(struct tty_struct *tty, struct file *filp)
+{
+ return 0;
+}
+
+static void nfcon_tty_close(struct tty_struct *tty, struct file *filp)
+{
+}
+
+static int nfcon_tty_write(struct tty_struct *tty, const unsigned char *buf,
+ int count)
+{
+ nfputs(buf, count);
+ return count;
+}
+
+static int nfcon_tty_put_char(struct tty_struct *tty, unsigned char ch)
+{
+ char temp[2] = { ch, 0 };
+
+ nf_call(stderr_id, temp);
+ return 1;
+}
+
+static int nfcon_tty_write_room(struct tty_struct *tty)
+{
+ return 64;
+}
+
+static const struct tty_operations nfcon_tty_ops = {
+ .open = nfcon_tty_open,
+ .close = nfcon_tty_close,
+ .write = nfcon_tty_write,
+ .put_char = nfcon_tty_put_char,
+ .write_room = nfcon_tty_write_room,
+};
+
+#ifndef MODULE
+
+static int __init nf_debug_setup(char *arg)
+{
+ if (strcmp(arg, "nfcon"))
+ return 0;
+
+ stderr_id = nf_get_id("NF_STDERR");
+ if (stderr_id) {
+ nf_console.flags |= CON_ENABLED;
+ register_console(&nf_console);
+ }
+
+ return 0;
+}
+
+early_param("debug", nf_debug_setup);
+
+#endif /* !MODULE */
+
+static int __init nfcon_init(void)
+{
+ int res;
+
+ stderr_id = nf_get_id("NF_STDERR");
+ if (!stderr_id)
+ return -ENODEV;
+
+ nfcon_tty_driver = alloc_tty_driver(1);
+ if (!nfcon_tty_driver)
+ return -ENOMEM;
+
+ nfcon_tty_driver->owner = THIS_MODULE;
+ nfcon_tty_driver->driver_name = "nfcon";
+ nfcon_tty_driver->name = "nfcon";
+ nfcon_tty_driver->type = TTY_DRIVER_TYPE_SYSTEM;
+ nfcon_tty_driver->subtype = SYSTEM_TYPE_TTY;
+ nfcon_tty_driver->init_termios = tty_std_termios;
+ nfcon_tty_driver->flags = TTY_DRIVER_REAL_RAW;
+
+ tty_set_operations(nfcon_tty_driver, &nfcon_tty_ops);
+ res = tty_register_driver(nfcon_tty_driver);
+ if (res) {
+ pr_err("failed to register nfcon tty driver\n");
+ put_tty_driver(nfcon_tty_driver);
+ return res;
+ }
+
+ if (!(nf_console.flags & CON_ENABLED))
+ register_console(&nf_console);
+
+ return 0;
+}
+
+static void __exit nfcon_exit(void)
+{
+ unregister_console(&nf_console);
+ tty_unregister_driver(nfcon_tty_driver);
+ put_tty_driver(nfcon_tty_driver);
+}
+
+module_init(nfcon_init);
+module_exit(nfcon_exit);
+
+MODULE_LICENSE("GPL");
diff --git a/arch/m68k/emu/nfeth.c b/arch/m68k/emu/nfeth.c
new file mode 100644
index 000000000000..8b6e201b2c20
--- /dev/null
+++ b/arch/m68k/emu/nfeth.c
@@ -0,0 +1,270 @@
+/*
+ * atari_nfeth.c - ARAnyM ethernet card driver for GNU/Linux
+ *
+ * Copyright (c) 2005 Milan Jurik, Petr Stehlik of ARAnyM dev team
+ *
+ * Based on ARAnyM driver for FreeMiNT written by Standa Opichal
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL), incorporated herein by reference.
+ */
+
+#define DRV_VERSION "0.3"
+#define DRV_RELDATE "10/12/2005"
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/module.h>
+#include <asm/natfeat.h>
+#include <asm/virtconvert.h>
+
+enum {
+ GET_VERSION = 0,/* no parameters, return NFAPI_VERSION in d0 */
+ XIF_INTLEVEL, /* no parameters, return Interrupt Level in d0 */
+ XIF_IRQ, /* acknowledge interrupt from host */
+ XIF_START, /* (ethX), called on 'ifup', start receiver thread */
+ XIF_STOP, /* (ethX), called on 'ifdown', stop the thread */
+ XIF_READLENGTH, /* (ethX), return size of network data block to read */
+ XIF_READBLOCK, /* (ethX, buffer, size), read block of network data */
+ XIF_WRITEBLOCK, /* (ethX, buffer, size), write block of network data */
+ XIF_GET_MAC, /* (ethX, buffer, size), return MAC HW addr in buffer */
+ XIF_GET_IPHOST, /* (ethX, buffer, size), return IP address of host */
+ XIF_GET_IPATARI,/* (ethX, buffer, size), return IP address of atari */
+ XIF_GET_NETMASK /* (ethX, buffer, size), return IP netmask */
+};
+
+#define MAX_UNIT 8
+
+/* These identify the driver base version and may not be removed. */
+static const char version[] __devinitdata =
+ KERN_INFO KBUILD_MODNAME ".c:v" DRV_VERSION " " DRV_RELDATE
+ " S.Opichal, M.Jurik, P.Stehlik\n"
+ KERN_INFO " http://aranym.org/\n";
+
+MODULE_AUTHOR("Milan Jurik");
+MODULE_DESCRIPTION("Atari NFeth driver");
+MODULE_LICENSE("GPL");
+/*
+MODULE_PARM(nfeth_debug, "i");
+MODULE_PARM_DESC(nfeth_debug, "nfeth_debug level (1-2)");
+*/
+
+
+static long nfEtherID;
+static int nfEtherIRQ;
+
+struct nfeth_private {
+ int ethX;
+};
+
+static struct net_device *nfeth_dev[MAX_UNIT];
+
+static int nfeth_open(struct net_device *dev)
+{
+ struct nfeth_private *priv = netdev_priv(dev);
+ int res;
+
+ res = nf_call(nfEtherID + XIF_START, priv->ethX);
+ netdev_dbg(dev, "%s: %d\n", __func__, res);
+
+ /* Ready for data */
+ netif_start_queue(dev);
+
+ return 0;
+}
+
+static int nfeth_stop(struct net_device *dev)
+{
+ struct nfeth_private *priv = netdev_priv(dev);
+
+ /* No more data */
+ netif_stop_queue(dev);
+
+ nf_call(nfEtherID + XIF_STOP, priv->ethX);
+
+ return 0;
+}
+
+/*
+ * Read a packet out of the adapter and pass it to the upper layers
+ */
+static inline void recv_packet(struct net_device *dev)
+{
+ struct nfeth_private *priv = netdev_priv(dev);
+ unsigned short pktlen;
+ struct sk_buff *skb;
+
+ /* read packet length (excluding 32 bit crc) */
+ pktlen = nf_call(nfEtherID + XIF_READLENGTH, priv->ethX);
+
+ netdev_dbg(dev, "%s: %u\n", __func__, pktlen);
+
+ if (!pktlen) {
+ netdev_dbg(dev, "%s: pktlen == 0\n", __func__);
+ dev->stats.rx_errors++;
+ return;
+ }
+
+ skb = dev_alloc_skb(pktlen + 2);
+ if (!skb) {
+ netdev_dbg(dev, "%s: out of mem (buf_alloc failed)\n",
+ __func__);
+ dev->stats.rx_dropped++;
+ return;
+ }
+
+ skb->dev = dev;
+ skb_reserve(skb, 2); /* 16 Byte align */
+ skb_put(skb, pktlen); /* make room */
+ nf_call(nfEtherID + XIF_READBLOCK, priv->ethX, virt_to_phys(skb->data),
+ pktlen);
+
+ skb->protocol = eth_type_trans(skb, dev);
+ netif_rx(skb);
+ dev->last_rx = jiffies;
+ dev->stats.rx_packets++;
+ dev->stats.rx_bytes += pktlen;
+
+ /* and enqueue packet */
+ return;
+}
+
+static irqreturn_t nfeth_interrupt(int irq, void *dev_id)
+{
+ int i, m, mask;
+
+ mask = nf_call(nfEtherID + XIF_IRQ, 0);
+ for (i = 0, m = 1; i < MAX_UNIT; m <<= 1, i++) {
+ if (mask & m && nfeth_dev[i]) {
+ recv_packet(nfeth_dev[i]);
+ nf_call(nfEtherID + XIF_IRQ, m);
+ }
+ }
+ return IRQ_HANDLED;
+}
+
+static int nfeth_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+ unsigned int len;
+ char *data, shortpkt[ETH_ZLEN];
+ struct nfeth_private *priv = netdev_priv(dev);
+
+ data = skb->data;
+ len = skb->len;
+ if (len < ETH_ZLEN) {
+ memset(shortpkt, 0, ETH_ZLEN);
+ memcpy(shortpkt, data, len);
+ data = shortpkt;
+ len = ETH_ZLEN;
+ }
+
+ netdev_dbg(dev, "%s: send %u bytes\n", __func__, len);
+ nf_call(nfEtherID + XIF_WRITEBLOCK, priv->ethX, virt_to_phys(data),
+ len);
+
+ dev->stats.tx_packets++;
+ dev->stats.tx_bytes += len;
+
+ dev_kfree_skb(skb);
+ return 0;
+}
+
+static void nfeth_tx_timeout(struct net_device *dev)
+{
+ dev->stats.tx_errors++;
+ netif_wake_queue(dev);
+}
+
+static const struct net_device_ops nfeth_netdev_ops = {
+ .ndo_open = nfeth_open,
+ .ndo_stop = nfeth_stop,
+ .ndo_start_xmit = nfeth_xmit,
+ .ndo_tx_timeout = nfeth_tx_timeout,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_change_mtu = eth_change_mtu,
+ .ndo_set_mac_address = eth_mac_addr,
+};
+
+static struct net_device * __init nfeth_probe(int unit)
+{
+ struct net_device *dev;
+ struct nfeth_private *priv;
+ char mac[ETH_ALEN], host_ip[32], local_ip[32];
+ int err;
+
+ if (!nf_call(nfEtherID + XIF_GET_MAC, unit, mac, ETH_ALEN))
+ return NULL;
+
+ dev = alloc_etherdev(sizeof(struct nfeth_private));
+ if (!dev)
+ return NULL;
+
+ dev->irq = nfEtherIRQ;
+ dev->netdev_ops = &nfeth_netdev_ops;
+
+ dev->flags |= NETIF_F_NO_CSUM;
+ memcpy(dev->dev_addr, mac, ETH_ALEN);
+
+ priv = netdev_priv(dev);
+ priv->ethX = unit;
+
+ err = register_netdev(dev);
+ if (err) {
+ free_netdev(dev);
+ return NULL;
+ }
+
+ nf_call(nfEtherID + XIF_GET_IPHOST, unit,
+ host_ip, sizeof(host_ip));
+ nf_call(nfEtherID + XIF_GET_IPATARI, unit,
+ local_ip, sizeof(local_ip));
+
+ netdev_info(dev, KBUILD_MODNAME " addr:%s (%s) HWaddr:%pM\n", host_ip,
+ local_ip, mac);
+
+ return dev;
+}
+
+static int __init nfeth_init(void)
+{
+ long ver;
+ int error, i;
+
+ nfEtherID = nf_get_id("ETHERNET");
+ if (!nfEtherID)
+ return -ENODEV;
+
+ ver = nf_call(nfEtherID + GET_VERSION);
+ pr_info("API %lu\n", ver);
+
+ nfEtherIRQ = nf_call(nfEtherID + XIF_INTLEVEL);
+ error = request_irq(nfEtherIRQ, nfeth_interrupt, IRQF_SHARED,
+ "eth emu", nfeth_interrupt);
+ if (error) {
+ pr_err("request for irq %d failed %d", nfEtherIRQ, error);
+ return error;
+ }
+
+ for (i = 0; i < MAX_UNIT; i++)
+ nfeth_dev[i] = nfeth_probe(i);
+
+ return 0;
+}
+
+static void __exit nfeth_cleanup(void)
+{
+ int i;
+
+ for (i = 0; i < MAX_UNIT; i++) {
+ if (nfeth_dev[i]) {
+ unregister_netdev(nfeth_dev[0]);
+ free_netdev(nfeth_dev[0]);
+ }
+ }
+ free_irq(nfEtherIRQ, nfeth_interrupt);
+}
+
+module_init(nfeth_init);
+module_exit(nfeth_cleanup);
diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h
index 213028cbe110..c94557b91448 100644
--- a/arch/m68k/include/asm/coldfire.h
+++ b/arch/m68k/include/asm/coldfire.h
@@ -14,39 +14,35 @@
/*
- * Define master clock frequency. This is essentially done at config
- * time now. No point enumerating dozens of possible clock options
- * here. Also the peripheral clock (bus clock) divide ratio is set
- * at config time too.
+ * Define master clock frequency. This is done at config time now.
+ * No point enumerating dozens of possible clock options here. And
+ * in any case new boards come along from time to time that have yet
+ * another different clocking frequency.
*/
#ifdef CONFIG_CLOCK_SET
#define MCF_CLK CONFIG_CLOCK_FREQ
-#define MCF_BUSCLK (CONFIG_CLOCK_FREQ / CONFIG_CLOCK_DIV)
#else
#error "Don't know what your ColdFire CPU clock frequency is??"
#endif
/*
- * Define the processor support peripherals base address.
- * This is generally setup by the boards start up code.
+ * Define the processor internal peripherals base address.
+ *
+ * The majority of ColdFire parts use an MBAR register to set
+ * the base address. Some have an IPSBAR register instead, and it
+ * has slightly different rules on its size and alignment. Some
+ * parts have fixed addresses and the internal peripherals cannot
+ * be relocated in the CPU address space.
+ *
+ * The value of MBAR or IPSBAR is config time selectable, we no
+ * longer hard define it here. No MBAR or IPSBAR will be defined if
+ * this part has a fixed peripheral address map.
*/
-#define MCF_MBAR 0x10000000
-#define MCF_MBAR2 0x80000000
-#if defined(CONFIG_M54xx)
-#define MCF_IPSBAR MCF_MBAR
-#elif defined(CONFIG_M520x)
-#define MCF_IPSBAR 0xFC000000
-#else
-#define MCF_IPSBAR 0x40000000
+#ifdef CONFIG_MBAR
+#define MCF_MBAR CONFIG_MBAR
#endif
-
-#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
- defined(CONFIG_M520x)
-#undef MCF_MBAR
-#define MCF_MBAR MCF_IPSBAR
-#elif defined(CONFIG_M532x)
-#undef MCF_MBAR
-#define MCF_MBAR 0x00000000
+#ifdef CONFIG_IPSBAR
+#define MCF_IPSBAR CONFIG_IPSBAR
#endif
/****************************************************************************/
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 561b03b5ddf8..9015eadd5c00 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -14,6 +14,7 @@
#define CPU_NAME "COLDFIRE(m5206)"
#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK MCF_CLK
#include <asm/m52xxacr.h>
@@ -48,14 +49,14 @@
#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */
#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */
-#define MCFSIM_DCRR 0x46 /* DRAM Refresh reg (r/w) */
-#define MCFSIM_DCTR 0x4a /* DRAM Timing reg (r/w) */
-#define MCFSIM_DAR0 0x4c /* DRAM 0 Address reg(r/w) */
-#define MCFSIM_DMR0 0x50 /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DCR0 0x57 /* DRAM 0 Control reg (r/w) */
-#define MCFSIM_DAR1 0x58 /* DRAM 1 Address reg (r/w) */
-#define MCFSIM_DMR1 0x5c /* DRAM 1 Mask reg (r/w) */
-#define MCFSIM_DCR1 0x63 /* DRAM 1 Control reg (r/w) */
+#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
+#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
+#define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
+#define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
+#define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
+#define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
+#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
+#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */
#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */
@@ -89,9 +90,15 @@
#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */
#endif
+#define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */
+#define MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */
+
#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
+#define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */
+#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */
+
#if defined(CONFIG_NETtel)
#define MCFUART_BASE1 0x180 /* Base address of UART1 */
#define MCFUART_BASE2 0x140 /* Base address of UART2 */
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 88ed8239fe4e..55d5a4c5fe0b 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -13,13 +13,14 @@
#define CPU_NAME "COLDFIRE(m520x)"
#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m52xxacr.h>
/*
* Define the 520x SIM register set addresses.
*/
-#define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@@ -35,9 +36,9 @@
* address to the SIMR and CIMR registers (not offsets into IPSBAR).
* The 520x family only has a single INTC unit.
*/
-#define MCFINTC0_SIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR)
-#define MCFINTC0_CIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR)
-#define MCFINTC0_ICR0 (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0)
+#define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR)
+#define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR)
+#define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0)
#define MCFINTC1_SIMR (0)
#define MCFINTC1_CIMR (0)
#define MCFINTC1_ICR0 (0)
@@ -52,19 +53,22 @@
/*
* SDRAM configuration registers.
*/
-#define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */
-#define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */
-#define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */
-#define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */
-#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */
-#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */
+#define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */
+#define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */
+#define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */
+#define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */
+#define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */
+#define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */
/*
* EPORT and GPIO registers.
*/
+#define MCFEPORT_EPPAR 0xFC088000
#define MCFEPORT_EPDDR 0xFC088002
+#define MCFEPORT_EPIER 0xFC088003
#define MCFEPORT_EPDR 0xFC088004
#define MCFEPORT_EPPDR 0xFC088005
+#define MCFEPORT_EPFR 0xFC088006
#define MCFGPIO_PODR_BUSCTL 0xFC0A4000
#define MCFGPIO_PODR_BE 0xFC0A4001
@@ -119,10 +123,10 @@
#define MCFGPIO_IRQ_MAX 8
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
-#define MCF_GPIO_PAR_UART (0xA4036)
-#define MCF_GPIO_PAR_FECI2C (0xA4033)
-#define MCF_GPIO_PAR_QSPI (0xA4034)
-#define MCF_GPIO_PAR_FEC (0xA4038)
+#define MCF_GPIO_PAR_UART 0xFC0A4036
+#define MCF_GPIO_PAR_FECI2C 0xFC0A4033
+#define MCF_GPIO_PAR_QSPI 0xFC0A4034
+#define MCF_GPIO_PAR_FEC 0xFC0A4038
#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)
#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002)
@@ -134,11 +138,23 @@
#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
/*
+ * PIT timer module.
+ */
+#define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */
+#define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */
+
+/*
* UART module.
*/
-#define MCFUART_BASE1 0x60000 /* Base address of UART1 */
-#define MCFUART_BASE2 0x64000 /* Base address of UART2 */
-#define MCFUART_BASE3 0x68000 /* Base address of UART2 */
+#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */
+#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
+#define MCFUART_BASE3 0xFC068000 /* Base address of UART2 */
+
+/*
+ * FEC module.
+ */
+#define MCFFEC_BASE 0xFC030000 /* Base of FEC ethernet */
+#define MCFFEC_SIZE 0x800 /* Register set size */
/*
* Reset Controll Unit.
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 4ad7a00257a8..8996df62ede4 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -13,14 +13,16 @@
#define CPU_NAME "COLDFIRE(m523x)"
#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m52xxacr.h>
/*
* Define the 523x SIM register set addresses.
*/
-#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
-#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
+
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@@ -39,11 +41,11 @@
/*
* SDRAM configuration registers.
*/
-#define MCFSIM_DCR 0x44 /* SDRAM control */
-#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
-#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
-#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
-#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
+#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
+#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
+#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
+#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
+#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
/*
* Reset Controll Unit (relative to IPSBAR).
@@ -57,10 +59,19 @@
/*
* UART module.
*/
-#define MCFUART_BASE1 0x200 /* Base address of UART1 */
-#define MCFUART_BASE2 0x240 /* Base address of UART2 */
-#define MCFUART_BASE3 0x280 /* Base address of UART3 */
+#define MCFUART_BASE1 (MCF_IPSBAR + 0x200)
+#define MCFUART_BASE2 (MCF_IPSBAR + 0x240)
+#define MCFUART_BASE3 (MCF_IPSBAR + 0x280)
+
+/*
+ * FEC ethernet module.
+ */
+#define MCFFEC_BASE (MCF_IPSBAR + 0x1000)
+#define MCFFEC_SIZE 0x800
+/*
+ * GPIO module.
+ */
#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
@@ -118,12 +129,22 @@
#define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C)
/*
- * EPort
+ * PIT timer base addresses.
*/
+#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
+#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
+#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
+#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
+/*
+ * EPort
+ */
+#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000)
#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
+#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003)
#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
+#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
/*
* Generic GPIO support
@@ -143,5 +164,14 @@
*/
#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
+
+/*
+ * DMA unit base addresses.
+ */
+#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100)
+#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140)
+#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180)
+#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0)
+
/****************************************************************************/
#endif /* m523xsim_h */
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 4908b118f2fd..805714ca8d7d 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -13,10 +13,16 @@
#define CPU_NAME "COLDFIRE(m5249)"
#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m52xxacr.h>
/*
+ * The 5249 has a second MBAR region, define its address.
+ */
+#define MCF_MBAR2 0x80000000
+
+/*
* Define the 5249 SIM register set addresses.
*/
#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
@@ -55,11 +61,17 @@
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
-#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
-#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
+#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
+#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
+#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
+#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
+#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
+
+/*
+ * Timer module.
+ */
+#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
+#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
/*
* UART module.
@@ -68,6 +80,14 @@
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
/*
+ * DMA unit base addresses.
+ */
+#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
+#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
+#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
+#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
+
+/*
* Some symbol defines for the above...
*/
#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index b7cc50abc831..759c2b07a994 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -14,6 +14,7 @@
#define CPU_NAME "COLDFIRE(m5272)"
#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK MCF_CLK
#include <asm/m52xxacr.h>
@@ -80,6 +81,13 @@
#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */
#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
+#define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */
+
+#define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */
+#define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */
+#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */
+#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */
+
/*
* Define system peripheral IRQ usage.
*/
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index e8042e8bc003..74855a66c050 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -13,14 +13,16 @@
#define CPU_NAME "COLDFIRE(m527x)"
#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m52xxacr.h>
/*
* Define the 5270/5271 SIM register set addresses.
*/
-#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
-#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */
+#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */
+
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@@ -42,29 +44,45 @@
* SDRAM configuration registers.
*/
#ifdef CONFIG_M5271
-#define MCFSIM_DCR 0x40 /* SDRAM control */
-#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
-#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
-#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
-#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
+#define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */
+#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
+#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
+#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
+#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
#endif
#ifdef CONFIG_M5275
-#define MCFSIM_DMR 0x40 /* SDRAM mode */
-#define MCFSIM_DCR 0x44 /* SDRAM control */
-#define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */
-#define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */
-#define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */
-#define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */
-#define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */
-#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */
+#define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */
+#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
+#define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */
+#define MCFSIM_DCFG2 (MCF_IPSBAR + 0x4c) /* Configuration 2 */
+#define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */
+#define MCFSIM_DMR0 (MCF_IPSBAR + 0x54) /* Address mask 0 */
+#define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */
+#define MCFSIM_DMR1 (MCF_IPSBAR + 0x5c) /* Address mask 1 */
#endif
/*
+ * DMA unit base addresses.
+ */
+#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100)
+#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140)
+#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180)
+#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0)
+
+/*
* UART module.
*/
-#define MCFUART_BASE1 0x200 /* Base address of UART1 */
-#define MCFUART_BASE2 0x240 /* Base address of UART2 */
-#define MCFUART_BASE3 0x280 /* Base address of UART3 */
+#define MCFUART_BASE1 (MCF_IPSBAR + 0x200)
+#define MCFUART_BASE2 (MCF_IPSBAR + 0x240)
+#define MCFUART_BASE3 (MCF_IPSBAR + 0x280)
+
+/*
+ * FEC ethernet module.
+ */
+#define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000)
+#define MCFFEC_SIZE0 0x800
+#define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800)
+#define MCFFEC_SIZE1 0x800
#ifdef CONFIG_M5271
#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
@@ -231,14 +249,22 @@
#endif
/*
- * EPort
+ * PIT timer base addresses.
*/
+#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
+#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
+#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
+#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
+/*
+ * EPort
+ */
+#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000)
#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
+#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003)
#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
-
-
+#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
/*
* GPIO pins setups to enable the UARTs.
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index a6d2f4d9aaa0..d798bd5df56c 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -13,14 +13,16 @@
#define CPU_NAME "COLDFIRE(m528x)"
#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK MCF_CLK
#include <asm/m52xxacr.h>
/*
* Define the 5280/5282 SIM register set addresses.
*/
-#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
-#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
+
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@@ -39,18 +41,32 @@
/*
* SDRAM configuration registers.
*/
-#define MCFSIM_DCR 0x44 /* SDRAM control */
-#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
-#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
-#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
-#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
+#define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */
+#define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */
+#define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */
+#define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */
+#define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */
+
+/*
+ * DMA unit base addresses.
+ */
+#define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100)
+#define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140)
+#define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180)
+#define MCFDMA_BASE3 (MCF_IPSBAR + 0x000001C0)
/*
* UART module.
*/
-#define MCFUART_BASE1 0x200 /* Base address of UART1 */
-#define MCFUART_BASE2 0x240 /* Base address of UART2 */
-#define MCFUART_BASE3 0x280 /* Base address of UART3 */
+#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000200)
+#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000240)
+#define MCFUART_BASE3 (MCF_IPSBAR + 0x00000280)
+
+/*
+ * FEC ethernet module.
+ */
+#define MCFFEC_BASE (MCF_IPSBAR + 0x00001000)
+#define MCFFEC_SIZE 0x800
/*
* GPIO registers
@@ -163,6 +179,14 @@
#define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C)
/*
+ * PIT timer base addresses.
+ */
+#define MCFPIT_BASE1 (MCF_IPSBAR + 0x00150000)
+#define MCFPIT_BASE2 (MCF_IPSBAR + 0x00160000)
+#define MCFPIT_BASE3 (MCF_IPSBAR + 0x00170000)
+#define MCFPIT_BASE4 (MCF_IPSBAR + 0x00180000)
+
+/*
* Edge Port registers
*/
#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000)
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 0bf57397e7a9..4c94c01f36c4 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -16,6 +16,7 @@
#define CPU_NAME "COLDFIRE(m5307)"
#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m53xxacr.h>
@@ -89,16 +90,30 @@
#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
#endif /* CONFIG_OLDMASK */
-#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
-#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
+#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
+#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM Addr/Ctrl 0 */
+#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM Mask 0 */
+#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM Addr/Ctrl 1 */
+#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM Mask 1 */
+
+/*
+ * Timer module.
+ */
+#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
+#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
#define MCFSIM_PADDR (MCF_MBAR + 0x244)
#define MCFSIM_PADAT (MCF_MBAR + 0x248)
/*
+ * DMA unit base addresses.
+ */
+#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
+#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
+#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
+#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
+
+/*
* UART module.
*/
#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index e6470f8ca324..ba4cc784f574 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -11,6 +11,7 @@
#define CPU_NAME "COLDFIRE(m532x)"
#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 3)
#include <asm/m53xxacr.h>
@@ -85,6 +86,14 @@
#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */
#define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */
+/*
+ * Timer module.
+ */
+#define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */
+#define MCFTIMER_BASE2 0xFC074000 /* Base address of TIMER2 */
+#define MCFTIMER_BASE3 0xFC078000 /* Base address of TIMER3 */
+#define MCFTIMER_BASE4 0xFC07C000 /* Base address of TIMER4 */
+
/*********************************************************************
*
* Reset Controller Module
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 75f5c28a551d..762c58c89050 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -16,6 +16,7 @@
#define CPU_NAME "COLDFIRE(m5407)"
#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m54xxacr.h>
@@ -72,11 +73,17 @@
#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
-#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
-#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
+#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
+#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
+#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
+#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
+#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
+
+/*
+ * Timer module.
+ */
+#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
+#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
@@ -85,6 +92,14 @@
#define MCFSIM_PADAT (MCF_MBAR + 0x248)
/*
+ * DMA unit base addresses.
+ */
+#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
+#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
+#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
+#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
+
+/*
* Generic GPIO support
*/
#define MCFGPIO_PIN_MAX 16
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index 462ae5328441..1ed8bfb02772 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -7,6 +7,7 @@
#define CPU_NAME "COLDFIRE(m54xx)"
#define CPU_INSTR_PER_JIFFY 2
+#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m54xxacr.h>
@@ -15,7 +16,8 @@
/*
* Interrupt Controller Registers
*/
-#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */
+
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
@@ -48,6 +50,16 @@
#define MCFGPIO_IRQ_VECBASE -1
/*
+ * EDGE Port support.
+ */
+#define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */
+#define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */
+#define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */
+#define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */
+#define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */
+#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */
+
+/*
* Some PSC related definitions
*/
#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3))
diff --git a/arch/m68k/include/asm/mcfdma.h b/arch/m68k/include/asm/mcfdma.h
index 705c52c79cd8..10bc7e391c14 100644
--- a/arch/m68k/include/asm/mcfdma.h
+++ b/arch/m68k/include/asm/mcfdma.h
@@ -11,29 +11,6 @@
#define mcfdma_h
/****************************************************************************/
-
-/*
- * Get address specific defines for this Coldfire member.
- */
-#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
-#define MCFDMA_BASE0 0x200 /* Base address of DMA 0 */
-#define MCFDMA_BASE1 0x240 /* Base address of DMA 1 */
-#elif defined(CONFIG_M5272)
-#define MCFDMA_BASE0 0x0e0 /* Base address of DMA 0 */
-#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
-/* These are relative to the IPSBAR, not MBAR */
-#define MCFDMA_BASE0 0x100 /* Base address of DMA 0 */
-#define MCFDMA_BASE1 0x140 /* Base address of DMA 1 */
-#define MCFDMA_BASE2 0x180 /* Base address of DMA 2 */
-#define MCFDMA_BASE3 0x1C0 /* Base address of DMA 3 */
-#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
-#define MCFDMA_BASE0 0x300 /* Base address of DMA 0 */
-#define MCFDMA_BASE1 0x340 /* Base address of DMA 1 */
-#define MCFDMA_BASE2 0x380 /* Base address of DMA 2 */
-#define MCFDMA_BASE3 0x3C0 /* Base address of DMA 3 */
-#endif
-
-
#if !defined(CONFIG_M5272)
/*
diff --git a/arch/m68k/include/asm/mcfpit.h b/arch/m68k/include/asm/mcfpit.h
index f570cf64fd29..9fd321ca0725 100644
--- a/arch/m68k/include/asm/mcfpit.h
+++ b/arch/m68k/include/asm/mcfpit.h
@@ -11,22 +11,8 @@
#define mcfpit_h
/****************************************************************************/
-
-/*
- * Get address specific defines for the 5270/5271, 5280/5282, and 5208.
- */
-#if defined(CONFIG_M520x)
-#define MCFPIT_BASE1 0x00080000 /* Base address of TIMER1 */
-#define MCFPIT_BASE2 0x00084000 /* Base address of TIMER2 */
-#else
-#define MCFPIT_BASE1 0x00150000 /* Base address of TIMER1 */
-#define MCFPIT_BASE2 0x00160000 /* Base address of TIMER2 */
-#define MCFPIT_BASE3 0x00170000 /* Base address of TIMER3 */
-#define MCFPIT_BASE4 0x00180000 /* Base address of TIMER4 */
-#endif
-
/*
- * Define the PIT timer register set addresses.
+ * Define the PIT timer register address offsets.
*/
#define MCFPIT_PCSR 0x0 /* PIT control register */
#define MCFPIT_PMR 0x2 /* PIT modulus register */
diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h
index 0f90f6d2227a..92b276fe8240 100644
--- a/arch/m68k/include/asm/mcftimer.h
+++ b/arch/m68k/include/asm/mcftimer.h
@@ -12,29 +12,6 @@
#define mcftimer_h
/****************************************************************************/
-
-/*
- * Get address specific defines for this ColdFire member.
- */
-#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
-#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */
-#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */
-#elif defined(CONFIG_M5272)
-#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */
-#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */
-#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */
-#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */
-#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
-#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */
-#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */
-#elif defined(CONFIG_M532x)
-#define MCFTIMER_BASE1 0xfc070000 /* Base address of TIMER1 */
-#define MCFTIMER_BASE2 0xfc074000 /* Base address of TIMER2 */
-#define MCFTIMER_BASE3 0xfc078000 /* Base address of TIMER3 */
-#define MCFTIMER_BASE4 0xfc07c000 /* Base address of TIMER4 */
-#endif
-
-
/*
* Define the TIMER register set addresses.
*/
diff --git a/arch/m68k/include/asm/natfeat.h b/arch/m68k/include/asm/natfeat.h
new file mode 100644
index 000000000000..a3521b80c3b9
--- /dev/null
+++ b/arch/m68k/include/asm/natfeat.h
@@ -0,0 +1,22 @@
+/*
+ * ARAnyM hardware support via Native Features (natfeats)
+ *
+ * Copyright (c) 2005 Petr Stehlik of ARAnyM dev team
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL), incorporated herein by reference.
+ */
+
+#ifndef _NATFEAT_H
+#define _NATFEAT_H
+
+long nf_get_id(const char *feature_name);
+long nf_call(long id, ...);
+
+void nf_init(void);
+void nf_shutdown(void);
+
+void nfprint(const char *fmt, ...)
+ __attribute__ ((format (printf, 1, 2)));
+
+# endif /* _NATFEAT_H */
diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h
index 278c69bad57a..f111b02b704f 100644
--- a/arch/m68k/include/asm/processor.h
+++ b/arch/m68k/include/asm/processor.h
@@ -113,6 +113,8 @@ static inline void start_thread(struct pt_regs * regs, unsigned long pc,
wrusp(usp);
}
+extern int handle_kernel_fault(struct pt_regs *regs);
+
#else
/*
diff --git a/arch/m68k/kernel/setup.c b/arch/m68k/kernel/setup.c
index b3963ab3d149..334d83640376 100644
--- a/arch/m68k/kernel/setup.c
+++ b/arch/m68k/kernel/setup.c
@@ -42,6 +42,7 @@
#ifdef CONFIG_SUN3X
#include <asm/dvma.h>
#endif
+#include <asm/natfeat.h>
#if !FPSTATESIZE || !NR_IRQS
#warning No CPU/platform type selected, your kernel will not work!
@@ -324,6 +325,10 @@ void __init setup_arch(char **cmdline_p)
panic("No configuration setup");
}
+#ifdef CONFIG_NATFEAT
+ nf_init();
+#endif
+
paging_init();
#ifndef CONFIG_SUN3
diff --git a/arch/m68k/kernel/signal.c b/arch/m68k/kernel/signal.c
index d12c3b0d9e4f..a0afc239304e 100644
--- a/arch/m68k/kernel/signal.c
+++ b/arch/m68k/kernel/signal.c
@@ -42,6 +42,7 @@
#include <linux/personality.h>
#include <linux/tty.h>
#include <linux/binfmts.h>
+#include <linux/module.h>
#include <asm/setup.h>
#include <asm/uaccess.h>
@@ -51,7 +52,7 @@
#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
-const int frame_extra_sizes[16] = {
+static const int frame_extra_sizes[16] = {
[1] = -1, /* sizeof(((struct frame *)0)->un.fmt1), */
[2] = sizeof(((struct frame *)0)->un.fmt2),
[3] = sizeof(((struct frame *)0)->un.fmt3),
@@ -69,6 +70,27 @@ const int frame_extra_sizes[16] = {
[15] = -1, /* sizeof(((struct frame *)0)->un.fmtf), */
};
+int handle_kernel_fault(struct pt_regs *regs)
+{
+ const struct exception_table_entry *fixup;
+ struct pt_regs *tregs;
+
+ /* Are we prepared to handle this kernel fault? */
+ fixup = search_exception_tables(regs->pc);
+ if (!fixup)
+ return 0;
+
+ /* Create a new four word stack frame, discarding the old one. */
+ regs->stkadj = frame_extra_sizes[regs->format];
+ tregs = (struct pt_regs *)((long)regs + regs->stkadj);
+ tregs->vector = regs->vector;
+ tregs->format = 0;
+ tregs->pc = fixup->fixup;
+ tregs->sr = regs->sr;
+
+ return 1;
+}
+
/*
* Atomically swap in the new signal mask, and wait for a signal.
*/
diff --git a/arch/m68k/kernel/time.c b/arch/m68k/kernel/time.c
index 06438dac08ff..18b34ee5db3b 100644
--- a/arch/m68k/kernel/time.c
+++ b/arch/m68k/kernel/time.c
@@ -37,11 +37,11 @@ static inline int set_rtc_mmss(unsigned long nowtime)
/*
* timer_interrupt() needs to keep up the real-time clock,
- * as well as call the "do_timer()" routine every clocktick
+ * as well as call the "xtime_update()" routine every clocktick
*/
static irqreturn_t timer_interrupt(int irq, void *dummy)
{
- do_timer(1);
+ xtime_update(1);
update_process_times(user_mode(get_irq_regs()));
profile_tick(CPU_PROFILING);
diff --git a/arch/m68k/kernel/traps.c b/arch/m68k/kernel/traps.c
index ada4f4cca811..4022bbc28878 100644
--- a/arch/m68k/kernel/traps.c
+++ b/arch/m68k/kernel/traps.c
@@ -48,10 +48,7 @@ asmlinkage void nmihandler(void);
asmlinkage void fpu_emu(void);
#endif
-e_vector vectors[256] = {
- [VEC_BUSERR] = buserr,
- [VEC_SYS] = system_call,
-};
+e_vector vectors[256];
/* nmi handler for the Amiga */
asm(".text\n"
@@ -61,10 +58,11 @@ asm(".text\n"
/*
* this must be called very early as the kernel might
* use some instruction that are emulated on the 060
+ * and so we're prepared for early probe attempts (e.g. nf_init).
*/
void __init base_trap_init(void)
{
- if(MACH_IS_SUN3X) {
+ if (MACH_IS_SUN3X) {
extern e_vector *sun3x_prom_vbr;
__asm__ volatile ("movec %%vbr, %0" : "=r" (sun3x_prom_vbr));
@@ -79,6 +77,10 @@ void __init base_trap_init(void)
vectors[VEC_UNIMPII] = unimp_vec;
}
+
+ vectors[VEC_BUSERR] = buserr;
+ vectors[VEC_ILLEGAL] = trap;
+ vectors[VEC_SYS] = system_call;
}
void __init trap_init (void)
@@ -1055,9 +1057,11 @@ asmlinkage void trap_c(struct frame *fp)
siginfo_t info;
if (fp->ptregs.sr & PS_S) {
- if ((fp->ptregs.vector >> 2) == VEC_TRACE) {
- /* traced a trapping instruction */
- } else
+ if (fp->ptregs.vector == VEC_TRACE << 2) {
+ /* traced a trapping instruction on a 68020/30,
+ * real exception will be executed afterwards.
+ */
+ } else if (!handle_kernel_fault(&fp->ptregs))
bad_super_trap(fp);
return;
}
diff --git a/arch/m68k/math-emu/Makefile b/arch/m68k/math-emu/Makefile
index a0935bf98362..547c23c6e40e 100644
--- a/arch/m68k/math-emu/Makefile
+++ b/arch/m68k/math-emu/Makefile
@@ -2,8 +2,8 @@
# Makefile for the linux kernel.
#
-#EXTRA_AFLAGS += -DFPU_EMU_DEBUG
-#EXTRA_CFLAGS += -DFPU_EMU_DEBUG
+#asflags-y := -DFPU_EMU_DEBUG
+#ccflags-y := -DFPU_EMU_DEBUG
obj-y := fp_entry.o fp_scan.o fp_util.o fp_move.o fp_movem.o \
fp_cond.o fp_arith.o fp_log.o fp_trig.o
diff --git a/arch/m68k/mm/fault.c b/arch/m68k/mm/fault.c
index a96394a0333d..2db6099784ba 100644
--- a/arch/m68k/mm/fault.c
+++ b/arch/m68k/mm/fault.c
@@ -18,7 +18,6 @@
#include <asm/pgalloc.h>
extern void die_if_kernel(char *, struct pt_regs *, long);
-extern const int frame_extra_sizes[]; /* in m68k/kernel/signal.c */
int send_fault_sig(struct pt_regs *regs)
{
@@ -35,21 +34,8 @@ int send_fault_sig(struct pt_regs *regs)
force_sig_info(siginfo.si_signo,
&siginfo, current);
} else {
- const struct exception_table_entry *fixup;
-
- /* Are we prepared to handle this kernel fault? */
- if ((fixup = search_exception_tables(regs->pc))) {
- struct pt_regs *tregs;
- /* Create a new four word stack frame, discarding the old
- one. */
- regs->stkadj = frame_extra_sizes[regs->format];
- tregs = (struct pt_regs *)((ulong)regs + regs->stkadj);
- tregs->vector = regs->vector;
- tregs->format = 0;
- tregs->pc = fixup->fixup;
- tregs->sr = regs->sr;
+ if (handle_kernel_fault(regs))
return -1;
- }
//if (siginfo.si_signo == SIGBUS)
// force_sig_info(siginfo.si_signo,
diff --git a/arch/m68k/mvme147/config.c b/arch/m68k/mvme147/config.c
index 100baaa692a1..6cb9c3a9b6c9 100644
--- a/arch/m68k/mvme147/config.c
+++ b/arch/m68k/mvme147/config.c
@@ -46,8 +46,8 @@ extern void mvme147_reset (void);
static int bcd2int (unsigned char b);
-/* Save tick handler routine pointer, will point to do_timer() in
- * kernel/sched.c, called via mvme147_process_int() */
+/* Save tick handler routine pointer, will point to xtime_update() in
+ * kernel/time/timekeeping.c, called via mvme147_process_int() */
irq_handler_t tick_handler;
diff --git a/arch/m68k/mvme16x/config.c b/arch/m68k/mvme16x/config.c
index 11edf61cc2c4..0b28e2621653 100644
--- a/arch/m68k/mvme16x/config.c
+++ b/arch/m68k/mvme16x/config.c
@@ -51,8 +51,8 @@ extern void mvme16x_reset (void);
int bcd2int (unsigned char b);
-/* Save tick handler routine pointer, will point to do_timer() in
- * kernel/sched.c, called via mvme16x_process_int() */
+/* Save tick handler routine pointer, will point to xtime_update() in
+ * kernel/time/timekeeping.c, called via mvme16x_process_int() */
static irq_handler_t tick_handler;
diff --git a/arch/m68k/sun3/sun3ints.c b/arch/m68k/sun3/sun3ints.c
index 2d9e21bd313a..6464ad3ae3e6 100644
--- a/arch/m68k/sun3/sun3ints.c
+++ b/arch/m68k/sun3/sun3ints.c
@@ -66,7 +66,7 @@ static irqreturn_t sun3_int5(int irq, void *dev_id)
#ifdef CONFIG_SUN3
intersil_clear();
#endif
- do_timer(1);
+ xtime_update(1);
update_process_times(user_mode(get_irq_regs()));
if (!(kstat_cpu(0).irqs[irq] % 20))
sun3_leds(led_pattern[(kstat_cpu(0).irqs[irq] % 160) / 20]);