diff options
Diffstat (limited to 'arch/m68k/include')
| -rw-r--r-- | arch/m68k/include/asm/atariints.h | 4 | ||||
| -rw-r--r-- | arch/m68k/include/asm/cacheflush_no.h | 32 | ||||
| -rw-r--r-- | arch/m68k/include/asm/entry.h | 6 | ||||
| -rw-r--r-- | arch/m68k/include/asm/flat.h | 7 | ||||
| -rw-r--r-- | arch/m68k/include/asm/io_mm.h | 7 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m528xsim.h | 179 | ||||
| -rw-r--r-- | arch/m68k/include/asm/mcfgpio.h | 57 | ||||
| -rw-r--r-- | arch/m68k/include/asm/unaligned.h | 2 | ||||
| -rw-r--r-- | arch/m68k/include/asm/vga.h | 27 |
9 files changed, 210 insertions, 111 deletions
diff --git a/arch/m68k/include/asm/atariints.h b/arch/m68k/include/asm/atariints.h index 656bbbf5a6ff..5fc13bdf9044 100644 --- a/arch/m68k/include/asm/atariints.h +++ b/arch/m68k/include/asm/atariints.h @@ -198,7 +198,7 @@ static inline int atari_irq_pending( unsigned irq ) return( get_mfp_bit( irq, MFP_PENDING ) ); } -unsigned long atari_register_vme_int( void ); -void atari_unregister_vme_int( unsigned long ); +unsigned int atari_register_vme_int(void); +void atari_unregister_vme_int(unsigned int); #endif /* linux/atariints.h */ diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index cb88aa96c4f1..7cafb537d03c 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h @@ -30,11 +30,8 @@ void mcf_cache_push(void); -static inline void __flush_cache_all(void) +static inline void __clear_cache_all(void) { -#ifdef CACHE_PUSH - mcf_cache_push(); -#endif #ifdef CACHE_INVALIDATE __asm__ __volatile__ ( "movel %0, %%d0\n\t" @@ -44,6 +41,14 @@ static inline void __flush_cache_all(void) #endif } +static inline void __flush_cache_all(void) +{ +#ifdef CACHE_PUSH + mcf_cache_push(); +#endif + __clear_cache_all(); +} + /* * Some ColdFire parts implement separate instruction and data caches, * on those we should just flush the appropriate cache. If we don't need @@ -76,4 +81,23 @@ static inline void __flush_dcache_all(void) __asm__ __volatile__ ( "nop" ); #endif } + +/* + * Push cache entries at supplied address. We want to write back any dirty + * data and the invalidate the cache lines associated with this address. + */ +static inline void cache_push(unsigned long paddr, int len) +{ + __flush_cache_all(); +} + +/* + * Clear cache entries at supplied address (that is don't write back any + * dirty data). + */ +static inline void cache_clear(unsigned long paddr, int len) +{ + __clear_cache_all(); +} + #endif /* _M68KNOMMU_CACHEFLUSH_H */ diff --git a/arch/m68k/include/asm/entry.h b/arch/m68k/include/asm/entry.h index 622138dc7288..d7de0f1a8957 100644 --- a/arch/m68k/include/asm/entry.h +++ b/arch/m68k/include/asm/entry.h @@ -33,13 +33,11 @@ /* the following macro is used when enabling interrupts */ #if defined(MACH_ATARI_ONLY) - /* block out HSYNC on the atari */ -#define ALLOWINT (~0x400) -#define MAX_NOINT_IPL 3 + /* block out HSYNC = ipl 2 on the atari */ +#define ALLOWINT (~0x500) #else /* portable version */ #define ALLOWINT (~0x700) -#define MAX_NOINT_IPL 0 #endif /* machine compilation types */ #ifdef __ASSEMBLY__ diff --git a/arch/m68k/include/asm/flat.h b/arch/m68k/include/asm/flat.h index a0e290793978..f9454b89a51b 100644 --- a/arch/m68k/include/asm/flat.h +++ b/arch/m68k/include/asm/flat.h @@ -11,6 +11,11 @@ #define flat_get_addr_from_rp(rp, relval, flags, p) get_unaligned(rp) #define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp) #define flat_get_relocate_addr(rel) (rel) -#define flat_set_persistent(relval, p) 0 + +static inline int flat_set_persistent(unsigned long relval, + unsigned long *persistent) +{ + return 0; +} #endif /* __M68KNOMMU_FLAT_H__ */ diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h index 0fb3468000e7..fa4324bcf566 100644 --- a/arch/m68k/include/asm/io_mm.h +++ b/arch/m68k/include/asm/io_mm.h @@ -278,6 +278,13 @@ static inline void isa_delay(void) #define readl(addr) in_le32(addr) #define writel(val,addr) out_le32((addr),(val)) +#define readsb(port, buf, nr) raw_insb((port), (u8 *)(buf), (nr)) +#define readsw(port, buf, nr) raw_insw((port), (u16 *)(buf), (nr)) +#define readsl(port, buf, nr) raw_insl((port), (u32 *)(buf), (nr)) +#define writesb(port, buf, nr) raw_outsb((port), (u8 *)(buf), (nr)) +#define writesw(port, buf, nr) raw_outsw((port), (u16 *)(buf), (nr)) +#define writesl(port, buf, nr) raw_outsl((port), (u32 *)(buf), (nr)) + #define mmiowb() static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size) diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index 569476fba18c..d63b99ff7ff7 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h @@ -97,100 +97,81 @@ /* * GPIO registers */ -#define MCFGPIO_PORTA (MCF_IPSBAR + 0x00100000) -#define MCFGPIO_PORTB (MCF_IPSBAR + 0x00100001) -#define MCFGPIO_PORTC (MCF_IPSBAR + 0x00100002) -#define MCFGPIO_PORTD (MCF_IPSBAR + 0x00100003) -#define MCFGPIO_PORTE (MCF_IPSBAR + 0x00100004) -#define MCFGPIO_PORTF (MCF_IPSBAR + 0x00100005) -#define MCFGPIO_PORTG (MCF_IPSBAR + 0x00100006) -#define MCFGPIO_PORTH (MCF_IPSBAR + 0x00100007) -#define MCFGPIO_PORTJ (MCF_IPSBAR + 0x00100008) -#define MCFGPIO_PORTDD (MCF_IPSBAR + 0x00100009) -#define MCFGPIO_PORTEH (MCF_IPSBAR + 0x0010000A) -#define MCFGPIO_PORTEL (MCF_IPSBAR + 0x0010000B) -#define MCFGPIO_PORTAS (MCF_IPSBAR + 0x0010000C) -#define MCFGPIO_PORTQS (MCF_IPSBAR + 0x0010000D) -#define MCFGPIO_PORTSD (MCF_IPSBAR + 0x0010000E) -#define MCFGPIO_PORTTC (MCF_IPSBAR + 0x0010000F) -#define MCFGPIO_PORTTD (MCF_IPSBAR + 0x00100010) -#define MCFGPIO_PORTUA (MCF_IPSBAR + 0x00100011) - -#define MCFGPIO_DDRA (MCF_IPSBAR + 0x00100014) -#define MCFGPIO_DDRB (MCF_IPSBAR + 0x00100015) -#define MCFGPIO_DDRC (MCF_IPSBAR + 0x00100016) -#define MCFGPIO_DDRD (MCF_IPSBAR + 0x00100017) -#define MCFGPIO_DDRE (MCF_IPSBAR + 0x00100018) -#define MCFGPIO_DDRF (MCF_IPSBAR + 0x00100019) -#define MCFGPIO_DDRG (MCF_IPSBAR + 0x0010001A) -#define MCFGPIO_DDRH (MCF_IPSBAR + 0x0010001B) -#define MCFGPIO_DDRJ (MCF_IPSBAR + 0x0010001C) -#define MCFGPIO_DDRDD (MCF_IPSBAR + 0x0010001D) -#define MCFGPIO_DDREH (MCF_IPSBAR + 0x0010001E) -#define MCFGPIO_DDREL (MCF_IPSBAR + 0x0010001F) -#define MCFGPIO_DDRAS (MCF_IPSBAR + 0x00100020) -#define MCFGPIO_DDRQS (MCF_IPSBAR + 0x00100021) -#define MCFGPIO_DDRSD (MCF_IPSBAR + 0x00100022) -#define MCFGPIO_DDRTC (MCF_IPSBAR + 0x00100023) -#define MCFGPIO_DDRTD (MCF_IPSBAR + 0x00100024) -#define MCFGPIO_DDRUA (MCF_IPSBAR + 0x00100025) - -#define MCFGPIO_PORTAP (MCF_IPSBAR + 0x00100028) -#define MCFGPIO_PORTBP (MCF_IPSBAR + 0x00100029) -#define MCFGPIO_PORTCP (MCF_IPSBAR + 0x0010002A) -#define MCFGPIO_PORTDP (MCF_IPSBAR + 0x0010002B) -#define MCFGPIO_PORTEP (MCF_IPSBAR + 0x0010002C) -#define MCFGPIO_PORTFP (MCF_IPSBAR + 0x0010002D) -#define MCFGPIO_PORTGP (MCF_IPSBAR + 0x0010002E) -#define MCFGPIO_PORTHP (MCF_IPSBAR + 0x0010002F) -#define MCFGPIO_PORTJP (MCF_IPSBAR + 0x00100030) -#define MCFGPIO_PORTDDP (MCF_IPSBAR + 0x00100031) -#define MCFGPIO_PORTEHP (MCF_IPSBAR + 0x00100032) -#define MCFGPIO_PORTELP (MCF_IPSBAR + 0x00100033) -#define MCFGPIO_PORTASP (MCF_IPSBAR + 0x00100034) -#define MCFGPIO_PORTQSP (MCF_IPSBAR + 0x00100035) -#define MCFGPIO_PORTSDP (MCF_IPSBAR + 0x00100036) -#define MCFGPIO_PORTTCP (MCF_IPSBAR + 0x00100037) -#define MCFGPIO_PORTTDP (MCF_IPSBAR + 0x00100038) -#define MCFGPIO_PORTUAP (MCF_IPSBAR + 0x00100039) - -#define MCFGPIO_SETA (MCF_IPSBAR + 0x00100028) -#define MCFGPIO_SETB (MCF_IPSBAR + 0x00100029) -#define MCFGPIO_SETC (MCF_IPSBAR + 0x0010002A) -#define MCFGPIO_SETD (MCF_IPSBAR + 0x0010002B) -#define MCFGPIO_SETE (MCF_IPSBAR + 0x0010002C) -#define MCFGPIO_SETF (MCF_IPSBAR + 0x0010002D) -#define MCFGPIO_SETG (MCF_IPSBAR + 0x0010002E) -#define MCFGPIO_SETH (MCF_IPSBAR + 0x0010002F) -#define MCFGPIO_SETJ (MCF_IPSBAR + 0x00100030) -#define MCFGPIO_SETDD (MCF_IPSBAR + 0x00100031) -#define MCFGPIO_SETEH (MCF_IPSBAR + 0x00100032) -#define MCFGPIO_SETEL (MCF_IPSBAR + 0x00100033) -#define MCFGPIO_SETAS (MCF_IPSBAR + 0x00100034) -#define MCFGPIO_SETQS (MCF_IPSBAR + 0x00100035) -#define MCFGPIO_SETSD (MCF_IPSBAR + 0x00100036) -#define MCFGPIO_SETTC (MCF_IPSBAR + 0x00100037) -#define MCFGPIO_SETTD (MCF_IPSBAR + 0x00100038) -#define MCFGPIO_SETUA (MCF_IPSBAR + 0x00100039) - -#define MCFGPIO_CLRA (MCF_IPSBAR + 0x0010003C) -#define MCFGPIO_CLRB (MCF_IPSBAR + 0x0010003D) -#define MCFGPIO_CLRC (MCF_IPSBAR + 0x0010003E) -#define MCFGPIO_CLRD (MCF_IPSBAR + 0x0010003F) -#define MCFGPIO_CLRE (MCF_IPSBAR + 0x00100040) -#define MCFGPIO_CLRF (MCF_IPSBAR + 0x00100041) -#define MCFGPIO_CLRG (MCF_IPSBAR + 0x00100042) -#define MCFGPIO_CLRH (MCF_IPSBAR + 0x00100043) -#define MCFGPIO_CLRJ (MCF_IPSBAR + 0x00100044) -#define MCFGPIO_CLRDD (MCF_IPSBAR + 0x00100045) -#define MCFGPIO_CLREH (MCF_IPSBAR + 0x00100046) -#define MCFGPIO_CLREL (MCF_IPSBAR + 0x00100047) -#define MCFGPIO_CLRAS (MCF_IPSBAR + 0x00100048) -#define MCFGPIO_CLRQS (MCF_IPSBAR + 0x00100049) -#define MCFGPIO_CLRSD (MCF_IPSBAR + 0x0010004A) -#define MCFGPIO_CLRTC (MCF_IPSBAR + 0x0010004B) -#define MCFGPIO_CLRTD (MCF_IPSBAR + 0x0010004C) -#define MCFGPIO_CLRUA (MCF_IPSBAR + 0x0010004D) +#define MCFGPIO_PODR_A (MCF_IPSBAR + 0x00100000) +#define MCFGPIO_PODR_B (MCF_IPSBAR + 0x00100001) +#define MCFGPIO_PODR_C (MCF_IPSBAR + 0x00100002) +#define MCFGPIO_PODR_D (MCF_IPSBAR + 0x00100003) +#define MCFGPIO_PODR_E (MCF_IPSBAR + 0x00100004) +#define MCFGPIO_PODR_F (MCF_IPSBAR + 0x00100005) +#define MCFGPIO_PODR_G (MCF_IPSBAR + 0x00100006) +#define MCFGPIO_PODR_H (MCF_IPSBAR + 0x00100007) +#define MCFGPIO_PODR_J (MCF_IPSBAR + 0x00100008) +#define MCFGPIO_PODR_DD (MCF_IPSBAR + 0x00100009) +#define MCFGPIO_PODR_EH (MCF_IPSBAR + 0x0010000A) +#define MCFGPIO_PODR_EL (MCF_IPSBAR + 0x0010000B) +#define MCFGPIO_PODR_AS (MCF_IPSBAR + 0x0010000C) +#define MCFGPIO_PODR_QS (MCF_IPSBAR + 0x0010000D) +#define MCFGPIO_PODR_SD (MCF_IPSBAR + 0x0010000E) +#define MCFGPIO_PODR_TC (MCF_IPSBAR + 0x0010000F) +#define MCFGPIO_PODR_TD (MCF_IPSBAR + 0x00100010) +#define MCFGPIO_PODR_UA (MCF_IPSBAR + 0x00100011) + +#define MCFGPIO_PDDR_A (MCF_IPSBAR + 0x00100014) +#define MCFGPIO_PDDR_B (MCF_IPSBAR + 0x00100015) +#define MCFGPIO_PDDR_C (MCF_IPSBAR + 0x00100016) +#define MCFGPIO_PDDR_D (MCF_IPSBAR + 0x00100017) +#define MCFGPIO_PDDR_E (MCF_IPSBAR + 0x00100018) +#define MCFGPIO_PDDR_F (MCF_IPSBAR + 0x00100019) +#define MCFGPIO_PDDR_G (MCF_IPSBAR + 0x0010001A) +#define MCFGPIO_PDDR_H (MCF_IPSBAR + 0x0010001B) +#define MCFGPIO_PDDR_J (MCF_IPSBAR + 0x0010001C) +#define MCFGPIO_PDDR_DD (MCF_IPSBAR + 0x0010001D) +#define MCFGPIO_PDDR_EH (MCF_IPSBAR + 0x0010001E) +#define MCFGPIO_PDDR_EL (MCF_IPSBAR + 0x0010001F) +#define MCFGPIO_PDDR_AS (MCF_IPSBAR + 0x00100020) +#define MCFGPIO_PDDR_QS (MCF_IPSBAR + 0x00100021) +#define MCFGPIO_PDDR_SD (MCF_IPSBAR + 0x00100022) +#define MCFGPIO_PDDR_TC (MCF_IPSBAR + 0x00100023) +#define MCFGPIO_PDDR_TD (MCF_IPSBAR + 0x00100024) +#define MCFGPIO_PDDR_UA (MCF_IPSBAR + 0x00100025) + +#define MCFGPIO_PPDSDR_A (MCF_IPSBAR + 0x00100028) +#define MCFGPIO_PPDSDR_B (MCF_IPSBAR + 0x00100029) +#define MCFGPIO_PPDSDR_C (MCF_IPSBAR + 0x0010002A) +#define MCFGPIO_PPDSDR_D (MCF_IPSBAR + 0x0010002B) +#define MCFGPIO_PPDSDR_E (MCF_IPSBAR + 0x0010002C) +#define MCFGPIO_PPDSDR_F (MCF_IPSBAR + 0x0010002D) +#define MCFGPIO_PPDSDR_G (MCF_IPSBAR + 0x0010002E) +#define MCFGPIO_PPDSDR_H (MCF_IPSBAR + 0x0010002F) +#define MCFGPIO_PPDSDR_J (MCF_IPSBAR + 0x00100030) +#define MCFGPIO_PPDSDR_DD (MCF_IPSBAR + 0x00100031) +#define MCFGPIO_PPDSDR_EH (MCF_IPSBAR + 0x00100032) +#define MCFGPIO_PPDSDR_EL (MCF_IPSBAR + 0x00100033) +#define MCFGPIO_PPDSDR_AS (MCF_IPSBAR + 0x00100034) +#define MCFGPIO_PPDSDR_QS (MCF_IPSBAR + 0x00100035) +#define MCFGPIO_PPDSDR_SD (MCF_IPSBAR + 0x00100036) +#define MCFGPIO_PPDSDR_TC (MCF_IPSBAR + 0x00100037) +#define MCFGPIO_PPDSDR_TD (MCF_IPSBAR + 0x00100038) +#define MCFGPIO_PPDSDR_UA (MCF_IPSBAR + 0x00100039) + +#define MCFGPIO_PCLRR_A (MCF_IPSBAR + 0x0010003C) +#define MCFGPIO_PCLRR_B (MCF_IPSBAR + 0x0010003D) +#define MCFGPIO_PCLRR_C (MCF_IPSBAR + 0x0010003E) +#define MCFGPIO_PCLRR_D (MCF_IPSBAR + 0x0010003F) +#define MCFGPIO_PCLRR_E (MCF_IPSBAR + 0x00100040) +#define MCFGPIO_PCLRR_F (MCF_IPSBAR + 0x00100041) +#define MCFGPIO_PCLRR_G (MCF_IPSBAR + 0x00100042) +#define MCFGPIO_PCLRR_H (MCF_IPSBAR + 0x00100043) +#define MCFGPIO_PCLRR_J (MCF_IPSBAR + 0x00100044) +#define MCFGPIO_PCLRR_DD (MCF_IPSBAR + 0x00100045) +#define MCFGPIO_PCLRR_EH (MCF_IPSBAR + 0x00100046) +#define MCFGPIO_PCLRR_EL (MCF_IPSBAR + 0x00100047) +#define MCFGPIO_PCLRR_AS (MCF_IPSBAR + 0x00100048) +#define MCFGPIO_PCLRR_QS (MCF_IPSBAR + 0x00100049) +#define MCFGPIO_PCLRR_SD (MCF_IPSBAR + 0x0010004A) +#define MCFGPIO_PCLRR_TC (MCF_IPSBAR + 0x0010004B) +#define MCFGPIO_PCLRR_TD (MCF_IPSBAR + 0x0010004C) +#define MCFGPIO_PCLRR_UA (MCF_IPSBAR + 0x0010004D) #define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050) #define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051) @@ -242,11 +223,11 @@ * definitions for generic gpio support * */ -#define MCFGPIO_PODR MCFGPIO_PORTA /* port output data */ -#define MCFGPIO_PDDR MCFGPIO_DDRA /* port data direction */ -#define MCFGPIO_PPDR MCFGPIO_PORTAP /* port pin data */ -#define MCFGPIO_SETR MCFGPIO_SETA /* set output */ -#define MCFGPIO_CLRR MCFGPIO_CLRA /* clr output */ +#define MCFGPIO_PODR MCFGPIO_PODR_A /* port output data */ +#define MCFGPIO_PDDR MCFGPIO_PDDR_A /* port data direction */ +#define MCFGPIO_PPDR MCFGPIO_PPDSDR_A/* port pin data */ +#define MCFGPIO_SETR MCFGPIO_PPDSDR_A/* set output */ +#define MCFGPIO_CLRR MCFGPIO_PCLRR_A /* clr output */ #define MCFGPIO_IRQ_MAX 8 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h index ee5e4ccce89e..fe468eaa51e0 100644 --- a/arch/m68k/include/asm/mcfgpio.h +++ b/arch/m68k/include/asm/mcfgpio.h @@ -29,6 +29,9 @@ struct mcf_gpio_chip { const u8 *gpio_to_pinmux; }; +extern struct mcf_gpio_chip mcf_gpio_chips[]; +extern unsigned int mcf_gpio_chips_size; + int mcf_gpio_direction_input(struct gpio_chip *, unsigned); int mcf_gpio_get_value(struct gpio_chip *, unsigned); int mcf_gpio_direction_output(struct gpio_chip *, unsigned, int); @@ -37,4 +40,58 @@ void mcf_gpio_set_value_fast(struct gpio_chip *, unsigned, int); int mcf_gpio_request(struct gpio_chip *, unsigned); void mcf_gpio_free(struct gpio_chip *, unsigned); +/* + * Define macros to ease the pain of setting up the GPIO tables. There + * are two cases we need to deal with here, they cover all currently + * available ColdFire GPIO hardware. There are of course minor differences + * in the layout and number of bits in each ColdFire part, but the macros + * take all that in. + * + * Firstly is the conventional GPIO registers where we toggle individual + * bits in a register, preserving the other bits in the register. For + * lack of a better term I have called this the slow method. + */ +#define MCFGPS(mlabel, mbase, mngpio, mpddr, mpodr, mppdr) \ + { \ + .gpio_chip = { \ + .label = #mlabel, \ + .request = mcf_gpio_request, \ + .free = mcf_gpio_free, \ + .direction_input = mcf_gpio_direction_input, \ + .direction_output = mcf_gpio_direction_output,\ + .get = mcf_gpio_get_value, \ + .set = mcf_gpio_set_value, \ + .base = mbase, \ + .ngpio = mngpio, \ + }, \ + .pddr = (void __iomem *) mpddr, \ + .podr = (void __iomem *) mpodr, \ + .ppdr = (void __iomem *) mppdr, \ + } + +/* + * Secondly is the faster case, where we have set and clear registers + * that allow us to set or clear a bit with a single write, not having + * to worry about preserving other bits. + */ +#define MCFGPF(mlabel, mbase, mngpio) \ + { \ + .gpio_chip = { \ + .label = #mlabel, \ + .request = mcf_gpio_request, \ + .free = mcf_gpio_free, \ + .direction_input = mcf_gpio_direction_input, \ + .direction_output = mcf_gpio_direction_output,\ + .get = mcf_gpio_get_value, \ + .set = mcf_gpio_set_value_fast, \ + .base = mbase, \ + .ngpio = mngpio, \ + }, \ + .pddr = (void __iomem *) MCFGPIO_PDDR_##mlabel, \ + .podr = (void __iomem *) MCFGPIO_PODR_##mlabel, \ + .ppdr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \ + .setr = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \ + .clrr = (void __iomem *) MCFGPIO_PCLRR_##mlabel, \ + } + #endif diff --git a/arch/m68k/include/asm/unaligned.h b/arch/m68k/include/asm/unaligned.h index 019caa740c21..f4043ae63db1 100644 --- a/arch/m68k/include/asm/unaligned.h +++ b/arch/m68k/include/asm/unaligned.h @@ -2,7 +2,7 @@ #define _ASM_M68K_UNALIGNED_H -#ifdef CONFIG_COLDFIRE +#if defined(CONFIG_COLDFIRE) || defined(CONFIG_M68000) #include <linux/unaligned/be_struct.h> #include <linux/unaligned/le_byteshift.h> #include <linux/unaligned/generic.h> diff --git a/arch/m68k/include/asm/vga.h b/arch/m68k/include/asm/vga.h new file mode 100644 index 000000000000..d3aa1401e7aa --- /dev/null +++ b/arch/m68k/include/asm/vga.h @@ -0,0 +1,27 @@ +#ifndef _ASM_M68K_VGA_H +#define _ASM_M68K_VGA_H + +#include <asm/raw_io.h> + +/* + * FIXME + * Ugh, we don't have PCI space, so map readb() and friends to use raw I/O + * accessors, which are identical to the z_*() Zorro bus accessors. + * This should make cirrusfb work again on Amiga + */ +#undef inb_p +#undef inw_p +#undef outb_p +#undef outw +#undef readb +#undef writeb +#undef writew +#define inb_p(port) 0 +#define inw_p(port) 0 +#define outb_p(port, val) do { } while (0) +#define outw(port, val) do { } while (0) +#define readb raw_inb +#define writeb raw_outb +#define writew raw_outw + +#endif /* _ASM_M68K_VGA_H */ |