diff options
Diffstat (limited to 'arch/blackfin/mach-bf561')
| -rw-r--r-- | arch/blackfin/mach-bf561/boards/acvilon.c | 2 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/boards/cm_bf561.c | 10 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/boards/ezkit.c | 68 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/coreb.c | 12 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/blackfin.h | 33 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/cdefBF561.h | 126 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/defBF561.h | 94 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/pll.h | 63 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/ints-priority.c | 16 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/smp.c | 24 |
10 files changed, 216 insertions, 232 deletions
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c index 35b6d124c1e3..0b1c20f14fe0 100644 --- a/arch/blackfin/mach-bf561/boards/acvilon.c +++ b/arch/blackfin/mach-bf561/boards/acvilon.c @@ -302,7 +302,7 @@ static struct platform_nand_data bfin_plat_nand_data = { static struct resource bfin_plat_nand_resources = { .start = 0x24000000, .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)), - .flags = IORESOURCE_IO, + .flags = IORESOURCE_MEM, }; static struct platform_device bfin_async_nand_device = { diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c index e127aedc1d7f..087b6b05cc73 100644 --- a/arch/blackfin/mach-bf561/boards/cm_bf561.c +++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c @@ -72,7 +72,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, @@ -111,12 +111,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { - .modalias = "ad1836", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .chip_select = 4, .controller_data = &ad1836_spi_chip_info, }, #endif @@ -278,7 +278,7 @@ static struct resource isp1362_hcd_resources[] = { }, { .start = IRQ_PF47, .end = IRQ_PF47, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index 9b93e2f95791..ab7a487975fd 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c @@ -14,6 +14,7 @@ #include <linux/spi/spi.h> #include <linux/irq.h> #include <linux/interrupt.h> +#include <linux/delay.h> #include <asm/dma.h> #include <asm/bfin5xx_spi.h> #include <asm/portmux.h> @@ -74,7 +75,7 @@ static struct resource isp1362_hcd_resources[] = { }, { .start = IRQ_PF8, .end = IRQ_PF8, - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; @@ -274,8 +275,8 @@ static struct platform_device ezkit_flash_device = { }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) \ - || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ + || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, @@ -328,14 +329,16 @@ static struct platform_device bfin_spi0_device = { #endif static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if defined(CONFIG_SND_BLACKFIN_AD183X) \ - || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ + || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { - .modalias = "ad1836", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .chip_select = 4, + .platform_data = "ad1836", /* only includes chip name for the moment */ .controller_data = &ad1836_spi_chip_info, + .mode = SPI_MODE_3, }, #endif #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) @@ -377,8 +380,8 @@ static struct platform_device bfin_device_gpiokeys = { #include <linux/i2c-gpio.h> static struct i2c_gpio_platform_data i2c_gpio_data = { - .sda_pin = 1, - .scl_pin = 0, + .sda_pin = GPIO_PF1, + .scl_pin = GPIO_PF0, .sda_is_open_drain = 0, .scl_is_open_drain = 0, .udelay = 40, @@ -420,6 +423,30 @@ static struct platform_device bfin_dpmc = { }, }; +#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) +static struct platform_device bfin_i2s = { + .name = "bfin-i2s", + .id = CONFIG_SND_BF5XX_SPORT_NUM, + /* TODO: add platform data here */ +}; +#endif + +#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) +static struct platform_device bfin_tdm = { + .name = "bfin-tdm", + .id = CONFIG_SND_BF5XX_SPORT_NUM, + /* TODO: add platform data here */ +}; +#endif + +#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) +static struct platform_device bfin_ac97 = { + .name = "bfin-ac97", + .id = CONFIG_SND_BF5XX_SPORT_NUM, + /* TODO: add platform data here */ +}; +#endif + static struct platform_device *ezkit_devices[] __initdata = { &bfin_dpmc, @@ -467,6 +494,18 @@ static struct platform_device *ezkit_devices[] __initdata = { #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) &ezkit_flash_device, #endif + +#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) + &bfin_i2s, +#endif + +#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) + &bfin_tdm, +#endif + +#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) + &bfin_ac97, +#endif }; static int __init ezkit_init(void) @@ -484,6 +523,17 @@ static int __init ezkit_init(void) SSYNC(); #endif +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) + bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 15)); + bfin_write_FIO0_FLAG_S(1 << 15); + SSYNC(); + /* + * This initialization lasts for approximately 4500 MCLKs. + * MCLK = 12.288MHz + */ + udelay(400); +#endif + spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); return 0; } diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c index deb2271d09a3..78ecb50bafc8 100644 --- a/arch/blackfin/mach-bf561/coreb.c +++ b/arch/blackfin/mach-bf561/coreb.c @@ -18,9 +18,9 @@ #include <linux/miscdevice.h> #include <linux/module.h> -#define CMD_COREB_START 2 -#define CMD_COREB_STOP 3 -#define CMD_COREB_RESET 4 +#define CMD_COREB_START _IO('b', 0) +#define CMD_COREB_STOP _IO('b', 1) +#define CMD_COREB_RESET _IO('b', 2) static long coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) @@ -29,10 +29,10 @@ coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) switch (cmd) { case CMD_COREB_START: - bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020); + bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020); break; case CMD_COREB_STOP: - bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020); + bfin_write_SYSCR(bfin_read_SYSCR() | 0x0020); bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); break; case CMD_COREB_RESET: @@ -51,6 +51,7 @@ coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) static const struct file_operations coreb_fops = { .owner = THIS_MODULE, .unlocked_ioctl = coreb_ioctl, + .llseek = noop_llseek, }; static struct miscdevice coreb_dev = { @@ -73,3 +74,4 @@ module_exit(bf561_coreb_exit); MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>"); MODULE_DESCRIPTION("BF561 Core B Support"); +MODULE_LICENSE("GPL"); diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h index 67d6bdcd3fa8..6c7dc58c018c 100644 --- a/arch/blackfin/mach-bf561/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h @@ -24,29 +24,16 @@ #define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() #define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) -#define SIC_IWR0 SICA_IWR0 -#define SIC_IWR1 SICA_IWR1 -#define SIC_IAR0 SICA_IAR0 -#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0 -#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1 -#define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0 -#define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1 - -#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0 -#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1 -#define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0 -#define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1 -#define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0 -#define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1 - -#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2)) -#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val) -#define bfin_read_SICB_IMASK(x) bfin_read32(SICB_IMASK0 + (x << 2)) -#define bfin_write_SICB_IMASK(x, val) bfin_write32((SICB_IMASK0 + (x << 2)), val) -#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2)) -#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val) -#define bfin_read_SICB_ISR(x) bfin_read32(SICB_ISR0 + (x << 2)) -#define bfin_write_SICB_ISR(x, val) bfin_write32((SICB_ISR0 + (x << 2)), val) +/* Weird muxer funcs which pick SIC regs from IMASK base */ +#define __SIC_MUX(base, x) ((base) + ((x) << 2)) +#define bfin_read_SIC_IMASK(x) bfin_read32(__SIC_MUX(SIC_IMASK0, x)) +#define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val) +#define bfin_read_SICB_IMASK(x) bfin_read32(__SIC_MUX(SICB_IMASK0, x)) +#define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val) +#define bfin_read_SIC_ISR(x) bfin_read32(__SIC_MUX(SIC_ISR0, x)) +#define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val) +#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x)) +#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val) #define BFIN_UART_NR_PORTS 1 diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h index 81ecdb71c6af..2bab99152495 100644 --- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h @@ -30,49 +30,41 @@ #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) #define bfin_read_CHIPID() bfin_read32(CHIPID) -/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ -#define bfin_read_SWRST() bfin_read_SICA_SWRST() -#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val) -#define bfin_read_SYSCR() bfin_read_SICA_SYSCR() -#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val) - /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ -#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) -#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val) -#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR) -#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR,val) -#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT) -#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT,val) -#define bfin_read_SICA_IMASK() bfin_read32(SICA_IMASK) -#define bfin_write_SICA_IMASK(val) bfin_write32(SICA_IMASK,val) -#define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0) -#define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0,val) -#define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1) -#define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1,val) -#define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0) -#define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0,val) -#define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1) -#define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1,val) -#define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2) -#define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2,val) -#define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3) -#define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3,val) -#define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4) -#define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4,val) -#define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5) -#define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5,val) -#define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6) -#define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6,val) -#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7) -#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7,val) -#define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0) -#define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0,val) -#define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1) -#define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1,val) -#define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0) -#define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0,val) -#define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1) -#define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1,val) +#define bfin_read_SWRST() bfin_read16(SWRST) +#define bfin_write_SWRST(val) bfin_write16(SWRST,val) +#define bfin_read_SYSCR() bfin_read16(SYSCR) +#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) +#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) +#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val) +#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) +#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val) +#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) +#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val) +#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) +#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val) +#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) +#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val) +#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) +#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val) +#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) +#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val) +#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) +#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4,val) +#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) +#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5,val) +#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) +#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6,val) +#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) +#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7,val) +#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) +#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0,val) +#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) +#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1,val) +#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) +#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val) +#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) +#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1,val) /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ #define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST) @@ -1534,54 +1526,4 @@ /* These need to be last due to the cdef/linux inter-dependencies */ #include <asm/irq.h> -/* Writing to PLL_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_PLL_CTL(unsigned int val) -{ - unsigned long flags, iwr0, iwr1; - - if (val == bfin_read_PLL_CTL()) - return; - - local_irq_save_hw(flags); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SICA_IWR0); - iwr1 = bfin_read32(SICA_IWR1); - /* Only allow PPL Wakeup) */ - bfin_write32(SICA_IWR0, IWR_ENABLE(0)); - bfin_write32(SICA_IWR1, 0); - - bfin_write16(PLL_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SICA_IWR0, iwr0); - bfin_write32(SICA_IWR1, iwr1); - local_irq_restore_hw(flags); -} - -/* Writing to VR_CTL initiates a PLL relock sequence. */ -static __inline__ void bfin_write_VR_CTL(unsigned int val) -{ - unsigned long flags, iwr0, iwr1; - - if (val == bfin_read_VR_CTL()) - return; - - local_irq_save_hw(flags); - /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SICA_IWR0); - iwr1 = bfin_read32(SICA_IWR1); - /* Only allow PPL Wakeup) */ - bfin_write32(SICA_IWR0, IWR_ENABLE(0)); - bfin_write32(SICA_IWR1, 0); - - bfin_write16(VR_CTL, val); - SSYNC(); - asm("IDLE;"); - - bfin_write32(SICA_IWR0, iwr0); - bfin_write32(SICA_IWR1, iwr1); - local_irq_restore_hw(flags); -} - #endif /* _CDEF_BF561_H */ diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h index 2674f0097576..79e048d452e0 100644 --- a/arch/blackfin/mach-bf561/include/mach/defBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h @@ -28,32 +28,29 @@ #define CHIPID 0xFFC00014 /* Chip ID Register */ /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ -#define SWRST SICA_SWRST -#define SYSCR SICA_SYSCR #define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A) #define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) #define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) #define RESET_SOFTWARE (SWRST_OCCURRED) /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ -#define SICA_SWRST 0xFFC00100 /* Software Reset register */ -#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */ -#define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ -#define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */ -#define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ -#define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ -#define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ -#define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ -#define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ -#define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ -#define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ -#define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ -#define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ -#define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ -#define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ -#define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ -#define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ -#define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */ +#define SWRST 0xFFC00100 /* Software Reset register */ +#define SYSCR 0xFFC00104 /* System Reset Configuration register */ +#define SIC_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ +#define SIC_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ +#define SIC_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ +#define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ +#define SIC_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ +#define SIC_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ +#define SIC_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ +#define SIC_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ +#define SIC_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ +#define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ +#define SIC_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ +#define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ +#define SIC_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */ /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ #define SICB_SWRST 0xFFC01100 /* reserved */ @@ -1271,63 +1268,6 @@ #define PF14_P 14 #define PF15_P 15 -/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */ - -/* SPI_CTL Masks */ -#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ -#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ -#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ -#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ -#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ -#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ -#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ -#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ -#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ -#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ -#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ -#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ - -/* SPI_FLG Masks */ -#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_FLG Bit Positions */ -#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_STAT Masks */ -#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ -#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */ -#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ -#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ -#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ -#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ -#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ - /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ /* AMGCTL Masks */ diff --git a/arch/blackfin/mach-bf561/include/mach/pll.h b/arch/blackfin/mach-bf561/include/mach/pll.h new file mode 100644 index 000000000000..f2b1fbdb8e72 --- /dev/null +++ b/arch/blackfin/mach-bf561/include/mach/pll.h @@ -0,0 +1,63 @@ +/* + * Copyright 2005-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _MACH_PLL_H +#define _MACH_PLL_H + +#include <asm/blackfin.h> +#include <asm/irqflags.h> + +/* Writing to PLL_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_PLL_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1; + + if (val == bfin_read_PLL_CTL()) + return; + + flags = hard_local_irq_save(); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SICA_IWR0); + iwr1 = bfin_read32(SICA_IWR1); + /* Only allow PPL Wakeup) */ + bfin_write32(SICA_IWR0, IWR_ENABLE(0)); + bfin_write32(SICA_IWR1, 0); + + bfin_write16(PLL_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SICA_IWR0, iwr0); + bfin_write32(SICA_IWR1, iwr1); + hard_local_irq_restore(flags); +} + +/* Writing to VR_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_VR_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1; + + if (val == bfin_read_VR_CTL()) + return; + + flags = hard_local_irq_save(); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SICA_IWR0); + iwr1 = bfin_read32(SICA_IWR1); + /* Only allow PPL Wakeup) */ + bfin_write32(SICA_IWR0, IWR_ENABLE(0)); + bfin_write32(SICA_IWR1, 0); + + bfin_write16(VR_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SICA_IWR0, iwr0); + bfin_write32(SICA_IWR1, iwr1); + hard_local_irq_restore(flags); +} + +#endif /* _MACH_PLL_H */ diff --git a/arch/blackfin/mach-bf561/ints-priority.c b/arch/blackfin/mach-bf561/ints-priority.c index b4424172ad9e..7ee9262fe132 100644 --- a/arch/blackfin/mach-bf561/ints-priority.c +++ b/arch/blackfin/mach-bf561/ints-priority.c @@ -13,7 +13,7 @@ void __init program_IAR(void) { /* Program the IAR0 Register with the configured priority */ - bfin_write_SICA_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | + bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | ((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) | ((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) | ((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) | @@ -22,7 +22,7 @@ void __init program_IAR(void) ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) | ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS)); - bfin_write_SICA_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) | + bfin_write_SIC_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) | ((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) | ((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) | ((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) | @@ -31,7 +31,7 @@ void __init program_IAR(void) ((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) | ((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS)); - bfin_write_SICA_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) | + bfin_write_SIC_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) | ((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) | ((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) | ((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) | @@ -40,7 +40,7 @@ void __init program_IAR(void) ((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) | ((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS)); - bfin_write_SICA_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) | + bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) | ((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) | ((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) | ((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) | @@ -49,7 +49,7 @@ void __init program_IAR(void) ((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) | ((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS)); - bfin_write_SICA_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) | + bfin_write_SIC_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) | ((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) | ((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) | ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | @@ -58,7 +58,7 @@ void __init program_IAR(void) ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) | ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS)); - bfin_write_SICA_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | + bfin_write_SIC_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) | ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) | ((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) | @@ -67,7 +67,7 @@ void __init program_IAR(void) ((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) | ((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS)); - bfin_write_SICA_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) | + bfin_write_SIC_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) | ((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) | ((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) | ((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) | @@ -76,7 +76,7 @@ void __init program_IAR(void) ((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) | ((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS)); - bfin_write_SICA_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) | + bfin_write_SIC_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) | ((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) | ((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) | ((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) | diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c index 3b9a4bf7dacc..f540ed1257d6 100644 --- a/arch/blackfin/mach-bf561/smp.c +++ b/arch/blackfin/mach-bf561/smp.c @@ -52,19 +52,19 @@ int __init setup_profiling_timer(unsigned int multiplier) /* not supported */ void __cpuinit platform_secondary_init(unsigned int cpu) { /* Clone setup for peripheral interrupt sources from CoreA. */ - bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0()); - bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1()); + bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0()); + bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1()); SSYNC(); /* Clone setup for IARs from CoreA. */ - bfin_write_SICB_IAR0(bfin_read_SICA_IAR0()); - bfin_write_SICB_IAR1(bfin_read_SICA_IAR1()); - bfin_write_SICB_IAR2(bfin_read_SICA_IAR2()); - bfin_write_SICB_IAR3(bfin_read_SICA_IAR3()); - bfin_write_SICB_IAR4(bfin_read_SICA_IAR4()); - bfin_write_SICB_IAR5(bfin_read_SICA_IAR5()); - bfin_write_SICB_IAR6(bfin_read_SICA_IAR6()); - bfin_write_SICB_IAR7(bfin_read_SICA_IAR7()); + bfin_write_SICB_IAR0(bfin_read_SIC_IAR0()); + bfin_write_SICB_IAR1(bfin_read_SIC_IAR1()); + bfin_write_SICB_IAR2(bfin_read_SIC_IAR2()); + bfin_write_SICB_IAR3(bfin_read_SIC_IAR3()); + bfin_write_SICB_IAR4(bfin_read_SIC_IAR4()); + bfin_write_SICB_IAR5(bfin_read_SIC_IAR5()); + bfin_write_SICB_IAR6(bfin_read_SIC_IAR6()); + bfin_write_SICB_IAR7(bfin_read_SIC_IAR7()); bfin_write_SICB_IWR0(IWR_DISABLE_ALL); bfin_write_SICB_IWR1(IWR_DISABLE_ALL); SSYNC(); @@ -86,12 +86,12 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle spin_lock(&boot_lock); - if ((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT) == 0) { + if ((bfin_read_SIC_SYSCR() & COREB_SRAM_INIT) == 0) { /* CoreB already running, sending ipi to wakeup it */ platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); } else { /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */ - bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT); + bfin_write_SIC_SYSCR(bfin_read_SIC_SYSCR() & ~COREB_SRAM_INIT); SSYNC(); } |