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-rw-r--r--arch/blackfin/mach-bf561/secondary.S7
-rw-r--r--arch/blackfin/mach-bf561/smp.c9
2 files changed, 6 insertions, 10 deletions
diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S
index 148e50764555..4c462838f4e1 100644
--- a/arch/blackfin/mach-bf561/secondary.S
+++ b/arch/blackfin/mach-bf561/secondary.S
@@ -13,7 +13,11 @@
#include <asm/asm-offsets.h>
#include <asm/trace.h>
-__INIT
+/*
+ * This code must come first as CoreB is hardcoded (in hardware)
+ * to start at the beginning of its L1 instruction memory.
+ */
+.section .l1.text.head
/* Lay the initial stack into the L1 scratch area of Core B */
#define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
@@ -160,7 +164,6 @@ ENTRY(_coreb_trampoline_start)
.LWAIT_HERE:
jump .LWAIT_HERE;
ENDPROC(_coreb_trampoline_start)
-ENTRY(_coreb_trampoline_end)
#ifdef CONFIG_HOTPLUG_CPU
.section ".text"
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index 1074a7ef81c7..82b94e137886 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -30,18 +30,11 @@ void __init platform_init_cpus(void)
void __init platform_prepare_cpus(unsigned int max_cpus)
{
- int len;
-
- len = &coreb_trampoline_end - &coreb_trampoline_start + 1;
- BUG_ON(len > L1_CODE_LENGTH);
-
- dma_memcpy((void *)COREB_L1_CODE_START, &coreb_trampoline_start, len);
+ bfin_relocate_coreb_l1_mem();
/* Both cores ought to be present on a bf561! */
cpu_set(0, cpu_present_map); /* CoreA */
cpu_set(1, cpu_present_map); /* CoreB */
-
- printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_L1_CODE_START);
}
int __init setup_profiling_timer(unsigned int multiplier) /* not supported */