diff options
Diffstat (limited to 'arch/blackfin/mach-bf538')
| -rw-r--r-- | arch/blackfin/mach-bf538/include/mach/cdefBF538.h | 64 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf538/include/mach/defBF539.h | 14 |
2 files changed, 7 insertions, 71 deletions
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h index 401ebd79d0aa..66aa722cf6c8 100644 --- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h +++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h @@ -1293,70 +1293,6 @@ #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) -#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV) -#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) -#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL) -#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val) -#define bfin_read_TWI0_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL) -#define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val) -#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) -#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) -#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) -#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) -#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL) -#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val) -#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) -#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) -#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) -#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) -#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT) -#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) -#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK) -#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) -#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL) -#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val) -#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) -#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) -#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) -#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) -#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) -#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) -#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) -#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) -#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) -#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) -#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) -#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) -#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) -#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) -#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL) -#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val) -#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) -#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) -#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) -#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) -#define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL) -#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val) -#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) -#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) -#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) -#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) -#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) -#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) -#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) -#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) -#define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL) -#define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val) -#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) -#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) -#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) -#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) -#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) -#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) -#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) -#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) -#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) -#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) #define bfin_read_CAN_MC1() bfin_read16(CAN_MC1) #define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val) #define bfin_read_CAN_MD1() bfin_read16(CAN_MD1) diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h index d7061d9f2a83..b674a1c4aef1 100644 --- a/arch/blackfin/mach-bf538/include/mach/defBF539.h +++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h @@ -442,15 +442,15 @@ /* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */ #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ #define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */ -#define TWI0_SLAVE_CTRL 0xFFC01408 /* Slave Mode Control Register */ +#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ #define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ #define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ -#define TWI0_MASTER_CTRL 0xFFC01414 /* Master Mode Control Register */ +#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ #define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ #define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ #define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */ #define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */ -#define TWI0_FIFO_CTRL 0xFFC01428 /* FIFO Control Register */ +#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ #define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ #define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ #define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ @@ -761,15 +761,15 @@ /* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */ #define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */ #define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */ -#define TWI1_SLAVE_CTRL 0xFFC02208 /* Slave Mode Control Register */ +#define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */ #define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */ #define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */ -#define TWI1_MASTER_CTRL 0xFFC02214 /* Master Mode Control Register */ +#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */ #define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */ #define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */ #define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */ #define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */ -#define TWI1_FIFO_CTRL 0xFFC02228 /* FIFO Control Register */ +#define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */ #define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */ #define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */ #define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */ @@ -2401,7 +2401,7 @@ #define XMTSERV 0x0040 /* Transmit FIFO Service */ #define RCVSERV 0x0080 /* Receive FIFO Service */ -/* TWIx_FIFO_CTRL Masks */ +/* TWIx_FIFO_CTL Masks */ #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ |