diff options
Diffstat (limited to 'arch/arm')
291 files changed, 18818 insertions, 20111 deletions
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index e255164ff087..a8fce3ccc707 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -625,7 +625,6 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)") .atag_offset = 0x100, .map_io = ams_delta_map_io, .init_early = omap1_init_early, - .reserve = omap_reserve, .init_irq = omap1_init_irq, .init_machine = ams_delta_init, .init_late = ams_delta_init_late, diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index 4b6de70c47a6..8b5800acf726 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c @@ -27,10 +27,10 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/tc.h> +#include <mach/tc.h> #include <mach/mux.h> #include <mach/flash.h> -#include <plat/fpga.h> +#include <../plat-omap/fpga.h> #include <linux/platform_data/keypad-omap.h> #include <mach/hardware.h> @@ -123,9 +123,9 @@ static struct resource smc91x_resources[] = { static void __init fsample_init_smc91x(void) { - fpga_write(1, H2P2_DBG_FPGA_LAN_RESET); + __raw_writeb(1, H2P2_DBG_FPGA_LAN_RESET); mdelay(50); - fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1, + __raw_writeb(__raw_readb(H2P2_DBG_FPGA_LAN_RESET) & ~1, H2P2_DBG_FPGA_LAN_RESET); mdelay(50); } @@ -362,7 +362,6 @@ MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample") .atag_offset = 0x100, .map_io = omap_fsample_map_io, .init_early = omap1_init_early, - .reserve = omap_reserve, .init_irq = omap1_init_irq, .init_machine = omap_fsample_init, .init_late = omap1_init_late, diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c index 4ec579fdd366..608e7d2a2778 100644 --- a/arch/arm/mach-omap1/board-generic.c +++ b/arch/arm/mach-omap1/board-generic.c @@ -81,7 +81,6 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710") .atag_offset = 0x100, .map_io = omap16xx_map_io, .init_early = omap1_init_early, - .reserve = omap_reserve, .init_irq = omap1_init_irq, .init_machine = omap_generic_init, .init_late = omap1_init_late, diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c index e1362ce48497..7119ef28e0ad 100644 --- a/arch/arm/mach-omap1/board-h2-mmc.c +++ b/arch/arm/mach-omap1/board-h2-mmc.c @@ -13,12 +13,11 @@ */ #include <linux/gpio.h> #include <linux/platform_device.h> - +#include <linux/platform_data/gpio-omap.h> #include <linux/i2c/tps65010.h> -#include <plat/mmc.h> - #include "board-h2.h" +#include "mmc.h" #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index 376f7f29ef77..9134b646f01b 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -39,8 +39,8 @@ #include <asm/mach/map.h> #include <mach/mux.h> -#include <plat/dma.h> -#include <plat/tc.h> +#include <plat-omap/dma-omap.h> +#include <mach/tc.h> #include <mach/irda.h> #include <linux/platform_data/keypad-omap.h> #include <mach/flash.h> @@ -50,6 +50,7 @@ #include "common.h" #include "board-h2.h" +#include "dma.h" /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ #define OMAP1610_ETHR_START 0x04000300 @@ -458,7 +459,6 @@ MACHINE_START(OMAP_H2, "TI-H2") .atag_offset = 0x100, .map_io = omap16xx_map_io, .init_early = omap1_init_early, - .reserve = omap_reserve, .init_irq = omap1_init_irq, .init_machine = h2_init, .init_late = omap1_init_late, diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c index c74daace8cd6..17d77914d769 100644 --- a/arch/arm/mach-omap1/board-h3-mmc.c +++ b/arch/arm/mach-omap1/board-h3-mmc.c @@ -16,9 +16,8 @@ #include <linux/i2c/tps65010.h> -#include <plat/mmc.h> - #include "board-h3.h" +#include "mmc.h" #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index ededdb7ef28c..bf213d1d8075 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -41,9 +41,9 @@ #include <asm/mach/map.h> #include <mach/mux.h> -#include <plat/tc.h> +#include <mach/tc.h> #include <linux/platform_data/keypad-omap.h> -#include <plat/dma.h> +#include <plat-omap/dma-omap.h> #include <mach/flash.h> #include <mach/hardware.h> @@ -452,7 +452,6 @@ MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board") .atag_offset = 0x100, .map_io = omap16xx_map_io, .init_early = omap1_init_early, - .reserve = omap_reserve, .init_irq = omap1_init_irq, .init_machine = h3_init, .init_late = omap1_init_late, diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index 87ab2086ef96..356f816c84a6 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -43,7 +43,7 @@ #include <asm/mach/arch.h> #include <mach/omap7xx.h> -#include <plat/mmc.h> +#include "mmc.h" #include <mach/irqs.h> #include <mach/usb.h> @@ -600,7 +600,6 @@ MACHINE_START(HERALD, "HTC Herald") .atag_offset = 0x100, .map_io = htcherald_map_io, .init_early = omap1_init_early, - .reserve = omap_reserve, .init_irq = omap1_init_irq, .init_machine = htcherald_init, .init_late = omap1_init_late, diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index db5f7d2976e7..c66334f22471 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c @@ -33,16 +33,16 @@ #include <mach/mux.h> #include <mach/flash.h> -#include <plat/fpga.h> -#include <plat/tc.h> +#include <../plat-omap/fpga.h> +#include <mach/tc.h> #include <linux/platform_data/keypad-omap.h> -#include <plat/mmc.h> #include <mach/hardware.h> #include <mach/usb.h> #include "iomap.h" #include "common.h" +#include "mmc.h" /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ #define INNOVATOR1610_ETHR_START 0x04000300 @@ -215,7 +215,7 @@ static struct platform_device *innovator1510_devices[] __initdata = { static int innovator_get_pendown_state(void) { - return !(fpga_read(OMAP1510_FPGA_TOUCHSCREEN) & (1 << 5)); + return !(__raw_readb(OMAP1510_FPGA_TOUCHSCREEN) & (1 << 5)); } static const struct ads7846_platform_data innovator1510_ts_info = { @@ -279,7 +279,7 @@ static struct platform_device *innovator1610_devices[] __initdata = { static void __init innovator_init_smc91x(void) { if (cpu_is_omap1510()) { - fpga_write(fpga_read(OMAP1510_FPGA_RST) & ~1, + __raw_writeb(__raw_readb(OMAP1510_FPGA_RST) & ~1, OMAP1510_FPGA_RST); udelay(750); } else { @@ -335,10 +335,10 @@ static int mmc_set_power(struct device *dev, int slot, int power_on, int vdd) { if (power_on) - fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3), + __raw_writeb(__raw_readb(OMAP1510_FPGA_POWER) | (1 << 3), OMAP1510_FPGA_POWER); else - fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3), + __raw_writeb(__raw_readb(OMAP1510_FPGA_POWER) & ~(1 << 3), OMAP1510_FPGA_POWER); return 0; @@ -390,14 +390,14 @@ static void __init innovator_init(void) omap_cfg_reg(UART3_TX); omap_cfg_reg(UART3_RX); - reg = fpga_read(OMAP1510_FPGA_POWER); + reg = __raw_readb(OMAP1510_FPGA_POWER); reg |= OMAP1510_FPGA_PCR_COM1_EN; - fpga_write(reg, OMAP1510_FPGA_POWER); + __raw_writeb(reg, OMAP1510_FPGA_POWER); udelay(10); - reg = fpga_read(OMAP1510_FPGA_POWER); + reg = __raw_readb(OMAP1510_FPGA_POWER); reg |= OMAP1510_FPGA_PCR_COM2_EN; - fpga_write(reg, OMAP1510_FPGA_POWER); + __raw_writeb(reg, OMAP1510_FPGA_POWER); udelay(10); platform_add_devices(innovator1510_devices, ARRAY_SIZE(innovator1510_devices)); @@ -437,6 +437,7 @@ static void __init innovator_init(void) */ static void __init innovator_map_io(void) { +#ifdef CONFIG_ARCH_OMAP15XX omap15xx_map_io(); iotable_init(innovator1510_io_desc, ARRAY_SIZE(innovator1510_io_desc)); @@ -444,9 +445,10 @@ static void __init innovator_map_io(void) /* Dump the Innovator FPGA rev early - useful info for support. */ pr_debug("Innovator FPGA Rev %d.%d Board Rev %d\n", - fpga_read(OMAP1510_FPGA_REV_HIGH), - fpga_read(OMAP1510_FPGA_REV_LOW), - fpga_read(OMAP1510_FPGA_BOARD_REV)); + __raw_readb(OMAP1510_FPGA_REV_HIGH), + __raw_readb(OMAP1510_FPGA_REV_LOW), + __raw_readb(OMAP1510_FPGA_BOARD_REV)); +#endif } MACHINE_START(OMAP_INNOVATOR, "TI-Innovator") @@ -454,7 +456,6 @@ MACHINE_START(OMAP_INNOVATOR, "TI-Innovator") .atag_offset = 0x100, .map_io = innovator_map_io, .init_early = omap1_init_early, - .reserve = omap_reserve, .init_irq = omap1_init_irq, .init_machine = innovator_init, .init_late = omap1_init_late, diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 7d5c06d6a52a..3e8ead67e459 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -29,13 +29,13 @@ #include <asm/mach/map.h> #include <mach/mux.h> -#include <plat/mmc.h> -#include <plat/clock.h> #include <mach/hardware.h> #include <mach/usb.h> #include "common.h" +#include "clock.h" +#include "mmc.h" #define ADS7846_PENDOWN_GPIO 15 @@ -251,7 +251,6 @@ MACHINE_START(NOKIA770, "Nokia 770") .atag_offset = 0x100, .map_io = omap16xx_map_io, .init_early = omap1_init_early, - .reserve = omap_reserve, .init_irq = omap1_init_irq, .init_machine = omap_nokia770_init, .init_late = omap1_init_late, diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 5973945a8741..872ea47cd28a 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -48,7 +48,7 @@ #include <mach/flash.h> #include <mach/mux.h> -#include <plat/tc.h> +#include <mach/tc.h> #include <mach/hardware.h> #include <mach/usb.h> @@ -606,7 +606,6 @@ MACHINE_START(OMAP_OSK, "TI-OSK") .atag_offset = 0x100, .map_io = omap16xx_map_io, .init_early = omap1_init_early, - .reserve = omap_reserve, .init_irq = omap1_init_irq, .init_machine = osk_init, .init_late = omap1_init_late, diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 1c578d58923a..584b6fab894b 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -36,8 +36,8 @@ #include <mach/flash.h> #include <mach/mux.h> -#include <plat/tc.h> -#include <plat/dma.h> +#include <mach/tc.h> +#include <plat-omap/dma-omap.h> #include <mach/irda.h> #include <linux/platform_data/keypad-omap.h> @@ -45,6 +45,7 @@ #include <mach/usb.h> #include "common.h" +#include "dma.h" #define PALMTE_USBDETECT_GPIO 0 #define PALMTE_USB_OR_DC_GPIO 1 @@ -264,7 +265,6 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E") .atag_offset = 0x100, .map_io = omap15xx_map_io, .init_early = omap1_init_early, - .reserve = omap_reserve, .init_irq = omap1_init_irq, .init_machine = omap_palmte_init, .init_late = omap1_init_late, diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index 97158095083c..fbc986bfe69e 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c @@ -28,16 +28,16 @@ #include <linux/spi/spi.h> #include <linux/spi/ads7846.h> #include <linux/platform_data/omap1_bl.h> +#include <linux/platform_data/leds-omap.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/led.h> #include <mach/flash.h> #include <mach/mux.h> -#include <plat/dma.h> -#include <plat/tc.h> +#include <plat-omap/dma-omap.h> +#include <mach/tc.h> #include <mach/irda.h> #include <linux/platform_data/keypad-omap.h> @@ -45,6 +45,7 @@ #include <mach/usb.h> #include "common.h" +#include "dma.h" #define PALMTT_USBDETECT_GPIO 0 #define PALMTT_CABLE_GPIO 1 @@ -310,7 +311,6 @@ MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T") .atag_offset = 0x100, .map_io = omap15xx_map_io, .init_early = omap1_init_early, - .reserve = omap_reserve, .init_irq = omap1_init_irq, .init_machine = omap_palmtt_init, .init_late = omap1_init_late, diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index e311032e7eeb..60d917a93763 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -38,8 +38,8 @@ #include <mach/flash.h> #include <mach/mux.h> -#include <plat/dma.h> -#include <plat/tc.h> +#include <plat-omap/dma-omap.h> +#include <mach/tc.h> #include <mach/irda.h> #include <linux/platform_data/keypad-omap.h> @@ -47,6 +47,7 @@ #include <mach/usb.h> #include "common.h" +#include "dma.h" #define PALMZ71_USBDETECT_GPIO 0 #define PALMZ71_PENIRQ_GPIO 6 @@ -326,7 +327,6 @@ MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71") .atag_offset = 0x100, .map_io = omap15xx_map_io, .init_early = omap1_init_early, - .reserve = omap_reserve, .init_irq = omap1_init_irq, .init_machine = omap_palmz71_init, .init_late = omap1_init_late, diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index 198b05417bfc..030bd48727be 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c @@ -28,9 +28,9 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/tc.h> +#include <mach/tc.h> #include <mach/mux.h> -#include <plat/fpga.h> +#include <../plat-omap/fpga.h> #include <mach/flash.h> #include <mach/hardware.h> @@ -231,9 +231,9 @@ static struct omap_lcd_config perseus2_lcd_config __initdata = { static void __init perseus2_init_smc91x(void) { - fpga_write(1, H2P2_DBG_FPGA_LAN_RESET); + __raw_writeb(1, H2P2_DBG_FPGA_LAN_RESET); mdelay(50); - fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1, + __raw_writeb(__raw_readb(H2P2_DBG_FPGA_LAN_RESET) & ~1, H2P2_DBG_FPGA_LAN_RESET); mdelay(50); } @@ -324,7 +324,6 @@ MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2") .atag_offset = 0x100, .map_io = omap_perseus2_map_io, .init_early = omap1_init_early, - .reserve = omap_reserve, .init_irq = omap1_init_irq, .init_machine = omap_perseus2_init, .init_late = omap1_init_late, diff --git a/arch/arm/mach-omap1/board-sx1-mmc.c b/arch/arm/mach-omap1/board-sx1-mmc.c index 5932d56e17bf..4fcf19c78a08 100644 --- a/arch/arm/mach-omap1/board-sx1-mmc.c +++ b/arch/arm/mach-omap1/board-sx1-mmc.c @@ -16,9 +16,10 @@ #include <linux/platform_device.h> #include <mach/hardware.h> -#include <plat/mmc.h> #include <mach/board-sx1.h> +#include "mmc.h" + #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) static int mmc_set_power(struct device *dev, int slot, int power_on, diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 13bf2cc56814..1ebc7e08d6e5 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c @@ -36,15 +36,16 @@ #include <mach/flash.h> #include <mach/mux.h> -#include <plat/dma.h> +#include <plat-omap/dma-omap.h> #include <mach/irda.h> -#include <plat/tc.h> +#include <mach/tc.h> #include <mach/board-sx1.h> #include <mach/hardware.h> #include <mach/usb.h> #include "common.h" +#include "dma.h" /* Write to I2C device */ int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value) @@ -403,7 +404,6 @@ MACHINE_START(SX1, "OMAP310 based Siemens SX1") .atag_offset = 0x100, .map_io = omap15xx_map_io, .init_early = omap1_init_early, - .reserve = omap_reserve, .init_irq = omap1_init_irq, .init_machine = omap_sx1_init, .init_late = omap1_init_late, diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index ad75e3411d46..abf705f49b19 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -34,7 +34,7 @@ #include <mach/board-voiceblue.h> #include <mach/flash.h> #include <mach/mux.h> -#include <plat/tc.h> +#include <mach/tc.h> #include <mach/hardware.h> #include <mach/usb.h> @@ -286,7 +286,6 @@ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910") .atag_offset = 0x100, .map_io = omap15xx_map_io, .init_early = omap1_init_early, - .reserve = omap_reserve, .init_irq = omap1_init_irq, .init_machine = voiceblue_init, .init_late = omap1_init_late, diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 638f4070fc70..931f3f6d396b 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -12,6 +12,7 @@ * published by the Free Software Foundation. */ #include <linux/kernel.h> +#include <linux/export.h> #include <linux/list.h> #include <linux/errno.h> #include <linux/err.h> @@ -21,14 +22,11 @@ #include <asm/mach-types.h> -#include <plat/cpu.h> -#include <plat/usb.h> -#include <plat/clock.h> -#include <plat/sram.h> -#include <plat/clkdev_omap.h> - #include <mach/hardware.h> +#include "../plat-omap/sram.h" + +#include "soc.h" #include "iomap.h" #include "clock.h" #include "opp.h" @@ -36,6 +34,10 @@ __u32 arm_idlect1_mask; struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; +static LIST_HEAD(clocks); +static DEFINE_MUTEX(clocks_mutex); +static DEFINE_SPINLOCK(clockfw_lock); + /* * Omap1 specific clock functions */ @@ -607,3 +609,497 @@ void omap1_clk_disable_unused(struct clk *clk) } #endif + + +int clk_enable(struct clk *clk) +{ + unsigned long flags; + int ret; + + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + spin_lock_irqsave(&clockfw_lock, flags); + ret = omap1_clk_enable(clk); + spin_unlock_irqrestore(&clockfw_lock, flags); + + return ret; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ + unsigned long flags; + + if (clk == NULL || IS_ERR(clk)) + return; + + spin_lock_irqsave(&clockfw_lock, flags); + if (clk->usecount == 0) { + pr_err("Trying disable clock %s with 0 usecount\n", + clk->name); + WARN_ON(1); + goto out; + } + + omap1_clk_disable(clk); + +out: + spin_unlock_irqrestore(&clockfw_lock, flags); +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + unsigned long flags; + unsigned long ret; + + if (clk == NULL || IS_ERR(clk)) + return 0; + + spin_lock_irqsave(&clockfw_lock, flags); + ret = clk->rate; + spin_unlock_irqrestore(&clockfw_lock, flags); + + return ret; +} +EXPORT_SYMBOL(clk_get_rate); + +/* + * Optional clock functions defined in include/linux/clk.h + */ + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long flags; + long ret; + + if (clk == NULL || IS_ERR(clk)) + return 0; + + spin_lock_irqsave(&clockfw_lock, flags); + ret = omap1_clk_round_rate(clk, rate); + spin_unlock_irqrestore(&clockfw_lock, flags); + + return ret; +} +EXPORT_SYMBOL(clk_round_rate); + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long flags; + int ret = -EINVAL; + + if (clk == NULL || IS_ERR(clk)) + return ret; + + spin_lock_irqsave(&clockfw_lock, flags); + ret = omap1_clk_set_rate(clk, rate); + if (ret == 0) + propagate_rate(clk); + spin_unlock_irqrestore(&clockfw_lock, flags); + + return ret; +} +EXPORT_SYMBOL(clk_set_rate); + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + WARN_ONCE(1, "clk_set_parent() not implemented for OMAP1\n"); + + return -EINVAL; +} +EXPORT_SYMBOL(clk_set_parent); + +struct clk *clk_get_parent(struct clk *clk) +{ + return clk->parent; +} +EXPORT_SYMBOL(clk_get_parent); + +/* + * OMAP specific clock functions shared between omap1 and omap2 + */ + +int __initdata mpurate; + +/* + * By default we use the rate set by the bootloader. + * You can override this with mpurate= cmdline option. + */ +static int __init omap_clk_setup(char *str) +{ + get_option(&str, &mpurate); + + if (!mpurate) + return 1; + + if (mpurate < 1000) + mpurate *= 1000000; + + return 1; +} +__setup("mpurate=", omap_clk_setup); + +/* Used for clocks that always have same value as the parent clock */ +unsigned long followparent_recalc(struct clk *clk) +{ + return clk->parent->rate; +} + +/* + * Used for clocks that have the same value as the parent clock, + * divided by some factor + */ +unsigned long omap_fixed_divisor_recalc(struct clk *clk) +{ + WARN_ON(!clk->fixed_div); + + return clk->parent->rate / clk->fixed_div; +} + +void clk_reparent(struct clk *child, struct clk *parent) +{ + list_del_init(&child->sibling); + if (parent) + list_add(&child->sibling, &parent->children); + child->parent = parent; + + /* now do the debugfs renaming to reattach the child + to the proper parent */ +} + +/* Propagate rate to children */ +void propagate_rate(struct clk *tclk) +{ + struct clk *clkp; + + list_for_each_entry(clkp, &tclk->children, sibling) { + if (clkp->recalc) + clkp->rate = clkp->recalc(clkp); + propagate_rate(clkp); + } +} + +static LIST_HEAD(root_clks); + +/** + * recalculate_root_clocks - recalculate and propagate all root clocks + * + * Recalculates all root clocks (clocks with no parent), which if the + * clock's .recalc is set correctly, should also propagate their rates. + * Called at init. + */ +void recalculate_root_clocks(void) +{ + struct clk *clkp; + + list_for_each_entry(clkp, &root_clks, sibling) { + if (clkp->recalc) + clkp->rate = clkp->recalc(clkp); + propagate_rate(clkp); + } +} + +/** + * clk_preinit - initialize any fields in the struct clk before clk init + * @clk: struct clk * to initialize + * + * Initialize any struct clk fields needed before normal clk initialization + * can run. No return value. + */ +void clk_preinit(struct clk *clk) +{ + INIT_LIST_HEAD(&clk->children); +} + +int clk_register(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + /* + * trap out already registered clocks + */ + if (clk->node.next || clk->node.prev) + return 0; + + mutex_lock(&clocks_mutex); + if (clk->parent) + list_add(&clk->sibling, &clk->parent->children); + else + list_add(&clk->sibling, &root_clks); + + list_add(&clk->node, &clocks); + if (clk->init) + clk->init(clk); + mutex_unlock(&clocks_mutex); + + return 0; +} +EXPORT_SYMBOL(clk_register); + +void clk_unregister(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return; + + mutex_lock(&clocks_mutex); + list_del(&clk->sibling); + list_del(&clk->node); + mutex_unlock(&clocks_mutex); +} +EXPORT_SYMBOL(clk_unregister); + +void clk_enable_init_clocks(void) +{ + struct clk *clkp; + + list_for_each_entry(clkp, &clocks, node) + if (clkp->flags & ENABLE_ON_INIT) + clk_enable(clkp); +} + +/** + * omap_clk_get_by_name - locate OMAP struct clk by its name + * @name: name of the struct clk to locate + * + * Locate an OMAP struct clk by its name. Assumes that struct clk + * names are unique. Returns NULL if not found or a pointer to the + * struct clk if found. + */ +struct clk *omap_clk_get_by_name(const char *name) +{ + struct clk *c; + struct clk *ret = NULL; + + mutex_lock(&clocks_mutex); + + list_for_each_entry(c, &clocks, node) { + if (!strcmp(c->name, name)) { + ret = c; + break; + } + } + + mutex_unlock(&clocks_mutex); + + return ret; +} + +int omap_clk_enable_autoidle_all(void) +{ + struct clk *c; + unsigned long flags; + + spin_lock_irqsave(&clockfw_lock, flags); + + list_for_each_entry(c, &clocks, node) + if (c->ops->allow_idle) + c->ops->allow_idle(c); + + spin_unlock_irqrestore(&clockfw_lock, flags); + + return 0; +} + +int omap_clk_disable_autoidle_all(void) +{ + struct clk *c; + unsigned long flags; + + spin_lock_irqsave(&clockfw_lock, flags); + + list_for_each_entry(c, &clocks, node) + if (c->ops->deny_idle) + c->ops->deny_idle(c); + + spin_unlock_irqrestore(&clockfw_lock, flags); + + return 0; +} + +/* + * Low level helpers + */ +static int clkll_enable_null(struct clk *clk) +{ + return 0; +} + +static void clkll_disable_null(struct clk *clk) +{ +} + +const struct clkops clkops_null = { + .enable = clkll_enable_null, + .disable = clkll_disable_null, +}; + +/* + * Dummy clock + * + * Used for clock aliases that are needed on some OMAPs, but not others + */ +struct clk dummy_ck = { + .name = "dummy", + .ops = &clkops_null, +}; + +/* + * + */ + +#ifdef CONFIG_OMAP_RESET_CLOCKS +/* + * Disable any unused clocks left on by the bootloader + */ +static int __init clk_disable_unused(void) +{ + struct clk *ck; + unsigned long flags; + + pr_info("clock: disabling unused clocks to save power\n"); + + spin_lock_irqsave(&clockfw_lock, flags); + list_for_each_entry(ck, &clocks, node) { + if (ck->ops == &clkops_null) + continue; + + if (ck->usecount > 0 || !ck->enable_reg) + continue; + + omap1_clk_disable_unused(ck); + } + spin_unlock_irqrestore(&clockfw_lock, flags); + + return 0; +} +late_initcall(clk_disable_unused); +late_initcall(omap_clk_enable_autoidle_all); +#endif + +#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) +/* + * debugfs support to trace clock tree hierarchy and attributes + */ + +#include <linux/debugfs.h> +#include <linux/seq_file.h> + +static struct dentry *clk_debugfs_root; + +static int clk_dbg_show_summary(struct seq_file *s, void *unused) +{ + struct clk *c; + struct clk *pa; + + mutex_lock(&clocks_mutex); + seq_printf(s, "%-30s %-30s %-10s %s\n", + "clock-name", "parent-name", "rate", "use-count"); + + list_for_each_entry(c, &clocks, node) { + pa = c->parent; + seq_printf(s, "%-30s %-30s %-10lu %d\n", + c->name, pa ? pa->name : "none", c->rate, + c->usecount); + } + mutex_unlock(&clocks_mutex); + + return 0; +} + +static int clk_dbg_open(struct inode *inode, struct file *file) +{ + return single_open(file, clk_dbg_show_summary, inode->i_private); +} + +static const struct file_operations debug_clock_fops = { + .open = clk_dbg_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int clk_debugfs_register_one(struct clk *c) +{ + int err; + struct dentry *d; + struct clk *pa = c->parent; + + d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root); + if (!d) + return -ENOMEM; + c->dent = d; + + d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount); + if (!d) { + err = -ENOMEM; + goto err_out; + } + d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate); + if (!d) { + err = -ENOMEM; + goto err_out; + } + d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags); + if (!d) { + err = -ENOMEM; + goto err_out; + } + return 0; + +err_out: + debugfs_remove_recursive(c->dent); + return err; +} + +static int clk_debugfs_register(struct clk *c) +{ + int err; + struct clk *pa = c->parent; + + if (pa && !pa->dent) { + err = clk_debugfs_register(pa); + if (err) + return err; + } + + if (!c->dent) { + err = clk_debugfs_register_one(c); + if (err) + return err; + } + return 0; +} + +static int __init clk_debugfs_init(void) +{ + struct clk *c; + struct dentry *d; + int err; + + d = debugfs_create_dir("clock", NULL); + if (!d) + return -ENOMEM; + clk_debugfs_root = d; + + list_for_each_entry(c, &clocks, node) { + err = clk_debugfs_register(c); + if (err) + goto err_out; + } + + d = debugfs_create_file("summary", S_IRUGO, + d, NULL, &debug_clock_fops); + if (!d) + return -ENOMEM; + + return 0; +err_out: + debugfs_remove_recursive(clk_debugfs_root); + return err; +} +late_initcall(clk_debugfs_init); + +#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */ diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index 3d04f4f67676..1e4918a3a5ee 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h @@ -14,8 +14,184 @@ #define __ARCH_ARM_MACH_OMAP1_CLOCK_H #include <linux/clk.h> +#include <linux/list.h> -#include <plat/clock.h> +#include <linux/clkdev.h> + +struct module; +struct clk; + +struct omap_clk { + u16 cpu; + struct clk_lookup lk; +}; + +#define CLK(dev, con, ck, cp) \ + { \ + .cpu = cp, \ + .lk = { \ + .dev_id = dev, \ + .con_id = con, \ + .clk = ck, \ + }, \ + } + +/* Platform flags for the clkdev-OMAP integration code */ +#define CK_310 (1 << 0) +#define CK_7XX (1 << 1) /* 7xx, 850 */ +#define CK_1510 (1 << 2) +#define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */ +#define CK_1710 (1 << 4) /* 1710 extra for rate selection */ + + +/* Temporary, needed during the common clock framework conversion */ +#define __clk_get_name(clk) (clk->name) +#define __clk_get_parent(clk) (clk->parent) +#define __clk_get_rate(clk) (clk->rate) + +/** + * struct clkops - some clock function pointers + * @enable: fn ptr that enables the current clock in hardware + * @disable: fn ptr that enables the current clock in hardware + * @find_idlest: function returning the IDLEST register for the clock's IP blk + * @find_companion: function returning the "companion" clk reg for the clock + * @allow_idle: fn ptr that enables autoidle for the current clock in hardware + * @deny_idle: fn ptr that disables autoidle for the current clock in hardware + * + * A "companion" clk is an accompanying clock to the one being queried + * that must be enabled for the IP module connected to the clock to + * become accessible by the hardware. Neither @find_idlest nor + * @find_companion should be needed; that information is IP + * block-specific; the hwmod code has been created to handle this, but + * until hwmod data is ready and drivers have been converted to use PM + * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and + * @find_companion must, unfortunately, remain. + */ +struct clkops { + int (*enable)(struct clk *); + void (*disable)(struct clk *); + void (*find_idlest)(struct clk *, void __iomem **, + u8 *, u8 *); + void (*find_companion)(struct clk *, void __iomem **, + u8 *); + void (*allow_idle)(struct clk *); + void (*deny_idle)(struct clk *); +}; + +/* + * struct clk.flags possibilities + * + * XXX document the rest of the clock flags here + * + * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL + * bits share the same register. This flag allows the + * omap4_dpllmx*() code to determine which GATE_CTRL bit field + * should be used. This is a temporary solution - a better approach + * would be to associate clock type-specific data with the clock, + * similar to the struct dpll_data approach. + */ +#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ +#define CLOCK_IDLE_CONTROL (1 << 1) +#define CLOCK_NO_IDLE_PARENT (1 << 2) +#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ +#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ +#define CLOCK_CLKOUTX2 (1 << 5) + +/** + * struct clk - OMAP struct clk + * @node: list_head connecting this clock into the full clock list + * @ops: struct clkops * for this clock + * @name: the name of the clock in the hardware (used in hwmod data and debug) + * @parent: pointer to this clock's parent struct clk + * @children: list_head connecting to the child clks' @sibling list_heads + * @sibling: list_head connecting this clk to its parent clk's @children + * @rate: current clock rate + * @enable_reg: register to write to enable the clock (see @enable_bit) + * @recalc: fn ptr that returns the clock's current rate + * @set_rate: fn ptr that can change the clock's current rate + * @round_rate: fn ptr that can round the clock's current rate + * @init: fn ptr to do clock-specific initialization + * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) + * @usecount: number of users that have requested this clock to be enabled + * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div + * @flags: see "struct clk.flags possibilities" above + * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) + * @src_offset: bitshift for source selection bitfield (OMAP1 only) + * + * XXX @rate_offset, @src_offset should probably be removed and OMAP1 + * clock code converted to use clksel. + * + * XXX @usecount is poorly named. It should be "enable_count" or + * something similar. "users" in the description refers to kernel + * code (core code or drivers) that have called clk_enable() and not + * yet called clk_disable(); the usecount of parent clocks is also + * incremented by the clock code when clk_enable() is called on child + * clocks and decremented by the clock code when clk_disable() is + * called on child clocks. + * + * XXX @clkdm, @usecount, @children, @sibling should be marked for + * internal use only. + * + * @children and @sibling are used to optimize parent-to-child clock + * tree traversals. (child-to-parent traversals use @parent.) + * + * XXX The notion of the clock's current rate probably needs to be + * separated from the clock's target rate. + */ +struct clk { + struct list_head node; + const struct clkops *ops; + const char *name; + struct clk *parent; + struct list_head children; + struct list_head sibling; /* node for children */ + unsigned long rate; + void __iomem *enable_reg; + unsigned long (*recalc)(struct clk *); + int (*set_rate)(struct clk *, unsigned long); + long (*round_rate)(struct clk *, unsigned long); + void (*init)(struct clk *); + u8 enable_bit; + s8 usecount; + u8 fixed_div; + u8 flags; + u8 rate_offset; + u8 src_offset; +#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) + struct dentry *dent; /* For visible tree hierarchy */ +#endif +}; + +struct clk_functions { + int (*clk_enable)(struct clk *clk); + void (*clk_disable)(struct clk *clk); + long (*clk_round_rate)(struct clk *clk, unsigned long rate); + int (*clk_set_rate)(struct clk *clk, unsigned long rate); + int (*clk_set_parent)(struct clk *clk, struct clk *parent); + void (*clk_allow_idle)(struct clk *clk); + void (*clk_deny_idle)(struct clk *clk); + void (*clk_disable_unused)(struct clk *clk); +}; + +extern int mpurate; + +extern int clk_init(struct clk_functions *custom_clocks); +extern void clk_preinit(struct clk *clk); +extern int clk_register(struct clk *clk); +extern void clk_reparent(struct clk *child, struct clk *parent); +extern void clk_unregister(struct clk *clk); +extern void propagate_rate(struct clk *clk); +extern void recalculate_root_clocks(void); +extern unsigned long followparent_recalc(struct clk *clk); +extern void clk_enable_init_clocks(void); +unsigned long omap_fixed_divisor_recalc(struct clk *clk); +extern struct clk *omap_clk_get_by_name(const char *name); +extern int omap_clk_enable_autoidle_all(void); +extern int omap_clk_disable_autoidle_all(void); + +extern const struct clkops clkops_null; + +extern struct clk dummy_ck; int omap1_clk_init(void); void omap1_clk_late_init(void); diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index 9b45f4b0ee22..28aea55a412e 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -22,14 +22,13 @@ #include <asm/mach-types.h> /* for machine_is_* */ -#include <plat/clock.h> -#include <plat/cpu.h> -#include <plat/clkdev_omap.h> -#include <plat/sram.h> /* for omap_sram_reprogram_clock() */ +#include "soc.h" #include <mach/hardware.h> #include <mach/usb.h> /* for OTG_BASE */ +#include "../plat-omap/sram.h" + #include "iomap.h" #include "clock.h" @@ -765,14 +764,6 @@ static struct omap_clk omap_clks[] = { * init */ -static struct clk_functions omap1_clk_functions = { - .clk_enable = omap1_clk_enable, - .clk_disable = omap1_clk_disable, - .clk_round_rate = omap1_clk_round_rate, - .clk_set_rate = omap1_clk_set_rate, - .clk_disable_unused = omap1_clk_disable_unused, -}; - static void __init omap1_show_rates(void) { pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", @@ -803,8 +794,6 @@ int __init omap1_clk_init(void) if (!cpu_is_omap15xx()) omap_writew(0, SOFT_REQ_REG2); - clk_init(&omap1_clk_functions); - /* By default all idlect1 clocks are allowed to idle */ arm_idlect1_mask = ~0; diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h index c2552b24f9f2..ecd0bb664dad 100644 --- a/arch/arm/mach-omap1/common.h +++ b/arch/arm/mach-omap1/common.h @@ -26,8 +26,11 @@ #ifndef __ARCH_ARM_MACH_OMAP1_COMMON_H #define __ARCH_ARM_MACH_OMAP1_COMMON_H -#include <plat/common.h> +#include "../plat-omap/common.h" #include <linux/mtd/mtd.h> +#include <linux/i2c-omap.h> + +#include "../plat-omap/i2c.h" #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) void omap7xx_map_io(void); @@ -38,6 +41,7 @@ static inline void omap7xx_map_io(void) #endif #ifdef CONFIG_ARCH_OMAP15XX +void omap1510_fpga_init_irq(void); void omap15xx_map_io(void); #else static inline void omap15xx_map_io(void) @@ -90,4 +94,6 @@ extern int ocpi_enable(void); static inline int ocpi_enable(void) { return 0; } #endif +extern u32 omap1_get_reset_sources(void); + #endif /* __ARCH_ARM_MACH_OMAP1_COMMON_H */ diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index d3fec92c54cb..745031870ce4 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -17,19 +17,23 @@ #include <linux/platform_device.h> #include <linux/spi/spi.h> +#include <linux/platform_data/omap-wd-timer.h> + #include <asm/mach/map.h> -#include <plat/tc.h> +#include <mach/tc.h> #include <mach/mux.h> -#include <plat/dma.h> -#include <plat/mmc.h> #include <mach/omap7xx.h> #include <mach/camera.h> #include <mach/hardware.h> +#include "../plat-omap/sram.h" + #include "common.h" #include "clock.h" +#include "dma.h" +#include "mmc.h" #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE) @@ -175,6 +179,13 @@ static int __init omap_mmc_add(const char *name, int id, unsigned long base, res[3].name = "tx"; res[3].flags = IORESOURCE_DMA; + if (cpu_is_omap7xx()) + data->slots[0].features = MMC_OMAP7XX; + if (cpu_is_omap15xx()) + data->slots[0].features = MMC_OMAP15XX; + if (cpu_is_omap16xx()) + data->slots[0].features = MMC_OMAP16XX; + ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res)); if (ret == 0) ret = platform_device_add_data(pdev, data, sizeof(*data)); @@ -439,18 +450,31 @@ static struct resource wdt_resources[] = { }; static struct platform_device omap_wdt_device = { - .name = "omap_wdt", - .id = -1, + .name = "omap_wdt", + .id = -1, .num_resources = ARRAY_SIZE(wdt_resources), .resource = wdt_resources, }; static int __init omap_init_wdt(void) { + struct omap_wd_timer_platform_data pdata; + int ret; + if (!cpu_is_omap16xx()) return -ENODEV; - return platform_device_register(&omap_wdt_device); + pdata.read_reset_sources = omap1_get_reset_sources; + + ret = platform_device_register(&omap_wdt_device); + if (!ret) { + ret = platform_device_add_data(&omap_wdt_device, &pdata, + sizeof(pdata)); + if (ret) + platform_device_del(&omap_wdt_device); + } + + return ret; } subsys_initcall(omap_init_wdt); #endif diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c index 29007fef84cd..71305c15fbd5 100644 --- a/arch/arm/mach-omap1/dma.c +++ b/arch/arm/mach-omap1/dma.c @@ -25,11 +25,13 @@ #include <linux/device.h> #include <linux/io.h> -#include <plat/dma.h> -#include <plat/tc.h> +#include <plat-omap/dma-omap.h> +#include <mach/tc.h> #include <mach/irqs.h> +#include "dma.h" + #define OMAP1_DMA_BASE (0xfffed800) #define OMAP1_LOGICAL_DMA_CH_COUNT 17 #define OMAP1_DMA_STRIDE 0x40 diff --git a/arch/arm/mach-omap1/dma.h b/arch/arm/mach-omap1/dma.h new file mode 100644 index 000000000000..da6345dab03f --- /dev/null +++ b/arch/arm/mach-omap1/dma.h @@ -0,0 +1,83 @@ +/* + * OMAP1 DMA channel definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __OMAP1_DMA_CHANNEL_H +#define __OMAP1_DMA_CHANNEL_H + +/* DMA channels for omap1 */ +#define OMAP_DMA_NO_DEVICE 0 +#define OMAP_DMA_MCSI1_TX 1 +#define OMAP_DMA_MCSI1_RX 2 +#define OMAP_DMA_I2C_RX 3 +#define OMAP_DMA_I2C_TX 4 +#define OMAP_DMA_EXT_NDMA_REQ 5 +#define OMAP_DMA_EXT_NDMA_REQ2 6 +#define OMAP_DMA_UWIRE_TX 7 +#define OMAP_DMA_MCBSP1_TX 8 +#define OMAP_DMA_MCBSP1_RX 9 +#define OMAP_DMA_MCBSP3_TX 10 +#define OMAP_DMA_MCBSP3_RX 11 +#define OMAP_DMA_UART1_TX 12 +#define OMAP_DMA_UART1_RX 13 +#define OMAP_DMA_UART2_TX 14 +#define OMAP_DMA_UART2_RX 15 +#define OMAP_DMA_MCBSP2_TX 16 +#define OMAP_DMA_MCBSP2_RX 17 +#define OMAP_DMA_UART3_TX 18 +#define OMAP_DMA_UART3_RX 19 +#define OMAP_DMA_CAMERA_IF_RX 20 +#define OMAP_DMA_MMC_TX 21 +#define OMAP_DMA_MMC_RX 22 +#define OMAP_DMA_NAND 23 +#define OMAP_DMA_IRQ_LCD_LINE 24 +#define OMAP_DMA_MEMORY_STICK 25 +#define OMAP_DMA_USB_W2FC_RX0 26 +#define OMAP_DMA_USB_W2FC_RX1 27 +#define OMAP_DMA_USB_W2FC_RX2 28 +#define OMAP_DMA_USB_W2FC_TX0 29 +#define OMAP_DMA_USB_W2FC_TX1 30 +#define OMAP_DMA_USB_W2FC_TX2 31 + +/* These are only for 1610 */ +#define OMAP_DMA_CRYPTO_DES_IN 32 +#define OMAP_DMA_SPI_TX 33 +#define OMAP_DMA_SPI_RX 34 +#define OMAP_DMA_CRYPTO_HASH 35 +#define OMAP_DMA_CCP_ATTN 36 +#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 +#define OMAP_DMA_CMT_APE_TX_CHAN_0 38 +#define OMAP_DMA_CMT_APE_RV_CHAN_0 39 +#define OMAP_DMA_CMT_APE_TX_CHAN_1 40 +#define OMAP_DMA_CMT_APE_RV_CHAN_1 41 +#define OMAP_DMA_CMT_APE_TX_CHAN_2 42 +#define OMAP_DMA_CMT_APE_RV_CHAN_2 43 +#define OMAP_DMA_CMT_APE_TX_CHAN_3 44 +#define OMAP_DMA_CMT_APE_RV_CHAN_3 45 +#define OMAP_DMA_CMT_APE_TX_CHAN_4 46 +#define OMAP_DMA_CMT_APE_RV_CHAN_4 47 +#define OMAP_DMA_CMT_APE_TX_CHAN_5 48 +#define OMAP_DMA_CMT_APE_RV_CHAN_5 49 +#define OMAP_DMA_CMT_APE_TX_CHAN_6 50 +#define OMAP_DMA_CMT_APE_RV_CHAN_6 51 +#define OMAP_DMA_CMT_APE_TX_CHAN_7 52 +#define OMAP_DMA_CMT_APE_RV_CHAN_7 53 +#define OMAP_DMA_MMC2_TX 54 +#define OMAP_DMA_MMC2_RX 55 +#define OMAP_DMA_CRYPTO_DES_OUT 56 + +#endif /* __OMAP1_DMA_CHANNEL_H */ diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c index 73ae6169aa4a..b3fb531af94e 100644 --- a/arch/arm/mach-omap1/flash.c +++ b/arch/arm/mach-omap1/flash.c @@ -10,7 +10,7 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/map.h> -#include <plat/tc.h> +#include <mach/tc.h> #include <mach/flash.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c index 29ec50fc688d..d940fac9a9ed 100644 --- a/arch/arm/mach-omap1/fpga.c +++ b/arch/arm/mach-omap1/fpga.c @@ -27,11 +27,12 @@ #include <asm/irq.h> #include <asm/mach/irq.h> -#include <plat/fpga.h> +#include <../plat-omap/fpga.h> #include <mach/hardware.h> #include "iomap.h" +#include "common.h" static void fpga_mask_irq(struct irq_data *d) { diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c index a0551a6d7451..32bcbb8d6c73 100644 --- a/arch/arm/mach-omap1/i2c.c +++ b/arch/arm/mach-omap1/i2c.c @@ -19,11 +19,25 @@ * */ -#include <plat/i2c.h> +#include <linux/i2c-omap.h> #include <mach/mux.h> -#include <plat/cpu.h> +#include "soc.h" -void __init omap1_i2c_mux_pins(int bus_id) +#include "../plat-omap/i2c.h" + +#define OMAP_I2C_SIZE 0x3f +#define OMAP1_I2C_BASE 0xfffb3800 +#define OMAP1_INT_I2C (32 + 4) + +static const char name[] = "omap_i2c"; + +static struct resource i2c_resources[2] = { +}; + +static struct platform_device omap_i2c_devices[1] = { +}; + +static void __init omap1_i2c_mux_pins(int bus_id) { if (cpu_is_omap7xx()) { omap_cfg_reg(I2C_7XX_SDA); @@ -33,3 +47,44 @@ void __init omap1_i2c_mux_pins(int bus_id) omap_cfg_reg(I2C_SCL); } } + +int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *pdata, + int bus_id) +{ + struct platform_device *pdev; + struct resource *res; + + omap1_i2c_mux_pins(bus_id); + + pdev = &omap_i2c_devices[bus_id - 1]; + pdev->id = bus_id; + pdev->name = name; + pdev->num_resources = ARRAY_SIZE(i2c_resources); + res = i2c_resources; + res[0].start = OMAP1_I2C_BASE; + res[0].end = res[0].start + OMAP_I2C_SIZE; + res[0].flags = IORESOURCE_MEM; + res[1].start = OMAP1_INT_I2C; + res[1].flags = IORESOURCE_IRQ; + pdev->resource = res; + + /* all OMAP1 have IP version 1 register set */ + pdata->rev = OMAP_I2C_IP_VERSION_1; + + /* all OMAP1 I2C are implemented like this */ + pdata->flags = OMAP_I2C_FLAG_NO_FIFO | + OMAP_I2C_FLAG_SIMPLE_CLOCK | + OMAP_I2C_FLAG_16BIT_DATA_REG | + OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK; + + /* how the cpu bus is wired up differs for 7xx only */ + + if (cpu_is_omap7xx()) + pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_1; + else + pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_2; + + pdev->dev.platform_data = pdata; + + return platform_device_register(pdev); +} diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c index a1b846aacdaf..52de382fc804 100644 --- a/arch/arm/mach-omap1/id.c +++ b/arch/arm/mach-omap1/id.c @@ -17,7 +17,7 @@ #include <linux/io.h> #include <asm/system_info.h> -#include <plat/cpu.h> +#include "soc.h" #include <mach/hardware.h> diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S index 2b36a281dc84..5c1a26c9f490 100644 --- a/arch/arm/mach-omap1/include/mach/debug-macro.S +++ b/arch/arm/mach-omap1/include/mach/debug-macro.S @@ -13,7 +13,7 @@ #include <linux/serial_reg.h> -#include <plat/serial.h> +#include "serial.h" .pushsection .data omap_uart_phys: .word 0x0 diff --git a/arch/arm/mach-omap1/include/mach/hardware.h b/arch/arm/mach-omap1/include/mach/hardware.h index 84248d250adb..dc3237bd72d2 100644 --- a/arch/arm/mach-omap1/include/mach/hardware.h +++ b/arch/arm/mach-omap1/include/mach/hardware.h @@ -39,7 +39,7 @@ #include <asm/sizes.h> #ifndef __ASSEMBLER__ #include <asm/types.h> -#include <plat/cpu.h> +#include "../../mach-omap1/soc.h" /* * NOTE: Please use ioremap + __raw_read/write where possible instead of these @@ -51,7 +51,7 @@ extern void omap_writeb(u8 v, u32 pa); extern void omap_writew(u16 v, u32 pa); extern void omap_writel(u32 v, u32 pa); -#include <plat/tc.h> +#include <mach/tc.h> /* Almost all documentation for chip and board memory maps assumes * BM is clear. Most devel boards have a switch to control booting @@ -72,7 +72,7 @@ static inline u32 omap_cs3_phys(void) #endif /* ifndef __ASSEMBLER__ */ -#include <plat/serial.h> +#include <mach/serial.h> /* * --------------------------------------------------------------------------- diff --git a/arch/arm/mach-omap1/include/mach/memory.h b/arch/arm/mach-omap1/include/mach/memory.h index 901082def9bd..351ae4f2c514 100644 --- a/arch/arm/mach-omap1/include/mach/memory.h +++ b/arch/arm/mach-omap1/include/mach/memory.h @@ -19,7 +19,7 @@ * because of the strncmp(). */ #if defined(CONFIG_ARCH_OMAP15XX) && !defined(__ASSEMBLER__) -#include <plat/cpu.h> +#include "../../mach-omap1/soc.h" /* * OMAP-1510 Local Bus address offset diff --git a/arch/arm/mach-omap1/include/mach/omap1510.h b/arch/arm/mach-omap1/include/mach/omap1510.h index 8fe05d6137c0..3d235244bf5c 100644 --- a/arch/arm/mach-omap1/include/mach/omap1510.h +++ b/arch/arm/mach-omap1/include/mach/omap1510.h @@ -45,5 +45,118 @@ #define OMAP1510_DSP_MMU_BASE (0xfffed200) +/* + * --------------------------------------------------------------------------- + * OMAP-1510 FPGA + * --------------------------------------------------------------------------- + */ +#define OMAP1510_FPGA_BASE 0xE8000000 /* VA */ +#define OMAP1510_FPGA_SIZE SZ_4K +#define OMAP1510_FPGA_START 0x08000000 /* PA */ + +/* Revision */ +#define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0) +#define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1) +#define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2) +#define OMAP1510_FPGA_LED_DIGIT IOMEM(OMAP1510_FPGA_BASE + 0x3) +#define INNOVATOR_FPGA_HID_SPI IOMEM(OMAP1510_FPGA_BASE + 0x4) +#define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5) + +/* Interrupt status */ +#define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6) +#define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7) + +/* Interrupt mask */ +#define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8) +#define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9) + +/* Reset registers */ +#define OMAP1510_FPGA_HOST_RESET IOMEM(OMAP1510_FPGA_BASE + 0xa) +#define OMAP1510_FPGA_RST IOMEM(OMAP1510_FPGA_BASE + 0xb) + +#define OMAP1510_FPGA_AUDIO IOMEM(OMAP1510_FPGA_BASE + 0xc) +#define OMAP1510_FPGA_DIP IOMEM(OMAP1510_FPGA_BASE + 0xe) +#define OMAP1510_FPGA_FPGA_IO IOMEM(OMAP1510_FPGA_BASE + 0xf) +#define OMAP1510_FPGA_UART1 IOMEM(OMAP1510_FPGA_BASE + 0x14) +#define OMAP1510_FPGA_UART2 IOMEM(OMAP1510_FPGA_BASE + 0x15) +#define OMAP1510_FPGA_OMAP1510_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x16) +#define OMAP1510_FPGA_BOARD_REV IOMEM(OMAP1510_FPGA_BASE + 0x18) +#define INNOVATOR_FPGA_CAM_USB_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20c) +#define OMAP1510P1_PPT_DATA IOMEM(OMAP1510_FPGA_BASE + 0x100) +#define OMAP1510P1_PPT_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x101) +#define OMAP1510P1_PPT_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x102) + +#define OMAP1510_FPGA_TOUCHSCREEN IOMEM(OMAP1510_FPGA_BASE + 0x204) + +#define INNOVATOR_FPGA_INFO IOMEM(OMAP1510_FPGA_BASE + 0x205) +#define INNOVATOR_FPGA_LCD_BRIGHT_LO IOMEM(OMAP1510_FPGA_BASE + 0x206) +#define INNOVATOR_FPGA_LCD_BRIGHT_HI IOMEM(OMAP1510_FPGA_BASE + 0x207) +#define INNOVATOR_FPGA_LED_GRN_LO IOMEM(OMAP1510_FPGA_BASE + 0x208) +#define INNOVATOR_FPGA_LED_GRN_HI IOMEM(OMAP1510_FPGA_BASE + 0x209) +#define INNOVATOR_FPGA_LED_RED_LO IOMEM(OMAP1510_FPGA_BASE + 0x20a) +#define INNOVATOR_FPGA_LED_RED_HI IOMEM(OMAP1510_FPGA_BASE + 0x20b) +#define INNOVATOR_FPGA_EXP_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20d) +#define INNOVATOR_FPGA_ISR2 IOMEM(OMAP1510_FPGA_BASE + 0x20e) +#define INNOVATOR_FPGA_IMR2 IOMEM(OMAP1510_FPGA_BASE + 0x210) + +#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300) + +/* + * Power up Giga UART driver, turn on HID clock. + * Turn off BT power, since we're not using it and it + * draws power. + */ +#define OMAP1510_FPGA_RESET_VALUE 0x42 + +#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7) +#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6) +#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5) +#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4) +#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3) +#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2) +#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1) +#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0) + +/* + * Innovator/OMAP1510 FPGA HID register bit definitions + */ +#define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */ +#define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */ +#define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */ +#define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */ +#define OMAP1510_FPGA_HID_MISO (1<<4) /* input */ +#define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */ +#define OMAP1510_FPGA_HID_rsrvd (1<<6) +#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */ + +/* The FPGA IRQ is cascaded through GPIO_13 */ +#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13) + +/* IRQ Numbers for interrupts muxed through the FPGA */ +#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0) +#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1) +#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2) +#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3) +#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4) +#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5) +#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6) +#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7) +#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8) +#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9) +#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10) +#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11) +#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12) +#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13) +#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14) +#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15) +#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16) +#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17) +#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18) +#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19) +#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20) +#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21) +#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22) +#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23) + #endif /* __ASM_ARCH_OMAP15XX_H */ diff --git a/arch/arm/mach-omap1/include/mach/serial.h b/arch/arm/mach-omap1/include/mach/serial.h new file mode 100644 index 000000000000..2ce6a2db470b --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/serial.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2009 Texas Instruments + * Added OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_SERIAL_H +#define __ASM_ARCH_SERIAL_H + +#include <linux/init.h> + +/* + * Memory entry used for the DEBUG_LL UART configuration, relative to + * start of RAM. See also uncompress.h and debug-macro.S. + * + * Note that using a memory location for storing the UART configuration + * has at least two limitations: + * + * 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the + * uncompress code could then partially overwrite itself + * 2. We assume printascii is called at least once before paging_init, + * and addruart has a chance to read OMAP_UART_INFO + */ +#define OMAP_UART_INFO_OFS 0x3ffc + +/* OMAP1 serial ports */ +#define OMAP1_UART1_BASE 0xfffb0000 +#define OMAP1_UART2_BASE 0xfffb0800 +#define OMAP1_UART3_BASE 0xfffb9800 + +#define OMAP_PORT_SHIFT 2 +#define OMAP7XX_PORT_SHIFT 0 + +#define OMAP1510_BASE_BAUD (12000000/16) +#define OMAP16XX_BASE_BAUD (48000000/16) + +/* + * DEBUG_LL port encoding stored into the UART1 scratchpad register by + * decomp_setup in uncompress.h + */ +#define OMAP1UART1 11 +#define OMAP1UART2 12 +#define OMAP1UART3 13 + +#ifndef __ASSEMBLER__ +extern void omap_serial_init(void); +#endif + +#endif diff --git a/arch/arm/plat-omap/include/plat/tc.h b/arch/arm/mach-omap1/include/mach/tc.h index 1b4b2da86203..1b4b2da86203 100644 --- a/arch/arm/plat-omap/include/plat/tc.h +++ b/arch/arm/mach-omap1/include/mach/tc.h diff --git a/arch/arm/mach-omap1/include/mach/uncompress.h b/arch/arm/mach-omap1/include/mach/uncompress.h index 0ff22dc075c7..ad6fbe7d83f2 100644 --- a/arch/arm/mach-omap1/include/mach/uncompress.h +++ b/arch/arm/mach-omap1/include/mach/uncompress.h @@ -1,5 +1,122 @@ /* - * arch/arm/mach-omap1/include/mach/uncompress.h + * arch/arm/plat-omap/include/mach/uncompress.h + * + * Serial port stubs for kernel decompress status messages + * + * Initially based on: + * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h + * Copyright (C) 2000 RidgeRun, Inc. + * Author: Greg Lonnon <glonnon@ridgerun.com> + * + * Rewritten by: + * Author: <source@mvista.com> + * 2004 (c) MontaVista Software, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. */ -#include <plat/uncompress.h> +#include <linux/types.h> +#include <linux/serial_reg.h> + +#include <asm/memory.h> +#include <asm/mach-types.h> + +#include "serial.h" + +#define MDR1_MODE_MASK 0x07 + +volatile u8 *uart_base; +int uart_shift; + +/* + * Store the DEBUG_LL uart number into memory. + * See also debug-macro.S, and serial.c for related code. + */ +static void set_omap_uart_info(unsigned char port) +{ + /* + * Get address of some.bss variable and round it down + * a la CONFIG_AUTO_ZRELADDR. + */ + u32 ram_start = (u32)&uart_shift & 0xf8000000; + u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS); + *uart_info = port; +} + +static void putc(int c) +{ + if (!uart_base) + return; + + /* Check for UART 16x mode */ + if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0) + return; + + while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE)) + barrier(); + uart_base[UART_TX << uart_shift] = c; +} + +static inline void flush(void) +{ +} + +/* + * Macros to configure UART1 and debug UART + */ +#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id) \ + if (machine_is_##mach()) { \ + uart_base = (volatile u8 *)(dbg_uart); \ + uart_shift = (dbg_shft); \ + port = (dbg_id); \ + set_omap_uart_info(port); \ + break; \ + } + +#define DEBUG_LL_OMAP7XX(p, mach) \ + _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, \ + OMAP1UART##p) + +#define DEBUG_LL_OMAP1(p, mach) \ + _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, \ + OMAP1UART##p) + +static inline void arch_decomp_setup(void) +{ + int port = 0; + + /* + * Initialize the port based on the machine ID from the bootloader. + * Note that we're using macros here instead of switch statement + * as machine_is functions are optimized out for the boards that + * are not selected. + */ + do { + /* omap7xx/8xx based boards using UART1 with shift 0 */ + DEBUG_LL_OMAP7XX(1, herald); + DEBUG_LL_OMAP7XX(1, omap_perseus2); + + /* omap15xx/16xx based boards using UART1 */ + DEBUG_LL_OMAP1(1, ams_delta); + DEBUG_LL_OMAP1(1, nokia770); + DEBUG_LL_OMAP1(1, omap_h2); + DEBUG_LL_OMAP1(1, omap_h3); + DEBUG_LL_OMAP1(1, omap_innovator); + DEBUG_LL_OMAP1(1, omap_osk); + DEBUG_LL_OMAP1(1, omap_palmte); + DEBUG_LL_OMAP1(1, omap_palmz71); + + /* omap15xx/16xx based boards using UART2 */ + DEBUG_LL_OMAP1(2, omap_palmtt); + + /* omap15xx/16xx based boards using UART3 */ + DEBUG_LL_OMAP1(3, sx1); + } while (0); +} + +/* + * nothing to do + */ +#define arch_decomp_wdog() diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index 6a5baab1f4cb..44389d7cd255 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c @@ -17,8 +17,8 @@ #include <asm/mach/map.h> #include <mach/mux.h> -#include <plat/tc.h> -#include <plat/dma.h> +#include <mach/tc.h> +#include <plat-omap/dma-omap.h> #include "iomap.h" #include "common.h" diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c index 6995fb6a3345..122ef67939a2 100644 --- a/arch/arm/mach-omap1/irq.c +++ b/arch/arm/mach-omap1/irq.c @@ -45,7 +45,7 @@ #include <asm/irq.h> #include <asm/mach/irq.h> -#include <plat/cpu.h> +#include "soc.h" #include <mach/hardware.h> diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c index ed42628611bc..7ed8c1857d56 100644 --- a/arch/arm/mach-omap1/lcd_dma.c +++ b/arch/arm/mach-omap1/lcd_dma.c @@ -27,11 +27,13 @@ #include <linux/interrupt.h> #include <linux/io.h> -#include <plat/dma.h> +#include <plat-omap/dma-omap.h> #include <mach/hardware.h> #include <mach/lcdc.h> +#include "dma.h" + int omap_lcd_dma_running(void) { /* diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index bdc2e7541adb..c6d8fdf92e9c 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c @@ -19,14 +19,15 @@ #include <linux/platform_device.h> #include <linux/slab.h> -#include <plat/dma.h> +#include <plat-omap/dma-omap.h> #include <mach/mux.h> -#include <plat/cpu.h> +#include "soc.h" #include <linux/platform_data/asoc-ti-mcbsp.h> #include <mach/irqs.h> #include "iomap.h" +#include "dma.h" #define DPS_RSTCT2_PER_EN (1 << 0) #define DSP_RSTCT2_WD_PER_EN (1 << 1) diff --git a/arch/arm/mach-omap1/mmc.h b/arch/arm/mach-omap1/mmc.h new file mode 100644 index 000000000000..39c2b13de884 --- /dev/null +++ b/arch/arm/mach-omap1/mmc.h @@ -0,0 +1,18 @@ +#include <linux/mmc/host.h> +#include <linux/platform_data/mmc-omap.h> + +#define OMAP15XX_NR_MMC 1 +#define OMAP16XX_NR_MMC 2 +#define OMAP1_MMC_SIZE 0x080 +#define OMAP1_MMC1_BASE 0xfffb7800 +#define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */ + +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) +void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, + int nr_controllers); +#else +static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, + int nr_controllers) +{ +} +#endif diff --git a/arch/arm/mach-omap1/opp_data.c b/arch/arm/mach-omap1/opp_data.c index 9cd4ddb51397..8dcebe6d8882 100644 --- a/arch/arm/mach-omap1/opp_data.c +++ b/arch/arm/mach-omap1/opp_data.c @@ -10,7 +10,7 @@ * published by the Free Software Foundation. */ -#include <plat/clkdev_omap.h> +#include "clock.h" #include "opp.h" /*------------------------------------------------------------------------- diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index 47ec16155483..b2c2328d7c18 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c @@ -49,17 +49,17 @@ #include <asm/mach/time.h> #include <asm/mach/irq.h> -#include <plat/cpu.h> -#include <plat/clock.h> -#include <plat/sram.h> -#include <plat/tc.h> +#include <mach/tc.h> #include <mach/mux.h> -#include <plat/dma.h> +#include <plat-omap/dma-omap.h> #include <plat/dmtimer.h> #include <mach/irqs.h> +#include "../plat-omap/sram.h" + #include "iomap.h" +#include "clock.h" #include "pm.h" static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c index 7868e75ad077..3f2d39672393 100644 --- a/arch/arm/mach-omap1/pm_bus.c +++ b/arch/arm/mach-omap1/pm_bus.c @@ -19,8 +19,7 @@ #include <linux/clk.h> #include <linux/err.h> -#include <plat/omap_device.h> -#include <plat/omap-pm.h> +#include "soc.h" #ifdef CONFIG_PM_RUNTIME static int omap1_pm_runtime_suspend(struct device *dev) diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c index b17709103866..5eebd7e889d0 100644 --- a/arch/arm/mach-omap1/reset.c +++ b/arch/arm/mach-omap1/reset.c @@ -4,12 +4,24 @@ #include <linux/kernel.h> #include <linux/io.h> -#include <plat/prcm.h> - #include <mach/hardware.h> +#include "iomap.h" #include "common.h" +/* ARM_SYSST bit shifts related to SoC reset sources */ +#define ARM_SYSST_POR_SHIFT 5 +#define ARM_SYSST_EXT_RST_SHIFT 4 +#define ARM_SYSST_ARM_WDRST_SHIFT 2 +#define ARM_SYSST_GLOB_SWRST_SHIFT 1 + +/* Standardized reset source bits (across all OMAP SoCs) */ +#define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT 0 +#define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT 1 +#define OMAP_MPU_WD_RST_SRC_ID_SHIFT 3 +#define OMAP_EXTWARM_RST_SRC_ID_SHIFT 5 + + void omap1_restart(char mode, const char *cmd) { /* @@ -23,3 +35,28 @@ void omap1_restart(char mode, const char *cmd) omap_writew(1, ARM_RSTCT1); } + +/** + * omap1_get_reset_sources - return the source of the SoC's last reset + * + * Returns bits that represent the last reset source for the SoC. The + * format is standardized across OMAPs for use by the OMAP watchdog. + */ +u32 omap1_get_reset_sources(void) +{ + u32 ret = 0; + u16 rs; + + rs = __raw_readw(OMAP1_IO_ADDRESS(ARM_SYSST)); + + if (rs & (1 << ARM_SYSST_POR_SHIFT)) + ret |= 1 << OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT; + if (rs & (1 << ARM_SYSST_EXT_RST_SHIFT)) + ret |= 1 << OMAP_EXTWARM_RST_SRC_ID_SHIFT; + if (rs & (1 << ARM_SYSST_ARM_WDRST_SHIFT)) + ret |= 1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT; + if (rs & (1 << ARM_SYSST_GLOB_SWRST_SHIFT)) + ret |= 1 << OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT; + + return ret; +} diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index b9d6834af835..d1ac08016f0b 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c @@ -23,7 +23,6 @@ #include <asm/mach-types.h> #include <mach/mux.h> -#include <plat/fpga.h> #include "pm.h" diff --git a/arch/arm/mach-omap1/soc.h b/arch/arm/mach-omap1/soc.h new file mode 100644 index 000000000000..6cf9c1cc2bef --- /dev/null +++ b/arch/arm/mach-omap1/soc.h @@ -0,0 +1,229 @@ +/* + * OMAP cpu type detection + * + * Copyright (C) 2004, 2008 Nokia Corporation + * + * Copyright (C) 2009-11 Texas Instruments. + * + * Written by Tony Lindgren <tony.lindgren@nokia.com> + * + * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARCH_OMAP_CPU_H +#define __ASM_ARCH_OMAP_CPU_H + +#ifndef __ASSEMBLY__ + +#include <linux/bitops.h> + +/* + * Test if multicore OMAP support is needed + */ +#undef MULTI_OMAP1 +#undef OMAP_NAME + +#ifdef CONFIG_ARCH_OMAP730 +# ifdef OMAP_NAME +# undef MULTI_OMAP1 +# define MULTI_OMAP1 +# else +# define OMAP_NAME omap730 +# endif +#endif +#ifdef CONFIG_ARCH_OMAP850 +# ifdef OMAP_NAME +# undef MULTI_OMAP1 +# define MULTI_OMAP1 +# else +# define OMAP_NAME omap850 +# endif +#endif +#ifdef CONFIG_ARCH_OMAP15XX +# ifdef OMAP_NAME +# undef MULTI_OMAP1 +# define MULTI_OMAP1 +# else +# define OMAP_NAME omap1510 +# endif +#endif +#ifdef CONFIG_ARCH_OMAP16XX +# ifdef OMAP_NAME +# undef MULTI_OMAP1 +# define MULTI_OMAP1 +# else +# define OMAP_NAME omap16xx +# endif +#endif + +/* + * omap_rev bits: + * CPU id bits (0730, 1510, 1710, 2422...) [31:16] + * CPU revision (See _REV_ defined in cpu.h) [15:08] + * CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00] + */ +unsigned int omap_rev(void); + +/* + * Get the CPU revision for OMAP devices + */ +#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff) + +/* + * Macros to group OMAP into cpu classes. + * These can be used in most places. + * cpu_is_omap7xx(): True for OMAP730, OMAP850 + * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310 + * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710 + */ +#define GET_OMAP_CLASS (omap_rev() & 0xff) + +#define IS_OMAP_CLASS(class, id) \ +static inline int is_omap ##class (void) \ +{ \ + return (GET_OMAP_CLASS == (id)) ? 1 : 0; \ +} + +#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff) + +#define IS_OMAP_SUBCLASS(subclass, id) \ +static inline int is_omap ##subclass (void) \ +{ \ + return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ +} + +IS_OMAP_CLASS(7xx, 0x07) +IS_OMAP_CLASS(15xx, 0x15) +IS_OMAP_CLASS(16xx, 0x16) + +#define cpu_is_omap7xx() 0 +#define cpu_is_omap15xx() 0 +#define cpu_is_omap16xx() 0 + +#if defined(MULTI_OMAP1) +# if defined(CONFIG_ARCH_OMAP730) +# undef cpu_is_omap7xx +# define cpu_is_omap7xx() is_omap7xx() +# endif +# if defined(CONFIG_ARCH_OMAP850) +# undef cpu_is_omap7xx +# define cpu_is_omap7xx() is_omap7xx() +# endif +# if defined(CONFIG_ARCH_OMAP15XX) +# undef cpu_is_omap15xx +# define cpu_is_omap15xx() is_omap15xx() +# endif +# if defined(CONFIG_ARCH_OMAP16XX) +# undef cpu_is_omap16xx +# define cpu_is_omap16xx() is_omap16xx() +# endif +#else +# if defined(CONFIG_ARCH_OMAP730) +# undef cpu_is_omap7xx +# define cpu_is_omap7xx() 1 +# endif +# if defined(CONFIG_ARCH_OMAP850) +# undef cpu_is_omap7xx +# define cpu_is_omap7xx() 1 +# endif +# if defined(CONFIG_ARCH_OMAP15XX) +# undef cpu_is_omap15xx +# define cpu_is_omap15xx() 1 +# endif +# if defined(CONFIG_ARCH_OMAP16XX) +# undef cpu_is_omap16xx +# define cpu_is_omap16xx() 1 +# endif +#endif + +/* + * Macros to detect individual cpu types. + * These are only rarely needed. + * cpu_is_omap310(): True for OMAP310 + * cpu_is_omap1510(): True for OMAP1510 + * cpu_is_omap1610(): True for OMAP1610 + * cpu_is_omap1611(): True for OMAP1611 + * cpu_is_omap5912(): True for OMAP5912 + * cpu_is_omap1621(): True for OMAP1621 + * cpu_is_omap1710(): True for OMAP1710 + */ +#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff) + +#define IS_OMAP_TYPE(type, id) \ +static inline int is_omap ##type (void) \ +{ \ + return (GET_OMAP_TYPE == (id)) ? 1 : 0; \ +} + +IS_OMAP_TYPE(310, 0x0310) +IS_OMAP_TYPE(1510, 0x1510) +IS_OMAP_TYPE(1610, 0x1610) +IS_OMAP_TYPE(1611, 0x1611) +IS_OMAP_TYPE(5912, 0x1611) +IS_OMAP_TYPE(1621, 0x1621) +IS_OMAP_TYPE(1710, 0x1710) + +#define cpu_is_omap310() 0 +#define cpu_is_omap1510() 0 +#define cpu_is_omap1610() 0 +#define cpu_is_omap5912() 0 +#define cpu_is_omap1611() 0 +#define cpu_is_omap1621() 0 +#define cpu_is_omap1710() 0 + +/* These are needed to compile common code */ +#ifdef CONFIG_ARCH_OMAP1 +#define cpu_is_omap242x() 0 +#define cpu_is_omap2430() 0 +#define cpu_is_omap243x() 0 +#define cpu_is_omap24xx() 0 +#define cpu_is_omap34xx() 0 +#define cpu_is_omap44xx() 0 +#define soc_is_omap54xx() 0 +#define soc_is_am33xx() 0 +#define cpu_class_is_omap1() 1 +#define cpu_class_is_omap2() 0 +#endif + +/* + * Whether we have MULTI_OMAP1 or not, we still need to distinguish + * between 310 vs. 1510 and 1611B/5912 vs. 1710. + */ + +#if defined(CONFIG_ARCH_OMAP15XX) +# undef cpu_is_omap310 +# undef cpu_is_omap1510 +# define cpu_is_omap310() is_omap310() +# define cpu_is_omap1510() is_omap1510() +#endif + +#if defined(CONFIG_ARCH_OMAP16XX) +# undef cpu_is_omap1610 +# undef cpu_is_omap1611 +# undef cpu_is_omap5912 +# undef cpu_is_omap1621 +# undef cpu_is_omap1710 +# define cpu_is_omap1610() is_omap1610() +# define cpu_is_omap1611() is_omap1611() +# define cpu_is_omap5912() is_omap5912() +# define cpu_is_omap1621() is_omap1621() +# define cpu_is_omap1710() is_omap1710() +#endif + +#endif /* __ASSEMBLY__ */ +#endif diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index d669e227e00c..c81bc508e7a3 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -34,6 +34,7 @@ config ARCH_OMAP2 select CPU_V6 select MULTI_IRQ_HANDLER select SOC_HAS_OMAP2_SDRC + select COMMON_CLK config ARCH_OMAP3 bool "TI OMAP3" @@ -47,6 +48,7 @@ config ARCH_OMAP3 select PM_OPP if PM select PM_RUNTIME if CPU_IDLE select SOC_HAS_OMAP2_SDRC + select COMMON_CLK select USB_ARCH_HAS_EHCI if USB_SUPPORT config ARCH_OMAP4 @@ -68,6 +70,7 @@ config ARCH_OMAP4 select PM_OPP if PM select PM_RUNTIME if CPU_IDLE select USB_ARCH_HAS_EHCI if USB_SUPPORT + select COMMON_CLK config SOC_OMAP5 bool "TI OMAP5" @@ -77,6 +80,7 @@ config SOC_OMAP5 select CPU_V7 select HAVE_SMP select SOC_HAS_REALTIME_COUNTER + select COMMON_CLK comment "OMAP Core Type" depends on ARCH_OMAP2 @@ -111,6 +115,7 @@ config SOC_AM33XX select ARM_CPU_SUSPEND if PM select CPU_V7 select MULTI_IRQ_HANDLER + select COMMON_CLK config OMAP_PACKAGE_ZAF bool diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index fe40d9e488c9..798f35b8ea59 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -4,30 +4,37 @@ # Common support obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \ - common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o - -# INTCPS IP block support - XXX should be moved to drivers/ -obj-$(CONFIG_ARCH_OMAP2) += irq.o -obj-$(CONFIG_ARCH_OMAP3) += irq.o -obj-$(CONFIG_SOC_AM33XX) += irq.o - -# Secure monitor API support -obj-$(CONFIG_ARCH_OMAP3) += omap-smc.o omap-secure.o -obj-$(CONFIG_ARCH_OMAP4) += omap-smc.o omap-secure.o -obj-$(CONFIG_SOC_OMAP5) += omap-smc.o omap-secure.o + common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \ + omap_device.o + +omap-2-3-common = irq.o +hwmod-common = omap_hwmod.o \ + omap_hwmod_common_data.o +clock-common = clock.o clock_common_data.o \ + clkt_dpll.o clkt_clksel.o +secure-common = omap-smc.o omap-secure.o + +obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) +obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) +obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) +obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) +obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) obj-y += mcbsp.o endif -obj-$(CONFIG_TWL4030_CORE) += omap_twl.o +obj-$(CONFIG_TWL4030_CORE) += omap_twl.o +obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o # SMP support ONLY available for OMAP4 obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o -obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o -obj-$(CONFIG_SOC_OMAP5) += omap4-common.o omap-wakeupgen.o +omap-4-5-common = omap4-common.o omap-wakeupgen.o \ + sleep44xx.o +obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) +obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) @@ -43,6 +50,11 @@ AFLAGS_sram242x.o :=-Wa,-march=armv6 AFLAGS_sram243x.o :=-Wa,-march=armv6 AFLAGS_sram34xx.o :=-Wa,-march=armv7-a +# Restart code (OMAP4/5 currently in omap4-common.c) +obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o +obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o +obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o + # Pin multiplexing obj-$(CONFIG_SOC_OMAP2420) += mux2420.o obj-$(CONFIG_SOC_OMAP2430) += mux2430.o @@ -52,7 +64,6 @@ obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o # SMS/SDRC obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o -obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o # OPP table initialization ifeq ($(CONFIG_PM_OPP),y) @@ -63,15 +74,15 @@ endif # Power Management ifeq ($(CONFIG_PM),y) -obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o sleep24xx.o +obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o +obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o -obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o -obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o sleep44xx.o +obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o -obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o +obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o AFLAGS_sleep24xx.o :=-Wa,-march=armv6 AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec) @@ -83,76 +94,82 @@ endif endif ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o -obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o +obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o +obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o endif # PRCM -obj-y += prcm.o prm_common.o -obj-$(CONFIG_ARCH_OMAP2) += cm2xxx_3xxx.o prm2xxx_3xxx.o -obj-$(CONFIG_ARCH_OMAP3) += cm2xxx_3xxx.o prm2xxx_3xxx.o +obj-y += prm_common.o cm_common.o +obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o +obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ prcm_mpu44xx.o prminst44xx.o \ - vc44xx_data.o vp44xx_data.o \ - prm44xx.o + vc44xx_data.o vp44xx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) # OMAP voltage domains -obj-y += voltage.o vc.o vp.o +voltagedomain-common := voltage.o vc.o vp.o +obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP2) += voltagedomains2xxx_data.o +obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o +obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o -obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o +obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common) +obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o +obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common) # OMAP powerdomain framework -obj-y += powerdomain.o powerdomain-common.o +powerdomain-common += powerdomain.o powerdomain-common.o +obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common) obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_data.o -obj-$(CONFIG_ARCH_OMAP2) += powerdomain2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_3xxx_data.o -obj-$(CONFIG_ARCH_OMAP3) += powerdomain2xxx_3xxx.o +obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common) obj-$(CONFIG_ARCH_OMAP3) += powerdomains3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o +obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o -obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o +obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o -obj-$(CONFIG_SOC_OMAP5) += powerdomain44xx.o +obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) # PRCM clockdomain control -obj-y += clockdomain.o -obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o +clockdomain-common += clockdomain.o +obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common) obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o -obj-$(CONFIG_ARCH_OMAP3) += clockdomain2xxx_3xxx.o +obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common) obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o +obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o -obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o +obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o -obj-$(CONFIG_SOC_OMAP5) += clockdomain44xx.o +obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) # Clock framework -obj-y += clock.o clock_common_data.o \ - clkt_dpll.o clkt_clksel.o -obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o clkt2xxx_sys.o +obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o +obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o +obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o -obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o -obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o -obj-$(CONFIG_ARCH_OMAP3) += clock3xxx.o +obj-$(CONFIG_SOC_OMAP2420) += cclock2420_data.o +obj-$(CONFIG_SOC_OMAP2430) += clock2430.o cclock2430_data.o +obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o -obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o clkt_iclk.o -obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += clock44xx_data.o +obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o +obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o +obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o +obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) cclock44xx_data.o obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o -obj-$(CONFIG_SOC_AM33XX) += dpll3xxx.o clock33xx_data.o +obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o +obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o +obj-$(CONFIG_SOC_OMAP5) += $(clock-common) obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o # OMAP2 clock rate set data (old "OPP" data) @@ -160,7 +177,6 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o # hwmod data -obj-y += omap_hwmod_common_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o @@ -206,10 +222,10 @@ obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o -obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o +obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o -obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o -obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o +obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o +obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o obj-$(CONFIG_MACH_ENCORE) += board-omap3encore.o obj-$(CONFIG_MACH_OVERO) += board-overo.o obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o diff --git a/arch/arm/mach-omap2/am33xx.h b/arch/arm/mach-omap2/am33xx.h index 06c19bb7bca6..43296c1af9ee 100644 --- a/arch/arm/mach-omap2/am33xx.h +++ b/arch/arm/mach-omap2/am33xx.h @@ -21,5 +21,6 @@ #define AM33XX_SCM_BASE 0x44E10000 #define AM33XX_CTRL_BASE AM33XX_SCM_BASE #define AM33XX_PRCM_BASE 0x44E00000 +#define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + 0x3FC) #endif /* __ASM_ARCH_AM33XX_H */ diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c index d0c54c573d34..af11dcdb7e2c 100644 --- a/arch/arm/mach-omap2/am35xx-emac.c +++ b/arch/arm/mach-omap2/am35xx-emac.c @@ -18,7 +18,7 @@ #include <linux/err.h> #include <linux/davinci_emac.h> #include <asm/system.h> -#include <plat/omap_device.h> +#include "omap_device.h" #include "am35xx.h" #include "control.h" #include "am35xx-emac.h" diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 95b384d54f8a..acb0a524ff7b 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -34,8 +34,7 @@ #include <asm/mach/map.h> #include "common.h" -#include <plat/gpmc.h> -#include <plat/usb.h> +#include "gpmc.h" #include "gpmc-smc91x.h" #include <video/omapdss.h> @@ -287,5 +286,5 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") .init_machine = omap_2430sdp_init, .init_late = omap2430_init_late, .timer = &omap2_timer, - .restart = omap_prcm_restart, + .restart = omap2xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 96cd3693e1ae..6601754f9512 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -30,15 +30,15 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/usb.h> #include "common.h" -#include <plat/dma.h> -#include <plat/gpmc.h> +#include <plat-omap/dma-omap.h> #include <video/omapdss.h> #include <video/omap-panel-tfp410.h> +#include "gpmc.h" #include "gpmc-smc91x.h" +#include "soc.h" #include "board-flash.h" #include "mux.h" #include "sdram-qimonda-hyb18m512160af-6.h" @@ -597,5 +597,5 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") .init_machine = omap_3430sdp_init, .init_late = omap3430_init_late, .timer = &omap3_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index fc224ad86747..050aaa771254 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -18,9 +18,8 @@ #include "common.h" #include "gpmc-smc91x.h" -#include <plat/usb.h> -#include <mach/board-zoom.h> +#include "board-zoom.h" #include "board-flash.h" #include "mux.h" @@ -213,5 +212,5 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board") .init_machine = omap_sdp_init, .init_late = omap3630_init_late, .timer = &omap3_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 3669c120c7e8..85dfa71e0dc6 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -27,6 +27,7 @@ #include <linux/leds.h> #include <linux/leds_pwm.h> #include <linux/platform_data/omap4-keypad.h> +#include <linux/usb/musb.h> #include <asm/hardware/gic.h> #include <asm/mach-types.h> @@ -34,8 +35,6 @@ #include <asm/mach/map.h> #include "common.h" -#include <plat/usb.h> -#include <plat/mmc.h> #include "omap4-keypad.h" #include <video/omapdss.h> #include <video/omap-panel-nokia-dsi.h> @@ -45,6 +44,7 @@ #include "soc.h" #include "mux.h" +#include "mmc.h" #include "hsmmc.h" #include "control.h" #include "common-board-devices.h" @@ -881,5 +881,5 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") .init_machine = omap_4430sdp_init, .init_late = omap4430_init_late, .timer = &omap4_timer, - .restart = omap_prcm_restart, + .restart = omap44xx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c index 318feadb1d6e..51b96a1206d1 100644 --- a/arch/arm/mach-omap2/board-am3517crane.c +++ b/arch/arm/mach-omap2/board-am3517crane.c @@ -26,7 +26,6 @@ #include <asm/mach/map.h> #include "common.h" -#include <plat/usb.h> #include "am35xx-emac.h" #include "mux.h" @@ -94,5 +93,5 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD") .init_machine = am3517_crane_init, .init_late = am35xx_init_late, .timer = &omap3_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index e16289755f2e..4be58fd071f6 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -25,6 +25,7 @@ #include <linux/can/platform/ti_hecc.h> #include <linux/davinci_emac.h> #include <linux/mmc/host.h> +#include <linux/usb/musb.h> #include <linux/platform_data/gpio-omap.h> #include "am35xx.h" @@ -33,7 +34,6 @@ #include <asm/mach/map.h> #include "common.h" -#include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> #include <video/omap-panel-tfp410.h> @@ -393,5 +393,5 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") .init_machine = am3517_evm_init, .init_late = am35xx_init_late, .timer = &omap3_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index cea3abace815..5d0a61f54165 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -28,14 +28,14 @@ #include <linux/clk.h> #include <linux/smc91x.h> #include <linux/gpio.h> +#include <linux/platform_data/leds-omap.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> -#include <plat/led.h> #include "common.h" -#include <plat/gpmc.h> +#include "gpmc.h" #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> @@ -338,5 +338,5 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon") .init_machine = omap_apollon_init, .init_late = omap2420_init_late, .timer = &omap2_timer, - .restart = omap_prcm_restart, + .restart = omap2xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 376d26eb601c..488f86fd0e72 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -38,10 +38,7 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include "common.h" #include <linux/platform_data/mtd-nand-omap2.h> -#include <plat/gpmc.h> -#include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> #include <video/omap-panel-tfp410.h> @@ -49,10 +46,13 @@ #include <mach/hardware.h> +#include "common.h" #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" #include "hsmmc.h" #include "common-board-devices.h" +#include "gpmc.h" +#include "gpmc-nand.h" #define CM_T35_GPIO_PENDOWN 57 #define SB_T35_USB_HUB_RESET_GPIO 167 @@ -181,7 +181,7 @@ static struct omap_nand_platform_data cm_t35_nand_data = { static void __init cm_t35_init_nand(void) { - if (gpmc_nand_init(&cm_t35_nand_data) < 0) + if (gpmc_nand_init(&cm_t35_nand_data, NULL) < 0) pr_err("CM-T35: Unable to register NAND device\n"); } #else @@ -753,18 +753,18 @@ MACHINE_START(CM_T35, "Compulab CM-T35") .init_machine = cm_t35_init, .init_late = omap35xx_init_late, .timer = &omap3_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END MACHINE_START(CM_T3730, "Compulab CM-T3730") - .atag_offset = 0x100, - .reserve = omap_reserve, - .map_io = omap3_map_io, - .init_early = omap3630_init_early, - .init_irq = omap3_init_irq, + .atag_offset = 0x100, + .reserve = omap_reserve, + .map_io = omap3_map_io, + .init_early = omap3630_init_early, + .init_irq = omap3_init_irq, .handle_irq = omap3_intc_handle_irq, - .init_machine = cm_t3730_init, + .init_machine = cm_t3730_init, .init_late = omap3630_init_late, - .timer = &omap3_timer, - .restart = omap_prcm_restart, + .timer = &omap3_timer, + .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index 59c0a45f75b0..699caec8f9e2 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -39,9 +39,8 @@ #include <asm/mach/map.h> #include "common.h" -#include <plat/usb.h> #include <linux/platform_data/mtd-nand-omap2.h> -#include <plat/gpmc.h> +#include "gpmc.h" #include "am35xx.h" @@ -49,6 +48,7 @@ #include "control.h" #include "common-board-devices.h" #include "am35xx-emac.h" +#include "gpmc-nand.h" #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) static struct gpio_led cm_t3517_leds[] = { @@ -240,7 +240,7 @@ static struct omap_nand_platform_data cm_t3517_nand_data = { static void __init cm_t3517_init_nand(void) { - if (gpmc_nand_init(&cm_t3517_nand_data) < 0) + if (gpmc_nand_init(&cm_t3517_nand_data, NULL) < 0) pr_err("CM-T3517: NAND initialization failed\n"); } #else @@ -298,5 +298,5 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517") .init_machine = cm_t3517_init, .init_late = am35xx_init_late, .timer = &omap3_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 1fd161e934c7..7667eb749522 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -39,9 +39,8 @@ #include <asm/mach/flash.h> #include "common.h" -#include <plat/gpmc.h> +#include "gpmc.h" #include <linux/platform_data/mtd-nand-omap2.h> -#include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> #include <video/omap-panel-tfp410.h> @@ -55,8 +54,11 @@ #include "sdram-micron-mt46h32m32lf-6.h" #include "mux.h" #include "hsmmc.h" +#include "board-flash.h" #include "common-board-devices.h" +#define NAND_CS 0 + #define OMAP_DM9000_GPIO_IRQ 25 #define OMAP3_DEVKIT_TS_GPIO 27 @@ -621,8 +623,9 @@ static void __init devkit8000_init(void) usb_musb_init(NULL); usbhs_init(&usbhs_bdata); - omap_nand_flash_init(NAND_BUSWIDTH_16, devkit8000_nand_partitions, - ARRAY_SIZE(devkit8000_nand_partitions)); + board_nand_init(devkit8000_nand_partitions, + ARRAY_SIZE(devkit8000_nand_partitions), NAND_CS, + NAND_BUSWIDTH_16, NULL); omap_twl4030_audio_init("omap3beagle"); /* Ensure SDRC pins are mux'd for self-refresh */ @@ -640,5 +643,5 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000") .init_machine = devkit8000_init, .init_late = omap35xx_init_late, .timer = &omap3_secure_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index e642acf9cad0..c33adea0247c 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -17,14 +17,14 @@ #include <linux/mtd/physmap.h> #include <linux/io.h> -#include <plat/cpu.h> -#include <plat/gpmc.h> #include <linux/platform_data/mtd-nand-omap2.h> #include <linux/platform_data/mtd-onenand-omap2.h> -#include <plat/tc.h> +#include "soc.h" #include "common.h" #include "board-flash.h" +#include "gpmc-onenand.h" +#include "gpmc-nand.h" #define REG_FPGA_REV 0x10 #define REG_FPGA_DIP_SWITCH_INPUT2 0x60 @@ -104,36 +104,35 @@ __init board_onenand_init(struct mtd_partition *onenand_parts, defined(CONFIG_MTD_NAND_OMAP2_MODULE) /* Note that all values in this struct are in nanoseconds */ -static struct gpmc_timings nand_timings = { +struct gpmc_timings nand_default_timings[1] = { + { + .sync_clk = 0, - .sync_clk = 0, + .cs_on = 0, + .cs_rd_off = 36, + .cs_wr_off = 36, - .cs_on = 0, - .cs_rd_off = 36, - .cs_wr_off = 36, + .adv_on = 6, + .adv_rd_off = 24, + .adv_wr_off = 36, - .adv_on = 6, - .adv_rd_off = 24, - .adv_wr_off = 36, + .we_off = 30, + .oe_off = 48, - .we_off = 30, - .oe_off = 48, + .access = 54, + .rd_cycle = 72, + .wr_cycle = 72, - .access = 54, - .rd_cycle = 72, - .wr_cycle = 72, - - .wr_access = 30, - .wr_data_mux_bus = 0, + .wr_access = 30, + .wr_data_mux_bus = 0, + }, }; -static struct omap_nand_platform_data board_nand_data = { - .gpmc_t = &nand_timings, -}; +static struct omap_nand_platform_data board_nand_data; void -__init board_nand_init(struct mtd_partition *nand_parts, - u8 nr_parts, u8 cs, int nand_type) +__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, + int nand_type, struct gpmc_timings *gpmc_t) { board_nand_data.cs = cs; board_nand_data.parts = nand_parts; @@ -141,7 +140,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, board_nand_data.devsize = nand_type; board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT; - gpmc_nand_init(&board_nand_data); + gpmc_nand_init(&board_nand_data, gpmc_t); } #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ @@ -238,5 +237,6 @@ void __init board_flash_init(struct flash_partitions partition_info[], pr_err("NAND: Unable to find configuration in GPMC\n"); else board_nand_init(partition_info[2].parts, - partition_info[2].nr_parts, nandcs, nand_type); + partition_info[2].nr_parts, nandcs, + nand_type, nand_default_timings); } diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h index c44b70d52021..2fb5d41a9fae 100644 --- a/arch/arm/mach-omap2/board-flash.h +++ b/arch/arm/mach-omap2/board-flash.h @@ -12,7 +12,7 @@ */ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> -#include <plat/gpmc.h> +#include "gpmc.h" #define PDC_NOR 1 #define PDC_NAND 2 @@ -40,12 +40,14 @@ static inline void board_flash_init(struct flash_partitions part[], #if defined(CONFIG_MTD_NAND_OMAP2) || \ defined(CONFIG_MTD_NAND_OMAP2_MODULE) extern void board_nand_init(struct mtd_partition *nand_parts, - u8 nr_parts, u8 cs, int nand_type); + u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t); +extern struct gpmc_timings nand_default_timings[]; #else static inline void board_nand_init(struct mtd_partition *nand_parts, - u8 nr_parts, u8 cs, int nand_type) + u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t) { } +#define nand_default_timings NULL #endif #if defined(CONFIG_MTD_ONENAND_OMAP2) || \ diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 601ecdfb1cf9..475e14f07216 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -57,7 +57,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)") .init_machine = omap_generic_init, .timer = &omap2_timer, .dt_compat = omap242x_boards_compat, - .restart = omap_prcm_restart, + .restart = omap2xxx_restart, MACHINE_END #endif @@ -76,7 +76,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)") .init_machine = omap_generic_init, .timer = &omap2_timer, .dt_compat = omap243x_boards_compat, - .restart = omap_prcm_restart, + .restart = omap2xxx_restart, MACHINE_END #endif @@ -95,7 +95,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") .init_machine = omap_generic_init, .timer = &omap3_timer, .dt_compat = omap3_boards_compat, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END #endif @@ -134,7 +134,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)") .init_late = omap4430_init_late, .timer = &omap4_timer, .dt_compat = omap4_boards_compat, - .restart = omap_prcm_restart, + .restart = omap44xx_restart, MACHINE_END #endif @@ -154,6 +154,6 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)") .init_machine = omap_generic_init, .timer = &omap5_timer, .dt_compat = omap5_boards_compat, - .restart = omap_prcm_restart, + .restart = omap44xx_restart, MACHINE_END #endif diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 8d04bf851af4..3c1e458f68a1 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -26,14 +26,13 @@ #include <linux/clk.h> #include <linux/io.h> #include <linux/input/matrix_keypad.h> +#include <linux/mfd/menelaus.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/menelaus.h> -#include <plat/dma.h> -#include <plat/gpmc.h> +#include <plat-omap/dma-omap.h> #include "debug-devices.h" #include <video/omapdss.h> @@ -42,6 +41,7 @@ #include "common.h" #include "mux.h" #include "control.h" +#include "gpmc.h" #define H4_FLASH_CS 0 #define H4_SMC91X_CS 1 @@ -386,5 +386,5 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board") .init_machine = omap_h4_init, .init_late = omap2420_init_late, .timer = &omap2_timer, - .restart = omap_prcm_restart, + .restart = omap2xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 48d5e41dfbfa..cea5d5292628 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -29,20 +29,19 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include "common.h" -#include <plat/gpmc.h> -#include <plat/usb.h> - #include <video/omapdss.h> #include <video/omap-panel-tfp410.h> #include <linux/platform_data/mtd-onenand-omap2.h> +#include "common.h" +#include "gpmc.h" #include "mux.h" #include "hsmmc.h" #include "sdram-numonyx-m65kxxxxam.h" #include "common-board-devices.h" #include "board-flash.h" #include "control.h" +#include "gpmc-onenand.h" #define IGEP2_SMSC911X_CS 5 #define IGEP2_SMSC911X_GPIO 176 @@ -175,7 +174,7 @@ static void __init igep_flash_init(void) pr_info("IGEP: initializing NAND memory device\n"); board_nand_init(igep_flash_partitions, ARRAY_SIZE(igep_flash_partitions), - 0, NAND_BUSWIDTH_16); + 0, NAND_BUSWIDTH_16, nand_default_timings); } else if (mux == IGEP_SYSBOOT_ONENAND) { pr_info("IGEP: initializing OneNAND memory device\n"); board_onenand_init(igep_flash_partitions, @@ -652,7 +651,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board") .init_machine = igep_init, .init_late = omap35xx_init_late, .timer = &omap3_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END MACHINE_START(IGEP0030, "IGEP OMAP3 module") @@ -665,5 +664,5 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module") .init_machine = igep_init, .init_late = omap35xx_init_late, .timer = &omap3_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index ee8c3cfb95b3..0869f4f3d3e1 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -35,9 +35,8 @@ #include <asm/mach/map.h> #include "common.h" -#include <plat/gpmc.h> -#include <mach/board-zoom.h> -#include <plat/usb.h> +#include "board-zoom.h" +#include "gpmc.h" #include "gpmc-smsc911x.h" #include <video/omapdss.h> @@ -420,8 +419,8 @@ static void __init omap_ldp_init(void) omap_serial_init(); omap_sdrc_init(NULL, NULL); usb_musb_init(NULL); - board_nand_init(ldp_nand_partitions, - ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0); + board_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions), + ZOOM_NAND_CS, 0, nand_default_timings); omap_hsmmc_init(mmc); ldp_display_init(); @@ -437,5 +436,5 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board") .init_machine = omap_ldp_init, .init_late = omap3430_init_late, .timer = &omap3_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index d95f727ca39a..a4e167c55c1d 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -22,16 +22,17 @@ #include <linux/usb/musb.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/platform_data/mtd-onenand-omap2.h> +#include <linux/mfd/menelaus.h> #include <sound/tlv320aic3x.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> #include "common.h" -#include <plat/menelaus.h> -#include <plat/mmc.h> +#include "mmc.h" #include "mux.h" +#include "gpmc-onenand.h" #define TUSB6010_ASYNC_CS 1 #define TUSB6010_SYNC_CS 4 @@ -689,7 +690,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800") .init_machine = n8x0_init_machine, .init_late = omap2420_init_late, .timer = &omap2_timer, - .restart = omap_prcm_restart, + .restart = omap2xxx_restart, MACHINE_END MACHINE_START(NOKIA_N810, "Nokia N810") @@ -702,7 +703,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810") .init_machine = n8x0_init_machine, .init_late = omap2420_init_late, .timer = &omap2_timer, - .restart = omap_prcm_restart, + .restart = omap2xxx_restart, MACHINE_END MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") @@ -715,5 +716,5 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") .init_machine = n8x0_init_machine, .init_late = omap2420_init_late, .timer = &omap2_timer, - .restart = omap_prcm_restart, + .restart = omap2xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index d41ab98890ff..22c483d5dfa8 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -39,19 +39,22 @@ #include <asm/mach/map.h> #include <asm/mach/flash.h> -#include "common.h" #include <video/omapdss.h> #include <video/omap-panel-tfp410.h> -#include <plat/gpmc.h> #include <linux/platform_data/mtd-nand-omap2.h> -#include <plat/usb.h> -#include <plat/omap_device.h> +#include "common.h" +#include "omap_device.h" +#include "gpmc.h" +#include "soc.h" #include "mux.h" #include "hsmmc.h" #include "pm.h" +#include "board-flash.h" #include "common-board-devices.h" +#define NAND_CS 0 + /* * OMAP3 Beagle revision * Run time detection of Beagle revision is done by reading GPIO. @@ -518,8 +521,9 @@ static void __init omap3_beagle_init(void) usb_musb_init(NULL); usbhs_init(&usbhs_bdata); - omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions, - ARRAY_SIZE(omap3beagle_nand_partitions)); + board_nand_init(omap3beagle_nand_partitions, + ARRAY_SIZE(omap3beagle_nand_partitions), NAND_CS, + NAND_BUSWIDTH_16, NULL); omap_twl4030_audio_init("omap3beagle"); /* Ensure msecure is mux'd to be able to set the RTC. */ @@ -541,5 +545,5 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") .init_machine = omap3_beagle_init, .init_late = omap3_init_late, .timer = &omap3_secure_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index b9b776b6c954..54647d6286b4 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -32,6 +32,7 @@ #include <linux/spi/ads7846.h> #include <linux/i2c/twl.h> #include <linux/usb/otg.h> +#include <linux/usb/musb.h> #include <linux/usb/nop-usb-xceiv.h> #include <linux/smsc911x.h> @@ -45,17 +46,20 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/usb.h> #include <linux/platform_data/mtd-nand-omap2.h> #include "common.h" #include <linux/platform_data/spi-omap2-mcspi.h> #include <video/omapdss.h> #include <video/omap-panel-tfp410.h> +#include "soc.h" #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" #include "hsmmc.h" #include "common-board-devices.h" +#include "board-flash.h" + +#define NAND_CS 0 #define OMAP3_EVM_TS_GPIO 175 #define OMAP3_EVM_EHCI_VBUS 22 @@ -731,8 +735,9 @@ static void __init omap3_evm_init(void) } usb_musb_init(&musb_board_data); usbhs_init(&usbhs_bdata); - omap_nand_flash_init(NAND_BUSWIDTH_16, omap3evm_nand_partitions, - ARRAY_SIZE(omap3evm_nand_partitions)); + board_nand_init(omap3evm_nand_partitions, + ARRAY_SIZE(omap3evm_nand_partitions), NAND_CS, + NAND_BUSWIDTH_16, NULL); omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL); omap3evm_init_smsc911x(); @@ -752,5 +757,5 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM") .init_machine = omap3_evm_init, .init_late = omap35xx_init_late, .timer = &omap3_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c index 7bd8253b5d1d..2a065ba6eb58 100644 --- a/arch/arm/mach-omap2/board-omap3logic.c +++ b/arch/arm/mach-omap2/board-omap3logic.c @@ -34,16 +34,13 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include "gpmc-smsc911x.h" -#include <plat/gpmc.h> -#include <plat/sdrc.h> -#include <plat/usb.h> - #include "common.h" #include "mux.h" #include "hsmmc.h" #include "control.h" #include "common-board-devices.h" +#include "gpmc.h" +#include "gpmc-smsc911x.h" #define OMAP3LOGIC_SMSC911X_CS 1 @@ -235,7 +232,7 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board") .init_machine = omap3logic_init, .init_late = omap35xx_init_late, .timer = &omap3_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board") @@ -248,5 +245,5 @@ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board") .init_machine = omap3logic_init, .init_late = omap35xx_init_late, .timer = &omap3_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 00a1f4ae6e44..a53a6683c1b8 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -42,7 +42,6 @@ #include <asm/mach/map.h> #include "common.h" -#include <plat/usb.h> #include <video/omapdss.h> #include <linux/platform_data/mtd-nand-omap2.h> @@ -50,6 +49,7 @@ #include "sdram-micron-mt46h32m32lf-6.h" #include "hsmmc.h" #include "common-board-devices.h" +#include "gpmc-nand.h" #define PANDORA_WIFI_IRQ_GPIO 21 #define PANDORA_WIFI_NRESET_GPIO 23 @@ -602,7 +602,7 @@ static void __init omap3pandora_init(void) omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL); usbhs_init(&usbhs_bdata); usb_musb_init(NULL); - gpmc_nand_init(&pandora_nand_data); + gpmc_nand_init(&pandora_nand_data, NULL); /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); @@ -619,5 +619,5 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") .init_machine = omap3pandora_init, .init_late = omap35xx_init_late, .timer = &omap3_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index 731235eb319e..d8638b3b4f94 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -40,9 +40,8 @@ #include <asm/mach/flash.h> #include "common.h" -#include <plat/gpmc.h> +#include "gpmc.h" #include <linux/platform_data/mtd-nand-omap2.h> -#include <plat/usb.h> #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> #include <video/omap-panel-tfp410.h> @@ -428,5 +427,5 @@ MACHINE_START(SBC3530, "OMAP3 STALKER") .init_machine = omap3_stalker_init, .init_late = omap35xx_init_late, .timer = &omap3_secure_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 944ffc436577..263cb9cfbf37 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -44,12 +44,12 @@ #include <asm/system_info.h> #include "common.h" -#include <plat/gpmc.h> +#include "gpmc.h" #include <linux/platform_data/mtd-nand-omap2.h> -#include <plat/usb.h> #include "mux.h" #include "hsmmc.h" +#include "board-flash.h" #include "common-board-devices.h" #include <asm/setup.h> @@ -59,6 +59,8 @@ #define TB_BL_PWM_TIMER 9 #define TB_KILL_POWER_GPIO 168 +#define NAND_CS 0 + static unsigned long touchbook_revision; static struct mtd_partition omap3touchbook_nand_partitions[] = { @@ -365,8 +367,9 @@ static void __init omap3_touchbook_init(void) omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata); usb_musb_init(NULL); usbhs_init(&usbhs_bdata); - omap_nand_flash_init(NAND_BUSWIDTH_16, omap3touchbook_nand_partitions, - ARRAY_SIZE(omap3touchbook_nand_partitions)); + board_nand_init(omap3touchbook_nand_partitions, + ARRAY_SIZE(omap3touchbook_nand_partitions), NAND_CS, + NAND_BUSWIDTH_16, NULL); /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); @@ -384,5 +387,5 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") .init_machine = omap3_touchbook_init, .init_late = omap3430_init_late, .timer = &omap3_secure_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index bfcd397e233c..12a3a24d5bb5 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -29,6 +29,7 @@ #include <linux/regulator/machine.h> #include <linux/regulator/fixed.h> #include <linux/ti_wilink_st.h> +#include <linux/usb/musb.h> #include <linux/wl12xx.h> #include <linux/platform_data/omap-abe-twl6040.h> @@ -38,12 +39,11 @@ #include <asm/mach/map.h> #include <video/omapdss.h> -#include "common.h" -#include <plat/usb.h> -#include <plat/mmc.h> #include <video/omap-panel-tfp410.h> +#include "common.h" #include "soc.h" +#include "mmc.h" #include "hsmmc.h" #include "control.h" #include "mux.h" @@ -524,5 +524,5 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board") .init_machine = omap4_panda_init, .init_late = omap4430_init_late, .timer = &omap4_timer, - .restart = omap_prcm_restart, + .restart = omap44xx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index b700685762b5..140b73094aff 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -49,14 +49,17 @@ #include <video/omapdss.h> #include <video/omap-panel-generic-dpi.h> #include <video/omap-panel-tfp410.h> -#include <plat/gpmc.h> -#include <plat/usb.h> +#include "common.h" #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" +#include "gpmc.h" #include "hsmmc.h" +#include "board-flash.h" #include "common-board-devices.h" +#define NAND_CS 0 + #define OVERO_GPIO_BT_XGATE 15 #define OVERO_GPIO_W2W_NRESET 16 #define OVERO_GPIO_PENDOWN 114 @@ -495,8 +498,8 @@ static void __init overo_init(void) omap_serial_init(); omap_sdrc_init(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); - omap_nand_flash_init(0, overo_nand_partitions, - ARRAY_SIZE(overo_nand_partitions)); + board_nand_init(overo_nand_partitions, + ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL); usb_musb_init(NULL); usbhs_init(&usbhs_bdata); overo_spi_init(); @@ -550,5 +553,5 @@ MACHINE_START(OVERO, "Gumstix Overo") .init_machine = overo_init, .init_late = omap35xx_init_late, .timer = &omap3_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c index 45997bfbcbd2..cbcb1b2dc31f 100644 --- a/arch/arm/mach-omap2/board-rm680.c +++ b/arch/arm/mach-omap2/board-rm680.c @@ -22,17 +22,14 @@ #include <asm/mach/arch.h> #include <asm/mach-types.h> -#include <plat/i2c.h> -#include <plat/mmc.h> -#include <plat/usb.h> -#include <plat/gpmc.h> #include "common.h" -#include <plat/serial.h> - #include "mux.h" +#include "gpmc.h" +#include "mmc.h" #include "hsmmc.h" #include "sdram-nokia.h" #include "common-board-devices.h" +#include "gpmc-onenand.h" static struct regulator_consumer_supply rm680_vemmc_consumers[] = { REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), @@ -151,7 +148,7 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board") .init_machine = rm680_init, .init_late = omap3630_init_late, .timer = &omap3_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END MACHINE_START(NOKIA_RM696, "Nokia RM-696 board") @@ -164,5 +161,5 @@ MACHINE_START(NOKIA_RM696, "Nokia RM-696 board") .init_machine = rm680_init, .init_late = omap3630_init_late, .timer = &omap3_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 020e03c95bfe..07005fe40a2a 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -31,9 +31,7 @@ #include <asm/system_info.h> #include "common.h" -#include <plat/dma.h> -#include <plat/gpmc.h> -#include <plat/omap-pm.h> +#include <plat-omap/dma-omap.h> #include "gpmc-smc91x.h" #include "board-rx51.h" @@ -52,8 +50,11 @@ #endif #include "mux.h" +#include "omap-pm.h" #include "hsmmc.h" #include "common-board-devices.h" +#include "gpmc.h" +#include "gpmc-onenand.h" #define SYSTEM_REV_B_USES_VAUX3 0x1699 #define SYSTEM_REV_S_USES_VAUX3 0x8 diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 7bbb05d9689b..bf8f74b0ce3e 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -17,18 +17,18 @@ #include <linux/io.h> #include <linux/gpio.h> #include <linux/leds.h> +#include <linux/usb/musb.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include "common.h" -#include <plat/dma.h> -#include <plat/gpmc.h> -#include <plat/usb.h> +#include <plat-omap/dma-omap.h> +#include "common.h" #include "mux.h" +#include "gpmc.h" #include "pm.h" #include "sdram-nokia.h" @@ -127,5 +127,5 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") .init_machine = rx51_init, .init_late = omap3430_init_late, .timer = &omap3_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c index c4f8833b4c3c..1a3e056d63a7 100644 --- a/arch/arm/mach-omap2/board-ti8168evm.c +++ b/arch/arm/mach-omap2/board-ti8168evm.c @@ -14,13 +14,14 @@ */ #include <linux/kernel.h> #include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/usb/musb.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include "common.h" -#include <plat/usb.h> static struct omap_musb_board_data musb_board_data = { .set_phy_power = ti81xx_musb_phy_power, @@ -45,7 +46,7 @@ MACHINE_START(TI8168EVM, "ti8168evm") .timer = &omap3_timer, .init_machine = ti81xx_evm_init, .init_late = ti81xx_init_late, - .restart = omap_prcm_restart, + .restart = omap44xx_restart, MACHINE_END MACHINE_START(TI8148EVM, "ti8148evm") @@ -57,5 +58,5 @@ MACHINE_START(TI8148EVM, "ti8148evm") .timer = &omap3_timer, .init_machine = ti81xx_evm_init, .init_late = ti81xx_init_late, - .restart = omap_prcm_restart, + .restart = omap44xx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c index afb2278a29f6..42e5f231a799 100644 --- a/arch/arm/mach-omap2/board-zoom-debugboard.c +++ b/arch/arm/mach-omap2/board-zoom-debugboard.c @@ -17,10 +17,10 @@ #include <linux/regulator/fixed.h> #include <linux/regulator/machine.h> -#include <plat/gpmc.h> +#include "gpmc.h" #include "gpmc-smsc911x.h" -#include <mach/board-zoom.h> +#include "board-zoom.h" #include "soc.h" #include "common.h" diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c index b940ab2259fb..1c7c834a5b5f 100644 --- a/arch/arm/mach-omap2/board-zoom-display.c +++ b/arch/arm/mach-omap2/board-zoom-display.c @@ -16,8 +16,9 @@ #include <linux/spi/spi.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <video/omapdss.h> -#include <mach/board-zoom.h> +#include "board-zoom.h" +#include "soc.h" #include "common.h" #define LCD_PANEL_RESET_GPIO_PROD 96 diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index c166fe1fdff9..26e07addc9d7 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -26,9 +26,8 @@ #include <asm/mach/map.h> #include "common.h" -#include <plat/usb.h> -#include <mach/board-zoom.h> +#include "board-zoom.h" #include "mux.h" #include "hsmmc.h" diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c index 4994438e1f46..d7fa31e67238 100644 --- a/arch/arm/mach-omap2/board-zoom.c +++ b/arch/arm/mach-omap2/board-zoom.c @@ -22,9 +22,8 @@ #include <asm/mach/arch.h> #include "common.h" -#include <plat/usb.h> -#include <mach/board-zoom.h> +#include "board-zoom.h" #include "board-flash.h" #include "mux.h" @@ -113,8 +112,9 @@ static void __init omap_zoom_init(void) usbhs_init(&usbhs_bdata); } - board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions), - ZOOM_NAND_CS, NAND_BUSWIDTH_16); + board_nand_init(zoom_nand_partitions, + ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS, + NAND_BUSWIDTH_16, nand_default_timings); zoom_debugboard_init(); zoom_peripherals_init(); @@ -138,7 +138,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") .init_machine = omap_zoom_init, .init_late = omap3430_init_late, .timer = &omap3_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") @@ -151,5 +151,5 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") .init_machine = omap_zoom_init, .init_late = omap3630_init_late, .timer = &omap3_timer, - .restart = omap_prcm_restart, + .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/board-zoom.h index 2e9486940ead..2e9486940ead 100644 --- a/arch/arm/mach-omap2/include/mach/board-zoom.h +++ b/arch/arm/mach-omap2/board-zoom.h diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c new file mode 100644 index 000000000000..7e5febe456d9 --- /dev/null +++ b/arch/arm/mach-omap2/cclock2420_data.c @@ -0,0 +1,1950 @@ +/* + * OMAP2420 clock data + * + * Copyright (C) 2005-2012 Texas Instruments, Inc. + * Copyright (C) 2004-2011 Nokia Corporation + * + * Contacts: + * Richard Woodruff <r-woodruff2@ti.com> + * Paul Walmsley + * Updated to COMMON clk format by Rajendra Nayak <rnayak@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/clk-private.h> +#include <linux/list.h> + +#include "soc.h" +#include "iomap.h" +#include "clock.h" +#include "clock2xxx.h" +#include "opp2xxx.h" +#include "cm2xxx.h" +#include "prm2xxx.h" +#include "prm-regbits-24xx.h" +#include "cm-regbits-24xx.h" +#include "sdrc.h" +#include "control.h" + +#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR + +/* + * 2420 clock tree. + * + * NOTE:In many cases here we are assigning a 'default' parent. In + * many cases the parent is selectable. The set parent calls will + * also switch sources. + * + * Several sources are given initial rates which may be wrong, this will + * be fixed up in the init func. + * + * Things are broadly separated below by clock domains. It is + * noteworthy that most peripherals have dependencies on multiple clock + * domains. Many get their interface clocks from the L4 domain, but get + * functional clocks from fixed sources or other core domain derived + * clocks. + */ + +DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0); + +DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); + +DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); + +static struct clk osc_ck; + +static const struct clk_ops osc_ck_ops = { + .recalc_rate = &omap2_osc_clk_recalc, +}; + +static struct clk_hw_omap osc_ck_hw = { + .hw = { + .clk = &osc_ck, + }, +}; + +static struct clk osc_ck = { + .name = "osc_ck", + .ops = &osc_ck_ops, + .hw = &osc_ck_hw.hw, + .flags = CLK_IS_ROOT, +}; + +DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); + +static struct clk sys_ck; + +static const char *sys_ck_parent_names[] = { + "osc_ck", +}; + +static const struct clk_ops sys_ck_ops = { + .init = &omap2_init_clk_clkdm, + .recalc_rate = &omap2xxx_sys_clk_recalc, +}; + +DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm"); +DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops); + +static struct dpll_data dpll_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .mult_mask = OMAP24XX_DPLL_MULT_MASK, + .div1_mask = OMAP24XX_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_mask = OMAP24XX_EN_DPLL_MASK, + .max_multiplier = 1023, + .min_divider = 1, + .max_divider = 16, +}; + +static struct clk dpll_ck; + +static const char *dpll_ck_parent_names[] = { + "sys_ck", +}; + +static const struct clk_ops dpll_ck_ops = { + .init = &omap2_init_clk_clkdm, + .get_parent = &omap2_init_dpll_parent, + .recalc_rate = &omap2_dpllcore_recalc, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap2_reprogram_dpllcore, +}; + +static struct clk_hw_omap dpll_ck_hw = { + .hw = { + .clk = &dpll_ck, + }, + .ops = &clkhwops_omap2xxx_dpll, + .dpll_data = &dpll_dd, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops); + +static struct clk core_ck; + +static const char *core_ck_parent_names[] = { + "dpll_ck", +}; + +static const struct clk_ops core_ck_ops = { + .init = &omap2_init_clk_clkdm, +}; + +DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm"); +DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops); + +DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk aes_ick; + +static const char *aes_ick_parent_names[] = { + "l4_ck", +}; + +static const struct clk_ops aes_ick_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, +}; + +static struct clk_hw_omap aes_ick_hw = { + .hw = { + .clk = &aes_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_AES_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk apll54_ck; + +static const struct clk_ops apll54_ck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_clk_apll54_enable, + .disable = &omap2_clk_apll54_disable, + .recalc_rate = &omap2_clk_apll54_recalc, +}; + +static struct clk_hw_omap apll54_ck_hw = { + .hw = { + .clk = &apll54_ck, + }, + .ops = &clkhwops_apll54, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops); + +static struct clk apll96_ck; + +static const struct clk_ops apll96_ck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_clk_apll96_enable, + .disable = &omap2_clk_apll96_disable, + .recalc_rate = &omap2_clk_apll96_recalc, +}; + +static struct clk_hw_omap apll96_ck_hw = { + .hw = { + .clk = &apll96_ck, + }, + .ops = &clkhwops_apll96, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops); + +static struct clk func_96m_ck; + +static const char *func_96m_ck_parent_names[] = { + "apll96_ck", +}; + +DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm"); +DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops); + +static struct clk cam_fck; + +static const char *cam_fck_parent_names[] = { + "func_96m_ck", +}; + +static struct clk_hw_omap cam_fck_hw = { + .hw = { + .clk = &cam_fck, + }, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_CAM_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk cam_ick; + +static struct clk_hw_omap cam_ick_hw = { + .hw = { + .clk = &cam_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_CAM_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk des_ick; + +static struct clk_hw_omap des_ick_hw = { + .hw = { + .clk = &des_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_DES_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate dsp_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 6, .val = 6, .flags = RATE_IN_242X }, + { .div = 8, .val = 8, .flags = RATE_IN_242X }, + { .div = 12, .val = 12, .flags = RATE_IN_242X }, + { .div = 0 } +}; + +static const struct clksel dsp_fck_clksel[] = { + { .parent = &core_ck, .rates = dsp_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *dsp_fck_parent_names[] = { + "core_ck", +}; + +static const struct clk_ops dsp_fck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, +}; + +DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + OMAP24XX_CLKSEL_DSP_MASK, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), + OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, + dsp_fck_parent_names, dsp_fck_ops); + +static const struct clksel dsp_ick_clksel[] = { + { .parent = &dsp_fck, .rates = dsp_ick_rates }, + { .parent = NULL }, +}; + +static const char *dsp_ick_parent_names[] = { + "dsp_fck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(dsp_ick, "dsp_clkdm", dsp_ick_clksel, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + OMAP24XX_CLKSEL_DSP_IF_MASK, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), + OMAP2420_EN_DSP_IPI_SHIFT, &clkhwops_iclk_wait, + dsp_ick_parent_names, dsp_fck_ops); + +static const struct clksel_rate dss1_fck_sys_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate dss1_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 5, .val = 5, .flags = RATE_IN_24XX }, + { .div = 6, .val = 6, .flags = RATE_IN_24XX }, + { .div = 8, .val = 8, .flags = RATE_IN_24XX }, + { .div = 9, .val = 9, .flags = RATE_IN_24XX }, + { .div = 12, .val = 12, .flags = RATE_IN_24XX }, + { .div = 16, .val = 16, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel dss1_fck_clksel[] = { + { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, + { .parent = &core_ck, .rates = dss1_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *dss1_fck_parent_names[] = { + "sys_ck", "core_ck", +}; + +static struct clk dss1_fck; + +static const struct clk_ops dss1_fck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_DSS1_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_DSS1_SHIFT, NULL, + dss1_fck_parent_names, dss1_fck_ops); + +static const struct clksel_rate dss2_fck_sys_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate dss2_fck_48m_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate func_48m_apll96_rates[] = { + { .div = 2, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate func_48m_alt_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel func_48m_clksel[] = { + { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, + { .parent = &alt_ck, .rates = func_48m_alt_rates }, + { .parent = NULL }, +}; + +static const char *func_48m_ck_parent_names[] = { + "apll96_ck", "alt_ck", +}; + +static struct clk func_48m_ck; + +static const struct clk_ops func_48m_ck_ops = { + .init = &omap2_init_clk_clkdm, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap func_48m_ck_hw = { + .hw = { + .clk = &func_48m_ck, + }, + .clksel = func_48m_clksel, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_mask = OMAP24XX_48M_SOURCE_MASK, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops); + +static const struct clksel dss2_fck_clksel[] = { + { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, + { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, + { .parent = NULL }, +}; + +static const char *dss2_fck_parent_names[] = { + "sys_ck", "func_48m_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_DSS2_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_DSS2_SHIFT, NULL, + dss2_fck_parent_names, dss1_fck_ops); + +static const char *func_54m_ck_parent_names[] = { + "apll54_ck", "alt_ck", +}; + +DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0, + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, + 0x0, NULL); + +static struct clk dss_54m_fck; + +static const char *dss_54m_fck_parent_names[] = { + "func_54m_ck", +}; + +static struct clk_hw_omap dss_54m_fck_hw = { + .hw = { + .clk = &dss_54m_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_TV_SHIFT, + .clkdm_name = "dss_clkdm", +}; + +DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops); + +static struct clk dss_ick; + +static struct clk_hw_omap dss_ick_hw = { + .hw = { + .clk = &dss_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_DSS1_SHIFT, + .clkdm_name = "dss_clkdm", +}; + +DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk eac_fck; + +static struct clk_hw_omap eac_fck_hw = { + .hw = { + .clk = &eac_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP2420_EN_EAC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk eac_ick; + +static struct clk_hw_omap eac_ick_hw = { + .hw = { + .clk = &eac_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_EAC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk emul_ck; + +static struct clk_hw_omap emul_ck_hw = { + .hw = { + .clk = &emul_ck, + }, + .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL, + .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops); + +DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4); + +static struct clk fac_fck; + +static const char *fac_fck_parent_names[] = { + "func_12m_ck", +}; + +static struct clk_hw_omap fac_fck_hw = { + .hw = { + .clk = &fac_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_FAC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops); + +static struct clk fac_ick; + +static struct clk_hw_omap fac_ick_hw = { + .hw = { + .clk = &fac_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_FAC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel gfx_fck_clksel[] = { + { .parent = &core_l3_ck, .rates = gfx_l3_rates }, + { .parent = NULL }, +}; + +static const char *gfx_2d_fck_parent_names[] = { + "core_l3_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel, + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), + OMAP_CLKSEL_GFX_MASK, + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + OMAP24XX_EN_2D_SHIFT, &clkhwops_wait, + gfx_2d_fck_parent_names, dsp_fck_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel, + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), + OMAP_CLKSEL_GFX_MASK, + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + OMAP24XX_EN_3D_SHIFT, &clkhwops_wait, + gfx_2d_fck_parent_names, dsp_fck_ops); + +static struct clk gfx_ick; + +static const char *gfx_ick_parent_names[] = { + "core_l3_ck", +}; + +static struct clk_hw_omap gfx_ick_hw = { + .hw = { + .clk = &gfx_ick, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), + .enable_bit = OMAP_EN_GFX_SHIFT, + .clkdm_name = "gfx_clkdm", +}; + +DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops); + +static struct clk gpios_fck; + +static const char *gpios_fck_parent_names[] = { + "func_32k_ck", +}; + +static struct clk_hw_omap gpios_fck_hw = { + .hw = { + .clk = &gpios_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops); + +static struct clk wu_l4_ick; + +DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm"); +DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops); + +static struct clk gpios_ick; + +static const char *gpios_ick_parent_names[] = { + "wu_l4_ick", +}; + +static struct clk_hw_omap gpios_ick_hw = { + .hw = { + .clk = &gpios_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk gpmc_fck; + +static struct clk_hw_omap gpmc_fck_hw = { + .hw = { + .clk = &gpmc_fck, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops); + +static const struct clksel_rate gpt_alt_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel omap24xx_gpt_clksel[] = { + { .parent = &func_32k_ck, .rates = gpt_32k_rates }, + { .parent = &sys_ck, .rates = gpt_sys_rates }, + { .parent = &alt_ck, .rates = gpt_alt_rates }, + { .parent = NULL }, +}; + +static const char *gpt10_fck_parent_names[] = { + "func_32k_ck", "sys_ck", "alt_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT10_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt10_ick; + +static struct clk_hw_omap gpt10_ick_hw = { + .hw = { + .clk = &gpt10_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT10_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT11_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt11_ick; + +static struct clk_hw_omap gpt11_ick_hw = { + .hw = { + .clk = &gpt11_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT11_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT12_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt12_ick; + +static struct clk_hw_omap gpt12_ick_hw = { + .hw = { + .clk = &gpt12_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT12_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clk_ops gpt1_fck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_GPT1_MASK, + OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, gpt1_fck_ops); + +static struct clk gpt1_ick; + +static struct clk_hw_omap gpt1_ick_hw = { + .hw = { + .clk = &gpt1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_GPT1_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT2_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt2_ick; + +static struct clk_hw_omap gpt2_ick_hw = { + .hw = { + .clk = &gpt2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT3_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt3_ick; + +static struct clk_hw_omap gpt3_ick_hw = { + .hw = { + .clk = &gpt3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT4_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt4_ick; + +static struct clk_hw_omap gpt4_ick_hw = { + .hw = { + .clk = &gpt4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT5_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt5_ick; + +static struct clk_hw_omap gpt5_ick_hw = { + .hw = { + .clk = &gpt5_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT5_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT6_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt6_ick; + +static struct clk_hw_omap gpt6_ick_hw = { + .hw = { + .clk = &gpt6_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT6_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT7_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt7_ick; + +static struct clk_hw_omap gpt7_ick_hw = { + .hw = { + .clk = &gpt7_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT7_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT8_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt8_ick; + +static struct clk_hw_omap gpt8_ick_hw = { + .hw = { + .clk = &gpt8_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT8_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT9_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt9_ick; + +static struct clk_hw_omap gpt9_ick_hw = { + .hw = { + .clk = &gpt9_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT9_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk hdq_fck; + +static struct clk_hw_omap hdq_fck_hw = { + .hw = { + .clk = &hdq_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_HDQ_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops); + +static struct clk hdq_ick; + +static struct clk_hw_omap hdq_ick_hw = { + .hw = { + .clk = &hdq_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_HDQ_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk i2c1_fck; + +static struct clk_hw_omap i2c1_fck_hw = { + .hw = { + .clk = &i2c1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP2420_EN_I2C1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops); + +static struct clk i2c1_ick; + +static struct clk_hw_omap i2c1_ick_hw = { + .hw = { + .clk = &i2c1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_I2C1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk i2c2_fck; + +static struct clk_hw_omap i2c2_fck_hw = { + .hw = { + .clk = &i2c2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP2420_EN_I2C2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops); + +static struct clk i2c2_ick; + +static struct clk_hw_omap i2c2_ick_hw = { + .hw = { + .clk = &i2c2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_I2C2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + OMAP2420_CLKSEL_IVA_MASK, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), + OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait, + dsp_fck_parent_names, dsp_fck_ops); + +static struct clk iva1_mpu_int_ifck; + +static const char *iva1_mpu_int_ifck_parent_names[] = { + "iva1_ifck", +}; + +static const struct clk_ops iva1_mpu_int_ifck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap_fixed_divisor_recalc, +}; + +static struct clk_hw_omap iva1_mpu_int_ifck_hw = { + .hw = { + .clk = &iva1_mpu_int_ifck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), + .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, + .clkdm_name = "iva1_clkdm", + .fixed_div = 2, +}; + +DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names, + iva1_mpu_int_ifck_ops); + +static struct clk mailboxes_ick; + +static struct clk_hw_omap mailboxes_ick_hw = { + .hw = { + .clk = &mailboxes_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate common_mcbsp_96m_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel mcbsp_fck_clksel[] = { + { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp1_fck_parent_names[] = { + "func_96m_ck", "mcbsp_clks", +}; + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + OMAP2_MCBSP1_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp1_ick; + +static struct clk_hw_omap mcbsp1_ick_hw = { + .hw = { + .clk = &mcbsp1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + OMAP2_MCBSP2_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp2_ick; + +static struct clk_hw_omap mcbsp2_ick_hw = { + .hw = { + .clk = &mcbsp2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mcspi1_fck; + +static const char *mcspi1_fck_parent_names[] = { + "func_48m_ck", +}; + +static struct clk_hw_omap mcspi1_fck_hw = { + .hw = { + .clk = &mcspi1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk mcspi1_ick; + +static struct clk_hw_omap mcspi1_ick_hw = { + .hw = { + .clk = &mcspi1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mcspi2_fck; + +static struct clk_hw_omap mcspi2_fck_hw = { + .hw = { + .clk = &mcspi2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk mcspi2_ick; + +static struct clk_hw_omap mcspi2_ick_hw = { + .hw = { + .clk = &mcspi2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mmc_fck; + +static struct clk_hw_omap mmc_fck_hw = { + .hw = { + .clk = &mmc_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP2420_EN_MMC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk mmc_ick; + +static struct clk_hw_omap mmc_ick_hw = { + .hw = { + .clk = &mmc_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_MMC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmc_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0, + OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), + OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk mpu_wdt_fck; + +static struct clk_hw_omap mpu_wdt_fck_hw = { + .hw = { + .clk = &mpu_wdt_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops); + +static struct clk mpu_wdt_ick; + +static struct clk_hw_omap mpu_wdt_ick_hw = { + .hw = { + .clk = &mpu_wdt_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk mspro_fck; + +static struct clk_hw_omap mspro_fck_hw = { + .hw = { + .clk = &mspro_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk mspro_ick; + +static struct clk_hw_omap mspro_ick_hw = { + .hw = { + .clk = &mspro_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk omapctrl_ick; + +static struct clk_hw_omap omapctrl_ick_hw = { + .hw = { + .clk = &omapctrl_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk pka_ick; + +static struct clk_hw_omap pka_ick_hw = { + .hw = { + .clk = &pka_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_PKA_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk rng_ick; + +static struct clk_hw_omap rng_ick_hw = { + .hw = { + .clk = &rng_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_RNG_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk sdma_fck; + +DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm"); +DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops); + +static struct clk sdma_ick; + +static struct clk_hw_omap sdma_ick_hw = { + .hw = { + .clk = &sdma_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops); + +static struct clk sdrc_ick; + +static struct clk_hw_omap sdrc_ick_hw = { + .hw = { + .clk = &sdrc_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops); + +static struct clk sha_ick; + +static struct clk_hw_omap sha_ick_hw = { + .hw = { + .clk = &sha_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_SHA_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk ssi_l4_ick; + +static struct clk_hw_omap ssi_l4_ick_hw = { + .hw = { + .clk = &ssi_l4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP24XX_EN_SSI_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 6, .val = 6, .flags = RATE_IN_242X }, + { .div = 8, .val = 8, .flags = RATE_IN_242X }, + { .div = 0 } +}; + +static const struct clksel ssi_ssr_sst_fck_clksel[] = { + { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *ssi_ssr_sst_fck_parent_names[] = { + "core_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm", + ssi_ssr_sst_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_SSI_MASK, + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait, + ssi_ssr_sst_fck_parent_names, dsp_fck_ops); + +static struct clk sync_32k_ick; + +static struct clk_hw_omap sync_32k_ick_hw = { + .hw = { + .clk = &sync_32k_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate common_clkout_src_core_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_clkout_src_sys_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_clkout_src_96m_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_clkout_src_54m_rates[] = { + { .div = 1, .val = 3, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel common_clkout_src_clksel[] = { + { .parent = &core_ck, .rates = common_clkout_src_core_rates }, + { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, + { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, + { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, + { .parent = NULL }, +}; + +static const char *sys_clkout_src_parent_names[] = { + "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel, + OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK, + OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT, + NULL, sys_clkout_src_parent_names, gpt1_fck_ops); + +DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0, + OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT, + OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm", + common_clkout_src_clksel, OMAP2420_PRCM_CLKOUT_CTRL, + OMAP2420_CLKOUT2_SOURCE_MASK, + OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_EN_SHIFT, + NULL, sys_clkout_src_parent_names, gpt1_fck_ops); + +DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0, + OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT, + OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +static struct clk uart1_fck; + +static struct clk_hw_omap uart1_fck_hw = { + .hw = { + .clk = &uart1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_UART1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk uart1_ick; + +static struct clk_hw_omap uart1_ick_hw = { + .hw = { + .clk = &uart1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_UART1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk uart2_fck; + +static struct clk_hw_omap uart2_fck_hw = { + .hw = { + .clk = &uart2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_UART2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk uart2_ick; + +static struct clk_hw_omap uart2_ick_hw = { + .hw = { + .clk = &uart2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_UART2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk uart3_fck; + +static struct clk_hw_omap uart3_fck_hw = { + .hw = { + .clk = &uart3_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP24XX_EN_UART3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk uart3_ick; + +static struct clk_hw_omap uart3_ick_hw = { + .hw = { + .clk = &uart3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP24XX_EN_UART3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk usb_fck; + +static struct clk_hw_omap usb_fck_hw = { + .hw = { + .clk = &usb_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP24XX_EN_USB_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel usb_l4_ick_clksel[] = { + { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, + { .parent = NULL }, +}; + +static const char *usb_l4_ick_parent_names[] = { + "core_l3_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_USB_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait, + usb_l4_ick_parent_names, dsp_fck_ops); + +static struct clk virt_prcm_set; + +static const char *virt_prcm_set_parent_names[] = { + "mpu_ck", +}; + +static const struct clk_ops virt_prcm_set_ops = { + .recalc_rate = &omap2_table_mpu_recalc, + .set_rate = &omap2_select_table_rate, + .round_rate = &omap2_round_to_table_rate, +}; + +DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL); +DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops); + +static const struct clksel_rate vlynq_fck_96m_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_242X }, + { .div = 0 } +}; + +static const struct clksel_rate vlynq_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_242X }, + { .div = 2, .val = 2, .flags = RATE_IN_242X }, + { .div = 3, .val = 3, .flags = RATE_IN_242X }, + { .div = 4, .val = 4, .flags = RATE_IN_242X }, + { .div = 6, .val = 6, .flags = RATE_IN_242X }, + { .div = 8, .val = 8, .flags = RATE_IN_242X }, + { .div = 9, .val = 9, .flags = RATE_IN_242X }, + { .div = 12, .val = 12, .flags = RATE_IN_242X }, + { .div = 16, .val = 16, .flags = RATE_IN_242X }, + { .div = 18, .val = 18, .flags = RATE_IN_242X }, + { .div = 0 } +}; + +static const struct clksel vlynq_fck_clksel[] = { + { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, + { .parent = &core_ck, .rates = vlynq_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *vlynq_fck_parent_names[] = { + "func_96m_ck", "core_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP2420_CLKSEL_VLYNQ_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait, + vlynq_fck_parent_names, dss1_fck_ops); + +static struct clk vlynq_ick; + +static struct clk_hw_omap vlynq_ick_hw = { + .hw = { + .clk = &vlynq_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops); + +static struct clk wdt1_ick; + +static struct clk_hw_omap wdt1_ick_hw = { + .hw = { + .clk = &wdt1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_WDT1_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk wdt1_osc_ck; + +static const struct clk_ops wdt1_osc_ck_ops = {}; + +DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL); +DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops); + +static struct clk wdt3_fck; + +static struct clk_hw_omap wdt3_fck_hw = { + .hw = { + .clk = &wdt3_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP2420_EN_WDT3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops); + +static struct clk wdt3_ick; + +static struct clk_hw_omap wdt3_ick_hw = { + .hw = { + .clk = &wdt3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_WDT3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk wdt4_fck; + +static struct clk_hw_omap wdt4_fck_hw = { + .hw = { + .clk = &wdt4_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_WDT4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops); + +static struct clk wdt4_ick; + +static struct clk_hw_omap wdt4_ick_hw = { + .hw = { + .clk = &wdt4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_WDT4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops); + +/* + * clkdev integration + */ + +static struct omap_clk omap2420_clks[] = { + /* external root sources */ + CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X), + CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X), + CLK(NULL, "osc_ck", &osc_ck, CK_242X), + CLK(NULL, "sys_ck", &sys_ck, CK_242X), + CLK(NULL, "alt_ck", &alt_ck, CK_242X), + CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X), + /* internal analog sources */ + CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), + CLK(NULL, "apll96_ck", &apll96_ck, CK_242X), + CLK(NULL, "apll54_ck", &apll54_ck, CK_242X), + /* internal prcm root sources */ + CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), + CLK(NULL, "core_ck", &core_ck, CK_242X), + CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), + CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), + CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), + CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X), + CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X), + CLK(NULL, "sys_clkout", &sys_clkout, CK_242X), + CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), + CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), + CLK(NULL, "emul_ck", &emul_ck, CK_242X), + /* mpu domain clocks */ + CLK(NULL, "mpu_ck", &mpu_ck, CK_242X), + /* dsp domain clocks */ + CLK(NULL, "dsp_fck", &dsp_fck, CK_242X), + CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), + CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), + CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), + /* GFX domain clocks */ + CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X), + CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), + CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), + /* DSS domain clocks */ + CLK("omapdss_dss", "ick", &dss_ick, CK_242X), + CLK(NULL, "dss_ick", &dss_ick, CK_242X), + CLK(NULL, "dss1_fck", &dss1_fck, CK_242X), + CLK(NULL, "dss2_fck", &dss2_fck, CK_242X), + CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X), + /* L3 domain clocks */ + CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), + CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), + CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X), + /* L4 domain clocks */ + CLK(NULL, "l4_ck", &l4_ck, CK_242X), + CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X), + CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X), + /* virtual meta-group clock */ + CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), + /* general l4 interface ck, multi-parent functional clk */ + CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X), + CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X), + CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X), + CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X), + CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X), + CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X), + CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X), + CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X), + CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X), + CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X), + CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X), + CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X), + CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X), + CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X), + CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X), + CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X), + CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X), + CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X), + CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X), + CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X), + CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X), + CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X), + CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), + CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), + CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X), + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X), + CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), + CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X), + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X), + CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), + CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X), + CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X), + CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), + CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X), + CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X), + CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), + CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), + CLK(NULL, "uart2_ick", &uart2_ick, CK_242X), + CLK(NULL, "uart2_fck", &uart2_fck, CK_242X), + CLK(NULL, "uart3_ick", &uart3_ick, CK_242X), + CLK(NULL, "uart3_fck", &uart3_fck, CK_242X), + CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), + CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), + CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), + CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X), + CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X), + CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), + CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), + CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), + CLK("omap24xxcam", "fck", &cam_fck, CK_242X), + CLK(NULL, "cam_fck", &cam_fck, CK_242X), + CLK("omap24xxcam", "ick", &cam_ick, CK_242X), + CLK(NULL, "cam_ick", &cam_ick, CK_242X), + CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X), + CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X), + CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X), + CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), + CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), + CLK(NULL, "mspro_ick", &mspro_ick, CK_242X), + CLK(NULL, "mspro_fck", &mspro_fck, CK_242X), + CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), + CLK(NULL, "mmc_ick", &mmc_ick, CK_242X), + CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), + CLK(NULL, "mmc_fck", &mmc_fck, CK_242X), + CLK(NULL, "fac_ick", &fac_ick, CK_242X), + CLK(NULL, "fac_fck", &fac_fck, CK_242X), + CLK(NULL, "eac_ick", &eac_ick, CK_242X), + CLK(NULL, "eac_fck", &eac_fck, CK_242X), + CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), + CLK(NULL, "hdq_ick", &hdq_ick, CK_242X), + CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X), + CLK(NULL, "hdq_fck", &hdq_fck, CK_242X), + CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X), + CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X), + CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X), + CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X), + CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X), + CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X), + CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), + CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), + CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), + CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X), + CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), + CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), + CLK(NULL, "des_ick", &des_ick, CK_242X), + CLK("omap-sham", "ick", &sha_ick, CK_242X), + CLK(NULL, "sha_ick", &sha_ick, CK_242X), + CLK("omap_rng", "ick", &rng_ick, CK_242X), + CLK(NULL, "rng_ick", &rng_ick, CK_242X), + CLK("omap-aes", "ick", &aes_ick, CK_242X), + CLK(NULL, "aes_ick", &aes_ick, CK_242X), + CLK(NULL, "pka_ick", &pka_ick, CK_242X), + CLK(NULL, "usb_fck", &usb_fck, CK_242X), + CLK("musb-hdrc", "fck", &osc_ck, CK_242X), + CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X), + CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X), + CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X), + CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X), +}; + + +static const char *enable_init_clks[] = { + "apll96_ck", + "apll54_ck", + "sync_32k_ick", + "omapctrl_ick", + "gpmc_fck", + "sdrc_ick", +}; + +/* + * init code + */ + +int __init omap2420_clk_init(void) +{ + struct omap_clk *c; + + prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; + cpu_mask = RATE_IN_242X; + rate_table = omap2420_rate_table; + + omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw); + + omap2xxx_clkt_vps_check_bootloader_rates(); + + for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); + c++) { + clkdev_add(&c->lk); + if (!__clk_init(NULL, c->lk.clk)) + omap2_init_clk_hw_omap_clocks(c->lk.clk); + } + + omap2_clk_disable_autoidle_all(); + + omap2_clk_enable_init_clocks(enable_init_clks, + ARRAY_SIZE(enable_init_clks)); + + pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", + (clk_get_rate(&sys_ck) / 1000000), + (clk_get_rate(&sys_ck) / 100000) % 10, + (clk_get_rate(&dpll_ck) / 1000000), + (clk_get_rate(&mpu_ck) / 1000000)); + + return 0; +} diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c new file mode 100644 index 000000000000..eda079b96c6a --- /dev/null +++ b/arch/arm/mach-omap2/cclock2430_data.c @@ -0,0 +1,2065 @@ +/* + * OMAP2430 clock data + * + * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc. + * Copyright (C) 2004-2011 Nokia Corporation + * + * Contacts: + * Richard Woodruff <r-woodruff2@ti.com> + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/clk-private.h> +#include <linux/list.h> + +#include "soc.h" +#include "iomap.h" +#include "clock.h" +#include "clock2xxx.h" +#include "opp2xxx.h" +#include "cm2xxx.h" +#include "prm2xxx.h" +#include "prm-regbits-24xx.h" +#include "cm-regbits-24xx.h" +#include "sdrc.h" +#include "control.h" + +#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR + +/* + * 2430 clock tree. + * + * NOTE:In many cases here we are assigning a 'default' parent. In + * many cases the parent is selectable. The set parent calls will + * also switch sources. + * + * Several sources are given initial rates which may be wrong, this will + * be fixed up in the init func. + * + * Things are broadly separated below by clock domains. It is + * noteworthy that most peripherals have dependencies on multiple clock + * domains. Many get their interface clocks from the L4 domain, but get + * functional clocks from fixed sources or other core domain derived + * clocks. + */ + +DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0); + +DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0); + +DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); + +static struct clk osc_ck; + +static const struct clk_ops osc_ck_ops = { + .enable = &omap2_enable_osc_ck, + .disable = omap2_disable_osc_ck, + .recalc_rate = &omap2_osc_clk_recalc, +}; + +static struct clk_hw_omap osc_ck_hw = { + .hw = { + .clk = &osc_ck, + }, +}; + +static struct clk osc_ck = { + .name = "osc_ck", + .ops = &osc_ck_ops, + .hw = &osc_ck_hw.hw, + .flags = CLK_IS_ROOT, +}; + +DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0); + +static struct clk sys_ck; + +static const char *sys_ck_parent_names[] = { + "osc_ck", +}; + +static const struct clk_ops sys_ck_ops = { + .init = &omap2_init_clk_clkdm, + .recalc_rate = &omap2xxx_sys_clk_recalc, +}; + +DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm"); +DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops); + +static struct dpll_data dpll_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .mult_mask = OMAP24XX_DPLL_MULT_MASK, + .div1_mask = OMAP24XX_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_mask = OMAP24XX_EN_DPLL_MASK, + .max_multiplier = 1023, + .min_divider = 1, + .max_divider = 16, +}; + +static struct clk dpll_ck; + +static const char *dpll_ck_parent_names[] = { + "sys_ck", +}; + +static const struct clk_ops dpll_ck_ops = { + .init = &omap2_init_clk_clkdm, + .get_parent = &omap2_init_dpll_parent, + .recalc_rate = &omap2_dpllcore_recalc, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap2_reprogram_dpllcore, +}; + +static struct clk_hw_omap dpll_ck_hw = { + .hw = { + .clk = &dpll_ck, + }, + .ops = &clkhwops_omap2xxx_dpll, + .dpll_data = &dpll_dd, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops); + +static struct clk core_ck; + +static const char *core_ck_parent_names[] = { + "dpll_ck", +}; + +static const struct clk_ops core_ck_ops = { + .init = &omap2_init_clk_clkdm, +}; + +DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm"); +DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops); + +DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk aes_ick; + +static const char *aes_ick_parent_names[] = { + "l4_ck", +}; + +static const struct clk_ops aes_ick_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, +}; + +static struct clk_hw_omap aes_ick_hw = { + .hw = { + .clk = &aes_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_AES_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk apll54_ck; + +static const struct clk_ops apll54_ck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_clk_apll54_enable, + .disable = &omap2_clk_apll54_disable, + .recalc_rate = &omap2_clk_apll54_recalc, +}; + +static struct clk_hw_omap apll54_ck_hw = { + .hw = { + .clk = &apll54_ck, + }, + .ops = &clkhwops_apll54, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops); + +static struct clk apll96_ck; + +static const struct clk_ops apll96_ck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_clk_apll96_enable, + .disable = &omap2_clk_apll96_disable, + .recalc_rate = &omap2_clk_apll96_recalc, +}; + +static struct clk_hw_omap apll96_ck_hw = { + .hw = { + .clk = &apll96_ck, + }, + .ops = &clkhwops_apll96, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops); + +static const char *func_96m_ck_parent_names[] = { + "apll96_ck", "alt_ck", +}; + +DEFINE_CLK_MUX(func_96m_ck, func_96m_ck_parent_names, NULL, 0x0, + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP2430_96M_SOURCE_SHIFT, + OMAP2430_96M_SOURCE_WIDTH, 0x0, NULL); + +static struct clk cam_fck; + +static const char *cam_fck_parent_names[] = { + "func_96m_ck", +}; + +static struct clk_hw_omap cam_fck_hw = { + .hw = { + .clk = &cam_fck, + }, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_CAM_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk cam_ick; + +static struct clk_hw_omap cam_ick_hw = { + .hw = { + .clk = &cam_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_CAM_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk des_ick; + +static struct clk_hw_omap des_ick_hw = { + .hw = { + .clk = &des_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_DES_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate dsp_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel dsp_fck_clksel[] = { + { .parent = &core_ck, .rates = dsp_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *dsp_fck_parent_names[] = { + "core_ck", +}; + +static struct clk dsp_fck; + +static const struct clk_ops dsp_fck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, +}; + +DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + OMAP24XX_CLKSEL_DSP_MASK, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), + OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, + dsp_fck_parent_names, dsp_fck_ops); + +static const struct clksel_rate dss1_fck_sys_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate dss1_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 5, .val = 5, .flags = RATE_IN_24XX }, + { .div = 6, .val = 6, .flags = RATE_IN_24XX }, + { .div = 8, .val = 8, .flags = RATE_IN_24XX }, + { .div = 9, .val = 9, .flags = RATE_IN_24XX }, + { .div = 12, .val = 12, .flags = RATE_IN_24XX }, + { .div = 16, .val = 16, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel dss1_fck_clksel[] = { + { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, + { .parent = &core_ck, .rates = dss1_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *dss1_fck_parent_names[] = { + "sys_ck", "core_ck", +}; + +static const struct clk_ops dss1_fck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_DSS1_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_DSS1_SHIFT, NULL, + dss1_fck_parent_names, dss1_fck_ops); + +static const struct clksel_rate dss2_fck_sys_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate dss2_fck_48m_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate func_48m_apll96_rates[] = { + { .div = 2, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate func_48m_alt_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel func_48m_clksel[] = { + { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, + { .parent = &alt_ck, .rates = func_48m_alt_rates }, + { .parent = NULL }, +}; + +static const char *func_48m_ck_parent_names[] = { + "apll96_ck", "alt_ck", +}; + +static struct clk func_48m_ck; + +static const struct clk_ops func_48m_ck_ops = { + .init = &omap2_init_clk_clkdm, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap func_48m_ck_hw = { + .hw = { + .clk = &func_48m_ck, + }, + .clksel = func_48m_clksel, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_mask = OMAP24XX_48M_SOURCE_MASK, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops); + +static const struct clksel dss2_fck_clksel[] = { + { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, + { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, + { .parent = NULL }, +}; + +static const char *dss2_fck_parent_names[] = { + "sys_ck", "func_48m_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_DSS2_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_DSS2_SHIFT, NULL, + dss2_fck_parent_names, dss1_fck_ops); + +static const char *func_54m_ck_parent_names[] = { + "apll54_ck", "alt_ck", +}; + +DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0, + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL); + +static struct clk dss_54m_fck; + +static const char *dss_54m_fck_parent_names[] = { + "func_54m_ck", +}; + +static struct clk_hw_omap dss_54m_fck_hw = { + .hw = { + .clk = &dss_54m_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_TV_SHIFT, + .clkdm_name = "dss_clkdm", +}; + +DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops); + +static struct clk dss_ick; + +static struct clk_hw_omap dss_ick_hw = { + .hw = { + .clk = &dss_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_DSS1_SHIFT, + .clkdm_name = "dss_clkdm", +}; + +DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk emul_ck; + +static struct clk_hw_omap emul_ck_hw = { + .hw = { + .clk = &emul_ck, + }, + .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL, + .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops); + +DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4); + +static struct clk fac_fck; + +static const char *fac_fck_parent_names[] = { + "func_12m_ck", +}; + +static struct clk_hw_omap fac_fck_hw = { + .hw = { + .clk = &fac_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_FAC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops); + +static struct clk fac_ick; + +static struct clk_hw_omap fac_ick_hw = { + .hw = { + .clk = &fac_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_FAC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel gfx_fck_clksel[] = { + { .parent = &core_l3_ck, .rates = gfx_l3_rates }, + { .parent = NULL }, +}; + +static const char *gfx_2d_fck_parent_names[] = { + "core_l3_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel, + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), + OMAP_CLKSEL_GFX_MASK, + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + OMAP24XX_EN_2D_SHIFT, &clkhwops_wait, + gfx_2d_fck_parent_names, dsp_fck_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel, + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), + OMAP_CLKSEL_GFX_MASK, + OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + OMAP24XX_EN_3D_SHIFT, &clkhwops_wait, + gfx_2d_fck_parent_names, dsp_fck_ops); + +static struct clk gfx_ick; + +static const char *gfx_ick_parent_names[] = { + "core_l3_ck", +}; + +static struct clk_hw_omap gfx_ick_hw = { + .hw = { + .clk = &gfx_ick, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), + .enable_bit = OMAP_EN_GFX_SHIFT, + .clkdm_name = "gfx_clkdm", +}; + +DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops); + +static struct clk gpio5_fck; + +static const char *gpio5_fck_parent_names[] = { + "func_32k_ck", +}; + +static struct clk_hw_omap gpio5_fck_hw = { + .hw = { + .clk = &gpio5_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_GPIO5_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpio5_fck, gpio5_fck_parent_names, aes_ick_ops); + +static struct clk gpio5_ick; + +static struct clk_hw_omap gpio5_ick_hw = { + .hw = { + .clk = &gpio5_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_GPIO5_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpio5_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk gpios_fck; + +static struct clk_hw_omap gpios_fck_hw = { + .hw = { + .clk = &gpios_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops); + +static struct clk wu_l4_ick; + +DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm"); +DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops); + +static struct clk gpios_ick; + +static const char *gpios_ick_parent_names[] = { + "wu_l4_ick", +}; + +static struct clk_hw_omap gpios_ick_hw = { + .hw = { + .clk = &gpios_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk gpmc_fck; + +static struct clk_hw_omap gpmc_fck_hw = { + .hw = { + .clk = &gpmc_fck, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops); + +static const struct clksel_rate gpt_alt_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel omap24xx_gpt_clksel[] = { + { .parent = &func_32k_ck, .rates = gpt_32k_rates }, + { .parent = &sys_ck, .rates = gpt_sys_rates }, + { .parent = &alt_ck, .rates = gpt_alt_rates }, + { .parent = NULL }, +}; + +static const char *gpt10_fck_parent_names[] = { + "func_32k_ck", "sys_ck", "alt_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT10_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt10_ick; + +static struct clk_hw_omap gpt10_ick_hw = { + .hw = { + .clk = &gpt10_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT10_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT11_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt11_ick; + +static struct clk_hw_omap gpt11_ick_hw = { + .hw = { + .clk = &gpt11_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT11_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT12_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt12_ick; + +static struct clk_hw_omap gpt12_ick_hw = { + .hw = { + .clk = &gpt12_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT12_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clk_ops gpt1_fck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_GPT1_MASK, + OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, gpt1_fck_ops); + +static struct clk gpt1_ick; + +static struct clk_hw_omap gpt1_ick_hw = { + .hw = { + .clk = &gpt1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_GPT1_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT2_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt2_ick; + +static struct clk_hw_omap gpt2_ick_hw = { + .hw = { + .clk = &gpt2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT3_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt3_ick; + +static struct clk_hw_omap gpt3_ick_hw = { + .hw = { + .clk = &gpt3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT4_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt4_ick; + +static struct clk_hw_omap gpt4_ick_hw = { + .hw = { + .clk = &gpt4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT5_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt5_ick; + +static struct clk_hw_omap gpt5_ick_hw = { + .hw = { + .clk = &gpt5_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT5_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT6_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt6_ick; + +static struct clk_hw_omap gpt6_ick_hw = { + .hw = { + .clk = &gpt6_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT6_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT7_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt7_ick; + +static struct clk_hw_omap gpt7_ick_hw = { + .hw = { + .clk = &gpt7_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT7_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk gpt8_fck; + +DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT8_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt8_ick; + +static struct clk_hw_omap gpt8_ick_hw = { + .hw = { + .clk = &gpt8_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT8_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), + OMAP24XX_CLKSEL_GPT9_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, dss1_fck_ops); + +static struct clk gpt9_ick; + +static struct clk_hw_omap gpt9_ick_hw = { + .hw = { + .clk = &gpt9_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_GPT9_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk hdq_fck; + +static struct clk_hw_omap hdq_fck_hw = { + .hw = { + .clk = &hdq_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_HDQ_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops); + +static struct clk hdq_ick; + +static struct clk_hw_omap hdq_ick_hw = { + .hw = { + .clk = &hdq_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_HDQ_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk i2c1_ick; + +static struct clk_hw_omap i2c1_ick_hw = { + .hw = { + .clk = &i2c1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_I2C1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk i2c2_ick; + +static struct clk_hw_omap i2c2_ick_hw = { + .hw = { + .clk = &i2c2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP2420_EN_I2C2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk i2chs1_fck; + +static struct clk_hw_omap i2chs1_fck_hw = { + .hw = { + .clk = &i2chs1_fck, + }, + .ops = &clkhwops_omap2430_i2chs_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2chs1_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk i2chs2_fck; + +static struct clk_hw_omap i2chs2_fck_hw = { + .hw = { + .clk = &i2chs2_fck, + }, + .ops = &clkhwops_omap2430_i2chs_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2chs2_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk icr_ick; + +static struct clk_hw_omap icr_ick_hw = { + .hw = { + .clk = &icr_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP2430_EN_ICR_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(icr_ick, gpios_ick_parent_names, aes_ick_ops); + +static const struct clksel dsp_ick_clksel[] = { + { .parent = &dsp_fck, .rates = dsp_ick_rates }, + { .parent = NULL }, +}; + +static const char *iva2_1_ick_parent_names[] = { + "dsp_fck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(iva2_1_ick, "dsp_clkdm", dsp_ick_clksel, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), + OMAP24XX_CLKSEL_DSP_IF_MASK, + OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), + OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait, + iva2_1_ick_parent_names, dsp_fck_ops); + +static struct clk mailboxes_ick; + +static struct clk_hw_omap mailboxes_ick_hw = { + .hw = { + .clk = &mailboxes_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate common_mcbsp_96m_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel mcbsp_fck_clksel[] = { + { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp1_fck_parent_names[] = { + "func_96m_ck", "mcbsp_clks", +}; + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + OMAP2_MCBSP1_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp1_ick; + +static struct clk_hw_omap mcbsp1_ick_hw = { + .hw = { + .clk = &mcbsp1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + OMAP2_MCBSP2_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp2_ick; + +static struct clk_hw_omap mcbsp2_ick_hw = { + .hw = { + .clk = &mcbsp2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), + OMAP2_MCBSP3_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + OMAP2430_EN_MCBSP3_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp3_ick; + +static struct clk_hw_omap mcbsp3_ick_hw = { + .hw = { + .clk = &mcbsp3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp3_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), + OMAP2_MCBSP4_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + OMAP2430_EN_MCBSP4_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp4_ick; + +static struct clk_hw_omap mcbsp4_ick_hw = { + .hw = { + .clk = &mcbsp4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp4_ick, aes_ick_parent_names, aes_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_fck_clksel, + OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), + OMAP2_MCBSP5_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + OMAP2430_EN_MCBSP5_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, dss1_fck_ops); + +static struct clk mcbsp5_ick; + +static struct clk_hw_omap mcbsp5_ick_hw = { + .hw = { + .clk = &mcbsp5_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp5_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mcspi1_fck; + +static const char *mcspi1_fck_parent_names[] = { + "func_48m_ck", +}; + +static struct clk_hw_omap mcspi1_fck_hw = { + .hw = { + .clk = &mcspi1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk mcspi1_ick; + +static struct clk_hw_omap mcspi1_ick_hw = { + .hw = { + .clk = &mcspi1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mcspi2_fck; + +static struct clk_hw_omap mcspi2_fck_hw = { + .hw = { + .clk = &mcspi2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk mcspi2_ick; + +static struct clk_hw_omap mcspi2_ick_hw = { + .hw = { + .clk = &mcspi2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mcspi3_fck; + +static struct clk_hw_omap mcspi3_fck_hw = { + .hw = { + .clk = &mcspi3_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi3_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk mcspi3_ick; + +static struct clk_hw_omap mcspi3_ick_hw = { + .hw = { + .clk = &mcspi3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi3_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate mdm_ick_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_243X }, + { .div = 4, .val = 4, .flags = RATE_IN_243X }, + { .div = 6, .val = 6, .flags = RATE_IN_243X }, + { .div = 9, .val = 9, .flags = RATE_IN_243X }, + { .div = 0 } +}; + +static const struct clksel mdm_ick_clksel[] = { + { .parent = &core_ck, .rates = mdm_ick_core_rates }, + { .parent = NULL }, +}; + +static const char *mdm_ick_parent_names[] = { + "core_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(mdm_ick, "mdm_clkdm", mdm_ick_clksel, + OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), + OMAP2430_CLKSEL_MDM_MASK, + OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), + OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, + &clkhwops_iclk_wait, mdm_ick_parent_names, + dsp_fck_ops); + +static struct clk mdm_intc_ick; + +static struct clk_hw_omap mdm_intc_ick_hw = { + .hw = { + .clk = &mdm_intc_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mdm_intc_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mdm_osc_ck; + +static struct clk_hw_omap mdm_osc_ck_hw = { + .hw = { + .clk = &mdm_osc_ck, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), + .enable_bit = OMAP2430_EN_OSC_SHIFT, + .clkdm_name = "mdm_clkdm", +}; + +DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops); + +static struct clk mmchs1_fck; + +static struct clk_hw_omap mmchs1_fck_hw = { + .hw = { + .clk = &mmchs1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchs1_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk mmchs1_ick; + +static struct clk_hw_omap mmchs1_ick_hw = { + .hw = { + .clk = &mmchs1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchs1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mmchs2_fck; + +static struct clk_hw_omap mmchs2_fck_hw = { + .hw = { + .clk = &mmchs2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchs2_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk mmchs2_ick; + +static struct clk_hw_omap mmchs2_ick_hw = { + .hw = { + .clk = &mmchs2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchs2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk mmchsdb1_fck; + +static struct clk_hw_omap mmchsdb1_fck_hw = { + .hw = { + .clk = &mmchsdb1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchsdb1_fck, gpio5_fck_parent_names, aes_ick_ops); + +static struct clk mmchsdb2_fck; + +static struct clk_hw_omap mmchsdb2_fck_hw = { + .hw = { + .clk = &mmchsdb2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchsdb2_fck, gpio5_fck_parent_names, aes_ick_ops); + +DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0, + OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), + OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk mpu_wdt_fck; + +static struct clk_hw_omap mpu_wdt_fck_hw = { + .hw = { + .clk = &mpu_wdt_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(mpu_wdt_fck, gpio5_fck_parent_names, aes_ick_ops); + +static struct clk mpu_wdt_ick; + +static struct clk_hw_omap mpu_wdt_ick_hw = { + .hw = { + .clk = &mpu_wdt_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk mspro_fck; + +static struct clk_hw_omap mspro_fck_hw = { + .hw = { + .clk = &mspro_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops); + +static struct clk mspro_ick; + +static struct clk_hw_omap mspro_ick_hw = { + .hw = { + .clk = &mspro_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk omapctrl_ick; + +static struct clk_hw_omap omapctrl_ick_hw = { + .hw = { + .clk = &omapctrl_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk pka_ick; + +static struct clk_hw_omap pka_ick_hw = { + .hw = { + .clk = &pka_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_PKA_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk rng_ick; + +static struct clk_hw_omap rng_ick_hw = { + .hw = { + .clk = &rng_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_RNG_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk sdma_fck; + +DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm"); +DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops); + +static struct clk sdma_ick; + +static struct clk_hw_omap sdma_ick_hw = { + .hw = { + .clk = &sdma_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops); + +static struct clk sdrc_ick; + +static struct clk_hw_omap sdrc_ick_hw = { + .hw = { + .clk = &sdrc_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP2430_EN_SDRC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops); + +static struct clk sha_ick; + +static struct clk_hw_omap sha_ick_hw = { + .hw = { + .clk = &sha_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), + .enable_bit = OMAP24XX_EN_SHA_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk ssi_l4_ick; + +static struct clk_hw_omap ssi_l4_ick_hw = { + .hw = { + .clk = &ssi_l4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP24XX_EN_SSI_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 3, .val = 3, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 5, .val = 5, .flags = RATE_IN_243X }, + { .div = 0 } +}; + +static const struct clksel ssi_ssr_sst_fck_clksel[] = { + { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, + { .parent = NULL }, +}; + +static const char *ssi_ssr_sst_fck_parent_names[] = { + "core_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm", + ssi_ssr_sst_fck_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_SSI_MASK, + OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait, + ssi_ssr_sst_fck_parent_names, dsp_fck_ops); + +static struct clk sync_32k_ick; + +static struct clk_hw_omap sync_32k_ick_hw = { + .hw = { + .clk = &sync_32k_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops); + +static const struct clksel_rate common_clkout_src_core_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_clkout_src_sys_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_clkout_src_96m_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_clkout_src_54m_rates[] = { + { .div = 1, .val = 3, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel common_clkout_src_clksel[] = { + { .parent = &core_ck, .rates = common_clkout_src_core_rates }, + { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, + { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, + { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, + { .parent = NULL }, +}; + +static const char *sys_clkout_src_parent_names[] = { + "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel, + OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK, + OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT, + NULL, sys_clkout_src_parent_names, gpt1_fck_ops); + +DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0, + OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT, + OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +static struct clk uart1_fck; + +static struct clk_hw_omap uart1_fck_hw = { + .hw = { + .clk = &uart1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_UART1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk uart1_ick; + +static struct clk_hw_omap uart1_ick_hw = { + .hw = { + .clk = &uart1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_UART1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk uart2_fck; + +static struct clk_hw_omap uart2_fck_hw = { + .hw = { + .clk = &uart2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_UART2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk uart2_ick; + +static struct clk_hw_omap uart2_ick_hw = { + .hw = { + .clk = &uart2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_UART2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk uart3_fck; + +static struct clk_hw_omap uart3_fck_hw = { + .hw = { + .clk = &uart3_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP24XX_EN_UART3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static struct clk uart3_ick; + +static struct clk_hw_omap uart3_ick_hw = { + .hw = { + .clk = &uart3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP24XX_EN_UART3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops); + +static struct clk usb_fck; + +static struct clk_hw_omap usb_fck_hw = { + .hw = { + .clk = &usb_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), + .enable_bit = OMAP24XX_EN_USB_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops); + +static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 2, .val = 2, .flags = RATE_IN_24XX }, + { .div = 4, .val = 4, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel usb_l4_ick_clksel[] = { + { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, + { .parent = NULL }, +}; + +static const char *usb_l4_ick_parent_names[] = { + "core_l3_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), + OMAP24XX_CLKSEL_USB_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait, + usb_l4_ick_parent_names, dsp_fck_ops); + +static struct clk usbhs_ick; + +static struct clk_hw_omap usbhs_ick_hw = { + .hw = { + .clk = &usbhs_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP2430_EN_USBHS_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(usbhs_ick, gfx_ick_parent_names, aes_ick_ops); + +static struct clk virt_prcm_set; + +static const char *virt_prcm_set_parent_names[] = { + "mpu_ck", +}; + +static const struct clk_ops virt_prcm_set_ops = { + .recalc_rate = &omap2_table_mpu_recalc, + .set_rate = &omap2_select_table_rate, + .round_rate = &omap2_round_to_table_rate, +}; + +DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL); +DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops); + +static struct clk wdt1_ick; + +static struct clk_hw_omap wdt1_ick_hw = { + .hw = { + .clk = &wdt1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP24XX_EN_WDT1_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); + +static struct clk wdt1_osc_ck; + +static const struct clk_ops wdt1_osc_ck_ops = {}; + +DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL); +DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops); + +static struct clk wdt4_fck; + +static struct clk_hw_omap wdt4_fck_hw = { + .hw = { + .clk = &wdt4_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP24XX_EN_WDT4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt4_fck, gpio5_fck_parent_names, aes_ick_ops); + +static struct clk wdt4_ick; + +static struct clk_hw_omap wdt4_ick_hw = { + .hw = { + .clk = &wdt4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP24XX_EN_WDT4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops); + +/* + * clkdev integration + */ + +static struct omap_clk omap2430_clks[] = { + /* external root sources */ + CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X), + CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X), + CLK(NULL, "osc_ck", &osc_ck, CK_243X), + CLK("twl", "fck", &osc_ck, CK_243X), + CLK(NULL, "sys_ck", &sys_ck, CK_243X), + CLK(NULL, "alt_ck", &alt_ck, CK_243X), + CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), + /* internal analog sources */ + CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), + CLK(NULL, "apll96_ck", &apll96_ck, CK_243X), + CLK(NULL, "apll54_ck", &apll54_ck, CK_243X), + /* internal prcm root sources */ + CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), + CLK(NULL, "core_ck", &core_ck, CK_243X), + CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), + CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), + CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), + CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X), + CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X), + CLK(NULL, "sys_clkout", &sys_clkout, CK_243X), + CLK(NULL, "emul_ck", &emul_ck, CK_243X), + /* mpu domain clocks */ + CLK(NULL, "mpu_ck", &mpu_ck, CK_243X), + /* dsp domain clocks */ + CLK(NULL, "dsp_fck", &dsp_fck, CK_243X), + CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), + /* GFX domain clocks */ + CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X), + CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X), + CLK(NULL, "gfx_ick", &gfx_ick, CK_243X), + /* Modem domain clocks */ + CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), + CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), + /* DSS domain clocks */ + CLK("omapdss_dss", "ick", &dss_ick, CK_243X), + CLK(NULL, "dss_ick", &dss_ick, CK_243X), + CLK(NULL, "dss1_fck", &dss1_fck, CK_243X), + CLK(NULL, "dss2_fck", &dss2_fck, CK_243X), + CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X), + /* L3 domain clocks */ + CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), + CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), + CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X), + /* L4 domain clocks */ + CLK(NULL, "l4_ck", &l4_ck, CK_243X), + CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X), + CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X), + /* virtual meta-group clock */ + CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X), + /* general l4 interface ck, multi-parent functional clk */ + CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X), + CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X), + CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X), + CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X), + CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X), + CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X), + CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X), + CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X), + CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X), + CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X), + CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X), + CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X), + CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X), + CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X), + CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X), + CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X), + CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X), + CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X), + CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X), + CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X), + CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X), + CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X), + CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), + CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), + CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X), + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X), + CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), + CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X), + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X), + CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), + CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X), + CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X), + CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), + CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X), + CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X), + CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), + CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X), + CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X), + CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X), + CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X), + CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X), + CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X), + CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X), + CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X), + CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), + CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X), + CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X), + CLK(NULL, "uart1_ick", &uart1_ick, CK_243X), + CLK(NULL, "uart1_fck", &uart1_fck, CK_243X), + CLK(NULL, "uart2_ick", &uart2_ick, CK_243X), + CLK(NULL, "uart2_fck", &uart2_fck, CK_243X), + CLK(NULL, "uart3_ick", &uart3_ick, CK_243X), + CLK(NULL, "uart3_fck", &uart3_fck, CK_243X), + CLK(NULL, "gpios_ick", &gpios_ick, CK_243X), + CLK(NULL, "gpios_fck", &gpios_fck, CK_243X), + CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X), + CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X), + CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X), + CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X), + CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X), + CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X), + CLK(NULL, "icr_ick", &icr_ick, CK_243X), + CLK("omap24xxcam", "fck", &cam_fck, CK_243X), + CLK(NULL, "cam_fck", &cam_fck, CK_243X), + CLK("omap24xxcam", "ick", &cam_ick, CK_243X), + CLK(NULL, "cam_ick", &cam_ick, CK_243X), + CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X), + CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X), + CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X), + CLK(NULL, "mspro_ick", &mspro_ick, CK_243X), + CLK(NULL, "mspro_fck", &mspro_fck, CK_243X), + CLK(NULL, "fac_ick", &fac_ick, CK_243X), + CLK(NULL, "fac_fck", &fac_fck, CK_243X), + CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), + CLK(NULL, "hdq_ick", &hdq_ick, CK_243X), + CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), + CLK(NULL, "hdq_fck", &hdq_fck, CK_243X), + CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X), + CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X), + CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X), + CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X), + CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X), + CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X), + CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), + CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), + CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), + CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), + CLK(NULL, "des_ick", &des_ick, CK_243X), + CLK("omap-sham", "ick", &sha_ick, CK_243X), + CLK("omap_rng", "ick", &rng_ick, CK_243X), + CLK(NULL, "rng_ick", &rng_ick, CK_243X), + CLK("omap-aes", "ick", &aes_ick, CK_243X), + CLK(NULL, "pka_ick", &pka_ick, CK_243X), + CLK(NULL, "usb_fck", &usb_fck, CK_243X), + CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), + CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X), + CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X), + CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X), + CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X), + CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X), + CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X), + CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X), + CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), + CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), + CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), + CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), + CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X), + CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), + CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X), + CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X), + CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X), + CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X), + CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X), +}; + +static const char *enable_init_clks[] = { + "apll96_ck", + "apll54_ck", + "sync_32k_ick", + "omapctrl_ick", + "gpmc_fck", + "sdrc_ick", +}; + +/* + * init code + */ + +int __init omap2430_clk_init(void) +{ + struct omap_clk *c; + + prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; + cpu_mask = RATE_IN_243X; + rate_table = omap2430_rate_table; + + omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw); + + omap2xxx_clkt_vps_check_bootloader_rates(); + + for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); + c++) { + clkdev_add(&c->lk); + if (!__clk_init(NULL, c->lk.clk)) + omap2_init_clk_hw_omap_clocks(c->lk.clk); + } + + omap2_clk_disable_autoidle_all(); + + omap2_clk_enable_init_clocks(enable_init_clks, + ARRAY_SIZE(enable_init_clks)); + + pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", + (clk_get_rate(&sys_ck) / 1000000), + (clk_get_rate(&sys_ck) / 100000) % 10, + (clk_get_rate(&dpll_ck) / 1000000), + (clk_get_rate(&mpu_ck) / 1000000)); + + return 0; +} diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c new file mode 100644 index 000000000000..ea64ad606759 --- /dev/null +++ b/arch/arm/mach-omap2/cclock33xx_data.c @@ -0,0 +1,961 @@ +/* + * AM33XX Clock data + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Vaibhav Hiremath <hvaibhav@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/clk-private.h> +#include <linux/clkdev.h> +#include <linux/io.h> + +#include "am33xx.h" +#include "soc.h" +#include "iomap.h" +#include "clock.h" +#include "control.h" +#include "cm.h" +#include "cm33xx.h" +#include "cm-regbits-33xx.h" +#include "prm.h" + +/* Modulemode control */ +#define AM33XX_MODULEMODE_HWCTRL_SHIFT 0 +#define AM33XX_MODULEMODE_SWCTRL_SHIFT 1 + +/*LIST_HEAD(clocks);*/ + +/* Root clocks */ + +/* RTC 32k */ +DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0); + +/* On-Chip 32KHz RC OSC */ +DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0); + +/* Crystal input clks */ +DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0); + +/* Oscillator clock */ +/* 19.2, 24, 25 or 26 MHz */ +static const char *sys_clkin_ck_parents[] = { + "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck", + "virt_26000000_ck", +}; + +/* + * sys_clk in: input to the dpll and also used as funtional clock for, + * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse + * + */ +DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0, + AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS), + AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT, + AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH, + 0, NULL); + +/* External clock - 12 MHz */ +DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0); + +/* Module clocks and DPLL outputs */ + +/* DPLL_CORE */ +static struct dpll_data dpll_core_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE, + .mult_mask = AM33XX_DPLL_MULT_MASK, + .div1_mask = AM33XX_DPLL_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + +/* CLKDCOLDO output */ +static const char *dpll_core_ck_parents[] = { + "sys_clkin_ck", +}; + +static struct clk dpll_core_ck; + +static const struct clk_ops dpll_core_ck_ops = { + .recalc_rate = &omap3_dpll_recalc, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_core_ck_hw = { + .hw = { + .clk = &dpll_core_ck, + }, + .dpll_data = &dpll_core_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops); + +static const char *dpll_core_x2_ck_parents[] = { + "dpll_core_ck", +}; + +static struct clk dpll_core_x2_ck; + +static const struct clk_ops dpll_x2_ck_ops = { + .recalc_rate = &omap3_clkoutx2_recalc, +}; + +static struct clk_hw_omap dpll_core_x2_ck_hw = { + .hw = { + .clk = &dpll_core_x2_ck, + }, + .flags = CLOCK_CLKOUTX2, +}; + +DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops); + +DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, + 0x0, AM33XX_CM_DIV_M4_DPLL_CORE, + AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT, + AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, + NULL); + +DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, + 0x0, AM33XX_CM_DIV_M5_DPLL_CORE, + AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT, + AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, + 0x0, AM33XX_CM_DIV_M6_DPLL_CORE, + AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT, + AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + + +/* DPLL_MPU */ +static struct dpll_data dpll_mpu_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU, + .mult_mask = AM33XX_DPLL_MULT_MASK, + .div1_mask = AM33XX_DPLL_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + +/* CLKOUT: fdpll/M2 */ +static struct clk dpll_mpu_ck; + +static const struct clk_ops dpll_mpu_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .recalc_rate = &omap3_dpll_recalc, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_mpu_ck_hw = { + .hw = { + .clk = &dpll_mpu_ck, + }, + .dpll_data = &dpll_mpu_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops); + +/* + * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 + * and ALT_CLK1/2) + */ +DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, + 0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT, + AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); + +/* DPLL_DDR */ +static struct dpll_data dpll_ddr_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR, + .mult_mask = AM33XX_DPLL_MULT_MASK, + .div1_mask = AM33XX_DPLL_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + +/* CLKOUT: fdpll/M2 */ +static struct clk dpll_ddr_ck; + +static const struct clk_ops dpll_ddr_ck_ops = { + .recalc_rate = &omap3_dpll_recalc, + .get_parent = &omap2_init_dpll_parent, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, +}; + +static struct clk_hw_omap dpll_ddr_ck_hw = { + .hw = { + .clk = &dpll_ddr_ck, + }, + .dpll_data = &dpll_ddr_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops); + +/* + * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 + * and ALT_CLK1/2) + */ +DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck, + 0x0, AM33XX_CM_DIV_M2_DPLL_DDR, + AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +/* emif_fck functional clock */ +DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, + 0x0, 1, 2); + +/* DPLL_DISP */ +static struct dpll_data dpll_disp_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP, + .mult_mask = AM33XX_DPLL_MULT_MASK, + .div1_mask = AM33XX_DPLL_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + +/* CLKOUT: fdpll/M2 */ +static struct clk dpll_disp_ck; + +static struct clk_hw_omap dpll_disp_ck_hw = { + .hw = { + .clk = &dpll_disp_ck, + }, + .dpll_data = &dpll_disp_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops); + +/* + * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 + * and ALT_CLK1/2) + */ +DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, 0x0, + AM33XX_CM_DIV_M2_DPLL_DISP, AM33XX_DPLL_CLKOUT_DIV_SHIFT, + AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); + +/* DPLL_PER */ +static struct dpll_data dpll_per_dd = { + .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = AM33XX_CM_CLKMODE_DPLL_PER, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER, + .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK, + .div1_mask = AM33XX_DPLL_PER_DIV_MASK, + .enable_mask = AM33XX_DPLL_EN_MASK, + .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, + .flags = DPLL_J_TYPE, +}; + +/* CLKDCOLDO */ +static struct clk dpll_per_ck; + +static struct clk_hw_omap dpll_per_ck_hw = { + .hw = { + .clk = &dpll_per_ck, + }, + .dpll_data = &dpll_per_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops); + +/* CLKOUT: fdpll/M2 */ +DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0, + AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT, + AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, + NULL); + +DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck", + &dpll_per_m2_ck, 0x0, 1, 4); + +DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck", + &dpll_per_m2_ck, 0x0, 1, 4); + +DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck", + &dpll_core_m4_ck, 0x0, 1, 2); + +DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0, + 1, 2); + +DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, + 8); + +/* + * Below clock nodes describes clockdomains derived out + * of core clock. + */ +static const struct clk_ops clk_ops_null = { +}; + +static const char *l3_gclk_parents[] = { + "dpll_core_m4_ck" +}; + +static struct clk l3_gclk; +DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL); +DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null); + +static struct clk l4hs_gclk; +DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL); +DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null); + +static const char *l3s_gclk_parents[] = { + "dpll_core_m4_div2_ck" +}; + +static struct clk l3s_gclk; +DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL); +DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null); + +static struct clk l4fw_gclk; +DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL); +DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null); + +static struct clk l4ls_gclk; +DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL); +DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null); + +static struct clk sysclk_div_ck; +DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL); +DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null); + +/* + * In order to match the clock domain with hwmod clockdomain entry, + * separate clock nodes is required for the modules which are + * directly getting their funtioncal clock from sys_clkin. + */ +static struct clk adc_tsc_fck; +DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL); +DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null); + +static struct clk dcan0_fck; +DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL); +DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null); + +static struct clk dcan1_fck; +DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL); +DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null); + +static struct clk mcasp0_fck; +DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL); +DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null); + +static struct clk mcasp1_fck; +DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL); +DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null); + +static struct clk smartreflex0_fck; +DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL); +DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null); + +static struct clk smartreflex1_fck; +DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL); +DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null); + +/* + * Modules clock nodes + * + * The following clock leaf nodes are added for the moment because: + * + * - hwmod data is not present for these modules, either hwmod + * control is not required or its not populated. + * - Driver code is not yet migrated to use hwmod/runtime pm + * - Modules outside kernel access (to disable them by default) + * + * - debugss + * - mmu (gfx domain) + * - cefuse + * - usbotg_fck (its additional clock and not really a modulemode) + * - ieee5000 + */ +DEFINE_CLK_GATE(debugss_ick, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0, + AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0, + AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0, + AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +/* + * clkdiv32 is generated from fixed division of 732.4219 + */ +DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732); + +DEFINE_CLK_GATE(clkdiv32k_ick, "clkdiv32k_ck", &clkdiv32k_ck, 0x0, + AM33XX_CM_PER_CLKDIV32K_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +/* "usbotg_fck" is an additional clock and not really a modulemode */ +DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0, + AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, + 0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL, + AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +/* Timers */ +static const struct clksel timer1_clkmux_sel[] = { + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &clkdiv32k_ick, .rates = div_1_1_rates }, + { .parent = &tclkin_ck, .rates = div_1_2_rates }, + { .parent = &clk_rc32k_ck, .rates = div_1_3_rates }, + { .parent = &clk_32768_ck, .rates = div_1_4_rates }, + { .parent = NULL }, +}; + +static const char *timer1_ck_parents[] = { + "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck", + "clk_32768_ck", +}; + +static struct clk timer1_fck; + +static const struct clk_ops timer1_fck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, + .init = &omap2_init_clk_clkdm, +}; + +static struct clk_hw_omap timer1_fck_hw = { + .hw = { + .clk = &timer1_fck, + }, + .clkdm_name = "l4ls_clkdm", + .clksel = timer1_clkmux_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK, + .clksel_mask = AM33XX_CLKSEL_0_2_MASK, +}; + +DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops); + +static const struct clksel timer2_to_7_clk_sel[] = { + { .parent = &tclkin_ck, .rates = div_1_0_rates }, + { .parent = &sys_clkin_ck, .rates = div_1_1_rates }, + { .parent = &clkdiv32k_ick, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *timer2_to_7_ck_parents[] = { + "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick", +}; + +static struct clk timer2_fck; + +static struct clk_hw_omap timer2_fck_hw = { + .hw = { + .clk = &timer2_fck, + }, + .clkdm_name = "l4ls_clkdm", + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, +}; + +DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops); + +static struct clk timer3_fck; + +static struct clk_hw_omap timer3_fck_hw = { + .hw = { + .clk = &timer3_fck, + }, + .clkdm_name = "l4ls_clkdm", + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, +}; + +DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops); + +static struct clk timer4_fck; + +static struct clk_hw_omap timer4_fck_hw = { + .hw = { + .clk = &timer4_fck, + }, + .clkdm_name = "l4ls_clkdm", + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, +}; + +DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops); + +static struct clk timer5_fck; + +static struct clk_hw_omap timer5_fck_hw = { + .hw = { + .clk = &timer5_fck, + }, + .clkdm_name = "l4ls_clkdm", + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, +}; + +DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops); + +static struct clk timer6_fck; + +static struct clk_hw_omap timer6_fck_hw = { + .hw = { + .clk = &timer6_fck, + }, + .clkdm_name = "l4ls_clkdm", + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, +}; + +DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops); + +static struct clk timer7_fck; + +static struct clk_hw_omap timer7_fck_hw = { + .hw = { + .clk = &timer7_fck, + }, + .clkdm_name = "l4ls_clkdm", + .clksel = timer2_to_7_clk_sel, + .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, +}; + +DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops); + +DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk, + "dpll_core_m5_ck", + &dpll_core_m5_ck, + 0x0, + 1, 2); + +static const struct clk_ops cpsw_fck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +static const struct clksel cpsw_cpts_rft_clkmux_sel[] = { + { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates }, + { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static const char *cpsw_cpts_rft_ck_parents[] = { + "dpll_core_m5_ck", "dpll_core_m4_ck", +}; + +static struct clk cpsw_cpts_rft_clk; + +static struct clk_hw_omap cpsw_cpts_rft_clk_hw = { + .hw = { + .clk = &cpsw_cpts_rft_clk, + }, + .clkdm_name = "cpsw_125mhz_clkdm", + .clksel = cpsw_cpts_rft_clkmux_sel, + .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL, + .clksel_mask = AM33XX_CLKSEL_0_0_MASK, +}; + +DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops); + + +/* gpio */ +static const char *gpio0_ck_parents[] = { + "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick", +}; + +static const struct clksel gpio0_dbclk_mux_sel[] = { + { .parent = &clk_rc32k_ck, .rates = div_1_0_rates }, + { .parent = &clk_32768_ck, .rates = div_1_1_rates }, + { .parent = &clkdiv32k_ick, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const struct clk_ops gpio_fck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, + .init = &omap2_init_clk_clkdm, +}; + +static struct clk gpio0_dbclk_mux_ck; + +static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = { + .hw = { + .clk = &gpio0_dbclk_mux_ck, + }, + .clkdm_name = "l4_wkup_clkdm", + .clksel = gpio0_dbclk_mux_sel, + .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, +}; + +DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops); + +DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0, + AM33XX_CM_WKUP_GPIO0_CLKCTRL, + AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0, + AM33XX_CM_PER_GPIO1_CLKCTRL, + AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0, + AM33XX_CM_PER_GPIO2_CLKCTRL, + AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0, + AM33XX_CM_PER_GPIO3_CLKCTRL, + AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL); + + +static const char *pruss_ck_parents[] = { + "l3_gclk", "dpll_disp_m2_ck", +}; + +static const struct clksel pruss_ocp_clk_mux_sel[] = { + { .parent = &l3_gclk, .rates = div_1_0_rates }, + { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static struct clk pruss_ocp_gclk; + +static struct clk_hw_omap pruss_ocp_gclk_hw = { + .hw = { + .clk = &pruss_ocp_gclk, + }, + .clkdm_name = "pruss_ocp_clkdm", + .clksel = pruss_ocp_clk_mux_sel, + .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK, + .clksel_mask = AM33XX_CLKSEL_0_0_MASK, +}; + +DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops); + +static const char *lcd_ck_parents[] = { + "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck", +}; + +static const struct clksel lcd_clk_mux_sel[] = { + { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates }, + { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates }, + { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static struct clk lcd_gclk; + +static struct clk_hw_omap lcd_gclk_hw = { + .hw = { + .clk = &lcd_gclk, + }, + .clkdm_name = "lcdc_clkdm", + .clksel = lcd_clk_mux_sel, + .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, +}; + +DEFINE_STRUCT_CLK(lcd_gclk, lcd_ck_parents, gpio_fck_ops); + +DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2); + +static const char *gfx_ck_parents[] = { + "dpll_core_m4_ck", "dpll_per_m2_ck", +}; + +static const struct clksel gfx_clksel_sel[] = { + { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates }, + { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static struct clk gfx_fclk_clksel_ck; + +static struct clk_hw_omap gfx_fclk_clksel_ck_hw = { + .hw = { + .clk = &gfx_fclk_clksel_ck, + }, + .clksel = gfx_clksel_sel, + .clksel_reg = AM33XX_CLKSEL_GFX_FCLK, + .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK, +}; + +DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops); + +static const struct clk_div_table div_1_0_2_1_rates[] = { + { .div = 1, .val = 0, }, + { .div = 2, .val = 1, }, + { .div = 0 }, +}; + +DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck", + &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK, + AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH, + 0x0, div_1_0_2_1_rates, NULL); + +static const char *sysclkout_ck_parents[] = { + "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck", + "lcd_gclk", +}; + +static const struct clksel sysclkout_pre_sel[] = { + { .parent = &clk_32768_ck, .rates = div_1_0_rates }, + { .parent = &l3_gclk, .rates = div_1_1_rates }, + { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates }, + { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates }, + { .parent = &lcd_gclk, .rates = div_1_4_rates }, + { .parent = NULL }, +}; + +static struct clk sysclkout_pre_ck; + +static struct clk_hw_omap sysclkout_pre_ck_hw = { + .hw = { + .clk = &sysclkout_pre_ck, + }, + .clksel = sysclkout_pre_sel, + .clksel_reg = AM33XX_CM_CLKOUT_CTRL, + .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK, +}; + +DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops); + +/* Divide by 8 clock rates with default clock is 1/1*/ +static const struct clk_div_table div8_rates[] = { + { .div = 1, .val = 0, }, + { .div = 2, .val = 1, }, + { .div = 3, .val = 2, }, + { .div = 4, .val = 3, }, + { .div = 5, .val = 4, }, + { .div = 6, .val = 5, }, + { .div = 7, .val = 6, }, + { .div = 8, .val = 7, }, + { .div = 0 }, +}; + +DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck, + 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT, + AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL); + +DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0, + AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL); + +static const char *wdt_ck_parents[] = { + "clk_rc32k_ck", "clkdiv32k_ick", +}; + +static const struct clksel wdt_clkmux_sel[] = { + { .parent = &clk_rc32k_ck, .rates = div_1_0_rates }, + { .parent = &clkdiv32k_ick, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static struct clk wdt1_fck; + +static struct clk_hw_omap wdt1_fck_hw = { + .hw = { + .clk = &wdt1_fck, + }, + .clkdm_name = "l4_wkup_clkdm", + .clksel = wdt_clkmux_sel, + .clksel_reg = AM33XX_CLKSEL_WDT1_CLK, + .clksel_mask = AM33XX_CLKSEL_0_1_MASK, +}; + +DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops); + +/* + * clkdev + */ +static struct omap_clk am33xx_clks[] = { + CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX), + CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX), + CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX), + CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX), + CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX), + CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX), + CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX), + CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX), + CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX), + CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX), + CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX), + CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX), + CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX), + CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX), + CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX), + CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX), + CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX), + CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX), + CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX), + CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX), + CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX), + CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX), + CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX), + CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX), + CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX), + CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX), + CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX), + CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck, CK_AM33XX), + CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX), + CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX), + CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX), + CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX), + CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX), + CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX), + CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX), + CLK(NULL, "mcasp0_fck", &mcasp0_fck, CK_AM33XX), + CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX), + CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX), + CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX), + CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX), + CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX), + CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX), + CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX), + CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX), + CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX), + CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX), + CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX), + CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX), + CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX), + CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX), + CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX), + CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX), + CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX), + CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX), + CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX), + CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX), + CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX), + CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX), + CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX), + CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX), + CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX), + CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX), + CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX), + CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX), + CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX), + CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX), + CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX), + CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX), + CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX), + CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX), + CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX), + CLK(NULL, "clkout2_div_ck", &clkout2_div_ck, CK_AM33XX), + CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX), + CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX), +}; + + +static const char *enable_init_clks[] = { + "dpll_ddr_m2_ck", + "dpll_mpu_m2_ck", + "l3_gclk", + "l4hs_gclk", + "l4fw_gclk", + "l4ls_gclk", +}; + +int __init am33xx_clk_init(void) +{ + struct omap_clk *c; + u32 cpu_clkflg; + + if (soc_is_am33xx()) { + cpu_mask = RATE_IN_AM33XX; + cpu_clkflg = CK_AM33XX; + } + + for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) { + if (c->cpu & cpu_clkflg) { + clkdev_add(&c->lk); + if (!__clk_init(NULL, c->lk.clk)) + omap2_init_clk_hw_omap_clocks(c->lk.clk); + } + } + + omap2_clk_disable_autoidle_all(); + + omap2_clk_enable_init_clocks(enable_init_clks, + ARRAY_SIZE(enable_init_clks)); + + /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always + * physically present, in such a case HWMOD enabling of + * clock would be failure with default parent. And timer + * probe thinks clock is already enabled, this leads to + * crash upon accessing timer 3 & 6 registers in probe. + * Fix by setting parent of both these timers to master + * oscillator clock. + */ + + clk_set_parent(&timer3_fck, &sys_clkin_ck); + clk_set_parent(&timer6_fck, &sys_clkin_ck); + + return 0; +} diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c new file mode 100644 index 000000000000..bdf39481fbd6 --- /dev/null +++ b/arch/arm/mach-omap2/cclock3xxx_data.c @@ -0,0 +1,3595 @@ +/* + * OMAP3 clock data + * + * Copyright (C) 2007-2012 Texas Instruments, Inc. + * Copyright (C) 2007-2011 Nokia Corporation + * + * Written by Paul Walmsley + * Updated to COMMON clk data format by Rajendra Nayak <rnayak@ti.com> + * With many device clock fixes by Kevin Hilman and Jouni Högander + * DPLL bypass clock support added by Roman Tereshonkov + * + */ + +/* + * Virtual clocks are introduced as convenient tools. + * They are sources for other clocks and not supposed + * to be requested from drivers directly. + */ + +#include <linux/kernel.h> +#include <linux/clk.h> +#include <linux/clk-private.h> +#include <linux/list.h> +#include <linux/io.h> + +#include "soc.h" +#include "iomap.h" +#include "clock.h" +#include "clock3xxx.h" +#include "clock34xx.h" +#include "clock36xx.h" +#include "clock3517.h" +#include "cm3xxx.h" +#include "cm-regbits-34xx.h" +#include "prm3xxx.h" +#include "prm-regbits-34xx.h" +#include "control.h" + +/* + * clocks + */ + +#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR + +/* Maximum DPLL multiplier, divider values for OMAP3 */ +#define OMAP3_MAX_DPLL_MULT 2047 +#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095 +#define OMAP3_MAX_DPLL_DIV 128 + +DEFINE_CLK_FIXED_RATE(dummy_apb_pclk, CLK_IS_ROOT, 0x0, 0x0); + +DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0); + +DEFINE_CLK_FIXED_RATE(omap_32k_fck, CLK_IS_ROOT, 32768, 0x0); + +DEFINE_CLK_FIXED_RATE(pclk_ck, CLK_IS_ROOT, 27000000, 0x0); + +DEFINE_CLK_FIXED_RATE(rmii_ck, CLK_IS_ROOT, 50000000, 0x0); + +DEFINE_CLK_FIXED_RATE(secure_32k_fck, CLK_IS_ROOT, 32768, 0x0); + +DEFINE_CLK_FIXED_RATE(sys_altclk, CLK_IS_ROOT, 0x0, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_16_8m_ck, CLK_IS_ROOT, 16800000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_38_4m_ck, CLK_IS_ROOT, 38400000, 0x0); + +static const char *osc_sys_ck_parent_names[] = { + "virt_12m_ck", "virt_13m_ck", "virt_19200000_ck", "virt_26000000_ck", + "virt_38_4m_ck", "virt_16_8m_ck", +}; + +DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0, + OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT, + OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL); + +DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck, 0x0, + OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT, + OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); + +static struct dpll_data dpll3_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, + .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, + .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, + .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, + .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, + .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), + .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, + .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .idlest_mask = OMAP3430_ST_CORE_CLK_MASK, + .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, + .max_divider = OMAP3_MAX_DPLL_DIV, +}; + +static struct clk dpll3_ck; + +static const char *dpll3_ck_parent_names[] = { + "sys_ck", +}; + +static const struct clk_ops dpll3_ck_ops = { + .init = &omap2_init_clk_clkdm, + .get_parent = &omap2_init_dpll_parent, + .recalc_rate = &omap3_dpll_recalc, + .round_rate = &omap2_dpll_round_rate, +}; + +static struct clk_hw_omap dpll3_ck_hw = { + .hw = { + .clk = &dpll3_ck, + }, + .ops = &clkhwops_omap3_dpll, + .dpll_data = &dpll3_dd, + .clkdm_name = "dpll3_clkdm", +}; + +DEFINE_STRUCT_CLK(dpll3_ck, dpll3_ck_parent_names, dpll3_ck_ops); + +DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0, + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT, + OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk core_ck; + +static const char *core_ck_parent_names[] = { + "dpll3_m2_ck", +}; + +static const struct clk_ops core_ck_ops = {}; + +DEFINE_STRUCT_CLK_HW_OMAP(core_ck, NULL); +DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops); + +DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck, 0x0, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + OMAP3430_CLKSEL_L3_SHIFT, OMAP3430_CLKSEL_L3_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick, 0x0, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk security_l4_ick2; + +static const char *security_l4_ick2_parent_names[] = { + "l4_ick", +}; + +DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2, NULL); +DEFINE_STRUCT_CLK(security_l4_ick2, security_l4_ick2_parent_names, core_ck_ops); + +static struct clk aes1_ick; + +static const char *aes1_ick_parent_names[] = { + "security_l4_ick2", +}; + +static const struct clk_ops aes1_ick_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, +}; + +static struct clk_hw_omap aes1_ick_hw = { + .hw = { + .clk = &aes1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP3430_EN_AES1_SHIFT, +}; + +DEFINE_STRUCT_CLK(aes1_ick, aes1_ick_parent_names, aes1_ick_ops); + +static struct clk core_l4_ick; + +static const struct clk_ops core_l4_ick_ops = { + .init = &omap2_init_clk_clkdm, +}; + +DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick, "core_l4_clkdm"); +DEFINE_STRUCT_CLK(core_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); + +static struct clk aes2_ick; + +static const char *aes2_ick_parent_names[] = { + "core_l4_ick", +}; + +static const struct clk_ops aes2_ick_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, +}; + +static struct clk_hw_omap aes2_ick_hw = { + .hw = { + .clk = &aes2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_AES2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(aes2_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk dpll1_fck; + +static struct dpll_data dpll1_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), + .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, + .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, + .clk_bypass = &dpll1_fck, + .clk_ref = &sys_ck, + .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, + .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), + .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, + .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, + .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, + .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), + .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, + .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), + .idlest_mask = OMAP3430_ST_MPU_CLK_MASK, + .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, + .max_divider = OMAP3_MAX_DPLL_DIV, +}; + +static struct clk dpll1_ck; + +static const struct clk_ops dpll1_ck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .get_parent = &omap2_init_dpll_parent, + .recalc_rate = &omap3_dpll_recalc, + .set_rate = &omap3_noncore_dpll_set_rate, + .round_rate = &omap2_dpll_round_rate, +}; + +static struct clk_hw_omap dpll1_ck_hw = { + .hw = { + .clk = &dpll1_ck, + }, + .ops = &clkhwops_omap3_dpll, + .dpll_data = &dpll1_dd, + .clkdm_name = "dpll1_clkdm", +}; + +DEFINE_STRUCT_CLK(dpll1_ck, dpll3_ck_parent_names, dpll1_ck_ops); + +DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, "dpll1_ck", &dpll1_ck, 0x0, 2, 1); + +DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck, 0x0, + OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), + OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT, + OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk mpu_ck; + +static const char *mpu_ck_parent_names[] = { + "dpll1_x2m2_ck", +}; + +DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck, "mpu_clkdm"); +DEFINE_STRUCT_CLK(mpu_ck, mpu_ck_parent_names, core_l4_ick_ops); + +DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck, 0x0, + OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), + OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH, + 0x0, NULL); + +static struct clk cam_ick; + +static struct clk_hw_omap cam_ick_hw = { + .hw = { + .clk = &cam_ick, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_CAM_SHIFT, + .clkdm_name = "cam_clkdm", +}; + +DEFINE_STRUCT_CLK(cam_ick, security_l4_ick2_parent_names, aes2_ick_ops); + +/* DPLL4 */ +/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ +/* Type: DPLL */ +static struct dpll_data dpll4_dd; + +static struct dpll_data dpll4_dd_34xx __initdata = { + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), + .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, + .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, + .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), + .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, + .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, + .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, + .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), + .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, + .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, + .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, + .max_divider = OMAP3_MAX_DPLL_DIV, +}; + +static struct dpll_data dpll4_dd_3630 __initdata = { + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), + .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK, + .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, + .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), + .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, + .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, + .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, + .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), + .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, + .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, + .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK, + .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK, + .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT, + .min_divider = 1, + .max_divider = OMAP3_MAX_DPLL_DIV, + .flags = DPLL_J_TYPE +}; + +static struct clk dpll4_ck; + +static const struct clk_ops dpll4_ck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .get_parent = &omap2_init_dpll_parent, + .recalc_rate = &omap3_dpll_recalc, + .set_rate = &omap3_dpll4_set_rate, + .round_rate = &omap2_dpll_round_rate, +}; + +static struct clk_hw_omap dpll4_ck_hw = { + .hw = { + .clk = &dpll4_ck, + }, + .dpll_data = &dpll4_dd, + .ops = &clkhwops_omap3_dpll, + .clkdm_name = "dpll4_clkdm", +}; + +DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops); + +DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0, + OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), + OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk dpll4_m5x2_ck; + +static const char *dpll4_m5x2_ck_parent_names[] = { + "dpll4_m5_ck", +}; + +static const struct clk_ops dpll4_m5x2_ck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap3_clkoutx2_recalc, +}; + +static const struct clk_ops dpll4_m5x2_ck_3630_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap36xx_pwrdn_clk_enable_with_hsdiv_restore, + .disable = &omap2_dflt_clk_disable, + .recalc_rate = &omap3_clkoutx2_recalc, +}; + +static struct clk_hw_omap dpll4_m5x2_ck_hw = { + .hw = { + .clk = &dpll4_m5x2_ck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", +}; + +DEFINE_STRUCT_CLK(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names, dpll4_m5x2_ck_ops); + +static struct clk dpll4_m5x2_ck_3630 = { + .name = "dpll4_m5x2_ck", + .hw = &dpll4_m5x2_ck_hw.hw, + .parent_names = dpll4_m5x2_ck_parent_names, + .num_parents = ARRAY_SIZE(dpll4_m5x2_ck_parent_names), + .ops = &dpll4_m5x2_ck_3630_ops, +}; + +static struct clk cam_mclk; + +static const char *cam_mclk_parent_names[] = { + "dpll4_m5x2_ck", +}; + +static struct clk_hw_omap cam_mclk_hw = { + .hw = { + .clk = &cam_mclk, + }, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_CAM_SHIFT, + .clkdm_name = "cam_clkdm", +}; + +DEFINE_STRUCT_CLK(cam_mclk, cam_mclk_parent_names, aes2_ick_ops); + +static const struct clksel_rate clkout2_src_core_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, + { .div = 0 } +}; + +static const struct clksel_rate clkout2_src_sys_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, + { .div = 0 } +}; + +static const struct clksel_rate clkout2_src_96m_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_3XXX }, + { .div = 0 } +}; + +DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck, 0x0, + OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), + OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk dpll4_m2x2_ck; + +static const char *dpll4_m2x2_ck_parent_names[] = { + "dpll4_m2_ck", +}; + +static struct clk_hw_omap dpll4_m2x2_ck_hw = { + .hw = { + .clk = &dpll4_m2x2_ck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP3430_PWRDN_96M_SHIFT, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", +}; + +DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops); + +static struct clk dpll4_m2x2_ck_3630 = { + .name = "dpll4_m2x2_ck", + .hw = &dpll4_m2x2_ck_hw.hw, + .parent_names = dpll4_m2x2_ck_parent_names, + .num_parents = ARRAY_SIZE(dpll4_m2x2_ck_parent_names), + .ops = &dpll4_m5x2_ck_3630_ops, +}; + +static struct clk omap_96m_alwon_fck; + +static const char *omap_96m_alwon_fck_parent_names[] = { + "dpll4_m2x2_ck", +}; + +DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL); +DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names, + core_ck_ops); + +static struct clk cm_96m_fck; + +static const char *cm_96m_fck_parent_names[] = { + "omap_96m_alwon_fck", +}; + +DEFINE_STRUCT_CLK_HW_OMAP(cm_96m_fck, NULL); +DEFINE_STRUCT_CLK(cm_96m_fck, cm_96m_fck_parent_names, core_ck_ops); + +static const struct clksel_rate clkout2_src_54m_rates[] = { + { .div = 1, .val = 3, .flags = RATE_IN_3XXX }, + { .div = 0 } +}; + +DEFINE_CLK_DIVIDER(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0, + OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), + OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk dpll4_m3x2_ck; + +static const char *dpll4_m3x2_ck_parent_names[] = { + "dpll4_m3_ck", +}; + +static struct clk_hw_omap dpll4_m3x2_ck_hw = { + .hw = { + .clk = &dpll4_m3x2_ck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP3430_PWRDN_TV_SHIFT, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", +}; + +DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops); + +static struct clk dpll4_m3x2_ck_3630 = { + .name = "dpll4_m3x2_ck", + .hw = &dpll4_m3x2_ck_hw.hw, + .parent_names = dpll4_m3x2_ck_parent_names, + .num_parents = ARRAY_SIZE(dpll4_m3x2_ck_parent_names), + .ops = &dpll4_m5x2_ck_3630_ops, +}; + +static const char *omap_54m_fck_parent_names[] = { + "dpll4_m3x2_ck", "sys_altclk", +}; + +DEFINE_CLK_MUX(omap_54m_fck, omap_54m_fck_parent_names, NULL, 0x0, + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_54M_SHIFT, + OMAP3430_SOURCE_54M_WIDTH, 0x0, NULL); + +static const struct clksel clkout2_src_clksel[] = { + { .parent = &core_ck, .rates = clkout2_src_core_rates }, + { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, + { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates }, + { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, + { .parent = NULL }, +}; + +static const char *clkout2_src_ck_parent_names[] = { + "core_ck", "sys_ck", "cm_96m_fck", "omap_54m_fck", +}; + +static const struct clk_ops clkout2_src_ck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +DEFINE_CLK_OMAP_MUX_GATE(clkout2_src_ck, "core_clkdm", + clkout2_src_clksel, OMAP3430_CM_CLKOUT_CTRL, + OMAP3430_CLKOUT2SOURCE_MASK, + OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_EN_SHIFT, + NULL, clkout2_src_ck_parent_names, clkout2_src_ck_ops); + +static const struct clksel_rate omap_48m_cm96m_rates[] = { + { .div = 2, .val = 0, .flags = RATE_IN_3XXX }, + { .div = 0 } +}; + +static const struct clksel_rate omap_48m_alt_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, + { .div = 0 } +}; + +static const struct clksel omap_48m_clksel[] = { + { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates }, + { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, + { .parent = NULL }, +}; + +static const char *omap_48m_fck_parent_names[] = { + "cm_96m_fck", "sys_altclk", +}; + +static struct clk omap_48m_fck; + +static const struct clk_ops omap_48m_fck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk_hw_omap omap_48m_fck_hw = { + .hw = { + .clk = &omap_48m_fck, + }, + .clksel = omap_48m_clksel, + .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_SOURCE_48M_MASK, +}; + +DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops); + +DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck, 0x0, 1, 4); + +static struct clk core_12m_fck; + +static const char *core_12m_fck_parent_names[] = { + "omap_12m_fck", +}; + +DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck, "core_l4_clkdm"); +DEFINE_STRUCT_CLK(core_12m_fck, core_12m_fck_parent_names, core_l4_ick_ops); + +static struct clk core_48m_fck; + +static const char *core_48m_fck_parent_names[] = { + "omap_48m_fck", +}; + +DEFINE_STRUCT_CLK_HW_OMAP(core_48m_fck, "core_l4_clkdm"); +DEFINE_STRUCT_CLK(core_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops); + +static const char *omap_96m_fck_parent_names[] = { + "cm_96m_fck", "sys_ck", +}; + +DEFINE_CLK_MUX(omap_96m_fck, omap_96m_fck_parent_names, NULL, 0x0, + OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), + OMAP3430_SOURCE_96M_SHIFT, OMAP3430_SOURCE_96M_WIDTH, 0x0, NULL); + +static struct clk core_96m_fck; + +static const char *core_96m_fck_parent_names[] = { + "omap_96m_fck", +}; + +DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck, "core_l4_clkdm"); +DEFINE_STRUCT_CLK(core_96m_fck, core_96m_fck_parent_names, core_l4_ick_ops); + +static struct clk core_l3_ick; + +static const char *core_l3_ick_parent_names[] = { + "l3_ick", +}; + +DEFINE_STRUCT_CLK_HW_OMAP(core_l3_ick, "core_l3_clkdm"); +DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops); + +DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck, 0x0, 2, 1); + +static struct clk corex2_fck; + +static const char *corex2_fck_parent_names[] = { + "dpll3_m2x2_ck", +}; + +DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL); +DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops); + +static struct clk cpefuse_fck; + +static struct clk_hw_omap cpefuse_fck_hw = { + .hw = { + .clk = &cpefuse_fck, + }, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), + .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(cpefuse_fck, dpll3_ck_parent_names, aes2_ick_ops); + +static struct clk csi2_96m_fck; + +static const char *csi2_96m_fck_parent_names[] = { + "core_96m_fck", +}; + +static struct clk_hw_omap csi2_96m_fck_hw = { + .hw = { + .clk = &csi2_96m_fck, + }, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_CSI2_SHIFT, + .clkdm_name = "cam_clkdm", +}; + +DEFINE_STRUCT_CLK(csi2_96m_fck, csi2_96m_fck_parent_names, aes2_ick_ops); + +static struct clk d2d_26m_fck; + +static struct clk_hw_omap d2d_26m_fck_hw = { + .hw = { + .clk = &d2d_26m_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, + .clkdm_name = "d2d_clkdm", +}; + +DEFINE_STRUCT_CLK(d2d_26m_fck, dpll3_ck_parent_names, aes2_ick_ops); + +static struct clk des1_ick; + +static struct clk_hw_omap des1_ick_hw = { + .hw = { + .clk = &des1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP3430_EN_DES1_SHIFT, +}; + +DEFINE_STRUCT_CLK(des1_ick, aes1_ick_parent_names, aes1_ick_ops); + +static struct clk des2_ick; + +static struct clk_hw_omap des2_ick_hw = { + .hw = { + .clk = &des2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_DES2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(des2_ick, aes2_ick_parent_names, aes2_ick_ops); + +DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck, 0x0, + OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), + OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk dpll2_fck; + +static struct dpll_data dpll2_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), + .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, + .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, + .clk_bypass = &dpll2_fck, + .clk_ref = &sys_ck, + .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, + .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), + .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, + .modes = ((1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | + (1 << DPLL_LOW_POWER_BYPASS)), + .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, + .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, + .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, + .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), + .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, + .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), + .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK, + .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, + .max_divider = OMAP3_MAX_DPLL_DIV, +}; + +static struct clk dpll2_ck; + +static struct clk_hw_omap dpll2_ck_hw = { + .hw = { + .clk = &dpll2_ck, + }, + .ops = &clkhwops_omap3_dpll, + .dpll_data = &dpll2_dd, + .clkdm_name = "dpll2_clkdm", +}; + +DEFINE_STRUCT_CLK(dpll2_ck, dpll3_ck_parent_names, dpll1_ck_ops); + +DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck, 0x0, + OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), + OMAP3430_IVA2_CLK_SRC_SHIFT, OMAP3430_IVA2_CLK_SRC_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck, 0x0, + OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL), + OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT, + OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck, 0x0, + OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk dpll3_m3x2_ck; + +static const char *dpll3_m3x2_ck_parent_names[] = { + "dpll3_m3_ck", +}; + +static struct clk_hw_omap dpll3_m3x2_ck_hw = { + .hw = { + .clk = &dpll3_m3x2_ck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll3_clkdm", +}; + +DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops); + +static struct clk dpll3_m3x2_ck_3630 = { + .name = "dpll3_m3x2_ck", + .hw = &dpll3_m3x2_ck_hw.hw, + .parent_names = dpll3_m3x2_ck_parent_names, + .num_parents = ARRAY_SIZE(dpll3_m3x2_ck_parent_names), + .ops = &dpll4_m5x2_ck_3630_ops, +}; + +DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1); + +DEFINE_CLK_DIVIDER(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0, + OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), + OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk dpll4_m4x2_ck; + +static const char *dpll4_m4x2_ck_parent_names[] = { + "dpll4_m4_ck", +}; + +static struct clk_hw_omap dpll4_m4x2_ck_hw = { + .hw = { + .clk = &dpll4_m4x2_ck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", +}; + +DEFINE_STRUCT_CLK(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names, dpll4_m5x2_ck_ops); + +static struct clk dpll4_m4x2_ck_3630 = { + .name = "dpll4_m4x2_ck", + .hw = &dpll4_m4x2_ck_hw.hw, + .parent_names = dpll4_m4x2_ck_parent_names, + .num_parents = ARRAY_SIZE(dpll4_m4x2_ck_parent_names), + .ops = &dpll4_m5x2_ck_3630_ops, +}; + +DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0, + OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk dpll4_m6x2_ck; + +static const char *dpll4_m6x2_ck_parent_names[] = { + "dpll4_m6_ck", +}; + +static struct clk_hw_omap dpll4_m6x2_ck_hw = { + .hw = { + .clk = &dpll4_m6x2_ck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, + .flags = INVERT_ENABLE, + .clkdm_name = "dpll4_clkdm", +}; + +DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops); + +static struct clk dpll4_m6x2_ck_3630 = { + .name = "dpll4_m6x2_ck", + .hw = &dpll4_m6x2_ck_hw.hw, + .parent_names = dpll4_m6x2_ck_parent_names, + .num_parents = ARRAY_SIZE(dpll4_m6x2_ck_parent_names), + .ops = &dpll4_m5x2_ck_3630_ops, +}; + +DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck, 0x0, 2, 1); + +static struct dpll_data dpll5_dd = { + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), + .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, + .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), + .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, + .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), + .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, + .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, + .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, + .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), + .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, + .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), + .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, + .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, + .max_divider = OMAP3_MAX_DPLL_DIV, +}; + +static struct clk dpll5_ck; + +static struct clk_hw_omap dpll5_ck_hw = { + .hw = { + .clk = &dpll5_ck, + }, + .ops = &clkhwops_omap3_dpll, + .dpll_data = &dpll5_dd, + .clkdm_name = "dpll5_clkdm", +}; + +DEFINE_STRUCT_CLK(dpll5_ck, dpll3_ck_parent_names, dpll1_ck_ops); + +DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck, 0x0, + OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), + OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk dss1_alwon_fck_3430es1; + +static const char *dss1_alwon_fck_3430es1_parent_names[] = { + "dpll4_m4x2_ck", +}; + +static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = { + .hw = { + .clk = &dss1_alwon_fck_3430es1, + }, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_DSS1_SHIFT, + .clkdm_name = "dss_clkdm", +}; + +DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es1, dss1_alwon_fck_3430es1_parent_names, + aes2_ick_ops); + +static struct clk dss1_alwon_fck_3430es2; + +static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = { + .hw = { + .clk = &dss1_alwon_fck_3430es2, + }, + .ops = &clkhwops_omap3430es2_dss_usbhost_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_DSS1_SHIFT, + .clkdm_name = "dss_clkdm", +}; + +DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es2, dss1_alwon_fck_3430es1_parent_names, + aes2_ick_ops); + +static struct clk dss2_alwon_fck; + +static struct clk_hw_omap dss2_alwon_fck_hw = { + .hw = { + .clk = &dss2_alwon_fck, + }, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_DSS2_SHIFT, + .clkdm_name = "dss_clkdm", +}; + +DEFINE_STRUCT_CLK(dss2_alwon_fck, dpll3_ck_parent_names, aes2_ick_ops); + +static struct clk dss_96m_fck; + +static struct clk_hw_omap dss_96m_fck_hw = { + .hw = { + .clk = &dss_96m_fck, + }, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_TV_SHIFT, + .clkdm_name = "dss_clkdm", +}; + +DEFINE_STRUCT_CLK(dss_96m_fck, core_96m_fck_parent_names, aes2_ick_ops); + +static struct clk dss_ick_3430es1; + +static struct clk_hw_omap dss_ick_3430es1_hw = { + .hw = { + .clk = &dss_ick_3430es1, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, + .clkdm_name = "dss_clkdm", +}; + +DEFINE_STRUCT_CLK(dss_ick_3430es1, security_l4_ick2_parent_names, aes2_ick_ops); + +static struct clk dss_ick_3430es2; + +static struct clk_hw_omap dss_ick_3430es2_hw = { + .hw = { + .clk = &dss_ick_3430es2, + }, + .ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, + .clkdm_name = "dss_clkdm", +}; + +DEFINE_STRUCT_CLK(dss_ick_3430es2, security_l4_ick2_parent_names, aes2_ick_ops); + +static struct clk dss_tv_fck; + +static const char *dss_tv_fck_parent_names[] = { + "omap_54m_fck", +}; + +static struct clk_hw_omap dss_tv_fck_hw = { + .hw = { + .clk = &dss_tv_fck, + }, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_TV_SHIFT, + .clkdm_name = "dss_clkdm", +}; + +DEFINE_STRUCT_CLK(dss_tv_fck, dss_tv_fck_parent_names, aes2_ick_ops); + +static struct clk emac_fck; + +static const char *emac_fck_parent_names[] = { + "rmii_ck", +}; + +static struct clk_hw_omap emac_fck_hw = { + .hw = { + .clk = &emac_fck, + }, + .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), + .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT, +}; + +DEFINE_STRUCT_CLK(emac_fck, emac_fck_parent_names, aes1_ick_ops); + +static struct clk ipss_ick; + +static const char *ipss_ick_parent_names[] = { + "core_l3_ick", +}; + +static struct clk_hw_omap ipss_ick_hw = { + .hw = { + .clk = &ipss_ick, + }, + .ops = &clkhwops_am35xx_ipss_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = AM35XX_EN_IPSS_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(ipss_ick, ipss_ick_parent_names, aes2_ick_ops); + +static struct clk emac_ick; + +static const char *emac_ick_parent_names[] = { + "ipss_ick", +}; + +static struct clk_hw_omap emac_ick_hw = { + .hw = { + .clk = &emac_ick, + }, + .ops = &clkhwops_am35xx_ipss_module_wait, + .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), + .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(emac_ick, emac_ick_parent_names, aes2_ick_ops); + +static struct clk emu_core_alwon_ck; + +static const char *emu_core_alwon_ck_parent_names[] = { + "dpll3_m3x2_ck", +}; + +DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck, "dpll3_clkdm"); +DEFINE_STRUCT_CLK(emu_core_alwon_ck, emu_core_alwon_ck_parent_names, + core_l4_ick_ops); + +static struct clk emu_mpu_alwon_ck; + +static const char *emu_mpu_alwon_ck_parent_names[] = { + "mpu_ck", +}; + +DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck, NULL); +DEFINE_STRUCT_CLK(emu_mpu_alwon_ck, emu_mpu_alwon_ck_parent_names, core_ck_ops); + +static struct clk emu_per_alwon_ck; + +static const char *emu_per_alwon_ck_parent_names[] = { + "dpll4_m6x2_ck", +}; + +DEFINE_STRUCT_CLK_HW_OMAP(emu_per_alwon_ck, "dpll4_clkdm"); +DEFINE_STRUCT_CLK(emu_per_alwon_ck, emu_per_alwon_ck_parent_names, + core_l4_ick_ops); + +static const char *emu_src_ck_parent_names[] = { + "sys_ck", "emu_core_alwon_ck", "emu_per_alwon_ck", "emu_mpu_alwon_ck", +}; + +static const struct clksel_rate emu_src_sys_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, + { .div = 0 }, +}; + +static const struct clksel_rate emu_src_core_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, + { .div = 0 }, +}; + +static const struct clksel_rate emu_src_per_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_3XXX }, + { .div = 0 }, +}; + +static const struct clksel_rate emu_src_mpu_rates[] = { + { .div = 1, .val = 3, .flags = RATE_IN_3XXX }, + { .div = 0 }, +}; + +static const struct clksel emu_src_clksel[] = { + { .parent = &sys_ck, .rates = emu_src_sys_rates }, + { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, + { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, + { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, + { .parent = NULL }, +}; + +static const struct clk_ops emu_src_ck_ops = { + .init = &omap2_init_clk_clkdm, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +static struct clk emu_src_ck; + +static struct clk_hw_omap emu_src_ck_hw = { + .hw = { + .clk = &emu_src_ck, + }, + .clksel = emu_src_clksel, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + .clksel_mask = OMAP3430_MUX_CTRL_MASK, + .clkdm_name = "emu_clkdm", +}; + +DEFINE_STRUCT_CLK(emu_src_ck, emu_src_ck_parent_names, emu_src_ck_ops); + +DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0, + OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk fac_ick; + +static struct clk_hw_omap fac_ick_hw = { + .hw = { + .clk = &fac_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk fshostusb_fck; + +static const char *fshostusb_fck_parent_names[] = { + "core_48m_fck", +}; + +static struct clk_hw_omap fshostusb_fck_hw = { + .hw = { + .clk = &fshostusb_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(fshostusb_fck, fshostusb_fck_parent_names, aes2_ick_ops); + +static struct clk gfx_l3_ck; + +static struct clk_hw_omap gfx_l3_ck_hw = { + .hw = { + .clk = &gfx_l3_ck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), + .enable_bit = OMAP_EN_GFX_SHIFT, + .clkdm_name = "gfx_3430es1_clkdm", +}; + +DEFINE_STRUCT_CLK(gfx_l3_ck, core_l3_ick_parent_names, aes1_ick_ops); + +DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick, 0x0, + OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), + OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk gfx_cg1_ck; + +static const char *gfx_cg1_ck_parent_names[] = { + "gfx_l3_fck", +}; + +static struct clk_hw_omap gfx_cg1_ck_hw = { + .hw = { + .clk = &gfx_cg1_ck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES1_EN_2D_SHIFT, + .clkdm_name = "gfx_3430es1_clkdm", +}; + +DEFINE_STRUCT_CLK(gfx_cg1_ck, gfx_cg1_ck_parent_names, aes2_ick_ops); + +static struct clk gfx_cg2_ck; + +static struct clk_hw_omap gfx_cg2_ck_hw = { + .hw = { + .clk = &gfx_cg2_ck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES1_EN_3D_SHIFT, + .clkdm_name = "gfx_3430es1_clkdm", +}; + +DEFINE_STRUCT_CLK(gfx_cg2_ck, gfx_cg1_ck_parent_names, aes2_ick_ops); + +static struct clk gfx_l3_ick; + +static const char *gfx_l3_ick_parent_names[] = { + "gfx_l3_ck", +}; + +DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick, "gfx_3430es1_clkdm"); +DEFINE_STRUCT_CLK(gfx_l3_ick, gfx_l3_ick_parent_names, core_l4_ick_ops); + +static struct clk wkup_32k_fck; + +static const char *wkup_32k_fck_parent_names[] = { + "omap_32k_fck", +}; + +DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck, "wkup_clkdm"); +DEFINE_STRUCT_CLK(wkup_32k_fck, wkup_32k_fck_parent_names, core_l4_ick_ops); + +static struct clk gpio1_dbck; + +static const char *gpio1_dbck_parent_names[] = { + "wkup_32k_fck", +}; + +static struct clk_hw_omap gpio1_dbck_hw = { + .hw = { + .clk = &gpio1_dbck, + }, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPIO1_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops); + +static struct clk wkup_l4_ick; + +DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm"); +DEFINE_STRUCT_CLK(wkup_l4_ick, dpll3_ck_parent_names, core_l4_ick_ops); + +static struct clk gpio1_ick; + +static const char *gpio1_ick_parent_names[] = { + "wkup_l4_ick", +}; + +static struct clk_hw_omap gpio1_ick_hw = { + .hw = { + .clk = &gpio1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPIO1_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpio1_ick, gpio1_ick_parent_names, aes2_ick_ops); + +static struct clk per_32k_alwon_fck; + +DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck, "per_clkdm"); +DEFINE_STRUCT_CLK(per_32k_alwon_fck, wkup_32k_fck_parent_names, + core_l4_ick_ops); + +static struct clk gpio2_dbck; + +static const char *gpio2_dbck_parent_names[] = { + "per_32k_alwon_fck", +}; + +static struct clk_hw_omap gpio2_dbck_hw = { + .hw = { + .clk = &gpio2_dbck, + }, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPIO2_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(gpio2_dbck, gpio2_dbck_parent_names, aes2_ick_ops); + +static struct clk per_l4_ick; + +DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick, "per_clkdm"); +DEFINE_STRUCT_CLK(per_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); + +static struct clk gpio2_ick; + +static const char *gpio2_ick_parent_names[] = { + "per_l4_ick", +}; + +static struct clk_hw_omap gpio2_ick_hw = { + .hw = { + .clk = &gpio2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPIO2_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(gpio2_ick, gpio2_ick_parent_names, aes2_ick_ops); + +static struct clk gpio3_dbck; + +static struct clk_hw_omap gpio3_dbck_hw = { + .hw = { + .clk = &gpio3_dbck, + }, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPIO3_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(gpio3_dbck, gpio2_dbck_parent_names, aes2_ick_ops); + +static struct clk gpio3_ick; + +static struct clk_hw_omap gpio3_ick_hw = { + .hw = { + .clk = &gpio3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPIO3_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(gpio3_ick, gpio2_ick_parent_names, aes2_ick_ops); + +static struct clk gpio4_dbck; + +static struct clk_hw_omap gpio4_dbck_hw = { + .hw = { + .clk = &gpio4_dbck, + }, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPIO4_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(gpio4_dbck, gpio2_dbck_parent_names, aes2_ick_ops); + +static struct clk gpio4_ick; + +static struct clk_hw_omap gpio4_ick_hw = { + .hw = { + .clk = &gpio4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPIO4_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(gpio4_ick, gpio2_ick_parent_names, aes2_ick_ops); + +static struct clk gpio5_dbck; + +static struct clk_hw_omap gpio5_dbck_hw = { + .hw = { + .clk = &gpio5_dbck, + }, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPIO5_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(gpio5_dbck, gpio2_dbck_parent_names, aes2_ick_ops); + +static struct clk gpio5_ick; + +static struct clk_hw_omap gpio5_ick_hw = { + .hw = { + .clk = &gpio5_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPIO5_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(gpio5_ick, gpio2_ick_parent_names, aes2_ick_ops); + +static struct clk gpio6_dbck; + +static struct clk_hw_omap gpio6_dbck_hw = { + .hw = { + .clk = &gpio6_dbck, + }, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_GPIO6_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(gpio6_dbck, gpio2_dbck_parent_names, aes2_ick_ops); + +static struct clk gpio6_ick; + +static struct clk_hw_omap gpio6_ick_hw = { + .hw = { + .clk = &gpio6_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPIO6_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(gpio6_ick, gpio2_ick_parent_names, aes2_ick_ops); + +static struct clk gpmc_fck; + +static struct clk_hw_omap gpmc_fck_hw = { + .hw = { + .clk = &gpmc_fck, + }, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(gpmc_fck, ipss_ick_parent_names, core_l4_ick_ops); + +static const struct clksel omap343x_gpt_clksel[] = { + { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, + { .parent = &sys_ck, .rates = gpt_sys_rates }, + { .parent = NULL }, +}; + +static const char *gpt10_fck_parent_names[] = { + "omap_32k_fck", "sys_ck", +}; + +DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap343x_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + OMAP3430_CLKSEL_GPT10_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP3430_EN_GPT10_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, clkout2_src_ck_ops); + +static struct clk gpt10_ick; + +static struct clk_hw_omap gpt10_ick_hw = { + .hw = { + .clk = &gpt10_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_GPT10_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt10_ick, aes2_ick_parent_names, aes2_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap343x_gpt_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + OMAP3430_CLKSEL_GPT11_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP3430_EN_GPT11_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, clkout2_src_ck_ops); + +static struct clk gpt11_ick; + +static struct clk_hw_omap gpt11_ick_hw = { + .hw = { + .clk = &gpt11_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_GPT11_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt11_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk gpt12_fck; + +static const char *gpt12_fck_parent_names[] = { + "secure_32k_fck", +}; + +DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck, "wkup_clkdm"); +DEFINE_STRUCT_CLK(gpt12_fck, gpt12_fck_parent_names, core_l4_ick_ops); + +static struct clk gpt12_ick; + +static struct clk_hw_omap gpt12_ick_hw = { + .hw = { + .clk = &gpt12_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT12_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt12_ick, gpio1_ick_parent_names, aes2_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "wkup_clkdm", omap343x_gpt_clksel, + OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), + OMAP3430_CLKSEL_GPT1_MASK, + OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + OMAP3430_EN_GPT1_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, clkout2_src_ck_ops); + +static struct clk gpt1_ick; + +static struct clk_hw_omap gpt1_ick_hw = { + .hw = { + .clk = &gpt1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT1_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt1_ick, gpio1_ick_parent_names, aes2_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "per_clkdm", omap343x_gpt_clksel, + OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + OMAP3430_CLKSEL_GPT2_MASK, + OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + OMAP3430_EN_GPT2_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, clkout2_src_ck_ops); + +static struct clk gpt2_ick; + +static struct clk_hw_omap gpt2_ick_hw = { + .hw = { + .clk = &gpt2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT2_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt2_ick, gpio2_ick_parent_names, aes2_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "per_clkdm", omap343x_gpt_clksel, + OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + OMAP3430_CLKSEL_GPT3_MASK, + OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + OMAP3430_EN_GPT3_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, clkout2_src_ck_ops); + +static struct clk gpt3_ick; + +static struct clk_hw_omap gpt3_ick_hw = { + .hw = { + .clk = &gpt3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT3_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt3_ick, gpio2_ick_parent_names, aes2_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "per_clkdm", omap343x_gpt_clksel, + OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + OMAP3430_CLKSEL_GPT4_MASK, + OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + OMAP3430_EN_GPT4_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, clkout2_src_ck_ops); + +static struct clk gpt4_ick; + +static struct clk_hw_omap gpt4_ick_hw = { + .hw = { + .clk = &gpt4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT4_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt4_ick, gpio2_ick_parent_names, aes2_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "per_clkdm", omap343x_gpt_clksel, + OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + OMAP3430_CLKSEL_GPT5_MASK, + OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + OMAP3430_EN_GPT5_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, clkout2_src_ck_ops); + +static struct clk gpt5_ick; + +static struct clk_hw_omap gpt5_ick_hw = { + .hw = { + .clk = &gpt5_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT5_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt5_ick, gpio2_ick_parent_names, aes2_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "per_clkdm", omap343x_gpt_clksel, + OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + OMAP3430_CLKSEL_GPT6_MASK, + OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + OMAP3430_EN_GPT6_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, clkout2_src_ck_ops); + +static struct clk gpt6_ick; + +static struct clk_hw_omap gpt6_ick_hw = { + .hw = { + .clk = &gpt6_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT6_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt6_ick, gpio2_ick_parent_names, aes2_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "per_clkdm", omap343x_gpt_clksel, + OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + OMAP3430_CLKSEL_GPT7_MASK, + OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + OMAP3430_EN_GPT7_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, clkout2_src_ck_ops); + +static struct clk gpt7_ick; + +static struct clk_hw_omap gpt7_ick_hw = { + .hw = { + .clk = &gpt7_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT7_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt7_ick, gpio2_ick_parent_names, aes2_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "per_clkdm", omap343x_gpt_clksel, + OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + OMAP3430_CLKSEL_GPT8_MASK, + OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + OMAP3430_EN_GPT8_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, clkout2_src_ck_ops); + +static struct clk gpt8_ick; + +static struct clk_hw_omap gpt8_ick_hw = { + .hw = { + .clk = &gpt8_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT8_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt8_ick, gpio2_ick_parent_names, aes2_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "per_clkdm", omap343x_gpt_clksel, + OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), + OMAP3430_CLKSEL_GPT9_MASK, + OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + OMAP3430_EN_GPT9_SHIFT, &clkhwops_wait, + gpt10_fck_parent_names, clkout2_src_ck_ops); + +static struct clk gpt9_ick; + +static struct clk_hw_omap gpt9_ick_hw = { + .hw = { + .clk = &gpt9_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_GPT9_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(gpt9_ick, gpio2_ick_parent_names, aes2_ick_ops); + +static struct clk hdq_fck; + +static const char *hdq_fck_parent_names[] = { + "core_12m_fck", +}; + +static struct clk_hw_omap hdq_fck_hw = { + .hw = { + .clk = &hdq_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_HDQ_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(hdq_fck, hdq_fck_parent_names, aes2_ick_ops); + +static struct clk hdq_ick; + +static struct clk_hw_omap hdq_ick_hw = { + .hw = { + .clk = &hdq_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_HDQ_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(hdq_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk hecc_ck; + +static struct clk_hw_omap hecc_ck_hw = { + .hw = { + .clk = &hecc_ck, + }, + .ops = &clkhwops_am35xx_ipss_module_wait, + .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), + .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(hecc_ck, dpll3_ck_parent_names, aes2_ick_ops); + +static struct clk hsotgusb_fck_am35xx; + +static struct clk_hw_omap hsotgusb_fck_am35xx_hw = { + .hw = { + .clk = &hsotgusb_fck_am35xx, + }, + .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), + .enable_bit = AM35XX_USBOTG_FCLK_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, dpll3_ck_parent_names, aes2_ick_ops); + +static struct clk hsotgusb_ick_3430es1; + +static struct clk_hw_omap hsotgusb_ick_3430es1_hw = { + .hw = { + .clk = &hsotgusb_ick_3430es1, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1, ipss_ick_parent_names, aes2_ick_ops); + +static struct clk hsotgusb_ick_3430es2; + +static struct clk_hw_omap hsotgusb_ick_3430es2_hw = { + .hw = { + .clk = &hsotgusb_ick_3430es2, + }, + .ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2, ipss_ick_parent_names, aes2_ick_ops); + +static struct clk hsotgusb_ick_am35xx; + +static struct clk_hw_omap hsotgusb_ick_am35xx_hw = { + .hw = { + .clk = &hsotgusb_ick_am35xx, + }, + .ops = &clkhwops_am35xx_ipss_module_wait, + .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), + .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx, emac_ick_parent_names, aes2_ick_ops); + +static struct clk i2c1_fck; + +static struct clk_hw_omap i2c1_fck_hw = { + .hw = { + .clk = &i2c1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_I2C1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c1_fck, csi2_96m_fck_parent_names, aes2_ick_ops); + +static struct clk i2c1_ick; + +static struct clk_hw_omap i2c1_ick_hw = { + .hw = { + .clk = &i2c1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_I2C1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c1_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk i2c2_fck; + +static struct clk_hw_omap i2c2_fck_hw = { + .hw = { + .clk = &i2c2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_I2C2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c2_fck, csi2_96m_fck_parent_names, aes2_ick_ops); + +static struct clk i2c2_ick; + +static struct clk_hw_omap i2c2_ick_hw = { + .hw = { + .clk = &i2c2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_I2C2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c2_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk i2c3_fck; + +static struct clk_hw_omap i2c3_fck_hw = { + .hw = { + .clk = &i2c3_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_I2C3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c3_fck, csi2_96m_fck_parent_names, aes2_ick_ops); + +static struct clk i2c3_ick; + +static struct clk_hw_omap i2c3_ick_hw = { + .hw = { + .clk = &i2c3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_I2C3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(i2c3_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk icr_ick; + +static struct clk_hw_omap icr_ick_hw = { + .hw = { + .clk = &icr_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_ICR_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(icr_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk iva2_ck; + +static const char *iva2_ck_parent_names[] = { + "dpll2_m2_ck", +}; + +static struct clk_hw_omap iva2_ck_hw = { + .hw = { + .clk = &iva2_ck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, + .clkdm_name = "iva2_clkdm", +}; + +DEFINE_STRUCT_CLK(iva2_ck, iva2_ck_parent_names, aes2_ick_ops); + +static struct clk mad2d_ick; + +static struct clk_hw_omap mad2d_ick_hw = { + .hw = { + .clk = &mad2d_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP3430_EN_MAD2D_SHIFT, + .clkdm_name = "d2d_clkdm", +}; + +DEFINE_STRUCT_CLK(mad2d_ick, core_l3_ick_parent_names, aes2_ick_ops); + +static struct clk mailboxes_ick; + +static struct clk_hw_omap mailboxes_ick_hw = { + .hw = { + .clk = &mailboxes_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mailboxes_ick, aes2_ick_parent_names, aes2_ick_ops); + +static const struct clksel_rate common_mcbsp_96m_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, + { .div = 0 } +}; + +static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, + { .div = 0 } +}; + +static const struct clksel mcbsp_15_clksel[] = { + { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp1_fck_parent_names[] = { + "core_96m_fck", "mcbsp_clks", +}; + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_15_clksel, + OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + OMAP2_MCBSP1_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP3430_EN_MCBSP1_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, clkout2_src_ck_ops); + +static struct clk mcbsp1_ick; + +static struct clk_hw_omap mcbsp1_ick_hw = { + .hw = { + .clk = &mcbsp1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp1_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk per_96m_fck; + +DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck, "per_clkdm"); +DEFINE_STRUCT_CLK(per_96m_fck, cm_96m_fck_parent_names, core_l4_ick_ops); + +static const struct clksel mcbsp_234_clksel[] = { + { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp2_fck_parent_names[] = { + "per_96m_fck", "mcbsp_clks", +}; + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "per_clkdm", mcbsp_234_clksel, + OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + OMAP2_MCBSP2_CLKS_MASK, + OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + OMAP3430_EN_MCBSP2_SHIFT, &clkhwops_wait, + mcbsp2_fck_parent_names, clkout2_src_ck_ops); + +static struct clk mcbsp2_ick; + +static struct clk_hw_omap mcbsp2_ick_hw = { + .hw = { + .clk = &mcbsp2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp2_ick, gpio2_ick_parent_names, aes2_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "per_clkdm", mcbsp_234_clksel, + OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), + OMAP2_MCBSP3_CLKS_MASK, + OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + OMAP3430_EN_MCBSP3_SHIFT, &clkhwops_wait, + mcbsp2_fck_parent_names, clkout2_src_ck_ops); + +static struct clk mcbsp3_ick; + +static struct clk_hw_omap mcbsp3_ick_hw = { + .hw = { + .clk = &mcbsp3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp3_ick, gpio2_ick_parent_names, aes2_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "per_clkdm", mcbsp_234_clksel, + OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), + OMAP2_MCBSP4_CLKS_MASK, + OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + OMAP3430_EN_MCBSP4_SHIFT, &clkhwops_wait, + mcbsp2_fck_parent_names, clkout2_src_ck_ops); + +static struct clk mcbsp4_ick; + +static struct clk_hw_omap mcbsp4_ick_hw = { + .hw = { + .clk = &mcbsp4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp4_ick, gpio2_ick_parent_names, aes2_ick_ops); + +DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_15_clksel, + OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), + OMAP2_MCBSP5_CLKS_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP3430_EN_MCBSP5_SHIFT, &clkhwops_wait, + mcbsp1_fck_parent_names, clkout2_src_ck_ops); + +static struct clk mcbsp5_ick; + +static struct clk_hw_omap mcbsp5_ick_hw = { + .hw = { + .clk = &mcbsp5_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcbsp5_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk mcspi1_fck; + +static struct clk_hw_omap mcspi1_fck_hw = { + .hw = { + .clk = &mcspi1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi1_fck, fshostusb_fck_parent_names, aes2_ick_ops); + +static struct clk mcspi1_ick; + +static struct clk_hw_omap mcspi1_ick_hw = { + .hw = { + .clk = &mcspi1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi1_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk mcspi2_fck; + +static struct clk_hw_omap mcspi2_fck_hw = { + .hw = { + .clk = &mcspi2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi2_fck, fshostusb_fck_parent_names, aes2_ick_ops); + +static struct clk mcspi2_ick; + +static struct clk_hw_omap mcspi2_ick_hw = { + .hw = { + .clk = &mcspi2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi2_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk mcspi3_fck; + +static struct clk_hw_omap mcspi3_fck_hw = { + .hw = { + .clk = &mcspi3_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi3_fck, fshostusb_fck_parent_names, aes2_ick_ops); + +static struct clk mcspi3_ick; + +static struct clk_hw_omap mcspi3_ick_hw = { + .hw = { + .clk = &mcspi3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi3_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk mcspi4_fck; + +static struct clk_hw_omap mcspi4_fck_hw = { + .hw = { + .clk = &mcspi4_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi4_fck, fshostusb_fck_parent_names, aes2_ick_ops); + +static struct clk mcspi4_ick; + +static struct clk_hw_omap mcspi4_ick_hw = { + .hw = { + .clk = &mcspi4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mcspi4_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk mmchs1_fck; + +static struct clk_hw_omap mmchs1_fck_hw = { + .hw = { + .clk = &mmchs1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MMC1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchs1_fck, csi2_96m_fck_parent_names, aes2_ick_ops); + +static struct clk mmchs1_ick; + +static struct clk_hw_omap mmchs1_ick_hw = { + .hw = { + .clk = &mmchs1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MMC1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchs1_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk mmchs2_fck; + +static struct clk_hw_omap mmchs2_fck_hw = { + .hw = { + .clk = &mmchs2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MMC2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchs2_fck, csi2_96m_fck_parent_names, aes2_ick_ops); + +static struct clk mmchs2_ick; + +static struct clk_hw_omap mmchs2_ick_hw = { + .hw = { + .clk = &mmchs2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MMC2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchs2_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk mmchs3_fck; + +static struct clk_hw_omap mmchs3_fck_hw = { + .hw = { + .clk = &mmchs3_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchs3_fck, csi2_96m_fck_parent_names, aes2_ick_ops); + +static struct clk mmchs3_ick; + +static struct clk_hw_omap mmchs3_ick_hw = { + .hw = { + .clk = &mmchs3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mmchs3_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk modem_fck; + +static struct clk_hw_omap modem_fck_hw = { + .hw = { + .clk = &modem_fck, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MODEM_SHIFT, + .clkdm_name = "d2d_clkdm", +}; + +DEFINE_STRUCT_CLK(modem_fck, dpll3_ck_parent_names, aes2_ick_ops); + +static struct clk mspro_fck; + +static struct clk_hw_omap mspro_fck_hw = { + .hw = { + .clk = &mspro_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_MSPRO_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mspro_fck, csi2_96m_fck_parent_names, aes2_ick_ops); + +static struct clk mspro_ick; + +static struct clk_hw_omap mspro_ick_hw = { + .hw = { + .clk = &mspro_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_MSPRO_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(mspro_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk omap_192m_alwon_fck; + +DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck, NULL); +DEFINE_STRUCT_CLK(omap_192m_alwon_fck, omap_96m_alwon_fck_parent_names, + core_ck_ops); + +static struct clk omap_32ksync_ick; + +static struct clk_hw_omap omap_32ksync_ick_hw = { + .hw = { + .clk = &omap_32ksync_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(omap_32ksync_ick, gpio1_ick_parent_names, aes2_ick_ops); + +static const struct clksel_rate omap_96m_alwon_fck_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_36XX }, + { .div = 2, .val = 2, .flags = RATE_IN_36XX }, + { .div = 0 } +}; + +static const struct clksel omap_96m_alwon_fck_clksel[] = { + { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates }, + { .parent = NULL } +}; + +static struct clk omap_96m_alwon_fck_3630; + +static const char *omap_96m_alwon_fck_3630_parent_names[] = { + "omap_192m_alwon_fck", +}; + +static const struct clk_ops omap_96m_alwon_fck_3630_ops = { + .set_rate = &omap2_clksel_set_rate, + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, +}; + +static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = { + .hw = { + .clk = &omap_96m_alwon_fck_3630, + }, + .clksel = omap_96m_alwon_fck_clksel, + .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + .clksel_mask = OMAP3630_CLKSEL_96M_MASK, +}; + +static struct clk omap_96m_alwon_fck_3630 = { + .name = "omap_96m_alwon_fck", + .hw = &omap_96m_alwon_fck_3630_hw.hw, + .parent_names = omap_96m_alwon_fck_3630_parent_names, + .num_parents = ARRAY_SIZE(omap_96m_alwon_fck_3630_parent_names), + .ops = &omap_96m_alwon_fck_3630_ops, +}; + +static struct clk omapctrl_ick; + +static struct clk_hw_omap omapctrl_ick_hw = { + .hw = { + .clk = &omapctrl_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(omapctrl_ick, aes2_ick_parent_names, aes2_ick_ops); + +DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck, 0x0, + OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + OMAP3430_CLKSEL_PCLK_SHIFT, OMAP3430_CLKSEL_PCLK_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck, 0x0, + OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk per_48m_fck; + +DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck, "per_clkdm"); +DEFINE_STRUCT_CLK(per_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops); + +static struct clk security_l3_ick; + +DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL); +DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops); + +static struct clk pka_ick; + +static const char *pka_ick_parent_names[] = { + "security_l3_ick", +}; + +static struct clk_hw_omap pka_ick_hw = { + .hw = { + .clk = &pka_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP3430_EN_PKA_SHIFT, +}; + +DEFINE_STRUCT_CLK(pka_ick, pka_ick_parent_names, aes1_ick_ops); + +DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0, + OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), + OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk rng_ick; + +static struct clk_hw_omap rng_ick_hw = { + .hw = { + .clk = &rng_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP3430_EN_RNG_SHIFT, +}; + +DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops); + +static struct clk sad2d_ick; + +static struct clk_hw_omap sad2d_ick_hw = { + .hw = { + .clk = &sad2d_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_SAD2D_SHIFT, + .clkdm_name = "d2d_clkdm", +}; + +DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops); + +static struct clk sdrc_ick; + +static struct clk_hw_omap sdrc_ick_hw = { + .hw = { + .clk = &sdrc_ick, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_SDRC_SHIFT, + .flags = ENABLE_ON_INIT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(sdrc_ick, ipss_ick_parent_names, aes2_ick_ops); + +static const struct clksel_rate sgx_core_rates[] = { + { .div = 2, .val = 5, .flags = RATE_IN_36XX }, + { .div = 3, .val = 0, .flags = RATE_IN_3XXX }, + { .div = 4, .val = 1, .flags = RATE_IN_3XXX }, + { .div = 6, .val = 2, .flags = RATE_IN_3XXX }, + { .div = 0 } +}; + +static const struct clksel_rate sgx_96m_rates[] = { + { .div = 1, .val = 3, .flags = RATE_IN_3XXX }, + { .div = 0 } +}; + +static const struct clksel_rate sgx_192m_rates[] = { + { .div = 1, .val = 4, .flags = RATE_IN_36XX }, + { .div = 0 } +}; + +static const struct clksel_rate sgx_corex2_rates[] = { + { .div = 3, .val = 6, .flags = RATE_IN_36XX }, + { .div = 5, .val = 7, .flags = RATE_IN_36XX }, + { .div = 0 } +}; + +static const struct clksel sgx_clksel[] = { + { .parent = &core_ck, .rates = sgx_core_rates }, + { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, + { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates }, + { .parent = &corex2_fck, .rates = sgx_corex2_rates }, + { .parent = NULL }, +}; + +static const char *sgx_fck_parent_names[] = { + "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck", +}; + +static struct clk sgx_fck; + +static const struct clk_ops sgx_fck_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +DEFINE_CLK_OMAP_MUX_GATE(sgx_fck, "sgx_clkdm", sgx_clksel, + OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), + OMAP3430ES2_CLKSEL_SGX_MASK, + OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), + OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, + &clkhwops_wait, sgx_fck_parent_names, sgx_fck_ops); + +static struct clk sgx_ick; + +static struct clk_hw_omap sgx_ick_hw = { + .hw = { + .clk = &sgx_ick, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), + .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, + .clkdm_name = "sgx_clkdm", +}; + +DEFINE_STRUCT_CLK(sgx_ick, core_l3_ick_parent_names, aes2_ick_ops); + +static struct clk sha11_ick; + +static struct clk_hw_omap sha11_ick_hw = { + .hw = { + .clk = &sha11_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), + .enable_bit = OMAP3430_EN_SHA11_SHIFT, +}; + +DEFINE_STRUCT_CLK(sha11_ick, aes1_ick_parent_names, aes1_ick_ops); + +static struct clk sha12_ick; + +static struct clk_hw_omap sha12_ick_hw = { + .hw = { + .clk = &sha12_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_SHA12_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(sha12_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk sr1_fck; + +static struct clk_hw_omap sr1_fck_hw = { + .hw = { + .clk = &sr1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_SR1_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(sr1_fck, dpll3_ck_parent_names, aes2_ick_ops); + +static struct clk sr2_fck; + +static struct clk_hw_omap sr2_fck_hw = { + .hw = { + .clk = &sr2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_SR2_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(sr2_fck, dpll3_ck_parent_names, aes2_ick_ops); + +static struct clk sr_l4_ick; + +DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick, "core_l4_clkdm"); +DEFINE_STRUCT_CLK(sr_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); + +static struct clk ssi_l4_ick; + +DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick, "core_l4_clkdm"); +DEFINE_STRUCT_CLK(ssi_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops); + +static struct clk ssi_ick_3430es1; + +static const char *ssi_ick_3430es1_parent_names[] = { + "ssi_l4_ick", +}; + +static struct clk_hw_omap ssi_ick_3430es1_hw = { + .hw = { + .clk = &ssi_ick_3430es1, + }, + .ops = &clkhwops_iclk, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_SSI_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(ssi_ick_3430es1, ssi_ick_3430es1_parent_names, aes2_ick_ops); + +static struct clk ssi_ick_3430es2; + +static struct clk_hw_omap ssi_ick_3430es2_hw = { + .hw = { + .clk = &ssi_ick_3430es2, + }, + .ops = &clkhwops_omap3430es2_iclk_ssi_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_SSI_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(ssi_ick_3430es2, ssi_ick_3430es1_parent_names, aes2_ick_ops); + +static const struct clksel_rate ssi_ssr_corex2_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, + { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, + { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, + { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, + { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, + { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, + { .div = 0 } +}; + +static const struct clksel ssi_ssr_clksel[] = { + { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, + { .parent = NULL }, +}; + +static const char *ssi_ssr_fck_3430es1_parent_names[] = { + "corex2_fck", +}; + +static const struct clk_ops ssi_ssr_fck_3430es1_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, +}; + +DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es1, "core_l4_clkdm", + ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + OMAP3430_CLKSEL_SSI_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP3430_EN_SSI_SHIFT, + NULL, ssi_ssr_fck_3430es1_parent_names, + ssi_ssr_fck_3430es1_ops); + +DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es2, "core_l4_clkdm", + ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + OMAP3430_CLKSEL_SSI_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + OMAP3430_EN_SSI_SHIFT, + NULL, ssi_ssr_fck_3430es1_parent_names, + ssi_ssr_fck_3430es1_ops); + +DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1", + &ssi_ssr_fck_3430es1, 0x0, 1, 2); + +DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2", + &ssi_ssr_fck_3430es2, 0x0, 1, 2); + +static struct clk sys_clkout1; + +static const char *sys_clkout1_parent_names[] = { + "osc_sys_ck", +}; + +static struct clk_hw_omap sys_clkout1_hw = { + .hw = { + .clk = &sys_clkout1, + }, + .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, + .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, +}; + +DEFINE_STRUCT_CLK(sys_clkout1, sys_clkout1_parent_names, aes1_ick_ops); + +DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck, 0x0, + OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_DIV_SHIFT, + OMAP3430_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +DEFINE_CLK_MUX(traceclk_src_fck, emu_src_ck_parent_names, NULL, 0x0, + OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + OMAP3430_TRACE_MUX_CTRL_SHIFT, OMAP3430_TRACE_MUX_CTRL_WIDTH, + 0x0, NULL); + +DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck, 0x0, + OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), + OMAP3430_CLKSEL_TRACECLK_SHIFT, + OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); + +static struct clk ts_fck; + +static struct clk_hw_omap ts_fck_hw = { + .hw = { + .clk = &ts_fck, + }, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), + .enable_bit = OMAP3430ES2_EN_TS_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(ts_fck, wkup_32k_fck_parent_names, aes2_ick_ops); + +static struct clk uart1_fck; + +static struct clk_hw_omap uart1_fck_hw = { + .hw = { + .clk = &uart1_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_UART1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart1_fck, fshostusb_fck_parent_names, aes2_ick_ops); + +static struct clk uart1_ick; + +static struct clk_hw_omap uart1_ick_hw = { + .hw = { + .clk = &uart1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_UART1_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart1_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk uart2_fck; + +static struct clk_hw_omap uart2_fck_hw = { + .hw = { + .clk = &uart2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = OMAP3430_EN_UART2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart2_fck, fshostusb_fck_parent_names, aes2_ick_ops); + +static struct clk uart2_ick; + +static struct clk_hw_omap uart2_ick_hw = { + .hw = { + .clk = &uart2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = OMAP3430_EN_UART2_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart2_ick, aes2_ick_parent_names, aes2_ick_ops); + +static struct clk uart3_fck; + +static const char *uart3_fck_parent_names[] = { + "per_48m_fck", +}; + +static struct clk_hw_omap uart3_fck_hw = { + .hw = { + .clk = &uart3_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_UART3_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(uart3_fck, uart3_fck_parent_names, aes2_ick_ops); + +static struct clk uart3_ick; + +static struct clk_hw_omap uart3_ick_hw = { + .hw = { + .clk = &uart3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_UART3_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(uart3_ick, gpio2_ick_parent_names, aes2_ick_ops); + +static struct clk uart4_fck; + +static struct clk_hw_omap uart4_fck_hw = { + .hw = { + .clk = &uart4_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3630_EN_UART4_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(uart4_fck, uart3_fck_parent_names, aes2_ick_ops); + +static struct clk uart4_fck_am35xx; + +static struct clk_hw_omap uart4_fck_am35xx_hw = { + .hw = { + .clk = &uart4_fck_am35xx, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), + .enable_bit = AM35XX_EN_UART4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart4_fck_am35xx, fshostusb_fck_parent_names, aes2_ick_ops); + +static struct clk uart4_ick; + +static struct clk_hw_omap uart4_ick_hw = { + .hw = { + .clk = &uart4_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3630_EN_UART4_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(uart4_ick, gpio2_ick_parent_names, aes2_ick_ops); + +static struct clk uart4_ick_am35xx; + +static struct clk_hw_omap uart4_ick_am35xx_hw = { + .hw = { + .clk = &uart4_ick_am35xx, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = AM35XX_EN_UART4_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(uart4_ick_am35xx, aes2_ick_parent_names, aes2_ick_ops); + +static const struct clksel_rate div2_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, + { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, + { .div = 0 } +}; + +static const struct clksel usb_l4_clksel[] = { + { .parent = &l4_ick, .rates = div2_rates }, + { .parent = NULL }, +}; + +static const char *usb_l4_ick_parent_names[] = { + "l4_ick", +}; + +DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_clksel, + OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), + OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, + OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + OMAP3430ES1_EN_FSHOSTUSB_SHIFT, + &clkhwops_iclk_wait, usb_l4_ick_parent_names, + ssi_ssr_fck_3430es1_ops); + +static struct clk usbhost_120m_fck; + +static const char *usbhost_120m_fck_parent_names[] = { + "dpll5_m2_ck", +}; + +static struct clk_hw_omap usbhost_120m_fck_hw = { + .hw = { + .clk = &usbhost_120m_fck, + }, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, + .clkdm_name = "usbhost_clkdm", +}; + +DEFINE_STRUCT_CLK(usbhost_120m_fck, usbhost_120m_fck_parent_names, + aes2_ick_ops); + +static struct clk usbhost_48m_fck; + +static struct clk_hw_omap usbhost_48m_fck_hw = { + .hw = { + .clk = &usbhost_48m_fck, + }, + .ops = &clkhwops_omap3430es2_dss_usbhost_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), + .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, + .clkdm_name = "usbhost_clkdm", +}; + +DEFINE_STRUCT_CLK(usbhost_48m_fck, core_48m_fck_parent_names, aes2_ick_ops); + +static struct clk usbhost_ick; + +static struct clk_hw_omap usbhost_ick_hw = { + .hw = { + .clk = &usbhost_ick, + }, + .ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), + .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, + .clkdm_name = "usbhost_clkdm", +}; + +DEFINE_STRUCT_CLK(usbhost_ick, security_l4_ick2_parent_names, aes2_ick_ops); + +static struct clk usbtll_fck; + +static struct clk_hw_omap usbtll_fck_hw = { + .hw = { + .clk = &usbtll_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), + .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(usbtll_fck, usbhost_120m_fck_parent_names, aes2_ick_ops); + +static struct clk usbtll_ick; + +static struct clk_hw_omap usbtll_ick_hw = { + .hw = { + .clk = &usbtll_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), + .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, + .clkdm_name = "core_l4_clkdm", +}; + +DEFINE_STRUCT_CLK(usbtll_ick, aes2_ick_parent_names, aes2_ick_ops); + +static const struct clksel_rate usim_96m_rates[] = { + { .div = 2, .val = 3, .flags = RATE_IN_3XXX }, + { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, + { .div = 8, .val = 5, .flags = RATE_IN_3XXX }, + { .div = 10, .val = 6, .flags = RATE_IN_3XXX }, + { .div = 0 } +}; + +static const struct clksel_rate usim_120m_rates[] = { + { .div = 4, .val = 7, .flags = RATE_IN_3XXX }, + { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, + { .div = 16, .val = 9, .flags = RATE_IN_3XXX }, + { .div = 20, .val = 10, .flags = RATE_IN_3XXX }, + { .div = 0 } +}; + +static const struct clksel usim_clksel[] = { + { .parent = &omap_96m_fck, .rates = usim_96m_rates }, + { .parent = &dpll5_m2_ck, .rates = usim_120m_rates }, + { .parent = &sys_ck, .rates = div2_rates }, + { .parent = NULL }, +}; + +static const char *usim_fck_parent_names[] = { + "omap_96m_fck", "dpll5_m2_ck", "sys_ck", +}; + +static struct clk usim_fck; + +static const struct clk_ops usim_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, +}; + +DEFINE_CLK_OMAP_MUX_GATE(usim_fck, NULL, usim_clksel, + OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), + OMAP3430ES2_CLKSEL_USIMOCP_MASK, + OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + OMAP3430ES2_EN_USIMOCP_SHIFT, &clkhwops_wait, + usim_fck_parent_names, usim_fck_ops); + +static struct clk usim_ick; + +static struct clk_hw_omap usim_ick_hw = { + .hw = { + .clk = &usim_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(usim_ick, gpio1_ick_parent_names, aes2_ick_ops); + +static struct clk vpfe_fck; + +static const char *vpfe_fck_parent_names[] = { + "pclk_ck", +}; + +static struct clk_hw_omap vpfe_fck_hw = { + .hw = { + .clk = &vpfe_fck, + }, + .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), + .enable_bit = AM35XX_VPFE_FCLK_SHIFT, +}; + +DEFINE_STRUCT_CLK(vpfe_fck, vpfe_fck_parent_names, aes1_ick_ops); + +static struct clk vpfe_ick; + +static struct clk_hw_omap vpfe_ick_hw = { + .hw = { + .clk = &vpfe_ick, + }, + .ops = &clkhwops_am35xx_ipss_module_wait, + .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), + .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT, + .clkdm_name = "core_l3_clkdm", +}; + +DEFINE_STRUCT_CLK(vpfe_ick, emac_ick_parent_names, aes2_ick_ops); + +static struct clk wdt1_fck; + +DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck, "wkup_clkdm"); +DEFINE_STRUCT_CLK(wdt1_fck, gpt12_fck_parent_names, core_l4_ick_ops); + +static struct clk wdt1_ick; + +static struct clk_hw_omap wdt1_ick_hw = { + .hw = { + .clk = &wdt1_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_WDT1_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt1_ick, gpio1_ick_parent_names, aes2_ick_ops); + +static struct clk wdt2_fck; + +static struct clk_hw_omap wdt2_fck_hw = { + .hw = { + .clk = &wdt2_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_WDT2_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt2_fck, gpio1_dbck_parent_names, aes2_ick_ops); + +static struct clk wdt2_ick; + +static struct clk_hw_omap wdt2_ick_hw = { + .hw = { + .clk = &wdt2_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_WDT2_SHIFT, + .clkdm_name = "wkup_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt2_ick, gpio1_ick_parent_names, aes2_ick_ops); + +static struct clk wdt3_fck; + +static struct clk_hw_omap wdt3_fck_hw = { + .hw = { + .clk = &wdt3_fck, + }, + .ops = &clkhwops_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3430_EN_WDT3_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt3_fck, gpio2_dbck_parent_names, aes2_ick_ops); + +static struct clk wdt3_ick; + +static struct clk_hw_omap wdt3_ick_hw = { + .hw = { + .clk = &wdt3_ick, + }, + .ops = &clkhwops_iclk_wait, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3430_EN_WDT3_SHIFT, + .clkdm_name = "per_clkdm", +}; + +DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops); + +/* + * clkdev + */ +static struct omap_clk omap3xxx_clks[] = { + CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX), + CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), + CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), + CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), + CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_3XXX), + CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_3XXX), + CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), + CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), + CLK("twl", "fck", &osc_sys_ck, CK_3XXX), + CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), + CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), + CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), + CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), + CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), + CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX), + CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX), + CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX), + CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX), + CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX), + CLK(NULL, "core_ck", &core_ck, CK_3XXX), + CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX), + CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX), + CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX), + CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX), + CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX), + CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), + CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX), + CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX), + CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX), + CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX), + CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX), + CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX), + CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX), + CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX), + CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX), + CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX), + CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX), + CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX), + CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX), + CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX), + CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX), + CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX), + CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX), + CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX), + CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX), + CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), + CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX), + CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX), + CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX), + CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX), + CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), + CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), + CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), + CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX), + CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX), + CLK(NULL, "l3_ick", &l3_ick, CK_3XXX), + CLK(NULL, "l4_ick", &l4_ick, CK_3XXX), + CLK(NULL, "rm_ick", &rm_ick, CK_3XXX), + CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), + CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), + CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), + CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), + CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), + CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), + CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX), + CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX), + CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX), + CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX), + CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX), + CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("usbhs_tll", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), + CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX), + CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX), + CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX), + CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX), + CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX), + CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX), + CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX), + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX), + CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX), + CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX), + CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX), + CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX), + CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX), + CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX), + CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX), + CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), + CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), + CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), + CLK(NULL, "hdq_fck", &hdq_fck, CK_3XXX), + CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), + CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX), + CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), + CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX), + CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX), + CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), + CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), + CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1, CK_3430ES1), + CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), + CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX), + CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX), + CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX), + CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX), + CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), + CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("usbhs_tll", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "mmchs3_ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), + CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), + CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX), + CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX), + CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX), + CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX), + CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_3XXX), + CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_3XXX), + CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX), + CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), + CLK(NULL, "hdq_ick", &hdq_ick, CK_3XXX), + CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), + CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX), + CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX), + CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX), + CLK(NULL, "mcspi4_ick", &mcspi4_ick, CK_3XXX), + CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_3XXX), + CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_3XXX), + CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_3XXX), + CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX), + CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX), + CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX), + CLK(NULL, "i2c3_ick", &i2c3_ick, CK_3XXX), + CLK(NULL, "i2c2_ick", &i2c2_ick, CK_3XXX), + CLK(NULL, "i2c1_ick", &i2c1_ick, CK_3XXX), + CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX), + CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX), + CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX), + CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX), + CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX), + CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX), + CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_3XXX), + CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_3XXX), + CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), + CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX), + CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX), + CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX), + CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), + CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX), + CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), + CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX), + CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX), + CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX), + CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX), + CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX), + CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), + CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX), + CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX), + CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX), + CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1), + CLK(NULL, "dss_ick", &dss_ick_3430es1, CK_3430ES1), + CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "dss_ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), + CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX), + CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX), + CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK("usbhs_omap", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), + CLK(NULL, "utmi_p1_gfclk", &dummy_ck, CK_3XXX), + CLK(NULL, "utmi_p2_gfclk", &dummy_ck, CK_3XXX), + CLK(NULL, "xclk60mhsp1_ck", &dummy_ck, CK_3XXX), + CLK(NULL, "xclk60mhsp2_ck", &dummy_ck, CK_3XXX), + CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX), + CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX), + CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), + CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), + CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), + CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), + CLK(NULL, "init_60m_fclk", &dummy_ck, CK_3XXX), + CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX), + CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), + CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), + CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX), + CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX), + CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX), + CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX), + CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX), + CLK(NULL, "wdt2_ick", &wdt2_ick, CK_3XXX), + CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX), + CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX), + CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), + CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), + CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), + CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), + CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), + CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), + CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX), + CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_AM35XX), + CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), + CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), + CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), + CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX), + CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX), + CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX), + CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX), + CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX), + CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX), + CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX), + CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX), + CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX), + CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX), + CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX), + CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX), + CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX), + CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX), + CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX), + CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX), + CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX), + CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX), + CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX), + CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX), + CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX), + CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX), + CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX), + CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX), + CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX), + CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX), + CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX), + CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX), + CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX), + CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX), + CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX), + CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX), + CLK(NULL, "mcbsp4_ick", &mcbsp2_ick, CK_3XXX), + CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_3XXX), + CLK(NULL, "mcbsp2_ick", &mcbsp4_ick, CK_3XXX), + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX), + CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX), + CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX), + CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX), + CLK(NULL, "emu_src_ck", &emu_src_ck, CK_3XXX), + CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX), + CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX), + CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX), + CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX), + CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX), + CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX), + CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX), + CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX), + CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX), + CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX), + CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX), + CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), + CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), + CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), + CLK(NULL, "emac_ick", &emac_ick, CK_AM35XX), + CLK(NULL, "emac_fck", &emac_fck, CK_AM35XX), + CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX), + CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX), + CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), + CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), + CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX), + CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx, CK_AM35XX), + CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), + CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), + CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX), + CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX), + CLK(NULL, "cpufreq_ck", &dpll1_ck, CK_3XXX), +}; + +static const char *enable_init_clks[] = { + "sdrc_ick", + "gpmc_fck", + "omapctrl_ick", +}; + +int __init omap3xxx_clk_init(void) +{ + struct omap_clk *c; + u32 cpu_clkflg = 0; + + /* + * 3505 must be tested before 3517, since 3517 returns true + * for both AM3517 chips and AM3517 family chips, which + * includes 3505. Unfortunately there's no obvious family + * test for 3517/3505 :-( + */ + if (soc_is_am35xx()) { + cpu_mask = RATE_IN_34XX; + cpu_clkflg = CK_AM35XX; + } else if (cpu_is_omap3630()) { + cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); + cpu_clkflg = CK_36XX; + } else if (cpu_is_ti816x()) { + cpu_mask = RATE_IN_TI816X; + cpu_clkflg = CK_TI816X; + } else if (soc_is_am33xx()) { + cpu_mask = RATE_IN_AM33XX; + } else if (cpu_is_ti814x()) { + cpu_mask = RATE_IN_TI814X; + } else if (cpu_is_omap34xx()) { + if (omap_rev() == OMAP3430_REV_ES1_0) { + cpu_mask = RATE_IN_3430ES1; + cpu_clkflg = CK_3430ES1; + } else { + /* + * Assume that anything that we haven't matched yet + * has 3430ES2-type clocks. + */ + cpu_mask = RATE_IN_3430ES2PLUS; + cpu_clkflg = CK_3430ES2PLUS; + } + } else { + WARN(1, "clock: could not identify OMAP3 variant\n"); + } + + if (omap3_has_192mhz_clk()) + omap_96m_alwon_fck = omap_96m_alwon_fck_3630; + + if (cpu_is_omap3630()) { + dpll3_m3x2_ck = dpll3_m3x2_ck_3630; + dpll4_m2x2_ck = dpll4_m2x2_ck_3630; + dpll4_m3x2_ck = dpll4_m3x2_ck_3630; + dpll4_m4x2_ck = dpll4_m4x2_ck_3630; + dpll4_m5x2_ck = dpll4_m5x2_ck_3630; + dpll4_m6x2_ck = dpll4_m6x2_ck_3630; + } + + /* + * XXX This type of dynamic rewriting of the clock tree is + * deprecated and should be revised soon. + */ + if (cpu_is_omap3630()) + dpll4_dd = dpll4_dd_3630; + else + dpll4_dd = dpll4_dd_34xx; + + for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); + c++) + if (c->cpu & cpu_clkflg) { + clkdev_add(&c->lk); + if (!__clk_init(NULL, c->lk.clk)) + omap2_init_clk_hw_omap_clocks(c->lk.clk); + } + + omap2_clk_disable_autoidle_all(); + + omap2_clk_enable_init_clocks(enable_init_clks, + ARRAY_SIZE(enable_init_clks)); + + pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", + (clk_get_rate(&osc_sys_ck) / 1000000), + (clk_get_rate(&osc_sys_ck) / 100000) % 10, + (clk_get_rate(&core_ck) / 1000000), + (clk_get_rate(&arm_fck) / 1000000)); + + /* + * Lock DPLL5 -- here only until other device init code can + * handle this + */ + if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0)) + omap3_clk_lock_dpll5(); + + /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ + sdrc_ick_p = clk_get(NULL, "sdrc_ick"); + arm_fck_p = clk_get(NULL, "arm_fck"); + + return 0; +} diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c new file mode 100644 index 000000000000..aa56c3e5bb34 --- /dev/null +++ b/arch/arm/mach-omap2/cclock44xx_data.c @@ -0,0 +1,1987 @@ +/* + * OMAP4 Clock data + * + * Copyright (C) 2009-2012 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation + * + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * Mike Turquette (mturquette@ti.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * XXX Some of the ES1 clocks have been removed/changed; once support + * is added for discriminating clocks by ES level, these should be added back + * in. + */ + +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/clk-private.h> +#include <linux/clkdev.h> +#include <linux/io.h> + +#include "soc.h" +#include "iomap.h" +#include "clock.h" +#include "clock44xx.h" +#include "cm1_44xx.h" +#include "cm2_44xx.h" +#include "cm-regbits-44xx.h" +#include "prm44xx.h" +#include "prm-regbits-44xx.h" +#include "control.h" +#include "scrm44xx.h" + +/* OMAP4 modulemode control */ +#define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0 +#define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1 + +/* Root clocks */ + +DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0); + +DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0); + +DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0, + OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT, + 0x0, NULL); + +DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0); + +DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0); + +DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0); + +DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0, + OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT, + 0x0, NULL); + +DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0); + +DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0); + +static const char *sys_clkin_ck_parents[] = { + "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck", + "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck", + "virt_38400000_ck", +}; + +DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0, + OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT, + OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL); + +DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0); + +DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0); + +DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0); + +DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0); + +DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0); + +/* Module clocks and DPLL outputs */ + +static const char *abe_dpll_bypass_clk_mux_ck_parents[] = { + "sys_clkin_ck", "sys_32k_ck", +}; + +DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, + NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT, + OMAP4430_CLKSEL_WIDTH, 0x0, NULL); + +DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL, + 0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, + OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); + +/* DPLL_ABE */ +static struct dpll_data dpll_abe_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, + .clk_bypass = &abe_dpll_bypass_clk_mux_ck, + .clk_ref = &abe_dpll_refclk_mux_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + + +static const char *dpll_abe_ck_parents[] = { + "abe_dpll_refclk_mux_ck", +}; + +static struct clk dpll_abe_ck; + +static const struct clk_ops dpll_abe_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .recalc_rate = &omap4_dpll_regm4xen_recalc, + .round_rate = &omap4_dpll_regm4xen_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_abe_ck_hw = { + .hw = { + .clk = &dpll_abe_ck, + }, + .dpll_data = &dpll_abe_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops); + +static const char *dpll_abe_x2_ck_parents[] = { + "dpll_abe_ck", +}; + +static struct clk dpll_abe_x2_ck; + +static const struct clk_ops dpll_abe_x2_ck_ops = { + .recalc_rate = &omap3_clkoutx2_recalc, +}; + +static struct clk_hw_omap dpll_abe_x2_ck_hw = { + .hw = { + .clk = &dpll_abe_x2_ck, + }, + .flags = CLOCK_CLKOUTX2, + .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, + .ops = &clkhwops_omap4_dpllmx, +}; + +DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops); + +static const struct clk_ops omap_hsdivider_ops = { + .set_rate = &omap2_clksel_set_rate, + .recalc_rate = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, +}; + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck, + 0x0, OMAP4430_CM_DIV_M2_DPLL_ABE, + OMAP4430_DPLL_CLKOUT_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, + 0x0, 1, 8); + +DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0, + OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT, + OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0, + OMAP4430_CM1_ABE_AESS_CLKCTRL, + OMAP4430_CLKSEL_AESS_FCLK_SHIFT, + OMAP4430_CLKSEL_AESS_FCLK_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck, + 0x0, OMAP4430_CM_DIV_M3_DPLL_ABE, + OMAP4430_DPLL_CLKOUTHIF_DIV_MASK); + +static const char *core_hsd_byp_clk_mux_ck_parents[] = { + "sys_clkin_ck", "dpll_abe_m3x2_ck", +}; + +DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL, + 0x0, OMAP4430_CM_CLKSEL_DPLL_CORE, + OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH, + 0x0, NULL); + +/* DPLL_CORE */ +static struct dpll_data dpll_core_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, + .clk_bypass = &core_hsd_byp_clk_mux_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + + +static const char *dpll_core_ck_parents[] = { + "sys_clkin_ck", +}; + +static struct clk dpll_core_ck; + +static const struct clk_ops dpll_core_ck_ops = { + .recalc_rate = &omap3_dpll_recalc, + .get_parent = &omap2_init_dpll_parent, +}; + +static struct clk_hw_omap dpll_core_ck_hw = { + .hw = { + .clk = &dpll_core_ck, + }, + .dpll_data = &dpll_core_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops); + +static const char *dpll_core_x2_ck_parents[] = { + "dpll_core_ck", +}; + +static struct clk dpll_core_x2_ck; + +static struct clk_hw_omap dpll_core_x2_ck_hw = { + .hw = { + .clk = &dpll_core_x2_ck, + }, +}; + +DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck", + &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE, + OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_CORE, + OMAP4430_DPLL_CLKOUT_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1, + 2); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck", + &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE, + OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); + +DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0, + OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT, + OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL); + +DEFINE_CLK_OMAP_HSDIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", + &dpll_core_m5x2_ck, 0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, + OMAP4430_CLKSEL_0_1_MASK); + +DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, + 0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT, + OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck", + &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE, + OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, + 0x0, 1, 2); + +DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, + OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); + +static const struct clk_ops dmic_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, + .set_parent = &omap2_clksel_set_parent, + .init = &omap2_init_clk_clkdm, +}; + +static const char *dpll_core_m3x2_ck_parents[] = { + "dpll_core_x2_ck", +}; + +static const struct clksel dpll_core_m3x2_div[] = { + { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +/* XXX Missing round_rate, set_rate in ops */ +DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div, + OMAP4430_CM_DIV_M3_DPLL_CORE, + OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, + OMAP4430_CM_DIV_M3_DPLL_CORE, + OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, + dpll_core_m3x2_ck_parents, dmic_fck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck", + &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE, + OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK); + +static const char *iva_hsd_byp_clk_mux_ck_parents[] = { + "sys_clkin_ck", "div_iva_hs_clk", +}; + +DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL, + 0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT, + OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL); + +/* DPLL_IVA */ +static struct dpll_data dpll_iva_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, + .clk_bypass = &iva_hsd_byp_clk_mux_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + +static struct clk dpll_iva_ck; + +static struct clk_hw_omap dpll_iva_ck_hw = { + .hw = { + .clk = &dpll_iva_ck, + }, + .dpll_data = &dpll_iva_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_core_ck_parents, dpll_abe_ck_ops); + +static const char *dpll_iva_x2_ck_parents[] = { + "dpll_iva_ck", +}; + +static struct clk dpll_iva_x2_ck; + +static struct clk_hw_omap dpll_iva_x2_ck_hw = { + .hw = { + .clk = &dpll_iva_x2_ck, + }, +}; + +DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck, + 0x0, OMAP4430_CM_DIV_M4_DPLL_IVA, + OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck, + 0x0, OMAP4430_CM_DIV_M5_DPLL_IVA, + OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); + +/* DPLL_MPU */ +static struct dpll_data dpll_mpu_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, + .clk_bypass = &div_mpu_hs_clk, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + +static struct clk dpll_mpu_ck; + +static struct clk_hw_omap dpll_mpu_ck_hw = { + .hw = { + .clk = &dpll_mpu_ck, + }, + .dpll_data = &dpll_mpu_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_abe_ck_ops); + +DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_MPU, + OMAP4430_DPLL_CLKOUT_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck", + &dpll_abe_m3x2_ck, 0x0, 1, 2); + +static const char *per_hsd_byp_clk_mux_ck_parents[] = { + "sys_clkin_ck", "per_hs_clk_div_ck", +}; + +DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL, + 0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT, + OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL); + +/* DPLL_PER */ +static struct dpll_data dpll_per_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, + .clk_bypass = &per_hsd_byp_clk_mux_ck, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER, + .mult_mask = OMAP4430_DPLL_MULT_MASK, + .div1_mask = OMAP4430_DPLL_DIV_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, +}; + + +static struct clk dpll_per_ck; + +static struct clk_hw_omap dpll_per_ck_hw = { + .hw = { + .clk = &dpll_per_ck, + }, + .dpll_data = &dpll_per_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_abe_ck_ops); + +DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, + OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); + +static const char *dpll_per_x2_ck_parents[] = { + "dpll_per_ck", +}; + +static struct clk dpll_per_x2_ck; + +static struct clk_hw_omap dpll_per_x2_ck_hw = { + .hw = { + .clk = &dpll_per_x2_ck, + }, + .flags = CLOCK_CLKOUTX2, + .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, + .ops = &clkhwops_omap4_dpllmx, +}; + +DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, + 0x0, OMAP4430_CM_DIV_M2_DPLL_PER, + OMAP4430_DPLL_CLKOUT_DIV_MASK); + +static const char *dpll_per_m3x2_ck_parents[] = { + "dpll_per_x2_ck", +}; + +static const struct clksel dpll_per_m3x2_div[] = { + { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates }, + { .parent = NULL }, +}; + +/* XXX Missing round_rate, set_rate in ops */ +DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div, + OMAP4430_CM_DIV_M3_DPLL_PER, + OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, + OMAP4430_CM_DIV_M3_DPLL_PER, + OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, + dpll_per_m3x2_ck_parents, dmic_fck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, + 0x0, OMAP4430_CM_DIV_M4_DPLL_PER, + OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, + 0x0, OMAP4430_CM_DIV_M5_DPLL_PER, + OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, + 0x0, OMAP4430_CM_DIV_M6_DPLL_PER, + OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, + 0x0, OMAP4430_CM_DIV_M7_DPLL_PER, + OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK); + +DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck", + &dpll_abe_m3x2_ck, 0x0, 1, 3); + +/* DPLL_USB */ +static struct dpll_data dpll_usb_dd = { + .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, + .clk_bypass = &usb_hs_clk_div_ck, + .flags = DPLL_J_TYPE, + .clk_ref = &sys_clkin_ck, + .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, + .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB, + .mult_mask = OMAP4430_DPLL_MULT_USB_MASK, + .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK, + .enable_mask = OMAP4430_DPLL_EN_MASK, + .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, + .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, + .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK, + .max_multiplier = 4095, + .max_divider = 256, + .min_divider = 1, +}; + +static struct clk dpll_usb_ck; + +static struct clk_hw_omap dpll_usb_ck_hw = { + .hw = { + .clk = &dpll_usb_ck, + }, + .dpll_data = &dpll_usb_dd, + .ops = &clkhwops_omap3_dpll, +}; + +DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_core_ck_parents, dpll_abe_ck_ops); + +static const char *dpll_usb_clkdcoldo_ck_parents[] = { + "dpll_usb_ck", +}; + +static struct clk dpll_usb_clkdcoldo_ck; + +static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = { +}; + +static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = { + .hw = { + .clk = &dpll_usb_clkdcoldo_ck, + }, + .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB, + .ops = &clkhwops_omap4_dpllmx, +}; + +DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents, + dpll_usb_clkdcoldo_ck_ops); + +DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0, + OMAP4430_CM_DIV_M2_DPLL_USB, + OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK); + +static const char *ducati_clk_mux_ck_parents[] = { + "div_core_ck", "dpll_per_m6x2_ck", +}; + +DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT, + OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); + +DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, 1, 16); + +DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, + 1, 4); + +DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, 1, 8); + +static const struct clk_div_table func_48m_fclk_rates[] = { + { .div = 4, .val = 0 }, + { .div = 8, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, + OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates, + NULL); + +DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, 1, 4); + +static const struct clk_div_table func_64m_fclk_rates[] = { + { .div = 2, .val = 0 }, + { .div = 4, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, + 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, + OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates, + NULL); + +static const struct clk_div_table func_96m_fclk_rates[] = { + { .div = 2, .val = 0 }, + { .div = 4, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, + 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, + OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates, + NULL); + +static const struct clk_div_table init_60m_fclk_rates[] = { + { .div = 1, .val = 0 }, + { .div = 8, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck, + 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ, + OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH, + 0x0, init_60m_fclk_rates, NULL); + +DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0, + OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT, + OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL); + +DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT, + OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL); + +DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, + 0x0, 1, 16); + +static const char *l4_wkup_clk_mux_ck_parents[] = { + "sys_clkin_ck", "lp_clk_div_ck", +}; + +DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, + OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); + +static const struct clk_div_table ocp_abe_iclk_rates[] = { + { .div = 2, .val = 0 }, + { .div = 1, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0, + OMAP4430_CM1_ABE_AESS_CLKCTRL, + OMAP4430_CLKSEL_AESS_FCLK_SHIFT, + OMAP4430_CLKSEL_AESS_FCLK_WIDTH, + 0x0, ocp_abe_iclk_rates, NULL); + +DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, + 0x0, 1, 4); + +DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0, + OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, + OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL); + +DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0, + OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, + OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); + +static struct clk dbgclk_mux_ck; +DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL); +DEFINE_STRUCT_CLK(dbgclk_mux_ck, dpll_core_ck_parents, + dpll_usb_clkdcoldo_ck_ops); + +/* Leaf clocks controlled by modules */ + +DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L4SEC_AES1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L4SEC_AES2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(aess_fck, "aess_fclk", &aess_fclk, 0x0, + OMAP4430_CM1_ABE_AESS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, + OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL); + +static const struct clk_div_table div_ts_ck_rates[] = { + { .div = 8, .val = 0 }, + { .div = 16, .val = 1 }, + { .div = 32, .val = 2 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, + 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, + OMAP4430_CLKSEL_24_25_SHIFT, + OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates, + NULL); + +DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0, + OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, + OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(des3des_fck, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +static const char *dmic_sync_mux_ck_parents[] = { + "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk", +}; + +DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, + 0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_dmic_abe_gfclk_sel[] = { + { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *dmic_fck_parents[] = { + "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_dmic_abe_gfclk into dmic */ +static struct clk dmic_fck; + +DEFINE_CLK_OMAP_MUX_GATE(dmic_fck, "abe_clkdm", func_dmic_abe_gfclk_sel, + OMAP4430_CM1_ABE_DMIC_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_DMIC_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + dmic_fck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(dsp_fck, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, 0x0, + OMAP4430_CM_TESLA_TESLA_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, + OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, + OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(efuse_ctrl_cust_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0, + OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(emif1_fck, "ddrphy_ck", &ddrphy_ck, 0x0, + OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(emif2_fck, "ddrphy_ck", &ddrphy_ck, 0x0, + OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, + OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT, + OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); + +DEFINE_CLK_GATE(fpka_fck, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_GPIO1_CLKCTRL, + OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio1_ick, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 0x0, + OMAP4430_CM_WKUP_GPIO1_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(gpio2_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO2_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO3_CLKCTRL, + OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio3_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO3_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(gpio4_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO4_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(gpio5_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO5_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(gpio6_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_GPIO6_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(gpmc_ick, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L3_2_GPMC_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, + 0x0, NULL); + +static const struct clksel sgx_clk_mux_sel[] = { + { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, + { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static const char *gpu_fck_parents[] = { + "dpll_core_m7x2_ck", "dpll_per_m7x2_ck", +}; + +/* Merged sgx_clk_mux into gpu */ +DEFINE_CLK_OMAP_MUX_GATE(gpu_fck, "l3_gfx_clkdm", sgx_clk_mux_sel, + OMAP4430_CM_GFX_GFX_CLKCTRL, + OMAP4430_CLKSEL_SGX_FCLK_MASK, + OMAP4430_CM_GFX_GFX_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + gpu_fck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(hdq1w_fck, "func_12m_fclk", &func_12m_fclk, 0x0, + OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0, + OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT, + OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO, + NULL); + +DEFINE_CLK_GATE(i2c1_fck, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_L4PER_I2C1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(i2c2_fck, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_L4PER_I2C2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(i2c3_fck, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_L4PER_I2C3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(i2c4_fck, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_L4PER_I2C4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(ipu_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0, + OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0, + OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(iss_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0, + OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(iva_fck, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0, + OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(kbd_fck, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static struct clk l3_instr_ick; + +static const char *l3_instr_ick_parent_names[] = { + "l3_div_ck", +}; + +static const struct clk_ops l3_instr_ick_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .init = &omap2_init_clk_clkdm, +}; + +static struct clk_hw_omap l3_instr_ick_hw = { + .hw = { + .clk = &l3_instr_ick, + }, + .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, + .clkdm_name = "l3_instr_clkdm", +}; + +DEFINE_STRUCT_CLK(l3_instr_ick, l3_instr_ick_parent_names, l3_instr_ick_ops); + +static struct clk l3_main_3_ick; +static struct clk_hw_omap l3_main_3_ick_hw = { + .hw = { + .clk = &l3_main_3_ick, + }, + .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, + .clkdm_name = "l3_instr_clkdm", +}; + +DEFINE_STRUCT_CLK(l3_main_3_ick, l3_instr_ick_parent_names, l3_instr_ick_ops); + +DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM1_ABE_MCASP_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_mcasp_abe_gfclk_sel[] = { + { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *mcasp_fck_parents[] = { + "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_mcasp_abe_gfclk into mcasp */ +DEFINE_CLK_OMAP_MUX_GATE(mcasp_fck, "abe_clkdm", func_mcasp_abe_gfclk_sel, + OMAP4430_CM1_ABE_MCASP_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_MCASP_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcasp_fck_parents, dmic_fck_ops); + +DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_mcbsp1_gfclk_sel[] = { + { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp1_fck_parents[] = { + "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_mcbsp1_gfclk into mcbsp1 */ +DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "abe_clkdm", func_mcbsp1_gfclk_sel, + OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcbsp1_fck_parents, dmic_fck_ops); + +DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_mcbsp2_gfclk_sel[] = { + { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp2_fck_parents[] = { + "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_mcbsp2_gfclk into mcbsp2 */ +DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "abe_clkdm", func_mcbsp2_gfclk_sel, + OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcbsp2_fck_parents, dmic_fck_ops); + +DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel func_mcbsp3_gfclk_sel[] = { + { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = &slimbus_clk, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp3_fck_parents[] = { + "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk", +}; + +/* Merged func_mcbsp3_gfclk into mcbsp3 */ +DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "abe_clkdm", func_mcbsp3_gfclk_sel, + OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_MASK, + OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcbsp3_fck_parents, dmic_fck_ops); + +static const char *mcbsp4_sync_mux_ck_parents[] = { + "func_96m_fclk", "per_abe_nc_fclk", +}; + +DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, + OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, + OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); + +static const struct clksel per_mcbsp4_gfclk_sel[] = { + { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates }, + { .parent = &pad_clks_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static const char *mcbsp4_fck_parents[] = { + "mcbsp4_sync_mux_ck", "pad_clks_ck", +}; + +/* Merged per_mcbsp4_gfclk into mcbsp4 */ +DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "l4_per_clkdm", per_mcbsp4_gfclk_sel, + OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, + OMAP4430_CLKSEL_SOURCE_24_24_MASK, + OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mcbsp4_fck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(mcpdm_fck, "pad_clks_ck", &pad_clks_ck, 0x0, + OMAP4430_CM1_ABE_PDM_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(mcspi1_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mcspi2_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mcspi3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mcspi4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static const struct clksel hsmmc1_fclk_sel[] = { + { .parent = &func_64m_fclk, .rates = div_1_0_rates }, + { .parent = &func_96m_fclk, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static const char *mmc1_fck_parents[] = { + "func_64m_fclk", "func_96m_fclk", +}; + +/* Merged hsmmc1_fclk into mmc1 */ +DEFINE_CLK_OMAP_MUX_GATE(mmc1_fck, "l3_init_clkdm", hsmmc1_fclk_sel, + OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L3INIT_MMC1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mmc1_fck_parents, dmic_fck_ops); + +/* Merged hsmmc2_fclk into mmc2 */ +DEFINE_CLK_OMAP_MUX_GATE(mmc2_fck, "l3_init_clkdm", hsmmc1_fclk_sel, + OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L3INIT_MMC2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + mmc1_fck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(mmc3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mmc4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(mmc5_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(ocp2scp_usb_phy_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +static struct clk ocp_wp_noc_ick; + +static struct clk_hw_omap ocp_wp_noc_ick_hw = { + .hw = { + .clk = &ocp_wp_noc_ick, + }, + .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT, + .clkdm_name = "l3_instr_clkdm", +}; + +DEFINE_STRUCT_CLK(ocp_wp_noc_ick, l3_instr_ick_parent_names, l3_instr_ick_ops); + +DEFINE_CLK_GATE(rng_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4SEC_RNG_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(sl2if_ick, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0, + OMAP4430_CM_IVAHD_SL2_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus1_fck, "ocp_abe_iclk", &ocp_abe_iclk, 0x0, + OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0, + OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0, + OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck", + &pad_slimbus_core_clks_ck, 0x0, + OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(slimbus2_fck, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, + 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, + 0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, + 0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static const struct clksel dmt1_clk_mux_sel[] = { + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +/* Merged dmt1_clk_mux into timer1 */ +DEFINE_CLK_OMAP_MUX_GATE(timer1_fck, "l4_wkup_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM_WKUP_TIMER1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm10_mux into timer10 */ +DEFINE_CLK_OMAP_MUX_GATE(timer10_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm11_mux into timer11 */ +DEFINE_CLK_OMAP_MUX_GATE(timer11_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm2_mux into timer2 */ +DEFINE_CLK_OMAP_MUX_GATE(timer2_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm3_mux into timer3 */ +DEFINE_CLK_OMAP_MUX_GATE(timer3_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +/* Merged cm2_dm4_mux into timer4 */ +DEFINE_CLK_OMAP_MUX_GATE(timer4_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +static const struct clksel timer5_sync_mux_sel[] = { + { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static const char *timer5_fck_parents[] = { + "syc_clk_div_ck", "sys_32k_ck", +}; + +/* Merged timer5_sync_mux into timer5 */ +DEFINE_CLK_OMAP_MUX_GATE(timer5_fck, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM1_ABE_TIMER5_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + timer5_fck_parents, dmic_fck_ops); + +/* Merged timer6_sync_mux into timer6 */ +DEFINE_CLK_OMAP_MUX_GATE(timer6_fck, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM1_ABE_TIMER6_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + timer5_fck_parents, dmic_fck_ops); + +/* Merged timer7_sync_mux into timer7 */ +DEFINE_CLK_OMAP_MUX_GATE(timer7_fck, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM1_ABE_TIMER7_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + timer5_fck_parents, dmic_fck_ops); + +/* Merged timer8_sync_mux into timer8 */ +DEFINE_CLK_OMAP_MUX_GATE(timer8_fck, "abe_clkdm", timer5_sync_mux_sel, + OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK, + OMAP4430_CM1_ABE_TIMER8_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + timer5_fck_parents, dmic_fck_ops); + +/* Merged cm2_dm9_mux into timer9 */ +DEFINE_CLK_OMAP_MUX_GATE(timer9_fck, "l4_per_clkdm", dmt1_clk_mux_sel, + OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + OMAP4430_CLKSEL_MASK, + OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, + abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); + +DEFINE_CLK_GATE(uart1_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_UART1_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(uart2_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_UART2_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(uart3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_UART3_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(uart4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L4PER_UART4_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static struct clk usb_host_fs_fck; + +static const char *usb_host_fs_fck_parent_names[] = { + "func_48mc_fclk", +}; + +static const struct clk_ops usb_host_fs_fck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, +}; + +static struct clk_hw_omap usb_host_fs_fck_hw = { + .hw = { + .clk = &usb_host_fs_fck, + }, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, + .clkdm_name = "l3_init_clkdm", +}; + +DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names, + usb_host_fs_fck_ops); + +static const char *utmi_p1_gfclk_parents[] = { + "init_60m_fclk", "xclk60mhsp1_ck", +}; + +DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH, + 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL); + +static const char *utmi_p2_gfclk_parents[] = { + "init_60m_fclk", "xclk60mhsp2_ck", +}; + +DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH, + 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck", + &dpll_usb_m2_ck, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk", + &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk", + &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck", + &dpll_usb_m2_ck, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); + +static const char *otg_60m_gfclk_parents[] = { + "utmi_phy_clkout_ck", "xclk60motg_ck", +}; + +DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0, + OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT, + OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL); + +DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0, + OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, + OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0, + OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_ALWON_USBPHY_CLKCTRL, + OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0, + OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL); + +DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0, + OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); + +static const struct clk_div_table usim_ck_rates[] = { + { .div = 14, .val = 0 }, + { .div = 18, .val = 1 }, + { .div = 0 }, +}; +DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, + OMAP4430_CM_WKUP_USIM_CLKCTRL, + OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH, + 0x0, usim_ck_rates, NULL); + +DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0, + OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(usim_fck, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(wd_timer2_fck, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM_WKUP_WDT2_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +DEFINE_CLK_GATE(wd_timer3_fck, "sys_32k_ck", &sys_32k_ck, 0x0, + OMAP4430_CM1_ABE_WDT3_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, + 0x0, NULL); + +/* Remaining optional clocks */ +static const char *pmd_stm_clock_mux_ck_parents[] = { + "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck", +}; + +DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT, + OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL); + +DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0, + OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, + OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT, + OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL); + +DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck", + &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, + OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT, + OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, + NULL); + +static const char *trace_clk_div_ck_parents[] = { + "pmd_trace_clk_mux_ck", +}; + +static const struct clksel trace_clk_div_div[] = { + { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, + { .parent = NULL }, +}; + +static struct clk trace_clk_div_ck; + +static const struct clk_ops trace_clk_div_ck_ops = { + .recalc_rate = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, + .init = &omap2_init_clk_clkdm, + .enable = &omap2_clkops_enable_clkdm, + .disable = &omap2_clkops_disable_clkdm, +}; + +static struct clk_hw_omap trace_clk_div_ck_hw = { + .hw = { + .clk = &trace_clk_div_ck, + }, + .clkdm_name = "emu_sys_clkdm", + .clksel = trace_clk_div_div, + .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, +}; + +DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents, + trace_clk_div_ck_ops); + +/* SCRM aux clk nodes */ + +static const struct clksel auxclk_src_sel[] = { + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, + { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, + { .parent = NULL }, +}; + +static const char *auxclk_src_ck_parents[] = { + "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck", +}; + +static const struct clk_ops auxclk_src_ck_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .recalc_rate = &omap2_clksel_recalc, + .get_parent = &omap2_clksel_find_parent_index, +}; + +DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0, + OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0, + OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0, + OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0, + OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0, + OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel, + OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK, + OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL, + auxclk_src_ck_parents, auxclk_src_ck_ops); + +DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0, + OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, + 0x0, NULL); + +static const char *auxclkreq_ck_parents[] = { + "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck", + "auxclk5_ck", +}; + +DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0, + OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, + 0x0, NULL); + +/* + * clkdev + */ + +static struct omap_clk omap44xx_clks[] = { + CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), + CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck, CK_443X), + CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), + CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), + CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), + CLK(NULL, "slimbus_src_clk", &slimbus_src_clk, CK_443X), + CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), + CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), + CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), + CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), + CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), + CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), + CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), + CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), + CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), + CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), + CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), + CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), + CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), + CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), + CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), + CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), + CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), + CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), + CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), + CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), + CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), + CLK(NULL, "abe_clk", &abe_clk, CK_443X), + CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), + CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), + CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), + CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), + CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), + CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), + CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), + CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), + CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), + CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), + CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), + CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), + CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), + CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), + CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), + CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), + CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), + CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), + CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), + CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), + CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), + CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), + CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), + CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), + CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), + CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), + CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), + CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), + CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), + CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), + CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), + CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), + CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), + CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), + CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), + CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), + CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), + CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), + CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), + CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), + CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), + CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), + CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), + CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), + CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), + CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), + CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), + CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), + CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), + CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), + CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), + CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), + CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), + CLK("smp_twd", NULL, &mpu_periphclk, CK_443X), + CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), + CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), + CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), + CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), + CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), + CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), + CLK(NULL, "aess_fck", &aess_fck, CK_443X), + CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), + CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), + CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), + CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), + CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), + CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), + CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), + CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), + CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), + CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), + CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), + CLK(NULL, "dss_fck", &dss_fck, CK_443X), + CLK("omapdss_dss", "ick", &dss_fck, CK_443X), + CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), + CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), + CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), + CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), + CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), + CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), + CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), + CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), + CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), + CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), + CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), + CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), + CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), + CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), + CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), + CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), + CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), + CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), + CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), + CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X), + CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), + CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X), + CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X), + CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X), + CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X), + CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), + CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), + CLK(NULL, "iss_fck", &iss_fck, CK_443X), + CLK(NULL, "iva_fck", &iva_fck, CK_443X), + CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), + CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X), + CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X), + CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), + CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), + CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), + CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X), + CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), + CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X), + CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), + CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X), + CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), + CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X), + CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), + CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X), + CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X), + CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X), + CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X), + CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X), + CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X), + CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X), + CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X), + CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X), + CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), + CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), + CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), + CLK(NULL, "rng_ick", &rng_ick, CK_443X), + CLK("omap_rng", "ick", &rng_ick, CK_443X), + CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), + CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), + CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), + CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), + CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), + CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), + CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), + CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), + CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), + CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), + CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), + CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), + CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), + CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), + CLK(NULL, "timer1_fck", &timer1_fck, CK_443X), + CLK(NULL, "timer10_fck", &timer10_fck, CK_443X), + CLK(NULL, "timer11_fck", &timer11_fck, CK_443X), + CLK(NULL, "timer2_fck", &timer2_fck, CK_443X), + CLK(NULL, "timer3_fck", &timer3_fck, CK_443X), + CLK(NULL, "timer4_fck", &timer4_fck, CK_443X), + CLK(NULL, "timer5_fck", &timer5_fck, CK_443X), + CLK(NULL, "timer6_fck", &timer6_fck, CK_443X), + CLK(NULL, "timer7_fck", &timer7_fck, CK_443X), + CLK(NULL, "timer8_fck", &timer8_fck, CK_443X), + CLK(NULL, "timer9_fck", &timer9_fck, CK_443X), + CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), + CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), + CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), + CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), + CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), + CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), + CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), + CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), + CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), + CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), + CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X), + CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), + CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), + CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X), + CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), + CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), + CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), + CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X), + CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X), + CLK(NULL, "usim_ck", &usim_ck, CK_443X), + CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), + CLK(NULL, "usim_fck", &usim_fck, CK_443X), + CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X), + CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), + CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), + CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), + CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), + CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), + CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X), + CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), + CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), + CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X), + CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), + CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), + CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X), + CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), + CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), + CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X), + CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), + CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), + CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X), + CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), + CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), + CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X), + CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), + CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), + CLK("omap-gpmc", "fck", &dummy_ck, CK_443X), + CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), + CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), + CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), + CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), + CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X), + CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X), + CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), + CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), + CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), + CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), + CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), + CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), + CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), + CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), + CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X), + CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X), + CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X), + CLK("omap_wdt", "ick", &dummy_ck, CK_443X), + CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X), + /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */ + CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), + CLK("49038000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4903a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), + CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), +}; + +static const char *enable_init_clks[] = { + "emif1_fck", + "emif2_fck", + "gpmc_ick", + "l3_instr_ick", + "l3_main_3_ick", + "ocp_wp_noc_ick", +}; + +int __init omap4xxx_clk_init(void) +{ + u32 cpu_clkflg; + struct omap_clk *c; + + if (cpu_is_omap443x()) { + cpu_mask = RATE_IN_4430; + cpu_clkflg = CK_443X; + } else if (cpu_is_omap446x() || cpu_is_omap447x()) { + cpu_mask = RATE_IN_4460 | RATE_IN_4430; + cpu_clkflg = CK_446X | CK_443X; + + if (cpu_is_omap447x()) + pr_warn("WARNING: OMAP4470 clock data incomplete!\n"); + } else { + return 0; + } + + for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); + c++) { + if (c->cpu & cpu_clkflg) { + clkdev_add(&c->lk); + if (!__clk_init(NULL, c->lk.clk)) + omap2_init_clk_hw_omap_clocks(c->lk.clk); + } + } + + omap2_clk_disable_autoidle_all(); + + omap2_clk_enable_init_clocks(enable_init_clks, + ARRAY_SIZE(enable_init_clks)); + + return 0; +} diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index c2d15212d64d..25b1feed480d 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c @@ -21,12 +21,10 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/clock.h> -#include <plat/prcm.h> #include "clock.h" #include "clock2xxx.h" -#include "cm2xxx_3xxx.h" +#include "cm2xxx.h" #include "cm-regbits-24xx.h" /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ @@ -38,92 +36,90 @@ #define APLLS_CLKIN_13MHZ 2 #define APLLS_CLKIN_12MHZ 3 -void __iomem *cm_idlest_pll; - /* Private functions */ -/* Enable an APLL if off */ -static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) +/** + * omap2xxx_clk_apll_locked - is the APLL locked? + * @hw: struct clk_hw * of the APLL to check + * + * If the APLL IP block referred to by @hw indicates that it's locked, + * return true; otherwise, return false. + */ +static bool omap2xxx_clk_apll_locked(struct clk_hw *hw) { - u32 cval, apll_mask; + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + u32 r, apll_mask; apll_mask = EN_APLL_LOCKED << clk->enable_bit; - cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); - - if ((cval & apll_mask) == apll_mask) - return 0; /* apll already enabled */ - - cval &= ~apll_mask; - cval |= apll_mask; - omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); - - omap2_cm_wait_idlest(cm_idlest_pll, status_mask, - OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk)); + r = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); - /* - * REVISIT: Should we return an error code if omap2_wait_clock_ready() - * fails? - */ - return 0; + return ((r & apll_mask) == apll_mask) ? true : false; } -static int omap2_clk_apll96_enable(struct clk *clk) +int omap2_clk_apll96_enable(struct clk_hw *hw) { - return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL_MASK); + return omap2xxx_cm_apll96_enable(); } -static int omap2_clk_apll54_enable(struct clk *clk) +int omap2_clk_apll54_enable(struct clk_hw *hw) { - return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK); + return omap2xxx_cm_apll54_enable(); } -static void _apll96_allow_idle(struct clk *clk) +static void _apll96_allow_idle(struct clk_hw_omap *clk) { omap2xxx_cm_set_apll96_auto_low_power_stop(); } -static void _apll96_deny_idle(struct clk *clk) +static void _apll96_deny_idle(struct clk_hw_omap *clk) { omap2xxx_cm_set_apll96_disable_autoidle(); } -static void _apll54_allow_idle(struct clk *clk) +static void _apll54_allow_idle(struct clk_hw_omap *clk) { omap2xxx_cm_set_apll54_auto_low_power_stop(); } -static void _apll54_deny_idle(struct clk *clk) +static void _apll54_deny_idle(struct clk_hw_omap *clk) { omap2xxx_cm_set_apll54_disable_autoidle(); } -/* Stop APLL */ -static void omap2_clk_apll_disable(struct clk *clk) +void omap2_clk_apll96_disable(struct clk_hw *hw) { - u32 cval; + omap2xxx_cm_apll96_disable(); +} - cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); - cval &= ~(EN_APLL_LOCKED << clk->enable_bit); - omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); +void omap2_clk_apll54_disable(struct clk_hw *hw) +{ + omap2xxx_cm_apll54_disable(); } -/* Public data */ +unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + return (omap2xxx_clk_apll_locked(hw)) ? 54000000 : 0; +} -const struct clkops clkops_apll96 = { - .enable = omap2_clk_apll96_enable, - .disable = omap2_clk_apll_disable, - .allow_idle = _apll96_allow_idle, - .deny_idle = _apll96_deny_idle, -}; +unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + return (omap2xxx_clk_apll_locked(hw)) ? 96000000 : 0; +} -const struct clkops clkops_apll54 = { - .enable = omap2_clk_apll54_enable, - .disable = omap2_clk_apll_disable, +/* Public data */ +const struct clk_hw_omap_ops clkhwops_apll54 = { .allow_idle = _apll54_allow_idle, .deny_idle = _apll54_deny_idle, }; +const struct clk_hw_omap_ops clkhwops_apll96 = { + .allow_idle = _apll96_allow_idle, + .deny_idle = _apll96_deny_idle, +}; + /* Public functions */ u32 omap2xxx_get_apll_clkin(void) diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c index 1502a7bc20bb..82572e277b97 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpll.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpll.c @@ -14,10 +14,8 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/clock.h> - #include "clock.h" -#include "cm2xxx_3xxx.h" +#include "cm2xxx.h" #include "cm-regbits-24xx.h" /* Private functions */ @@ -31,7 +29,7 @@ * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1 * instead. Add some mechanism to optionally enter this mode. */ -static void _allow_idle(struct clk *clk) +static void _allow_idle(struct clk_hw_omap *clk) { if (!clk || !clk->dpll_data) return; @@ -45,7 +43,7 @@ static void _allow_idle(struct clk *clk) * * Disable DPLL automatic idle control. No return value. */ -static void _deny_idle(struct clk *clk) +static void _deny_idle(struct clk_hw_omap *clk) { if (!clk || !clk->dpll_data) return; @@ -55,9 +53,7 @@ static void _deny_idle(struct clk *clk) /* Public data */ - -const struct clkops clkops_omap2xxx_dpll_ops = { +const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = { .allow_idle = _allow_idle, .deny_idle = _deny_idle, }; - diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index 4ae439222085..a0ae3c09f97a 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -25,21 +25,26 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/clock.h> -#include <plat/sram.h> -#include <plat/sdrc.h> +#include "../plat-omap/sram.h" #include "clock.h" #include "clock2xxx.h" #include "opp2xxx.h" -#include "cm2xxx_3xxx.h" +#include "cm2xxx.h" #include "cm-regbits-24xx.h" +#include "sdrc.h" /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ +/* + * dpll_core_ck: pointer to the combined dpll_ck + core_ck on OMAP2xxx + * (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set + * during dpll_ck init and used later by omap2xxx_clk_get_core_rate(). + */ +static struct clk_hw_omap *dpll_core_ck; + /** * omap2xxx_clk_get_core_rate - return the CORE_CLK rate - * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck") * * Returns the CORE_CLK rate. CORE_CLK can have one of three rate * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz @@ -47,12 +52,14 @@ * struct clk *dpll_ck, which is a composite clock of dpll_ck and * core_ck. */ -unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) +unsigned long omap2xxx_clk_get_core_rate(void) { long long core_clk; u32 v; - core_clk = omap2_get_dpll_rate(clk); + WARN_ON(!dpll_core_ck); + + core_clk = omap2_get_dpll_rate(dpll_core_ck); v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); v &= OMAP24XX_CORE_CLK_SRC_MASK; @@ -98,19 +105,22 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) } -unsigned long omap2_dpllcore_recalc(struct clk *clk) +unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, + unsigned long parent_rate) { - return omap2xxx_clk_get_core_rate(clk); + return omap2xxx_clk_get_core_rate(); } -int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) +int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) { + struct clk_hw_omap *clk = to_clk_hw_omap(hw); u32 cur_rate, low, mult, div, valid_rate, done_rate; u32 bypass = 0; struct prcm_config tmpset; const struct dpll_data *dd; - cur_rate = omap2xxx_clk_get_core_rate(dclk); + cur_rate = omap2xxx_clk_get_core_rate(); mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); mult &= OMAP24XX_CORE_CLK_SRC_MASK; @@ -171,3 +181,19 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) return 0; } +/** + * omap2xxx_clkt_dpllcore_init - clk init function for dpll_ck + * @clk: struct clk *dpll_ck + * + * Store a local copy of @clk in dpll_core_ck so other code can query + * the core rate without having to clk_get(), which can sleep. Must + * only be called once. No return value. XXX If the clock + * registration process is ever changed such that dpll_ck is no longer + * statically defined, this code may need to change to increment some + * kind of use count on dpll_ck. + */ +void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw) +{ + WARN(dpll_core_ck, "dpll_core_ck already set - should never happen"); + dpll_core_ck = to_clk_hw_omap(hw); +} diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c index c3460928b5e0..19f54d433490 100644 --- a/arch/arm/mach-omap2/clkt2xxx_osc.c +++ b/arch/arm/mach-omap2/clkt2xxx_osc.c @@ -23,8 +23,6 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/clock.h> - #include "clock.h" #include "clock2xxx.h" #include "prm2xxx_3xxx.h" @@ -37,7 +35,7 @@ * clk_enable/clk_disable()-based usecounting for osc_ck should be * replaced with autoidle-based usecounting. */ -static int omap2_enable_osc_ck(struct clk *clk) +int omap2_enable_osc_ck(struct clk_hw *clk) { u32 pcc; @@ -55,7 +53,7 @@ static int omap2_enable_osc_ck(struct clk *clk) * clk_enable/clk_disable()-based usecounting for osc_ck should be * replaced with autoidle-based usecounting. */ -static void omap2_disable_osc_ck(struct clk *clk) +void omap2_disable_osc_ck(struct clk_hw *clk) { u32 pcc; @@ -64,13 +62,8 @@ static void omap2_disable_osc_ck(struct clk *clk) __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); } -const struct clkops clkops_oscck = { - .enable = omap2_enable_osc_ck, - .disable = omap2_disable_osc_ck, -}; - -unsigned long omap2_osc_clk_recalc(struct clk *clk) +unsigned long omap2_osc_clk_recalc(struct clk_hw *clk, + unsigned long parent_rate) { return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv(); } - diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c index 8693cfdac49a..f467d072cd02 100644 --- a/arch/arm/mach-omap2/clkt2xxx_sys.c +++ b/arch/arm/mach-omap2/clkt2xxx_sys.c @@ -22,8 +22,6 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/clock.h> - #include "clock.h" #include "clock2xxx.h" #include "prm2xxx_3xxx.h" @@ -42,9 +40,8 @@ u32 omap2xxx_get_sysclkdiv(void) return div; } -unsigned long omap2xxx_sys_clk_recalc(struct clk *clk) +unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk, + unsigned long parent_rate) { - return clk->parent->rate / omap2xxx_get_sysclkdiv(); + return parent_rate / omap2xxx_get_sysclkdiv(); } - - diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index 3524f0e7b6d5..7af224208a25 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -1,7 +1,7 @@ /* * OMAP2xxx DVFS virtual clock functions * - * Copyright (C) 2005-2008 Texas Instruments, Inc. + * Copyright (C) 2005-2008, 2012 Texas Instruments, Inc. * Copyright (C) 2004-2010 Nokia Corporation * * Contacts: @@ -33,27 +33,34 @@ #include <linux/cpufreq.h> #include <linux/slab.h> -#include <plat/clock.h> -#include <plat/sram.h> -#include <plat/sdrc.h> +#include "../plat-omap/sram.h" #include "soc.h" #include "clock.h" #include "clock2xxx.h" #include "opp2xxx.h" -#include "cm2xxx_3xxx.h" +#include "cm2xxx.h" #include "cm-regbits-24xx.h" +#include "sdrc.h" const struct prcm_config *curr_prcm_set; const struct prcm_config *rate_table; +/* + * sys_ck_rate: the rate of the external high-frequency clock + * oscillator on the board. Set by the SoC-specific clock init code. + * Once set during a boot, will not change. + */ +static unsigned long sys_ck_rate; + /** * omap2_table_mpu_recalc - just return the MPU speed * @clk: virt_prcm_set struct clk * * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. */ -unsigned long omap2_table_mpu_recalc(struct clk *clk) +unsigned long omap2_table_mpu_recalc(struct clk_hw *clk, + unsigned long parent_rate) { return curr_prcm_set->mpu_speed; } @@ -65,18 +72,18 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk) * Some might argue L3-DDR, others ARM, others IVA. This code is simple and * just uses the ARM rates. */ -long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) +long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) { const struct prcm_config *ptr; - long highest_rate, sys_clk_rate; + long highest_rate; highest_rate = -EINVAL; - sys_clk_rate = __clk_get_rate(sclk); for (ptr = rate_table; ptr->mpu_speed; ptr++) { if (!(ptr->flags & cpu_mask)) continue; - if (ptr->xtal_speed != sys_clk_rate) + if (ptr->xtal_speed != sys_ck_rate) continue; highest_rate = ptr->mpu_speed; @@ -89,21 +96,19 @@ long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) } /* Sets basic clocks based on the specified rate */ -int omap2_select_table_rate(struct clk *clk, unsigned long rate) +int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) { u32 cur_rate, done_rate, bypass = 0, tmp; const struct prcm_config *prcm; unsigned long found_speed = 0; unsigned long flags; - long sys_clk_rate; - - sys_clk_rate = __clk_get_rate(sclk); for (prcm = rate_table; prcm->mpu_speed; prcm++) { if (!(prcm->flags & cpu_mask)) continue; - if (prcm->xtal_speed != sys_clk_rate) + if (prcm->xtal_speed != sys_ck_rate) continue; if (prcm->mpu_speed <= rate) { @@ -119,7 +124,7 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate) } curr_prcm_set = prcm; - cur_rate = omap2xxx_clk_get_core_rate(dclk); + cur_rate = omap2xxx_clk_get_core_rate(); if (prcm->dpll_speed == cur_rate / 2) { omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); @@ -169,3 +174,50 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate) return 0; } + +/** + * omap2xxx_clkt_vps_check_bootloader_rate - determine which of the rate + * table sets matches the current CORE DPLL hardware rate + * + * Check the MPU rate set by bootloader. Sets the 'curr_prcm_set' + * global to point to the active rate set when found; otherwise, sets + * it to NULL. No return value; + */ +void omap2xxx_clkt_vps_check_bootloader_rates(void) +{ + const struct prcm_config *prcm = NULL; + unsigned long rate; + + rate = omap2xxx_clk_get_core_rate(); + for (prcm = rate_table; prcm->mpu_speed; prcm++) { + if (!(prcm->flags & cpu_mask)) + continue; + if (prcm->xtal_speed != sys_ck_rate) + continue; + if (prcm->dpll_speed <= rate) + break; + } + curr_prcm_set = prcm; +} + +/** + * omap2xxx_clkt_vps_late_init - store a copy of the sys_ck rate + * + * Store a copy of the sys_ck rate for later use by the OMAP2xxx DVFS + * code. (The sys_ck rate does not -- or rather, must not -- change + * during kernel runtime.) Must be called after we have a valid + * sys_ck rate, but before the virt_prcm_set clock rate is + * recalculated. No return value. + */ +void omap2xxx_clkt_vps_late_init(void) +{ + struct clk *c; + + c = clk_get(NULL, "sys_ck"); + if (IS_ERR(c)) { + WARN(1, "could not locate sys_ck\n"); + } else { + sys_ck_rate = clk_get_rate(c); + clk_put(c); + } +} diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index 7c6da2f731dc..8e48c6d602e7 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -21,9 +21,7 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/clock.h> -#include <plat/sram.h> -#include <plat/sdrc.h> +#include "../plat-omap/sram.h" #include "clock.h" #include "clock3xxx.h" @@ -47,8 +45,10 @@ * Program the DPLL M2 divider with the rounded target rate. Returns * -EINVAL upon error, or 0 upon success. */ -int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) +int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) { + struct clk_hw_omap *clk = to_clk_hw_omap(hw); u32 new_div = 0; u32 unlock_dll = 0; u32 c; @@ -66,7 +66,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) return -EINVAL; sdrcrate = __clk_get_rate(sdrc_ick_p); - clkrate = __clk_get_rate(clk); + clkrate = __clk_get_rate(hw->clk); if (rate > clkrate) sdrcrate <<= ((rate / clkrate) >> 1); else @@ -115,8 +115,6 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 0, 0, 0, 0); - clk->rate = rate; - return 0; } diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index 3ff22114d702..0ec9f6fdf046 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -41,12 +41,10 @@ #include <linux/kernel.h> #include <linux/errno.h> -#include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/io.h> #include <linux/bug.h> -#include <plat/clock.h> - #include "clock.h" /* Private functions */ @@ -60,11 +58,14 @@ * the element associated with the supplied parent clock address. * Returns a pointer to the struct clksel on success or NULL on error. */ -static const struct clksel *_get_clksel_by_parent(struct clk *clk, +static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, struct clk *src_clk) { const struct clksel *clks; + if (!src_clk) + return NULL; + for (clks = clk->clksel; clks->parent; clks++) if (clks->parent == src_clk) break; /* Found the requested parent */ @@ -72,7 +73,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk, if (!clks->parent) { /* This indicates a data problem */ WARN(1, "clock: %s: could not find parent clock %s in clksel array\n", - __clk_get_name(clk), __clk_get_name(src_clk)); + __clk_get_name(clk->hw.clk), __clk_get_name(src_clk)); return NULL; } @@ -80,64 +81,6 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk, } /** - * _get_div_and_fieldval() - find the new clksel divisor and field value to use - * @src_clk: planned new parent struct clk * - * @clk: struct clk * that is being reparented - * @field_val: pointer to a u32 to contain the register data for the divisor - * - * Given an intended new parent struct clk * @src_clk, and the struct - * clk * @clk to the clock that is being reparented, find the - * appropriate rate divisor for the new clock (returned as the return - * value), and the corresponding register bitfield data to program to - * reach that divisor (returned in the u32 pointed to by @field_val). - * Returns 0 on error, or returns the newly-selected divisor upon - * success (in this latter case, the corresponding register bitfield - * value is passed back in the variable pointed to by @field_val) - */ -static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, - u32 *field_val) -{ - const struct clksel *clks; - const struct clksel_rate *clkr, *max_clkr = NULL; - u8 max_div = 0; - - clks = _get_clksel_by_parent(clk, src_clk); - if (!clks) - return 0; - - /* - * Find the highest divisor (e.g., the one resulting in the - * lowest rate) to use as the default. This should avoid - * clock rates that are too high for the device. XXX A better - * solution here would be to try to determine if there is a - * divisor matching the original clock rate before the parent - * switch, and if it cannot be found, to fall back to the - * highest divisor. - */ - for (clkr = clks->rates; clkr->div; clkr++) { - if (!(clkr->flags & cpu_mask)) - continue; - - if (clkr->div > max_div) { - max_div = clkr->div; - max_clkr = clkr; - } - } - - if (max_div == 0) { - /* This indicates an error in the clksel data */ - WARN(1, "clock: %s: could not find divisor for parent %s\n", - __clk_get_name(clk), - __clk_get_name(__clk_get_parent(src_clk))); - return 0; - } - - *field_val = max_clkr->val; - - return max_div; -} - -/** * _write_clksel_reg() - program a clock's clksel register in hardware * @clk: struct clk * to program * @v: clksel bitfield value to program (with LSB at bit 0) @@ -150,7 +93,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk, * take into account any time the hardware might take to switch the * clock source. */ -static void _write_clksel_reg(struct clk *clk, u32 field_val) +static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val) { u32 v; @@ -173,13 +116,14 @@ static void _write_clksel_reg(struct clk *clk, u32 field_val) * before calling. Returns 0 on error or returns the actual integer divisor * upon success. */ -static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) +static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val) { const struct clksel *clks; const struct clksel_rate *clkr; struct clk *parent; - parent = __clk_get_parent(clk); + parent = __clk_get_parent(clk->hw.clk); + clks = _get_clksel_by_parent(clk, parent); if (!clks) return 0; @@ -195,7 +139,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) if (!clkr->div) { /* This indicates a data error */ WARN(1, "clock: %s: could not find fieldval %d for parent %s\n", - __clk_get_name(clk), field_val, __clk_get_name(parent)); + __clk_get_name(clk->hw.clk), field_val, + __clk_get_name(parent)); return 0; } @@ -212,7 +157,7 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val) * register field value _before_ left-shifting (i.e., LSB is at bit * 0); or returns 0xFFFFFFFF (~0) upon error. */ -static u32 _divisor_to_clksel(struct clk *clk, u32 div) +static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) { const struct clksel *clks; const struct clksel_rate *clkr; @@ -221,7 +166,7 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) /* should never happen */ WARN_ON(div == 0); - parent = __clk_get_parent(clk); + parent = __clk_get_parent(clk->hw.clk); clks = _get_clksel_by_parent(clk, parent); if (!clks) return ~0; @@ -236,7 +181,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) if (!clkr->div) { pr_err("clock: %s: could not find divisor %d for parent %s\n", - __clk_get_name(clk), div, __clk_get_name(parent)); + __clk_get_name(clk->hw.clk), div, + __clk_get_name(parent)); return ~0; } @@ -251,7 +197,7 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div) * into the hardware, convert it into the actual divisor value, and * return it; or return 0 on error. */ -static u32 _read_divisor(struct clk *clk) +static u32 _read_divisor(struct clk_hw_omap *clk) { u32 v; @@ -279,7 +225,8 @@ static u32 _read_divisor(struct clk *clk) * * Returns the rounded clock rate or returns 0xffffffff on error. */ -u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, +u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, + unsigned long target_rate, u32 *new_div) { unsigned long test_rate; @@ -290,9 +237,9 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, unsigned long parent_rate; const char *clk_name; - parent = __clk_get_parent(clk); + parent = __clk_get_parent(clk->hw.clk); + clk_name = __clk_get_name(clk->hw.clk); parent_rate = __clk_get_rate(parent); - clk_name = __clk_get_name(clk); if (!clk->clksel || !clk->clksel_mask) return ~0; @@ -343,27 +290,35 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, */ /** - * omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr - * @clk: OMAP clock struct ptr to use + * omap2_clksel_find_parent_index() - return the array index of the current + * hardware parent of @hw + * @hw: struct clk_hw * to find the current hardware parent of * - * Given a pointer @clk to a source-selectable struct clk, read the - * hardware register and determine what its parent is currently set - * to. Update @clk's .parent field with the appropriate clk ptr. No - * return value. + * Given a struct clk_hw pointer @hw to the 'hw' member of a struct + * clk_hw_omap record representing a source-selectable hardware clock, + * read the hardware register and determine what its parent is + * currently set to. Intended to be called only by the common clock + * framework struct clk_hw_ops.get_parent function pointer. Return + * the array index of this parent clock upon success -- there is no + * way to return an error, so if we encounter an error, just WARN() + * and pretend that we know that we're doing. */ -void omap2_init_clksel_parent(struct clk *clk) +u8 omap2_clksel_find_parent_index(struct clk_hw *hw) { + struct clk_hw_omap *clk = to_clk_hw_omap(hw); const struct clksel *clks; const struct clksel_rate *clkr; u32 r, found = 0; struct clk *parent; const char *clk_name; + int ret = 0, f = 0; - if (!clk->clksel || !clk->clksel_mask) - return; + parent = __clk_get_parent(hw->clk); + clk_name = __clk_get_name(hw->clk); - parent = __clk_get_parent(clk); - clk_name = __clk_get_name(clk); + /* XXX should be able to return an error */ + WARN((!clk->clksel || !clk->clksel_mask), + "clock: %s: attempt to call on a non-clksel clock", clk_name); r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; r >>= __ffs(clk->clksel_mask); @@ -374,27 +329,21 @@ void omap2_init_clksel_parent(struct clk *clk) continue; if (clkr->val == r) { - if (parent != clks->parent) { - pr_debug("clock: %s: inited parent to %s (was %s)\n", - clk_name, - __clk_get_name(clks->parent), - ((parent) ? - __clk_get_name(parent) : - "NULL")); - clk_reparent(clk, clks->parent); - } found = 1; + ret = f; } } + f++; } /* This indicates a data error */ WARN(!found, "clock: %s: init parent: could not find regval %0x\n", clk_name, r); - return; + return ret; } + /** * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field * @clk: struct clk * @@ -404,21 +353,23 @@ void omap2_init_clksel_parent(struct clk *clk) * function. Returns the clock's current rate, based on its parent's rate * and its current divisor setting in the hardware. */ -unsigned long omap2_clksel_recalc(struct clk *clk) +unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate) { unsigned long rate; u32 div = 0; - struct clk *parent; + struct clk_hw_omap *clk = to_clk_hw_omap(hw); - div = _read_divisor(clk); - if (div == 0) - return __clk_get_rate(clk); + if (!parent_rate) + return 0; - parent = __clk_get_parent(clk); - rate = __clk_get_rate(parent) / div; + div = _read_divisor(clk); + if (!div) + rate = parent_rate; + else + rate = parent_rate / div; - pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", - __clk_get_name(clk), rate, div); + pr_debug("%s: recalc'd %s's rate to %lu (div %d)\n", __func__, + __clk_get_name(hw->clk), rate, div); return rate; } @@ -434,8 +385,10 @@ unsigned long omap2_clksel_recalc(struct clk *clk) * * Returns the rounded clock rate or returns 0xffffffff on error. */ -long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) +long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, + unsigned long *parent_rate) { + struct clk_hw_omap *clk = to_clk_hw_omap(hw); u32 new_div; return omap2_clksel_round_rate_div(clk, target_rate, &new_div); @@ -456,8 +409,10 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) * is changed, they will all be affected without any notification. * Returns -EINVAL upon error, or 0 upon success. */ -int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) +int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) { + struct clk_hw_omap *clk = to_clk_hw_omap(hw); u32 field_val, validrate, new_div = 0; if (!clk->clksel || !clk->clksel_mask) @@ -473,10 +428,8 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) _write_clksel_reg(clk, field_val); - clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div; - - pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk), - __clk_get_rate(clk)); + pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(hw->clk), + __clk_get_rate(hw->clk)); return 0; } @@ -501,32 +454,13 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) * affected without any notification. Returns -EINVAL upon error, or * 0 upon success. */ -int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent) +int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val) { - u32 field_val = 0; - u32 parent_div; + struct clk_hw_omap *clk = to_clk_hw_omap(hw); if (!clk->clksel || !clk->clksel_mask) return -EINVAL; - parent_div = _get_div_and_fieldval(new_parent, clk, &field_val); - if (!parent_div) - return -EINVAL; - _write_clksel_reg(clk, field_val); - - clk_reparent(clk, new_parent); - - /* CLKSEL clocks follow their parents' rates, divided by a divisor */ - clk->rate = __clk_get_rate(new_parent); - - if (parent_div > 0) - __clk_get_rate(clk) /= parent_div; - - pr_debug("clock: %s: set parent to %s (new rate %ld)\n", - __clk_get_name(clk), - __clk_get_name(__clk_get_parent(clk)), - __clk_get_rate(clk)); - return 0; } diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 80411142f482..924c230f8948 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -16,13 +16,11 @@ #include <linux/kernel.h> #include <linux/errno.h> -#include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/io.h> #include <asm/div64.h> -#include <plat/clock.h> - #include "soc.h" #include "clock.h" #include "cm-regbits-24xx.h" @@ -78,7 +76,7 @@ * (assuming that it is counting N upwards), or -2 if the enclosing loop * should skip to the next iteration (again assuming N is increasing). */ -static int _dpll_test_fint(struct clk *clk, u8 n) +static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n) { struct dpll_data *dd; long fint, fint_min, fint_max; @@ -87,7 +85,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n) dd = clk->dpll_data; /* DPLL divider must result in a valid jitter correction val */ - fint = __clk_get_rate(__clk_get_parent(clk)) / n; + fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n; if (cpu_is_omap24xx()) { /* Should not be called for OMAP2, so warn if it is called */ @@ -188,15 +186,15 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, } /* Public functions */ - -void omap2_init_dpll_parent(struct clk *clk) +u8 omap2_init_dpll_parent(struct clk_hw *hw) { + struct clk_hw_omap *clk = to_clk_hw_omap(hw); u32 v; struct dpll_data *dd; dd = clk->dpll_data; if (!dd) - return; + return -EINVAL; v = __raw_readl(dd->control_reg); v &= dd->enable_mask; @@ -206,18 +204,18 @@ void omap2_init_dpll_parent(struct clk *clk) if (cpu_is_omap24xx()) { if (v == OMAP2XXX_EN_DPLL_LPBYPASS || v == OMAP2XXX_EN_DPLL_FRBYPASS) - clk_reparent(clk, dd->clk_bypass); + return 1; } else if (cpu_is_omap34xx()) { if (v == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) - clk_reparent(clk, dd->clk_bypass); + return 1; } else if (soc_is_am33xx() || cpu_is_omap44xx()) { if (v == OMAP4XXX_EN_DPLL_LPBYPASS || v == OMAP4XXX_EN_DPLL_FRBYPASS || v == OMAP4XXX_EN_DPLL_MNBYPASS) - clk_reparent(clk, dd->clk_bypass); + return 1; } - return; + return 0; } /** @@ -234,7 +232,7 @@ void omap2_init_dpll_parent(struct clk *clk) * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 * if the clock @clk is not a DPLL. */ -u32 omap2_get_dpll_rate(struct clk *clk) +unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) { long long dpll_clk; u32 dpll_mult, dpll_div, v; @@ -290,8 +288,10 @@ u32 omap2_get_dpll_rate(struct clk *clk) * (expensive) function again. Returns ~0 if the target rate cannot * be rounded, or the rounded rate upon success. */ -long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) +long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, + unsigned long *parent_rate) { + struct clk_hw_omap *clk = to_clk_hw_omap(hw); int m, n, r, scaled_max_m; unsigned long scaled_rt_rp; unsigned long new_rate = 0; @@ -305,7 +305,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) dd = clk->dpll_data; ref_rate = __clk_get_rate(dd->clk_ref); - clk_name = __clk_get_name(clk); + clk_name = __clk_get_name(hw->clk); pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", clk_name, target_rate); diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c index 3d43fba2542f..f10eb03ce3e2 100644 --- a/arch/arm/mach-omap2/clkt_iclk.c +++ b/arch/arm/mach-omap2/clkt_iclk.c @@ -11,11 +11,9 @@ #undef DEBUG #include <linux/kernel.h> -#include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/io.h> -#include <plat/clock.h> -#include <plat/prcm.h> #include "clock.h" #include "clock2xxx.h" @@ -25,7 +23,7 @@ /* Private functions */ /* XXX */ -void omap2_clkt_iclk_allow_idle(struct clk *clk) +void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk) { u32 v, r; @@ -37,7 +35,7 @@ void omap2_clkt_iclk_allow_idle(struct clk *clk) } /* XXX */ -void omap2_clkt_iclk_deny_idle(struct clk *clk) +void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk) { u32 v, r; @@ -50,33 +48,17 @@ void omap2_clkt_iclk_deny_idle(struct clk *clk) /* Public data */ -const struct clkops clkops_omap2_iclk_dflt_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_companion = omap2_clk_dflt_find_companion, - .find_idlest = omap2_clk_dflt_find_idlest, +const struct clk_hw_omap_ops clkhwops_iclk = { .allow_idle = omap2_clkt_iclk_allow_idle, .deny_idle = omap2_clkt_iclk_deny_idle, }; -const struct clkops clkops_omap2_iclk_dflt = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, +const struct clk_hw_omap_ops clkhwops_iclk_wait = { .allow_idle = omap2_clkt_iclk_allow_idle, .deny_idle = omap2_clkt_iclk_deny_idle, + .find_idlest = omap2_clk_dflt_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, }; -const struct clkops clkops_omap2_iclk_idle_only = { - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, -}; -const struct clkops clkops_omap2_mdmclk_dflt_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_companion = omap2_clk_dflt_find_companion, - .find_idlest = omap2_clk_dflt_find_idlest, - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, -}; diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 961ac8f7e13d..e4ec3a69ee2e 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -15,27 +15,35 @@ #undef DEBUG #include <linux/kernel.h> +#include <linux/export.h> #include <linux/list.h> #include <linux/errno.h> #include <linux/err.h> #include <linux/delay.h> -#include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/io.h> #include <linux/bitops.h> #include <asm/cpu.h> -#include <plat/clock.h> -#include <plat/prcm.h> #include <trace/events/power.h> #include "soc.h" #include "clockdomain.h" #include "clock.h" -#include "cm2xxx_3xxx.h" +#include "cm.h" +#include "cm2xxx.h" +#include "cm3xxx.h" #include "cm-regbits-24xx.h" #include "cm-regbits-34xx.h" +#include "common.h" + +/* + * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait + * for a module to indicate that it is no longer in idle + */ +#define MAX_MODULE_ENABLE_WAIT 100000 u16 cpu_mask; @@ -47,12 +55,69 @@ u16 cpu_mask; */ static bool clkdm_control = true; +static LIST_HEAD(clk_hw_omap_clocks); + +/* + * Used for clocks that have the same value as the parent clock, + * divided by some factor + */ +unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_hw_omap *oclk; + + if (!hw) { + pr_warn("%s: hw is NULL\n", __func__); + return -EINVAL; + } + + oclk = to_clk_hw_omap(hw); + + WARN_ON(!oclk->fixed_div); + + return parent_rate / oclk->fixed_div; +} + /* * OMAP2+ specific clock functions */ /* Private functions */ + +/** + * _wait_idlest_generic - wait for a module to leave the idle state + * @reg: virtual address of module IDLEST register + * @mask: value to mask against to determine if the module is active + * @idlest: idle state indicator (0 or 1) for the clock + * @name: name of the clock (for printk) + * + * Wait for a module to leave idle, where its idle-status register is + * not inside the CM module. Returns 1 if the module left idle + * promptly, or 0 if the module did not leave idle before the timeout + * elapsed. XXX Deprecated - should be moved into drivers for the + * individual IP block that the IDLEST register exists in. + */ +static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest, + const char *name) +{ + int i = 0, ena = 0; + + ena = (idlest) ? 0 : mask; + + omap_test_timeout(((__raw_readl(reg) & mask) == ena), + MAX_MODULE_ENABLE_WAIT, i); + + if (i < MAX_MODULE_ENABLE_WAIT) + pr_debug("omap clock: module associated with clock %s ready after %d loops\n", + name, i); + else + pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n", + name, MAX_MODULE_ENABLE_WAIT); + + return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0; +}; + /** * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE * @clk: struct clk * belonging to the module @@ -63,10 +128,12 @@ static bool clkdm_control = true; * belong in the clock code and will be moved in the medium term to * module-dependent code. No return value. */ -static void _omap2_module_wait_ready(struct clk *clk) +static void _omap2_module_wait_ready(struct clk_hw_omap *clk) { void __iomem *companion_reg, *idlest_reg; - u8 other_bit, idlest_bit, idlest_val; + u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; + s16 prcm_mod; + int r; /* Not all modules have multiple clocks that their IDLEST depends on */ if (clk->ops->find_companion) { @@ -76,9 +143,14 @@ static void _omap2_module_wait_ready(struct clk *clk) } clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); - - omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val, - __clk_get_name(clk)); + r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id); + if (r) { + /* IDLEST register not in the CM module */ + _wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val, + __clk_get_name(clk->hw.clk)); + } else { + cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit); + }; } /* Public functions */ @@ -91,15 +163,16 @@ static void _omap2_module_wait_ready(struct clk *clk) * clockdomain pointer, and save it into the struct clk. Intended to be * called during clk_register(). No return value. */ -void omap2_init_clk_clkdm(struct clk *clk) +void omap2_init_clk_clkdm(struct clk_hw *hw) { + struct clk_hw_omap *clk = to_clk_hw_omap(hw); struct clockdomain *clkdm; const char *clk_name; if (!clk->clkdm_name) return; - clk_name = __clk_get_name(clk); + clk_name = __clk_get_name(hw->clk); clkdm = clkdm_lookup(clk->clkdm_name); if (clkdm) { @@ -146,8 +219,8 @@ void __init omap2_clk_disable_clkdm_control(void) * associate this type of code with per-module data structures to * avoid this issue, and remove the casts. No return value. */ -void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, - u8 *other_bit) +void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, + void __iomem **other_reg, u8 *other_bit) { u32 r; @@ -175,8 +248,8 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, * register address ID (e.g., that CM_FCLKEN2 corresponds to * CM_IDLEST2). This is not true for all modules. No return value. */ -void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, - u8 *idlest_bit, u8 *idlest_val) +void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, + void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) { u32 r; @@ -198,16 +271,44 @@ void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, } -int omap2_dflt_clk_enable(struct clk *clk) +/** + * omap2_dflt_clk_enable - enable a clock in the hardware + * @hw: struct clk_hw * of the clock to enable + * + * Enable the clock @hw in the hardware. We first call into the OMAP + * clockdomain code to "enable" the corresponding clockdomain if this + * is the first enabled user of the clockdomain. Then program the + * hardware to enable the clock. Then wait for the IP block that uses + * this clock to leave idle (if applicable). Returns the error value + * from clkdm_clk_enable() if it terminated with an error, or -EINVAL + * if @hw has a null clock enable_reg, or zero upon success. + */ +int omap2_dflt_clk_enable(struct clk_hw *hw) { + struct clk_hw_omap *clk; u32 v; + int ret = 0; + + clk = to_clk_hw_omap(hw); + + if (clkdm_control && clk->clkdm) { + ret = clkdm_clk_enable(clk->clkdm, hw->clk); + if (ret) { + WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", + __func__, __clk_get_name(hw->clk), + clk->clkdm->name, ret); + return ret; + } + } if (unlikely(clk->enable_reg == NULL)) { - pr_err("clock.c: Enable for %s without enable code\n", - clk->name); - return 0; /* REVISIT: -EINVAL */ + pr_err("%s: %s missing enable_reg\n", __func__, + __clk_get_name(hw->clk)); + ret = -EINVAL; + goto err; } + /* FIXME should not have INVERT_ENABLE bit here */ v = __raw_readl(clk->enable_reg); if (clk->flags & INVERT_ENABLE) v &= ~(1 << clk->enable_bit); @@ -216,22 +317,39 @@ int omap2_dflt_clk_enable(struct clk *clk) __raw_writel(v, clk->enable_reg); v = __raw_readl(clk->enable_reg); /* OCP barrier */ - if (clk->ops->find_idlest) + if (clk->ops && clk->ops->find_idlest) _omap2_module_wait_ready(clk); return 0; + +err: + if (clkdm_control && clk->clkdm) + clkdm_clk_disable(clk->clkdm, hw->clk); + return ret; } -void omap2_dflt_clk_disable(struct clk *clk) +/** + * omap2_dflt_clk_disable - disable a clock in the hardware + * @hw: struct clk_hw * of the clock to disable + * + * Disable the clock @hw in the hardware, and call into the OMAP + * clockdomain code to "disable" the corresponding clockdomain if all + * clocks/hwmods in that clockdomain are now disabled. No return + * value. + */ +void omap2_dflt_clk_disable(struct clk_hw *hw) { + struct clk_hw_omap *clk; u32 v; + clk = to_clk_hw_omap(hw); if (!clk->enable_reg) { /* - * 'Independent' here refers to a clock which is not + * 'independent' here refers to a clock which is not * controlled by its parent. */ - pr_err("clock: clk_disable called on independent clock %s which has no enable_reg\n", clk->name); + pr_err("%s: independent clock %s has no enable_reg\n", + __func__, __clk_get_name(hw->clk)); return; } @@ -242,191 +360,213 @@ void omap2_dflt_clk_disable(struct clk *clk) v &= ~(1 << clk->enable_bit); __raw_writel(v, clk->enable_reg); /* No OCP barrier needed here since it is a disable operation */ -} - -const struct clkops clkops_omap2_dflt_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_companion = omap2_clk_dflt_find_companion, - .find_idlest = omap2_clk_dflt_find_idlest, -}; -const struct clkops clkops_omap2_dflt = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, -}; + if (clkdm_control && clk->clkdm) + clkdm_clk_disable(clk->clkdm, hw->clk); +} /** - * omap2_clk_disable - disable a clock, if the system is not using it - * @clk: struct clk * to disable + * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw + * @hw: struct clk_hw * of the clock being enabled * - * Decrements the usecount on struct clk @clk. If there are no users - * left, call the clkops-specific clock disable function to disable it - * in hardware. If the clock is part of a clockdomain (which they all - * should be), request that the clockdomain be disabled. (It too has - * a usecount, and so will not be disabled in the hardware until it no - * longer has any users.) If the clock has a parent clock (most of - * them do), then call ourselves, recursing on the parent clock. This - * can cause an entire branch of the clock tree to be powered off by - * simply disabling one clock. Intended to be called with the clockfw_lock - * spinlock held. No return value. + * Increment the usecount of the clockdomain of the clock pointed to + * by @hw; if the usecount is 1, the clockdomain will be "enabled." + * Only needed for clocks that don't use omap2_dflt_clk_enable() as + * their enable function pointer. Passes along the return value of + * clkdm_clk_enable(), -EINVAL if @hw is not associated with a + * clockdomain, or 0 if clock framework-based clockdomain control is + * not implemented. */ -void omap2_clk_disable(struct clk *clk) +int omap2_clkops_enable_clkdm(struct clk_hw *hw) { - if (clk->usecount == 0) { - WARN(1, "clock: %s: omap2_clk_disable() called, but usecount already 0?", clk->name); - return; - } + struct clk_hw_omap *clk; + int ret = 0; - pr_debug("clock: %s: decrementing usecount\n", clk->name); + clk = to_clk_hw_omap(hw); - clk->usecount--; - - if (clk->usecount > 0) - return; + if (unlikely(!clk->clkdm)) { + pr_err("%s: %s: no clkdm set ?!\n", __func__, + __clk_get_name(hw->clk)); + return -EINVAL; + } - pr_debug("clock: %s: disabling in hardware\n", clk->name); + if (unlikely(clk->enable_reg)) + pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__, + __clk_get_name(hw->clk)); - if (clk->ops && clk->ops->disable) { - trace_clock_disable(clk->name, 0, smp_processor_id()); - clk->ops->disable(clk); + if (!clkdm_control) { + pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", + __func__, __clk_get_name(hw->clk)); + return 0; } - if (clkdm_control && clk->clkdm) - clkdm_clk_disable(clk->clkdm, clk); + ret = clkdm_clk_enable(clk->clkdm, hw->clk); + WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n", + __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret); - if (clk->parent) - omap2_clk_disable(clk->parent); + return ret; } /** - * omap2_clk_enable - request that the system enable a clock - * @clk: struct clk * to enable + * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw + * @hw: struct clk_hw * of the clock being disabled * - * Increments the usecount on struct clk @clk. If there were no users - * previously, then recurse up the clock tree, enabling all of the - * clock's parents and all of the parent clockdomains, and finally, - * enabling @clk's clockdomain, and @clk itself. Intended to be - * called with the clockfw_lock spinlock held. Returns 0 upon success - * or a negative error code upon failure. + * Decrement the usecount of the clockdomain of the clock pointed to + * by @hw; if the usecount is 0, the clockdomain will be "disabled." + * Only needed for clocks that don't use omap2_dflt_clk_disable() as their + * disable function pointer. No return value. */ -int omap2_clk_enable(struct clk *clk) +void omap2_clkops_disable_clkdm(struct clk_hw *hw) { - int ret; - - pr_debug("clock: %s: incrementing usecount\n", clk->name); - - clk->usecount++; - - if (clk->usecount > 1) - return 0; + struct clk_hw_omap *clk; - pr_debug("clock: %s: enabling in hardware\n", clk->name); + clk = to_clk_hw_omap(hw); - if (clk->parent) { - ret = omap2_clk_enable(clk->parent); - if (ret) { - WARN(1, "clock: %s: could not enable parent %s: %d\n", - clk->name, clk->parent->name, ret); - goto oce_err1; - } + if (unlikely(!clk->clkdm)) { + pr_err("%s: %s: no clkdm set ?!\n", __func__, + __clk_get_name(hw->clk)); + return; } - if (clkdm_control && clk->clkdm) { - ret = clkdm_clk_enable(clk->clkdm, clk); - if (ret) { - WARN(1, "clock: %s: could not enable clockdomain %s: %d\n", - clk->name, clk->clkdm->name, ret); - goto oce_err2; - } - } + if (unlikely(clk->enable_reg)) + pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__, + __clk_get_name(hw->clk)); - if (clk->ops && clk->ops->enable) { - trace_clock_enable(clk->name, 1, smp_processor_id()); - ret = clk->ops->enable(clk); - if (ret) { - WARN(1, "clock: %s: could not enable: %d\n", - clk->name, ret); - goto oce_err3; - } + if (!clkdm_control) { + pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", + __func__, __clk_get_name(hw->clk)); + return; } - return 0; - -oce_err3: - if (clkdm_control && clk->clkdm) - clkdm_clk_disable(clk->clkdm, clk); -oce_err2: - if (clk->parent) - omap2_clk_disable(clk->parent); -oce_err1: - clk->usecount--; - - return ret; + clkdm_clk_disable(clk->clkdm, hw->clk); } -/* Given a clock and a rate apply a clock specific rounding function */ -long omap2_clk_round_rate(struct clk *clk, unsigned long rate) +/** + * omap2_dflt_clk_is_enabled - is clock enabled in the hardware? + * @hw: struct clk_hw * to check + * + * Return 1 if the clock represented by @hw is enabled in the + * hardware, or 0 otherwise. Intended for use in the struct + * clk_ops.is_enabled function pointer. + */ +int omap2_dflt_clk_is_enabled(struct clk_hw *hw) { - if (clk->round_rate) - return clk->round_rate(clk, rate); + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + u32 v; + + v = __raw_readl(clk->enable_reg); + + if (clk->flags & INVERT_ENABLE) + v ^= BIT(clk->enable_bit); + + v &= BIT(clk->enable_bit); - return clk->rate; + return v ? 1 : 0; } -/* Set the clock rate for a clock source */ -int omap2_clk_set_rate(struct clk *clk, unsigned long rate) +static int __initdata mpurate; + +/* + * By default we use the rate set by the bootloader. + * You can override this with mpurate= cmdline option. + */ +static int __init omap_clk_setup(char *str) { - int ret = -EINVAL; + get_option(&str, &mpurate); - pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); + if (!mpurate) + return 1; - /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ - if (clk->set_rate) { - trace_clock_set_rate(clk->name, rate, smp_processor_id()); - ret = clk->set_rate(clk, rate); - } + if (mpurate < 1000) + mpurate *= 1000000; - return ret; + return 1; } +__setup("mpurate=", omap_clk_setup); -int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) +/** + * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock + * @clk: struct clk * to initialize + * + * Add an OMAP clock @clk to the internal list of OMAP clocks. Used + * temporarily for autoidle handling, until this support can be + * integrated into the common clock framework code in some way. No + * return value. + */ +void omap2_init_clk_hw_omap_clocks(struct clk *clk) { - if (!clk->clksel) - return -EINVAL; + struct clk_hw_omap *c; - if (clk->parent == new_parent) - return 0; + if (__clk_get_flags(clk) & CLK_IS_BASIC) + return; - return omap2_clksel_set_parent(clk, new_parent); + c = to_clk_hw_omap(__clk_get_hw(clk)); + list_add(&c->node, &clk_hw_omap_clocks); } -/* - * OMAP2+ clock reset and init functions +/** + * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that + * support it + * + * Enable clock autoidle on all OMAP clocks that have allow_idle + * function pointers associated with them. This function is intended + * to be temporary until support for this is added to the common clock + * code. Returns 0. */ +int omap2_clk_enable_autoidle_all(void) +{ + struct clk_hw_omap *c; + + list_for_each_entry(c, &clk_hw_omap_clocks, node) + if (c->ops && c->ops->allow_idle) + c->ops->allow_idle(c); + return 0; +} -#ifdef CONFIG_OMAP_RESET_CLOCKS -void omap2_clk_disable_unused(struct clk *clk) +/** + * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that + * support it + * + * Disable clock autoidle on all OMAP clocks that have allow_idle + * function pointers associated with them. This function is intended + * to be temporary until support for this is added to the common clock + * code. Returns 0. + */ +int omap2_clk_disable_autoidle_all(void) { - u32 regval32, v; + struct clk_hw_omap *c; - v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; + list_for_each_entry(c, &clk_hw_omap_clocks, node) + if (c->ops && c->ops->deny_idle) + c->ops->deny_idle(c); + return 0; +} - regval32 = __raw_readl(clk->enable_reg); - if ((regval32 & (1 << clk->enable_bit)) == v) - return; +/** + * omap2_clk_enable_init_clocks - prepare & enable a list of clocks + * @clk_names: ptr to an array of strings of clock names to enable + * @num_clocks: number of clock names in @clk_names + * + * Prepare and enable a list of clocks, named by @clk_names. No + * return value. XXX Deprecated; only needed until these clocks are + * properly claimed and enabled by the drivers or core code that uses + * them. XXX What code disables & calls clk_put on these clocks? + */ +void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) +{ + struct clk *init_clk; + int i; - pr_debug("Disabling unused clock \"%s\"\n", clk->name); - if (cpu_is_omap34xx()) { - omap2_clk_enable(clk); - omap2_clk_disable(clk); - } else { - clk->ops->disable(clk); + for (i = 0; i < num_clocks; i++) { + init_clk = clk_get(NULL, clk_names[i]); + clk_prepare_enable(init_clk); } - if (clk->clkdm != NULL) - pwrdm_state_switch(clk->clkdm->pwrdm.ptr); } -#endif + +const struct clk_hw_omap_ops clkhwops_wait = { + .find_idlest = omap2_clk_dflt_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, +}; /** * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument @@ -458,14 +598,12 @@ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) r = clk_set_rate(mpurate_ck, mpurate); if (IS_ERR_VALUE(r)) { WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", - mpurate_ck->name, mpurate, r); + mpurate_ck_name, mpurate, r); clk_put(mpurate_ck); return -EINVAL; } calibrate_delay(); - recalculate_root_clocks(); - clk_put(mpurate_ck); return 0; @@ -509,15 +647,3 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, (clk_get_rate(core_ck) / 1000000), (clk_get_rate(mpu_ck) / 1000000)); } - -/* Common data */ - -struct clk_functions omap2_clk_functions = { - .clk_enable = omap2_clk_enable, - .clk_disable = omap2_clk_disable, - .clk_round_rate = omap2_clk_round_rate, - .clk_set_rate = omap2_clk_set_rate, - .clk_set_parent = omap2_clk_set_parent, - .clk_disable_unused = omap2_clk_disable_unused, -}; - diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 35ec5f3d9a73..9917f793c3b6 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -17,8 +17,311 @@ #define __ARCH_ARM_MACH_OMAP2_CLOCK_H #include <linux/kernel.h> +#include <linux/list.h> -#include <plat/clock.h> +#include <linux/clkdev.h> +#include <linux/clk-provider.h> + +struct omap_clk { + u16 cpu; + struct clk_lookup lk; +}; + +#define CLK(dev, con, ck, cp) \ + { \ + .cpu = cp, \ + .lk = { \ + .dev_id = dev, \ + .con_id = con, \ + .clk = ck, \ + }, \ + } + +/* Platform flags for the clkdev-OMAP integration code */ +#define CK_242X (1 << 0) +#define CK_243X (1 << 1) /* 243x, 253x */ +#define CK_3430ES1 (1 << 2) /* 34xxES1 only */ +#define CK_3430ES2PLUS (1 << 3) /* 34xxES2, ES3, non-Sitara 35xx only */ +#define CK_AM35XX (1 << 4) /* Sitara AM35xx */ +#define CK_36XX (1 << 5) /* 36xx/37xx-specific clocks */ +#define CK_443X (1 << 6) +#define CK_TI816X (1 << 7) +#define CK_446X (1 << 8) +#define CK_AM33XX (1 << 9) /* AM33xx specific clocks */ + + +#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) +#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX) + +struct clockdomain; +#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) + +#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \ + static struct clk _name = { \ + .name = #_name, \ + .hw = &_name##_hw.hw, \ + .parent_names = _parent_array_name, \ + .num_parents = ARRAY_SIZE(_parent_array_name), \ + .ops = &_clkops_name, \ + }; + +#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \ + static struct clk_hw_omap _name##_hw = { \ + .hw = { \ + .clk = &_name, \ + }, \ + .clkdm_name = _clkdm_name, \ + }; + +#define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \ + _clksel_reg, _clksel_mask, \ + _parent_names, _ops) \ + static struct clk _name; \ + static struct clk_hw_omap _name##_hw = { \ + .hw = { \ + .clk = &_name, \ + }, \ + .clksel = _clksel, \ + .clksel_reg = _clksel_reg, \ + .clksel_mask = _clksel_mask, \ + .clkdm_name = _clkdm_name, \ + }; \ + DEFINE_STRUCT_CLK(_name, _parent_names, _ops); + +#define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \ + _clksel_reg, _clksel_mask, \ + _enable_reg, _enable_bit, \ + _hwops, _parent_names, _ops) \ + static struct clk _name; \ + static struct clk_hw_omap _name##_hw = { \ + .hw = { \ + .clk = &_name, \ + }, \ + .ops = _hwops, \ + .enable_reg = _enable_reg, \ + .enable_bit = _enable_bit, \ + .clksel = _clksel, \ + .clksel_reg = _clksel_reg, \ + .clksel_mask = _clksel_mask, \ + .clkdm_name = _clkdm_name, \ + }; \ + DEFINE_STRUCT_CLK(_name, _parent_names, _ops); + +#define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \ + _parent_ptr, _flags, \ + _clksel_reg, _clksel_mask) \ + static const struct clksel _name##_div[] = { \ + { \ + .parent = _parent_ptr, \ + .rates = div31_1to31_rates \ + }, \ + { .parent = NULL }, \ + }; \ + static struct clk _name; \ + static const char *_name##_parent_names[] = { \ + _parent_name, \ + }; \ + static struct clk_hw_omap _name##_hw = { \ + .hw = { \ + .clk = &_name, \ + }, \ + .clksel = _name##_div, \ + .clksel_reg = _clksel_reg, \ + .clksel_mask = _clksel_mask, \ + .ops = &clkhwops_omap4_dpllmx, \ + }; \ + DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops); + +/* struct clksel_rate.flags possibilities */ +#define RATE_IN_242X (1 << 0) +#define RATE_IN_243X (1 << 1) +#define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */ +#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */ +#define RATE_IN_36XX (1 << 4) +#define RATE_IN_4430 (1 << 5) +#define RATE_IN_TI816X (1 << 6) +#define RATE_IN_4460 (1 << 7) +#define RATE_IN_AM33XX (1 << 8) +#define RATE_IN_TI814X (1 << 9) + +#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) +#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) +#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX) +#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460) + +/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */ +#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX) + + +/** + * struct clksel_rate - register bitfield values corresponding to clk divisors + * @val: register bitfield value (shifted to bit 0) + * @div: clock divisor corresponding to @val + * @flags: (see "struct clksel_rate.flags possibilities" above) + * + * @val should match the value of a read from struct clk.clksel_reg + * AND'ed with struct clk.clksel_mask, shifted right to bit 0. + * + * @div is the divisor that should be applied to the parent clock's rate + * to produce the current clock's rate. + */ +struct clksel_rate { + u32 val; + u8 div; + u16 flags; +}; + +/** + * struct clksel - available parent clocks, and a pointer to their divisors + * @parent: struct clk * to a possible parent clock + * @rates: available divisors for this parent clock + * + * A struct clksel is always associated with one or more struct clks + * and one or more struct clksel_rates. + */ +struct clksel { + struct clk *parent; + const struct clksel_rate *rates; +}; + +/** + * struct dpll_data - DPLL registers and integration data + * @mult_div1_reg: register containing the DPLL M and N bitfields + * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg + * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg + * @clk_bypass: struct clk pointer to the clock's bypass clock input + * @clk_ref: struct clk pointer to the clock's reference clock input + * @control_reg: register containing the DPLL mode bitfield + * @enable_mask: mask of the DPLL mode bitfield in @control_reg + * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() + * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() + * @max_multiplier: maximum valid non-bypass multiplier value (actual) + * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() + * @min_divider: minimum valid non-bypass divider value (actual) + * @max_divider: maximum valid non-bypass divider value (actual) + * @modes: possible values of @enable_mask + * @autoidle_reg: register containing the DPLL autoidle mode bitfield + * @idlest_reg: register containing the DPLL idle status bitfield + * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg + * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg + * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg + * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg + * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs + * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs + * @flags: DPLL type/features (see below) + * + * Possible values for @flags: + * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) + * + * @freqsel_mask is only used on the OMAP34xx family and AM35xx. + * + * XXX Some DPLLs have multiple bypass inputs, so it's not technically + * correct to only have one @clk_bypass pointer. + * + * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, + * @last_rounded_n) should be separated from the runtime-fixed fields + * and placed into a different structure, so that the runtime-fixed data + * can be placed into read-only space. + */ +struct dpll_data { + void __iomem *mult_div1_reg; + u32 mult_mask; + u32 div1_mask; + struct clk *clk_bypass; + struct clk *clk_ref; + void __iomem *control_reg; + u32 enable_mask; + unsigned long last_rounded_rate; + u16 last_rounded_m; + u16 max_multiplier; + u8 last_rounded_n; + u8 min_divider; + u16 max_divider; + u8 modes; + void __iomem *autoidle_reg; + void __iomem *idlest_reg; + u32 autoidle_mask; + u32 freqsel_mask; + u32 idlest_mask; + u32 dco_mask; + u32 sddiv_mask; + u8 auto_recal_bit; + u8 recal_en_bit; + u8 recal_st_bit; + u8 flags; +}; + +/* + * struct clk.flags possibilities + * + * XXX document the rest of the clock flags here + * + * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL + * bits share the same register. This flag allows the + * omap4_dpllmx*() code to determine which GATE_CTRL bit field + * should be used. This is a temporary solution - a better approach + * would be to associate clock type-specific data with the clock, + * similar to the struct dpll_data approach. + */ +#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ +#define CLOCK_IDLE_CONTROL (1 << 1) +#define CLOCK_NO_IDLE_PARENT (1 << 2) +#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ +#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ +#define CLOCK_CLKOUTX2 (1 << 5) + +/** + * struct clk_hw_omap - OMAP struct clk + * @node: list_head connecting this clock into the full clock list + * @enable_reg: register to write to enable the clock (see @enable_bit) + * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) + * @flags: see "struct clk.flags possibilities" above + * @clksel_reg: for clksel clks, register va containing src/divisor select + * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector + * @clksel: for clksel clks, pointer to struct clksel for this clock + * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock + * @clkdm_name: clockdomain name that this clock is contained in + * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime + * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) + * @src_offset: bitshift for source selection bitfield (OMAP1 only) + * + * XXX @rate_offset, @src_offset should probably be removed and OMAP1 + * clock code converted to use clksel. + * + */ + +struct clk_hw_omap_ops; + +struct clk_hw_omap { + struct clk_hw hw; + struct list_head node; + unsigned long fixed_rate; + u8 fixed_div; + void __iomem *enable_reg; + u8 enable_bit; + u8 flags; + void __iomem *clksel_reg; + u32 clksel_mask; + const struct clksel *clksel; + struct dpll_data *dpll_data; + const char *clkdm_name; + struct clockdomain *clkdm; + const struct clk_hw_omap_ops *ops; +}; + +struct clk_hw_omap_ops { + void (*find_idlest)(struct clk_hw_omap *oclk, + void __iomem **idlest_reg, + u8 *idlest_bit, u8 *idlest_val); + void (*find_companion)(struct clk_hw_omap *oclk, + void __iomem **other_reg, + u8 *other_bit); + void (*allow_idle)(struct clk_hw_omap *oclk); + void (*deny_idle)(struct clk_hw_omap *oclk); +}; + +unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, + unsigned long parent_rate); /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ #define CORE_CLK_SRC_32K 0x0 @@ -49,84 +352,62 @@ /* DPLL Type and DCO Selection Flags */ #define DPLL_J_TYPE 0x1 -int omap2_clk_enable(struct clk *clk); -void omap2_clk_disable(struct clk *clk); -long omap2_clk_round_rate(struct clk *clk, unsigned long rate); -int omap2_clk_set_rate(struct clk *clk, unsigned long rate); -int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); -long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); -unsigned long omap3_dpll_recalc(struct clk *clk); -unsigned long omap3_clkoutx2_recalc(struct clk *clk); -void omap3_dpll_allow_idle(struct clk *clk); -void omap3_dpll_deny_idle(struct clk *clk); -u32 omap3_dpll_autoidle_read(struct clk *clk); -int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); -int omap3_noncore_dpll_enable(struct clk *clk); -void omap3_noncore_dpll_disable(struct clk *clk); -int omap4_dpllmx_gatectrl_read(struct clk *clk); -void omap4_dpllmx_allow_gatectrl(struct clk *clk); -void omap4_dpllmx_deny_gatectrl(struct clk *clk); -long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate); -unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk); - -#ifdef CONFIG_OMAP_RESET_CLOCKS -void omap2_clk_disable_unused(struct clk *clk); -#else -#define omap2_clk_disable_unused NULL -#endif +long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, + unsigned long *parent_rate); +unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); +int omap3_noncore_dpll_enable(struct clk_hw *hw); +void omap3_noncore_dpll_disable(struct clk_hw *hw); +int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate); +u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); +void omap3_dpll_allow_idle(struct clk_hw_omap *clk); +void omap3_dpll_deny_idle(struct clk_hw_omap *clk); +unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, + unsigned long parent_rate); +int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk); +void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk); +void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk); +unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, + unsigned long parent_rate); +long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, + unsigned long target_rate, + unsigned long *parent_rate); -void omap2_init_clk_clkdm(struct clk *clk); +void omap2_init_clk_clkdm(struct clk_hw *clk); void __init omap2_clk_disable_clkdm_control(void); /* clkt_clksel.c public functions */ -u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, +u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, + unsigned long target_rate, u32 *new_div); -void omap2_init_clksel_parent(struct clk *clk); -unsigned long omap2_clksel_recalc(struct clk *clk); -long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); -int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); -int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); +u8 omap2_clksel_find_parent_index(struct clk_hw *hw); +unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate); +long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, + unsigned long *parent_rate); +int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate); +int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val); /* clkt_iclk.c public functions */ -extern void omap2_clkt_iclk_allow_idle(struct clk *clk); -extern void omap2_clkt_iclk_deny_idle(struct clk *clk); - -u32 omap2_get_dpll_rate(struct clk *clk); -void omap2_init_dpll_parent(struct clk *clk); +extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); +extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); -int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); - - -#ifdef CONFIG_ARCH_OMAP2 -void omap2xxx_clk_prepare_for_reboot(void); -#else -static inline void omap2xxx_clk_prepare_for_reboot(void) -{ -} -#endif +u8 omap2_init_dpll_parent(struct clk_hw *hw); +unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); -#ifdef CONFIG_ARCH_OMAP3 -void omap3_clk_prepare_for_reboot(void); -#else -static inline void omap3_clk_prepare_for_reboot(void) -{ -} -#endif - -#ifdef CONFIG_ARCH_OMAP4 -void omap4_clk_prepare_for_reboot(void); -#else -static inline void omap4_clk_prepare_for_reboot(void) -{ -} -#endif - -int omap2_dflt_clk_enable(struct clk *clk); -void omap2_dflt_clk_disable(struct clk *clk); -void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, +int omap2_dflt_clk_enable(struct clk_hw *hw); +void omap2_dflt_clk_disable(struct clk_hw *hw); +int omap2_dflt_clk_is_enabled(struct clk_hw *hw); +void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, + void __iomem **other_reg, u8 *other_bit); -void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, +void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, + void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val); +void omap2_init_clk_hw_omap_clocks(struct clk *clk); +int omap2_clk_enable_autoidle_all(void); +int omap2_clk_disable_autoidle_all(void); +void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, @@ -139,34 +420,43 @@ extern const struct clkops clkops_dummy; extern const struct clkops clkops_omap2_dflt; extern struct clk_functions omap2_clk_functions; -extern struct clk *vclk, *sclk; extern const struct clksel_rate gpt_32k_rates[]; extern const struct clksel_rate gpt_sys_rates[]; extern const struct clksel_rate gfx_l3_rates[]; extern const struct clksel_rate dsp_ick_rates[]; +extern struct clk dummy_ck; -extern const struct clkops clkops_omap2_iclk_dflt_wait; -extern const struct clkops clkops_omap2_iclk_dflt; -extern const struct clkops clkops_omap2_iclk_idle_only; -extern const struct clkops clkops_omap2_mdmclk_dflt_wait; -extern const struct clkops clkops_omap2xxx_dpll_ops; -extern const struct clkops clkops_omap3_noncore_dpll_ops; -extern const struct clkops clkops_omap3_core_dpll_ops; -extern const struct clkops clkops_omap4_dpllmx_ops; +extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; +extern const struct clk_hw_omap_ops clkhwops_iclk_wait; +extern const struct clk_hw_omap_ops clkhwops_wait; +extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; +extern const struct clk_hw_omap_ops clkhwops_iclk; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait; +extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; +extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; +extern const struct clk_hw_omap_ops clkhwops_apll54; +extern const struct clk_hw_omap_ops clkhwops_apll96; +extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; +extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; /* clksel_rate blocks shared between OMAP44xx and AM33xx */ extern const struct clksel_rate div_1_0_rates[]; +extern const struct clksel_rate div3_1to4_rates[]; extern const struct clksel_rate div_1_1_rates[]; extern const struct clksel_rate div_1_2_rates[]; extern const struct clksel_rate div_1_3_rates[]; extern const struct clksel_rate div_1_4_rates[]; extern const struct clksel_rate div31_1to31_rates[]; -/* clocks shared between various OMAP SoCs */ -extern struct clk virt_19200000_ck; -extern struct clk virt_26000000_ck; - extern int am33xx_clk_init(void); +extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); +extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); + #endif diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c deleted file mode 100644 index c3cde1a2b6de..000000000000 --- a/arch/arm/mach-omap2/clock2420_data.c +++ /dev/null @@ -1,1990 +0,0 @@ -/* - * OMAP2420 clock data - * - * Copyright (C) 2005-2009 Texas Instruments, Inc. - * Copyright (C) 2004-2011 Nokia Corporation - * - * Contacts: - * Richard Woodruff <r-woodruff2@ti.com> - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/clk.h> -#include <linux/list.h> - -#include <plat/clkdev_omap.h> - -#include "soc.h" -#include "iomap.h" -#include "clock.h" -#include "clock2xxx.h" -#include "opp2xxx.h" -#include "cm2xxx_3xxx.h" -#include "prm2xxx_3xxx.h" -#include "prm-regbits-24xx.h" -#include "cm-regbits-24xx.h" -#include "sdrc.h" -#include "control.h" - -#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR - -/* - * 2420 clock tree. - * - * NOTE:In many cases here we are assigning a 'default' parent. In - * many cases the parent is selectable. The set parent calls will - * also switch sources. - * - * Several sources are given initial rates which may be wrong, this will - * be fixed up in the init func. - * - * Things are broadly separated below by clock domains. It is - * noteworthy that most peripherals have dependencies on multiple clock - * domains. Many get their interface clocks from the L4 domain, but get - * functional clocks from fixed sources or other core domain derived - * clocks. - */ - -/* Base external input clocks */ -static struct clk func_32k_ck = { - .name = "func_32k_ck", - .ops = &clkops_null, - .rate = 32768, - .clkdm_name = "wkup_clkdm", -}; - -static struct clk secure_32k_ck = { - .name = "secure_32k_ck", - .ops = &clkops_null, - .rate = 32768, - .clkdm_name = "wkup_clkdm", -}; - -/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ -static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ - .name = "osc_ck", - .ops = &clkops_oscck, - .clkdm_name = "wkup_clkdm", - .recalc = &omap2_osc_clk_recalc, -}; - -/* Without modem likely 12MHz, with modem likely 13MHz */ -static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ - .name = "sys_ck", /* ~ ref_clk also */ - .ops = &clkops_null, - .parent = &osc_ck, - .clkdm_name = "wkup_clkdm", - .recalc = &omap2xxx_sys_clk_recalc, -}; - -static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ - .name = "alt_ck", - .ops = &clkops_null, - .rate = 54000000, - .clkdm_name = "wkup_clkdm", -}; - -/* Optional external clock input for McBSP CLKS */ -static struct clk mcbsp_clks = { - .name = "mcbsp_clks", - .ops = &clkops_null, -}; - -/* - * Analog domain root source clocks - */ - -/* dpll_ck, is broken out in to special cases through clksel */ -/* REVISIT: Rate changes on dpll_ck trigger a full set change. ... - * deal with this - */ - -static struct dpll_data dpll_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .mult_mask = OMAP24XX_DPLL_MULT_MASK, - .div1_mask = OMAP24XX_DPLL_DIV_MASK, - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_mask = OMAP24XX_EN_DPLL_MASK, - .max_multiplier = 1023, - .min_divider = 1, - .max_divider = 16, -}; - -/* - * XXX Cannot add round_rate here yet, as this is still a composite clock, - * not just a DPLL - */ -static struct clk dpll_ck = { - .name = "dpll_ck", - .ops = &clkops_omap2xxx_dpll_ops, - .parent = &sys_ck, /* Can be func_32k also */ - .dpll_data = &dpll_dd, - .clkdm_name = "wkup_clkdm", - .recalc = &omap2_dpllcore_recalc, - .set_rate = &omap2_reprogram_dpllcore, -}; - -static struct clk apll96_ck = { - .name = "apll96_ck", - .ops = &clkops_apll96, - .parent = &sys_ck, - .rate = 96000000, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, -}; - -static struct clk apll54_ck = { - .name = "apll54_ck", - .ops = &clkops_apll54, - .parent = &sys_ck, - .rate = 54000000, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, -}; - -/* - * PRCM digital base sources - */ - -/* func_54m_ck */ - -static const struct clksel_rate func_54m_apll54_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 }, -}; - -static const struct clksel_rate func_54m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 }, -}; - -static const struct clksel func_54m_clksel[] = { - { .parent = &apll54_ck, .rates = func_54m_apll54_rates, }, - { .parent = &alt_ck, .rates = func_54m_alt_rates, }, - { .parent = NULL }, -}; - -static struct clk func_54m_ck = { - .name = "func_54m_ck", - .ops = &clkops_null, - .parent = &apll54_ck, /* can also be alt_clk */ - .clkdm_name = "wkup_clkdm", - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_54M_SOURCE_MASK, - .clksel = func_54m_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk core_ck = { - .name = "core_ck", - .ops = &clkops_null, - .parent = &dpll_ck, /* can also be 32k */ - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk func_96m_ck = { - .name = "func_96m_ck", - .ops = &clkops_null, - .parent = &apll96_ck, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -/* func_48m_ck */ - -static const struct clksel_rate func_48m_apll96_rates[] = { - { .div = 2, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 }, -}; - -static const struct clksel_rate func_48m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 }, -}; - -static const struct clksel func_48m_clksel[] = { - { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, - { .parent = &alt_ck, .rates = func_48m_alt_rates }, - { .parent = NULL } -}; - -static struct clk func_48m_ck = { - .name = "func_48m_ck", - .ops = &clkops_null, - .parent = &apll96_ck, /* 96M or Alt */ - .clkdm_name = "wkup_clkdm", - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_48M_SOURCE_MASK, - .clksel = func_48m_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -static struct clk func_12m_ck = { - .name = "func_12m_ck", - .ops = &clkops_null, - .parent = &func_48m_ck, - .fixed_div = 4, - .clkdm_name = "wkup_clkdm", - .recalc = &omap_fixed_divisor_recalc, -}; - -/* Secure timer, only available in secure mode */ -static struct clk wdt1_osc_ck = { - .name = "ck_wdt1_osc", - .ops = &clkops_null, /* RMK: missing? */ - .parent = &osc_ck, - .recalc = &followparent_recalc, -}; - -/* - * The common_clkout* clksel_rate structs are common to - * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src. - * sys_clkout2_* are 2420-only, so the - * clksel_rate flags fields are inaccurate for those clocks. This is - * harmless since access to those clocks are gated by the struct clk - * flags fields, which mark them as 2420-only. - */ -static const struct clksel_rate common_clkout_src_core_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_96m_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_54m_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel common_clkout_src_clksel[] = { - { .parent = &core_ck, .rates = common_clkout_src_core_rates }, - { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, - { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, - { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, - { .parent = NULL } -}; - -static struct clk sys_clkout_src = { - .name = "sys_clkout_src", - .ops = &clkops_omap2_dflt, - .parent = &func_54m_ck, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL, - .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, - .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, - .clksel = common_clkout_src_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -static const struct clksel_rate common_clkout_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 2, .val = 1, .flags = RATE_IN_24XX }, - { .div = 4, .val = 2, .flags = RATE_IN_24XX }, - { .div = 8, .val = 3, .flags = RATE_IN_24XX }, - { .div = 16, .val = 4, .flags = RATE_IN_24XX }, - { .div = 0 }, -}; - -static const struct clksel sys_clkout_clksel[] = { - { .parent = &sys_clkout_src, .rates = common_clkout_rates }, - { .parent = NULL } -}; - -static struct clk sys_clkout = { - .name = "sys_clkout", - .ops = &clkops_null, - .parent = &sys_clkout_src, - .clkdm_name = "wkup_clkdm", - .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, - .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, - .clksel = sys_clkout_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -/* In 2430, new in 2420 ES2 */ -static struct clk sys_clkout2_src = { - .name = "sys_clkout2_src", - .ops = &clkops_omap2_dflt, - .parent = &func_54m_ck, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL, - .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, - .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK, - .clksel = common_clkout_src_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -static const struct clksel sys_clkout2_clksel[] = { - { .parent = &sys_clkout2_src, .rates = common_clkout_rates }, - { .parent = NULL } -}; - -/* In 2430, new in 2420 ES2 */ -static struct clk sys_clkout2 = { - .name = "sys_clkout2", - .ops = &clkops_null, - .parent = &sys_clkout2_src, - .clkdm_name = "wkup_clkdm", - .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL, - .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, - .clksel = sys_clkout2_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -static struct clk emul_ck = { - .name = "emul_ck", - .ops = &clkops_omap2_dflt, - .parent = &func_54m_ck, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL, - .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, - .recalc = &followparent_recalc, - -}; - -/* - * MPU clock domain - * Clocks: - * MPU_FCLK, MPU_ICLK - * INT_M_FCLK, INT_M_I_CLK - * - * - Individual clocks are hardware managed. - * - Base divider comes from: CM_CLKSEL_MPU - * - */ -static const struct clksel_rate mpu_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_242X }, - { .div = 6, .val = 6, .flags = RATE_IN_242X }, - { .div = 8, .val = 8, .flags = RATE_IN_242X }, - { .div = 0 }, -}; - -static const struct clksel mpu_clksel[] = { - { .parent = &core_ck, .rates = mpu_core_rates }, - { .parent = NULL } -}; - -static struct clk mpu_ck = { /* Control cpu */ - .name = "mpu_ck", - .ops = &clkops_null, - .parent = &core_ck, - .clkdm_name = "mpu_clkdm", - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), - .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, - .clksel = mpu_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* - * DSP (2420-UMA+IVA1) clock domain - * Clocks: - * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP - * - * Won't be too specific here. The core clock comes into this block - * it is divided then tee'ed. One branch goes directly to xyz enable - * controls. The other branch gets further divided by 2 then possibly - * routed into a synchronizer and out of clocks abc. - */ -static const struct clksel_rate dsp_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 6, .val = 6, .flags = RATE_IN_242X }, - { .div = 8, .val = 8, .flags = RATE_IN_242X }, - { .div = 12, .val = 12, .flags = RATE_IN_242X }, - { .div = 0 }, -}; - -static const struct clksel dsp_fck_clksel[] = { - { .parent = &core_ck, .rates = dsp_fck_core_rates }, - { .parent = NULL } -}; - -static struct clk dsp_fck = { - .name = "dsp_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_ck, - .clkdm_name = "dsp_clkdm", - .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, - .clksel = dsp_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel dsp_ick_clksel[] = { - { .parent = &dsp_fck, .rates = dsp_ick_rates }, - { .parent = NULL } -}; - -static struct clk dsp_ick = { - .name = "dsp_ick", /* apparently ipi and isp */ - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &dsp_fck, - .clkdm_name = "dsp_clkdm", - .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), - .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ - .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, - .clksel = dsp_ick_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* - * The IVA1 is an ARM7 core on the 2420 that has nothing to do with - * the C54x, but which is contained in the DSP powerdomain. Does not - * exist on later OMAPs. - */ -static struct clk iva1_ifck = { - .name = "iva1_ifck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_ck, - .clkdm_name = "iva1_clkdm", - .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - .clksel_mask = OMAP2420_CLKSEL_IVA_MASK, - .clksel = dsp_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* IVA1 mpu/int/i/f clocks are /2 of parent */ -static struct clk iva1_mpu_int_ifck = { - .name = "iva1_mpu_int_ifck", - .ops = &clkops_omap2_dflt_wait, - .parent = &iva1_ifck, - .clkdm_name = "iva1_clkdm", - .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; - -/* - * L3 clock domain - * L3 clocks are used for both interface and functional clocks to - * multiple entities. Some of these clocks are completely managed - * by hardware, and some others allow software control. Hardware - * managed ones general are based on directly CLK_REQ signals and - * various auto idle settings. The functional spec sets many of these - * as 'tie-high' for their enables. - * - * I-CLOCKS: - * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA - * CAM, HS-USB. - * F-CLOCK - * SSI. - * - * GPMC memories and SDRC have timing and clock sensitive registers which - * may very well need notification when the clock changes. Currently for low - * operating points, these are taken care of in sleep.S. - */ -static const struct clksel_rate core_l3_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_242X }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 6, .val = 6, .flags = RATE_IN_24XX }, - { .div = 8, .val = 8, .flags = RATE_IN_242X }, - { .div = 12, .val = 12, .flags = RATE_IN_242X }, - { .div = 16, .val = 16, .flags = RATE_IN_242X }, - { .div = 0 } -}; - -static const struct clksel core_l3_clksel[] = { - { .parent = &core_ck, .rates = core_l3_core_rates }, - { .parent = NULL } -}; - -static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ - .name = "core_l3_ck", - .ops = &clkops_null, - .parent = &core_ck, - .clkdm_name = "core_l3_clkdm", - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, - .clksel = core_l3_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* usb_l4_ick */ -static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel usb_l4_ick_clksel[] = { - { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, - { .parent = NULL }, -}; - -/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ -static struct clk usb_l4_ick = { /* FS-USB interface clock */ - .name = "usb_l4_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l3_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP24XX_EN_USB_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, - .clksel = usb_l4_ick_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* - * L4 clock management domain - * - * This domain contains lots of interface clocks from the L4 interface, some - * functional clocks. Fixed APLL functional source clocks are managed in - * this domain. - */ -static const struct clksel_rate l4_core_l3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel l4_clksel[] = { - { .parent = &core_l3_ck, .rates = l4_core_l3_rates }, - { .parent = NULL } -}; - -static struct clk l4_ck = { /* used both as an ick and fck */ - .name = "l4_ck", - .ops = &clkops_null, - .parent = &core_l3_ck, - .clkdm_name = "core_l4_clkdm", - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, - .clksel = l4_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* - * SSI is in L3 management domain, its direct parent is core not l3, - * many core power domain entities are grouped into the L3 clock - * domain. - * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK - * - * ssr = core/1/2/3/4/5, sst = 1/2 ssr. - */ -static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 6, .val = 6, .flags = RATE_IN_242X }, - { .div = 8, .val = 8, .flags = RATE_IN_242X }, - { .div = 0 } -}; - -static const struct clksel ssi_ssr_sst_fck_clksel[] = { - { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, - { .parent = NULL } -}; - -static struct clk ssi_ssr_sst_fck = { - .name = "ssi_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_ck, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP24XX_EN_SSI_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, - .clksel = ssi_ssr_sst_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* - * Presumably this is the same as SSI_ICLK. - * TRM contradicts itself on what clockdomain SSI_ICLK is in - */ -static struct clk ssi_l4_ick = { - .name = "ssi_l4_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP24XX_EN_SSI_SHIFT, - .recalc = &followparent_recalc, -}; - - -/* - * GFX clock domain - * Clocks: - * GFX_FCLK, GFX_ICLK - * GFX_CG1(2d), GFX_CG2(3d) - * - * GFX_FCLK runs from L3, and is divided by (1,2,3,4) - * The 2d and 3d clocks run at a hardware determined - * divided value of fclk. - * - */ - -/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ -static const struct clksel gfx_fck_clksel[] = { - { .parent = &core_l3_ck, .rates = gfx_l3_rates }, - { .parent = NULL }, -}; - -static struct clk gfx_3d_fck = { - .name = "gfx_3d_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l3_ck, - .clkdm_name = "gfx_clkdm", - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_3D_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), - .clksel_mask = OMAP_CLKSEL_GFX_MASK, - .clksel = gfx_fck_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -static struct clk gfx_2d_fck = { - .name = "gfx_2d_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l3_ck, - .clkdm_name = "gfx_clkdm", - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_2D_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), - .clksel_mask = OMAP_CLKSEL_GFX_MASK, - .clksel = gfx_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* This interface clock does not have a CM_AUTOIDLE bit */ -static struct clk gfx_ick = { - .name = "gfx_ick", /* From l3 */ - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l3_ck, - .clkdm_name = "gfx_clkdm", - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), - .enable_bit = OMAP_EN_GFX_SHIFT, - .recalc = &followparent_recalc, -}; - -/* - * DSS clock domain - * CLOCKs: - * DSS_L4_ICLK, DSS_L3_ICLK, - * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK - * - * DSS is both initiator and target. - */ -/* XXX Add RATE_NOT_VALIDATED */ - -static const struct clksel_rate dss1_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate dss1_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 5, .val = 5, .flags = RATE_IN_24XX }, - { .div = 6, .val = 6, .flags = RATE_IN_24XX }, - { .div = 8, .val = 8, .flags = RATE_IN_24XX }, - { .div = 9, .val = 9, .flags = RATE_IN_24XX }, - { .div = 12, .val = 12, .flags = RATE_IN_24XX }, - { .div = 16, .val = 16, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel dss1_fck_clksel[] = { - { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, - { .parent = &core_ck, .rates = dss1_fck_core_rates }, - { .parent = NULL }, -}; - -static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ - .name = "dss_ick", - .ops = &clkops_omap2_iclk_dflt, - .parent = &l4_ck, /* really both l3 and l4 */ - .clkdm_name = "dss_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_DSS1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk dss1_fck = { - .name = "dss1_fck", - .ops = &clkops_omap2_dflt, - .parent = &core_ck, /* Core or sys */ - .clkdm_name = "dss_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_DSS1_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, - .clksel = dss1_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate dss2_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate dss2_fck_48m_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel dss2_fck_clksel[] = { - { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, - { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, - { .parent = NULL } -}; - -static struct clk dss2_fck = { /* Alt clk used in power management */ - .name = "dss2_fck", - .ops = &clkops_omap2_dflt, - .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ - .clkdm_name = "dss_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_DSS2_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, - .clksel = dss2_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk dss_54m_fck = { /* Alt clk used in power management */ - .name = "dss_54m_fck", /* 54m tv clk */ - .ops = &clkops_omap2_dflt_wait, - .parent = &func_54m_ck, - .clkdm_name = "dss_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_TV_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk wu_l4_ick = { - .name = "wu_l4_ick", - .ops = &clkops_null, - .parent = &sys_ck, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -/* - * CORE power domain ICLK & FCLK defines. - * Many of the these can have more than one possible parent. Entries - * here will likely have an L4 interface parent, and may have multiple - * functional clock parents. - */ -static const struct clksel_rate gpt_alt_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel omap24xx_gpt_clksel[] = { - { .parent = &func_32k_ck, .rates = gpt_32k_rates }, - { .parent = &sys_ck, .rates = gpt_sys_rates }, - { .parent = &alt_ck, .rates = gpt_alt_rates }, - { .parent = NULL }, -}; - -static struct clk gpt1_ick = { - .name = "gpt1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wu_l4_ick, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_GPT1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt1_fck = { - .name = "gpt1_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_GPT1_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -static struct clk gpt2_ick = { - .name = "gpt2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt2_fck = { - .name = "gpt2_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT2_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt3_ick = { - .name = "gpt3_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT3_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt3_fck = { - .name = "gpt3_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT3_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt4_ick = { - .name = "gpt4_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT4_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt4_fck = { - .name = "gpt4_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT4_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt5_ick = { - .name = "gpt5_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT5_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt5_fck = { - .name = "gpt5_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT5_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt6_ick = { - .name = "gpt6_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT6_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt6_fck = { - .name = "gpt6_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT6_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt7_ick = { - .name = "gpt7_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT7_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt7_fck = { - .name = "gpt7_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT7_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt8_ick = { - .name = "gpt8_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT8_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt8_fck = { - .name = "gpt8_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT8_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt9_ick = { - .name = "gpt9_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT9_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt9_fck = { - .name = "gpt9_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT9_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt10_ick = { - .name = "gpt10_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT10_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt10_fck = { - .name = "gpt10_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT10_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt11_ick = { - .name = "gpt11_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT11_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt11_fck = { - .name = "gpt11_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT11_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt12_ick = { - .name = "gpt12_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT12_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt12_fck = { - .name = "gpt12_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &secure_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT12_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp1_ick = { - .name = "mcbsp1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .recalc = &followparent_recalc, -}; - -static const struct clksel_rate common_mcbsp_96m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel mcbsp_fck_clksel[] = { - { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, - { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, - { .parent = NULL } -}; - -static struct clk mcbsp1_fck = { - .name = "mcbsp1_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .init = &omap2_init_clksel_parent, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, - .clksel = mcbsp_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp2_ick = { - .name = "mcbsp2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp2_fck = { - .name = "mcbsp2_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .init = &omap2_init_clksel_parent, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, - .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, - .clksel = mcbsp_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcspi1_ick = { - .name = "mcspi1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi1_fck = { - .name = "mcspi1_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_48m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi2_ick = { - .name = "mcspi2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi2_fck = { - .name = "mcspi2_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_48m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk uart1_ick = { - .name = "uart1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_UART1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk uart1_fck = { - .name = "uart1_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_48m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_UART1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk uart2_ick = { - .name = "uart2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_UART2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk uart2_fck = { - .name = "uart2_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_48m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_UART2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk uart3_ick = { - .name = "uart3_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP24XX_EN_UART3_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk uart3_fck = { - .name = "uart3_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_48m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP24XX_EN_UART3_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpios_ick = { - .name = "gpios_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wu_l4_ick, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpios_fck = { - .name = "gpios_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mpu_wdt_ick = { - .name = "mpu_wdt_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wu_l4_ick, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mpu_wdt_fck = { - .name = "mpu_wdt_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk sync_32k_ick = { - .name = "sync_32k_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wu_l4_ick, - .clkdm_name = "wkup_clkdm", - .flags = ENABLE_ON_INIT, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk wdt1_ick = { - .name = "wdt1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wu_l4_ick, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_WDT1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk omapctrl_ick = { - .name = "omapctrl_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wu_l4_ick, - .clkdm_name = "wkup_clkdm", - .flags = ENABLE_ON_INIT, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk cam_ick = { - .name = "cam_ick", - .ops = &clkops_omap2_iclk_dflt, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_CAM_SHIFT, - .recalc = &followparent_recalc, -}; - -/* - * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be - * split into two separate clocks, since the parent clocks are different - * and the clockdomains are also different. - */ -static struct clk cam_fck = { - .name = "cam_fck", - .ops = &clkops_omap2_dflt, - .parent = &func_96m_ck, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_CAM_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mailboxes_ick = { - .name = "mailboxes_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk wdt4_ick = { - .name = "wdt4_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_WDT4_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk wdt4_fck = { - .name = "wdt4_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_WDT4_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk wdt3_ick = { - .name = "wdt3_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_WDT3_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk wdt3_fck = { - .name = "wdt3_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_WDT3_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mspro_ick = { - .name = "mspro_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mspro_fck = { - .name = "mspro_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mmc_ick = { - .name = "mmc_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_MMC_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mmc_fck = { - .name = "mmc_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_MMC_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk fac_ick = { - .name = "fac_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_FAC_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk fac_fck = { - .name = "fac_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_12m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_FAC_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk eac_ick = { - .name = "eac_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_EAC_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk eac_fck = { - .name = "eac_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_EAC_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk hdq_ick = { - .name = "hdq_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_HDQ_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk hdq_fck = { - .name = "hdq_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_12m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_HDQ_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk i2c2_ick = { - .name = "i2c2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_I2C2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk i2c2_fck = { - .name = "i2c2_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_12m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_I2C2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk i2c1_ick = { - .name = "i2c1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_I2C1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk i2c1_fck = { - .name = "i2c1_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_12m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_I2C1_SHIFT, - .recalc = &followparent_recalc, -}; - -/* - * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE - * accesses derived from this data. - */ -static struct clk gpmc_fck = { - .name = "gpmc_fck", - .ops = &clkops_omap2_iclk_idle_only, - .parent = &core_l3_ck, - .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk sdma_fck = { - .name = "sdma_fck", - .ops = &clkops_null, /* RMK: missing? */ - .parent = &core_l3_ck, - .clkdm_name = "core_l3_clkdm", - .recalc = &followparent_recalc, -}; - -/* - * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE - * accesses derived from this data. - */ -static struct clk sdma_ick = { - .name = "sdma_ick", - .ops = &clkops_omap2_iclk_idle_only, - .parent = &core_l3_ck, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, - .recalc = &followparent_recalc, -}; - -/* - * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE - * accesses derived from this data. - */ -static struct clk sdrc_ick = { - .name = "sdrc_ick", - .ops = &clkops_omap2_iclk_idle_only, - .parent = &core_l3_ck, - .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk vlynq_ick = { - .name = "vlynq_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l3_ck, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, - .recalc = &followparent_recalc, -}; - -static const struct clksel_rate vlynq_fck_96m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_242X }, - { .div = 0 } -}; - -static const struct clksel_rate vlynq_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_242X }, - { .div = 2, .val = 2, .flags = RATE_IN_242X }, - { .div = 3, .val = 3, .flags = RATE_IN_242X }, - { .div = 4, .val = 4, .flags = RATE_IN_242X }, - { .div = 6, .val = 6, .flags = RATE_IN_242X }, - { .div = 8, .val = 8, .flags = RATE_IN_242X }, - { .div = 9, .val = 9, .flags = RATE_IN_242X }, - { .div = 12, .val = 12, .flags = RATE_IN_242X }, - { .div = 16, .val = 16, .flags = RATE_IN_242X }, - { .div = 18, .val = 18, .flags = RATE_IN_242X }, - { .div = 0 } -}; - -static const struct clksel vlynq_fck_clksel[] = { - { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, - { .parent = &core_ck, .rates = vlynq_fck_core_rates }, - { .parent = NULL } -}; - -static struct clk vlynq_fck = { - .name = "vlynq_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK, - .clksel = vlynq_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk des_ick = { - .name = "des_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_DES_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk sha_ick = { - .name = "sha_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_SHA_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk rng_ick = { - .name = "rng_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_RNG_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk aes_ick = { - .name = "aes_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_AES_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk pka_ick = { - .name = "pka_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_PKA_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk usb_fck = { - .name = "usb_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_48m_ck, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP24XX_EN_USB_SHIFT, - .recalc = &followparent_recalc, -}; - -/* - * This clock is a composite clock which does entire set changes then - * forces a rebalance. It keys on the MPU speed, but it really could - * be any key speed part of a set in the rate table. - * - * to really change a set, you need memory table sets which get changed - * in sram, pre-notifiers & post notifiers, changing the top set, without - * having low level display recalc's won't work... this is why dpm notifiers - * work, isr's off, walk a list of clocks already _off_ and not messing with - * the bus. - * - * This clock should have no parent. It embodies the entire upper level - * active set. A parent will mess up some of the init also. - */ -static struct clk virt_prcm_set = { - .name = "virt_prcm_set", - .ops = &clkops_null, - .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ - .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ - .set_rate = &omap2_select_table_rate, - .round_rate = &omap2_round_to_table_rate, -}; - - -/* - * clkdev integration - */ - -static struct omap_clk omap2420_clks[] = { - /* external root sources */ - CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X), - CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X), - CLK(NULL, "osc_ck", &osc_ck, CK_242X), - CLK(NULL, "sys_ck", &sys_ck, CK_242X), - CLK(NULL, "alt_ck", &alt_ck, CK_242X), - CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X), - /* internal analog sources */ - CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), - CLK(NULL, "apll96_ck", &apll96_ck, CK_242X), - CLK(NULL, "apll54_ck", &apll54_ck, CK_242X), - /* internal prcm root sources */ - CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), - CLK(NULL, "core_ck", &core_ck, CK_242X), - CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), - CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), - CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), - CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X), - CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X), - CLK(NULL, "sys_clkout", &sys_clkout, CK_242X), - CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), - CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), - CLK(NULL, "emul_ck", &emul_ck, CK_242X), - /* mpu domain clocks */ - CLK(NULL, "mpu_ck", &mpu_ck, CK_242X), - /* dsp domain clocks */ - CLK(NULL, "dsp_fck", &dsp_fck, CK_242X), - CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), - CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), - CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), - /* GFX domain clocks */ - CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X), - CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), - CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), - /* DSS domain clocks */ - CLK("omapdss_dss", "ick", &dss_ick, CK_242X), - CLK(NULL, "dss_ick", &dss_ick, CK_242X), - CLK(NULL, "dss1_fck", &dss1_fck, CK_242X), - CLK(NULL, "dss2_fck", &dss2_fck, CK_242X), - CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X), - /* L3 domain clocks */ - CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), - CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), - CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X), - /* L4 domain clocks */ - CLK(NULL, "l4_ck", &l4_ck, CK_242X), - CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X), - CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X), - /* virtual meta-group clock */ - CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), - /* general l4 interface ck, multi-parent functional clk */ - CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X), - CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X), - CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X), - CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X), - CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X), - CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X), - CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X), - CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X), - CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X), - CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X), - CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X), - CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X), - CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X), - CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X), - CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X), - CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X), - CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X), - CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X), - CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X), - CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X), - CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X), - CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X), - CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), - CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), - CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), - CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X), - CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X), - CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), - CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X), - CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X), - CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), - CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X), - CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X), - CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), - CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X), - CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X), - CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), - CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), - CLK(NULL, "uart2_ick", &uart2_ick, CK_242X), - CLK(NULL, "uart2_fck", &uart2_fck, CK_242X), - CLK(NULL, "uart3_ick", &uart3_ick, CK_242X), - CLK(NULL, "uart3_fck", &uart3_fck, CK_242X), - CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), - CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), - CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), - CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X), - CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X), - CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), - CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), - CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), - CLK("omap24xxcam", "fck", &cam_fck, CK_242X), - CLK(NULL, "cam_fck", &cam_fck, CK_242X), - CLK("omap24xxcam", "ick", &cam_ick, CK_242X), - CLK(NULL, "cam_ick", &cam_ick, CK_242X), - CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X), - CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X), - CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X), - CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), - CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), - CLK(NULL, "mspro_ick", &mspro_ick, CK_242X), - CLK(NULL, "mspro_fck", &mspro_fck, CK_242X), - CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), - CLK(NULL, "mmc_ick", &mmc_ick, CK_242X), - CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), - CLK(NULL, "mmc_fck", &mmc_fck, CK_242X), - CLK(NULL, "fac_ick", &fac_ick, CK_242X), - CLK(NULL, "fac_fck", &fac_fck, CK_242X), - CLK(NULL, "eac_ick", &eac_ick, CK_242X), - CLK(NULL, "eac_fck", &eac_fck, CK_242X), - CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), - CLK(NULL, "hdq_ick", &hdq_ick, CK_242X), - CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X), - CLK(NULL, "hdq_fck", &hdq_fck, CK_242X), - CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X), - CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X), - CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X), - CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X), - CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X), - CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X), - CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), - CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), - CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), - CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X), - CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), - CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), - CLK(NULL, "des_ick", &des_ick, CK_242X), - CLK("omap-sham", "ick", &sha_ick, CK_242X), - CLK(NULL, "sha_ick", &sha_ick, CK_242X), - CLK("omap_rng", "ick", &rng_ick, CK_242X), - CLK(NULL, "rng_ick", &rng_ick, CK_242X), - CLK("omap-aes", "ick", &aes_ick, CK_242X), - CLK(NULL, "aes_ick", &aes_ick, CK_242X), - CLK(NULL, "pka_ick", &pka_ick, CK_242X), - CLK(NULL, "usb_fck", &usb_fck, CK_242X), - CLK("musb-hdrc", "fck", &osc_ck, CK_242X), - CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X), - CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X), - CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X), - CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X), -}; - -/* - * init code - */ - -int __init omap2420_clk_init(void) -{ - const struct prcm_config *prcm; - struct omap_clk *c; - u32 clkrate; - - prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; - cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST); - cpu_mask = RATE_IN_242X; - rate_table = omap2420_rate_table; - - clk_init(&omap2_clk_functions); - - for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); - c++) - clk_preinit(c->lk.clk); - - osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); - propagate_rate(&osc_ck); - sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck); - propagate_rate(&sys_ck); - - for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks); - c++) { - clkdev_add(&c->lk); - clk_register(c->lk.clk); - omap2_init_clk_clkdm(c->lk.clk); - } - - /* Disable autoidle on all clocks; let the PM code enable it later */ - omap_clk_disable_autoidle_all(); - - /* Check the MPU rate set by bootloader */ - clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); - for (prcm = rate_table; prcm->mpu_speed; prcm++) { - if (!(prcm->flags & cpu_mask)) - continue; - if (prcm->xtal_speed != sys_ck.rate) - continue; - if (prcm->dpll_speed <= clkrate) - break; - } - curr_prcm_set = prcm; - - recalculate_root_clocks(); - - pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", - (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, - (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; - - /* - * Only enable those clocks we will need, let the drivers - * enable other clocks as necessary - */ - clk_enable_init_clocks(); - - /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ - vclk = clk_get(NULL, "virt_prcm_set"); - sclk = clk_get(NULL, "sys_ck"); - dclk = clk_get(NULL, "dpll_ck"); - - return 0; -} - diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c index a8e326177466..cef0c8d1de52 100644 --- a/arch/arm/mach-omap2/clock2430.c +++ b/arch/arm/mach-omap2/clock2430.c @@ -21,13 +21,11 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/clock.h> - #include "soc.h" #include "iomap.h" #include "clock.h" #include "clock2xxx.h" -#include "cm2xxx_3xxx.h" +#include "cm2xxx.h" #include "cm-regbits-24xx.h" /** @@ -42,7 +40,7 @@ * passes back the correct CM_IDLEST register address for I2CHS * modules. No return value. */ -static void omap2430_clk_i2chs_find_idlest(struct clk *clk, +static void omap2430_clk_i2chs_find_idlest(struct clk_hw_omap *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) @@ -53,9 +51,7 @@ static void omap2430_clk_i2chs_find_idlest(struct clk *clk, } /* 2430 I2CHS has non-standard IDLEST register */ -const struct clkops clkops_omap2430_i2chs_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, +const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait = { .find_idlest = omap2430_clk_i2chs_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, + .find_companion = omap2_clk_dflt_find_companion, }; diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c deleted file mode 100644 index 22404fe435e7..000000000000 --- a/arch/arm/mach-omap2/clock2430_data.c +++ /dev/null @@ -1,2089 +0,0 @@ -/* - * OMAP2430 clock data - * - * Copyright (C) 2005-2009 Texas Instruments, Inc. - * Copyright (C) 2004-2011 Nokia Corporation - * - * Contacts: - * Richard Woodruff <r-woodruff2@ti.com> - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/clk.h> -#include <linux/list.h> - -#include <plat/clkdev_omap.h> - -#include "soc.h" -#include "iomap.h" -#include "clock.h" -#include "clock2xxx.h" -#include "opp2xxx.h" -#include "cm2xxx_3xxx.h" -#include "prm2xxx_3xxx.h" -#include "prm-regbits-24xx.h" -#include "cm-regbits-24xx.h" -#include "sdrc.h" -#include "control.h" - -#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR - -/* - * 2430 clock tree. - * - * NOTE:In many cases here we are assigning a 'default' parent. In - * many cases the parent is selectable. The set parent calls will - * also switch sources. - * - * Several sources are given initial rates which may be wrong, this will - * be fixed up in the init func. - * - * Things are broadly separated below by clock domains. It is - * noteworthy that most peripherals have dependencies on multiple clock - * domains. Many get their interface clocks from the L4 domain, but get - * functional clocks from fixed sources or other core domain derived - * clocks. - */ - -/* Base external input clocks */ -static struct clk func_32k_ck = { - .name = "func_32k_ck", - .ops = &clkops_null, - .rate = 32768, - .clkdm_name = "wkup_clkdm", -}; - -static struct clk secure_32k_ck = { - .name = "secure_32k_ck", - .ops = &clkops_null, - .rate = 32768, - .clkdm_name = "wkup_clkdm", -}; - -/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ -static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ - .name = "osc_ck", - .ops = &clkops_oscck, - .clkdm_name = "wkup_clkdm", - .recalc = &omap2_osc_clk_recalc, -}; - -/* Without modem likely 12MHz, with modem likely 13MHz */ -static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ - .name = "sys_ck", /* ~ ref_clk also */ - .ops = &clkops_null, - .parent = &osc_ck, - .clkdm_name = "wkup_clkdm", - .recalc = &omap2xxx_sys_clk_recalc, -}; - -static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ - .name = "alt_ck", - .ops = &clkops_null, - .rate = 54000000, - .clkdm_name = "wkup_clkdm", -}; - -/* Optional external clock input for McBSP CLKS */ -static struct clk mcbsp_clks = { - .name = "mcbsp_clks", - .ops = &clkops_null, -}; - -/* - * Analog domain root source clocks - */ - -/* dpll_ck, is broken out in to special cases through clksel */ -/* REVISIT: Rate changes on dpll_ck trigger a full set change. ... - * deal with this - */ - -static struct dpll_data dpll_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .mult_mask = OMAP24XX_DPLL_MULT_MASK, - .div1_mask = OMAP24XX_DPLL_DIV_MASK, - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_mask = OMAP24XX_EN_DPLL_MASK, - .max_multiplier = 1023, - .min_divider = 1, - .max_divider = 16, -}; - -/* - * XXX Cannot add round_rate here yet, as this is still a composite clock, - * not just a DPLL - */ -static struct clk dpll_ck = { - .name = "dpll_ck", - .ops = &clkops_omap2xxx_dpll_ops, - .parent = &sys_ck, /* Can be func_32k also */ - .dpll_data = &dpll_dd, - .clkdm_name = "wkup_clkdm", - .recalc = &omap2_dpllcore_recalc, - .set_rate = &omap2_reprogram_dpllcore, -}; - -static struct clk apll96_ck = { - .name = "apll96_ck", - .ops = &clkops_apll96, - .parent = &sys_ck, - .rate = 96000000, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, -}; - -static struct clk apll54_ck = { - .name = "apll54_ck", - .ops = &clkops_apll54, - .parent = &sys_ck, - .rate = 54000000, - .flags = ENABLE_ON_INIT, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, -}; - -/* - * PRCM digital base sources - */ - -/* func_54m_ck */ - -static const struct clksel_rate func_54m_apll54_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 }, -}; - -static const struct clksel_rate func_54m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 }, -}; - -static const struct clksel func_54m_clksel[] = { - { .parent = &apll54_ck, .rates = func_54m_apll54_rates, }, - { .parent = &alt_ck, .rates = func_54m_alt_rates, }, - { .parent = NULL }, -}; - -static struct clk func_54m_ck = { - .name = "func_54m_ck", - .ops = &clkops_null, - .parent = &apll54_ck, /* can also be alt_clk */ - .clkdm_name = "wkup_clkdm", - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_54M_SOURCE_MASK, - .clksel = func_54m_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk core_ck = { - .name = "core_ck", - .ops = &clkops_null, - .parent = &dpll_ck, /* can also be 32k */ - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -/* func_96m_ck */ -static const struct clksel_rate func_96m_apll96_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 }, -}; - -static const struct clksel_rate func_96m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_243X }, - { .div = 0 }, -}; - -static const struct clksel func_96m_clksel[] = { - { .parent = &apll96_ck, .rates = func_96m_apll96_rates }, - { .parent = &alt_ck, .rates = func_96m_alt_rates }, - { .parent = NULL } -}; - -static struct clk func_96m_ck = { - .name = "func_96m_ck", - .ops = &clkops_null, - .parent = &apll96_ck, - .clkdm_name = "wkup_clkdm", - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP2430_96M_SOURCE_MASK, - .clksel = func_96m_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* func_48m_ck */ - -static const struct clksel_rate func_48m_apll96_rates[] = { - { .div = 2, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 }, -}; - -static const struct clksel_rate func_48m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 }, -}; - -static const struct clksel func_48m_clksel[] = { - { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, - { .parent = &alt_ck, .rates = func_48m_alt_rates }, - { .parent = NULL } -}; - -static struct clk func_48m_ck = { - .name = "func_48m_ck", - .ops = &clkops_null, - .parent = &apll96_ck, /* 96M or Alt */ - .clkdm_name = "wkup_clkdm", - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_48M_SOURCE_MASK, - .clksel = func_48m_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -static struct clk func_12m_ck = { - .name = "func_12m_ck", - .ops = &clkops_null, - .parent = &func_48m_ck, - .fixed_div = 4, - .clkdm_name = "wkup_clkdm", - .recalc = &omap_fixed_divisor_recalc, -}; - -/* Secure timer, only available in secure mode */ -static struct clk wdt1_osc_ck = { - .name = "ck_wdt1_osc", - .ops = &clkops_null, /* RMK: missing? */ - .parent = &osc_ck, - .recalc = &followparent_recalc, -}; - -/* - * The common_clkout* clksel_rate structs are common to - * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src. - * sys_clkout2_* are 2420-only, so the - * clksel_rate flags fields are inaccurate for those clocks. This is - * harmless since access to those clocks are gated by the struct clk - * flags fields, which mark them as 2420-only. - */ -static const struct clksel_rate common_clkout_src_core_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_96m_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_clkout_src_54m_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel common_clkout_src_clksel[] = { - { .parent = &core_ck, .rates = common_clkout_src_core_rates }, - { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, - { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, - { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, - { .parent = NULL } -}; - -static struct clk sys_clkout_src = { - .name = "sys_clkout_src", - .ops = &clkops_omap2_dflt, - .parent = &func_54m_ck, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP2430_PRCM_CLKOUT_CTRL, - .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL, - .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK, - .clksel = common_clkout_src_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -static const struct clksel_rate common_clkout_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 2, .val = 1, .flags = RATE_IN_24XX }, - { .div = 4, .val = 2, .flags = RATE_IN_24XX }, - { .div = 8, .val = 3, .flags = RATE_IN_24XX }, - { .div = 16, .val = 4, .flags = RATE_IN_24XX }, - { .div = 0 }, -}; - -static const struct clksel sys_clkout_clksel[] = { - { .parent = &sys_clkout_src, .rates = common_clkout_rates }, - { .parent = NULL } -}; - -static struct clk sys_clkout = { - .name = "sys_clkout", - .ops = &clkops_null, - .parent = &sys_clkout_src, - .clkdm_name = "wkup_clkdm", - .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL, - .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, - .clksel = sys_clkout_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -static struct clk emul_ck = { - .name = "emul_ck", - .ops = &clkops_omap2_dflt, - .parent = &func_54m_ck, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL, - .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, - .recalc = &followparent_recalc, - -}; - -/* - * MPU clock domain - * Clocks: - * MPU_FCLK, MPU_ICLK - * INT_M_FCLK, INT_M_I_CLK - * - * - Individual clocks are hardware managed. - * - Base divider comes from: CM_CLKSEL_MPU - * - */ -static const struct clksel_rate mpu_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 }, -}; - -static const struct clksel mpu_clksel[] = { - { .parent = &core_ck, .rates = mpu_core_rates }, - { .parent = NULL } -}; - -static struct clk mpu_ck = { /* Control cpu */ - .name = "mpu_ck", - .ops = &clkops_null, - .parent = &core_ck, - .clkdm_name = "mpu_clkdm", - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), - .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, - .clksel = mpu_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* - * DSP (2430-IVA2.1) clock domain - * Clocks: - * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK - * - * Won't be too specific here. The core clock comes into this block - * it is divided then tee'ed. One branch goes directly to xyz enable - * controls. The other branch gets further divided by 2 then possibly - * routed into a synchronizer and out of clocks abc. - */ -static const struct clksel_rate dsp_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 0 }, -}; - -static const struct clksel dsp_fck_clksel[] = { - { .parent = &core_ck, .rates = dsp_fck_core_rates }, - { .parent = NULL } -}; - -static struct clk dsp_fck = { - .name = "dsp_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_ck, - .clkdm_name = "dsp_clkdm", - .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK, - .clksel = dsp_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel dsp_ick_clksel[] = { - { .parent = &dsp_fck, .rates = dsp_ick_rates }, - { .parent = NULL } -}; - -/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ -static struct clk iva2_1_ick = { - .name = "iva2_1_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &dsp_fck, - .clkdm_name = "dsp_clkdm", - .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), - .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, - .clksel = dsp_ick_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* - * L3 clock domain - * L3 clocks are used for both interface and functional clocks to - * multiple entities. Some of these clocks are completely managed - * by hardware, and some others allow software control. Hardware - * managed ones general are based on directly CLK_REQ signals and - * various auto idle settings. The functional spec sets many of these - * as 'tie-high' for their enables. - * - * I-CLOCKS: - * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA - * CAM, HS-USB. - * F-CLOCK - * SSI. - * - * GPMC memories and SDRC have timing and clock sensitive registers which - * may very well need notification when the clock changes. Currently for low - * operating points, these are taken care of in sleep.S. - */ -static const struct clksel_rate core_l3_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 6, .val = 6, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel core_l3_clksel[] = { - { .parent = &core_ck, .rates = core_l3_core_rates }, - { .parent = NULL } -}; - -static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ - .name = "core_l3_ck", - .ops = &clkops_null, - .parent = &core_ck, - .clkdm_name = "core_l3_clkdm", - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, - .clksel = core_l3_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* usb_l4_ick */ -static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel usb_l4_ick_clksel[] = { - { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, - { .parent = NULL }, -}; - -/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ -static struct clk usb_l4_ick = { /* FS-USB interface clock */ - .name = "usb_l4_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l3_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP24XX_EN_USB_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_CLKSEL_USB_MASK, - .clksel = usb_l4_ick_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* - * L4 clock management domain - * - * This domain contains lots of interface clocks from the L4 interface, some - * functional clocks. Fixed APLL functional source clocks are managed in - * this domain. - */ -static const struct clksel_rate l4_core_l3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel l4_clksel[] = { - { .parent = &core_l3_ck, .rates = l4_core_l3_rates }, - { .parent = NULL } -}; - -static struct clk l4_ck = { /* used both as an ick and fck */ - .name = "l4_ck", - .ops = &clkops_null, - .parent = &core_l3_ck, - .clkdm_name = "core_l4_clkdm", - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, - .clksel = l4_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* - * SSI is in L3 management domain, its direct parent is core not l3, - * many core power domain entities are grouped into the L3 clock - * domain. - * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK - * - * ssr = core/1/2/3/4/5, sst = 1/2 ssr. - */ -static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 5, .val = 5, .flags = RATE_IN_243X }, - { .div = 0 } -}; - -static const struct clksel ssi_ssr_sst_fck_clksel[] = { - { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, - { .parent = NULL } -}; - -static struct clk ssi_ssr_sst_fck = { - .name = "ssi_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_ck, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP24XX_EN_SSI_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, - .clksel = ssi_ssr_sst_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* - * Presumably this is the same as SSI_ICLK. - * TRM contradicts itself on what clockdomain SSI_ICLK is in - */ -static struct clk ssi_l4_ick = { - .name = "ssi_l4_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP24XX_EN_SSI_SHIFT, - .recalc = &followparent_recalc, -}; - - -/* - * GFX clock domain - * Clocks: - * GFX_FCLK, GFX_ICLK - * GFX_CG1(2d), GFX_CG2(3d) - * - * GFX_FCLK runs from L3, and is divided by (1,2,3,4) - * The 2d and 3d clocks run at a hardware determined - * divided value of fclk. - * - */ - -/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ -static const struct clksel gfx_fck_clksel[] = { - { .parent = &core_l3_ck, .rates = gfx_l3_rates }, - { .parent = NULL }, -}; - -static struct clk gfx_3d_fck = { - .name = "gfx_3d_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l3_ck, - .clkdm_name = "gfx_clkdm", - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_3D_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), - .clksel_mask = OMAP_CLKSEL_GFX_MASK, - .clksel = gfx_fck_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -static struct clk gfx_2d_fck = { - .name = "gfx_2d_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l3_ck, - .clkdm_name = "gfx_clkdm", - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_2D_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), - .clksel_mask = OMAP_CLKSEL_GFX_MASK, - .clksel = gfx_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* This interface clock does not have a CM_AUTOIDLE bit */ -static struct clk gfx_ick = { - .name = "gfx_ick", /* From l3 */ - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l3_ck, - .clkdm_name = "gfx_clkdm", - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), - .enable_bit = OMAP_EN_GFX_SHIFT, - .recalc = &followparent_recalc, -}; - -/* - * Modem clock domain (2430) - * CLOCKS: - * MDM_OSC_CLK - * MDM_ICLK - * These clocks are usable in chassis mode only. - */ -static const struct clksel_rate mdm_ick_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_243X }, - { .div = 4, .val = 4, .flags = RATE_IN_243X }, - { .div = 6, .val = 6, .flags = RATE_IN_243X }, - { .div = 9, .val = 9, .flags = RATE_IN_243X }, - { .div = 0 } -}; - -static const struct clksel mdm_ick_clksel[] = { - { .parent = &core_ck, .rates = mdm_ick_core_rates }, - { .parent = NULL } -}; - -static struct clk mdm_ick = { /* used both as a ick and fck */ - .name = "mdm_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_ck, - .clkdm_name = "mdm_clkdm", - .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), - .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), - .clksel_mask = OMAP2430_CLKSEL_MDM_MASK, - .clksel = mdm_ick_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mdm_osc_ck = { - .name = "mdm_osc_ck", - .ops = &clkops_omap2_mdmclk_dflt_wait, - .parent = &osc_ck, - .clkdm_name = "mdm_clkdm", - .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), - .enable_bit = OMAP2430_EN_OSC_SHIFT, - .recalc = &followparent_recalc, -}; - -/* - * DSS clock domain - * CLOCKs: - * DSS_L4_ICLK, DSS_L3_ICLK, - * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK - * - * DSS is both initiator and target. - */ -/* XXX Add RATE_NOT_VALIDATED */ - -static const struct clksel_rate dss1_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate dss1_fck_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 2, .val = 2, .flags = RATE_IN_24XX }, - { .div = 3, .val = 3, .flags = RATE_IN_24XX }, - { .div = 4, .val = 4, .flags = RATE_IN_24XX }, - { .div = 5, .val = 5, .flags = RATE_IN_24XX }, - { .div = 6, .val = 6, .flags = RATE_IN_24XX }, - { .div = 8, .val = 8, .flags = RATE_IN_24XX }, - { .div = 9, .val = 9, .flags = RATE_IN_24XX }, - { .div = 12, .val = 12, .flags = RATE_IN_24XX }, - { .div = 16, .val = 16, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel dss1_fck_clksel[] = { - { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, - { .parent = &core_ck, .rates = dss1_fck_core_rates }, - { .parent = NULL }, -}; - -static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ - .name = "dss_ick", - .ops = &clkops_omap2_iclk_dflt, - .parent = &l4_ck, /* really both l3 and l4 */ - .clkdm_name = "dss_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_DSS1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk dss1_fck = { - .name = "dss1_fck", - .ops = &clkops_omap2_dflt, - .parent = &core_ck, /* Core or sys */ - .clkdm_name = "dss_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_DSS1_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, - .clksel = dss1_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate dss2_fck_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate dss2_fck_48m_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel dss2_fck_clksel[] = { - { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, - { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, - { .parent = NULL } -}; - -static struct clk dss2_fck = { /* Alt clk used in power management */ - .name = "dss2_fck", - .ops = &clkops_omap2_dflt, - .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ - .clkdm_name = "dss_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_DSS2_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, - .clksel = dss2_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk dss_54m_fck = { /* Alt clk used in power management */ - .name = "dss_54m_fck", /* 54m tv clk */ - .ops = &clkops_omap2_dflt_wait, - .parent = &func_54m_ck, - .clkdm_name = "dss_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_TV_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk wu_l4_ick = { - .name = "wu_l4_ick", - .ops = &clkops_null, - .parent = &sys_ck, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -/* - * CORE power domain ICLK & FCLK defines. - * Many of the these can have more than one possible parent. Entries - * here will likely have an L4 interface parent, and may have multiple - * functional clock parents. - */ -static const struct clksel_rate gpt_alt_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel omap24xx_gpt_clksel[] = { - { .parent = &func_32k_ck, .rates = gpt_32k_rates }, - { .parent = &sys_ck, .rates = gpt_sys_rates }, - { .parent = &alt_ck, .rates = gpt_alt_rates }, - { .parent = NULL }, -}; - -static struct clk gpt1_ick = { - .name = "gpt1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wu_l4_ick, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_GPT1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt1_fck = { - .name = "gpt1_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_GPT1_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1), - .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -static struct clk gpt2_ick = { - .name = "gpt2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt2_fck = { - .name = "gpt2_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT2_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt3_ick = { - .name = "gpt3_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT3_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt3_fck = { - .name = "gpt3_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT3_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt4_ick = { - .name = "gpt4_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT4_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt4_fck = { - .name = "gpt4_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT4_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt5_ick = { - .name = "gpt5_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT5_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt5_fck = { - .name = "gpt5_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT5_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt6_ick = { - .name = "gpt6_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT6_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt6_fck = { - .name = "gpt6_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT6_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt7_ick = { - .name = "gpt7_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT7_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt7_fck = { - .name = "gpt7_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT7_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt8_ick = { - .name = "gpt8_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT8_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt8_fck = { - .name = "gpt8_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT8_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt9_ick = { - .name = "gpt9_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT9_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt9_fck = { - .name = "gpt9_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT9_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt10_ick = { - .name = "gpt10_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT10_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt10_fck = { - .name = "gpt10_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT10_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt11_ick = { - .name = "gpt11_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT11_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt11_fck = { - .name = "gpt11_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT11_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt12_ick = { - .name = "gpt12_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_GPT12_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpt12_fck = { - .name = "gpt12_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &secure_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_GPT12_SHIFT, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2), - .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK, - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp1_ick = { - .name = "mcbsp1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .recalc = &followparent_recalc, -}; - -static const struct clksel_rate common_mcbsp_96m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_24XX }, - { .div = 0 } -}; - -static const struct clksel mcbsp_fck_clksel[] = { - { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, - { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, - { .parent = NULL } -}; - -static struct clk mcbsp1_fck = { - .name = "mcbsp1_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .init = &omap2_init_clksel_parent, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, - .clksel = mcbsp_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp2_ick = { - .name = "mcbsp2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp2_fck = { - .name = "mcbsp2_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .init = &omap2_init_clksel_parent, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, - .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, - .clksel = mcbsp_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp3_ick = { - .name = "mcbsp3_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp3_fck = { - .name = "mcbsp3_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .init = &omap2_init_clksel_parent, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, - .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), - .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, - .clksel = mcbsp_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp4_ick = { - .name = "mcbsp4_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp4_fck = { - .name = "mcbsp4_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .init = &omap2_init_clksel_parent, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, - .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), - .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, - .clksel = mcbsp_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp5_ick = { - .name = "mcbsp5_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp5_fck = { - .name = "mcbsp5_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .init = &omap2_init_clksel_parent, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, - .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), - .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, - .clksel = mcbsp_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcspi1_ick = { - .name = "mcspi1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi1_fck = { - .name = "mcspi1_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_48m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi2_ick = { - .name = "mcspi2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi2_fck = { - .name = "mcspi2_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_48m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi3_ick = { - .name = "mcspi3_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi3_fck = { - .name = "mcspi3_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_48m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk uart1_ick = { - .name = "uart1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_UART1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk uart1_fck = { - .name = "uart1_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_48m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_UART1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk uart2_ick = { - .name = "uart2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_UART2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk uart2_fck = { - .name = "uart2_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_48m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_UART2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk uart3_ick = { - .name = "uart3_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP24XX_EN_UART3_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk uart3_fck = { - .name = "uart3_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_48m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP24XX_EN_UART3_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpios_ick = { - .name = "gpios_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wu_l4_ick, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpios_fck = { - .name = "gpios_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mpu_wdt_ick = { - .name = "mpu_wdt_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wu_l4_ick, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mpu_wdt_fck = { - .name = "mpu_wdt_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk sync_32k_ick = { - .name = "sync_32k_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .flags = ENABLE_ON_INIT, - .parent = &wu_l4_ick, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk wdt1_ick = { - .name = "wdt1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wu_l4_ick, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_WDT1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk omapctrl_ick = { - .name = "omapctrl_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .flags = ENABLE_ON_INIT, - .parent = &wu_l4_ick, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk icr_ick = { - .name = "icr_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wu_l4_ick, - .clkdm_name = "wkup_clkdm", - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP2430_EN_ICR_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk cam_ick = { - .name = "cam_ick", - .ops = &clkops_omap2_iclk_dflt, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_CAM_SHIFT, - .recalc = &followparent_recalc, -}; - -/* - * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be - * split into two separate clocks, since the parent clocks are different - * and the clockdomains are also different. - */ -static struct clk cam_fck = { - .name = "cam_fck", - .ops = &clkops_omap2_dflt, - .parent = &func_96m_ck, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_CAM_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mailboxes_ick = { - .name = "mailboxes_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk wdt4_ick = { - .name = "wdt4_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_WDT4_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk wdt4_fck = { - .name = "wdt4_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_WDT4_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mspro_ick = { - .name = "mspro_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mspro_fck = { - .name = "mspro_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk fac_ick = { - .name = "fac_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_FAC_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk fac_fck = { - .name = "fac_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_12m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_FAC_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk hdq_ick = { - .name = "hdq_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP24XX_EN_HDQ_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk hdq_fck = { - .name = "hdq_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_12m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP24XX_EN_HDQ_SHIFT, - .recalc = &followparent_recalc, -}; - -/* - * XXX This is marked as a 2420-only define, but it claims to be present - * on 2430 also. Double-check. - */ -static struct clk i2c2_ick = { - .name = "i2c2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_I2C2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk i2chs2_fck = { - .name = "i2chs2_fck", - .ops = &clkops_omap2430_i2chs_wait, - .parent = &func_96m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, - .recalc = &followparent_recalc, -}; - -/* - * XXX This is marked as a 2420-only define, but it claims to be present - * on 2430 also. Double-check. - */ -static struct clk i2c1_ick = { - .name = "i2c1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP2420_EN_I2C1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk i2chs1_fck = { - .name = "i2chs1_fck", - .ops = &clkops_omap2430_i2chs_wait, - .parent = &func_96m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, - .recalc = &followparent_recalc, -}; - -/* - * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE - * accesses derived from this data. - */ -static struct clk gpmc_fck = { - .name = "gpmc_fck", - .ops = &clkops_omap2_iclk_idle_only, - .parent = &core_l3_ck, - .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk sdma_fck = { - .name = "sdma_fck", - .ops = &clkops_null, /* RMK: missing? */ - .parent = &core_l3_ck, - .clkdm_name = "core_l3_clkdm", - .recalc = &followparent_recalc, -}; - -/* - * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE - * accesses derived from this data. - */ -static struct clk sdma_ick = { - .name = "sdma_ick", - .ops = &clkops_omap2_iclk_idle_only, - .parent = &core_l3_ck, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk sdrc_ick = { - .name = "sdrc_ick", - .ops = &clkops_omap2_iclk_idle_only, - .parent = &core_l3_ck, - .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP2430_EN_SDRC_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk des_ick = { - .name = "des_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_DES_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk sha_ick = { - .name = "sha_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_SHA_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk rng_ick = { - .name = "rng_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_RNG_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk aes_ick = { - .name = "aes_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_AES_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk pka_ick = { - .name = "pka_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), - .enable_bit = OMAP24XX_EN_PKA_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk usb_fck = { - .name = "usb_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_48m_ck, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP24XX_EN_USB_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk usbhs_ick = { - .name = "usbhs_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l3_ck, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_USBHS_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mmchs1_ick = { - .name = "mmchs1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mmchs1_fck = { - .name = "mmchs1_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mmchs2_ick = { - .name = "mmchs2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mmchs2_fck = { - .name = "mmchs2_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpio5_ick = { - .name = "gpio5_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_GPIO5_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gpio5_fck = { - .name = "gpio5_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_GPIO5_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mdm_intc_ick = { - .name = "mdm_intc_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mmchsdb1_fck = { - .name = "mmchsdb1_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk mmchsdb2_fck = { - .name = "mmchsdb2_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), - .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, - .recalc = &followparent_recalc, -}; - -/* - * This clock is a composite clock which does entire set changes then - * forces a rebalance. It keys on the MPU speed, but it really could - * be any key speed part of a set in the rate table. - * - * to really change a set, you need memory table sets which get changed - * in sram, pre-notifiers & post notifiers, changing the top set, without - * having low level display recalc's won't work... this is why dpm notifiers - * work, isr's off, walk a list of clocks already _off_ and not messing with - * the bus. - * - * This clock should have no parent. It embodies the entire upper level - * active set. A parent will mess up some of the init also. - */ -static struct clk virt_prcm_set = { - .name = "virt_prcm_set", - .ops = &clkops_null, - .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ - .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ - .set_rate = &omap2_select_table_rate, - .round_rate = &omap2_round_to_table_rate, -}; - - -/* - * clkdev integration - */ - -static struct omap_clk omap2430_clks[] = { - /* external root sources */ - CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X), - CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X), - CLK(NULL, "osc_ck", &osc_ck, CK_243X), - CLK("twl", "fck", &osc_ck, CK_243X), - CLK(NULL, "sys_ck", &sys_ck, CK_243X), - CLK(NULL, "alt_ck", &alt_ck, CK_243X), - CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), - /* internal analog sources */ - CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), - CLK(NULL, "apll96_ck", &apll96_ck, CK_243X), - CLK(NULL, "apll54_ck", &apll54_ck, CK_243X), - /* internal prcm root sources */ - CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), - CLK(NULL, "core_ck", &core_ck, CK_243X), - CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), - CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), - CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), - CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X), - CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X), - CLK(NULL, "sys_clkout", &sys_clkout, CK_243X), - CLK(NULL, "emul_ck", &emul_ck, CK_243X), - /* mpu domain clocks */ - CLK(NULL, "mpu_ck", &mpu_ck, CK_243X), - /* dsp domain clocks */ - CLK(NULL, "dsp_fck", &dsp_fck, CK_243X), - CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), - /* GFX domain clocks */ - CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X), - CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X), - CLK(NULL, "gfx_ick", &gfx_ick, CK_243X), - /* Modem domain clocks */ - CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), - CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), - /* DSS domain clocks */ - CLK("omapdss_dss", "ick", &dss_ick, CK_243X), - CLK(NULL, "dss_ick", &dss_ick, CK_243X), - CLK(NULL, "dss1_fck", &dss1_fck, CK_243X), - CLK(NULL, "dss2_fck", &dss2_fck, CK_243X), - CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X), - /* L3 domain clocks */ - CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), - CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), - CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X), - /* L4 domain clocks */ - CLK(NULL, "l4_ck", &l4_ck, CK_243X), - CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X), - CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X), - /* virtual meta-group clock */ - CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X), - /* general l4 interface ck, multi-parent functional clk */ - CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X), - CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X), - CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X), - CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X), - CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X), - CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X), - CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X), - CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X), - CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X), - CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X), - CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X), - CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X), - CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X), - CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X), - CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X), - CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X), - CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X), - CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X), - CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X), - CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X), - CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X), - CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X), - CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), - CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), - CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), - CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X), - CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X), - CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), - CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X), - CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X), - CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), - CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X), - CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X), - CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), - CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X), - CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X), - CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), - CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X), - CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X), - CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X), - CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X), - CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X), - CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X), - CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X), - CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X), - CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), - CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X), - CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X), - CLK(NULL, "uart1_ick", &uart1_ick, CK_243X), - CLK(NULL, "uart1_fck", &uart1_fck, CK_243X), - CLK(NULL, "uart2_ick", &uart2_ick, CK_243X), - CLK(NULL, "uart2_fck", &uart2_fck, CK_243X), - CLK(NULL, "uart3_ick", &uart3_ick, CK_243X), - CLK(NULL, "uart3_fck", &uart3_fck, CK_243X), - CLK(NULL, "gpios_ick", &gpios_ick, CK_243X), - CLK(NULL, "gpios_fck", &gpios_fck, CK_243X), - CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X), - CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X), - CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X), - CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X), - CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X), - CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X), - CLK(NULL, "icr_ick", &icr_ick, CK_243X), - CLK("omap24xxcam", "fck", &cam_fck, CK_243X), - CLK(NULL, "cam_fck", &cam_fck, CK_243X), - CLK("omap24xxcam", "ick", &cam_ick, CK_243X), - CLK(NULL, "cam_ick", &cam_ick, CK_243X), - CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X), - CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X), - CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X), - CLK(NULL, "mspro_ick", &mspro_ick, CK_243X), - CLK(NULL, "mspro_fck", &mspro_fck, CK_243X), - CLK(NULL, "fac_ick", &fac_ick, CK_243X), - CLK(NULL, "fac_fck", &fac_fck, CK_243X), - CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), - CLK(NULL, "hdq_ick", &hdq_ick, CK_243X), - CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), - CLK(NULL, "hdq_fck", &hdq_fck, CK_243X), - CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X), - CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X), - CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X), - CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X), - CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X), - CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X), - CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), - CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), - CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), - CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), - CLK(NULL, "des_ick", &des_ick, CK_243X), - CLK("omap-sham", "ick", &sha_ick, CK_243X), - CLK("omap_rng", "ick", &rng_ick, CK_243X), - CLK(NULL, "rng_ick", &rng_ick, CK_243X), - CLK("omap-aes", "ick", &aes_ick, CK_243X), - CLK(NULL, "pka_ick", &pka_ick, CK_243X), - CLK(NULL, "usb_fck", &usb_fck, CK_243X), - CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), - CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X), - CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X), - CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X), - CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X), - CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X), - CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X), - CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X), - CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), - CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), - CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), - CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), - CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X), - CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), - CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X), - CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X), - CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X), - CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X), - CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X), -}; - -/* - * init code - */ - -int __init omap2430_clk_init(void) -{ - const struct prcm_config *prcm; - struct omap_clk *c; - u32 clkrate; - - prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; - cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST); - cpu_mask = RATE_IN_243X; - rate_table = omap2430_rate_table; - - clk_init(&omap2_clk_functions); - - for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); - c++) - clk_preinit(c->lk.clk); - - osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); - propagate_rate(&osc_ck); - sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck); - propagate_rate(&sys_ck); - - for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks); - c++) { - clkdev_add(&c->lk); - clk_register(c->lk.clk); - omap2_init_clk_clkdm(c->lk.clk); - } - - /* Disable autoidle on all clocks; let the PM code enable it later */ - omap_clk_disable_autoidle_all(); - - /* Check the MPU rate set by bootloader */ - clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); - for (prcm = rate_table; prcm->mpu_speed; prcm++) { - if (!(prcm->flags & cpu_mask)) - continue; - if (prcm->xtal_speed != sys_ck.rate) - continue; - if (prcm->dpll_speed <= clkrate) - break; - } - curr_prcm_set = prcm; - - recalculate_root_clocks(); - - pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", - (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, - (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; - - /* - * Only enable those clocks we will need, let the drivers - * enable other clocks as necessary - */ - clk_enable_init_clocks(); - - /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ - vclk = clk_get(NULL, "virt_prcm_set"); - sclk = clk_get(NULL, "sys_ck"); - dclk = clk_get(NULL, "dpll_ck"); - - return 0; -} - diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c index e92be1fc1a00..1ff646908627 100644 --- a/arch/arm/mach-omap2/clock2xxx.c +++ b/arch/arm/mach-omap2/clock2xxx.c @@ -22,35 +22,18 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/clock.h> - #include "soc.h" #include "clock.h" #include "clock2xxx.h" #include "cm.h" #include "cm-regbits-24xx.h" -struct clk *vclk, *sclk, *dclk; - +struct clk_hw *dclk_hw; /* * Omap24xx specific clock functions */ /* - * Set clocks for bypass mode for reboot to work. - */ -void omap2xxx_clk_prepare_for_reboot(void) -{ - u32 rate; - - if (vclk == NULL || sclk == NULL) - return; - - rate = clk_get_rate(sclk); - clk_set_rate(vclk, rate); -} - -/* * Switch the MPU rate if specified on cmdline. We cannot do this * early until cmdline is parsed. XXX This should be removed from the * clock code and handled by the OPP layer code in the near future. diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h index cb6df8ca9e4a..539dc08afbba 100644 --- a/arch/arm/mach-omap2/clock2xxx.h +++ b/arch/arm/mach-omap2/clock2xxx.h @@ -8,17 +8,34 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H #define __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H -unsigned long omap2_table_mpu_recalc(struct clk *clk); -int omap2_select_table_rate(struct clk *clk, unsigned long rate); -long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); -unsigned long omap2xxx_sys_clk_recalc(struct clk *clk); -unsigned long omap2_osc_clk_recalc(struct clk *clk); -unsigned long omap2_dpllcore_recalc(struct clk *clk); -int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); -unsigned long omap2xxx_clk_get_core_rate(struct clk *clk); +#include <linux/clk-provider.h> +#include "clock.h" + +unsigned long omap2_table_mpu_recalc(struct clk_hw *clk, + unsigned long parent_rate); +int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate); +long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate); +unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk, + unsigned long parent_rate); +unsigned long omap2_osc_clk_recalc(struct clk_hw *clk, + unsigned long parent_rate); +unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, + unsigned long parent_rate); +int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate, + unsigned long parent_rate); +void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw); +unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw, + unsigned long parent_rate); +unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw, + unsigned long parent_rate); +unsigned long omap2xxx_clk_get_core_rate(void); u32 omap2xxx_get_apll_clkin(void); u32 omap2xxx_get_sysclkdiv(void); void omap2xxx_clk_prepare_for_reboot(void); +void omap2xxx_clkt_vps_check_bootloader_rates(void); +void omap2xxx_clkt_vps_late_init(void); #ifdef CONFIG_SOC_OMAP2420 int omap2420_clk_init(void); @@ -32,13 +49,14 @@ int omap2430_clk_init(void); #define omap2430_clk_init() do { } while(0) #endif -extern void __iomem *prcm_clksrc_ctrl, *cm_idlest_pll; +extern void __iomem *prcm_clksrc_ctrl; -extern struct clk *dclk; - -extern const struct clkops clkops_omap2430_i2chs_wait; -extern const struct clkops clkops_oscck; -extern const struct clkops clkops_apll96; -extern const struct clkops clkops_apll54; +extern struct clk_hw *dclk_hw; +int omap2_enable_osc_ck(struct clk_hw *hw); +void omap2_disable_osc_ck(struct clk_hw *hw); +int omap2_clk_apll96_enable(struct clk_hw *hw); +int omap2_clk_apll54_enable(struct clk_hw *hw); +void omap2_clk_apll96_disable(struct clk_hw *hw); +void omap2_clk_apll54_disable(struct clk_hw *hw); #endif diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c deleted file mode 100644 index 88fa9494d5e9..000000000000 --- a/arch/arm/mach-omap2/clock33xx_data.c +++ /dev/null @@ -1,1112 +0,0 @@ -/* - * AM33XX Clock data - * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * Vaibhav Hiremath <hvaibhav@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/clk.h> -#include <plat/clkdev_omap.h> - -#include "am33xx.h" -#include "iomap.h" -#include "control.h" -#include "clock.h" -#include "cm.h" -#include "cm33xx.h" -#include "cm-regbits-33xx.h" -#include "prm.h" - -/* Maximum DPLL multiplier, divider values for AM33XX */ -#define AM33XX_MAX_DPLL_MULT 2047 -#define AM33XX_MAX_DPLL_DIV 128 - -/* Modulemode control */ -#define AM33XX_MODULEMODE_HWCTRL 0 -#define AM33XX_MODULEMODE_SWCTRL 1 - -/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always - * physically present, in such a case HWMOD enabling of - * clock would be failure with default parent. And timer - * probe thinks clock is already enabled, this leads to - * crash upon accessing timer 3 & 6 registers in probe. - * Fix by setting parent of both these timers to master - * oscillator clock. - */ -static inline void am33xx_init_timer_parent(struct clk *clk) -{ - omap2_clksel_set_parent(clk, clk->parent); -} - -/* Root clocks */ - -/* RTC 32k */ -static struct clk clk_32768_ck = { - .name = "clk_32768_ck", - .clkdm_name = "l4_rtc_clkdm", - .rate = 32768, - .ops = &clkops_null, -}; - -/* On-Chip 32KHz RC OSC */ -static struct clk clk_rc32k_ck = { - .name = "clk_rc32k_ck", - .rate = 32000, - .ops = &clkops_null, -}; - -/* Crystal input clks */ -static struct clk virt_24000000_ck = { - .name = "virt_24000000_ck", - .rate = 24000000, - .ops = &clkops_null, -}; - -static struct clk virt_25000000_ck = { - .name = "virt_25000000_ck", - .rate = 25000000, - .ops = &clkops_null, -}; - -/* Oscillator clock */ -/* 19.2, 24, 25 or 26 MHz */ -static const struct clksel sys_clkin_sel[] = { - { .parent = &virt_19200000_ck, .rates = div_1_0_rates }, - { .parent = &virt_24000000_ck, .rates = div_1_1_rates }, - { .parent = &virt_25000000_ck, .rates = div_1_2_rates }, - { .parent = &virt_26000000_ck, .rates = div_1_3_rates }, - { .parent = NULL }, -}; - -/* External clock - 12 MHz */ -static struct clk tclkin_ck = { - .name = "tclkin_ck", - .rate = 12000000, - .ops = &clkops_null, -}; - -/* - * sys_clk in: input to the dpll and also used as funtional clock for, - * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse - * - */ -static struct clk sys_clkin_ck = { - .name = "sys_clkin_ck", - .parent = &virt_24000000_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS), - .clksel_mask = AM33XX_CONTROL_STATUS_SYSBOOT1_MASK, - .clksel = sys_clkin_sel, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -/* DPLL_CORE */ -static struct dpll_data dpll_core_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE, - .mult_mask = AM33XX_DPLL_MULT_MASK, - .div1_mask = AM33XX_DPLL_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = AM33XX_MAX_DPLL_MULT, - .max_divider = AM33XX_MAX_DPLL_DIV, - .min_divider = 1, -}; - -/* CLKDCOLDO output */ -static struct clk dpll_core_ck = { - .name = "dpll_core_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_core_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_core_dpll_ops, - .recalc = &omap3_dpll_recalc, -}; - -static struct clk dpll_core_x2_ck = { - .name = "dpll_core_x2_ck", - .parent = &dpll_core_ck, - .flags = CLOCK_CLKOUTX2, - .ops = &clkops_null, - .recalc = &omap3_clkoutx2_recalc, -}; - - -static const struct clksel dpll_core_m4_div[] = { - { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_core_m4_ck = { - .name = "dpll_core_m4_ck", - .parent = &dpll_core_x2_ck, - .init = &omap2_init_clksel_parent, - .clksel = dpll_core_m4_div, - .clksel_reg = AM33XX_CM_DIV_M4_DPLL_CORE, - .clksel_mask = AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel dpll_core_m5_div[] = { - { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_core_m5_ck = { - .name = "dpll_core_m5_ck", - .parent = &dpll_core_x2_ck, - .init = &omap2_init_clksel_parent, - .clksel = dpll_core_m5_div, - .clksel_reg = AM33XX_CM_DIV_M5_DPLL_CORE, - .clksel_mask = AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel dpll_core_m6_div[] = { - { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_core_m6_ck = { - .name = "dpll_core_m6_ck", - .parent = &dpll_core_x2_ck, - .init = &omap2_init_clksel_parent, - .clksel = dpll_core_m6_div, - .clksel_reg = AM33XX_CM_DIV_M6_DPLL_CORE, - .clksel_mask = AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -/* DPLL_MPU */ -static struct dpll_data dpll_mpu_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU, - .mult_mask = AM33XX_DPLL_MULT_MASK, - .div1_mask = AM33XX_DPLL_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = AM33XX_MAX_DPLL_MULT, - .max_divider = AM33XX_MAX_DPLL_DIV, - .min_divider = 1, -}; - -/* CLKOUT: fdpll/M2 */ -static struct clk dpll_mpu_ck = { - .name = "dpll_mpu_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_mpu_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -/* - * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 - * and ALT_CLK1/2) - */ -static const struct clksel dpll_mpu_m2_div[] = { - { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_mpu_m2_ck = { - .name = "dpll_mpu_m2_ck", - .clkdm_name = "mpu_clkdm", - .parent = &dpll_mpu_ck, - .clksel = dpll_mpu_m2_div, - .clksel_reg = AM33XX_CM_DIV_M2_DPLL_MPU, - .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -/* DPLL_DDR */ -static struct dpll_data dpll_ddr_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR, - .mult_mask = AM33XX_DPLL_MULT_MASK, - .div1_mask = AM33XX_DPLL_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = AM33XX_MAX_DPLL_MULT, - .max_divider = AM33XX_MAX_DPLL_DIV, - .min_divider = 1, -}; - -/* CLKOUT: fdpll/M2 */ -static struct clk dpll_ddr_ck = { - .name = "dpll_ddr_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_ddr_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_null, - .recalc = &omap3_dpll_recalc, -}; - -/* - * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 - * and ALT_CLK1/2) - */ -static const struct clksel dpll_ddr_m2_div[] = { - { .parent = &dpll_ddr_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_ddr_m2_ck = { - .name = "dpll_ddr_m2_ck", - .parent = &dpll_ddr_ck, - .clksel = dpll_ddr_m2_div, - .clksel_reg = AM33XX_CM_DIV_M2_DPLL_DDR, - .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -/* emif_fck functional clock */ -static struct clk dpll_ddr_m2_div2_ck = { - .name = "dpll_ddr_m2_div2_ck", - .clkdm_name = "l3_clkdm", - .parent = &dpll_ddr_m2_ck, - .ops = &clkops_null, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; - -/* DPLL_DISP */ -static struct dpll_data dpll_disp_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP, - .mult_mask = AM33XX_DPLL_MULT_MASK, - .div1_mask = AM33XX_DPLL_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = AM33XX_MAX_DPLL_MULT, - .max_divider = AM33XX_MAX_DPLL_DIV, - .min_divider = 1, -}; - -/* CLKOUT: fdpll/M2 */ -static struct clk dpll_disp_ck = { - .name = "dpll_disp_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_disp_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_null, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -/* - * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 - * and ALT_CLK1/2) - */ -static const struct clksel dpll_disp_m2_div[] = { - { .parent = &dpll_disp_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_disp_m2_ck = { - .name = "dpll_disp_m2_ck", - .parent = &dpll_disp_ck, - .clksel = dpll_disp_m2_div, - .clksel_reg = AM33XX_CM_DIV_M2_DPLL_DISP, - .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -/* DPLL_PER */ -static struct dpll_data dpll_per_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_PER, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER, - .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK, - .div1_mask = AM33XX_DPLL_PER_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = AM33XX_MAX_DPLL_MULT, - .max_divider = AM33XX_MAX_DPLL_DIV, - .min_divider = 1, - .flags = DPLL_J_TYPE, -}; - -/* CLKDCOLDO */ -static struct clk dpll_per_ck = { - .name = "dpll_per_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_per_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_null, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -/* CLKOUT: fdpll/M2 */ -static const struct clksel dpll_per_m2_div[] = { - { .parent = &dpll_per_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_per_m2_ck = { - .name = "dpll_per_m2_ck", - .parent = &dpll_per_ck, - .clksel = dpll_per_m2_div, - .clksel_reg = AM33XX_CM_DIV_M2_DPLL_PER, - .clksel_mask = AM33XX_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_per_m2_div4_wkupdm_ck = { - .name = "dpll_per_m2_div4_wkupdm_ck", - .clkdm_name = "l4_wkup_clkdm", - .parent = &dpll_per_m2_ck, - .fixed_div = 4, - .ops = &clkops_null, - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk dpll_per_m2_div4_ck = { - .name = "dpll_per_m2_div4_ck", - .clkdm_name = "l4ls_clkdm", - .parent = &dpll_per_m2_ck, - .fixed_div = 4, - .ops = &clkops_null, - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk l3_gclk = { - .name = "l3_gclk", - .clkdm_name = "l3_clkdm", - .parent = &dpll_core_m4_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk dpll_core_m4_div2_ck = { - .name = "dpll_core_m4_div2_ck", - .clkdm_name = "l4_wkup_clkdm", - .parent = &dpll_core_m4_ck, - .ops = &clkops_null, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk l4_rtc_gclk = { - .name = "l4_rtc_gclk", - .parent = &dpll_core_m4_ck, - .ops = &clkops_null, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk clk_24mhz = { - .name = "clk_24mhz", - .parent = &dpll_per_m2_ck, - .fixed_div = 8, - .ops = &clkops_null, - .recalc = &omap_fixed_divisor_recalc, -}; - -/* - * Below clock nodes describes clockdomains derived out - * of core clock. - */ -static struct clk l4hs_gclk = { - .name = "l4hs_gclk", - .clkdm_name = "l4hs_clkdm", - .parent = &dpll_core_m4_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk l3s_gclk = { - .name = "l3s_gclk", - .clkdm_name = "l3s_clkdm", - .parent = &dpll_core_m4_div2_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk l4fw_gclk = { - .name = "l4fw_gclk", - .clkdm_name = "l4fw_clkdm", - .parent = &dpll_core_m4_div2_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk l4ls_gclk = { - .name = "l4ls_gclk", - .clkdm_name = "l4ls_clkdm", - .parent = &dpll_core_m4_div2_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk sysclk_div_ck = { - .name = "sysclk_div_ck", - .parent = &dpll_core_m4_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -/* - * In order to match the clock domain with hwmod clockdomain entry, - * separate clock nodes is required for the modules which are - * directly getting their funtioncal clock from sys_clkin. - */ -static struct clk adc_tsc_fck = { - .name = "adc_tsc_fck", - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk dcan0_fck = { - .name = "dcan0_fck", - .clkdm_name = "l4ls_clkdm", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk dcan1_fck = { - .name = "dcan1_fck", - .clkdm_name = "l4ls_clkdm", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk mcasp0_fck = { - .name = "mcasp0_fck", - .clkdm_name = "l3s_clkdm", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk mcasp1_fck = { - .name = "mcasp1_fck", - .clkdm_name = "l3s_clkdm", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk smartreflex_mpu_fck = { - .name = "smartreflex_mpu_fck", - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk smartreflex_core_fck = { - .name = "smartreflex_core_fck", - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -/* - * Modules clock nodes - * - * The following clock leaf nodes are added for the moment because: - * - * - hwmod data is not present for these modules, either hwmod - * control is not required or its not populated. - * - Driver code is not yet migrated to use hwmod/runtime pm - * - Modules outside kernel access (to disable them by default) - * - * - debugss - * - mmu (gfx domain) - * - cefuse - * - usbotg_fck (its additional clock and not really a modulemode) - * - ieee5000 - */ -static struct clk debugss_ick = { - .name = "debugss_ick", - .clkdm_name = "l3_aon_clkdm", - .parent = &dpll_core_m4_ck, - .ops = &clkops_omap2_dflt, - .enable_reg = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, - .enable_bit = AM33XX_MODULEMODE_SWCTRL, - .recalc = &followparent_recalc, -}; - -static struct clk mmu_fck = { - .name = "mmu_fck", - .clkdm_name = "gfx_l3_clkdm", - .parent = &dpll_core_m4_ck, - .ops = &clkops_omap2_dflt, - .enable_reg = AM33XX_CM_GFX_MMUDATA_CLKCTRL, - .enable_bit = AM33XX_MODULEMODE_SWCTRL, - .recalc = &followparent_recalc, -}; - -static struct clk cefuse_fck = { - .name = "cefuse_fck", - .clkdm_name = "l4_cefuse_clkdm", - .parent = &sys_clkin_ck, - .enable_reg = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, - .enable_bit = AM33XX_MODULEMODE_SWCTRL, - .ops = &clkops_omap2_dflt, - .recalc = &followparent_recalc, -}; - -/* - * clkdiv32 is generated from fixed division of 732.4219 - */ -static struct clk clkdiv32k_ick = { - .name = "clkdiv32k_ick", - .clkdm_name = "clk_24mhz_clkdm", - .rate = 32768, - .parent = &clk_24mhz, - .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL, - .enable_bit = AM33XX_MODULEMODE_SWCTRL, - .ops = &clkops_omap2_dflt, -}; - -static struct clk usbotg_fck = { - .name = "usbotg_fck", - .clkdm_name = "l3s_clkdm", - .parent = &dpll_per_ck, - .enable_reg = AM33XX_CM_CLKDCOLDO_DPLL_PER, - .enable_bit = AM33XX_ST_DPLL_CLKDCOLDO_SHIFT, - .ops = &clkops_omap2_dflt, - .recalc = &followparent_recalc, -}; - -static struct clk ieee5000_fck = { - .name = "ieee5000_fck", - .clkdm_name = "l3s_clkdm", - .parent = &dpll_core_m4_div2_ck, - .enable_reg = AM33XX_CM_PER_IEEE5000_CLKCTRL, - .enable_bit = AM33XX_MODULEMODE_SWCTRL, - .ops = &clkops_omap2_dflt, - .recalc = &followparent_recalc, -}; - -/* Timers */ -static const struct clksel timer1_clkmux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &clkdiv32k_ick, .rates = div_1_1_rates }, - { .parent = &tclkin_ck, .rates = div_1_2_rates }, - { .parent = &clk_rc32k_ck, .rates = div_1_3_rates }, - { .parent = &clk_32768_ck, .rates = div_1_4_rates }, - { .parent = NULL }, -}; - -static struct clk timer1_fck = { - .name = "timer1_fck", - .clkdm_name = "l4ls_clkdm", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .clksel = timer1_clkmux_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK, - .clksel_mask = AM33XX_CLKSEL_0_2_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel timer2_to_7_clk_sel[] = { - { .parent = &tclkin_ck, .rates = div_1_0_rates }, - { .parent = &sys_clkin_ck, .rates = div_1_1_rates }, - { .parent = &clkdiv32k_ick, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static struct clk timer2_fck = { - .name = "timer2_fck", - .clkdm_name = "l4ls_clkdm", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk timer3_fck = { - .name = "timer3_fck", - .clkdm_name = "l4ls_clkdm", - .parent = &sys_clkin_ck, - .init = &am33xx_init_timer_parent, - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk timer4_fck = { - .name = "timer4_fck", - .clkdm_name = "l4ls_clkdm", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk timer5_fck = { - .name = "timer5_fck", - .clkdm_name = "l4ls_clkdm", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk timer6_fck = { - .name = "timer6_fck", - .clkdm_name = "l4ls_clkdm", - .parent = &sys_clkin_ck, - .init = &am33xx_init_timer_parent, - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk timer7_fck = { - .name = "timer7_fck", - .clkdm_name = "l4ls_clkdm", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk cpsw_125mhz_gclk = { - .name = "cpsw_125mhz_gclk", - .clkdm_name = "cpsw_125mhz_clkdm", - .parent = &dpll_core_m5_ck, - .ops = &clkops_null, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; - -static const struct clksel cpsw_cpts_rft_clkmux_sel[] = { - { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk cpsw_cpts_rft_clk = { - .name = "cpsw_cpts_rft_clk", - .clkdm_name = "cpsw_125mhz_clkdm", - .parent = &dpll_core_m5_ck, - .clksel = cpsw_cpts_rft_clkmux_sel, - .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL, - .clksel_mask = AM33XX_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -/* gpio */ -static const struct clksel gpio0_dbclk_mux_sel[] = { - { .parent = &clk_rc32k_ck, .rates = div_1_0_rates }, - { .parent = &clk_32768_ck, .rates = div_1_1_rates }, - { .parent = &clkdiv32k_ick, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static struct clk gpio0_dbclk_mux_ck = { - .name = "gpio0_dbclk_mux_ck", - .clkdm_name = "l4_wkup_clkdm", - .parent = &clk_rc32k_ck, - .init = &omap2_init_clksel_parent, - .clksel = gpio0_dbclk_mux_sel, - .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpio0_dbclk = { - .name = "gpio0_dbclk", - .clkdm_name = "l4_wkup_clkdm", - .parent = &gpio0_dbclk_mux_ck, - .enable_reg = AM33XX_CM_WKUP_GPIO0_CLKCTRL, - .enable_bit = AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, - .ops = &clkops_omap2_dflt, - .recalc = &followparent_recalc, -}; - -static struct clk gpio1_dbclk = { - .name = "gpio1_dbclk", - .clkdm_name = "l4ls_clkdm", - .parent = &clkdiv32k_ick, - .enable_reg = AM33XX_CM_PER_GPIO1_CLKCTRL, - .enable_bit = AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, - .ops = &clkops_omap2_dflt, - .recalc = &followparent_recalc, -}; - -static struct clk gpio2_dbclk = { - .name = "gpio2_dbclk", - .clkdm_name = "l4ls_clkdm", - .parent = &clkdiv32k_ick, - .enable_reg = AM33XX_CM_PER_GPIO2_CLKCTRL, - .enable_bit = AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, - .ops = &clkops_omap2_dflt, - .recalc = &followparent_recalc, -}; - -static struct clk gpio3_dbclk = { - .name = "gpio3_dbclk", - .clkdm_name = "l4ls_clkdm", - .parent = &clkdiv32k_ick, - .enable_reg = AM33XX_CM_PER_GPIO3_CLKCTRL, - .enable_bit = AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, - .ops = &clkops_omap2_dflt, - .recalc = &followparent_recalc, -}; - -static const struct clksel pruss_ocp_clk_mux_sel[] = { - { .parent = &l3_gclk, .rates = div_1_0_rates }, - { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk pruss_ocp_gclk = { - .name = "pruss_ocp_gclk", - .clkdm_name = "pruss_ocp_clkdm", - .parent = &l3_gclk, - .init = &omap2_init_clksel_parent, - .clksel = pruss_ocp_clk_mux_sel, - .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK, - .clksel_mask = AM33XX_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static const struct clksel lcd_clk_mux_sel[] = { - { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates }, - { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static struct clk lcd_gclk = { - .name = "lcd_gclk", - .clkdm_name = "lcdc_clkdm", - .parent = &dpll_disp_m2_ck, - .init = &omap2_init_clksel_parent, - .clksel = lcd_clk_mux_sel, - .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk mmc_clk = { - .name = "mmc_clk", - .clkdm_name = "l4ls_clkdm", - .parent = &dpll_per_m2_ck, - .ops = &clkops_null, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk mmc2_fck = { - .name = "mmc2_fck", - .clkdm_name = "l3s_clkdm", - .parent = &mmc_clk, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static const struct clksel gfx_clksel_sel[] = { - { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates }, - { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk gfx_fclk_clksel_ck = { - .name = "gfx_fclk_clksel_ck", - .parent = &dpll_core_m4_ck, - .clksel = gfx_clksel_sel, - .ops = &clkops_null, - .clksel_reg = AM33XX_CLKSEL_GFX_FCLK, - .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate div_1_0_2_1_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_AM33XX }, - { .div = 2, .val = 1, .flags = RATE_IN_AM33XX }, - { .div = 0 }, -}; - -static const struct clksel gfx_div_sel[] = { - { .parent = &gfx_fclk_clksel_ck, .rates = div_1_0_2_1_rates }, - { .parent = NULL }, -}; - -static struct clk gfx_fck_div_ck = { - .name = "gfx_fck_div_ck", - .clkdm_name = "gfx_l3_clkdm", - .parent = &gfx_fclk_clksel_ck, - .init = &omap2_init_clksel_parent, - .clksel = gfx_div_sel, - .clksel_reg = AM33XX_CLKSEL_GFX_FCLK, - .clksel_mask = AM33XX_CLKSEL_0_0_MASK, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .ops = &clkops_null, -}; - -static const struct clksel sysclkout_pre_sel[] = { - { .parent = &clk_32768_ck, .rates = div_1_0_rates }, - { .parent = &l3_gclk, .rates = div_1_1_rates }, - { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates }, - { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates }, - { .parent = &lcd_gclk, .rates = div_1_4_rates }, - { .parent = NULL }, -}; - -static struct clk sysclkout_pre_ck = { - .name = "sysclkout_pre_ck", - .parent = &clk_32768_ck, - .init = &omap2_init_clksel_parent, - .clksel = sysclkout_pre_sel, - .clksel_reg = AM33XX_CM_CLKOUT_CTRL, - .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -/* Divide by 8 clock rates with default clock is 1/1*/ -static const struct clksel_rate div8_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_AM33XX }, - { .div = 2, .val = 1, .flags = RATE_IN_AM33XX }, - { .div = 3, .val = 2, .flags = RATE_IN_AM33XX }, - { .div = 4, .val = 3, .flags = RATE_IN_AM33XX }, - { .div = 5, .val = 4, .flags = RATE_IN_AM33XX }, - { .div = 6, .val = 5, .flags = RATE_IN_AM33XX }, - { .div = 7, .val = 6, .flags = RATE_IN_AM33XX }, - { .div = 8, .val = 7, .flags = RATE_IN_AM33XX }, - { .div = 0 }, -}; - -static const struct clksel clkout2_div[] = { - { .parent = &sysclkout_pre_ck, .rates = div8_rates }, - { .parent = NULL }, -}; - -static struct clk clkout2_ck = { - .name = "clkout2_ck", - .parent = &sysclkout_pre_ck, - .ops = &clkops_omap2_dflt, - .clksel = clkout2_div, - .clksel_reg = AM33XX_CM_CLKOUT_CTRL, - .clksel_mask = AM33XX_CLKOUT2DIV_MASK, - .enable_reg = AM33XX_CM_CLKOUT_CTRL, - .enable_bit = AM33XX_CLKOUT2EN_SHIFT, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel wdt_clkmux_sel[] = { - { .parent = &clk_rc32k_ck, .rates = div_1_0_rates }, - { .parent = &clkdiv32k_ick, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk wdt1_fck = { - .name = "wdt1_fck", - .clkdm_name = "l4_wkup_clkdm", - .parent = &clk_rc32k_ck, - .init = &omap2_init_clksel_parent, - .clksel = wdt_clkmux_sel, - .clksel_reg = AM33XX_CLKSEL_WDT1_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -/* - * clkdev - */ -static struct omap_clk am33xx_clks[] = { - CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX), - CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX), - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX), - CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX), - CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX), - CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX), - CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX), - CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX), - CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX), - CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX), - CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX), - CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX), - CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX), - CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX), - CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX), - CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX), - CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX), - CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX), - CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX), - CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX), - CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX), - CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX), - CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX), - CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX), - CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX), - CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX), - CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX), - CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX), - CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX), - CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX), - CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX), - CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX), - CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX), - CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX), - CLK("davinci-mcasp.0", NULL, &mcasp0_fck, CK_AM33XX), - CLK("davinci-mcasp.1", NULL, &mcasp1_fck, CK_AM33XX), - CLK(NULL, "mcasp0_fck", &mcasp0_fck, CK_AM33XX), - CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX), - CLK("NULL", "mmc2_fck", &mmc2_fck, CK_AM33XX), - CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX), - CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_AM33XX), - CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_AM33XX), - CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX), - CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX), - CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX), - CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX), - CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX), - CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX), - CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX), - CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX), - CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX), - CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX), - CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX), - CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX), - CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX), - CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX), - CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX), - CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX), - CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX), - CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX), - CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX), - CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX), - CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX), - CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX), - CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX), - CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX), - CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX), - CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX), - CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX), - CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX), - CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX), - CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX), - CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX), - CLK(NULL, "clkout2_ck", &clkout2_ck, CK_AM33XX), - CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX), - CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX), -}; - -int __init am33xx_clk_init(void) -{ - struct omap_clk *c; - u32 cpu_clkflg; - - if (soc_is_am33xx()) { - cpu_mask = RATE_IN_AM33XX; - cpu_clkflg = CK_AM33XX; - } - - clk_init(&omap2_clk_functions); - - for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) - clk_preinit(c->lk.clk); - - for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) { - if (c->cpu & cpu_clkflg) { - clkdev_add(&c->lk); - clk_register(c->lk.clk); - omap2_init_clk_clkdm(c->lk.clk); - } - } - - recalculate_root_clocks(); - - /* - * Only enable those clocks we will need, let the drivers - * enable other clocks as necessary - */ - clk_enable_init_clocks(); - - return 0; -} diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 1fc96b9ee330..4596468e50ab 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -21,11 +21,9 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/clock.h> - #include "clock.h" #include "clock34xx.h" -#include "cm2xxx_3xxx.h" +#include "cm3xxx.h" #include "cm-regbits-34xx.h" /** @@ -39,7 +37,7 @@ * from the CM_{I,F}CLKEN bit. Pass back the correct info via * @idlest_reg and @idlest_bit. No return value. */ -static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, +static void omap3430es2_clk_ssi_find_idlest(struct clk_hw_omap *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) @@ -51,21 +49,16 @@ static void omap3430es2_clk_ssi_find_idlest(struct clk *clk, *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; *idlest_val = OMAP34XX_CM_IDLEST_VAL; } - -const struct clkops clkops_omap3430es2_ssi_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, +const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait = { .find_idlest = omap3430es2_clk_ssi_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, + .find_companion = omap2_clk_dflt_find_companion, }; -const struct clkops clkops_omap3430es2_iclk_ssi_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_idlest = omap3430es2_clk_ssi_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, +const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait = { .allow_idle = omap2_clkt_iclk_allow_idle, .deny_idle = omap2_clkt_iclk_deny_idle, + .find_idlest = omap3430es2_clk_ssi_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, }; /** @@ -82,7 +75,7 @@ const struct clkops clkops_omap3430es2_iclk_ssi_wait = { * default find_idlest code assumes that they are at the same * position.) No return value. */ -static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, +static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk_hw_omap *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) @@ -96,20 +89,16 @@ static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk, *idlest_val = OMAP34XX_CM_IDLEST_VAL; } -const struct clkops clkops_omap3430es2_dss_usbhost_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, +const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait = { .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, + .find_companion = omap2_clk_dflt_find_companion, }; -const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, +const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait = { .allow_idle = omap2_clkt_iclk_allow_idle, .deny_idle = omap2_clkt_iclk_deny_idle, + .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, }; /** @@ -123,7 +112,7 @@ const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait = { * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via * @idlest_reg and @idlest_bit. No return value. */ -static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, +static void omap3430es2_clk_hsotgusb_find_idlest(struct clk_hw_omap *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) @@ -136,18 +125,14 @@ static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk, *idlest_val = OMAP34XX_CM_IDLEST_VAL; } -const struct clkops clkops_omap3430es2_hsotgusb_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, +const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait = { + .allow_idle = omap2_clkt_iclk_allow_idle, + .deny_idle = omap2_clkt_iclk_deny_idle, .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, + .find_companion = omap2_clk_dflt_find_companion, }; -const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, +const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait = { .find_idlest = omap3430es2_clk_hsotgusb_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, + .find_companion = omap2_clk_dflt_find_companion, }; diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c index 2e97d08f0e56..4d79ae2c0241 100644 --- a/arch/arm/mach-omap2/clock3517.c +++ b/arch/arm/mach-omap2/clock3517.c @@ -21,11 +21,9 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/clock.h> - #include "clock.h" #include "clock3517.h" -#include "cm2xxx_3xxx.h" +#include "cm3xxx.h" #include "cm-regbits-34xx.h" /* @@ -49,7 +47,7 @@ * in the enable register itsel at a bit offset of 4 from the enable * bit. A value of 1 indicates that clock is enabled. */ -static void am35xx_clk_find_idlest(struct clk *clk, +static void am35xx_clk_find_idlest(struct clk_hw_omap *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) @@ -73,8 +71,9 @@ static void am35xx_clk_find_idlest(struct clk *clk, * associate this type of code with per-module data structures to * avoid this issue, and remove the casts. No return value. */ -static void am35xx_clk_find_companion(struct clk *clk, void __iomem **other_reg, - u8 *other_bit) +static void am35xx_clk_find_companion(struct clk_hw_omap *clk, + void __iomem **other_reg, + u8 *other_bit) { *other_reg = (__force void __iomem *)(clk->enable_reg); if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) @@ -82,10 +81,7 @@ static void am35xx_clk_find_companion(struct clk *clk, void __iomem **other_reg, else *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; } - -const struct clkops clkops_am35xx_ipss_module_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, +const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait = { .find_idlest = am35xx_clk_find_idlest, .find_companion = am35xx_clk_find_companion, }; @@ -101,7 +97,7 @@ const struct clkops clkops_am35xx_ipss_module_wait = { * CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg * and @idlest_bit. No return value. */ -static void am35xx_clk_ipss_find_idlest(struct clk *clk, +static void am35xx_clk_ipss_find_idlest(struct clk_hw_omap *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) @@ -114,13 +110,9 @@ static void am35xx_clk_ipss_find_idlest(struct clk *clk, *idlest_val = OMAP34XX_CM_IDLEST_VAL; } -const struct clkops clkops_am35xx_ipss_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_idlest = am35xx_clk_ipss_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, +const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = { .allow_idle = omap2_clkt_iclk_allow_idle, .deny_idle = omap2_clkt_iclk_deny_idle, + .find_idlest = am35xx_clk_ipss_find_idlest, + .find_companion = omap2_clk_dflt_find_companion, }; - - diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c index 0c5e25ed8879..8f3bf4e50908 100644 --- a/arch/arm/mach-omap2/clock36xx.c +++ b/arch/arm/mach-omap2/clock36xx.c @@ -22,8 +22,6 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/clock.h> - #include "clock.h" #include "clock36xx.h" @@ -39,34 +37,32 @@ * (Any other value different from the Read value) to the * corresponding CM_CLKSEL register will refresh the dividers. */ -static int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk *clk) +int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) { + struct clk_hw_omap *parent; + struct clk_hw *parent_hw; u32 dummy_v, orig_v, clksel_shift; int ret; /* Clear PWRDN bit of HSDIVIDER */ ret = omap2_dflt_clk_enable(clk); + parent_hw = __clk_get_hw(__clk_get_parent(clk->clk)); + parent = to_clk_hw_omap(parent_hw); + /* Restore the dividers */ if (!ret) { - clksel_shift = __ffs(clk->parent->clksel_mask); - orig_v = __raw_readl(clk->parent->clksel_reg); + clksel_shift = __ffs(parent->clksel_mask); + orig_v = __raw_readl(parent->clksel_reg); dummy_v = orig_v; /* Write any other value different from the Read value */ dummy_v ^= (1 << clksel_shift); - __raw_writel(dummy_v, clk->parent->clksel_reg); + __raw_writel(dummy_v, parent->clksel_reg); /* Write the original divider */ - __raw_writel(orig_v, clk->parent->clksel_reg); + __raw_writel(orig_v, parent->clksel_reg); } return ret; } - -const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore = { - .enable = omap36xx_pwrdn_clk_enable_with_hsdiv_restore, - .disable = omap2_dflt_clk_disable, - .find_companion = omap2_clk_dflt_find_companion, - .find_idlest = omap2_clk_dflt_find_idlest, -}; diff --git a/arch/arm/mach-omap2/clock36xx.h b/arch/arm/mach-omap2/clock36xx.h index a7dee5bc6364..945bb7f083e9 100644 --- a/arch/arm/mach-omap2/clock36xx.h +++ b/arch/arm/mach-omap2/clock36xx.h @@ -8,6 +8,6 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H #define __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H -extern const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; +extern int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *hw); #endif diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index 83bb01427d40..4eacab8f1176 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c @@ -21,8 +21,6 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/clock.h> - #include "soc.h" #include "clock.h" #include "clock3xxx.h" @@ -40,8 +38,8 @@ /* needed by omap3_core_dpll_m2_set_rate() */ struct clk *sdrc_ick_p, *arm_fck_p; - -int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) +int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) { /* * According to the 12-5 CDP code from TI, "Limitation 2.5" @@ -53,7 +51,7 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) return -EINVAL; } - return omap3_noncore_dpll_set_rate(clk, rate); + return omap3_noncore_dpll_set_rate(hw, rate, parent_rate); } void __init omap3_clk_lock_dpll5(void) diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h index 8bbeeaf399e2..8cd4b0a882ae 100644 --- a/arch/arm/mach-omap2/clock3xxx.h +++ b/arch/arm/mach-omap2/clock3xxx.h @@ -9,8 +9,10 @@ #define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H int omap3xxx_clk_init(void); -int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); -int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); +int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, + unsigned long parent_rate); +int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate, + unsigned long parent_rate); void omap3_clk_lock_dpll5(void); extern struct clk *sdrc_ick_p; diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c deleted file mode 100644 index d1786fca6919..000000000000 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ /dev/null @@ -1,3617 +0,0 @@ -/* - * OMAP3 clock data - * - * Copyright (C) 2007-2010, 2012 Texas Instruments, Inc. - * Copyright (C) 2007-2011 Nokia Corporation - * - * Written by Paul Walmsley - * With many device clock fixes by Kevin Hilman and Jouni Högander - * DPLL bypass clock support added by Roman Tereshonkov - * - */ - -/* - * Virtual clocks are introduced as convenient tools. - * They are sources for other clocks and not supposed - * to be requested from drivers directly. - */ - -#include <linux/kernel.h> -#include <linux/clk.h> -#include <linux/list.h> -#include <linux/io.h> - -#include <plat/clkdev_omap.h> - -#include "soc.h" -#include "iomap.h" -#include "clock.h" -#include "clock3xxx.h" -#include "clock34xx.h" -#include "clock36xx.h" -#include "clock3517.h" -#include "cm2xxx_3xxx.h" -#include "cm-regbits-34xx.h" -#include "prm2xxx_3xxx.h" -#include "prm-regbits-34xx.h" -#include "control.h" - -/* - * clocks - */ - -#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR - -/* Maximum DPLL multiplier, divider values for OMAP3 */ -#define OMAP3_MAX_DPLL_MULT 2047 -#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095 -#define OMAP3_MAX_DPLL_DIV 128 - -/* - * DPLL1 supplies clock to the MPU. - * DPLL2 supplies clock to the IVA2. - * DPLL3 supplies CORE domain clocks. - * DPLL4 supplies peripheral clocks. - * DPLL5 supplies other peripheral clocks (USBHOST, USIM). - */ - -/* Forward declarations for DPLL bypass clocks */ -static struct clk dpll1_fck; -static struct clk dpll2_fck; - -/* PRM CLOCKS */ - -/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ -static struct clk omap_32k_fck = { - .name = "omap_32k_fck", - .ops = &clkops_null, - .rate = 32768, -}; - -static struct clk secure_32k_fck = { - .name = "secure_32k_fck", - .ops = &clkops_null, - .rate = 32768, -}; - -/* Virtual source clocks for osc_sys_ck */ -static struct clk virt_12m_ck = { - .name = "virt_12m_ck", - .ops = &clkops_null, - .rate = 12000000, -}; - -static struct clk virt_13m_ck = { - .name = "virt_13m_ck", - .ops = &clkops_null, - .rate = 13000000, -}; - -static struct clk virt_16_8m_ck = { - .name = "virt_16_8m_ck", - .ops = &clkops_null, - .rate = 16800000, -}; - -static struct clk virt_38_4m_ck = { - .name = "virt_38_4m_ck", - .ops = &clkops_null, - .rate = 38400000, -}; - -static const struct clksel_rate osc_sys_12m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel_rate osc_sys_13m_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel_rate osc_sys_16_8m_rates[] = { - { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 0 } -}; - -static const struct clksel_rate osc_sys_19_2m_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel_rate osc_sys_26m_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel_rate osc_sys_38_4m_rates[] = { - { .div = 1, .val = 4, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel osc_sys_clksel[] = { - { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, - { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, - { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, - { .parent = &virt_19200000_ck, .rates = osc_sys_19_2m_rates }, - { .parent = &virt_26000000_ck, .rates = osc_sys_26m_rates }, - { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, - { .parent = NULL }, -}; - -/* Oscillator clock */ -/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ -static struct clk osc_sys_ck = { - .name = "osc_sys_ck", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP3430_PRM_CLKSEL, - .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, - .clksel = osc_sys_clksel, - /* REVISIT: deal with autoextclkmode? */ - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate div2_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, - { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel sys_clksel[] = { - { .parent = &osc_sys_ck, .rates = div2_rates }, - { .parent = NULL } -}; - -/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ -/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ -static struct clk sys_ck = { - .name = "sys_ck", - .ops = &clkops_null, - .parent = &osc_sys_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, - .clksel_mask = OMAP_SYSCLKDIV_MASK, - .clksel = sys_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk sys_altclk = { - .name = "sys_altclk", - .ops = &clkops_null, -}; - -/* Optional external clock input for some McBSPs */ -static struct clk mcbsp_clks = { - .name = "mcbsp_clks", - .ops = &clkops_null, -}; - -/* PRM EXTERNAL CLOCK OUTPUT */ - -static struct clk sys_clkout1 = { - .name = "sys_clkout1", - .ops = &clkops_omap2_dflt, - .parent = &osc_sys_ck, - .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, - .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, - .recalc = &followparent_recalc, -}; - -/* DPLLS */ - -/* CM CLOCKS */ - -static const struct clksel_rate div16_dpll_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, - { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, - { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, - { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, - { .div = 5, .val = 5, .flags = RATE_IN_3XXX }, - { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, - { .div = 7, .val = 7, .flags = RATE_IN_3XXX }, - { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, - { .div = 9, .val = 9, .flags = RATE_IN_3XXX }, - { .div = 10, .val = 10, .flags = RATE_IN_3XXX }, - { .div = 11, .val = 11, .flags = RATE_IN_3XXX }, - { .div = 12, .val = 12, .flags = RATE_IN_3XXX }, - { .div = 13, .val = 13, .flags = RATE_IN_3XXX }, - { .div = 14, .val = 14, .flags = RATE_IN_3XXX }, - { .div = 15, .val = 15, .flags = RATE_IN_3XXX }, - { .div = 16, .val = 16, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel_rate dpll4_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, - { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, - { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, - { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, - { .div = 5, .val = 5, .flags = RATE_IN_3XXX }, - { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, - { .div = 7, .val = 7, .flags = RATE_IN_3XXX }, - { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, - { .div = 9, .val = 9, .flags = RATE_IN_3XXX }, - { .div = 10, .val = 10, .flags = RATE_IN_3XXX }, - { .div = 11, .val = 11, .flags = RATE_IN_3XXX }, - { .div = 12, .val = 12, .flags = RATE_IN_3XXX }, - { .div = 13, .val = 13, .flags = RATE_IN_3XXX }, - { .div = 14, .val = 14, .flags = RATE_IN_3XXX }, - { .div = 15, .val = 15, .flags = RATE_IN_3XXX }, - { .div = 16, .val = 16, .flags = RATE_IN_3XXX }, - { .div = 17, .val = 17, .flags = RATE_IN_36XX }, - { .div = 18, .val = 18, .flags = RATE_IN_36XX }, - { .div = 19, .val = 19, .flags = RATE_IN_36XX }, - { .div = 20, .val = 20, .flags = RATE_IN_36XX }, - { .div = 21, .val = 21, .flags = RATE_IN_36XX }, - { .div = 22, .val = 22, .flags = RATE_IN_36XX }, - { .div = 23, .val = 23, .flags = RATE_IN_36XX }, - { .div = 24, .val = 24, .flags = RATE_IN_36XX }, - { .div = 25, .val = 25, .flags = RATE_IN_36XX }, - { .div = 26, .val = 26, .flags = RATE_IN_36XX }, - { .div = 27, .val = 27, .flags = RATE_IN_36XX }, - { .div = 28, .val = 28, .flags = RATE_IN_36XX }, - { .div = 29, .val = 29, .flags = RATE_IN_36XX }, - { .div = 30, .val = 30, .flags = RATE_IN_36XX }, - { .div = 31, .val = 31, .flags = RATE_IN_36XX }, - { .div = 32, .val = 32, .flags = RATE_IN_36XX }, - { .div = 0 } -}; - -/* DPLL1 */ -/* MPU clock source */ -/* Type: DPLL */ -static struct dpll_data dpll1_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), - .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, - .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, - .clk_bypass = &dpll1_fck, - .clk_ref = &sys_ck, - .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, - .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), - .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, - .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, - .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, - .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), - .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, - .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), - .idlest_mask = OMAP3430_ST_MPU_CLK_MASK, - .max_multiplier = OMAP3_MAX_DPLL_MULT, - .min_divider = 1, - .max_divider = OMAP3_MAX_DPLL_DIV, -}; - -static struct clk dpll1_ck = { - .name = "dpll1_ck", - .ops = &clkops_omap3_noncore_dpll_ops, - .parent = &sys_ck, - .dpll_data = &dpll1_dd, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .clkdm_name = "dpll1_clkdm", - .recalc = &omap3_dpll_recalc, -}; - -/* - * This virtual clock provides the CLKOUTX2 output from the DPLL if the - * DPLL isn't bypassed. - */ -static struct clk dpll1_x2_ck = { - .name = "dpll1_x2_ck", - .ops = &clkops_null, - .parent = &dpll1_ck, - .clkdm_name = "dpll1_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */ -static const struct clksel div16_dpll1_x2m2_clksel[] = { - { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates }, - { .parent = NULL } -}; - -/* - * Does not exist in the TRM - needed to separate the M2 divider from - * bypass selection in mpu_ck - */ -static struct clk dpll1_x2m2_ck = { - .name = "dpll1_x2m2_ck", - .ops = &clkops_null, - .parent = &dpll1_x2_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), - .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, - .clksel = div16_dpll1_x2m2_clksel, - .clkdm_name = "dpll1_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* DPLL2 */ -/* IVA2 clock source */ -/* Type: DPLL */ - -static struct dpll_data dpll2_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), - .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, - .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, - .clk_bypass = &dpll2_fck, - .clk_ref = &sys_ck, - .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, - .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), - .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, - .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | - (1 << DPLL_LOW_POWER_BYPASS), - .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, - .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, - .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, - .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), - .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, - .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), - .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK, - .max_multiplier = OMAP3_MAX_DPLL_MULT, - .min_divider = 1, - .max_divider = OMAP3_MAX_DPLL_DIV, -}; - -static struct clk dpll2_ck = { - .name = "dpll2_ck", - .ops = &clkops_omap3_noncore_dpll_ops, - .parent = &sys_ck, - .dpll_data = &dpll2_dd, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .clkdm_name = "dpll2_clkdm", - .recalc = &omap3_dpll_recalc, -}; - -static const struct clksel div16_dpll2_m2x2_clksel[] = { - { .parent = &dpll2_ck, .rates = div16_dpll_rates }, - { .parent = NULL } -}; - -/* - * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT - * or CLKOUTX2. CLKOUT seems most plausible. - */ -static struct clk dpll2_m2_ck = { - .name = "dpll2_m2_ck", - .ops = &clkops_null, - .parent = &dpll2_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, - OMAP3430_CM_CLKSEL2_PLL), - .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, - .clksel = div16_dpll2_m2x2_clksel, - .clkdm_name = "dpll2_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* - * DPLL3 - * Source clock for all interfaces and for some device fclks - * REVISIT: Also supports fast relock bypass - not included below - */ -static struct dpll_data dpll3_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, - .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK, - .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, - .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, - .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, - .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, - .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), - .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, - .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .idlest_mask = OMAP3430_ST_CORE_CLK_MASK, - .max_multiplier = OMAP3_MAX_DPLL_MULT, - .min_divider = 1, - .max_divider = OMAP3_MAX_DPLL_DIV, -}; - -static struct clk dpll3_ck = { - .name = "dpll3_ck", - .ops = &clkops_omap3_core_dpll_ops, - .parent = &sys_ck, - .dpll_data = &dpll3_dd, - .round_rate = &omap2_dpll_round_rate, - .clkdm_name = "dpll3_clkdm", - .recalc = &omap3_dpll_recalc, -}; - -/* - * This virtual clock provides the CLKOUTX2 output from the DPLL if the - * DPLL isn't bypassed - */ -static struct clk dpll3_x2_ck = { - .name = "dpll3_x2_ck", - .ops = &clkops_null, - .parent = &dpll3_ck, - .clkdm_name = "dpll3_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -static const struct clksel_rate div31_dpll3_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, - { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, - { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX }, - { .div = 0 }, -}; - -static const struct clksel div31_dpll3m2_clksel[] = { - { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, - { .parent = NULL } -}; - -/* DPLL3 output M2 - primary control point for CORE speed */ -static struct clk dpll3_m2_ck = { - .name = "dpll3_m2_ck", - .ops = &clkops_null, - .parent = &dpll3_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, - .clksel = div31_dpll3m2_clksel, - .clkdm_name = "dpll3_clkdm", - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap3_core_dpll_m2_set_rate, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk core_ck = { - .name = "core_ck", - .ops = &clkops_null, - .parent = &dpll3_m2_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dpll3_m2x2_ck = { - .name = "dpll3_m2x2_ck", - .ops = &clkops_null, - .parent = &dpll3_m2_ck, - .clkdm_name = "dpll3_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static const struct clksel div16_dpll3_clksel[] = { - { .parent = &dpll3_ck, .rates = div16_dpll_rates }, - { .parent = NULL } -}; - -/* This virtual clock is the source for dpll3_m3x2_ck */ -static struct clk dpll3_m3_ck = { - .name = "dpll3_m3_ck", - .ops = &clkops_null, - .parent = &dpll3_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_DIV_DPLL3_MASK, - .clksel = div16_dpll3_clksel, - .clkdm_name = "dpll3_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static struct clk dpll3_m3x2_ck = { - .name = "dpll3_m3x2_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll3_m3_ck, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, - .flags = INVERT_ENABLE, - .clkdm_name = "dpll3_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -static struct clk emu_core_alwon_ck = { - .name = "emu_core_alwon_ck", - .ops = &clkops_null, - .parent = &dpll3_m3x2_ck, - .clkdm_name = "dpll3_clkdm", - .recalc = &followparent_recalc, -}; - -/* DPLL4 */ -/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ -/* Type: DPLL */ -static struct dpll_data dpll4_dd; - -static struct dpll_data dpll4_dd_34xx __initdata = { - .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), - .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, - .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK, - .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, - .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), - .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, - .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, - .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, - .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), - .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, - .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, - .max_multiplier = OMAP3_MAX_DPLL_MULT, - .min_divider = 1, - .max_divider = OMAP3_MAX_DPLL_DIV, -}; - -static struct dpll_data dpll4_dd_3630 __initdata = { - .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), - .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK, - .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, - .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), - .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, - .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, - .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, - .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), - .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, - .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, - .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK, - .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK, - .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT, - .min_divider = 1, - .max_divider = OMAP3_MAX_DPLL_DIV, - .flags = DPLL_J_TYPE -}; - -static struct clk dpll4_ck = { - .name = "dpll4_ck", - .ops = &clkops_omap3_noncore_dpll_ops, - .parent = &sys_ck, - .dpll_data = &dpll4_dd, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_dpll4_set_rate, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap3_dpll_recalc, -}; - -/* - * This virtual clock provides the CLKOUTX2 output from the DPLL if the - * DPLL isn't bypassed -- - * XXX does this serve any downstream clocks? - */ -static struct clk dpll4_x2_ck = { - .name = "dpll4_x2_ck", - .ops = &clkops_null, - .parent = &dpll4_ck, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -static const struct clksel dpll4_clksel[] = { - { .parent = &dpll4_ck, .rates = dpll4_rates }, - { .parent = NULL } -}; - -/* This virtual clock is the source for dpll4_m2x2_ck */ -static struct clk dpll4_m2_ck = { - .name = "dpll4_m2_ck", - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), - .clksel_mask = OMAP3630_DIV_96M_MASK, - .clksel = dpll4_clksel, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static struct clk dpll4_m2x2_ck = { - .name = "dpll4_m2x2_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll4_m2_ck, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP3430_PWRDN_96M_SHIFT, - .flags = INVERT_ENABLE, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -/* - * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as - * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM: - * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and - * CM_96K_(F)CLK. - */ - -/* Adding 192MHz Clock node needed by SGX */ -static struct clk omap_192m_alwon_fck = { - .name = "omap_192m_alwon_fck", - .ops = &clkops_null, - .parent = &dpll4_m2x2_ck, - .recalc = &followparent_recalc, -}; - -static const struct clksel_rate omap_96m_alwon_fck_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_36XX }, - { .div = 2, .val = 2, .flags = RATE_IN_36XX }, - { .div = 0 } -}; - -static const struct clksel omap_96m_alwon_fck_clksel[] = { - { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates }, - { .parent = NULL } -}; - -static const struct clksel_rate omap_96m_dpll_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel_rate omap_96m_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static struct clk omap_96m_alwon_fck = { - .name = "omap_96m_alwon_fck", - .ops = &clkops_null, - .parent = &dpll4_m2x2_ck, - .recalc = &followparent_recalc, -}; - -static struct clk omap_96m_alwon_fck_3630 = { - .name = "omap_96m_alwon_fck", - .parent = &omap_192m_alwon_fck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), - .clksel_mask = OMAP3630_CLKSEL_96M_MASK, - .clksel = omap_96m_alwon_fck_clksel -}; - -static struct clk cm_96m_fck = { - .name = "cm_96m_fck", - .ops = &clkops_null, - .parent = &omap_96m_alwon_fck, - .recalc = &followparent_recalc, -}; - -static const struct clksel omap_96m_fck_clksel[] = { - { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, - { .parent = &sys_ck, .rates = omap_96m_sys_rates }, - { .parent = NULL } -}; - -static struct clk omap_96m_fck = { - .name = "omap_96m_fck", - .ops = &clkops_null, - .parent = &sys_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_SOURCE_96M_MASK, - .clksel = omap_96m_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* This virtual clock is the source for dpll4_m3x2_ck */ -static struct clk dpll4_m3_ck = { - .name = "dpll4_m3_ck", - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), - .clksel_mask = OMAP3630_CLKSEL_TV_MASK, - .clksel = dpll4_clksel, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static struct clk dpll4_m3x2_ck = { - .name = "dpll4_m3x2_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll4_m3_ck, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP3430_PWRDN_TV_SHIFT, - .flags = INVERT_ENABLE, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -static const struct clksel_rate omap_54m_d4m3x2_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel_rate omap_54m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel omap_54m_clksel[] = { - { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates }, - { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, - { .parent = NULL } -}; - -static struct clk omap_54m_fck = { - .name = "omap_54m_fck", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_SOURCE_54M_MASK, - .clksel = omap_54m_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate omap_48m_cm96m_rates[] = { - { .div = 2, .val = 0, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel_rate omap_48m_alt_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel omap_48m_clksel[] = { - { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates }, - { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, - { .parent = NULL } -}; - -static struct clk omap_48m_fck = { - .name = "omap_48m_fck", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_SOURCE_48M_MASK, - .clksel = omap_48m_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk omap_12m_fck = { - .name = "omap_12m_fck", - .ops = &clkops_null, - .parent = &omap_48m_fck, - .fixed_div = 4, - .recalc = &omap_fixed_divisor_recalc, -}; - -/* This virtual clock is the source for dpll4_m4x2_ck */ -static struct clk dpll4_m4_ck = { - .name = "dpll4_m4_ck", - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), - .clksel_mask = OMAP3630_CLKSEL_DSS1_MASK, - .clksel = dpll4_clksel, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static struct clk dpll4_m4x2_ck = { - .name = "dpll4_m4x2_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll4_m4_ck, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT, - .flags = INVERT_ENABLE, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -/* This virtual clock is the source for dpll4_m5x2_ck */ -static struct clk dpll4_m5_ck = { - .name = "dpll4_m5_ck", - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), - .clksel_mask = OMAP3630_CLKSEL_CAM_MASK, - .clksel = dpll4_clksel, - .clkdm_name = "dpll4_clkdm", - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, - .recalc = &omap2_clksel_recalc, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static struct clk dpll4_m5x2_ck = { - .name = "dpll4_m5x2_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll4_m5_ck, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, - .flags = INVERT_ENABLE, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -/* This virtual clock is the source for dpll4_m6x2_ck */ -static struct clk dpll4_m6_ck = { - .name = "dpll4_m6_ck", - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3630_DIV_DPLL4_MASK, - .clksel = dpll4_clksel, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static struct clk dpll4_m6x2_ck = { - .name = "dpll4_m6x2_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll4_m6_ck, - .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), - .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, - .flags = INVERT_ENABLE, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap3_clkoutx2_recalc, -}; - -static struct clk emu_per_alwon_ck = { - .name = "emu_per_alwon_ck", - .ops = &clkops_null, - .parent = &dpll4_m6x2_ck, - .clkdm_name = "dpll4_clkdm", - .recalc = &followparent_recalc, -}; - -/* DPLL5 */ -/* Supplies 120MHz clock, USIM source clock */ -/* Type: DPLL */ -/* 3430ES2 only */ -static struct dpll_data dpll5_dd = { - .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), - .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, - .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK, - .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), - .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, - .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), - .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, - .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, - .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, - .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), - .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, - .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), - .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, - .max_multiplier = OMAP3_MAX_DPLL_MULT, - .min_divider = 1, - .max_divider = OMAP3_MAX_DPLL_DIV, -}; - -static struct clk dpll5_ck = { - .name = "dpll5_ck", - .ops = &clkops_omap3_noncore_dpll_ops, - .parent = &sys_ck, - .dpll_data = &dpll5_dd, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .clkdm_name = "dpll5_clkdm", - .recalc = &omap3_dpll_recalc, -}; - -static const struct clksel div16_dpll5_clksel[] = { - { .parent = &dpll5_ck, .rates = div16_dpll_rates }, - { .parent = NULL } -}; - -static struct clk dpll5_m2_ck = { - .name = "dpll5_m2_ck", - .ops = &clkops_null, - .parent = &dpll5_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), - .clksel_mask = OMAP3430ES2_DIV_120M_MASK, - .clksel = div16_dpll5_clksel, - .clkdm_name = "dpll5_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* CM EXTERNAL CLOCK OUTPUTS */ - -static const struct clksel_rate clkout2_src_core_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel_rate clkout2_src_sys_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel_rate clkout2_src_96m_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel_rate clkout2_src_54m_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel clkout2_src_clksel[] = { - { .parent = &core_ck, .rates = clkout2_src_core_rates }, - { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, - { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates }, - { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, - { .parent = NULL } -}; - -static struct clk clkout2_src_ck = { - .name = "clkout2_src_ck", - .ops = &clkops_omap2_dflt, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP3430_CM_CLKOUT_CTRL, - .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, - .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, - .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, - .clksel = clkout2_src_clksel, - .clkdm_name = "core_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate sys_clkout2_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, - { .div = 2, .val = 1, .flags = RATE_IN_3XXX }, - { .div = 4, .val = 2, .flags = RATE_IN_3XXX }, - { .div = 8, .val = 3, .flags = RATE_IN_3XXX }, - { .div = 16, .val = 4, .flags = RATE_IN_3XXX }, - { .div = 0 }, -}; - -static const struct clksel sys_clkout2_clksel[] = { - { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, - { .parent = NULL }, -}; - -static struct clk sys_clkout2 = { - .name = "sys_clkout2", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, - .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, - .clksel = sys_clkout2_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -/* CM OUTPUT CLOCKS */ - -static struct clk corex2_fck = { - .name = "corex2_fck", - .ops = &clkops_null, - .parent = &dpll3_m2x2_ck, - .recalc = &followparent_recalc, -}; - -/* DPLL power domain clock controls */ - -static const struct clksel_rate div4_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, - { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, - { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel div4_core_clksel[] = { - { .parent = &core_ck, .rates = div4_rates }, - { .parent = NULL } -}; - -/* - * REVISIT: Are these in DPLL power domain or CM power domain? docs - * may be inconsistent here? - */ -static struct clk dpll1_fck = { - .name = "dpll1_fck", - .ops = &clkops_null, - .parent = &core_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), - .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, - .clksel = div4_core_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mpu_ck = { - .name = "mpu_ck", - .ops = &clkops_null, - .parent = &dpll1_x2m2_ck, - .clkdm_name = "mpu_clkdm", - .recalc = &followparent_recalc, -}; - -/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ -static const struct clksel_rate arm_fck_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, - { .div = 2, .val = 1, .flags = RATE_IN_3XXX }, - { .div = 0 }, -}; - -static const struct clksel arm_fck_clksel[] = { - { .parent = &mpu_ck, .rates = arm_fck_rates }, - { .parent = NULL } -}; - -static struct clk arm_fck = { - .name = "arm_fck", - .ops = &clkops_null, - .parent = &mpu_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), - .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, - .clksel = arm_fck_clksel, - .clkdm_name = "mpu_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* XXX What about neon_clkdm ? */ - -/* - * REVISIT: This clock is never specifically defined in the 3430 TRM, - * although it is referenced - so this is a guess - */ -static struct clk emu_mpu_alwon_ck = { - .name = "emu_mpu_alwon_ck", - .ops = &clkops_null, - .parent = &mpu_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dpll2_fck = { - .name = "dpll2_fck", - .ops = &clkops_null, - .parent = &core_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), - .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, - .clksel = div4_core_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk iva2_ck = { - .name = "iva2_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll2_m2_ck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, - .clkdm_name = "iva2_clkdm", - .recalc = &followparent_recalc, -}; - -/* Common interface clocks */ - -static const struct clksel div2_core_clksel[] = { - { .parent = &core_ck, .rates = div2_rates }, - { .parent = NULL } -}; - -static struct clk l3_ick = { - .name = "l3_ick", - .ops = &clkops_null, - .parent = &core_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_L3_MASK, - .clksel = div2_core_clksel, - .clkdm_name = "core_l3_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel div2_l3_clksel[] = { - { .parent = &l3_ick, .rates = div2_rates }, - { .parent = NULL } -}; - -static struct clk l4_ick = { - .name = "l4_ick", - .ops = &clkops_null, - .parent = &l3_ick, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_L4_MASK, - .clksel = div2_l3_clksel, - .clkdm_name = "core_l4_clkdm", - .recalc = &omap2_clksel_recalc, - -}; - -static const struct clksel div2_l4_clksel[] = { - { .parent = &l4_ick, .rates = div2_rates }, - { .parent = NULL } -}; - -static struct clk rm_ick = { - .name = "rm_ick", - .ops = &clkops_null, - .parent = &l4_ick, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_RM_MASK, - .clksel = div2_l4_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* GFX power domain */ - -/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ - -static const struct clksel gfx_l3_clksel[] = { - { .parent = &l3_ick, .rates = gfx_l3_rates }, - { .parent = NULL } -}; - -/* - * Virtual parent clock for gfx_l3_ick and gfx_l3_fck - * This interface clock does not have a CM_AUTOIDLE bit - */ -static struct clk gfx_l3_ck = { - .name = "gfx_l3_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &l3_ick, - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), - .enable_bit = OMAP_EN_GFX_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk gfx_l3_fck = { - .name = "gfx_l3_fck", - .ops = &clkops_null, - .parent = &gfx_l3_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), - .clksel_mask = OMAP_CLKSEL_GFX_MASK, - .clksel = gfx_l3_clksel, - .clkdm_name = "gfx_3430es1_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gfx_l3_ick = { - .name = "gfx_l3_ick", - .ops = &clkops_null, - .parent = &gfx_l3_ck, - .clkdm_name = "gfx_3430es1_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gfx_cg1_ck = { - .name = "gfx_cg1_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &gfx_l3_fck, /* REVISIT: correct? */ - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - .enable_bit = OMAP3430ES1_EN_2D_SHIFT, - .clkdm_name = "gfx_3430es1_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gfx_cg2_ck = { - .name = "gfx_cg2_ck", - .ops = &clkops_omap2_dflt_wait, - .parent = &gfx_l3_fck, /* REVISIT: correct? */ - .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), - .enable_bit = OMAP3430ES1_EN_3D_SHIFT, - .clkdm_name = "gfx_3430es1_clkdm", - .recalc = &followparent_recalc, -}; - -/* SGX power domain - 3430ES2 only */ - -static const struct clksel_rate sgx_core_rates[] = { - { .div = 2, .val = 5, .flags = RATE_IN_36XX }, - { .div = 3, .val = 0, .flags = RATE_IN_3XXX }, - { .div = 4, .val = 1, .flags = RATE_IN_3XXX }, - { .div = 6, .val = 2, .flags = RATE_IN_3XXX }, - { .div = 0 }, -}; - -static const struct clksel_rate sgx_192m_rates[] = { - { .div = 1, .val = 4, .flags = RATE_IN_36XX }, - { .div = 0 }, -}; - -static const struct clksel_rate sgx_corex2_rates[] = { - { .div = 3, .val = 6, .flags = RATE_IN_36XX }, - { .div = 5, .val = 7, .flags = RATE_IN_36XX }, - { .div = 0 }, -}; - -static const struct clksel_rate sgx_96m_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_3XXX }, - { .div = 0 }, -}; - -static const struct clksel sgx_clksel[] = { - { .parent = &core_ck, .rates = sgx_core_rates }, - { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, - { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates }, - { .parent = &corex2_fck, .rates = sgx_corex2_rates }, - { .parent = NULL } -}; - -static struct clk sgx_fck = { - .name = "sgx_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), - .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, - .clksel = sgx_clksel, - .clkdm_name = "sgx_clkdm", - .recalc = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate -}; - -/* This interface clock does not have a CM_AUTOIDLE bit */ -static struct clk sgx_ick = { - .name = "sgx_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &l3_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), - .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, - .clkdm_name = "sgx_clkdm", - .recalc = &followparent_recalc, -}; - -/* CORE power domain */ - -static struct clk d2d_26m_fck = { - .name = "d2d_26m_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &sys_ck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, - .clkdm_name = "d2d_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk modem_fck = { - .name = "modem_fck", - .ops = &clkops_omap2_mdmclk_dflt_wait, - .parent = &sys_ck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MODEM_SHIFT, - .clkdm_name = "d2d_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk sad2d_ick = { - .name = "sad2d_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l3_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_SAD2D_SHIFT, - .clkdm_name = "d2d_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mad2d_ick = { - .name = "mad2d_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l3_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP3430_EN_MAD2D_SHIFT, - .clkdm_name = "d2d_clkdm", - .recalc = &followparent_recalc, -}; - -static const struct clksel omap343x_gpt_clksel[] = { - { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, - { .parent = &sys_ck, .rates = gpt_sys_rates }, - { .parent = NULL} -}; - -static struct clk gpt10_fck = { - .name = "gpt10_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &sys_ck, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_GPT10_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "core_l4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt11_fck = { - .name = "gpt11_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &sys_ck, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_GPT11_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "core_l4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk cpefuse_fck = { - .name = "cpefuse_fck", - .ops = &clkops_omap2_dflt, - .parent = &sys_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), - .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk ts_fck = { - .name = "ts_fck", - .ops = &clkops_omap2_dflt, - .parent = &omap_32k_fck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), - .enable_bit = OMAP3430ES2_EN_TS_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk usbtll_fck = { - .name = "usbtll_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll5_m2_ck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), - .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, - .recalc = &followparent_recalc, -}; - -/* CORE 96M FCLK-derived clocks */ - -static struct clk core_96m_fck = { - .name = "core_96m_fck", - .ops = &clkops_null, - .parent = &omap_96m_fck, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mmchs3_fck = { - .name = "mmchs3_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mmchs2_fck = { - .name = "mmchs2_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MMC2_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mspro_fck = { - .name = "mspro_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MSPRO_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mmchs1_fck = { - .name = "mmchs1_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MMC1_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk i2c3_fck = { - .name = "i2c3_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_I2C3_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk i2c2_fck = { - .name = "i2c2_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_I2C2_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk i2c1_fck = { - .name = "i2c1_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_I2C1_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -/* - * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; - * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. - */ -static const struct clksel_rate common_mcbsp_96m_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel mcbsp_15_clksel[] = { - { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, - { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, - { .parent = NULL } -}; - -static struct clk mcbsp5_fck = { - .name = "mcbsp5_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, - .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), - .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, - .clksel = mcbsp_15_clksel, - .clkdm_name = "core_l4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp1_fck = { - .name = "mcbsp1_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, - .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, - .clksel = mcbsp_15_clksel, - .clkdm_name = "core_l4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* CORE_48M_FCK-derived clocks */ - -static struct clk core_48m_fck = { - .name = "core_48m_fck", - .ops = &clkops_null, - .parent = &omap_48m_fck, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcspi4_fck = { - .name = "mcspi4_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, - .recalc = &followparent_recalc, - .clkdm_name = "core_l4_clkdm", -}; - -static struct clk mcspi3_fck = { - .name = "mcspi3_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, - .recalc = &followparent_recalc, - .clkdm_name = "core_l4_clkdm", -}; - -static struct clk mcspi2_fck = { - .name = "mcspi2_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, - .recalc = &followparent_recalc, - .clkdm_name = "core_l4_clkdm", -}; - -static struct clk mcspi1_fck = { - .name = "mcspi1_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, - .recalc = &followparent_recalc, - .clkdm_name = "core_l4_clkdm", -}; - -static struct clk uart2_fck = { - .name = "uart2_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_UART2_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk uart1_fck = { - .name = "uart1_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_UART1_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk fshostusb_fck = { - .name = "fshostusb_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_48m_fck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, - .recalc = &followparent_recalc, -}; - -/* CORE_12M_FCK based clocks */ - -static struct clk core_12m_fck = { - .name = "core_12m_fck", - .ops = &clkops_null, - .parent = &omap_12m_fck, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk hdq_fck = { - .name = "hdq_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_12m_fck, - .clkdm_name = "core_l4_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_HDQ_SHIFT, - .recalc = &followparent_recalc, -}; - -/* DPLL3-derived clock */ - -static const struct clksel_rate ssi_ssr_corex2_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, - { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, - { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, - { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, - { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, - { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, - { .div = 0 } -}; - -static const struct clksel ssi_ssr_clksel[] = { - { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, - { .parent = NULL } -}; - -static struct clk ssi_ssr_fck_3430es1 = { - .name = "ssi_ssr_fck", - .ops = &clkops_omap2_dflt, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_SSI_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, - .clksel = ssi_ssr_clksel, - .clkdm_name = "core_l4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk ssi_ssr_fck_3430es2 = { - .name = "ssi_ssr_fck", - .ops = &clkops_omap3430es2_ssi_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = OMAP3430_EN_SSI_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, - .clksel = ssi_ssr_clksel, - .clkdm_name = "core_l4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk ssi_sst_fck_3430es1 = { - .name = "ssi_sst_fck", - .ops = &clkops_null, - .parent = &ssi_ssr_fck_3430es1, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk ssi_sst_fck_3430es2 = { - .name = "ssi_sst_fck", - .ops = &clkops_null, - .parent = &ssi_ssr_fck_3430es2, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; - - - -/* CORE_L3_ICK based clocks */ - -/* - * XXX must add clk_enable/clk_disable for these if standard code won't - * handle it - */ -static struct clk core_l3_ick = { - .name = "core_l3_ick", - .ops = &clkops_null, - .parent = &l3_ick, - .clkdm_name = "core_l3_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk hsotgusb_ick_3430es1 = { - .name = "hsotgusb_ick", - .ops = &clkops_omap2_iclk_dflt, - .parent = &core_l3_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, - .clkdm_name = "core_l3_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk hsotgusb_ick_3430es2 = { - .name = "hsotgusb_ick", - .ops = &clkops_omap3430es2_iclk_hsotgusb_wait, - .parent = &core_l3_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, - .clkdm_name = "core_l3_clkdm", - .recalc = &followparent_recalc, -}; - -/* This interface clock does not have a CM_AUTOIDLE bit */ -static struct clk sdrc_ick = { - .name = "sdrc_ick", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l3_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_SDRC_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l3_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpmc_fck = { - .name = "gpmc_fck", - .ops = &clkops_null, - .parent = &core_l3_ick, - .flags = ENABLE_ON_INIT, /* huh? */ - .clkdm_name = "core_l3_clkdm", - .recalc = &followparent_recalc, -}; - -/* SECURITY_L3_ICK based clocks */ - -static struct clk security_l3_ick = { - .name = "security_l3_ick", - .ops = &clkops_null, - .parent = &l3_ick, - .recalc = &followparent_recalc, -}; - -static struct clk pka_ick = { - .name = "pka_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &security_l3_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP3430_EN_PKA_SHIFT, - .recalc = &followparent_recalc, -}; - -/* CORE_L4_ICK based clocks */ - -static struct clk core_l4_ick = { - .name = "core_l4_ick", - .ops = &clkops_null, - .parent = &l4_ick, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk usbtll_ick = { - .name = "usbtll_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), - .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mmchs3_ick = { - .name = "mmchs3_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -/* Intersystem Communication Registers - chassis mode only */ -static struct clk icr_ick = { - .name = "icr_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_ICR_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk aes2_ick = { - .name = "aes2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_AES2_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk sha12_ick = { - .name = "sha12_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_SHA12_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk des2_ick = { - .name = "des2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_DES2_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mmchs2_ick = { - .name = "mmchs2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MMC2_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mmchs1_ick = { - .name = "mmchs1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MMC1_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mspro_ick = { - .name = "mspro_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MSPRO_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk hdq_ick = { - .name = "hdq_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_HDQ_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcspi4_ick = { - .name = "mcspi4_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcspi3_ick = { - .name = "mcspi3_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcspi2_ick = { - .name = "mcspi2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcspi1_ick = { - .name = "mcspi1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk i2c3_ick = { - .name = "i2c3_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_I2C3_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk i2c2_ick = { - .name = "i2c2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_I2C2_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk i2c1_ick = { - .name = "i2c1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_I2C1_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk uart2_ick = { - .name = "uart2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_UART2_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk uart1_ick = { - .name = "uart1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_UART1_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt11_ick = { - .name = "gpt11_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_GPT11_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt10_ick = { - .name = "gpt10_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_GPT10_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp5_ick = { - .name = "mcbsp5_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp1_ick = { - .name = "mcbsp1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk fac_ick = { - .name = "fac_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mailboxes_ick = { - .name = "mailboxes_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk omapctrl_ick = { - .name = "omapctrl_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, - .flags = ENABLE_ON_INIT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -/* SSI_L4_ICK based clocks */ - -static struct clk ssi_l4_ick = { - .name = "ssi_l4_ick", - .ops = &clkops_null, - .parent = &l4_ick, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk ssi_ick_3430es1 = { - .name = "ssi_ick", - .ops = &clkops_omap2_iclk_dflt, - .parent = &ssi_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_SSI_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk ssi_ick_3430es2 = { - .name = "ssi_ick", - .ops = &clkops_omap3430es2_iclk_ssi_wait, - .parent = &ssi_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430_EN_SSI_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -/* REVISIT: Technically the TRM claims that this is CORE_CLK based, - * but l4_ick makes more sense to me */ - -static const struct clksel usb_l4_clksel[] = { - { .parent = &l4_ick, .rates = div2_rates }, - { .parent = NULL }, -}; - -static struct clk usb_l4_ick = { - .name = "usb_l4_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ick, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, - .clksel = usb_l4_clksel, - .clkdm_name = "core_l4_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* SECURITY_L4_ICK2 based clocks */ - -static struct clk security_l4_ick2 = { - .name = "security_l4_ick2", - .ops = &clkops_null, - .parent = &l4_ick, - .recalc = &followparent_recalc, -}; - -static struct clk aes1_ick = { - .name = "aes1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &security_l4_ick2, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP3430_EN_AES1_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk rng_ick = { - .name = "rng_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &security_l4_ick2, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP3430_EN_RNG_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk sha11_ick = { - .name = "sha11_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &security_l4_ick2, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP3430_EN_SHA11_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk des1_ick = { - .name = "des1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &security_l4_ick2, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), - .enable_bit = OMAP3430_EN_DES1_SHIFT, - .recalc = &followparent_recalc, -}; - -/* DSS */ -static struct clk dss1_alwon_fck_3430es1 = { - .name = "dss1_alwon_fck", - .ops = &clkops_omap2_dflt, - .parent = &dpll4_m4x2_ck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_DSS1_SHIFT, - .clkdm_name = "dss_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk dss1_alwon_fck_3430es2 = { - .name = "dss1_alwon_fck", - .ops = &clkops_omap3430es2_dss_usbhost_wait, - .parent = &dpll4_m4x2_ck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_DSS1_SHIFT, - .clkdm_name = "dss_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk dss_tv_fck = { - .name = "dss_tv_fck", - .ops = &clkops_omap2_dflt, - .parent = &omap_54m_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_TV_SHIFT, - .clkdm_name = "dss_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk dss_96m_fck = { - .name = "dss_96m_fck", - .ops = &clkops_omap2_dflt, - .parent = &omap_96m_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_TV_SHIFT, - .clkdm_name = "dss_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk dss2_alwon_fck = { - .name = "dss2_alwon_fck", - .ops = &clkops_omap2_dflt, - .parent = &sys_ck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_DSS2_SHIFT, - .clkdm_name = "dss_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk dss_ick_3430es1 = { - /* Handles both L3 and L4 clocks */ - .name = "dss_ick", - .ops = &clkops_omap2_iclk_dflt, - .parent = &l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, - .clkdm_name = "dss_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk dss_ick_3430es2 = { - /* Handles both L3 and L4 clocks */ - .name = "dss_ick", - .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait, - .parent = &l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, - .clkdm_name = "dss_clkdm", - .recalc = &followparent_recalc, -}; - -/* CAM */ - -static struct clk cam_mclk = { - .name = "cam_mclk", - .ops = &clkops_omap2_dflt, - .parent = &dpll4_m5x2_ck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_CAM_SHIFT, - .clkdm_name = "cam_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk cam_ick = { - /* Handles both L3 and L4 clocks */ - .name = "cam_ick", - .ops = &clkops_omap2_iclk_dflt, - .parent = &l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_CAM_SHIFT, - .clkdm_name = "cam_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk csi2_96m_fck = { - .name = "csi2_96m_fck", - .ops = &clkops_omap2_dflt, - .parent = &core_96m_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_CSI2_SHIFT, - .clkdm_name = "cam_clkdm", - .recalc = &followparent_recalc, -}; - -/* USBHOST - 3430ES2 only */ - -static struct clk usbhost_120m_fck = { - .name = "usbhost_120m_fck", - .ops = &clkops_omap2_dflt, - .parent = &dpll5_m2_ck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), - .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, - .clkdm_name = "usbhost_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk usbhost_48m_fck = { - .name = "usbhost_48m_fck", - .ops = &clkops_omap3430es2_dss_usbhost_wait, - .parent = &omap_48m_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), - .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, - .clkdm_name = "usbhost_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk usbhost_ick = { - /* Handles both L3 and L4 clocks */ - .name = "usbhost_ick", - .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait, - .parent = &l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), - .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, - .clkdm_name = "usbhost_clkdm", - .recalc = &followparent_recalc, -}; - -/* WKUP */ - -static const struct clksel_rate usim_96m_rates[] = { - { .div = 2, .val = 3, .flags = RATE_IN_3XXX }, - { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, - { .div = 8, .val = 5, .flags = RATE_IN_3XXX }, - { .div = 10, .val = 6, .flags = RATE_IN_3XXX }, - { .div = 0 }, -}; - -static const struct clksel_rate usim_120m_rates[] = { - { .div = 4, .val = 7, .flags = RATE_IN_3XXX }, - { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, - { .div = 16, .val = 9, .flags = RATE_IN_3XXX }, - { .div = 20, .val = 10, .flags = RATE_IN_3XXX }, - { .div = 0 }, -}; - -static const struct clksel usim_clksel[] = { - { .parent = &omap_96m_fck, .rates = usim_96m_rates }, - { .parent = &dpll5_m2_ck, .rates = usim_120m_rates }, - { .parent = &sys_ck, .rates = div2_rates }, - { .parent = NULL }, -}; - -/* 3430ES2 only */ -static struct clk usim_fck = { - .name = "usim_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, - .clksel = usim_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ -static struct clk gpt1_fck = { - .name = "gpt1_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPT1_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "wkup_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk wkup_32k_fck = { - .name = "wkup_32k_fck", - .ops = &clkops_null, - .parent = &omap_32k_fck, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio1_dbck = { - .name = "gpio1_dbck", - .ops = &clkops_omap2_dflt, - .parent = &wkup_32k_fck, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPIO1_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk wdt2_fck = { - .name = "wdt2_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &wkup_32k_fck, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_WDT2_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk wkup_l4_ick = { - .name = "wkup_l4_ick", - .ops = &clkops_null, - .parent = &sys_ck, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -/* 3430ES2 only */ -/* Never specifically named in the TRM, so we have to infer a likely name */ -static struct clk usim_ick = { - .name = "usim_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk wdt2_ick = { - .name = "wdt2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_WDT2_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk wdt1_ick = { - .name = "wdt1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_WDT1_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio1_ick = { - .name = "gpio1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPIO1_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk omap_32ksync_ick = { - .name = "omap_32ksync_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -/* XXX This clock no longer exists in 3430 TRM rev F */ -static struct clk gpt12_ick = { - .name = "gpt12_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT12_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt1_ick = { - .name = "gpt1_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT1_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - - - -/* PER clock domain */ - -static struct clk per_96m_fck = { - .name = "per_96m_fck", - .ops = &clkops_null, - .parent = &omap_96m_alwon_fck, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk per_48m_fck = { - .name = "per_48m_fck", - .ops = &clkops_null, - .parent = &omap_48m_fck, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk uart3_fck = { - .name = "uart3_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_48m_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_UART3_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk uart4_fck = { - .name = "uart4_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_48m_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3630_EN_UART4_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk uart4_fck_am35xx = { - .name = "uart4_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &core_48m_fck, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), - .enable_bit = AM35XX_EN_UART4_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt2_fck = { - .name = "gpt2_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPT2_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt3_fck = { - .name = "gpt3_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPT3_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt4_fck = { - .name = "gpt4_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPT4_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt5_fck = { - .name = "gpt5_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPT5_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt6_fck = { - .name = "gpt6_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPT6_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt7_fck = { - .name = "gpt7_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPT7_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt8_fck = { - .name = "gpt8_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPT8_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt9_fck = { - .name = "gpt9_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPT9_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), - .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, - .clksel = omap343x_gpt_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk per_32k_alwon_fck = { - .name = "per_32k_alwon_fck", - .ops = &clkops_null, - .parent = &omap_32k_fck, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio6_dbck = { - .name = "gpio6_dbck", - .ops = &clkops_omap2_dflt, - .parent = &per_32k_alwon_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPIO6_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio5_dbck = { - .name = "gpio5_dbck", - .ops = &clkops_omap2_dflt, - .parent = &per_32k_alwon_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPIO5_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio4_dbck = { - .name = "gpio4_dbck", - .ops = &clkops_omap2_dflt, - .parent = &per_32k_alwon_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPIO4_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio3_dbck = { - .name = "gpio3_dbck", - .ops = &clkops_omap2_dflt, - .parent = &per_32k_alwon_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPIO3_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio2_dbck = { - .name = "gpio2_dbck", - .ops = &clkops_omap2_dflt, - .parent = &per_32k_alwon_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_GPIO2_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk wdt3_fck = { - .name = "wdt3_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &per_32k_alwon_fck, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_WDT3_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk per_l4_ick = { - .name = "per_l4_ick", - .ops = &clkops_null, - .parent = &l4_ick, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio6_ick = { - .name = "gpio6_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPIO6_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio5_ick = { - .name = "gpio5_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPIO5_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio4_ick = { - .name = "gpio4_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPIO4_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio3_ick = { - .name = "gpio3_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPIO3_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpio2_ick = { - .name = "gpio2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPIO2_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk wdt3_ick = { - .name = "wdt3_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_WDT3_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk uart3_ick = { - .name = "uart3_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_UART3_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk uart4_ick = { - .name = "uart4_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3630_EN_UART4_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt9_ick = { - .name = "gpt9_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT9_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt8_ick = { - .name = "gpt8_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT8_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt7_ick = { - .name = "gpt7_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT7_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt6_ick = { - .name = "gpt6_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT6_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt5_ick = { - .name = "gpt5_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT5_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt4_ick = { - .name = "gpt4_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT4_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt3_ick = { - .name = "gpt3_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT3_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk gpt2_ick = { - .name = "gpt2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_GPT2_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp2_ick = { - .name = "mcbsp2_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp3_ick = { - .name = "mcbsp3_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp4_ick = { - .name = "mcbsp4_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), - .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, - .clkdm_name = "per_clkdm", - .recalc = &followparent_recalc, -}; - -static const struct clksel mcbsp_234_clksel[] = { - { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, - { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, - { .parent = NULL } -}; - -static struct clk mcbsp2_fck = { - .name = "mcbsp2_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, - .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), - .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, - .clksel = mcbsp_234_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp3_fck = { - .name = "mcbsp3_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, - .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), - .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, - .clksel = mcbsp_234_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp4_fck = { - .name = "mcbsp4_fck", - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, - .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), - .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, - .clksel = mcbsp_234_clksel, - .clkdm_name = "per_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* EMU clocks */ - -/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ - -static const struct clksel_rate emu_src_sys_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, - { .div = 0 }, -}; - -static const struct clksel_rate emu_src_core_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, - { .div = 0 }, -}; - -static const struct clksel_rate emu_src_per_rates[] = { - { .div = 1, .val = 2, .flags = RATE_IN_3XXX }, - { .div = 0 }, -}; - -static const struct clksel_rate emu_src_mpu_rates[] = { - { .div = 1, .val = 3, .flags = RATE_IN_3XXX }, - { .div = 0 }, -}; - -static const struct clksel emu_src_clksel[] = { - { .parent = &sys_ck, .rates = emu_src_sys_rates }, - { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, - { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, - { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, - { .parent = NULL }, -}; - -/* - * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only - * to switch the source of some of the EMU clocks. - * XXX Are there CLKEN bits for these EMU clks? - */ -static struct clk emu_src_ck = { - .name = "emu_src_ck", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_MUX_CTRL_MASK, - .clksel = emu_src_clksel, - .clkdm_name = "emu_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate pclk_emu_rates[] = { - { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, - { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, - { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, - { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, - { .div = 0 }, -}; - -static const struct clksel pclk_emu_clksel[] = { - { .parent = &emu_src_ck, .rates = pclk_emu_rates }, - { .parent = NULL }, -}; - -static struct clk pclk_fck = { - .name = "pclk_fck", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, - .clksel = pclk_emu_clksel, - .clkdm_name = "emu_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate pclkx2_emu_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, - { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, - { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, - { .div = 0 }, -}; - -static const struct clksel pclkx2_emu_clksel[] = { - { .parent = &emu_src_ck, .rates = pclkx2_emu_rates }, - { .parent = NULL }, -}; - -static struct clk pclkx2_fck = { - .name = "pclkx2_fck", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, - .clksel = pclkx2_emu_clksel, - .clkdm_name = "emu_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel atclk_emu_clksel[] = { - { .parent = &emu_src_ck, .rates = div2_rates }, - { .parent = NULL }, -}; - -static struct clk atclk_fck = { - .name = "atclk_fck", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, - .clksel = atclk_emu_clksel, - .clkdm_name = "emu_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static struct clk traceclk_src_fck = { - .name = "traceclk_src_fck", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, - .clksel = emu_src_clksel, - .clkdm_name = "emu_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate traceclk_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, - { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, - { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, - { .div = 0 }, -}; - -static const struct clksel traceclk_clksel[] = { - { .parent = &traceclk_src_fck, .rates = traceclk_rates }, - { .parent = NULL }, -}; - -static struct clk traceclk_fck = { - .name = "traceclk_fck", - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), - .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, - .clksel = traceclk_clksel, - .clkdm_name = "emu_clkdm", - .recalc = &omap2_clksel_recalc, -}; - -/* SR clocks */ - -/* SmartReflex fclk (VDD1) */ -static struct clk smartreflex_mpu_iva_fck = { - .name = "smartreflex_mpu_iva_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &sys_ck, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_SR1_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -/* SmartReflex fclk (VDD2) */ -static struct clk smartreflex_core_fck = { - .name = "smartreflex_core_fck", - .ops = &clkops_omap2_dflt_wait, - .parent = &sys_ck, - .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), - .enable_bit = OMAP3430_EN_SR2_SHIFT, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk sr_l4_ick = { - .name = "sr_l4_ick", - .ops = &clkops_null, /* RMK: missing? */ - .parent = &l4_ick, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -/* SECURE_32K_FCK clocks */ - -static struct clk gpt12_fck = { - .name = "gpt12_fck", - .ops = &clkops_null, - .parent = &secure_32k_fck, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk wdt1_fck = { - .name = "wdt1_fck", - .ops = &clkops_null, - .parent = &secure_32k_fck, - .clkdm_name = "wkup_clkdm", - .recalc = &followparent_recalc, -}; - -/* Clocks for AM35XX */ -static struct clk ipss_ick = { - .name = "ipss_ick", - .ops = &clkops_am35xx_ipss_wait, - .parent = &core_l3_ick, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = AM35XX_EN_IPSS_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk emac_ick = { - .name = "emac_ick", - .ops = &clkops_am35xx_ipss_module_wait, - .parent = &ipss_ick, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), - .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk rmii_ck = { - .name = "rmii_ck", - .ops = &clkops_null, - .rate = 50000000, -}; - -static struct clk emac_fck = { - .name = "emac_fck", - .ops = &clkops_omap2_dflt, - .parent = &rmii_ck, - .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), - .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk hsotgusb_ick_am35xx = { - .name = "hsotgusb_ick", - .ops = &clkops_am35xx_ipss_module_wait, - .parent = &ipss_ick, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), - .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk hsotgusb_fck_am35xx = { - .name = "hsotgusb_fck", - .ops = &clkops_omap2_dflt, - .parent = &sys_ck, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), - .enable_bit = AM35XX_USBOTG_FCLK_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk hecc_ck = { - .name = "hecc_ck", - .ops = &clkops_am35xx_ipss_module_wait, - .parent = &sys_ck, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), - .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk vpfe_ick = { - .name = "vpfe_ick", - .ops = &clkops_am35xx_ipss_module_wait, - .parent = &ipss_ick, - .clkdm_name = "core_l3_clkdm", - .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), - .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT, - .recalc = &followparent_recalc, -}; - -static struct clk pclk_ck = { - .name = "pclk_ck", - .ops = &clkops_null, - .rate = 27000000, -}; - -static struct clk vpfe_fck = { - .name = "vpfe_fck", - .ops = &clkops_omap2_dflt, - .parent = &pclk_ck, - .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), - .enable_bit = AM35XX_VPFE_FCLK_SHIFT, - .recalc = &followparent_recalc, -}; - -/* - * The UART1/2 functional clock acts as the functional clock for - * UART4. No separate fclk control available. XXX Well now we have a - * uart4_fck that is apparently used as the UART4 functional clock, - * but it also seems that uart1_fck or uart2_fck are still needed, at - * least for UART4 softresets to complete. This really needs - * clarification. - */ -static struct clk uart4_ick_am35xx = { - .name = "uart4_ick", - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), - .enable_bit = AM35XX_EN_UART4_SHIFT, - .clkdm_name = "core_l4_clkdm", - .recalc = &followparent_recalc, -}; - -static struct clk dummy_apb_pclk = { - .name = "apb_pclk", - .ops = &clkops_null, -}; - -/* - * clkdev - */ - -static struct omap_clk omap3xxx_clks[] = { - CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX), - CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), - CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), - CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), - CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_3XXX), - CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_3XXX), - CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), - CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), - CLK("twl", "fck", &osc_sys_ck, CK_3XXX), - CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), - CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), - CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), - CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), - CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), - CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX), - CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX), - CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX), - CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX), - CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX), - CLK(NULL, "core_ck", &core_ck, CK_3XXX), - CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX), - CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX), - CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX), - CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX), - CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX), - CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), - CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), - CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX), - CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX), - CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX), - CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX), - CLK(NULL, "omap_96m_alwon_fck_3630", &omap_96m_alwon_fck_3630, CK_36XX), - CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX), - CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX), - CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX), - CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX), - CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX), - CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX), - CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX), - CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX), - CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX), - CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX), - CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX), - CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX), - CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX), - CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX), - CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX), - CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), - CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), - CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX), - CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX), - CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX), - CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX), - CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), - CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), - CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), - CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), - CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX), - CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX), - CLK(NULL, "l3_ick", &l3_ick, CK_3XXX), - CLK(NULL, "l4_ick", &l4_ick, CK_3XXX), - CLK(NULL, "rm_ick", &rm_ick, CK_3XXX), - CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), - CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), - CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), - CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), - CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), - CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), - CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX), - CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX), - CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX), - CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX), - CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX), - CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("usbhs_tll", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), - CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX), - CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX), - CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX), - CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX), - CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX), - CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX), - CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX), - CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX), - CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX), - CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX), - CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX), - CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX), - CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX), - CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX), - CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX), - CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), - CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), - CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), - CLK(NULL, "hdq_fck", &hdq_fck, CK_3XXX), - CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), - CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX), - CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), - CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX), - CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX), - CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), - CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), - CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1, CK_3430ES1), - CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), - CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX), - CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX), - CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX), - CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX), - CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), - CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("usbhs_tll", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "mmchs3_ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), - CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), - CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX), - CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX), - CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX), - CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX), - CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_3XXX), - CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_3XXX), - CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX), - CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), - CLK(NULL, "hdq_ick", &hdq_ick, CK_3XXX), - CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), - CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX), - CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX), - CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX), - CLK(NULL, "mcspi4_ick", &mcspi4_ick, CK_3XXX), - CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_3XXX), - CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_3XXX), - CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_3XXX), - CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX), - CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX), - CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX), - CLK(NULL, "i2c3_ick", &i2c3_ick, CK_3XXX), - CLK(NULL, "i2c2_ick", &i2c2_ick, CK_3XXX), - CLK(NULL, "i2c1_ick", &i2c1_ick, CK_3XXX), - CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX), - CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX), - CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX), - CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX), - CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX), - CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX), - CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_3XXX), - CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_3XXX), - CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), - CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX), - CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX), - CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX), - CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), - CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX), - CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), - CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX), - CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX), - CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX), - CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX), - CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX), - CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), - CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX), - CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX), - CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX), - CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1), - CLK(NULL, "dss_ick", &dss_ick_3430es1, CK_3430ES1), - CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "dss_ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), - CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX), - CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX), - CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("usbhs_omap", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "utmi_p1_gfclk", &dummy_ck, CK_3XXX), - CLK(NULL, "utmi_p2_gfclk", &dummy_ck, CK_3XXX), - CLK(NULL, "xclk60mhsp1_ck", &dummy_ck, CK_3XXX), - CLK(NULL, "xclk60mhsp2_ck", &dummy_ck, CK_3XXX), - CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX), - CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX), - CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), - CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), - CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), - CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), - CLK(NULL, "init_60m_fclk", &dummy_ck, CK_3XXX), - CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX), - CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), - CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), - CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX), - CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX), - CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX), - CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX), - CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX), - CLK(NULL, "wdt2_ick", &wdt2_ick, CK_3XXX), - CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX), - CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX), - CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), - CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), - CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), - CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), - CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), - CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), - CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX), - CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_AM35XX), - CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), - CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), - CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), - CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX), - CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX), - CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX), - CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX), - CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX), - CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX), - CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX), - CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX), - CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX), - CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX), - CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX), - CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX), - CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX), - CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX), - CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX), - CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX), - CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX), - CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX), - CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX), - CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX), - CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX), - CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX), - CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX), - CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX), - CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX), - CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX), - CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX), - CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX), - CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX), - CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX), - CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX), - CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX), - CLK(NULL, "mcbsp4_ick", &mcbsp2_ick, CK_3XXX), - CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_3XXX), - CLK(NULL, "mcbsp2_ick", &mcbsp4_ick, CK_3XXX), - CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX), - CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX), - CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX), - CLK(NULL, "emu_src_ck", &emu_src_ck, CK_3XXX), - CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX), - CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX), - CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX), - CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX), - CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX), - CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX), - CLK(NULL, "smartreflex_mpu_iva_fck", &smartreflex_mpu_iva_fck, CK_34XX | CK_36XX), - CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_34XX | CK_36XX), - CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX), - CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX), - CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX), - CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX), - CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), - CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), - CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), - CLK(NULL, "emac_ick", &emac_ick, CK_AM35XX), - CLK(NULL, "emac_fck", &emac_fck, CK_AM35XX), - CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX), - CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX), - CLK(NULL, "vpfe_ick", &emac_ick, CK_AM35XX), - CLK(NULL, "vpfe_fck", &emac_fck, CK_AM35XX), - CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), - CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), - CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX), - CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx, CK_AM35XX), - CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), - CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), - CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX), - CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX), - CLK(NULL, "cpufreq_ck", &dpll1_ck, CK_3XXX), -}; - - -int __init omap3xxx_clk_init(void) -{ - struct omap_clk *c; - u32 cpu_clkflg = 0; - - if (soc_is_am35xx()) { - cpu_mask = RATE_IN_34XX; - cpu_clkflg = CK_AM35XX; - } else if (cpu_is_omap3630()) { - cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); - cpu_clkflg = CK_36XX; - } else if (cpu_is_ti816x()) { - cpu_mask = RATE_IN_TI816X; - cpu_clkflg = CK_TI816X; - } else if (soc_is_am33xx()) { - cpu_mask = RATE_IN_AM33XX; - } else if (cpu_is_ti814x()) { - cpu_mask = RATE_IN_TI814X; - } else if (cpu_is_omap34xx()) { - if (omap_rev() == OMAP3430_REV_ES1_0) { - cpu_mask = RATE_IN_3430ES1; - cpu_clkflg = CK_3430ES1; - } else { - /* - * Assume that anything that we haven't matched yet - * has 3430ES2-type clocks. - */ - cpu_mask = RATE_IN_3430ES2PLUS; - cpu_clkflg = CK_3430ES2PLUS; - } - } else { - WARN(1, "clock: could not identify OMAP3 variant\n"); - } - - if (omap3_has_192mhz_clk()) - omap_96m_alwon_fck = omap_96m_alwon_fck_3630; - - if (cpu_is_omap3630()) { - /* - * XXX This type of dynamic rewriting of the clock tree is - * deprecated and should be revised soon. - * - * For 3630: override clkops_omap2_dflt_wait for the - * clocks affected from PWRDN reset Limitation - */ - dpll3_m3x2_ck.ops = - &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; - dpll4_m2x2_ck.ops = - &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; - dpll4_m3x2_ck.ops = - &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; - dpll4_m4x2_ck.ops = - &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; - dpll4_m5x2_ck.ops = - &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; - dpll4_m6x2_ck.ops = - &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; - } - - /* - * XXX This type of dynamic rewriting of the clock tree is - * deprecated and should be revised soon. - */ - if (cpu_is_omap3630()) - dpll4_dd = dpll4_dd_3630; - else - dpll4_dd = dpll4_dd_34xx; - - clk_init(&omap2_clk_functions); - - for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); - c++) - clk_preinit(c->lk.clk); - - for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); - c++) - if (c->cpu & cpu_clkflg) { - clkdev_add(&c->lk); - clk_register(c->lk.clk); - omap2_init_clk_clkdm(c->lk.clk); - } - - /* Disable autoidle on all clocks; let the PM code enable it later */ - omap_clk_disable_autoidle_all(); - - recalculate_root_clocks(); - - pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", - (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, - (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); - - /* - * Only enable those clocks we will need, let the drivers - * enable other clocks as necessary - */ - clk_enable_init_clocks(); - - /* - * Lock DPLL5 -- here only until other device init code can - * handle this - */ - if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0)) - omap3_clk_lock_dpll5(); - - /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ - sdrc_ick_p = clk_get(NULL, "sdrc_ick"); - arm_fck_p = clk_get(NULL, "arm_fck"); - - return 0; -} diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c deleted file mode 100644 index dc92e5f4e78e..000000000000 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ /dev/null @@ -1,3402 +0,0 @@ -/* - * OMAP4 Clock data - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * Copyright (C) 2009-2010 Nokia Corporation - * - * Paul Walmsley (paul@pwsan.com) - * Rajendra Nayak (rnayak@ti.com) - * Benoit Cousson (b-cousson@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * XXX Some of the ES1 clocks have been removed/changed; once support - * is added for discriminating clocks by ES level, these should be added back - * in. - */ - -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/clk.h> -#include <linux/io.h> - -#include <plat/clkdev_omap.h> - -#include "soc.h" -#include "iomap.h" -#include "clock.h" -#include "clock44xx.h" -#include "cm1_44xx.h" -#include "cm2_44xx.h" -#include "cm-regbits-44xx.h" -#include "prm44xx.h" -#include "prm-regbits-44xx.h" -#include "control.h" -#include "scrm44xx.h" - -/* OMAP4 modulemode control */ -#define OMAP4430_MODULEMODE_HWCTRL 0 -#define OMAP4430_MODULEMODE_SWCTRL 1 - -/* Root clocks */ - -static struct clk extalt_clkin_ck = { - .name = "extalt_clkin_ck", - .rate = 59000000, - .ops = &clkops_null, -}; - -static struct clk pad_clks_ck = { - .name = "pad_clks_ck", - .rate = 12000000, - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CLKSEL_ABE, - .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT, -}; - -static struct clk pad_slimbus_core_clks_ck = { - .name = "pad_slimbus_core_clks_ck", - .rate = 12000000, - .ops = &clkops_null, -}; - -static struct clk secure_32k_clk_src_ck = { - .name = "secure_32k_clk_src_ck", - .rate = 32768, - .ops = &clkops_null, -}; - -static struct clk slimbus_clk = { - .name = "slimbus_clk", - .rate = 12000000, - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CLKSEL_ABE, - .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT, -}; - -static struct clk sys_32k_ck = { - .name = "sys_32k_ck", - .clkdm_name = "prm_clkdm", - .rate = 32768, - .ops = &clkops_null, -}; - -static struct clk virt_12000000_ck = { - .name = "virt_12000000_ck", - .ops = &clkops_null, - .rate = 12000000, -}; - -static struct clk virt_13000000_ck = { - .name = "virt_13000000_ck", - .ops = &clkops_null, - .rate = 13000000, -}; - -static struct clk virt_16800000_ck = { - .name = "virt_16800000_ck", - .ops = &clkops_null, - .rate = 16800000, -}; - -static struct clk virt_27000000_ck = { - .name = "virt_27000000_ck", - .ops = &clkops_null, - .rate = 27000000, -}; - -static struct clk virt_38400000_ck = { - .name = "virt_38400000_ck", - .ops = &clkops_null, - .rate = 38400000, -}; - -static const struct clksel_rate div_1_5_rates[] = { - { .div = 1, .val = 5, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel_rate div_1_6_rates[] = { - { .div = 1, .val = 6, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel_rate div_1_7_rates[] = { - { .div = 1, .val = 7, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel sys_clkin_sel[] = { - { .parent = &virt_12000000_ck, .rates = div_1_1_rates }, - { .parent = &virt_13000000_ck, .rates = div_1_2_rates }, - { .parent = &virt_16800000_ck, .rates = div_1_3_rates }, - { .parent = &virt_19200000_ck, .rates = div_1_4_rates }, - { .parent = &virt_26000000_ck, .rates = div_1_5_rates }, - { .parent = &virt_27000000_ck, .rates = div_1_6_rates }, - { .parent = &virt_38400000_ck, .rates = div_1_7_rates }, - { .parent = NULL }, -}; - -static struct clk sys_clkin_ck = { - .name = "sys_clkin_ck", - .rate = 38400000, - .clksel = sys_clkin_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_SYS_CLKSEL, - .clksel_mask = OMAP4430_SYS_CLKSEL_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk tie_low_clock_ck = { - .name = "tie_low_clock_ck", - .rate = 0, - .ops = &clkops_null, -}; - -static struct clk utmi_phy_clkout_ck = { - .name = "utmi_phy_clkout_ck", - .rate = 60000000, - .ops = &clkops_null, -}; - -static struct clk xclk60mhsp1_ck = { - .name = "xclk60mhsp1_ck", - .rate = 60000000, - .ops = &clkops_null, -}; - -static struct clk xclk60mhsp2_ck = { - .name = "xclk60mhsp2_ck", - .rate = 60000000, - .ops = &clkops_null, -}; - -static struct clk xclk60motg_ck = { - .name = "xclk60motg_ck", - .rate = 60000000, - .ops = &clkops_null, -}; - -/* Module clocks and DPLL outputs */ - -static const struct clksel abe_dpll_bypass_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk abe_dpll_bypass_clk_mux_ck = { - .name = "abe_dpll_bypass_clk_mux_ck", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk abe_dpll_refclk_mux_ck = { - .name = "abe_dpll_refclk_mux_ck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL, - .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -/* DPLL_ABE */ -static struct dpll_data dpll_abe_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, - .clk_bypass = &abe_dpll_bypass_clk_mux_ck, - .clk_ref = &abe_dpll_refclk_mux_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - - -static struct clk dpll_abe_ck = { - .name = "dpll_abe_ck", - .parent = &abe_dpll_refclk_mux_ck, - .dpll_data = &dpll_abe_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap4_dpll_regm4xen_recalc, - .round_rate = &omap4_dpll_regm4xen_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -static struct clk dpll_abe_x2_ck = { - .name = "dpll_abe_x2_ck", - .parent = &dpll_abe_ck, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, - .flags = CLOCK_CLKOUTX2, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap3_clkoutx2_recalc, -}; - -static const struct clksel dpll_abe_m2x2_div[] = { - { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_abe_m2x2_ck = { - .name = "dpll_abe_m2x2_ck", - .parent = &dpll_abe_x2_ck, - .clksel = dpll_abe_m2x2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk abe_24m_fclk = { - .name = "abe_24m_fclk", - .parent = &dpll_abe_m2x2_ck, - .ops = &clkops_null, - .fixed_div = 8, - .recalc = &omap_fixed_divisor_recalc, -}; - -static const struct clksel_rate div3_1to4_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 4, .val = 2, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel abe_clk_div[] = { - { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, -}; - -static struct clk abe_clk = { - .name = "abe_clk", - .parent = &dpll_abe_m2x2_ck, - .clksel = abe_clk_div, - .clksel_reg = OMAP4430_CM_CLKSEL_ABE, - .clksel_mask = OMAP4430_CLKSEL_OPP_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel_rate div2_1to2_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel aess_fclk_div[] = { - { .parent = &abe_clk, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; - -static struct clk aess_fclk = { - .name = "aess_fclk", - .parent = &abe_clk, - .clksel = aess_fclk_div, - .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_abe_m3x2_ck = { - .name = "dpll_abe_m3x2_ck", - .parent = &dpll_abe_x2_ck, - .clksel = dpll_abe_m2x2_div, - .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE, - .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel core_hsd_byp_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk core_hsd_byp_clk_mux_ck = { - .name = "core_hsd_byp_clk_mux_ck", - .parent = &sys_clkin_ck, - .clksel = core_hsd_byp_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, - .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -/* DPLL_CORE */ -static struct dpll_data dpll_core_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, - .clk_bypass = &core_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - - -static struct clk dpll_core_ck = { - .name = "dpll_core_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_core_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_core_dpll_ops, - .recalc = &omap3_dpll_recalc, -}; - -static struct clk dpll_core_x2_ck = { - .name = "dpll_core_x2_ck", - .parent = &dpll_core_ck, - .flags = CLOCK_CLKOUTX2, - .ops = &clkops_null, - .recalc = &omap3_clkoutx2_recalc, -}; - -static const struct clksel dpll_core_m6x2_div[] = { - { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_core_m6x2_ck = { - .name = "dpll_core_m6x2_ck", - .parent = &dpll_core_x2_ck, - .clksel = dpll_core_m6x2_div, - .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel dbgclk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk dbgclk_mux_ck = { - .name = "dbgclk_mux_ck", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static const struct clksel dpll_core_m2_div[] = { - { .parent = &dpll_core_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_core_m2_ck = { - .name = "dpll_core_m2_ck", - .parent = &dpll_core_ck, - .clksel = dpll_core_m2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk ddrphy_ck = { - .name = "ddrphy_ck", - .parent = &dpll_core_m2_ck, - .ops = &clkops_null, - .clkdm_name = "l3_emif_clkdm", - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk dpll_core_m5x2_ck = { - .name = "dpll_core_m5x2_ck", - .parent = &dpll_core_x2_ck, - .clksel = dpll_core_m6x2_div, - .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel div_core_div[] = { - { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; - -static struct clk div_core_ck = { - .name = "div_core_ck", - .parent = &dpll_core_m5x2_ck, - .clksel = div_core_div, - .clksel_reg = OMAP4430_CM_CLKSEL_CORE, - .clksel_mask = OMAP4430_CLKSEL_CORE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel_rate div4_1to8_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 4, .val = 2, .flags = RATE_IN_4430 }, - { .div = 8, .val = 3, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel div_iva_hs_clk_div[] = { - { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates }, - { .parent = NULL }, -}; - -static struct clk div_iva_hs_clk = { - .name = "div_iva_hs_clk", - .parent = &dpll_core_m5x2_ck, - .clksel = div_iva_hs_clk_div, - .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA, - .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk div_mpu_hs_clk = { - .name = "div_mpu_hs_clk", - .parent = &dpll_core_m5x2_ck, - .clksel = div_iva_hs_clk_div, - .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU, - .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_core_m4x2_ck = { - .name = "dpll_core_m4x2_ck", - .parent = &dpll_core_x2_ck, - .clksel = dpll_core_m6x2_div, - .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dll_clk_div_ck = { - .name = "dll_clk_div_ck", - .parent = &dpll_core_m4x2_ck, - .ops = &clkops_null, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; - -static const struct clksel dpll_abe_m2_div[] = { - { .parent = &dpll_abe_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_abe_m2_ck = { - .name = "dpll_abe_m2_ck", - .parent = &dpll_abe_ck, - .clksel = dpll_abe_m2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_core_m3x2_ck = { - .name = "dpll_core_m3x2_ck", - .parent = &dpll_core_x2_ck, - .clksel = dpll_core_m6x2_div, - .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, - .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, - .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, -}; - -static struct clk dpll_core_m7x2_ck = { - .name = "dpll_core_m7x2_ck", - .parent = &dpll_core_x2_ck, - .clksel = dpll_core_m6x2_div, - .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel iva_hsd_byp_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &div_iva_hs_clk, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk iva_hsd_byp_clk_mux_ck = { - .name = "iva_hsd_byp_clk_mux_ck", - .parent = &sys_clkin_ck, - .clksel = iva_hsd_byp_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, - .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -/* DPLL_IVA */ -static struct dpll_data dpll_iva_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, - .clk_bypass = &iva_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - - -static struct clk dpll_iva_ck = { - .name = "dpll_iva_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_iva_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -static struct clk dpll_iva_x2_ck = { - .name = "dpll_iva_x2_ck", - .parent = &dpll_iva_ck, - .flags = CLOCK_CLKOUTX2, - .ops = &clkops_null, - .recalc = &omap3_clkoutx2_recalc, -}; - -static const struct clksel dpll_iva_m4x2_div[] = { - { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_iva_m4x2_ck = { - .name = "dpll_iva_m4x2_ck", - .parent = &dpll_iva_x2_ck, - .clksel = dpll_iva_m4x2_div, - .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_iva_m5x2_ck = { - .name = "dpll_iva_m5x2_ck", - .parent = &dpll_iva_x2_ck, - .clksel = dpll_iva_m4x2_div, - .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -/* DPLL_MPU */ -static struct dpll_data dpll_mpu_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, - .clk_bypass = &div_mpu_hs_clk, - .clk_ref = &sys_clkin_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - - -static struct clk dpll_mpu_ck = { - .name = "dpll_mpu_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_mpu_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -static const struct clksel dpll_mpu_m2_div[] = { - { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_mpu_m2_ck = { - .name = "dpll_mpu_m2_ck", - .parent = &dpll_mpu_ck, - .clkdm_name = "cm_clkdm", - .clksel = dpll_mpu_m2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk per_hs_clk_div_ck = { - .name = "per_hs_clk_div_ck", - .parent = &dpll_abe_m3x2_ck, - .ops = &clkops_null, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; - -static const struct clksel per_hsd_byp_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk per_hsd_byp_clk_mux_ck = { - .name = "per_hsd_byp_clk_mux_ck", - .parent = &sys_clkin_ck, - .clksel = per_hsd_byp_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER, - .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -/* DPLL_PER */ -static struct dpll_data dpll_per_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, - .clk_bypass = &per_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - - -static struct clk dpll_per_ck = { - .name = "dpll_per_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_per_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -static const struct clksel dpll_per_m2_div[] = { - { .parent = &dpll_per_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_per_m2_ck = { - .name = "dpll_per_m2_ck", - .parent = &dpll_per_ck, - .clksel = dpll_per_m2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_per_x2_ck = { - .name = "dpll_per_x2_ck", - .parent = &dpll_per_ck, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, - .flags = CLOCK_CLKOUTX2, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap3_clkoutx2_recalc, -}; - -static const struct clksel dpll_per_m2x2_div[] = { - { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_per_m2x2_ck = { - .name = "dpll_per_m2x2_ck", - .parent = &dpll_per_x2_ck, - .clksel = dpll_per_m2x2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_per_m3x2_ck = { - .name = "dpll_per_m3x2_ck", - .parent = &dpll_per_x2_ck, - .clksel = dpll_per_m2x2_div, - .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, - .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER, - .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, -}; - -static struct clk dpll_per_m4x2_ck = { - .name = "dpll_per_m4x2_ck", - .parent = &dpll_per_x2_ck, - .clksel = dpll_per_m2x2_div, - .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_per_m5x2_ck = { - .name = "dpll_per_m5x2_ck", - .parent = &dpll_per_x2_ck, - .clksel = dpll_per_m2x2_div, - .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_per_m6x2_ck = { - .name = "dpll_per_m6x2_ck", - .parent = &dpll_per_x2_ck, - .clksel = dpll_per_m2x2_div, - .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_per_m7x2_ck = { - .name = "dpll_per_m7x2_ck", - .parent = &dpll_per_x2_ck, - .clksel = dpll_per_m2x2_div, - .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER, - .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk usb_hs_clk_div_ck = { - .name = "usb_hs_clk_div_ck", - .parent = &dpll_abe_m3x2_ck, - .ops = &clkops_null, - .fixed_div = 3, - .recalc = &omap_fixed_divisor_recalc, -}; - -/* DPLL_USB */ -static struct dpll_data dpll_usb_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, - .clk_bypass = &usb_hs_clk_div_ck, - .flags = DPLL_J_TYPE, - .clk_ref = &sys_clkin_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB, - .mult_mask = OMAP4430_DPLL_MULT_USB_MASK, - .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK, - .max_multiplier = 4095, - .max_divider = 256, - .min_divider = 1, -}; - - -static struct clk dpll_usb_ck = { - .name = "dpll_usb_ck", - .parent = &sys_clkin_ck, - .dpll_data = &dpll_usb_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .clkdm_name = "l3_init_clkdm", -}; - -static struct clk dpll_usb_clkdcoldo_ck = { - .name = "dpll_usb_clkdcoldo_ck", - .parent = &dpll_usb_ck, - .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &followparent_recalc, -}; - -static const struct clksel dpll_usb_m2_div[] = { - { .parent = &dpll_usb_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -static struct clk dpll_usb_m2_ck = { - .name = "dpll_usb_m2_ck", - .parent = &dpll_usb_ck, - .clksel = dpll_usb_m2_div, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB, - .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK, - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel ducati_clk_mux_sel[] = { - { .parent = &div_core_ck, .rates = div_1_0_rates }, - { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk ducati_clk_mux_ck = { - .name = "ducati_clk_mux_ck", - .parent = &div_core_ck, - .clksel = ducati_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, - .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk func_12m_fclk = { - .name = "func_12m_fclk", - .parent = &dpll_per_m2x2_ck, - .ops = &clkops_null, - .fixed_div = 16, - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk func_24m_clk = { - .name = "func_24m_clk", - .parent = &dpll_per_m2_ck, - .ops = &clkops_null, - .fixed_div = 4, - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk func_24mc_fclk = { - .name = "func_24mc_fclk", - .parent = &dpll_per_m2x2_ck, - .ops = &clkops_null, - .fixed_div = 8, - .recalc = &omap_fixed_divisor_recalc, -}; - -static const struct clksel_rate div2_4to8_rates[] = { - { .div = 4, .val = 0, .flags = RATE_IN_4430 }, - { .div = 8, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel func_48m_fclk_div[] = { - { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates }, - { .parent = NULL }, -}; - -static struct clk func_48m_fclk = { - .name = "func_48m_fclk", - .parent = &dpll_per_m2x2_ck, - .clksel = func_48m_fclk_div, - .clksel_reg = OMAP4430_CM_SCALE_FCLK, - .clksel_mask = OMAP4430_SCALE_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk func_48mc_fclk = { - .name = "func_48mc_fclk", - .parent = &dpll_per_m2x2_ck, - .ops = &clkops_null, - .fixed_div = 4, - .recalc = &omap_fixed_divisor_recalc, -}; - -static const struct clksel_rate div2_2to4_rates[] = { - { .div = 2, .val = 0, .flags = RATE_IN_4430 }, - { .div = 4, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel func_64m_fclk_div[] = { - { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates }, - { .parent = NULL }, -}; - -static struct clk func_64m_fclk = { - .name = "func_64m_fclk", - .parent = &dpll_per_m4x2_ck, - .clksel = func_64m_fclk_div, - .clksel_reg = OMAP4430_CM_SCALE_FCLK, - .clksel_mask = OMAP4430_SCALE_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel func_96m_fclk_div[] = { - { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates }, - { .parent = NULL }, -}; - -static struct clk func_96m_fclk = { - .name = "func_96m_fclk", - .parent = &dpll_per_m2x2_ck, - .clksel = func_96m_fclk_div, - .clksel_reg = OMAP4430_CM_SCALE_FCLK, - .clksel_mask = OMAP4430_SCALE_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel_rate div2_1to8_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 8, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel init_60m_fclk_div[] = { - { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates }, - { .parent = NULL }, -}; - -static struct clk init_60m_fclk = { - .name = "init_60m_fclk", - .parent = &dpll_usb_m2_ck, - .clksel = init_60m_fclk_div, - .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ, - .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel l3_div_div[] = { - { .parent = &div_core_ck, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; - -static struct clk l3_div_ck = { - .name = "l3_div_ck", - .parent = &div_core_ck, - .clkdm_name = "cm_clkdm", - .clksel = l3_div_div, - .clksel_reg = OMAP4430_CM_CLKSEL_CORE, - .clksel_mask = OMAP4430_CLKSEL_L3_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel l4_div_div[] = { - { .parent = &l3_div_ck, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; - -static struct clk l4_div_ck = { - .name = "l4_div_ck", - .parent = &l3_div_ck, - .clksel = l4_div_div, - .clksel_reg = OMAP4430_CM_CLKSEL_CORE, - .clksel_mask = OMAP4430_CLKSEL_L4_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk lp_clk_div_ck = { - .name = "lp_clk_div_ck", - .parent = &dpll_abe_m2x2_ck, - .ops = &clkops_null, - .fixed_div = 16, - .recalc = &omap_fixed_divisor_recalc, -}; - -static const struct clksel l4_wkup_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &lp_clk_div_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk l4_wkup_clk_mux_ck = { - .name = "l4_wkup_clk_mux_ck", - .parent = &sys_clkin_ck, - .clksel = l4_wkup_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL, - .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate div2_2to1_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_4430 }, - { .div = 2, .val = 0, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel ocp_abe_iclk_div[] = { - { .parent = &aess_fclk, .rates = div2_2to1_rates }, - { .parent = NULL }, -}; - -static struct clk mpu_periphclk = { - .name = "mpu_periphclk", - .parent = &dpll_mpu_ck, - .ops = &clkops_null, - .fixed_div = 2, - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk ocp_abe_iclk = { - .name = "ocp_abe_iclk", - .parent = &aess_fclk, - .clksel = ocp_abe_iclk_div, - .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk per_abe_24m_fclk = { - .name = "per_abe_24m_fclk", - .parent = &dpll_abe_m2_ck, - .ops = &clkops_null, - .fixed_div = 4, - .recalc = &omap_fixed_divisor_recalc, -}; - -static const struct clksel per_abe_nc_fclk_div[] = { - { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; - -static struct clk per_abe_nc_fclk = { - .name = "per_abe_nc_fclk", - .parent = &dpll_abe_m2_ck, - .clksel = per_abe_nc_fclk_div, - .clksel_reg = OMAP4430_CM_SCALE_FCLK, - .clksel_mask = OMAP4430_SCALE_FCLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel pmd_stm_clock_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, - { .parent = &tie_low_clock_ck, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static struct clk pmd_stm_clock_mux_ck = { - .name = "pmd_stm_clock_mux_ck", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk pmd_trace_clk_mux_ck = { - .name = "pmd_trace_clk_mux_ck", - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static const struct clksel syc_clk_div_div[] = { - { .parent = &sys_clkin_ck, .rates = div2_1to2_rates }, - { .parent = NULL }, -}; - -static struct clk syc_clk_div_ck = { - .name = "syc_clk_div_ck", - .parent = &sys_clkin_ck, - .clksel = syc_clk_div_div, - .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL, - .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -/* Leaf clocks controlled by modules */ - -static struct clk aes1_fck = { - .name = "aes1_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_secure_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk aes2_fck = { - .name = "aes2_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_secure_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk aess_fck = { - .name = "aess_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", - .parent = &aess_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk bandgap_fclk = { - .name = "bandgap_fclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk des3des_fck = { - .name = "des3des_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_secure_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static const struct clksel dmic_sync_mux_sel[] = { - { .parent = &abe_24m_fclk, .rates = div_1_0_rates }, - { .parent = &syc_clk_div_ck, .rates = div_1_1_rates }, - { .parent = &func_24m_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static struct clk dmic_sync_mux_ck = { - .name = "dmic_sync_mux_ck", - .parent = &abe_24m_fclk, - .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel func_dmic_abe_gfclk_sel[] = { - { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -/* Merged func_dmic_abe_gfclk into dmic */ -static struct clk dmic_fck = { - .name = "dmic_fck", - .parent = &dmic_sync_mux_ck, - .clksel = func_dmic_abe_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -static struct clk dsp_fck = { - .name = "dsp_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "tesla_clkdm", - .parent = &dpll_iva_m4x2_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dss_sys_clk = { - .name = "dss_sys_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, - .clkdm_name = "l3_dss_clkdm", - .parent = &syc_clk_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dss_tv_clk = { - .name = "dss_tv_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, - .clkdm_name = "l3_dss_clkdm", - .parent = &extalt_clkin_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dss_dss_clk = { - .name = "dss_dss_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, - .clkdm_name = "l3_dss_clkdm", - .parent = &dpll_per_m5x2_ck, - .recalc = &followparent_recalc, -}; - -static const struct clksel_rate div3_8to32_rates[] = { - { .div = 8, .val = 0, .flags = RATE_IN_4460 }, - { .div = 16, .val = 1, .flags = RATE_IN_4460 }, - { .div = 32, .val = 2, .flags = RATE_IN_4460 }, - { .div = 0 }, -}; - -static const struct clksel div_ts_div[] = { - { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates }, - { .parent = NULL }, -}; - -static struct clk div_ts_ck = { - .name = "div_ts_ck", - .parent = &l4_wkup_clk_mux_ck, - .clksel = div_ts_div, - .clksel_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk bandgap_ts_fclk = { - .name = "bandgap_ts_fclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, - .enable_bit = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT, - .clkdm_name = "l4_wkup_clkdm", - .parent = &div_ts_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dss_48mhz_clk = { - .name = "dss_48mhz_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, - .clkdm_name = "l3_dss_clkdm", - .parent = &func_48mc_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk dss_fck = { - .name = "dss_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_dss_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk efuse_ctrl_cust_fck = { - .name = "efuse_ctrl_cust_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_cefuse_clkdm", - .parent = &sys_clkin_ck, - .recalc = &followparent_recalc, -}; - -static struct clk emif1_fck = { - .name = "emif1_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .flags = ENABLE_ON_INIT, - .clkdm_name = "l3_emif_clkdm", - .parent = &ddrphy_ck, - .recalc = &followparent_recalc, -}; - -static struct clk emif2_fck = { - .name = "emif2_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .flags = ENABLE_ON_INIT, - .clkdm_name = "l3_emif_clkdm", - .parent = &ddrphy_ck, - .recalc = &followparent_recalc, -}; - -static const struct clksel fdif_fclk_div[] = { - { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, -}; - -/* Merged fdif_fclk into fdif */ -static struct clk fdif_fck = { - .name = "fdif_fck", - .parent = &dpll_per_m4x2_ck, - .clksel = fdif_fclk_div, - .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "iss_clkdm", -}; - -static struct clk fpka_fck = { - .name = "fpka_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_secure_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio1_dbclk = { - .name = "gpio1_dbclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio1_ick = { - .name = "gpio1_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l4_wkup_clkdm", - .parent = &l4_wkup_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio2_dbclk = { - .name = "gpio2_dbclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio2_ick = { - .name = "gpio2_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio3_dbclk = { - .name = "gpio3_dbclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio3_ick = { - .name = "gpio3_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio4_dbclk = { - .name = "gpio4_dbclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio4_ick = { - .name = "gpio4_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio5_dbclk = { - .name = "gpio5_dbclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio5_ick = { - .name = "gpio5_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio6_dbclk = { - .name = "gpio6_dbclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio6_ick = { - .name = "gpio6_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpmc_ick = { - .name = "gpmc_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .flags = ENABLE_ON_INIT, - .clkdm_name = "l3_2_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static const struct clksel sgx_clk_mux_sel[] = { - { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, - { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -/* Merged sgx_clk_mux into gpu */ -static struct clk gpu_fck = { - .name = "gpu_fck", - .parent = &dpll_core_m7x2_ck, - .clksel = sgx_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_gfx_clkdm", -}; - -static struct clk hdq1w_fck = { - .name = "hdq1w_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_12m_fclk, - .recalc = &followparent_recalc, -}; - -static const struct clksel hsi_fclk_div[] = { - { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, -}; - -/* Merged hsi_fclk into hsi */ -static struct clk hsi_fck = { - .name = "hsi_fck", - .parent = &dpll_per_m2x2_ck, - .clksel = hsi_fclk_div, - .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_init_clkdm", -}; - -static struct clk i2c1_fck = { - .name = "i2c1_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk i2c2_fck = { - .name = "i2c2_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk i2c3_fck = { - .name = "i2c3_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk i2c4_fck = { - .name = "i2c4_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk ipu_fck = { - .name = "ipu_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "ducati_clkdm", - .parent = &ducati_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -static struct clk iss_ctrlclk = { - .name = "iss_ctrlclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, - .clkdm_name = "iss_clkdm", - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk iss_fck = { - .name = "iss_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "iss_clkdm", - .parent = &ducati_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -static struct clk iva_fck = { - .name = "iva_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "ivahd_clkdm", - .parent = &dpll_iva_m5x2_ck, - .recalc = &followparent_recalc, -}; - -static struct clk kbd_fck = { - .name = "kbd_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk l3_instr_ick = { - .name = "l3_instr_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .flags = ENABLE_ON_INIT, - .clkdm_name = "l3_instr_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk l3_main_3_ick = { - .name = "l3_main_3_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .flags = ENABLE_ON_INIT, - .clkdm_name = "l3_instr_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk mcasp_sync_mux_ck = { - .name = "mcasp_sync_mux_ck", - .parent = &abe_24m_fclk, - .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel func_mcasp_abe_gfclk_sel[] = { - { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -/* Merged func_mcasp_abe_gfclk into mcasp */ -static struct clk mcasp_fck = { - .name = "mcasp_fck", - .parent = &mcasp_sync_mux_ck, - .clksel = func_mcasp_abe_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -static struct clk mcbsp1_sync_mux_ck = { - .name = "mcbsp1_sync_mux_ck", - .parent = &abe_24m_fclk, - .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel func_mcbsp1_gfclk_sel[] = { - { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -/* Merged func_mcbsp1_gfclk into mcbsp1 */ -static struct clk mcbsp1_fck = { - .name = "mcbsp1_fck", - .parent = &mcbsp1_sync_mux_ck, - .clksel = func_mcbsp1_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -static struct clk mcbsp2_sync_mux_ck = { - .name = "mcbsp2_sync_mux_ck", - .parent = &abe_24m_fclk, - .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel func_mcbsp2_gfclk_sel[] = { - { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -/* Merged func_mcbsp2_gfclk into mcbsp2 */ -static struct clk mcbsp2_fck = { - .name = "mcbsp2_fck", - .parent = &mcbsp2_sync_mux_ck, - .clksel = func_mcbsp2_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -static struct clk mcbsp3_sync_mux_ck = { - .name = "mcbsp3_sync_mux_ck", - .parent = &abe_24m_fclk, - .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel func_mcbsp3_gfclk_sel[] = { - { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -/* Merged func_mcbsp3_gfclk into mcbsp3 */ -static struct clk mcbsp3_fck = { - .name = "mcbsp3_fck", - .parent = &mcbsp3_sync_mux_ck, - .clksel = func_mcbsp3_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -static const struct clksel mcbsp4_sync_mux_sel[] = { - { .parent = &func_96m_fclk, .rates = div_1_0_rates }, - { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk mcbsp4_sync_mux_ck = { - .name = "mcbsp4_sync_mux_ck", - .parent = &func_96m_fclk, - .clksel = mcbsp4_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel per_mcbsp4_gfclk_sel[] = { - { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -/* Merged per_mcbsp4_gfclk into mcbsp4 */ -static struct clk mcbsp4_fck = { - .name = "mcbsp4_fck", - .parent = &mcbsp4_sync_mux_ck, - .clksel = per_mcbsp4_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -static struct clk mcpdm_fck = { - .name = "mcpdm_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", - .parent = &pad_clks_ck, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi1_fck = { - .name = "mcspi1_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi2_fck = { - .name = "mcspi2_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi3_fck = { - .name = "mcspi3_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi4_fck = { - .name = "mcspi4_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static const struct clksel hsmmc1_fclk_sel[] = { - { .parent = &func_64m_fclk, .rates = div_1_0_rates }, - { .parent = &func_96m_fclk, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -/* Merged hsmmc1_fclk into mmc1 */ -static struct clk mmc1_fck = { - .name = "mmc1_fck", - .parent = &func_64m_fclk, - .clksel = hsmmc1_fclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_init_clkdm", -}; - -/* Merged hsmmc2_fclk into mmc2 */ -static struct clk mmc2_fck = { - .name = "mmc2_fck", - .parent = &func_64m_fclk, - .clksel = hsmmc1_fclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_init_clkdm", -}; - -static struct clk mmc3_fck = { - .name = "mmc3_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk mmc4_fck = { - .name = "mmc4_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk mmc5_fck = { - .name = "mmc5_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk ocp2scp_usb_phy_phy_48m = { - .name = "ocp2scp_usb_phy_phy_48m", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk ocp2scp_usb_phy_ick = { - .name = "ocp2scp_usb_phy_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk ocp_wp_noc_ick = { - .name = "ocp_wp_noc_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .flags = ENABLE_ON_INIT, - .clkdm_name = "l3_instr_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk rng_ick = { - .name = "rng_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l4_secure_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk sha2md5_fck = { - .name = "sha2md5_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_secure_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk sl2if_ick = { - .name = "sl2if_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "ivahd_clkdm", - .parent = &dpll_iva_m5x2_ck, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus1_fclk_1 = { - .name = "slimbus1_fclk_1", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT, - .clkdm_name = "abe_clkdm", - .parent = &func_24m_clk, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus1_fclk_0 = { - .name = "slimbus1_fclk_0", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT, - .clkdm_name = "abe_clkdm", - .parent = &abe_24m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus1_fclk_2 = { - .name = "slimbus1_fclk_2", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT, - .clkdm_name = "abe_clkdm", - .parent = &pad_clks_ck, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus1_slimbus_clk = { - .name = "slimbus1_slimbus_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, - .clkdm_name = "abe_clkdm", - .parent = &slimbus_clk, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus1_fck = { - .name = "slimbus1_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", - .parent = &ocp_abe_iclk, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus2_fclk_1 = { - .name = "slimbus2_fclk_1", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &per_abe_24m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus2_fclk_0 = { - .name = "slimbus2_fclk_0", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &func_24mc_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus2_slimbus_clk = { - .name = "slimbus2_slimbus_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, - .clkdm_name = "l4_per_clkdm", - .parent = &pad_slimbus_core_clks_ck, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus2_fck = { - .name = "slimbus2_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk smartreflex_core_fck = { - .name = "smartreflex_core_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_ao_clkdm", - .parent = &l4_wkup_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -static struct clk smartreflex_iva_fck = { - .name = "smartreflex_iva_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_ao_clkdm", - .parent = &l4_wkup_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -static struct clk smartreflex_mpu_fck = { - .name = "smartreflex_mpu_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_ao_clkdm", - .parent = &l4_wkup_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -/* Merged dmt1_clk_mux into timer1 */ -static struct clk timer1_fck = { - .name = "timer1_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_wkup_clkdm", -}; - -/* Merged cm2_dm10_mux into timer10 */ -static struct clk timer10_fck = { - .name = "timer10_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* Merged cm2_dm11_mux into timer11 */ -static struct clk timer11_fck = { - .name = "timer11_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* Merged cm2_dm2_mux into timer2 */ -static struct clk timer2_fck = { - .name = "timer2_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* Merged cm2_dm3_mux into timer3 */ -static struct clk timer3_fck = { - .name = "timer3_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* Merged cm2_dm4_mux into timer4 */ -static struct clk timer4_fck = { - .name = "timer4_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -static const struct clksel timer5_sync_mux_sel[] = { - { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -/* Merged timer5_sync_mux into timer5 */ -static struct clk timer5_fck = { - .name = "timer5_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* Merged timer6_sync_mux into timer6 */ -static struct clk timer6_fck = { - .name = "timer6_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* Merged timer7_sync_mux into timer7 */ -static struct clk timer7_fck = { - .name = "timer7_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* Merged timer8_sync_mux into timer8 */ -static struct clk timer8_fck = { - .name = "timer8_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* Merged cm2_dm9_mux into timer9 */ -static struct clk timer9_fck = { - .name = "timer9_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -static struct clk uart1_fck = { - .name = "uart1_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk uart2_fck = { - .name = "uart2_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk uart3_fck = { - .name = "uart3_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk uart4_fck = { - .name = "uart4_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_fs_fck = { - .name = "usb_host_fs_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &func_48mc_fclk, - .recalc = &followparent_recalc, -}; - -static const struct clksel utmi_p1_gfclk_sel[] = { - { .parent = &init_60m_fclk, .rates = div_1_0_rates }, - { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk utmi_p1_gfclk = { - .name = "utmi_p1_gfclk", - .parent = &init_60m_fclk, - .clksel = utmi_p1_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk usb_host_hs_utmi_p1_clk = { - .name = "usb_host_hs_utmi_p1_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &utmi_p1_gfclk, - .recalc = &followparent_recalc, -}; - -static const struct clksel utmi_p2_gfclk_sel[] = { - { .parent = &init_60m_fclk, .rates = div_1_0_rates }, - { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk utmi_p2_gfclk = { - .name = "utmi_p2_gfclk", - .parent = &init_60m_fclk, - .clksel = utmi_p2_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk usb_host_hs_utmi_p2_clk = { - .name = "usb_host_hs_utmi_p2_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &utmi_p2_gfclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_utmi_p3_clk = { - .name = "usb_host_hs_utmi_p3_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_hsic480m_p1_clk = { - .name = "usb_host_hs_hsic480m_p1_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &dpll_usb_m2_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_hsic60m_p1_clk = { - .name = "usb_host_hs_hsic60m_p1_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_hsic60m_p2_clk = { - .name = "usb_host_hs_hsic60m_p2_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_hsic480m_p2_clk = { - .name = "usb_host_hs_hsic480m_p2_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &dpll_usb_m2_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_func48mclk = { - .name = "usb_host_hs_func48mclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &func_48mc_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_fck = { - .name = "usb_host_hs_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static const struct clksel otg_60m_gfclk_sel[] = { - { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates }, - { .parent = &xclk60motg_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk otg_60m_gfclk = { - .name = "otg_60m_gfclk", - .parent = &utmi_phy_clkout_ck, - .clksel = otg_60m_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_60M_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk usb_otg_hs_xclk = { - .name = "usb_otg_hs_xclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &otg_60m_gfclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_otg_hs_ick = { - .name = "usb_otg_hs_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usb_phy_cm_clk32k = { - .name = "usb_phy_cm_clk32k", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT, - .clkdm_name = "l4_ao_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usb_tll_hs_usb_ch2_clk = { - .name = "usb_tll_hs_usb_ch2_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_tll_hs_usb_ch0_clk = { - .name = "usb_tll_hs_usb_ch0_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_tll_hs_usb_ch1_clk = { - .name = "usb_tll_hs_usb_ch1_clk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, - .clkdm_name = "l3_init_clkdm", - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_tll_hs_ick = { - .name = "usb_tll_hs_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static const struct clksel_rate div2_14to18_rates[] = { - { .div = 14, .val = 0, .flags = RATE_IN_4430 }, - { .div = 18, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel usim_fclk_div[] = { - { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates }, - { .parent = NULL }, -}; - -static struct clk usim_ck = { - .name = "usim_ck", - .parent = &dpll_per_m4x2_ck, - .clksel = usim_fclk_div, - .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk usim_fclk = { - .name = "usim_fclk", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT, - .clkdm_name = "l4_wkup_clkdm", - .parent = &usim_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usim_fck = { - .name = "usim_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk wd_timer2_fck = { - .name = "wd_timer2_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_wkup_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk wd_timer3_fck = { - .name = "wd_timer3_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -/* Remaining optional clocks */ -static const struct clksel stm_clk_div_div[] = { - { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, -}; - -static struct clk stm_clk_div_ck = { - .name = "stm_clk_div_ck", - .parent = &pmd_stm_clock_mux_ck, - .clksel = stm_clk_div_div, - .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel trace_clk_div_div[] = { - { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, -}; - -static struct clk trace_clk_div_ck = { - .name = "trace_clk_div_ck", - .parent = &pmd_trace_clk_mux_ck, - .clkdm_name = "emu_sys_clkdm", - .clksel = trace_clk_div_div, - .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -/* SCRM aux clk nodes */ - -static const struct clksel auxclk_src_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, - { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static const struct clksel_rate div16_1to16_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 3, .val = 2, .flags = RATE_IN_4430 }, - { .div = 4, .val = 3, .flags = RATE_IN_4430 }, - { .div = 5, .val = 4, .flags = RATE_IN_4430 }, - { .div = 6, .val = 5, .flags = RATE_IN_4430 }, - { .div = 7, .val = 6, .flags = RATE_IN_4430 }, - { .div = 8, .val = 7, .flags = RATE_IN_4430 }, - { .div = 9, .val = 8, .flags = RATE_IN_4430 }, - { .div = 10, .val = 9, .flags = RATE_IN_4430 }, - { .div = 11, .val = 10, .flags = RATE_IN_4430 }, - { .div = 12, .val = 11, .flags = RATE_IN_4430 }, - { .div = 13, .val = 12, .flags = RATE_IN_4430 }, - { .div = 14, .val = 13, .flags = RATE_IN_4430 }, - { .div = 15, .val = 14, .flags = RATE_IN_4430 }, - { .div = 16, .val = 15, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static struct clk auxclk0_src_ck = { - .name = "auxclk0_src_ck", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, - .clksel = auxclk_src_sel, - .clksel_reg = OMAP4_SCRM_AUXCLK0, - .clksel_mask = OMAP4_SRCSELECT_MASK, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4_SCRM_AUXCLK0, - .enable_bit = OMAP4_ENABLE_SHIFT, -}; - -static const struct clksel auxclk0_sel[] = { - { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates }, - { .parent = NULL }, -}; - -static struct clk auxclk0_ck = { - .name = "auxclk0_ck", - .parent = &auxclk0_src_ck, - .clksel = auxclk0_sel, - .clksel_reg = OMAP4_SCRM_AUXCLK0, - .clksel_mask = OMAP4_CLKDIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk auxclk1_src_ck = { - .name = "auxclk1_src_ck", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, - .clksel = auxclk_src_sel, - .clksel_reg = OMAP4_SCRM_AUXCLK1, - .clksel_mask = OMAP4_SRCSELECT_MASK, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4_SCRM_AUXCLK1, - .enable_bit = OMAP4_ENABLE_SHIFT, -}; - -static const struct clksel auxclk1_sel[] = { - { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates }, - { .parent = NULL }, -}; - -static struct clk auxclk1_ck = { - .name = "auxclk1_ck", - .parent = &auxclk1_src_ck, - .clksel = auxclk1_sel, - .clksel_reg = OMAP4_SCRM_AUXCLK1, - .clksel_mask = OMAP4_CLKDIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk auxclk2_src_ck = { - .name = "auxclk2_src_ck", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, - .clksel = auxclk_src_sel, - .clksel_reg = OMAP4_SCRM_AUXCLK2, - .clksel_mask = OMAP4_SRCSELECT_MASK, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4_SCRM_AUXCLK2, - .enable_bit = OMAP4_ENABLE_SHIFT, -}; - -static const struct clksel auxclk2_sel[] = { - { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates }, - { .parent = NULL }, -}; - -static struct clk auxclk2_ck = { - .name = "auxclk2_ck", - .parent = &auxclk2_src_ck, - .clksel = auxclk2_sel, - .clksel_reg = OMAP4_SCRM_AUXCLK2, - .clksel_mask = OMAP4_CLKDIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk auxclk3_src_ck = { - .name = "auxclk3_src_ck", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, - .clksel = auxclk_src_sel, - .clksel_reg = OMAP4_SCRM_AUXCLK3, - .clksel_mask = OMAP4_SRCSELECT_MASK, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4_SCRM_AUXCLK3, - .enable_bit = OMAP4_ENABLE_SHIFT, -}; - -static const struct clksel auxclk3_sel[] = { - { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates }, - { .parent = NULL }, -}; - -static struct clk auxclk3_ck = { - .name = "auxclk3_ck", - .parent = &auxclk3_src_ck, - .clksel = auxclk3_sel, - .clksel_reg = OMAP4_SCRM_AUXCLK3, - .clksel_mask = OMAP4_CLKDIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk auxclk4_src_ck = { - .name = "auxclk4_src_ck", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, - .clksel = auxclk_src_sel, - .clksel_reg = OMAP4_SCRM_AUXCLK4, - .clksel_mask = OMAP4_SRCSELECT_MASK, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4_SCRM_AUXCLK4, - .enable_bit = OMAP4_ENABLE_SHIFT, -}; - -static const struct clksel auxclk4_sel[] = { - { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates }, - { .parent = NULL }, -}; - -static struct clk auxclk4_ck = { - .name = "auxclk4_ck", - .parent = &auxclk4_src_ck, - .clksel = auxclk4_sel, - .clksel_reg = OMAP4_SCRM_AUXCLK4, - .clksel_mask = OMAP4_CLKDIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk auxclk5_src_ck = { - .name = "auxclk5_src_ck", - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, - .clksel = auxclk_src_sel, - .clksel_reg = OMAP4_SCRM_AUXCLK5, - .clksel_mask = OMAP4_SRCSELECT_MASK, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4_SCRM_AUXCLK5, - .enable_bit = OMAP4_ENABLE_SHIFT, -}; - -static const struct clksel auxclk5_sel[] = { - { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates }, - { .parent = NULL }, -}; - -static struct clk auxclk5_ck = { - .name = "auxclk5_ck", - .parent = &auxclk5_src_ck, - .clksel = auxclk5_sel, - .clksel_reg = OMAP4_SCRM_AUXCLK5, - .clksel_mask = OMAP4_CLKDIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel auxclkreq_sel[] = { - { .parent = &auxclk0_ck, .rates = div_1_0_rates }, - { .parent = &auxclk1_ck, .rates = div_1_1_rates }, - { .parent = &auxclk2_ck, .rates = div_1_2_rates }, - { .parent = &auxclk3_ck, .rates = div_1_3_rates }, - { .parent = &auxclk4_ck, .rates = div_1_4_rates }, - { .parent = &auxclk5_ck, .rates = div_1_5_rates }, - { .parent = NULL }, -}; - -static struct clk auxclkreq0_ck = { - .name = "auxclkreq0_ck", - .parent = &auxclk0_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_null, - .clksel = auxclkreq_sel, - .clksel_reg = OMAP4_SCRM_AUXCLKREQ0, - .clksel_mask = OMAP4_MAPPING_MASK, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk auxclkreq1_ck = { - .name = "auxclkreq1_ck", - .parent = &auxclk1_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_null, - .clksel = auxclkreq_sel, - .clksel_reg = OMAP4_SCRM_AUXCLKREQ1, - .clksel_mask = OMAP4_MAPPING_MASK, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk auxclkreq2_ck = { - .name = "auxclkreq2_ck", - .parent = &auxclk2_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_null, - .clksel = auxclkreq_sel, - .clksel_reg = OMAP4_SCRM_AUXCLKREQ2, - .clksel_mask = OMAP4_MAPPING_MASK, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk auxclkreq3_ck = { - .name = "auxclkreq3_ck", - .parent = &auxclk3_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_null, - .clksel = auxclkreq_sel, - .clksel_reg = OMAP4_SCRM_AUXCLKREQ3, - .clksel_mask = OMAP4_MAPPING_MASK, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk auxclkreq4_ck = { - .name = "auxclkreq4_ck", - .parent = &auxclk4_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_null, - .clksel = auxclkreq_sel, - .clksel_reg = OMAP4_SCRM_AUXCLKREQ4, - .clksel_mask = OMAP4_MAPPING_MASK, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk auxclkreq5_ck = { - .name = "auxclkreq5_ck", - .parent = &auxclk5_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_null, - .clksel = auxclkreq_sel, - .clksel_reg = OMAP4_SCRM_AUXCLKREQ5, - .clksel_mask = OMAP4_MAPPING_MASK, - .recalc = &omap2_clksel_recalc, -}; - -/* - * clkdev - */ - -static struct omap_clk omap44xx_clks[] = { - CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), - CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), - CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), - CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), - CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), - CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), - CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), - CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), - CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), - CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), - CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), - CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), - CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), - CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), - CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), - CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), - CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), - CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), - CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), - CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), - CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), - CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), - CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), - CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), - CLK(NULL, "abe_clk", &abe_clk, CK_443X), - CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), - CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), - CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), - CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), - CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), - CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), - CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), - CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), - CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), - CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), - CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), - CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), - CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), - CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), - CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), - CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), - CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), - CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), - CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), - CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), - CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), - CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), - CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), - CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), - CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), - CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), - CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), - CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), - CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), - CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), - CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), - CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), - CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), - CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), - CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), - CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), - CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), - CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), - CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), - CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), - CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), - CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), - CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), - CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), - CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), - CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), - CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), - CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), - CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), - CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), - CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), - CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), - CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), - CLK("smp_twd", NULL, &mpu_periphclk, CK_443X), - CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), - CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), - CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), - CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), - CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), - CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), - CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), - CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), - CLK(NULL, "aess_fck", &aess_fck, CK_443X), - CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), - CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), - CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), - CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), - CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), - CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), - CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), - CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), - CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), - CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), - CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), - CLK(NULL, "dss_fck", &dss_fck, CK_443X), - CLK("omapdss_dss", "ick", &dss_fck, CK_443X), - CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), - CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), - CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), - CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), - CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), - CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), - CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), - CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), - CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), - CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), - CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), - CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), - CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), - CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), - CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), - CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), - CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), - CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), - CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), - CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X), - CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), - CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X), - CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X), - CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X), - CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X), - CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), - CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), - CLK(NULL, "iss_fck", &iss_fck, CK_443X), - CLK(NULL, "iva_fck", &iva_fck, CK_443X), - CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), - CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X), - CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X), - CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), - CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), - CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), - CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X), - CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), - CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X), - CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), - CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X), - CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), - CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X), - CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), - CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X), - CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X), - CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X), - CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X), - CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X), - CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X), - CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X), - CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X), - CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X), - CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), - CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), - CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), - CLK(NULL, "rng_ick", &rng_ick, CK_443X), - CLK("omap_rng", "ick", &rng_ick, CK_443X), - CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), - CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), - CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), - CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), - CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), - CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), - CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), - CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), - CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), - CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), - CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), - CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), - CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), - CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), - CLK(NULL, "timer1_fck", &timer1_fck, CK_443X), - CLK(NULL, "timer10_fck", &timer10_fck, CK_443X), - CLK(NULL, "timer11_fck", &timer11_fck, CK_443X), - CLK(NULL, "timer2_fck", &timer2_fck, CK_443X), - CLK(NULL, "timer3_fck", &timer3_fck, CK_443X), - CLK(NULL, "timer4_fck", &timer4_fck, CK_443X), - CLK(NULL, "timer5_fck", &timer5_fck, CK_443X), - CLK(NULL, "timer6_fck", &timer6_fck, CK_443X), - CLK(NULL, "timer7_fck", &timer7_fck, CK_443X), - CLK(NULL, "timer8_fck", &timer8_fck, CK_443X), - CLK(NULL, "timer9_fck", &timer9_fck, CK_443X), - CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), - CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), - CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), - CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), - CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), - CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), - CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), - CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), - CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), - CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), - CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), - CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), - CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), - CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), - CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X), - CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), - CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), - CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X), - CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), - CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), - CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), - CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), - CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), - CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), - CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X), - CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X), - CLK(NULL, "usim_ck", &usim_ck, CK_443X), - CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), - CLK(NULL, "usim_fck", &usim_fck, CK_443X), - CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X), - CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), - CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), - CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), - CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X), - CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), - CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), - CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X), - CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), - CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), - CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X), - CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), - CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), - CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X), - CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), - CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), - CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X), - CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), - CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), - CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X), - CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), - CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), - CLK("omap-gpmc", "fck", &dummy_ck, CK_443X), - CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), - CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), - CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), - CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), - CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X), - CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X), - CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), - CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), - CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), - CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), - CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), - CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), - CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), - CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), - CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X), - CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X), - CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X), - CLK("omap_wdt", "ick", &dummy_ck, CK_443X), - CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X), - /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */ - CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X), - CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X), - CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X), - CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X), - CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), - CLK("49038000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), - CLK("4903a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), - CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), - CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), - CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), -}; - -int __init omap4xxx_clk_init(void) -{ - struct omap_clk *c; - u32 cpu_clkflg; - - if (cpu_is_omap443x()) { - cpu_mask = RATE_IN_4430; - cpu_clkflg = CK_443X; - } else if (cpu_is_omap446x() || cpu_is_omap447x()) { - cpu_mask = RATE_IN_4460 | RATE_IN_4430; - cpu_clkflg = CK_446X | CK_443X; - - if (cpu_is_omap447x()) - pr_warn("WARNING: OMAP4470 clock data incomplete!\n"); - } else { - return 0; - } - - clk_init(&omap2_clk_functions); - - /* - * Must stay commented until all OMAP SoC drivers are - * converted to runtime PM, or drivers may start crashing - * - * omap2_clk_disable_clkdm_control(); - */ - - for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); - c++) - clk_preinit(c->lk.clk); - - for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); - c++) - if (c->cpu & cpu_clkflg) { - clkdev_add(&c->lk); - clk_register(c->lk.clk); - omap2_init_clk_clkdm(c->lk.clk); - } - - /* Disable autoidle on all clocks; let the PM code enable it later */ - omap_clk_disable_autoidle_all(); - - recalculate_root_clocks(); - - /* - * Only enable those clocks we will need, let the drivers - * enable other clocks as necessary - */ - clk_enable_init_clocks(); - - return 0; -} diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c index b9f3ba68148c..ef4d21bfb964 100644 --- a/arch/arm/mach-omap2/clock_common_data.c +++ b/arch/arm/mach-omap2/clock_common_data.c @@ -16,6 +16,7 @@ * OMAP3xxx clock definition files. */ +#include <linux/clk-private.h> #include "clock.h" /* clksel_rate data common to 24xx/343x */ @@ -52,6 +53,13 @@ const struct clksel_rate div_1_0_rates[] = { { .div = 0 }, }; +const struct clksel_rate div3_1to4_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_4430 }, + { .div = 2, .val = 1, .flags = RATE_IN_4430 }, + { .div = 4, .val = 2, .flags = RATE_IN_4430 }, + { .div = 0 }, +}; + const struct clksel_rate div_1_1_rates[] = { { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, { .div = 0 }, @@ -109,14 +117,10 @@ const struct clksel_rate div31_1to31_rates[] = { /* Clocks shared between various OMAP SoCs */ -struct clk virt_19200000_ck = { - .name = "virt_19200000_ck", - .ops = &clkops_null, - .rate = 19200000, -}; +static struct clk_ops dummy_ck_ops = {}; -struct clk virt_26000000_ck = { - .name = "virt_26000000_ck", - .ops = &clkops_null, - .rate = 26000000, +struct clk dummy_ck = { + .name = "dummy_clk", + .ops = &dummy_ck_ops, + .flags = CLK_IS_BASIC, }; diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 512e79a842cb..384873580b23 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -22,12 +22,14 @@ #include <linux/clk.h> #include <linux/limits.h> #include <linux/err.h> +#include <linux/clk-provider.h> #include <linux/io.h> #include <linux/bitops.h> -#include <plat/clock.h> +#include "soc.h" +#include "clock.h" #include "clockdomain.h" /* clkdm_list contains all registered struct clockdomains */ @@ -946,35 +948,6 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) return 0; } -static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm) -{ - unsigned long flags; - - if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) - return -EINVAL; - - spin_lock_irqsave(&clkdm->lock, flags); - - if (atomic_read(&clkdm->usecount) == 0) { - spin_unlock_irqrestore(&clkdm->lock, flags); - WARN_ON(1); /* underflow */ - return -ERANGE; - } - - if (atomic_dec_return(&clkdm->usecount) > 0) { - spin_unlock_irqrestore(&clkdm->lock, flags); - return 0; - } - - arch_clkdm->clkdm_clk_disable(clkdm); - pwrdm_state_switch(clkdm->pwrdm.ptr); - spin_unlock_irqrestore(&clkdm->lock, flags); - - pr_debug("clockdomain: %s: disabled\n", clkdm->name); - - return 0; -} - /** * clkdm_clk_enable - add an enabled downstream clock to this clkdm * @clkdm: struct clockdomain * @@ -1017,15 +990,37 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) */ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) { - /* - * XXX Rewrite this code to maintain a list of enabled - * downstream clocks for debugging purposes? - */ + unsigned long flags; - if (!clk) + if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) return -EINVAL; - return _clkdm_clk_hwmod_disable(clkdm); + spin_lock_irqsave(&clkdm->lock, flags); + + /* corner case: disabling unused clocks */ + if (__clk_get_enable_count(clk) == 0) + goto ccd_exit; + + if (atomic_read(&clkdm->usecount) == 0) { + spin_unlock_irqrestore(&clkdm->lock, flags); + WARN_ON(1); /* underflow */ + return -ERANGE; + } + + if (atomic_dec_return(&clkdm->usecount) > 0) { + spin_unlock_irqrestore(&clkdm->lock, flags); + return 0; + } + + arch_clkdm->clkdm_clk_disable(clkdm); + pwrdm_state_switch(clkdm->pwrdm.ptr); + + pr_debug("clockdomain: %s: disabled\n", clkdm->name); + +ccd_exit: + spin_unlock_irqrestore(&clkdm->lock, flags); + + return 0; } /** @@ -1076,6 +1071,8 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh) */ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh) { + unsigned long flags; + /* The clkdm attribute does not exist yet prior OMAP4 */ if (cpu_is_omap24xx() || cpu_is_omap34xx()) return 0; @@ -1085,9 +1082,28 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh) * downstream hwmods for debugging purposes? */ - if (!oh) + if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) return -EINVAL; - return _clkdm_clk_hwmod_disable(clkdm); + spin_lock_irqsave(&clkdm->lock, flags); + + if (atomic_read(&clkdm->usecount) == 0) { + spin_unlock_irqrestore(&clkdm->lock, flags); + WARN_ON(1); /* underflow */ + return -ERANGE; + } + + if (atomic_dec_return(&clkdm->usecount) > 0) { + spin_unlock_irqrestore(&clkdm->lock, flags); + return 0; + } + + arch_clkdm->clkdm_clk_disable(clkdm); + pwrdm_state_switch(clkdm->pwrdm.ptr); + spin_unlock_irqrestore(&clkdm->lock, flags); + + pr_debug("clockdomain: %s: disabled\n", clkdm->name); + + return 0; } diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 629576be7444..bc42446e23ab 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -18,9 +18,8 @@ #include <linux/spinlock.h> #include "powerdomain.h" -#include <plat/clock.h> -#include <plat/omap_hwmod.h> -#include <plat/cpu.h> +#include "clock.h" +#include "omap_hwmod.h" /* * Clockdomain flags diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c deleted file mode 100644 index 70294f54e35a..000000000000 --- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c +++ /dev/null @@ -1,339 +0,0 @@ -/* - * OMAP2 and OMAP3 clockdomain control - * - * Copyright (C) 2008-2010 Texas Instruments, Inc. - * Copyright (C) 2008-2010 Nokia Corporation - * - * Derived from mach-omap2/clockdomain.c written by Paul Walmsley - * Rajendra Nayak <rnayak@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/types.h> -#include <plat/prcm.h> -#include "prm.h" -#include "prm2xxx_3xxx.h" -#include "cm.h" -#include "cm2xxx_3xxx.h" -#include "cm-regbits-24xx.h" -#include "cm-regbits-34xx.h" -#include "prm-regbits-24xx.h" -#include "clockdomain.h" - -static int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1, - struct clockdomain *clkdm2) -{ - omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit), - clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); - return 0; -} - -static int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1, - struct clockdomain *clkdm2) -{ - omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), - clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); - return 0; -} - -static int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1, - struct clockdomain *clkdm2) -{ - return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, - PM_WKDEP, (1 << clkdm2->dep_bit)); -} - -static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm) -{ - struct clkdm_dep *cd; - u32 mask = 0; - - for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { - if (!cd->clkdm) - continue; /* only happens if data is erroneous */ - - /* PRM accesses are slow, so minimize them */ - mask |= 1 << cd->clkdm->dep_bit; - atomic_set(&cd->wkdep_usecount, 0); - } - - omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, - PM_WKDEP); - return 0; -} - -static int omap3_clkdm_add_sleepdep(struct clockdomain *clkdm1, - struct clockdomain *clkdm2) -{ - omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit), - clkdm1->pwrdm.ptr->prcm_offs, - OMAP3430_CM_SLEEPDEP); - return 0; -} - -static int omap3_clkdm_del_sleepdep(struct clockdomain *clkdm1, - struct clockdomain *clkdm2) -{ - omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit), - clkdm1->pwrdm.ptr->prcm_offs, - OMAP3430_CM_SLEEPDEP); - return 0; -} - -static int omap3_clkdm_read_sleepdep(struct clockdomain *clkdm1, - struct clockdomain *clkdm2) -{ - return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, - OMAP3430_CM_SLEEPDEP, (1 << clkdm2->dep_bit)); -} - -static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) -{ - struct clkdm_dep *cd; - u32 mask = 0; - - for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) { - if (!cd->clkdm) - continue; /* only happens if data is erroneous */ - - /* PRM accesses are slow, so minimize them */ - mask |= 1 << cd->clkdm->dep_bit; - atomic_set(&cd->sleepdep_usecount, 0); - } - omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, - OMAP3430_CM_SLEEPDEP); - return 0; -} - -static int omap2_clkdm_sleep(struct clockdomain *clkdm) -{ - omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, - clkdm->pwrdm.ptr->prcm_offs, - OMAP2_PM_PWSTCTRL); - return 0; -} - -static int omap2_clkdm_wakeup(struct clockdomain *clkdm) -{ - omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, - clkdm->pwrdm.ptr->prcm_offs, - OMAP2_PM_PWSTCTRL); - return 0; -} - -static void omap2_clkdm_allow_idle(struct clockdomain *clkdm) -{ - if (atomic_read(&clkdm->usecount) > 0) - _clkdm_add_autodeps(clkdm); - - omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); -} - -static void omap2_clkdm_deny_idle(struct clockdomain *clkdm) -{ - omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - - if (atomic_read(&clkdm->usecount) > 0) - _clkdm_del_autodeps(clkdm); -} - -static void _enable_hwsup(struct clockdomain *clkdm) -{ - if (cpu_is_omap24xx()) - omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - else if (cpu_is_omap34xx()) - omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); -} - -static void _disable_hwsup(struct clockdomain *clkdm) -{ - if (cpu_is_omap24xx()) - omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - else if (cpu_is_omap34xx()) - omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); -} - -static int omap3_clkdm_sleep(struct clockdomain *clkdm) -{ - omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - return 0; -} - -static int omap3_clkdm_wakeup(struct clockdomain *clkdm) -{ - omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - return 0; -} - -static int omap2_clkdm_clk_enable(struct clockdomain *clkdm) -{ - bool hwsup = false; - - if (!clkdm->clktrctrl_mask) - return 0; - - hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - - if (hwsup) { - /* Disable HW transitions when we are changing deps */ - _disable_hwsup(clkdm); - _clkdm_add_autodeps(clkdm); - _enable_hwsup(clkdm); - } else { - if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) - omap2_clkdm_wakeup(clkdm); - } - - return 0; -} - -static int omap2_clkdm_clk_disable(struct clockdomain *clkdm) -{ - bool hwsup = false; - - if (!clkdm->clktrctrl_mask) - return 0; - - hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - - if (hwsup) { - /* Disable HW transitions when we are changing deps */ - _disable_hwsup(clkdm); - _clkdm_del_autodeps(clkdm); - _enable_hwsup(clkdm); - } else { - if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP) - omap2_clkdm_sleep(clkdm); - } - - return 0; -} - -static void omap3_clkdm_allow_idle(struct clockdomain *clkdm) -{ - if (atomic_read(&clkdm->usecount) > 0) - _clkdm_add_autodeps(clkdm); - - omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); -} - -static void omap3_clkdm_deny_idle(struct clockdomain *clkdm) -{ - omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - - if (atomic_read(&clkdm->usecount) > 0) - _clkdm_del_autodeps(clkdm); -} - -static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm) -{ - bool hwsup = false; - - if (!clkdm->clktrctrl_mask) - return 0; - - /* - * The CLKDM_MISSING_IDLE_REPORTING flag documentation has - * more details on the unpleasant problem this is working - * around - */ - if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) && - (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) { - omap3_clkdm_wakeup(clkdm); - return 0; - } - - hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - - if (hwsup) { - /* Disable HW transitions when we are changing deps */ - _disable_hwsup(clkdm); - _clkdm_add_autodeps(clkdm); - _enable_hwsup(clkdm); - } else { - if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) - omap3_clkdm_wakeup(clkdm); - } - - return 0; -} - -static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm) -{ - bool hwsup = false; - - if (!clkdm->clktrctrl_mask) - return 0; - - /* - * The CLKDM_MISSING_IDLE_REPORTING flag documentation has - * more details on the unpleasant problem this is working - * around - */ - if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING && - !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) { - _enable_hwsup(clkdm); - return 0; - } - - hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, - clkdm->clktrctrl_mask); - - if (hwsup) { - /* Disable HW transitions when we are changing deps */ - _disable_hwsup(clkdm); - _clkdm_del_autodeps(clkdm); - _enable_hwsup(clkdm); - } else { - if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP) - omap3_clkdm_sleep(clkdm); - } - - return 0; -} - -struct clkdm_ops omap2_clkdm_operations = { - .clkdm_add_wkdep = omap2_clkdm_add_wkdep, - .clkdm_del_wkdep = omap2_clkdm_del_wkdep, - .clkdm_read_wkdep = omap2_clkdm_read_wkdep, - .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps, - .clkdm_sleep = omap2_clkdm_sleep, - .clkdm_wakeup = omap2_clkdm_wakeup, - .clkdm_allow_idle = omap2_clkdm_allow_idle, - .clkdm_deny_idle = omap2_clkdm_deny_idle, - .clkdm_clk_enable = omap2_clkdm_clk_enable, - .clkdm_clk_disable = omap2_clkdm_clk_disable, -}; - -struct clkdm_ops omap3_clkdm_operations = { - .clkdm_add_wkdep = omap2_clkdm_add_wkdep, - .clkdm_del_wkdep = omap2_clkdm_del_wkdep, - .clkdm_read_wkdep = omap2_clkdm_read_wkdep, - .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps, - .clkdm_add_sleepdep = omap3_clkdm_add_sleepdep, - .clkdm_del_sleepdep = omap3_clkdm_del_sleepdep, - .clkdm_read_sleepdep = omap3_clkdm_read_sleepdep, - .clkdm_clear_all_sleepdeps = omap3_clkdm_clear_all_sleepdeps, - .clkdm_sleep = omap3_clkdm_sleep, - .clkdm_wakeup = omap3_clkdm_wakeup, - .clkdm_allow_idle = omap3_clkdm_allow_idle, - .clkdm_deny_idle = omap3_clkdm_deny_idle, - .clkdm_clk_enable = omap3xxx_clkdm_clk_enable, - .clkdm_clk_disable = omap3xxx_clkdm_clk_disable, -}; diff --git a/arch/arm/mach-omap2/clockdomain33xx.c b/arch/arm/mach-omap2/clockdomain33xx.c deleted file mode 100644 index aca6388fad76..000000000000 --- a/arch/arm/mach-omap2/clockdomain33xx.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * AM33XX clockdomain control - * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ - * Vaibhav Hiremath <hvaibhav@ti.com> - * - * Derived from mach-omap2/clockdomain44xx.c written by Rajendra Nayak - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> - -#include "clockdomain.h" -#include "cm33xx.h" - - -static int am33xx_clkdm_sleep(struct clockdomain *clkdm) -{ - am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs); - return 0; -} - -static int am33xx_clkdm_wakeup(struct clockdomain *clkdm) -{ - am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs); - return 0; -} - -static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm) -{ - am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); -} - -static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm) -{ - am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); -} - -static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm) -{ - if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) - return am33xx_clkdm_wakeup(clkdm); - - return 0; -} - -static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm) -{ - bool hwsup = false; - - hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); - - if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) - am33xx_clkdm_sleep(clkdm); - - return 0; -} - -struct clkdm_ops am33xx_clkdm_operations = { - .clkdm_sleep = am33xx_clkdm_sleep, - .clkdm_wakeup = am33xx_clkdm_wakeup, - .clkdm_allow_idle = am33xx_clkdm_allow_idle, - .clkdm_deny_idle = am33xx_clkdm_deny_idle, - .clkdm_clk_enable = am33xx_clkdm_clk_enable, - .clkdm_clk_disable = am33xx_clkdm_clk_disable, -}; diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c deleted file mode 100644 index 6fc6155625bc..000000000000 --- a/arch/arm/mach-omap2/clockdomain44xx.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * OMAP4 clockdomain control - * - * Copyright (C) 2008-2010 Texas Instruments, Inc. - * Copyright (C) 2008-2010 Nokia Corporation - * - * Derived from mach-omap2/clockdomain.c written by Paul Walmsley - * Rajendra Nayak <rnayak@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include "clockdomain.h" -#include "cminst44xx.h" -#include "cm44xx.h" - -static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1, - struct clockdomain *clkdm2) -{ - omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit), - clkdm1->prcm_partition, - clkdm1->cm_inst, clkdm1->clkdm_offs + - OMAP4_CM_STATICDEP); - return 0; -} - -static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1, - struct clockdomain *clkdm2) -{ - omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit), - clkdm1->prcm_partition, - clkdm1->cm_inst, clkdm1->clkdm_offs + - OMAP4_CM_STATICDEP); - return 0; -} - -static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1, - struct clockdomain *clkdm2) -{ - return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition, - clkdm1->cm_inst, clkdm1->clkdm_offs + - OMAP4_CM_STATICDEP, - (1 << clkdm2->dep_bit)); -} - -static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm) -{ - struct clkdm_dep *cd; - u32 mask = 0; - - if (!clkdm->prcm_partition) - return 0; - - for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { - if (!cd->clkdm) - continue; /* only happens if data is erroneous */ - - mask |= 1 << cd->clkdm->dep_bit; - atomic_set(&cd->wkdep_usecount, 0); - } - - omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition, - clkdm->cm_inst, clkdm->clkdm_offs + - OMAP4_CM_STATICDEP); - return 0; -} - -static int omap4_clkdm_sleep(struct clockdomain *clkdm) -{ - omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, - clkdm->cm_inst, clkdm->clkdm_offs); - return 0; -} - -static int omap4_clkdm_wakeup(struct clockdomain *clkdm) -{ - omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition, - clkdm->cm_inst, clkdm->clkdm_offs); - return 0; -} - -static void omap4_clkdm_allow_idle(struct clockdomain *clkdm) -{ - omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, - clkdm->cm_inst, clkdm->clkdm_offs); -} - -static void omap4_clkdm_deny_idle(struct clockdomain *clkdm) -{ - if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) - omap4_clkdm_wakeup(clkdm); - else - omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition, - clkdm->cm_inst, - clkdm->clkdm_offs); -} - -static int omap4_clkdm_clk_enable(struct clockdomain *clkdm) -{ - if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) - return omap4_clkdm_wakeup(clkdm); - - return 0; -} - -static int omap4_clkdm_clk_disable(struct clockdomain *clkdm) -{ - bool hwsup = false; - - if (!clkdm->prcm_partition) - return 0; - - /* - * The CLKDM_MISSING_IDLE_REPORTING flag documentation has - * more details on the unpleasant problem this is working - * around - */ - if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING && - !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) { - omap4_clkdm_allow_idle(clkdm); - return 0; - } - - hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, - clkdm->cm_inst, clkdm->clkdm_offs); - - if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) - omap4_clkdm_sleep(clkdm); - - return 0; -} - -struct clkdm_ops omap4_clkdm_operations = { - .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep, - .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep, - .clkdm_read_wkdep = omap4_clkdm_read_wkup_sleep_dep, - .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps, - .clkdm_add_sleepdep = omap4_clkdm_add_wkup_sleep_dep, - .clkdm_del_sleepdep = omap4_clkdm_del_wkup_sleep_dep, - .clkdm_read_sleepdep = omap4_clkdm_read_wkup_sleep_dep, - .clkdm_clear_all_sleepdeps = omap4_clkdm_clear_all_wkup_sleep_deps, - .clkdm_sleep = omap4_clkdm_sleep, - .clkdm_wakeup = omap4_clkdm_wakeup, - .clkdm_allow_idle = omap4_clkdm_allow_idle, - .clkdm_deny_idle = omap4_clkdm_deny_idle, - .clkdm_clk_enable = omap4_clkdm_clk_enable, - .clkdm_clk_disable = omap4_clkdm_clk_disable, -}; diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c index 5c741852fac0..7e76becf3a4a 100644 --- a/arch/arm/mach-omap2/clockdomains2420_data.c +++ b/arch/arm/mach-omap2/clockdomains2420_data.c @@ -35,6 +35,7 @@ #include <linux/kernel.h> #include <linux/io.h> +#include "soc.h" #include "clockdomain.h" #include "prm2xxx_3xxx.h" #include "cm2xxx_3xxx.h" diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c index f09617555e15..b923007e45d0 100644 --- a/arch/arm/mach-omap2/clockdomains2430_data.c +++ b/arch/arm/mach-omap2/clockdomains2430_data.c @@ -35,6 +35,7 @@ #include <linux/kernel.h> #include <linux/io.h> +#include "soc.h" #include "clockdomain.h" #include "prm2xxx_3xxx.h" #include "cm2xxx_3xxx.h" diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c index 933a35cd124a..e6b91e552d3d 100644 --- a/arch/arm/mach-omap2/clockdomains3xxx_data.c +++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c @@ -33,6 +33,7 @@ #include <linux/kernel.h> #include <linux/io.h> +#include "soc.h" #include "clockdomain.h" #include "prm2xxx_3xxx.h" #include "cm2xxx_3xxx.h" diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index 686290437568..669ef51b17a8 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h @@ -59,6 +59,7 @@ /* CM_CLKSEL_MPU */ #define OMAP24XX_CLKSEL_MPU_SHIFT 0 #define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0) +#define OMAP24XX_CLKSEL_MPU_WIDTH 5 /* CM_CLKSTCTRL_MPU */ #define OMAP24XX_AUTOSTATE_MPU_SHIFT 0 @@ -237,8 +238,10 @@ #define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8) #define OMAP24XX_CLKSEL_L4_SHIFT 5 #define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5) +#define OMAP24XX_CLKSEL_L4_WIDTH 2 #define OMAP24XX_CLKSEL_L3_SHIFT 0 #define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0) +#define OMAP24XX_CLKSEL_L3_WIDTH 5 /* CM_CLKSEL2_CORE */ #define OMAP24XX_CLKSEL_GPT12_SHIFT 22 @@ -333,7 +336,9 @@ #define OMAP24XX_EN_DPLL_MASK (0x3 << 0) /* CM_IDLEST_CKGEN */ +#define OMAP24XX_ST_54M_APLL_SHIFT 9 #define OMAP24XX_ST_54M_APLL_MASK (1 << 9) +#define OMAP24XX_ST_96M_APLL_SHIFT 8 #define OMAP24XX_ST_96M_APLL_MASK (1 << 8) #define OMAP24XX_ST_54M_CLK_MASK (1 << 6) #define OMAP24XX_ST_12M_CLK_MASK (1 << 5) @@ -361,8 +366,10 @@ #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) #define OMAP24XX_54M_SOURCE_SHIFT 5 #define OMAP24XX_54M_SOURCE_MASK (1 << 5) +#define OMAP24XX_54M_SOURCE_WIDTH 1 #define OMAP2430_96M_SOURCE_SHIFT 4 #define OMAP2430_96M_SOURCE_MASK (1 << 4) +#define OMAP2430_96M_SOURCE_WIDTH 1 #define OMAP24XX_48M_SOURCE_SHIFT 3 #define OMAP24XX_48M_SOURCE_MASK (1 << 3) #define OMAP2430_ALTCLK_SOURCE_SHIFT 0 diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 59598ffd8783..adf78d325804 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -81,6 +81,7 @@ /* CM_CLKSEL1_PLL_IVA2 */ #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 #define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19) +#define OMAP3430_IVA2_CLK_SRC_WIDTH 3 #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 @@ -89,6 +90,7 @@ /* CM_CLKSEL2_PLL_IVA2 */ #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) +#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5 /* CM_CLKSTCTRL_IVA2 */ #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 @@ -118,6 +120,7 @@ /* CM_IDLEST_PLL_MPU */ #define OMAP3430_ST_MPU_CLK_SHIFT 0 #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) +#define OMAP3430_ST_MPU_CLK_WIDTH 1 /* CM_AUTOIDLE_PLL_MPU */ #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 @@ -126,6 +129,7 @@ /* CM_CLKSEL1_PLL_MPU */ #define OMAP3430_MPU_CLK_SRC_SHIFT 19 #define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19) +#define OMAP3430_MPU_CLK_SRC_WIDTH 3 #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 @@ -134,6 +138,7 @@ /* CM_CLKSEL2_PLL_MPU */ #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) +#define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5 /* CM_CLKSTCTRL_MPU */ #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 @@ -345,10 +350,13 @@ #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) #define OMAP3430_CLKSEL_L4_SHIFT 2 #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) +#define OMAP3430_CLKSEL_L4_WIDTH 2 #define OMAP3430_CLKSEL_L3_SHIFT 0 #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) +#define OMAP3430_CLKSEL_L3_WIDTH 2 #define OMAP3630_CLKSEL_96M_SHIFT 12 #define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) +#define OMAP3630_CLKSEL_96M_WIDTH 2 /* CM_CLKSTCTRL_CORE */ #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 @@ -452,6 +460,7 @@ #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) #define OMAP3430_CLKSEL_RM_SHIFT 1 #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) +#define OMAP3430_CLKSEL_RM_WIDTH 2 #define OMAP3430_CLKSEL_GPT1_SHIFT 0 #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) @@ -520,14 +529,17 @@ /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) +#define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5 #define OMAP3430_CORE_DPLL_MULT_SHIFT 16 #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) #define OMAP3430_SOURCE_96M_SHIFT 6 #define OMAP3430_SOURCE_96M_MASK (1 << 6) +#define OMAP3430_SOURCE_96M_WIDTH 1 #define OMAP3430_SOURCE_54M_SHIFT 5 #define OMAP3430_SOURCE_54M_MASK (1 << 5) +#define OMAP3430_SOURCE_54M_WIDTH 1 #define OMAP3430_SOURCE_48M_SHIFT 3 #define OMAP3430_SOURCE_48M_MASK (1 << 3) @@ -545,7 +557,9 @@ /* CM_CLKSEL3_PLL */ #define OMAP3430_DIV_96M_SHIFT 0 #define OMAP3430_DIV_96M_MASK (0x1f << 0) +#define OMAP3430_DIV_96M_WIDTH 5 #define OMAP3630_DIV_96M_MASK (0x3f << 0) +#define OMAP3630_DIV_96M_WIDTH 6 /* CM_CLKSEL4_PLL */ #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 @@ -556,12 +570,14 @@ /* CM_CLKSEL5_PLL */ #define OMAP3430ES2_DIV_120M_SHIFT 0 #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) +#define OMAP3430ES2_DIV_120M_WIDTH 5 /* CM_CLKOUT_CTRL */ #define OMAP3430_CLKOUT2_EN_SHIFT 7 #define OMAP3430_CLKOUT2_EN_MASK (1 << 7) #define OMAP3430_CLKOUT2_DIV_SHIFT 3 #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) +#define OMAP3430_CLKOUT2_DIV_WIDTH 3 #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) @@ -592,10 +608,14 @@ /* CM_CLKSEL_DSS */ #define OMAP3430_CLKSEL_TV_SHIFT 8 #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) +#define OMAP3430_CLKSEL_TV_WIDTH 5 #define OMAP3630_CLKSEL_TV_MASK (0x3f << 8) +#define OMAP3630_CLKSEL_TV_WIDTH 6 #define OMAP3430_CLKSEL_DSS1_SHIFT 0 #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) +#define OMAP3430_CLKSEL_DSS1_WIDTH 5 #define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0) +#define OMAP3630_CLKSEL_DSS1_WIDTH 6 /* CM_SLEEPDEP_DSS specific bits */ @@ -623,7 +643,9 @@ /* CM_CLKSEL_CAM */ #define OMAP3430_CLKSEL_CAM_SHIFT 0 #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) +#define OMAP3430_CLKSEL_CAM_WIDTH 5 #define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0) +#define OMAP3630_CLKSEL_CAM_WIDTH 6 /* CM_SLEEPDEP_CAM specific bits */ @@ -721,21 +743,30 @@ /* CM_CLKSEL1_EMU */ #define OMAP3430_DIV_DPLL4_SHIFT 24 #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) +#define OMAP3430_DIV_DPLL4_WIDTH 5 #define OMAP3630_DIV_DPLL4_MASK (0x3f << 24) +#define OMAP3630_DIV_DPLL4_WIDTH 6 #define OMAP3430_DIV_DPLL3_SHIFT 16 #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) +#define OMAP3430_DIV_DPLL3_WIDTH 5 #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) +#define OMAP3430_CLKSEL_TRACECLK_WIDTH 3 #define OMAP3430_CLKSEL_PCLK_SHIFT 8 #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) +#define OMAP3430_CLKSEL_PCLK_WIDTH 3 #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) +#define OMAP3430_CLKSEL_PCLKX2_WIDTH 2 #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) +#define OMAP3430_CLKSEL_ATCLK_WIDTH 2 #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) +#define OMAP3430_TRACE_MUX_CTRL_WIDTH 2 #define OMAP3430_MUX_CTRL_SHIFT 0 #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) +#define OMAP3430_MUX_CTRL_WIDTH 2 /* CM_CLKSTCTRL_EMU */ #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index f24e3f7a2bbc..93473f9a551c 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -1,7 +1,7 @@ /* * OMAP2+ Clock Management prototypes * - * Copyright (C) 2007-2009 Texas Instruments, Inc. + * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc. * Copyright (C) 2007-2009 Nokia Corporation * * Written by Paul Walmsley @@ -22,6 +22,12 @@ */ #define MAX_MODULE_READY_TIME 2000 +# ifndef __ASSEMBLER__ +extern void __iomem *cm_base; +extern void __iomem *cm2_base; +extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2); +# endif + /* * MAX_MODULE_DISABLE_TIME: max duration in microseconds to wait for * the PRCM to request that a module enter the inactive state in the @@ -33,4 +39,26 @@ */ #define MAX_MODULE_DISABLE_TIME 5000 +# ifndef __ASSEMBLER__ + +/** + * struct cm_ll_data - fn ptrs to per-SoC CM function implementations + * @split_idlest_reg: ptr to the SoC CM-specific split_idlest_reg impl + * @wait_module_ready: ptr to the SoC CM-specific wait_module_ready impl + */ +struct cm_ll_data { + int (*split_idlest_reg)(void __iomem *idlest_reg, s16 *prcm_inst, + u8 *idlest_reg_id); + int (*wait_module_ready)(s16 prcm_mod, u8 idlest_id, u8 idlest_shift); +}; + +extern int cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst, + u8 *idlest_reg_id); +extern int cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift); + +extern int cm_register(struct cm_ll_data *cld); +extern int cm_unregister(struct cm_ll_data *cld); + +# endif + #endif diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c new file mode 100644 index 000000000000..db650690e9d0 --- /dev/null +++ b/arch/arm/mach-omap2/cm2xxx.c @@ -0,0 +1,381 @@ +/* + * OMAP2xxx CM module functions + * + * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc. + * Paul Walmsley + * Rajendra Nayak <rnayak@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/io.h> + +#include "soc.h" +#include "iomap.h" +#include "common.h" +#include "prm2xxx.h" +#include "cm.h" +#include "cm2xxx.h" +#include "cm-regbits-24xx.h" +#include "clockdomain.h" + +/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */ +#define DPLL_AUTOIDLE_DISABLE 0x0 +#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3 + +/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */ +#define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0 +#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3 + +/* CM_IDLEST_PLL bit value offset for APLLs (OMAP2xxx only) */ +#define EN_APLL_LOCKED 3 + +static const u8 omap2xxx_cm_idlest_offs[] = { + CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4 +}; + +/* + * + */ + +static void _write_clktrctrl(u8 c, s16 module, u32 mask) +{ + u32 v; + + v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL); + v &= ~mask; + v |= c << __ffs(mask); + omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL); +} + +bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask) +{ + u32 v; + + v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL); + v &= mask; + v >>= __ffs(mask); + + return (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0; +} + +void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask) +{ + _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask); +} + +void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask) +{ + _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask); +} + +/* + * DPLL autoidle control + */ + +static void _omap2xxx_set_dpll_autoidle(u8 m) +{ + u32 v; + + v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); + v &= ~OMAP24XX_AUTO_DPLL_MASK; + v |= m << OMAP24XX_AUTO_DPLL_SHIFT; + omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); +} + +void omap2xxx_cm_set_dpll_disable_autoidle(void) +{ + _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP); +} + +void omap2xxx_cm_set_dpll_auto_low_power_stop(void) +{ + _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE); +} + +/* + * APLL control + */ + +static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask) +{ + u32 v; + + v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); + v &= ~mask; + v |= m << __ffs(mask); + omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); +} + +void omap2xxx_cm_set_apll54_disable_autoidle(void) +{ + _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP, + OMAP24XX_AUTO_54M_MASK); +} + +void omap2xxx_cm_set_apll54_auto_low_power_stop(void) +{ + _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE, + OMAP24XX_AUTO_54M_MASK); +} + +void omap2xxx_cm_set_apll96_disable_autoidle(void) +{ + _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP, + OMAP24XX_AUTO_96M_MASK); +} + +void omap2xxx_cm_set_apll96_auto_low_power_stop(void) +{ + _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE, + OMAP24XX_AUTO_96M_MASK); +} + +/* Enable an APLL if off */ +static int _omap2xxx_apll_enable(u8 enable_bit, u8 status_bit) +{ + u32 v, m; + + m = EN_APLL_LOCKED << enable_bit; + + v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); + if (v & m) + return 0; /* apll already enabled */ + + v |= m; + omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN); + + omap2xxx_cm_wait_module_ready(PLL_MOD, 1, status_bit); + + /* + * REVISIT: Should we return an error code if + * omap2xxx_cm_wait_module_ready() fails? + */ + return 0; +} + +/* Stop APLL */ +static void _omap2xxx_apll_disable(u8 enable_bit) +{ + u32 v; + + v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); + v &= ~(EN_APLL_LOCKED << enable_bit); + omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN); +} + +/* Enable an APLL if off */ +int omap2xxx_cm_apll54_enable(void) +{ + return _omap2xxx_apll_enable(OMAP24XX_EN_54M_PLL_SHIFT, + OMAP24XX_ST_54M_APLL_SHIFT); +} + +/* Enable an APLL if off */ +int omap2xxx_cm_apll96_enable(void) +{ + return _omap2xxx_apll_enable(OMAP24XX_EN_96M_PLL_SHIFT, + OMAP24XX_ST_96M_APLL_SHIFT); +} + +/* Stop APLL */ +void omap2xxx_cm_apll54_disable(void) +{ + _omap2xxx_apll_disable(OMAP24XX_EN_54M_PLL_SHIFT); +} + +/* Stop APLL */ +void omap2xxx_cm_apll96_disable(void) +{ + _omap2xxx_apll_disable(OMAP24XX_EN_96M_PLL_SHIFT); +} + +/** + * omap2xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components + * @idlest_reg: CM_IDLEST* virtual address + * @prcm_inst: pointer to an s16 to return the PRCM instance offset + * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID + * + * XXX This function is only needed until absolute register addresses are + * removed from the OMAP struct clk records. + */ +int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst, + u8 *idlest_reg_id) +{ + unsigned long offs; + u8 idlest_offs; + int i; + + if (idlest_reg < cm_base || idlest_reg > (cm_base + 0x0fff)) + return -EINVAL; + + idlest_offs = (unsigned long)idlest_reg & 0xff; + for (i = 0; i < ARRAY_SIZE(omap2xxx_cm_idlest_offs); i++) { + if (idlest_offs == omap2xxx_cm_idlest_offs[i]) { + *idlest_reg_id = i + 1; + break; + } + } + + if (i == ARRAY_SIZE(omap2xxx_cm_idlest_offs)) + return -EINVAL; + + offs = idlest_reg - cm_base; + offs &= 0xff00; + *prcm_inst = offs; + + return 0; +} + +/* + * + */ + +/** + * omap2xxx_cm_wait_module_ready - wait for a module to leave idle or standby + * @prcm_mod: PRCM module offset + * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3) + * @idlest_shift: shift of the bit in the CM_IDLEST* register to check + * + * Wait for the PRCM to indicate that the module identified by + * (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon + * success or -EBUSY if the module doesn't enable in time. + */ +int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) +{ + int ena = 0, i = 0; + u8 cm_idlest_reg; + u32 mask; + + if (!idlest_id || (idlest_id > ARRAY_SIZE(omap2xxx_cm_idlest_offs))) + return -EINVAL; + + cm_idlest_reg = omap2xxx_cm_idlest_offs[idlest_id - 1]; + + mask = 1 << idlest_shift; + ena = mask; + + omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & + mask) == ena), MAX_MODULE_READY_TIME, i); + + return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; +} + +/* Clockdomain low-level functions */ + +static void omap2xxx_clkdm_allow_idle(struct clockdomain *clkdm) +{ + if (atomic_read(&clkdm->usecount) > 0) + _clkdm_add_autodeps(clkdm); + + omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); +} + +static void omap2xxx_clkdm_deny_idle(struct clockdomain *clkdm) +{ + omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + + if (atomic_read(&clkdm->usecount) > 0) + _clkdm_del_autodeps(clkdm); +} + +static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm) +{ + bool hwsup = false; + + if (!clkdm->clktrctrl_mask) + return 0; + + hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + + if (hwsup) { + /* Disable HW transitions when we are changing deps */ + omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + _clkdm_add_autodeps(clkdm); + omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + } else { + if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) + omap2xxx_clkdm_wakeup(clkdm); + } + + return 0; +} + +static int omap2xxx_clkdm_clk_disable(struct clockdomain *clkdm) +{ + bool hwsup = false; + + if (!clkdm->clktrctrl_mask) + return 0; + + hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + + if (hwsup) { + /* Disable HW transitions when we are changing deps */ + omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + _clkdm_del_autodeps(clkdm); + omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + } else { + if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP) + omap2xxx_clkdm_sleep(clkdm); + } + + return 0; +} + +struct clkdm_ops omap2_clkdm_operations = { + .clkdm_add_wkdep = omap2_clkdm_add_wkdep, + .clkdm_del_wkdep = omap2_clkdm_del_wkdep, + .clkdm_read_wkdep = omap2_clkdm_read_wkdep, + .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps, + .clkdm_sleep = omap2xxx_clkdm_sleep, + .clkdm_wakeup = omap2xxx_clkdm_wakeup, + .clkdm_allow_idle = omap2xxx_clkdm_allow_idle, + .clkdm_deny_idle = omap2xxx_clkdm_deny_idle, + .clkdm_clk_enable = omap2xxx_clkdm_clk_enable, + .clkdm_clk_disable = omap2xxx_clkdm_clk_disable, +}; + +/* + * + */ + +static struct cm_ll_data omap2xxx_cm_ll_data = { + .split_idlest_reg = &omap2xxx_cm_split_idlest_reg, + .wait_module_ready = &omap2xxx_cm_wait_module_ready, +}; + +int __init omap2xxx_cm_init(void) +{ + if (!cpu_is_omap24xx()) + return 0; + + return cm_register(&omap2xxx_cm_ll_data); +} + +static void __exit omap2xxx_cm_exit(void) +{ + if (!cpu_is_omap24xx()) + return; + + /* Should never happen */ + WARN(cm_unregister(&omap2xxx_cm_ll_data), + "%s: cm_ll_data function pointer mismatch\n", __func__); +} +__exitcall(omap2xxx_cm_exit); diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h new file mode 100644 index 000000000000..4cbb39b051d2 --- /dev/null +++ b/arch/arm/mach-omap2/cm2xxx.h @@ -0,0 +1,70 @@ +/* + * OMAP2xxx Clock Management (CM) register definitions + * + * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc. + * Copyright (C) 2007-2010 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * The CM hardware modules on the OMAP2/3 are quite similar to each + * other. The CM modules/instances on OMAP4 are quite different, so + * they are handled in a separate file. + */ +#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_H +#define __ARCH_ASM_MACH_OMAP2_CM2XXX_H + +#include "prcm-common.h" +#include "cm2xxx_3xxx.h" + +#define OMAP2420_CM_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) +#define OMAP2430_CM_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) + +/* + * Module specific CM register offsets from CM_BASE + domain offset + * Use cm_{read,write}_mod_reg() with these registers. + * These register offsets generally appear in more than one PRCM submodule. + */ + +/* OMAP2-specific register offsets */ + +#define OMAP24XX_CM_FCLKEN2 0x0004 +#define OMAP24XX_CM_ICLKEN4 0x001c +#define OMAP24XX_CM_AUTOIDLE4 0x003c +#define OMAP24XX_CM_IDLEST4 0x002c + +/* CM_IDLEST bit field values to indicate deasserted IdleReq */ + +#define OMAP24XX_CM_IDLEST_VAL 0 + + +/* Clock management domain register get/set */ + +#ifndef __ASSEMBLER__ + +extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask); +extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask); + +extern void omap2xxx_cm_set_dpll_disable_autoidle(void); +extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void); + +extern void omap2xxx_cm_set_apll54_disable_autoidle(void); +extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void); +extern void omap2xxx_cm_set_apll96_disable_autoidle(void); +extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void); + +extern bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask); +extern int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, + u8 idlest_shift); +extern int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg, + s16 *prcm_inst, u8 *idlest_reg_id); + +extern int __init omap2xxx_cm_init(void); + +#endif + +#endif diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h index 57b2f3c2fbf3..bfbd16fe9151 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h @@ -16,28 +16,7 @@ #ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H #define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H -#include "prcm-common.h" - -#define OMAP2420_CM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) -#define OMAP2430_CM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) -#define OMAP34XX_CM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) - - -/* - * OMAP3-specific global CM registers - * Use cm_{read,write}_reg() with these registers. - * These registers appear once per CM module. - */ - -#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000) -#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010) -#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c) - -#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070 -#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) +#include "cm.h" /* * Module specific CM register offsets from CM_BASE + domain offset @@ -57,6 +36,7 @@ #define CM_IDLEST 0x0020 #define CM_IDLEST1 CM_IDLEST #define CM_IDLEST2 0x0024 +#define OMAP2430_CM_IDLEST3 0x0028 #define CM_AUTOIDLE 0x0030 #define CM_AUTOIDLE1 CM_AUTOIDLE #define CM_AUTOIDLE2 0x0034 @@ -66,70 +46,60 @@ #define CM_CLKSEL2 0x0044 #define OMAP2_CM_CLKSTCTRL 0x0048 -/* OMAP2-specific register offsets */ - -#define OMAP24XX_CM_FCLKEN2 0x0004 -#define OMAP24XX_CM_ICLKEN4 0x001c -#define OMAP24XX_CM_AUTOIDLE4 0x003c -#define OMAP24XX_CM_IDLEST4 0x002c - -#define OMAP2430_CM_IDLEST3 0x0028 - -/* OMAP3-specific register offsets */ - -#define OMAP3430_CM_CLKEN_PLL 0x0004 -#define OMAP3430ES2_CM_CLKEN2 0x0004 -#define OMAP3430ES2_CM_FCLKEN3 0x0008 -#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 -#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 -#define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2 -#define OMAP3430_CM_CLKSEL1 CM_CLKSEL -#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL -#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 -#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 -#define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL -#define OMAP3430_CM_CLKSTST 0x004c -#define OMAP3430ES2_CM_CLKSEL4 0x004c -#define OMAP3430ES2_CM_CLKSEL5 0x0050 -#define OMAP3430_CM_CLKSEL2_EMU 0x0050 -#define OMAP3430_CM_CLKSEL3_EMU 0x0054 +#ifndef __ASSEMBLER__ +#include <linux/io.h> -/* CM_IDLEST bit field values to indicate deasserted IdleReq */ +static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx) +{ + return __raw_readl(cm_base + module + idx); +} -#define OMAP24XX_CM_IDLEST_VAL 0 -#define OMAP34XX_CM_IDLEST_VAL 1 +static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx) +{ + __raw_writel(val, cm_base + module + idx); +} +/* Read-modify-write a register in a CM module. Caller must lock */ +static inline u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, + s16 idx) +{ + u32 v; -/* Clock management domain register get/set */ + v = omap2_cm_read_mod_reg(module, idx); + v &= ~mask; + v |= bits; + omap2_cm_write_mod_reg(v, module, idx); -#ifndef __ASSEMBLER__ + return v; +} -extern u32 omap2_cm_read_mod_reg(s16 module, u16 idx); -extern void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx); -extern u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); +/* Read a CM register, AND it, and shift the result down to bit 0 */ +static inline u32 omap2_cm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) +{ + u32 v; -extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, - u8 idlest_shift); -extern u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); -extern u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); + v = omap2_cm_read_mod_reg(domain, idx); + v &= mask; + v >>= __ffs(mask); -extern bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask); -extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask); -extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask); + return v; +} -extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask); -extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask); -extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask); -extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask); +static inline u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) +{ + return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx); +} -extern void omap2xxx_cm_set_dpll_disable_autoidle(void); -extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void); +static inline u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) +{ + return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx); +} -extern void omap2xxx_cm_set_apll54_disable_autoidle(void); -extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void); -extern void omap2xxx_cm_set_apll96_disable_autoidle(void); -extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void); +extern int omap2xxx_cm_apll54_enable(void); +extern void omap2xxx_cm_apll54_disable(void); +extern int omap2xxx_cm_apll96_enable(void); +extern void omap2xxx_cm_apll96_disable(void); #endif @@ -138,6 +108,7 @@ extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void); /* CM_CLKSEL_GFX */ #define OMAP_CLKSEL_GFX_SHIFT 0 #define OMAP_CLKSEL_GFX_MASK (0x7 << 0) +#define OMAP_CLKSEL_GFX_WIDTH 3 /* CM_ICLKEN_GFX */ #define OMAP_EN_GFX_SHIFT 0 @@ -146,11 +117,4 @@ extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void); /* CM_IDLEST_GFX */ #define OMAP_ST_GFX_MASK (1 << 0) - -/* Function prototypes */ -# ifndef __ASSEMBLER__ -extern void omap3_cm_save_context(void); -extern void omap3_cm_restore_context(void); -# endif - #endif diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c index 13f56eafef03..b2dfcd777194 100644 --- a/arch/arm/mach-omap2/cm33xx.c +++ b/arch/arm/mach-omap2/cm33xx.c @@ -22,8 +22,9 @@ #include <linux/err.h> #include <linux/io.h> -#include <plat/common.h> +#include "../plat-omap/common.h" +#include "clockdomain.h" #include "cm.h" #include "cm33xx.h" #include "cm-regbits-34xx.h" @@ -311,3 +312,58 @@ void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs) v &= ~AM33XX_MODULEMODE_MASK; am33xx_cm_write_reg(v, inst, clkctrl_offs); } + +/* + * Clockdomain low-level functions + */ + +static int am33xx_clkdm_sleep(struct clockdomain *clkdm) +{ + am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs); + return 0; +} + +static int am33xx_clkdm_wakeup(struct clockdomain *clkdm) +{ + am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs); + return 0; +} + +static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm) +{ + am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); +} + +static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm) +{ + am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); +} + +static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm) +{ + if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) + return am33xx_clkdm_wakeup(clkdm); + + return 0; +} + +static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm) +{ + bool hwsup = false; + + hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); + + if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) + am33xx_clkdm_sleep(clkdm); + + return 0; +} + +struct clkdm_ops am33xx_clkdm_operations = { + .clkdm_sleep = am33xx_clkdm_sleep, + .clkdm_wakeup = am33xx_clkdm_wakeup, + .clkdm_allow_idle = am33xx_clkdm_allow_idle, + .clkdm_deny_idle = am33xx_clkdm_deny_idle, + .clkdm_clk_enable = am33xx_clkdm_clk_enable, + .clkdm_clk_disable = am33xx_clkdm_clk_disable, +}; diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm3xxx.c index 7f07ab02a5b3..c2086f2e86b6 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/cm3xxx.c @@ -1,8 +1,10 @@ /* - * OMAP2/3 CM module functions + * OMAP3xxx CM module functions * * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc. * Paul Walmsley + * Rajendra Nayak <rnayak@ti.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -12,8 +14,6 @@ #include <linux/kernel.h> #include <linux/types.h> #include <linux/delay.h> -#include <linux/spinlock.h> -#include <linux/list.h> #include <linux/errno.h> #include <linux/err.h> #include <linux/io.h> @@ -21,56 +21,16 @@ #include "soc.h" #include "iomap.h" #include "common.h" +#include "prm2xxx_3xxx.h" #include "cm.h" -#include "cm2xxx_3xxx.h" -#include "cm-regbits-24xx.h" +#include "cm3xxx.h" #include "cm-regbits-34xx.h" +#include "clockdomain.h" -/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */ -#define DPLL_AUTOIDLE_DISABLE 0x0 -#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3 - -/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */ -#define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0 -#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3 - -static const u8 cm_idlest_offs[] = { - CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4 +static const u8 omap3xxx_cm_idlest_offs[] = { + CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 }; -u32 omap2_cm_read_mod_reg(s16 module, u16 idx) -{ - return __raw_readl(cm_base + module + idx); -} - -void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx) -{ - __raw_writel(val, cm_base + module + idx); -} - -/* Read-modify-write a register in a CM module. Caller must lock */ -u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) -{ - u32 v; - - v = omap2_cm_read_mod_reg(module, idx); - v &= ~mask; - v |= bits; - omap2_cm_write_mod_reg(v, module, idx); - - return v; -} - -u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) -{ - return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx); -} - -u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) -{ - return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx); -} - /* * */ @@ -85,33 +45,15 @@ static void _write_clktrctrl(u8 c, s16 module, u32 mask) omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL); } -bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask) +bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask) { u32 v; - bool ret = 0; - - BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx()); v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL); v &= mask; v >>= __ffs(mask); - if (cpu_is_omap24xx()) - ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0; - else - ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0; - - return ret; -} - -void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask) -{ - _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask); -} - -void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask) -{ - _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask); + return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0; } void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask) @@ -135,109 +77,247 @@ void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask) } /* - * DPLL autoidle control + * */ -static void _omap2xxx_set_dpll_autoidle(u8 m) +/** + * omap3xxx_cm_wait_module_ready - wait for a module to leave idle or standby + * @prcm_mod: PRCM module offset + * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3) + * @idlest_shift: shift of the bit in the CM_IDLEST* register to check + * + * Wait for the PRCM to indicate that the module identified by + * (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon + * success or -EBUSY if the module doesn't enable in time. + */ +int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) { - u32 v; + int ena = 0, i = 0; + u8 cm_idlest_reg; + u32 mask; - v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); - v &= ~OMAP24XX_AUTO_DPLL_MASK; - v |= m << OMAP24XX_AUTO_DPLL_SHIFT; - omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); -} + if (!idlest_id || (idlest_id > ARRAY_SIZE(omap3xxx_cm_idlest_offs))) + return -EINVAL; -void omap2xxx_cm_set_dpll_disable_autoidle(void) -{ - _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP); + cm_idlest_reg = omap3xxx_cm_idlest_offs[idlest_id - 1]; + + mask = 1 << idlest_shift; + ena = 0; + + omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & + mask) == ena), MAX_MODULE_READY_TIME, i); + + return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; } -void omap2xxx_cm_set_dpll_auto_low_power_stop(void) +/** + * omap3xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components + * @idlest_reg: CM_IDLEST* virtual address + * @prcm_inst: pointer to an s16 to return the PRCM instance offset + * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID + * + * XXX This function is only needed until absolute register addresses are + * removed from the OMAP struct clk records. + */ +int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst, + u8 *idlest_reg_id) { - _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE); + unsigned long offs; + u8 idlest_offs; + int i; + + if (idlest_reg < (cm_base + OMAP3430_IVA2_MOD) || + idlest_reg > (cm_base + 0x1ffff)) + return -EINVAL; + + idlest_offs = (unsigned long)idlest_reg & 0xff; + for (i = 0; i < ARRAY_SIZE(omap3xxx_cm_idlest_offs); i++) { + if (idlest_offs == omap3xxx_cm_idlest_offs[i]) { + *idlest_reg_id = i + 1; + break; + } + } + + if (i == ARRAY_SIZE(omap3xxx_cm_idlest_offs)) + return -EINVAL; + + offs = idlest_reg - cm_base; + offs &= 0xff00; + *prcm_inst = offs; + + return 0; } -/* - * APLL autoidle control - */ +/* Clockdomain low-level operations */ -static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask) +static int omap3xxx_clkdm_add_sleepdep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) { - u32 v; + omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit), + clkdm1->pwrdm.ptr->prcm_offs, + OMAP3430_CM_SLEEPDEP); + return 0; +} - v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); - v &= ~mask; - v |= m << __ffs(mask); - omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); +static int omap3xxx_clkdm_del_sleepdep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) +{ + omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit), + clkdm1->pwrdm.ptr->prcm_offs, + OMAP3430_CM_SLEEPDEP); + return 0; } -void omap2xxx_cm_set_apll54_disable_autoidle(void) +static int omap3xxx_clkdm_read_sleepdep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) { - _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP, - OMAP24XX_AUTO_54M_MASK); + return omap2_cm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, + OMAP3430_CM_SLEEPDEP, + (1 << clkdm2->dep_bit)); } -void omap2xxx_cm_set_apll54_auto_low_power_stop(void) +static int omap3xxx_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) { - _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE, - OMAP24XX_AUTO_54M_MASK); + struct clkdm_dep *cd; + u32 mask = 0; + + for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) { + if (!cd->clkdm) + continue; /* only happens if data is erroneous */ + + mask |= 1 << cd->clkdm->dep_bit; + atomic_set(&cd->sleepdep_usecount, 0); + } + omap2_cm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, + OMAP3430_CM_SLEEPDEP); + return 0; } -void omap2xxx_cm_set_apll96_disable_autoidle(void) +static int omap3xxx_clkdm_sleep(struct clockdomain *clkdm) { - _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP, - OMAP24XX_AUTO_96M_MASK); + omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + return 0; } -void omap2xxx_cm_set_apll96_auto_low_power_stop(void) +static int omap3xxx_clkdm_wakeup(struct clockdomain *clkdm) { - _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE, - OMAP24XX_AUTO_96M_MASK); + omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + return 0; } -/* - * - */ +static void omap3xxx_clkdm_allow_idle(struct clockdomain *clkdm) +{ + if (atomic_read(&clkdm->usecount) > 0) + _clkdm_add_autodeps(clkdm); -/** - * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby - * @prcm_mod: PRCM module offset - * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3) - * @idlest_shift: shift of the bit in the CM_IDLEST* register to check - * - * XXX document - */ -int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) + omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); +} + +static void omap3xxx_clkdm_deny_idle(struct clockdomain *clkdm) { - int ena = 0, i = 0; - u8 cm_idlest_reg; - u32 mask; + omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); - if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs))) - return -EINVAL; + if (atomic_read(&clkdm->usecount) > 0) + _clkdm_del_autodeps(clkdm); +} - cm_idlest_reg = cm_idlest_offs[idlest_id - 1]; +static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm) +{ + bool hwsup = false; - mask = 1 << idlest_shift; + if (!clkdm->clktrctrl_mask) + return 0; - if (cpu_is_omap24xx()) - ena = mask; - else if (cpu_is_omap34xx()) - ena = 0; - else - BUG(); + /* + * The CLKDM_MISSING_IDLE_REPORTING flag documentation has + * more details on the unpleasant problem this is working + * around + */ + if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) && + (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) { + omap3xxx_clkdm_wakeup(clkdm); + return 0; + } + + hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + + if (hwsup) { + /* Disable HW transitions when we are changing deps */ + omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + _clkdm_add_autodeps(clkdm); + omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + } else { + if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) + omap3xxx_clkdm_wakeup(clkdm); + } + + return 0; +} - omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), - MAX_MODULE_READY_TIME, i); +static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm) +{ + bool hwsup = false; - return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; + if (!clkdm->clktrctrl_mask) + return 0; + + /* + * The CLKDM_MISSING_IDLE_REPORTING flag documentation has + * more details on the unpleasant problem this is working + * around + */ + if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING && + !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) { + omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + return 0; + } + + hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + + if (hwsup) { + /* Disable HW transitions when we are changing deps */ + omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + _clkdm_del_autodeps(clkdm); + omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, + clkdm->clktrctrl_mask); + } else { + if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP) + omap3xxx_clkdm_sleep(clkdm); + } + + return 0; } +struct clkdm_ops omap3_clkdm_operations = { + .clkdm_add_wkdep = omap2_clkdm_add_wkdep, + .clkdm_del_wkdep = omap2_clkdm_del_wkdep, + .clkdm_read_wkdep = omap2_clkdm_read_wkdep, + .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps, + .clkdm_add_sleepdep = omap3xxx_clkdm_add_sleepdep, + .clkdm_del_sleepdep = omap3xxx_clkdm_del_sleepdep, + .clkdm_read_sleepdep = omap3xxx_clkdm_read_sleepdep, + .clkdm_clear_all_sleepdeps = omap3xxx_clkdm_clear_all_sleepdeps, + .clkdm_sleep = omap3xxx_clkdm_sleep, + .clkdm_wakeup = omap3xxx_clkdm_wakeup, + .clkdm_allow_idle = omap3xxx_clkdm_allow_idle, + .clkdm_deny_idle = omap3xxx_clkdm_deny_idle, + .clkdm_clk_enable = omap3xxx_clkdm_clk_enable, + .clkdm_clk_disable = omap3xxx_clkdm_clk_disable, +}; + /* * Context save/restore code - OMAP3 only */ -#ifdef CONFIG_ARCH_OMAP3 struct omap3_cm_regs { u32 iva2_cm_clksel1; u32 iva2_cm_clksel2; @@ -555,4 +635,31 @@ void omap3_cm_restore_context(void) omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD, OMAP3_CM_CLKOUT_CTRL_OFFSET); } -#endif + +/* + * + */ + +static struct cm_ll_data omap3xxx_cm_ll_data = { + .split_idlest_reg = &omap3xxx_cm_split_idlest_reg, + .wait_module_ready = &omap3xxx_cm_wait_module_ready, +}; + +int __init omap3xxx_cm_init(void) +{ + if (!cpu_is_omap34xx()) + return 0; + + return cm_register(&omap3xxx_cm_ll_data); +} + +static void __exit omap3xxx_cm_exit(void) +{ + if (!cpu_is_omap34xx()) + return; + + /* Should never happen */ + WARN(cm_unregister(&omap3xxx_cm_ll_data), + "%s: cm_ll_data function pointer mismatch\n", __func__); +} +__exitcall(omap3xxx_cm_exit); diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h new file mode 100644 index 000000000000..e8e146f4a43f --- /dev/null +++ b/arch/arm/mach-omap2/cm3xxx.h @@ -0,0 +1,91 @@ +/* + * OMAP2/3 Clock Management (CM) register definitions + * + * Copyright (C) 2007-2009 Texas Instruments, Inc. + * Copyright (C) 2007-2010 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * The CM hardware modules on the OMAP2/3 are quite similar to each + * other. The CM modules/instances on OMAP4 are quite different, so + * they are handled in a separate file. + */ +#ifndef __ARCH_ASM_MACH_OMAP2_CM3XXX_H +#define __ARCH_ASM_MACH_OMAP2_CM3XXX_H + +#include "prcm-common.h" +#include "cm2xxx_3xxx.h" + +#define OMAP34XX_CM_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) + + +/* + * OMAP3-specific global CM registers + * Use cm_{read,write}_reg() with these registers. + * These registers appear once per CM module. + */ + +#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000) +#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010) +#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c) + +#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070 +#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) + +/* + * Module specific CM register offsets from CM_BASE + domain offset + * Use cm_{read,write}_mod_reg() with these registers. + * These register offsets generally appear in more than one PRCM submodule. + */ + +/* OMAP3-specific register offsets */ + +#define OMAP3430_CM_CLKEN_PLL 0x0004 +#define OMAP3430ES2_CM_CLKEN2 0x0004 +#define OMAP3430ES2_CM_FCLKEN3 0x0008 +#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 +#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 +#define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2 +#define OMAP3430_CM_CLKSEL1 CM_CLKSEL +#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL +#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 +#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 +#define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL +#define OMAP3430_CM_CLKSTST 0x004c +#define OMAP3430ES2_CM_CLKSEL4 0x004c +#define OMAP3430ES2_CM_CLKSEL5 0x0050 +#define OMAP3430_CM_CLKSEL2_EMU 0x0050 +#define OMAP3430_CM_CLKSEL3_EMU 0x0054 + + +/* CM_IDLEST bit field values to indicate deasserted IdleReq */ + +#define OMAP34XX_CM_IDLEST_VAL 1 + + +#ifndef __ASSEMBLER__ + +extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask); +extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask); +extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask); +extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask); + +extern bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask); +extern int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, + u8 idlest_shift); + +extern int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg, + s16 *prcm_inst, u8 *idlest_reg_id); + +extern void omap3_cm_save_context(void); +extern void omap3_cm_restore_context(void); + +extern int __init omap3xxx_cm_init(void); + +#endif + +#endif diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c new file mode 100644 index 000000000000..0bab493ec133 --- /dev/null +++ b/arch/arm/mach-omap2/cm_common.c @@ -0,0 +1,139 @@ +/* + * OMAP2+ common Clock Management (CM) IP block functions + * + * Copyright (C) 2012 Texas Instruments, Inc. + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * XXX This code should eventually be moved to a CM driver. + */ + +#include <linux/kernel.h> +#include <linux/init.h> + +#include "cm2xxx.h" +#include "cm3xxx.h" +#include "cm44xx.h" +#include "common.h" + +/* + * cm_ll_data: function pointers to SoC-specific implementations of + * common CM functions + */ +static struct cm_ll_data null_cm_ll_data; +static struct cm_ll_data *cm_ll_data = &null_cm_ll_data; + +/* cm_base: base virtual address of the CM IP block */ +void __iomem *cm_base; + +/* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */ +void __iomem *cm2_base; + +/** + * omap2_set_globals_cm - set the CM/CM2 base addresses (for early use) + * @cm: CM base virtual address + * @cm2: CM2 base virtual address (if present on the booted SoC) + * + * XXX Will be replaced when the PRM/CM drivers are completed. + */ +void __init omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2) +{ + cm_base = cm; + cm2_base = cm2; +} + +/** + * cm_split_idlest_reg - split CM_IDLEST reg addr into its components + * @idlest_reg: CM_IDLEST* virtual address + * @prcm_inst: pointer to an s16 to return the PRCM instance offset + * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID + * + * Given an absolute CM_IDLEST register address @idlest_reg, passes + * the PRCM instance offset and IDLEST register ID back to the caller + * via the @prcm_inst and @idlest_reg_id. Returns -EINVAL upon error, + * or 0 upon success. XXX This function is only needed until absolute + * register addresses are removed from the OMAP struct clk records. + */ +int cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst, + u8 *idlest_reg_id) +{ + if (!cm_ll_data->split_idlest_reg) { + WARN_ONCE(1, "cm: %s: no low-level function defined\n", + __func__); + return -EINVAL; + } + + return cm_ll_data->split_idlest_reg(idlest_reg, prcm_inst, + idlest_reg_id); +} + +/** + * cm_wait_module_ready - wait for a module to leave idle or standby + * @prcm_mod: PRCM module offset + * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3) + * @idlest_shift: shift of the bit in the CM_IDLEST* register to check + * + * Wait for the PRCM to indicate that the module identified by + * (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon + * success, -EBUSY if the module doesn't enable in time, or -EINVAL if + * no per-SoC wait_module_ready() function pointer has been registered + * or if the idlest register is unknown on the SoC. + */ +int cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) +{ + if (!cm_ll_data->wait_module_ready) { + WARN_ONCE(1, "cm: %s: no low-level function defined\n", + __func__); + return -EINVAL; + } + + return cm_ll_data->wait_module_ready(prcm_mod, idlest_id, idlest_shift); +} + +/** + * cm_register - register per-SoC low-level data with the CM + * @cld: low-level per-SoC OMAP CM data & function pointers to register + * + * Register per-SoC low-level OMAP CM data and function pointers with + * the OMAP CM common interface. The caller must keep the data + * pointed to by @cld valid until it calls cm_unregister() and + * it returns successfully. Returns 0 upon success, -EINVAL if @cld + * is NULL, or -EEXIST if cm_register() has already been called + * without an intervening cm_unregister(). + */ +int cm_register(struct cm_ll_data *cld) +{ + if (!cld) + return -EINVAL; + + if (cm_ll_data != &null_cm_ll_data) + return -EEXIST; + + cm_ll_data = cld; + + return 0; +} + +/** + * cm_unregister - unregister per-SoC low-level data & function pointers + * @cld: low-level per-SoC OMAP CM data & function pointers to unregister + * + * Unregister per-SoC low-level OMAP CM data and function pointers + * that were previously registered with cm_register(). The + * caller may not destroy any of the data pointed to by @cld until + * this function returns successfully. Returns 0 upon success, or + * -EINVAL if @cld is NULL or if @cld does not match the struct + * cm_ll_data * previously registered by cm_register(). + */ +int cm_unregister(struct cm_ll_data *cld) +{ + if (!cld || cm_ll_data != cld) + return -EINVAL; + + cm_ll_data = &null_cm_ll_data; + + return 0; +} diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c index 1894015ff04b..7f9a464f01e9 100644 --- a/arch/arm/mach-omap2/cminst44xx.c +++ b/arch/arm/mach-omap2/cminst44xx.c @@ -2,8 +2,9 @@ * OMAP4 CM instance functions * * Copyright (C) 2009 Nokia Corporation - * Copyright (C) 2011 Texas Instruments, Inc. + * Copyright (C) 2008-2011 Texas Instruments, Inc. * Paul Walmsley + * Rajendra Nayak <rnayak@ti.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -22,6 +23,7 @@ #include "iomap.h" #include "common.h" +#include "clockdomain.h" #include "cm.h" #include "cm1_44xx.h" #include "cm2_44xx.h" @@ -343,3 +345,141 @@ void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs, v &= ~OMAP4430_MODULEMODE_MASK; omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs); } + +/* + * Clockdomain low-level functions + */ + +static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) +{ + omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit), + clkdm1->prcm_partition, + clkdm1->cm_inst, clkdm1->clkdm_offs + + OMAP4_CM_STATICDEP); + return 0; +} + +static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) +{ + omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit), + clkdm1->prcm_partition, + clkdm1->cm_inst, clkdm1->clkdm_offs + + OMAP4_CM_STATICDEP); + return 0; +} + +static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) +{ + return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition, + clkdm1->cm_inst, + clkdm1->clkdm_offs + + OMAP4_CM_STATICDEP, + (1 << clkdm2->dep_bit)); +} + +static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm) +{ + struct clkdm_dep *cd; + u32 mask = 0; + + if (!clkdm->prcm_partition) + return 0; + + for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { + if (!cd->clkdm) + continue; /* only happens if data is erroneous */ + + mask |= 1 << cd->clkdm->dep_bit; + atomic_set(&cd->wkdep_usecount, 0); + } + + omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition, + clkdm->cm_inst, clkdm->clkdm_offs + + OMAP4_CM_STATICDEP); + return 0; +} + +static int omap4_clkdm_sleep(struct clockdomain *clkdm) +{ + omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, + clkdm->cm_inst, clkdm->clkdm_offs); + return 0; +} + +static int omap4_clkdm_wakeup(struct clockdomain *clkdm) +{ + omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition, + clkdm->cm_inst, clkdm->clkdm_offs); + return 0; +} + +static void omap4_clkdm_allow_idle(struct clockdomain *clkdm) +{ + omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, + clkdm->cm_inst, clkdm->clkdm_offs); +} + +static void omap4_clkdm_deny_idle(struct clockdomain *clkdm) +{ + if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) + omap4_clkdm_wakeup(clkdm); + else + omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition, + clkdm->cm_inst, + clkdm->clkdm_offs); +} + +static int omap4_clkdm_clk_enable(struct clockdomain *clkdm) +{ + if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) + return omap4_clkdm_wakeup(clkdm); + + return 0; +} + +static int omap4_clkdm_clk_disable(struct clockdomain *clkdm) +{ + bool hwsup = false; + + if (!clkdm->prcm_partition) + return 0; + + /* + * The CLKDM_MISSING_IDLE_REPORTING flag documentation has + * more details on the unpleasant problem this is working + * around + */ + if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING && + !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) { + omap4_clkdm_allow_idle(clkdm); + return 0; + } + + hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, + clkdm->cm_inst, clkdm->clkdm_offs); + + if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) + omap4_clkdm_sleep(clkdm); + + return 0; +} + +struct clkdm_ops omap4_clkdm_operations = { + .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep, + .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep, + .clkdm_read_wkdep = omap4_clkdm_read_wkup_sleep_dep, + .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps, + .clkdm_add_sleepdep = omap4_clkdm_add_wkup_sleep_dep, + .clkdm_del_sleepdep = omap4_clkdm_del_wkup_sleep_dep, + .clkdm_read_sleepdep = omap4_clkdm_read_wkup_sleep_dep, + .clkdm_clear_all_sleepdeps = omap4_clkdm_clear_all_wkup_sleep_deps, + .clkdm_sleep = omap4_clkdm_sleep, + .clkdm_wakeup = omap4_clkdm_wakeup, + .clkdm_allow_idle = omap4_clkdm_allow_idle, + .clkdm_deny_idle = omap4_clkdm_deny_idle, + .clkdm_clk_enable = omap4_clkdm_clk_enable, + .clkdm_clk_disable = omap4_clkdm_clk_disable, +}; diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h index d69fdefef985..bd7bab889745 100644 --- a/arch/arm/mach-omap2/cminst44xx.h +++ b/arch/arm/mach-omap2/cminst44xx.h @@ -38,4 +38,6 @@ extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask); +extern void omap_cm_base_init(void); + #endif diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c index 48daac2581b4..ad856092c06a 100644 --- a/arch/arm/mach-omap2/common-board-devices.c +++ b/arch/arm/mach-omap2/common-board-devices.c @@ -25,7 +25,6 @@ #include <linux/spi/ads7846.h> #include <linux/platform_data/spi-omap2-mcspi.h> -#include <linux/platform_data/mtd-nand-omap2.h> #include "common.h" #include "common-board-devices.h" @@ -96,48 +95,3 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce, { } #endif - -#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE) -static struct omap_nand_platform_data nand_data; - -void __init omap_nand_flash_init(int options, struct mtd_partition *parts, - int nr_parts) -{ - u8 cs = 0; - u8 nandcs = GPMC_CS_NUM + 1; - - /* find out the chip-select on which NAND exists */ - while (cs < GPMC_CS_NUM) { - u32 ret = 0; - ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); - - if ((ret & 0xC00) == 0x800) { - printk(KERN_INFO "Found NAND on CS%d\n", cs); - if (nandcs > GPMC_CS_NUM) - nandcs = cs; - } - cs++; - } - - if (nandcs > GPMC_CS_NUM) { - pr_info("NAND: Unable to find configuration in GPMC\n"); - return; - } - - if (nandcs < GPMC_CS_NUM) { - nand_data.cs = nandcs; - nand_data.parts = parts; - nand_data.nr_parts = nr_parts; - nand_data.devsize = options; - - printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); - if (gpmc_nand_init(&nand_data) < 0) - printk(KERN_ERR "Unable to register NAND device\n"); - } -} -#else -void __init omap_nand_flash_init(int options, struct mtd_partition *parts, - int nr_parts) -{ -} -#endif diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h index a0b4a42836ab..72bb41b3fd25 100644 --- a/arch/arm/mach-omap2/common-board-devices.h +++ b/arch/arm/mach-omap2/common-board-devices.h @@ -10,6 +10,5 @@ struct ads7846_platform_data; void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce, struct ads7846_platform_data *board_pdata); -void omap_nand_flash_init(int opts, struct mtd_partition *parts, int n_parts); #endif /* __OMAP_COMMON_BOARD_DEVICES__ */ diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c index 17950c6e130b..5c2fd4863b2b 100644 --- a/arch/arm/mach-omap2/common.c +++ b/arch/arm/mach-omap2/common.c @@ -14,189 +14,26 @@ */ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/clk.h> -#include <linux/io.h> +#include <linux/platform_data/dsp-omap.h> -#include <plat/clock.h> +#include <plat/vram.h> -#include "soc.h" -#include "iomap.h" #include "common.h" -#include "sdrc.h" -#include "control.h" - -/* Global address base setup code */ - -static void __init __omap2_set_globals(struct omap_globals *omap2_globals) -{ - omap2_set_globals_tap(omap2_globals); - omap2_set_globals_sdrc(omap2_globals); - omap2_set_globals_control(omap2_globals); - omap2_set_globals_prcm(omap2_globals); -} - -#if defined(CONFIG_SOC_OMAP2420) - -static struct omap_globals omap242x_globals = { - .class = OMAP242X_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(0x48014000), - .sdrc = OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), - .sms = OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE), - .ctrl = OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE), - .prm = OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE), - .cm = OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), -}; - -void __init omap2_set_globals_242x(void) -{ - __omap2_set_globals(&omap242x_globals); -} - -void __init omap242x_map_io(void) -{ - omap242x_map_common_io(); -} -#endif - -#if defined(CONFIG_SOC_OMAP2430) - -static struct omap_globals omap243x_globals = { - .class = OMAP243X_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(0x4900a000), - .sdrc = OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), - .sms = OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE), - .ctrl = OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), - .prm = OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE), - .cm = OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), -}; - -void __init omap2_set_globals_243x(void) -{ - __omap2_set_globals(&omap243x_globals); -} - -void __init omap243x_map_io(void) -{ - omap243x_map_common_io(); -} -#endif - -#if defined(CONFIG_ARCH_OMAP3) - -static struct omap_globals omap3_globals = { - .class = OMAP343X_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(0x4830A000), - .sdrc = OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), - .sms = OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE), - .ctrl = OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), - .prm = OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE), - .cm = OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), -}; - -void __init omap2_set_globals_3xxx(void) -{ - __omap2_set_globals(&omap3_globals); -} - -void __init omap3_map_io(void) -{ - omap34xx_map_common_io(); -} +#include "omap-secure.h" /* - * Adjust TAP register base such that omap3_check_revision accesses the correct - * TI81XX register for checking device ID (it adds 0x204 to tap base while - * TI81XX DEVICE ID register is at offset 0x600 from control base). + * Stub function for OMAP2 so that common files + * continue to build when custom builds are used */ -#define TI81XX_TAP_BASE (TI81XX_CTRL_BASE + \ - TI81XX_CONTROL_DEVICE_ID - 0x204) - -static struct omap_globals ti81xx_globals = { - .class = OMAP343X_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE), - .ctrl = OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), - .prm = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), - .cm = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), -}; - -void __init omap2_set_globals_ti81xx(void) -{ - __omap2_set_globals(&ti81xx_globals); -} - -void __init ti81xx_map_io(void) -{ - omapti81xx_map_common_io(); -} -#endif - -#if defined(CONFIG_SOC_AM33XX) -#define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + \ - TI81XX_CONTROL_DEVICE_ID - 0x204) - -static struct omap_globals am33xx_globals = { - .class = AM335X_CLASS, - .tap = AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE), - .ctrl = AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), - .prm = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), - .cm = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), -}; - -void __init omap2_set_globals_am33xx(void) -{ - __omap2_set_globals(&am33xx_globals); -} - -void __init am33xx_map_io(void) -{ - omapam33xx_map_common_io(); -} -#endif - -#if defined(CONFIG_ARCH_OMAP4) -static struct omap_globals omap4_globals = { - .class = OMAP443X_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), - .ctrl = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), - .ctrl_pad = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE), - .prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE), - .cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), - .cm2 = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE), - .prcm_mpu = OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE), -}; - -void __init omap2_set_globals_443x(void) -{ - __omap2_set_globals(&omap4_globals); -} - -void __init omap4_map_io(void) -{ - omap44xx_map_common_io(); -} -#endif - -#if defined(CONFIG_SOC_OMAP5) -static struct omap_globals omap5_globals = { - .class = OMAP54XX_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), - .ctrl = OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), - .ctrl_pad = OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE), - .prm = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE), - .cm = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE), - .cm2 = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE), - .prcm_mpu = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE), -}; - -void __init omap2_set_globals_5xxx(void) +int __weak omap_secure_ram_reserve_memblock(void) { - omap2_set_globals_tap(&omap5_globals); - omap2_set_globals_control(&omap5_globals); - omap2_set_globals_prcm(&omap5_globals); + return 0; } -void __init omap5_map_io(void) +void __init omap_reserve(void) { - omap5_map_common_io(); + omap_vram_reserve_sdram_memblock(); + omap_dsp_reserve_sdram_memblock(); + omap_secure_ram_reserve_memblock(); + omap_barrier_reserve_memblock(); } -#endif diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 7045e4d61ac3..c57eeeac7d11 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -28,63 +28,20 @@ #include <linux/irq.h> #include <linux/delay.h> +#include <linux/i2c.h> #include <linux/i2c/twl.h> +#include <linux/i2c-omap.h> #include <asm/proc-fns.h> -#include <plat/cpu.h> -#include <plat/serial.h> -#include <plat/common.h> +#include "../plat-omap/common.h" -#define OMAP_INTC_START NR_IRQS +#include "i2c.h" +#include "serial.h" -#ifdef CONFIG_SOC_OMAP2420 -extern void omap242x_map_common_io(void); -#else -static inline void omap242x_map_common_io(void) -{ -} -#endif - -#ifdef CONFIG_SOC_OMAP2430 -extern void omap243x_map_common_io(void); -#else -static inline void omap243x_map_common_io(void) -{ -} -#endif +#include "usb.h" -#ifdef CONFIG_ARCH_OMAP3 -extern void omap34xx_map_common_io(void); -#else -static inline void omap34xx_map_common_io(void) -{ -} -#endif - -#ifdef CONFIG_SOC_TI81XX -extern void omapti81xx_map_common_io(void); -#else -static inline void omapti81xx_map_common_io(void) -{ -} -#endif - -#ifdef CONFIG_SOC_AM33XX -extern void omapam33xx_map_common_io(void); -#else -static inline void omapam33xx_map_common_io(void) -{ -} -#endif - -#ifdef CONFIG_ARCH_OMAP4 -extern void omap44xx_map_common_io(void); -#else -static inline void omap44xx_map_common_io(void) -{ -} -#endif +#define OMAP_INTC_START NR_IRQS #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP2) int omap2_pm_init(void); @@ -122,14 +79,6 @@ static inline int omap_mux_late_init(void) } #endif -#ifdef CONFIG_SOC_OMAP5 -extern void omap5_map_common_io(void); -#else -static inline void omap5_map_common_io(void) -{ -} -#endif - extern void omap2_init_common_infrastructure(void); extern struct sys_timer omap2_timer; @@ -162,52 +111,43 @@ void am35xx_init_late(void); void ti81xx_init_late(void); void omap4430_init_late(void); int omap2_common_pm_late_init(void); -void omap_prcm_restart(char, const char *); -/* - * IO bases for various OMAP processors - * Except the tap base, rest all the io bases - * listed are physical addresses. - */ -struct omap_globals { - u32 class; /* OMAP class to detect */ - void __iomem *tap; /* Control module ID code */ - void __iomem *sdrc; /* SDRAM Controller */ - void __iomem *sms; /* SDRAM Memory Scheduler */ - void __iomem *ctrl; /* System Control Module */ - void __iomem *ctrl_pad; /* PAD Control Module */ - void __iomem *prm; /* Power and Reset Management */ - void __iomem *cm; /* Clock Management */ - void __iomem *cm2; - void __iomem *prcm_mpu; -}; - -void omap2_set_globals_242x(void); -void omap2_set_globals_243x(void); -void omap2_set_globals_3xxx(void); -void omap2_set_globals_443x(void); -void omap2_set_globals_5xxx(void); -void omap2_set_globals_ti81xx(void); -void omap2_set_globals_am33xx(void); - -/* These get called from omap2_set_globals_xxxx(), do not call these */ -void omap2_set_globals_tap(struct omap_globals *); -#if defined(CONFIG_SOC_HAS_OMAP2_SDRC) -void omap2_set_globals_sdrc(struct omap_globals *); +#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) +void omap2xxx_restart(char mode, const char *cmd); #else -static inline void omap2_set_globals_sdrc(struct omap_globals *omap2_globals) -{ } +static inline void omap2xxx_restart(char mode, const char *cmd) +{ +} #endif -void omap2_set_globals_control(struct omap_globals *); -void omap2_set_globals_prcm(struct omap_globals *); - -void omap242x_map_io(void); -void omap243x_map_io(void); -void omap3_map_io(void); -void am33xx_map_io(void); -void omap4_map_io(void); -void omap5_map_io(void); -void ti81xx_map_io(void); + +#ifdef CONFIG_ARCH_OMAP3 +void omap3xxx_restart(char mode, const char *cmd); +#else +static inline void omap3xxx_restart(char mode, const char *cmd) +{ +} +#endif + +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) +void omap44xx_restart(char mode, const char *cmd); +#else +static inline void omap44xx_restart(char mode, const char *cmd) +{ +} +#endif + +/* This gets called from mach-omap2/io.c, do not call this */ +void __init omap2_set_globals_tap(u32 class, void __iomem *tap); + +void __init omap242x_map_io(void); +void __init omap243x_map_io(void); +void __init omap3_map_io(void); +void __init am33xx_map_io(void); +void __init omap4_map_io(void); +void __init omap5_map_io(void); +void __init ti81xx_map_io(void); + +/* omap_barriers_init() is OMAP4 only */ void omap_barriers_init(void); /** @@ -338,6 +278,7 @@ extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1); struct omap2_hsmmc_info; extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers); +extern void omap_reserve(void); #endif /* __ASSEMBLER__ */ #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index d1ff8399a222..2adb2683f074 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -1,7 +1,7 @@ /* * OMAP2/3 System Control Module register access * - * Copyright (C) 2007 Texas Instruments, Inc. + * Copyright (C) 2007, 2012 Texas Instruments, Inc. * Copyright (C) 2007 Nokia Corporation * * Written by Paul Walmsley @@ -15,15 +15,13 @@ #include <linux/kernel.h> #include <linux/io.h> -#include <plat/sdrc.h> - #include "soc.h" #include "iomap.h" #include "common.h" #include "cm-regbits-34xx.h" #include "prm-regbits-34xx.h" -#include "prm2xxx_3xxx.h" -#include "cm2xxx_3xxx.h" +#include "prm3xxx.h" +#include "cm3xxx.h" #include "sdrc.h" #include "pm.h" #include "control.h" @@ -149,13 +147,11 @@ static struct omap3_control_regs control_context; #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) #define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg)) -void __init omap2_set_globals_control(struct omap_globals *omap2_globals) +void __init omap2_set_globals_control(void __iomem *ctrl, + void __iomem *ctrl_pad) { - if (omap2_globals->ctrl) - omap2_ctrl_base = omap2_globals->ctrl; - - if (omap2_globals->ctrl_pad) - omap4_ctrl_pad_base = omap2_globals->ctrl_pad; + omap2_ctrl_base = ctrl; + omap4_ctrl_pad_base = ctrl_pad; } void __iomem *omap_ctrl_base_get(void) diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index d236257626bf..3d944d3263d2 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -415,6 +415,8 @@ extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr); extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); extern void omap3630_ctrl_disable_rta(void); extern int omap3_ctrl_save_padconf(void); +extern void omap2_set_globals_control(void __iomem *ctrl, + void __iomem *ctrl_pad); #else #define omap_ctrl_base_get() 0 #define omap_ctrl_readb(x) 0 diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index bc2756959be5..bca7a8885703 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -27,7 +27,6 @@ #include <linux/export.h> #include <linux/cpu_pm.h> -#include <plat/prcm.h> #include "powerdomain.h" #include "clockdomain.h" diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index c72b5a727720..d2215e9873a5 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -24,10 +24,11 @@ #include <asm/mach-types.h> #include <asm/mach/map.h> +#include <plat-omap/dma-omap.h> + #include "iomap.h" -#include <plat/dma.h> -#include <plat/omap_hwmod.h> -#include <plat/omap_device.h> +#include "omap_hwmod.h" +#include "omap_device.h" #include "omap4-keypad.h" #include "soc.h" @@ -35,6 +36,7 @@ #include "mux.h" #include "control.h" #include "devices.h" +#include "dma.h" #define L3_MODULES_MAX_LEN 12 #define L3_MODULES 3 @@ -723,29 +725,3 @@ static int __init omap2_init_devices(void) return 0; } arch_initcall(omap2_init_devices); - -#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) -static int __init omap_init_wdt(void) -{ - int id = -1; - struct platform_device *pdev; - struct omap_hwmod *oh; - char *oh_name = "wd_timer2"; - char *dev_name = "omap_wdt"; - - if (!cpu_class_is_omap2() || of_have_populated_dt()) - return 0; - - oh = omap_hwmod_lookup(oh_name); - if (!oh) { - pr_err("Could not look up wd_timer%d hwmod\n", id); - return -EINVAL; - } - - pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0); - WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n", - dev_name, oh->name); - return 0; -} -subsys_initcall(omap_init_wdt); -#endif diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index 1011995f150a..38ba58c97628 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -25,15 +25,17 @@ #include <linux/delay.h> #include <video/omapdss.h> -#include <plat/omap_hwmod.h> -#include <plat/omap_device.h> -#include <plat/omap-pm.h> +#include "omap_hwmod.h" +#include "omap_device.h" +#include "omap-pm.h" #include "common.h" +#include "soc.h" #include "iomap.h" #include "mux.h" #include "control.h" #include "display.h" +#include "prm.h" #define DISPC_CONTROL 0x0040 #define DISPC_CONTROL2 0x0238 @@ -284,6 +286,35 @@ err: return ERR_PTR(r); } +static enum omapdss_version __init omap_display_get_version(void) +{ + if (cpu_is_omap24xx()) + return OMAPDSS_VER_OMAP24xx; + else if (cpu_is_omap3630()) + return OMAPDSS_VER_OMAP3630; + else if (cpu_is_omap34xx()) { + if (soc_is_am35xx()) { + return OMAPDSS_VER_AM35xx; + } else { + if (omap_rev() < OMAP3430_REV_ES3_0) + return OMAPDSS_VER_OMAP34xx_ES1; + else + return OMAPDSS_VER_OMAP34xx_ES3; + } + } else if (omap_rev() == OMAP4430_REV_ES1_0) + return OMAPDSS_VER_OMAP4430_ES1; + else if (omap_rev() == OMAP4430_REV_ES2_0 || + omap_rev() == OMAP4430_REV_ES2_1 || + omap_rev() == OMAP4430_REV_ES2_2) + return OMAPDSS_VER_OMAP4430_ES2; + else if (cpu_is_omap44xx()) + return OMAPDSS_VER_OMAP4; + else if (soc_is_omap54xx()) + return OMAPDSS_VER_OMAP5; + else + return OMAPDSS_VER_UNKNOWN; +} + int __init omap_display_init(struct omap_dss_board_info *board_data) { int r = 0; @@ -291,9 +322,18 @@ int __init omap_display_init(struct omap_dss_board_info *board_data) int i, oh_count; const struct omap_dss_hwmod_data *curr_dss_hwmod; struct platform_device *dss_pdev; + enum omapdss_version ver; /* create omapdss device */ + ver = omap_display_get_version(); + + if (ver == OMAPDSS_VER_UNKNOWN) { + pr_err("DSS not supported on this SoC\n"); + return -ENODEV; + } + + board_data->version = ver; board_data->dsi_enable_pads = omap_dsi_enable_pads; board_data->dsi_disable_pads = omap_dsi_disable_pads; board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count; @@ -473,7 +513,6 @@ static void dispc_disable_outputs(void) } } -#define MAX_MODULE_SOFTRESET_WAIT 10000 int omap_dss_reset(struct omap_hwmod *oh) { struct omap_hwmod_opt_clk *oc; diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index ff75abe60af2..b1926cd70468 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -28,9 +28,11 @@ #include <linux/init.h> #include <linux/device.h> -#include <plat/omap_hwmod.h> -#include <plat/omap_device.h> -#include <plat/dma.h> +#include <plat-omap/dma-omap.h> + +#include "soc.h" +#include "omap_hwmod.h" +#include "omap_device.h" #define OMAP2_DMA_STRIDE 0x60 diff --git a/arch/arm/mach-omap2/dma.h b/arch/arm/mach-omap2/dma.h new file mode 100644 index 000000000000..eba80dbc5218 --- /dev/null +++ b/arch/arm/mach-omap2/dma.h @@ -0,0 +1,131 @@ +/* + * OMAP2PLUS DMA channel definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __OMAP2PLUS_DMA_CHANNEL_H +#define __OMAP2PLUS_DMA_CHANNEL_H + + +/* DMA channels for 24xx */ +#define OMAP24XX_DMA_NO_DEVICE 0 +#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */ +#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */ +#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */ +#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ +#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */ +#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */ +#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */ +#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */ +#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */ +#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */ +#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */ +#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */ +#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */ +#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */ +#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */ +#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */ +#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */ +#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */ +#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */ +#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */ +#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ +#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */ +#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */ +#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */ +#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */ +#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */ +#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */ +#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */ +#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */ +#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */ +#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */ +#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */ +#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */ +#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */ +#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */ +#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */ +#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */ +#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */ +#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */ +#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */ +#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */ +#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */ +#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */ +#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */ +#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */ +#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */ +#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */ +#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */ +#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */ +#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */ +#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */ +#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */ +#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */ +#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */ +#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */ +#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */ +#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */ +#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */ +#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */ +#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */ +#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */ +#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */ +#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */ +#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */ +#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */ +#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */ +#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */ +#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */ +#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */ +#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */ +#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */ +#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */ +#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */ +#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */ +#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */ +#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */ +#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */ +#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */ +#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */ +#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */ +#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */ +#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */ +#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */ +#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */ +#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */ +#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */ +#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */ +#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */ +#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */ +#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */ +#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */ +#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */ +#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */ +#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */ +#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */ +#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */ +#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ +#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ + +#define OMAP36XX_DMA_UART4_TX 81 /* S_DMA_80 */ +#define OMAP36XX_DMA_UART4_RX 82 /* S_DMA_81 */ + +/* Only for AM35xx */ +#define AM35XX_DMA_UART4_TX 54 +#define AM35XX_DMA_UART4_RX 55 + +#endif /* __OMAP2PLUS_DMA_CHANNEL_H */ diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 814e1808e158..fafb28c0dcbc 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -28,9 +28,8 @@ #include <linux/bitops.h> #include <linux/clkdev.h> -#include <plat/clock.h> - #include "soc.h" +#include "clockdomain.h" #include "clock.h" #include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" @@ -44,7 +43,7 @@ /* Private functions */ /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ -static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) +static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits) { const struct dpll_data *dd; u32 v; @@ -58,7 +57,7 @@ static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) } /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ -static int _omap3_wait_dpll_status(struct clk *clk, u8 state) +static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state) { const struct dpll_data *dd; int i = 0; @@ -66,7 +65,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) const char *clk_name; dd = clk->dpll_data; - clk_name = __clk_get_name(clk); + clk_name = __clk_get_name(clk->hw.clk); state <<= __ffs(dd->idlest_mask); @@ -90,7 +89,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) } /* From 3430 TRM ES2 4.7.6.2 */ -static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) +static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n) { unsigned long fint; u16 f = 0; @@ -135,14 +134,14 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) * locked successfully, return 0; if the DPLL did not lock in the time * allotted, or DPLL3 was passed in, return -EINVAL. */ -static int _omap3_noncore_dpll_lock(struct clk *clk) +static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk) { const struct dpll_data *dd; u8 ai; u8 state = 1; int r = 0; - pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk)); + pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk)); dd = clk->dpll_data; state <<= __ffs(dd->idlest_mask); @@ -180,7 +179,7 @@ done: * DPLL3 was passed in, or the DPLL does not support low-power bypass, * return -EINVAL. */ -static int _omap3_noncore_dpll_bypass(struct clk *clk) +static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk) { int r; u8 ai; @@ -189,7 +188,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk) return -EINVAL; pr_debug("clock: configuring DPLL %s for low-power bypass\n", - __clk_get_name(clk)); + __clk_get_name(clk->hw.clk)); ai = omap3_dpll_autoidle_read(clk); @@ -212,14 +211,14 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk) * code. If DPLL3 was passed in, or the DPLL does not support * low-power stop, return -EINVAL; otherwise, return 0. */ -static int _omap3_noncore_dpll_stop(struct clk *clk) +static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk) { u8 ai; if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) return -EINVAL; - pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk)); + pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk)); ai = omap3_dpll_autoidle_read(clk); @@ -243,11 +242,11 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) * XXX This code is not needed for 3430/AM35xx; can it be optimized * out in non-multi-OMAP builds for those chips? */ -static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) +static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n) { unsigned long fint, clkinp; /* watch out for overflow */ - clkinp = __clk_get_rate(__clk_get_parent(clk)); + clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); fint = (clkinp / n) * m; if (fint < 1000000000) @@ -268,12 +267,12 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) * XXX This code is not needed for 3430/AM35xx; can it be optimized * out in non-multi-OMAP builds for those chips? */ -static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) +static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) { unsigned long clkinp, sd; /* watch out for overflow */ int mod1, mod2; - clkinp = __clk_get_rate(__clk_get_parent(clk)); + clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); /* * target sigma-delta to near 250MHz @@ -300,7 +299,8 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) * Program the DPLL with the supplied M, N values, and wait for the DPLL to * lock.. Returns -EINVAL upon error, or 0 upon success. */ -static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) +static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n, + u16 freqsel) { struct dpll_data *dd = clk->dpll_data; u8 dco, sd_div; @@ -357,8 +357,10 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) * * Recalculate and propagate the DPLL rate. */ -unsigned long omap3_dpll_recalc(struct clk *clk) +unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate) { + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + return omap2_get_dpll_rate(clk); } @@ -378,8 +380,9 @@ unsigned long omap3_dpll_recalc(struct clk *clk) * support low-power stop, or if the DPLL took too long to enter * bypass or lock, return -EINVAL; otherwise, return 0. */ -int omap3_noncore_dpll_enable(struct clk *clk) +int omap3_noncore_dpll_enable(struct clk_hw *hw) { + struct clk_hw_omap *clk = to_clk_hw_omap(hw); int r; struct dpll_data *dd; struct clk *parent; @@ -388,22 +391,26 @@ int omap3_noncore_dpll_enable(struct clk *clk) if (!dd) return -EINVAL; - parent = __clk_get_parent(clk); + if (clk->clkdm) { + r = clkdm_clk_enable(clk->clkdm, hw->clk); + if (r) { + WARN(1, + "%s: could not enable %s's clockdomain %s: %d\n", + __func__, __clk_get_name(hw->clk), + clk->clkdm->name, r); + return r; + } + } - if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) { + parent = __clk_get_parent(hw->clk); + + if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) { WARN_ON(parent != dd->clk_bypass); r = _omap3_noncore_dpll_bypass(clk); } else { WARN_ON(parent != dd->clk_ref); r = _omap3_noncore_dpll_lock(clk); } - /* - *FIXME: this is dubious - if clk->rate has changed, what about - * propagating? - */ - if (!r) - clk->rate = (clk->recalc) ? clk->recalc(clk) : - omap2_get_dpll_rate(clk); return r; } @@ -415,9 +422,13 @@ int omap3_noncore_dpll_enable(struct clk *clk) * Instructs a non-CORE DPLL to enter low-power stop. This function is * intended for use in struct clkops. No return value. */ -void omap3_noncore_dpll_disable(struct clk *clk) +void omap3_noncore_dpll_disable(struct clk_hw *hw) { + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + _omap3_noncore_dpll_stop(clk); + if (clk->clkdm) + clkdm_clk_disable(clk->clkdm, hw->clk); } @@ -434,80 +445,72 @@ void omap3_noncore_dpll_disable(struct clk *clk) * target rate if it hasn't been done already, then program and lock * the DPLL. Returns -EINVAL upon error, or 0 upon success. */ -int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) +int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) { + struct clk_hw_omap *clk = to_clk_hw_omap(hw); struct clk *new_parent = NULL; - unsigned long hw_rate, bypass_rate; u16 freqsel = 0; struct dpll_data *dd; int ret; - if (!clk || !rate) + if (!hw || !rate) return -EINVAL; dd = clk->dpll_data; if (!dd) return -EINVAL; - hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk); - if (rate == hw_rate) - return 0; + __clk_prepare(dd->clk_bypass); + clk_enable(dd->clk_bypass); + __clk_prepare(dd->clk_ref); + clk_enable(dd->clk_ref); - /* - * Ensure both the bypass and ref clocks are enabled prior to - * doing anything; we need the bypass clock running to reprogram - * the DPLL. - */ - omap2_clk_enable(dd->clk_bypass); - omap2_clk_enable(dd->clk_ref); - - bypass_rate = __clk_get_rate(dd->clk_bypass); - if (bypass_rate == rate && - (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { - pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); + if (__clk_get_rate(dd->clk_bypass) == rate && + (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { + pr_debug("%s: %s: set rate: entering bypass.\n", + __func__, __clk_get_name(hw->clk)); ret = _omap3_noncore_dpll_bypass(clk); if (!ret) new_parent = dd->clk_bypass; } else { if (dd->last_rounded_rate != rate) - rate = clk->round_rate(clk, rate); + rate = __clk_round_rate(hw->clk, rate); if (dd->last_rounded_rate == 0) return -EINVAL; /* No freqsel on OMAP4 and OMAP3630 */ - if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) { + if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); if (!freqsel) WARN_ON(1); } - pr_debug("clock: %s: set rate: locking rate to %lu.\n", - __clk_get_name(clk), rate); + pr_debug("%s: %s: set rate: locking rate to %lu.\n", + __func__, __clk_get_name(hw->clk), rate); ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, - dd->last_rounded_n, freqsel); + dd->last_rounded_n, freqsel); if (!ret) new_parent = dd->clk_ref; } - if (!ret) { - /* - * Switch the parent clock in the hierarchy, and make sure - * that the new parent's usecount is correct. Note: we - * enable the new parent before disabling the old to avoid - * any unnecessary hardware disable->enable transitions. - */ - if (clk->usecount) { - omap2_clk_enable(new_parent); - omap2_clk_disable(clk->parent); - } - clk_reparent(clk, new_parent); - clk->rate = rate; - } - omap2_clk_disable(dd->clk_ref); - omap2_clk_disable(dd->clk_bypass); + /* + * FIXME - this is all wrong. common code handles reparenting and + * migrating prepare/enable counts. dplls should be a multiplexer + * clock and this should be a set_parent operation so that all of that + * stuff is inherited for free + */ + + if (!ret) + __clk_reparent(hw->clk, new_parent); + + clk_disable(dd->clk_ref); + __clk_unprepare(dd->clk_ref); + clk_disable(dd->clk_bypass); + __clk_unprepare(dd->clk_bypass); return 0; } @@ -522,7 +525,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) * -EINVAL if passed a null pointer or if the struct clk does not * appear to refer to a DPLL. */ -u32 omap3_dpll_autoidle_read(struct clk *clk) +u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) { const struct dpll_data *dd; u32 v; @@ -551,7 +554,7 @@ u32 omap3_dpll_autoidle_read(struct clk *clk) * OMAP3430. The DPLL will enter low-power stop when its downstream * clocks are gated. No return value. */ -void omap3_dpll_allow_idle(struct clk *clk) +void omap3_dpll_allow_idle(struct clk_hw_omap *clk) { const struct dpll_data *dd; u32 v; @@ -561,11 +564,8 @@ void omap3_dpll_allow_idle(struct clk *clk) dd = clk->dpll_data; - if (!dd->autoidle_reg) { - pr_debug("clock: DPLL %s: autoidle not supported\n", - __clk_get_name(clk)); + if (!dd->autoidle_reg) return; - } /* * REVISIT: CORE DPLL can optionally enter low-power bypass @@ -585,7 +585,7 @@ void omap3_dpll_allow_idle(struct clk *clk) * * Disable DPLL automatic idle control. No return value. */ -void omap3_dpll_deny_idle(struct clk *clk) +void omap3_dpll_deny_idle(struct clk_hw_omap *clk) { const struct dpll_data *dd; u32 v; @@ -595,11 +595,8 @@ void omap3_dpll_deny_idle(struct clk *clk) dd = clk->dpll_data; - if (!dd->autoidle_reg) { - pr_debug("clock: DPLL %s: autoidle not supported\n", - __clk_get_name(clk)); + if (!dd->autoidle_reg) return; - } v = __raw_readl(dd->autoidle_reg); v &= ~dd->autoidle_mask; @@ -617,18 +614,25 @@ void omap3_dpll_deny_idle(struct clk *clk) * Using parent clock DPLL data, look up DPLL state. If locked, set our * rate to the dpll_clk * 2; otherwise, just use dpll_clk. */ -unsigned long omap3_clkoutx2_recalc(struct clk *clk) +unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, + unsigned long parent_rate) { const struct dpll_data *dd; unsigned long rate; u32 v; - struct clk *pclk; - unsigned long parent_rate; + struct clk_hw_omap *pclk = NULL; + struct clk *parent; /* Walk up the parents of clk, looking for a DPLL */ - pclk = __clk_get_parent(clk); - while (pclk && !pclk->dpll_data) - pclk = __clk_get_parent(pclk); + do { + do { + parent = __clk_get_parent(hw->clk); + hw = __clk_get_hw(parent); + } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC)); + if (!hw) + break; + pclk = to_clk_hw_omap(hw); + } while (pclk && !pclk->dpll_data); /* clk does not have a DPLL as a parent? error in the clock data */ if (!pclk) { @@ -640,7 +644,6 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) WARN_ON(!dd->enable_mask); - parent_rate = __clk_get_rate(__clk_get_parent(clk)); v = __raw_readl(dd->control_reg) & dd->enable_mask; v >>= __ffs(dd->enable_mask); if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) @@ -651,15 +654,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) } /* OMAP3/4 non-CORE DPLL clkops */ - -const struct clkops clkops_omap3_noncore_dpll_ops = { - .enable = omap3_noncore_dpll_enable, - .disable = omap3_noncore_dpll_disable, - .allow_idle = omap3_dpll_allow_idle, - .deny_idle = omap3_dpll_deny_idle, -}; - -const struct clkops clkops_omap3_core_dpll_ops = { +const struct clk_hw_omap_ops clkhwops_omap3_dpll = { .allow_idle = omap3_dpll_allow_idle, .deny_idle = omap3_dpll_deny_idle, }; diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 09d0ccccb861..d3326c474fdc 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -15,15 +15,13 @@ #include <linux/io.h> #include <linux/bitops.h> -#include <plat/clock.h> - #include "soc.h" #include "clock.h" #include "clock44xx.h" #include "cm-regbits-44xx.h" /* Supported only on OMAP4 */ -int omap4_dpllmx_gatectrl_read(struct clk *clk) +int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) { u32 v; u32 mask; @@ -42,7 +40,7 @@ int omap4_dpllmx_gatectrl_read(struct clk *clk) return v; } -void omap4_dpllmx_allow_gatectrl(struct clk *clk) +void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) { u32 v; u32 mask; @@ -60,7 +58,7 @@ void omap4_dpllmx_allow_gatectrl(struct clk *clk) __raw_writel(v, clk->clksel_reg); } -void omap4_dpllmx_deny_gatectrl(struct clk *clk) +void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) { u32 v; u32 mask; @@ -78,9 +76,9 @@ void omap4_dpllmx_deny_gatectrl(struct clk *clk) __raw_writel(v, clk->clksel_reg); } -const struct clkops clkops_omap4_dpllmx_ops = { +const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = { .allow_idle = omap4_dpllmx_allow_gatectrl, - .deny_idle = omap4_dpllmx_deny_gatectrl, + .deny_idle = omap4_dpllmx_deny_gatectrl, }; /** @@ -92,8 +90,10 @@ const struct clkops clkops_omap4_dpllmx_ops = { * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers) * upon success, or 0 upon error. */ -unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk) +unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, + unsigned long parent_rate) { + struct clk_hw_omap *clk = to_clk_hw_omap(hw); u32 v; unsigned long rate; struct dpll_data *dd; @@ -125,8 +125,11 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk) * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or * ~0 if an error occurred in omap2_dpll_round_rate(). */ -long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate) +long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, + unsigned long target_rate, + unsigned long *parent_rate) { + struct clk_hw_omap *clk = to_clk_hw_omap(hw); u32 v; struct dpll_data *dd; long r; @@ -142,7 +145,7 @@ long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate) if (v) target_rate = target_rate / OMAP4430_REGM4XEN_MULT; - r = omap2_dpll_round_rate(clk, target_rate); + r = omap2_dpll_round_rate(hw, target_rate, NULL); if (r == ~0) return r; diff --git a/arch/arm/mach-omap2/drm.c b/arch/arm/mach-omap2/drm.c index 72e0f01b715c..6282cc826613 100644 --- a/arch/arm/mach-omap2/drm.c +++ b/arch/arm/mach-omap2/drm.c @@ -24,8 +24,8 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> -#include <plat/omap_device.h> -#include <plat/omap_hwmod.h> +#include "omap_device.h" +#include "omap_hwmod.h" #if defined(CONFIG_DRM_OMAP) || (CONFIG_DRM_OMAP_MODULE) diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c index 98388109f22a..b155500e84a8 100644 --- a/arch/arm/mach-omap2/dsp.c +++ b/arch/arm/mach-omap2/dsp.c @@ -27,7 +27,7 @@ #include "cm2xxx_3xxx.h" #include "prm2xxx_3xxx.h" #ifdef CONFIG_BRIDGE_DVFS -#include <plat/omap-pm.h> +#include "omap-pm.h" #endif #include <linux/platform_data/dsp-omap.h> diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c index d1058f16fb40..399acabc3d0b 100644 --- a/arch/arm/mach-omap2/gpio.c +++ b/arch/arm/mach-omap2/gpio.c @@ -23,9 +23,9 @@ #include <linux/of.h> #include <linux/platform_data/gpio-omap.h> -#include <plat/omap_hwmod.h> -#include <plat/omap_device.h> -#include <plat/omap-pm.h> +#include "omap_hwmod.h" +#include "omap_device.h" +#include "omap-pm.h" #include "powerdomain.h" diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 4acf497faeb3..8607735b3ab3 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -17,9 +17,12 @@ #include <asm/mach/flash.h> -#include <plat/gpmc.h> - +#include "gpmc.h" #include "soc.h" +#include "gpmc-nand.h" + +/* minimum size for IO mapping */ +#define NAND_IO_SIZE 4 static struct resource gpmc_nand_resource[] = { { @@ -40,41 +43,36 @@ static struct platform_device gpmc_nand_device = { .resource = gpmc_nand_resource, }; -static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data) +static int omap2_nand_gpmc_retime( + struct omap_nand_platform_data *gpmc_nand_data, + struct gpmc_timings *gpmc_t) { struct gpmc_timings t; int err; - if (!gpmc_nand_data->gpmc_t) - return 0; - memset(&t, 0, sizeof(t)); - t.sync_clk = gpmc_nand_data->gpmc_t->sync_clk; - t.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on); - t.adv_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->adv_on); + t.sync_clk = gpmc_t->sync_clk; + t.cs_on = gpmc_round_ns_to_ticks(gpmc_t->cs_on); + t.adv_on = gpmc_round_ns_to_ticks(gpmc_t->adv_on); /* Read */ - t.adv_rd_off = gpmc_round_ns_to_ticks( - gpmc_nand_data->gpmc_t->adv_rd_off); + t.adv_rd_off = gpmc_round_ns_to_ticks(gpmc_t->adv_rd_off); t.oe_on = t.adv_on; - t.access = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->access); - t.oe_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->oe_off); - t.cs_rd_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_rd_off); - t.rd_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->rd_cycle); + t.access = gpmc_round_ns_to_ticks(gpmc_t->access); + t.oe_off = gpmc_round_ns_to_ticks(gpmc_t->oe_off); + t.cs_rd_off = gpmc_round_ns_to_ticks(gpmc_t->cs_rd_off); + t.rd_cycle = gpmc_round_ns_to_ticks(gpmc_t->rd_cycle); /* Write */ - t.adv_wr_off = gpmc_round_ns_to_ticks( - gpmc_nand_data->gpmc_t->adv_wr_off); + t.adv_wr_off = gpmc_round_ns_to_ticks(gpmc_t->adv_wr_off); t.we_on = t.oe_on; if (cpu_is_omap34xx()) { - t.wr_data_mux_bus = gpmc_round_ns_to_ticks( - gpmc_nand_data->gpmc_t->wr_data_mux_bus); - t.wr_access = gpmc_round_ns_to_ticks( - gpmc_nand_data->gpmc_t->wr_access); + t.wr_data_mux_bus = gpmc_round_ns_to_ticks(gpmc_t->wr_data_mux_bus); + t.wr_access = gpmc_round_ns_to_ticks(gpmc_t->wr_access); } - t.we_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->we_off); - t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_wr_off); - t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle); + t.we_off = gpmc_round_ns_to_ticks(gpmc_t->we_off); + t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_t->cs_wr_off); + t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_t->wr_cycle); /* Configure GPMC */ if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) @@ -91,7 +89,29 @@ static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data return 0; } -int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data) +static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) +{ + /* support only OMAP3 class */ + if (!cpu_is_omap34xx()) { + pr_err("BCH ecc is not supported on this CPU\n"); + return 0; + } + + /* + * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1. + * Other chips may be added if confirmed to work. + */ + if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) && + (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) { + pr_err("BCH 4-bit mode is not supported on this CPU\n"); + return 0; + } + + return 1; +} + +int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, + struct gpmc_timings *gpmc_t) { int err = 0; struct device *dev = &gpmc_nand_device.dev; @@ -112,11 +132,13 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data) gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE); gpmc_nand_resource[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); - /* Set timings in GPMC */ - err = omap2_nand_gpmc_retime(gpmc_nand_data); - if (err < 0) { - dev_err(dev, "Unable to set gpmc timings: %d\n", err); - return err; + + if (gpmc_t) { + err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t); + if (err < 0) { + dev_err(dev, "Unable to set gpmc timings: %d\n", err); + return err; + } } /* Enable RD PIN Monitoring Reg */ @@ -126,6 +148,9 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data) gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); + if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) + return -EINVAL; + err = platform_device_register(&gpmc_nand_device); if (err < 0) { dev_err(dev, "Unable to register NAND device\n"); diff --git a/arch/arm/mach-omap2/gpmc-nand.h b/arch/arm/mach-omap2/gpmc-nand.h new file mode 100644 index 000000000000..d59e1281e851 --- /dev/null +++ b/arch/arm/mach-omap2/gpmc-nand.h @@ -0,0 +1,27 @@ +/* + * arch/arm/mach-omap2/gpmc-nand.h + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __OMAP2_GPMC_NAND_H +#define __OMAP2_GPMC_NAND_H + +#include "gpmc.h" +#include <linux/platform_data/mtd-nand-omap2.h> + +#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2) +extern int gpmc_nand_init(struct omap_nand_platform_data *d, + struct gpmc_timings *gpmc_t); +#else +static inline int gpmc_nand_init(struct omap_nand_platform_data *d, + struct gpmc_timings *gpmc_t) +{ + return 0; +} +#endif + +#endif diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index 916716e1da3b..d102183ed9a5 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c @@ -16,15 +16,25 @@ #include <linux/mtd/onenand_regs.h> #include <linux/io.h> #include <linux/platform_data/mtd-onenand-omap2.h> +#include <linux/err.h> #include <asm/mach/flash.h> -#include <plat/gpmc.h> - +#include "gpmc.h" #include "soc.h" +#include "gpmc-onenand.h" #define ONENAND_IO_SIZE SZ_128K +#define ONENAND_FLAG_SYNCREAD (1 << 0) +#define ONENAND_FLAG_SYNCWRITE (1 << 1) +#define ONENAND_FLAG_HF (1 << 2) +#define ONENAND_FLAG_VHF (1 << 3) + +static unsigned onenand_flags; +static unsigned latency; +static int fclk_offset; + static struct omap_onenand_platform_data *gpmc_onenand_data; static struct resource gpmc_onenand_resource = { @@ -38,11 +48,9 @@ static struct platform_device gpmc_onenand_device = { .resource = &gpmc_onenand_resource, }; -static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) +static struct gpmc_timings omap2_onenand_calc_async_timings(void) { struct gpmc_timings t; - u32 reg; - int err; const int t_cer = 15; const int t_avdp = 12; @@ -55,11 +63,6 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) const int t_wpl = 40; const int t_wph = 30; - /* Ensure sync read and sync write are disabled */ - reg = readw(onenand_base + ONENAND_REG_SYS_CFG1); - reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE; - writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); - memset(&t, 0, sizeof(t)); t.sync_clk = 0; t.cs_on = 0; @@ -86,25 +89,30 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph); t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez); + return t; +} + +static int gpmc_set_async_mode(int cs, struct gpmc_timings *t) +{ /* Configure GPMC for asynchronous read */ gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, GPMC_CONFIG1_DEVICESIZE_16 | GPMC_CONFIG1_MUXADDDATA); - err = gpmc_cs_set_timings(cs, &t); - if (err) - return err; + return gpmc_cs_set_timings(cs, t); +} + +static void omap2_onenand_set_async_mode(void __iomem *onenand_base) +{ + u32 reg; /* Ensure sync read and sync write are disabled */ reg = readw(onenand_base + ONENAND_REG_SYS_CFG1); reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE; writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); - - return 0; } -static void set_onenand_cfg(void __iomem *onenand_base, int latency, - int sync_read, int sync_write, int hf, int vhf) +static void set_onenand_cfg(void __iomem *onenand_base) { u32 reg; @@ -112,19 +120,19 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency, reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9)); reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) | ONENAND_SYS_CFG1_BL_16; - if (sync_read) + if (onenand_flags & ONENAND_FLAG_SYNCREAD) reg |= ONENAND_SYS_CFG1_SYNC_READ; else reg &= ~ONENAND_SYS_CFG1_SYNC_READ; - if (sync_write) + if (onenand_flags & ONENAND_FLAG_SYNCWRITE) reg |= ONENAND_SYS_CFG1_SYNC_WRITE; else reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE; - if (hf) + if (onenand_flags & ONENAND_FLAG_HF) reg |= ONENAND_SYS_CFG1_HF; else reg &= ~ONENAND_SYS_CFG1_HF; - if (vhf) + if (onenand_flags & ONENAND_FLAG_VHF) reg |= ONENAND_SYS_CFG1_VHF; else reg &= ~ONENAND_SYS_CFG1_VHF; @@ -132,21 +140,10 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency, } static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg, - void __iomem *onenand_base, bool *clk_dep) + void __iomem *onenand_base) { u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID); - int freq = 0; - - if (cfg->get_freq) { - struct onenand_freq_info fi; - - fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID); - fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID); - fi.ver_id = ver; - freq = cfg->get_freq(&fi, clk_dep); - if (freq) - return freq; - } + int freq; switch ((ver >> 4) & 0xf) { case 0: @@ -172,9 +169,9 @@ static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg, return freq; } -static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, - void __iomem *onenand_base, - int *freq_ptr) +static struct gpmc_timings +omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg, + int freq) { struct gpmc_timings t; const int t_cer = 15; @@ -184,29 +181,15 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, const int t_wpl = 40; const int t_wph = 30; int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; - int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency; - int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0; - int err, ticks_cez; - int cs = cfg->cs, freq = *freq_ptr; u32 reg; - bool clk_dep = false; + int div, fclk_offset_ns, gpmc_clk_ns; + int ticks_cez; + int cs = cfg->cs; - if (cfg->flags & ONENAND_SYNC_READ) { - sync_read = 1; - } else if (cfg->flags & ONENAND_SYNC_READWRITE) { - sync_read = 1; - sync_write = 1; - } else - return omap2_onenand_set_async_mode(cs, onenand_base); - - if (!freq) { - /* Very first call freq is not known */ - err = omap2_onenand_set_async_mode(cs, onenand_base); - if (err) - return err; - freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep); - first_time = 1; - } + if (cfg->flags & ONENAND_SYNC_READ) + onenand_flags = ONENAND_FLAG_SYNCREAD; + else if (cfg->flags & ONENAND_SYNC_READWRITE) + onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE; switch (freq) { case 104: @@ -244,44 +227,31 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, t_ach = 9; t_aavdh = 7; t_rdyo = 15; - sync_write = 0; + onenand_flags &= ~ONENAND_FLAG_SYNCWRITE; break; } - div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period); + div = gpmc_calc_divider(min_gpmc_clk_period); gpmc_clk_ns = gpmc_ticks_to_ns(div); if (gpmc_clk_ns < 15) /* >66Mhz */ - hf = 1; + onenand_flags |= ONENAND_FLAG_HF; + else + onenand_flags &= ~ONENAND_FLAG_HF; if (gpmc_clk_ns < 12) /* >83Mhz */ - vhf = 1; - if (vhf) + onenand_flags |= ONENAND_FLAG_VHF; + else + onenand_flags &= ~ONENAND_FLAG_VHF; + if (onenand_flags & ONENAND_FLAG_VHF) latency = 8; - else if (hf) + else if (onenand_flags & ONENAND_FLAG_HF) latency = 6; else if (gpmc_clk_ns >= 25) /* 40 MHz*/ latency = 3; else latency = 4; - if (clk_dep) { - if (gpmc_clk_ns < 12) { /* >83Mhz */ - t_ces = 3; - t_avds = 4; - } else if (gpmc_clk_ns < 15) { /* >66Mhz */ - t_ces = 5; - t_avds = 4; - } else if (gpmc_clk_ns < 25) { /* >40Mhz */ - t_ces = 6; - t_avds = 5; - } else { - t_ces = 7; - t_avds = 7; - } - } - - if (first_time) - set_onenand_cfg(onenand_base, latency, - sync_read, sync_write, hf, vhf); + /* Set synchronous read timings */ + memset(&t, 0, sizeof(t)); if (div == 1) { reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2); @@ -307,8 +277,6 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg); } - /* Set synchronous read timings */ - memset(&t, 0, sizeof(t)); t.sync_clk = min_gpmc_clk_period; t.cs_on = 0; t.adv_on = 0; @@ -330,7 +298,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, ticks_cez); /* Write */ - if (sync_write) { + if (onenand_flags & ONENAND_FLAG_SYNCWRITE) { t.adv_wr_off = t.adv_rd_off; t.we_on = 0; t.we_off = t.cs_rd_off; @@ -355,6 +323,14 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, } } + return t; +} + +static int gpmc_set_sync_mode(int cs, struct gpmc_timings *t) +{ + unsigned sync_read = onenand_flags & ONENAND_FLAG_SYNCREAD; + unsigned sync_write = onenand_flags & ONENAND_FLAG_SYNCWRITE; + /* Configure GPMC for synchronous read */ gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, GPMC_CONFIG1_WRAPBURST_SUPP | @@ -371,11 +347,45 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, GPMC_CONFIG1_DEVICETYPE_NOR | GPMC_CONFIG1_MUXADDDATA); - err = gpmc_cs_set_timings(cs, &t); - if (err) - return err; + return gpmc_cs_set_timings(cs, t); +} + +static int omap2_onenand_setup_async(void __iomem *onenand_base) +{ + struct gpmc_timings t; + int ret; + + omap2_onenand_set_async_mode(onenand_base); - set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf); + t = omap2_onenand_calc_async_timings(); + + ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t); + if (IS_ERR_VALUE(ret)) + return ret; + + omap2_onenand_set_async_mode(onenand_base); + + return 0; +} + +static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr) +{ + int ret, freq = *freq_ptr; + struct gpmc_timings t; + + if (!freq) { + /* Very first call freq is not known */ + freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base); + set_onenand_cfg(onenand_base); + } + + t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq); + + ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t); + if (IS_ERR_VALUE(ret)) + return ret; + + set_onenand_cfg(onenand_base); *freq_ptr = freq; @@ -385,15 +395,22 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr) { struct device *dev = &gpmc_onenand_device.dev; + unsigned l = ONENAND_SYNC_READ | ONENAND_SYNC_READWRITE; + int ret; - /* Set sync timings in GPMC */ - if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base, - freq_ptr) < 0) { - dev_err(dev, "Unable to set synchronous mode\n"); - return -EINVAL; + ret = omap2_onenand_setup_async(onenand_base); + if (ret) { + dev_err(dev, "unable to set to async mode\n"); + return ret; } - return 0; + if (!(gpmc_onenand_data->flags & l)) + return 0; + + ret = omap2_onenand_setup_sync(onenand_base, freq_ptr); + if (ret) + dev_err(dev, "unable to set to sync mode\n"); + return ret; } void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) @@ -411,6 +428,11 @@ void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) gpmc_onenand_data->flags |= ONENAND_SYNC_READ; } + if (cpu_is_omap34xx()) + gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX; + else + gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX; + err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE, (unsigned long *)&gpmc_onenand_resource.start); if (err < 0) { diff --git a/arch/arm/mach-omap2/gpmc-onenand.h b/arch/arm/mach-omap2/gpmc-onenand.h new file mode 100644 index 000000000000..216f23a8b45c --- /dev/null +++ b/arch/arm/mach-omap2/gpmc-onenand.h @@ -0,0 +1,24 @@ +/* + * arch/arm/mach-omap2/gpmc-onenand.h + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __OMAP2_GPMC_ONENAND_H +#define __OMAP2_GPMC_ONENAND_H + +#include <linux/platform_data/mtd-onenand-omap2.h> + +#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2) +extern void gpmc_onenand_init(struct omap_onenand_platform_data *d); +#else +#define board_onenand_data NULL +static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d) +{ +} +#endif + +#endif diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c index 565475310374..6eed907d594c 100644 --- a/arch/arm/mach-omap2/gpmc-smc91x.c +++ b/arch/arm/mach-omap2/gpmc-smc91x.c @@ -17,7 +17,7 @@ #include <linux/io.h> #include <linux/smc91x.h> -#include <plat/gpmc.h> +#include "gpmc.h" #include "gpmc-smc91x.h" #include "soc.h" diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c index 249a0b440cd6..ef990118d32b 100644 --- a/arch/arm/mach-omap2/gpmc-smsc911x.c +++ b/arch/arm/mach-omap2/gpmc-smsc911x.c @@ -20,7 +20,7 @@ #include <linux/io.h> #include <linux/smsc911x.h> -#include <plat/gpmc.h> +#include "gpmc.h" #include "gpmc-smsc911x.h" static struct resource gpmc_smsc911x_resources[] = { diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 92b5718fa722..bf6117c32f4b 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -26,16 +26,14 @@ #include <linux/interrupt.h> #include <linux/platform_device.h> -#include <asm/mach-types.h> -#include <plat/gpmc.h> +#include <linux/platform_data/mtd-nand-omap2.h> -#include <plat/cpu.h> -#include <plat/gpmc.h> -#include <plat/sdrc.h> -#include <plat/omap_device.h> +#include <asm/mach-types.h> #include "soc.h" #include "common.h" +#include "omap_device.h" +#include "gpmc.h" #define DEVICE_NAME "omap-gpmc" @@ -59,6 +57,9 @@ #define GPMC_ECC_SIZE_CONFIG 0x1fc #define GPMC_ECC1_RESULT 0x200 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */ +#define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */ +#define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */ +#define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */ /* GPMC ECC control settings */ #define GPMC_ECC_CTRL_ECCCLEAR 0x100 @@ -75,6 +76,7 @@ #define GPMC_CS0_OFFSET 0x60 #define GPMC_CS_SIZE 0x30 +#define GPMC_BCH_SIZE 0x10 #define GPMC_MEM_START 0x00000000 #define GPMC_MEM_END 0x3FFFFFFF @@ -137,7 +139,6 @@ static struct resource gpmc_mem_root; static struct resource gpmc_cs_mem[GPMC_CS_NUM]; static DEFINE_SPINLOCK(gpmc_mem_lock); static unsigned int gpmc_cs_map; /* flag for cs which are initialized */ -static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */ static struct device *gpmc_dev; static int gpmc_irq; static resource_size_t phys_base, mem_size; @@ -158,22 +159,6 @@ static u32 gpmc_read_reg(int idx) return __raw_readl(gpmc_base + idx); } -static void gpmc_cs_write_byte(int cs, int idx, u8 val) -{ - void __iomem *reg_addr; - - reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; - __raw_writeb(val, reg_addr); -} - -static u8 gpmc_cs_read_byte(int cs, int idx) -{ - void __iomem *reg_addr; - - reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; - return __raw_readb(reg_addr); -} - void gpmc_cs_write_reg(int cs, int idx, u32 val) { void __iomem *reg_addr; @@ -288,7 +273,7 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, return -1 #endif -int gpmc_cs_calc_divider(int cs, unsigned int sync_clk) +int gpmc_calc_divider(unsigned int sync_clk) { int div; u32 l; @@ -308,7 +293,7 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) int div; u32 l; - div = gpmc_cs_calc_divider(cs, t->sync_clk); + div = gpmc_calc_divider(t->sync_clk); if (div < 0) return div; @@ -509,44 +494,6 @@ void gpmc_cs_free(int cs) EXPORT_SYMBOL(gpmc_cs_free); /** - * gpmc_read_status - read access request to get the different gpmc status - * @cmd: command type - * @return status - */ -int gpmc_read_status(int cmd) -{ - int status = -EINVAL; - u32 regval = 0; - - switch (cmd) { - case GPMC_GET_IRQ_STATUS: - status = gpmc_read_reg(GPMC_IRQSTATUS); - break; - - case GPMC_PREFETCH_FIFO_CNT: - regval = gpmc_read_reg(GPMC_PREFETCH_STATUS); - status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval); - break; - - case GPMC_PREFETCH_COUNT: - regval = gpmc_read_reg(GPMC_PREFETCH_STATUS); - status = GPMC_PREFETCH_STATUS_COUNT(regval); - break; - - case GPMC_STATUS_BUFFER: - regval = gpmc_read_reg(GPMC_STATUS); - /* 1 : buffer is available to write */ - status = regval & GPMC_STATUS_BUFF_EMPTY; - break; - - default: - printk(KERN_ERR "gpmc_read_status: Not supported\n"); - } - return status; -} -EXPORT_SYMBOL(gpmc_read_status); - -/** * gpmc_cs_configure - write request to configure gpmc * @cs: chip select number * @cmd: command type @@ -614,121 +561,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval) } EXPORT_SYMBOL(gpmc_cs_configure); -/** - * gpmc_nand_read - nand specific read access request - * @cs: chip select number - * @cmd: command type - */ -int gpmc_nand_read(int cs, int cmd) -{ - int rval = -EINVAL; - - switch (cmd) { - case GPMC_NAND_DATA: - rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA); - break; - - default: - printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n"); - } - return rval; -} -EXPORT_SYMBOL(gpmc_nand_read); - -/** - * gpmc_nand_write - nand specific write request - * @cs: chip select number - * @cmd: command type - * @wval: value to write - */ -int gpmc_nand_write(int cs, int cmd, int wval) -{ - int err = 0; - - switch (cmd) { - case GPMC_NAND_COMMAND: - gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval); - break; - - case GPMC_NAND_ADDRESS: - gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval); - break; - - case GPMC_NAND_DATA: - gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval); - - default: - printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n"); - err = -EINVAL; - } - return err; -} -EXPORT_SYMBOL(gpmc_nand_write); - - - -/** - * gpmc_prefetch_enable - configures and starts prefetch transfer - * @cs: cs (chip select) number - * @fifo_th: fifo threshold to be used for read/ write - * @dma_mode: dma mode enable (1) or disable (0) - * @u32_count: number of bytes to be transferred - * @is_write: prefetch read(0) or write post(1) mode - */ -int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode, - unsigned int u32_count, int is_write) -{ - - if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) { - pr_err("gpmc: fifo threshold is not supported\n"); - return -1; - } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { - /* Set the amount of bytes to be prefetched */ - gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count); - - /* Set dma/mpu mode, the prefetch read / post write and - * enable the engine. Set which cs is has requested for. - */ - gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) | - PREFETCH_FIFOTHRESHOLD(fifo_th) | - ENABLE_PREFETCH | - (dma_mode << DMA_MPU_MODE) | - (0x1 & is_write))); - - /* Start the prefetch engine */ - gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1); - } else { - return -EBUSY; - } - - return 0; -} -EXPORT_SYMBOL(gpmc_prefetch_enable); - -/** - * gpmc_prefetch_reset - disables and stops the prefetch engine - */ -int gpmc_prefetch_reset(int cs) -{ - u32 config1; - - /* check if the same module/cs is trying to reset */ - config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); - if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs) - return -EINVAL; - - /* Stop the PFPW engine */ - gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0); - - /* Reset/disable the PFPW engine */ - gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0); - - return 0; -} -EXPORT_SYMBOL(gpmc_prefetch_reset); - void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) { + int i; + reg->gpmc_status = gpmc_base + GPMC_STATUS; reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; @@ -744,7 +580,17 @@ void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; - reg->gpmc_bch_result0 = gpmc_base + GPMC_ECC_BCH_RESULT_0; + + for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) { + reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 + + GPMC_BCH_SIZE * i; + reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 + + GPMC_BCH_SIZE * i; + reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 + + GPMC_BCH_SIZE * i; + reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 + + GPMC_BCH_SIZE * i; + } } int gpmc_get_client_irq(unsigned irq_config) @@ -1093,267 +939,3 @@ void omap3_gpmc_restore_context(void) } } #endif /* CONFIG_ARCH_OMAP3 */ - -/** - * gpmc_enable_hwecc - enable hardware ecc functionality - * @cs: chip select number - * @mode: read/write mode - * @dev_width: device bus width(1 for x16, 0 for x8) - * @ecc_size: bytes for which ECC will be generated - */ -int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size) -{ - unsigned int val; - - /* check if ecc module is in used */ - if (gpmc_ecc_used != -EINVAL) - return -EINVAL; - - gpmc_ecc_used = cs; - - /* clear ecc and enable bits */ - gpmc_write_reg(GPMC_ECC_CONTROL, - GPMC_ECC_CTRL_ECCCLEAR | - GPMC_ECC_CTRL_ECCREG1); - - /* program ecc and result sizes */ - val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F)); - gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val); - - switch (mode) { - case GPMC_ECC_READ: - case GPMC_ECC_WRITE: - gpmc_write_reg(GPMC_ECC_CONTROL, - GPMC_ECC_CTRL_ECCCLEAR | - GPMC_ECC_CTRL_ECCREG1); - break; - case GPMC_ECC_READSYN: - gpmc_write_reg(GPMC_ECC_CONTROL, - GPMC_ECC_CTRL_ECCCLEAR | - GPMC_ECC_CTRL_ECCDISABLE); - break; - default: - printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode); - break; - } - - /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ - val = (dev_width << 7) | (cs << 1) | (0x1); - gpmc_write_reg(GPMC_ECC_CONFIG, val); - return 0; -} -EXPORT_SYMBOL_GPL(gpmc_enable_hwecc); - -/** - * gpmc_calculate_ecc - generate non-inverted ecc bytes - * @cs: chip select number - * @dat: data pointer over which ecc is computed - * @ecc_code: ecc code buffer - * - * Using non-inverted ECC is considered ugly since writing a blank - * page (padding) will clear the ECC bytes. This is not a problem as long - * no one is trying to write data on the seemingly unused page. Reading - * an erased page will produce an ECC mismatch between generated and read - * ECC bytes that has to be dealt with separately. - */ -int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code) -{ - unsigned int val = 0x0; - - if (gpmc_ecc_used != cs) - return -EINVAL; - - /* read ecc result */ - val = gpmc_read_reg(GPMC_ECC1_RESULT); - *ecc_code++ = val; /* P128e, ..., P1e */ - *ecc_code++ = val >> 16; /* P128o, ..., P1o */ - /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ - *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); - - gpmc_ecc_used = -EINVAL; - return 0; -} -EXPORT_SYMBOL_GPL(gpmc_calculate_ecc); - -#ifdef CONFIG_ARCH_OMAP3 - -/** - * gpmc_init_hwecc_bch - initialize hardware BCH ecc functionality - * @cs: chip select number - * @nsectors: how many 512-byte sectors to process - * @nerrors: how many errors to correct per sector (4 or 8) - * - * This function must be executed before any call to gpmc_enable_hwecc_bch. - */ -int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors) -{ - /* check if ecc module is in use */ - if (gpmc_ecc_used != -EINVAL) - return -EINVAL; - - /* support only OMAP3 class */ - if (!cpu_is_omap34xx()) { - printk(KERN_ERR "BCH ecc is not supported on this CPU\n"); - return -EINVAL; - } - - /* - * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1. - * Other chips may be added if confirmed to work. - */ - if ((nerrors == 4) && - (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) { - printk(KERN_ERR "BCH 4-bit mode is not supported on this CPU\n"); - return -EINVAL; - } - - /* sanity check */ - if (nsectors > 8) { - printk(KERN_ERR "BCH cannot process %d sectors (max is 8)\n", - nsectors); - return -EINVAL; - } - - return 0; -} -EXPORT_SYMBOL_GPL(gpmc_init_hwecc_bch); - -/** - * gpmc_enable_hwecc_bch - enable hardware BCH ecc functionality - * @cs: chip select number - * @mode: read/write mode - * @dev_width: device bus width(1 for x16, 0 for x8) - * @nsectors: how many 512-byte sectors to process - * @nerrors: how many errors to correct per sector (4 or 8) - */ -int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors, - int nerrors) -{ - unsigned int val; - - /* check if ecc module is in use */ - if (gpmc_ecc_used != -EINVAL) - return -EINVAL; - - gpmc_ecc_used = cs; - - /* clear ecc and enable bits */ - gpmc_write_reg(GPMC_ECC_CONTROL, 0x1); - - /* - * When using BCH, sector size is hardcoded to 512 bytes. - * Here we are using wrapping mode 6 both for reading and writing, with: - * size0 = 0 (no additional protected byte in spare area) - * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) - */ - gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, (32 << 22) | (0 << 12)); - - /* BCH configuration */ - val = ((1 << 16) | /* enable BCH */ - (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */ - (0x06 << 8) | /* wrap mode = 6 */ - (dev_width << 7) | /* bus width */ - (((nsectors-1) & 0x7) << 4) | /* number of sectors */ - (cs << 1) | /* ECC CS */ - (0x1)); /* enable ECC */ - - gpmc_write_reg(GPMC_ECC_CONFIG, val); - gpmc_write_reg(GPMC_ECC_CONTROL, 0x101); - return 0; -} -EXPORT_SYMBOL_GPL(gpmc_enable_hwecc_bch); - -/** - * gpmc_calculate_ecc_bch4 - Generate 7 ecc bytes per sector of 512 data bytes - * @cs: chip select number - * @dat: The pointer to data on which ecc is computed - * @ecc: The ecc output buffer - */ -int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc) -{ - int i; - unsigned long nsectors, reg, val1, val2; - - if (gpmc_ecc_used != cs) - return -EINVAL; - - nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1; - - for (i = 0; i < nsectors; i++) { - - reg = GPMC_ECC_BCH_RESULT_0 + 16*i; - - /* Read hw-computed remainder */ - val1 = gpmc_read_reg(reg + 0); - val2 = gpmc_read_reg(reg + 4); - - /* - * Add constant polynomial to remainder, in order to get an ecc - * sequence of 0xFFs for a buffer filled with 0xFFs; and - * left-justify the resulting polynomial. - */ - *ecc++ = 0x28 ^ ((val2 >> 12) & 0xFF); - *ecc++ = 0x13 ^ ((val2 >> 4) & 0xFF); - *ecc++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF)); - *ecc++ = 0x39 ^ ((val1 >> 20) & 0xFF); - *ecc++ = 0x96 ^ ((val1 >> 12) & 0xFF); - *ecc++ = 0xac ^ ((val1 >> 4) & 0xFF); - *ecc++ = 0x7f ^ ((val1 & 0xF) << 4); - } - - gpmc_ecc_used = -EINVAL; - return 0; -} -EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch4); - -/** - * gpmc_calculate_ecc_bch8 - Generate 13 ecc bytes per block of 512 data bytes - * @cs: chip select number - * @dat: The pointer to data on which ecc is computed - * @ecc: The ecc output buffer - */ -int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc) -{ - int i; - unsigned long nsectors, reg, val1, val2, val3, val4; - - if (gpmc_ecc_used != cs) - return -EINVAL; - - nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1; - - for (i = 0; i < nsectors; i++) { - - reg = GPMC_ECC_BCH_RESULT_0 + 16*i; - - /* Read hw-computed remainder */ - val1 = gpmc_read_reg(reg + 0); - val2 = gpmc_read_reg(reg + 4); - val3 = gpmc_read_reg(reg + 8); - val4 = gpmc_read_reg(reg + 12); - - /* - * Add constant polynomial to remainder, in order to get an ecc - * sequence of 0xFFs for a buffer filled with 0xFFs. - */ - *ecc++ = 0xef ^ (val4 & 0xFF); - *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF); - *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF); - *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF); - *ecc++ = 0xed ^ (val3 & 0xFF); - *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF); - *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF); - *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF); - *ecc++ = 0x97 ^ (val2 & 0xFF); - *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF); - *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF); - *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF); - *ecc++ = 0xb5 ^ (val1 & 0xFF); - } - - gpmc_ecc_used = -EINVAL; - return 0; -} -EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch8); - -#endif /* CONFIG_ARCH_OMAP3 */ diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/mach-omap2/gpmc.h index 2e6e2597178c..79f4dfc2adb3 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/mach-omap2/gpmc.h @@ -11,6 +11,8 @@ #ifndef __OMAP2_GPMC_H #define __OMAP2_GPMC_H +#include <linux/platform_data/mtd-nand-omap2.h> + /* Maximum Number of Chip Selects */ #define GPMC_CS_NUM 8 @@ -32,15 +34,6 @@ #define GPMC_SET_IRQ_STATUS 0x00000004 #define GPMC_CONFIG_WP 0x00000005 -#define GPMC_GET_IRQ_STATUS 0x00000006 -#define GPMC_PREFETCH_FIFO_CNT 0x00000007 /* bytes available in FIFO for r/w */ -#define GPMC_PREFETCH_COUNT 0x00000008 /* remaining bytes to be read/write*/ -#define GPMC_STATUS_BUFFER 0x00000009 /* 1: buffer is available to write */ - -#define GPMC_NAND_COMMAND 0x0000000a -#define GPMC_NAND_ADDRESS 0x0000000b -#define GPMC_NAND_DATA 0x0000000c - #define GPMC_ENABLE_IRQ 0x0000000d /* ECC commands */ @@ -76,25 +69,10 @@ #define GPMC_DEVICETYPE_NOR 0 #define GPMC_DEVICETYPE_NAND 2 #define GPMC_CONFIG_WRITEPROTECT 0x00000010 -#define GPMC_STATUS_BUFF_EMPTY 0x00000001 #define WR_RD_PIN_MONITORING 0x00600000 -#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) -#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) #define GPMC_IRQ_FIFOEVENTENABLE 0x01 #define GPMC_IRQ_COUNT_EVENT 0x02 -#define PREFETCH_FIFOTHRESHOLD_MAX 0x40 -#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) - -enum omap_ecc { - /* 1-bit ecc: stored at end of spare area */ - OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */ - OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */ - /* 1-bit ecc: stored at beginning of spare area as romcode */ - OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */ - OMAP_ECC_BCH4_CODE_HW, /* 4-bit BCH ecc code */ - OMAP_ECC_BCH8_CODE_HW, /* 8-bit BCH ecc code */ -}; /* * Note that all values in this struct are in nanoseconds except sync_clk @@ -133,22 +111,6 @@ struct gpmc_timings { u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */ }; -struct gpmc_nand_regs { - void __iomem *gpmc_status; - void __iomem *gpmc_nand_command; - void __iomem *gpmc_nand_address; - void __iomem *gpmc_nand_data; - void __iomem *gpmc_prefetch_config1; - void __iomem *gpmc_prefetch_config2; - void __iomem *gpmc_prefetch_control; - void __iomem *gpmc_prefetch_status; - void __iomem *gpmc_ecc_config; - void __iomem *gpmc_ecc_control; - void __iomem *gpmc_ecc_size_config; - void __iomem *gpmc_ecc1_result; - void __iomem *gpmc_bch_result0; -}; - extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs); extern int gpmc_get_client_irq(unsigned irq_config); @@ -160,31 +122,14 @@ extern unsigned long gpmc_get_fclk_period(void); extern void gpmc_cs_write_reg(int cs, int idx, u32 val); extern u32 gpmc_cs_read_reg(int cs, int idx); -extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk); +extern int gpmc_calc_divider(unsigned int sync_clk); extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t); extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); extern void gpmc_cs_free(int cs); extern int gpmc_cs_set_reserved(int cs, int reserved); extern int gpmc_cs_reserved(int cs); -extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode, - unsigned int u32_count, int is_write); -extern int gpmc_prefetch_reset(int cs); extern void omap3_gpmc_save_context(void); extern void omap3_gpmc_restore_context(void); -extern int gpmc_read_status(int cmd); extern int gpmc_cs_configure(int cs, int cmd, int wval); -extern int gpmc_nand_read(int cs, int cmd); -extern int gpmc_nand_write(int cs, int cmd, int wval); - -int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size); -int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code); - -#ifdef CONFIG_ARCH_OMAP3 -int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors); -int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors, - int nerrors); -int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc); -int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc); -#endif /* CONFIG_ARCH_OMAP3 */ #endif diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c index e003f2bba30c..ab7bf181a105 100644 --- a/arch/arm/mach-omap2/hdq1w.c +++ b/arch/arm/mach-omap2/hdq1w.c @@ -27,15 +27,13 @@ #include <linux/err.h> #include <linux/platform_device.h> -#include <plat/omap_hwmod.h> -#include <plat/omap_device.h> +#include "omap_hwmod.h" +#include "omap_device.h" #include "hdq1w.h" +#include "prm.h" #include "common.h" -/* Maximum microseconds to wait for OMAP module to softreset */ -#define MAX_MODULE_SOFTRESET_WAIT 10000 - /** * omap_hdq1w_reset - reset the OMAP HDQ1W module * @oh: struct omap_hwmod * diff --git a/arch/arm/mach-omap2/hdq1w.h b/arch/arm/mach-omap2/hdq1w.h index 0c1efc846d8d..c7e08d2a7a46 100644 --- a/arch/arm/mach-omap2/hdq1w.h +++ b/arch/arm/mach-omap2/hdq1w.h @@ -21,7 +21,7 @@ #ifndef ARCH_ARM_MACH_OMAP2_HDQ1W_H #define ARCH_ARM_MACH_OMAP2_HDQ1W_H -#include <plat/omap_hwmod.h> +#include "omap_hwmod.h" /* * XXX A future cleanup patch should modify diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 4d3a6324155f..e3406dce59be 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -17,11 +17,12 @@ #include <mach/hardware.h> #include <linux/platform_data/gpio-omap.h> -#include <plat/mmc.h> -#include <plat/omap-pm.h> -#include <plat/omap_device.h> +#include "soc.h" +#include "omap_device.h" +#include "omap-pm.h" #include "mux.h" +#include "mmc.h" #include "hsmmc.h" #include "control.h" diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c index 8763c8520dc2..1df9b5feda16 100644 --- a/arch/arm/mach-omap2/hwspinlock.c +++ b/arch/arm/mach-omap2/hwspinlock.c @@ -21,8 +21,8 @@ #include <linux/err.h> #include <linux/hwspinlock.h> -#include <plat/omap_hwmod.h> -#include <plat/omap_device.h> +#include "omap_hwmod.h" +#include "omap_device.h" static struct hwspinlock_pdata omap_hwspinlock_pdata __initdata = { .base_id = 0, diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c index fc57e67b321f..be092e8e5d85 100644 --- a/arch/arm/mach-omap2/i2c.c +++ b/arch/arm/mach-omap2/i2c.c @@ -19,21 +19,23 @@ * */ -#include <plat/i2c.h> -#include "common.h" -#include <plat/omap_hwmod.h> +#include "soc.h" +#include "omap_hwmod.h" +#include "omap_device.h" +#include "prm.h" +#include "common.h" #include "mux.h" +#include "i2c.h" /* In register I2C_CON, Bit 15 is the I2C enable bit */ #define I2C_EN BIT(15) #define OMAP2_I2C_CON_OFFSET 0x24 #define OMAP4_I2C_CON_OFFSET 0xA4 -/* Maximum microseconds to wait for OMAP module to softreset */ -#define MAX_MODULE_SOFTRESET_WAIT 10000 +#define MAX_OMAP_I2C_HWMOD_NAME_LEN 16 -void __init omap2_i2c_mux_pins(int bus_id) +static void __init omap2_i2c_mux_pins(int bus_id) { char mux_name[sizeof("i2c2_scl.i2c2_scl")]; @@ -104,3 +106,46 @@ int omap_i2c_reset(struct omap_hwmod *oh) return 0; } + +static const char name[] = "omap_i2c"; + +int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata, + int bus_id) +{ + int l; + struct omap_hwmod *oh; + struct platform_device *pdev; + char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN]; + struct omap_i2c_bus_platform_data *pdata; + struct omap_i2c_dev_attr *dev_attr; + + omap2_i2c_mux_pins(bus_id); + + l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id); + WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN, + "String buffer overflow in I2C%d device setup\n", bus_id); + oh = omap_hwmod_lookup(oh_name); + if (!oh) { + pr_err("Could not look up %s\n", oh_name); + return -EEXIST; + } + + pdata = i2c_pdata; + /* + * pass the hwmod class's CPU-specific knowledge of I2C IP revision in + * use, and functionality implementation flags, up to the OMAP I2C + * driver via platform data + */ + pdata->rev = oh->class->rev; + + dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr; + pdata->flags = dev_attr->flags; + + pdev = omap_device_build(name, bus_id, oh, pdata, + sizeof(struct omap_i2c_bus_platform_data), + NULL, 0, 0); + WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name); + + return PTR_RET(pdev); +} + diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/mach-omap2/i2c.h index 7c22b9e10dc3..81dbb992a6bc 100644 --- a/arch/arm/plat-omap/include/plat/i2c.h +++ b/arch/arm/mach-omap2/i2c.h @@ -18,24 +18,11 @@ * 02110-1301 USA * */ -#ifndef __ASM__ARCH_OMAP_I2C_H -#define __ASM__ARCH_OMAP_I2C_H -#include <linux/i2c.h> -#include <linux/i2c-omap.h> +#include "../plat-omap/i2c.h" -#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) -extern int omap_register_i2c_bus(int bus_id, u32 clkrate, - struct i2c_board_info const *info, - unsigned len); -#else -static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, - struct i2c_board_info const *info, - unsigned len) -{ - return 0; -} -#endif +#ifndef __MACH_OMAP2_I2C_H +#define __MACH_OMAP2_I2C_H /** * i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod @@ -50,10 +37,6 @@ struct omap_i2c_dev_attr { u32 flags; }; -void __init omap1_i2c_mux_pins(int bus_id); -void __init omap2_i2c_mux_pins(int bus_id); - -struct omap_hwmod; int omap_i2c_reset(struct omap_hwmod *oh); -#endif /* __ASM__ARCH_OMAP_I2C_H */ +#endif /* __MACH_OMAP2_I2C_H */ diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index cf2362ccb234..f1e121502789 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -559,11 +559,12 @@ void __init omap5xxx_check_revision(void) * detect the exact revision later on in omap2_detect_revision() once map_io * is done. */ -void __init omap2_set_globals_tap(struct omap_globals *omap2_globals) +void __init omap2_set_globals_tap(u32 class, void __iomem *tap) { - omap_revision = omap2_globals->class; - tap_base = omap2_globals->tap; + omap_revision = class; + tap_base = tap; + /* XXX What is this intended to do? */ if (cpu_is_omap34xx()) tap_prod_id = 0x0210; else diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index 93d10de7129f..4b5cbdfac028 100644 --- a/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S @@ -13,7 +13,7 @@ #include <linux/serial_reg.h> -#include <plat/serial.h> +#include <../mach-omap2/serial.h> #define UART_OFFSET(addr) ((addr) & 0x00ffffff) diff --git a/arch/arm/mach-omap2/include/mach/uncompress.h b/arch/arm/mach-omap2/include/mach/uncompress.h index 78e0557bfd4e..28d1ec0e869a 100644 --- a/arch/arm/mach-omap2/include/mach/uncompress.h +++ b/arch/arm/mach-omap2/include/mach/uncompress.h @@ -1,5 +1,176 @@ /* - * arch/arm/mach-omap2/include/mach/uncompress.h + * arch/arm/plat-omap/include/mach/uncompress.h + * + * Serial port stubs for kernel decompress status messages + * + * Initially based on: + * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h + * Copyright (C) 2000 RidgeRun, Inc. + * Author: Greg Lonnon <glonnon@ridgerun.com> + * + * Rewritten by: + * Author: <source@mvista.com> + * 2004 (c) MontaVista Software, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. */ -#include <plat/uncompress.h> +#include <linux/types.h> +#include <linux/serial_reg.h> + +#include <asm/memory.h> +#include <asm/mach-types.h> + +#include <../mach-omap2/serial.h> + +#define MDR1_MODE_MASK 0x07 + +volatile u8 *uart_base; +int uart_shift; + +/* + * Store the DEBUG_LL uart number into memory. + * See also debug-macro.S, and serial.c for related code. + */ +static void set_omap_uart_info(unsigned char port) +{ + /* + * Get address of some.bss variable and round it down + * a la CONFIG_AUTO_ZRELADDR. + */ + u32 ram_start = (u32)&uart_shift & 0xf8000000; + u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS); + *uart_info = port; +} + +static void putc(int c) +{ + if (!uart_base) + return; + + /* Check for UART 16x mode */ + if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0) + return; + + while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE)) + barrier(); + uart_base[UART_TX << uart_shift] = c; +} + +static inline void flush(void) +{ +} + +/* + * Macros to configure UART1 and debug UART + */ +#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id) \ + if (machine_is_##mach()) { \ + uart_base = (volatile u8 *)(dbg_uart); \ + uart_shift = (dbg_shft); \ + port = (dbg_id); \ + set_omap_uart_info(port); \ + break; \ + } + +#define DEBUG_LL_OMAP2(p, mach) \ + _DEBUG_LL_ENTRY(mach, OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, \ + OMAP2UART##p) + +#define DEBUG_LL_OMAP3(p, mach) \ + _DEBUG_LL_ENTRY(mach, OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, \ + OMAP3UART##p) + +#define DEBUG_LL_OMAP4(p, mach) \ + _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, \ + OMAP4UART##p) + +#define DEBUG_LL_OMAP5(p, mach) \ + _DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT, \ + OMAP5UART##p) +/* Zoom2/3 shift is different for UART1 and external port */ +#define DEBUG_LL_ZOOM(mach) \ + _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART) + +#define DEBUG_LL_TI81XX(p, mach) \ + _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ + TI81XXUART##p) + +#define DEBUG_LL_AM33XX(p, mach) \ + _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ + AM33XXUART##p) + +static inline void arch_decomp_setup(void) +{ + int port = 0; + + /* + * Initialize the port based on the machine ID from the bootloader. + * Note that we're using macros here instead of switch statement + * as machine_is functions are optimized out for the boards that + * are not selected. + */ + do { + /* omap2 based boards using UART1 */ + DEBUG_LL_OMAP2(1, omap_2430sdp); + DEBUG_LL_OMAP2(1, omap_apollon); + DEBUG_LL_OMAP2(1, omap_h4); + + /* omap2 based boards using UART3 */ + DEBUG_LL_OMAP2(3, nokia_n800); + DEBUG_LL_OMAP2(3, nokia_n810); + DEBUG_LL_OMAP2(3, nokia_n810_wimax); + + /* omap3 based boards using UART1 */ + DEBUG_LL_OMAP2(1, omap3evm); + DEBUG_LL_OMAP3(1, omap_3430sdp); + DEBUG_LL_OMAP3(1, omap_3630sdp); + DEBUG_LL_OMAP3(1, omap3530_lv_som); + DEBUG_LL_OMAP3(1, omap3_torpedo); + + /* omap3 based boards using UART3 */ + DEBUG_LL_OMAP3(3, cm_t35); + DEBUG_LL_OMAP3(3, cm_t3517); + DEBUG_LL_OMAP3(3, cm_t3730); + DEBUG_LL_OMAP3(3, craneboard); + DEBUG_LL_OMAP3(3, devkit8000); + DEBUG_LL_OMAP3(3, igep0020); + DEBUG_LL_OMAP3(3, igep0030); + DEBUG_LL_OMAP3(3, nokia_rm680); + DEBUG_LL_OMAP3(3, nokia_rm696); + DEBUG_LL_OMAP3(3, nokia_rx51); + DEBUG_LL_OMAP3(3, omap3517evm); + DEBUG_LL_OMAP3(3, omap3_beagle); + DEBUG_LL_OMAP3(3, omap3_pandora); + DEBUG_LL_OMAP3(3, omap_ldp); + DEBUG_LL_OMAP3(3, overo); + DEBUG_LL_OMAP3(3, touchbook); + + /* omap4 based boards using UART3 */ + DEBUG_LL_OMAP4(3, omap_4430sdp); + DEBUG_LL_OMAP4(3, omap4_panda); + + /* omap5 based boards using UART3 */ + DEBUG_LL_OMAP5(3, omap5_sevm); + + /* zoom2/3 external uart */ + DEBUG_LL_ZOOM(omap_zoom2); + DEBUG_LL_ZOOM(omap_zoom3); + + /* TI8168 base boards using UART3 */ + DEBUG_LL_TI81XX(3, ti8168evm); + + /* TI8148 base boards using UART1 */ + DEBUG_LL_TI81XX(1, ti8148evm); + + /* AM33XX base boards using UART1 */ + DEBUG_LL_AM33XX(1, am335xevm); + } while (0); +} + +/* + * nothing to do + */ +#define arch_decomp_wdog() diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 4234d28dc171..924bf24693cd 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -25,14 +25,11 @@ #include <asm/tlb.h> #include <asm/mach/map.h> -#include <plat/sram.h> -#include <plat/sdrc.h> -#include <plat/serial.h> -#include <plat/omap-pm.h> -#include <plat/omap_hwmod.h> -#include <plat/multi.h> -#include <plat/dma.h> +#include <plat-omap/dma-omap.h> +#include "../plat-omap/sram.h" + +#include "omap_hwmod.h" #include "soc.h" #include "iomap.h" #include "voltage.h" @@ -43,7 +40,17 @@ #include "clock2xxx.h" #include "clock3xxx.h" #include "clock44xx.h" - +#include "omap-pm.h" +#include "sdrc.h" +#include "control.h" +#include "serial.h" +#include "cm2xxx.h" +#include "cm3xxx.h" +#include "prm.h" +#include "cm.h" +#include "prcm_mpu44xx.h" +#include "prminst44xx.h" +#include "cminst44xx.h" /* * The machine specific code may provide the extra mapping besides the * default mapping provided here. @@ -265,7 +272,7 @@ static struct map_desc omap54xx_io_desc[] __initdata = { #endif #ifdef CONFIG_SOC_OMAP2420 -void __init omap242x_map_common_io(void) +void __init omap242x_map_io(void) { iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); @@ -273,7 +280,7 @@ void __init omap242x_map_common_io(void) #endif #ifdef CONFIG_SOC_OMAP2430 -void __init omap243x_map_common_io(void) +void __init omap243x_map_io(void) { iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); @@ -281,28 +288,28 @@ void __init omap243x_map_common_io(void) #endif #ifdef CONFIG_ARCH_OMAP3 -void __init omap34xx_map_common_io(void) +void __init omap3_map_io(void) { iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); } #endif #ifdef CONFIG_SOC_TI81XX -void __init omapti81xx_map_common_io(void) +void __init ti81xx_map_io(void) { iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); } #endif #ifdef CONFIG_SOC_AM33XX -void __init omapam33xx_map_common_io(void) +void __init am33xx_map_io(void) { iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); } #endif #ifdef CONFIG_ARCH_OMAP4 -void __init omap44xx_map_common_io(void) +void __init omap4_map_io(void) { iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); omap_barriers_init(); @@ -310,7 +317,7 @@ void __init omap44xx_map_common_io(void) #endif #ifdef CONFIG_SOC_OMAP5 -void __init omap5_map_common_io(void) +void __init omap5_map_io(void) { iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); } @@ -377,8 +384,15 @@ static void __init omap_hwmod_init_postsetup(void) #ifdef CONFIG_SOC_OMAP2420 void __init omap2420_init_early(void) { - omap2_set_globals_242x(); + omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); + omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), + OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE), + NULL); + omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE)); + omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL); omap2xxx_check_revision(); + omap2xxx_cm_init(); omap_common_init_early(); omap2xxx_voltagedomains_init(); omap242x_powerdomains_init(); @@ -393,14 +407,22 @@ void __init omap2420_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap2_pm_init(); + omap2_clk_enable_autoidle_all(); } #endif #ifdef CONFIG_SOC_OMAP2430 void __init omap2430_init_early(void) { - omap2_set_globals_243x(); + omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); + omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), + OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), + NULL); + omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE)); + omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL); omap2xxx_check_revision(); + omap2xxx_cm_init(); omap_common_init_early(); omap2xxx_voltagedomains_init(); omap243x_powerdomains_init(); @@ -415,6 +437,7 @@ void __init omap2430_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap2_pm_init(); + omap2_clk_enable_autoidle_all(); } #endif @@ -425,9 +448,16 @@ void __init omap2430_init_late(void) #ifdef CONFIG_ARCH_OMAP3 void __init omap3_init_early(void) { - omap2_set_globals_3xxx(); + omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); + omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), + OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), + NULL); + omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); + omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL); omap3xxx_check_revision(); omap3xxx_check_features(); + omap3xxx_cm_init(); omap_common_init_early(); omap3xxx_voltagedomains_init(); omap3xxx_powerdomains_init(); @@ -459,7 +489,12 @@ void __init am35xx_init_early(void) void __init ti81xx_init_early(void) { - omap2_set_globals_ti81xx(); + omap2_set_globals_tap(OMAP343X_CLASS, + OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), + NULL); + omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); + omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); omap3xxx_check_revision(); ti81xx_check_features(); omap_common_init_early(); @@ -476,6 +511,7 @@ void __init omap3_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap3_pm_init(); + omap2_clk_enable_autoidle_all(); } void __init omap3430_init_late(void) @@ -483,6 +519,7 @@ void __init omap3430_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap3_pm_init(); + omap2_clk_enable_autoidle_all(); } void __init omap35xx_init_late(void) @@ -490,6 +527,7 @@ void __init omap35xx_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap3_pm_init(); + omap2_clk_enable_autoidle_all(); } void __init omap3630_init_late(void) @@ -497,6 +535,7 @@ void __init omap3630_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap3_pm_init(); + omap2_clk_enable_autoidle_all(); } void __init am35xx_init_late(void) @@ -504,6 +543,7 @@ void __init am35xx_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap3_pm_init(); + omap2_clk_enable_autoidle_all(); } void __init ti81xx_init_late(void) @@ -511,13 +551,19 @@ void __init ti81xx_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap3_pm_init(); + omap2_clk_enable_autoidle_all(); } #endif #ifdef CONFIG_SOC_AM33XX void __init am33xx_init_early(void) { - omap2_set_globals_am33xx(); + omap2_set_globals_tap(AM335X_CLASS, + AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); + omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), + NULL); + omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE)); + omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL); omap3xxx_check_revision(); ti81xx_check_features(); omap_common_init_early(); @@ -533,7 +579,16 @@ void __init am33xx_init_early(void) #ifdef CONFIG_ARCH_OMAP4 void __init omap4430_init_early(void) { - omap2_set_globals_443x(); + omap2_set_globals_tap(OMAP443X_CLASS, + OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), + OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE)); + omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE)); + omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), + OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE)); + omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); + omap_prm_base_init(); + omap_cm_base_init(); omap4xxx_check_revision(); omap4xxx_check_features(); omap_common_init_early(); @@ -550,13 +605,23 @@ void __init omap4430_init_late(void) omap_mux_late_init(); omap2_common_pm_late_init(); omap4_pm_init(); + omap2_clk_enable_autoidle_all(); } #endif #ifdef CONFIG_SOC_OMAP5 void __init omap5_init_early(void) { - omap2_set_globals_5xxx(); + omap2_set_globals_tap(OMAP54XX_CLASS, + OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), + OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE)); + omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE)); + omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE), + OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); + omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); + omap_prm_base_init(); + omap_cm_base_init(); omap5xxx_check_revision(); omap_common_init_early(); } diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 37f8f948047b..bf496510eb5e 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -19,16 +19,17 @@ #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/platform_data/asoc-ti-mcbsp.h> - -#include <plat/dma.h> -#include <plat/omap_device.h> #include <linux/pm_runtime.h> +#include <plat-omap/dma-omap.h> + +#include "omap_device.h" + /* * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle. * Sidetone needs non-gated ICLK and sidetone autoidle is broken. */ -#include "cm2xxx_3xxx.h" +#include "cm3xxx.h" #include "cm-regbits-34xx.h" static int omap3_enable_st_clock(unsigned int id, bool enable) diff --git a/arch/arm/mach-omap2/mmc.h b/arch/arm/mach-omap2/mmc.h new file mode 100644 index 000000000000..0cd4b089da9c --- /dev/null +++ b/arch/arm/mach-omap2/mmc.h @@ -0,0 +1,23 @@ +#include <linux/mmc/host.h> +#include <linux/platform_data/mmc-omap.h> + +#define OMAP24XX_NR_MMC 2 +#define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE +#define OMAP2_MMC1_BASE 0x4809c000 + +#define OMAP4_MMC_REG_OFFSET 0x100 + +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) +void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data); +#else +static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) +{ +} +#endif + +struct omap_hwmod; +int omap_msdi_reset(struct omap_hwmod *oh); + +/* called from board-specific card detection service routine */ +extern void omap_mmc_notify_cover_event(struct device *dev, int slot, + int is_closed); diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c index 9e57b4aadb06..aafdd4ca9f4f 100644 --- a/arch/arm/mach-omap2/msdi.c +++ b/arch/arm/mach-omap2/msdi.c @@ -25,13 +25,13 @@ #include <linux/err.h> #include <linux/platform_data/gpio-omap.h> -#include <plat/omap_hwmod.h> -#include <plat/omap_device.h> -#include <plat/mmc.h> - +#include "prm.h" #include "common.h" #include "control.h" +#include "omap_hwmod.h" +#include "omap_device.h" #include "mux.h" +#include "mmc.h" /* * MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register @@ -44,9 +44,6 @@ #define MSDI_CON_CLKD_MASK (0x3f << 0) #define MSDI_CON_CLKD_SHIFT 0 -/* Maximum microseconds to wait for OMAP module to softreset */ -#define MAX_MODULE_SOFTRESET_WAIT 10000 - /* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */ #define MSDI_TARGET_RESET_CLKD 0x3ff diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 701e17cba468..26126343d6ac 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -36,8 +36,9 @@ #include <linux/interrupt.h> -#include <plat/omap_hwmod.h> +#include "omap_hwmod.h" +#include "soc.h" #include "control.h" #include "mux.h" #include "prm.h" diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c index ff4e6a0e9c7c..3f5fd7e3549d 100644 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c @@ -50,6 +50,7 @@ #include <asm/suspend.h> #include <asm/hardware/cache-l2x0.h> +#include "soc.h" #include "common.h" #include "omap44xx.h" #include "omap4-sar-layout.h" diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/mach-omap2/omap-pm.h index 67faa7b8fe92..67faa7b8fe92 100644 --- a/arch/arm/plat-omap/include/plat/omap-pm.h +++ b/arch/arm/mach-omap2/omap-pm.h diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index e089e4d1ae38..b970440cffca 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -18,7 +18,6 @@ #include <asm/cacheflush.h> #include <asm/memblock.h> -#include <plat/omap-secure.h> #include "omap-secure.h" static phys_addr_t omap_secure_memblock_base; diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index c90a43589abe..0e729170c46b 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -52,6 +52,13 @@ extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2, u32 arg3, u32 arg4); extern u32 omap_smc2(u32 id, u32 falg, u32 pargs); extern phys_addr_t omap_secure_ram_mempool_base(void); +extern int omap_secure_ram_reserve_memblock(void); +#ifdef CONFIG_OMAP4_ERRATA_I688 +extern int omap_barrier_reserve_memblock(void); +#else +static inline void omap_barrier_reserve_memblock(void) +{ } +#endif #endif /* __ASSEMBLER__ */ #endif /* OMAP_ARCH_OMAP_SECURE_H */ diff --git a/arch/arm/mach-omap2/omap2-restart.c b/arch/arm/mach-omap2/omap2-restart.c new file mode 100644 index 000000000000..be6bc89ab1e8 --- /dev/null +++ b/arch/arm/mach-omap2/omap2-restart.c @@ -0,0 +1,65 @@ +/* + * omap2-restart.c - code common to all OMAP2xxx machines. + * + * Copyright (C) 2012 Texas Instruments + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include "common.h" +#include "prm2xxx.h" + +/* + * reset_virt_prcm_set_ck, reset_sys_ck: pointers to the virt_prcm_set + * clock and the sys_ck. Used during the reset process + */ +static struct clk *reset_virt_prcm_set_ck, *reset_sys_ck; + +/* Reboot handling */ + +/** + * omap2xxx_restart - Set DPLL to bypass mode for reboot to work + * + * Set the DPLL to bypass so that reboot completes successfully. No + * return value. + */ +void omap2xxx_restart(char mode, const char *cmd) +{ + u32 rate; + + rate = clk_get_rate(reset_sys_ck); + clk_set_rate(reset_virt_prcm_set_ck, rate); + + /* XXX Should save the cmd argument for use after the reboot */ + + omap2xxx_prm_dpll_reset(); /* never returns */ + while (1); +} + +/** + * omap2xxx_common_look_up_clks_for_reset - look up clocks needed for restart + * + * Some clocks need to be looked up in advance for the SoC restart + * operation to work - see omap2xxx_restart(). Returns -EINVAL upon + * error or 0 upon success. + */ +static int __init omap2xxx_common_look_up_clks_for_reset(void) +{ + reset_virt_prcm_set_ck = clk_get(NULL, "virt_prcm_set"); + if (IS_ERR(reset_virt_prcm_set_ck)) + return -EINVAL; + + reset_sys_ck = clk_get(NULL, "sys_ck"); + if (IS_ERR(reset_sys_ck)) + return -EINVAL; + + return 0; +} +core_initcall(omap2xxx_common_look_up_clks_for_reset); diff --git a/arch/arm/mach-omap2/omap3-restart.c b/arch/arm/mach-omap2/omap3-restart.c new file mode 100644 index 000000000000..923c582189e5 --- /dev/null +++ b/arch/arm/mach-omap2/omap3-restart.c @@ -0,0 +1,36 @@ +/* + * omap3-restart.c - Code common to all OMAP3xxx machines. + * + * Copyright (C) 2009, 2012 Texas Instruments + * Copyright (C) 2010 Nokia Corporation + * Tony Lindgren <tony@atomide.com> + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/init.h> + +#include "iomap.h" +#include "common.h" +#include "control.h" +#include "prm3xxx.h" + +/* Global address base setup code */ + +/** + * omap3xxx_restart - trigger a software restart of the SoC + * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c + * @cmd: passed from the userspace program rebooting the system (if provided) + * + * Resets the SoC. For @cmd, see the 'reboot' syscall in + * kernel/sys.c. No return value. + */ +void omap3xxx_restart(char mode, const char *cmd) +{ + omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0)); + omap3xxx_prm_dpll3_reset(); /* never returns */ + while (1); +} diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index e1f289748c5d..64fce07a3ccd 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -25,16 +25,18 @@ #include <asm/mach/map.h> #include <asm/memblock.h> -#include <plat/sram.h> -#include <plat/omap-secure.h> -#include <plat/mmc.h> +#include "../plat-omap/sram.h" #include "omap-wakeupgen.h" - #include "soc.h" +#include "iomap.h" #include "common.h" +#include "mmc.h" #include "hsmmc.h" +#include "prminst44xx.h" +#include "prcm_mpu44xx.h" #include "omap4-sar-layout.h" +#include "omap-secure.h" #ifdef CONFIG_CACHE_L2X0 static void __iomem *l2cache_base; @@ -281,3 +283,19 @@ int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) return 0; } #endif + +/** + * omap44xx_restart - trigger a software restart of the SoC + * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c + * @cmd: passed from the userspace program rebooting the system (if provided) + * + * Resets the SoC. For @cmd, see the 'reboot' syscall in + * kernel/sys.c. No return value. + */ +void omap44xx_restart(char mode, const char *cmd) +{ + /* XXX Should save 'cmd' into scratchpad for use after reboot */ + omap4_prminst_global_warm_sw_reset(); /* never returns */ + while (1); +} + diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/mach-omap2/omap_device.c index 7a7d1f2a65e9..0ef934fec364 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -89,9 +89,8 @@ #include <linux/of.h> #include <linux/notifier.h> -#include <plat/omap_device.h> -#include <plat/omap_hwmod.h> -#include <plat/clock.h> +#include "omap_device.h" +#include "omap_hwmod.h" /* These parameters are passed to _omap_device_{de,}activate() */ #define USE_WAKEUP_LAT 0 diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/mach-omap2/omap_device.h index 106f50665804..0933c599bf89 100644 --- a/arch/arm/plat-omap/include/plat/omap_device.h +++ b/arch/arm/mach-omap2/omap_device.h @@ -34,7 +34,7 @@ #include <linux/kernel.h> #include <linux/platform_device.h> -#include <plat/omap_hwmod.h> +#include "omap_hwmod.h" extern struct dev_pm_domain omap_device_pm_domain; diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 87cc6d058de2..3f3bf323e201 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -130,7 +130,7 @@ #include <linux/kernel.h> #include <linux/errno.h> #include <linux/io.h> -#include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/list.h> @@ -139,27 +139,25 @@ #include <linux/slab.h> #include <linux/bootmem.h> -#include <plat/clock.h> -#include <plat/omap_hwmod.h> -#include <plat/prcm.h> +#include "clock.h" +#include "omap_hwmod.h" #include "soc.h" #include "common.h" #include "clockdomain.h" #include "powerdomain.h" -#include "cm2xxx_3xxx.h" +#include "cm2xxx.h" +#include "cm3xxx.h" #include "cminst44xx.h" #include "cm33xx.h" -#include "prm2xxx_3xxx.h" +#include "prm.h" +#include "prm3xxx.h" #include "prm44xx.h" #include "prm33xx.h" #include "prminst44xx.h" #include "mux.h" #include "pm.h" -/* Maximum microseconds to wait for OMAP module to softreset */ -#define MAX_MODULE_SOFTRESET_WAIT 10000 - /* Name of the OMAP hwmod for the MPU */ #define MPU_INITIATOR_NAME "mpu" @@ -648,6 +646,19 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) return 0; } +static struct clockdomain *_get_clkdm(struct omap_hwmod *oh) +{ + struct clk_hw_omap *clk; + + if (oh->clkdm) { + return oh->clkdm; + } else if (oh->_clk) { + clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); + return clk->clkdm; + } + return NULL; +} + /** * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active * @oh: struct omap_hwmod * @@ -663,13 +674,18 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) */ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) { - if (!oh->_clk) + struct clockdomain *clkdm, *init_clkdm; + + clkdm = _get_clkdm(oh); + init_clkdm = _get_clkdm(init_oh); + + if (!clkdm || !init_clkdm) return -EINVAL; - if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) + if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) return 0; - return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); + return clkdm_add_sleepdep(clkdm, init_clkdm); } /** @@ -687,13 +703,18 @@ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) */ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) { - if (!oh->_clk) + struct clockdomain *clkdm, *init_clkdm; + + clkdm = _get_clkdm(oh); + init_clkdm = _get_clkdm(init_oh); + + if (!clkdm || !init_clkdm) return -EINVAL; - if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) + if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) return 0; - return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); + return clkdm_del_sleepdep(clkdm, init_clkdm); } /** @@ -727,7 +748,7 @@ static int _init_main_clk(struct omap_hwmod *oh) */ clk_prepare(oh->_clk); - if (!oh->_clk->clkdm) + if (!_get_clkdm(oh)) pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", oh->name, oh->main_clk); @@ -1310,6 +1331,7 @@ static void _enable_sysc(struct omap_hwmod *oh) u8 idlemode, sf; u32 v; bool clkdm_act; + struct clockdomain *clkdm; if (!oh->class->sysc) return; @@ -1329,11 +1351,9 @@ static void _enable_sysc(struct omap_hwmod *oh) v = oh->_sysc_cache; sf = oh->class->sysc->sysc_flags; + clkdm = _get_clkdm(oh); if (sf & SYSC_HAS_SIDLEMODE) { - clkdm_act = ((oh->clkdm && - oh->clkdm->flags & CLKDM_ACTIVE_WITH_MPU) || - (oh->_clk && oh->_clk->clkdm && - oh->_clk->clkdm->flags & CLKDM_ACTIVE_WITH_MPU)); + clkdm_act = (clkdm && clkdm->flags & CLKDM_ACTIVE_WITH_MPU); if (clkdm_act && !(oh->class->sysc->idlemodes & (SIDLE_SMART | SIDLE_SMART_WKUP))) idlemode = HWMOD_IDLEMODE_FORCE; @@ -1535,11 +1555,12 @@ static int _init_clocks(struct omap_hwmod *oh, void *data) pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); + if (soc_ops.init_clkdm) + ret |= soc_ops.init_clkdm(oh); + ret |= _init_main_clk(oh); ret |= _init_interface_clks(oh); ret |= _init_opt_clks(oh); - if (soc_ops.init_clkdm) - ret |= soc_ops.init_clkdm(oh); if (!ret) oh->_state = _HWMOD_STATE_CLKS_INITED; @@ -2095,7 +2116,8 @@ static int _enable(struct omap_hwmod *oh) _enable_sysc(oh); } } else { - _omap4_disable_module(oh); + if (soc_ops.disable_module) + soc_ops.disable_module(oh); _disable_clocks(oh); pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", oh->name, r); @@ -2703,7 +2725,34 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois) /* Static functions intended only for use in soc_ops field function pointers */ /** - * _omap2_wait_target_ready - wait for a module to leave slave idle + * _omap2xxx_wait_target_ready - wait for a module to leave slave idle + * @oh: struct omap_hwmod * + * + * Wait for a module @oh to leave slave idle. Returns 0 if the module + * does not have an IDLEST bit or if the module successfully leaves + * slave idle; otherwise, pass along the return value of the + * appropriate *_cm*_wait_module_ready() function. + */ +static int _omap2xxx_wait_target_ready(struct omap_hwmod *oh) +{ + if (!oh) + return -EINVAL; + + if (oh->flags & HWMOD_NO_IDLEST) + return 0; + + if (!_find_mpu_rt_port(oh)) + return 0; + + /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ + + return omap2xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs, + oh->prcm.omap2.idlest_reg_id, + oh->prcm.omap2.idlest_idle_bit); +} + +/** + * _omap3xxx_wait_target_ready - wait for a module to leave slave idle * @oh: struct omap_hwmod * * * Wait for a module @oh to leave slave idle. Returns 0 if the module @@ -2711,7 +2760,7 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois) * slave idle; otherwise, pass along the return value of the * appropriate *_cm*_wait_module_ready() function. */ -static int _omap2_wait_target_ready(struct omap_hwmod *oh) +static int _omap3xxx_wait_target_ready(struct omap_hwmod *oh) { if (!oh) return -EINVAL; @@ -2724,9 +2773,9 @@ static int _omap2_wait_target_ready(struct omap_hwmod *oh) /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ - return omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs, - oh->prcm.omap2.idlest_reg_id, - oh->prcm.omap2.idlest_idle_bit); + return omap3xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs, + oh->prcm.omap2.idlest_reg_id, + oh->prcm.omap2.idlest_idle_bit); } /** @@ -3565,10 +3614,15 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) { struct clk *c; struct omap_hwmod_ocp_if *oi; + struct clockdomain *clkdm; + struct clk_hw_omap *clk; if (!oh) return NULL; + if (oh->clkdm) + return oh->clkdm->pwrdm.ptr; + if (oh->_clk) { c = oh->_clk; } else { @@ -3578,11 +3632,12 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) c = oi->_clk; } - if (!c->clkdm) + clk = to_clk_hw_omap(__clk_get_hw(c)); + clkdm = clk->clkdm; + if (!clkdm) return NULL; - return c->clkdm->pwrdm.ptr; - + return clkdm->pwrdm.ptr; } /** @@ -3994,8 +4049,13 @@ int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx) */ void __init omap_hwmod_init(void) { - if (cpu_is_omap24xx() || cpu_is_omap34xx()) { - soc_ops.wait_target_ready = _omap2_wait_target_ready; + if (cpu_is_omap24xx()) { + soc_ops.wait_target_ready = _omap2xxx_wait_target_ready; + soc_ops.assert_hardreset = _omap2_assert_hardreset; + soc_ops.deassert_hardreset = _omap2_deassert_hardreset; + soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; + } else if (cpu_is_omap34xx()) { + soc_ops.wait_target_ready = _omap3xxx_wait_target_ready; soc_ops.assert_hardreset = _omap2_assert_hardreset; soc_ops.deassert_hardreset = _omap2_deassert_hardreset; soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 1db029438022..87a3c5b7aa74 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -35,7 +35,6 @@ #include <linux/list.h> #include <linux/ioport.h> #include <linux/spinlock.h> -#include <plat/cpu.h> struct omap_device; diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index b5db6007c523..a8b3368dca3d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -12,21 +12,24 @@ * XXX handle crossbar/shared link difference for L3? * XXX these should be marked initdata for multi-OMAP kernels */ + +#include <linux/i2c-omap.h> #include <linux/platform_data/spi-omap2-mcspi.h> -#include <plat/omap_hwmod.h> -#include <plat/dma.h> -#include <plat/serial.h> -#include <plat/i2c.h> +#include <plat-omap/dma-omap.h> #include <plat/dmtimer.h> + +#include "omap_hwmod.h" #include "l3_2xxx.h" #include "l4_2xxx.h" -#include <plat/mmc.h> #include "omap_hwmod_common_data.h" #include "cm-regbits-24xx.h" #include "prm-regbits-24xx.h" +#include "i2c.h" +#include "mmc.h" +#include "serial.h" #include "wd_timer.h" /* diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index c455e41b0237..dc768c50e523 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -12,21 +12,23 @@ * XXX handle crossbar/shared link difference for L3? * XXX these should be marked initdata for multi-OMAP kernels */ + +#include <linux/i2c-omap.h> #include <linux/platform_data/asoc-ti-mcbsp.h> #include <linux/platform_data/spi-omap2-mcspi.h> -#include <plat/omap_hwmod.h> -#include <plat/dma.h> -#include <plat/serial.h> -#include <plat/i2c.h> +#include <plat-omap/dma-omap.h> #include <plat/dmtimer.h> -#include <plat/mmc.h> + +#include "omap_hwmod.h" +#include "mmc.h" #include "l3_2xxx.h" #include "soc.h" #include "omap_hwmod_common_data.h" #include "prm-regbits-24xx.h" #include "cm-regbits-24xx.h" +#include "i2c.h" #include "wd_timer.h" /* diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c index cbb4ef6544ad..0413daba2dba 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c @@ -13,8 +13,7 @@ */ #include <asm/sizes.h> -#include <plat/omap_hwmod.h> -#include <plat/serial.h> +#include "omap_hwmod.h" #include "omap_hwmod_common_data.h" diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c index 8851bbb6bb24..05c6a5906550 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c @@ -9,13 +9,16 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#include <plat/omap_hwmod.h> -#include <plat/serial.h> -#include <plat/dma.h> -#include <plat/common.h> + +#include <plat-omap/dma-omap.h> + +#include "../plat-omap/common.h" + +#include "omap_hwmod.h" #include "hdq1w.h" #include "omap_hwmod_common_data.h" +#include "dma.h" /* UART */ diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c index 1a1287d62648..47901a5e76de 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c @@ -13,10 +13,10 @@ */ #include <asm/sizes.h> -#include <plat/omap_hwmod.h> -#include <plat/serial.h> +#include "omap_hwmod.h" #include "l3_2xxx.h" #include "l4_2xxx.h" +#include "serial.h" #include "omap_hwmod_common_data.h" diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index bd9220ed5ab9..a0116d08cf45 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -8,13 +8,13 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#include <plat/omap_hwmod.h> -#include <plat/serial.h> + #include <linux/platform_data/gpio-omap.h> -#include <plat/dma.h> +#include <plat-omap/dma-omap.h> #include <plat/dmtimer.h> #include <linux/platform_data/spi-omap2-mcspi.h> +#include "omap_hwmod.h" #include "omap_hwmod_common_data.h" #include "cm-regbits-24xx.h" #include "prm-regbits-24xx.h" diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 59d5c1cd316d..ad8d43b33273 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -14,13 +14,11 @@ * GNU General Public License for more details. */ -#include <plat/omap_hwmod.h> -#include <plat/cpu.h> +#include <linux/i2c-omap.h> + +#include "omap_hwmod.h" #include <linux/platform_data/gpio-omap.h> #include <linux/platform_data/spi-omap2-mcspi.h> -#include <plat/dma.h> -#include <plat/mmc.h> -#include <plat/i2c.h> #include "omap_hwmod_common_data.h" @@ -28,6 +26,8 @@ #include "cm33xx.h" #include "prm33xx.h" #include "prm-regbits-33xx.h" +#include "i2c.h" +#include "mmc.h" /* * IP blocks diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 9693a187ff66..abe66ced903f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -14,16 +14,14 @@ * * XXX these should be marked initdata for multi-OMAP kernels */ + +#include <linux/i2c-omap.h> #include <linux/power/smartreflex.h> #include <linux/platform_data/gpio-omap.h> -#include <plat/omap_hwmod.h> -#include <plat/dma.h> -#include <plat/serial.h> +#include <plat-omap/dma-omap.h> #include "l3_3xxx.h" #include "l4_3xxx.h" -#include <plat/i2c.h> -#include <plat/mmc.h> #include <linux/platform_data/asoc-ti-mcbsp.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <plat/dmtimer.h> @@ -32,10 +30,16 @@ #include "am35xx.h" #include "soc.h" +#include "omap_hwmod.h" #include "omap_hwmod_common_data.h" #include "prm-regbits-34xx.h" #include "cm-regbits-34xx.h" + +#include "dma.h" +#include "i2c.h" +#include "mmc.h" #include "wd_timer.h" +#include "serial.h" /* * OMAP3xxx hardware module integration data @@ -1406,7 +1410,7 @@ static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { static struct omap_hwmod omap34xx_sr1_hwmod = { .name = "smartreflex_mpu_iva", .class = &omap34xx_smartreflex_hwmod_class, - .main_clk = "smartreflex_mpu_iva_fck", + .main_clk = "sr1_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, @@ -1424,7 +1428,7 @@ static struct omap_hwmod omap34xx_sr1_hwmod = { static struct omap_hwmod omap36xx_sr1_hwmod = { .name = "smartreflex_mpu_iva", .class = &omap36xx_smartreflex_hwmod_class, - .main_clk = "smartreflex_mpu_iva_fck", + .main_clk = "sr1_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, @@ -1451,7 +1455,7 @@ static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { static struct omap_hwmod omap34xx_sr2_hwmod = { .name = "smartreflex_core", .class = &omap34xx_smartreflex_hwmod_class, - .main_clk = "smartreflex_core_fck", + .main_clk = "sr2_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, @@ -1469,7 +1473,7 @@ static struct omap_hwmod omap34xx_sr2_hwmod = { static struct omap_hwmod omap36xx_sr2_hwmod = { .name = "smartreflex_core", .class = &omap36xx_smartreflex_hwmod_class, - .main_clk = "smartreflex_core_fck", + .main_clk = "sr2_fck", .prcm = { .omap2 = { .prcm_reg_id = 1, diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 0b1249e00398..d6700d3ddd04 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -22,22 +22,25 @@ #include <linux/platform_data/gpio-omap.h> #include <linux/power/smartreflex.h> #include <linux/platform_data/omap_ocp2scp.h> +#include <linux/i2c-omap.h> + +#include <plat-omap/dma-omap.h> -#include <plat/omap_hwmod.h> -#include <plat/i2c.h> -#include <plat/dma.h> #include <linux/platform_data/spi-omap2-mcspi.h> #include <linux/platform_data/asoc-ti-mcbsp.h> -#include <plat/mmc.h> #include <plat/dmtimer.h> -#include <plat/common.h> #include <plat/iommu.h> +#include "../plat-omap/common.h" + +#include "omap_hwmod.h" #include "omap_hwmod_common_data.h" #include "cm1_44xx.h" #include "cm2_44xx.h" #include "prm44xx.h" #include "prm-regbits-44xx.h" +#include "i2c.h" +#include "mmc.h" #include "wd_timer.h" /* Base offset for all OMAP4 interrupts external to MPUSS */ diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c index 9f1ccdc8cc8c..79d623b83e49 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c @@ -16,7 +16,7 @@ * data and their integration with other OMAP modules and Linux. */ -#include <plat/omap_hwmod.h> +#include "omap_hwmod.h" #include "omap_hwmod_common_data.h" diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index 2bc8f1705d4a..cfcce299177c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -13,7 +13,7 @@ #ifndef __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_COMMON_DATA_H #define __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_COMMON_DATA_H -#include <plat/omap_hwmod.h> +#include "omap_hwmod.h" #include "common.h" #include "display.h" diff --git a/arch/arm/mach-omap2/omap_opp_data.h b/arch/arm/mach-omap2/omap_opp_data.h index 18a750e296a8..336fdfcf88bb 100644 --- a/arch/arm/mach-omap2/omap_opp_data.h +++ b/arch/arm/mach-omap2/omap_opp_data.h @@ -19,7 +19,7 @@ #ifndef __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H #define __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H -#include <plat/omap_hwmod.h> +#include "omap_hwmod.h" #include "voltage.h" diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c index 9b56e5e1a2d2..e237602e10ea 100644 --- a/arch/arm/mach-omap2/omap_phy_internal.c +++ b/arch/arm/mach-omap2/omap_phy_internal.c @@ -27,11 +27,11 @@ #include <linux/io.h> #include <linux/err.h> #include <linux/usb.h> - -#include <plat/usb.h> +#include <linux/usb/musb.h> #include "soc.h" #include "control.h" +#include "usb.h" #define CONTROL_DEV_CONF 0x300 #define PHY_PD 0x1 diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c index 7ff9667d9761..fefd40166624 100644 --- a/arch/arm/mach-omap2/omap_twl.c +++ b/arch/arm/mach-omap2/omap_twl.c @@ -18,6 +18,7 @@ #include <linux/kernel.h> #include <linux/i2c/twl.h> +#include "soc.h" #include "voltage.h" #include "pm.h" diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c index 58e16aef40bb..bd41d59a7cab 100644 --- a/arch/arm/mach-omap2/opp.c +++ b/arch/arm/mach-omap2/opp.c @@ -20,7 +20,7 @@ #include <linux/opp.h> #include <linux/cpu.h> -#include <plat/omap_device.h> +#include "omap_device.h" #include "omap_opp_data.h" diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c index 75cef5f67a8a..62772e0e0d69 100644 --- a/arch/arm/mach-omap2/opp3xxx_data.c +++ b/arch/arm/mach-omap2/opp3xxx_data.c @@ -19,6 +19,7 @@ */ #include <linux/module.h> +#include "soc.h" #include "control.h" #include "omap_opp_data.h" #include "pm.h" diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 46092cd806fa..3cf4fdfd7ab0 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -27,12 +27,13 @@ #include <linux/module.h> #include <linux/slab.h> -#include <plat/clock.h> +#include "clock.h" #include "powerdomain.h" #include "clockdomain.h" #include <plat/dmtimer.h> -#include <plat/omap-pm.h> +#include "omap-pm.h" +#include "soc.h" #include "cm2xxx_3xxx.h" #include "prm2xxx_3xxx.h" #include "pm.h" diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index ef668c756db7..f4b3143a8b1d 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -20,10 +20,11 @@ #include <asm/system_misc.h> -#include <plat/omap-pm.h> -#include <plat/omap_device.h> +#include "omap-pm.h" +#include "omap_device.h" #include "common.h" +#include "soc.h" #include "prcm-common.h" #include "voltage.h" #include "powerdomain.h" diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 8af6cd6ac331..3d35bd64487c 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -25,7 +25,7 @@ #include <linux/sysfs.h> #include <linux/module.h> #include <linux/delay.h> -#include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/irq.h> #include <linux/time.h> #include <linux/gpio.h> @@ -36,14 +36,16 @@ #include <asm/mach-types.h> #include <asm/system_misc.h> -#include <plat/clock.h> -#include <plat/sram.h> -#include <plat/dma.h> +#include <plat-omap/dma-omap.h> +#include "../plat-omap/sram.h" + +#include "soc.h" #include "common.h" -#include "prm2xxx_3xxx.h" +#include "clock.h" +#include "prm2xxx.h" #include "prm-regbits-24xx.h" -#include "cm2xxx_3xxx.h" +#include "cm2xxx.h" #include "cm-regbits-24xx.h" #include "sdrc.h" #include "pm.h" @@ -200,7 +202,7 @@ static int omap2_can_sleep(void) { if (omap2_fclks_active()) return 0; - if (osc_ck->usecount > 1) + if (__clk_is_enabled(osc_ck)) return 0; if (omap_dma_running()) return 0; diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 3a904de4313e..a9b8da1629bf 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -35,20 +35,19 @@ #include <asm/suspend.h> #include <asm/system_misc.h> -#include <plat/sram.h> #include "clockdomain.h" #include "powerdomain.h" -#include <plat/sdrc.h> -#include <plat/prcm.h> -#include <plat/gpmc.h> -#include <plat/dma.h> +#include <plat-omap/dma-omap.h> +#include "../plat-omap/sram.h" + +#include "soc.h" #include "common.h" -#include "cm2xxx_3xxx.h" +#include "cm3xxx.h" #include "cm-regbits-34xx.h" +#include "gpmc.h" #include "prm-regbits-34xx.h" - -#include "prm2xxx_3xxx.h" +#include "prm3xxx.h" #include "pm.h" #include "sdrc.h" #include "control.h" diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index f2d69be9b77e..aa6fd98f606e 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -18,6 +18,7 @@ #include <linux/slab.h> #include <asm/system_misc.h> +#include "soc.h" #include "common.h" #include "clockdomain.h" #include "powerdomain.h" diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c index 2a791766283d..3cf79b54ce61 100644 --- a/arch/arm/mach-omap2/pmu.c +++ b/arch/arm/mach-omap2/pmu.c @@ -15,8 +15,9 @@ #include <asm/pmu.h> -#include <plat/omap_hwmod.h> -#include <plat/omap_device.h> +#include "soc.h" +#include "omap_hwmod.h" +#include "omap_device.h" static char *omap2_pmu_oh_names[] = {"mpu"}; static char *omap3_pmu_oh_names[] = {"mpu", "debugss"}; diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 1678a3284233..dea62a9aad07 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -29,8 +29,6 @@ #include <asm/cpu.h> -#include <plat/prcm.h> - #include "powerdomain.h" #include "clockdomain.h" diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index baee90608d11..5277d56eb37f 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -22,8 +22,6 @@ #include <linux/atomic.h> -#include <plat/cpu.h> - #include "voltage.h" /* Powerdomain basic power states */ diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c deleted file mode 100644 index 3950ccfe5f4a..000000000000 --- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * OMAP2 and OMAP3 powerdomain control - * - * Copyright (C) 2009-2011 Texas Instruments, Inc. - * Copyright (C) 2007-2009 Nokia Corporation - * - * Derived from mach-omap2/powerdomain.c written by Paul Walmsley - * Rajendra Nayak <rnayak@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/io.h> -#include <linux/errno.h> -#include <linux/delay.h> -#include <linux/bug.h> - -#include <plat/prcm.h> - -#include "powerdomain.h" -#include "prm.h" -#include "prm-regbits-24xx.h" -#include "prm-regbits-34xx.h" - - -/* Common functions across OMAP2 and OMAP3 */ -static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) -{ - omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, - (pwrst << OMAP_POWERSTATE_SHIFT), - pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); - return 0; -} - -static int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) -{ - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, - OMAP2_PM_PWSTCTRL, - OMAP_POWERSTATE_MASK); -} - -static int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm) -{ - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, - OMAP2_PM_PWSTST, - OMAP_POWERSTATEST_MASK); -} - -static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, - u8 pwrst) -{ - u32 m; - - m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); - - omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, - OMAP2_PM_PWSTCTRL); - - return 0; -} - -static int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, - u8 pwrst) -{ - u32 m; - - m = omap2_pwrdm_get_mem_bank_retst_mask(bank); - - omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, - OMAP2_PM_PWSTCTRL); - - return 0; -} - -static int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) -{ - u32 m; - - m = omap2_pwrdm_get_mem_bank_stst_mask(bank); - - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, - m); -} - -static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) -{ - u32 m; - - m = omap2_pwrdm_get_mem_bank_retst_mask(bank); - - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, - OMAP2_PM_PWSTCTRL, m); -} - -static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) -{ - u32 v; - - v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK); - omap2_prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v, - pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); - - return 0; -} - -static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm) -{ - u32 c = 0; - - /* - * REVISIT: pwrdm_wait_transition() may be better implemented - * via a callback and a periodic timer check -- how long do we expect - * powerdomain transitions to take? - */ - - /* XXX Is this udelay() value meaningful? */ - while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) & - OMAP_INTRANSITION_MASK) && - (c++ < PWRDM_TRANSITION_BAILOUT)) - udelay(1); - - if (c > PWRDM_TRANSITION_BAILOUT) { - pr_err("powerdomain: %s: waited too long to complete transition\n", - pwrdm->name); - return -EAGAIN; - } - - pr_debug("powerdomain: completed transition in %d loops\n", c); - - return 0; -} - -/* Applicable only for OMAP3. Not supported on OMAP2 */ -static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) -{ - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, - OMAP3430_PM_PREPWSTST, - OMAP3430_LASTPOWERSTATEENTERED_MASK); -} - -static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) -{ - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, - OMAP2_PM_PWSTST, - OMAP3430_LOGICSTATEST_MASK); -} - -static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm) -{ - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, - OMAP2_PM_PWSTCTRL, - OMAP3430_LOGICSTATEST_MASK); -} - -static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) -{ - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, - OMAP3430_PM_PREPWSTST, - OMAP3430_LASTLOGICSTATEENTERED_MASK); -} - -static int omap3_get_mem_bank_lastmemst_mask(u8 bank) -{ - switch (bank) { - case 0: - return OMAP3430_LASTMEM1STATEENTERED_MASK; - case 1: - return OMAP3430_LASTMEM2STATEENTERED_MASK; - case 2: - return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK; - case 3: - return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK; - default: - WARN_ON(1); /* should never happen */ - return -EEXIST; - } - return 0; -} - -static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) -{ - u32 m; - - m = omap3_get_mem_bank_lastmemst_mask(bank); - - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, - OMAP3430_PM_PREPWSTST, m); -} - -static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) -{ - omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST); - return 0; -} - -static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) -{ - return omap2_prm_rmw_mod_reg_bits(0, - 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, - pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); -} - -static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) -{ - return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, - 0, pwrdm->prcm_offs, - OMAP2_PM_PWSTCTRL); -} - -struct pwrdm_ops omap2_pwrdm_operations = { - .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst, - .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst, - .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst, - .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst, - .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst, - .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst, - .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst, - .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst, - .pwrdm_wait_transition = omap2_pwrdm_wait_transition, -}; - -struct pwrdm_ops omap3_pwrdm_operations = { - .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst, - .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst, - .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst, - .pwrdm_read_prev_pwrst = omap3_pwrdm_read_prev_pwrst, - .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst, - .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst, - .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst, - .pwrdm_read_prev_logic_pwrst = omap3_pwrdm_read_prev_logic_pwrst, - .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst, - .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst, - .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst, - .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst, - .pwrdm_read_prev_mem_pwrst = omap3_pwrdm_read_prev_mem_pwrst, - .pwrdm_clear_all_prev_pwrst = omap3_pwrdm_clear_all_prev_pwrst, - .pwrdm_enable_hdwr_sar = omap3_pwrdm_enable_hdwr_sar, - .pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar, - .pwrdm_wait_transition = omap2_pwrdm_wait_transition, -}; diff --git a/arch/arm/mach-omap2/powerdomain33xx.c b/arch/arm/mach-omap2/powerdomain33xx.c deleted file mode 100644 index 67c5663899b6..000000000000 --- a/arch/arm/mach-omap2/powerdomain33xx.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * AM33XX Powerdomain control - * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * Derived from mach-omap2/powerdomain44xx.c written by Rajendra Nayak - * <rnayak@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/io.h> -#include <linux/errno.h> -#include <linux/delay.h> - -#include <plat/prcm.h> - -#include "powerdomain.h" -#include "prm33xx.h" -#include "prm-regbits-33xx.h" - - -static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) -{ - am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK, - (pwrst << OMAP_POWERSTATE_SHIFT), - pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); - return 0; -} - -static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) -{ - u32 v; - - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); - v &= OMAP_POWERSTATE_MASK; - v >>= OMAP_POWERSTATE_SHIFT; - - return v; -} - -static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm) -{ - u32 v; - - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); - v &= OMAP_POWERSTATEST_MASK; - v >>= OMAP_POWERSTATEST_SHIFT; - - return v; -} - -static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) -{ - u32 v; - - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); - v &= AM33XX_LASTPOWERSTATEENTERED_MASK; - v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT; - - return v; -} - -static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) -{ - am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK, - (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT), - pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); - return 0; -} - -static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) -{ - am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK, - AM33XX_LASTPOWERSTATEENTERED_MASK, - pwrdm->prcm_offs, pwrdm->pwrstst_offs); - return 0; -} - -static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) -{ - u32 m; - - m = pwrdm->logicretstate_mask; - if (!m) - return -EINVAL; - - am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), - pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); - - return 0; -} - -static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) -{ - u32 v; - - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); - v &= AM33XX_LOGICSTATEST_MASK; - v >>= AM33XX_LOGICSTATEST_SHIFT; - - return v; -} - -static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm) -{ - u32 v, m; - - m = pwrdm->logicretstate_mask; - if (!m) - return -EINVAL; - - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); - v &= m; - v >>= __ffs(m); - - return v; -} - -static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, - u8 pwrst) -{ - u32 m; - - m = pwrdm->mem_on_mask[bank]; - if (!m) - return -EINVAL; - - am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), - pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); - - return 0; -} - -static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, - u8 pwrst) -{ - u32 m; - - m = pwrdm->mem_ret_mask[bank]; - if (!m) - return -EINVAL; - - am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), - pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); - - return 0; -} - -static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) -{ - u32 m, v; - - m = pwrdm->mem_pwrst_mask[bank]; - if (!m) - return -EINVAL; - - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); - v &= m; - v >>= __ffs(m); - - return v; -} - -static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) -{ - u32 m, v; - - m = pwrdm->mem_retst_mask[bank]; - if (!m) - return -EINVAL; - - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); - v &= m; - v >>= __ffs(m); - - return v; -} - -static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm) -{ - u32 c = 0; - - /* - * REVISIT: pwrdm_wait_transition() may be better implemented - * via a callback and a periodic timer check -- how long do we expect - * powerdomain transitions to take? - */ - - /* XXX Is this udelay() value meaningful? */ - while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs) - & OMAP_INTRANSITION_MASK) && - (c++ < PWRDM_TRANSITION_BAILOUT)) - udelay(1); - - if (c > PWRDM_TRANSITION_BAILOUT) { - pr_err("powerdomain: %s: waited too long to complete transition\n", - pwrdm->name); - return -EAGAIN; - } - - pr_debug("powerdomain: completed transition in %d loops\n", c); - - return 0; -} - -struct pwrdm_ops am33xx_pwrdm_operations = { - .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst, - .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst, - .pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst, - .pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst, - .pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst, - .pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst, - .pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst, - .pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst, - .pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange, - .pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst, - .pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst, - .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst, - .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst, - .pwrdm_wait_transition = am33xx_pwrdm_wait_transition, -}; diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c deleted file mode 100644 index aceb4f464c9b..000000000000 --- a/arch/arm/mach-omap2/powerdomain44xx.c +++ /dev/null @@ -1,285 +0,0 @@ -/* - * OMAP4 powerdomain control - * - * Copyright (C) 2009-2010, 2012 Texas Instruments, Inc. - * Copyright (C) 2007-2009 Nokia Corporation - * - * Derived from mach-omap2/powerdomain.c written by Paul Walmsley - * Rajendra Nayak <rnayak@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/io.h> -#include <linux/errno.h> -#include <linux/delay.h> -#include <linux/bug.h> - -#include "powerdomain.h" -#include <plat/prcm.h> -#include "prm2xxx_3xxx.h" -#include "prm44xx.h" -#include "prminst44xx.h" -#include "prm-regbits-44xx.h" - -static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) -{ - omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK, - (pwrst << OMAP_POWERSTATE_SHIFT), - pwrdm->prcm_partition, - pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); - return 0; -} - -static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) -{ - u32 v; - - v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, - OMAP4_PM_PWSTCTRL); - v &= OMAP_POWERSTATE_MASK; - v >>= OMAP_POWERSTATE_SHIFT; - - return v; -} - -static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm) -{ - u32 v; - - v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, - OMAP4_PM_PWSTST); - v &= OMAP_POWERSTATEST_MASK; - v >>= OMAP_POWERSTATEST_SHIFT; - - return v; -} - -static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) -{ - u32 v; - - v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, - OMAP4_PM_PWSTST); - v &= OMAP4430_LASTPOWERSTATEENTERED_MASK; - v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT; - - return v; -} - -static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) -{ - omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK, - (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT), - pwrdm->prcm_partition, - pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); - return 0; -} - -static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) -{ - omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK, - OMAP4430_LASTPOWERSTATEENTERED_MASK, - pwrdm->prcm_partition, - pwrdm->prcm_offs, OMAP4_PM_PWSTST); - return 0; -} - -static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) -{ - u32 v; - - v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK); - omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v, - pwrdm->prcm_partition, pwrdm->prcm_offs, - OMAP4_PM_PWSTCTRL); - - return 0; -} - -static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, - u8 pwrst) -{ - u32 m; - - m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); - - omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)), - pwrdm->prcm_partition, pwrdm->prcm_offs, - OMAP4_PM_PWSTCTRL); - - return 0; -} - -static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, - u8 pwrst) -{ - u32 m; - - m = omap2_pwrdm_get_mem_bank_retst_mask(bank); - - omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)), - pwrdm->prcm_partition, pwrdm->prcm_offs, - OMAP4_PM_PWSTCTRL); - - return 0; -} - -static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) -{ - u32 v; - - v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, - OMAP4_PM_PWSTST); - v &= OMAP4430_LOGICSTATEST_MASK; - v >>= OMAP4430_LOGICSTATEST_SHIFT; - - return v; -} - -static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm) -{ - u32 v; - - v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, - OMAP4_PM_PWSTCTRL); - v &= OMAP4430_LOGICRETSTATE_MASK; - v >>= OMAP4430_LOGICRETSTATE_SHIFT; - - return v; -} - -/** - * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate - * @pwrdm: struct powerdomain * to read the state for - * - * Reads the previous logic powerstate for a powerdomain. This - * function must determine the previous logic powerstate by first - * checking the previous powerstate for the domain. If that was OFF, - * then logic has been lost. If previous state was RETENTION, the - * function reads the setting for the next retention logic state to - * see the actual value. In every other case, the logic is - * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET - * depending whether the logic was retained or not. - */ -static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) -{ - int state; - - state = omap4_pwrdm_read_prev_pwrst(pwrdm); - - if (state == PWRDM_POWER_OFF) - return PWRDM_POWER_OFF; - - if (state != PWRDM_POWER_RET) - return PWRDM_POWER_RET; - - return omap4_pwrdm_read_logic_retst(pwrdm); -} - -static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) -{ - u32 m, v; - - m = omap2_pwrdm_get_mem_bank_stst_mask(bank); - - v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, - OMAP4_PM_PWSTST); - v &= m; - v >>= __ffs(m); - - return v; -} - -static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) -{ - u32 m, v; - - m = omap2_pwrdm_get_mem_bank_retst_mask(bank); - - v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, - OMAP4_PM_PWSTCTRL); - v &= m; - v >>= __ffs(m); - - return v; -} - -/** - * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate - * @pwrdm: struct powerdomain * to read mem powerstate for - * @bank: memory bank index - * - * Reads the previous memory powerstate for a powerdomain. This - * function must determine the previous memory powerstate by first - * checking the previous powerstate for the domain. If that was OFF, - * then logic has been lost. If previous state was RETENTION, the - * function reads the setting for the next memory retention state to - * see the actual value. In every other case, the logic is - * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET - * depending whether logic was retained or not. - */ -static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) -{ - int state; - - state = omap4_pwrdm_read_prev_pwrst(pwrdm); - - if (state == PWRDM_POWER_OFF) - return PWRDM_POWER_OFF; - - if (state != PWRDM_POWER_RET) - return PWRDM_POWER_RET; - - return omap4_pwrdm_read_mem_retst(pwrdm, bank); -} - -static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm) -{ - u32 c = 0; - - /* - * REVISIT: pwrdm_wait_transition() may be better implemented - * via a callback and a periodic timer check -- how long do we expect - * powerdomain transitions to take? - */ - - /* XXX Is this udelay() value meaningful? */ - while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition, - pwrdm->prcm_offs, - OMAP4_PM_PWSTST) & - OMAP_INTRANSITION_MASK) && - (c++ < PWRDM_TRANSITION_BAILOUT)) - udelay(1); - - if (c > PWRDM_TRANSITION_BAILOUT) { - pr_err("powerdomain: %s: waited too long to complete transition\n", - pwrdm->name); - return -EAGAIN; - } - - pr_debug("powerdomain: completed transition in %d loops\n", c); - - return 0; -} - -struct pwrdm_ops omap4_pwrdm_operations = { - .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst, - .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst, - .pwrdm_read_pwrst = omap4_pwrdm_read_pwrst, - .pwrdm_read_prev_pwrst = omap4_pwrdm_read_prev_pwrst, - .pwrdm_set_lowpwrstchange = omap4_pwrdm_set_lowpwrstchange, - .pwrdm_clear_all_prev_pwrst = omap4_pwrdm_clear_all_prev_pwrst, - .pwrdm_set_logic_retst = omap4_pwrdm_set_logic_retst, - .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst, - .pwrdm_read_prev_logic_pwrst = omap4_pwrdm_read_prev_logic_pwrst, - .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst, - .pwrdm_read_mem_pwrst = omap4_pwrdm_read_mem_pwrst, - .pwrdm_read_mem_retst = omap4_pwrdm_read_mem_retst, - .pwrdm_read_prev_mem_pwrst = omap4_pwrdm_read_prev_mem_pwrst, - .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst, - .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst, - .pwrdm_wait_transition = omap4_pwrdm_wait_transition, -}; diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c index 2385c1f009ee..ba520d4f7c7b 100644 --- a/arch/arm/mach-omap2/powerdomains2xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c @@ -14,6 +14,7 @@ #include <linux/kernel.h> #include <linux/init.h> +#include "soc.h" #include "powerdomain.h" #include "powerdomains2xxx_3xxx_data.h" diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 72df97482cc0..c7d355fafd24 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -406,11 +406,6 @@ #define OMAP3430_EN_CORE_MASK (1 << 0) -/* - * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP - * submodule to exit hardreset - */ -#define MAX_MODULE_HARDRESET_WAIT 10000 /* * Maximum time(us) it takes to output the signal WUCLKOUT of the last @@ -419,24 +414,7 @@ * microseconds on OMAP4, so this timeout may be too high. */ #define MAX_IOPAD_LATCH_TIME 100 - # ifndef __ASSEMBLER__ -extern void __iomem *prm_base; -extern void __iomem *cm_base; -extern void __iomem *cm2_base; -extern void __iomem *prcm_mpu_base; - -#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) -extern void omap_prm_base_init(void); -extern void omap_cm_base_init(void); -#else -static inline void omap_prm_base_init(void) -{ -} -static inline void omap_cm_base_init(void) -{ -} -#endif /** * struct omap_prcm_irq - describes a PRCM interrupt bit diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c deleted file mode 100644 index 0f51e034e0aa..000000000000 --- a/arch/arm/mach-omap2/prcm.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/prcm.c - * - * OMAP 24xx Power Reset and Clock Management (PRCM) functions - * - * Copyright (C) 2005 Nokia Corporation - * - * Written by Tony Lindgren <tony.lindgren@nokia.com> - * - * Copyright (C) 2007 Texas Instruments, Inc. - * Rajendra Nayak <rnayak@ti.com> - * - * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc. - * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/delay.h> -#include <linux/export.h> - -#include "common.h" -#include <plat/prcm.h> - -#include "clock.h" -#include "clock2xxx.h" -#include "cm2xxx_3xxx.h" -#include "prm2xxx_3xxx.h" -#include "prm44xx.h" -#include "prminst44xx.h" -#include "cminst44xx.h" -#include "prm-regbits-24xx.h" -#include "prm-regbits-44xx.h" -#include "control.h" - -void __iomem *prm_base; -void __iomem *cm_base; -void __iomem *cm2_base; -void __iomem *prcm_mpu_base; - -#define MAX_MODULE_ENABLE_WAIT 100000 - -u32 omap_prcm_get_reset_sources(void) -{ - /* XXX This presumably needs modification for 34XX */ - if (cpu_is_omap24xx() || cpu_is_omap34xx()) - return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; - if (cpu_is_omap44xx()) - return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; - - return 0; -} -EXPORT_SYMBOL(omap_prcm_get_reset_sources); - -/* Resets clock rates and reboots the system. Only called from system.h */ -void omap_prcm_restart(char mode, const char *cmd) -{ - s16 prcm_offs = 0; - - if (cpu_is_omap24xx()) { - omap2xxx_clk_prepare_for_reboot(); - - prcm_offs = WKUP_MOD; - } else if (cpu_is_omap34xx()) { - prcm_offs = OMAP3430_GR_MOD; - omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0)); - } else if (cpu_is_omap44xx()) { - omap4_prminst_global_warm_sw_reset(); /* never returns */ - } else { - WARN_ON(1); - } - - /* - * As per Errata i520, in some cases, user will not be able to - * access DDR memory after warm-reset. - * This situation occurs while the warm-reset happens during a read - * access to DDR memory. In that particular condition, DDR memory - * does not respond to a corrupted read command due to the warm - * reset occurrence but SDRC is waiting for read completion. - * SDRC is not sensitive to the warm reset, but the interconnect is - * reset on the fly, thus causing a misalignment between SDRC logic, - * interconnect logic and DDR memory state. - * WORKAROUND: - * Steps to perform before a Warm reset is trigged: - * 1. enable self-refresh on idle request - * 2. put SDRC in idle - * 3. wait until SDRC goes to idle - * 4. generate SW reset (Global SW reset) - * - * Steps to be performed after warm reset occurs (in bootloader): - * if HW warm reset is the source, apply below steps before any - * accesses to SDRAM: - * 1. Reset SMS and SDRC and wait till reset is complete - * 2. Re-initialize SMS, SDRC and memory - * - * NOTE: Above work around is required only if arch reset is implemented - * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need - * the WA since it resets SDRC as well as part of cold reset. - */ - - /* XXX should be moved to some OMAP2/3 specific code */ - omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, - OMAP2_RM_RSTCTRL); - omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */ -} - -/** - * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness - * @reg: physical address of module IDLEST register - * @mask: value to mask against to determine if the module is active - * @idlest: idle state indicator (0 or 1) for the clock - * @name: name of the clock (for printk) - * - * Returns 1 if the module indicated readiness in time, or 0 if it - * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds. - * - * XXX This function is deprecated. It should be removed once the - * hwmod conversion is complete. - */ -int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, - const char *name) -{ - int i = 0; - int ena = 0; - - if (idlest) - ena = 0; - else - ena = mask; - - /* Wait for lock */ - omap_test_timeout(((__raw_readl(reg) & mask) == ena), - MAX_MODULE_ENABLE_WAIT, i); - - if (i < MAX_MODULE_ENABLE_WAIT) - pr_debug("cm: Module associated with clock %s ready after %d loops\n", - name, i); - else - pr_err("cm: Module associated with clock %s didn't enable in %d tries\n", - name, MAX_MODULE_ENABLE_WAIT); - - return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0; -}; - -void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) -{ - if (omap2_globals->prm) - prm_base = omap2_globals->prm; - if (omap2_globals->cm) - cm_base = omap2_globals->cm; - if (omap2_globals->cm2) - cm2_base = omap2_globals->cm2; - if (omap2_globals->prcm_mpu) - prcm_mpu_base = omap2_globals->prcm_mpu; - - if (cpu_is_omap44xx() || soc_is_omap54xx()) { - omap_prm_base_init(); - omap_cm_base_init(); - } -} - -/* - * Stubbed functions so that common files continue to build when - * custom builds are used - * XXX These are temporary and should be removed at the earliest possible - * opportunity - */ -int __weak omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, - u16 clkctrl_offs) -{ - return 0; -} - -void __weak omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, - s16 cdoffs, u16 clkctrl_offs) -{ -} - -void __weak omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs, - u16 clkctrl_offs) -{ -} diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.c b/arch/arm/mach-omap2/prcm_mpu44xx.c index 928dbd4f20ed..c30e44a7fab0 100644 --- a/arch/arm/mach-omap2/prcm_mpu44xx.c +++ b/arch/arm/mach-omap2/prcm_mpu44xx.c @@ -20,6 +20,12 @@ #include "prcm_mpu44xx.h" #include "cm-regbits-44xx.h" +/* + * prcm_mpu_base: the virtual address of the start of the PRCM_MPU IP + * block registers + */ +void __iomem *prcm_mpu_base; + /* PRCM_MPU low-level functions */ u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 reg) @@ -43,3 +49,14 @@ u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) return v; } + +/** + * omap2_set_globals_prcm_mpu - set the MPU PRCM base address (for early use) + * @prcm_mpu: PRCM_MPU base virtual address + * + * XXX Will be replaced when the PRM/CM drivers are completed. + */ +void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu) +{ + prcm_mpu_base = prcm_mpu; +} diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h index 8a6e250f04b5..884af7bb4afd 100644 --- a/arch/arm/mach-omap2/prcm_mpu44xx.h +++ b/arch/arm/mach-omap2/prcm_mpu44xx.h @@ -1,7 +1,7 @@ /* * OMAP44xx PRCM MPU instance offset macros * - * Copyright (C) 2010 Texas Instruments, Inc. + * Copyright (C) 2010, 2012 Texas Instruments, Inc. * Copyright (C) 2010 Nokia Corporation * * Paul Walmsley (paul@pwsan.com) @@ -25,6 +25,12 @@ #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H +#include "common.h" + +# ifndef __ASSEMBLER__ +extern void __iomem *prcm_mpu_base; +# endif + #define OMAP4430_PRCM_MPU_BASE 0x48243000 #define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \ @@ -98,6 +104,7 @@ extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx); extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx); extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); +extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu); # endif #endif diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h index 6ac966103f34..91aa5106d637 100644 --- a/arch/arm/mach-omap2/prm-regbits-24xx.h +++ b/arch/arm/mach-omap2/prm-regbits-24xx.h @@ -14,7 +14,7 @@ * published by the Free Software Foundation. */ -#include "prm2xxx_3xxx.h" +#include "prm2xxx.h" /* Bits shared between registers */ @@ -107,12 +107,14 @@ #define OMAP2420_CLKOUT2_EN_MASK (1 << 15) #define OMAP2420_CLKOUT2_DIV_SHIFT 11 #define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11) +#define OMAP2420_CLKOUT2_DIV_WIDTH 3 #define OMAP2420_CLKOUT2_SOURCE_SHIFT 8 #define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) #define OMAP24XX_CLKOUT_EN_SHIFT 7 #define OMAP24XX_CLKOUT_EN_MASK (1 << 7) #define OMAP24XX_CLKOUT_DIV_SHIFT 3 #define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3) +#define OMAP24XX_CLKOUT_DIV_WIDTH 3 #define OMAP24XX_CLKOUT_SOURCE_SHIFT 0 #define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0) @@ -209,9 +211,13 @@ /* RM_RSTST_WKUP specific bits */ /* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */ +#define OMAP24XX_EXTWMPU_RST_SHIFT 6 #define OMAP24XX_EXTWMPU_RST_MASK (1 << 6) +#define OMAP24XX_SECU_WD_RST_SHIFT 5 #define OMAP24XX_SECU_WD_RST_MASK (1 << 5) +#define OMAP24XX_MPU_WD_RST_SHIFT 4 #define OMAP24XX_MPU_WD_RST_MASK (1 << 4) +#define OMAP24XX_SECU_VIOL_RST_SHIFT 3 #define OMAP24XX_SECU_VIOL_RST_MASK (1 << 3) /* PM_WKEN_WKUP specific bits */ diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index 64c087af6a8b..b0a2142eeb91 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h @@ -14,7 +14,7 @@ #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H -#include "prm2xxx_3xxx.h" +#include "prm3xxx.h" /* Shared register bits */ @@ -384,6 +384,7 @@ /* PRM_CLKSEL */ #define OMAP3430_SYS_CLKIN_SEL_SHIFT 0 #define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0) +#define OMAP3430_SYS_CLKIN_SEL_WIDTH 3 /* PRM_CLKOUT_CTRL */ #define OMAP3430_CLKOUT_EN_MASK (1 << 7) @@ -509,15 +510,25 @@ #define OMAP3430_RSTTIME1_MASK (0xff << 0) /* PRM_RSTST */ +#define OMAP3430_ICECRUSHER_RST_SHIFT 10 #define OMAP3430_ICECRUSHER_RST_MASK (1 << 10) +#define OMAP3430_ICEPICK_RST_SHIFT 9 #define OMAP3430_ICEPICK_RST_MASK (1 << 9) +#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT 8 #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK (1 << 8) +#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT 7 #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK (1 << 7) +#define OMAP3430_EXTERNAL_WARM_RST_SHIFT 6 #define OMAP3430_EXTERNAL_WARM_RST_MASK (1 << 6) +#define OMAP3430_SECURE_WD_RST_SHIFT 5 #define OMAP3430_SECURE_WD_RST_MASK (1 << 5) +#define OMAP3430_MPU_WD_RST_SHIFT 4 #define OMAP3430_MPU_WD_RST_MASK (1 << 4) +#define OMAP3430_SECURITY_VIOL_RST_SHIFT 3 #define OMAP3430_SECURITY_VIOL_RST_MASK (1 << 3) +#define OMAP3430_GLOBAL_SW_RST_SHIFT 1 #define OMAP3430_GLOBAL_SW_RST_MASK (1 << 1) +#define OMAP3430_GLOBAL_COLD_RST_SHIFT 0 #define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0) /* PRM_VOLTCTRL */ diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 39d562169d18..a1a266ce90da 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -1,7 +1,7 @@ /* * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions * - * Copyright (C) 2007-2009 Texas Instruments, Inc. + * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc. * Copyright (C) 2010 Nokia Corporation * * Paul Walmsley @@ -15,6 +15,28 @@ #include "prcm-common.h" +# ifndef __ASSEMBLER__ +extern void __iomem *prm_base; +extern void omap2_set_globals_prm(void __iomem *prm); +# endif + + +/* + * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP + * module to softreset + */ +#define MAX_MODULE_SOFTRESET_WAIT 10000 + +/* + * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP + * submodule to exit hardreset + */ +#define MAX_MODULE_HARDRESET_WAIT 10000 + +/* + * Register bitfields + */ + /* * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP * @@ -52,5 +74,58 @@ #define OMAP_POWERSTATE_SHIFT 0 #define OMAP_POWERSTATE_MASK (0x3 << 0) +/* + * Standardized OMAP reset source bits + * + * To the extent these happen to match the hardware register bit + * shifts, it's purely coincidental. Used by omap-wdt.c. + * OMAP_UNKNOWN_RST_SRC_ID_SHIFT is a special value, used whenever + * there are any bits remaining in the global PRM_RSTST register that + * haven't been identified, or when the PRM code for the current SoC + * doesn't know how to interpret the register. + */ +#define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT 0 +#define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT 1 +#define OMAP_SECU_VIOL_RST_SRC_ID_SHIFT 2 +#define OMAP_MPU_WD_RST_SRC_ID_SHIFT 3 +#define OMAP_SECU_WD_RST_SRC_ID_SHIFT 4 +#define OMAP_EXTWARM_RST_SRC_ID_SHIFT 5 +#define OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT 6 +#define OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT 7 +#define OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT 8 +#define OMAP_ICEPICK_RST_SRC_ID_SHIFT 9 +#define OMAP_ICECRUSHER_RST_SRC_ID_SHIFT 10 +#define OMAP_C2C_RST_SRC_ID_SHIFT 11 +#define OMAP_UNKNOWN_RST_SRC_ID_SHIFT 12 + +#ifndef __ASSEMBLER__ + +/** + * struct prm_reset_src_map - map register bitshifts to standard bitshifts + * @reg_shift: bitshift in the PRM reset source register + * @std_shift: bitshift equivalent in the standard reset source list + * + * The fields are signed because -1 is used as a terminator. + */ +struct prm_reset_src_map { + s8 reg_shift; + s8 std_shift; +}; + +/** + * struct prm_ll_data - fn ptrs to per-SoC PRM function implementations + * @read_reset_sources: ptr to the Soc PRM-specific get_reset_source impl + */ +struct prm_ll_data { + u32 (*read_reset_sources)(void); +}; + +extern int prm_register(struct prm_ll_data *pld); +extern int prm_unregister(struct prm_ll_data *pld); + +extern u32 prm_read_reset_sources(void); + +#endif + #endif diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c new file mode 100644 index 000000000000..bf24fc47603b --- /dev/null +++ b/arch/arm/mach-omap2/prm2xxx.c @@ -0,0 +1,139 @@ +/* + * OMAP2xxx PRM module functions + * + * Copyright (C) 2010-2012 Texas Instruments, Inc. + * Copyright (C) 2010 Nokia Corporation + * Benoît Cousson + * Paul Walmsley + * Rajendra Nayak <rnayak@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/irq.h> + +#include "common.h" +#include <plat/cpu.h> + +#include "vp.h" +#include "powerdomain.h" +#include "clockdomain.h" +#include "prm2xxx.h" +#include "cm2xxx_3xxx.h" +#include "prm-regbits-24xx.h" + +/* + * omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP + * hardware register (which are specific to the OMAP2xxx SoCs) to + * reset source ID bit shifts (which is an OMAP SoC-independent + * enumeration) + */ +static struct prm_reset_src_map omap2xxx_prm_reset_src_map[] = { + { OMAP_GLOBALCOLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT }, + { OMAP_GLOBALWARM_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT }, + { OMAP24XX_SECU_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT }, + { OMAP24XX_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT }, + { OMAP24XX_SECU_WD_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT }, + { OMAP24XX_EXTWMPU_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT }, + { -1, -1 }, +}; + +/** + * omap2xxx_prm_read_reset_sources - return the last SoC reset source + * + * Return a u32 representing the last reset sources of the SoC. The + * returned reset source bits are standardized across OMAP SoCs. + */ +static u32 omap2xxx_prm_read_reset_sources(void) +{ + struct prm_reset_src_map *p; + u32 r = 0; + u32 v; + + v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST); + + p = omap2xxx_prm_reset_src_map; + while (p->reg_shift >= 0 && p->std_shift >= 0) { + if (v & (1 << p->reg_shift)) + r |= 1 << p->std_shift; + p++; + } + + return r; +} + +/** + * omap2xxx_prm_dpll_reset - use DPLL reset to reboot the OMAP SoC + * + * Set the DPLL reset bit, which should reboot the SoC. This is the + * recommended way to restart the SoC. No return value. + */ +void omap2xxx_prm_dpll_reset(void) +{ + omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, WKUP_MOD, + OMAP2_RM_RSTCTRL); + /* OCP barrier */ + omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL); +} + +int omap2xxx_clkdm_sleep(struct clockdomain *clkdm) +{ + omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, + clkdm->pwrdm.ptr->prcm_offs, + OMAP2_PM_PWSTCTRL); + return 0; +} + +int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm) +{ + omap2_prm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, + clkdm->pwrdm.ptr->prcm_offs, + OMAP2_PM_PWSTCTRL); + return 0; +} + +struct pwrdm_ops omap2_pwrdm_operations = { + .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst, + .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst, + .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst, + .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst, + .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst, + .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst, + .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst, + .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst, + .pwrdm_wait_transition = omap2_pwrdm_wait_transition, +}; + +/* + * + */ + +static struct prm_ll_data omap2xxx_prm_ll_data = { + .read_reset_sources = &omap2xxx_prm_read_reset_sources, +}; + +static int __init omap2xxx_prm_init(void) +{ + if (!cpu_is_omap24xx()) + return 0; + + return prm_register(&omap2xxx_prm_ll_data); +} +subsys_initcall(omap2xxx_prm_init); + +static void __exit omap2xxx_prm_exit(void) +{ + if (!cpu_is_omap24xx()) + return; + + /* Should never happen */ + WARN(prm_unregister(&omap2xxx_prm_ll_data), + "%s: prm_ll_data function pointer mismatch\n", __func__); +} +__exitcall(omap2xxx_prm_exit); diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h new file mode 100644 index 000000000000..fe8a14f190ab --- /dev/null +++ b/arch/arm/mach-omap2/prm2xxx.h @@ -0,0 +1,134 @@ +/* + * OMAP2xxx Power/Reset Management (PRM) register definitions + * + * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc. + * Copyright (C) 2008-2010 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * The PRM hardware modules on the OMAP2/3 are quite similar to each + * other. The PRM on OMAP4 has a new register layout, and is handled + * in a separate file. + */ +#ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_H +#define __ARCH_ARM_MACH_OMAP2_PRM2XXX_H + +#include "prcm-common.h" +#include "prm.h" +#include "prm2xxx_3xxx.h" + +#define OMAP2420_PRM_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) +#define OMAP2430_PRM_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) + +/* + * OMAP2-specific global PRM registers + * Use __raw_{read,write}l() with these registers. + * + * With a few exceptions, these are the register names beginning with + * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE + * bits.) + * + */ + +#define OMAP2_PRCM_REVISION_OFFSET 0x0000 +#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000) +#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010 +#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010) + +#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018 +#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018) +#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c +#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c) + +#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050 +#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050) +#define OMAP2_PRCM_VOLTST_OFFSET 0x0054 +#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054) +#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060 +#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060) +#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070 +#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070) +#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078 +#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078) +#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080 +#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080) +#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084 +#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084) +#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090 +#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090) +#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094 +#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094) +#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098 +#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098) + +#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000) +#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010) + +#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018) +#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c) + +#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050) +#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054) +#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060) +#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070) +#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078) +#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080) +#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084) +#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090) +#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094) +#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098) + +/* + * Module specific PRM register offsets from PRM_BASE + domain offset + * + * Use prm_{read,write}_mod_reg() with these registers. + * + * With a few exceptions, these are the register names beginning with + * {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the + * IRQSTATUS and IRQENABLE bits.) + */ + +/* Register offsets appearing on both OMAP2 and OMAP3 */ + +#define OMAP2_RM_RSTCTRL 0x0050 +#define OMAP2_RM_RSTTIME 0x0054 +#define OMAP2_RM_RSTST 0x0058 +#define OMAP2_PM_PWSTCTRL 0x00e0 +#define OMAP2_PM_PWSTST 0x00e4 + +#define PM_WKEN 0x00a0 +#define PM_WKEN1 PM_WKEN +#define PM_WKST 0x00b0 +#define PM_WKST1 PM_WKST +#define PM_WKDEP 0x00c8 +#define PM_EVGENCTRL 0x00d4 +#define PM_EVGENONTIM 0x00d8 +#define PM_EVGENOFFTIM 0x00dc + +/* OMAP2xxx specific register offsets */ +#define OMAP24XX_PM_WKEN2 0x00a4 +#define OMAP24XX_PM_WKST2 0x00b4 + +#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */ +#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */ +#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8 +#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc + +#ifndef __ASSEMBLER__ +/* Function prototypes */ +extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm); +extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm); + +extern void omap2xxx_prm_dpll_reset(void); + +extern int __init prm2xxx_init(void); +extern int __exit prm2xxx_exit(void); + +#endif + +#endif diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c index 9529984d8d2b..30517f5af707 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c @@ -15,82 +15,12 @@ #include <linux/errno.h> #include <linux/err.h> #include <linux/io.h> -#include <linux/irq.h> -#include <plat/prcm.h> - -#include "soc.h" #include "common.h" -#include "vp.h" - +#include "powerdomain.h" #include "prm2xxx_3xxx.h" -#include "cm2xxx_3xxx.h" #include "prm-regbits-24xx.h" -#include "prm-regbits-34xx.h" - -static const struct omap_prcm_irq omap3_prcm_irqs[] = { - OMAP_PRCM_IRQ("wkup", 0, 0), - OMAP_PRCM_IRQ("io", 9, 1), -}; - -static struct omap_prcm_irq_setup omap3_prcm_irq_setup = { - .ack = OMAP3_PRM_IRQSTATUS_MPU_OFFSET, - .mask = OMAP3_PRM_IRQENABLE_MPU_OFFSET, - .nr_regs = 1, - .irqs = omap3_prcm_irqs, - .nr_irqs = ARRAY_SIZE(omap3_prcm_irqs), - .irq = 11 + OMAP_INTC_START, - .read_pending_irqs = &omap3xxx_prm_read_pending_irqs, - .ocp_barrier = &omap3xxx_prm_ocp_barrier, - .save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen, - .restore_irqen = &omap3xxx_prm_restore_irqen, -}; - -u32 omap2_prm_read_mod_reg(s16 module, u16 idx) -{ - return __raw_readl(prm_base + module + idx); -} - -void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx) -{ - __raw_writel(val, prm_base + module + idx); -} - -/* Read-modify-write a register in a PRM module. Caller must lock */ -u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) -{ - u32 v; - - v = omap2_prm_read_mod_reg(module, idx); - v &= ~mask; - v |= bits; - omap2_prm_write_mod_reg(v, module, idx); - - return v; -} - -/* Read a PRM register, AND it, and shift the result down to bit 0 */ -u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) -{ - u32 v; - - v = omap2_prm_read_mod_reg(domain, idx); - v &= mask; - v >>= __ffs(mask); - - return v; -} - -u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) -{ - return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx); -} - -u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) -{ - return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx); -} - +#include "clockdomain.h" /** * omap2_prm_is_hardreset_asserted - read the HW reset line state of @@ -104,9 +34,6 @@ u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) */ int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift) { - if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) - return -EINVAL; - return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, (1 << shift)); } @@ -127,9 +54,6 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) { u32 mask; - if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) - return -EINVAL; - mask = 1 << shift; omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); @@ -156,9 +80,6 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift) u32 rst, st; int c; - if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) - return -EINVAL; - rst = 1 << rst_shift; st = 1 << st_shift; @@ -178,188 +99,155 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift) return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; } -/* PRM VP */ - -/* - * struct omap3_vp - OMAP3 VP register access description. - * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg - */ -struct omap3_vp { - u32 tranxdone_status; -}; - -static struct omap3_vp omap3_vp[] = { - [OMAP3_VP_VDD_MPU_ID] = { - .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK, - }, - [OMAP3_VP_VDD_CORE_ID] = { - .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK, - }, -}; - -#define MAX_VP_ID ARRAY_SIZE(omap3_vp); - -u32 omap3_prm_vp_check_txdone(u8 vp_id) -{ - struct omap3_vp *vp = &omap3_vp[vp_id]; - u32 irqstatus; - irqstatus = omap2_prm_read_mod_reg(OCP_MOD, - OMAP3_PRM_IRQSTATUS_MPU_OFFSET); - return irqstatus & vp->tranxdone_status; -} +/* Powerdomain low-level functions */ -void omap3_prm_vp_clear_txdone(u8 vp_id) +/* Common functions across OMAP2 and OMAP3 */ +int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) { - struct omap3_vp *vp = &omap3_vp[vp_id]; - - omap2_prm_write_mod_reg(vp->tranxdone_status, - OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); + omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, + (pwrst << OMAP_POWERSTATE_SHIFT), + pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); + return 0; } -u32 omap3_prm_vcvp_read(u8 offset) +int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) { - return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL, + OMAP_POWERSTATE_MASK); } -void omap3_prm_vcvp_write(u32 val, u8 offset) +int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm) { - omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTST, + OMAP_POWERSTATEST_MASK); } -u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) +int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, + u8 pwrst) { - return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset); + u32 m; + + m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); + + omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL); + + return 0; } -/** - * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events - * @events: ptr to a u32, preallocated by caller - * - * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM - * MPU IRQs, and store the result into the u32 pointed to by @events. - * No return value. - */ -void omap3xxx_prm_read_pending_irqs(unsigned long *events) +int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, + u8 pwrst) { - u32 mask, st; + u32 m; + + m = omap2_pwrdm_get_mem_bank_retst_mask(bank); - /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */ - mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); - st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); + omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL); - events[0] = mask & st; + return 0; } -/** - * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete - * - * Force any buffered writes to the PRM IP block to complete. Needed - * by the PRM IRQ handler, which reads and writes directly to the IP - * block, to avoid race conditions after acknowledging or clearing IRQ - * bits. No return value. - */ -void omap3xxx_prm_ocp_barrier(void) +int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) { - omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET); + u32 m; + + m = omap2_pwrdm_get_mem_bank_stst_mask(bank); + + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, + m); } -/** - * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg - * @saved_mask: ptr to a u32 array to save IRQENABLE bits - * - * Save the PRM_IRQENABLE_MPU register to @saved_mask. @saved_mask - * must be allocated by the caller. Intended to be used in the PRM - * interrupt handler suspend callback. The OCP barrier is needed to - * ensure the write to disable PRM interrupts reaches the PRM before - * returning; otherwise, spurious interrupts might occur. No return - * value. - */ -void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask) +int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) { - saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD, - OMAP3_PRM_IRQENABLE_MPU_OFFSET); - omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); + u32 m; + + m = omap2_pwrdm_get_mem_bank_retst_mask(bank); - /* OCP barrier */ - omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL, m); } -/** - * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args - * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously - * - * Restore the PRM_IRQENABLE_MPU register from @saved_mask. Intended - * to be used in the PRM interrupt handler resume callback to restore - * values saved by omap3xxx_prm_save_and_clear_irqen(). No OCP - * barrier should be needed here; any pending PRM interrupts will fire - * once the writes reach the PRM. No return value. - */ -void omap3xxx_prm_restore_irqen(u32 *saved_mask) +int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) { - omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD, - OMAP3_PRM_IRQENABLE_MPU_OFFSET); + u32 v; + + v = pwrst << __ffs(OMAP_LOGICRETSTATE_MASK); + omap2_prm_rmw_mod_reg_bits(OMAP_LOGICRETSTATE_MASK, v, pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL); + + return 0; } -/** - * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain - * - * Clear any previously-latched I/O wakeup events and ensure that the - * I/O wakeup gates are aligned with the current mux settings. Works - * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then - * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit. No - * return value. - */ -void omap3xxx_prm_reconfigure_io_chain(void) +int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm) { - int i = 0; + u32 c = 0; - omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, - PM_WKEN); + /* + * REVISIT: pwrdm_wait_transition() may be better implemented + * via a callback and a periodic timer check -- how long do we expect + * powerdomain transitions to take? + */ - omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) & - OMAP3430_ST_IO_CHAIN_MASK, - MAX_IOPAD_LATCH_TIME, i); - if (i == MAX_IOPAD_LATCH_TIME) - pr_warn("PRM: I/O chain clock line assertion timed out\n"); + /* XXX Is this udelay() value meaningful? */ + while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) & + OMAP_INTRANSITION_MASK) && + (c++ < PWRDM_TRANSITION_BAILOUT)) + udelay(1); - omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, - PM_WKEN); + if (c > PWRDM_TRANSITION_BAILOUT) { + pr_err("powerdomain: %s: waited too long to complete transition\n", + pwrdm->name); + return -EAGAIN; + } - omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD, - PM_WKST); + pr_debug("powerdomain: completed transition in %d loops\n", c); - omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST); + return 0; } -/** - * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches - * - * Activates the I/O wakeup event latches and allows events logged by - * those latches to signal a wakeup event to the PRCM. For I/O - * wakeups to occur, WAKEUPENABLE bits must be set in the pad mux - * registers, and omap3xxx_prm_reconfigure_io_chain() must be called. - * No return value. - */ -static void __init omap3xxx_prm_enable_io_wakeup(void) +int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) +{ + omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit), + clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); + return 0; +} + +int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) +{ + omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), + clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); + return 0; +} + +int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2) { - if (omap3_has_io_wakeup()) - omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, - PM_WKEN); + return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, + PM_WKDEP, (1 << clkdm2->dep_bit)); } -static int __init omap3xxx_prcm_init(void) +int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm) { - int ret = 0; - - if (cpu_is_omap34xx()) { - omap3xxx_prm_enable_io_wakeup(); - ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup); - if (!ret) - irq_set_status_flags(omap_prcm_event_to_irq("io"), - IRQ_NOAUTOEN); + struct clkdm_dep *cd; + u32 mask = 0; + + for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { + if (!cd->clkdm) + continue; /* only happens if data is erroneous */ + + /* PRM accesses are slow, so minimize them */ + mask |= 1 << cd->clkdm->dep_bit; + atomic_set(&cd->wkdep_usecount, 0); } - return ret; + omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, + PM_WKDEP); + return 0; } -subsys_initcall(omap3xxx_prcm_init); + diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h index c19d249b4816..9624b40836d4 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h @@ -1,7 +1,7 @@ /* - * OMAP2/3 Power/Reset Management (PRM) register definitions + * OMAP2xxx/3xxx-common Power/Reset Management (PRM) register definitions * - * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc. + * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc. * Copyright (C) 2008-2010 Nokia Corporation * Paul Walmsley * @@ -19,160 +19,6 @@ #include "prcm-common.h" #include "prm.h" -#define OMAP2420_PRM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) -#define OMAP2430_PRM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) -#define OMAP34XX_PRM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) - - -/* - * OMAP2-specific global PRM registers - * Use __raw_{read,write}l() with these registers. - * - * With a few exceptions, these are the register names beginning with - * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE - * bits.) - * - */ - -#define OMAP2_PRCM_REVISION_OFFSET 0x0000 -#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000) -#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010 -#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010) - -#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018 -#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018) -#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c -#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c) - -#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050 -#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050) -#define OMAP2_PRCM_VOLTST_OFFSET 0x0054 -#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054) -#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060 -#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060) -#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070 -#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070) -#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078 -#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078) -#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080 -#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080) -#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084 -#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084) -#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090 -#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090) -#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094 -#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094) -#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098 -#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098) - -#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000) -#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010) - -#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018) -#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c) - -#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050) -#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054) -#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060) -#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070) -#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078) -#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080) -#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084) -#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090) -#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094) -#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098) - -/* - * OMAP3-specific global PRM registers - * Use __raw_{read,write}l() with these registers. - * - * With a few exceptions, these are the register names beginning with - * PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE - * bits.) - */ - -#define OMAP3_PRM_REVISION_OFFSET 0x0004 -#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004) -#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014 -#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014) - -#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018 -#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018) -#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c -#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c) - - -#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020 -#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) -#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024 -#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) -#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028 -#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) -#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c -#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) -#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030 -#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) -#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034 -#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) -#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038 -#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) -#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c -#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) -#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050 -#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) -#define OMAP3_PRM_RSTTIME_OFFSET 0x0054 -#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) -#define OMAP3_PRM_RSTST_OFFSET 0x0058 -#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) -#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060 -#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) -#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064 -#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) -#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070 -#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) -#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090 -#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) -#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094 -#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) -#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098 -#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) -#define OMAP3_PRM_POLCTRL_OFFSET 0x009c -#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) -#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0 -#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) -#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0 -#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) -#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4 -#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) -#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8 -#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) -#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc -#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) -#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0 -#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) -#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4 -#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) -#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0 -#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) -#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4 -#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) -#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8 -#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) -#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc -#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) -#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0 -#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) -#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4 -#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) - -#define OMAP3_PRM_CLKSEL_OFFSET 0x0040 -#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) -#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070 -#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) - /* * Module specific PRM register offsets from PRM_BASE + domain offset * @@ -200,66 +46,83 @@ #define PM_EVGENONTIM 0x00d8 #define PM_EVGENOFFTIM 0x00dc -/* OMAP2xxx specific register offsets */ -#define OMAP24XX_PM_WKEN2 0x00a4 -#define OMAP24XX_PM_WKST2 0x00b4 - -#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */ -#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */ -#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8 -#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc -/* OMAP3 specific register offsets */ -#define OMAP3430ES2_PM_WKEN3 0x00f0 -#define OMAP3430ES2_PM_WKST3 0x00b8 - -#define OMAP3430_PM_MPUGRPSEL 0x00a4 -#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL -#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8 - -#define OMAP3430_PM_IVAGRPSEL 0x00a8 -#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL -#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4 - -#define OMAP3430_PM_PREPWSTST 0x00e8 - -#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 -#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc +#ifndef __ASSEMBLER__ +#include <linux/io.h> +#include "powerdomain.h" -#ifndef __ASSEMBLER__ /* Power/reset management domain register get/set */ -extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx); -extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx); -extern u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); -extern u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); -extern u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); -extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); +static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx) +{ + return __raw_readl(prm_base + module + idx); +} + +static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx) +{ + __raw_writel(val, prm_base + module + idx); +} + +/* Read-modify-write a register in a PRM module. Caller must lock */ +static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, + s16 idx) +{ + u32 v; + + v = omap2_prm_read_mod_reg(module, idx); + v &= ~mask; + v |= bits; + omap2_prm_write_mod_reg(v, module, idx); + + return v; +} + +/* Read a PRM register, AND it, and shift the result down to bit 0 */ +static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) +{ + u32 v; + + v = omap2_prm_read_mod_reg(domain, idx); + v &= mask; + v >>= __ffs(mask); + + return v; +} + +static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) +{ + return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx); +} + +static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) +{ + return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx); +} /* These omap2_ PRM functions apply to both OMAP2 and 3 */ extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift); extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift); -/* OMAP3-specific VP functions */ -u32 omap3_prm_vp_check_txdone(u8 vp_id); -void omap3_prm_vp_clear_txdone(u8 vp_id); - -/* - * OMAP3 access functions for voltage controller (VC) and - * voltage proccessor (VP) in the PRM. - */ -extern u32 omap3_prm_vcvp_read(u8 offset); -extern void omap3_prm_vcvp_write(u32 val, u8 offset); -extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); - -extern void omap3xxx_prm_reconfigure_io_chain(void); - -/* PRM interrupt-related functions */ -extern void omap3xxx_prm_read_pending_irqs(unsigned long *events); -extern void omap3xxx_prm_ocp_barrier(void); -extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask); -extern void omap3xxx_prm_restore_irqen(u32 *saved_mask); +extern int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); +extern int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm); +extern int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm); +extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, + u8 pwrst); +extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, + u8 pwrst); +extern int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); +extern int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); +extern int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst); +extern int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm); + +extern int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2); +extern int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2); +extern int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1, + struct clockdomain *clkdm2); +extern int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm); #endif /* __ASSEMBLER */ @@ -289,6 +152,7 @@ extern void omap3xxx_prm_restore_irqen(u32 *saved_mask); /* Named PRCM_CLKSRC_CTRL on the 24XX */ #define OMAP_SYSCLKDIV_SHIFT 6 #define OMAP_SYSCLKDIV_MASK (0x3 << 6) +#define OMAP_SYSCLKDIV_WIDTH 2 #define OMAP_AUTOEXTCLKMODE_SHIFT 3 #define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3) #define OMAP_SYSCLKSEL_SHIFT 0 @@ -348,7 +212,9 @@ extern void omap3xxx_prm_restore_irqen(u32 *saved_mask); * * 3430: RM_RSTST_CORE, RM_RSTST_EMU */ +#define OMAP_GLOBALWARM_RST_SHIFT 1 #define OMAP_GLOBALWARM_RST_MASK (1 << 1) +#define OMAP_GLOBALCOLD_RST_SHIFT 0 #define OMAP_GLOBALCOLD_RST_MASK (1 << 0) /* @@ -376,11 +242,4 @@ extern void omap3xxx_prm_restore_irqen(u32 *saved_mask); #define OMAP_LOGICRETSTATE_MASK (1 << 2) -/* - * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP - * submodule to exit hardreset - */ -#define MAX_MODULE_HARDRESET_WAIT 10000 - - #endif diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c index e7dbb6cf1255..53ec9cbaa3d3 100644 --- a/arch/arm/mach-omap2/prm33xx.c +++ b/arch/arm/mach-omap2/prm33xx.c @@ -19,9 +19,10 @@ #include <linux/err.h> #include <linux/io.h> -#include <plat/common.h> +#include "../plat-omap/common.h" #include "common.h" +#include "powerdomain.h" #include "prm33xx.h" #include "prm-regbits-33xx.h" @@ -133,3 +134,204 @@ int am33xx_prm_deassert_hardreset(u8 shift, s16 inst, return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; } + +static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) +{ + am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK, + (pwrst << OMAP_POWERSTATE_SHIFT), + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + return 0; +} + +static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + v &= OMAP_POWERSTATE_MASK; + v >>= OMAP_POWERSTATE_SHIFT; + + return v; +} + +static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); + v &= OMAP_POWERSTATEST_MASK; + v >>= OMAP_POWERSTATEST_SHIFT; + + return v; +} + +static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); + v &= AM33XX_LASTPOWERSTATEENTERED_MASK; + v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT; + + return v; +} + +static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) +{ + am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK, + (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT), + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + return 0; +} + +static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) +{ + am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK, + AM33XX_LASTPOWERSTATEENTERED_MASK, + pwrdm->prcm_offs, pwrdm->pwrstst_offs); + return 0; +} + +static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) +{ + u32 m; + + m = pwrdm->logicretstate_mask; + if (!m) + return -EINVAL; + + am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + + return 0; +} + +static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); + v &= AM33XX_LOGICSTATEST_MASK; + v >>= AM33XX_LOGICSTATEST_SHIFT; + + return v; +} + +static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm) +{ + u32 v, m; + + m = pwrdm->logicretstate_mask; + if (!m) + return -EINVAL; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + v &= m; + v >>= __ffs(m); + + return v; +} + +static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, + u8 pwrst) +{ + u32 m; + + m = pwrdm->mem_on_mask[bank]; + if (!m) + return -EINVAL; + + am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + + return 0; +} + +static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, + u8 pwrst) +{ + u32 m; + + m = pwrdm->mem_ret_mask[bank]; + if (!m) + return -EINVAL; + + am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), + pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + + return 0; +} + +static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) +{ + u32 m, v; + + m = pwrdm->mem_pwrst_mask[bank]; + if (!m) + return -EINVAL; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); + v &= m; + v >>= __ffs(m); + + return v; +} + +static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) +{ + u32 m, v; + + m = pwrdm->mem_retst_mask[bank]; + if (!m) + return -EINVAL; + + v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); + v &= m; + v >>= __ffs(m); + + return v; +} + +static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm) +{ + u32 c = 0; + + /* + * REVISIT: pwrdm_wait_transition() may be better implemented + * via a callback and a periodic timer check -- how long do we expect + * powerdomain transitions to take? + */ + + /* XXX Is this udelay() value meaningful? */ + while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs) + & OMAP_INTRANSITION_MASK) && + (c++ < PWRDM_TRANSITION_BAILOUT)) + udelay(1); + + if (c > PWRDM_TRANSITION_BAILOUT) { + pr_err("powerdomain: %s: waited too long to complete transition\n", + pwrdm->name); + return -EAGAIN; + } + + pr_debug("powerdomain: completed transition in %d loops\n", c); + + return 0; +} + +struct pwrdm_ops am33xx_pwrdm_operations = { + .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst, + .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst, + .pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst, + .pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst, + .pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst, + .pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst, + .pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst, + .pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst, + .pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange, + .pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst, + .pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst, + .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst, + .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst, + .pwrdm_wait_transition = am33xx_pwrdm_wait_transition, +}; diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c new file mode 100644 index 000000000000..b86116cf0db9 --- /dev/null +++ b/arch/arm/mach-omap2/prm3xxx.c @@ -0,0 +1,417 @@ +/* + * OMAP3xxx PRM module functions + * + * Copyright (C) 2010-2012 Texas Instruments, Inc. + * Copyright (C) 2010 Nokia Corporation + * Benoît Cousson + * Paul Walmsley + * Rajendra Nayak <rnayak@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/irq.h> + +#include "common.h" +#include <plat/cpu.h> + +#include "vp.h" +#include "powerdomain.h" +#include "prm3xxx.h" +#include "prm2xxx_3xxx.h" +#include "cm2xxx_3xxx.h" +#include "prm-regbits-34xx.h" + +static const struct omap_prcm_irq omap3_prcm_irqs[] = { + OMAP_PRCM_IRQ("wkup", 0, 0), + OMAP_PRCM_IRQ("io", 9, 1), +}; + +static struct omap_prcm_irq_setup omap3_prcm_irq_setup = { + .ack = OMAP3_PRM_IRQSTATUS_MPU_OFFSET, + .mask = OMAP3_PRM_IRQENABLE_MPU_OFFSET, + .nr_regs = 1, + .irqs = omap3_prcm_irqs, + .nr_irqs = ARRAY_SIZE(omap3_prcm_irqs), + .irq = 11 + OMAP_INTC_START, + .read_pending_irqs = &omap3xxx_prm_read_pending_irqs, + .ocp_barrier = &omap3xxx_prm_ocp_barrier, + .save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen, + .restore_irqen = &omap3xxx_prm_restore_irqen, +}; + +/* + * omap3_prm_reset_src_map - map from bits in the PRM_RSTST hardware + * register (which are specific to OMAP3xxx SoCs) to reset source ID + * bit shifts (which is an OMAP SoC-independent enumeration) + */ +static struct prm_reset_src_map omap3xxx_prm_reset_src_map[] = { + { OMAP3430_GLOBAL_COLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT }, + { OMAP3430_GLOBAL_SW_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT }, + { OMAP3430_SECURITY_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT }, + { OMAP3430_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT }, + { OMAP3430_SECURE_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT }, + { OMAP3430_EXTERNAL_WARM_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT }, + { OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT, + OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT }, + { OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT, + OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT }, + { OMAP3430_ICEPICK_RST_SHIFT, OMAP_ICEPICK_RST_SRC_ID_SHIFT }, + { OMAP3430_ICECRUSHER_RST_SHIFT, OMAP_ICECRUSHER_RST_SRC_ID_SHIFT }, + { -1, -1 }, +}; + +/* PRM VP */ + +/* + * struct omap3_vp - OMAP3 VP register access description. + * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg + */ +struct omap3_vp { + u32 tranxdone_status; +}; + +static struct omap3_vp omap3_vp[] = { + [OMAP3_VP_VDD_MPU_ID] = { + .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK, + }, + [OMAP3_VP_VDD_CORE_ID] = { + .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK, + }, +}; + +#define MAX_VP_ID ARRAY_SIZE(omap3_vp); + +u32 omap3_prm_vp_check_txdone(u8 vp_id) +{ + struct omap3_vp *vp = &omap3_vp[vp_id]; + u32 irqstatus; + + irqstatus = omap2_prm_read_mod_reg(OCP_MOD, + OMAP3_PRM_IRQSTATUS_MPU_OFFSET); + return irqstatus & vp->tranxdone_status; +} + +void omap3_prm_vp_clear_txdone(u8 vp_id) +{ + struct omap3_vp *vp = &omap3_vp[vp_id]; + + omap2_prm_write_mod_reg(vp->tranxdone_status, + OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); +} + +u32 omap3_prm_vcvp_read(u8 offset) +{ + return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset); +} + +void omap3_prm_vcvp_write(u32 val, u8 offset) +{ + omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset); +} + +u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) +{ + return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset); +} + +/** + * omap3xxx_prm_dpll3_reset - use DPLL3 reset to reboot the OMAP SoC + * + * Set the DPLL3 reset bit, which should reboot the SoC. This is the + * recommended way to restart the SoC, considering Errata i520. No + * return value. + */ +void omap3xxx_prm_dpll3_reset(void) +{ + omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, OMAP3430_GR_MOD, + OMAP2_RM_RSTCTRL); + /* OCP barrier */ + omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP2_RM_RSTCTRL); +} + +/** + * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events + * @events: ptr to a u32, preallocated by caller + * + * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM + * MPU IRQs, and store the result into the u32 pointed to by @events. + * No return value. + */ +void omap3xxx_prm_read_pending_irqs(unsigned long *events) +{ + u32 mask, st; + + /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */ + mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); + st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); + + events[0] = mask & st; +} + +/** + * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete + * + * Force any buffered writes to the PRM IP block to complete. Needed + * by the PRM IRQ handler, which reads and writes directly to the IP + * block, to avoid race conditions after acknowledging or clearing IRQ + * bits. No return value. + */ +void omap3xxx_prm_ocp_barrier(void) +{ + omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET); +} + +/** + * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg + * @saved_mask: ptr to a u32 array to save IRQENABLE bits + * + * Save the PRM_IRQENABLE_MPU register to @saved_mask. @saved_mask + * must be allocated by the caller. Intended to be used in the PRM + * interrupt handler suspend callback. The OCP barrier is needed to + * ensure the write to disable PRM interrupts reaches the PRM before + * returning; otherwise, spurious interrupts might occur. No return + * value. + */ +void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask) +{ + saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD, + OMAP3_PRM_IRQENABLE_MPU_OFFSET); + omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); + + /* OCP barrier */ + omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET); +} + +/** + * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args + * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously + * + * Restore the PRM_IRQENABLE_MPU register from @saved_mask. Intended + * to be used in the PRM interrupt handler resume callback to restore + * values saved by omap3xxx_prm_save_and_clear_irqen(). No OCP + * barrier should be needed here; any pending PRM interrupts will fire + * once the writes reach the PRM. No return value. + */ +void omap3xxx_prm_restore_irqen(u32 *saved_mask) +{ + omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD, + OMAP3_PRM_IRQENABLE_MPU_OFFSET); +} + +/** + * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain + * + * Clear any previously-latched I/O wakeup events and ensure that the + * I/O wakeup gates are aligned with the current mux settings. Works + * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then + * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit. No + * return value. + */ +void omap3xxx_prm_reconfigure_io_chain(void) +{ + int i = 0; + + omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, + PM_WKEN); + + omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) & + OMAP3430_ST_IO_CHAIN_MASK, + MAX_IOPAD_LATCH_TIME, i); + if (i == MAX_IOPAD_LATCH_TIME) + pr_warn("PRM: I/O chain clock line assertion timed out\n"); + + omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, + PM_WKEN); + + omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD, + PM_WKST); + + omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST); +} + +/** + * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches + * + * Activates the I/O wakeup event latches and allows events logged by + * those latches to signal a wakeup event to the PRCM. For I/O + * wakeups to occur, WAKEUPENABLE bits must be set in the pad mux + * registers, and omap3xxx_prm_reconfigure_io_chain() must be called. + * No return value. + */ +static void __init omap3xxx_prm_enable_io_wakeup(void) +{ + if (omap3_has_io_wakeup()) + omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, + PM_WKEN); +} + +/** + * omap3xxx_prm_read_reset_sources - return the last SoC reset source + * + * Return a u32 representing the last reset sources of the SoC. The + * returned reset source bits are standardized across OMAP SoCs. + */ +static u32 omap3xxx_prm_read_reset_sources(void) +{ + struct prm_reset_src_map *p; + u32 r = 0; + u32 v; + + v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST); + + p = omap3xxx_prm_reset_src_map; + while (p->reg_shift >= 0 && p->std_shift >= 0) { + if (v & (1 << p->reg_shift)) + r |= 1 << p->std_shift; + p++; + } + + return r; +} + +/* Powerdomain low-level functions */ + +/* Applicable only for OMAP3. Not supported on OMAP2 */ +static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) +{ + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP3430_PM_PREPWSTST, + OMAP3430_LASTPOWERSTATEENTERED_MASK); +} + +static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) +{ + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTST, + OMAP3430_LOGICSTATEST_MASK); +} + +static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm) +{ + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL, + OMAP3430_LOGICSTATEST_MASK); +} + +static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) +{ + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP3430_PM_PREPWSTST, + OMAP3430_LASTLOGICSTATEENTERED_MASK); +} + +static int omap3_get_mem_bank_lastmemst_mask(u8 bank) +{ + switch (bank) { + case 0: + return OMAP3430_LASTMEM1STATEENTERED_MASK; + case 1: + return OMAP3430_LASTMEM2STATEENTERED_MASK; + case 2: + return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK; + case 3: + return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK; + default: + WARN_ON(1); /* should never happen */ + return -EEXIST; + } + return 0; +} + +static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) +{ + u32 m; + + m = omap3_get_mem_bank_lastmemst_mask(bank); + + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP3430_PM_PREPWSTST, m); +} + +static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) +{ + omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST); + return 0; +} + +static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) +{ + return omap2_prm_rmw_mod_reg_bits(0, + 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, + pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); +} + +static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) +{ + return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, + 0, pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL); +} + +struct pwrdm_ops omap3_pwrdm_operations = { + .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst, + .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst, + .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst, + .pwrdm_read_prev_pwrst = omap3_pwrdm_read_prev_pwrst, + .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst, + .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst, + .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst, + .pwrdm_read_prev_logic_pwrst = omap3_pwrdm_read_prev_logic_pwrst, + .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst, + .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst, + .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst, + .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst, + .pwrdm_read_prev_mem_pwrst = omap3_pwrdm_read_prev_mem_pwrst, + .pwrdm_clear_all_prev_pwrst = omap3_pwrdm_clear_all_prev_pwrst, + .pwrdm_enable_hdwr_sar = omap3_pwrdm_enable_hdwr_sar, + .pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar, + .pwrdm_wait_transition = omap2_pwrdm_wait_transition, +}; + +/* + * + */ + +static struct prm_ll_data omap3xxx_prm_ll_data = { + .read_reset_sources = &omap3xxx_prm_read_reset_sources, +}; + +static int __init omap3xxx_prm_init(void) +{ + int ret; + + if (!cpu_is_omap34xx()) + return 0; + + ret = prm_register(&omap3xxx_prm_ll_data); + if (ret) + return ret; + + omap3xxx_prm_enable_io_wakeup(); + ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup); + if (!ret) + irq_set_status_flags(omap_prcm_event_to_irq("io"), + IRQ_NOAUTOEN); + + + return ret; +} +subsys_initcall(omap3xxx_prm_init); + +static void __exit omap3xxx_prm_exit(void) +{ + if (!cpu_is_omap34xx()) + return; + + /* Should never happen */ + WARN(prm_unregister(&omap3xxx_prm_ll_data), + "%s: prm_ll_data function pointer mismatch\n", __func__); +} +__exitcall(omap3xxx_prm_exit); diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h new file mode 100644 index 000000000000..10cd41a8129e --- /dev/null +++ b/arch/arm/mach-omap2/prm3xxx.h @@ -0,0 +1,162 @@ +/* + * OMAP3xxx Power/Reset Management (PRM) register definitions + * + * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc. + * Copyright (C) 2008-2010 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * The PRM hardware modules on the OMAP2/3 are quite similar to each + * other. The PRM on OMAP4 has a new register layout, and is handled + * in a separate file. + */ +#ifndef __ARCH_ARM_MACH_OMAP2_PRM3XXX_H +#define __ARCH_ARM_MACH_OMAP2_PRM3XXX_H + +#include "prcm-common.h" +#include "prm.h" +#include "prm2xxx_3xxx.h" + +#define OMAP34XX_PRM_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) + + +/* + * OMAP3-specific global PRM registers + * Use __raw_{read,write}l() with these registers. + * + * With a few exceptions, these are the register names beginning with + * PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE + * bits.) + */ + +#define OMAP3_PRM_REVISION_OFFSET 0x0004 +#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004) +#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014 +#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014) + +#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018 +#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018) +#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c +#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c) + + +#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020 +#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) +#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024 +#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) +#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028 +#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) +#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c +#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) +#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030 +#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) +#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034 +#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) +#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038 +#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) +#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c +#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) +#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050 +#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) +#define OMAP3_PRM_RSTTIME_OFFSET 0x0054 +#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) +#define OMAP3_PRM_RSTST_OFFSET 0x0058 +#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) +#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060 +#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) +#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064 +#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) +#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070 +#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) +#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090 +#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) +#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094 +#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) +#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098 +#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) +#define OMAP3_PRM_POLCTRL_OFFSET 0x009c +#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) +#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0 +#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) +#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0 +#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) +#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4 +#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) +#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8 +#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) +#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc +#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) +#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0 +#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) +#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4 +#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) +#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0 +#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) +#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4 +#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) +#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8 +#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) +#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc +#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) +#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0 +#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) +#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4 +#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) + +#define OMAP3_PRM_CLKSEL_OFFSET 0x0040 +#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) +#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070 +#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) + +/* OMAP3 specific register offsets */ +#define OMAP3430ES2_PM_WKEN3 0x00f0 +#define OMAP3430ES2_PM_WKST3 0x00b8 + +#define OMAP3430_PM_MPUGRPSEL 0x00a4 +#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL +#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8 + +#define OMAP3430_PM_IVAGRPSEL 0x00a8 +#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL +#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4 + +#define OMAP3430_PM_PREPWSTST 0x00e8 + +#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 +#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc + + +#ifndef __ASSEMBLER__ + +/* OMAP3-specific VP functions */ +u32 omap3_prm_vp_check_txdone(u8 vp_id); +void omap3_prm_vp_clear_txdone(u8 vp_id); + +/* + * OMAP3 access functions for voltage controller (VC) and + * voltage proccessor (VP) in the PRM. + */ +extern u32 omap3_prm_vcvp_read(u8 offset); +extern void omap3_prm_vcvp_write(u32 val, u8 offset); +extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); + +extern void omap3xxx_prm_reconfigure_io_chain(void); + +/* PRM interrupt-related functions */ +extern void omap3xxx_prm_read_pending_irqs(unsigned long *events); +extern void omap3xxx_prm_ocp_barrier(void); +extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask); +extern void omap3xxx_prm_restore_irqen(u32 *saved_mask); + +extern void omap3xxx_prm_dpll3_reset(void); + +extern u32 omap3xxx_prm_get_reset_sources(void); + +#endif /* __ASSEMBLER */ + + +#endif diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index f0c4d5f4a174..6d3467af205d 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -1,10 +1,11 @@ /* * OMAP4 PRM module functions * - * Copyright (C) 2011 Texas Instruments, Inc. + * Copyright (C) 2011-2012 Texas Instruments, Inc. * Copyright (C) 2010 Nokia Corporation * Benoît Cousson * Paul Walmsley + * Rajendra Nayak <rnayak@ti.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -17,7 +18,6 @@ #include <linux/err.h> #include <linux/io.h> -#include <plat/prcm.h> #include "soc.h" #include "iomap.h" @@ -27,6 +27,9 @@ #include "prm-regbits-44xx.h" #include "prcm44xx.h" #include "prminst44xx.h" +#include "powerdomain.h" + +/* Static data */ static const struct omap_prcm_irq omap4_prcm_irqs[] = { OMAP_PRCM_IRQ("wkup", 0, 0), @@ -46,6 +49,33 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = { .restore_irqen = &omap44xx_prm_restore_irqen, }; +/* + * omap44xx_prm_reset_src_map - map from bits in the PRM_RSTST + * hardware register (which are specific to OMAP44xx SoCs) to reset + * source ID bit shifts (which is an OMAP SoC-independent + * enumeration) + */ +static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = { + { OMAP4430_RST_GLOBAL_WARM_SW_SHIFT, + OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT }, + { OMAP4430_RST_GLOBAL_COLD_SW_SHIFT, + OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT }, + { OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT, + OMAP_SECU_VIOL_RST_SRC_ID_SHIFT }, + { OMAP4430_MPU_WDT_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT }, + { OMAP4430_SECURE_WDT_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT }, + { OMAP4430_EXTERNAL_WARM_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT }, + { OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT, + OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT }, + { OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT, + OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT }, + { OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT, + OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT }, + { OMAP4430_ICEPICK_RST_SHIFT, OMAP_ICEPICK_RST_SRC_ID_SHIFT }, + { OMAP4430_C2C_RST_SHIFT, OMAP_C2C_RST_SRC_ID_SHIFT }, + { -1, -1 }, +}; + /* PRM low-level functions */ /* Read a register in a CM/PRM instance in the PRM module */ @@ -291,12 +321,324 @@ static void __init omap44xx_prm_enable_io_wakeup(void) OMAP4_PRM_IO_PMCTRL_OFFSET); } -static int __init omap4xxx_prcm_init(void) +/** + * omap44xx_prm_read_reset_sources - return the last SoC reset source + * + * Return a u32 representing the last reset sources of the SoC. The + * returned reset source bits are standardized across OMAP SoCs. + */ +static u32 omap44xx_prm_read_reset_sources(void) +{ + struct prm_reset_src_map *p; + u32 r = 0; + u32 v; + + v = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, + OMAP4_RM_RSTST); + + p = omap44xx_prm_reset_src_map; + while (p->reg_shift >= 0 && p->std_shift >= 0) { + if (v & (1 << p->reg_shift)) + r |= 1 << p->std_shift; + p++; + } + + return r; +} + +/* Powerdomain low-level functions */ + +static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) +{ + omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK, + (pwrst << OMAP_POWERSTATE_SHIFT), + pwrdm->prcm_partition, + pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); + return 0; +} + +static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTCTRL); + v &= OMAP_POWERSTATE_MASK; + v >>= OMAP_POWERSTATE_SHIFT; + + return v; +} + +static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTST); + v &= OMAP_POWERSTATEST_MASK; + v >>= OMAP_POWERSTATEST_SHIFT; + + return v; +} + +static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTST); + v &= OMAP4430_LASTPOWERSTATEENTERED_MASK; + v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT; + + return v; +} + +static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) +{ + omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK, + (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT), + pwrdm->prcm_partition, + pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); + return 0; +} + +static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) +{ + omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK, + OMAP4430_LASTPOWERSTATEENTERED_MASK, + pwrdm->prcm_partition, + pwrdm->prcm_offs, OMAP4_PM_PWSTST); + return 0; +} + +static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) +{ + u32 v; + + v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK); + omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v, + pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTCTRL); + + return 0; +} + +static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, + u8 pwrst) +{ + u32 m; + + m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); + + omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)), + pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTCTRL); + + return 0; +} + +static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, + u8 pwrst) +{ + u32 m; + + m = omap2_pwrdm_get_mem_bank_retst_mask(bank); + + omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)), + pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTCTRL); + + return 0; +} + +static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) +{ + u32 v; + + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTST); + v &= OMAP4430_LOGICSTATEST_MASK; + v >>= OMAP4430_LOGICSTATEST_SHIFT; + + return v; +} + +static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm) { - if (cpu_is_omap44xx()) { - omap44xx_prm_enable_io_wakeup(); - return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup); + u32 v; + + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTCTRL); + v &= OMAP4430_LOGICRETSTATE_MASK; + v >>= OMAP4430_LOGICRETSTATE_SHIFT; + + return v; +} + +/** + * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate + * @pwrdm: struct powerdomain * to read the state for + * + * Reads the previous logic powerstate for a powerdomain. This + * function must determine the previous logic powerstate by first + * checking the previous powerstate for the domain. If that was OFF, + * then logic has been lost. If previous state was RETENTION, the + * function reads the setting for the next retention logic state to + * see the actual value. In every other case, the logic is + * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET + * depending whether the logic was retained or not. + */ +static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) +{ + int state; + + state = omap4_pwrdm_read_prev_pwrst(pwrdm); + + if (state == PWRDM_POWER_OFF) + return PWRDM_POWER_OFF; + + if (state != PWRDM_POWER_RET) + return PWRDM_POWER_RET; + + return omap4_pwrdm_read_logic_retst(pwrdm); +} + +static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) +{ + u32 m, v; + + m = omap2_pwrdm_get_mem_bank_stst_mask(bank); + + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTST); + v &= m; + v >>= __ffs(m); + + return v; +} + +static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) +{ + u32 m, v; + + m = omap2_pwrdm_get_mem_bank_retst_mask(bank); + + v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, + OMAP4_PM_PWSTCTRL); + v &= m; + v >>= __ffs(m); + + return v; +} + +/** + * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate + * @pwrdm: struct powerdomain * to read mem powerstate for + * @bank: memory bank index + * + * Reads the previous memory powerstate for a powerdomain. This + * function must determine the previous memory powerstate by first + * checking the previous powerstate for the domain. If that was OFF, + * then logic has been lost. If previous state was RETENTION, the + * function reads the setting for the next memory retention state to + * see the actual value. In every other case, the logic is + * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET + * depending whether logic was retained or not. + */ +static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) +{ + int state; + + state = omap4_pwrdm_read_prev_pwrst(pwrdm); + + if (state == PWRDM_POWER_OFF) + return PWRDM_POWER_OFF; + + if (state != PWRDM_POWER_RET) + return PWRDM_POWER_RET; + + return omap4_pwrdm_read_mem_retst(pwrdm, bank); +} + +static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm) +{ + u32 c = 0; + + /* + * REVISIT: pwrdm_wait_transition() may be better implemented + * via a callback and a periodic timer check -- how long do we expect + * powerdomain transitions to take? + */ + + /* XXX Is this udelay() value meaningful? */ + while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition, + pwrdm->prcm_offs, + OMAP4_PM_PWSTST) & + OMAP_INTRANSITION_MASK) && + (c++ < PWRDM_TRANSITION_BAILOUT)) + udelay(1); + + if (c > PWRDM_TRANSITION_BAILOUT) { + pr_err("powerdomain: %s: waited too long to complete transition\n", + pwrdm->name); + return -EAGAIN; } + + pr_debug("powerdomain: completed transition in %d loops\n", c); + return 0; } -subsys_initcall(omap4xxx_prcm_init); + +struct pwrdm_ops omap4_pwrdm_operations = { + .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst, + .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst, + .pwrdm_read_pwrst = omap4_pwrdm_read_pwrst, + .pwrdm_read_prev_pwrst = omap4_pwrdm_read_prev_pwrst, + .pwrdm_set_lowpwrstchange = omap4_pwrdm_set_lowpwrstchange, + .pwrdm_clear_all_prev_pwrst = omap4_pwrdm_clear_all_prev_pwrst, + .pwrdm_set_logic_retst = omap4_pwrdm_set_logic_retst, + .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst, + .pwrdm_read_prev_logic_pwrst = omap4_pwrdm_read_prev_logic_pwrst, + .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst, + .pwrdm_read_mem_pwrst = omap4_pwrdm_read_mem_pwrst, + .pwrdm_read_mem_retst = omap4_pwrdm_read_mem_retst, + .pwrdm_read_prev_mem_pwrst = omap4_pwrdm_read_prev_mem_pwrst, + .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst, + .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst, + .pwrdm_wait_transition = omap4_pwrdm_wait_transition, +}; + +/* + * XXX document + */ +static struct prm_ll_data omap44xx_prm_ll_data = { + .read_reset_sources = &omap44xx_prm_read_reset_sources, +}; + +static int __init omap44xx_prm_init(void) +{ + int ret; + + if (!cpu_is_omap44xx()) + return 0; + + ret = prm_register(&omap44xx_prm_ll_data); + if (ret) + return ret; + + omap44xx_prm_enable_io_wakeup(); + + return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup); +} +subsys_initcall(omap44xx_prm_init); + +static void __exit omap44xx_prm_exit(void) +{ + if (!cpu_is_omap44xx()) + return; + + /* Should never happen */ + WARN(prm_unregister(&omap44xx_prm_ll_data), + "%s: prm_ll_data function pointer mismatch\n", __func__); +} +__exitcall(omap44xx_prm_exit); diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index ee72ae6bd8c9..c8e1accdc90e 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h @@ -771,6 +771,8 @@ extern void omap44xx_prm_ocp_barrier(void); extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask); extern void omap44xx_prm_restore_irqen(u32 *saved_mask); +extern u32 omap44xx_prm_get_reset_sources(void); + # endif #endif diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 6b4d332be2f6..d2e0798a4c82 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -24,11 +24,13 @@ #include <linux/interrupt.h> #include <linux/slab.h> -#include <plat/common.h> -#include <plat/prcm.h> +#include "../plat-omap/common.h" #include "prm2xxx_3xxx.h" +#include "prm2xxx.h" +#include "prm3xxx.h" #include "prm44xx.h" +#include "common.h" /* * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs @@ -53,6 +55,16 @@ static struct irq_chip_generic **prcm_irq_chips; */ static struct omap_prcm_irq_setup *prcm_irq_setup; +/* prm_base: base virtual address of the PRM IP block */ +void __iomem *prm_base; + +/* + * prm_ll_data: function pointers to SoC-specific implementations of + * common PRM functions + */ +static struct prm_ll_data null_prm_ll_data; +static struct prm_ll_data *prm_ll_data = &null_prm_ll_data; + /* Private functions */ /* @@ -319,64 +331,82 @@ err: return -ENOMEM; } -/* - * Stubbed functions so that common files continue to build when - * custom builds are used - * XXX These are temporary and should be removed at the earliest possible - * opportunity +/** + * omap2_set_globals_prm - set the PRM base address (for early use) + * @prm: PRM base virtual address + * + * XXX Will be replaced when the PRM/CM drivers are completed. */ -u32 __weak omap2_prm_read_mod_reg(s16 module, u16 idx) +void __init omap2_set_globals_prm(void __iomem *prm) { - WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n"); - return 0; + prm_base = prm; } -void __weak omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx) +/** + * prm_read_reset_sources - return the sources of the SoC's last reset + * + * Return a u32 bitmask representing the reset sources that caused the + * SoC to reset. The low-level per-SoC functions called by this + * function remap the SoC-specific reset source bits into an + * OMAP-common set of reset source bits, defined in + * arch/arm/mach-omap2/prm.h. Returns the standardized reset source + * u32 bitmask from the hardware upon success, or returns (1 << + * OMAP_UNKNOWN_RST_SRC_ID_SHIFT) if no low-level read_reset_sources() + * function was registered. + */ +u32 prm_read_reset_sources(void) { - WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n"); -} + u32 ret = 1 << OMAP_UNKNOWN_RST_SRC_ID_SHIFT; -u32 __weak omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, - s16 module, s16 idx) -{ - WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n"); - return 0; -} + if (prm_ll_data->read_reset_sources) + ret = prm_ll_data->read_reset_sources(); + else + WARN_ONCE(1, "prm: %s: no mapping function defined for reset sources\n", __func__); -u32 __weak omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) -{ - WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n"); - return 0; + return ret; } -u32 __weak omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) +/** + * prm_register - register per-SoC low-level data with the PRM + * @pld: low-level per-SoC OMAP PRM data & function pointers to register + * + * Register per-SoC low-level OMAP PRM data and function pointers with + * the OMAP PRM common interface. The caller must keep the data + * pointed to by @pld valid until it calls prm_unregister() and + * it returns successfully. Returns 0 upon success, -EINVAL if @pld + * is NULL, or -EEXIST if prm_register() has already been called + * without an intervening prm_unregister(). + */ +int prm_register(struct prm_ll_data *pld) { - WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n"); - return 0; -} + if (!pld) + return -EINVAL; -u32 __weak omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) -{ - WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n"); - return 0; -} + if (prm_ll_data != &null_prm_ll_data) + return -EEXIST; -int __weak omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift) -{ - WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n"); - return 0; -} + prm_ll_data = pld; -int __weak omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) -{ - WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n"); return 0; } -int __weak omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, - u8 st_shift) +/** + * prm_unregister - unregister per-SoC low-level data & function pointers + * @pld: low-level per-SoC OMAP PRM data & function pointers to unregister + * + * Unregister per-SoC low-level OMAP PRM data and function pointers + * that were previously registered with prm_register(). The + * caller may not destroy any of the data pointed to by @pld until + * this function returns successfully. Returns 0 upon success, or + * -EINVAL if @pld is NULL or if @pld does not match the struct + * prm_ll_data * previously registered by prm_register(). + */ +int prm_unregister(struct prm_ll_data *pld) { - WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n"); + if (!pld || prm_ll_data != pld) + return -EINVAL; + + prm_ll_data = &null_prm_ll_data; + return 0; } - diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h index 46f2efb36596..a2ede2d65481 100644 --- a/arch/arm/mach-omap2/prminst44xx.h +++ b/arch/arm/mach-omap2/prminst44xx.h @@ -30,4 +30,6 @@ extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst, extern int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst, u16 rstctrl_offs); +extern void omap_prm_base_init(void); + #endif diff --git a/arch/arm/mach-omap2/scrm44xx.h b/arch/arm/mach-omap2/scrm44xx.h index 701bf2d32949..e897ac89a3fd 100644 --- a/arch/arm/mach-omap2/scrm44xx.h +++ b/arch/arm/mach-omap2/scrm44xx.h @@ -127,12 +127,14 @@ /* AUXCLKREQ0 */ #define OMAP4_MAPPING_SHIFT 2 #define OMAP4_MAPPING_MASK (0x7 << 2) +#define OMAP4_MAPPING_WIDTH 3 #define OMAP4_ACCURACY_SHIFT 1 #define OMAP4_ACCURACY_MASK (1 << 1) /* AUXCLK0 */ #define OMAP4_CLKDIV_SHIFT 16 #define OMAP4_CLKDIV_MASK (0xf << 16) +#define OMAP4_CLKDIV_WIDTH 4 #define OMAP4_DISABLECLK_SHIFT 9 #define OMAP4_DISABLECLK_MASK (1 << 9) #define OMAP4_ENABLE_SHIFT 8 diff --git a/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h b/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h index 8bfaf342a028..1ee58c281a31 100644 --- a/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h +++ b/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h @@ -11,7 +11,7 @@ #ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM #define __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM -#include <plat/sdrc.h> +#include "sdrc.h" /* Hynix H8MBX00U0MER-0EM */ static struct omap_sdrc_params h8mbx00u0mer0em_sdrc_params[] = { diff --git a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h index a391b4939f74..85cccc004c06 100644 --- a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h +++ b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h @@ -14,7 +14,7 @@ #ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF #define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF -#include <plat/sdrc.h> +#include "sdrc.h" /* Micron MT46H32M32LF-6 */ /* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */ diff --git a/arch/arm/mach-omap2/sdram-nokia.c b/arch/arm/mach-omap2/sdram-nokia.c index 845c4fd2b125..0fa7ffa9b5ed 100644 --- a/arch/arm/mach-omap2/sdram-nokia.c +++ b/arch/arm/mach-omap2/sdram-nokia.c @@ -18,10 +18,8 @@ #include <linux/io.h> #include "common.h" -#include <plat/clock.h> -#include <plat/sdrc.h> - #include "sdram-nokia.h" +#include "sdrc.h" /* In picoseconds, except for tREF (ns), tXP, tCKE, tWTR (clks) */ struct sdram_timings { diff --git a/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h b/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h index cd4352917022..003f7bf4e2e3 100644 --- a/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h +++ b/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h @@ -11,7 +11,7 @@ #ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM #define __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM -#include <plat/sdrc.h> +#include "sdrc.h" /* Numonyx M65KXXXXAM */ static struct omap_sdrc_params m65kxxxxam_sdrc_params[] = { diff --git a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h index 0e518a72831f..8dc3de5ebb5b 100644 --- a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h +++ b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h @@ -14,7 +14,7 @@ #ifndef ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6 #define ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6 -#include <plat/sdrc.h> +#include "sdrc.h" /* Qimonda HYB18M512160AF-6 */ static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = { diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c index e3d345f46409..3ed0d62333c5 100644 --- a/arch/arm/mach-omap2/sdrc.c +++ b/arch/arm/mach-omap2/sdrc.c @@ -23,11 +23,10 @@ #include <linux/clk.h> #include <linux/io.h> -#include "common.h" -#include <plat/clock.h> -#include <plat/sram.h> +#include "../plat-omap/sram.h" -#include <plat/sdrc.h> +#include "common.h" +#include "clock.h" #include "sdrc.h" static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1; @@ -115,12 +114,10 @@ int omap2_sdrc_get_params(unsigned long r, } -void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals) +void __init omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms) { - if (omap2_globals->sdrc) - omap2_sdrc_base = omap2_globals->sdrc; - if (omap2_globals->sms) - omap2_sms_base = omap2_globals->sms; + omap2_sdrc_base = sdrc; + omap2_sms_base = sms; } /** @@ -160,19 +157,3 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, sdrc_write_reg(l, SDRC_POWER); omap2_sms_save_context(); } - -void omap2_sms_write_rot_control(u32 val, unsigned ctx) -{ - sms_write_reg(val, SMS_ROT_CONTROL(ctx)); -} - -void omap2_sms_write_rot_size(u32 val, unsigned ctx) -{ - sms_write_reg(val, SMS_ROT_SIZE(ctx)); -} - -void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx) -{ - sms_write_reg(val, SMS_ROT_PHYSICAL_BA(ctx)); -} - diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h index b3f83799e6cf..446aa13511fd 100644 --- a/arch/arm/mach-omap2/sdrc.h +++ b/arch/arm/mach-omap2/sdrc.h @@ -2,12 +2,14 @@ #define __ARCH_ARM_MACH_OMAP2_SDRC_H /* - * OMAP2 SDRC register definitions + * OMAP2/3 SDRC/SMS macros and prototypes * - * Copyright (C) 2007 Texas Instruments, Inc. - * Copyright (C) 2007 Nokia Corporation + * Copyright (C) 2007-2008, 2012 Texas Instruments, Inc. + * Copyright (C) 2007-2008 Nokia Corporation * - * Written by Paul Walmsley + * Paul Walmsley + * Tony Lindgren + * Richard Woodruff * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -15,8 +17,6 @@ */ #undef DEBUG -#include <plat/sdrc.h> - #ifndef __ASSEMBLER__ #include <linux/io.h> @@ -50,6 +50,60 @@ static inline u32 sms_read_reg(u16 reg) { return __raw_readl(OMAP_SMS_REGADDR(reg)); } + +extern void omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms); + + +/** + * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate + * @rate: SDRC clock rate (in Hz) + * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate + * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate + * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate + * @mr: Value to program to SDRC_MR for this rate + * + * This structure holds a pre-computed set of register values for the + * SDRC for a given SDRC clock rate and SDRAM chip. These are + * intended to be pre-computed and specified in an array in the board-*.c + * files. The structure is keyed off the 'rate' field. + */ +struct omap_sdrc_params { + unsigned long rate; + u32 actim_ctrla; + u32 actim_ctrlb; + u32 rfr_ctrl; + u32 mr; +}; + +#ifdef CONFIG_SOC_HAS_OMAP2_SDRC +void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, + struct omap_sdrc_params *sdrc_cs1); +#else +static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, + struct omap_sdrc_params *sdrc_cs1) {}; +#endif + +int omap2_sdrc_get_params(unsigned long r, + struct omap_sdrc_params **sdrc_cs0, + struct omap_sdrc_params **sdrc_cs1); +void omap2_sms_save_context(void); +void omap2_sms_restore_context(void); + +struct memory_timings { + u32 m_type; /* ddr = 1, sdr = 0 */ + u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */ + u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */ + u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */ + u32 base_cs; /* base chip select to use for calculations */ +}; + +extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode); +struct omap_sdrc_params *rx51_get_sdram_timings(void); + +u32 omap2xxx_sdrc_dll_is_unlocked(void); +u32 omap2xxx_sdrc_reprogram(u32 level, u32 force); + + #else #define OMAP242X_SDRC_REGADDR(reg) \ OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg)) @@ -57,6 +111,7 @@ static inline u32 sms_read_reg(u16 reg) OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg)) #define OMAP34XX_SDRC_REGADDR(reg) \ OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) + #endif /* __ASSEMBLER__ */ /* Minimum frequency that the SDRC DLL can lock at */ @@ -74,4 +129,85 @@ static inline u32 sms_read_reg(u16 reg) */ #define SDRC_MPURATE_LOOPS 96 +/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */ + +#define SDRC_SYSCONFIG 0x010 +#define SDRC_CS_CFG 0x040 +#define SDRC_SHARING 0x044 +#define SDRC_ERR_TYPE 0x04C +#define SDRC_DLLA_CTRL 0x060 +#define SDRC_DLLA_STATUS 0x064 +#define SDRC_DLLB_CTRL 0x068 +#define SDRC_DLLB_STATUS 0x06C +#define SDRC_POWER 0x070 +#define SDRC_MCFG_0 0x080 +#define SDRC_MR_0 0x084 +#define SDRC_EMR2_0 0x08c +#define SDRC_ACTIM_CTRL_A_0 0x09c +#define SDRC_ACTIM_CTRL_B_0 0x0a0 +#define SDRC_RFR_CTRL_0 0x0a4 +#define SDRC_MANUAL_0 0x0a8 +#define SDRC_MCFG_1 0x0B0 +#define SDRC_MR_1 0x0B4 +#define SDRC_EMR2_1 0x0BC +#define SDRC_ACTIM_CTRL_A_1 0x0C4 +#define SDRC_ACTIM_CTRL_B_1 0x0C8 +#define SDRC_RFR_CTRL_1 0x0D4 +#define SDRC_MANUAL_1 0x0D8 + +#define SDRC_POWER_AUTOCOUNT_SHIFT 8 +#define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT) +#define SDRC_POWER_CLKCTRL_SHIFT 4 +#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT) +#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT) + +/* + * These values represent the number of memory clock cycles between + * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192 + * rows per device, and include a subtraction of a 50 cycle window in the + * event that the autorefresh command is delayed due to other SDRC activity. + * The '| 1' sets the ARE field to send one autorefresh when the autorefresh + * counter reaches 0. + * + * These represent optimal values for common parts, it won't work for all. + * As long as you scale down, most parameters are still work, they just + * become sub-optimal. The RFR value goes in the opposite direction. If you + * don't adjust it down as your clock period increases the refresh interval + * will not be met. Setting all parameters for complete worst case may work, + * but may cut memory performance by 2x. Due to errata the DLLs need to be + * unlocked and their value needs run time calibration. A dynamic call is + * need for that as no single right value exists acorss production samples. + * + * Only the FULL speed values are given. Current code is such that rate + * changes must be made at DPLLoutx2. The actual value adjustment for low + * frequency operation will be handled by omap_set_performance() + * + * By having the boot loader boot up in the fastest L4 speed available likely + * will result in something which you can switch between. + */ +#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1) +#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1) +#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1) +#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */ +#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */ + + +/* + * SMS register access + */ + +#define OMAP242X_SMS_REGADDR(reg) \ + (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg) +#define OMAP243X_SMS_REGADDR(reg) \ + (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg) +#define OMAP343X_SMS_REGADDR(reg) \ + (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg) + +/* SMS register offsets - read/write with sms_{read,write}_reg() */ + +#define SMS_SYSCONFIG 0x010 +/* REVISIT: fill in other SMS registers here */ + + + #endif diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c index 73e55e485329..26c1728e09ca 100644 --- a/arch/arm/mach-omap2/sdrc2xxx.c +++ b/arch/arm/mach-omap2/sdrc2xxx.c @@ -24,14 +24,12 @@ #include <linux/clk.h> #include <linux/io.h> -#include <plat/clock.h> -#include <plat/sram.h> -#include <plat/sdrc.h> +#include "../plat-omap/sram.h" #include "soc.h" #include "iomap.h" #include "common.h" -#include "prm2xxx_3xxx.h" +#include "prm2xxx.h" #include "clock.h" #include "sdrc.h" diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index a507cd6cf4f1..aa30a3c20883 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -28,19 +28,20 @@ #include <linux/console.h> #include <plat/omap-serial.h> -#include "common.h" -#include <plat/dma.h> -#include <plat/omap_hwmod.h> -#include <plat/omap_device.h> -#include <plat/omap-pm.h> -#include <plat/serial.h> +#include <plat-omap/dma-omap.h> +#include "common.h" +#include "omap_hwmod.h" +#include "omap_device.h" +#include "omap-pm.h" +#include "soc.h" #include "prm2xxx_3xxx.h" #include "pm.h" #include "cm2xxx_3xxx.h" #include "prm-regbits-34xx.h" #include "control.h" #include "mux.h" +#include "serial.h" /* * NOTE: By default the serial auto_suspend timeout is disabled as it causes diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/mach-omap2/serial.h index 65fce44dce34..6a6806271fcf 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/mach-omap2/serial.h @@ -29,11 +29,6 @@ */ #define OMAP_UART_INFO_OFS 0x3ffc -/* OMAP1 serial ports */ -#define OMAP1_UART1_BASE 0xfffb0000 -#define OMAP1_UART2_BASE 0xfffb0800 -#define OMAP1_UART3_BASE 0xfffb9800 - /* OMAP2 serial ports */ #define OMAP2_UART1_BASE 0x4806a000 #define OMAP2_UART2_BASE 0x4806c000 @@ -76,20 +71,14 @@ #define ZOOM_UART_VIRT 0xfa400000 #define OMAP_PORT_SHIFT 2 -#define OMAP7XX_PORT_SHIFT 0 #define ZOOM_PORT_SHIFT 1 -#define OMAP1510_BASE_BAUD (12000000/16) -#define OMAP16XX_BASE_BAUD (48000000/16) #define OMAP24XX_BASE_BAUD (48000000/16) /* * DEBUG_LL port encoding stored into the UART1 scratchpad register by * decomp_setup in uncompress.h */ -#define OMAP1UART1 11 -#define OMAP1UART2 12 -#define OMAP1UART3 13 #define OMAP2UART1 21 #define OMAP2UART2 22 #define OMAP2UART3 23 @@ -109,15 +98,6 @@ #define OMAP5UART4 OMAP4UART4 #define ZOOM_UART 95 /* Only on zoom2/3 */ -/* This is only used by 8250.c for omap1510 */ -#define is_omap_port(pt) ({int __ret = 0; \ - if ((pt)->port.mapbase == OMAP1_UART1_BASE || \ - (pt)->port.mapbase == OMAP1_UART2_BASE || \ - (pt)->port.mapbase == OMAP1_UART3_BASE) \ - __ret = 1; \ - __ret; \ - }) - #ifndef __ASSEMBLER__ struct omap_board_data; diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 506987979c1c..474dba7263e3 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -26,12 +26,12 @@ #include <asm/assembler.h> -#include <plat/sram.h> +#include "../plat-omap/sram.h" #include "omap34xx.h" #include "iomap.h" -#include "cm2xxx_3xxx.h" -#include "prm2xxx_3xxx.h" +#include "cm3xxx.h" +#include "prm3xxx.h" #include "sdrc.h" #include "control.h" diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index fc9b96daf851..070096496e20 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h @@ -1,7 +1,473 @@ -#include <plat/cpu.h> +/* + * OMAP cpu type detection + * + * Copyright (C) 2004, 2008 Nokia Corporation + * + * Copyright (C) 2009-11 Texas Instruments. + * + * Written by Tony Lindgren <tony.lindgren@nokia.com> + * + * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + #include "omap24xx.h" #include "omap34xx.h" #include "omap44xx.h" #include "ti81xx.h" #include "am33xx.h" #include "omap54xx.h" + +#ifndef __ASSEMBLY__ + +#include <linux/bitops.h> + +/* + * Test if multicore OMAP support is needed + */ +#undef MULTI_OMAP2 +#undef OMAP_NAME + +#ifdef CONFIG_SOC_OMAP2420 +# ifdef OMAP_NAME +# undef MULTI_OMAP2 +# define MULTI_OMAP2 +# else +# define OMAP_NAME omap2420 +# endif +#endif +#ifdef CONFIG_SOC_OMAP2430 +# ifdef OMAP_NAME +# undef MULTI_OMAP2 +# define MULTI_OMAP2 +# else +# define OMAP_NAME omap2430 +# endif +#endif +#ifdef CONFIG_ARCH_OMAP3 +# ifdef OMAP_NAME +# undef MULTI_OMAP2 +# define MULTI_OMAP2 +# else +# define OMAP_NAME omap3 +# endif +#endif +#ifdef CONFIG_ARCH_OMAP4 +# ifdef OMAP_NAME +# undef MULTI_OMAP2 +# define MULTI_OMAP2 +# else +# define OMAP_NAME omap4 +# endif +#endif + +#ifdef CONFIG_SOC_OMAP5 +# ifdef OMAP_NAME +# undef MULTI_OMAP2 +# define MULTI_OMAP2 +# else +# define OMAP_NAME omap5 +# endif +#endif + +#ifdef CONFIG_SOC_AM33XX +# ifdef OMAP_NAME +# undef MULTI_OMAP2 +# define MULTI_OMAP2 +# else +# define OMAP_NAME am33xx +# endif +#endif + +/* + * Omap device type i.e. EMU/HS/TST/GP/BAD + */ +#define OMAP2_DEVICE_TYPE_TEST 0 +#define OMAP2_DEVICE_TYPE_EMU 1 +#define OMAP2_DEVICE_TYPE_SEC 2 +#define OMAP2_DEVICE_TYPE_GP 3 +#define OMAP2_DEVICE_TYPE_BAD 4 + +int omap_type(void); + +/* + * omap_rev bits: + * CPU id bits (0730, 1510, 1710, 2422...) [31:16] + * CPU revision (See _REV_ defined in cpu.h) [15:08] + * CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00] + */ +unsigned int omap_rev(void); + +/* + * Get the CPU revision for OMAP devices + */ +#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff) + +/* + * Macros to group OMAP into cpu classes. + * These can be used in most places. + * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430 + * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423 + * cpu_is_omap243x(): True for OMAP2430 + * cpu_is_omap343x(): True for OMAP3430 + * cpu_is_omap443x(): True for OMAP4430 + * cpu_is_omap446x(): True for OMAP4460 + * cpu_is_omap447x(): True for OMAP4470 + * soc_is_omap543x(): True for OMAP5430, OMAP5432 + */ +#define GET_OMAP_CLASS (omap_rev() & 0xff) + +#define IS_OMAP_CLASS(class, id) \ +static inline int is_omap ##class (void) \ +{ \ + return (GET_OMAP_CLASS == (id)) ? 1 : 0; \ +} + +#define GET_AM_CLASS ((omap_rev() >> 24) & 0xff) + +#define IS_AM_CLASS(class, id) \ +static inline int is_am ##class (void) \ +{ \ + return (GET_AM_CLASS == (id)) ? 1 : 0; \ +} + +#define GET_TI_CLASS ((omap_rev() >> 24) & 0xff) + +#define IS_TI_CLASS(class, id) \ +static inline int is_ti ##class (void) \ +{ \ + return (GET_TI_CLASS == (id)) ? 1 : 0; \ +} + +#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff) + +#define IS_OMAP_SUBCLASS(subclass, id) \ +static inline int is_omap ##subclass (void) \ +{ \ + return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ +} + +#define IS_TI_SUBCLASS(subclass, id) \ +static inline int is_ti ##subclass (void) \ +{ \ + return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ +} + +#define IS_AM_SUBCLASS(subclass, id) \ +static inline int is_am ##subclass (void) \ +{ \ + return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ +} + +IS_OMAP_CLASS(24xx, 0x24) +IS_OMAP_CLASS(34xx, 0x34) +IS_OMAP_CLASS(44xx, 0x44) +IS_AM_CLASS(35xx, 0x35) +IS_OMAP_CLASS(54xx, 0x54) +IS_AM_CLASS(33xx, 0x33) + +IS_TI_CLASS(81xx, 0x81) + +IS_OMAP_SUBCLASS(242x, 0x242) +IS_OMAP_SUBCLASS(243x, 0x243) +IS_OMAP_SUBCLASS(343x, 0x343) +IS_OMAP_SUBCLASS(363x, 0x363) +IS_OMAP_SUBCLASS(443x, 0x443) +IS_OMAP_SUBCLASS(446x, 0x446) +IS_OMAP_SUBCLASS(447x, 0x447) +IS_OMAP_SUBCLASS(543x, 0x543) + +IS_TI_SUBCLASS(816x, 0x816) +IS_TI_SUBCLASS(814x, 0x814) +IS_AM_SUBCLASS(335x, 0x335) + +#define cpu_is_omap24xx() 0 +#define cpu_is_omap242x() 0 +#define cpu_is_omap243x() 0 +#define cpu_is_omap34xx() 0 +#define cpu_is_omap343x() 0 +#define cpu_is_ti81xx() 0 +#define cpu_is_ti816x() 0 +#define cpu_is_ti814x() 0 +#define soc_is_am35xx() 0 +#define soc_is_am33xx() 0 +#define soc_is_am335x() 0 +#define cpu_is_omap44xx() 0 +#define cpu_is_omap443x() 0 +#define cpu_is_omap446x() 0 +#define cpu_is_omap447x() 0 +#define soc_is_omap54xx() 0 +#define soc_is_omap543x() 0 + +#if defined(MULTI_OMAP2) +# if defined(CONFIG_ARCH_OMAP2) +# undef cpu_is_omap24xx +# define cpu_is_omap24xx() is_omap24xx() +# endif +# if defined (CONFIG_SOC_OMAP2420) +# undef cpu_is_omap242x +# define cpu_is_omap242x() is_omap242x() +# endif +# if defined (CONFIG_SOC_OMAP2430) +# undef cpu_is_omap243x +# define cpu_is_omap243x() is_omap243x() +# endif +# if defined(CONFIG_ARCH_OMAP3) +# undef cpu_is_omap34xx +# undef cpu_is_omap343x +# define cpu_is_omap34xx() is_omap34xx() +# define cpu_is_omap343x() is_omap343x() +# endif +#else +# if defined(CONFIG_ARCH_OMAP2) +# undef cpu_is_omap24xx +# define cpu_is_omap24xx() 1 +# endif +# if defined(CONFIG_SOC_OMAP2420) +# undef cpu_is_omap242x +# define cpu_is_omap242x() 1 +# endif +# if defined(CONFIG_SOC_OMAP2430) +# undef cpu_is_omap243x +# define cpu_is_omap243x() 1 +# endif +# if defined(CONFIG_ARCH_OMAP3) +# undef cpu_is_omap34xx +# define cpu_is_omap34xx() 1 +# endif +# if defined(CONFIG_SOC_OMAP3430) +# undef cpu_is_omap343x +# define cpu_is_omap343x() 1 +# endif +#endif + +/* + * Macros to detect individual cpu types. + * These are only rarely needed. + * cpu_is_omap2420(): True for OMAP2420 + * cpu_is_omap2422(): True for OMAP2422 + * cpu_is_omap2423(): True for OMAP2423 + * cpu_is_omap2430(): True for OMAP2430 + * cpu_is_omap3430(): True for OMAP3430 + */ +#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff) + +#define IS_OMAP_TYPE(type, id) \ +static inline int is_omap ##type (void) \ +{ \ + return (GET_OMAP_TYPE == (id)) ? 1 : 0; \ +} + +IS_OMAP_TYPE(2420, 0x2420) +IS_OMAP_TYPE(2422, 0x2422) +IS_OMAP_TYPE(2423, 0x2423) +IS_OMAP_TYPE(2430, 0x2430) +IS_OMAP_TYPE(3430, 0x3430) + +#define cpu_is_omap2420() 0 +#define cpu_is_omap2422() 0 +#define cpu_is_omap2423() 0 +#define cpu_is_omap2430() 0 +#define cpu_is_omap3430() 0 +#define cpu_is_omap3630() 0 +#define soc_is_omap5430() 0 + +/* These are needed for the common code */ +#ifdef CONFIG_ARCH_OMAP2PLUS +#define cpu_is_omap7xx() 0 +#define cpu_is_omap15xx() 0 +#define cpu_is_omap16xx() 0 +#define cpu_is_omap1510() 0 +#define cpu_is_omap1610() 0 +#define cpu_is_omap1611() 0 +#define cpu_is_omap1621() 0 +#define cpu_is_omap1710() 0 +#define cpu_class_is_omap1() 0 +#define cpu_class_is_omap2() 1 +#endif + +#if defined(CONFIG_ARCH_OMAP2) +# undef cpu_is_omap2420 +# undef cpu_is_omap2422 +# undef cpu_is_omap2423 +# undef cpu_is_omap2430 +# define cpu_is_omap2420() is_omap2420() +# define cpu_is_omap2422() is_omap2422() +# define cpu_is_omap2423() is_omap2423() +# define cpu_is_omap2430() is_omap2430() +#endif + +#if defined(CONFIG_ARCH_OMAP3) +# undef cpu_is_omap3430 +# undef cpu_is_ti81xx +# undef cpu_is_ti816x +# undef cpu_is_ti814x +# undef soc_is_am35xx +# define cpu_is_omap3430() is_omap3430() +# undef cpu_is_omap3630 +# define cpu_is_omap3630() is_omap363x() +# define cpu_is_ti81xx() is_ti81xx() +# define cpu_is_ti816x() is_ti816x() +# define cpu_is_ti814x() is_ti814x() +# define soc_is_am35xx() is_am35xx() +#endif + +# if defined(CONFIG_SOC_AM33XX) +# undef soc_is_am33xx +# undef soc_is_am335x +# define soc_is_am33xx() is_am33xx() +# define soc_is_am335x() is_am335x() +#endif + +# if defined(CONFIG_ARCH_OMAP4) +# undef cpu_is_omap44xx +# undef cpu_is_omap443x +# undef cpu_is_omap446x +# undef cpu_is_omap447x +# define cpu_is_omap44xx() is_omap44xx() +# define cpu_is_omap443x() is_omap443x() +# define cpu_is_omap446x() is_omap446x() +# define cpu_is_omap447x() is_omap447x() +# endif + +# if defined(CONFIG_SOC_OMAP5) +# undef soc_is_omap54xx +# undef soc_is_omap543x +# define soc_is_omap54xx() is_omap54xx() +# define soc_is_omap543x() is_omap543x() +#endif + +/* Various silicon revisions for omap2 */ +#define OMAP242X_CLASS 0x24200024 +#define OMAP2420_REV_ES1_0 OMAP242X_CLASS +#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (0x1 << 8)) + +#define OMAP243X_CLASS 0x24300024 +#define OMAP2430_REV_ES1_0 OMAP243X_CLASS + +#define OMAP343X_CLASS 0x34300034 +#define OMAP3430_REV_ES1_0 OMAP343X_CLASS +#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (0x1 << 8)) +#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (0x2 << 8)) +#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (0x3 << 8)) +#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (0x4 << 8)) +#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (0x5 << 8)) + +#define OMAP363X_CLASS 0x36300034 +#define OMAP3630_REV_ES1_0 OMAP363X_CLASS +#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (0x1 << 8)) +#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (0x2 << 8)) + +#define TI816X_CLASS 0x81600034 +#define TI8168_REV_ES1_0 TI816X_CLASS +#define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8)) + +#define TI814X_CLASS 0x81400034 +#define TI8148_REV_ES1_0 TI814X_CLASS +#define TI8148_REV_ES2_0 (TI814X_CLASS | (0x1 << 8)) +#define TI8148_REV_ES2_1 (TI814X_CLASS | (0x2 << 8)) + +#define AM35XX_CLASS 0x35170034 +#define AM35XX_REV_ES1_0 AM35XX_CLASS +#define AM35XX_REV_ES1_1 (AM35XX_CLASS | (0x1 << 8)) + +#define AM335X_CLASS 0x33500033 +#define AM335X_REV_ES1_0 AM335X_CLASS + +#define OMAP443X_CLASS 0x44300044 +#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8)) +#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8)) +#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8)) +#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8)) +#define OMAP4430_REV_ES2_3 (OMAP443X_CLASS | (0x23 << 8)) + +#define OMAP446X_CLASS 0x44600044 +#define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8)) +#define OMAP4460_REV_ES1_1 (OMAP446X_CLASS | (0x11 << 8)) + +#define OMAP447X_CLASS 0x44700044 +#define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8)) + +#define OMAP54XX_CLASS 0x54000054 +#define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8)) +#define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8)) + +void omap2xxx_check_revision(void); +void omap3xxx_check_revision(void); +void omap4xxx_check_revision(void); +void omap5xxx_check_revision(void); +void omap3xxx_check_features(void); +void ti81xx_check_features(void); +void omap4xxx_check_features(void); + +/* + * Runtime detection of OMAP3 features + * + * OMAP3_HAS_IO_CHAIN_CTRL: Some later members of the OMAP3 chip + * family have OS-level control over the I/O chain clock. This is + * to avoid a window during which wakeups could potentially be lost + * during powerdomain transitions. If this bit is set, it + * indicates that the chip does support OS-level control of this + * feature. + */ +extern u32 omap_features; + +#define OMAP3_HAS_L2CACHE BIT(0) +#define OMAP3_HAS_IVA BIT(1) +#define OMAP3_HAS_SGX BIT(2) +#define OMAP3_HAS_NEON BIT(3) +#define OMAP3_HAS_ISP BIT(4) +#define OMAP3_HAS_192MHZ_CLK BIT(5) +#define OMAP3_HAS_IO_WAKEUP BIT(6) +#define OMAP3_HAS_SDRC BIT(7) +#define OMAP3_HAS_IO_CHAIN_CTRL BIT(8) +#define OMAP4_HAS_MPU_1GHZ BIT(9) +#define OMAP4_HAS_MPU_1_2GHZ BIT(10) +#define OMAP4_HAS_MPU_1_5GHZ BIT(11) + + +#define OMAP3_HAS_FEATURE(feat,flag) \ +static inline unsigned int omap3_has_ ##feat(void) \ +{ \ + return omap_features & OMAP3_HAS_ ##flag; \ +} \ + +OMAP3_HAS_FEATURE(l2cache, L2CACHE) +OMAP3_HAS_FEATURE(sgx, SGX) +OMAP3_HAS_FEATURE(iva, IVA) +OMAP3_HAS_FEATURE(neon, NEON) +OMAP3_HAS_FEATURE(isp, ISP) +OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) +OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP) +OMAP3_HAS_FEATURE(sdrc, SDRC) +OMAP3_HAS_FEATURE(io_chain_ctrl, IO_CHAIN_CTRL) + +/* + * Runtime detection of OMAP4 features + */ +#define OMAP4_HAS_FEATURE(feat, flag) \ +static inline unsigned int omap4_has_ ##feat(void) \ +{ \ + return omap_features & OMAP4_HAS_ ##flag; \ +} \ + +OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ) +OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ) +OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ) + +#endif /* __ASSEMBLY__ */ + diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c index a04bc25a1d26..b9753fe27232 100644 --- a/arch/arm/mach-omap2/sr_device.c +++ b/arch/arm/mach-omap2/sr_device.c @@ -23,8 +23,8 @@ #include <linux/slab.h> #include <linux/io.h> -#include <plat/omap_device.h> - +#include "soc.h" +#include "omap_device.h" #include "voltage.h" #include "control.h" #include "pm.h" diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S index 8f7326cd435b..680a7c56cc3e 100644 --- a/arch/arm/mach-omap2/sram242x.S +++ b/arch/arm/mach-omap2/sram242x.S @@ -34,8 +34,8 @@ #include "soc.h" #include "iomap.h" -#include "prm2xxx_3xxx.h" -#include "cm2xxx_3xxx.h" +#include "prm2xxx.h" +#include "cm2xxx.h" #include "sdrc.h" .text diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S index b140d6578529..a1e9edd673f4 100644 --- a/arch/arm/mach-omap2/sram243x.S +++ b/arch/arm/mach-omap2/sram243x.S @@ -34,8 +34,8 @@ #include "soc.h" #include "iomap.h" -#include "prm2xxx_3xxx.h" -#include "cm2xxx_3xxx.h" +#include "prm2xxx.h" +#include "cm2xxx.h" #include "sdrc.h" .text diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 2d0ceaa23fb8..1446331b576a 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -32,7 +32,7 @@ #include "soc.h" #include "iomap.h" #include "sdrc.h" -#include "cm2xxx_3xxx.h" +#include "cm3xxx.h" /* * This file needs be built unconditionally as ARM to interoperate correctly diff --git a/arch/arm/mach-omap2/ti81xx.h b/arch/arm/mach-omap2/ti81xx.h index 8f9843f78422..a1e6caf0dba6 100644 --- a/arch/arm/mach-omap2/ti81xx.h +++ b/arch/arm/mach-omap2/ti81xx.h @@ -22,6 +22,15 @@ #define TI81XX_CTRL_BASE TI81XX_SCM_BASE #define TI81XX_PRCM_BASE 0x48180000 +/* + * Adjust TAP register base such that omap3_check_revision accesses the correct + * TI81XX register for checking device ID (it adds 0x204 to tap base while + * TI81XX DEVICE ID register is at offset 0x600 from control base). + */ +#define TI81XX_TAP_BASE (TI81XX_CTRL_BASE + \ + TI81XX_CONTROL_DEVICE_ID - 0x204) + + #define TI81XX_ARM_INTC_BASE 0x48200000 #endif /* __ASM_ARCH_TI81XX_H */ diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 69e46631a7cd..565e5755c9bc 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -43,10 +43,10 @@ #include <asm/sched_clock.h> #include <asm/arch_timer.h> -#include <plat/omap_hwmod.h> -#include <plat/omap_device.h> +#include "omap_hwmod.h" +#include "omap_device.h" #include <plat/dmtimer.h> -#include <plat/omap-pm.h> +#include "omap-pm.h" #include "soc.h" #include "common.h" diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c index 44c42057b61c..3fa2bdb44106 100644 --- a/arch/arm/mach-omap2/twl-common.c +++ b/arch/arm/mach-omap2/twl-common.c @@ -26,9 +26,6 @@ #include <linux/regulator/machine.h> #include <linux/regulator/fixed.h> -#include <plat/i2c.h> -#include <plat/usb.h> - #include "soc.h" #include "twl-common.h" #include "pm.h" diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c index 3c434498e12e..d1dbe125b34f 100644 --- a/arch/arm/mach-omap2/usb-host.c +++ b/arch/arm/mach-omap2/usb-host.c @@ -25,10 +25,10 @@ #include <asm/io.h> -#include <plat/usb.h> -#include <plat/omap_device.h> - +#include "soc.h" +#include "omap_device.h" #include "mux.h" +#include "usb.h" #ifdef CONFIG_MFD_OMAP_USB_HOST diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 51da21cb78f1..7b33b375fe77 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -25,12 +25,10 @@ #include <linux/io.h> #include <linux/usb/musb.h> -#include <plat/usb.h> -#include <plat/omap_device.h> - -#include "am35xx.h" - +#include "omap_device.h" +#include "soc.h" #include "mux.h" +#include "usb.h" static struct musb_hdrc_config musb_config = { .multipoint = 1, diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c index 805bea6edf17..a8795ff19e6d 100644 --- a/arch/arm/mach-omap2/usb-tusb6010.c +++ b/arch/arm/mach-omap2/usb-tusb6010.c @@ -15,10 +15,11 @@ #include <linux/platform_device.h> #include <linux/gpio.h> #include <linux/export.h> +#include <linux/platform_data/usb-omap.h> #include <linux/usb/musb.h> -#include <plat/gpmc.h> +#include "gpmc.h" #include "mux.h" diff --git a/arch/arm/mach-omap2/usb.h b/arch/arm/mach-omap2/usb.h new file mode 100644 index 000000000000..9b986ead7c45 --- /dev/null +++ b/arch/arm/mach-omap2/usb.h @@ -0,0 +1,82 @@ +#include <linux/platform_data/usb-omap.h> + +/* AM35x */ +/* USB 2.0 PHY Control */ +#define CONF2_PHY_GPIOMODE (1 << 23) +#define CONF2_OTGMODE (3 << 14) +#define CONF2_NO_OVERRIDE (0 << 14) +#define CONF2_FORCE_HOST (1 << 14) +#define CONF2_FORCE_DEVICE (2 << 14) +#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14) +#define CONF2_SESENDEN (1 << 13) +#define CONF2_VBDTCTEN (1 << 12) +#define CONF2_REFFREQ_24MHZ (2 << 8) +#define CONF2_REFFREQ_26MHZ (7 << 8) +#define CONF2_REFFREQ_13MHZ (6 << 8) +#define CONF2_REFFREQ (0xf << 8) +#define CONF2_PHYCLKGD (1 << 7) +#define CONF2_VBUSSENSE (1 << 6) +#define CONF2_PHY_PLLON (1 << 5) +#define CONF2_RESET (1 << 4) +#define CONF2_PHYPWRDN (1 << 3) +#define CONF2_OTGPWRDN (1 << 2) +#define CONF2_DATPOL (1 << 1) + +/* TI81XX specific definitions */ +#define USBCTRL0 0x620 +#define USBSTAT0 0x624 + +/* TI816X PHY controls bits */ +#define TI816X_USBPHY0_NORMAL_MODE (1 << 0) +#define TI816X_USBPHY_REFCLK_OSC (1 << 8) + +/* TI814X PHY controls bits */ +#define USBPHY_CM_PWRDN (1 << 0) +#define USBPHY_OTG_PWRDN (1 << 1) +#define USBPHY_CHGDET_DIS (1 << 2) +#define USBPHY_CHGDET_RSTRT (1 << 3) +#define USBPHY_SRCONDM (1 << 4) +#define USBPHY_SINKONDP (1 << 5) +#define USBPHY_CHGISINK_EN (1 << 6) +#define USBPHY_CHGVSRC_EN (1 << 7) +#define USBPHY_DMPULLUP (1 << 8) +#define USBPHY_DPPULLUP (1 << 9) +#define USBPHY_CDET_EXTCTL (1 << 10) +#define USBPHY_GPIO_MODE (1 << 12) +#define USBPHY_DPOPBUFCTL (1 << 13) +#define USBPHY_DMOPBUFCTL (1 << 14) +#define USBPHY_DPINPUT (1 << 15) +#define USBPHY_DMINPUT (1 << 16) +#define USBPHY_DPGPIO_PD (1 << 17) +#define USBPHY_DMGPIO_PD (1 << 18) +#define USBPHY_OTGVDET_EN (1 << 19) +#define USBPHY_OTGSESSEND_EN (1 << 20) +#define USBPHY_DATA_POLARITY (1 << 23) + +struct usbhs_omap_board_data { + enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; + + /* have to be valid if phy_reset is true and portx is in phy mode */ + int reset_gpio_port[OMAP3_HS_USB_PORTS]; + + /* Set this to true for ES2.x silicon */ + unsigned es2_compatibility:1; + + unsigned phy_reset:1; + + /* + * Regulators for USB PHYs. + * Each PHY can have a separate regulator. + */ + struct regulator *regulator[OMAP3_HS_USB_PORTS]; +}; + +extern void usb_musb_init(struct omap_musb_board_data *board_data); +extern void usbhs_init(const struct usbhs_omap_board_data *pdata); + +extern void am35x_musb_reset(void); +extern void am35x_musb_phy_power(u8 on); +extern void am35x_musb_clear_irq(void); +extern void am35x_set_mode(u8 musb_mode); +extern void ti81xx_musb_phy_power(u8 on); + diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c index b893c8e6f88f..48b22a0a0c88 100644 --- a/arch/arm/mach-omap2/voltagedomains44xx_data.c +++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c @@ -22,7 +22,7 @@ #include <linux/init.h> #include "common.h" - +#include "soc.h" #include "prm-regbits-44xx.h" #include "prm44xx.h" #include "prcm44xx.h" diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c index b2f1c67043a2..7c2b4ed38f02 100644 --- a/arch/arm/mach-omap2/wd_timer.c +++ b/arch/arm/mach-omap2/wd_timer.c @@ -1,6 +1,8 @@ /* * OMAP2+ MPU WD_TIMER-specific code * + * Copyright (C) 2012 Texas Instruments, Inc. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -11,10 +13,14 @@ #include <linux/io.h> #include <linux/err.h> -#include <plat/omap_hwmod.h> +#include <linux/platform_data/omap-wd-timer.h> +#include "omap_hwmod.h" +#include "omap_device.h" #include "wd_timer.h" #include "common.h" +#include "prm.h" +#include "soc.h" /* * In order to avoid any assumptions from bootloader regarding WDT @@ -26,9 +32,6 @@ #define OMAP_WDT_WPS 0x34 #define OMAP_WDT_SPR 0x48 -/* Maximum microseconds to wait for OMAP module to softreset */ -#define MAX_MODULE_SOFTRESET_WAIT 10000 - int omap2_wd_timer_disable(struct omap_hwmod *oh) { void __iomem *base; @@ -99,3 +102,32 @@ int omap2_wd_timer_reset(struct omap_hwmod *oh) return (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : omap2_wd_timer_disable(oh); } + +static int __init omap_init_wdt(void) +{ + int id = -1; + struct platform_device *pdev; + struct omap_hwmod *oh; + char *oh_name = "wd_timer2"; + char *dev_name = "omap_wdt"; + struct omap_wd_timer_platform_data pdata; + + if (!cpu_class_is_omap2() || of_have_populated_dt()) + return 0; + + oh = omap_hwmod_lookup(oh_name); + if (!oh) { + pr_err("Could not look up wd_timer%d hwmod\n", id); + return -EINVAL; + } + + pdata.read_reset_sources = prm_read_reset_sources; + + pdev = omap_device_build(dev_name, id, oh, &pdata, + sizeof(struct omap_wd_timer_platform_data), + NULL, 0, 0); + WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n", + dev_name, oh->name); + return 0; +} +subsys_initcall(omap_init_wdt); diff --git a/arch/arm/mach-omap2/wd_timer.h b/arch/arm/mach-omap2/wd_timer.h index f6bbba73b535..a78f81034a9f 100644 --- a/arch/arm/mach-omap2/wd_timer.h +++ b/arch/arm/mach-omap2/wd_timer.h @@ -10,7 +10,7 @@ #ifndef __ARCH_ARM_MACH_OMAP2_WD_TIMER_H #define __ARCH_ARM_MACH_OMAP2_WD_TIMER_H -#include <plat/omap_hwmod.h> +#include "omap_hwmod.h" extern int omap2_wd_timer_disable(struct omap_hwmod *oh); extern int omap2_wd_timer_reset(struct omap_hwmod *oh); diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index dacaee009a4e..4bd0ace20e98 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -3,13 +3,12 @@ # # Common support -obj-y := common.o sram.o clock.o dma.o fb.o counter_32k.o +obj-y := common.o sram.o dma.o fb.o counter_32k.o obj-m := obj-n := obj- := # omap_device support (OMAP2+ only at the moment) -obj-$(CONFIG_ARCH_OMAP2PLUS) += omap_device.o obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c deleted file mode 100644 index 9d7ac20ef8f9..000000000000 --- a/arch/arm/plat-omap/clock.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * linux/arch/arm/plat-omap/clock.c - * - * Copyright (C) 2004 - 2008 Nokia corporation - * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> - * - * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/list.h> -#include <linux/errno.h> -#include <linux/export.h> -#include <linux/err.h> -#include <linux/string.h> -#include <linux/clk.h> -#include <linux/mutex.h> -#include <linux/cpufreq.h> -#include <linux/io.h> - -#include <plat/clock.h> - -static LIST_HEAD(clocks); -static DEFINE_MUTEX(clocks_mutex); -static DEFINE_SPINLOCK(clockfw_lock); - -static struct clk_functions *arch_clock; - -/* - * Standard clock functions defined in include/linux/clk.h - */ - -int clk_enable(struct clk *clk) -{ - unsigned long flags; - int ret; - - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - if (!arch_clock || !arch_clock->clk_enable) - return -EINVAL; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = arch_clock->clk_enable(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - if (clk == NULL || IS_ERR(clk)) - return; - - if (!arch_clock || !arch_clock->clk_disable) - return; - - spin_lock_irqsave(&clockfw_lock, flags); - if (clk->usecount == 0) { - pr_err("Trying disable clock %s with 0 usecount\n", - clk->name); - WARN_ON(1); - goto out; - } - - arch_clock->clk_disable(clk); - -out: - spin_unlock_irqrestore(&clockfw_lock, flags); -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - unsigned long flags; - unsigned long ret; - - if (clk == NULL || IS_ERR(clk)) - return 0; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = clk->rate; - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_get_rate); - -/* - * Optional clock functions defined in include/linux/clk.h - */ - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - unsigned long flags; - long ret; - - if (clk == NULL || IS_ERR(clk)) - return 0; - - if (!arch_clock || !arch_clock->clk_round_rate) - return 0; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = arch_clock->clk_round_rate(clk, rate); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long flags; - int ret = -EINVAL; - - if (clk == NULL || IS_ERR(clk)) - return ret; - - if (!arch_clock || !arch_clock->clk_set_rate) - return ret; - - spin_lock_irqsave(&clockfw_lock, flags); - ret = arch_clock->clk_set_rate(clk, rate); - if (ret == 0) - propagate_rate(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - unsigned long flags; - int ret = -EINVAL; - - if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent)) - return ret; - - if (!arch_clock || !arch_clock->clk_set_parent) - return ret; - - spin_lock_irqsave(&clockfw_lock, flags); - if (clk->usecount == 0) { - ret = arch_clock->clk_set_parent(clk, parent); - if (ret == 0) - propagate_rate(clk); - } else - ret = -EBUSY; - spin_unlock_irqrestore(&clockfw_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_set_parent); - -struct clk *clk_get_parent(struct clk *clk) -{ - return clk->parent; -} -EXPORT_SYMBOL(clk_get_parent); - -/* - * OMAP specific clock functions shared between omap1 and omap2 - */ - -int __initdata mpurate; - -/* - * By default we use the rate set by the bootloader. - * You can override this with mpurate= cmdline option. - */ -static int __init omap_clk_setup(char *str) -{ - get_option(&str, &mpurate); - - if (!mpurate) - return 1; - - if (mpurate < 1000) - mpurate *= 1000000; - - return 1; -} -__setup("mpurate=", omap_clk_setup); - -/* Used for clocks that always have same value as the parent clock */ -unsigned long followparent_recalc(struct clk *clk) -{ - return clk->parent->rate; -} - -/* - * Used for clocks that have the same value as the parent clock, - * divided by some factor - */ -unsigned long omap_fixed_divisor_recalc(struct clk *clk) -{ - WARN_ON(!clk->fixed_div); - - return clk->parent->rate / clk->fixed_div; -} - -void clk_reparent(struct clk *child, struct clk *parent) -{ - list_del_init(&child->sibling); - if (parent) - list_add(&child->sibling, &parent->children); - child->parent = parent; - - /* now do the debugfs renaming to reattach the child - to the proper parent */ -} - -/* Propagate rate to children */ -void propagate_rate(struct clk *tclk) -{ - struct clk *clkp; - - list_for_each_entry(clkp, &tclk->children, sibling) { - if (clkp->recalc) - clkp->rate = clkp->recalc(clkp); - propagate_rate(clkp); - } -} - -static LIST_HEAD(root_clks); - -/** - * recalculate_root_clocks - recalculate and propagate all root clocks - * - * Recalculates all root clocks (clocks with no parent), which if the - * clock's .recalc is set correctly, should also propagate their rates. - * Called at init. - */ -void recalculate_root_clocks(void) -{ - struct clk *clkp; - - list_for_each_entry(clkp, &root_clks, sibling) { - if (clkp->recalc) - clkp->rate = clkp->recalc(clkp); - propagate_rate(clkp); - } -} - -/** - * clk_preinit - initialize any fields in the struct clk before clk init - * @clk: struct clk * to initialize - * - * Initialize any struct clk fields needed before normal clk initialization - * can run. No return value. - */ -void clk_preinit(struct clk *clk) -{ - INIT_LIST_HEAD(&clk->children); -} - -int clk_register(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - /* - * trap out already registered clocks - */ - if (clk->node.next || clk->node.prev) - return 0; - - mutex_lock(&clocks_mutex); - if (clk->parent) - list_add(&clk->sibling, &clk->parent->children); - else - list_add(&clk->sibling, &root_clks); - - list_add(&clk->node, &clocks); - if (clk->init) - clk->init(clk); - mutex_unlock(&clocks_mutex); - - return 0; -} -EXPORT_SYMBOL(clk_register); - -void clk_unregister(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return; - - mutex_lock(&clocks_mutex); - list_del(&clk->sibling); - list_del(&clk->node); - mutex_unlock(&clocks_mutex); -} -EXPORT_SYMBOL(clk_unregister); - -void clk_enable_init_clocks(void) -{ - struct clk *clkp; - - list_for_each_entry(clkp, &clocks, node) { - if (clkp->flags & ENABLE_ON_INIT) - clk_enable(clkp); - } -} - -int omap_clk_enable_autoidle_all(void) -{ - struct clk *c; - unsigned long flags; - - spin_lock_irqsave(&clockfw_lock, flags); - - list_for_each_entry(c, &clocks, node) - if (c->ops->allow_idle) - c->ops->allow_idle(c); - - spin_unlock_irqrestore(&clockfw_lock, flags); - - return 0; -} - -int omap_clk_disable_autoidle_all(void) -{ - struct clk *c; - unsigned long flags; - - spin_lock_irqsave(&clockfw_lock, flags); - - list_for_each_entry(c, &clocks, node) - if (c->ops->deny_idle) - c->ops->deny_idle(c); - - spin_unlock_irqrestore(&clockfw_lock, flags); - - return 0; -} - -/* - * Low level helpers - */ -static int clkll_enable_null(struct clk *clk) -{ - return 0; -} - -static void clkll_disable_null(struct clk *clk) -{ -} - -const struct clkops clkops_null = { - .enable = clkll_enable_null, - .disable = clkll_disable_null, -}; - -/* - * Dummy clock - * - * Used for clock aliases that are needed on some OMAPs, but not others - */ -struct clk dummy_ck = { - .name = "dummy", - .ops = &clkops_null, -}; - -/* - * - */ - -#ifdef CONFIG_OMAP_RESET_CLOCKS -/* - * Disable any unused clocks left on by the bootloader - */ -static int __init clk_disable_unused(void) -{ - struct clk *ck; - unsigned long flags; - - if (!arch_clock || !arch_clock->clk_disable_unused) - return 0; - - pr_info("clock: disabling unused clocks to save power\n"); - - spin_lock_irqsave(&clockfw_lock, flags); - list_for_each_entry(ck, &clocks, node) { - if (ck->ops == &clkops_null) - continue; - - if (ck->usecount > 0 || !ck->enable_reg) - continue; - - arch_clock->clk_disable_unused(ck); - } - spin_unlock_irqrestore(&clockfw_lock, flags); - - return 0; -} -late_initcall(clk_disable_unused); -late_initcall(omap_clk_enable_autoidle_all); -#endif - -int __init clk_init(struct clk_functions * custom_clocks) -{ - if (!custom_clocks) { - pr_err("No custom clock functions registered\n"); - BUG(); - } - - arch_clock = custom_clocks; - - return 0; -} - -#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) -/* - * debugfs support to trace clock tree hierarchy and attributes - */ - -#include <linux/debugfs.h> -#include <linux/seq_file.h> - -static struct dentry *clk_debugfs_root; - -static int clk_dbg_show_summary(struct seq_file *s, void *unused) -{ - struct clk *c; - struct clk *pa; - - mutex_lock(&clocks_mutex); - seq_printf(s, "%-30s %-30s %-10s %s\n", - "clock-name", "parent-name", "rate", "use-count"); - - list_for_each_entry(c, &clocks, node) { - pa = c->parent; - seq_printf(s, "%-30s %-30s %-10lu %d\n", - c->name, pa ? pa->name : "none", c->rate, c->usecount); - } - mutex_unlock(&clocks_mutex); - - return 0; -} - -static int clk_dbg_open(struct inode *inode, struct file *file) -{ - return single_open(file, clk_dbg_show_summary, inode->i_private); -} - -static const struct file_operations debug_clock_fops = { - .open = clk_dbg_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int clk_debugfs_register_one(struct clk *c) -{ - int err; - struct dentry *d; - struct clk *pa = c->parent; - - d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root); - if (!d) - return -ENOMEM; - c->dent = d; - - d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount); - if (!d) { - err = -ENOMEM; - goto err_out; - } - d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate); - if (!d) { - err = -ENOMEM; - goto err_out; - } - d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags); - if (!d) { - err = -ENOMEM; - goto err_out; - } - return 0; - -err_out: - debugfs_remove_recursive(c->dent); - return err; -} - -static int clk_debugfs_register(struct clk *c) -{ - int err; - struct clk *pa = c->parent; - - if (pa && !pa->dent) { - err = clk_debugfs_register(pa); - if (err) - return err; - } - - if (!c->dent) { - err = clk_debugfs_register_one(c); - if (err) - return err; - } - return 0; -} - -static int __init clk_debugfs_init(void) -{ - struct clk *c; - struct dentry *d; - int err; - - d = debugfs_create_dir("clock", NULL); - if (!d) - return -ENOMEM; - clk_debugfs_root = d; - - list_for_each_entry(c, &clocks, node) { - err = clk_debugfs_register(c); - if (err) - goto err_out; - } - - d = debugfs_create_file("summary", S_IRUGO, - d, NULL, &debug_clock_fops); - if (!d) - return -ENOMEM; - - return 0; -err_out: - debugfs_remove_recursive(clk_debugfs_root); - return err; -} -late_initcall(clk_debugfs_init); - -#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */ diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 111315a69354..a1555e028123 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -16,20 +16,8 @@ #include <linux/io.h> #include <linux/dma-mapping.h> -#include <plat/common.h> -#include <plat/vram.h> -#include <linux/platform_data/dsp-omap.h> -#include <plat/dma.h> - -#include <plat/omap-secure.h> - -void __init omap_reserve(void) -{ - omap_vram_reserve_sdram_memblock(); - omap_dsp_reserve_sdram_memblock(); - omap_secure_ram_reserve_memblock(); - omap_barrier_reserve_memblock(); -} +#include "common.h" +#include <plat-omap/dma-omap.h> void __init omap_init_consistent_dma_size(void) { @@ -37,12 +25,3 @@ void __init omap_init_consistent_dma_size(void) init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20); #endif } - -/* - * Stub function for OMAP2 so that common files - * continue to build when custom builds are used - */ -int __weak omap_secure_ram_reserve_memblock(void) -{ - return 0; -} diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/common.h index d1cb6f527b7e..8ae0542a37d9 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/common.h @@ -1,7 +1,5 @@ /* - * arch/arm/plat-omap/include/mach/common.h - * - * Header for code common to all OMAP machines. + * Header for shared OMAP code in plat-omap. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -27,16 +25,12 @@ #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H #define __ARCH_ARM_MACH_OMAP_COMMON_H -#include <plat/i2c.h> -#include <plat/omap_hwmod.h> - extern int __init omap_init_clocksource_32k(void __iomem *vbase); extern void __init omap_check_revision(void); extern void omap_reserve(void); +struct omap_hwmod; extern int omap_dss_reset(struct omap_hwmod *); -void omap_sram_init(void); - #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c index 87ba8dd0d791..66bf3f9324fe 100644 --- a/arch/arm/plat-omap/counter_32k.c +++ b/arch/arm/plat-omap/counter_32k.c @@ -22,8 +22,7 @@ #include <asm/mach/time.h> #include <asm/sched_clock.h> -#include <plat/common.h> -#include <plat/clock.h> +#include "common.h" /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */ #define OMAP2_32KSYNCNT_REV_OFF 0x0 diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c index ea29bbe8e5cf..feca128bc8ed 100644 --- a/arch/arm/plat-omap/debug-leds.c +++ b/arch/arm/plat-omap/debug-leds.c @@ -20,7 +20,7 @@ #include <mach/hardware.h> #include <asm/mach-types.h> -#include <plat/fpga.h> +#include "fpga.h" /* Many OMAP development platforms reuse the same "debug board"; these * platforms include H2, H3, H4, and Perseus2. There are 16 LEDs on the diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index c76ed8bff838..49803cc18787 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -36,9 +36,10 @@ #include <linux/slab.h> #include <linux/delay.h> -#include <plat/cpu.h> -#include <plat/dma.h> -#include <plat/tc.h> +#include <plat-omap/dma-omap.h> + +#include "../mach-omap1/soc.h" +#include "../mach-omap2/soc.h" /* * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA @@ -175,6 +176,7 @@ static inline void set_gdma_dev(int req, int dev) #define omap_writel(val, reg) do {} while (0) #endif +#ifdef CONFIG_ARCH_OMAP1 void omap_set_dma_priority(int lch, int dst_port, int priority) { unsigned long reg; @@ -203,18 +205,22 @@ void omap_set_dma_priority(int lch, int dst_port, int priority) l |= (priority & 0xf) << 8; omap_writel(l, reg); } +} +#endif - if (cpu_class_is_omap2()) { - u32 ccr; +#ifdef CONFIG_ARCH_OMAP2PLUS +void omap_set_dma_priority(int lch, int dst_port, int priority) +{ + u32 ccr; - ccr = p->dma_read(CCR, lch); - if (priority) - ccr |= (1 << 6); - else - ccr &= ~(1 << 6); - p->dma_write(ccr, CCR, lch); - } + ccr = p->dma_read(CCR, lch); + if (priority) + ccr |= (1 << 6); + else + ccr &= ~(1 << 6); + p->dma_write(ccr, CCR, lch); } +#endif EXPORT_SYMBOL(omap_set_dma_priority); void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 938b50a33439..4a0b30a4ebda 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -42,10 +42,11 @@ #include <linux/pm_runtime.h> #include <plat/dmtimer.h> -#include <plat/omap-pm.h> #include <mach/hardware.h> +#include "../mach-omap2/omap-pm.h" + static u32 omap_reserved_systimers; static LIST_HEAD(omap_timer_list); static DEFINE_SPINLOCK(dm_timer_lock); diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c index bcbb9d5dc293..f868caeedfd6 100644 --- a/arch/arm/plat-omap/fb.c +++ b/arch/arm/plat-omap/fb.c @@ -33,6 +33,67 @@ #include <mach/hardware.h> #include <asm/mach/map.h> +#include <plat/cpu.h> + +#ifdef CONFIG_OMAP2_VRFB + +/* + * The first memory resource is the register region for VRFB, + * the rest are VRFB virtual memory areas for each VRFB context. + */ + +static const struct resource omap2_vrfb_resources[] = { + DEFINE_RES_MEM_NAMED(0x68008000u, 0x40, "vrfb-regs"), + DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"), + DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"), + DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"), + DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"), +}; + +static const struct resource omap3_vrfb_resources[] = { + DEFINE_RES_MEM_NAMED(0x6C000180u, 0xc0, "vrfb-regs"), + DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"), + DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"), + DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"), + DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"), + DEFINE_RES_MEM_NAMED(0xe0000000u, 0x4000000, "vrfb-area-4"), + DEFINE_RES_MEM_NAMED(0xe4000000u, 0x4000000, "vrfb-area-5"), + DEFINE_RES_MEM_NAMED(0xe8000000u, 0x4000000, "vrfb-area-6"), + DEFINE_RES_MEM_NAMED(0xec000000u, 0x4000000, "vrfb-area-7"), + DEFINE_RES_MEM_NAMED(0xf0000000u, 0x4000000, "vrfb-area-8"), + DEFINE_RES_MEM_NAMED(0xf4000000u, 0x4000000, "vrfb-area-9"), + DEFINE_RES_MEM_NAMED(0xf8000000u, 0x4000000, "vrfb-area-10"), + DEFINE_RES_MEM_NAMED(0xfc000000u, 0x4000000, "vrfb-area-11"), +}; + +static int __init omap_init_vrfb(void) +{ + struct platform_device *pdev; + const struct resource *res; + unsigned int num_res; + + if (cpu_is_omap24xx()) { + res = omap2_vrfb_resources; + num_res = ARRAY_SIZE(omap2_vrfb_resources); + } else if (cpu_is_omap34xx()) { + res = omap3_vrfb_resources; + num_res = ARRAY_SIZE(omap3_vrfb_resources); + } else { + return 0; + } + + pdev = platform_device_register_resndata(NULL, "omapvrfb", -1, + res, num_res, NULL, 0); + + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + else + return 0; +} + +arch_initcall(omap_init_vrfb); +#endif + #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE) static bool omapfb_lcd_configured; diff --git a/arch/arm/plat-omap/fpga.h b/arch/arm/plat-omap/fpga.h new file mode 100644 index 000000000000..54faaa93e6f4 --- /dev/null +++ b/arch/arm/plat-omap/fpga.h @@ -0,0 +1,74 @@ +/* + * arch/arm/plat-omap/include/mach/fpga.h + * + * Interrupt handler for OMAP-1510 FPGA + * + * Copyright (C) 2001 RidgeRun, Inc. + * Author: Greg Lonnon <glonnon@ridgerun.com> + * + * Copyright (C) 2002 MontaVista Software, Inc. + * + * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 + * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_OMAP_FPGA_H +#define __ASM_ARCH_OMAP_FPGA_H + +/* + * --------------------------------------------------------------------------- + * H2/P2 Debug board FPGA + * --------------------------------------------------------------------------- + */ +/* maps in the FPGA registers and the ETHR registers */ +#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */ +#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ +#define H2P2_DBG_FPGA_START 0x04000000 /* PA */ + +#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300) +#define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ +#define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */ +#define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */ +#define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */ +#define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */ +#define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */ +#define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */ + +/* NOTE: most boards don't have a static mapping for the FPGA ... */ +struct h2p2_dbg_fpga { + /* offset 0x00 */ + u16 smc91x[8]; + /* offset 0x10 */ + u16 fpga_rev; + u16 board_rev; + u16 gpio_outputs; + u16 leds; + /* offset 0x18 */ + u16 misc_inputs; + u16 lan_status; + u16 lan_reset; + u16 reserved0; + /* offset 0x20 */ + u16 ps2_data; + u16 ps2_ctrl; + /* plus also 4 rs232 ports ... */ +}; + +/* LEDs definition on debug board (16 LEDs, all physically green) */ +#define H2P2_DBG_FPGA_LED_GREEN (1 << 15) +#define H2P2_DBG_FPGA_LED_AMBER (1 << 14) +#define H2P2_DBG_FPGA_LED_RED (1 << 13) +#define H2P2_DBG_FPGA_LED_BLUE (1 << 12) +/* cpu0 load-meter LEDs */ +#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ... +#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11 +#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1) + +#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0) +#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1) + +#endif diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index a5683a84c6ee..be6deb7c12ec 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c @@ -26,52 +26,20 @@ #include <linux/kernel.h> #include <linux/platform_device.h> #include <linux/i2c.h> +#include <linux/i2c-omap.h> #include <linux/slab.h> #include <linux/err.h> #include <linux/clk.h> #include <mach/irqs.h> -#include <plat/i2c.h> -#include <plat/omap_device.h> -#define OMAP_I2C_SIZE 0x3f -#define OMAP1_I2C_BASE 0xfffb3800 -#define OMAP1_INT_I2C (32 + 4) +#include "../mach-omap1/soc.h" +#include "../mach-omap2/soc.h" -static const char name[] = "omap_i2c"; +#include "i2c.h" -#define I2C_RESOURCE_BUILDER(base, irq) \ - { \ - .start = (base), \ - .end = (base) + OMAP_I2C_SIZE, \ - .flags = IORESOURCE_MEM, \ - }, \ - { \ - .start = (irq), \ - .flags = IORESOURCE_IRQ, \ - }, - -static struct resource i2c_resources[][2] = { - { I2C_RESOURCE_BUILDER(0, 0) }, -}; - -#define I2C_DEV_BUILDER(bus_id, res, data) \ - { \ - .id = (bus_id), \ - .name = name, \ - .num_resources = ARRAY_SIZE(res), \ - .resource = (res), \ - .dev = { \ - .platform_data = (data), \ - }, \ - } - -#define MAX_OMAP_I2C_HWMOD_NAME_LEN 16 #define OMAP_I2C_MAX_CONTROLLERS 4 static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS]; -static struct platform_device omap_i2c_devices[] = { - I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]), -}; #define OMAP_I2C_CMDLINE_SETUP (BIT(31)) @@ -91,95 +59,6 @@ static int __init omap_i2c_nr_ports(void) return ports; } -static inline int omap1_i2c_add_bus(int bus_id) -{ - struct platform_device *pdev; - struct omap_i2c_bus_platform_data *pdata; - struct resource *res; - - omap1_i2c_mux_pins(bus_id); - - pdev = &omap_i2c_devices[bus_id - 1]; - res = pdev->resource; - res[0].start = OMAP1_I2C_BASE; - res[0].end = res[0].start + OMAP_I2C_SIZE; - res[1].start = OMAP1_INT_I2C; - pdata = &i2c_pdata[bus_id - 1]; - - /* all OMAP1 have IP version 1 register set */ - pdata->rev = OMAP_I2C_IP_VERSION_1; - - /* all OMAP1 I2C are implemented like this */ - pdata->flags = OMAP_I2C_FLAG_NO_FIFO | - OMAP_I2C_FLAG_SIMPLE_CLOCK | - OMAP_I2C_FLAG_16BIT_DATA_REG | - OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK; - - /* how the cpu bus is wired up differs for 7xx only */ - - if (cpu_is_omap7xx()) - pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_1; - else - pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_2; - - return platform_device_register(pdev); -} - - -#ifdef CONFIG_ARCH_OMAP2PLUS -static inline int omap2_i2c_add_bus(int bus_id) -{ - int l; - struct omap_hwmod *oh; - struct platform_device *pdev; - char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN]; - struct omap_i2c_bus_platform_data *pdata; - struct omap_i2c_dev_attr *dev_attr; - - omap2_i2c_mux_pins(bus_id); - - l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id); - WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN, - "String buffer overflow in I2C%d device setup\n", bus_id); - oh = omap_hwmod_lookup(oh_name); - if (!oh) { - pr_err("Could not look up %s\n", oh_name); - return -EEXIST; - } - - pdata = &i2c_pdata[bus_id - 1]; - /* - * pass the hwmod class's CPU-specific knowledge of I2C IP revision in - * use, and functionality implementation flags, up to the OMAP I2C - * driver via platform data - */ - pdata->rev = oh->class->rev; - - dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr; - pdata->flags = dev_attr->flags; - - pdev = omap_device_build(name, bus_id, oh, pdata, - sizeof(struct omap_i2c_bus_platform_data), - NULL, 0, 0); - WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name); - - return PTR_RET(pdev); -} -#else -static inline int omap2_i2c_add_bus(int bus_id) -{ - return 0; -} -#endif - -static int __init omap_i2c_add_bus(int bus_id) -{ - if (cpu_class_is_omap1()) - return omap1_i2c_add_bus(bus_id); - else - return omap2_i2c_add_bus(bus_id); -} - /** * omap_i2c_bus_setup - Process command line options for the I2C bus speed * @str: String of options @@ -218,7 +97,7 @@ static int __init omap_register_i2c_bus_cmdline(void) for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++) if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) { i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP; - err = omap_i2c_add_bus(i + 1); + err = omap_i2c_add_bus(&i2c_pdata[i], i + 1); if (err) goto out; } @@ -256,5 +135,5 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate, i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP; - return omap_i2c_add_bus(bus_id); + return omap_i2c_add_bus(&i2c_pdata[bus_id - 1], bus_id); } diff --git a/arch/arm/plat-omap/i2c.h b/arch/arm/plat-omap/i2c.h new file mode 100644 index 000000000000..7a9028cb5a75 --- /dev/null +++ b/arch/arm/plat-omap/i2c.h @@ -0,0 +1,47 @@ +/* + * Helper module for board specific I2C bus registration + * + * Copyright (C) 2009 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#ifndef __PLAT_OMAP_I2C_H +#define __PLAT_OMAP_I2C_H + +struct i2c_board_info; +struct omap_i2c_bus_platform_data; + +int omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata, + int bus_id); + +#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) +extern int omap_register_i2c_bus(int bus_id, u32 clkrate, + struct i2c_board_info const *info, + unsigned len); +#else +static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, + struct i2c_board_info const *info, + unsigned len) +{ + return 0; +} +#endif + +struct omap_hwmod; +int omap_i2c_reset(struct omap_hwmod *oh); + +#endif /* __PLAT_OMAP_I2C_H */ diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat-omap/dma-omap.h index 0a87b052f8f7..222be7e934e5 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat-omap/dma-omap.h @@ -1,5 +1,5 @@ /* - * arch/arm/plat-omap/include/mach/dma.h + * OMAP DMA handling defines and function * * Copyright (C) 2003 Nokia Corporation * Author: Juha Yrjölä <juha.yrjola@nokia.com> @@ -23,187 +23,8 @@ #include <linux/platform_device.h> -/* - * TODO: These dma channel defines should go away once all - * the omap drivers hwmod adapted. - */ - -/* Move omap4 specific defines to dma-44xx.h */ -#include "dma-44xx.h" - #define INT_DMA_LCD 25 -/* DMA channels for omap1 */ -#define OMAP_DMA_NO_DEVICE 0 -#define OMAP_DMA_MCSI1_TX 1 -#define OMAP_DMA_MCSI1_RX 2 -#define OMAP_DMA_I2C_RX 3 -#define OMAP_DMA_I2C_TX 4 -#define OMAP_DMA_EXT_NDMA_REQ 5 -#define OMAP_DMA_EXT_NDMA_REQ2 6 -#define OMAP_DMA_UWIRE_TX 7 -#define OMAP_DMA_MCBSP1_TX 8 -#define OMAP_DMA_MCBSP1_RX 9 -#define OMAP_DMA_MCBSP3_TX 10 -#define OMAP_DMA_MCBSP3_RX 11 -#define OMAP_DMA_UART1_TX 12 -#define OMAP_DMA_UART1_RX 13 -#define OMAP_DMA_UART2_TX 14 -#define OMAP_DMA_UART2_RX 15 -#define OMAP_DMA_MCBSP2_TX 16 -#define OMAP_DMA_MCBSP2_RX 17 -#define OMAP_DMA_UART3_TX 18 -#define OMAP_DMA_UART3_RX 19 -#define OMAP_DMA_CAMERA_IF_RX 20 -#define OMAP_DMA_MMC_TX 21 -#define OMAP_DMA_MMC_RX 22 -#define OMAP_DMA_NAND 23 -#define OMAP_DMA_IRQ_LCD_LINE 24 -#define OMAP_DMA_MEMORY_STICK 25 -#define OMAP_DMA_USB_W2FC_RX0 26 -#define OMAP_DMA_USB_W2FC_RX1 27 -#define OMAP_DMA_USB_W2FC_RX2 28 -#define OMAP_DMA_USB_W2FC_TX0 29 -#define OMAP_DMA_USB_W2FC_TX1 30 -#define OMAP_DMA_USB_W2FC_TX2 31 - -/* These are only for 1610 */ -#define OMAP_DMA_CRYPTO_DES_IN 32 -#define OMAP_DMA_SPI_TX 33 -#define OMAP_DMA_SPI_RX 34 -#define OMAP_DMA_CRYPTO_HASH 35 -#define OMAP_DMA_CCP_ATTN 36 -#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 -#define OMAP_DMA_CMT_APE_TX_CHAN_0 38 -#define OMAP_DMA_CMT_APE_RV_CHAN_0 39 -#define OMAP_DMA_CMT_APE_TX_CHAN_1 40 -#define OMAP_DMA_CMT_APE_RV_CHAN_1 41 -#define OMAP_DMA_CMT_APE_TX_CHAN_2 42 -#define OMAP_DMA_CMT_APE_RV_CHAN_2 43 -#define OMAP_DMA_CMT_APE_TX_CHAN_3 44 -#define OMAP_DMA_CMT_APE_RV_CHAN_3 45 -#define OMAP_DMA_CMT_APE_TX_CHAN_4 46 -#define OMAP_DMA_CMT_APE_RV_CHAN_4 47 -#define OMAP_DMA_CMT_APE_TX_CHAN_5 48 -#define OMAP_DMA_CMT_APE_RV_CHAN_5 49 -#define OMAP_DMA_CMT_APE_TX_CHAN_6 50 -#define OMAP_DMA_CMT_APE_RV_CHAN_6 51 -#define OMAP_DMA_CMT_APE_TX_CHAN_7 52 -#define OMAP_DMA_CMT_APE_RV_CHAN_7 53 -#define OMAP_DMA_MMC2_TX 54 -#define OMAP_DMA_MMC2_RX 55 -#define OMAP_DMA_CRYPTO_DES_OUT 56 - -/* DMA channels for 24xx */ -#define OMAP24XX_DMA_NO_DEVICE 0 -#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */ -#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */ -#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */ -#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ -#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */ -#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */ -#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */ -#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */ -#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */ -#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */ -#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */ -#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */ -#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */ -#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */ -#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */ -#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */ -#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */ -#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */ -#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */ -#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */ -#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ -#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */ -#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */ -#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */ -#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */ -#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */ -#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */ -#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */ -#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */ -#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */ -#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */ -#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */ -#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */ -#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */ -#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */ -#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */ -#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */ -#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */ -#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */ -#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */ -#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */ -#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */ -#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */ -#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */ -#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */ -#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */ -#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */ -#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */ -#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */ -#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */ -#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */ -#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */ -#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */ -#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */ -#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */ -#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */ -#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */ -#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */ -#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */ -#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */ -#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */ -#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */ -#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */ -#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */ -#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */ -#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */ -#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */ -#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */ -#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */ -#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */ -#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */ -#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */ -#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */ -#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */ -#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */ -#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */ -#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */ -#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */ -#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */ -#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */ -#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */ -#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */ -#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */ -#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */ -#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */ -#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */ -#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */ -#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */ -#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */ -#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */ -#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */ -#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */ -#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */ -#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */ -#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */ -#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */ -#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ -#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ - -#define OMAP36XX_DMA_UART4_TX 81 /* S_DMA_80 */ -#define OMAP36XX_DMA_UART4_RX 82 /* S_DMA_81 */ - -/* Only for AM35xx */ -#define AM35XX_DMA_UART4_TX 54 -#define AM35XX_DMA_UART4_RX 55 - -/*----------------------------------------------------------------------------*/ - #define OMAP1_DMA_TOUT_IRQ (1 << 0) #define OMAP_DMA_DROP_IRQ (1 << 1) #define OMAP_DMA_HALF_IRQ (1 << 2) diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h deleted file mode 100644 index 025d85a3ee86..000000000000 --- a/arch/arm/plat-omap/include/plat/clkdev_omap.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * clkdev <-> OMAP integration - * - * Russell King <linux@arm.linux.org.uk> - * - */ - -#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H -#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H - -#include <linux/clkdev.h> - -struct omap_clk { - u16 cpu; - struct clk_lookup lk; -}; - -#define CLK(dev, con, ck, cp) \ - { \ - .cpu = cp, \ - .lk = { \ - .dev_id = dev, \ - .con_id = con, \ - .clk = ck, \ - }, \ - } - -/* Platform flags for the clkdev-OMAP integration code */ -#define CK_310 (1 << 0) -#define CK_7XX (1 << 1) /* 7xx, 850 */ -#define CK_1510 (1 << 2) -#define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */ -#define CK_242X (1 << 4) -#define CK_243X (1 << 5) /* 243x, 253x */ -#define CK_3430ES1 (1 << 6) /* 34xxES1 only */ -#define CK_3430ES2PLUS (1 << 7) /* 34xxES2, ES3, non-Sitara 35xx only */ -#define CK_AM35XX (1 << 9) /* Sitara AM35xx */ -#define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */ -#define CK_443X (1 << 11) -#define CK_TI816X (1 << 12) -#define CK_446X (1 << 13) -#define CK_AM33XX (1 << 14) /* AM33xx specific clocks */ -#define CK_1710 (1 << 15) /* 1710 extra for rate selection */ - - -#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) -#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX) - - -#endif - diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h deleted file mode 100644 index e2e2d045e428..000000000000 --- a/arch/arm/plat-omap/include/plat/clock.h +++ /dev/null @@ -1,309 +0,0 @@ -/* - * OMAP clock: data structure definitions, function prototypes, shared macros - * - * Copyright (C) 2004-2005, 2008-2010 Nokia Corporation - * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> - * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_OMAP_CLOCK_H -#define __ARCH_ARM_OMAP_CLOCK_H - -#include <linux/list.h> - -struct module; -struct clk; -struct clockdomain; - -/* Temporary, needed during the common clock framework conversion */ -#define __clk_get_name(clk) (clk->name) -#define __clk_get_parent(clk) (clk->parent) -#define __clk_get_rate(clk) (clk->rate) - -/** - * struct clkops - some clock function pointers - * @enable: fn ptr that enables the current clock in hardware - * @disable: fn ptr that enables the current clock in hardware - * @find_idlest: function returning the IDLEST register for the clock's IP blk - * @find_companion: function returning the "companion" clk reg for the clock - * @allow_idle: fn ptr that enables autoidle for the current clock in hardware - * @deny_idle: fn ptr that disables autoidle for the current clock in hardware - * - * A "companion" clk is an accompanying clock to the one being queried - * that must be enabled for the IP module connected to the clock to - * become accessible by the hardware. Neither @find_idlest nor - * @find_companion should be needed; that information is IP - * block-specific; the hwmod code has been created to handle this, but - * until hwmod data is ready and drivers have been converted to use PM - * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and - * @find_companion must, unfortunately, remain. - */ -struct clkops { - int (*enable)(struct clk *); - void (*disable)(struct clk *); - void (*find_idlest)(struct clk *, void __iomem **, - u8 *, u8 *); - void (*find_companion)(struct clk *, void __iomem **, - u8 *); - void (*allow_idle)(struct clk *); - void (*deny_idle)(struct clk *); -}; - -#ifdef CONFIG_ARCH_OMAP2PLUS - -/* struct clksel_rate.flags possibilities */ -#define RATE_IN_242X (1 << 0) -#define RATE_IN_243X (1 << 1) -#define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */ -#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */ -#define RATE_IN_36XX (1 << 4) -#define RATE_IN_4430 (1 << 5) -#define RATE_IN_TI816X (1 << 6) -#define RATE_IN_4460 (1 << 7) -#define RATE_IN_AM33XX (1 << 8) -#define RATE_IN_TI814X (1 << 9) - -#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) -#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) -#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX) -#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460) - -/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */ -#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX) - - -/** - * struct clksel_rate - register bitfield values corresponding to clk divisors - * @val: register bitfield value (shifted to bit 0) - * @div: clock divisor corresponding to @val - * @flags: (see "struct clksel_rate.flags possibilities" above) - * - * @val should match the value of a read from struct clk.clksel_reg - * AND'ed with struct clk.clksel_mask, shifted right to bit 0. - * - * @div is the divisor that should be applied to the parent clock's rate - * to produce the current clock's rate. - */ -struct clksel_rate { - u32 val; - u8 div; - u16 flags; -}; - -/** - * struct clksel - available parent clocks, and a pointer to their divisors - * @parent: struct clk * to a possible parent clock - * @rates: available divisors for this parent clock - * - * A struct clksel is always associated with one or more struct clks - * and one or more struct clksel_rates. - */ -struct clksel { - struct clk *parent; - const struct clksel_rate *rates; -}; - -/** - * struct dpll_data - DPLL registers and integration data - * @mult_div1_reg: register containing the DPLL M and N bitfields - * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg - * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg - * @clk_bypass: struct clk pointer to the clock's bypass clock input - * @clk_ref: struct clk pointer to the clock's reference clock input - * @control_reg: register containing the DPLL mode bitfield - * @enable_mask: mask of the DPLL mode bitfield in @control_reg - * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() - * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() - * @max_multiplier: maximum valid non-bypass multiplier value (actual) - * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() - * @min_divider: minimum valid non-bypass divider value (actual) - * @max_divider: maximum valid non-bypass divider value (actual) - * @modes: possible values of @enable_mask - * @autoidle_reg: register containing the DPLL autoidle mode bitfield - * @idlest_reg: register containing the DPLL idle status bitfield - * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg - * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg - * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg - * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg - * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs - * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs - * @flags: DPLL type/features (see below) - * - * Possible values for @flags: - * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) - * - * @freqsel_mask is only used on the OMAP34xx family and AM35xx. - * - * XXX Some DPLLs have multiple bypass inputs, so it's not technically - * correct to only have one @clk_bypass pointer. - * - * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, - * @last_rounded_n) should be separated from the runtime-fixed fields - * and placed into a different structure, so that the runtime-fixed data - * can be placed into read-only space. - */ -struct dpll_data { - void __iomem *mult_div1_reg; - u32 mult_mask; - u32 div1_mask; - struct clk *clk_bypass; - struct clk *clk_ref; - void __iomem *control_reg; - u32 enable_mask; - unsigned long last_rounded_rate; - u16 last_rounded_m; - u16 max_multiplier; - u8 last_rounded_n; - u8 min_divider; - u16 max_divider; - u8 modes; - void __iomem *autoidle_reg; - void __iomem *idlest_reg; - u32 autoidle_mask; - u32 freqsel_mask; - u32 idlest_mask; - u32 dco_mask; - u32 sddiv_mask; - u8 auto_recal_bit; - u8 recal_en_bit; - u8 recal_st_bit; - u8 flags; -}; - -#endif - -/* - * struct clk.flags possibilities - * - * XXX document the rest of the clock flags here - * - * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL - * bits share the same register. This flag allows the - * omap4_dpllmx*() code to determine which GATE_CTRL bit field - * should be used. This is a temporary solution - a better approach - * would be to associate clock type-specific data with the clock, - * similar to the struct dpll_data approach. - */ -#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ -#define CLOCK_IDLE_CONTROL (1 << 1) -#define CLOCK_NO_IDLE_PARENT (1 << 2) -#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ -#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ -#define CLOCK_CLKOUTX2 (1 << 5) - -/** - * struct clk - OMAP struct clk - * @node: list_head connecting this clock into the full clock list - * @ops: struct clkops * for this clock - * @name: the name of the clock in the hardware (used in hwmod data and debug) - * @parent: pointer to this clock's parent struct clk - * @children: list_head connecting to the child clks' @sibling list_heads - * @sibling: list_head connecting this clk to its parent clk's @children - * @rate: current clock rate - * @enable_reg: register to write to enable the clock (see @enable_bit) - * @recalc: fn ptr that returns the clock's current rate - * @set_rate: fn ptr that can change the clock's current rate - * @round_rate: fn ptr that can round the clock's current rate - * @init: fn ptr to do clock-specific initialization - * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) - * @usecount: number of users that have requested this clock to be enabled - * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div - * @flags: see "struct clk.flags possibilities" above - * @clksel_reg: for clksel clks, register va containing src/divisor select - * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector - * @clksel: for clksel clks, pointer to struct clksel for this clock - * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock - * @clkdm_name: clockdomain name that this clock is contained in - * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime - * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) - * @src_offset: bitshift for source selection bitfield (OMAP1 only) - * - * XXX @rate_offset, @src_offset should probably be removed and OMAP1 - * clock code converted to use clksel. - * - * XXX @usecount is poorly named. It should be "enable_count" or - * something similar. "users" in the description refers to kernel - * code (core code or drivers) that have called clk_enable() and not - * yet called clk_disable(); the usecount of parent clocks is also - * incremented by the clock code when clk_enable() is called on child - * clocks and decremented by the clock code when clk_disable() is - * called on child clocks. - * - * XXX @clkdm, @usecount, @children, @sibling should be marked for - * internal use only. - * - * @children and @sibling are used to optimize parent-to-child clock - * tree traversals. (child-to-parent traversals use @parent.) - * - * XXX The notion of the clock's current rate probably needs to be - * separated from the clock's target rate. - */ -struct clk { - struct list_head node; - const struct clkops *ops; - const char *name; - struct clk *parent; - struct list_head children; - struct list_head sibling; /* node for children */ - unsigned long rate; - void __iomem *enable_reg; - unsigned long (*recalc)(struct clk *); - int (*set_rate)(struct clk *, unsigned long); - long (*round_rate)(struct clk *, unsigned long); - void (*init)(struct clk *); - u8 enable_bit; - s8 usecount; - u8 fixed_div; - u8 flags; -#ifdef CONFIG_ARCH_OMAP2PLUS - void __iomem *clksel_reg; - u32 clksel_mask; - const struct clksel *clksel; - struct dpll_data *dpll_data; - const char *clkdm_name; - struct clockdomain *clkdm; -#else - u8 rate_offset; - u8 src_offset; -#endif -#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) - struct dentry *dent; /* For visible tree hierarchy */ -#endif -}; - -struct clk_functions { - int (*clk_enable)(struct clk *clk); - void (*clk_disable)(struct clk *clk); - long (*clk_round_rate)(struct clk *clk, unsigned long rate); - int (*clk_set_rate)(struct clk *clk, unsigned long rate); - int (*clk_set_parent)(struct clk *clk, struct clk *parent); - void (*clk_allow_idle)(struct clk *clk); - void (*clk_deny_idle)(struct clk *clk); - void (*clk_disable_unused)(struct clk *clk); -}; - -extern int mpurate; - -extern int clk_init(struct clk_functions *custom_clocks); -extern void clk_preinit(struct clk *clk); -extern int clk_register(struct clk *clk); -extern void clk_reparent(struct clk *child, struct clk *parent); -extern void clk_unregister(struct clk *clk); -extern void propagate_rate(struct clk *clk); -extern void recalculate_root_clocks(void); -extern unsigned long followparent_recalc(struct clk *clk); -extern void clk_enable_init_clocks(void); -unsigned long omap_fixed_divisor_recalc(struct clk *clk); -extern struct clk *omap_clk_get_by_name(const char *name); -extern int omap_clk_enable_autoidle_all(void); -extern int omap_clk_disable_autoidle_all(void); - -extern const struct clkops clkops_null; - -extern struct clk dummy_ck; - -#endif diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 67da857783ce..ba542ec8d513 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -1,6 +1,4 @@ /* - * arch/arm/plat-omap/include/mach/cpu.h - * * OMAP cpu type detection * * Copyright (C) 2004, 2008 Nokia Corporation @@ -30,470 +28,12 @@ #ifndef __ASM_ARCH_OMAP_CPU_H #define __ASM_ARCH_OMAP_CPU_H -#ifndef __ASSEMBLY__ - -#include <linux/bitops.h> -#include <plat/multi.h> - -/* - * Omap device type i.e. EMU/HS/TST/GP/BAD - */ -#define OMAP2_DEVICE_TYPE_TEST 0 -#define OMAP2_DEVICE_TYPE_EMU 1 -#define OMAP2_DEVICE_TYPE_SEC 2 -#define OMAP2_DEVICE_TYPE_GP 3 -#define OMAP2_DEVICE_TYPE_BAD 4 - -int omap_type(void); - -/* - * omap_rev bits: - * CPU id bits (0730, 1510, 1710, 2422...) [31:16] - * CPU revision (See _REV_ defined in cpu.h) [15:08] - * CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00] - */ -unsigned int omap_rev(void); - -/* - * Get the CPU revision for OMAP devices - */ -#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff) - -/* - * Macros to group OMAP into cpu classes. - * These can be used in most places. - * cpu_is_omap7xx(): True for OMAP730, OMAP850 - * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310 - * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710 - * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430 - * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423 - * cpu_is_omap243x(): True for OMAP2430 - * cpu_is_omap343x(): True for OMAP3430 - * cpu_is_omap443x(): True for OMAP4430 - * cpu_is_omap446x(): True for OMAP4460 - * cpu_is_omap447x(): True for OMAP4470 - * soc_is_omap543x(): True for OMAP5430, OMAP5432 - */ -#define GET_OMAP_CLASS (omap_rev() & 0xff) - -#define IS_OMAP_CLASS(class, id) \ -static inline int is_omap ##class (void) \ -{ \ - return (GET_OMAP_CLASS == (id)) ? 1 : 0; \ -} - -#define GET_AM_CLASS ((omap_rev() >> 24) & 0xff) - -#define IS_AM_CLASS(class, id) \ -static inline int is_am ##class (void) \ -{ \ - return (GET_AM_CLASS == (id)) ? 1 : 0; \ -} - -#define GET_TI_CLASS ((omap_rev() >> 24) & 0xff) - -#define IS_TI_CLASS(class, id) \ -static inline int is_ti ##class (void) \ -{ \ - return (GET_TI_CLASS == (id)) ? 1 : 0; \ -} - -#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff) - -#define IS_OMAP_SUBCLASS(subclass, id) \ -static inline int is_omap ##subclass (void) \ -{ \ - return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ -} - -#define IS_TI_SUBCLASS(subclass, id) \ -static inline int is_ti ##subclass (void) \ -{ \ - return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ -} - -#define IS_AM_SUBCLASS(subclass, id) \ -static inline int is_am ##subclass (void) \ -{ \ - return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ -} - -IS_OMAP_CLASS(7xx, 0x07) -IS_OMAP_CLASS(15xx, 0x15) -IS_OMAP_CLASS(16xx, 0x16) -IS_OMAP_CLASS(24xx, 0x24) -IS_OMAP_CLASS(34xx, 0x34) -IS_OMAP_CLASS(44xx, 0x44) -IS_AM_CLASS(35xx, 0x35) -IS_OMAP_CLASS(54xx, 0x54) -IS_AM_CLASS(33xx, 0x33) - -IS_TI_CLASS(81xx, 0x81) - -IS_OMAP_SUBCLASS(242x, 0x242) -IS_OMAP_SUBCLASS(243x, 0x243) -IS_OMAP_SUBCLASS(343x, 0x343) -IS_OMAP_SUBCLASS(363x, 0x363) -IS_OMAP_SUBCLASS(443x, 0x443) -IS_OMAP_SUBCLASS(446x, 0x446) -IS_OMAP_SUBCLASS(447x, 0x447) -IS_OMAP_SUBCLASS(543x, 0x543) - -IS_TI_SUBCLASS(816x, 0x816) -IS_TI_SUBCLASS(814x, 0x814) -IS_AM_SUBCLASS(335x, 0x335) - -#define cpu_is_omap7xx() 0 -#define cpu_is_omap15xx() 0 -#define cpu_is_omap16xx() 0 -#define cpu_is_omap24xx() 0 -#define cpu_is_omap242x() 0 -#define cpu_is_omap243x() 0 -#define cpu_is_omap34xx() 0 -#define cpu_is_omap343x() 0 -#define cpu_is_ti81xx() 0 -#define cpu_is_ti816x() 0 -#define cpu_is_ti814x() 0 -#define soc_is_am35xx() 0 -#define soc_is_am33xx() 0 -#define soc_is_am335x() 0 -#define cpu_is_omap44xx() 0 -#define cpu_is_omap443x() 0 -#define cpu_is_omap446x() 0 -#define cpu_is_omap447x() 0 -#define soc_is_omap54xx() 0 -#define soc_is_omap543x() 0 - -#if defined(MULTI_OMAP1) -# if defined(CONFIG_ARCH_OMAP730) -# undef cpu_is_omap7xx -# define cpu_is_omap7xx() is_omap7xx() -# endif -# if defined(CONFIG_ARCH_OMAP850) -# undef cpu_is_omap7xx -# define cpu_is_omap7xx() is_omap7xx() -# endif -# if defined(CONFIG_ARCH_OMAP15XX) -# undef cpu_is_omap15xx -# define cpu_is_omap15xx() is_omap15xx() -# endif -# if defined(CONFIG_ARCH_OMAP16XX) -# undef cpu_is_omap16xx -# define cpu_is_omap16xx() is_omap16xx() -# endif -#else -# if defined(CONFIG_ARCH_OMAP730) -# undef cpu_is_omap7xx -# define cpu_is_omap7xx() 1 -# endif -# if defined(CONFIG_ARCH_OMAP850) -# undef cpu_is_omap7xx -# define cpu_is_omap7xx() 1 -# endif -# if defined(CONFIG_ARCH_OMAP15XX) -# undef cpu_is_omap15xx -# define cpu_is_omap15xx() 1 -# endif -# if defined(CONFIG_ARCH_OMAP16XX) -# undef cpu_is_omap16xx -# define cpu_is_omap16xx() 1 -# endif -#endif - -#if defined(MULTI_OMAP2) -# if defined(CONFIG_ARCH_OMAP2) -# undef cpu_is_omap24xx -# define cpu_is_omap24xx() is_omap24xx() -# endif -# if defined (CONFIG_SOC_OMAP2420) -# undef cpu_is_omap242x -# define cpu_is_omap242x() is_omap242x() -# endif -# if defined (CONFIG_SOC_OMAP2430) -# undef cpu_is_omap243x -# define cpu_is_omap243x() is_omap243x() -# endif -# if defined(CONFIG_ARCH_OMAP3) -# undef cpu_is_omap34xx -# undef cpu_is_omap343x -# define cpu_is_omap34xx() is_omap34xx() -# define cpu_is_omap343x() is_omap343x() -# endif -#else -# if defined(CONFIG_ARCH_OMAP2) -# undef cpu_is_omap24xx -# define cpu_is_omap24xx() 1 -# endif -# if defined(CONFIG_SOC_OMAP2420) -# undef cpu_is_omap242x -# define cpu_is_omap242x() 1 -# endif -# if defined(CONFIG_SOC_OMAP2430) -# undef cpu_is_omap243x -# define cpu_is_omap243x() 1 -# endif -# if defined(CONFIG_ARCH_OMAP3) -# undef cpu_is_omap34xx -# define cpu_is_omap34xx() 1 -# endif -# if defined(CONFIG_SOC_OMAP3430) -# undef cpu_is_omap343x -# define cpu_is_omap343x() 1 -# endif -#endif - -/* - * Macros to detect individual cpu types. - * These are only rarely needed. - * cpu_is_omap310(): True for OMAP310 - * cpu_is_omap1510(): True for OMAP1510 - * cpu_is_omap1610(): True for OMAP1610 - * cpu_is_omap1611(): True for OMAP1611 - * cpu_is_omap5912(): True for OMAP5912 - * cpu_is_omap1621(): True for OMAP1621 - * cpu_is_omap1710(): True for OMAP1710 - * cpu_is_omap2420(): True for OMAP2420 - * cpu_is_omap2422(): True for OMAP2422 - * cpu_is_omap2423(): True for OMAP2423 - * cpu_is_omap2430(): True for OMAP2430 - * cpu_is_omap3430(): True for OMAP3430 - */ -#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff) - -#define IS_OMAP_TYPE(type, id) \ -static inline int is_omap ##type (void) \ -{ \ - return (GET_OMAP_TYPE == (id)) ? 1 : 0; \ -} - -IS_OMAP_TYPE(310, 0x0310) -IS_OMAP_TYPE(1510, 0x1510) -IS_OMAP_TYPE(1610, 0x1610) -IS_OMAP_TYPE(1611, 0x1611) -IS_OMAP_TYPE(5912, 0x1611) -IS_OMAP_TYPE(1621, 0x1621) -IS_OMAP_TYPE(1710, 0x1710) -IS_OMAP_TYPE(2420, 0x2420) -IS_OMAP_TYPE(2422, 0x2422) -IS_OMAP_TYPE(2423, 0x2423) -IS_OMAP_TYPE(2430, 0x2430) -IS_OMAP_TYPE(3430, 0x3430) - -#define cpu_is_omap310() 0 -#define cpu_is_omap1510() 0 -#define cpu_is_omap1610() 0 -#define cpu_is_omap5912() 0 -#define cpu_is_omap1611() 0 -#define cpu_is_omap1621() 0 -#define cpu_is_omap1710() 0 -#define cpu_is_omap2420() 0 -#define cpu_is_omap2422() 0 -#define cpu_is_omap2423() 0 -#define cpu_is_omap2430() 0 -#define cpu_is_omap3430() 0 -#define cpu_is_omap3630() 0 -#define soc_is_omap5430() 0 - -/* - * Whether we have MULTI_OMAP1 or not, we still need to distinguish - * between 310 vs. 1510 and 1611B/5912 vs. 1710. - */ - -#if defined(CONFIG_ARCH_OMAP15XX) -# undef cpu_is_omap310 -# undef cpu_is_omap1510 -# define cpu_is_omap310() is_omap310() -# define cpu_is_omap1510() is_omap1510() -#endif - -#if defined(CONFIG_ARCH_OMAP16XX) -# undef cpu_is_omap1610 -# undef cpu_is_omap1611 -# undef cpu_is_omap5912 -# undef cpu_is_omap1621 -# undef cpu_is_omap1710 -# define cpu_is_omap1610() is_omap1610() -# define cpu_is_omap1611() is_omap1611() -# define cpu_is_omap5912() is_omap5912() -# define cpu_is_omap1621() is_omap1621() -# define cpu_is_omap1710() is_omap1710() -#endif - -#if defined(CONFIG_ARCH_OMAP2) -# undef cpu_is_omap2420 -# undef cpu_is_omap2422 -# undef cpu_is_omap2423 -# undef cpu_is_omap2430 -# define cpu_is_omap2420() is_omap2420() -# define cpu_is_omap2422() is_omap2422() -# define cpu_is_omap2423() is_omap2423() -# define cpu_is_omap2430() is_omap2430() -#endif - -#if defined(CONFIG_ARCH_OMAP3) -# undef cpu_is_omap3430 -# undef cpu_is_ti81xx -# undef cpu_is_ti816x -# undef cpu_is_ti814x -# undef soc_is_am35xx -# define cpu_is_omap3430() is_omap3430() -# undef cpu_is_omap3630 -# define cpu_is_omap3630() is_omap363x() -# define cpu_is_ti81xx() is_ti81xx() -# define cpu_is_ti816x() is_ti816x() -# define cpu_is_ti814x() is_ti814x() -# define soc_is_am35xx() is_am35xx() +#ifdef CONFIG_ARCH_OMAP1 +#include "../../mach-omap1/soc.h" #endif -# if defined(CONFIG_SOC_AM33XX) -# undef soc_is_am33xx -# undef soc_is_am335x -# define soc_is_am33xx() is_am33xx() -# define soc_is_am335x() is_am335x() +#ifdef CONFIG_ARCH_OMAP2PLUS +#include "../../mach-omap2/soc.h" #endif -# if defined(CONFIG_ARCH_OMAP4) -# undef cpu_is_omap44xx -# undef cpu_is_omap443x -# undef cpu_is_omap446x -# undef cpu_is_omap447x -# define cpu_is_omap44xx() is_omap44xx() -# define cpu_is_omap443x() is_omap443x() -# define cpu_is_omap446x() is_omap446x() -# define cpu_is_omap447x() is_omap447x() -# endif - -# if defined(CONFIG_SOC_OMAP5) -# undef soc_is_omap54xx -# undef soc_is_omap543x -# define soc_is_omap54xx() is_omap54xx() -# define soc_is_omap543x() is_omap543x() -#endif - -/* Macros to detect if we have OMAP1 or OMAP2 */ -#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \ - cpu_is_omap16xx()) -#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \ - cpu_is_omap44xx() || soc_is_omap54xx() || \ - soc_is_am33xx()) - -/* Various silicon revisions for omap2 */ -#define OMAP242X_CLASS 0x24200024 -#define OMAP2420_REV_ES1_0 OMAP242X_CLASS -#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (0x1 << 8)) - -#define OMAP243X_CLASS 0x24300024 -#define OMAP2430_REV_ES1_0 OMAP243X_CLASS - -#define OMAP343X_CLASS 0x34300034 -#define OMAP3430_REV_ES1_0 OMAP343X_CLASS -#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (0x1 << 8)) -#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (0x2 << 8)) -#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (0x3 << 8)) -#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (0x4 << 8)) -#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (0x5 << 8)) - -#define OMAP363X_CLASS 0x36300034 -#define OMAP3630_REV_ES1_0 OMAP363X_CLASS -#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (0x1 << 8)) -#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (0x2 << 8)) - -#define TI816X_CLASS 0x81600034 -#define TI8168_REV_ES1_0 TI816X_CLASS -#define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8)) - -#define TI814X_CLASS 0x81400034 -#define TI8148_REV_ES1_0 TI814X_CLASS -#define TI8148_REV_ES2_0 (TI814X_CLASS | (0x1 << 8)) -#define TI8148_REV_ES2_1 (TI814X_CLASS | (0x2 << 8)) - -#define AM35XX_CLASS 0x35170034 -#define AM35XX_REV_ES1_0 AM35XX_CLASS -#define AM35XX_REV_ES1_1 (AM35XX_CLASS | (0x1 << 8)) - -#define AM335X_CLASS 0x33500033 -#define AM335X_REV_ES1_0 AM335X_CLASS - -#define OMAP443X_CLASS 0x44300044 -#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8)) -#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8)) -#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8)) -#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8)) -#define OMAP4430_REV_ES2_3 (OMAP443X_CLASS | (0x23 << 8)) - -#define OMAP446X_CLASS 0x44600044 -#define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8)) -#define OMAP4460_REV_ES1_1 (OMAP446X_CLASS | (0x11 << 8)) - -#define OMAP447X_CLASS 0x44700044 -#define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8)) - -#define OMAP54XX_CLASS 0x54000054 -#define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8)) -#define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8)) - -void omap2xxx_check_revision(void); -void omap3xxx_check_revision(void); -void omap4xxx_check_revision(void); -void omap5xxx_check_revision(void); -void omap3xxx_check_features(void); -void ti81xx_check_features(void); -void omap4xxx_check_features(void); - -/* - * Runtime detection of OMAP3 features - * - * OMAP3_HAS_IO_CHAIN_CTRL: Some later members of the OMAP3 chip - * family have OS-level control over the I/O chain clock. This is - * to avoid a window during which wakeups could potentially be lost - * during powerdomain transitions. If this bit is set, it - * indicates that the chip does support OS-level control of this - * feature. - */ -extern u32 omap_features; - -#define OMAP3_HAS_L2CACHE BIT(0) -#define OMAP3_HAS_IVA BIT(1) -#define OMAP3_HAS_SGX BIT(2) -#define OMAP3_HAS_NEON BIT(3) -#define OMAP3_HAS_ISP BIT(4) -#define OMAP3_HAS_192MHZ_CLK BIT(5) -#define OMAP3_HAS_IO_WAKEUP BIT(6) -#define OMAP3_HAS_SDRC BIT(7) -#define OMAP3_HAS_IO_CHAIN_CTRL BIT(8) -#define OMAP4_HAS_MPU_1GHZ BIT(9) -#define OMAP4_HAS_MPU_1_2GHZ BIT(10) -#define OMAP4_HAS_MPU_1_5GHZ BIT(11) - - -#define OMAP3_HAS_FEATURE(feat,flag) \ -static inline unsigned int omap3_has_ ##feat(void) \ -{ \ - return omap_features & OMAP3_HAS_ ##flag; \ -} \ - -OMAP3_HAS_FEATURE(l2cache, L2CACHE) -OMAP3_HAS_FEATURE(sgx, SGX) -OMAP3_HAS_FEATURE(iva, IVA) -OMAP3_HAS_FEATURE(neon, NEON) -OMAP3_HAS_FEATURE(isp, ISP) -OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) -OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP) -OMAP3_HAS_FEATURE(sdrc, SDRC) -OMAP3_HAS_FEATURE(io_chain_ctrl, IO_CHAIN_CTRL) - -/* - * Runtime detection of OMAP4 features - */ -#define OMAP4_HAS_FEATURE(feat, flag) \ -static inline unsigned int omap4_has_ ##feat(void) \ -{ \ - return omap_features & OMAP4_HAS_ ##flag; \ -} \ - -OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ) -OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ) -OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ) - -#endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/plat-omap/include/plat/dma-44xx.h b/arch/arm/plat-omap/include/plat/dma-44xx.h deleted file mode 100644 index 1f767cb2f38a..000000000000 --- a/arch/arm/plat-omap/include/plat/dma-44xx.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * OMAP4 SDMA channel definitions - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * Copyright (C) 2009-2010 Nokia Corporation - * - * Santosh Shilimkar (santosh.shilimkar@ti.com) - * Benoit Cousson (b-cousson@ti.com) - * Paul Walmsley (paul@pwsan.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H -#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H - -#define OMAP44XX_DMA_SYS_REQ0 2 -#define OMAP44XX_DMA_SYS_REQ1 3 -#define OMAP44XX_DMA_GPMC 4 -#define OMAP44XX_DMA_DSS_DISPC_REQ 6 -#define OMAP44XX_DMA_SYS_REQ2 7 -#define OMAP44XX_DMA_MCASP1_AXEVT 8 -#define OMAP44XX_DMA_ISS_REQ1 9 -#define OMAP44XX_DMA_ISS_REQ2 10 -#define OMAP44XX_DMA_MCASP1_AREVT 11 -#define OMAP44XX_DMA_ISS_REQ3 12 -#define OMAP44XX_DMA_ISS_REQ4 13 -#define OMAP44XX_DMA_DSS_RFBI_REQ 14 -#define OMAP44XX_DMA_SPI3_TX0 15 -#define OMAP44XX_DMA_SPI3_RX0 16 -#define OMAP44XX_DMA_MCBSP2_TX 17 -#define OMAP44XX_DMA_MCBSP2_RX 18 -#define OMAP44XX_DMA_MCBSP3_TX 19 -#define OMAP44XX_DMA_MCBSP3_RX 20 -#define OMAP44XX_DMA_C2C_SSCM_GPO0 21 -#define OMAP44XX_DMA_C2C_SSCM_GPO1 22 -#define OMAP44XX_DMA_SPI3_TX1 23 -#define OMAP44XX_DMA_SPI3_RX1 24 -#define OMAP44XX_DMA_I2C3_TX 25 -#define OMAP44XX_DMA_I2C3_RX 26 -#define OMAP44XX_DMA_I2C1_TX 27 -#define OMAP44XX_DMA_I2C1_RX 28 -#define OMAP44XX_DMA_I2C2_TX 29 -#define OMAP44XX_DMA_I2C2_RX 30 -#define OMAP44XX_DMA_MCBSP4_TX 31 -#define OMAP44XX_DMA_MCBSP4_RX 32 -#define OMAP44XX_DMA_MCBSP1_TX 33 -#define OMAP44XX_DMA_MCBSP1_RX 34 -#define OMAP44XX_DMA_SPI1_TX0 35 -#define OMAP44XX_DMA_SPI1_RX0 36 -#define OMAP44XX_DMA_SPI1_TX1 37 -#define OMAP44XX_DMA_SPI1_RX1 38 -#define OMAP44XX_DMA_SPI1_TX2 39 -#define OMAP44XX_DMA_SPI1_RX2 40 -#define OMAP44XX_DMA_SPI1_TX3 41 -#define OMAP44XX_DMA_SPI1_RX3 42 -#define OMAP44XX_DMA_SPI2_TX0 43 -#define OMAP44XX_DMA_SPI2_RX0 44 -#define OMAP44XX_DMA_SPI2_TX1 45 -#define OMAP44XX_DMA_SPI2_RX1 46 -#define OMAP44XX_DMA_MMC2_TX 47 -#define OMAP44XX_DMA_MMC2_RX 48 -#define OMAP44XX_DMA_UART1_TX 49 -#define OMAP44XX_DMA_UART1_RX 50 -#define OMAP44XX_DMA_UART2_TX 51 -#define OMAP44XX_DMA_UART2_RX 52 -#define OMAP44XX_DMA_UART3_TX 53 -#define OMAP44XX_DMA_UART3_RX 54 -#define OMAP44XX_DMA_UART4_TX 55 -#define OMAP44XX_DMA_UART4_RX 56 -#define OMAP44XX_DMA_MMC4_TX 57 -#define OMAP44XX_DMA_MMC4_RX 58 -#define OMAP44XX_DMA_MMC5_TX 59 -#define OMAP44XX_DMA_MMC5_RX 60 -#define OMAP44XX_DMA_MMC1_TX 61 -#define OMAP44XX_DMA_MMC1_RX 62 -#define OMAP44XX_DMA_SYS_REQ3 64 -#define OMAP44XX_DMA_MCPDM_UP 65 -#define OMAP44XX_DMA_MCPDM_DL 66 -#define OMAP44XX_DMA_DMIC_REQ 67 -#define OMAP44XX_DMA_C2C_SSCM_GPO2 68 -#define OMAP44XX_DMA_C2C_SSCM_GPO3 69 -#define OMAP44XX_DMA_SPI4_TX0 70 -#define OMAP44XX_DMA_SPI4_RX0 71 -#define OMAP44XX_DMA_DSS_DSI1_REQ0 72 -#define OMAP44XX_DMA_DSS_DSI1_REQ1 73 -#define OMAP44XX_DMA_DSS_DSI1_REQ2 74 -#define OMAP44XX_DMA_DSS_DSI1_REQ3 75 -#define OMAP44XX_DMA_DSS_HDMI_REQ 76 -#define OMAP44XX_DMA_MMC3_TX 77 -#define OMAP44XX_DMA_MMC3_RX 78 -#define OMAP44XX_DMA_USIM_TX 79 -#define OMAP44XX_DMA_USIM_RX 80 -#define OMAP44XX_DMA_DSS_DSI2_REQ0 81 -#define OMAP44XX_DMA_DSS_DSI2_REQ1 82 -#define OMAP44XX_DMA_DSS_DSI2_REQ2 83 -#define OMAP44XX_DMA_DSS_DSI2_REQ3 84 -#define OMAP44XX_DMA_SLIMBUS1_TX0 85 -#define OMAP44XX_DMA_SLIMBUS1_TX1 86 -#define OMAP44XX_DMA_SLIMBUS1_TX2 87 -#define OMAP44XX_DMA_SLIMBUS1_TX3 88 -#define OMAP44XX_DMA_SLIMBUS1_RX0 89 -#define OMAP44XX_DMA_SLIMBUS1_RX1 90 -#define OMAP44XX_DMA_SLIMBUS1_RX2 91 -#define OMAP44XX_DMA_SLIMBUS1_RX3 92 -#define OMAP44XX_DMA_SLIMBUS2_TX0 93 -#define OMAP44XX_DMA_SLIMBUS2_TX1 94 -#define OMAP44XX_DMA_SLIMBUS2_TX2 95 -#define OMAP44XX_DMA_SLIMBUS2_TX3 96 -#define OMAP44XX_DMA_SLIMBUS2_RX0 97 -#define OMAP44XX_DMA_SLIMBUS2_RX1 98 -#define OMAP44XX_DMA_SLIMBUS2_RX2 99 -#define OMAP44XX_DMA_SLIMBUS2_RX3 100 -#define OMAP44XX_DMA_ABE_REQ_0 101 -#define OMAP44XX_DMA_ABE_REQ_1 102 -#define OMAP44XX_DMA_ABE_REQ_2 103 -#define OMAP44XX_DMA_ABE_REQ_3 104 -#define OMAP44XX_DMA_ABE_REQ_4 105 -#define OMAP44XX_DMA_ABE_REQ_5 106 -#define OMAP44XX_DMA_ABE_REQ_6 107 -#define OMAP44XX_DMA_ABE_REQ_7 108 -#define OMAP44XX_DMA_AES1_P_CTX_IN_REQ 109 -#define OMAP44XX_DMA_AES1_P_DATA_IN_REQ 110 -#define OMAP44XX_DMA_AES1_P_DATA_OUT_REQ 111 -#define OMAP44XX_DMA_AES2_P_CTX_IN_REQ 112 -#define OMAP44XX_DMA_AES2_P_DATA_IN_REQ 113 -#define OMAP44XX_DMA_AES2_P_DATA_OUT_REQ 114 -#define OMAP44XX_DMA_DES_P_CTX_IN_REQ 115 -#define OMAP44XX_DMA_DES_P_DATA_IN_REQ 116 -#define OMAP44XX_DMA_DES_P_DATA_OUT_REQ 117 -#define OMAP44XX_DMA_SHA2_CTXIN_P 118 -#define OMAP44XX_DMA_SHA2_DIN_P 119 -#define OMAP44XX_DMA_SHA2_CTXOUT_P 120 -#define OMAP44XX_DMA_AES1_P_CONTEXT_OUT_REQ 121 -#define OMAP44XX_DMA_AES2_P_CONTEXT_OUT_REQ 122 -#define OMAP44XX_DMA_I2C4_TX 124 -#define OMAP44XX_DMA_I2C4_RX 125 - -#endif diff --git a/arch/arm/plat-omap/include/plat/fpga.h b/arch/arm/plat-omap/include/plat/fpga.h deleted file mode 100644 index bd3c6324ae1f..000000000000 --- a/arch/arm/plat-omap/include/plat/fpga.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/fpga.h - * - * Interrupt handler for OMAP-1510 FPGA - * - * Copyright (C) 2001 RidgeRun, Inc. - * Author: Greg Lonnon <glonnon@ridgerun.com> - * - * Copyright (C) 2002 MontaVista Software, Inc. - * - * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 - * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_OMAP_FPGA_H -#define __ASM_ARCH_OMAP_FPGA_H - -extern void omap1510_fpga_init_irq(void); - -#define fpga_read(reg) __raw_readb(reg) -#define fpga_write(val, reg) __raw_writeb(val, reg) - -/* - * --------------------------------------------------------------------------- - * H2/P2 Debug board FPGA - * --------------------------------------------------------------------------- - */ -/* maps in the FPGA registers and the ETHR registers */ -#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */ -#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ -#define H2P2_DBG_FPGA_START 0x04000000 /* PA */ - -#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300) -#define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ -#define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */ -#define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */ -#define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */ -#define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */ -#define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */ -#define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */ - -/* NOTE: most boards don't have a static mapping for the FPGA ... */ -struct h2p2_dbg_fpga { - /* offset 0x00 */ - u16 smc91x[8]; - /* offset 0x10 */ - u16 fpga_rev; - u16 board_rev; - u16 gpio_outputs; - u16 leds; - /* offset 0x18 */ - u16 misc_inputs; - u16 lan_status; - u16 lan_reset; - u16 reserved0; - /* offset 0x20 */ - u16 ps2_data; - u16 ps2_ctrl; - /* plus also 4 rs232 ports ... */ -}; - -/* LEDs definition on debug board (16 LEDs, all physically green) */ -#define H2P2_DBG_FPGA_LED_GREEN (1 << 15) -#define H2P2_DBG_FPGA_LED_AMBER (1 << 14) -#define H2P2_DBG_FPGA_LED_RED (1 << 13) -#define H2P2_DBG_FPGA_LED_BLUE (1 << 12) -/* cpu0 load-meter LEDs */ -#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ... -#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11 -#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1) - -#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0) -#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1) - -/* - * --------------------------------------------------------------------------- - * OMAP-1510 FPGA - * --------------------------------------------------------------------------- - */ -#define OMAP1510_FPGA_BASE 0xE8000000 /* VA */ -#define OMAP1510_FPGA_SIZE SZ_4K -#define OMAP1510_FPGA_START 0x08000000 /* PA */ - -/* Revision */ -#define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0) -#define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1) - -#define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2) -#define OMAP1510_FPGA_LED_DIGIT IOMEM(OMAP1510_FPGA_BASE + 0x3) -#define INNOVATOR_FPGA_HID_SPI IOMEM(OMAP1510_FPGA_BASE + 0x4) -#define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5) - -/* Interrupt status */ -#define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6) -#define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7) - -/* Interrupt mask */ -#define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8) -#define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9) - -/* Reset registers */ -#define OMAP1510_FPGA_HOST_RESET IOMEM(OMAP1510_FPGA_BASE + 0xa) -#define OMAP1510_FPGA_RST IOMEM(OMAP1510_FPGA_BASE + 0xb) - -#define OMAP1510_FPGA_AUDIO IOMEM(OMAP1510_FPGA_BASE + 0xc) -#define OMAP1510_FPGA_DIP IOMEM(OMAP1510_FPGA_BASE + 0xe) -#define OMAP1510_FPGA_FPGA_IO IOMEM(OMAP1510_FPGA_BASE + 0xf) -#define OMAP1510_FPGA_UART1 IOMEM(OMAP1510_FPGA_BASE + 0x14) -#define OMAP1510_FPGA_UART2 IOMEM(OMAP1510_FPGA_BASE + 0x15) -#define OMAP1510_FPGA_OMAP1510_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x16) -#define OMAP1510_FPGA_BOARD_REV IOMEM(OMAP1510_FPGA_BASE + 0x18) -#define OMAP1510P1_PPT_DATA IOMEM(OMAP1510_FPGA_BASE + 0x100) -#define OMAP1510P1_PPT_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x101) -#define OMAP1510P1_PPT_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x102) - -#define OMAP1510_FPGA_TOUCHSCREEN IOMEM(OMAP1510_FPGA_BASE + 0x204) - -#define INNOVATOR_FPGA_INFO IOMEM(OMAP1510_FPGA_BASE + 0x205) -#define INNOVATOR_FPGA_LCD_BRIGHT_LO IOMEM(OMAP1510_FPGA_BASE + 0x206) -#define INNOVATOR_FPGA_LCD_BRIGHT_HI IOMEM(OMAP1510_FPGA_BASE + 0x207) -#define INNOVATOR_FPGA_LED_GRN_LO IOMEM(OMAP1510_FPGA_BASE + 0x208) -#define INNOVATOR_FPGA_LED_GRN_HI IOMEM(OMAP1510_FPGA_BASE + 0x209) -#define INNOVATOR_FPGA_LED_RED_LO IOMEM(OMAP1510_FPGA_BASE + 0x20a) -#define INNOVATOR_FPGA_LED_RED_HI IOMEM(OMAP1510_FPGA_BASE + 0x20b) -#define INNOVATOR_FPGA_CAM_USB_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20c) -#define INNOVATOR_FPGA_EXP_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20d) -#define INNOVATOR_FPGA_ISR2 IOMEM(OMAP1510_FPGA_BASE + 0x20e) -#define INNOVATOR_FPGA_IMR2 IOMEM(OMAP1510_FPGA_BASE + 0x210) - -#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300) - -/* - * Power up Giga UART driver, turn on HID clock. - * Turn off BT power, since we're not using it and it - * draws power. - */ -#define OMAP1510_FPGA_RESET_VALUE 0x42 - -#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7) -#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6) -#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5) -#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4) -#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3) -#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2) -#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1) -#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0) - -/* - * Innovator/OMAP1510 FPGA HID register bit definitions - */ -#define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */ -#define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */ -#define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */ -#define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */ -#define OMAP1510_FPGA_HID_MISO (1<<4) /* input */ -#define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */ -#define OMAP1510_FPGA_HID_rsrvd (1<<6) -#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */ - -/* The FPGA IRQ is cascaded through GPIO_13 */ -#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13) - -/* IRQ Numbers for interrupts muxed through the FPGA */ -#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0) -#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1) -#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2) -#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3) -#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4) -#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5) -#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6) -#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7) -#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8) -#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9) -#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10) -#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11) -#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12) -#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13) -#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14) -#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15) -#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16) -#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17) -#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18) -#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19) -#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20) -#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21) -#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22) -#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23) - -#endif diff --git a/arch/arm/plat-omap/include/plat/led.h b/arch/arm/plat-omap/include/plat/led.h deleted file mode 100644 index 25e451e7e2fd..000000000000 --- a/arch/arm/plat-omap/include/plat/led.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/led.h - * - * Copyright (C) 2006 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef ASMARM_ARCH_LED_H -#define ASMARM_ARCH_LED_H - -struct omap_led_config { - struct led_classdev cdev; - s16 gpio; -}; - -struct omap_led_platform_data { - s16 nr_leds; - struct omap_led_config *leds; -}; - -#endif diff --git a/arch/arm/plat-omap/include/plat/menelaus.h b/arch/arm/plat-omap/include/plat/menelaus.h deleted file mode 100644 index 4a970ec62dd1..000000000000 --- a/arch/arm/plat-omap/include/plat/menelaus.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/menelaus.h - * - * Functions to access Menelaus power management chip - */ - -#ifndef __ASM_ARCH_MENELAUS_H -#define __ASM_ARCH_MENELAUS_H - -struct device; - -struct menelaus_platform_data { - int (* late_init)(struct device *dev); -}; - -extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask), - void *data); -extern void menelaus_unregister_mmc_callback(void); -extern int menelaus_set_mmc_opendrain(int slot, int enable); -extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on); - -extern int menelaus_set_vmem(unsigned int mV); -extern int menelaus_set_vio(unsigned int mV); -extern int menelaus_set_vmmc(unsigned int mV); -extern int menelaus_set_vaux(unsigned int mV); -extern int menelaus_set_vdcdc(int dcdc, unsigned int mV); -extern int menelaus_set_slot_sel(int enable); -extern int menelaus_get_slot_pin_states(void); -extern int menelaus_set_vcore_sw(unsigned int mV); -extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV); - -#define EN_VPLL_SLEEP (1 << 7) -#define EN_VMMC_SLEEP (1 << 6) -#define EN_VAUX_SLEEP (1 << 5) -#define EN_VIO_SLEEP (1 << 4) -#define EN_VMEM_SLEEP (1 << 3) -#define EN_DC3_SLEEP (1 << 2) -#define EN_DC2_SLEEP (1 << 1) -#define EN_VC_SLEEP (1 << 0) - -extern int menelaus_set_regulator_sleep(int enable, u32 val); - -#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_MENELAUS) -#define omap_has_menelaus() 1 -#else -#define omap_has_menelaus() 0 -#endif - -#endif diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h deleted file mode 100644 index 8b4e4f2da2f5..000000000000 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ /dev/null @@ -1,188 +0,0 @@ -/* - * MMC definitions for OMAP2 - * - * Copyright (C) 2006 Nokia Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __OMAP2_MMC_H -#define __OMAP2_MMC_H - -#include <linux/types.h> -#include <linux/device.h> -#include <linux/mmc/host.h> - -#include <plat/omap_hwmod.h> - -#define OMAP15XX_NR_MMC 1 -#define OMAP16XX_NR_MMC 2 -#define OMAP1_MMC_SIZE 0x080 -#define OMAP1_MMC1_BASE 0xfffb7800 -#define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */ - -#define OMAP24XX_NR_MMC 2 -#define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE -#define OMAP2_MMC1_BASE 0x4809c000 - -#define OMAP4_MMC_REG_OFFSET 0x100 - -#define OMAP_MMC_MAX_SLOTS 2 - -/* - * struct omap_mmc_dev_attr.flags possibilities - * - * OMAP_HSMMC_SUPPORTS_DUAL_VOLT: Some HSMMC controller instances can - * operate with either 1.8Vdc or 3.0Vdc card voltages; this flag - * should be set if this is the case. See for example Section 22.5.3 - * "MMC/SD/SDIO1 Bus Voltage Selection" of the OMAP34xx Multimedia - * Device Silicon Revision 3.1.x Revision ZR (July 2011) (SWPU223R). - * - * OMAP_HSMMC_BROKEN_MULTIBLOCK_READ: Multiple-block read transfers - * don't work correctly on some MMC controller instances on some - * OMAP3 SoCs; this flag should be set if this is the case. See - * for example Advisory 2.1.1.128 "MMC: Multiple Block Read - * Operation Issue" in _OMAP3530/3525/3515/3503 Silicon Errata_ - * Revision F (October 2010) (SPRZ278F). - */ -#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0) -#define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ BIT(1) - -struct omap_mmc_dev_attr { - u8 flags; -}; - -struct omap_mmc_platform_data { - /* back-link to device */ - struct device *dev; - - /* number of slots per controller */ - unsigned nr_slots:2; - - /* set if your board has components or wiring that limits the - * maximum frequency on the MMC bus */ - unsigned int max_freq; - - /* switch the bus to a new slot */ - int (*switch_slot)(struct device *dev, int slot); - /* initialize board-specific MMC functionality, can be NULL if - * not supported */ - int (*init)(struct device *dev); - void (*cleanup)(struct device *dev); - void (*shutdown)(struct device *dev); - - /* To handle board related suspend/resume functionality for MMC */ - int (*suspend)(struct device *dev, int slot); - int (*resume)(struct device *dev, int slot); - - /* Return context loss count due to PM states changing */ - int (*get_context_loss_count)(struct device *dev); - - /* Integrating attributes from the omap_hwmod layer */ - u8 controller_flags; - - /* Register offset deviation */ - u16 reg_offset; - - struct omap_mmc_slot_data { - - /* - * 4/8 wires and any additional host capabilities - * need to OR'd all capabilities (ref. linux/mmc/host.h) - */ - u8 wires; /* Used for the MMC driver on omap1 and 2420 */ - u32 caps; /* Used for the MMC driver on 2430 and later */ - u32 pm_caps; /* PM capabilities of the mmc */ - - /* - * nomux means "standard" muxing is wrong on this board, and - * that board-specific code handled it before common init logic. - */ - unsigned nomux:1; - - /* switch pin can be for card detect (default) or card cover */ - unsigned cover:1; - - /* use the internal clock */ - unsigned internal_clock:1; - - /* nonremovable e.g. eMMC */ - unsigned nonremovable:1; - - /* Try to sleep or power off when possible */ - unsigned power_saving:1; - - /* If using power_saving and the MMC power is not to go off */ - unsigned no_off:1; - - /* eMMC does not handle power off when not in sleep state */ - unsigned no_regulator_off_init:1; - - /* Regulator off remapped to sleep */ - unsigned vcc_aux_disable_is_sleep:1; - - /* we can put the features above into this variable */ -#define HSMMC_HAS_PBIAS (1 << 0) -#define HSMMC_HAS_UPDATED_RESET (1 << 1) - unsigned features; - - int switch_pin; /* gpio (card detect) */ - int gpio_wp; /* gpio (write protect) */ - - int (*set_bus_mode)(struct device *dev, int slot, int bus_mode); - int (*set_power)(struct device *dev, int slot, - int power_on, int vdd); - int (*get_ro)(struct device *dev, int slot); - void (*remux)(struct device *dev, int slot, int power_on); - /* Call back before enabling / disabling regulators */ - void (*before_set_reg)(struct device *dev, int slot, - int power_on, int vdd); - /* Call back after enabling / disabling regulators */ - void (*after_set_reg)(struct device *dev, int slot, - int power_on, int vdd); - /* if we have special card, init it using this callback */ - void (*init_card)(struct mmc_card *card); - - /* return MMC cover switch state, can be NULL if not supported. - * - * possible return values: - * 0 - closed - * 1 - open - */ - int (*get_cover_state)(struct device *dev, int slot); - - const char *name; - u32 ocr_mask; - - /* Card detection IRQs */ - int card_detect_irq; - int (*card_detect)(struct device *dev, int slot); - - unsigned int ban_openended:1; - - } slots[OMAP_MMC_MAX_SLOTS]; -}; - -/* called from board-specific card detection service routine */ -extern void omap_mmc_notify_cover_event(struct device *dev, int slot, - int is_closed); - -#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) -void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, - int nr_controllers); -void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data); -#else -static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, - int nr_controllers) -{ -} -static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) -{ -} -#endif - -extern int omap_msdi_reset(struct omap_hwmod *oh); - -#endif diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h deleted file mode 100644 index 324d31b14852..000000000000 --- a/arch/arm/plat-omap/include/plat/multi.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Support for compiling in multiple OMAP processors - * - * Copyright (C) 2010 Nokia Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __PLAT_OMAP_MULTI_H -#define __PLAT_OMAP_MULTI_H - -/* - * Test if multicore OMAP support is needed - */ -#undef MULTI_OMAP1 -#undef MULTI_OMAP2 -#undef OMAP_NAME - -#ifdef CONFIG_ARCH_OMAP730 -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap730 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP850 -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap850 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP15XX -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap1510 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP16XX -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap16xx -# endif -#endif -#ifdef CONFIG_ARCH_OMAP2PLUS -# if (defined(OMAP_NAME) || defined(MULTI_OMAP1)) -# error "OMAP1 and OMAP2PLUS can't be selected at the same time" -# endif -#endif -#ifdef CONFIG_SOC_OMAP2420 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap2420 -# endif -#endif -#ifdef CONFIG_SOC_OMAP2430 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap2430 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP3 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap3 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP4 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap4 -# endif -#endif - -#ifdef CONFIG_SOC_OMAP5 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap5 -# endif -#endif - -#ifdef CONFIG_SOC_AM33XX -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME am33xx -# endif -#endif - -#endif /* __PLAT_OMAP_MULTI_H */ diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h deleted file mode 100644 index 0e4acd2d2deb..000000000000 --- a/arch/arm/plat-omap/include/plat/omap-secure.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef __OMAP_SECURE_H__ -#define __OMAP_SECURE_H__ - -#include <linux/types.h> - -extern int omap_secure_ram_reserve_memblock(void); - -#ifdef CONFIG_OMAP4_ERRATA_I688 -extern int omap_barrier_reserve_memblock(void); -#else -static inline void omap_barrier_reserve_memblock(void) -{ } -#endif -#endif /* __OMAP_SECURE_H__ */ diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h deleted file mode 100644 index 267f43bb2a4e..000000000000 --- a/arch/arm/plat-omap/include/plat/prcm.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/prcm.h - * - * Access definations for use in OMAP24XX clock and power management - * - * Copyright (C) 2005 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * XXX This file is deprecated. The PRCM is an OMAP2+-only subsystem, - * so this file doesn't belong in plat-omap/include/plat. Please - * do not add anything new to this file. - */ - -#ifndef __ASM_ARM_ARCH_OMAP_PRCM_H -#define __ASM_ARM_ARCH_OMAP_PRCM_H - -u32 omap_prcm_get_reset_sources(void); -int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, - const char *name); - -#endif - - - diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h deleted file mode 100644 index 36d6a7666216..000000000000 --- a/arch/arm/plat-omap/include/plat/sdrc.h +++ /dev/null @@ -1,164 +0,0 @@ -#ifndef ____ASM_ARCH_SDRC_H -#define ____ASM_ARCH_SDRC_H - -/* - * OMAP2/3 SDRC/SMS register definitions - * - * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2008 Nokia Corporation - * - * Tony Lindgren - * Paul Walmsley - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - - -/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */ - -#define SDRC_SYSCONFIG 0x010 -#define SDRC_CS_CFG 0x040 -#define SDRC_SHARING 0x044 -#define SDRC_ERR_TYPE 0x04C -#define SDRC_DLLA_CTRL 0x060 -#define SDRC_DLLA_STATUS 0x064 -#define SDRC_DLLB_CTRL 0x068 -#define SDRC_DLLB_STATUS 0x06C -#define SDRC_POWER 0x070 -#define SDRC_MCFG_0 0x080 -#define SDRC_MR_0 0x084 -#define SDRC_EMR2_0 0x08c -#define SDRC_ACTIM_CTRL_A_0 0x09c -#define SDRC_ACTIM_CTRL_B_0 0x0a0 -#define SDRC_RFR_CTRL_0 0x0a4 -#define SDRC_MANUAL_0 0x0a8 -#define SDRC_MCFG_1 0x0B0 -#define SDRC_MR_1 0x0B4 -#define SDRC_EMR2_1 0x0BC -#define SDRC_ACTIM_CTRL_A_1 0x0C4 -#define SDRC_ACTIM_CTRL_B_1 0x0C8 -#define SDRC_RFR_CTRL_1 0x0D4 -#define SDRC_MANUAL_1 0x0D8 - -#define SDRC_POWER_AUTOCOUNT_SHIFT 8 -#define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT) -#define SDRC_POWER_CLKCTRL_SHIFT 4 -#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT) -#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT) - -/* - * These values represent the number of memory clock cycles between - * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192 - * rows per device, and include a subtraction of a 50 cycle window in the - * event that the autorefresh command is delayed due to other SDRC activity. - * The '| 1' sets the ARE field to send one autorefresh when the autorefresh - * counter reaches 0. - * - * These represent optimal values for common parts, it won't work for all. - * As long as you scale down, most parameters are still work, they just - * become sub-optimal. The RFR value goes in the opposite direction. If you - * don't adjust it down as your clock period increases the refresh interval - * will not be met. Setting all parameters for complete worst case may work, - * but may cut memory performance by 2x. Due to errata the DLLs need to be - * unlocked and their value needs run time calibration. A dynamic call is - * need for that as no single right value exists acorss production samples. - * - * Only the FULL speed values are given. Current code is such that rate - * changes must be made at DPLLoutx2. The actual value adjustment for low - * frequency operation will be handled by omap_set_performance() - * - * By having the boot loader boot up in the fastest L4 speed available likely - * will result in something which you can switch between. - */ -#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1) -#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1) -#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1) -#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */ -#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */ - - -/* - * SMS register access - */ - -#define OMAP242X_SMS_REGADDR(reg) \ - (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg) -#define OMAP243X_SMS_REGADDR(reg) \ - (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg) -#define OMAP343X_SMS_REGADDR(reg) \ - (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg) - -/* SMS register offsets - read/write with sms_{read,write}_reg() */ - -#define SMS_SYSCONFIG 0x010 -#define SMS_ROT_CONTROL(context) (0x180 + 0x10 * context) -#define SMS_ROT_SIZE(context) (0x184 + 0x10 * context) -#define SMS_ROT_PHYSICAL_BA(context) (0x188 + 0x10 * context) -/* REVISIT: fill in other SMS registers here */ - - -#ifndef __ASSEMBLER__ - -/** - * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate - * @rate: SDRC clock rate (in Hz) - * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate - * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate - * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate - * @mr: Value to program to SDRC_MR for this rate - * - * This structure holds a pre-computed set of register values for the - * SDRC for a given SDRC clock rate and SDRAM chip. These are - * intended to be pre-computed and specified in an array in the board-*.c - * files. The structure is keyed off the 'rate' field. - */ -struct omap_sdrc_params { - unsigned long rate; - u32 actim_ctrla; - u32 actim_ctrlb; - u32 rfr_ctrl; - u32 mr; -}; - -#ifdef CONFIG_SOC_HAS_OMAP2_SDRC -void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, - struct omap_sdrc_params *sdrc_cs1); -#else -static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, - struct omap_sdrc_params *sdrc_cs1) {}; -#endif - -int omap2_sdrc_get_params(unsigned long r, - struct omap_sdrc_params **sdrc_cs0, - struct omap_sdrc_params **sdrc_cs1); -void omap2_sms_save_context(void); -void omap2_sms_restore_context(void); - -void omap2_sms_write_rot_control(u32 val, unsigned ctx); -void omap2_sms_write_rot_size(u32 val, unsigned ctx); -void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx); - -#ifdef CONFIG_ARCH_OMAP2 - -struct memory_timings { - u32 m_type; /* ddr = 1, sdr = 0 */ - u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */ - u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */ - u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */ - u32 base_cs; /* base chip select to use for calculations */ -}; - -extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode); -struct omap_sdrc_params *rx51_get_sdram_timings(void); - -u32 omap2xxx_sdrc_dll_is_unlocked(void); -u32 omap2xxx_sdrc_reprogram(u32 level, u32 force); - -#endif /* CONFIG_ARCH_OMAP2 */ - -#endif /* __ASSEMBLER__ */ - -#endif diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h deleted file mode 100644 index 227ae2657554..000000000000 --- a/arch/arm/plat-omap/include/plat/sram.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/sram.h - * - * Interface for functions that need to be run in internal SRAM - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_OMAP_SRAM_H -#define __ARCH_ARM_OMAP_SRAM_H - -#ifndef __ASSEMBLY__ -#include <asm/fncpy.h> - -extern void *omap_sram_push_address(unsigned long size); - -/* Macro to push a function to the internal SRAM, using the fncpy API */ -#define omap_sram_push(funcp, size) ({ \ - typeof(&(funcp)) _res = NULL; \ - void *_sram_address = omap_sram_push_address(size); \ - if (_sram_address) \ - _res = fncpy(_sram_address, &(funcp), size); \ - _res; \ -}) - -extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); - -extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, - u32 base_cs, u32 force_unlock); -extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, - u32 mem_type); -extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); - -extern u32 omap3_configure_core_dpll( - u32 m2, u32 unlock_dll, u32 f, u32 inc, - u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0, - u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0, - u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1, - u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1); -extern void omap3_sram_restore_context(void); - -/* Do not use these */ -extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); -extern unsigned long omap1_sram_reprogram_clock_sz; - -extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl); -extern unsigned long omap24xx_sram_reprogram_clock_sz; - -extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, - u32 base_cs, u32 force_unlock); -extern unsigned long omap242x_sram_ddr_init_sz; - -extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, - int bypass); -extern unsigned long omap242x_sram_set_prcm_sz; - -extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, - u32 mem_type); -extern unsigned long omap242x_sram_reprogram_sdrc_sz; - - -extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, - u32 base_cs, u32 force_unlock); -extern unsigned long omap243x_sram_ddr_init_sz; - -extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, - int bypass); -extern unsigned long omap243x_sram_set_prcm_sz; - -extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, - u32 mem_type); -extern unsigned long omap243x_sram_reprogram_sdrc_sz; - -extern u32 omap3_sram_configure_core_dpll( - u32 m2, u32 unlock_dll, u32 f, u32 inc, - u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0, - u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0, - u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1, - u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1); -extern unsigned long omap3_sram_configure_core_dpll_sz; - -#ifdef CONFIG_PM -extern void omap_push_sram_idle(void); -#else -static inline void omap_push_sram_idle(void) {} -#endif /* CONFIG_PM */ - -#endif /* __ASSEMBLY__ */ - -/* - * OMAP2+: define the SRAM PA addresses. - * Used by the SRAM management code and the idle sleep code. - */ -#define OMAP2_SRAM_PA 0x40200000 -#define OMAP3_SRAM_PA 0x40200000 -#ifdef CONFIG_OMAP4_ERRATA_I688 -#define OMAP4_SRAM_PA 0x40304000 -#define OMAP4_SRAM_VA 0xfe404000 -#else -#define OMAP4_SRAM_PA 0x40300000 -#endif -#define AM33XX_SRAM_PA 0x40300000 -#endif diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h deleted file mode 100644 index 7f7b112acccb..000000000000 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/uncompress.h - * - * Serial port stubs for kernel decompress status messages - * - * Initially based on: - * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h - * Copyright (C) 2000 RidgeRun, Inc. - * Author: Greg Lonnon <glonnon@ridgerun.com> - * - * Rewritten by: - * Author: <source@mvista.com> - * 2004 (c) MontaVista Software, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include <linux/types.h> -#include <linux/serial_reg.h> - -#include <asm/memory.h> -#include <asm/mach-types.h> - -#include <plat/serial.h> - -#define MDR1_MODE_MASK 0x07 - -volatile u8 *uart_base; -int uart_shift; - -/* - * Store the DEBUG_LL uart number into memory. - * See also debug-macro.S, and serial.c for related code. - */ -static void set_omap_uart_info(unsigned char port) -{ - /* - * Get address of some.bss variable and round it down - * a la CONFIG_AUTO_ZRELADDR. - */ - u32 ram_start = (u32)&uart_shift & 0xf8000000; - u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS); - *uart_info = port; -} - -static void putc(int c) -{ - if (!uart_base) - return; - - /* Check for UART 16x mode */ - if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0) - return; - - while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE)) - barrier(); - uart_base[UART_TX << uart_shift] = c; -} - -static inline void flush(void) -{ -} - -/* - * Macros to configure UART1 and debug UART - */ -#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id) \ - if (machine_is_##mach()) { \ - uart_base = (volatile u8 *)(dbg_uart); \ - uart_shift = (dbg_shft); \ - port = (dbg_id); \ - set_omap_uart_info(port); \ - break; \ - } - -#define DEBUG_LL_OMAP7XX(p, mach) \ - _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, \ - OMAP1UART##p) - -#define DEBUG_LL_OMAP1(p, mach) \ - _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, \ - OMAP1UART##p) - -#define DEBUG_LL_OMAP2(p, mach) \ - _DEBUG_LL_ENTRY(mach, OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, \ - OMAP2UART##p) - -#define DEBUG_LL_OMAP3(p, mach) \ - _DEBUG_LL_ENTRY(mach, OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, \ - OMAP3UART##p) - -#define DEBUG_LL_OMAP4(p, mach) \ - _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, \ - OMAP4UART##p) - -#define DEBUG_LL_OMAP5(p, mach) \ - _DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT, \ - OMAP5UART##p) -/* Zoom2/3 shift is different for UART1 and external port */ -#define DEBUG_LL_ZOOM(mach) \ - _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART) - -#define DEBUG_LL_TI81XX(p, mach) \ - _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ - TI81XXUART##p) - -#define DEBUG_LL_AM33XX(p, mach) \ - _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ - AM33XXUART##p) - -static inline void arch_decomp_setup(void) -{ - int port = 0; - - /* - * Initialize the port based on the machine ID from the bootloader. - * Note that we're using macros here instead of switch statement - * as machine_is functions are optimized out for the boards that - * are not selected. - */ - do { - /* omap7xx/8xx based boards using UART1 with shift 0 */ - DEBUG_LL_OMAP7XX(1, herald); - DEBUG_LL_OMAP7XX(1, omap_perseus2); - - /* omap15xx/16xx based boards using UART1 */ - DEBUG_LL_OMAP1(1, ams_delta); - DEBUG_LL_OMAP1(1, nokia770); - DEBUG_LL_OMAP1(1, omap_h2); - DEBUG_LL_OMAP1(1, omap_h3); - DEBUG_LL_OMAP1(1, omap_innovator); - DEBUG_LL_OMAP1(1, omap_osk); - DEBUG_LL_OMAP1(1, omap_palmte); - DEBUG_LL_OMAP1(1, omap_palmz71); - - /* omap15xx/16xx based boards using UART2 */ - DEBUG_LL_OMAP1(2, omap_palmtt); - - /* omap15xx/16xx based boards using UART3 */ - DEBUG_LL_OMAP1(3, sx1); - - /* omap2 based boards using UART1 */ - DEBUG_LL_OMAP2(1, omap_2430sdp); - DEBUG_LL_OMAP2(1, omap_apollon); - DEBUG_LL_OMAP2(1, omap_h4); - - /* omap2 based boards using UART3 */ - DEBUG_LL_OMAP2(3, nokia_n800); - DEBUG_LL_OMAP2(3, nokia_n810); - DEBUG_LL_OMAP2(3, nokia_n810_wimax); - - /* omap3 based boards using UART1 */ - DEBUG_LL_OMAP2(1, omap3evm); - DEBUG_LL_OMAP3(1, omap_3430sdp); - DEBUG_LL_OMAP3(1, omap_3630sdp); - DEBUG_LL_OMAP3(1, omap3530_lv_som); - DEBUG_LL_OMAP3(1, omap3_torpedo); - - /* omap3 based boards using UART3 */ - DEBUG_LL_OMAP3(3, cm_t35); - DEBUG_LL_OMAP3(3, cm_t3517); - DEBUG_LL_OMAP3(3, cm_t3730); - DEBUG_LL_OMAP3(3, craneboard); - DEBUG_LL_OMAP3(3, devkit8000); - DEBUG_LL_OMAP3(3, igep0020); - DEBUG_LL_OMAP3(3, igep0030); - DEBUG_LL_OMAP3(3, nokia_rm680); - DEBUG_LL_OMAP3(3, nokia_rm696); - DEBUG_LL_OMAP3(3, nokia_rx51); - DEBUG_LL_OMAP3(3, omap3517evm); - DEBUG_LL_OMAP3(3, omap3_beagle); - DEBUG_LL_OMAP3(3, omap3_pandora); - DEBUG_LL_OMAP3(3, omap_ldp); - DEBUG_LL_OMAP3(3, overo); - DEBUG_LL_OMAP3(3, touchbook); - - /* omap4 based boards using UART3 */ - DEBUG_LL_OMAP4(3, omap_4430sdp); - DEBUG_LL_OMAP4(3, omap4_panda); - - /* omap5 based boards using UART3 */ - DEBUG_LL_OMAP5(3, omap5_sevm); - - /* zoom2/3 external uart */ - DEBUG_LL_ZOOM(omap_zoom2); - DEBUG_LL_ZOOM(omap_zoom3); - - /* TI8168 base boards using UART3 */ - DEBUG_LL_TI81XX(3, ti8168evm); - - /* TI8148 base boards using UART1 */ - DEBUG_LL_TI81XX(1, ti8148evm); - - /* AM33XX base boards using UART1 */ - DEBUG_LL_AM33XX(1, am335xevm); - } while (0); -} - -/* - * nothing to do - */ -#define arch_decomp_wdog() diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h deleted file mode 100644 index 87ee140fefaa..000000000000 --- a/arch/arm/plat-omap/include/plat/usb.h +++ /dev/null @@ -1,179 +0,0 @@ -// include/asm-arm/mach-omap/usb.h - -#ifndef __ASM_ARCH_OMAP_USB_H -#define __ASM_ARCH_OMAP_USB_H - -#include <linux/io.h> -#include <linux/platform_device.h> -#include <linux/usb/musb.h> - -#define OMAP3_HS_USB_PORTS 3 - -enum usbhs_omap_port_mode { - OMAP_USBHS_PORT_MODE_UNUSED, - OMAP_EHCI_PORT_MODE_PHY, - OMAP_EHCI_PORT_MODE_TLL, - OMAP_EHCI_PORT_MODE_HSIC, - OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0, - OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM, - OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0, - OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM, - OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0, - OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM, - OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0, - OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM, - OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0, - OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM -}; - -struct usbhs_omap_board_data { - enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; - - /* have to be valid if phy_reset is true and portx is in phy mode */ - int reset_gpio_port[OMAP3_HS_USB_PORTS]; - - /* Set this to true for ES2.x silicon */ - unsigned es2_compatibility:1; - - unsigned phy_reset:1; - - /* - * Regulators for USB PHYs. - * Each PHY can have a separate regulator. - */ - struct regulator *regulator[OMAP3_HS_USB_PORTS]; -}; - -#ifdef CONFIG_ARCH_OMAP2PLUS - -struct ehci_hcd_omap_platform_data { - enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; - int reset_gpio_port[OMAP3_HS_USB_PORTS]; - struct regulator *regulator[OMAP3_HS_USB_PORTS]; - unsigned phy_reset:1; -}; - -struct ohci_hcd_omap_platform_data { - enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; - unsigned es2_compatibility:1; -}; - -struct usbhs_omap_platform_data { - enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; - - struct ehci_hcd_omap_platform_data *ehci_data; - struct ohci_hcd_omap_platform_data *ohci_data; -}; - -struct usbtll_omap_platform_data { - enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; -}; -/*-------------------------------------------------------------------------*/ - -struct omap_musb_board_data { - u8 interface_type; - u8 mode; - u16 power; - unsigned extvbus:1; - void (*set_phy_power)(u8 on); - void (*clear_irq)(void); - void (*set_mode)(u8 mode); - void (*reset)(void); -}; - -enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI}; - -extern void usb_musb_init(struct omap_musb_board_data *board_data); - -extern void usbhs_init(const struct usbhs_omap_board_data *pdata); -extern int omap_tll_enable(void); -extern int omap_tll_disable(void); - -extern int omap4430_phy_power(struct device *dev, int ID, int on); -extern int omap4430_phy_set_clk(struct device *dev, int on); -extern int omap4430_phy_init(struct device *dev); -extern int omap4430_phy_exit(struct device *dev); -extern int omap4430_phy_suspend(struct device *dev, int suspend); - -#endif - -extern void am35x_musb_reset(void); -extern void am35x_musb_phy_power(u8 on); -extern void am35x_musb_clear_irq(void); -extern void am35x_set_mode(u8 musb_mode); -extern void ti81xx_musb_phy_power(u8 on); - -/* AM35x */ -/* USB 2.0 PHY Control */ -#define CONF2_PHY_GPIOMODE (1 << 23) -#define CONF2_OTGMODE (3 << 14) -#define CONF2_NO_OVERRIDE (0 << 14) -#define CONF2_FORCE_HOST (1 << 14) -#define CONF2_FORCE_DEVICE (2 << 14) -#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14) -#define CONF2_SESENDEN (1 << 13) -#define CONF2_VBDTCTEN (1 << 12) -#define CONF2_REFFREQ_24MHZ (2 << 8) -#define CONF2_REFFREQ_26MHZ (7 << 8) -#define CONF2_REFFREQ_13MHZ (6 << 8) -#define CONF2_REFFREQ (0xf << 8) -#define CONF2_PHYCLKGD (1 << 7) -#define CONF2_VBUSSENSE (1 << 6) -#define CONF2_PHY_PLLON (1 << 5) -#define CONF2_RESET (1 << 4) -#define CONF2_PHYPWRDN (1 << 3) -#define CONF2_OTGPWRDN (1 << 2) -#define CONF2_DATPOL (1 << 1) - -/* TI81XX specific definitions */ -#define USBCTRL0 0x620 -#define USBSTAT0 0x624 - -/* TI816X PHY controls bits */ -#define TI816X_USBPHY0_NORMAL_MODE (1 << 0) -#define TI816X_USBPHY_REFCLK_OSC (1 << 8) - -/* TI814X PHY controls bits */ -#define USBPHY_CM_PWRDN (1 << 0) -#define USBPHY_OTG_PWRDN (1 << 1) -#define USBPHY_CHGDET_DIS (1 << 2) -#define USBPHY_CHGDET_RSTRT (1 << 3) -#define USBPHY_SRCONDM (1 << 4) -#define USBPHY_SINKONDP (1 << 5) -#define USBPHY_CHGISINK_EN (1 << 6) -#define USBPHY_CHGVSRC_EN (1 << 7) -#define USBPHY_DMPULLUP (1 << 8) -#define USBPHY_DPPULLUP (1 << 9) -#define USBPHY_CDET_EXTCTL (1 << 10) -#define USBPHY_GPIO_MODE (1 << 12) -#define USBPHY_DPOPBUFCTL (1 << 13) -#define USBPHY_DMOPBUFCTL (1 << 14) -#define USBPHY_DPINPUT (1 << 15) -#define USBPHY_DMINPUT (1 << 16) -#define USBPHY_DPGPIO_PD (1 << 17) -#define USBPHY_DMGPIO_PD (1 << 18) -#define USBPHY_OTGVDET_EN (1 << 19) -#define USBPHY_OTGSESSEND_EN (1 << 20) -#define USBPHY_DATA_POLARITY (1 << 23) - -#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB) -u32 omap1_usb0_init(unsigned nwires, unsigned is_device); -u32 omap1_usb1_init(unsigned nwires); -u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup); -#else -static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device) -{ - return 0; -} -static inline u32 omap1_usb1_init(unsigned nwires) -{ - return 0; - -} -static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup) -{ - return 0; -} -#endif - -#endif /* __ASM_ARCH_OMAP_USB_H */ diff --git a/arch/arm/plat-omap/include/plat/vrfb.h b/arch/arm/plat-omap/include/plat/vrfb.h deleted file mode 100644 index 3792bdea2f6d..000000000000 --- a/arch/arm/plat-omap/include/plat/vrfb.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * VRFB Rotation Engine - * - * Copyright (C) 2009 Nokia Corporation - * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - -#ifndef __OMAP_VRFB_H__ -#define __OMAP_VRFB_H__ - -#define OMAP_VRFB_LINE_LEN 2048 - -struct vrfb { - u8 context; - void __iomem *vaddr[4]; - unsigned long paddr[4]; - u16 xres; - u16 yres; - u16 xoffset; - u16 yoffset; - u8 bytespp; - bool yuv_mode; -}; - -#ifdef CONFIG_OMAP2_VRFB -extern int omap_vrfb_request_ctx(struct vrfb *vrfb); -extern void omap_vrfb_release_ctx(struct vrfb *vrfb); -extern void omap_vrfb_adjust_size(u16 *width, u16 *height, - u8 bytespp); -extern u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp); -extern u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp); -extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr, - u16 width, u16 height, - unsigned bytespp, bool yuv_mode); -extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot); -extern void omap_vrfb_restore_context(void); - -#else -static inline int omap_vrfb_request_ctx(struct vrfb *vrfb) { return 0; } -static inline void omap_vrfb_release_ctx(struct vrfb *vrfb) {} -static inline void omap_vrfb_adjust_size(u16 *width, u16 *height, - u8 bytespp) {} -static inline u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp) - { return 0; } -static inline u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp) - { return 0; } -static inline void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr, - u16 width, u16 height, unsigned bytespp, bool yuv_mode) {} -static inline int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot) - { return 0; } -static inline void omap_vrfb_restore_context(void) {} -#endif -#endif /* __VRFB_H */ diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c index 9722f418ae1f..198685b894b0 100644 --- a/arch/arm/plat-omap/omap-pm-noop.c +++ b/arch/arm/plat-omap/omap-pm-noop.c @@ -22,9 +22,8 @@ #include <linux/device.h> #include <linux/platform_device.h> -/* Interface documentation is in mach/omap-pm.h */ -#include <plat/omap-pm.h> -#include <plat/omap_device.h> +#include "../mach-omap2/omap_device.h" +#include "../mach-omap2/omap-pm.h" static bool off_mode_enabled; static int dummy_context_loss_counter; diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 28acb383e7df..70dcc225157f 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -25,8 +25,8 @@ #include <asm/mach/map.h> -#include <plat/sram.h> -#include <plat/cpu.h> +#include "../mach-omap1/soc.h" +#include "../mach-omap2/soc.h" #include "sram.h" diff --git a/arch/arm/plat-omap/sram.h b/arch/arm/plat-omap/sram.h index 29b43ef97f20..cefda2e09869 100644 --- a/arch/arm/plat-omap/sram.h +++ b/arch/arm/plat-omap/sram.h @@ -1,6 +1,107 @@ -#ifndef __PLAT_OMAP_SRAM_H__ -#define __PLAT_OMAP_SRAM_H__ +/* + * arch/arm/plat-omap/include/mach/sram.h + * + * Interface for functions that need to be run in internal SRAM + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ -extern int __init omap_sram_init(void); +#ifndef __ARCH_ARM_OMAP_SRAM_H +#define __ARCH_ARM_OMAP_SRAM_H -#endif /* __PLAT_OMAP_SRAM_H__ */ +#ifndef __ASSEMBLY__ +#include <asm/fncpy.h> + +int __init omap_sram_init(void); + +extern void *omap_sram_push_address(unsigned long size); + +/* Macro to push a function to the internal SRAM, using the fncpy API */ +#define omap_sram_push(funcp, size) ({ \ + typeof(&(funcp)) _res = NULL; \ + void *_sram_address = omap_sram_push_address(size); \ + if (_sram_address) \ + _res = fncpy(_sram_address, &(funcp), size); \ + _res; \ +}) + +extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); + +extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, + u32 base_cs, u32 force_unlock); +extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, + u32 mem_type); +extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); + +extern u32 omap3_configure_core_dpll( + u32 m2, u32 unlock_dll, u32 f, u32 inc, + u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0, + u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0, + u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1, + u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1); +extern void omap3_sram_restore_context(void); + +/* Do not use these */ +extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); +extern unsigned long omap1_sram_reprogram_clock_sz; + +extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl); +extern unsigned long omap24xx_sram_reprogram_clock_sz; + +extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, + u32 base_cs, u32 force_unlock); +extern unsigned long omap242x_sram_ddr_init_sz; + +extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, + int bypass); +extern unsigned long omap242x_sram_set_prcm_sz; + +extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, + u32 mem_type); +extern unsigned long omap242x_sram_reprogram_sdrc_sz; + + +extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, + u32 base_cs, u32 force_unlock); +extern unsigned long omap243x_sram_ddr_init_sz; + +extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, + int bypass); +extern unsigned long omap243x_sram_set_prcm_sz; + +extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, + u32 mem_type); +extern unsigned long omap243x_sram_reprogram_sdrc_sz; + +extern u32 omap3_sram_configure_core_dpll( + u32 m2, u32 unlock_dll, u32 f, u32 inc, + u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0, + u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0, + u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1, + u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1); +extern unsigned long omap3_sram_configure_core_dpll_sz; + +#ifdef CONFIG_PM +extern void omap_push_sram_idle(void); +#else +static inline void omap_push_sram_idle(void) {} +#endif /* CONFIG_PM */ + +#endif /* __ASSEMBLY__ */ + +/* + * OMAP2+: define the SRAM PA addresses. + * Used by the SRAM management code and the idle sleep code. + */ +#define OMAP2_SRAM_PA 0x40200000 +#define OMAP3_SRAM_PA 0x40200000 +#ifdef CONFIG_OMAP4_ERRATA_I688 +#define OMAP4_SRAM_PA 0x40304000 +#define OMAP4_SRAM_VA 0xfe404000 +#else +#define OMAP4_SRAM_PA 0x40300000 +#endif +#define AM33XX_SRAM_PA 0x40300000 +#endif |