diff options
Diffstat (limited to 'arch/arm')
564 files changed, 19764 insertions, 4738 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index bbac2867062d..218bf25b369a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -41,6 +41,7 @@ config ARM select CPU_PM if SUSPEND || CPU_IDLE select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS select DMA_DECLARE_COHERENT + select DMA_OPS select DMA_REMAP if MMU select EDAC_SUPPORT select EDAC_ATOMIC_SCRUB @@ -72,7 +73,6 @@ config ARM select HAVE_ARM_SMCCC if CPU_V7 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 select HAVE_CONTEXT_TRACKING - select HAVE_COPY_THREAD_TLS select HAVE_C_RECORDMCOUNT select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL select HAVE_DMA_CONTIGUOUS if MMU @@ -668,6 +668,8 @@ source "arch/arm/mach-mmp/Kconfig" source "arch/arm/mach-moxart/Kconfig" +source "arch/arm/mach-mstar/Kconfig" + source "arch/arm/mach-mv78xx0/Kconfig" source "arch/arm/mach-mvebu/Kconfig" @@ -1655,7 +1657,7 @@ config UACCESS_WITH_MEMCPY config SECCOMP bool prompt "Enable seccomp to safely compute untrusted bytecode" - ---help--- + help This kernel feature is useful for number crunching applications that may need to compute untrusted bytecode during their execution. By using pipes or other transports made available to @@ -1749,7 +1751,7 @@ config DEPRECATED_PARAM_STRUCT # TEXT and BSS so we preserve their values in the config files. config ZBOOT_ROM_TEXT hex "Compressed ROM boot loader base address" - default "0" + default 0x0 help The physical address at which the ROM-able zImage is to be placed in the target. Platforms which normally make use of @@ -1760,7 +1762,7 @@ config ZBOOT_ROM_TEXT config ZBOOT_ROM_BSS hex "Compressed ROM boot loader BSS address" - default "0" + default 0x0 help The base address of an area of read/write memory in the target for the ROM-able zImage which must be available while the @@ -1963,7 +1965,7 @@ config EFI select EFI_STUB select EFI_GENERIC_STUB select EFI_RUNTIME_WRAPPERS - ---help--- + help This option provides support for runtime services provided by UEFI firmware (such as non-volatile variables, realtime clock, and platform reset). A UEFI stub is also provided to @@ -2005,7 +2007,7 @@ comment "At least one emulation must be selected" config FPE_NWFPE bool "NWFPE math emulation" depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL - ---help--- + help Say Y to include the NWFPE floating point emulator in the kernel. This is necessary to run most binaries. Linux does not currently support floating point hardware so you need to say Y here even if @@ -2029,7 +2031,7 @@ config FPE_NWFPE_XP config FPE_FASTFPE bool "FastFPE math emulation (EXPERIMENTAL)" depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 - ---help--- + help Say Y here to include the FAST floating point emulator in the kernel. This is an experimental much faster emulator which now also has full precision for the mantissa. It does not support any exceptions. diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 26a158e35e2c..80000a66a4e3 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -9,7 +9,7 @@ config ARM_PTDUMP_DEBUGFS depends on MMU select ARM_PTDUMP_CORE select DEBUG_FS - ---help--- + help Say Y here if you want to show the kernel pagetable layout in a debugfs file. This information is only useful for kernel developers who are working in architecture specific areas of the kernel. @@ -21,7 +21,7 @@ config DEBUG_WX bool "Warn on W+X mappings at boot" depends on MMU select ARM_PTDUMP_CORE - ---help--- + help Generate a warning if any W+X mappings are found at boot. This is useful for discovering cases where the kernel is leaving diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 59fde2d598d8..e7f4ca060c0f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -197,6 +197,7 @@ machine-$(CONFIG_ARCH_MXC) += imx machine-$(CONFIG_ARCH_MEDIATEK) += mediatek machine-$(CONFIG_ARCH_MILBEAUT) += milbeaut machine-$(CONFIG_ARCH_MXS) += mxs +machine-$(CONFIG_ARCH_MSTARV7) += mstar machine-$(CONFIG_ARCH_NOMADIK) += nomadik machine-$(CONFIG_ARCH_NPCM) += npcm machine-$(CONFIG_ARCH_NSPIRE) += nspire diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index c79db44ba128..434a16982e34 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -1410,7 +1410,11 @@ memdump: mov r12, r0 __hyp_reentry_vectors: W(b) . @ reset W(b) . @ undef +#ifdef CONFIG_EFI_STUB + W(b) __enter_kernel_from_hyp @ hvc from HYP +#else W(b) . @ svc +#endif W(b) . @ pabort W(b) . @ dabort W(b) __enter_kernel @ hyp @@ -1429,14 +1433,72 @@ __enter_kernel: reloc_code_end: #ifdef CONFIG_EFI_STUB +__enter_kernel_from_hyp: + mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR + bic r0, r0, #0x5 @ disable MMU and caches + mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR + isb + b __enter_kernel + ENTRY(efi_enter_kernel) mov r4, r0 @ preserve image base mov r8, r1 @ preserve DT pointer + ARM( adrl r0, call_cache_fn ) + THUMB( adr r0, call_cache_fn ) + adr r1, 0f @ clean the region of code we + bl cache_clean_flush @ may run with the MMU off + +#ifdef CONFIG_ARM_VIRT_EXT + @ + @ The EFI spec does not support booting on ARM in HYP mode, + @ since it mandates that the MMU and caches are on, with all + @ 32-bit addressable DRAM mapped 1:1 using short descriptors. + @ + @ While the EDK2 reference implementation adheres to this, + @ U-Boot might decide to enter the EFI stub in HYP mode + @ anyway, with the MMU and caches either on or off. + @ + mrs r0, cpsr @ get the current mode + msr spsr_cxsf, r0 @ record boot mode + and r0, r0, #MODE_MASK @ are we running in HYP mode? + cmp r0, #HYP_MODE + bne .Lefi_svc + + mrc p15, 4, r1, c1, c0, 0 @ read HSCTLR + tst r1, #0x1 @ MMU enabled at HYP? + beq 1f + + @ + @ When running in HYP mode with the caches on, we're better + @ off just carrying on using the cached 1:1 mapping that the + @ firmware provided. Set up the HYP vectors so HVC instructions + @ issued from HYP mode take us to the correct handler code. We + @ will disable the MMU before jumping to the kernel proper. + @ + adr r0, __hyp_reentry_vectors + mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR) + isb + b .Lefi_hyp + + @ + @ When running in HYP mode with the caches off, we need to drop + @ into SVC mode now, and let the decompressor set up its cached + @ 1:1 mapping as usual. + @ +1: mov r9, r4 @ preserve image base + bl __hyp_stub_install @ install HYP stub vectors + safe_svcmode_maskall r1 @ drop to SVC mode + msr spsr_cxsf, r0 @ record boot mode + orr r4, r9, #1 @ restore image base and set LSB + b .Lefi_hyp +.Lefi_svc: +#endif mrc p15, 0, r0, c1, c0, 0 @ read SCTLR tst r0, #0x1 @ MMU enabled? orreq r4, r4, #1 @ set LSB if not +.Lefi_hyp: mov r0, r8 @ DT start add r1, r8, r2 @ DT end bl cache_clean_flush diff --git a/arch/arm/boot/deflate_xip_data.sh b/arch/arm/boot/deflate_xip_data.sh index 739f0464321e..304495c3c2c5 100755 --- a/arch/arm/boot/deflate_xip_data.sh +++ b/arch/arm/boot/deflate_xip_data.sh @@ -56,7 +56,7 @@ trap 'rm -f "$XIPIMAGE.tmp"; exit 1' 1 2 3 # substitute the data section by a compressed version $DD if="$XIPIMAGE" count=$data_start iflag=count_bytes of="$XIPIMAGE.tmp" $DD if="$XIPIMAGE" skip=$data_start iflag=skip_bytes | -$_GZIP -9 >> "$XIPIMAGE.tmp" +$KGZIP -9 >> "$XIPIMAGE.tmp" # replace kernel binary mv -f "$XIPIMAGE.tmp" "$XIPIMAGE" diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e6a1cac0bfc7..4572db3fa5ae 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -455,6 +455,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-pico-hobbit.dtb \ imx6dl-pico-nymph.dtb \ imx6dl-pico-pi.dtb \ + imx6dl-prtrvt.dtb \ + imx6dl-prtvt7.dtb \ imx6dl-rex-basic.dtb \ imx6dl-riotboard.dtb \ imx6dl-sabreauto.dtb \ @@ -543,6 +545,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-pico-nymph.dtb \ imx6q-pico-pi.dtb \ imx6q-pistachio.dtb \ + imx6q-prti6q.dtb \ + imx6q-prtwd2.dtb \ imx6q-rex-pro.dtb \ imx6q-sabreauto.dtb \ imx6q-sabrelite.dtb \ @@ -592,6 +596,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-sdb-reva.dtb \ imx6sx-sdb-sai.dtb \ imx6sx-sdb.dtb \ + imx6sx-sdb-mqs.dtb \ imx6sx-softing-vining-2000.dtb \ imx6sx-udoo-neo-basic.dtb \ imx6sx-udoo-neo-extended.dtb \ @@ -617,6 +622,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-14x14-evk.dtb \ imx6ull-colibri-eval-v3.dtb \ imx6ull-colibri-wifi-eval-v3.dtb \ + imx6ull-myir-mys-6ulx-eval.dtb \ imx6ull-opos6uldev.dtb \ imx6ull-phytec-segin-ff-rdk-nand.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ @@ -890,6 +896,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-ipq4019-ap.dk07.1-c1.dtb \ qcom-ipq4019-ap.dk07.1-c2.dtb \ qcom-ipq8064-ap148.dtb \ + qcom-ipq8064-rb3011.dtb \ qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb \ qcom-msm8974-fairphone-fp2.dtb \ @@ -927,6 +934,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ r8a7742-iwg21d-q7.dtb \ + r8a7742-iwg21d-q7-dbcm-ca.dtb \ r8a7743-iwg20d-q7.dtb \ r8a7743-iwg20d-q7-dbcm-ca.dtb \ r8a7743-sk-rzg1m.dtb \ @@ -974,6 +982,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-popmetal.dtb \ rk3288-r89.dtb \ rk3288-rock2-square.dtb \ + rk3288-rock-pi-n8.dtb \ rk3288-tinker.dtb \ rk3288-tinker-s.dtb \ rk3288-veyron-brain.dtb \ @@ -1197,6 +1206,7 @@ dtb-$(CONFIG_MACH_SUNIV) += \ dtb-$(CONFIG_ARCH_TANGO) += \ tango4-vantage-1172.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ + tegra20-acer-a500-picasso.dtb \ tegra20-harmony.dtb \ tegra20-colibri-eval-v3.dtb \ tegra20-colibri-iris.dtb \ @@ -1210,6 +1220,9 @@ dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-apalis-eval.dtb \ tegra30-apalis-v1.1-eval.dtb \ + tegra30-asus-nexus7-grouper-PM269.dtb \ + tegra30-asus-nexus7-grouper-E1565.dtb \ + tegra30-asus-nexus7-tilapia-E1565.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ @@ -1342,10 +1355,15 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt8127-moose.dtb \ mt8135-evbp1.dtb dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb +dtb-$(CONFIG_ARCH_MSTARV7) += \ + infinity-msc313-breadbee_crust.dtb \ + infinity3-msc313e-breadbee.dtb \ + mercury5-ssc8336n-midrived08.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2500-evb.dtb \ aspeed-ast2600-evb.dtb \ + aspeed-bmc-amd-ethanolx.dtb \ aspeed-bmc-arm-centriq2400-rep.dtb \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ aspeed-bmc-facebook-cmm.dtb \ diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts index 386d5f89978e..56915b6d818d 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /* diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts index b0df7256db13..d8d60398d803 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir3220.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /* diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts index d6aa46e8700e..8096d459b93f 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /* diff --git a/arch/arm/boot/dts/am335x-baltos-leds.dtsi b/arch/arm/boot/dts/am335x-baltos-leds.dtsi index 4e11a160d88f..9a79f727baf6 100644 --- a/arch/arm/boot/dts/am335x-baltos-leds.dtsi +++ b/arch/arm/boot/dts/am335x-baltos-leds.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /* diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi index 05e7b5d4a95b..b7f64c7ba83d 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/am335x-baltos.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /* @@ -369,7 +369,7 @@ &mmc2 { status = "okay"; vmmc-supply = <&wl12xx_vmmc>; - ti,non-removable; + non-removable; bus-width = <4>; cap-power-off-card; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 6c9187bc0f17..2d51d4bba6d4 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ / { diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index 43bfbce41049..b5d85ef51a02 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/am335x-boneblack-common.dtsi b/arch/arm/boot/dts/am335x-boneblack-common.dtsi index 91f93bc89716..64c3e9269f40 100644 --- a/arch/arm/boot/dts/am335x-boneblack-common.dtsi +++ b/arch/arm/boot/dts/am335x-boneblack-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/display/tda998x.h> @@ -22,6 +22,7 @@ pinctrl-0 = <&emmc_pins>; bus-width = <8>; status = "okay"; + non-removable; }; &am33xx_pinmux { diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/am335x-boneblack-wireless.dts index 3124d94c0b3c..86cad9912906 100644 --- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts +++ b/arch/arm/boot/dts/am335x-boneblack-wireless.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -75,7 +75,6 @@ bus-width = <4>; non-removable; cap-power-off-card; - ti,needs-special-hs-handling; keep-power-in-suspend; pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins &wl18xx_pins>; diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts index d3928662aed4..b4feb85e171a 100644 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ b/arch/arm/boot/dts/am335x-boneblack.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -23,3 +23,147 @@ opp-supported-hw = <0x06 0x0100>; }; }; + +&gpio0 { + gpio-line-names = + "[ethernet]", + "[ethernet]", + "P9_22 [spi0_sclk]", + "P9_21 [spi0_d0]", + "P9_18 [spi0_d1]", + "P9_17 [spi0_cs0]", + "[sd card]", + "P9_42A [ecappwm0]", + "P8_35 [hdmi]", + "P8_33 [hdmi]", + "P8_31 [hdmi]", + "P8_32 [hdmi]", + "P9_20 [i2c2_sda]", + "P9_19 [i2c2_scl]", + "P9_26 [uart1_rxd]", + "P9_24 [uart1_txd]", + "[ethernet]", + "[ethernet]", + "[usb]", + "[hdmi]", + "P9_41B", + "[ethernet]", + "P8_19 [ehrpwm2a]", + "P8_13 [ehrpwm2b]", + "[NC]", + "[NC]", + "P8_14", + "P8_17", + "[ethernet]", + "[ethernet]", + "P9_11 [uart4_rxd]", + "P9_13 [uart4_txd]"; +}; + +&gpio1 { + gpio-line-names = + "P8_25 [emmc]", + "[emmc]", + "P8_5 [emmc]", + "P8_6 [emmc]", + "P8_23 [emmc]", + "P8_22 [emmc]", + "P8_3 [emmc]", + "P8_4 [emmc]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "P8_12", + "P8_11", + "P8_16", + "P8_15", + "P9_15A", + "P9_23", + "P9_14 [ehrpwm1a]", + "P9_16 [ehrpwm1b]", + "[emmc]", + "[usr0 led]", + "[usr1 led]", + "[usr2 led]", + "[usr3 led]", + "[hdmi]", + "[usb]", + "[hdmi audio]", + "P9_12", + "P8_26", + "P8_21 [emmc]", + "P8_20 [emmc]"; +}; + +&gpio2 { + gpio-line-names = + "P9_15B", + "P8_18", + "P8_7", + "P8_8", + "P8_10", + "P8_9", + "P8_45 [hdmi]", + "P8_46 [hdmi]", + "P8_43 [hdmi]", + "P8_44 [hdmi]", + "P8_41 [hdmi]", + "P8_42 [hdmi]", + "P8_39 [hdmi]", + "P8_40 [hdmi]", + "P8_37 [hdmi]", + "P8_38 [hdmi]", + "P8_36 [hdmi]", + "P8_34 [hdmi]", + "[ethernet]", + "[ethernet]", + "[ethernet]", + "[ethernet]", + "P8_27 [hdmi]", + "P8_29 [hdmi]", + "P8_28 [hdmi]", + "P8_30 [hdmi]", + "[emmc]", + "[emmc]", + "[emmc]", + "[emmc]", + "[emmc]", + "[emmc]"; +}; + +&gpio3 { + gpio-line-names = + "[ethernet]", + "[ethernet]", + "[ethernet]", + "[ethernet]", + "[ethernet]", + "[i2c0]", + "[i2c0]", + "[emu]", + "[emu]", + "[ethernet]", + "[ethernet]", + "[NC]", + "[NC]", + "[usb]", + "P9_31 [spi1_sclk]", + "P9_29 [spi1_d0]", + "P9_30 [spi1_d1]", + "P9_28 [spi1_cs0]", + "P9_42B [ecappwm0]", + "P9_27", + "P9_41A", + "P9_25", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "[NC]"; +}; diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts index 5811fb8d4fdf..c696d57cf364 100644 --- a/arch/arm/boot/dts/am335x-boneblue.dts +++ b/arch/arm/boot/dts/am335x-boneblue.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -367,7 +367,6 @@ bus-width = <4>; non-removable; cap-power-off-card; - ti,needs-special-hs-handling; keep-power-in-suspend; pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins &wl18xx_pins>; diff --git a/arch/arm/boot/dts/am335x-bonegreen-common.dtsi b/arch/arm/boot/dts/am335x-bonegreen-common.dtsi index 7a8826633cef..9f7fb63744d0 100644 --- a/arch/arm/boot/dts/am335x-bonegreen-common.dtsi +++ b/arch/arm/boot/dts/am335x-bonegreen-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ &ldo3_reg { diff --git a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts index 4092cd193b8a..7615327d906a 100644 --- a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts +++ b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -75,7 +75,6 @@ bus-width = <4>; non-removable; cap-power-off-card; - ti,needs-special-hs-handling; keep-power-in-suspend; pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins &wl18xx_pins>; diff --git a/arch/arm/boot/dts/am335x-bonegreen.dts b/arch/arm/boot/dts/am335x-bonegreen.dts index c12bb0717779..18cc0f49e999 100644 --- a/arch/arm/boot/dts/am335x-bonegreen.dts +++ b/arch/arm/boot/dts/am335x-bonegreen.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts index b14a2759c69b..5660b5f6942d 100644 --- a/arch/arm/boot/dts/am335x-chiliboard.dts +++ b/arch/arm/boot/dts/am335x-chiliboard.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/ + * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/ * Author: Rostislav Lisovy <lisovy@jablotron.cz> */ /dts-v1/; diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi b/arch/arm/boot/dts/am335x-chilisom.dtsi index b31e2f7a4ad9..43b61e43ed1e 100644 --- a/arch/arm/boot/dts/am335x-chilisom.dtsi +++ b/arch/arm/boot/dts/am335x-chilisom.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/ + * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/ * Author: Rostislav Lisovy <lisovy@jablotron.cz> */ #include "am33xx.dtsi" diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 68252dab32c3..12dffccd1ffd 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -743,8 +743,7 @@ bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins &wlan_pins>; - ti,non-removable; - ti,needs-special-hs-handling; + non-removable; cap-power-off-card; keep-power-in-suspend; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 32f515a295ee..b43b94122d3c 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /* @@ -655,7 +655,7 @@ &mmc2 { status = "okay"; vmmc-supply = <&wl12xx_vmmc>; - ti,non-removable; + non-removable; bus-width = <4>; cap-power-off-card; keep-power-in-suspend; diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index 0ebe9e2c150e..1918766c1f80 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * Copyright (C) 2018 Robert Bosch Power Tools GmbH */ /dts-v1/; diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index 021eb57261fe..b958ab56a412 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ */ /* diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts index fef582852820..cd55f11260ea 100644 --- a/arch/arm/boot/dts/am335x-lxm.dts +++ b/arch/arm/boot/dts/am335x-lxm.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014 NovaTech LLC - http://www.novatechweb.com + * Copyright (C) 2014 NovaTech LLC - https://www.novatechweb.com */ /dts-v1/; @@ -339,7 +339,7 @@ pinctrl-0 = <&emmc_pins>; vmmc-supply = <&vmmcsd_fixed>; bus-width = <8>; - ti,non-removable; + non-removable; status = "okay"; }; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi index 6495a125c01f..4e90f9c23d2e 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi @@ -159,7 +159,7 @@ vmmc-supply = <&vmmcsd_fixed>; bus-width = <8>; pinctrl-0 = <&mmc1_pins_default>; - ti,non-removable; + non-removable; status = "okay"; }; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts index 244df9c5a537..f03e72cada41 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts +++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts @@ -451,7 +451,7 @@ vmmc-supply = <&vmmcsd_fixed>; bus-width = <8>; pinctrl-0 = <&mmc2_pins_default>; - ti,non-removable; + non-removable; status = "okay"; }; diff --git a/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts b/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts index 1e4dbc85c120..8303b832aa50 100644 --- a/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts +++ b/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /* diff --git a/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts b/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts index 9a6cd8ef821f..f8e0e95a751f 100644 --- a/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts +++ b/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /* diff --git a/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts b/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts index 2298563f7334..a4e137527215 100644 --- a/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts +++ b/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /* diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts index 1d2902083483..f841afb27844 100644 --- a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts +++ b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts @@ -1,5 +1,5 @@ //SPDX-License-Identifier: GPL-2.0 -/* Copyright (C) 2018 Octavo Systems LLC - http://www.octavosystems.com/ +/* Copyright (C) 2018 Octavo Systems LLC - https://www.octavosystems.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -107,7 +107,7 @@ * below to "crossed" and uncomment the video-ports -property * in tda19988 node. * AM335x errata for wiring: - * http://www.ti.com/lit/er/sprz360i/sprz360i.pdf + * https://www.ti.com/lit/er/sprz360i/sprz360i.pdf */ blue-and-red-wiring = "straight"; diff --git a/arch/arm/boot/dts/am335x-osd335x-common.dtsi b/arch/arm/boot/dts/am335x-osd335x-common.dtsi index a8b6842489f7..2888b15999ee 100644 --- a/arch/arm/boot/dts/am335x-osd335x-common.dtsi +++ b/arch/arm/boot/dts/am335x-osd335x-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * * Author: Robert Nelson <robertcnelson@gmail.com> */ diff --git a/arch/arm/boot/dts/am335x-pdu001.dts b/arch/arm/boot/dts/am335x-pdu001.dts index e4dcfa087a1b..d41a5ffd83cf 100644 --- a/arch/arm/boot/dts/am335x-pdu001.dts +++ b/arch/arm/boot/dts/am335x-pdu001.dts @@ -5,7 +5,7 @@ * * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts index 6d7608d9377b..f9a027b47962 100644 --- a/arch/arm/boot/dts/am335x-pepper.dts +++ b/arch/arm/boot/dts/am335x-pepper.dts @@ -341,7 +341,7 @@ pinctrl-0 = <&emmc_pins>; vmmc-supply = <&ldo3_reg>; bus-width = <8>; - ti,non-removable; + non-removable; }; &mmc3 { @@ -351,7 +351,7 @@ pinctrl-0 = <&wireless_pins>; vmmmc-supply = <&v3v3c_reg>; bus-width = <4>; - ti,non-removable; + non-removable; dmas = <&edma_xbar 12 0 1 &edma_xbar 13 0 2>; dma-names = "tx", "rx"; diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi index 3d0672b53d77..7e46b4c02709 100644 --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi @@ -69,7 +69,7 @@ pinctrl-0 = <&emmc_pins>; vmmc-supply = <&vmmc_reg>; bus-width = <8>; - ti,non-removable; + non-removable; status = "disabled"; }; diff --git a/arch/arm/boot/dts/am335x-pocketbeagle.dts b/arch/arm/boot/dts/am335x-pocketbeagle.dts index 4da719098028..d526c5941c9b 100644 --- a/arch/arm/boot/dts/am335x-pocketbeagle.dts +++ b/arch/arm/boot/dts/am335x-pocketbeagle.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * * Author: Robert Nelson <robertcnelson@gmail.com> */ @@ -59,7 +59,276 @@ }; }; +&gpio0 { + gpio-line-names = + "[NC]", + "[NC]", + "P1.08 [SPI0_CLK]", + "P1.10 [SPI0_MISO]", + "P1.12 [SPI0_MOSI]", + "P1.06 [SPI0_CS]", + "[MMC0_CD]", + "P2.29 [SPI1_CLK]", + "[SYSBOOT]", + "[SYSBOOT]", + "[SYSBOOT]", + "[SYSBOOT]", + "P1.26 [I2C2_SDA]", + "P1.28 [I2C2_SCL]", + "P2.11 [I2C1_SDA]", + "P2.09 [I2C1_SCL]", + "[NC]", + "[NC]", + "[NC]", + "P2.31 [SPI1_CS]", + "P1.20 [PRU0.16]", + "[NC]", + "[NC]", + "P2.03", + "[NC]", + "[NC]", + "P1.34", + "P2.19", + "[NC]", + "[NC]", + "P2.05 [UART4_RX]", + "P2.07 [UART4_TX]"; +}; + +&gpio1 { + gpio-line-names = + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "P2.25 [SPI1_MOSI]", + "P1.32 [UART0_RX]", + "P1.30 [UART0_TX]", + "P2.24", + "P2.33", + "P2.22", + "P2.18", + "[NC]", + "[NC]", + "P2.01 [PWM1A]", + "[NC]", + "P2.10", + "[USR LED 0]", + "[USR LED 1]", + "[USR LED 2]", + "[USR LED 3]", + "P2.06", + "P2.04", + "P2.02", + "P2.08", + "[NC]", + "[NC]", + "[NC]"; +}; + +&gpio2 { + gpio-line-names = + "P2.20", + "P2.17", + "[NC]", + "[NC]", + "[NC]", + "[EEPROM_WP]", + "[SYSBOOT]", + "[SYSBOOT]", + "[SYSBOOT]", + "[SYSBOOT]", + "[SYSBOOT]", + "[SYSBOOT]", + "[SYSBOOT]", + "[SYSBOOT]", + "[SYSBOOT]", + "[SYSBOOT]", + "[SYSBOOT]", + "[SYSBOOT]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "P2.35 [AIN5]", + "P1.02 [AIN6]", + "P1.35 [PRU1.10]", + "P1.04 [PRU1.11]", + "[MMC0_DAT3]", + "[MMC0_DAT2]", + "[MMC0_DAT1]", + "[MMC0_DAT0]", + "[MMC0_CLK]", + "[MMC0_CMD]"; +}; + +&gpio3 { + gpio-line-names = + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "[I2C0_SDA]", + "[I2C0_SCL]", + "[JTAG]", + "[JTAG]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "P1.03 [USB1]", + "P1.36 [PWM0A]", + "P1.33 [PRU0.1]", + "P2.32 [PRU0.2]", + "P2.30 [PRU0.3]", + "P1.31 [PRU0.4]", + "P2.34 [PRU0.5]", + "P2.28 [PRU0.6]", + "P1.29 [PRU0.7]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "[NC]", + "[NC]"; +}; + &am33xx_pinmux { + + pinctrl-names = "default"; + + pinctrl-0 = < &P2_03_gpio &P1_34_gpio &P2_19_gpio &P2_24_gpio + &P2_33_gpio &P2_22_gpio &P2_18_gpio &P2_10_gpio + &P2_06_gpio &P2_04_gpio &P2_02_gpio &P2_08_gpio + &P2_17_gpio >; + + /* P2_03 (ZCZ ball T10) gpio0_23 0x824 PIN 9 */ + P2_03_gpio: pinmux_P2_03_gpio { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P1_34 (ZCZ ball T11) gpio0_26 0x828 PIN 10 */ + P1_34_gpio: pinmux_P1_34_gpio { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_19 (ZCZ ball U12) gpio0_27 0x82c PIN 11 */ + P2_19_gpio: pinmux_P2_19_gpio { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_24 (ZCZ ball T12) gpio1_12 0x830 PIN 12 */ + P2_24_gpio: pinmux_P2_24_gpio { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_33 (ZCZ ball R12) gpio1_13 0x834 PIN 13 */ + P2_33_gpio: pinmux_P2_33_gpio { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_22 (ZCZ ball V13) gpio1_14 0x838 PIN 14 */ + P2_22_gpio: pinmux_P2_22_gpio { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_18 (ZCZ ball U13) gpio1_15 0x83c PIN 15 */ + P2_18_gpio: pinmux_P2_18_gpio { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_10 (ZCZ ball R14) gpio1_20 0x850 PIN 20 */ + P2_10_gpio: pinmux_P2_10_gpio { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_06 (ZCZ ball U16) gpio1_25 0x864 PIN 25 */ + P2_06_gpio: pinmux_P2_06_gpio { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_04 (ZCZ ball T16) gpio1_26 0x868 PIN 26 */ + P2_04_gpio: pinmux_P2_04_gpio { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_02 (ZCZ ball V17) gpio1_27 0x86c PIN 27 */ + P2_02_gpio: pinmux_P2_02_gpio { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + + /* P2_08 (ZCZ ball U18) gpio1_28 0x878 PIN 30 */ + P2_08_gpio: pinmux_P2_08_gpio { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x00 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x00 0x00 0x10 0x18>; + }; + + /* P2_17 (ZCZ ball V12) gpio2_1 0x88c PIN 35 */ + P2_17_gpio: pinmux_P2_17_gpio { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE7) + >; + pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; + pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; + }; + i2c2_pins: pinmux-i2c2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ @@ -88,7 +357,6 @@ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* (B12) mcasp0_aclkr.mmc0_sdwp */ >; }; diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/am335x-sancloud-bbe.dts index e5fdb7abb0d5..275ba339adf4 100644 --- a/arch/arm/boot/dts/am335x-sancloud-bbe.dts +++ b/arch/arm/boot/dts/am335x-sancloud-bbe.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 7ff11d6bf0f2..45de2ff6a777 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -151,6 +151,18 @@ gpio0: gpio@0 { compatible = "ti,omap4-gpio"; + gpio-ranges = <&am33xx_pinmux 0 82 8>, + <&am33xx_pinmux 8 52 4>, + <&am33xx_pinmux 12 94 4>, + <&am33xx_pinmux 16 71 2>, + <&am33xx_pinmux 18 135 1>, + <&am33xx_pinmux 19 108 2>, + <&am33xx_pinmux 21 73 1>, + <&am33xx_pinmux 22 8 2>, + <&am33xx_pinmux 26 10 2>, + <&am33xx_pinmux 28 74 1>, + <&am33xx_pinmux 29 81 1>, + <&am33xx_pinmux 30 28 2>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1296,6 +1308,10 @@ gpio1: gpio@0 { compatible = "ti,omap4-gpio"; + gpio-ranges = <&am33xx_pinmux 0 0 8>, + <&am33xx_pinmux 8 90 4>, + <&am33xx_pinmux 12 12 16>, + <&am33xx_pinmux 28 30 4>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1335,10 +1351,8 @@ ranges = <0x0 0x60000 0x1000>; mmc1: mmc@0 { - compatible = "ti,omap4-hsmmc"; - ti,dual-volt; + compatible = "ti,am335-sdhci"; ti,needs-special-reset; - ti,needs-special-hs-handling; dmas = <&edma_xbar 24 0 0 &edma_xbar 25 0 0>; dma-names = "tx", "rx"; @@ -1698,6 +1712,9 @@ gpio2: gpio@0 { compatible = "ti,omap4-gpio"; + gpio-ranges = <&am33xx_pinmux 0 34 18>, + <&am33xx_pinmux 18 77 4>, + <&am33xx_pinmux 22 56 10>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1731,6 +1748,11 @@ gpio3: gpio@0 { compatible = "ti,omap4-gpio"; + gpio-ranges = <&am33xx_pinmux 0 66 5>, + <&am33xx_pinmux 5 98 2>, + <&am33xx_pinmux 7 75 2>, + <&am33xx_pinmux 13 141 1>, + <&am33xx_pinmux 14 100 8>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1816,7 +1838,7 @@ ranges = <0x0 0xd8000 0x1000>; mmc2: mmc@0 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,am335-sdhci"; ti,needs-special-reset; dmas = <&edma 2 0 &edma 3 0>; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 3b177c9c4412..5cb4cc37cb6d 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for AM33XX SoC * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -322,10 +322,11 @@ ranges = <0x0 0x47810000 0x1000>; mmc3: mmc@0 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,am335-sdhci"; ti,needs-special-reset; interrupts = <29>; reg = <0x0 0x1000>; + status = "disabled"; }; }; @@ -335,7 +336,7 @@ <0x47400010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP2_SOFTRESET)>; + SYSC_OMAP4_SOFTRESET)>; ti,sysc-midle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; @@ -347,7 +348,7 @@ clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x47400000 0x5000>; + ranges = <0x0 0x47400000 0x8000>; usb0_phy: usb-phy@1300 { compatible = "ti,am335x-usb-phy"; diff --git a/arch/arm/boot/dts/am3517-craneboard.dts b/arch/arm/boot/dts/am3517-craneboard.dts index eb3517dabee1..3642cfc80194 100644 --- a/arch/arm/boot/dts/am3517-craneboard.dts +++ b/arch/arm/boot/dts/am3517-craneboard.dts @@ -2,7 +2,7 @@ /* * See craneboard.org for more details * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/am3517-evm-ui.dtsi b/arch/arm/boot/dts/am3517-evm-ui.dtsi index 48631a45da51..250c40da2535 100644 --- a/arch/arm/boot/dts/am3517-evm-ui.dtsi +++ b/arch/arm/boot/dts/am3517-evm-ui.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2018 Logic PD, Inc - http://www.logicpd.com/ + * Copyright (C) 2018 Logic PD, Inc - https://www.logicpd.com/ */ #include <dt-bindings/input/input.h> diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts index 92466b9eb6ba..04f20e7680b1 100644 --- a/arch/arm/boot/dts/am3517-evm.dts +++ b/arch/arm/boot/dts/am3517-evm.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi index dc8927f14b6c..de33c4f89f33 100644 --- a/arch/arm/boot/dts/am3517.dtsi +++ b/arch/arm/boot/dts/am3517.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for am3517 SoC * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -10,6 +10,10 @@ #include "omap3.dtsi" +/* AM3517 doesn't appear to have the crypto engines defined in omap3.dtsi */ +/delete-node/ &aes1_target; +/delete-node/ &aes2_target; + / { aliases { serial3 = &uart4; diff --git a/arch/arm/boot/dts/am3874-iceboard.dts b/arch/arm/boot/dts/am3874-iceboard.dts index 1b4b2b0500e4..1bb57019d082 100644 --- a/arch/arm/boot/dts/am3874-iceboard.dts +++ b/arch/arm/boot/dts/am3874-iceboard.dts @@ -2,8 +2,8 @@ /* * Device tree for Winterland IceBoard * - * http://mcgillcosmology.com - * http://threespeedlogic.com + * https://mcgillcosmology.com + * https://threespeedlogic.com * * This is an ARM + FPGA instrumentation board used at telescopes in * Antarctica (the South Pole Telescope), Chile (POLARBEAR), and at the DRAO diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index b4861f70f178..14314046256c 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for AM4372 SoC * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -153,7 +153,7 @@ clocks = <&mpu_periphclk>; }; - l2-cache-controller@48242000 { + cache-controller@48242000 { compatible = "arm,pl310-cache"; reg = <0x48242000 0x1000>; cache-unified; @@ -316,10 +316,11 @@ ranges = <0x0 0x47810000 0x1000>; mmc3: mmc@0 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,am437-sdhci"; ti,needs-special-reset; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0x1000>; + status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/am437x-cm-t43.dts index 063113a5da2d..a6b4fca8626a 100644 --- a/arch/arm/boot/dts/am437x-cm-t43.dts +++ b/arch/arm/boot/dts/am437x-cm-t43.dts @@ -291,7 +291,7 @@ pinctrl-0 = <&emmc_pins>; vmmc-supply = <&vmmc_3v3>; bus-width = <8>; - ti,non-removable; + non-removable; }; &spi0 { diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index d692e3b2812a..b28e5c8cd02a 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ /* AM437x GP EVM */ @@ -91,22 +91,6 @@ backlight = <&lcd_bl>; - panel-timing { - clock-frequency = <33000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <210>; - hback-porch = <16>; - hsync-len = <30>; - vback-porch = <10>; - vfront-porch = <22>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - port { lcd_in: endpoint { remote-endpoint = <&dpi_out>; @@ -869,7 +853,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&emmc_pins_default>; pinctrl-1 = <&emmc_pins_sleep>; - ti,non-removable; + non-removable; }; &mmc3 { @@ -886,7 +870,7 @@ pinctrl-1 = <&mmc3_pins_sleep>; cap-power-off-card; keep-power-in-suspend; - ti,non-removable; + non-removable; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts index a958f9ee4a5a..8b986c45f09d 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/am437x-idk-evm.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index 0d0f9fe4a882..3d393fe252c6 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -1083,9 +1083,8 @@ ranges = <0x0 0x60000 0x1000>; mmc1: mmc@0 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,am437-sdhci"; reg = <0x0 0x1000>; - ti,dual-volt; ti,needs-special-reset; dmas = <&edma 24 0>, <&edma 25 0>; @@ -1541,8 +1540,9 @@ reg = <0xcc020 0x4>; reg-names = "rev"; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>; - clock-names = "fck"; + clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>, + <&dcan0_fck>; + clock-names = "fck", "osc"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xcc000 0x2000>; @@ -1550,6 +1550,8 @@ dcan0: can@0 { compatible = "ti,am4372-d_can", "ti,am3352-d_can"; reg = <0x0 0x2000>; + clocks = <&dcan0_fck>; + clock-names = "fck"; syscon-raminit = <&scm_conf 0x644 0>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -1561,8 +1563,9 @@ reg = <0xd0020 0x4>; reg-names = "rev"; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>; - clock-names = "fck"; + clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>, + <&dcan1_fck>; + clock-names = "fck", "osc"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd0000 0x2000>; @@ -1570,6 +1573,8 @@ dcan1: can@0 { compatible = "ti,am4372-d_can", "ti,am3352-d_can"; reg = <0x0 0x2000>; + clocks = <&dcan1_fck>; + clock-name = "fck"; syscon-raminit = <&scm_conf 0x644 1>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -1598,7 +1603,7 @@ ranges = <0x0 0xd8000 0x1000>; mmc2: mmc@0 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,am437-sdhci"; reg = <0x0 0x1000>; ti,needs-special-reset; dmas = <&edma 2 0>, @@ -2352,7 +2357,6 @@ target-module@80000 { /* 0x48380000, ap 123 42.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_otg_ss0"; reg = <0x80000 0x4>, <0x80010 0x4>; reg-names = "rev", "sysc"; @@ -2433,7 +2437,6 @@ target-module@c0000 { /* 0x483c0000, ap 127 7a.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_otg_ss1"; reg = <0xc0000 0x4>, <0xc0010 0x4>; reg-names = "rev", "sysc"; diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 4d5a7ca2e25d..5fffdce853b1 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ */ /* AM437x SK EVM */ @@ -134,22 +134,6 @@ enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - panel-timing { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <2>; - hback-porch = <2>; - hsync-len = <41>; - vfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - port { lcd_in: endpoint { remote-endpoint = <&dpi_out>; @@ -719,7 +703,7 @@ pinctrl-1 = <&mmc3_pins_sleep>; cap-power-off-card; keep-power-in-suspend; - ti,non-removable; + non-removable; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 27259fd6f741..de4fc78498a0 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ /* AM43x EPOS EVM */ @@ -47,22 +47,6 @@ backlight = <&lcd_bl>; - panel-timing { - clock-frequency = <33000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <210>; - hback-porch = <16>; - hsync-len = <30>; - vback-porch = <10>; - vfront-porch = <22>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - port { lcd_in: endpoint { remote-endpoint = <&dpi_out>; diff --git a/arch/arm/boot/dts/am57-pruss.dtsi b/arch/arm/boot/dts/am57-pruss.dtsi index b1c583dee10b..032c1acfcda3 100644 --- a/arch/arm/boot/dts/am57-pruss.dtsi +++ b/arch/arm/boot/dts/am57-pruss.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * * Common PRUSS data for TI AM57xx platforms */ diff --git a/arch/arm/boot/dts/am5718.dtsi b/arch/arm/boot/dts/am5718.dtsi index a80c2e3eee2e..ebf4d3cc1cfb 100644 --- a/arch/arm/boot/dts/am5718.dtsi +++ b/arch/arm/boot/dts/am5718.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ #include "dra72x.dtsi" diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts index 99a408a2ec6a..391a92e24472 100644 --- a/arch/arm/boot/dts/am571x-idk.dts +++ b/arch/arm/boot/dts/am571x-idk.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/am5728.dtsi b/arch/arm/boot/dts/am5728.dtsi index 9a3810f5adcc..5e0bdf16d485 100644 --- a/arch/arm/boot/dts/am5728.dtsi +++ b/arch/arm/boot/dts/am5728.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ #include "dra74x.dtsi" diff --git a/arch/arm/boot/dts/am5729-beagleboneai.dts b/arch/arm/boot/dts/am5729-beagleboneai.dts index 9877d7709d41..e9c7f44126e7 100644 --- a/arch/arm/boot/dts/am5729-beagleboneai.dts +++ b/arch/arm/boot/dts/am5729-beagleboneai.dts @@ -8,6 +8,7 @@ #include "dra74x.dtsi" #include "am57xx-commercial-grade.dtsi" #include "dra74x-mmc-iodelay.dtsi" +#include "dra74-ipu-dsp-common.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/dra.h> @@ -505,7 +506,7 @@ &cpsw_emac0 { phy-handle = <&phy0>; - phy-mode = "rgmii"; + phy-mode = "rgmii-rxid"; }; &ocp { @@ -629,58 +630,6 @@ status = "okay"; }; -&mailbox1 { - status = "okay"; -}; - -&mailbox2 { - status = "okay"; -}; - -&mailbox3 { - status = "okay"; -}; - -&mailbox4 { - status = "okay"; -}; - -&mailbox5 { - status = "okay"; -}; - -&mailbox6 { - status = "okay"; -}; - -&mailbox7 { - status = "okay"; -}; - -&mailbox8 { - status = "okay"; -}; - -&mailbox9 { - status = "okay"; -}; - -&mailbox10 { - status = "okay"; -}; - -&mailbox11 { - status = "okay"; -}; - -&mailbox12 { - status = "okay"; -}; - -&mailbox13 { - status = "okay"; -}; - &cpu_alert0 { temperature = <55000>; /* milliCelsius */ }; @@ -729,3 +678,23 @@ opp-shared; }; }; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_memory_region>; +}; diff --git a/arch/arm/boot/dts/am572x-idk-common.dtsi b/arch/arm/boot/dts/am572x-idk-common.dtsi index 37ce2d7c4173..1d66278c3a72 100644 --- a/arch/arm/boot/dts/am572x-idk-common.dtsi +++ b/arch/arm/boot/dts/am572x-idk-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/gpio/gpio.h> diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts index c3d966904d64..1a3af4b54308 100644 --- a/arch/arm/boot/dts/am572x-idk.dts +++ b/arch/arm/boot/dts/am572x-idk.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/am5748.dtsi b/arch/arm/boot/dts/am5748.dtsi index 2b65317b1513..2cb577432766 100644 --- a/arch/arm/boot/dts/am5748.dtsi +++ b/arch/arm/boot/dts/am5748.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ #include "dra76x.dtsi" diff --git a/arch/arm/boot/dts/am574x-idk.dts b/arch/arm/boot/dts/am574x-idk.dts index 85c95cc551dd..c9275d0c62cf 100644 --- a/arch/arm/boot/dts/am574x-idk.dts +++ b/arch/arm/boot/dts/am574x-idk.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi index 94135fc5dd44..b3a0206ebd6c 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts b/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts index 39d1c4ff5749..83e174e053c7 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts +++ b/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ */ #include "am57xx-beagle-x15-common.dtsi" diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts b/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts index 4187a9729f96..656dd84460d2 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts +++ b/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include "am57xx-beagle-x15-common.dtsi" diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts index a5c24ed4d12f..0a8b16505ed9 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15.dts +++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ */ #include "am57xx-beagle-x15-common.dtsi" diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi index 2c0aab352b44..1c77006cccd1 100644 --- a/arch/arm/boot/dts/am57xx-idk-common.dtsi +++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ */ #include "am57xx-industrial-grade.dtsi" diff --git a/arch/arm/boot/dts/arm-realview-eb-mp.dtsi b/arch/arm/boot/dts/arm-realview-eb-mp.dtsi index 29b636fce23f..26783d053ac7 100644 --- a/arch/arm/boot/dts/arm-realview-eb-mp.dtsi +++ b/arch/arm/boot/dts/arm-realview-eb-mp.dtsi @@ -59,7 +59,7 @@ interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; }; - L2: l2-cache { + L2: cache-controller { compatible = "arm,l220-cache"; reg = <0x1f002000 0x1000>; interrupt-parent = <&intc>; diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts index 2625ce66f8e7..f925782f8560 100644 --- a/arch/arm/boot/dts/arm-realview-pb1176.dts +++ b/arch/arm/boot/dts/arm-realview-pb1176.dts @@ -323,7 +323,7 @@ <0x10120000 0x100>; }; - L2: l2-cache { + L2: cache-controller { compatible = "arm,l220-cache"; reg = <0x10110000 0x1000>; interrupt-parent = <&intc_dc1176>; diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts index c69cf7ddbe61..9748e0fe800f 100644 --- a/arch/arm/boot/dts/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts @@ -92,7 +92,7 @@ <0x1f000100 0x100>; }; - L2: l2-cache { + L2: cache-controller { compatible = "arm,l220-cache"; reg = <0x1f002000 0x1000>; interrupt-parent = <&intc_tc11mp>; diff --git a/arch/arm/boot/dts/arm-realview-pbx-a9.dts b/arch/arm/boot/dts/arm-realview-pbx-a9.dts index 90d00b407f85..85d3968fbb91 100644 --- a/arch/arm/boot/dts/arm-realview-pbx-a9.dts +++ b/arch/arm/boot/dts/arm-realview-pbx-a9.dts @@ -60,7 +60,7 @@ }; }; - L2: l2-cache { + L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0x1f002000 0x1000>; cache-unified; diff --git a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts index baa459dd51e4..2008c6eaaa52 100644 --- a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts +++ b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts @@ -247,9 +247,8 @@ &mdio { phy0: ethernet-phy@0 { /* Marvell 88E1318 */ reg = <0>; - marvell,reg-init = <0x0 0x16 0x0 0x0002>, - <0x0 0x19 0x0 0x0077>, - <0x0 0x18 0x0 0x5747>; + marvell,reg-init = <0x2 0x19 0x0 0x0077>, + <0x2 0x18 0x0 0x5747>; }; }; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 348116501aa2..9b1a24cc5e91 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -342,7 +342,8 @@ comphy: phy@18300 { compatible = "marvell,armada-380-comphy"; - reg = <0x18300 0x100>; + reg-names = "comphy", "conf"; + reg = <0x18300 0x100>, <0x18460 4>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts new file mode 100644 index 000000000000..60ba86f3e5bc --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020 AMD Inc. +// Author: Supreeth Venkatesh <supreeth.venkatesh@amd.com> +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> + +/ { + model = "AMD EthanolX BMC"; + compatible = "amd,ethanolx-bmc", "aspeed,ast2500"; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + aliases { + serial0 = &uart1; + serial4 = &uart5; + }; + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + leds { + compatible = "gpio-leds"; + + fault { + gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; + }; + + identify { + gpios = <&gpio ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>; + }; + }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + #include "openbmc-flash-layout.dtsi" + }; +}; + + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; +}; + +&uart1 { + //Host Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart5 { + //BMC Console + status = "okay"; +}; + +&adc { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default>; +}; + +//APML for P0 +&i2c0 { + status = "okay"; +}; + +//APML for P1 +&i2c1 { + status = "okay"; +}; + +// Thermal Sensors +&i2c7 { + status = "okay"; + + lm75a@48 { + compatible = "national,lm75a"; + reg = <0x48>; + }; + + lm75a@49 { + compatible = "national,lm75a"; + reg = <0x49>; + }; + + lm75a@4a { + compatible = "national,lm75a"; + reg = <0x4a>; + }; + + lm75a@4b { + compatible = "national,lm75a"; + reg = <0x4b>; + }; + + lm75a@4c { + compatible = "national,lm75a"; + reg = <0x4c>; + }; + + lm75a@4d { + compatible = "national,lm75a"; + reg = <0x4d>; + }; + + lm75a@4e { + compatible = "national,lm75a"; + reg = <0x4e>; + }; + + lm75a@4f { + compatible = "national,lm75a"; + reg = <0x4f>; + }; +}; + +&kcs1 { + status = "okay"; + kcs_addr = <0x60>; +}; + +&kcs2 { + status = "okay"; + kcs_addr = <0x62>; +}; + +&kcs4 { + status = "okay"; + kcs_addr = <0x97DE>; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&lpc_ctrl { + //Enable lpc clock + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm2_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default + &pinctrl_pwm5_default + &pinctrl_pwm6_default + &pinctrl_pwm7_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; +}; + + + diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts index 016bbcb99bb6..7bc7df7ed428 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts @@ -19,8 +19,8 @@ serial3 = &uart4; /* - * Hardcode the bus number of i2c switches' channels to - * avoid breaking the legacy applications. + * PCA9548 (1-0077) provides 8 channels for connecting to + * 4 Line Cards and 4 Fabric Cards. */ i2c16 = &imux16; i2c17 = &imux17; @@ -30,6 +30,11 @@ i2c21 = &imux21; i2c22 = &imux22; i2c23 = &imux23; + + /* + * PCA9548 (2-0071) provides 8 channels for connecting to + * Power Distribution Board. + */ i2c24 = &imux24; i2c25 = &imux25; i2c26 = &imux26; @@ -38,6 +43,11 @@ i2c29 = &imux29; i2c30 = &imux30; i2c31 = &imux31; + + /* + * PCA9548 (8-0077) provides 8 channels and the first 4 + * channels are connecting to 4 Fan Control Boards. + */ i2c32 = &imux32; i2c33 = &imux33; i2c34 = &imux34; @@ -46,6 +56,226 @@ i2c37 = &imux37; i2c38 = &imux38; i2c39 = &imux39; + + /* + * 2 PCA9548 (18-0070 & 18-0073), 16 channels connecting + * to Line Card #1. + */ + i2c40 = &imux40; + i2c41 = &imux41; + i2c42 = &imux42; + i2c43 = &imux43; + i2c44 = &imux44; + i2c45 = &imux45; + i2c46 = &imux46; + i2c47 = &imux47; + i2c48 = &imux48; + i2c49 = &imux49; + i2c50 = &imux50; + i2c51 = &imux51; + i2c52 = &imux52; + i2c53 = &imux53; + i2c54 = &imux54; + i2c55 = &imux55; + + /* + * 2 PCA9548 (19-0070 & 19-0073), 16 channels connecting + * to Line Card #2. + */ + i2c56 = &imux56; + i2c57 = &imux57; + i2c58 = &imux58; + i2c59 = &imux59; + i2c60 = &imux60; + i2c61 = &imux61; + i2c62 = &imux62; + i2c63 = &imux63; + i2c64 = &imux64; + i2c65 = &imux65; + i2c66 = &imux66; + i2c67 = &imux67; + i2c68 = &imux68; + i2c69 = &imux69; + i2c70 = &imux70; + i2c71 = &imux71; + + /* + * 2 PCA9548 (20-0070 & 20-0073), 16 channels connecting + * to Line Card #3. + */ + i2c72 = &imux72; + i2c73 = &imux73; + i2c74 = &imux74; + i2c75 = &imux75; + i2c76 = &imux76; + i2c77 = &imux77; + i2c78 = &imux78; + i2c79 = &imux79; + i2c80 = &imux80; + i2c81 = &imux81; + i2c82 = &imux82; + i2c83 = &imux83; + i2c84 = &imux84; + i2c85 = &imux85; + i2c86 = &imux86; + i2c87 = &imux87; + + /* + * 2 PCA9548 (21-0070 & 21-0073), 16 channels connecting + * to Line Card #4. + */ + i2c88 = &imux88; + i2c89 = &imux89; + i2c90 = &imux90; + i2c91 = &imux91; + i2c92 = &imux92; + i2c93 = &imux93; + i2c94 = &imux94; + i2c95 = &imux95; + i2c96 = &imux96; + i2c97 = &imux97; + i2c98 = &imux98; + i2c99 = &imux99; + i2c100 = &imux100; + i2c101 = &imux101; + i2c102 = &imux102; + i2c103 = &imux103; + + /* + * 2 PCA9548 (16-0070 & 16-0073), 16 channels connecting + * to Fabric Card #1. + */ + i2c104 = &imux104; + i2c105 = &imux105; + i2c106 = &imux106; + i2c107 = &imux107; + i2c108 = &imux108; + i2c109 = &imux109; + i2c110 = &imux110; + i2c111 = &imux111; + i2c112 = &imux112; + i2c113 = &imux113; + i2c114 = &imux114; + i2c115 = &imux115; + i2c116 = &imux116; + i2c117 = &imux117; + i2c118 = &imux118; + i2c119 = &imux119; + + /* + * 2 PCA9548 (17-0070 & 17-0073), 16 channels connecting + * to Fabric Card #2. + */ + i2c120 = &imux120; + i2c121 = &imux121; + i2c122 = &imux122; + i2c123 = &imux123; + i2c124 = &imux124; + i2c125 = &imux125; + i2c126 = &imux126; + i2c127 = &imux127; + i2c128 = &imux128; + i2c129 = &imux129; + i2c130 = &imux130; + i2c131 = &imux131; + i2c132 = &imux132; + i2c133 = &imux133; + i2c134 = &imux134; + i2c135 = &imux135; + + /* + * 2 PCA9548 (22-0070 & 22-0073), 16 channels connecting + * to Fabric Card #3. + */ + i2c136 = &imux136; + i2c137 = &imux137; + i2c138 = &imux138; + i2c139 = &imux139; + i2c140 = &imux140; + i2c141 = &imux141; + i2c142 = &imux142; + i2c143 = &imux143; + i2c144 = &imux144; + i2c145 = &imux145; + i2c146 = &imux146; + i2c147 = &imux147; + i2c148 = &imux148; + i2c149 = &imux149; + i2c150 = &imux150; + i2c151 = &imux151; + + /* + * 2 PCA9548 (23-0070 & 23-0073), 16 channels connecting + * to Fabric Card #4. + */ + i2c152 = &imux152; + i2c153 = &imux153; + i2c154 = &imux154; + i2c155 = &imux155; + i2c156 = &imux156; + i2c157 = &imux157; + i2c158 = &imux158; + i2c159 = &imux159; + i2c160 = &imux160; + i2c161 = &imux161; + i2c162 = &imux162; + i2c163 = &imux163; + i2c164 = &imux164; + i2c165 = &imux165; + i2c166 = &imux166; + i2c167 = &imux167; + + /* + * PCA9548 (32-0070), 8 channels connecting to Fan Control + # Board #1. + */ + i2c168 = &imux168; + i2c169 = &imux169; + i2c170 = &imux170; + i2c171 = &imux171; + i2c172 = &imux172; + i2c173 = &imux173; + i2c174 = &imux174; + i2c175 = &imux175; + + /* + * PCA9548 (33-0070), 8 channels connecting to Fan Control + # Board #2. + */ + i2c176 = &imux176; + i2c177 = &imux177; + i2c178 = &imux178; + i2c179 = &imux179; + i2c180 = &imux180; + i2c181 = &imux181; + i2c182 = &imux182; + i2c183 = &imux183; + + /* + * PCA9548 (34-0070), 8 channels connecting to Fan Control + # Board #3. + */ + i2c184 = &imux184; + i2c185 = &imux185; + i2c186 = &imux186; + i2c187 = &imux187; + i2c188 = &imux188; + i2c189 = &imux189; + i2c190 = &imux190; + i2c191 = &imux191; + + /* + * PCA9548 (35-0070), 8 channels connecting to Fan Control + # Board #4. + */ + i2c192 = &imux192; + i2c193 = &imux193; + i2c194 = &imux194; + i2c195 = &imux195; + i2c196 = &imux196; + i2c197 = &imux197; + i2c198 = &imux198; + i2c199 = &imux199; }; chosen { @@ -103,53 +333,846 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x77>; + i2c-mux-idle-disconnect; + /* To Fabric Card #1 */ imux16: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux104: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux105: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux106: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux107: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux108: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux109: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux110: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux111: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux112: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux113: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux114: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux115: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux116: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux117: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux118: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux119: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* To Fabric Card #2 */ imux17: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux120: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux121: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux122: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux123: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux124: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux125: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux126: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux127: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux128: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux129: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux130: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux131: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux132: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux133: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux134: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux135: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* To Line Card #1 */ imux18: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux40: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux41: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux42: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux43: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux44: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux45: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux46: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux47: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux48: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux49: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux50: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux51: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux52: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux53: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux54: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux55: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* To Line Card #2 */ imux19: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux56: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux57: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux58: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux59: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux60: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux61: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux62: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux63: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux64: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux65: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux66: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux67: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux68: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux69: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux70: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux71: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* To LC3 SCM */ imux20: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux72: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux73: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux74: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux75: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux76: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux77: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux78: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux79: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux80: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux81: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux82: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux83: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux84: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux85: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux86: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux87: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* To Line Card #4 */ imux21: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux88: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux89: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux90: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux91: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux92: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux93: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux94: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux95: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux96: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux97: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux98: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux99: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux100: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux101: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux102: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux103: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* To Fabric Card #3 */ imux22: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux136: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux137: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux138: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux139: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux140: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux141: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux142: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux143: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux144: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux145: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux146: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux147: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux148: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux149: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux150: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux151: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* To Fabric Card #4 */ imux23: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux152: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux153: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux154: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux155: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux156: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux157: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux158: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux159: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux160: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux161: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux162: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux163: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux164: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux165: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux166: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux167: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; }; }; @@ -165,6 +1188,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x71>; + i2c-mux-idle-disconnect; imux24: i2c@0 { #address-cells = <1>; @@ -252,7 +1276,7 @@ }; /* - * I2C bus to Fan Control Board. + * I2C bus to Fan Control Boards. */ &i2c8 { status = "okay"; @@ -262,29 +1286,230 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x77>; + i2c-mux-idle-disconnect; + /* To Fan Control Board #1 */ imux32: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux168: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux169: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux170: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux171: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux172: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux173: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux174: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux175: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* To Fan Control Board #2 */ imux33: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux176: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux177: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux178: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux179: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux180: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux181: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux182: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux183: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* To Fan Control Board #3 */ imux34: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux184: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux185: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux186: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux187: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux188: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux189: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux190: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux191: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* To Fan Control Board #4 */ imux35: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux192: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + imux193: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + imux194: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + imux195: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + imux196: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + imux197: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + imux198: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + imux199: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; imux36: i2c@4 { diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts index 54e508530dce..8ac23ff6b09e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts @@ -27,6 +27,11 @@ memory@40000000 { reg = <0x40000000 0x20000000>; }; + + ast-adc-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>; + }; }; &wdt1 { @@ -115,26 +120,47 @@ status = "okay"; }; -&i2c9 { +&i2c11 { status = "okay"; }; -&i2c10 { +&i2c12 { status = "okay"; }; -&i2c11 { +&vhub { status = "okay"; }; -&i2c12 { +&adc { status = "okay"; }; -&i2c13 { +&pwm_tacho { status = "okay"; -}; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm6_default + &pinctrl_pwm7_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; + }; -&vhub { - status = "okay"; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; + }; + + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>; + }; + + fan@7 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>; + }; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index bdfe342bf7c5..b94421f6cbd5 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -12,6 +12,23 @@ aliases { serial4 = &uart5; + i2c16 = &i2c2mux0; + i2c17 = &i2c2mux1; + i2c18 = &i2c2mux2; + i2c19 = &i2c2mux3; + + spi10 = &cfam0_spi0; + spi11 = &cfam0_spi1; + spi12 = &cfam0_spi2; + spi13 = &cfam0_spi3; + spi20 = &cfam1_spi0; + spi21 = &cfam1_spi1; + spi22 = &cfam1_spi2; + spi23 = &cfam1_spi3; + spi30 = &cfam2_spi0; + spi31 = &cfam2_spi1; + spi32 = &cfam2_spi2; + spi33 = &cfam2_spi3; }; chosen { @@ -68,12 +85,51 @@ }; }; + i2c2mux: i2cmux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + i2c-parent = <&i2c2>; + mux-gpios = <&gpio0 ASPEED_GPIO(G, 4) GPIO_ACTIVE_HIGH>, + <&gpio0 ASPEED_GPIO(G, 5) GPIO_ACTIVE_HIGH>; + idle-state = <0>; + + i2c2mux0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c2mux1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c2mux2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c2mux3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&ehci1 { + status = "okay"; }; &gpio0 { gpio-line-names = /*A0-A7*/ "","","","","","","","", - /*B0-B7*/ "","","","","","","","", + /*B0-B7*/ "","","","","","","checkstop","", /*C0-C7*/ "","","","","","","","", /*D0-D7*/ "","","","","","","","", /*E0-E7*/ "","","","","","","","", @@ -86,7 +142,7 @@ /*L0-L7*/ "","","","","","","","", /*M0-M7*/ "","","","","","","","", /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","","","","","", + /*O0-O7*/ "","","","usb-power","","","","", /*P0-P7*/ "","","","","","","","", /*Q0-Q7*/ "cfam-reset","","","","","","","", /*R0-R7*/ "","","","","","","","", @@ -102,6 +158,20 @@ /*AA0-AA7*/ "","","","","","","","", /*AB0-AB7*/ "","","","","","","","", /*AC0-AC7*/ "","","","","","","",""; + + pin_mclr_vpp { + gpio-hog; + gpios = <ASPEED_GPIO(P, 7) GPIO_OPEN_DRAIN>; + output-high; + line-name = "mclr_vpp"; + }; + + i2c3_mux_oe_n { + gpio-hog; + gpios = <ASPEED_GPIO(G, 6) GPIO_ACTIVE_LOW>; + output-high; + line-name = "I2C3_MUX_OE_N"; + }; }; &emmc_controller { @@ -118,6 +188,12 @@ #address-cells = <2>; #size-cells = <0>; + /* + * CFAM Reset is supposed to be active low but pass1 hardware is wired + * active high. + */ + cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; + cfam@0,0 { reg = <0 0>; #address-cells = <1>; @@ -129,6 +205,84 @@ reg = <0x1000 0x400>; }; + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam0_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam0_spi2: spi@40 { + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam0_spi3: spi@60 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + sbefifo@2400 { compatible = "ibm,p9-sbefifo"; reg = <0x2400 0x400>; @@ -136,7 +290,7 @@ #size-cells = <0>; fsi_occ0: occ { - compatible = "ibm,p9-occ"; + compatible = "ibm,p10-occ"; }; }; @@ -163,6 +317,84 @@ reg = <0x1000 0x400>; }; + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam1_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam1_spi2: spi@40 { + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam1_spi3: spi@60 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + sbefifo@2400 { compatible = "ibm,p9-sbefifo"; reg = <0x2400 0x400>; @@ -170,7 +402,7 @@ #size-cells = <0>; fsi_occ1: occ { - compatible = "ibm,p9-occ"; + compatible = "ibm,p10-occ"; }; }; @@ -183,6 +415,116 @@ no-scan-on-init; }; }; + + cfam@2,0 { + reg = <2 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <2>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam2_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam2_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam2_spi2: spi@40 { + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam2_spi3: spi@60 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ2: occ { + compatible = "ibm,p10-occ"; + }; + }; + + fsi_hub2: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; }; /* Legacy OCC numbering (to get rid of when userspace is fixed) */ @@ -194,6 +536,10 @@ reg = <2>; }; +&fsi_occ2 { + reg = <3>; +}; + &ibt { status = "okay"; }; @@ -205,6 +551,21 @@ compatible = "atmel,24c64"; reg = <0x51>; }; + + tca9554@40 { + compatible = "ti,tca9554"; + reg = <0x40>; + gpio-controller; + #gpio-cells = <2>; + + smbus0 { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "smbus0"; + }; + }; + }; &i2c1 { @@ -519,6 +880,96 @@ compatible = "atmel,24c64"; reg = <0x51>; }; + + pca1: pca9552@61 { + compatible = "nxp,pca9552"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + }; &i2c9 { @@ -656,13 +1107,6 @@ spi-max-frequency = <50000000>; #include "openbmc-flash-layout-128.dtsi" }; - - flash@1 { - status = "okay"; - m25p,fast-read; - label = "alt-bmc"; - spi-max-frequency = <50000000>; - }; }; &spi1 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts index 60e545b6396f..cb85168f6761 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts @@ -820,12 +820,50 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; + + tca9554@39 { + compatible = "ti,tca9554"; + reg = <0x39>; + gpio-controller; + #gpio-cells = <2>; + + smbus0 { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "smbus0"; + }; + }; + + tmp431@4c { + compatible = "ti,tmp401"; + reg = <0x4c>; + }; }; bus9_mux232: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; + + tca9554@39 { + compatible = "ti,tca9554"; + reg = <0x39>; + gpio-controller; + #gpio-cells = <2>; + + smbus1 { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "smbus1"; + }; + }; + + tmp431@4c { + compatible = "ti,tmp401"; + reg = <0x4c>; + }; }; bus9_mux233: i2c@2 { @@ -855,12 +893,50 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; + + tca9554@39 { + compatible = "ti,tca9554"; + reg = <0x39>; + gpio-controller; + #gpio-cells = <2>; + + smbus2 { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "smbus2"; + }; + }; + + tmp431@4c { + compatible = "ti,tmp401"; + reg = <0x4c>; + }; }; bus9_mux236: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; + + tca9554@39 { + compatible = "ti,tca9554"; + reg = <0x39>; + gpio-controller; + #gpio-cells = <2>; + + smbus3 { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "smbus3"; + }; + }; + + tmp431@4c { + compatible = "ti,tmp401"; + reg = <0x4c>; + }; }; bus9_mux237: i2c@2 { @@ -909,12 +985,50 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; + + tca9554@39 { + compatible = "ti,tca9554"; + reg = <0x39>; + gpio-controller; + #gpio-cells = <2>; + + smbus4 { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "smbus4"; + }; + }; + + tmp431@4c { + compatible = "ti,tmp401"; + reg = <0x4c>; + }; }; bus10_mux240: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; + + tca9554@39 { + compatible = "ti,tca9554"; + reg = <0x39>; + gpio-controller; + #gpio-cells = <2>; + + smbus5 { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "smbus5"; + }; + }; + + tmp431@4c { + compatible = "ti,tmp401"; + reg = <0x4c>; + }; }; bus10_mux241: i2c@2 { @@ -944,12 +1058,50 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; + + tca9554@39 { + compatible = "ti,tca9554"; + reg = <0x39>; + gpio-controller; + #gpio-cells = <2>; + + smbus6 { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "smbus6"; + }; + }; + + tmp431@4c { + compatible = "ti,tmp401"; + reg = <0x4c>; + }; }; bus10_mux244: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; + + tca9554@39 { + compatible = "ti,tca9554"; + reg = <0x39>; + gpio-controller; + #gpio-cells = <2>; + + smbus7 { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "smbus7"; + }; + }; + + tmp431@4c { + compatible = "ti,tmp401"; + reg = <0x4c>; + }; }; bus10_mux245: i2c@2 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index 13c4aa02f4de..5f4ee67ac787 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -29,76 +29,17 @@ no-map; reg = <0xb8000000 0x4000000>; /* 64M */ }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - checkstop { - label = "checkstop"; - gpios = <&gpio0 ASPEED_GPIO(E, 3) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(E, 3)>; - }; - - ps0-presence { - label = "ps0-presence"; - gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(H, 3)>; - }; - - ps1-presence { - label = "ps1-presence"; - gpios = <&gpio0 ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(E, 5)>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <1000>; - - fan0-presence { - label = "fan0-presence"; - gpios = <&pca0 4 GPIO_ACTIVE_LOW>; - linux,code = <4>; - }; - - fan1-presence { - label = "fan1-presence"; - gpios = <&pca0 5 GPIO_ACTIVE_LOW>; - linux,code = <5>; - }; - fan2-presence { - label = "fan2-presence"; - gpios = <&pca0 6 GPIO_ACTIVE_LOW>; - linux,code = <6>; - }; - - fan3-presence { - label = "fan3-presence"; - gpios = <&pca0 7 GPIO_ACTIVE_LOW>; - linux,code = <7>; + vga_memory: region@bf000000 { + no-map; + compatible = "shared-dma-pool"; + reg = <0xbf000000 0x01000000>; /* 16M */ }; }; gpio-keys { compatible = "gpio-keys"; - air-water { - label = "air-water"; - gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(Q, 7)>; - }; - - checkstop { - label = "checkstop"; - gpios = <&gpio0 ASPEED_GPIO(E, 3) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(E, 3)>; - }; - ps0-presence { label = "ps0-presence"; gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; @@ -154,6 +95,10 @@ }; }; +&ehci1 { + status = "okay"; +}; + &gpio0 { gpio-line-names = /*A0-A7*/ "","","","","","","","", @@ -170,7 +115,7 @@ /*L0-L7*/ "","","","","","","","", /*M0-M7*/ "","","","","","","","", /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "led-rear-power","led-rear-id","","","","","","", + /*O0-O7*/ "led-rear-power","led-rear-id","","usb-power","","","","", /*P0-P7*/ "","","","","","","","", /*Q0-Q7*/ "cfam-reset","","","","","","","fsi-routing", /*R0-R7*/ "","","","","","","","", @@ -244,6 +189,7 @@ fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>; + cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_LOW>; cfam@0,0 { reg = <0 0>; @@ -912,3 +858,8 @@ pinctrl-0 = <&pinctrl_lpc_default>, <&pinctrl_lsirq_default>; }; + +&xdma { + status = "okay"; + memory-region = <&vga_memory>; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts index a0f99e34ac8e..85d58a63ae90 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -27,6 +27,12 @@ reg = <0x98000000 0x04000000>; /* 64M */ }; + vga_memory: region@9f000000 { + no-map; + compatible = "shared-dma-pool"; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + gfx_memory: framebuffer { size = <0x01000000>; alignment = <0x01000000>; @@ -690,4 +696,9 @@ memory-region = <&video_engine_memory>; }; +&xdma { + status = "okay"; + memory-region = <&vga_memory>; +}; + #include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index de7fd80b022a..9c91afb2b404 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ #include <dt-bindings/clock/aspeed-clock.h> +#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h> / { model = "Aspeed BMC"; @@ -267,8 +268,8 @@ reg = <0x1e6e7000 0x100>; clocks = <&syscon ASPEED_CLK_GATE_BCLK>; resets = <&syscon ASPEED_RESET_XDMA>; - interrupts-extended = <&vic 6>, <&scu_ic 2>; - pcie-device = "bmc"; + interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>; + aspeed,pcie-device = "bmc"; aspeed,scu = <&syscon>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 9d8d8e18bc90..b58220a49cbd 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -2,6 +2,7 @@ // Copyright 2019 IBM Corp. #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h> #include <dt-bindings/clock/ast2600-clock.h> / { @@ -346,22 +347,12 @@ resets = <&syscon ASPEED_RESET_DEV_XDMA>, <&syscon ASPEED_RESET_RC_XDMA>; reset-names = "device", "root-complex"; interrupts-extended = <&gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <&scu_ic0 2>; - pcie-device = "bmc"; + <&scu_ic0 ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI>; + aspeed,pcie-device = "bmc"; aspeed,scu = <&syscon>; status = "disabled"; }; - video: video@1e700000 { - compatible = "aspeed,ast2600-video-engine"; - reg = <0x1e700000 0x1000>; - clocks = <&syscon ASPEED_CLK_GATE_VCLK>, - <&syscon ASPEED_CLK_GATE_ECLK>; - clock-names = "vclk", "eclk"; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - gpio0: gpio@1e780000 { #gpio-cells = <2>; gpio-controller; diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts index a5f5718c711a..ca15ff8fea18 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -309,6 +309,10 @@ }; }; +&gpbr { + status = "okay"; +}; + &i2s { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2s_default>; @@ -470,9 +474,9 @@ pinctrl_classd_default: classd { atmel,pins = <AT91_PIOA 24 AT91_PERIPH_C AT91_PINCTRL_PULL_UP - AT91_PIOA 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP + AT91_PIOA 25 AT91_PERIPH_C AT91_PINCTRL_PULL_DOWN AT91_PIOA 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP - AT91_PIOA 27 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; + AT91_PIOA 27 AT91_PERIPH_C AT91_PINCTRL_PULL_DOWN>; }; }; @@ -636,6 +640,11 @@ }; }; +&rtt { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "okay"; +}; + &shutdown_controller { atmel,shdwc-debouncer = <976>; status = "okay"; diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index a927165ea7c2..058fae1b4a76 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -168,16 +168,6 @@ }; }; - pdmic@f8018000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pdmic_default>; - atmel,model = "PDMIC @ sama5d2_xplained"; - atmel,mic-min-freq = <1000000>; - atmel,mic-max-freq = <3246000>; - atmel,mic-offset = <0x0>; - status = "okay"; - }; - uart1: serial@f8020000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; @@ -490,14 +480,18 @@ bias-pull-up; }; - pinctrl_classd_default: classd_default { + pinctrl_classd_default_pfets: classd_default_pfets { pinmux = <PIN_PB1__CLASSD_R0>, - <PIN_PB2__CLASSD_R1>, - <PIN_PB3__CLASSD_R2>, - <PIN_PB4__CLASSD_R3>; + <PIN_PB3__CLASSD_R2>; bias-pull-up; }; + pinctrl_classd_default_nfets: classd_default_nfets { + pinmux = <PIN_PB2__CLASSD_R1>, + <PIN_PB4__CLASSD_R3>; + bias-pull-down; + }; + pinctrl_flx0_default: flx0_default { pinmux = <PIN_PB28__FLEXCOM0_IO0>, <PIN_PB29__FLEXCOM0_IO1>; @@ -595,12 +589,6 @@ bias-disable; }; - pinctrl_pdmic_default: pdmic_default { - pinmux = <PIN_PB26__PDMIC_DAT>, - <PIN_PB27__PDMIC_CLK>; - bias-disable; - }; - pinctrl_qspi0_default: qspi0_default { sck_cs { pinmux = <PIN_PA22__QSPI0_SCK>, @@ -696,7 +684,7 @@ classd: classd@fc048000 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_classd_default>; + pinctrl-0 = <&pinctrl_classd_default_pfets &pinctrl_classd_default_nfets>; atmel,pwm-type = "diff"; atmel,non-overlap-time = <10>; status = "okay"; diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts index 61f068a7b362..7abf555cd2fe 100644 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts @@ -128,7 +128,7 @@ }; macb0: ethernet@f0028000 { - phy-mode = "rgmii"; + phy-mode = "rgmii-rxid"; #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 1bc45cfd5453..35bdd0969f0a 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -91,7 +91,7 @@ <0x20100 0x100>; }; - L2: l2-cache@22000 { + L2: cache-controller@22000 { compatible = "arm,pl310-cache"; reg = <0x22000 0x1000>; cache-unified; diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi index 5e5f5ca3c86f..cbebed5f050e 100644 --- a/arch/arm/boot/dts/bcm-hr2.dtsi +++ b/arch/arm/boot/dts/bcm-hr2.dtsi @@ -104,7 +104,7 @@ <0x20100 0x100>; }; - L2: l2-cache@22000 { + L2: cache-controller@22000 { compatible = "arm,pl310-cache"; reg = <0x22000 0x1000>; cache-unified; diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index da6d70f09ef1..0346ea621f0f 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -122,7 +122,7 @@ <0x20100 0x100>; }; - L2: l2-cache@22000 { + L2: cache-controller@22000 { compatible = "arm,pl310-cache"; reg = <0x22000 0x1000>; cache-unified; @@ -200,7 +200,7 @@ status = "disabled"; }; - dma@20000 { + dma: dma@20000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x20000 0x1000>; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, @@ -215,6 +215,8 @@ clocks = <&iprocslow>; clock-names = "apb_pclk"; #dma-cells = <1>; + dma-coherent; + status = "disabled"; }; sdio: sdhci@21000 { @@ -257,10 +259,10 @@ status = "disabled"; }; - mailbox: mailbox@25000 { + mailbox: mailbox@25c00 { compatible = "brcm,iproc-fa2-mbox"; - reg = <0x25000 0x445>; - interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x25c00 0x400>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <1>; brcm,rx-status-len = <32>; brcm,use-bcm-hdr; diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi index 3cf66faf3b56..58ec1b2f8ef6 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/bcm21664.dtsi @@ -90,7 +90,7 @@ reg-io-width = <4>; }; - L2: l2-cache@3ff20000 { + L2: cache-controller@3ff20000 { compatible = "arm,pl310-cache"; reg = <0x3ff20000 0x1000>; cache-unified; diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index c7f1d97e69bb..222d7825e1ab 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -69,6 +69,11 @@ }; &firmware { + firmware_clocks: clocks { + compatible = "raspberrypi,firmware-clocks"; + #clock-cells = <1>; + }; + expgpio: gpio { compatible = "raspberrypi,firmware-gpio"; gpio-controller; diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index a91cf68e3c4c..00bcaed1be32 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -12,6 +12,13 @@ interrupt-parent = <&gicv2>; + clk_108MHz: clk-108M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <108000000>; + clock-output-names = "108MHz-clock"; + }; + soc { /* * Defined ranges: @@ -244,6 +251,14 @@ hvs@7e400000 { interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; }; + + dvp: clock@7ef00000 { + compatible = "brcm,brcm2711-dvp"; + reg = <0x7ef00000 0x10>; + clocks = <&clk_108MHz>; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; /* diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts index e58c8077be1d..810fc32f1895 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts @@ -60,3 +60,28 @@ &usb3_phy { status = "okay"; }; + +&srab { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "poe"; + }; + + port@4 { + reg = <4>; + label = "lan"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts index 766db617455b..7604b4480bb1 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts @@ -67,3 +67,23 @@ &usb3_phy { status = "okay"; }; + +&srab { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + label = "lan"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts index b9d95011637d..1ec655809e57 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts @@ -60,3 +60,23 @@ &usb3_phy { status = "okay"; }; + +&srab { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + label = "poe"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts index 0052e1b24130..04bfd58127fc 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts @@ -108,3 +108,43 @@ &usb3_phy { status = "okay"; }; + +&srab { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts index b47fb0700a1f..068e384b8ab7 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts @@ -54,3 +54,28 @@ &spi_nor { status = "okay"; }; + +&srab { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "poe"; + }; + + port@1 { + reg = <1>; + label = "lan"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts index 334325390aed..9ae815ddbb4b 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x18000000>; }; @@ -51,3 +52,23 @@ &spi_nor { status = "okay"; }; + +&srab { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts index ac7515423474..a21b2d185596 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts @@ -103,3 +103,43 @@ &usb3_phy { status = "okay"; }; + +&srab { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts index 6d28b7dacd05..4d5c5aa7dc42 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts @@ -74,3 +74,43 @@ &spi_nor { status = "okay"; }; + +&srab { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts index 8c388eb8a08f..7be4c4e628e0 100644 --- a/arch/arm/boot/dts/bcm958522er.dts +++ b/arch/arm/boot/dts/bcm958522er.dts @@ -58,6 +58,10 @@ /* USB 3 support needed to be complete */ +&dma { + status = "okay"; +}; + &amac0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts index c339771bb22e..e58ed7e95346 100644 --- a/arch/arm/boot/dts/bcm958525er.dts +++ b/arch/arm/boot/dts/bcm958525er.dts @@ -58,6 +58,10 @@ /* USB 3 support needed to be complete */ +&dma { + status = "okay"; +}; + &amac0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts index 1c72ec8288de..716da62f5788 100644 --- a/arch/arm/boot/dts/bcm958525xmc.dts +++ b/arch/arm/boot/dts/bcm958525xmc.dts @@ -58,6 +58,10 @@ /* XHCI support needed to be complete */ +&dma { + status = "okay"; +}; + &amac0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts index 96a021cebd97..a49c2fd21f4a 100644 --- a/arch/arm/boot/dts/bcm958622hr.dts +++ b/arch/arm/boot/dts/bcm958622hr.dts @@ -58,6 +58,10 @@ /* USB 3 and SLIC support needed to be complete */ +&dma { + status = "okay"; +}; + &amac0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts index b2c7f21d471e..dd6dff6452b8 100644 --- a/arch/arm/boot/dts/bcm958623hr.dts +++ b/arch/arm/boot/dts/bcm958623hr.dts @@ -58,6 +58,10 @@ /* USB 3 and SLIC support needed to be complete */ +&dma { + status = "okay"; +}; + &amac0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts index 536fb24f38bb..a71371b4065e 100644 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -69,6 +69,10 @@ status = "okay"; }; +&dma { + status = "okay"; +}; + &amac0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index 3fcca12d83c2..7b84b54436ed 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -48,6 +48,10 @@ }; }; +&dma { + status = "okay"; +}; + &amac0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index 3ab3cd250da7..6194857f8a02 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -106,7 +106,7 @@ status = "disabled"; }; - l2: l2-cache-controller@ac0000 { + l2: cache-controller@ac0000 { compatible = "marvell,tauros3-cache", "arm,pl310-cache"; reg = <0xac0000 0x1000>; cache-unified; diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi index 7cf3e6302d75..6f30d7eb3b41 100644 --- a/arch/arm/boot/dts/berlin2cd.dtsi +++ b/arch/arm/boot/dts/berlin2cd.dtsi @@ -71,7 +71,7 @@ status = "disabled"; }; - l2: l2-cache-controller@ac0000 { + l2: cache-controller@ac0000 { compatible = "arm,pl310-cache"; reg = <0xac0000 0x1000>; cache-unified; diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index c44a32e873f4..b6a0acac6836 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -149,7 +149,7 @@ status = "disabled"; }; - l2: l2-cache-controller@ac0000 { + l2: cache-controller@ac0000 { compatible = "arm,pl310-cache"; reg = <0xac0000 0x1000>; cache-unified; diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index f2e7609e5346..87c517d65f62 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -2,7 +2,7 @@ /* * Device Tree for DA850 EVM board * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; #include "da850.dtsi" diff --git a/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi b/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi index 1c39a8459b39..e75569383dd8 100644 --- a/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi +++ b/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for DRA7x SoC DSPEVE thermal * - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi index f89a64cbcd53..0f71a9f37a72 100644 --- a/arch/arm/boot/dts/dra7-evm-common.dtsi +++ b/arch/arm/boot/dts/dra7-evm-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include "dra74-ipu-dsp-common.dtsi" @@ -245,26 +245,6 @@ rx-num-evt = <32>; }; -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; -}; - &pcie1_rc { status = "okay"; }; diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 7aeb30daf3b8..a952d934fcf2 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/dra7-iva-thermal.dtsi b/arch/arm/boot/dts/dra7-iva-thermal.dtsi index dd74a5337d1f..a7077321613f 100644 --- a/arch/arm/boot/dts/dra7-iva-thermal.dtsi +++ b/arch/arm/boot/dts/dra7-iva-thermal.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for DRA7x SoC IVA thermal * - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 62ca89551219..27a6a83cc60c 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -1207,9 +1207,8 @@ <SYSC_IDLE_SMART>, <SYSC_IDLE_SMART_WKUP>; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>, - <&timer_sys_clk_div>; - clock-names = "fck", "timer_sys_ck"; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x36000 0x1000>; @@ -3352,8 +3351,8 @@ <SYSC_IDLE_SMART>, <SYSC_IDLE_SMART_WKUP>; /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ - clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>, <&timer_sys_clk_div>; - clock-names = "fck", "timer_sys_ck"; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x20000 0x1000>; @@ -3361,8 +3360,8 @@ timer5: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -3379,9 +3378,8 @@ <SYSC_IDLE_SMART>, <SYSC_IDLE_SMART_WKUP>; /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ - clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>, - <&timer_sys_clk_div>; - clock-names = "fck", "timer_sys_ck"; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x22000 0x1000>; @@ -3389,8 +3387,8 @@ timer6: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -3498,8 +3496,8 @@ timer14: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; ti,timer-pwm; }; @@ -3526,8 +3524,8 @@ timer15: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; ti,timer-pwm; }; @@ -3554,8 +3552,8 @@ timer16: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; ti,timer-pwm; }; @@ -4007,7 +4005,6 @@ target-module@80000 { /* 0x48880000, ap 83 0e.1 */ compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_otg_ss1"; reg = <0x80000 0x4>, <0x80010 0x4>; reg-names = "rev", "sysc"; @@ -4057,7 +4054,6 @@ target-module@c0000 { /* 0x488c0000, ap 79 06.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_otg_ss2"; reg = <0xc0000 0x4>, <0xc0010 0x4>; reg-names = "rev", "sysc"; @@ -4108,7 +4104,6 @@ usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_otg_ss3"; reg = <0x100000 0x4>, <0x100010 0x4>; reg-names = "rev", "sysc"; @@ -4157,7 +4152,6 @@ usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_otg_ss4"; reg = <0x140000 0x4>, <0x140010 0x4>; reg-names = "rev", "sysc"; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 099546be5014..cca6b123856f 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * * Based on "omap4.dtsi" */ diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts index a5d275ea7bd3..10da51bee42f 100644 --- a/arch/arm/boot/dts/dra71-evm.dts +++ b/arch/arm/boot/dts/dra71-evm.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ */ #include "dra71x.dtsi" diff --git a/arch/arm/boot/dts/dra71x.dtsi b/arch/arm/boot/dts/dra71x.dtsi index 695a08ed0360..cad0e4a2bd8d 100644 --- a/arch/arm/boot/dts/dra71x.dtsi +++ b/arch/arm/boot/dts/dra71x.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index c84b63bf0fc8..9273a7d6fa29 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts index 6e70858f6313..54dab0f212d1 100644 --- a/arch/arm/boot/dts/dra72-evm-revc.dts +++ b/arch/arm/boot/dts/dra72-evm-revc.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ */ #include "dra72-evm-common.dtsi" #include "dra72x-mmc-iodelay.dtsi" diff --git a/arch/arm/boot/dts/dra72-evm-tps65917.dtsi b/arch/arm/boot/dts/dra72-evm-tps65917.dtsi index 5ff9c43ef30b..7b433f549239 100644 --- a/arch/arm/boot/dts/dra72-evm-tps65917.dtsi +++ b/arch/arm/boot/dts/dra72-evm-tps65917.dtsi @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ */ /* * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/tps65917-q1.pdf + * https://www.ti.com/lit/ds/symlink/tps65917-q1.pdf */ &tps65917 { diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index 951152fe206a..6ea9936f7d9c 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ */ #include "dra72-evm-common.dtsi" #include "dra72x-mmc-iodelay.dtsi" diff --git a/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi index edad87c4292c..a9dce919d443 100644 --- a/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi +++ b/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi @@ -1,7 +1,7 @@ /* * MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs. * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi index ae23ec14e8fa..d403acc754b6 100644 --- a/arch/arm/boot/dts/dra72x.dtsi +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ * * Based on "omap4.dtsi" */ diff --git a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi index 214b9e6de2c3..e86da7a970b6 100644 --- a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi +++ b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi @@ -1,7 +1,7 @@ /* * MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs. * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index 46d8e7615180..e1850d6c841a 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ * * Based on "omap4.dtsi" */ @@ -49,27 +49,47 @@ reg = <0x41500000 0x100>; }; - omap_dwc3_4: omap_dwc3_4@48940000 { - compatible = "ti,dwc3"; - ti,hwmods = "usb_otg_ss4"; - reg = <0x48940000 0x10000>; - interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; + target-module@48940000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x48940000 0x4>, + <0x48940010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; - utmi-mode = <2>; - ranges; - status = "disabled"; - usb4: usb@48950000 { - compatible = "snps,dwc3"; - reg = <0x48950000 0x17000>; - interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "peripheral", - "host", - "otg"; - maximum-speed = "high-speed"; - dr_mode = "otg"; + ranges = <0x0 0x48940000 0x20000>; + + omap_dwc3_4: omap_dwc3_4@0 { + compatible = "ti,dwc3"; + reg = <0 0x10000>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges; + status = "disabled"; + usb4: usb@10000 { + compatible = "snps,dwc3"; + reg = <0x10000 0x17000>; + interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "peripheral", + "host", + "otg"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; }; }; diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index 820a0ece20d4..803981cc762e 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi index 42b8a205b64f..b69c7d40f5d8 100644 --- a/arch/arm/boot/dts/dra76x.dtsi +++ b/arch/arm/boot/dts/dra76x.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include "dra74x.dtsi" diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index b27a82072365..6c2f320be2f4 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -352,6 +352,14 @@ }; &pinctrl_1 { + bten: bten { + samsung,pins ="gpx1-7"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_DOWN>; + }; + wlanen: wlanen { samsung,pins = "gpx2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; @@ -364,6 +372,22 @@ samsung,pins = "gpx3-5"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; + + bthostwake: bthostwake { + samsung,pins = "gpx3-6"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; + + btwake: btwake { + samsung,pins = "gpx3-7"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT0>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_DOWN>; + }; }; &rtc { @@ -372,6 +396,23 @@ status = "okay"; }; +&serial_0 { + assigned-clocks = <&cmu CLK_SCLK_UART0>; + assigned-clock-rates = <100000000>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&bten &btwake &bthostwake>; + max-speed = <3000000>; + shutdown-gpios = <&gpx1 7 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx3 6 GPIO_ACTIVE_HIGH>; + clocks = <&s2mps14_osc S2MPS11_CLK_BT>; + }; +}; + &tmu { status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 044e5da64a76..d3fb45a56527 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -418,33 +418,26 @@ status = "disabled"; }; - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma0: pdma@12680000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12680000 0x1000>; - interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cmu CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@12690000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12690000 0x1000>; - interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cmu CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; + pdma0: pdma@12680000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12680000 0x1000>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma@12690000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12690000 0x1000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; }; adc: adc@126c0000 { diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index d2779a790ce3..a1e54449f33f 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -669,45 +669,37 @@ status = "disabled"; }; - amba: amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - pdma0: pdma@12680000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12680000 0x1000>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@12690000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12690000 0x1000>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - mdma1: mdma@12850000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12850000 0x1000>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_MDMA>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - }; + pdma0: pdma@12680000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12680000 0x1000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma@12690000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12690000 0x1000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + mdma1: mdma@12850000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12850000 0x1000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MDMA>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <1>; }; fimd: fimd@11c00000 { diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 3d791db6095c..5cc96f04a4fa 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -30,62 +30,58 @@ stdout-path = "serial2:115200n8"; }; - regulators { - compatible = "simple-bus"; - - vemmc_reg: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vemmc_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - tsp_reg: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "TSP_FIXED_VOLTAGES"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpl0 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + tsp_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "TSP_FIXED_VOLTAGES"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpl0 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - cam_af_28v_reg: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "8M_AF_2.8V_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpk1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + cam_af_28v_reg: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "8M_AF_2.8V_EN"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpk1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - cam_io_en_reg: regulator-3 { - compatible = "regulator-fixed"; - regulator-name = "CAM_IO_EN"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpe2 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + cam_io_en_reg: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "CAM_IO_EN"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpe2 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - cam_io_12v_reg: regulator-4 { - compatible = "regulator-fixed"; - regulator-name = "8M_1.2V_EN"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpe2 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + cam_io_12v_reg: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "8M_1.2V_EN"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpe2 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vt_core_15v_reg: regulator-5 { - compatible = "regulator-fixed"; - regulator-name = "VT_CORE_1.5V"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpe2 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vt_core_15v_reg: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "VT_CORE_1.5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpe2 2 GPIO_ACTIVE_HIGH>; + enable-active-high; }; gpio-keys { diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 02fde1a75ebd..99ce53b120ac 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -181,20 +181,6 @@ }; }; -&amba { - mdma0: mdma@12840000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12840000 0x1000>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_MDMA>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - power-domains = <&pd_lcd0>; - }; -}; - &camera { status = "okay"; @@ -616,6 +602,20 @@ /delete-property/dma-names; }; +&soc { + mdma0: mdma@12840000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12840000 0x1000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MDMA>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <1>; + power-domains = <&pd_lcd0>; + }; +}; + &sysram { smp-sram@0 { status = "disabled"; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index b4466232f0c1..33435ce79ce4 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -97,7 +97,7 @@ label = "LCD1"; }; - l2c: l2-cache-controller@10502000 { + l2c: cache-controller@10502000 { compatible = "arm,pl310-cache"; reg = <0x10502000 0x1000>; cache-unified; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index dc865be40751..8b11ad391252 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -33,20 +33,13 @@ reg = <0x0203F000 0x1000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - mmc_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + mmc_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; }; display-timings { diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 48868947373e..7002832eb4c0 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -213,7 +213,7 @@ label = "ISP"; }; - l2c: l2-cache-controller@10502000 { + l2c: cache-controller@10502000 { compatible = "arm,pl310-cache"; reg = <0x10502000 0x1000>; cache-unified; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index c4cc7611898c..59872d83da6e 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -84,60 +84,48 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - main_dc_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "MAIN_DC"; - regulator-always-on; - }; + main_dc_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "MAIN_DC"; + regulator-always-on; + }; - mmc_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "VDD_MMC"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; + mmc_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VDD_MMC"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; - reg_hdmi_en: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdmi-en"; - regulator-always-on; - }; + reg_hdmi_en: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "hdmi-en"; + regulator-always-on; + }; - vcc_1v2_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "VCC_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; + vcc_1v2_reg: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; - vcc_1v8_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; + vcc_1v8_reg: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; - vcc_3v3_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + vcc_3v3_reg: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; }; sound { diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index b6135af7ef39..e3dbe4166836 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -679,56 +679,48 @@ samsung,pmureg-phandle = <&pmu_system_controller>; }; - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - pdma0: pdma@121a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121A0000 0x1000>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@121b0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121B0000 0x1000>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - mdma0: mdma@10800000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x10800000 0x1000>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_MDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - }; - - mdma1: mdma@11c10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x11C10000 0x1000>; - interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_MDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - }; + pdma0: pdma@121a0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121A0000 0x1000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma@121b0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121B0000 0x1000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + mdma0: mdma@10800000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x10800000 0x1000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <1>; + }; + + mdma1: mdma@11c10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x11C10000 0x1000>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <1>; }; gsc_0: gsc@13e00000 { diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi index 369a8a7f2105..e5d0a2a4f648 100644 --- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi @@ -3,7 +3,7 @@ * Exynos5410 SoC pin-mux and pin-config device tree source * * Copyright (c) 2013 Hardkernel Co., Ltd. - * http://www.hardkernel.com + * https://www.hardkernel.com */ #include <dt-bindings/pinctrl/samsung.h> diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 2eab80bf5f3a..abe75b9e39f5 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -189,34 +189,26 @@ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; }; - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - pdma0: pdma@121a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121a0000 0x1000>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; + pdma0: pdma@121a0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121a0000 0x1000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; - pdma1: pdma@121b0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121b0000 0x1000>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; + pdma1: pdma@121b0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121b0000 0x1000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; }; audi2s0: i2s@3830000 { diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index e3f2afe8359a..83fa800fa1eb 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -32,40 +32,31 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd: fixed-regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd-supply"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; + vdd: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "vdd-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; - dbvdd: fixed-regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "dbvdd-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + dbvdd: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "dbvdd-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - spkvdd: fixed-regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "spkvdd-supply"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + spkvdd: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "spkvdd-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; }; - usb300_vbus_reg: regulator-usb300 { + usb300_vbus_reg: regulator-3 { compatible = "regulator-fixed"; regulator-name = "VBUS0"; regulator-min-microvolt = <5000000>; @@ -76,7 +67,7 @@ enable-active-high; }; - usb301_vbus_reg: regulator-usb301 { + usb301_vbus_reg: regulator-4 { compatible = "regulator-fixed"; regulator-name = "VBUS1"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index b672080e7469..c76460b70532 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -433,76 +433,68 @@ power-domains = <&mau_pd>; }; - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - adma: adma@3880000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x03880000 0x1000>; - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock_audss EXYNOS_ADMA>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <6>; - #dma-requests = <16>; - power-domains = <&mau_pd>; - }; - - pdma0: pdma@121a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121A0000 0x1000>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@121b0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x121B0000 0x1000>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - mdma0: mdma@10800000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x10800000 0x1000>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_MDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - }; + adma: adma@3880000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x03880000 0x1000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock_audss EXYNOS_ADMA>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <6>; + #dma-requests = <16>; + power-domains = <&mau_pd>; + }; - mdma1: mdma@11c10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x11C10000 0x1000>; - interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_MDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; - /* - * MDMA1 can support both secure and non-secure - * AXI transactions. When this is enabled in - * the kernel for boards that run in secure - * mode, we are getting imprecise external - * aborts causing the kernel to oops. - */ - status = "disabled"; - }; + pdma0: pdma@121a0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121A0000 0x1000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma@121b0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121B0000 0x1000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + mdma0: mdma@10800000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x10800000 0x1000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <1>; + }; + + mdma1: mdma@11c10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x11C10000 0x1000>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <1>; + /* + * MDMA1 can support both secure and non-secure + * AXI transactions. When this is enabled in + * the kernel for boards that run in secure + * mode, we are getting imprecise external + * aborts causing the kernel to oops. + */ + status = "disabled"; }; i2s0: i2s@3830000 { diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index ab27ff8bc3dc..afe090578e8f 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -411,12 +411,6 @@ status = "okay"; }; -&bus_fsys { - operating-points-v2 = <&bus_fsys2_opp_table>; - devfreq = <&bus_wcore>; - status = "okay"; -}; - &bus_fsys2 { operating-points-v2 = <&bus_fsys2_opp_table>; devfreq = <&bus_wcore>; diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi index dfb99ab53c3e..526729dad53f 100644 --- a/arch/arm/boot/dts/exynos5800.dtsi +++ b/arch/arm/boot/dts/exynos5800.dtsi @@ -23,17 +23,17 @@ &cluster_a15_opp_table { opp-2000000000 { opp-hz = /bits/ 64 <2000000000>; - opp-microvolt = <1312500>; + opp-microvolt = <1312500 1312500 1500000>; clock-latency-ns = <140000>; }; opp-1900000000 { opp-hz = /bits/ 64 <1900000000>; - opp-microvolt = <1262500>; + opp-microvolt = <1262500 1262500 1500000>; clock-latency-ns = <140000>; }; opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1237500>; + opp-microvolt = <1237500 1237500 1500000>; clock-latency-ns = <140000>; }; opp-1700000000 { diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index 9c207a690df5..f0af1bf2b4d8 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -71,7 +71,7 @@ interrupt-parent = <&gic>; ranges = <0 0xfc000000 0x2000000>; - L2: l2-cache { + L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0x100000 0x100000>; interrupts = <0 15 4>; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 696e6982a688..3ee7967c202d 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -381,7 +381,7 @@ interrupts = <1 13 0xf01>; }; - l2: l2-cache { + l2: cache-controller { compatible = "arm,pl310-cache"; reg = <0x00a10000 0x100000>; interrupts = <0 15 4>; diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi index b30448cde582..9b940987864c 100644 --- a/arch/arm/boot/dts/imx1.dtsi +++ b/arch/arm/boot/dts/imx1.dtsi @@ -125,7 +125,7 @@ }; pwm: pwm@208000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx1-pwm"; reg = <0x00208000 0x1000>; interrupts = <34>; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index c5edff381213..18289f6fb1f3 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -442,7 +442,7 @@ status = "disabled"; }; - ocotp@8002c000 { + efuse@8002c000 { compatible = "fsl,imx23-ocotp", "fsl,ocotp"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 1123e683025c..1ab19f1268f8 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -411,7 +411,7 @@ pwm2: pwm@53fa0000 { compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; - #pwm-cells = <2>; + #pwm-cells = <3>; reg = <0x53fa0000 0x4000>; clocks = <&clks 106>, <&clks 52>; clock-names = "ipg", "per"; @@ -430,7 +430,7 @@ pwm3: pwm@53fa8000 { compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; - #pwm-cells = <2>; + #pwm-cells = <3>; reg = <0x53fa8000 0x4000>; clocks = <&clks 107>, <&clks 52>; clock-names = "ipg", "per"; @@ -453,7 +453,7 @@ interrupts = <22>; }; - esdhc1: esdhc@53fb4000 { + esdhc1: mmc@53fb4000 { compatible = "fsl,imx25-esdhc"; reg = <0x53fb4000 0x4000>; interrupts = <9>; @@ -462,7 +462,7 @@ status = "disabled"; }; - esdhc2: esdhc@53fb8000 { + esdhc2: mmc@53fb8000 { compatible = "fsl,imx25-esdhc"; reg = <0x53fb8000 0x4000>; interrupts = <8>; @@ -488,7 +488,7 @@ pwm4: pwm@53fc8000 { compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; - #pwm-cells = <2>; + #pwm-cells = <3>; reg = <0x53fc8000 0x4000>; clocks = <&clks 108>, <&clks 52>; clock-names = "ipg", "per"; @@ -535,14 +535,14 @@ pwm1: pwm@53fe0000 { compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; - #pwm-cells = <2>; + #pwm-cells = <3>; reg = <0x53fe0000 0x4000>; clocks = <&clks 105>, <&clks 52>; clock-names = "ipg", "per"; interrupts = <26>; }; - iim: iim@53ff0000 { + iim: efuse@53ff0000 { compatible = "fsl,imx25-iim", "fsl,imx27-iim"; reg = <0x53ff0000 0x4000>; interrupts = <19>; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 002cd223f22d..fc0b318f8733 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -134,7 +134,7 @@ }; pwm: pwm@10006000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx27-pwm"; reg = <0x10006000 0x1000>; interrupts = <23>; @@ -265,7 +265,7 @@ status = "disabled"; }; - sdhci1: sdhci@10013000 { + sdhci1: mmc@10013000 { compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; reg = <0x10013000 0x1000>; interrupts = <11>; @@ -277,7 +277,7 @@ status = "disabled"; }; - sdhci2: sdhci@10014000 { + sdhci2: mmc@10014000 { compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; reg = <0x10014000 0x1000>; interrupts = <10>; @@ -431,7 +431,7 @@ status = "disabled"; }; - sdhci3: sdhci@1001e000 { + sdhci3: mmc@1001e000 { compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; reg = <0x1001e000 0x1000>; interrupts = <9>; @@ -540,7 +540,7 @@ #clock-cells = <1>; }; - iim: iim@10028000 { + iim: efuse@10028000 { compatible = "fsl,imx27-iim"; reg = <0x10028000 0x1000>; interrupts = <62>; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index a1cbbeb39a4f..a2b799c56f8f 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -1011,7 +1011,7 @@ status = "disabled"; }; - ocotp: ocotp@8002c000 { + ocotp: efuse@8002c000 { compatible = "fsl,imx28-ocotp", "fsl,ocotp"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 18270ec648fe..45333f7e10ea 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -173,7 +173,7 @@ reg = <0x50000000 0x100000>; ranges; - sdhci1: sdhci@50004000 { + sdhci1: mmc@50004000 { compatible = "fsl,imx31-mmc"; reg = <0x50004000 0x4000>; interrupts = <9>; @@ -184,7 +184,7 @@ status = "disabled"; }; - sdhci2: sdhci@50008000 { + sdhci2: mmc@50008000 { compatible = "fsl,imx31-mmc"; reg = <0x50008000 0x4000>; interrupts = <8>; @@ -217,7 +217,7 @@ status = "disabled"; }; - iim: iim@5001c000 { + iim: efuse@5001c000 { compatible = "fsl,imx31-iim", "fsl,imx27-iim"; reg = <0x5001c000 0x1000>; interrupts = <19>; @@ -327,7 +327,7 @@ interrupts = <26>; clocks = <&clks 10>, <&clks 42>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index 2ebf2c1fa682..aba16252faab 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -59,7 +59,7 @@ interrupt-parent = <&avic>; ranges; - L2: l2-cache@30000000 { + L2: cache-controller@30000000 { compatible = "arm,l210-cache"; reg = <0x30000000 0x1000>; cache-unified; @@ -231,7 +231,7 @@ #interrupt-cells = <2>; }; - esdhc1: esdhc@53fb4000 { + esdhc1: mmc@53fb4000 { compatible = "fsl,imx35-esdhc"; reg = <0x53fb4000 0x4000>; interrupts = <7>; @@ -240,7 +240,7 @@ status = "disabled"; }; - esdhc2: esdhc@53fb8000 { + esdhc2: mmc@53fb8000 { compatible = "fsl,imx35-esdhc"; reg = <0x53fb8000 0x4000>; interrupts = <8>; @@ -249,7 +249,7 @@ status = "disabled"; }; - esdhc3: esdhc@53fbc000 { + esdhc3: mmc@53fbc000 { compatible = "fsl,imx35-esdhc"; reg = <0x53fbc000 0x4000>; interrupts = <9>; @@ -320,7 +320,7 @@ status = "disabled"; }; - iim@53ff0000 { + efuse@53ff0000 { compatible = "fsl,imx35-iim"; reg = <0x53ff0000 0x4000>; interrupts = <19>; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 1f4ecbca5225..b6b2e6af9b96 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -115,7 +115,7 @@ reg = <0x50000000 0x40000>; ranges; - esdhc1: esdhc@50004000 { + esdhc1: mmc@50004000 { compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; reg = <0x50004000 0x4000>; interrupts = <1>; @@ -127,7 +127,7 @@ status = "disabled"; }; - esdhc2: esdhc@50008000 { + esdhc2: mmc@50008000 { compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; reg = <0x50008000 0x4000>; interrupts = <2>; @@ -176,7 +176,7 @@ status = "disabled"; }; - esdhc3: esdhc@50020000 { + esdhc3: mmc@50020000 { compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; reg = <0x50020000 0x4000>; interrupts = <3>; @@ -188,7 +188,7 @@ status = "disabled"; }; - esdhc4: esdhc@50024000 { + esdhc4: mmc@50024000 { compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc"; reg = <0x50024000 0x4000>; interrupts = <4>; @@ -289,7 +289,7 @@ }; pwm1: pwm@53fb4000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; reg = <0x53fb4000 0x4000>; clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, @@ -299,7 +299,7 @@ }; pwm2: pwm@53fb8000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; reg = <0x53fb8000 0x4000>; clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts index 4344632f7940..6ecb83e7f336 100644 --- a/arch/arm/boot/dts/imx51-ts4800.dts +++ b/arch/arm/boot/dts/imx51-ts4800.dts @@ -113,6 +113,7 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm_backlight>; status = "okay"; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index d3583aad8323..985e1be03ad6 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -185,7 +185,7 @@ reg = <0x70000000 0x40000>; ranges; - esdhc1: esdhc@70004000 { + esdhc1: mmc@70004000 { compatible = "fsl,imx51-esdhc"; reg = <0x70004000 0x4000>; interrupts = <1>; @@ -196,7 +196,7 @@ status = "disabled"; }; - esdhc2: esdhc@70008000 { + esdhc2: mmc@70008000 { compatible = "fsl,imx51-esdhc"; reg = <0x70008000 0x4000>; interrupts = <2>; @@ -245,7 +245,7 @@ status = "disabled"; }; - esdhc3: esdhc@70020000 { + esdhc3: mmc@70020000 { compatible = "fsl,imx51-esdhc"; reg = <0x70020000 0x4000>; interrupts = <3>; @@ -257,7 +257,7 @@ status = "disabled"; }; - esdhc4: esdhc@70024000 { + esdhc4: mmc@70024000 { compatible = "fsl,imx51-esdhc"; reg = <0x70024000 0x4000>; interrupts = <4>; @@ -400,7 +400,7 @@ }; pwm1: pwm@73fb4000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; reg = <0x73fb4000 0x4000>; clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, @@ -410,7 +410,7 @@ }; pwm2: pwm@73fb8000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; reg = <0x73fb8000 0x4000>; clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, @@ -466,7 +466,7 @@ reg = <0x83f00000 0x60>; }; - iim: iim@83f98000 { + iim: efuse@83f98000 { compatible = "fsl,imx51-iim", "fsl,imx27-iim"; reg = <0x83f98000 0x4000>; interrupts = <69>; diff --git a/arch/arm/boot/dts/imx53-kp.dtsi b/arch/arm/boot/dts/imx53-kp.dtsi index 8b25416a5303..4508f34139a0 100644 --- a/arch/arm/boot/dts/imx53-kp.dtsi +++ b/arch/arm/boot/dts/imx53-kp.dtsi @@ -162,6 +162,14 @@ >; }; +&pwm1 { + #pwm-cells = <2>; +}; + +&pwm2 { + #pwm-cells = <2>; +}; + &uart1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts index daab56abe94a..a1a6228d1aa6 100644 --- a/arch/arm/boot/dts/imx53-m53evk.dts +++ b/arch/arm/boot/dts/imx53-m53evk.dts @@ -321,6 +321,7 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts index 5ff9a179c83c..f7dcdf96e5c0 100644 --- a/arch/arm/boot/dts/imx53-ppd.dts +++ b/arch/arm/boot/dts/imx53-ppd.dts @@ -176,7 +176,7 @@ power-supply = <®_3v3_lcd>; }; - leds { + leds-brightness { compatible = "pwm-leds"; alarm-brightness { @@ -185,6 +185,32 @@ }; }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_alarmled_pins>; + + alarm1 { + label = "alarm:red"; + gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; + }; + + alarm2 { + label = "alarm:yellow"; + gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; + }; + + alarm3 { + label = "alarm:blue"; + gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + }; + + alarm4 { + label = "alarm:silenced"; + gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; + }; + }; + gpio-poweroff { compatible = "gpio-poweroff"; gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; @@ -598,12 +624,14 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; &pwm2 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; status = "okay"; @@ -909,18 +937,10 @@ MX53_PAD_NANDF_CS3__GPIO6_16 0x0 /* POWER_AND_BOOT_STATUS_INDICATOR */ MX53_PAD_PATA_INTRQ__GPIO7_2 0x1e4 - /* ACTIVATE_ALARM_LIGHT_RED */ - MX53_PAD_PATA_DIOR__GPIO7_3 0x0 - /* ACTIVATE_ALARM_LIGHT_YELLOW */ - MX53_PAD_PATA_DA_1__GPIO7_7 0x0 - /* ACTIVATE_ALARM_LIGHT_CYAN */ - MX53_PAD_PATA_DA_2__GPIO7_8 0x0 /* RUNNING_ON_BATTERY_INDICATOR_GREEN */ MX53_PAD_GPIO_16__GPIO7_11 0x0 /* BATTERY_STATUS_INDICATOR_AMBER */ MX53_PAD_GPIO_17__GPIO7_12 0x0 - /* AUDIO_ALARMS_SILENCED_INDICATOR */ - MX53_PAD_GPIO_18__GPIO7_13 0x0 >; }; @@ -1080,4 +1100,17 @@ MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x180 >; }; + + pinctrl_alarmled_pins: qmx6alarmledgrp { + fsl,pins = < + /* ACTIVATE_ALARM_LIGHT_RED */ + MX53_PAD_PATA_DIOR__GPIO7_3 0x0 + /* ACTIVATE_ALARM_LIGHT_YELLOW */ + MX53_PAD_PATA_DA_1__GPIO7_7 0x0 + /* ACTIVATE_ALARM_LIGHT_CYAN */ + MX53_PAD_PATA_DA_2__GPIO7_8 0x0 + /* AUDIO_ALARMS_SILENCED_INDICATOR */ + MX53_PAD_GPIO_18__GPIO7_13 0x0 + >; + }; }; diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi index ea90fd95ad01..9a6cb138adf3 100644 --- a/arch/arm/boot/dts/imx53-tqma53.dtsi +++ b/arch/arm/boot/dts/imx53-tqma53.dtsi @@ -209,6 +209,14 @@ }; }; +&pwm1 { + #pwm-cells = <2>; +}; + +&pwm2 { + #pwm-cells = <2>; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi index 4ab135906949..7c9730f3f820 100644 --- a/arch/arm/boot/dts/imx53-tx53.dtsi +++ b/arch/arm/boot/dts/imx53-tx53.dtsi @@ -542,7 +542,6 @@ &pwm2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; - #pwm-cells = <3>; }; &sdma { diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index afa57bf7b0ed..500eeaa3a27c 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -236,7 +236,7 @@ reg = <0x50000000 0x40000>; ranges; - esdhc1: esdhc@50004000 { + esdhc1: mmc@50004000 { compatible = "fsl,imx53-esdhc"; reg = <0x50004000 0x4000>; interrupts = <1>; @@ -248,7 +248,7 @@ status = "disabled"; }; - esdhc2: esdhc@50008000 { + esdhc2: mmc@50008000 { compatible = "fsl,imx53-esdhc"; reg = <0x50008000 0x4000>; interrupts = <2>; @@ -301,7 +301,7 @@ status = "disabled"; }; - esdhc3: esdhc@50020000 { + esdhc3: mmc@50020000 { compatible = "fsl,imx53-esdhc"; reg = <0x50020000 0x4000>; interrupts = <3>; @@ -313,7 +313,7 @@ status = "disabled"; }; - esdhc4: esdhc@50024000 { + esdhc4: mmc@50024000 { compatible = "fsl,imx53-esdhc"; reg = <0x50024000 0x4000>; interrupts = <4>; @@ -525,7 +525,7 @@ }; pwm1: pwm@53fb4000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; reg = <0x53fb4000 0x4000>; clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, @@ -535,7 +535,7 @@ }; pwm2: pwm@53fb8000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; reg = <0x53fb8000 0x4000>; clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, @@ -667,7 +667,7 @@ reg = <0x63f00000 0x60>; }; - iim: iim@63f98000 { + iim: efuse@63f98000 { compatible = "fsl,imx53-iim", "fsl,imx27-iim"; reg = <0x63f98000 0x4000>; interrupts = <69>; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts index 37f80ab8ccd0..809ca5611072 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts @@ -79,5 +79,6 @@ }; &pwm1 { + #pwm-cells = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts index 8d8c8c27e482..4d58cb4436d9 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts @@ -69,5 +69,6 @@ }; &pwm3 { + #pwm-cells = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6dl-mamoj.dts b/arch/arm/boot/dts/imx6dl-mamoj.dts index 385ce7b0029e..028951955bde 100644 --- a/arch/arm/boot/dts/imx6dl-mamoj.dts +++ b/arch/arm/boot/dts/imx6dl-mamoj.dts @@ -303,6 +303,7 @@ }; &pwm3 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6dl-prtrvt.dts b/arch/arm/boot/dts/imx6dl-prtrvt.dts new file mode 100644 index 000000000000..fa882458957b --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-prtrvt.dts @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-prti6q.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + model = "Protonic RVT board"; + compatible = "prt,prtrvt", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x10000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-debug0 { + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + nfc@0 { + compatible = "ti,trf7970a"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + spi-max-frequency = <2000000>; + interrupts-extended = <&gpio5 14 IRQ_TYPE_LEVEL_LOW>; + ti,enable-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>, + <&gpio5 11 GPIO_ACTIVE_LOW>; + vin-supply = <®_3v3>; + vin-voltage-override = <3100000>; + autosuspend-delay = <30000>; + irq-status-read-quirk; + en2-rf-quirk; + t5t-rmb-extra-byte-quirk; + status = "okay"; + }; +}; + +&i2c3 { + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* nc */ + channel@4 { + reg = <4>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* nc */ + channel@5 { + reg = <5>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can1_l */ + channel@6 { + reg = <6>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can1_h */ + channel@7 { + reg = <7>; + ti,gain = <3>; + ti,datarate = <3>; + }; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&pcie { + status = "okay"; +}; + +&usbh1 { + status = "disabled"; +}; + +&vpu { + status = "disabled"; +}; + +&iomuxc { + pinctrl_can1phy: can1phy { + fsl,pins = < + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + /* CAN1_TERM */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + /* NFC_ASK_OOK */ + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x100b1 + /* NFC_PWR_EN */ + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x100b1 + /* NFC_EN2 */ + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x100b1 + /* NFC_EN */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 + /* NFC_MOD */ + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1 + /* NFC_IRQ */ + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts new file mode 100644 index 000000000000..306b4f7bf762 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016 Protonic Holland + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-prti6q.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/sound/fsl-imx-audmux.h> + +/ { + model = "Protonic VT7"; + compatible = "prt,prtvt7", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm1 0 500000>; + brightness-levels = <0 20 81 248 1000>; + default-brightness-level = <20>; + num-interpolated-steps = <21>; + power-supply = <®_bl_12v0>; + enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + }; + + keys { + compatible = "gpio-keys"; + autorepeat; + + esc { + label = "GPIO Key ESC"; + linux,code = <KEY_ESC>; + gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>; + }; + + up { + label = "GPIO Key UP"; + linux,code = <KEY_UP>; + gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>; + }; + + down { + label = "GPIO Key DOWN"; + linux,code = <KEY_DOWN>; + gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>; + }; + + enter { + label = "GPIO Key Enter"; + linux,code = <KEY_ENTER>; + gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>; + }; + + cycle { + label = "GPIO Key CYCLE"; + linux,code = <KEY_CYCLEWINDOWS>; + gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>; + }; + + f1 { + label = "GPIO Key F1"; + linux,code = <KEY_F1>; + gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>; + }; + + f2 { + label = "GPIO Key F2"; + linux,code = <KEY_F2>; + gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>; + }; + + f3 { + label = "GPIO Key F3"; + linux,code = <KEY_F3>; + gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>; + }; + + f4 { + label = "GPIO Key F4"; + linux,code = <KEY_F4>; + gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>; + }; + + f5 { + label = "GPIO Key F5"; + linux,code = <KEY_F5>; + gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>; + }; + + f6 { + label = "GPIO Key F6"; + linux,code = <KEY_F6>; + gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>; + }; + + f7 { + label = "GPIO Key F7"; + linux,code = <KEY_F7>; + gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>; + }; + + f8 { + label = "GPIO Key F8"; + linux,code = <KEY_F8>; + gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>; + }; + + f9 { + label = "GPIO Key F9"; + linux,code = <KEY_F9>; + gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>; + }; + + f10 { + label = "GPIO Key F10"; + linux,code = <KEY_F10>; + gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-debug0 { + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_bl_12v0: regulator-bl-12v0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_bl_12v0>; + regulator-name = "bl-12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "prti6q-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Line", "Line In Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "External Speaker", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + system-clock-frequency = <0>; + }; + + simple-audio-card,codec { + sound-dai = <&sgtl5000>; + bitclock-master; + frame-master; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux-ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN 0 + IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TFSDIR 0 + IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux-pins3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) + 0 IMX_AUDMUX_V2_PDCR_TXRXEN + >; + }; +}; + +&can1 { + pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&i2c1 { + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0xa>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec>; + #sound-dai-cells = <0>; + clocks = <&clks 201>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + VDDD-supply = <®_1v8>; + }; +}; + +&i2c3 { + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + gpio_pca: gpio@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + interrupts-extended = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&ipu1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; + status = "okay"; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&ssi1 { + #sound-dai-cells = <0>; + fsl,mode = "ac97-slave"; + status = "okay"; +}; + +&usbh1 { + status = "disabled"; +}; + +&vpu { + status = "disabled"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 + >; + }; + + pinctrl_can1phy: can1phy { + fsl,pins = < + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + /* CAN1_TERM */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_codec: codecgrp { + fsl,pins = < + /* AUDIO_nRESET */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + /* ITU656_nRESET */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + /* ITU656_nPDN */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 + >; + }; + + pinctrl_ipu1_disp: ipudisp1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xb0 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xb0 + + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xb0 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xb0 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xb0 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xb0 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xb0 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xb0 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xb0 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xb0 + + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xb0 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xb0 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xb0 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xb0 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xb0 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xb0 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xb0 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xb0 + + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xb0 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xb0 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xb0 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xb0 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xb0 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xb0 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xb0 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xb0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 + >; + }; + + pinctrl_reg_bl_12v0: 12blgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + >; + }; + + pinctrl_tsc: tscgrp { + + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi index 2b9423d55c37..c4a235d212b6 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -540,7 +540,6 @@ }; &pwm1 { - #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "disabled"; diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi index 37c63402157b..fc81f2f4b62d 100644 --- a/arch/arm/boot/dts/imx6q-ba16.dtsi +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi @@ -334,6 +334,7 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts index a2dd7e549568..a685b1c3208f 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts +++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts @@ -253,7 +253,6 @@ &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; - #pwm-cells = <3>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-display5.dtsi b/arch/arm/boot/dts/imx6q-display5.dtsi index 83524bb99eb3..fef5d7254536 100644 --- a/arch/arm/boot/dts/imx6q-display5.dtsi +++ b/arch/arm/boot/dts/imx6q-display5.dtsi @@ -399,7 +399,6 @@ }; &pwm2 { - #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-kp.dtsi b/arch/arm/boot/dts/imx6q-kp.dtsi index 24c8169baf44..1ade0bff681d 100644 --- a/arch/arm/boot/dts/imx6q-kp.dtsi +++ b/arch/arm/boot/dts/imx6q-kp.dtsi @@ -378,12 +378,14 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; &pwm2 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-mccmon6.dts b/arch/arm/boot/dts/imx6q-mccmon6.dts index a4d295455e67..55692c73943d 100644 --- a/arch/arm/boot/dts/imx6q-mccmon6.dts +++ b/arch/arm/boot/dts/imx6q-mccmon6.dts @@ -237,7 +237,6 @@ }; &pwm2 { - #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts index 69f170ff31c5..52e3567d1859 100644 --- a/arch/arm/boot/dts/imx6q-novena.dts +++ b/arch/arm/boot/dts/imx6q-novena.dts @@ -455,6 +455,7 @@ }; &pwm1 { + #pwm-cells = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-pistachio.dts b/arch/arm/boot/dts/imx6q-pistachio.dts index a31b17eaf51c..7a33e54cc0f1 100644 --- a/arch/arm/boot/dts/imx6q-pistachio.dts +++ b/arch/arm/boot/dts/imx6q-pistachio.dts @@ -570,6 +570,7 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-prti6q.dts b/arch/arm/boot/dts/imx6q-prti6q.dts new file mode 100644 index 000000000000..de6cbaab8b49 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-prti6q.dts @@ -0,0 +1,543 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-prti6q.dtsi" +#include <dt-bindings/leds/common.h> +#include <dt-bindings/sound/fsl-imx-audmux.h> + +/ { + model = "Protonic PRTI6Q board"; + compatible = "prt,prti6q", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xf0000000>; + }; + + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 16 64 255>; + num-interpolated-steps = <16>; + default-brightness-level = <1>; + power-supply = <®_3v3>; + enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + }; + + can_osc: can-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-debug0 { + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-debug1 { + function = LED_FUNCTION_SD; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + }; + + panel { + compatible = "kyo,tcg121xglp"; + backlight = <&backlight_lcd>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_wifi: regulator-wifi { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + enable-active-high; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "regulator-WL12xx"; + startup-delay-us = <70000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "prti6q-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Line", "Line In Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "External Speaker", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + system-clock-frequency = <0>; + }; + + simple-audio-card,codec { + sound-dai = <&sgtl5000>; + bitclock-master; + frame-master; + }; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-in; + spdif-out; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux-ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN 0 + IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TFSDIR 0 + IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux-pins3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) + 0 IMX_AUDMUX_V2_PDCR_TXRXEN + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + status = "okay"; + + can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can3>; + clocks = <&can_osc>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <5000000>; + }; + + adc@1 { + compatible = "ti,adc128s052"; + reg = <1>; + spi-max-frequency = <2000000>; + vref-supply = <®_3v3>; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ9031RNX PHY */ + rgmii_phy: ethernet-phy@4 { + reg = <4>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0xa>; + #sound-dai-cells = <0>; + clocks = <&clks 201>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + VDDD-supply = <®_1v8>; + }; +}; + +/* DDC */ +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* can2_l */ + channel@4 { + reg = <4>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can2_h */ + channel@5 { + reg = <5>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can1_l */ + channel@6 { + reg = <6>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can1_h */ + channel@7 { + reg = <7>; + ti,gain = <3>; + ti,datarate = <3>; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&sata { + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "okay"; +}; + +&ssi1 { + #sound-dai-cells = <0>; + fsl,mode = "ac97-slave"; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + pinctrl-0 = <&pinctrl_usbotg &pinctrl_usbotg_id>; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + vmmc-supply = <®_wifi>; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + wifi { + compatible = "ti,wl1271"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = "38400000"; + tcxo-clock-frequency = "19200000"; + }; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b008 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b008 + >; + }; + + pinctrl_can3: can3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 + >; + }; + + pinctrl_ecspi2_cs: ecspi2csgrp { + fsl,pins = < + /* ADC128S022 CS */ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + /* NOTE: DDC is done via I2C2, so DON'T + * configure DDC pins for HDMI! + */ + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + /* DDC */ + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg_id: usbotgidgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f058 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + /* WL12xx IRQ */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880 + >; + }; + + pinctrl_wifi_npd: wifinpd { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-prtwd2.dts b/arch/arm/boot/dts/imx6q-prtwd2.dts new file mode 100644 index 000000000000..dffafbcaa7af --- /dev/null +++ b/arch/arm/boot/dts/imx6q-prtwd2.dts @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2018 Protonic Holland + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-prti6q.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + model = "Protonic WD2 board"; + compatible = "prt,prtwd2", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + usdhc2_wifi_pwrseq: usdhc2_wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; + }; + + /* PRTWD2 rev 1 bitbang I2C for Ethernet Switch */ + i2c@4 { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + i2c-gpio,delay-us = <20>; /* ~10 kHz */ + i2c-gpio,scl-output-only; + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>; + clock-names = "ipg", "ahb"; + status = "okay"; + + fixed-link { + speed = <100>; + pause; + full-duplex; + }; +}; + +&i2c3 { + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* V in */ + channel@4 { + reg = <4>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* I charge */ + channel@5 { + reg = <5>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* V bus */ + channel@6 { + reg = <6>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* nc */ + channel@7 { + reg = <7>; + ti,gain = <1>; + ti,datarate = <3>; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc2_wifi_pwrseq>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_eth_chg>; + + pinctrl_can1phy: can1phy { + fsl,pins = < + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x130b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 + + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1f8b0 + MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f8b0 + >; + }; + + pinctrl_usb_eth_chg: usbethchggrp { + fsl,pins = < + /* USB charging control */ + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x130b0 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x130b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x130b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x130b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_wifi_npd: wifinpd { + fsl,pins = < + /* WL_REG_ON */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts index bfff87ce2e1f..861e05d53157 100644 --- a/arch/arm/boot/dts/imx6q-tbs2910.dts +++ b/arch/arm/boot/dts/imx6q-tbs2910.dts @@ -99,8 +99,20 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + phy-handle = <&phy>; status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@4 { + reg = <4>; + qca,clk-out-frequency = <125000000>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + }; + }; }; &hdmi { diff --git a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts index c54362fcc508..a57c2e3a8435 100644 --- a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts +++ b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts @@ -203,6 +203,7 @@ }; &pwm2 { + #pwm-cells = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index e34be8fabd93..dbdd7db60325 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -371,6 +371,7 @@ }; &pwm4 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "disabled"; diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi index b8e74ab3c993..2577eb4f535a 100644 --- a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi @@ -211,6 +211,7 @@ }; &pwm3 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi index 376750882ed3..d38630d4b892 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi @@ -336,6 +336,7 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 240b86d2eb71..0930194fd960 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -312,6 +312,7 @@ /* Colibri PWM<A> */ &pwm3 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "disabled"; @@ -362,7 +363,6 @@ }; &usbotg { - pinctrl-names = "default"; disable-over-current; dr_mode = "peripheral"; status = "disabled"; diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi index e3be453d8a4a..67042793b0ca 100644 --- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi @@ -233,6 +233,7 @@ }; &pwm1 { + #pwm-cells = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi index 70d26616d771..35e230f991f1 100644 --- a/arch/arm/boot/dts/imx6qdl-emcon.dtsi +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi @@ -737,14 +737,17 @@ }; &pwm1 { + #pwm-cells = <2>; status = "okay"; }; &pwm3 { + #pwm-cells = <2>; status = "okay"; }; &pwm4 { + #pwm-cells = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index 419a7cdc8ab5..7705285d9e3c 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> / { /* these are used by bootloader for disabling nodes */ @@ -19,6 +20,53 @@ bootargs = "console=ttymxc1,115200"; }; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = <BTN_1>; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = <BTN_2>; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = <BTN_3>; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = <BTN_4>; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = <BTN_5>; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -102,6 +150,103 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 GPIO_ACTIVE_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_an1"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + eeprom1: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; @@ -126,13 +271,6 @@ pagesize = <16>; }; - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - rtc: ds1672@68 { compatible = "dallas,ds1672"; reg = <0x68>; @@ -387,6 +525,7 @@ fsl,pins = < MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 60563ff0b7ce..a46ea98228c2 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> / { /* these are used by bootloader for disabling nodes */ @@ -28,6 +29,53 @@ default-brightness-level = <7>; }; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = <BTN_1>; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = <BTN_2>; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = <BTN_3>; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = <BTN_4>; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = <BTN_5>; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -165,6 +213,109 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 GPIO_ACTIVE_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + + channel@29 { + gw,mode = <1>; + reg = <0x29>; + label = "vdd_an1"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + eeprom1: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; @@ -189,13 +340,6 @@ pagesize = <16>; }; - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - rtc: ds1672@68 { compatible = "dallas,ds1672"; reg = <0x68>; @@ -365,6 +509,7 @@ }; &pwm4 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; @@ -504,6 +649,7 @@ fsl,pins = < MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 8942bec65c5c..a28e79463d0c 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> / { /* these are used by bootloader for disabling nodes */ @@ -28,6 +29,53 @@ default-brightness-level = <7>; }; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = <BTN_1>; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = <BTN_2>; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = <BTN_3>; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = <BTN_4>; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = <BTN_5>; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -158,6 +206,115 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 GPIO_ACTIVE_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + + channel@26 { + gw,mode = <1>; + reg = <0x26>; + label = "vdd_gps"; + }; + + channel@29 { + gw,mode = <1>; + reg = <0x29>; + label = "vdd_an1"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + eeprom1: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; @@ -182,13 +339,6 @@ pagesize = <16>; }; - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - rtc: ds1672@68 { compatible = "dallas,ds1672"; reg = <0x68>; @@ -356,6 +506,7 @@ }; &pwm4 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; @@ -486,6 +637,7 @@ fsl,pins = < MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index c40583dbd96d..b5f934b8a239 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/sound/fsl-imx-audmux.h> / { @@ -29,6 +30,53 @@ default-brightness-level = <7>; }; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = <BTN_1>; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = <BTN_2>; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = <BTN_3>; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = <BTN_4>; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = <BTN_5>; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -195,6 +243,117 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 GPIO_ACTIVE_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + + channel@26 { + gw,mode = <1>; + reg = <0x26>; + label = "vdd_gps"; + }; + }; + + fan-controller@2c { + compatible = "gw,gsc-fan"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2c>; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + eeprom1: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; @@ -219,13 +378,6 @@ pagesize = <16>; }; - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - rtc: ds1672@68 { compatible = "dallas,ds1672"; reg = <0x68>; @@ -419,6 +571,7 @@ }; &pwm4 { + #pwm-cells = <2>; pinctrl-names = "default", "state_dio"; pinctrl-0 = <&pinctrl_pwm4_backlight>; pinctrl-1 = <&pinctrl_pwm4_dio>; @@ -571,6 +724,7 @@ fsl,pins = < MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi index c38e86eedcc0..1516e2b0bcde 100644 --- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi @@ -47,6 +47,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/media/tda1997x.h> +#include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/sound/fsl-imx-audmux.h> / { @@ -63,6 +64,53 @@ bootargs = "console=ttymxc1,115200"; }; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = <BTN_1>; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = <BTN_2>; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = <BTN_3>; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = <BTN_4>; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = <BTN_5>; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -110,7 +158,7 @@ simple-audio-card,frame-master = <&sound_codec>; sound_cpu: simple-audio-card,cpu { - sound-dai = <&ssi2>; + sound-dai = <&ssi1>; }; sound_codec: simple-audio-card,codec { @@ -167,6 +215,97 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 GPIO_ACTIVE_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8a"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0b"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + eeprom1: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; @@ -191,13 +330,6 @@ pagesize = <16>; }; - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - rtc: ds1672@68 { compatible = "dallas,ds1672"; reg = <0x68>; @@ -464,6 +596,7 @@ fsl,pins = < MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi index bb3597132c62..0da6e6f7482b 100644 --- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> / { /* these are used by bootloader for disabling nodes */ @@ -20,6 +21,53 @@ bootargs = "console=ttymxc1,115200"; }; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = <BTN_1>; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = <BTN_2>; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = <BTN_3>; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = <BTN_4>; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = <BTN_5>; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -92,6 +140,103 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 GPIO_ACTIVE_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + eeprom1: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; @@ -116,13 +261,6 @@ pagesize = <16>; }; - gpio: pca9555@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - rtc: ds1672@68 { compatible = "dallas,ds1672"; reg = <0x68>; @@ -305,6 +443,7 @@ fsl,pins = < MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi index ee85031c3916..db30de5d6490 100644 --- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi @@ -46,6 +46,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> / { /* these are used by bootloader for disabling nodes */ @@ -61,6 +62,53 @@ stdout-path = &uart2; }; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = <BTN_1>; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = <BTN_2>; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = <BTN_3>; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = <BTN_4>; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = <BTN_5>; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -130,11 +178,101 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - gpio: pca9555@23 { + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 GPIO_ACTIVE_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8a"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0b"; + }; + + channel@26 { + gw,mode = <1>; + reg = <0x26>; + label = "vdd_an1"; + }; + }; + }; + + gsc_gpio: gpio@23 { compatible = "nxp,pca9555"; reg = <0x23>; gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; }; eeprom1: eeprom@50 { @@ -428,6 +566,7 @@ fsl,pins = < MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi index 69ca70d3baa8..d6b074597518 100644 --- a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi @@ -88,6 +88,53 @@ default-on; }; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = <BTN_1>; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = <BTN_2>; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = <BTN_3>; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = <BTN_4>; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = <BTN_5>; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -243,6 +290,115 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 GPIO_ACTIVE_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_an1"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + + channel@26 { + gw,mode = <1>; + reg = <0x26>; + label = "vdd_gps"; + }; + + channel@29 { + gw,mode = <1>; + reg = <0x29>; + label = "vdd_an2"; + }; + }; + }; + + gsc_gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + eeprom1: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; @@ -267,13 +423,6 @@ pagesize = <16>; }; - pca9555: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - ds1672: rtc@68 { compatible = "dallas,ds1672"; reg = <0x68>; @@ -471,6 +620,7 @@ }; &pwm4 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; @@ -608,6 +758,7 @@ fsl,pins = < MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi index aee9221f0f29..fbe6c32bd756 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi @@ -46,6 +46,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> / { chosen { @@ -71,6 +72,53 @@ default-brightness-level = <100>; }; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = <BTN_1>; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = <BTN_2>; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = <BTN_3>; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = <BTN_4>; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = <BTN_5>; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -183,11 +231,101 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pca9555: gpio@23 { + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 GPIO_ACTIVE_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_an1"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + }; + }; + + gsc_gpio: gpio@23 { compatible = "nxp,pca9555"; reg = <0x23>; gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; }; eeprom1: eeprom@50 { @@ -365,6 +503,7 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi index 76d6cf57f1c3..23c6e4047621 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi @@ -46,6 +46,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> / { /* these are used by bootloader for disabling nodes */ @@ -68,6 +69,53 @@ default-brightness-level = <7>; }; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = <BTN_1>; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = <BTN_2>; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = <BTN_3>; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = <BTN_4>; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = <BTN_5>; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -205,11 +253,101 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pca9555: gpio@23 { + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 GPIO_ACTIVE_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_an1"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + }; + }; + + gsc_gpio: gpio@23 { compatible = "nxp,pca9555"; reg = <0x23>; gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; }; eeprom1: eeprom@50 { @@ -401,6 +539,7 @@ }; &pwm4 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; @@ -503,6 +642,7 @@ fsl,pins = < MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw5907.dtsi b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi index 0bdebddffd51..b1ff7c859c4d 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5907.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> / { /* these are used by bootloader for disabling nodes */ @@ -19,6 +20,53 @@ stdout-path = &uart2; }; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = <BTN_1>; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = <BTN_2>; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = <BTN_3>; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = <BTN_4>; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = <BTN_5>; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -102,11 +150,101 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - gpio@23 { + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 GPIO_ACTIVE_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_an1"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + }; + }; + + gsc_gpio: gpio@23 { compatible = "nxp,pca9555"; reg = <0x23>; gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; }; eeprom@50 { @@ -133,7 +271,7 @@ pagesize = <16>; }; - rtc@68 { + ds1672@68 { compatible = "dallas,ds1672"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi index 0857de505192..11f84ee7b88f 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> / { /* these are used by bootloader for disabling nodes */ @@ -22,6 +23,53 @@ reg = <0x10000000 0x20000000>; }; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = <BTN_1>; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = <BTN_2>; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = <BTN_3>; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = <BTN_4>; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = <BTN_5>; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -111,11 +159,121 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - gpio@23 { + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 GPIO_ACTIVE_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <3>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vdd_vin"; + gw,voltage-divider-ohms = <22100 1000>; + gw,voltage-offset-microvolt = <800000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vdd_5p0"; + gw,voltage-divider-ohms = <22100 10000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_2p5"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_3p0"; + }; + + channel@8e { + gw,mode = <2>; + reg = <0x8e>; + label = "vdd_arm"; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_soc"; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_1p5"; + }; + + channel@98 { + gw,mode = <2>; + reg = <0x98>; + label = "vdd_1p8"; + }; + + channel@9a { + gw,mode = <2>; + reg = <0x9a>; + label = "vdd_1p0"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@9c { + gw,mode = <2>; + reg = <0x9c>; + label = "vdd_an1"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + }; + + gsc_gpio: gpio@23 { compatible = "nxp,pca9555"; reg = <0x23>; gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; }; eeprom@50 { diff --git a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi index 8c57fd2f9a0b..0a1ffff9eb75 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> / { /* these are used by bootloader for disabling nodes */ @@ -20,6 +21,53 @@ stdout-path = &uart2; }; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = <BTN_1>; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = <BTN_2>; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = <BTN_3>; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = <BTN_4>; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = <BTN_5>; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -106,11 +154,109 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - gpio@23 { + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 GPIO_ACTIVE_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + gw,mode = <0>; + reg = <0x00>; + label = "temp"; + }; + + channel@2 { + gw,mode = <1>; + reg = <0x02>; + label = "vdd_vin"; + }; + + channel@5 { + gw,mode = <1>; + reg = <0x05>; + label = "vdd_3p3"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@b { + gw,mode = <1>; + reg = <0x0b>; + label = "vdd_5p0"; + }; + + channel@e { + gw,mode = <1>; + reg = <0xe>; + label = "vdd_arm"; + }; + + channel@11 { + gw,mode = <1>; + reg = <0x11>; + label = "vdd_soc"; + }; + + channel@14 { + gw,mode = <1>; + reg = <0x14>; + label = "vdd_3p0"; + }; + + channel@17 { + gw,mode = <1>; + reg = <0x17>; + label = "vdd_1p5"; + }; + + channel@1d { + gw,mode = <1>; + reg = <0x1d>; + label = "vdd_1p8"; + }; + + channel@20 { + gw,mode = <1>; + reg = <0x20>; + label = "vdd_1p0"; + }; + + channel@23 { + gw,mode = <1>; + reg = <0x23>; + label = "vdd_2p5"; + }; + }; + + fan-controller@a { + compatible = "gw,gsc-fan"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0a>; + }; + }; + + gsc_gpio: gpio@23 { compatible = "nxp,pca9555"; reg = <0x23>; gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; }; eeprom@50 { diff --git a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi index 635c203bd64d..d62a8da49367 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> / { /* these are used by bootloader for disabling nodes */ @@ -19,6 +20,53 @@ stdout-path = &uart2; }; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user-pb { + label = "user_pb"; + gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = <BTN_1>; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key-erased"; + linux,code = <BTN_2>; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = <BTN_3>; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = <BTN_4>; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = <BTN_5>; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -87,11 +135,114 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - gpio@23 { + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 GPIO_ACTIVE_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <3>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vdd_vin"; + gw,voltage-divider-ohms = <22100 1000>; + gw,voltage-offset-microvolt = <800000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vdd_5p0"; + gw,voltage-divider-ohms = <22100 10000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_2p5"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_arm"; + }; + + channel@8e { + gw,mode = <2>; + reg = <0x8e>; + label = "vdd_soc"; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_1p5"; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_1p0"; + }; + + channel@98 { + gw,mode = <2>; + reg = <0x98>; + label = "vdd_3p0"; + }; + + channel@9a { + gw,mode = <2>; + reg = <0x9a>; + label = "vdd_an1"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + }; + + gsc_gpio: gpio@23 { compatible = "nxp,pca9555"; reg = <0x23>; gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; }; eeprom@50 { diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi index 756f3a9f1b4f..23c318d9636f 100644 --- a/arch/arm/boot/dts/imx6qdl-icore.dtsi +++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi @@ -245,6 +245,7 @@ }; &pwm3 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; @@ -397,7 +398,7 @@ pinctrl_usbotg: usbotggrp { fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 >; }; @@ -409,6 +410,7 @@ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index 2418cf8f2317..d526f01a2c52 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -497,6 +497,7 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; @@ -509,6 +510,7 @@ }; &pwm4 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index c3415aa348a2..185a1a31ca39 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -736,12 +736,14 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; &pwm2 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; status = "okay"; @@ -754,6 +756,7 @@ }; &pwm4 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi index ed53f07c6b7b..4bbe54e1ddb5 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi @@ -639,6 +639,7 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; @@ -651,6 +652,7 @@ }; &pwm4 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 8b0e432099b5..c63e1bc1ad3a 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -596,6 +596,7 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; @@ -608,6 +609,7 @@ }; &pwm4 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi index 9ebd438dce7d..019938562aa9 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi @@ -218,6 +218,7 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-prti6q.dtsi b/arch/arm/boot/dts/imx6qdl-prti6q.dtsi new file mode 100644 index 000000000000..19578f660b09 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-prti6q.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2014 Protonic Holland + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + chosen { + stdout-path = &uart4; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_h1_vbus: regulator-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "h1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&can1 { + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + temperature-sensor@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b008 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b008 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index cf628465cd0a..55f736dbee0b 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -800,6 +800,7 @@ }; &pwm3 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 8468216dae9b..95f9ddab5996 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -687,18 +687,21 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; &pwm3 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; }; &pwm4 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 28b35ccb3757..68b3e68cb8df 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -203,9 +203,21 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + phy-handle = <&phy>; fsl,magic-packet; status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@1 { + reg = <1>; + qca,clk-out-frequency = <125000000>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + }; + }; }; &hdmi { @@ -729,6 +741,7 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-savageboard.dtsi b/arch/arm/boot/dts/imx6qdl-savageboard.dtsi index a616e3c400d3..02e6d36e85fa 100644 --- a/arch/arm/boot/dts/imx6qdl-savageboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-savageboard.dtsi @@ -140,6 +140,7 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index c68cb90fd801..362e65ccaa78 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -738,14 +738,12 @@ &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; - #pwm-cells = <3>; status = "disabled"; }; &pwm2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; - #pwm-cells = <3>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 20350e803377..5af9ce977b12 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -719,6 +719,8 @@ mdio { #address-cells = <1>; #size-cells = <0>; + clock-frequency = <12500000>; + suppress-preamble; status = "okay"; switch: switch@0 { diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 32114cf6acee..43edbf1156c7 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -69,17 +69,6 @@ }; }; - tempmon: tempmon { - compatible = "fsl,imx6q-tempmon"; - interrupt-parent = <&gpc>; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; - #thermal-sensor-cells = <0>; - }; - ldb: ldb { #address-cells = <1>; #size-cells = <0>; @@ -256,7 +245,7 @@ interrupt-parent = <&intc>; }; - L2: l2-cache@a02000 { + L2: cache-controller@a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; @@ -510,7 +499,7 @@ }; pwm1: pwm@2080000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; @@ -521,7 +510,7 @@ }; pwm2: pwm@2084000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; @@ -532,7 +521,7 @@ }; pwm3: pwm@2088000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; @@ -543,7 +532,7 @@ }; pwm4: pwm@208c000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; @@ -795,6 +784,17 @@ anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; }; + + tempmon: tempmon { + compatible = "fsl,imx6q-tempmon"; + interrupt-parent = <&gpc>; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + #thermal-sensor-cells = <0>; + }; }; usbphy1: usbphy@20c9000 { @@ -871,8 +871,7 @@ reg = <0x020dc000 0x4000>; interrupt-controller; #interrupt-cells = <3>; - interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, - <0 90 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; clocks = <&clks IMX6QDL_CLK_IPG>; clock-names = "ipg"; @@ -1057,7 +1056,7 @@ <0 126 IRQ_TYPE_LEVEL_HIGH>; }; - usdhc1: usdhc@2190000 { + usdhc1: mmc@2190000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02190000 0x4000>; interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; @@ -1069,7 +1068,7 @@ status = "disabled"; }; - usdhc2: usdhc@2194000 { + usdhc2: mmc@2194000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02194000 0x4000>; interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; @@ -1081,7 +1080,7 @@ status = "disabled"; }; - usdhc3: usdhc@2198000 { + usdhc3: mmc@2198000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02198000 0x4000>; interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; @@ -1093,7 +1092,7 @@ status = "disabled"; }; - usdhc4: usdhc@219c000 { + usdhc4: mmc@219c000 { compatible = "fsl,imx6q-usdhc"; reg = <0x0219c000 0x4000>; interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; @@ -1162,7 +1161,7 @@ status = "disabled"; }; - ocotp: ocotp-ctrl@21bc000 { + ocotp: efuse@21bc000 { compatible = "fsl,imx6q-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6QDL_CLK_IIM>; diff --git a/arch/arm/boot/dts/imx6qp-sabreauto.dts b/arch/arm/boot/dts/imx6qp-sabreauto.dts index d4caeeb0af70..639d9dd35377 100644 --- a/arch/arm/boot/dts/imx6qp-sabreauto.dts +++ b/arch/arm/boot/dts/imx6qp-sabreauto.dts @@ -50,6 +50,10 @@ status = "disabled"; }; +&sata { + status = "okay"; +}; + &vgen3_reg { regulator-always-on; }; diff --git a/arch/arm/boot/dts/imx6qp-sabresd.dts b/arch/arm/boot/dts/imx6qp-sabresd.dts index f1b9cb104fdd..480e73183f6b 100644 --- a/arch/arm/boot/dts/imx6qp-sabresd.dts +++ b/arch/arm/boot/dts/imx6qp-sabresd.dts @@ -53,3 +53,7 @@ &pcie { status = "disabled"; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index bc86cfaaa9c2..b1b069e723d2 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -575,6 +575,7 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 911d8cf77f2c..1c7180f28539 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -93,16 +93,6 @@ }; }; - tempmon: tempmon { - compatible = "fsl,imx6q-tempmon"; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gpc>; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; - }; - pmu { compatible = "arm,cortex-a9-pmu"; interrupt-parent = <&gpc>; @@ -136,7 +126,7 @@ interrupt-parent = <&intc>; }; - L2: l2-cache@a02000 { + L2: cache-controller@a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; @@ -344,7 +334,7 @@ }; pwm1: pwm@2080000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; @@ -354,7 +344,7 @@ }; pwm2: pwm@2084000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; @@ -364,7 +354,7 @@ }; pwm3: pwm@2088000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; @@ -374,7 +364,7 @@ }; pwm4: pwm@208c000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; @@ -628,6 +618,16 @@ anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; }; + + tempmon: tempmon { + compatible = "fsl,imx6q-tempmon"; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gpc>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; + }; }; usbphy1: usbphy@20c9000 { @@ -854,7 +854,7 @@ status = "disabled"; }; - usdhc1: usdhc@2190000 { + usdhc1: mmc@2190000 { compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; reg = <0x02190000 0x4000>; interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; @@ -866,7 +866,7 @@ status = "disabled"; }; - usdhc2: usdhc@2194000 { + usdhc2: mmc@2194000 { compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; reg = <0x02194000 0x4000>; interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; @@ -878,7 +878,7 @@ status = "disabled"; }; - usdhc3: usdhc@2198000 { + usdhc3: mmc@2198000 { compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; reg = <0x02198000 0x4000>; interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; @@ -890,7 +890,7 @@ status = "disabled"; }; - usdhc4: usdhc@219c000 { + usdhc4: mmc@219c000 { compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; reg = <0x0219c000 0x4000>; interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; @@ -952,7 +952,7 @@ status = "disabled"; }; - ocotp: ocotp-ctrl@21bc000 { + ocotp: efuse@21bc000 { compatible = "fsl,imx6sl-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6SL_CLK_OCOTP>; diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index 5ace9e6acf85..c755cbdb7cde 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -260,6 +260,7 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index edd3abb9a9f1..fb5d3bc50c6b 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -105,16 +105,6 @@ clock-output-names = "ipp_di1"; }; - tempmon: temperature-sensor { - compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon"; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gpc>; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; - }; - soc { #address-cells = <1>; #size-cells = <1>; @@ -136,7 +126,7 @@ interrupt-parent = <&intc>; }; - L2: l2-cache@a02000 { + L2: cache-controller@a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; @@ -271,7 +261,7 @@ status = "disabled"; }; - ssi1: ssi-controller@2028000 { + ssi1: ssi@2028000 { compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; reg = <0x02028000 0x4000>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; @@ -284,7 +274,7 @@ status = "disabled"; }; - ssi2: ssi-controller@202c000 { + ssi2: ssi@202c000 { compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; reg = <0x0202c000 0x4000>; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; @@ -297,7 +287,7 @@ status = "disabled"; }; - ssi3: ssi-controller@2030000 { + ssi3: ssi@2030000 { compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; reg = <0x02030000 0x4000>; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; @@ -331,7 +321,7 @@ clocks = <&clks IMX6SLL_CLK_PWM1>, <&clks IMX6SLL_CLK_PWM1>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; pwm2: pwm@2084000 { @@ -341,7 +331,7 @@ clocks = <&clks IMX6SLL_CLK_PWM2>, <&clks IMX6SLL_CLK_PWM2>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; pwm3: pwm@2088000 { @@ -351,7 +341,7 @@ clocks = <&clks IMX6SLL_CLK_PWM3>, <&clks IMX6SLL_CLK_PWM3>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; pwm4: pwm@208c000 { @@ -361,7 +351,7 @@ clocks = <&clks IMX6SLL_CLK_PWM4>, <&clks IMX6SLL_CLK_PWM4>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; gpt1: timer@2098000 { @@ -531,6 +521,16 @@ anatop-max-voltage = <3400000>; anatop-enable-bit = <0>; }; + + tempmon: temperature-sensor { + compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon"; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gpc>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; + }; }; usbphy1: usb-phy@20c9000 { @@ -786,7 +786,7 @@ clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>; }; - ocotp: ocotp-ctrl@21bc000 { + ocotp: efuse@21bc000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,imx6sll-ocotp", "syscon"; diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index d84ea6999377..66af78e83b70 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -229,6 +229,7 @@ }; &pwm4 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts index 825924448ab4..83ee97252ff1 100644 --- a/arch/arm/boot/dts/imx6sx-sabreauto.dts +++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts @@ -66,12 +66,68 @@ enable-active-high; vin-supply = <®_can_en>; }; + + reg_cs42888: cs42888_supply { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound-cs42888 { + compatible = "fsl,imx6-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + audio-cpu = <&esai>; + audio-asrc = <&asrc>; + audio-codec = <&cs42888>; + audio-routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-in; + }; }; &anaclk2 { clock-frequency = <24576000>; }; +&clks { + assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>, + <&clks IMX6SX_PLL4_BYPASS>, + <&clks IMX6SX_CLK_PLL4_POST_DIV>; + assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>, + <&clks IMX6SX_PLL4_BYPASS_SRC>; + assigned-clock-rates = <0>, <0>, <24576000>; +}; + +&esai { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai>; + assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>, + <&clks IMX6SX_CLK_ESAI_EXTAL>; + assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; @@ -99,7 +155,7 @@ &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <ðphy0>; fsl,magic-packet; status = "okay"; @@ -193,6 +249,21 @@ >; }; + pinctrl_esai: esaigrp { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 @@ -227,6 +298,12 @@ >; }; + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 @@ -313,6 +390,17 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&anaclk2 0>; + clock-names = "mclk"; + VA-supply = <®_cs42888>; + VD-supply = <®_cs42888>; + VLS-supply = <®_cs42888>; + VLC-supply = <®_cs42888>; + }; + touchscreen@4 { compatible = "eeti,egalax_ts"; reg = <0x04>; @@ -454,6 +542,14 @@ }; }; +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; diff --git a/arch/arm/boot/dts/imx6sx-sdb-mqs.dts b/arch/arm/boot/dts/imx6sx-sdb-mqs.dts new file mode 100644 index 000000000000..a4ab2d3e960c --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sdb-mqs.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2014 Freescale Semiconductor, Inc. + +#include "imx6sx-sdb.dts" +/ { + + sound { + status = "disabled"; + }; + + sound-mqs { + compatible = "fsl,imx6sx-sdb-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + audio-cpu = <&sai1>; + audio-asrc = <&asrc>; + audio-codec = <&mqs>; + }; +}; + +&usdhc2 { + /* pin conflict with mqs*/ + status = "disabled"; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + clocks = <&clks IMX6SX_CLK_SAI1>; + clock-names = "mclk"; + status = "okay"; +}; + +&sai1 { + pinctrl-0 = <>; + status = "okay"; +}; + +&ssi2 { + status = "disabled"; +}; + +&sdma { + gpr = <&gpr>; + /* SDMA event remap for SAI1 */ + fsl,sdma-event-remap = <0 15 1>, <0 16 1>; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi index 3e5fb72f21fc..b8c23eba9dc7 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi @@ -179,6 +179,15 @@ }; }; }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif", + "fsl,imx6sx-sdb-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + }; + }; &audmux { @@ -213,7 +222,7 @@ &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <ðphy2>; status = "okay"; }; @@ -281,6 +290,7 @@ }; &pwm3 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; @@ -296,6 +306,14 @@ status = "disabled"; }; +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + &ssi2 { status = "okay"; }; @@ -505,6 +523,13 @@ >; }; + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0 + MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0 @@ -562,6 +587,12 @@ >; }; + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts index 6b728b03f1f2..d25e27d0315f 100644 --- a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts +++ b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts @@ -505,18 +505,21 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; &pwm2 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; status = "okay"; }; &pwm6 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm6>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 94e3df47d1ad..b480dfa9e251 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -134,14 +134,10 @@ clock-output-names = "anaclk2"; }; - tempmon: tempmon { - compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; - interrupt-parent = <&gpc>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; + mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + status = "disabled"; }; pmu { @@ -183,7 +179,7 @@ interrupt-parent = <&intc>; }; - L2: l2-cache@a02000 { + L2: cache-controller@a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; @@ -335,6 +331,7 @@ }; esai: esai@2024000 { + compatible = "fsl,imx6sx-esai", "fsl,imx35-esai"; reg = <0x02024000 0x4000>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_ESAI_IPG>, @@ -344,6 +341,9 @@ <&clks IMX6SX_CLK_SPBA>; clock-names = "core", "mem", "extal", "fsys", "spba"; + dmas = <&sdma 23 21 0>, + <&sdma 24 21 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -390,18 +390,28 @@ }; asrc: asrc@2034000 { + compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc"; reg = <0x02034000 0x4000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SX_CLK_ASRC_MEM>, - <&clks IMX6SX_CLK_ASRC_IPG>, - <&clks IMX6SX_CLK_SPDIF>, - <&clks IMX6SX_CLK_SPBA>; - clock-names = "mem", "ipg", "asrck", "spba"; - dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, - <&sdma 19 20 1>, <&sdma 20 20 1>, - <&sdma 21 20 1>, <&sdma 22 20 1>; + clocks = <&clks IMX6SX_CLK_ASRC_IPG>, + <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>, + <&clks IMX6SX_CLK_SPBA>; + clock-names = "mem", "ipg", "asrck_0", + "asrck_1", "asrck_2", "asrck_3", "asrck_4", + "asrck_5", "asrck_6", "asrck_7", "asrck_8", + "asrck_9", "asrck_a", "asrck_b", "asrck_c", + "asrck_d", "asrck_e", "asrck_f", "spba"; + dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, + <&sdma 19 23 1>, <&sdma 20 23 1>, + <&sdma 21 23 1>, <&sdma 22 23 1>; dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc"; + fsl,asrc-rate = <48000>; + fsl,asrc-width = <16>; status = "okay"; }; }; @@ -413,7 +423,7 @@ clocks = <&clks IMX6SX_CLK_PWM1>, <&clks IMX6SX_CLK_PWM1>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; pwm2: pwm@2084000 { @@ -423,7 +433,7 @@ clocks = <&clks IMX6SX_CLK_PWM2>, <&clks IMX6SX_CLK_PWM2>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; pwm3: pwm@2088000 { @@ -433,7 +443,7 @@ clocks = <&clks IMX6SX_CLK_PWM3>, <&clks IMX6SX_CLK_PWM3>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; pwm4: pwm@208c000 { @@ -443,7 +453,7 @@ clocks = <&clks IMX6SX_CLK_PWM4>, <&clks IMX6SX_CLK_PWM4>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; flexcan1: can@2090000 { @@ -696,6 +706,16 @@ anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; }; + + tempmon: tempmon { + compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; + interrupt-parent = <&gpc>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; + }; }; usbphy1: usbphy@20c9000 { @@ -943,7 +963,7 @@ status = "disabled"; }; - usdhc1: usdhc@2190000 { + usdhc1: mmc@2190000 { compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; reg = <0x02190000 0x4000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; @@ -955,7 +975,7 @@ status = "disabled"; }; - usdhc2: usdhc@2194000 { + usdhc2: mmc@2194000 { compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; reg = <0x02194000 0x4000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; @@ -967,7 +987,7 @@ status = "disabled"; }; - usdhc3: usdhc@2198000 { + usdhc3: mmc@2198000 { compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; reg = <0x02198000 0x4000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; @@ -979,7 +999,7 @@ status = "disabled"; }; - usdhc4: usdhc@219c000 { + usdhc4: mmc@219c000 { compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; reg = <0x0219c000 0x4000>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; @@ -1055,7 +1075,7 @@ status = "disabled"; }; - ocotp: ocotp-ctrl@21bc000 { + ocotp: efuse@21bc000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,imx6sx-ocotp", "syscon"; @@ -1337,7 +1357,7 @@ clocks = <&clks IMX6SX_CLK_PWM5>, <&clks IMX6SX_CLK_PWM5>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; pwm6: pwm@22a8000 { @@ -1347,7 +1367,7 @@ clocks = <&clks IMX6SX_CLK_PWM6>, <&clks IMX6SX_CLK_PWM6>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; pwm7: pwm@22ac000 { @@ -1357,7 +1377,7 @@ clocks = <&clks IMX6SX_CLK_PWM7>, <&clks IMX6SX_CLK_PWM7>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; pwm8: pwm@22b0000 { @@ -1367,7 +1387,7 @@ clocks = <&clks IMX6SX_CLK_PWM8>, <&clks IMX6SX_CLK_PWM8>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; }; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi index 265bf4108cb6..64c2d1e9f7fc 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi @@ -228,6 +228,7 @@ }; &pwm1 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts index 5d3805b07032..a0bbec57ddc7 100644 --- a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts +++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts @@ -168,6 +168,7 @@ }; &pwm5 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm5>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6ul-geam.dts b/arch/arm/boot/dts/imx6ul-geam.dts index 9f63706383a7..a0097da03f38 100644 --- a/arch/arm/boot/dts/imx6ul-geam.dts +++ b/arch/arm/boot/dts/imx6ul-geam.dts @@ -195,6 +195,7 @@ }; &pwm8 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm8>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi b/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi index 18966350bfd8..935a77d717a6 100644 --- a/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi +++ b/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi @@ -155,6 +155,7 @@ }; &pwm3 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi index cc9adce638f5..14fc4828ba4e 100644 --- a/arch/arm/boot/dts/imx6ul-isiot.dtsi +++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi @@ -187,6 +187,7 @@ }; &pwm8 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm8>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts b/arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts index 5bad29683cc3..5bfad4655b22 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts +++ b/arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts @@ -41,6 +41,7 @@ }; &pwm7 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm7>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi index f05e91841202..a35be2a369b3 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi +++ b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi @@ -153,6 +153,7 @@ }; &pwm8 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm8>; status = "okay"; @@ -232,13 +233,6 @@ status = "okay"; }; -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - &iomuxc { pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>; @@ -409,10 +403,4 @@ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 >; }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0 - >; - }; }; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi index a17af4d9bfdf..61ba21a605a8 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi +++ b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi @@ -57,6 +57,13 @@ status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reset_out>; @@ -106,4 +113,10 @@ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x18b0 + >; + }; }; diff --git a/arch/arm/boot/dts/imx6ul-pico.dtsi b/arch/arm/boot/dts/imx6ul-pico.dtsi index df1da98ab10f..357ffb2f5ad6 100644 --- a/arch/arm/boot/dts/imx6ul-pico.dtsi +++ b/arch/arm/boot/dts/imx6ul-pico.dtsi @@ -175,6 +175,7 @@ }; &pwm3 { + #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi index bb6dbfd5546b..938a32ced88d 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi @@ -549,7 +549,6 @@ &pwm5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm5>; - #pwm-cells = <3>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 5379a03391bd..2b088f210331 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -131,16 +131,6 @@ clock-output-names = "ipp_di1"; }; - tempmon: tempmon { - compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; - interrupt-parent = <&gpc>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; - }; - pmu { compatible = "arm,cortex-a7-pmu"; interrupt-parent = <&gpc>; @@ -351,6 +341,31 @@ dma-names = "rx", "tx"; status = "disabled"; }; + + asrc: asrc@2034000 { + compatible = "fsl,imx6ul-asrc", "fsl,imx53-asrc"; + reg = <0x2034000 0x4000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ASRC_IPG>, + <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>, + <&clks IMX6UL_CLK_SPBA>; + clock-names = "mem", "ipg", "asrck_0", + "asrck_1", "asrck_2", "asrck_3", "asrck_4", + "asrck_5", "asrck_6", "asrck_7", "asrck_8", + "asrck_9", "asrck_a", "asrck_b", "asrck_c", + "asrck_d", "asrck_e", "asrck_f", "spba"; + dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, + <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <48000>; + fsl,asrc-width = <16>; + status = "okay"; + }; }; tsc: tsc@2040000 { @@ -371,7 +386,7 @@ clocks = <&clks IMX6UL_CLK_PWM1>, <&clks IMX6UL_CLK_PWM1>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -382,7 +397,7 @@ clocks = <&clks IMX6UL_CLK_PWM2>, <&clks IMX6UL_CLK_PWM2>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -393,7 +408,7 @@ clocks = <&clks IMX6UL_CLK_PWM3>, <&clks IMX6UL_CLK_PWM3>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -404,7 +419,7 @@ clocks = <&clks IMX6UL_CLK_PWM4>, <&clks IMX6UL_CLK_PWM4>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -612,6 +627,16 @@ anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; }; + + tempmon: tempmon { + compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; + interrupt-parent = <&gpc>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; + }; }; usbphy1: usbphy@20c9000 { @@ -734,7 +759,7 @@ clocks = <&clks IMX6UL_CLK_PWM5>, <&clks IMX6UL_CLK_PWM5>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -745,7 +770,7 @@ clocks = <&clks IMX6UL_CLK_PWM6>, <&clks IMX6UL_CLK_PWM6>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -756,7 +781,7 @@ clocks = <&clks IMX6UL_CLK_PWM7>, <&clks IMX6UL_CLK_PWM7>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -767,7 +792,7 @@ clocks = <&clks IMX6UL_CLK_PWM8>, <&clks IMX6UL_CLK_PWM8>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; }; @@ -861,7 +886,7 @@ status = "disabled"; }; - usdhc1: usdhc@2190000 { + usdhc1: mmc@2190000 { compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; reg = <0x02190000 0x4000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; @@ -875,7 +900,7 @@ status = "disabled"; }; - usdhc2: usdhc@2194000 { + usdhc2: mmc@2194000 { compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; reg = <0x02194000 0x4000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; @@ -948,7 +973,7 @@ status = "disabled"; }; - ocotp: ocotp-ctrl@21bc000 { + ocotp: efuse@21bc000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,imx6ul-ocotp", "syscon"; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 9145c536d71a..6cf95939121d 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -145,25 +145,21 @@ &pwm4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; - #pwm-cells = <3>; }; &pwm5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm5>; - #pwm-cells = <3>; }; &pwm6 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm6>; - #pwm-cells = <3>; }; &pwm7 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm7>; - #pwm-cells = <3>; }; &sdma { diff --git a/arch/arm/boot/dts/imx6ull-myir-mys-6ulx-eval.dts b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx-eval.dts new file mode 100644 index 000000000000..ecbb2cc5b9ab --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx-eval.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi <parthiban@linumiz.com> + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-myir-mys-6ulx.dtsi" + +/ { + model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND"; + compatible = "myir,imx6ull-mys-6ulx-eval", "fsl,imx6ull"; +}; + +&gpmi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi new file mode 100644 index 000000000000..d03694feaf5c --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Linumiz + * Author: Parthiban Nallathambi <parthiban@linumiz.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "MYiR MYS-6ULX Single Board Computer"; + compatible = "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + reg_vdd_5v: regulator-vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_vdd_3v3: regulator-vdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_vdd_5v>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-supply = <®_vdd_3v3>; + status = "okay"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_vdd_3v3>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + non-removable; + keep-power-in-suspend; + vmmc-supply = <®_vdd_3v3>; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index f6bb35d3ce51..1cfaf410aa43 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -147,16 +147,6 @@ }; }; - tempmon: tempmon { - compatible = "fsl,imx7d-tempmon"; - interrupt-parent = <&gpc>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&fuse_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; - }; - timer { compatible = "arm,armv7-timer"; interrupt-parent = <&intc>; @@ -536,7 +526,7 @@ }; }; - ocotp: ocotp-ctrl@30350000 { + ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,imx7d-ocotp", "syscon"; @@ -586,6 +576,16 @@ anatop-max-voltage = <1300000>; anatop-enable-bit = <0>; }; + + tempmon: tempmon { + compatible = "fsl,imx7d-tempmon"; + interrupt-parent = <&gpc>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&fuse_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; + }; }; snvs: snvs@30370000 { @@ -1126,7 +1126,7 @@ reg = <0x30b30200 0x200>; }; - usdhc1: usdhc@30b40000 { + usdhc1: mmc@30b40000 { compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; reg = <0x30b40000 0x10000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; @@ -1138,7 +1138,7 @@ status = "disabled"; }; - usdhc2: usdhc@30b50000 { + usdhc2: mmc@30b50000 { compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; reg = <0x30b50000 0x10000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; @@ -1150,7 +1150,7 @@ status = "disabled"; }; - usdhc3: usdhc@30b60000 { + usdhc3: mmc@30b60000 { compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; reg = <0x30b60000 0x10000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index f7c4878534c8..367439639da9 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -452,7 +452,7 @@ reg = <0x410a3000 0x1000>; }; - ocotp: ocotp-ctrl@410a6000 { + ocotp: efuse@410a6000 { compatible = "fsl,imx7ulp-ocotp", "syscon"; reg = <0x410a6000 0x4000>; clocks = <&scg1 IMX7ULP_CLK_DUMMY>; diff --git a/arch/arm/boot/dts/infinity-msc313-breadbee_crust.dts b/arch/arm/boot/dts/infinity-msc313-breadbee_crust.dts new file mode 100644 index 000000000000..f24c5580d3e4 --- /dev/null +++ b/arch/arm/boot/dts/infinity-msc313-breadbee_crust.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 thingy.jp. + * Author: Daniel Palmer <daniel@thingy.jp> + */ + +/dts-v1/; +#include "infinity-msc313.dtsi" + +/ { + model = "BreadBee Crust"; + compatible = "thingyjp,breadbee-crust", "mstar,infinity"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/infinity-msc313.dtsi b/arch/arm/boot/dts/infinity-msc313.dtsi new file mode 100644 index 000000000000..42f2b5552c77 --- /dev/null +++ b/arch/arm/boot/dts/infinity-msc313.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer <daniel@thingy.jp> + */ + +#include "infinity.dtsi" + +/ { + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x4000000>; + }; +}; diff --git a/arch/arm/boot/dts/infinity.dtsi b/arch/arm/boot/dts/infinity.dtsi new file mode 100644 index 000000000000..cd911adef014 --- /dev/null +++ b/arch/arm/boot/dts/infinity.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer <daniel@thingy.jp> + */ + +#include "mstar-v7.dtsi" + +&imi { + reg = <0xa0000000 0x16000>; +}; diff --git a/arch/arm/boot/dts/infinity3-msc313e-breadbee.dts b/arch/arm/boot/dts/infinity3-msc313e-breadbee.dts new file mode 100644 index 000000000000..1f93401c8530 --- /dev/null +++ b/arch/arm/boot/dts/infinity3-msc313e-breadbee.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 thingy.jp. + * Author: Daniel Palmer <daniel@thingy.jp> + */ + +/dts-v1/; +#include "infinity3-msc313e.dtsi" + +/ { + model = "BreadBee"; + compatible = "thingyjp,breadbee", "mstar,infinity3"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/infinity3-msc313e.dtsi b/arch/arm/boot/dts/infinity3-msc313e.dtsi new file mode 100644 index 000000000000..4e7239afd823 --- /dev/null +++ b/arch/arm/boot/dts/infinity3-msc313e.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer <daniel@thingy.jp> + */ + +#include "infinity3.dtsi" + +/ { + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x4000000>; + }; +}; diff --git a/arch/arm/boot/dts/infinity3.dtsi b/arch/arm/boot/dts/infinity3.dtsi new file mode 100644 index 000000000000..9b918c802654 --- /dev/null +++ b/arch/arm/boot/dts/infinity3.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer <daniel@thingy.jp> + */ + +#include "infinity.dtsi" + +&imi { + reg = <0xa0000000 0x20000>; +}; diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts index db640bab8c1d..8b3d64c913d8 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts @@ -402,7 +402,7 @@ &gbe0 { phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; + phy-mode = "rgmii-rxid"; status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-b3.dts b/arch/arm/boot/dts/kirkwood-b3.dts index 17f48f88a983..a7636fe28501 100644 --- a/arch/arm/boot/dts/kirkwood-b3.dts +++ b/arch/arm/boot/dts/kirkwood-b3.dts @@ -9,7 +9,7 @@ * L2 cache. If your B3 silently fails to boot, u-boot is probably too * old. Either upgrade, or consider the following email: * - * http://lists.debian.org/debian-arm/2012/08/msg00128.html + * https://lists.debian.org/debian-arm/2012/08/msg00128.html */ /dts-v1/; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 760a68c163c8..069af9a19bb6 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -59,6 +59,7 @@ ethernet0 = &enet0; ethernet1 = &enet1; ethernet2 = &enet2; + rtc1 = &ftm_alarm0; serial0 = &lpuart0; serial1 = &lpuart1; serial2 = &lpuart2; @@ -772,7 +773,7 @@ fsl,tmr-prsc = <2>; fsl,tmr-add = <0xaaaaaaab>; fsl,tmr-fiper1 = <999999995>; - fsl,tmr-fiper2 = <99990>; + fsl,tmr-fiper2 = <999999995>; fsl,max-adj = <499999999>; fsl,extts-fifo; }; @@ -1002,5 +1003,19 @@ big-endian; }; + rcpm: power-controller@1ee2140 { + compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1ee2140 0x0 0x8>; + #fsl,rcpm-wakeup-cells = <2>; + }; + + ftm_alarm0: timer0@29d0000 { + compatible = "fsl,ls1021a-ftm-alarm"; + reg = <0x0 0x29d0000 0x0 0x10000>; + reg-names = "ftm"; + fsl,rcpm-wakeup = <&rcpm 0x20000 0x0>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + big-endian; + }; }; }; diff --git a/arch/arm/boot/dts/mercury5-ssc8336n-midrived08.dts b/arch/arm/boot/dts/mercury5-ssc8336n-midrived08.dts new file mode 100644 index 000000000000..f24bd8cb8e60 --- /dev/null +++ b/arch/arm/boot/dts/mercury5-ssc8336n-midrived08.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer <daniel@thingy.jp> + */ + +/dts-v1/; +#include "mercury5-ssc8336n.dtsi" + +/ { + model = "70mai Midrive D08"; + compatible = "70mai,midrived08", "mstar,mercury5"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mercury5-ssc8336n.dtsi b/arch/arm/boot/dts/mercury5-ssc8336n.dtsi new file mode 100644 index 000000000000..7d4a4630c25c --- /dev/null +++ b/arch/arm/boot/dts/mercury5-ssc8336n.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer <daniel@thingy.jp> + */ + +#include "mercury5.dtsi" + +/ { + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x4000000>; + }; +}; diff --git a/arch/arm/boot/dts/mercury5.dtsi b/arch/arm/boot/dts/mercury5.dtsi new file mode 100644 index 000000000000..a7d0dd9d6132 --- /dev/null +++ b/arch/arm/boot/dts/mercury5.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer <daniel@thingy.jp> + */ + +#include "mstar-v7.dtsi" + +&imi { + reg = <0xa0000000 0x20000>; +}; diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index ae89deaa8c9c..eadb0832bcfc 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -11,7 +11,7 @@ #size-cells = <1>; interrupt-parent = <&gic>; - L2: l2-cache-controller@c4200000 { + L2: cache-controller@c4200000 { compatible = "arm,pl310-cache"; reg = <0xc4200000 0x1000>; cache-unified; @@ -140,6 +140,13 @@ status = "disabled"; }; + sdhc: mmc@8e00 { + compatible = "amlogic,meson-mx-sdhc"; + reg = <0x8e00 0x42>; + interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + gpio_intc: interrupt-controller@9880 { compatible = "amlogic,meson-gpio-intc"; reg = <0x9880 0x10>; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index eedb92526968..277c0bb10453 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/meson8-ddr-clkc.h> #include <dt-bindings/clock/meson8b-clkc.h> #include <dt-bindings/gpio/meson8-gpio.h> +#include <dt-bindings/power/meson8-power.h> #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> #include <dt-bindings/reset/amlogic,meson8b-reset.h> #include "meson.dtsi" @@ -385,6 +386,15 @@ }; }; + sdxc_b_pins: sdxc-b { + mux { + groups = "sdxc_d0_b", "sdxc_d13_b", + "sdxc_clk_b", "sdxc_cmd_b"; + function = "sdxc_b"; + bias-pull-up; + }; + }; + spi_nor_pins: nor { mux { groups = "nor_d", "nor_q", "nor_c", "nor_cs"; @@ -454,6 +464,8 @@ ðmac { clocks = <&clkc CLKID_ETH>; clock-names = "stmmaceth"; + + power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>; }; &gpio_intc { @@ -469,6 +481,16 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + pwrc: power-controller { + compatible = "amlogic,meson8-pwrc"; + #power-domain-cells = <1>; + amlogic,ao-sysctrl = <&pmu>; + clocks = <&clkc CLKID_VPU>; + clock-names = "vpu"; + assigned-clocks = <&clkc CLKID_VPU>; + assigned-clock-rates = <364285714>; + }; }; &hwrng { @@ -547,6 +569,16 @@ nvmem-cell-names = "temperature_calib"; }; +&sdhc { + compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; + clocks = <&xtal>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_SDHC>; + clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; +}; + &sdio { compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 163a200d5a7b..ed06102a4014 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -27,6 +27,11 @@ reg = <0x40000000 0x40000000>; }; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + gpio-keys { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -299,6 +304,26 @@ vref-supply = <&vcc_1v8>; }; +&sdhc { + status = "okay"; + + pinctrl-0 = <&sdxc_c_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + max-frequency = <50000000>; + + cap-mmc-highspeed; + disable-wp; + non-removable; + no-sdio; + + mmc-pwrseq = <&emmc_pwrseq>; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_3v3>; +}; + &sdio { status = "okay"; diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index cb21ac9f517c..0c26467de4d0 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -15,6 +15,7 @@ aliases { serial0 = &uart_AO; mmc0 = &sd_card_slot; + mmc1 = &sdhc; }; chosen { @@ -26,6 +27,11 @@ reg = <0x40000000 0x40000000>; }; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + leds { compatible = "gpio-leds"; blue { @@ -310,6 +316,26 @@ vref-supply = <&vcc_1v8>; }; +&sdhc { + status = "okay"; + + pinctrl-0 = <&sdxc_c_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + max-frequency = <100000000>; + + disable-wp; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + + mmc-pwrseq = <&emmc_pwrseq>; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; +}; + &sdio { status = "okay"; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index ba36168b9c1b..2401cdf5f751 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/clock/meson8-ddr-clkc.h> #include <dt-bindings/clock/meson8b-clkc.h> #include <dt-bindings/gpio/meson8b-gpio.h> +#include <dt-bindings/power/meson8-power.h> #include <dt-bindings/reset/amlogic,meson8b-reset.h> #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> #include "meson.dtsi" @@ -362,6 +363,16 @@ }; }; + sdxc_c_pins: sdxc-c { + mux { + groups = "sdxc_d0_c", "sdxc_d13_c", + "sdxc_d47_c", "sdxc_clk_c", + "sdxc_cmd_c"; + function = "sdxc_c"; + bias-pull-up; + }; + }; + pwm_c1_pins: pwm-c1 { mux { groups = "pwm_c1"; @@ -433,6 +444,8 @@ resets = <&reset RESET_ETHERNET>; reset-names = "stmmaceth"; + + power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>; }; &gpio_intc { @@ -449,6 +462,30 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + pwrc: power-controller { + compatible = "amlogic,meson8b-pwrc"; + #power-domain-cells = <1>; + amlogic,ao-sysctrl = <&pmu>; + resets = <&reset RESET_DBLK>, + <&reset RESET_PIC_DC>, + <&reset RESET_HDMI_APB>, + <&reset RESET_HDMI_SYSTEM_RESET>, + <&reset RESET_VENCI>, + <&reset RESET_VENCP>, + <&reset RESET_VDAC_4>, + <&reset RESET_VENCL>, + <&reset RESET_VIU>, + <&reset RESET_VENC>, + <&reset RESET_RDMA>; + reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", + "venci", "vencp", "vdac", "vencl", "viu", + "venc", "rdma"; + clocks = <&clkc CLKID_VPU>; + clock-names = "vpu"; + assigned-clocks = <&clkc CLKID_VPU>; + assigned-clock-rates = <182142857>; + }; }; &hwrng { @@ -527,6 +564,16 @@ nvmem-cell-names = "temperature_calib"; }; +&sdhc { + compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; + clocks = <&xtal>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_SDHC>; + clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; +}; + &sdio { compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio"; clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi index 2397ba06d608..6725dd9fd825 100644 --- a/arch/arm/boot/dts/meson8m2.dtsi +++ b/arch/arm/boot/dts/meson8m2.dtsi @@ -61,10 +61,33 @@ }; }; +&pwrc { + compatible = "amlogic,meson8m2-pwrc"; + resets = <&reset RESET_DBLK>, + <&reset RESET_PIC_DC>, + <&reset RESET_HDMI_APB>, + <&reset RESET_HDMI_SYSTEM_RESET>, + <&reset RESET_VENCI>, + <&reset RESET_VENCP>, + <&reset RESET_VDAC_4>, + <&reset RESET_VENCL>, + <&reset RESET_VIU>, + <&reset RESET_VENC>, + <&reset RESET_RDMA>; + reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", "venci", + "vencp", "vdac", "vencl", "viu", "venc", "rdma"; + assigned-clocks = <&clkc CLKID_VPU>; + assigned-clock-rates = <364000000>; +}; + &saradc { compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc"; }; +&sdhc { + compatible = "amlogic,meson8m2-sdhc", "amlogic,meson-mx-sdhc"; +}; + &usb0_phy { compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; }; diff --git a/arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts b/arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts index 6cfa0d4a1884..f1a41152e9dd 100644 --- a/arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts +++ b/arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts @@ -57,30 +57,12 @@ linux,code = <SW_TABLET_MODE>; wakeup-source; }; - - microphone_insert { - label = "Microphone Plug"; - gpios = <&gpio 96 GPIO_ACTIVE_HIGH>; - linux,input-type = <EV_SW>; - linux,code = <SW_MICROPHONE_INSERT>; - debounce-interval = <100>; - wakeup-source; - }; - - headphone_insert { - label = "Headphone Plug"; - gpios = <&gpio 97 GPIO_ACTIVE_HIGH>; - linux,input-type = <EV_SW>; - linux,code = <SW_HEADPHONE_INSERT>; - debounce-interval = <100>; - wakeup-source; - }; }; - camera_i2c { + i2c { compatible = "i2c-gpio"; - gpios = <&gpio 109 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>, - <&gpio 108 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 109 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio 108 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; i2c-gpio,timeout-ms = <1000>; @@ -123,6 +105,18 @@ reset-gpios = <&gpio 58 GPIO_ACTIVE_HIGH>; }; + sound-card { + compatible = "audio-graph-card"; + label = "OLPC XO"; + dais = <&sspa0_dai>; + routing = "Headphones", "HPOL", + "Headphones", "HPOR", + "MIC2", "Mic Jack"; + widgets = "Headphone", "Headphones", "Microphone", "Mic Jack"; + hp-det-gpio = <&gpio 97 GPIO_ACTIVE_HIGH>; + mic-det-gpio = <&gpio 96 GPIO_ACTIVE_HIGH>; + }; + soc { axi@d4200000 { ap-sp@d4290000 { @@ -197,6 +191,14 @@ compatible = "realtek,alc5631"; reg = <0x1a>; status = "okay"; + + port { + rt5631_0: endpoint { + mclk-fs = <256>; + clocks = <&audio_clk 0>; + remote-endpoint = <&sspa0_0>; + }; + }; }; }; @@ -221,7 +223,8 @@ }; &ssp3 { - #address-cells = <0>; + /delete-property/ #address-cells; + /delete-property/ #size-cells; spi-slave; status = "okay"; ready-gpio = <&gpio 125 GPIO_ACTIVE_HIGH>; @@ -242,3 +245,34 @@ }; }; }; + +&asram { + status = "okay"; +}; + +&adma0 { + status = "okay"; +}; + +&audio_clk { + status = "okay"; +}; + +&sspa0 { + status = "okay"; + dmas = <&adma0 0>, <&adma0 1>; + dma-names = "tx", "rx"; + + sspa0_dai: port { + sspa0_0: endpoint { + remote-endpoint = <&rt5631_0>; + frame-master; + bitclock-master; + dai-format = "i2s"; + }; + }; +}; + +&gpu { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index 4306f3a6742b..445bdcd50b9e 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi @@ -5,6 +5,7 @@ */ #include <dt-bindings/clock/marvell,mmp2.h> +#include <dt-bindings/power/marvell,mmp2.h> / { #address-cells = <1>; @@ -38,6 +39,17 @@ reg = <0xd4200000 0x00200000>; ranges; + gpu: gpu@d420d000 { + compatible = "vivante,gc"; + reg = <0xd420d000 0x4000>; + interrupts = <8>; + status = "disabled"; + clocks = <&soc_clocks MMP2_CLK_GPU_3D>, + <&soc_clocks MMP2_CLK_GPU_BUS>; + clock-names = "core", "bus"; + power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>; + }; + intc: interrupt-controller@d4282000 { compatible = "mrvl,mmp2-intc"; interrupt-controller; @@ -192,6 +204,63 @@ clock-output-names = "mclk"; status = "disabled"; }; + + adma0: dma-controller@d42a0800 { + compatible = "marvell,adma-1.0"; + reg = <0xd42a0800 0x100>; + interrupts = <48>; + #dma-cells = <1>; + asram = <&asram>; + iram = <&asram>; + status = "disabled"; + }; + + adma1: dma-controller@d42a0900 { + compatible = "marvell,adma-1.0"; + reg = <0xd42a0900 0x100>; + interrupts = <48>; + #dma-cells = <1>; + status = "disabled"; + }; + + audio_clk: clocks@d42a0c30 { + compatible = "marvell,mmp2-audio-clock"; + reg = <0xd42a0c30 0x10>; + clock-names = "audio", "vctcxo", "i2s0", "i2s1"; + clocks = <&soc_clocks MMP2_CLK_AUDIO>, + <&soc_clocks MMP2_CLK_VCTCXO>, + <&soc_clocks MMP2_CLK_I2S0>, + <&soc_clocks MMP2_CLK_I2S1>; + power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>; + #clock-cells = <1>; + status = "disabled"; + }; + + sspa0: audio-controller@d42a0c00 { + compatible = "marvell,mmp-sspa"; + reg = <0xd42a0c00 0x30>, + <0xd42a0c80 0x30>; + interrupts = <2>; + clock-names = "audio", "bitclk"; + clocks = <&soc_clocks MMP2_CLK_AUDIO>, + <&audio_clk 1>; + power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sspa1: audio-controller@d42a0d00 { + compatible = "marvell,mmp-sspa"; + reg = <0xd42a0d00 0x30>, + <0xd42a0d80 0x30>; + interrupts = <3>; + clock-names = "audio", "bitclk"; + clocks = <&soc_clocks MMP2_CLK_AUDIO>, + <&audio_clk 2>; + power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; + }; }; apb@d4000000 { /* APB */ @@ -201,6 +270,14 @@ reg = <0xd4000000 0x00200000>; ranges; + dma-controller@d4000000 { + compatible = "marvell,pdma-1.0"; + reg = <0xd4000000 0x10000>; + interrupts = <48>; + #dma-channels = <16>; + status = "disabled"; + }; + timer0: timer@d4014000 { compatible = "mrvl,mmp-timer"; reg = <0xd4014000 0x100>; @@ -413,14 +490,24 @@ }; }; + asram: sram@e0000000 { + compatible = "mmio-sram"; + reg = <0xe0000000 0x10000>; + ranges = <0 0xe0000000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + soc_clocks: clocks { compatible = "marvell,mmp2-clock"; - reg = <0xd4050000 0x1000>, + reg = <0xd4050000 0x2000>, <0xd4282800 0x400>, <0xd4015000 0x1000>; reg-names = "mpmu", "apmu", "apbc"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; }; }; }; diff --git a/arch/arm/boot/dts/mmp3-dell-ariel.dts b/arch/arm/boot/dts/mmp3-dell-ariel.dts index b0ec14c42164..fe3b1cd695ee 100644 --- a/arch/arm/boot/dts/mmp3-dell-ariel.dts +++ b/arch/arm/boot/dts/mmp3-dell-ariel.dts @@ -114,3 +114,11 @@ cs-gpios = <&gpio 56 GPIO_ACTIVE_LOW>; status = "okay"; }; + +&gpu_2d { + status = "okay"; +}; + +&gpu_3d { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mmp3.dtsi b/arch/arm/boot/dts/mmp3.dtsi index 57231d49d938..cc4efd0efabd 100644 --- a/arch/arm/boot/dts/mmp3.dtsi +++ b/arch/arm/boot/dts/mmp3.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/marvell,mmp2.h> +#include <dt-bindings/power/marvell,mmp2.h> #include <dt-bindings/interrupt-controller/arm-gic.h> / { @@ -310,6 +311,30 @@ clock-output-names = "mclk"; status = "disabled"; }; + + gpu_3d: gpu@d420d000 { + compatible = "vivante,gc"; + reg = <0xd420d000 0x2000>; + interrupt-parent = <&gpu_mux>; + interrupts = <0>; + status = "disabled"; + clocks = <&soc_clocks MMP3_CLK_GPU_3D>, + <&soc_clocks MMP3_CLK_GPU_BUS>; + clock-names = "core", "bus"; + power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>; + }; + + gpu_2d: gpu@d420f000 { + compatible = "vivante,gc"; + reg = <0xd420f000 0x2000>; + interrupt-parent = <&gpu_mux>; + interrupts = <2>; + status = "disabled"; + clocks = <&soc_clocks MMP3_CLK_GPU_2D>, + <&soc_clocks MMP3_CLK_GPU_BUS>; + clock-names = "core", "bus"; + power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>; + }; }; apb@d4000000 { diff --git a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi index e39eee628afd..08a7d3ce383f 100644 --- a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi +++ b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi @@ -13,8 +13,10 @@ #interrupt-cells = <2>; #address-cells = <1>; #size-cells = <0>; - spi-max-frequency = <3000000>; + spi-max-frequency = <9600000>; spi-cs-high; + spi-cpol; + spi-cpha; cpcap_adc: adc { compatible = "motorola,mapphone-cpcap-adc"; diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi new file mode 100644 index 000000000000..3b7b9b793736 --- /dev/null +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer <daniel@thingy.jp> + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + }; + + arch_timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) + | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) + | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) + | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) + | IRQ_TYPE_LEVEL_LOW)>; + /* + * we shouldn't need this but the vendor + * u-boot is broken + */ + clock-frequency = <6000000>; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x16001000 0x16001000 0x00007000>, + <0x1f000000 0x1f000000 0x00400000>, + <0xa0000000 0xa0000000 0x20000>; + + gic: interrupt-controller@16001000 { + compatible = "arm,cortex-a7-gic"; + reg = <0x16001000 0x1000>, + <0x16002000 0x2000>, + <0x16004000 0x2000>, + <0x16006000 0x2000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) + | IRQ_TYPE_LEVEL_LOW)>; + }; + + riu: bus@1f000000 { + compatible = "simple-bus"; + reg = <0x1f000000 0x00400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1f000000 0x00400000>; + + pmsleep: syscon@1c00 { + compatible = "mstar,msc313-pmsleep", "syscon"; + reg = <0x1c00 0x100>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&pmsleep>; + offset = <0xb8>; + mask = <0x79>; + }; + + l3bridge: l3bridge@204400 { + compatible = "mstar,l3bridge"; + reg = <0x204400 0x200>; + }; + + pm_uart: uart@221000 { + compatible = "ns16550a"; + reg = <0x221000 0x100>; + reg-shift = <3>; + clock-frequency = <172000000>; + status = "disabled"; + }; + }; + + imi: sram@a0000000 { + compatible = "mmio-sram"; + reg = <0xa0000000 0x10000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi index 8a5cb44bfe2f..f9c2a9938898 100644 --- a/arch/arm/boot/dts/omap2.dtsi +++ b/arch/arm/boot/dts/omap2.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for OMAP2 SoC * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts index 7d660271400d..af964f139abf 100644 --- a/arch/arm/boot/dts/omap2420-h4.dts +++ b/arch/arm/boot/dts/omap2420-h4.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index 6c5c7c0e8b94..494bf6972005 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for OMAP2420 SoC * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any diff --git a/arch/arm/boot/dts/omap2430-sdp.dts b/arch/arm/boot/dts/omap2430-sdp.dts index f7e324886642..7d27e907533f 100644 --- a/arch/arm/boot/dts/omap2430-sdp.dts +++ b/arch/arm/boot/dts/omap2430-sdp.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 6a1f5bb3c06a..d19d8ba3b607 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for OMAP243x SoC * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any diff --git a/arch/arm/boot/dts/omap3-beagle-xm-ab.dts b/arch/arm/boot/dts/omap3-beagle-xm-ab.dts index e498495b8465..cb6968a8bce8 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm-ab.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm-ab.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #include "omap3-beagle-xm.dts" diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index 125ed933ca75..05077f3c75cd 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index dfa158647d91..79bc710c05fc 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi b/arch/arm/boot/dts/omap3-cpu-thermal.dtsi index 235ecfd61e2d..aee46fa8c055 100644 --- a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi +++ b/arch/arm/boot/dts/omap3-cpu-thermal.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for OMAP3 SoC CPU thermal * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts index e0c0382388f0..c9332195d096 100644 --- a/arch/arm/boot/dts/omap3-evm-37xx.dts +++ b/arch/arm/boot/dts/omap3-evm-37xx.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts index 6a94815feb76..5cc0cf7cd16c 100644 --- a/arch/arm/boot/dts/omap3-evm.dts +++ b/arch/arm/boot/dts/omap3-evm.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/omap3-ha-common.dtsi b/arch/arm/boot/dts/omap3-ha-common.dtsi index 33132855d517..a010585d0302 100644 --- a/arch/arm/boot/dts/omap3-ha-common.dtsi +++ b/arch/arm/boot/dts/omap3-ha-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * Copyright (C) 2014 Stefan Roese <sr@denx.de> */ diff --git a/arch/arm/boot/dts/omap3-ha-lcd.dts b/arch/arm/boot/dts/omap3-ha-lcd.dts index c9ecbc45c8e2..b3f7f9966c3c 100644 --- a/arch/arm/boot/dts/omap3-ha-lcd.dts +++ b/arch/arm/boot/dts/omap3-ha-lcd.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * Copyright (C) 2014 Stefan Roese <sr@denx.de> */ diff --git a/arch/arm/boot/dts/omap3-ha.dts b/arch/arm/boot/dts/omap3-ha.dts index 35c4e15abeb7..19e471eb3b4e 100644 --- a/arch/arm/boot/dts/omap3-ha.dts +++ b/arch/arm/boot/dts/omap3-ha.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * Copyright (C) 2014 Stefan Roese <sr@denx.de> */ diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts index ec9ba04ef43b..9c6a92724590 100644 --- a/arch/arm/boot/dts/omap3-ldp.dts +++ b/arch/arm/boot/dts/omap3-ldp.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 4089d97405c9..bc24e3dc7cda 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -19,7 +19,11 @@ * but it is not widely used and to prevent kernel crash rather AES is disabled. * There is also no runtime detection code if AES is disabled in L3 firewall... */ -&aes { +&aes1_target { + status = "disabled"; +}; + +&aes2_target { status = "disabled"; }; @@ -105,6 +109,14 @@ linux,code = <SW_FRONT_PROXIMITY>; linux,can-disable; }; + + machine_cover { + label = "Machine Cover"; + gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* 160 */ + linux,input-type = <EV_SW>; + linux,code = <SW_MACHINE_COVER>; + linux,can-disable; + }; }; isp1707: isp1707 { @@ -819,10 +831,6 @@ pinctrl-0 = <&mmc1_pins>; vmmc-supply = <&vmmc1>; bus-width = <4>; - /* For debugging, it is often good idea to remove this GPIO. - It means you can remove back cover (to reboot by removing - battery) and still use the MMC card. */ - cd-gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* 160 */ }; /* most boards use vaux3, only some old versions use vmmc2 instead */ diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi index f24e2326cfa7..580bfa1931c8 100644 --- a/arch/arm/boot/dts/omap3-tao3530.dtsi +++ b/arch/arm/boot/dts/omap3-tao3530.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * Copyright (C) 2014 Stefan Roese <sr@denx.de> */ /dts-v1/; @@ -8,7 +8,11 @@ #include "omap34xx.dtsi" /* Secure omaps have some devices inaccessible depending on the firmware */ -&aes { +&aes1_target { + status = "disabled"; +}; + +&aes2_target { status = "disabled"; }; diff --git a/arch/arm/boot/dts/omap3-thunder.dts b/arch/arm/boot/dts/omap3-thunder.dts index 64221e3b3477..f7930f198ce5 100644 --- a/arch/arm/boot/dts/omap3-thunder.dts +++ b/arch/arm/boot/dts/omap3-thunder.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * Copyright (C) 2014 Stefan Roese <sr@denx.de> */ diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts index d240e39f2151..0482676d1830 100644 --- a/arch/arm/boot/dts/omap3-zoom3.dts +++ b/arch/arm/boot/dts/omap3-zoom3.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 1296d0643943..cf22a7e1c63c 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for OMAP3 SoC * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -157,13 +157,56 @@ }; }; - aes: aes@480c5000 { - compatible = "ti,omap3-aes"; - ti,hwmods = "aes"; - reg = <0x480c5000 0x50>; - interrupts = <0>; - dmas = <&sdma 65 &sdma 66>; - dma-names = "tx", "rx"; + aes1_target: target-module@480a6000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x480a6044 0x4>, + <0x480a6048 0x4>, + <0x480a604c 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,syss-mask = <1>; + clocks = <&aes1_ick>; + clock-names = "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x480a6000 0x2000>; + + aes1: aes1@0 { + compatible = "ti,omap3-aes"; + reg = <0 0x50>; + interrupts = <0>; + dmas = <&sdma 9 &sdma 10>; + dma-names = "tx", "rx"; + }; + }; + + aes2_target: target-module@480c5000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x480c5044 0x4>, + <0x480c5048 0x4>, + <0x480c504c 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,syss-mask = <1>; + clocks = <&aes2_ick>; + clock-names = "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x480c5000 0x2000>; + + aes2: aes2@0 { + compatible = "ti,omap3-aes"; + reg = <0 0x50>; + interrupts = <0>; + dmas = <&sdma 65 &sdma 66>; + dma-names = "tx", "rx"; + }; }; prm: prm@48306000 { diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts index 7bfde8aac7ae..c5b903718414 100644 --- a/arch/arm/boot/dts/omap3430-sdp.dts +++ b/arch/arm/boot/dts/omap3430-sdp.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index c4dd9801840d..9c3ee4ac8165 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for OMAP34xx/OMAP35xx SoC * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 71f3c8f1f924..9c3beefc0fe0 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for OMAP3 SoC * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any diff --git a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi index ab7f87ae96f0..03d054b2bf9a 100644 --- a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi +++ b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for OMAP4/5 SoC CPU thermal * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * Contact: Eduardo Valentin <eduardo.valentin@ti.com> * * This file is licensed under the terms of the GNU General Public License diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts index 8047e8cdb3af..4548d87534e3 100644 --- a/arch/arm/boot/dts/omap4-duovero-parlor.dts +++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts @@ -139,7 +139,7 @@ ethernet@gpmc { reg = <5 0 0xff>; interrupt-parent = <&gpio2>; - interrupts = <12 IRQ_TYPE_EDGE_FALLING>; /* gpio_44 */ + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; /* gpio_44 */ phy-mode = "mii"; diff --git a/arch/arm/boot/dts/omap4-l4-abe.dtsi b/arch/arm/boot/dts/omap4-l4-abe.dtsi index a6feb201c569..b2cf5f41e222 100644 --- a/arch/arm/boot/dts/omap4-l4-abe.dtsi +++ b/arch/arm/boot/dts/omap4-l4-abe.dtsi @@ -333,8 +333,9 @@ compatible = "ti,omap4430-timer"; reg = <0x00000000 0x80>, <0x49038000 0x80>; - clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>, + <&syc_clk_div_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; ti,timer-dsp; }; @@ -363,8 +364,9 @@ compatible = "ti,omap4430-timer"; reg = <0x00000000 0x80>, <0x4903a000 0x80>; - clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>, + <&syc_clk_div_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; ti,timer-dsp; }; @@ -393,8 +395,9 @@ compatible = "ti,omap4430-timer"; reg = <0x00000000 0x80>, <0x4903c000 0x80>; - clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>, + <&syc_clk_div_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; ti,timer-dsp; }; @@ -423,8 +426,9 @@ compatible = "ti,omap4430-timer"; reg = <0x00000000 0x80>, <0x4903e000 0x80>; - clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>, + <&syc_clk_div_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; ti,timer-pwm; ti,timer-dsp; diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index fcc52121ff09..de742bf84efb 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -240,7 +240,6 @@ target-module@62000 { /* 0x4a062000, ap 11 16.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "usb_tll_hs"; reg = <0x62000 0x4>, <0x62010 0x4>, <0x62014 0x4>; @@ -268,7 +267,6 @@ target-module@64000 { /* 0x4a064000, ap 86 1e.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_host_hs"; reg = <0x64000 0x4>, <0x64010 0x4>, <0x64014 0x4>; @@ -1163,8 +1161,9 @@ timer1: timer@0 { compatible = "ti,omap3430-timer"; reg = <0x0 0x80>; - clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; ti,timer-alwon; }; @@ -1439,8 +1438,9 @@ timer2: timer@0 { compatible = "ti,omap3430-timer"; reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -1466,8 +1466,9 @@ timer3: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -1493,8 +1494,9 @@ timer4: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -1520,8 +1522,9 @@ timer9: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; ti,timer-pwm; }; @@ -1954,8 +1957,9 @@ timer10: timer@0 { compatible = "ti,omap3430-timer"; reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; ti,timer-pwm; }; @@ -1982,8 +1986,9 @@ timer11: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; ti,timer-pwm; }; diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts index 64083075dd52..8fd076e5d1b0 100644 --- a/arch/arm/boot/dts/omap4-panda-a4.dts +++ b/arch/arm/boot/dts/omap4-panda-a4.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 55ea8b6189af..3e78caefa2b8 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011-2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011-2013 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/input/input.h> #include "elpida_ecb240abacn.dtsi" @@ -12,6 +12,26 @@ reg = <0x80000000 0x40000000>; /* 1 GB */ }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dsp_memory_region: dsp-memory@98000000 { + compatible = "shared-dma-pool"; + reg = <0x98000000 0x800000>; + reusable; + status = "okay"; + }; + + ipu_memory_region: ipu-memory@98800000 { + compatible = "shared-dma-pool"; + reg = <0x98800000 0x7000000>; + reusable; + status = "okay"; + }; + }; + chosen { stdout-path = &uart3; }; @@ -571,3 +591,17 @@ }; }; }; + +&dsp { + status = "okay"; + memory-region = <&dsp_memory_region>; + ti,timers = <&timer5>; + ti,watchdog-timers = <&timer6>; +}; + +&ipu { + status = "okay"; + memory-region = <&ipu_memory_region>; + ti,timers = <&timer3>; + ti,watchdog-timers = <&timer9>, <&timer11>; +}; diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts index 9dd307b52604..cfa85aa3da08 100644 --- a/arch/arm/boot/dts/omap4-panda-es.dts +++ b/arch/arm/boot/dts/omap4-panda-es.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts index fb2f47717b45..529d5bcceaaf 100644 --- a/arch/arm/boot/dts/omap4-panda.dts +++ b/arch/arm/boot/dts/omap4-panda.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts index 42154520d383..869f6279b5be 100644 --- a/arch/arm/boot/dts/omap4-sdp-es23plus.dts +++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ #include "omap4-sdp.dts" diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 91480ac1f328..79e7a41ecb7e 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -428,7 +428,7 @@ /* * Temperature Sensor - * http://www.ti.com/lit/ds/symlink/tmp105.pdf + * https://www.ti.com/lit/ds/symlink/tmp105.pdf */ tmp105@48 { compatible = "ti,tmp105"; @@ -453,7 +453,7 @@ /* * 3-Axis Digital Compass - * http://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf + * https://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf */ hmc5843@1e { compatible = "honeywell,hmc5843"; diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi index 41de32bcf187..334cbbaa5b8b 100644 --- a/arch/arm/boot/dts/omap4-var-som-om44.dtsi +++ b/arch/arm/boot/dts/omap4-var-som-om44.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Joachim Eastwood <manabian@gmail.com> - * Copyright (C) 2012 Variscite Ltd. - http://www.variscite.com + * Copyright (C) 2012 Variscite Ltd. - https://www.variscite.com */ #include "omap4460.dtsi" #include "omap4-mcpdm.dtsi" diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 6c2b07f0704d..0282b9de3384 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/bus/ti-sysc.h> @@ -26,6 +26,8 @@ serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; + rproc0 = &dsp; + rproc1 = &ipu; }; cpus { @@ -71,7 +73,7 @@ interrupt-parent = <&gic>; }; - L2: l2-cache-controller@48242000 { + L2: cache-controller@48242000 { compatible = "arm,pl310-cache"; reg = <0x48242000 0x1000>; cache-unified; @@ -106,10 +108,6 @@ sram = <&ocmcram>; }; - dsp { - compatible = "ti,omap3-c64"; - }; - iva { compatible = "ti,ivahd"; ti,hwmods = "iva"; @@ -277,6 +275,29 @@ hw-caps-temp-alert; }; + dsp: dsp { + compatible = "ti,omap4-dsp"; + ti,bootreg = <&scm_conf 0x304 0>; + iommus = <&mmu_dsp>; + resets = <&prm_tesla 0>; + clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; + firmware-name = "omap4-dsp-fw.xe64T"; + mboxes = <&mailbox &mbox_dsp>; + status = "disabled"; + }; + + ipu: ipu@55020000 { + compatible = "ti,omap4-ipu"; + reg = <0x55020000 0x10000>; + reg-names = "l2ram"; + iommus = <&mmu_ipu>; + resets = <&prm_core 0>, <&prm_core 1>; + clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>; + firmware-name = "omap4-ipu-fw.xem3"; + mboxes = <&mailbox &mbox_ipu>; + status = "disabled"; + }; + aes1_target: target-module@4b501000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x4b501080 0x4>, @@ -662,6 +683,6 @@ ti,no-idle; timer@0 { assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>; - assigned-clock-parents = <&sys_clkin_ck>; + assigned-clock-parents = <&sys_32k_ck>; }; }; diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi index cbcdcb4e7d1c..8ed510ab00c5 100644 --- a/arch/arm/boot/dts/omap443x.dtsi +++ b/arch/arm/boot/dts/omap443x.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for OMAP443x SoC * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi index 2223dc0d63c0..2d3e54901b6e 100644 --- a/arch/arm/boot/dts/omap4460.dtsi +++ b/arch/arm/boot/dts/omap4460.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for OMAP4460 SoC * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index 68ac04641bdb..edf1906016c8 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ #include "omap5.dtsi" #include <dt-bindings/interrupt-controller/irq.h> diff --git a/arch/arm/boot/dts/omap5-core-thermal.dtsi b/arch/arm/boot/dts/omap5-core-thermal.dtsi index de8a3d456cf7..02e76338bfbc 100644 --- a/arch/arm/boot/dts/omap5-core-thermal.dtsi +++ b/arch/arm/boot/dts/omap5-core-thermal.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for OMAP543x SoC CORE thermal * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * Contact: Eduardo Valentin <eduardo.valentin@ti.com> * * This file is licensed under the terms of the GNU General Public License diff --git a/arch/arm/boot/dts/omap5-gpu-thermal.dtsi b/arch/arm/boot/dts/omap5-gpu-thermal.dtsi index bc3090f2e84b..bf8fa9372e57 100644 --- a/arch/arm/boot/dts/omap5-gpu-thermal.dtsi +++ b/arch/arm/boot/dts/omap5-gpu-thermal.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for OMAP543x SoC GPU thermal * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * Contact: Eduardo Valentin <eduardo.valentin@ti.com> * * This file is licensed under the terms of the GNU General Public License diff --git a/arch/arm/boot/dts/omap5-l4-abe.dtsi b/arch/arm/boot/dts/omap5-l4-abe.dtsi index bafd6adf9f45..25b7fce8de2d 100644 --- a/arch/arm/boot/dts/omap5-l4-abe.dtsi +++ b/arch/arm/boot/dts/omap5-l4-abe.dtsi @@ -298,8 +298,9 @@ compatible = "ti,omap5430-timer"; reg = <0x0 0x80>, <0x49038000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>, + <&dss_syc_gfclk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; ti,timer-dsp; ti,timer-pwm; @@ -329,8 +330,9 @@ compatible = "ti,omap5430-timer"; reg = <0x0 0x80>, <0x4903a000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>, + <&dss_syc_gfclk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; ti,timer-dsp; ti,timer-pwm; @@ -360,8 +362,9 @@ compatible = "ti,omap5430-timer"; reg = <0x0 0x80>, <0x4903c000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>, + <&dss_syc_gfclk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; ti,timer-dsp; }; @@ -390,8 +393,9 @@ compatible = "ti,omap5430-timer"; reg = <0x0 0x80>, <0x4903e000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>, + <&dss_syc_gfclk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; ti,timer-dsp; ti,timer-pwm; diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index 5217805bf126..f3d3a16b7c64 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -167,7 +167,6 @@ target-module@20000 { /* 0x4a020000, ap 109 08.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_otg_ss"; reg = <0x20000 0x4>, <0x20010 0x4>; reg-names = "rev", "sysc"; @@ -269,7 +268,6 @@ target-module@62000 { /* 0x4a062000, ap 11 0e.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "usb_tll_hs"; reg = <0x62000 0x4>, <0x62010 0x4>, <0x62014 0x4>; @@ -298,7 +296,6 @@ target-module@64000 { /* 0x4a064000, ap 71 1e.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "usb_host_hs"; reg = <0x64000 0x4>, <0x64010 0x4>; reg-names = "rev", "sysc"; @@ -1082,8 +1079,9 @@ timer2: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -1109,8 +1107,9 @@ timer3: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -1136,8 +1135,9 @@ timer4: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -1163,8 +1163,9 @@ timer9: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; ti,timer-pwm; }; @@ -1730,8 +1731,9 @@ timer10: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; ti,timer-pwm; }; @@ -1758,8 +1760,9 @@ timer11: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; ti,timer-pwm; }; @@ -2387,8 +2390,9 @@ timer1: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; ti,timer-alwon; }; diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 9441e9a572ad..51d5fcae5081 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -15,6 +15,26 @@ reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dsp_memory_region: dsp-memory@95000000 { + compatible = "shared-dma-pool"; + reg = <0 0x95000000 0 0x800000>; + reusable; + status = "okay"; + }; + + ipu_memory_region: ipu-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0 0x95800000 0 0x3800000>; + reusable; + status = "okay"; + }; + }; + aliases { ethernet = ðernet; }; @@ -198,3 +218,17 @@ &wlcore { compatible = "ti,wl1837"; }; + +&dsp { + status = "okay"; + memory-region = <&dsp_memory_region>; + ti,timers = <&timer5>; + ti,watchdog-timers = <&timer6>; +}; + +&ipu { + status = "okay"; + memory-region = <&ipu_memory_region>; + ti,timers = <&timer3>; + ti,watchdog-timers = <&timer9>, <&timer11>; +}; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index fb889c5b00c9..5da9cff7a53c 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * * Based on "omap4.dtsi" */ @@ -31,6 +31,8 @@ serial3 = &uart4; serial4 = &uart5; serial5 = &uart6; + rproc0 = &dsp; + rproc1 = &ipu; }; cpus { @@ -216,6 +218,29 @@ }; }; + dsp: dsp { + compatible = "ti,omap5-dsp"; + ti,bootreg = <&scm_conf 0x304 0>; + iommus = <&mmu_dsp>; + resets = <&prm_dsp 0>; + clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; + firmware-name = "omap5-dsp-fw.xe64T"; + mboxes = <&mailbox &mbox_dsp>; + status = "disabled"; + }; + + ipu: ipu@55020000 { + compatible = "ti,omap5-ipu"; + reg = <0x55020000 0x10000>; + reg-names = "l2ram"; + iommus = <&mmu_ipu>; + resets = <&prm_core 0>, <&prm_core 1>; + clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; + firmware-name = "omap5-ipu-fw.xem4"; + mboxes = <&mailbox &mbox_ipu>; + status = "disabled"; + }; + dmm@4e000000 { compatible = "ti,omap5-dmm"; reg = <0x4e000000 0x800>; diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts new file mode 100644 index 000000000000..282b89ce3d45 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-ipq8064.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "MikroTik RB3011UiAS-RM"; + compatible = "mikrotik,rb3011"; + + aliases { + serial0 = &gsbi7_serial; + ethernet0 = &gmac0; + ethernet1 = &gmac3; + mdio-gpio0 = &mdio0; + mdio-gpio1 = &mdio1; + }; + + chosen { + bootargs = "loglevel=8 console=ttyMSM0,115200"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + reg = <0x42000000 0x3e000000>; + device_type = "memory"; + }; + + mdio0: mdio@0 { + status = "okay"; + compatible = "virtual,mdio-gpio"; + gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, + <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + switch0: switch@10 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + + dsa,member = <0 0>; + + pinctrl-0 = <&sw0_reset_pin>; + pinctrl-names = "default"; + + reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + switch0cpu: port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "sw1"; + }; + + port@2 { + reg = <2>; + label = "sw2"; + }; + + port@3 { + reg = <3>; + label = "sw3"; + }; + + port@4 { + reg = <4>; + label = "sw4"; + }; + + port@5 { + reg = <5>; + label = "sw5"; + }; + }; + }; + }; + + mdio1: mdio@1 { + status = "okay"; + compatible = "virtual,mdio-gpio"; + gpios = <&qcom_pinmux 11 GPIO_ACTIVE_HIGH>, + <&qcom_pinmux 10 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&mdio1_pins>; + pinctrl-names = "default"; + + switch1: switch@14 { + compatible = "qca,qca8337"; + #address-cells = <1>; + #size-cells = <0>; + + dsa,member = <1 0>; + + pinctrl-0 = <&sw1_reset_pin>; + pinctrl-names = "default"; + + reset-gpios = <&qcom_pinmux 17 GPIO_ACTIVE_LOW>; + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + switch1cpu: port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&gmac3>; + phy-mode = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "sw6"; + }; + + port@2 { + reg = <2>; + label = "sw7"; + }; + + port@3 { + reg = <3>; + label = "sw8"; + }; + + port@4 { + reg = <4>; + label = "sw9"; + }; + + port@5 { + reg = <5>; + label = "sw10"; + }; + }; + }; + }; + + soc { + gsbi5: gsbi@1a200000 { + qcom,mode = <GSBI_PROT_SPI>; + status = "okay"; + + spi4: spi@1a280000 { + status = "okay"; + spi-max-frequency = <50000000>; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + norflash: s25fl016k@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + partition@0 { + label = "RouterBoot"; + reg = <0x0 0x40000>; + }; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-0 = <&buttons_pins>; + pinctrl-names = "default"; + + button@1 { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&qcom_pinmux 66 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&leds_pins>; + pinctrl-names = "default"; + + led@7 { + label = "rb3011:green:user"; + gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + }; +}; + +&gmac0 { + status = "okay"; + + phy-mode = "rgmii"; + qcom,id = <0>; + phy-handle = <&switch0cpu>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac3 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <3>; + phy-handle = <&switch1cpu>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gsbi7 { + status = "okay"; + qcom,mode = <GSBI_PROT_I2C_UART>; +}; + +&gsbi7_serial { + status = "okay"; +}; + +&qcom_pinmux { + buttons_pins: buttons_pins { + mux { + pins = "gpio66"; + drive-strength = <16>; + bias-disable; + }; + }; + + leds_pins: leds_pins { + mux { + pins = "gpio33"; + drive-strength = <16>; + bias-disable; + }; + }; + + mdio0_pins: mdio0_pins { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + }; + + mdio1_pins: mdio1_pins { + mux { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + }; + + sw0_reset_pin: sw0_reset_pin { + mux { + pins = "gpio16"; + drive-strength = <16>; + function = "gpio"; + bias-disable; + input-disable; + }; + }; + + sw1_reset_pin: sw1_reset_pin { + mux { + pins = "gpio17"; + drive-strength = <16>; + function = "gpio"; + bias-disable; + input-disable; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index b912da9a3ff3..c51481405e7f 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -425,6 +425,13 @@ qcom,controller-type = "pmic-arbiter"; }; + qfprom: qfprom@700000 { + compatible = "qcom,qfprom"; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + gcc: clock-controller@900000 { compatible = "qcom,gcc-ipq8064"; reg = <0x00900000 0x4000>; @@ -597,6 +604,114 @@ perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; }; + nss_common: syscon@03000000 { + compatible = "syscon"; + reg = <0x03000000 0x0000FFFF>; + }; + + qsgmii_csr: syscon@1bb00000 { + compatible = "syscon"; + reg = <0x1bb00000 0x000001FF>; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <7>; + snps,rd_osr_lmt = <7>; + snps,blen = <16 0 0 0 0 0 0>; + }; + + gmac0: ethernet@37000000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac"; + reg = <0x37000000 0x200000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + + snps,axi-config = <&stmmac_axi_setup>; + snps,pbl = <32>; + snps,aal = <1>; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE1_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE1_RESET>; + reset-names = "stmmaceth"; + + status = "disabled"; + }; + + gmac1: ethernet@37200000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac"; + reg = <0x37200000 0x200000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + + snps,axi-config = <&stmmac_axi_setup>; + snps,pbl = <32>; + snps,aal = <1>; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE2_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE2_RESET>; + reset-names = "stmmaceth"; + + status = "disabled"; + }; + + gmac2: ethernet@37400000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac"; + reg = <0x37400000 0x200000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + + snps,axi-config = <&stmmac_axi_setup>; + snps,pbl = <32>; + snps,aal = <1>; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE3_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE3_RESET>; + reset-names = "stmmaceth"; + + status = "disabled"; + }; + + gmac3: ethernet@37600000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac"; + reg = <0x37600000 0x200000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + + snps,axi-config = <&stmmac_axi_setup>; + snps,pbl = <32>; + snps,aal = <1>; + + qcom,nss-common = <&nss_common>; + qcom,qsgmii-csr = <&qsgmii_csr>; + + clocks = <&gcc GMAC_CORE4_CLK>; + clock-names = "stmmaceth"; + + resets = <&gcc GMAC_CORE4_RESET>; + reset-names = "stmmaceth"; + + status = "disabled"; + }; + vsdcc_fixed: vsdcc-regulator { compatible = "regulator-fixed"; regulator-name = "SDCC Power"; diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 0a567d8ebc66..b9b138888048 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -323,7 +323,7 @@ status = "disabled"; }; - sdhi0: sd@e804e000 { + sdhi0: mmc@e804e000 { compatible = "renesas,sdhi-r7s72100"; reg = <0xe804e000 0x100>; interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, @@ -339,7 +339,7 @@ status = "disabled"; }; - sdhi1: sd@e804e800 { + sdhi1: mmc@e804e800 { compatible = "renesas,sdhi-r7s72100"; reg = <0xe804e800 0x100>; interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi index cace43807497..838920aef992 100644 --- a/arch/arm/boot/dts/r7s9210.dtsi +++ b/arch/arm/boot/dts/r7s9210.dtsi @@ -416,7 +416,7 @@ status = "disabled"; }; - sdhi0: sd@e8228000 { + sdhi0: mmc@e8228000 { compatible = "renesas,sdhi-r7s9210"; reg = <0xe8228000 0x8c0>; interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; @@ -428,7 +428,7 @@ status = "disabled"; }; - sdhi1: sd@e822a000 { + sdhi1: mmc@e822a000 { compatible = "renesas,sdhi-r7s9210"; reg = <0xe822a000 0x8c0>; interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index a3ba722a9d7f..b92e72579836 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -409,7 +409,7 @@ status = "disabled"; }; - sdhi0: sd@ee100000 { + sdhi0: mmc@ee100000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee100000 0 0x100>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; @@ -419,7 +419,7 @@ status = "disabled"; }; - sdhi1: sd@ee120000 { + sdhi1: mmc@ee120000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee120000 0 0x100>; interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; @@ -429,7 +429,7 @@ status = "disabled"; }; - sdhi2: sd@ee140000 { + sdhi2: mmc@ee140000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee140000 0 0x100>; interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 0588d4446f9a..8048303037ee 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -349,7 +349,7 @@ status = "disabled"; }; - sdhi0: sd@e6850000 { + sdhi0: mmc@e6850000 { compatible = "renesas,sdhi-r8a7740"; reg = <0xe6850000 0x100>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, @@ -362,7 +362,7 @@ status = "disabled"; }; - sdhi1: sd@e6860000 { + sdhi1: mmc@e6860000 { compatible = "renesas,sdhi-r8a7740"; reg = <0xe6860000 0x100>; interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, @@ -375,7 +375,7 @@ status = "disabled"; }; - sdhi2: sd@e6870000 { + sdhi2: mmc@e6870000 { compatible = "renesas,sdhi-r8a7740"; reg = <0xe6870000 0x100>; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts new file mode 100644 index 000000000000..1479ced50873 --- /dev/null +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZ/G1H Qseven board development + * platform with camera daughter board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a7742-iwg21d-q7.dts" + +/ { + model = "iWave Systems RZ/G1H Qseven development platform with camera add-on"; + compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742"; + + aliases { + serial0 = &scif0; + serial1 = &scif1; + serial3 = &scifb1; + serial5 = &hscif0; + ethernet1 = ðer; + }; +}; + +&avb { + /* Pins shared with VIN0, keep status disabled */ + status = "disabled"; +}; + +ðer { + pinctrl-0 = <ðer_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + micrel,led-mode = <1>; + }; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&pfc { + ether_pins: ether { + groups = "eth_mdio", "eth_rmii"; + function = "eth"; + }; + + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + scif1_pins: scif1 { + groups = "scif1_data"; + function = "scif1"; + }; + + scifb1_pins: scifb1 { + groups = "scifb1_data"; + function = "scifb1"; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&scifb1 { + pinctrl-0 = <&scifb1_pins>; + pinctrl-names = "default"; + status = "okay"; + + rts-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index 1f5c35c66d91..e90aaf1c94f0 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -5,6 +5,29 @@ * Copyright (C) 2020 Renesas Electronics Corp. */ +/* + * SSI-SGTL5000 + * + * This command is required when Playback/Capture + * + * amixer set "DVC Out" 100% + * amixer set "DVC In" 100% + * + * You can use Mute + * + * amixer set "DVC Out Mute" on + * amixer set "DVC In Mute" on + * + * You can use Volume Ramp + * + * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" + * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" + * amixer set "DVC Out Ramp" on + * aplay xxx.wav & + * amixer set "DVC Out" 80% // Volume Down + * amixer set "DVC Out" 100% // Volume Up + */ + /dts-v1/; #include "r8a7742-iwg21m.dtsi" @@ -14,19 +37,158 @@ aliases { serial2 = &scifa2; + serial4 = &scifb2; + ethernet0 = &avb; }; chosen { bootargs = "ignore_loglevel root=/dev/mmcblk0p1 rw rootwait"; stdout-path = "serial2:115200n8"; }; + + audio_clock: audio_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + reg_1p5v: 1p5v { + compatible = "regulator-fixed"; + regulator-name = "1P5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + rsnd_sgtl5000: sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; + + vcc_sdhi2: regulator-vcc-sdhi2 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI2 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio1 27 GPIO_ACTIVE_LOW>; + }; + + vccq_sdhi2: regulator-vccq-sdhi2 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI2 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy3>; + phy-mode = "gmii"; + renesas,no-ether-link; + status = "okay"; + + phy3: ethernet-phy@3 { + reg = <3>; + micrel,led-mode = <1>; + }; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + reg = <0x0a>; + clocks = <&audio_clock>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + VDDD-supply = <®_1p5v>; + }; }; &pfc { + avb_pins: avb { + groups = "avb_mdio", "avb_gmii"; + function = "avb"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2_b"; + function = "i2c2"; + }; + scifa2_pins: scifa2 { groups = "scifa2_data_c"; function = "scifa2"; }; + + scifb2_pins: scifb2 { + groups = "scifb2_data", "scifb2_ctrl"; + function = "scifb2"; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; + + sound_pins: sound { + groups = "ssi34_ctrl", "ssi3_data", "ssi4_data"; + function = "ssi"; + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + rcar_sound,dai { + dai0 { + playback = <&ssi4 &src4 &dvc1>; + capture = <&ssi3 &src3 &dvc0>; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; }; &scifa2 { @@ -35,3 +197,28 @@ status = "okay"; }; + +&scifb2 { + pinctrl-0 = <&scifb2_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi2>; + vqmmc-supply = <&vccq_sdhi2>; + cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; + status = "okay"; +}; + +&ssi4 { + shared-pin; +}; diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 305d8086a3dd..9743b4242801 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -15,9 +15,31 @@ #address-cells = <2>; #size-cells = <2>; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -200,6 +222,17 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7742-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7742", "renesas,rcar-gen2-gpio"; @@ -305,6 +338,18 @@ #reset-cells = <1>; }; + apmu@e6151000 { + compatible = "renesas,r8a7742-apmu", "renesas,apmu"; + reg = <0 0xe6151000 0 0x188>; + cpus = <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + + apmu@e6152000 { + compatible = "renesas,r8a7742-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + rst: reset-controller@e6160000 { compatible = "renesas,r8a7742-rst"; reg = <0 0xe6160000 0 0x0100>; @@ -330,6 +375,17 @@ resets = <&cpg 407>; }; + thermal: thermal@e61f0000 { + compatible = "renesas,thermal-r8a7742", + "renesas,rcar-gen2-thermal"; + reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; + icram0: sram@e63a0000 { compatible = "mmio-sram"; reg = <0 0xe63a0000 0 0x12000>; @@ -359,6 +415,195 @@ ranges = <0 0 0xe6300000 0x40000>; }; + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7742", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7742", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7742", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7742", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + iic0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7742", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + iic1: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7742", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 323>; + status = "disabled"; + }; + + iic2: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7742", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6520000 0 0x425>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 300>; + dmas = <&dmac0 0x69>, <&dmac0 0x6a>, + <&dmac1 0x69>, <&dmac1 0x6a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + + iic3: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7742"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7742", + "renesas,rcar-gen2-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7742", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7742-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7742-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a7742", "renesas,rcar-dmac"; @@ -425,6 +670,19 @@ dma-channels = <15>; }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7742", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7742", "renesas,rcar-gen2-scifa", "renesas,scifa"; @@ -595,6 +853,515 @@ status = "disabled"; }; + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7742", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 0>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7742", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7742", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 205>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c90000 { + compatible = "renesas,msiof-r8a7742", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6c90000 0 0x0064>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 215>; + dmas = <&dmac0 0x45>, <&dmac0 0x46>, + <&dmac1 0x45>, <&dmac1 0x46>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 215>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7742", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7742_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma1 0x02>, + <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma1 0x04>, + <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma1 0x06>, + <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma1 0x08>, + <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma1 0x0a>, + <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, + <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, + <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma1 0x10>, + <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma1 0x12>, + <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma1 0x14>, + <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7742", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7742", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + xhci: usb@ee000000 { + compatible = "renesas,xhci-r8a7742", + "renesas,rcar-gen2-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 328>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; + }; + + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7742", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + }; + + pci1: pci@ee0b0000 { + compatible = "renesas,pci-r8a7742", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0b0000 0 0xc00>, + <0 0xee0a0000 0 0x1100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + }; + + pci2: pci@ee0d0000 { + compatible = "renesas,pci-r8a7742", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 703>; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + bus-range = <2 2>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x20800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x21000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + }; + + sdhi0: mmc@ee100000 { + compatible = "renesas,sdhi-r8a7742", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: mmc@ee120000 { + compatible = "renesas,sdhi-r8a7742", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee120000 0 0x328>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 313>; + dmas = <&dmac0 0xc9>, <&dmac0 0xca>, + <&dmac1 0xc9>, <&dmac1 0xca>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: mmc@ee140000 { + compatible = "renesas,sdhi-r8a7742", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee140000 0 0x100>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: mmc@ee160000 { + compatible = "renesas,sdhi-r8a7742", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee160000 0 0x100>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7742", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; + }; + mmcif1: mmc@ee220000 { compatible = "renesas,mmcif-r8a7742", "renesas,sh-mmcif"; @@ -611,6 +1378,42 @@ max-frequency = <97500000>; }; + sata0: sata@ee300000 { + compatible = "renesas,sata-r8a7742", + "renesas,rcar-gen2-sata"; + reg = <0 0xee300000 0 0x200000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 815>; + status = "disabled"; + }; + + sata1: sata@ee500000 { + compatible = "renesas,sata-r8a7742", + "renesas,rcar-gen2-sata"; + reg = <0 0xee500000 0 0x200000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 814>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 814>; + status = "disabled"; + }; + + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7742", + "renesas,rcar-gen2-ether"; + reg = <0 0xee700000 0 0x400>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -629,6 +1432,57 @@ compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; }; + + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7742-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7742-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 329>; + status = "disabled"; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <95000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + }; + }; }; timer { diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index fff123753b85..896916a00b84 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -1520,7 +1520,7 @@ }; }; - sdhi0: sd@ee100000 { + sdhi0: mmc@ee100000 { compatible = "renesas,sdhi-r8a7743", "renesas,rcar-gen2-sdhi"; reg = <0 0xee100000 0 0x328>; @@ -1535,7 +1535,7 @@ status = "disabled"; }; - sdhi1: sd@ee140000 { + sdhi1: mmc@ee140000 { compatible = "renesas,sdhi-r8a7743", "renesas,rcar-gen2-sdhi"; reg = <0 0xee140000 0 0x100>; @@ -1550,7 +1550,7 @@ status = "disabled"; }; - sdhi2: sd@ee160000 { + sdhi2: mmc@ee160000 { compatible = "renesas,sdhi-r8a7743", "renesas,rcar-gen2-sdhi"; reg = <0 0xee160000 0 0x100>; diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 5050ac19041d..6b56aa286337 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -1520,7 +1520,7 @@ }; }; - sdhi0: sd@ee100000 { + sdhi0: mmc@ee100000 { compatible = "renesas,sdhi-r8a7744", "renesas,rcar-gen2-sdhi"; reg = <0 0xee100000 0 0x328>; @@ -1535,7 +1535,7 @@ status = "disabled"; }; - sdhi1: sd@ee140000 { + sdhi1: mmc@ee140000 { compatible = "renesas,sdhi-r8a7744", "renesas,rcar-gen2-sdhi"; reg = <0 0xee140000 0 0x100>; @@ -1550,7 +1550,7 @@ status = "disabled"; }; - sdhi2: sd@ee160000 { + sdhi2: mmc@ee160000 { compatible = "renesas,sdhi-r8a7744", "renesas,rcar-gen2-sdhi"; reg = <0 0xee160000 0 0x100>; diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index b0d1fc24e97e..636248f370e0 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -1396,7 +1396,7 @@ }; }; - sdhi0: sd@ee100000 { + sdhi0: mmc@ee100000 { compatible = "renesas,sdhi-r8a7745", "renesas,rcar-gen2-sdhi"; reg = <0 0xee100000 0 0x328>; @@ -1411,7 +1411,7 @@ status = "disabled"; }; - sdhi1: sd@ee140000 { + sdhi1: mmc@ee140000 { compatible = "renesas,sdhi-r8a7745", "renesas,rcar-gen2-sdhi"; reg = <0 0xee140000 0 0x100>; @@ -1426,7 +1426,7 @@ status = "disabled"; }; - sdhi2: sd@ee160000 { + sdhi2: mmc@ee160000 { compatible = "renesas,sdhi-r8a7745", "renesas,rcar-gen2-sdhi"; reg = <0 0xee160000 0 0x100>; diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index f55153192276..6baa126b6590 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -882,7 +882,7 @@ status = "disabled"; }; - sdhi0: sd@ee100000 { + sdhi0: mmc@ee100000 { compatible = "renesas,sdhi-r8a77470", "renesas,rcar-gen2-sdhi"; reg = <0 0xee100000 0 0x328>; @@ -897,7 +897,7 @@ status = "disabled"; }; - sdhi1: sd@ee300000 { + sdhi1: mmc@ee300000 { compatible = "renesas,sdhi-mmc-r8a77470"; reg = <0 0xee300000 0 0x2000>; interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; @@ -908,7 +908,7 @@ status = "disabled"; }; - sdhi2: sd@ee160000 { + sdhi2: mmc@ee160000 { compatible = "renesas,sdhi-r8a77470", "renesas,rcar-gen2-sdhi"; reg = <0 0xee160000 0 0x328>; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 593c6df90303..1612b003fb55 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -78,7 +78,8 @@ <0xfe780010 4>, <0xfe780024 4>, <0xfe780044 4>, - <0xfe780064 4>; + <0xfe780064 4>, + <0xfe780000 4>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, @@ -400,7 +401,7 @@ status = "disabled"; }; - sdhi0: sd@ffe4c000 { + sdhi0: mmc@ffe4c000 { compatible = "renesas,sdhi-r8a7778", "renesas,rcar-gen1-sdhi"; reg = <0xffe4c000 0x100>; @@ -410,7 +411,7 @@ status = "disabled"; }; - sdhi1: sd@ffe4d000 { + sdhi1: mmc@ffe4d000 { compatible = "renesas,sdhi-r8a7778", "renesas,rcar-gen1-sdhi"; reg = <0xffe4d000 0x100>; @@ -420,7 +421,7 @@ status = "disabled"; }; - sdhi2: sd@ffe4f000 { + sdhi2: mmc@ffe4f000 { compatible = "renesas,sdhi-r8a7778", "renesas,rcar-gen1-sdhi"; reg = <0xffe4f000 0x100>; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index c0999e27e9b1..c5634daef96f 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -385,7 +385,7 @@ status = "disabled"; }; - sdhi0: sd@ffe4c000 { + sdhi0: mmc@ffe4c000 { compatible = "renesas,sdhi-r8a7779", "renesas,rcar-gen1-sdhi"; reg = <0xffe4c000 0x100>; @@ -395,7 +395,7 @@ status = "disabled"; }; - sdhi1: sd@ffe4d000 { + sdhi1: mmc@ffe4d000 { compatible = "renesas,sdhi-r8a7779", "renesas,rcar-gen1-sdhi"; reg = <0xffe4d000 0x100>; @@ -405,7 +405,7 @@ status = "disabled"; }; - sdhi2: sd@ffe4e000 { + sdhi2: mmc@ffe4e000 { compatible = "renesas,sdhi-r8a7779", "renesas,rcar-gen1-sdhi"; reg = <0xffe4e000 0x100>; @@ -415,7 +415,7 @@ status = "disabled"; }; - sdhi3: sd@ffe4f000 { + sdhi3: mmc@ffe4f000 { compatible = "renesas,sdhi-r8a7779", "renesas,rcar-gen1-sdhi"; reg = <0xffe4f000 0x100>; diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index bfe778c4c47b..09a152b91557 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -343,7 +343,6 @@ composite-in@20 { compatible = "adi,adv7180"; reg = <0x20>; - remote = <&vin1>; port { adv7180: endpoint { diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 166d5566229d..769ba2a33d39 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1467,7 +1467,7 @@ }; }; - sdhi0: sd@ee100000 { + sdhi0: mmc@ee100000 { compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; reg = <0 0xee100000 0 0x328>; @@ -1482,7 +1482,7 @@ status = "disabled"; }; - sdhi1: sd@ee120000 { + sdhi1: mmc@ee120000 { compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; reg = <0 0xee120000 0 0x328>; @@ -1497,7 +1497,7 @@ status = "disabled"; }; - sdhi2: sd@ee140000 { + sdhi2: mmc@ee140000 { compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; reg = <0 0xee140000 0 0x100>; @@ -1512,7 +1512,7 @@ status = "disabled"; }; - sdhi3: sd@ee160000 { + sdhi3: mmc@ee160000 { compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; reg = <0 0xee160000 0 0x100>; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index fc74c6cd6def..f603cba5441f 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -366,7 +366,6 @@ composite-in@20 { compatible = "adi,adv7180"; reg = <0x20>; - remote = <&vin1>; port { adv7180: endpoint { diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index 114bf1c4199b..c6d563fb7ec7 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -162,7 +162,6 @@ composite-in@20 { compatible = "adi,adv7180"; reg = <0x20>; - remote = <&vin0>; port { adv7180: endpoint { diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 225676fbe312..499cf388735f 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1563,7 +1563,7 @@ }; }; - sdhi0: sd@ee100000 { + sdhi0: mmc@ee100000 { compatible = "renesas,sdhi-r8a7791", "renesas,rcar-gen2-sdhi"; reg = <0 0xee100000 0 0x328>; @@ -1578,7 +1578,7 @@ status = "disabled"; }; - sdhi1: sd@ee140000 { + sdhi1: mmc@ee140000 { compatible = "renesas,sdhi-r8a7791", "renesas,rcar-gen2-sdhi"; reg = <0 0xee140000 0 0x100>; @@ -1593,7 +1593,7 @@ status = "disabled"; }; - sdhi2: sd@ee160000 { + sdhi2: mmc@ee160000 { compatible = "renesas,sdhi-r8a7791", "renesas,rcar-gen2-sdhi"; reg = <0 0xee160000 0 0x100>; diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 4627eefa502b..597848ad4dfa 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -780,7 +780,7 @@ status = "disabled"; }; - sdhi0: sd@ee100000 { + sdhi0: mmc@ee100000 { compatible = "renesas,sdhi-r8a7792", "renesas,rcar-gen2-sdhi"; reg = <0 0xee100000 0 0x328>; diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index 79baf06019f5..abf487e8fe0f 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -334,9 +334,8 @@ composite-in@20 { compatible = "adi,adv7180cp"; reg = <0x20>; - remote = <&vin1>; - port { + ports { #address-cells = <1>; #size-cells = <0>; @@ -394,7 +393,7 @@ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; default-input = <0>; - port { + ports { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 1b62a7e06b42..6d507091b163 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -1227,7 +1227,7 @@ dma-channels = <13>; }; - sdhi0: sd@ee100000 { + sdhi0: mmc@ee100000 { compatible = "renesas,sdhi-r8a7793", "renesas,rcar-gen2-sdhi"; reg = <0 0xee100000 0 0x328>; @@ -1242,7 +1242,7 @@ status = "disabled"; }; - sdhi1: sd@ee140000 { + sdhi1: mmc@ee140000 { compatible = "renesas,sdhi-r8a7793", "renesas,rcar-gen2-sdhi"; reg = <0 0xee140000 0 0x100>; @@ -1257,7 +1257,7 @@ status = "disabled"; }; - sdhi2: sd@ee160000 { + sdhi2: mmc@ee160000 { compatible = "renesas,sdhi-r8a7793", "renesas,rcar-gen2-sdhi"; reg = <0 0xee160000 0 0x100>; diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 935935c1dbac..3f1cc5bbf329 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -167,7 +167,6 @@ composite-in@20 { compatible = "adi,adv7180"; reg = <0x20>; - remote = <&vin0>; port { adv7180: endpoint { diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index b8b0941f677c..677596f6c9c9 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -236,7 +236,6 @@ composite-in@20 { compatible = "adi,adv7180"; reg = <0x20>; - remote = <&vin0>; port { adv7180: endpoint { diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 8d7f8798628a..5f340397ab64 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -1232,7 +1232,7 @@ }; }; - sdhi0: sd@ee100000 { + sdhi0: mmc@ee100000 { compatible = "renesas,sdhi-r8a7794", "renesas,rcar-gen2-sdhi"; reg = <0 0xee100000 0 0x328>; @@ -1247,7 +1247,7 @@ status = "disabled"; }; - sdhi1: sd@ee140000 { + sdhi1: mmc@ee140000 { compatible = "renesas,sdhi-r8a7794", "renesas,rcar-gen2-sdhi"; reg = <0 0xee140000 0 0x100>; @@ -1262,7 +1262,7 @@ status = "disabled"; }; - sdhi2: sd@ee160000 { + sdhi2: mmc@ee160000 { compatible = "renesas,sdhi-r8a7794", "renesas,rcar-gen2-sdhi"; reg = <0 0xee160000 0 0x100>; diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 4c1ab49c7d39..ee59cc84f212 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -174,7 +174,7 @@ }; gic: interrupt-controller@44101000 { - compatible = "arm,cortex-a7-gic", "arm,gic-400"; + compatible = "arm,gic-400", "arm,cortex-a7-gic"; interrupt-controller; #interrupt-cells = <3>; reg = <0x44101000 0x1000>, /* Distributer */ diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index d9a0c9a29b68..093567022386 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -67,6 +67,7 @@ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMAC2>; clock-names = "apb_pclk"; }; diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index b0fd92befdeb..48e6e8d44a1a 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -107,6 +107,7 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMAC>; clock-names = "apb_pclk"; }; @@ -520,9 +521,9 @@ resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; + pinctrl-0 = <&otp_pin>; pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; + pinctrl-2 = <&otp_pin>; #thermal-sensor-cells = <0>; rockchip,hw-tshut-temp = <95000>; status = "disabled"; @@ -1111,7 +1112,7 @@ }; tsadc { - otp_gpio: otp-gpio { + otp_pin: otp-pin { rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; diff --git a/arch/arm/boot/dts/rk3288-rock-pi-n8.dts b/arch/arm/boot/dts/rk3288-rock-pi-n8.dts new file mode 100644 index 000000000000..b19593021713 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-rock-pi-n8.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Vamrs Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +/dts-v1/; +#include "rk3288.dtsi" +#include <arm/rockchip-radxa-dalang-carrier.dtsi> +#include "rk3288-vmarc-som.dtsi" + +/ { + model = "Radxa ROCK Pi N8"; + compatible = "radxa,rockpi-n8", "vamrs,rk3288-vmarc-som", + "rockchip,rk3288"; +}; diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts index 171ba6185b6d..af77ab20586d 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts @@ -44,10 +44,25 @@ }; }; +&sdio0 { + #address-cells = <1>; + #size-cells = <0>; + + btmrvl: btmrvl@2 { + compatible = "marvell,sd8897-bt"; + reg = <2>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PD7 IRQ_TYPE_LEVEL_LOW>; + marvell,wakeup-pin = /bits/ 16 <13>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l>; + }; +}; + &sdmmc { disable-wp; pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin &sdmmc_bus4>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts index 66f00d28801a..2c916c50dda5 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts @@ -192,7 +192,7 @@ &sdmmc { disable-wp; pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin &sdmmc_bus4>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-mighty.dts b/arch/arm/boot/dts/rk3288-veyron-mighty.dts index 27fbc07476d2..fa695a88f236 100644 --- a/arch/arm/boot/dts/rk3288-veyron-mighty.dts +++ b/arch/arm/boot/dts/rk3288-veyron-mighty.dts @@ -18,8 +18,8 @@ }; &sdmmc { - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_wp_gpio &sdmmc_bus4>; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin + &sdmmc_wp_pin &sdmmc_bus4>; wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>; /delete-property/ disable-wp; @@ -27,7 +27,7 @@ &pinctrl { sdmmc { - sdmmc_wp_gpio: sdmmc-wp-gpio { + sdmmc_wp_pin: sdmmc-wp-pin { rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index 383fad1a88a1..f8b69e0a16a0 100644 --- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts @@ -114,7 +114,7 @@ &sdmmc { disable-wp; pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin &sdmmc_bus4>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts index 71e6629cc208..4e9fdb0f722d 100644 --- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts +++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts @@ -105,7 +105,7 @@ }; sdmmc { - sdmmc_wp_gpio: sdmmc-wp-gpio { + sdmmc_wp_pin: sdmmc-wp-pin { rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; }; }; @@ -126,8 +126,8 @@ &sdmmc { pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_wp_gpio &sdmmc_bus4>; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin + &sdmmc_wp_pin &sdmmc_bus4>; wp-gpios = <&gpio7 RK_PB2 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi index fe950f9863e8..27fb06ce907e 100644 --- a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi @@ -41,7 +41,7 @@ }; /* This is where we actually hook up CD */ - sdmmc_cd_gpio: sdmmc-cd-gpio { + sdmmc_cd_pin: sdmmc-cd-pin { rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts index e354c61a45e7..4a3ea934d03e 100644 --- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts +++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts @@ -54,7 +54,7 @@ &sdmmc { disable-wp; pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin &sdmmc_bus4>; }; diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi new file mode 100644 index 000000000000..4a373f5aa600 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Vamrs Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> + +/ { + compatible = "vamrs,rk3288-vmarc-som", "rockchip,rk3288"; + + vccio_flash: vccio-flash-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_flash"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vccio_flash>; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + phy-supply = <&vcc_io>; + snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec_c0>; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vcc_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1400000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-ramp-delay = <6000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_tp: LDO_REG1 { + regulator-name = "vcc_tp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_codec: LDO_REG2 { + regulator-name = "vcca_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_wl: LDO_REG4 { + regulator-name = "vcc_wl"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-name = "vdd10_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_18: LDO_REG7 { + regulator-name = "vcc_18"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_lcd: LDO_REG8 { + regulator-name = "vcc18_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_sd: SWITCH_REG1 { + regulator-name = "vcc_sd"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_lcd: SWITCH_REG2 { + regulator-name = "vcc_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&io_domains { + bb-supply = <&vcc_io>; + flash0-supply = <&vccio_flash>; + gpio1830-supply = <&vcc_18>; + gpio30-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + status = "okay"; +}; + +&pinctrl { + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; + }; + }; + + vbus_host { + usb1_en_oc: usb1-en-oc { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + vbus_typec { + usb0_en_oc: usb0-en-oc { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&vbus_host { + enable-active-high; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; /* USB1_EN_OC# */ +}; + +&vbus_typec { + enable-active-high; + gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; /* USB0_EN_OC# */ +}; diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts index 385dd59393e1..1a20854a1317 100644 --- a/arch/arm/boot/dts/rk3288-vyasa.dts +++ b/arch/arm/boot/dts/rk3288-vyasa.dts @@ -99,8 +99,6 @@ pinctrl-0 = <&otg_vbus_drv>; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; vin-supply = <&vsus_5v>; }; @@ -416,6 +414,7 @@ }; &usb_otg { + vbus-supply = <&vusb1_5v>; status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 2e1edd85f04a..68d5a58cfe88 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -167,6 +167,7 @@ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMAC2>; clock-names = "apb_pclk"; }; @@ -178,6 +179,7 @@ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMAC1>; clock-names = "apb_pclk"; status = "disabled"; @@ -190,6 +192,7 @@ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMAC1>; clock-names = "apb_pclk"; }; @@ -574,9 +577,9 @@ resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; + pinctrl-0 = <&otp_pin>; pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; + pinctrl-2 = <&otp_pin>; #thermal-sensor-cells = <1>; rockchip,grf = <&grf>; rockchip,hw-tshut-temp = <95000>; @@ -613,7 +616,16 @@ status = "disabled"; }; - /* NOTE: ohci@ff520000 doesn't actually work on hardware */ + /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */ + usb_host0_ohci: usb@ff520000 { + compatible = "generic-ohci"; + reg = <0x0 0xff520000 0x0 0x100>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_USBHOST0>; + phys = <&usbphy1>; + phy-names = "usb"; + status = "disabled"; + }; usb_host1: usb@ff540000 { compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", @@ -1929,7 +1941,7 @@ }; tsadc { - otp_gpio: otp-gpio { + otp_pin: otp-pin { rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index d929b60517ab..859a7477909f 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -45,6 +45,7 @@ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMA1>; clock-names = "apb_pclk"; }; @@ -56,6 +57,7 @@ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMA1>; clock-names = "apb_pclk"; status = "disabled"; @@ -68,6 +70,7 @@ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMA2>; clock-names = "apb_pclk"; }; diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi index df3712aedf8a..26b53eac4706 100644 --- a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi +++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi @@ -8,36 +8,66 @@ #include <dt-bindings/pwm/pwm.h> / { - chosen { - stdout-path = "serial2:1500000n8"; + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; }; -}; -&gmac { - status = "okay"; + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vbus_host: vbus-host { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_en_oc>; + regulator-name = "vbus_host"; /* HOST-5V */ + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vbus_typec: vbus-typec { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_en_oc>; + regulator-name = "vbus_typec"; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; }; -&i2c1 { +&gmac { + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; status = "okay"; - i2c-scl-rising-time-ns = <140>; - i2c-scl-falling-time-ns = <30>; }; -&i2c2 { +&hdmi { status = "okay"; - clock-frequency = <400000>; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio4>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - }; }; &pwm0 { @@ -52,10 +82,8 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; disable-wp; vqmmc-supply = <&vccio_sd>; - max-frequency = <150000000>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; status = "okay"; @@ -71,11 +99,18 @@ status = "okay"; }; -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = - <4 RK_PD6 0 &pcfg_pull_up>; - }; - }; +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; }; diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index f9cfe2c80791..a1a08cb9364e 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -97,6 +97,7 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMAC>; clock-names = "apb_pclk"; }; @@ -351,9 +352,9 @@ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; clock-names = "tsadc", "apb_pclk"; pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; + pinctrl-0 = <&otp_pin>; pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; + pinctrl-2 = <&otp_pin>; resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; rockchip,hw-tshut-temp = <120000>; @@ -728,7 +729,7 @@ <0 RK_PC6 3 &pcfg_pull_none>; }; - i2c2m1_gpio: i2c2m1-gpio { + i2c2m1_pins: i2c2m1-pins { rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; }; @@ -740,7 +741,7 @@ <1 RK_PD4 2 &pcfg_pull_none>; }; - i2c2m05v_gpio: i2c2m05v-gpio { + i2c2m05v_pins: i2c2m05v-pins { rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; }; @@ -867,7 +868,7 @@ rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; }; - otp_gpio: otp-gpio { + otp_pin: otp-pin { rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -886,7 +887,7 @@ rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; }; - uart0_rts_gpio: uart0-rts-gpio { + uart0_rts_pin: uart0-rts-pin { rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index cf858029292e..822207f63ee0 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -69,6 +69,18 @@ pinctrl-0 = <&touchkey_vdd_ena>; }; + gp2a_vled: regulator-fixed-2 { + compatible = "regulator-fixed"; + regulator-name = "VLED"; + enable-active-high; + gpio = <&gpj1 4 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gp2a_power>; + }; + wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpg1 2 GPIO_ACTIVE_LOW>; @@ -137,9 +149,13 @@ pinctrl-names = "default"; pinctrl-0 = <&accel_i2c_pins>; - status = "disabled"; + accelerometer@38 { + compatible = "bosch,bma023"; + reg = <0x38>; - /* bma023 accelerometer, no mainline binding */ + vdd-supply = <&ldo9_reg>; + vddio-supply = <&ldo9_reg>; + }; }; i2c_pmic: i2c-gpio-2 { @@ -425,10 +441,8 @@ pinctrl-names = "default"; pinctrl-0 = <&fg_i2c_pins>; - fuelgauge@36 { + fg: fuelgauge@36 { compatible = "maxim,max17040"; - interrupt-parent = <&vic0>; - interrupts = <7>; reg = <0x36>; }; }; @@ -470,9 +484,21 @@ pinctrl-names = "default"; pinctrl-0 = <&prox_i2c_pins>; - status = "disabled"; + light-sensor@44 { + compatible = "sharp,gp2ap002a00f"; + reg = <0x44>; + interrupt-parent = <&gph0>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&gp2a_vled>; + vio-supply = <&gp2a_vled>; + io-channels = <&gp2a_shunt>; + io-channel-names = "alsout"; + sharp,proximity-far-hysteresis = /bits/ 8 <0x40>; + sharp,proximity-close-hysteresis = /bits/ 8 <0x20>; - /* Sharp gp2a prox/light sensor, incomplete mainline binding */ + pinctrl-names = "default"; + pinctrl-0 = <&gp2a_irq>; + }; }; i2c_magnetometer: i2c-gpio-7 { @@ -545,6 +571,14 @@ vdd-supply = <&ldo4_reg>; status = "okay"; + + gp2a_shunt: current-sense-shunt { + compatible = "current-sense-shunt"; + io-channels = <&adc 9>; + shunt-resistor-micro-ohms = <47000000>; /* 47 ohms */ + #io-channel-cells = <0>; + io-channel-ranges; + }; }; &fimd { @@ -595,6 +629,13 @@ }; &pinctrl0 { + bt_reset: bt-reset { + samsung,pins = "gpb-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + wlan_bt_en: wlan-bt-en { samsung,pins = "gpb-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; @@ -620,6 +661,19 @@ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; + bt_wake: bt-wake { + samsung,pins = "gpg3-4"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + }; + + gp2a_irq: gp2a-irq { + samsung,pins = "gph0-2"; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + pmic_dvs_pins: pmic-dvs-pins { samsung,pins = "gph0-3", "gph0-4", "gph0-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; @@ -688,6 +742,13 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; + gp2a_power: gp2a-power { + samsung,pins = "gpj1-4"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + touchkey_i2c_pins: touchkey-i2c-pins { samsung,pins = "gpj3-0", "gpj3-1"; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; @@ -797,16 +858,23 @@ }; &uart0 { + assigned-clocks = <&clocks MOUT_UART0>, <&clocks SCLK_UART0>; + assigned-clock-rates = <0>, <111166667>; + assigned-clock-parents = <&clocks MOUT_MPLL>; + status = "okay"; bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <115200>; + compatible = "brcm,bcm4329-bt"; + max-speed = <3000000>; pinctrl-names = "default"; - pinctrl-0 = <&uart0_data &uart0_fctl &bt_host_wake>; + pinctrl-0 = <&uart0_data &uart0_fctl &bt_host_wake + &bt_reset &bt_wake>; shutdown-gpios = <&gpb 3 GPIO_ACTIVE_HIGH>; device-wakeup-gpios = <&gpg3 4 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gph2 5 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gph2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; }; }; diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/s5pv210-fascinate4g.dts index 5e1b81823a8d..65eed01cfced 100644 --- a/arch/arm/boot/dts/s5pv210-fascinate4g.dts +++ b/arch/arm/boot/dts/s5pv210-fascinate4g.dts @@ -37,10 +37,27 @@ }; }; +&fg { + compatible = "maxim,max77836-battery"; + + interrupt-parent = <&gph3>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&fg_irq>; +}; + &pinctrl0 { pinctrl-names = "default"; pinctrl-0 = <&sleep_cfg>; + fg_irq: fg-irq { + samsung,pins = "gph3-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + /* Based on vendor kernel v2.6.35.7 */ sleep_cfg: sleep-cfg { PIN_SLP(gpa0-0, PREV, NONE); diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi index 5e8b66281f01..b8c5172c31dd 100644 --- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi +++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi @@ -273,6 +273,8 @@ gph3: gph3 { gpio-controller; #gpio-cells = <2>; + + interrupt-controller; #interrupt-cells = <2>; }; diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index 6763423d64b8..d10843da4a85 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -661,6 +661,13 @@ status = "disabled"; }; + rtt: rtt@fffffe20 { + compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; + reg = <0xfffffe20 0x20>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k 0>; + }; + pit: timer@fffffe40 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe40 0x10>; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 31d8766ec7ef..d7f25706892d 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -375,23 +375,23 @@ }; tcb0: timer@f800c000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; #address-cells = <1>; #size-cells = <0>; reg = <0xf800c000 0x100>; interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>; + clock-names = "t0_clk", "gclk", "slow_clk"; }; tcb1: timer@f8010000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; #address-cells = <1>; #size-cells = <0>; reg = <0xf8010000 0x100>; interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>; + clock-names = "t0_clk", "gclk", "slow_clk"; }; hsmc: hsmc@f8014000 { diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 01fd06328420..a4d63125ac56 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -321,7 +321,7 @@ status = "disabled"; }; - sdhi0: sd@ee100000 { + sdhi0: mmc@ee100000 { compatible = "renesas,sdhi-sh73a0"; reg = <0xee100000 0x100>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, @@ -334,7 +334,7 @@ }; /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ - sdhi1: sd@ee120000 { + sdhi1: mmc@ee120000 { compatible = "renesas,sdhi-sh73a0"; reg = <0xee120000 0x100>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, @@ -346,7 +346,7 @@ status = "disabled"; }; - sdhi2: sd@ee140000 { + sdhi2: mmc@ee140000 { compatible = "renesas,sdhi-sh73a0"; reg = <0xee140000 0x100>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, @@ -584,6 +584,7 @@ compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2"; reg = <0xec230000 0x400>; interrupts = <GIC_SPI 146 0x4>; + clocks = <&mstp3_clks SH73A0_CLK_FSI>; power-domains = <&pd_a4mp>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index c2b54af417a2..0b021eef0b53 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -726,7 +726,7 @@ }; }; - L2: l2-cache@fffef000 { + L2: cache-controller@fffef000 { compatible = "arm,pl310-cache"; reg = <0xfffef000 0x1000>; interrupts = <0 38 0x04>; @@ -829,6 +829,7 @@ num-cs = <4>; clocks = <&spi_m_clk>; resets = <&rst SPIM0_RESET>; + reset-names = "spi"; status = "disabled"; }; @@ -841,6 +842,7 @@ num-cs = <4>; clocks = <&spi_m_clk>; resets = <&rst SPIM1_RESET>; + reset-names = "spi"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 3b8571b8b412..fc4abef143a0 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -613,6 +613,7 @@ /*32bit_access;*/ clocks = <&spi_m_clk>; resets = <&rst SPIM0_RESET>; + reset-names = "spi"; status = "disabled"; }; @@ -628,6 +629,7 @@ rx-dma-channel = <&pdma 17>; clocks = <&spi_m_clk>; resets = <&rst SPIM1_RESET>; + reset-names = "spi"; status = "disabled"; }; @@ -636,7 +638,7 @@ reg = <0xffcfb100 0x80>; }; - L2: l2-cache@fffff000 { + L2: cache-controller@fffff000 { compatible = "arm,pl310-cache"; reg = <0xfffff000 0x1000>; interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 0efbeccc5cd2..7edebe20e859 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -162,6 +162,11 @@ compatible = "ltc2977"; reg = <0x5c>; }; + + temp@4c { + compatible = "maxim,max1619"; + reg = <0x4c>; + }; }; &uart1 { diff --git a/arch/arm/boot/dts/ste-ab8500.dtsi b/arch/arm/boot/dts/ste-ab8500.dtsi index 3cd6ee6d50e0..aab5719cc1a9 100644 --- a/arch/arm/boot/dts/ste-ab8500.dtsi +++ b/arch/arm/boot/dts/ste-ab8500.dtsi @@ -201,7 +201,19 @@ compatible = "stericsson,ab8500-sysctrl"; }; - ab8500-pwm { + ab8500-pwm-1 { + compatible = "stericsson,ab8500-pwm"; + clocks = <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "intclk"; + }; + + ab8500-pwm-2 { + compatible = "stericsson,ab8500-pwm"; + clocks = <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "intclk"; + }; + + ab8500-pwm-3 { compatible = "stericsson,ab8500-pwm"; clocks = <&ab8500_clock AB8500_SYSCLK_INT>; clock-names = "intclk"; diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 3e10da3f8fd3..05fd544b06c1 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -260,7 +260,7 @@ reg = <0x80150000 0x2000>; }; - L2: l2-cache { + L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0xa0412000 0x1000>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index f78b4eabd68c..4f38aeecadb3 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -15,7 +15,7 @@ <0x08000000 0x04000000>; }; - L2: l2-cache { + L2: cache-controller { compatible = "arm,l210-cache"; reg = <0x10210000 0x1000>; interrupt-parent = <&vica>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts index 5b499c0b2745..1e26b711d43d 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts @@ -24,6 +24,32 @@ stdout-path = &serial2; }; + i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio2 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio2 13 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_0_default>; + + #address-cells = <1>; + #size-cells = <0>; + + touchkey@20 { + compatible = "coreriver,tc360-touchkey"; + reg = <0x20>; + vdd-supply = <&ab8500_ldo_aux4_reg>; + vcc-supply = <&ab8500_ldo_aux6_reg>; + + interrupt-parent = <&gpio2>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_default>; + linux,keycodes = <KEY_MENU KEY_BACK>; + }; + }; + i2c-gpio-1 { compatible = "i2c-gpio"; sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; @@ -403,6 +429,16 @@ }; }; + i2c-gpio-0 { + i2c_gpio_0_default: i2c_gpio_0 { + golden_cfg1 { + pins = "GPIO77", /* TOUCHKEY_SCL */ + "GPIO78"; /* TOUCHKEY_SDA */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + i2c-gpio-1 { i2c_gpio_1_default: i2c_gpio_1 { golden_cfg1 { @@ -413,6 +449,15 @@ }; }; + touchkey { + touchkey_default: touchkey_default { + golden_cfg1 { + pins = "GPIO79"; /* TOUCHKEY_INT */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + sdi0 { sd_level_translator_default: sd_level_translator_default { golden_cfg1 { diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts index 8edef161613a..d6f6ac04a48a 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -349,8 +349,8 @@ interrupt-parent = <&gpio7>; interrupts = <0 IRQ_TYPE_EDGE_RISING>; - mount-matrix = "0", "1", "0", - "-1", "0", "0", + mount-matrix = "0", "-1", "0", + "1", "0", "0", "0", "0", "1"; vdd-supply = <&ab8500_ldo_aux1_reg>; vddio-supply = <&ab8500_ldo_aux8_reg>; diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index c27fa355e5ab..67e7648de41e 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -104,17 +104,17 @@ leds { compatible = "gpio-leds"; - green { + led-green { gpios = <&gpiog 6 1>; linux,default-trigger = "heartbeat"; }; - orange { + led-orange { gpios = <&gpiog 7 1>; }; - red { + led-red { gpios = <&gpiog 10 1>; }; - blue { + led-blue { gpios = <&gpiog 12 1>; }; }; @@ -240,7 +240,7 @@ <dc { status = "okay"; - pinctrl-0 = <<dc_pins>; + pinctrl-0 = <<dc_pins_a>; pinctrl-names = "default"; port { diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts index 4ea3f98dd275..ca8c192449ee 100644 --- a/arch/arm/boot/dts/stm32746g-eval.dts +++ b/arch/arm/boot/dts/stm32746g-eval.dts @@ -66,17 +66,17 @@ leds { compatible = "gpio-leds"; - green { + led-green { gpios = <&gpiof 10 1>; linux,default-trigger = "heartbeat"; }; - orange { + led-orange { gpios = <&stmfx_pinctrl 17 1>; }; - red { + led-red { gpios = <&gpiob 7 1>; }; - blue { + led-blue { gpios = <&stmfx_pinctrl 19 1>; }; }; diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 392fa143ce07..4774163af54b 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -257,7 +257,7 @@ }; }; - pwm1_pins: pwm-1 { + pwm1_pins: pwm1-0 { pins { pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */ <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */ @@ -265,7 +265,7 @@ }; }; - pwm3_pins: pwm-3 { + pwm3_pins: pwm3-0 { pins { pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */ <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */ @@ -282,7 +282,7 @@ }; }; - ltdc_pins: ltdc-0 { + ltdc_pins_a: ltdc-0 { pins { pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */ @@ -316,6 +316,85 @@ }; }; + ltdc_pins_b: ltdc-1 { + pins { + pinmux = <STM32_PINMUX('C', 6, AF14)>, + /* LCD_HSYNC */ + <STM32_PINMUX('A', 4, AF14)>, + /* LCD_VSYNC */ + <STM32_PINMUX('G', 7, AF14)>, + /* LCD_CLK */ + <STM32_PINMUX('C', 10, AF14)>, + /* LCD_R2 */ + <STM32_PINMUX('B', 0, AF9)>, + /* LCD_R3 */ + <STM32_PINMUX('A', 11, AF14)>, + /* LCD_R4 */ + <STM32_PINMUX('A', 12, AF14)>, + /* LCD_R5 */ + <STM32_PINMUX('B', 1, AF9)>, + /* LCD_R6*/ + <STM32_PINMUX('G', 6, AF14)>, + /* LCD_R7 */ + <STM32_PINMUX('A', 6, AF14)>, + /* LCD_G2 */ + <STM32_PINMUX('G', 10, AF9)>, + /* LCD_G3 */ + <STM32_PINMUX('B', 10, AF14)>, + /* LCD_G4 */ + <STM32_PINMUX('D', 6, AF14)>, + /* LCD_B2 */ + <STM32_PINMUX('G', 11, AF14)>, + /* LCD_B3*/ + <STM32_PINMUX('B', 11, AF14)>, + /* LCD_G5 */ + <STM32_PINMUX('C', 7, AF14)>, + /* LCD_G6 */ + <STM32_PINMUX('D', 3, AF14)>, + /* LCD_G7 */ + <STM32_PINMUX('G', 12, AF9)>, + /* LCD_B4 */ + <STM32_PINMUX('A', 3, AF14)>, + /* LCD_B5 */ + <STM32_PINMUX('B', 8, AF14)>, + /* LCD_B6 */ + <STM32_PINMUX('B', 9, AF14)>, + /* LCD_B7 */ + <STM32_PINMUX('F', 10, AF14)>; + /* LCD_DE */ + slew-rate = <2>; + }; + }; + + spi5_pins: spi5-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 7, AF5)>, + /* SPI5_CLK */ + <STM32_PINMUX('F', 9, AF5)>; + /* SPI5_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 8, AF5)>; + /* SPI5_MISO */ + bias-disable; + }; + }; + + i2c3_pins: i2c3-0 { + pins { + pinmux = <STM32_PINMUX('C', 9, AF4)>, + /* I2C3_SDA */ + <STM32_PINMUX('A', 8, AF4)>; + /* I2C3_SCL */ + bias-disable; + drive-open-drain; + slew-rate = <3>; + }; + }; + dcmi_pins: dcmi-0 { pins { pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */ diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 30c0f6717871..3dc068b91ca1 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -49,6 +49,8 @@ #include "stm32f429.dtsi" #include "stm32f429-pinctrl.dtsi" #include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> / { model = "STMicroelectronics STM32F429i-DISCO board"; @@ -70,10 +72,10 @@ leds { compatible = "gpio-leds"; - red { + led-red { gpios = <&gpiog 14 0>; }; - green { + led-green { gpios = <&gpiog 13 0>; linux,default-trigger = "heartbeat"; }; @@ -108,12 +110,103 @@ status = "okay"; }; +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <100000>; + status = "okay"; + + stmpe811@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioa>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 7 length fractional part in z */ + st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + }; + + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; + }; +}; + +<dc { + status = "okay"; + pinctrl-0 = <<dc_pins_b>; + pinctrl-names = "default"; + + port { + ltdc_out_rgb: endpoint { + remote-endpoint = <&panel_in_rgb>; + }; + }; +}; + &rtc { assigned-clocks = <&rcc 1 CLK_RTC>; assigned-clock-parents = <&rcc 1 CLK_LSI>; status = "okay"; }; +&spi5 { + status = "okay"; + pinctrl-0 = <&spi5_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>, <&gpioc 2 GPIO_ACTIVE_LOW>; + + l3gd20: l3gd20@0 { + compatible = "st,l3gd20-gyro"; + spi-max-frequency = <10000000>; + st,drdy-int-pin = <2>; + interrupt-parent = <&gpioa>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>, + <2 IRQ_TYPE_EDGE_RISING>; + reg = <0>; + status = "okay"; + }; + + display: display@1{ + /* Connect panel-ilitek-9341 to ltdc */ + compatible = "st,sf-tc240t-9370-t"; + reg = <1>; + spi-3wire; + spi-max-frequency = <10000000>; + dc-gpios = <&gpiod 13 0>; + port { + panel_in_rgb: endpoint { + remote-endpoint = <<dc_out_rgb>; + }; + }; + }; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 393f43c85a3c..ad715a0e1c9a 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -322,7 +322,6 @@ assigned-clock-parents = <&rcc 1 CLK_LSE>; interrupt-parent = <&exti>; interrupts = <17 1>; - interrupt-names = "alarm"; st,syscfg = <&pwrcfg 0x00 0x100>; status = "disabled"; }; @@ -402,6 +401,18 @@ status = "disabled"; }; + i2c3: i2c@40005c00 { + compatible = "st,stm32f4-i2c"; + reg = <0x40005c00 0x400>; + interrupts = <72>, + <73>; + resets = <&rcc STM32F4_APB1_RESET(I2C3)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + dac: dac@40007400 { compatible = "st,stm32f4-dac-core"; reg = <0x40007400 0x400>; @@ -586,8 +597,8 @@ status = "disabled"; }; - syscfg: system-config@40013800 { - compatible = "syscon"; + syscfg: syscon@40013800 { + compatible = "st,stm32-syscfg", "syscon"; reg = <0x40013800 0x400>; }; @@ -660,6 +671,9 @@ reg = <0x40015000 0x400>; interrupts = <85>; clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>; + dmas = <&dma2 3 2 0x400 0x0>, + <&dma2 4 2 0x400 0x0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -674,7 +688,7 @@ }; pwrcfg: power-config@40007000 { - compatible = "syscon"; + compatible = "st,stm32-power-config", "syscon"; reg = <0x40007000 0x400>; }; diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts index 9397db0c43de..2e1b3bbbe4b5 100644 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ b/arch/arm/boot/dts/stm32f469-disco.dts @@ -89,17 +89,17 @@ leds { compatible = "gpio-leds"; - green { + led-green { gpios = <&gpiog 6 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; - orange { + led-orange { gpios = <&gpiod 4 GPIO_ACTIVE_LOW>; }; - red { + led-red { gpios = <&gpiod 5 GPIO_ACTIVE_LOW>; }; - blue { + led-blue { gpios = <&gpiok 3 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 93c063796780..640ff54ed00c 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -304,7 +304,6 @@ assigned-clock-parents = <&rcc 1 CLK_LSE>; interrupt-parent = <&exti>; interrupts = <17 1>; - interrupt-names = "alarm"; st,syscfg = <&pwrcfg 0x00 0x100>; status = "disabled"; }; @@ -496,8 +495,8 @@ status = "disabled"; }; - syscfg: system-config@40013800 { - compatible = "syscon"; + syscfg: syscon@40013800 { + compatible = "st,stm32-syscfg", "syscon"; reg = <0x40013800 0x400>; }; @@ -564,7 +563,7 @@ }; pwrcfg: power-config@40007000 { - compatible = "syscon"; + compatible = "st,stm32-power-config", "syscon"; reg = <0x40007000 0x400>; }; diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts index 1626e00bb2cb..0ce7fbc20fa4 100644 --- a/arch/arm/boot/dts/stm32f769-disco.dts +++ b/arch/arm/boot/dts/stm32f769-disco.dts @@ -66,11 +66,11 @@ leds { compatible = "gpio-leds"; - green { + led-green { gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - red { + led-red { gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi index e44e7baa3f17..fa5dcb6a5fdd 100644 --- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi @@ -163,7 +163,7 @@ #interrupt-cells = <2>; }; - i2c1_pins_a: i2c1@0 { + i2c1_pins_a: i2c1-0 { pins { pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */ <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */ @@ -173,7 +173,7 @@ }; }; - ethernet_rmii: rmii@0 { + ethernet_rmii: rmii-0 { pins { pinmux = <STM32_PINMUX('G', 11, AF11)>, <STM32_PINMUX('G', 13, AF11)>, @@ -256,7 +256,7 @@ }; }; - usart1_pins: usart1@0 { + usart1_pins: usart1-0 { pins1 { pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */ bias-disable; @@ -269,7 +269,7 @@ }; }; - usart2_pins: usart2@0 { + usart2_pins: usart2-0 { pins1 { pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */ bias-disable; @@ -282,7 +282,7 @@ }; }; - usbotg_hs_pins_a: usbotg-hs@0 { + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */ <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */ diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 9b7fc68380e9..69e2f1e78ed6 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -361,8 +361,8 @@ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>; }; - syscfg: system-config@58000400 { - compatible = "syscon"; + syscfg: syscon@58000400 { + compatible = "st,stm32-syscfg", "syscon"; reg = <0x58000400 0x400>; }; @@ -487,7 +487,6 @@ assigned-clock-parents = <&rcc LSE_CK>; interrupt-parent = <&exti>; interrupts = <17 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "alarm"; st,syscfg = <&pwrcfg 0x00 0x100>; status = "disabled"; }; @@ -502,7 +501,7 @@ }; pwrcfg: power-config@58024800 { - compatible = "syscon"; + compatible = "st,stm32-power-config", "syscon"; reg = <0x58024800 0x400>; }; diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 7eb858732d6d..b5a66429670c 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -210,8 +210,8 @@ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ - <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ - <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */ @@ -453,7 +453,7 @@ i2c5_pins_b: i2c5-1 { pins { pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */ - <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */ + <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */ bias-disable; drive-open-drain; slew-rate = <0>; @@ -463,7 +463,7 @@ i2c5_sleep_pins_b: i2c5-sleep-1 { pins { pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */ - <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */ + <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */ }; }; @@ -1072,7 +1072,6 @@ }; }; - sai2a_pins_b: sai2a-1 { pins1 { pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ @@ -1574,6 +1573,147 @@ }; }; + uart4_pins_a: uart4-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_idle_pins_a: uart4-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_sleep_pins_a: uart4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */ + <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ + }; + }; + + uart4_pins_b: uart4-1 { + pins1 { + pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_pins_c: uart4-2 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart7_pins_a: uart7-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */ + <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */ + <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */ + bias-disable; + }; + }; + + uart7_pins_b: uart7-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */ + bias-disable; + }; + }; + + uart7_pins_c: uart7-2 { + pins1 { + pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ + bias-disable; + }; + }; + + uart7_idle_pins_c: uart7-idle-2 { + pins1 { + pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ + bias-disable; + }; + }; + + uart7_sleep_pins_c: uart7-sleep-2 { + pins { + pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */ + <STM32_PINMUX('E', 7, ANALOG)>; /* UART7_RX */ + }; + }; + + uart8_pins_a: uart8-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */ + bias-disable; + }; + }; + + spi4_pins_a: spi4-0 { + pins { + pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */ + <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */ + bias-disable; + }; + }; + usart2_pins_a: usart2-0 { pins1 { pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ @@ -1622,99 +1762,127 @@ }; }; - usart3_pins_a: usart3-0 { + usart2_pins_c: usart2-2 { pins1 { - pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ + pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */ + <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ bias-disable; drive-push-pull; - slew-rate = <0>; + slew-rate = <3>; }; pins2 { - pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ + pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ + <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ bias-disable; }; }; - uart4_pins_a: uart4-0 { + usart2_idle_pins_c: usart2-idle-2 { pins1 { - pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; + pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ + <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ }; pins2 { - pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */ bias-disable; }; }; - uart4_pins_b: uart4-1 { + usart2_sleep_pins_c: usart2-sleep-2 { + pins { + pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ + <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ + <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ + }; + }; + + usart3_pins_a: usart3-0 { pins1 { - pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */ + pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ bias-disable; }; }; - uart4_pins_c: uart4-2 { + usart3_pins_b: usart3-1 { pins1 { - pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ + pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ + <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */ bias-disable; }; }; - uart7_pins_a: uart7-0 { + usart3_idle_pins_b: usart3-idle-1 { pins1 { - pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; + pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ + <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */ }; pins2 { - pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */ - <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */ - <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */ + pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ bias-disable; }; }; - uart7_pins_b: uart7-1 { + usart3_sleep_pins_b: usart3-sleep-1 { + pins { + pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ + <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */ + <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ + }; + }; + + usart3_pins_c: usart3-2 { pins1 { - pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */ + pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */ + pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ + <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */ bias-disable; }; }; - uart8_pins_a: uart8-0 { + usart3_idle_pins_c: usart3-idle-2 { pins1 { - pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; + pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ + <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */ }; pins2 { - pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */ + pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ bias-disable; }; }; + usart3_sleep_pins_c: usart3-sleep-2 { + pins { + pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ + <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */ + <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ + }; + }; + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ @@ -1776,18 +1944,4 @@ bias-disable; }; }; - - spi4_pins_a: spi4-0 { - pins { - pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */ - <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - pins2 { - pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */ - bias-disable; - }; - }; }; diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 36f38a95b4de..bfe29023fbd5 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1127,7 +1127,7 @@ }; pwr_mcu: pwr_mcu@50001014 { - compatible = "syscon"; + compatible = "st,stm32mp151-pwr-mcu", "syscon"; reg = <0x50001014 0x4>; }; @@ -1331,6 +1331,8 @@ dma-names = "tx", "rx"; clocks = <&rcc QSPI_K>; resets = <&rcc QSPI_R>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts index d03d4cd2606a..4c8be9c8eb20 100644 --- a/arch/arm/boot/dts/stm32mp157a-dk1.dts +++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts @@ -18,6 +18,8 @@ aliases { ethernet0 = ðernet0; serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart7; }; chosen { diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts index 9a8a26710ac1..045636555ddd 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts @@ -19,6 +19,9 @@ aliases { ethernet0 = ðernet0; serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart7; + serial3 = &usart2; }; chosen { @@ -84,3 +87,11 @@ }; }; }; + +&usart2 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_c>; + pinctrl-1 = <&usart2_sleep_pins_c>; + pinctrl-2 = <&usart2_idle_pins_c>; + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 32ccd50b4144..ca109dc18238 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -353,8 +353,10 @@ }; &uart4 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index b19056557ef0..85628e16d2d5 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -19,6 +19,7 @@ aliases { serial0 = &uart4; + serial1 = &usart3; ethernet0 = ðernet0; }; @@ -341,6 +342,20 @@ }; }; +&usart3 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart3_pins_b>; + pinctrl-1 = <&usart3_sleep_pins_b>; + pinctrl-2 = <&usart3_idle_pins_b>; + /* + * HW flow control USART3_RTS is optional, and isn't default wired to + * the connector. SB23 needs to be soldered in order to use it, and R77 + * (ETH_CLK) should be removed. + */ + uart-has-rtscts; + status = "disabled"; +}; + &usbh_ehci { phys = <&usbphyc_port0>; status = "okay"; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 70db923a45f7..a5307745719a 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -62,7 +62,7 @@ led { compatible = "gpio-leds"; - blue { + led-blue { label = "heartbeat"; gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -365,6 +365,19 @@ }; }; +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_a>; + pinctrl-1 = <&i2c5_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <400000>; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; +}; + &i2s2 { clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; clock-names = "pclk", "i2sclk", "x8k", "x11k"; @@ -584,20 +597,39 @@ }; &uart4 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; status = "okay"; }; +&uart7 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart7_pins_c>; + pinctrl-1 = <&uart7_sleep_pins_c>; + pinctrl-2 = <&uart7_idle_pins_c>; + status = "disabled"; +}; + +&usart3 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart3_pins_c>; + pinctrl-1 = <&usart3_sleep_pins_c>; + pinctrl-2 = <&usart3_idle_pins_c>; + uart-has-rtscts; + status = "disabled"; +}; + &usbh_ehci { phys = <&usbphyc_port0>; status = "okay"; }; &usbotg_hs { - dr_mode = "peripheral"; phys = <&usbphyc_port1 0>; phy-names = "usb2-phy"; + usb-role-switch; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index bf531efc0610..0f95a6ef8543 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -198,7 +198,7 @@ default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; - alloc-ranges = <0x4a000000 0x6000000>; + alloc-ranges = <0x40000000 0x10000000>; reusable; linux,cma-default; }; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index e6b036734a64..c2b4fbf552a3 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -117,7 +117,7 @@ default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; - alloc-ranges = <0x4a000000 0x6000000>; + alloc-ranges = <0x40000000 0x10000000>; reusable; linux,cma-default; }; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index ffe1d10a1a84..6d6a37940db2 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -181,7 +181,7 @@ default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; - alloc-ranges = <0x4a000000 0x6000000>; + alloc-ranges = <0x40000000 0x10000000>; reusable; linux,cma-default; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts index b8f46e2802fd..251bbab7d707 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts @@ -70,6 +70,21 @@ }; }; + leds { + compatible = "gpio-leds"; + + pwr { + label = "orangepi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + status { + label = "orangepi:red:status"; + gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; + }; + }; + reg_vcc3v3: vcc3v3 { compatible = "regulator-fixed"; regulator-name = "vcc3v3"; @@ -88,6 +103,10 @@ status = "okay"; }; +&ehci0 { + status = "okay"; +}; + &hdmi { status = "okay"; }; @@ -132,8 +151,27 @@ status = "okay"; }; +&ohci0 { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pa_pins>; status = "okay"; }; + +&usb_otg { + /* + * According to schematics CN1 MicroUSB port can be used to take + * external 5V to power up the board VBUS. On the contrary CN1 MicroUSB + * port cannot provide power externally even if the board is powered + * via GPIO pins. It thus makes sense to force peripheral mode. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi index 22466afd38a3..235994a4a2eb 100644 --- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi +++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi @@ -16,15 +16,27 @@ regulator-type = "voltage"; regulator-boot-on; regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <1108475>; + regulator-max-microvolt = <1308475>; regulator-ramp-delay = <50>; /* 4ms */ gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */ gpios-states = <0x1>; - states = <1100000 0>, <1300000 1>; + states = <1108475 0>, <1308475 1>; }; }; &cpu0 { cpu-supply = <®_vdd_cpux>; }; + +&cpu1 { + cpu-supply = <®_vdd_cpux>; +}; + +&cpu2 { + cpu-supply = <®_vdd_cpux>; +}; + +&cpu3 { + cpu-supply = <®_vdd_cpux>; +}; diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi index 19b3b23cfaa8..c44fd726945a 100644 --- a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi +++ b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi @@ -128,6 +128,18 @@ cpu-supply = <®_vdd_cpux>; }; +&cpu1 { + cpu-supply = <®_vdd_cpux>; +}; + +&cpu2 { + cpu-supply = <®_vdd_cpux>; +}; + +&cpu3 { + cpu-supply = <®_vdd_cpux>; +}; + &de { status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 08be733ee2cd..c04162ddec3c 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -769,7 +769,6 @@ battery: smart-battery@b { compatible = "ti,bq20z45", "sbs,sbs-battery"; reg = <0xb>; - battery-name = "battery"; sbs,i2c-retry-count = <2>; sbs,poll-retry-count = <100>; power-supplies = <&charger>; @@ -1109,14 +1108,14 @@ }; }; - sdhci@78000400 { + mmc@78000400 { cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; status = "okay"; }; - sdhci@78000600 { + mmc@78000600 { bus-width = <8>; status = "okay"; non-removable; @@ -1152,17 +1151,10 @@ default-brightness-level = <6>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { @@ -1194,83 +1186,70 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_ac_bat_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_ac_bat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + vdd_ac_bat_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_ac_bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - dvdd_ts_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "dvdd_ts"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; - }; + dvdd_ts_reg: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "dvdd_ts"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; + }; - usb1_vbus_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&tps65090_dcdc1_reg>; - }; + usb1_vbus_reg: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&tps65090_dcdc1_reg>; + }; - usb3_vbus_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "usb2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&tps65090_dcdc1_reg>; - }; + usb3_vbus_reg: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&tps65090_dcdc1_reg>; + }; - vdd_hdmi_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "vdd_hdmi_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&tps65090_dcdc1_reg>; - }; + vdd_hdmi_reg: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "vdd_hdmi_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&tps65090_dcdc1_reg>; + }; - vdd_cam_1v8_reg: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "vdd_cam_1v8_reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&palmas_gpio 6 0>; - }; + vdd_cam_1v8_reg: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "vdd_cam_1v8_reg"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&palmas_gpio 6 0>; + }; - vdd_5v0_hdmi: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "VDD_5V0_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&tps65090_dcdc1_reg>; - }; + vdd_5v0_hdmi: regulator@7 { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&tps65090_dcdc1_reg>; }; sound { diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index 3d3835591cd2..07960171fabe 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -37,7 +37,7 @@ dsi@54300000 { status = "okay"; - vdd-supply = <&vdd_1v2_ap>; + avdd-dsi-csi-supply = <&vdd_1v2_ap>; panel@0 { compatible = "lg,lh500wx1-sd03"; @@ -962,7 +962,7 @@ }; /* SD card */ - sdhci@78000400 { + mmc@78000400 { status = "okay"; bus-width = <4>; vqmmc-supply = <&vddio_sdmmc3>; @@ -971,7 +971,7 @@ }; /* eMMC */ - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; @@ -1016,17 +1016,10 @@ enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { @@ -1052,76 +1045,64 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - lcd_bl_en: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "lcd_bl_en"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; + lcd_bl_en: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "lcd_bl_en"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; - vdd_lcd: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_lcd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vdd_1v8>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; + vdd_lcd: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_lcd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vdd_1v8>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_1v8_ts"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>; - regulator-boot-on; - }; + regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_ts"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>; + regulator-boot-on; + }; - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_3v3_ts"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; + regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_ts"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "vdd_1v8_com"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vdd_1v8>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; + regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_com"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vdd_1v8>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; - regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "vdd_3v3_com"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_sys>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; - regulator-always-on; - regulator-boot-on; - }; + regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_com"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_sys>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; }; }; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index bfdd1bf61816..745d234b105b 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -37,7 +37,7 @@ dsi@54300000 { status = "okay"; - vdd-supply = <&vdd_1v2_ap>; + avdd-dsi-csi-supply = <&vdd_1v2_ap>; panel@0 { compatible = "lg,ld070wx3-sl01"; @@ -242,7 +242,7 @@ }; /* eMMC */ - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; @@ -273,17 +273,10 @@ power-supply = <&lcd_bl_en>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { @@ -309,44 +302,35 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - /* FIXME: output of BQ24192 */ - vs_sys: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "VS_SYS"; - regulator-min-microvolt = <4200000>; - regulator-max-microvolt = <4200000>; - regulator-always-on; - regulator-boot-on; - }; + /* FIXME: output of BQ24192 */ + vs_sys: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "VS_SYS"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + regulator-boot-on; + }; - lcd_bl_en: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "VDD_LCD_BL"; - regulator-min-microvolt = <16500000>; - regulator-max-microvolt = <16500000>; - gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vs_sys>; - regulator-boot-on; - }; + lcd_bl_en: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VDD_LCD_BL"; + regulator-min-microvolt = <16500000>; + regulator-max-microvolt = <16500000>; + gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vs_sys>; + regulator-boot-on; + }; - vdd_lcd: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "VD_LCD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_1v8>; - regulator-boot-on; - }; + vdd_lcd: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "VD_LCD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_1v8>; + regulator-boot-on; }; }; diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 450a1f1b12a0..fb99b3e971c3 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -18,11 +18,13 @@ }; host1x@50000000 { - compatible = "nvidia,tegra114-host1x", "simple-bus"; + compatible = "nvidia,tegra114-host1x"; reg = <0x50000000 0x00028000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ + interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA114_CLK_HOST1X>; + clock-names = "host1x"; resets = <&tegra_car 28>; reset-names = "host1x"; iommus = <&mc TEGRA_SWGROUP_HC>; @@ -33,7 +35,7 @@ ranges = <0x54000000 0x54000000 0x01000000>; gr2d@54140000 { - compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d"; + compatible = "nvidia,tegra114-gr2d"; reg = <0x54140000 0x00040000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_GR2D>; @@ -44,7 +46,7 @@ }; gr3d@54180000 { - compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d"; + compatible = "nvidia,tegra114-gr3d"; reg = <0x54180000 0x00040000>; clocks = <&tegra_car TEGRA114_CLK_GR3D>; resets = <&tegra_car 24>; @@ -54,7 +56,7 @@ }; dc@54200000 { - compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra114-dc"; reg = <0x54200000 0x00040000>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_DISP1>, @@ -73,7 +75,7 @@ }; dc@54240000 { - compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra114-dc"; reg = <0x54240000 0x00040000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_DISP2>, @@ -253,14 +255,14 @@ apbmisc@70000800 { compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; - reg = <0x70000800 0x64 /* Chip revision */ - 0x70000008 0x04>; /* Strapping options */ + reg = <0x70000800 0x64>, /* Chip revision */ + <0x70000008 0x04>; /* Strapping options */ }; pinmux: pinmux@70000868 { compatible = "nvidia,tegra114-pinmux"; - reg = <0x70000868 0x148 /* Pad control registers */ - 0x70003000 0x40c>; /* Mux registers */ + reg = <0x70000868 0x148>, /* Pad control registers */ + <0x70003000 0x40c>; /* Mux registers */ }; /* @@ -644,41 +646,45 @@ #nvidia,mipi-calibrate-cells = <1>; }; - sdhci@78000000 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; + mmc@78000000 { + compatible = "nvidia,tegra114-sdhci"; reg = <0x78000000 0x200>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; + clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; status = "disabled"; }; - sdhci@78000200 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; + mmc@78000200 { + compatible = "nvidia,tegra114-sdhci"; reg = <0x78000200 0x200>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; + clock-names = "sdhci"; resets = <&tegra_car 9>; reset-names = "sdhci"; status = "disabled"; }; - sdhci@78000400 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; + mmc@78000400 { + compatible = "nvidia,tegra114-sdhci"; reg = <0x78000400 0x200>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; + clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; status = "disabled"; }; - sdhci@78000600 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; + mmc@78000600 { + compatible = "nvidia,tegra114-sdhci"; reg = <0x78000600 0x200>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; + clock-names = "sdhci"; resets = <&tegra_car 15>; reset-names = "sdhci"; status = "disabled"; @@ -698,7 +704,8 @@ phy1: usb-phy@7d000000 { compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x7d000000 0x4000 0x7d000000 0x4000>; + reg = <0x7d000000 0x4000>, + <0x7d000000 0x4000>; phy_type = "utmi"; clocks = <&tegra_car TEGRA114_CLK_USBD>, <&tegra_car TEGRA114_CLK_PLL_U>, @@ -706,6 +713,7 @@ clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 22>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; @@ -734,7 +742,8 @@ phy3: usb-phy@7d008000 { compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x7d008000 0x4000 0x7d000000 0x4000>; + reg = <0x7d008000 0x4000>, + <0x7d000000 0x4000>; phy_type = "utmi"; clocks = <&tegra_car TEGRA114_CLK_USB3>, <&tegra_car TEGRA114_CLK_PLL_U>, @@ -742,6 +751,7 @@ clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 59>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index ceb3f6388c7d..28c29b6813a7 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -130,7 +130,7 @@ }; /* Apalis MMC1 */ - sdhci@700b0000 { + mmc@700b0000 { status = "okay"; bus-width = <4>; /* MMC1_CD# */ @@ -139,7 +139,7 @@ }; /* Apalis SD1 */ - sdhci@700b0400 { + mmc@700b0400 { status = "okay"; bus-width = <4>; /* SD1_CD# */ diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts index 826b776fbe6f..f3afde410615 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -132,7 +132,7 @@ }; /* Apalis MMC1 */ - sdhci@700b0000 { + mmc@700b0000 { status = "okay"; bus-width = <4>; /* MMC1_CD# */ @@ -141,7 +141,7 @@ }; /* Apalis SD1 */ - sdhci@700b0400 { + mmc@700b0400 { status = "okay"; bus-width = <4>; /* SD1_CD# */ diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index de499f736bda..1e30fa405fa0 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -40,7 +40,7 @@ phy-names = "pcie-0"; status = "okay"; - pcie@0 { + ethernet@0,0 { reg = <0 0 0 0 0>; local-mac-address = [00 00 00 00 00 00]; }; @@ -1562,6 +1562,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_module_3v3_audio>; VDDD-supply = <®_1v8_vddio>; VDDIO-supply = <®_1v8_vddio>; @@ -1916,7 +1917,7 @@ }; /* eMMC */ - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index d70a86da4ee4..608896f8dd52 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -39,7 +39,7 @@ phy-names = "pcie-0"; status = "okay"; - pcie@0 { + ethernet@0,0 { reg = <0 0 0 0 0>; local-mac-address = [00 00 00 00 00 00]; }; @@ -1555,6 +1555,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_module_3v3_audio>; VDDD-supply = <®_1v8_vddio>; VDDIO-supply = <®_1v8_vddio>; @@ -1908,7 +1909,7 @@ }; /* eMMC */ - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 1b567e2d5ce0..414cd1cafa7f 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1782,6 +1782,12 @@ }; ports { + /* Micro A/B */ + usb2-0 { + status = "okay"; + mode = "host"; + }; + /* Mini PCIe */ usb2-1 { status = "okay"; @@ -1804,7 +1810,7 @@ }; /* SD card */ - sdhci@700b0400 { + mmc@700b0400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; @@ -1814,7 +1820,7 @@ }; /* eMMC */ - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; @@ -1862,17 +1868,10 @@ vbus-supply = <&vdd_usb3_vbus>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; cpus { @@ -1893,145 +1892,127 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_mux: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; + vdd_mux: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; + vdd_5v0_sys: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; + vdd_3v3_sys: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; - vdd_3v3_run: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; + vdd_3v3_run: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; - vdd_3v3_hdmi: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; + vdd_3v3_hdmi: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; - vdd_usb1_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "+USB0_VBUS_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_usb1_vbus: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "+USB0_VBUS_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_usb3_vbus: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_usb3_vbus: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_3v3_lp0: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "+3.3V_LP0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; + vdd_3v3_lp0: regulator@7 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; - vdd_hdmi_pll: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; + vdd_hdmi_pll: regulator@8 { + compatible = "regulator-fixed"; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; - vdd_5v0_hdmi: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_5v0_hdmi: regulator@9 { + compatible = "regulator-fixed"; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; - /* Molex power connector */ - vdd_5v0_sata: regulator@13 { - compatible = "regulator-fixed"; - reg = <13>; - regulator-name = "+5V_SATA"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; + /* Molex power connector */ + vdd_5v0_sata: regulator@10 { + compatible = "regulator-fixed"; + regulator-name = "+5V_SATA"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_12v0_sata: regulator@14 { - compatible = "regulator-fixed"; - reg = <14>; - regulator-name = "+12V_SATA"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; + vdd_12v0_sata: regulator@11 { + compatible = "regulator-fixed"; + regulator-name = "+12V_SATA"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; }; sound { diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts index d97791b98958..1d2aac2cb6d0 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big.dts +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts @@ -16,11 +16,12 @@ panel: panel { compatible = "auo,b133xtn01"; + power-supply = <&vdd_3v3_panel>; backlight = <&backlight>; ddc-i2c-bus = <&dpaux>; }; - sdhci@700b0400 { /* SD Card on this bus */ + mmc@700b0400 { /* SD Card on this bus */ wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts index 2a029ee86dd7..677babde6460 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze.dts +++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts @@ -18,6 +18,7 @@ panel: panel { compatible = "samsung,ltn140at29-301"; + power-supply = <&vdd_3v3_panel>; backlight = <&backlight>; ddc-i2c-bus = <&dpaux>; }; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 9b1af50cd4b8..5f71add38dfe 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -48,6 +48,9 @@ sor@54540000 { status = "okay"; + avdd-io-hdmi-dp-supply = <&vdd_3v3_hdmi>; + vdd-hdmi-dp-pll-supply = <&vdd_hdmi_pll>; + nvidia,dpaux = <&dpaux>; nvidia,panel = <&panel>; }; @@ -495,7 +498,7 @@ reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; }; - sdhci@700b0000 { /* WiFi/BT on this bus */ + mmc@700b0000 { /* WiFi/BT on this bus */ status = "okay"; bus-width = <4>; no-1-8-v; @@ -506,7 +509,7 @@ keep-power-in-suspend; }; - sdhci@700b0400 { /* SD Card on this bus */ + mmc@700b0400 { /* SD Card on this bus */ status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; @@ -515,7 +518,7 @@ vqmmc-supply = <&vddio_sdmmc3>; }; - sdhci@700b0600 { /* eMMC on this bus */ + mmc@700b0600 { /* eMMC on this bus */ status = "okay"; bus-width = <8>; no-1-8-v; @@ -579,17 +582,10 @@ 256>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; cpus { @@ -619,157 +615,138 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_mux: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; + vdd_mux: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; + vdd_5v0_sys: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; + vdd_3v3_sys: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; - vdd_3v3_run: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; + vdd_3v3_run: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; - vdd_3v3_hdmi: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; + vdd_3v3_hdmi: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; - vdd_led: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "+VDD_LED"; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; + vdd_led: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "+VDD_LED"; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; + }; - vdd_5v0_ts: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "+5V_VDD_TS_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_5v0_ts: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "+5V_VDD_TS_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_usb1_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_usb1_vbus: regulator@7 { + compatible = "regulator-fixed"; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_usb3_vbus: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+5V_USB_SS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_usb3_vbus: regulator@8 { + compatible = "regulator-fixed"; + regulator-name = "+5V_USB_SS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_3v3_panel: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "+3.3V_PANEL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_run>; - }; + vdd_3v3_panel: regulator@9 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_PANEL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_run>; + }; - vdd_3v3_lp0: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "+3.3V_LP0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* - * TODO: find a way to wire this up with the USB EHCI - * controllers so that it can be enabled on demand. - */ - regulator-always-on; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; + vdd_3v3_lp0: regulator@10 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* + * TODO: find a way to wire this up with the USB EHCI + * controllers so that it can be enabled on demand. + */ + regulator-always-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; - vdd_hdmi_pll: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; + vdd_hdmi_pll: regulator@11 { + compatible = "regulator-fixed"; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; - vdd_5v0_hdmi: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_5v0_hdmi: regulator@12 { + compatible = "regulator-fixed"; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; }; sound { diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 73361dbe2e43..e6b54ac1ebd1 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -1002,7 +1002,7 @@ }; }; - sdhci@700b0400 { + mmc@700b0400 { cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; @@ -1011,7 +1011,7 @@ vqmmc-supply = <&vddio_sdmmc3>; }; - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; @@ -1061,17 +1061,10 @@ default-brightness-level = <6>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { @@ -1088,164 +1081,145 @@ panel: panel { compatible = "lg,lp129qe"; - + power-supply = <&vdd_3v3_panel>; backlight = <&backlight>; ddc-i2c-bus = <&dpaux>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_mux: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; + vdd_mux: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; + vdd_5v0_sys: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; + vdd_3v3_sys: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; - vdd_3v3_run: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; + vdd_3v3_run: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; - vdd_3v3_hdmi: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; + vdd_3v3_hdmi: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; - vdd_led: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "+VDD_LED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; + vdd_led: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "+VDD_LED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; + }; - vdd_5v0_ts: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "+5V_VDD_TS_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_5v0_ts: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "+5V_VDD_TS_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_usb1_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_usb1_vbus: regulator@7 { + compatible = "regulator-fixed"; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_usb3_vbus: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+5V_USB_SS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_usb3_vbus: regulator@8 { + compatible = "regulator-fixed"; + regulator-name = "+5V_USB_SS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_3v3_panel: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "+3.3V_PANEL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_run>; - }; + vdd_3v3_panel: regulator@9 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_PANEL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_run>; + }; - vdd_3v3_lp0: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "+3.3V_LP0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* - * TODO: find a way to wire this up with the USB EHCI - * controllers so that it can be enabled on demand. - */ - regulator-always-on; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; + vdd_3v3_lp0: regulator@10 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* + * TODO: find a way to wire this up with the USB EHCI + * controllers so that it can be enabled on demand. + */ + regulator-always-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; - vdd_hdmi_pll: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; + vdd_hdmi_pll: regulator@11 { + compatible = "regulator-fixed"; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; - vdd_5v0_hdmi: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_5v0_hdmi: regulator@12 { + compatible = "regulator-fixed"; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; }; sound { diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 94cac13d3e50..64f488ba1e72 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -22,9 +22,9 @@ pcie@1003000 { compatible = "nvidia,tegra124-pcie"; device_type = "pci"; - reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ - 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ - 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ + reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ + <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ + <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ reg-names = "pads", "afi", "cs"; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ @@ -38,11 +38,11 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ - 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ - 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ - 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ - 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ + ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ + <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ + <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ + <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ + <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ clocks = <&tegra_car TEGRA124_CLK_PCIE>, <&tegra_car TEGRA124_CLK_AFI>, @@ -85,11 +85,13 @@ }; host1x@50000000 { - compatible = "nvidia,tegra124-host1x", "simple-bus"; + compatible = "nvidia,tegra124-host1x"; reg = <0x0 0x50000000 0x0 0x00034000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ + interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA124_CLK_HOST1X>; + clock-names = "host1x"; resets = <&tegra_car 28>; reset-names = "host1x"; iommus = <&mc TEGRA_SWGROUP_HC>; @@ -103,9 +105,8 @@ compatible = "nvidia,tegra124-dc"; reg = <0x0 0x54200000 0x0 0x00040000>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&tegra_car TEGRA124_CLK_DISP1>, - <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "dc", "parent"; + clocks = <&tegra_car TEGRA124_CLK_DISP1>; + clock-names = "dc"; resets = <&tegra_car 27>; reset-names = "dc"; @@ -118,9 +119,8 @@ compatible = "nvidia,tegra124-dc"; reg = <0x0 0x54240000 0x0 0x00040000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&tegra_car TEGRA124_CLK_DISP2>, - <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "dc", "parent"; + clocks = <&tegra_car TEGRA124_CLK_DISP2>; + clock-names = "dc"; resets = <&tegra_car 26>; reset-names = "dc"; @@ -178,6 +178,11 @@ resets = <&tegra_car 181>; reset-names = "dpaux"; status = "disabled"; + + i2c-bus { + #address-cells = <1>; + #size-cells = <0>; + }; }; }; @@ -622,6 +627,7 @@ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; #iommu-cells = <1>; + #reset-cells = <1>; }; emc: external-memory-controller@7001b000 { @@ -679,8 +685,8 @@ <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, <&tegra_car TEGRA124_CLK_XUSB_SS>, - <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, <&tegra_car TEGRA124_CLK_PLL_U_480M>, @@ -688,7 +694,7 @@ <&tegra_car TEGRA124_CLK_PLL_E>; clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", "xusb_ss", - "xusb_ss_div2", "xusb_ss_src", + "xusb_ss_src", "xusb_ss_div2", "xusb_hs_src", "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; resets = <&tegra_car 89>, <&tegra_car 156>, @@ -833,41 +839,45 @@ }; }; - sdhci@700b0000 { + mmc@700b0000 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; + clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; status = "disabled"; }; - sdhci@700b0200 { + mmc@700b0200 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0200 0x0 0x200>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; + clock-names = "sdhci"; resets = <&tegra_car 9>; reset-names = "sdhci"; status = "disabled"; }; - sdhci@700b0400 { + mmc@700b0400 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0400 0x0 0x200>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; + clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; status = "disabled"; }; - sdhci@700b0600 { + mmc@700b0600 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0600 0x0 0x200>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; + clock-names = "sdhci"; resets = <&tegra_car 15>; reset-names = "sdhci"; status = "disabled"; @@ -885,8 +895,8 @@ soctherm: thermal-sensor@700e2000 { compatible = "nvidia,tegra124-soctherm"; - reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ - 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ + reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ + <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ reg-names = "soctherm-reg", "car-reg"; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, @@ -1056,6 +1066,7 @@ clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 22>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; @@ -1093,6 +1104,7 @@ clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; @@ -1129,6 +1141,7 @@ clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 59>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts new file mode 100644 index 000000000000..2d683c9a1a5d --- /dev/null +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -0,0 +1,1438 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/thermal/thermal.h> + +#include "tegra20.dtsi" +#include "tegra20-cpu-opp.dtsi" +#include "tegra20-cpu-opp-microvolt.dtsi" + +/ { + model = "Acer Iconia Tab A500"; + compatible = "acer,picasso", "nvidia,tegra20"; + + aliases { + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + serial0 = &uartd; /* Docking station */ + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + memory@0 { + reg = <0x00000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@2ffe0000 { + compatible = "ramoops"; + reg = <0x2ffe0000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + linux,cma@30000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x30000000 0x10000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + port@0 { + lcd_output: endpoint { + remote-endpoint = <&lvds_encoder_input>; + bus-width = <18>; + }; + }; + }; + }; + + hdmi@54280000 { + status = "okay"; + + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + hdmi-supply = <&vdd_5v0_sys>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gmb", "spia", + "spib", "spic"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp", "lm1"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "vi"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + gmd { + nvidia,pins = "gmd"; + nvidia,function = "sflash"; + }; + gpu { + nvidia,pins = "gpu"; + nvidia,function = "pwm"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uartb"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", + "lsdi", "lvp0"; + nvidia,function = "rsvd4"; + }; + ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lpp", "lsc0", + "lsc1", "lsck", "lsda", "lspi", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk"; + nvidia,function = "sdio3"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxd { + nvidia,pins = "slxd"; + nvidia,function = "spdif"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", + "cdev1", "cdev2", "csus", "dap1", + "dap4", "dte", "dtf", "gma", "gmc", + "gme", "gpu", "gpu7", "gpv", "i2cp", + "irrx", "irtx", "pta", "rm", + "sdc", "sdd", "slxc", "slxd", "slxk", + "spdi", "spdo", "uac", "uad", "uda"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_ate { + nvidia,pins = "ate", "dap2", "dap3", + "gmd", "owc", "spia", "spib", "spic", + "spid", "spie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + }; + conf_crtp { + nvidia,pins = "crtp", "gmb", "slxa", "spig", + "spih"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_dte { + nvidia,pins = "spif"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsck", "lsda", "lsdi", + "lvp0"; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_kbca { + nvidia,pins = "kbca", "kbcc", "kbcd", + "kbce", "kbcf", "sdio1", "uaa", + "uab", "uca", "ucb"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lsc1", "lspi", + "lvp1", "lvs", "pmc", "sdb"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + }; + drive_ddc { + nvidia,pins = "drive_ddc", + "drive_vi1", + "drive_sdio1"; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>; + }; + drive_dbg { + nvidia,pins = "drive_dbg", + "drive_vi2", + "drive_at1", + "drive_ao1"; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + }; + + state_i2cmux_ddc: pinmux_i2cmux_ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux_i2cmux_pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + + state_i2cmux_idle: pinmux_i2cmux_idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + }; + + tegra_i2s1: i2s@70002800 { + status = "okay"; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra20-hsuart"; + /* GPS BCM4751 */ + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra20-hsuart"; + status = "okay"; + + /* Azurewave AW-NH665 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + + /* PLLP 216MHz / 16 / 4 */ + max-speed = <3375000>; + + clocks = <&rtc_32k_wifi>; + clock-names = "txco"; + + vbat-supply = <&vdd_3v3_sys>; + vddio-supply = <&vdd_1v8_sys>; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + }; + }; + + uartd: serial@70006300 { + /* Docking station */ + }; + + i2c@7000c000 { + clock-frequency = <400000>; + status = "okay"; + + wm8903: audio-codec@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-cfg = < + 0x0000 /* MIC_LR_OUT# GPIO, output, low */ + 0x0000 /* FM2018-enable GPIO, output, low */ + 0x0000 /* Speaker-enable GPIO, output, low */ + 0x0200 /* Interrupt, output */ + 0x01a0 /* BCLK, input, active high */ + >; + + AVDD-supply = <&vdd_1v8_sys>; + CPVDD-supply = <&vdd_1v8_sys>; + DBVDD-supply = <&vdd_1v8_sys>; + DCVDD-supply = <&vdd_1v8_sys>; + }; + + touchscreen@4c { + compatible = "atmel,maxtouch"; + reg = <0x4c>; + + atmel,cfg_name = "maxtouch-acer-iconia-tab-a500.cfg"; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; + + avdd-supply = <&vdd_3v3_sys>; + vdd-supply = <&vdd_3v3_sys>; + }; + + gyroscope@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&vdd_3v3_sys>; + vlogic-supply = <&vdd_1v8_sys>; + + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@f { + compatible = "kionix,kxtf9"; + reg = <0x0f>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>; + + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + }; + }; + }; + }; + + i2c@7000c400 { + clock-frequency = <10000>; + status = "okay"; + }; + + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + panel_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + i2c@7000d000 { + clock-frequency = <100000>; + status = "okay"; + + magnetometer@c { + compatible = "ak,ak8975"; + reg = <0x0c>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&vdd_3v3_sys>; + vid-supply = <&vdd_1v8_sys>; + + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; + + pmic: pmic@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_sys>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + sys_reg: sys { + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + vdd_core: sm0 { + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&rtc_vdd &vdd_cpu>; + regulator-coupled-max-spread = <170000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-core-regulator; + }; + + vdd_cpu: sm1 { + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1125000>; + regulator-coupled-with = <&vdd_core &rtc_vdd>; + regulator-coupled-max-spread = <550000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-cpu-regulator; + }; + + sm2_reg: sm2 { + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + ldo1 { + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + rtc_vdd: ldo2 { + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&vdd_core &vdd_cpu>; + regulator-coupled-max-spread = <170000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-rtc-regulator; + }; + + ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vcore_emmc: ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + avdd_vdac_reg: ldo6 { + regulator-name = "vdd_ldo6,avdd_vdac"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + hdmi_vdd_reg: ldo7 { + regulator-name = "vdd_ldo7,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: ldo8 { + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo_rtc { + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + nct1008: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <100>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <458>; + nvidia,sys-clock-req-active-high; + }; + + usb@c5000000 { + compatible = "nvidia,tegra20-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@c5000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&vdd_vbus1>; + }; + + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&vdd_vbus3>; + }; + + brcm_wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&rtc_32k_wifi>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + + mmc@c8000000 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + max-frequency = <25000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_3v3_sys>; + + /* Azurewave AW-NH611 BCM4329 */ + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; + }; + + mmc@c8000400 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_3v3_sys>; + }; + + mmc@c8000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_3v3_sys>; + non-removable; + }; + + mains: ac-adapter-detect { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_3v3_sys>; + pwms = <&pwm 2 41667>; + + brightness-levels = <7 255>; + num-interpolated-steps = <248>; + default-brightness-level = <20>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "tps658621-out32k"; + }; + + /* + * This standalone onboard fixed-clock always-ON 32KHz + * oscillator is used as a reference clock-source by the + * Azurewave WiFi/BT module. + */ + rtc_32k_wifi: clock@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "kk3270032"; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + display-panel { + compatible = "auo,b101ew05", "panel-lvds"; + + ddc-i2c-bus = <&panel_ddc>; + power-supply = <&vdd_pnl>; + backlight = <&backlight>; + + width-mm = <218>; + height-mm = <135>; + + data-mapping = "jeida-18"; + + panel-timing { + clock-frequency = <71200000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <8>; + hback-porch = <18>; + hsync-len = <184>; + vsync-len = <3>; + vfront-porch = <4>; + vback-porch = <8>; + }; + + port { + panel_input: endpoint { + remote-endpoint = <&lvds_encoder_output>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; + linux,code = <KEY_POWER>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + + rotation-lock { + label = "Rotate-lock"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>; + linux,code = <SW_ROTATE_LOCK>; + linux,input-type = <EV_SW>; + debounce-interval = <10>; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + }; + + haptic-feedback { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; + vcc-supply = <&vdd_3v3_sys>; + }; + + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + + powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_encoder_input: endpoint { + remote-endpoint = <&lcd_output>; + }; + }; + + port@1 { + reg = <1>; + + lvds_encoder_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + + vdd_5v0_sys: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_3v3_sys: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_vs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_1v8_sys: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_vs"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_pnl: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <300000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_vbus1: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_vbus3: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + gpio = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-picasso", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Acer Iconia Tab A500 WM8903"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "LINEOUTL", + "Int Spk", "LINEOUTR", + "Mic Jack", "MICBIAS", + "IN2L", "Mic Jack", + "IN2R", "Mic Jack", + "IN1L", "Int Mic", + "IN1R", "Int Mic"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; + nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>; + nvidia,headset; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; + + thermal-zones { + nct1008-local { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <0>; /* milliseconds */ + + thermal-sensors = <&nct1008 0>; + }; + + nct1008-remote { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct1008 1>; + + trips { + trip0: cpu-alert0 { + /* start throttling at 50C */ + temperature = <50000>; + hysteresis = <3000>; + type = "passive"; + }; + + trip1: cpu-crit { + /* shut down at 60C */ + temperature = <60000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + memory-controller@7000f400 { + nvidia,use-ram-code; + + emc-tables@0 { + nvidia,ram-code = <0>; /* elpida-8gb */ + + #address-cells = <1>; + #size-cells = <0>; + + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007dd510 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e1 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e1510 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + + emc-tables@1 { + nvidia,ram-code = <1>; /* elpida-4gb */ + + #address-cells = <1>; + #size-cells = <0>; + + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007e4010 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e1 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e0010 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + + emc-tables@2 { + nvidia,ram-code = <2>; /* hynix-8gb */ + + #address-cells = <1>; + #size-cells = <0>; + + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007dd010 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e1 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e2010 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + + emc-tables@3 { + nvidia,ram-code = <3>; /* hynix-4gb */ + + #address-cells = <1>; + #size-cells = <0>; + + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00078000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007e4010 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e1 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e0010 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts index 37ad508b61d9..a05fb3853da8 100644 --- a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts @@ -183,7 +183,7 @@ }; /* SD/MMC */ - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; bus-width = <4>; cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index af4740847769..425494b9ed54 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -171,7 +171,7 @@ }; /* SD/MMC */ - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; bus-width = <4>; cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ diff --git a/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi index e85ffdbef876..dce85d39480d 100644 --- a/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi +++ b/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi @@ -2,199 +2,199 @@ / { cpu0_opp_table: cpu_opp_table0 { - opp@216000000_750 { + opp@216000000,750 { opp-microvolt = <750000 750000 1125000>; }; - opp@216000000_800 { + opp@216000000,800 { opp-microvolt = <800000 800000 1125000>; }; - opp@312000000_750 { + opp@312000000,750 { opp-microvolt = <750000 750000 1125000>; }; - opp@312000000_800 { + opp@312000000,800 { opp-microvolt = <800000 800000 1125000>; }; - opp@456000000_750 { + opp@456000000,750 { opp-microvolt = <750000 750000 1125000>; }; - opp@456000000_800 { + opp@456000000,800 { opp-microvolt = <800000 800000 1125000>; }; - opp@456000000_800_2_2 { + opp@456000000,800,2,2 { opp-microvolt = <800000 800000 1125000>; }; - opp@456000000_800_3_2 { + opp@456000000,800,3,2 { opp-microvolt = <800000 800000 1125000>; }; - opp@456000000_825 { + opp@456000000,825 { opp-microvolt = <825000 825000 1125000>; }; - opp@608000000_750 { + opp@608000000,750 { opp-microvolt = <750000 750000 1125000>; }; - opp@608000000_800 { + opp@608000000,800 { opp-microvolt = <800000 800000 1125000>; }; - opp@608000000_800_3_2 { + opp@608000000,800,3,2 { opp-microvolt = <800000 800000 1125000>; }; - opp@608000000_825 { + opp@608000000,825 { opp-microvolt = <825000 825000 1125000>; }; - opp@608000000_850 { + opp@608000000,850 { opp-microvolt = <850000 850000 1125000>; }; - opp@608000000_900 { + opp@608000000,900 { opp-microvolt = <900000 900000 1125000>; }; - opp@760000000_775 { + opp@760000000,775 { opp-microvolt = <775000 775000 1125000>; }; - opp@760000000_800 { + opp@760000000,800 { opp-microvolt = <800000 800000 1125000>; }; - opp@760000000_850 { + opp@760000000,850 { opp-microvolt = <850000 850000 1125000>; }; - opp@760000000_875 { + opp@760000000,875 { opp-microvolt = <875000 875000 1125000>; }; - opp@760000000_875_1_1 { + opp@760000000,875,1,1 { opp-microvolt = <875000 875000 1125000>; }; - opp@760000000_875_0_2 { + opp@760000000,875,0,2 { opp-microvolt = <875000 875000 1125000>; }; - opp@760000000_875_1_2 { + opp@760000000,875,1,2 { opp-microvolt = <875000 875000 1125000>; }; - opp@760000000_900 { + opp@760000000,900 { opp-microvolt = <900000 900000 1125000>; }; - opp@760000000_975 { + opp@760000000,975 { opp-microvolt = <975000 975000 1125000>; }; - opp@816000000_800 { + opp@816000000,800 { opp-microvolt = <800000 800000 1125000>; }; - opp@816000000_850 { + opp@816000000,850 { opp-microvolt = <850000 850000 1125000>; }; - opp@816000000_875 { + opp@816000000,875 { opp-microvolt = <875000 875000 1125000>; }; - opp@816000000_950 { + opp@816000000,950 { opp-microvolt = <950000 950000 1125000>; }; - opp@816000000_1000 { + opp@816000000,1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@912000000_850 { + opp@912000000,850 { opp-microvolt = <850000 850000 1125000>; }; - opp@912000000_900 { + opp@912000000,900 { opp-microvolt = <900000 900000 1125000>; }; - opp@912000000_925 { + opp@912000000,925 { opp-microvolt = <925000 925000 1125000>; }; - opp@912000000_950 { + opp@912000000,950 { opp-microvolt = <950000 950000 1125000>; }; - opp@912000000_950_0_2 { + opp@912000000,950,0,2 { opp-microvolt = <950000 950000 1125000>; }; - opp@912000000_950_2_2 { + opp@912000000,950,2,2 { opp-microvolt = <950000 950000 1125000>; }; - opp@912000000_1000 { + opp@912000000,1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@912000000_1050 { + opp@912000000,1050 { opp-microvolt = <1050000 1050000 1125000>; }; - opp@1000000000_875 { + opp@1000000000,875 { opp-microvolt = <875000 875000 1125000>; }; - opp@1000000000_900 { + opp@1000000000,900 { opp-microvolt = <900000 900000 1125000>; }; - opp@1000000000_950 { + opp@1000000000,950 { opp-microvolt = <950000 950000 1125000>; }; - opp@1000000000_975 { + opp@1000000000,975 { opp-microvolt = <975000 975000 1125000>; }; - opp@1000000000_1000 { + opp@1000000000,1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@1000000000_1000_0_2 { + opp@1000000000,1000,0,2 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@1000000000_1025 { + opp@1000000000,1025 { opp-microvolt = <1025000 1025000 1125000>; }; - opp@1000000000_1100 { + opp@1000000000,1100 { opp-microvolt = <1100000 1100000 1125000>; }; - opp@1200000000_1000 { + opp@1200000000,1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@1200000000_1050 { + opp@1200000000,1050 { opp-microvolt = <1050000 1050000 1125000>; }; - opp@1200000000_1100 { + opp@1200000000,1100 { opp-microvolt = <1100000 1100000 1125000>; }; - opp@1200000000_1125 { + opp@1200000000,1125 { opp-microvolt = <1125000 1125000 1125000>; }; }; diff --git a/arch/arm/boot/dts/tegra20-cpu-opp.dtsi b/arch/arm/boot/dts/tegra20-cpu-opp.dtsi index c878f4231791..9b8fedb57a1b 100644 --- a/arch/arm/boot/dts/tegra20-cpu-opp.dtsi +++ b/arch/arm/boot/dts/tegra20-cpu-opp.dtsi @@ -5,295 +5,295 @@ compatible = "operating-points-v2"; opp-shared; - opp@216000000_750 { + opp@216000000,750 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0003>; opp-hz = /bits/ 64 <216000000>; }; - opp@216000000_800 { + opp@216000000,800 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0004>; opp-hz = /bits/ 64 <216000000>; }; - opp@312000000_750 { + opp@312000000,750 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0003>; opp-hz = /bits/ 64 <312000000>; }; - opp@312000000_800 { + opp@312000000,800 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0004>; opp-hz = /bits/ 64 <312000000>; }; - opp@456000000_750 { + opp@456000000,750 { clock-latency-ns = <400000>; opp-supported-hw = <0x0C 0x0003>; opp-hz = /bits/ 64 <456000000>; }; - opp@456000000_800 { + opp@456000000,800 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0006>; opp-hz = /bits/ 64 <456000000>; }; - opp@456000000_800_2_2 { + opp@456000000,800,2,2 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <456000000>; }; - opp@456000000_800_3_2 { + opp@456000000,800,3,2 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <456000000>; }; - opp@456000000_825 { + opp@456000000,825 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <456000000>; }; - opp@608000000_750 { + opp@608000000,750 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0003>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000_800 { + opp@608000000,800 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0006>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000_800_3_2 { + opp@608000000,800,3,2 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000_825 { + opp@608000000,825 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000_850 { + opp@608000000,850 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0006>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000_900 { + opp@608000000,900 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <608000000>; }; - opp@760000000_775 { + opp@760000000,775 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0003>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_800 { + opp@760000000,800 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850 { + opp@760000000,850 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0006>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_875 { + opp@760000000,875 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_875_1_1 { + opp@760000000,875,1,1 { clock-latency-ns = <400000>; opp-supported-hw = <0x02 0x0002>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_875_0_2 { + opp@760000000,875,0,2 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0004>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_875_1_2 { + opp@760000000,875,1,2 { clock-latency-ns = <400000>; opp-supported-hw = <0x02 0x0004>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900 { + opp@760000000,900 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0002>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_975 { + opp@760000000,975 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <760000000>; }; - opp@816000000_800 { + opp@816000000,800 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0007>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000_850 { + opp@816000000,850 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000_875 { + opp@816000000,875 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0005>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000_950 { + opp@816000000,950 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0006>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000_1000 { + opp@816000000,1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <816000000>; }; - opp@912000000_850 { + opp@912000000,850 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0007>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000_900 { + opp@912000000,900 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000_925 { + opp@912000000,925 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000_950 { + opp@912000000,950 { clock-latency-ns = <400000>; opp-supported-hw = <0x02 0x0006>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000_950_0_2 { + opp@912000000,950,0,2 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0004>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000_950_2_2 { + opp@912000000,950,2,2 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000_1000 { + opp@912000000,1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0002>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000_1050 { + opp@912000000,1050 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <912000000>; }; - opp@1000000000_875 { + opp@1000000000,875 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0007>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_900 { + opp@1000000000,900 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_950 { + opp@1000000000,950 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975 { + opp@1000000000,975 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_1000 { + opp@1000000000,1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x02 0x0006>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_1000_0_2 { + opp@1000000000,1000,0,2 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0004>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_1025 { + opp@1000000000,1025 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0002>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_1100 { + opp@1000000000,1100 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1200000000_1000 { + opp@1200000000,1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1050 { + opp@1200000000,1050 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1100 { + opp@1200000000,1100 { clock-latency-ns = <400000>; opp-supported-hw = <0x02 0x0004>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1125 { + opp@1200000000,1125 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0004>; opp-hz = /bits/ 64 <1200000000>; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 02cd67ea2503..86494cb4d5a1 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -613,7 +613,7 @@ status = "okay"; }; - sdhci@c8000200 { + mmc@c8000200 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; @@ -621,7 +621,7 @@ bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; @@ -640,17 +640,10 @@ default-brightness-level = <6>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { @@ -673,79 +666,66 @@ backlight = <&backlight>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v0_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; + regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - pci_vdd_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_1v05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + pci_vdd_reg: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vdd_pnl_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "vdd_pnl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vdd_pnl_reg: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vdd_bl_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vdd_bl_reg: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vdd_5v0_hdmi: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "VDDIO_HDMI"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_reg>; - }; + vdd_5v0_hdmi: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_reg>; }; sound { diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index c73510cd501c..a348ca30e522 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -59,7 +59,7 @@ panel: panel { compatible = "innolux,n156bge-l21"; - power-supply = <&vdd_1v8_reg>, <&vdd_3v3_reg>; + power-supply = <&vdd_1v8_reg>; // <&vdd_3v3_reg>; enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; backlight = <&backlight>; @@ -92,44 +92,38 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; - regulators { - vcc_24v_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vcc_24v"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - }; + vcc_24v_reg: regulator@100 { + compatible = "regulator-fixed"; + regulator-name = "vcc_24v"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + regulator-always-on; + }; - vdd_5v0_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "vdd_5v0"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + vdd_5v0_reg: regulator@101 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - vdd_3v3_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "vdd_3v3"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + vdd_3v3_reg: regulator@102 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - vdd_1v8_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "vdd_1v8"; - vin-supply = <&vdd_3v3_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; + vdd_1v8_reg: regulator@103 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8"; + vin-supply = <&vdd_3v3_reg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; }; }; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index cce3a3fb82ed..ada2bed8b1b5 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -314,7 +314,7 @@ memory-controller@7000f400 { nvidia,use-ram-code; - emc-tables@hynix { + emc-tables@0 { nvidia,ram-code = <0x0>; #address-cells = <1>; #size-cells = <0>; @@ -543,7 +543,7 @@ status = "okay"; }; - sdhci@c8000000 { + mmc@c8000000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; @@ -551,7 +551,7 @@ bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; @@ -569,17 +569,10 @@ backlight-boot-off; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { @@ -596,7 +589,7 @@ gpio-leds { compatible = "gpio-leds"; - wifi { + led-0 { label = "wifi-led"; gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; linux,default-trigger = "rfkill0"; @@ -613,30 +606,22 @@ backlight = <&backlight>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - p5valw_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+5valw"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + p5valw_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "+5valw"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - vdd_pnl_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+3VS,vdd_pnl"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vdd_pnl_reg: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "+3VS,vdd_pnl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; }; sound { diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts index 429e4605fbdb..378f23b2958b 100644 --- a/arch/arm/boot/dts/tegra20-plutux.dts +++ b/arch/arm/boot/dts/tegra20-plutux.dts @@ -60,44 +60,38 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; - regulators { - vcc_24v_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vcc_24v"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - }; + vcc_24v_reg: regulator@100 { + compatible = "regulator-fixed"; + regulator-name = "vcc_24v"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + regulator-always-on; + }; - vdd_5v0_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "vdd_5v0"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + vdd_5v0_reg: regulator@101 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - vdd_3v3_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "vdd_3v3"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + vdd_3v3_reg: regulator@102 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - vdd_1v8_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "vdd_1v8"; - vin-supply = <&vdd_3v3_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; + vdd_1v8_reg: regulator@103 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8"; + vin-supply = <&vdd_3v3_reg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; }; }; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 376ecb6435f4..c24d4a37613e 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -394,10 +394,10 @@ #size-cells = <0>; smart-battery@b { - compatible = "ti,bq20z75", "smart-battery-1.1"; + compatible = "ti,bq20z75", "sbs,sbs-battery"; reg = <0xb>; - ti,i2c-retry-count = <2>; - ti,poll-retry-count = <10>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; }; }; }; @@ -760,14 +760,14 @@ status = "okay"; }; - sdhci@c8000000 { + mmc@c8000000 { status = "okay"; power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; bus-width = <4>; keep-power-in-suspend; }; - sdhci@c8000400 { + mmc@c8000400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; @@ -775,7 +775,7 @@ bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; @@ -792,17 +792,10 @@ default-brightness-level = <6>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { @@ -835,81 +828,68 @@ ddc-i2c-bus = <&lvds_ddc>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v0_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; + regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vbus_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_vbus_wup1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 0) 0>; - regulator-always-on; - regulator-boot-on; - }; + vbus_reg: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_vbus_wup1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 0) 0>; + regulator-always-on; + regulator-boot-on; + }; - vdd_pnl_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "vdd_pnl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vdd_pnl_reg: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vdd_bl_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vdd_bl_reg: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vdd_hdmi: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "VDDIO_HDMI"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_reg>; - }; + vdd_hdmi: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_reg>; }; sound { diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 20137fc578b1..95e6bccdb4f6 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -495,40 +495,25 @@ status = "okay"; }; - sdhci@c8000600 { + mmc@c8000600 { cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; bus-width = <4>; status = "okay"; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; - regulators { - compatible = "simple-bus"; - - #address-cells = <1>; - #size-cells = <0>; - - pci_vdd_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_1v05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&pmic 2 0>; - enable-active-high; - }; + pci_vdd_reg: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&pmic 2 0>; + enable-active-high; }; }; diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts index 4dec27737238..44ced60315de 100644 --- a/arch/arm/boot/dts/tegra20-tec.dts +++ b/arch/arm/boot/dts/tegra20-tec.dts @@ -69,44 +69,38 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; - regulators { - vcc_24v_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vcc_24v"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - }; + vcc_24v_reg: regulator@100 { + compatible = "regulator-fixed"; + regulator-name = "vcc_24v"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + regulator-always-on; + }; - vdd_5v0_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "vdd_5v0"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + vdd_5v0_reg: regulator@101 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - vdd_3v3_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "vdd_3v3"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + vdd_3v3_reg: regulator@102 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - vdd_1v8_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "vdd_1v8"; - vin-supply = <&vdd_3v3_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; + vdd_1v8_reg: regulator@103 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8"; + vin-supply = <&vdd_3v3_reg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; }; }; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 8debd3d3c20d..4bc87bc0c2a4 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -366,30 +366,23 @@ status = "okay"; }; - sdhci@c8000000 { + mmc@c8000000 { status = "okay"; broken-cd; bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { @@ -408,58 +401,47 @@ gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - hdmi_vdd_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + hdmi_vdd_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - hdmi_pll_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; + hdmi_pll_reg: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; - vbus_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(V, 2) 0>; - regulator-always-on; - regulator-boot-on; - }; + vbus_reg: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(V, 2) 0>; + regulator-always-on; + regulator-boot-on; + }; - pci_clk_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "pci_clk"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + pci_clk_reg: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "pci_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - pci_vdd_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "pci_vdd"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; + pci_vdd_reg: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "pci_vdd"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; }; sound { diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 022649119821..b158771ac0b7 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -554,14 +554,14 @@ status = "okay"; }; - sdhci@c8000000 { + mmc@c8000000 { status = "okay"; power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; bus-width = <4>; keep-power-in-suspend; }; - sdhci@c8000400 { + mmc@c8000400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; @@ -569,7 +569,7 @@ bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; @@ -586,17 +586,10 @@ default-brightness-level = <6>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { @@ -620,58 +613,47 @@ ddc-i2c-bus = <&lvds_ddc>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v0_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; + regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vdd_pnl_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_pnl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vdd_pnl_reg: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vdd_bl_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vdd_bl_reg: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; }; sound { diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index c3b8ad53b967..72a4211a618f 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -17,25 +17,27 @@ reg = <0 0>; }; - iram@40000000 { + sram@40000000 { compatible = "mmio-sram"; reg = <0x40000000 0x40000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40000000 0x40000>; - vde_pool: vde@400 { + vde_pool: sram@400 { reg = <0x400 0x3fc00>; pool; }; }; host1x@50000000 { - compatible = "nvidia,tegra20-host1x", "simple-bus"; + compatible = "nvidia,tegra20-host1x"; reg = <0x50000000 0x00024000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ + interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA20_CLK_HOST1X>; + clock-names = "host1x"; resets = <&tegra_car 28>; reset-names = "host1x"; @@ -154,7 +156,9 @@ dsi@54300000 { compatible = "nvidia,tegra20-dsi"; reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA20_CLK_DSI>; + clocks = <&tegra_car TEGRA20_CLK_DSI>, + <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; resets = <&tegra_car 48>; reset-names = "dsi"; status = "disabled"; @@ -172,8 +176,8 @@ intc: interrupt-controller@50041000 { compatible = "arm,cortex-a9-gic"; - reg = <0x50041000 0x1000 - 0x50040100 0x0100>; + reg = <0x50041000 0x1000>, + <0x50040100 0x0100>; interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&intc>; @@ -272,15 +276,15 @@ vde@6001a000 { compatible = "nvidia,tegra20-vde"; - reg = <0x6001a000 0x1000 /* Syntax Engine */ - 0x6001b000 0x1000 /* Video Bitstream Engine */ - 0x6001c000 0x100 /* Macroblock Engine */ - 0x6001c200 0x100 /* Post-processing Engine */ - 0x6001c400 0x100 /* Motion Compensation Engine */ - 0x6001c600 0x100 /* Transform Engine */ - 0x6001c800 0x100 /* Pixel prediction block */ - 0x6001ca00 0x100 /* Video DMA */ - 0x6001d800 0x300>; /* Video frame controls */ + reg = <0x6001a000 0x1000>, /* Syntax Engine */ + <0x6001b000 0x1000>, /* Video Bitstream Engine */ + <0x6001c000 0x100>, /* Macroblock Engine */ + <0x6001c200 0x100>, /* Post-processing Engine */ + <0x6001c400 0x100>, /* Motion Compensation Engine */ + <0x6001c600 0x100>, /* Transform Engine */ + <0x6001c800 0x100>, /* Pixel prediction block */ + <0x6001ca00 0x100>, /* Video DMA */ + <0x6001d800 0x300>; /* Video frame controls */ reg-names = "sxe", "bsev", "mbe", "ppe", "mce", "tfe", "ppb", "vdma", "frameid"; iram = <&vde_pool>; /* IRAM region */ @@ -295,16 +299,16 @@ apbmisc@70000800 { compatible = "nvidia,tegra20-apbmisc"; - reg = <0x70000800 0x64 /* Chip revision */ - 0x70000008 0x04>; /* Strapping options */ + reg = <0x70000800 0x64>, /* Chip revision */ + <0x70000008 0x04>; /* Strapping options */ }; pinmux: pinmux@70000014 { compatible = "nvidia,tegra20-pinmux"; - reg = <0x70000014 0x10 /* Tri-state registers */ - 0x70000080 0x20 /* Mux registers */ - 0x700000a0 0x14 /* Pull-up/down registers */ - 0x70000868 0xa8>; /* Pad control registers */ + reg = <0x70000014 0x10>, /* Tri-state registers */ + <0x70000080 0x20>, /* Mux registers */ + <0x700000a0 0x14>, /* Pull-up/down registers */ + <0x70000868 0xa8>; /* Pad control registers */ }; das@70000c00 { @@ -619,8 +623,8 @@ mc: memory-controller@7000f000 { compatible = "nvidia,tegra20-mc-gart"; - reg = <0x7000f000 0x400 /* controller registers */ - 0x58000000 0x02000000>; /* GART aperture */ + reg = <0x7000f000 0x00000400>, /* controller registers */ + <0x58000000 0x02000000>; /* GART aperture */ clocks = <&tegra_car TEGRA20_CLK_MC>; clock-names = "mc"; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; @@ -649,12 +653,12 @@ pcie@80003000 { compatible = "nvidia,tegra20-pcie"; device_type = "pci"; - reg = <0x80003000 0x00000800 /* PADS registers */ - 0x80003800 0x00000200 /* AFI registers */ - 0x90000000 0x10000000>; /* configuration space */ + reg = <0x80003000 0x00000800>, /* PADS registers */ + <0x80003800 0x00000200>, /* AFI registers */ + <0x90000000 0x10000000>; /* configuration space */ reg-names = "pads", "afi", "cs"; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ - GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ interrupt-names = "intr", "msi"; #interrupt-cells = <1>; @@ -665,11 +669,11 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ - 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ - 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */ - 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ + ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */ + <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */ + <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */ + <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */ + <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ clocks = <&tegra_car TEGRA20_CLK_PEX>, <&tegra_car TEGRA20_CLK_AFI>, @@ -726,7 +730,8 @@ phy1: usb-phy@c5000000 { compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5000000 0x4000 0xc5000000 0x4000>; + reg = <0xc5000000 0x4000>, + <0xc5000000 0x4000>; phy_type = "utmi"; clocks = <&tegra_car TEGRA20_CLK_USBD>, <&tegra_car TEGRA20_CLK_PLL_U>, @@ -735,6 +740,7 @@ clock-names = "reg", "pll_u", "timer", "utmi-pads"; resets = <&tegra_car 22>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,has-legacy-mode; nvidia,hssync-start-delay = <9>; nvidia,idle-wait-delay = <17>; @@ -769,6 +775,7 @@ clock-names = "reg", "pll_u", "ulpi-link"; resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; status = "disabled"; }; @@ -786,7 +793,8 @@ phy3: usb-phy@c5008000 { compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5008000 0x4000 0xc5000000 0x4000>; + reg = <0xc5008000 0x4000>, + <0xc5000000 0x4000>; phy_type = "utmi"; clocks = <&tegra_car TEGRA20_CLK_USB3>, <&tegra_car TEGRA20_CLK_PLL_U>, @@ -795,6 +803,7 @@ clock-names = "reg", "pll_u", "timer", "utmi-pads"; resets = <&tegra_car 59>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <9>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; @@ -805,41 +814,45 @@ status = "disabled"; }; - sdhci@c8000000 { + mmc@c8000000 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000000 0x200>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; status = "disabled"; }; - sdhci@c8000200 { + mmc@c8000200 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000200 0x200>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; + clock-names = "sdhci"; resets = <&tegra_car 9>; reset-names = "sdhci"; status = "disabled"; }; - sdhci@c8000400 { + mmc@c8000400 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000400 0x200>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; + clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; status = "disabled"; }; - sdhci@c8000600 { + mmc@c8000600 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000600 0x200>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; + clock-names = "sdhci"; resets = <&tegra_car 15>; reset-names = "sdhci"; status = "disabled"; diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index b39c26806bf2..9f653ef41da4 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -120,7 +120,7 @@ }; /* Apalis SD1 */ - sdhci@78000000 { + mmc@78000000 { status = "okay"; bus-width = <4>; /* SD1_CD# */ @@ -129,7 +129,7 @@ }; /* Apalis MMC1 */ - sdhci@78000400 { + mmc@78000400 { status = "okay"; bus-width = <8>; /* MMC1_CD# */ diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts index e29dca92ba0a..86e138e8c7f0 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts @@ -121,7 +121,7 @@ }; /* Apalis SD1 */ - sdhci@78000000 { + mmc@78000000 { status = "okay"; bus-width = <4>; /* SD1_CD# */ @@ -130,7 +130,7 @@ }; /* Apalis MMC1 */ - sdhci@78000400 { + mmc@78000400 { status = "okay"; bus-width = <8>; /* MMC1_CD# */ @@ -248,8 +248,8 @@ regulator-max-microvolt = <3300000>; regulator-type = "voltage"; gpios = <&gpio TEGRA_GPIO(J, 5) GPIO_ACTIVE_HIGH>; - states = <1800000 0x0 - 3300000 0x1>; + states = <1800000 0x0>, + <3300000 0x1>; startup-delay-us = <100000>; vin-supply = <&vddio_sdmmc_1v8_reg>; }; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi index 387b17458e22..6a3a72f81c44 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi @@ -37,7 +37,7 @@ status = "okay"; nvidia,num-lanes = <1>; - pcie@0 { + ethernet@0,0 { reg = <0 0 0 0 0>; local-mac-address = [00 00 00 00 00 00]; }; @@ -855,6 +855,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_module_3v3_audio>; VDDD-supply = <®_1v8_vio>; VDDIO-supply = <®_module_3v3>; @@ -1112,7 +1113,7 @@ }; /* eMMC */ - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 6648506f3aa4..6544ce70b46f 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -36,7 +36,7 @@ status = "okay"; nvidia,num-lanes = <1>; - pcie@0 { + ethernet@0,0 { reg = <0 0 0 0 0>; local-mac-address = [00 00 00 00 00 00]; }; @@ -846,6 +846,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_module_3v3_audio>; VDDD-supply = <®_1v8_vio>; VDDIO-supply = <®_module_3v3>; @@ -1094,7 +1095,7 @@ }; /* eMMC */ - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-E1565.dts b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-E1565.dts new file mode 100644 index 000000000000..a25b8560b0cd --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-E1565.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-nexus7-grouper-maxim-pmic.dtsi" +#include "tegra30-asus-nexus7-grouper.dtsi" + +/ { + model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) E1565"; +}; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-PM269.dts b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-PM269.dts new file mode 100644 index 000000000000..06ef13ea5df8 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-PM269.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-nexus7-grouper-ti-pmic.dtsi" +#include "tegra30-asus-nexus7-grouper.dtsi" + +/ { + model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) PM269"; +}; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi new file mode 100644 index 000000000000..3922517145e7 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -0,0 +1,1232 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/thermal/thermal.h> + +#include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" + +/ { + aliases { + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + + ramoops@bfdf0000 { + compatible = "ramoops"; + reg = <0xbfdf0000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; + no-map; + }; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + port@0 { + lcd_output: endpoint { + remote-endpoint = <&lvds_encoder_input>; + bus-width = <24>; + }; + }; + }; + }; + }; + + gpio@6000d000 { + init-mode { + gpio-hog; + gpios = <TEGRA_GPIO(DD, 7) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + output-low; + }; + + init-low-power-mode { + gpio-hog; + gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + input; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat3_pb4", + "sdmmc3_dat2_pb5", + "sdmmc3_dat1_pb6", + "sdmmc3_dat0_pb7", + "sdmmc3_dat4_pd1", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a18_pb1"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pwr1_pc1", + "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + lcd_pclk_pb3 { + nvidia,pins = "lcd_pclk_pb3", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_cs0_n_pn4", + "lcd_sdout_pn5", + "lcd_dc0_pn6", + "lcd_cs1_n_pw0", + "lcd_sdin_pz2", + "lcd_sck_pz4"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs4_n_pk2", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4", + "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_dat5_pd0 { + nvidia,pins = "sdmmc3_dat5_pd0"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad14_ph6", + "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad2_pg2 { + nvidia,pins = "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad6_pg6", + "gmi_ad7_pg7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad4_pg4 { + nvidia,pins = "gmi_ad4_pg4", + "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad11_ph3 { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "pwm3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_adv_n_pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad15_ph7 { + nvidia,pins = "gmi_ad15_ph7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_dqs_pi2 { + nvidia,pins = "gmi_dqs_pi2", + "pu2", + "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_rst_n_pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_cs7_n_pi6 { + nvidia,pins = "gmi_cs7_n_pi6", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0", + "kb_col1_pq1", + "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2", + "kb_col3_pq3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4", + "kb_col5_pq5", + "kb_col7_pq7", + "kb_row2_pr2", + "kb_row4_pr4", + "kb_row5_pr5", + "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6", + "kb_row8_ps0", + "kb_row9_ps1", + "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3", + "kb_row12_ps4"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu0 { + nvidia,pins = "pu0", + "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2", + "spi2_miso_px1", + "spi2_sck_px2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_cs0_n_px3 { + nvidia,pins = "spi2_cs0_n_px3"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4", + "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_wr_n_pz3 { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + pbb0 { + nvidia,pins = "pbb0", + "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb7 { + nvidia,pins = "pbb7", + "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_rst_n_pcc3 { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l2_clkreq_n_pcc7"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + drive_sdio1 { + nvidia,pins = "drive_sdio1", + "drive_sdio3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; + }; + drive_gma { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + }; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + /* GPS BCM4751 */ + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + status = "okay"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + /* Azurewave AW-NH665 BCM4330B1 */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + + max-speed = <4000000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + vbat-supply = <&vdd_3v3_sys>; + vddio-supply = <&vdd_1v8>; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + }; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c400 { + clock-frequency = <400000>; + status = "okay"; + }; + + i2c@7000c500 { + clock-frequency = <100000>; + status = "okay"; + + compass@e { + compatible = "asahi-kasei,ak8974"; + reg = <0x0e>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(W, 0) IRQ_TYPE_EDGE_RISING>; + + avdd-supply = <&vdd_3v3_sys>; + dvdd-supply = <&vdd_1v8>; + + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; + }; + + light-sensor@1c { + compatible = "dynaimage,al3010"; + reg = <0x1c>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; + + vdd-supply = <&vdd_3v3_sys>; + }; + + accelerometer@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&vdd_3v3_sys>; + vddio-supply = <&vdd_1v8>; + + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; + }; + }; + + i2c@7000d000 { + clock-frequency = <100000>; + status = "okay"; + + rt5640: audio-codec@1c { + compatible = "realtek,rt5640"; + reg = <0x1c>; + + realtek,dmic1-data-pin = <1>; + }; + + nct72: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + + battery@55 { + compatible = "ti,bq27541"; + reg = <0x55>; + }; + }; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + }; + + ahub@70080000 { + i2s@70080400 { + status = "okay"; + }; + }; + + brcm_wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + + mmc@78000400 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_1v8>; + + /* Azurewave AW-NH665 BCM4330 */ + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; + }; + + mmc@78000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8>; + non-removable; + }; + + usb@7d000000 { + compatible = "nvidia,tegra30-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + power-supply = <&vdd_5v0_sys>; + pwms = <&pwm 0 50000>; + + brightness-levels = <1 255>; + num-interpolated-steps = <254>; + default-brightness-level = <15>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + display-panel { + compatible = "hydis,hv070wx2-1e0", "chunghwa,claa070wp03xg", + "panel-lvds"; + + power-supply = <&vdd_pnl>; + backlight = <&backlight>; + + width-mm = <94>; + height-mm = <150>; + rotation = <180>; + + data-mapping = "jeida-24"; + + port { + panel_input: endpoint { + remote-endpoint = <&lvds_encoder_output>; + }; + }; + }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <0x0>; + tlm,version-minor = <0x0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + hall-sensor { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + debounce-interval = <500>; + wakeup-event-action = <EV_ACT_DEASSERTED>; + wakeup-source; + }; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + }; + + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + + powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_encoder_input: endpoint { + remote-endpoint = <&lcd_output>; + }; + }; + + port@1 { + reg = <1>; + + lvds_encoder_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + + vdd_5v0_sys: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3_sys: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_pnl: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <300000>; + gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vcc_3v3_ts: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "ldo_s-1167_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v0_sys>; + }; + + sound { + compatible = "nvidia,tegra-audio-rt5640-grouper", + "nvidia,tegra-audio-rt5640"; + nvidia,model = "ASUS Google Nexus 7 ALC5642"; + + nvidia,audio-routing = + "Headphones", "HPOR", + "Headphones", "HPOL", + "Speakers", "SPORP", + "Speakers", "SPORN", + "Speakers", "SPOLP", + "Speakers", "SPOLN", + "DMIC1", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&rt5640>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + thermal-zones { + nct72-local { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <0>; /* milliseconds */ + + thermal-sensors = <&nct72 0>; + }; + + nct72-remote { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 1>; + + trips { + trip0: cpu-alert0 { + /* start throttling at 50C */ + temperature = <50000>; + hysteresis = <3000>; + type = "passive"; + }; + + trip1: cpu-crit { + /* shut down at 60C */ + temperature = <60000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi new file mode 100644 index 000000000000..b25b3fa90ac6 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/mfd/max77620.h> + +/ { + i2c@7000d000 { + pmic: pmic@3c { + compatible = "maxim,max77663"; + reg = <0x3c>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + #gpio-cells = <2>; + gpio-controller; + + system-power-controller; + + pinctrl-names = "default"; + pinctrl-0 = <&max77620_default>; + + max77620_default: pinmux { + gpio4 { + pins = "gpio4"; + function = "32k-out1"; + }; + }; + + cpu-pwr-req { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + input; + }; + + fps { + fps0 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + }; + + fps1 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + }; + + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + }; + }; + + regulators { + in-sd0-supply = <&vdd_5v0_sys>; + in-sd1-supply = <&vdd_5v0_sys>; + in-sd2-supply = <&vdd_5v0_sys>; + in-sd3-supply = <&vdd_5v0_sys>; + in-sd4-supply = <&vdd_5v0_sys>; + + in-ldo0-1-supply = <&vdd_1v35>; + in-ldo2-supply = <&vdd_3v3_sys>; + in-ldo3-5-supply = <&vdd_3v3_sys>; + in-ldo4-6-supply = <&vdd_5v0_sys>; + in-ldo7-8-supply = <&vdd_1v35>; + + vdd_cpu: sd0 { + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-cpu-regulator; + }; + + vdd_core: sd1 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-core-regulator; + }; + + vdd_1v8: sd2 { + regulator-name = "vdd_gen1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v35: sd3 { + regulator-name = "vdd_ddr3l_1v35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo0 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo2 { + regulator-name = "vdd_ddr_rx"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + + vcore_emmc: ldo3 { + regulator-name = "vcore_emmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo5 { + regulator-name = "vdd_camera"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo6 { + regulator-name = "vddio_sdmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo7 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo8 { + regulator-name = "avdd_pll"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + + vdd_3v3_sys: regulator@1 { + gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "avdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; +}; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi new file mode 100644 index 000000000000..bc0f6f29b956 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi @@ -0,0 +1,1565 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + memory-controller@7000f000 { + emc-timings-0 { + nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */ + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < + 0x00020001 /* MC_EMEM_ARB_CFG */ + 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74830303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < + 0x00010001 /* MC_EMEM_ARB_CFG */ + 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x73430303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x00000001 /* MC_EMEM_ARB_CFG */ + 0xc0000030 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x72830504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000003 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x72440a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < + 0x00000005 /* MC_EMEM_ARB_CFG */ + 0xc000003d /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000008 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0608 /* MC_EMEM_ARB_DA_COVERS */ + 0x70850f09 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < + 0x0000000a /* MC_EMEM_ARB_CFG */ + 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000010 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b10 /* MC_EMEM_ARB_DA_COVERS */ + 0x70ea1f11 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + + emc-timings-1 { + nvidia,ram-code = <1>; /* Hynix H5TC2G83CFR */ + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < + 0x00020001 /* MC_EMEM_ARB_CFG */ + 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74830303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < + 0x00010001 /* MC_EMEM_ARB_CFG */ + 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x73430303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x00000001 /* MC_EMEM_ARB_CFG */ + 0xc0000030 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x72830504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000003 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x72440a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < + 0x00000005 /* MC_EMEM_ARB_CFG */ + 0xc000003d /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000008 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0608 /* MC_EMEM_ARB_DA_COVERS */ + 0x70850f09 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < + 0x0000000a /* MC_EMEM_ARB_CFG */ + 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000010 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b10 /* MC_EMEM_ARB_DA_COVERS */ + 0x70ea1f11 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */ + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000004 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000005 /* EMC_TXSR */ + 0x00000005 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000001 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x00000008 /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000009 /* EMC_TXSR */ + 0x00000009 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x00000005 /* EMC_RC */ + 0x00000010 /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000012 /* EMC_TXSR */ + 0x00000012 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000004 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x0000000a /* EMC_RC */ + 0x00000020 /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000023 /* EMC_TXSR */ + 0x00000023 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000007 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < + 0x0000000f /* EMC_RC */ + 0x00000034 /* EMC_RFC */ + 0x0000000a /* EMC_RAS */ + 0x00000003 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x00000009 /* EMC_W2P */ + 0x00000003 /* EMC_RD_RCD */ + 0x00000003 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x000009e9 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x0000027a /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000e /* EMC_RW2PDEN */ + 0x00000039 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x0000000a /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000a2a /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x002600a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ + 0x00014000 /* EMC_DLL_XFORM_DQS4 */ + 0x00014000 /* EMC_DLL_XFORM_DQS5 */ + 0x00014000 /* EMC_DLL_XFORM_DQS6 */ + 0x00014000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x018b000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800014d4 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x0000001f /* EMC_RC */ + 0x00000069 /* EMC_RFC */ + 0x00000017 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000c /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000011 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000b /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001412 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000e /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000c /* EMC_AR2PDEN */ + 0x00000016 /* EMC_RW2PDEN */ + 0x00000072 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000007 /* EMC_TCLKSTOP */ + 0x00001453 /* EMC_TREFBW */ + 0x0000000c /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf00b0191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000008 /* EMC_DLL_XFORM_DQS0 */ + 0x00000008 /* EMC_DLL_XFORM_DQS1 */ + 0x00000008 /* EMC_DLL_XFORM_DQS2 */ + 0x00000008 /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000c /* EMC_DLL_XFORM_DQ0 */ + 0x0000000c /* EMC_DLL_XFORM_DQ1 */ + 0x0000000c /* EMC_DLL_XFORM_DQ2 */ + 0x0000000c /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0156000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ + 0xf8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + + emc-timings-1 { + nvidia,ram-code = <1>; /* Hynix H5TC2G83CFR */ + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000004 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000005 /* EMC_TXSR */ + 0x00000005 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000001 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x00000008 /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000009 /* EMC_TXSR */ + 0x00000009 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x00000005 /* EMC_RC */ + 0x00000010 /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000012 /* EMC_TXSR */ + 0x00000012 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000004 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x0000000a /* EMC_RC */ + 0x00000020 /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000023 /* EMC_TXSR */ + 0x00000023 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000007 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < + 0x0000000f /* EMC_RC */ + 0x00000034 /* EMC_RFC */ + 0x0000000a /* EMC_RAS */ + 0x00000003 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x00000009 /* EMC_W2P */ + 0x00000003 /* EMC_RD_RCD */ + 0x00000003 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x000009e9 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x0000027a /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000e /* EMC_RW2PDEN */ + 0x00000039 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x0000000a /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000a2a /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x002600a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ + 0x00014000 /* EMC_DLL_XFORM_DQS4 */ + 0x00014000 /* EMC_DLL_XFORM_DQS5 */ + 0x00014000 /* EMC_DLL_XFORM_DQS6 */ + 0x00014000 /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x018b000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800014d4 /* EMC_DYN_SELF_REF_CONTROL */ + 0xf8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x00000020 /* EMC_RC */ + 0x0000006a /* EMC_RFC */ + 0x00000017 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000c /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000011 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001412 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000e /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000c /* EMC_AR2PDEN */ + 0x00000016 /* EMC_RW2PDEN */ + 0x00000072 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000007 /* EMC_TCLKSTOP */ + 0x00001453 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf00b0191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000c /* EMC_DLL_XFORM_DQ0 */ + 0x0000000c /* EMC_DLL_XFORM_DQ1 */ + 0x0000000c /* EMC_DLL_XFORM_DQ2 */ + 0x0000000c /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0400013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0155000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi new file mode 100644 index 000000000000..bfc06b988781 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + i2c@7000d000 { + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; + ti,system-power-controller; + ti,sleep-keep-ck32k; + ti,sleep-enable; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_5v0_sys>; + vcc2-supply = <&vdd_5v0_sys>; + vcc3-supply = <&vdd_1v8>; + vcc4-supply = <&vdd_5v0_sys>; + vcc5-supply = <&vdd_5v0_sys>; + vcc6-supply = <&vdd2_reg>; + vcc7-supply = <&vdd_5v0_sys>; + vccio-supply = <&vdd_5v0_sys>; + + regulators { + vdd1 { + regulator-name = "vddio_ddr_1v2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <8>; + }; + + vdd2_reg: vdd2 { + regulator-name = "vdd2_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_cpu: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + ti,regulator-ext-sleep-control = <1>; + + nvidia,tegra-cpu-regulator; + }; + + vdd_1v8: vio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vcore_emmc: ldo1 { + regulator-name = "vdd_pexa,vdd_pexb"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo2 { + regulator-name = "vdd_sata,avdd_plle"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + /* LDO3 is not connected to anything */ + + ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo5 { + regulator-name = "vddio_sdmmc,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + ti,regulator-ext-sleep-control = <8>; + }; + + ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + ti,regulator-ext-sleep-control = <8>; + }; + }; + }; + + vdd_core: core-regulator@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-boot-on; + regulator-always-on; + ti,enable-vout-discharge; + ti,vsel0-state-high; + ti,vsel1-state-high; + + nvidia,tegra-core-regulator; + }; + }; + + vdd_3v3_sys: regulator@1 { + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi new file mode 100644 index 000000000000..a044dbd200a9 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "tegra30-asus-nexus7-grouper-common.dtsi" +#include "tegra30-asus-nexus7-grouper-memory-timings.dtsi" + +/ { + compatible = "asus,grouper", "nvidia,tegra30"; + + display-panel { + panel-timing { + clock-frequency = <68000000>; + hactive = <800>; + vactive = <1280>; + hfront-porch = <24>; + hback-porch = <32>; + hsync-len = <24>; + vsync-len = <1>; + vfront-porch = <5>; + vback-porch = <32>; + }; + }; + + pinmux@70000868 { + state_default: pinmux { + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs4_n_pk2", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + }; + }; + + i2c@7000c500 { + nfc@28 { + compatible = "nxp,pn544-i2c"; + reg = <0x28>; + clock-frequency = <100000>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(X, 0) IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&gpio TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>; + firmware-gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-E1565.dts b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-E1565.dts new file mode 100644 index 000000000000..f1c63feb4af9 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-E1565.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-nexus7-grouper-maxim-pmic.dtsi" +#include "tegra30-asus-nexus7-tilapia.dtsi" + +/ { + model = "ASUS Google Nexus 7 (Project Bach / ME370TG) E1565"; +}; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-memory-timings.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-memory-timings.dtsi new file mode 100644 index 000000000000..9169de34fa00 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-memory-timings.dtsi @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "tegra30-asus-nexus7-grouper-memory-timings.dtsi" + +/ { + /* + * Tilapia's memory timings are pretty much the same as the Grouper's + * ones. There are few minor tunings made for a higher clock rates, + * these differentiating timings are overridden here for Tilapia. + */ + + memory-controller@7000f400 { + emc-timings-0 { + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x0000001f /* EMC_RC */ + 0x00000069 /* EMC_RFC */ + 0x00000017 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000c /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000011 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000b /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001412 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000e /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000c /* EMC_AR2PDEN */ + 0x00000016 /* EMC_RW2PDEN */ + 0x00000072 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000007 /* EMC_TCLKSTOP */ + 0x00001453 /* EMC_TREFBW */ + 0x0000000c /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf00b0191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000008 /* EMC_DLL_XFORM_DQS0 */ + 0x00000008 /* EMC_DLL_XFORM_DQS1 */ + 0x00000008 /* EMC_DLL_XFORM_DQS2 */ + 0x00000008 /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000c /* EMC_DLL_XFORM_DQ0 */ + 0x0000000c /* EMC_DLL_XFORM_DQ1 */ + 0x0000000c /* EMC_DLL_XFORM_DQ2 */ + 0x0000000c /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0156000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + + emc-timings-1 { + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < + 0x0000000f /* EMC_RC */ + 0x00000034 /* EMC_RFC */ + 0x0000000a /* EMC_RAS */ + 0x00000003 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x00000009 /* EMC_W2P */ + 0x00000003 /* EMC_RD_RCD */ + 0x00000003 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x000009e9 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x0000027a /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000e /* EMC_RW2PDEN */ + 0x00000039 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x0000000a /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000a2a /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x002600a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ + 0x00014000 /* EMC_DLL_XFORM_DQS4 */ + 0x00014000 /* EMC_DLL_XFORM_DQS5 */ + 0x00014000 /* EMC_DLL_XFORM_DQS6 */ + 0x00014000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x018b000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800014d4 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < + 0x00000020 /* EMC_RC */ + 0x0000006a /* EMC_RFC */ + 0x00000017 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000c /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000011 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001412 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000e /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000c /* EMC_AR2PDEN */ + 0x00000016 /* EMC_RW2PDEN */ + 0x00000072 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000007 /* EMC_TCLKSTOP */ + 0x00001453 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf00b0191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000008 /* EMC_DLL_XFORM_DQS0 */ + 0x00000008 /* EMC_DLL_XFORM_DQS1 */ + 0x00000008 /* EMC_DLL_XFORM_DQS2 */ + 0x00000008 /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x0c000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0155000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi new file mode 100644 index 000000000000..e3da89f1941a --- /dev/null +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "tegra30-asus-nexus7-grouper-common.dtsi" +#include "tegra30-asus-nexus7-tilapia-memory-timings.dtsi" + +/ { + compatible = "asus,tilapia", "asus,grouper", "nvidia,tegra30"; + + display-panel { + enable-gpios = <&gpio TEGRA_GPIO(V, 6) GPIO_ACTIVE_HIGH>; + + panel-timing { + clock-frequency = <81750000>; + hactive = <800>; + vactive = <1280>; + hfront-porch = <64>; + hback-porch = <128>; + hsync-len = <64>; + vsync-len = <1>; + vfront-porch = <5>; + vback-porch = <2>; + }; + }; + + gpio@6000d000 { + init-mode-3g { + gpio-hog; + gpios = <TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(P, 1) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(X, 5) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(U, 5) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(EE, 1) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(Y, 2) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(Y, 3) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(U, 3) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(N, 1) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(N, 2) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(N, 0) GPIO_ACTIVE_HIGH>, + <TEGRA_GPIO(N, 3) GPIO_ACTIVE_HIGH>; + output-low; + }; + }; + + pinmux@70000868 { + state_default: pinmux { + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs4_n_pk2", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + }; + }; + + i2c@7000c500 { + proximity-sensor@28 { + compatible = "microchip,cap1106"; + reg = <0x28>; + + /* + * Binding doesn't support specifying linux,input-type + * and this results in unwanted key-presses handled by + * applications, hence keep it disabled for now. + */ + status = "disabled"; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(R, 3) IRQ_TYPE_LEVEL_HIGH>; + + linux,keycodes = <KEY_RESERVED>, + <KEY_RESERVED>, + <KEY_RESERVED>, + <KEY_RESERVED>, + <KEY_RESERVED>, + <SW_FRONT_PROXIMITY>; + }; + + nfc@2a { + compatible = "nxp,pn544-i2c"; + reg = <0x2a>; + + clock-frequency = <100000>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>; + firmware-gpios = <&gpio TEGRA_GPIO(P, 3) GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 6b6fd8a8058f..e0624b74fb50 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1922,7 +1922,7 @@ }; }; - sdhci@78000000 { + mmc@78000000 { status = "okay"; vqmmc-supply = <&ldo5_reg>; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; @@ -1931,7 +1931,7 @@ bus-width = <4>; }; - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; @@ -1965,17 +1965,10 @@ status = "okay"; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-leds { @@ -1991,118 +1984,103 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v_in_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_5v_in"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + vdd_5v_in_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v_in"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - chargepump_5v_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "chargepump_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - enable-active-high; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; + chargepump_5v_reg: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "chargepump_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; - ddr_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v_in_reg>; - }; + ddr_reg: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v_in_reg>; + }; - vdd_5v_sata_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_5v_sata"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v_in_reg>; - }; + vdd_5v_sata_reg: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v_sata"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v_in_reg>; + }; - usb1_vbus_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v_in_reg>; - }; + usb1_vbus_reg: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v_in_reg>; + }; - usb3_vbus_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "usb3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v_in_reg>; - }; + usb3_vbus_reg: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v_in_reg>; + }; - sys_3v3_reg: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "sys_3v3,vdd_3v3_alw"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v_in_reg>; - }; + sys_3v3_reg: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "sys_3v3,vdd_3v3_alw"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v_in_reg>; + }; - sys_3v3_pexs_reg: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "sys_3v3_pexs"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + sys_3v3_pexs_reg: regulator@7 { + compatible = "regulator-fixed"; + regulator-name = "sys_3v3_pexs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; - vdd_5v0_hdmi: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+VDD_5V_HDMI"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&sys_3v3_reg>; - }; + vdd_5v0_hdmi: regulator@8 { + compatible = "regulator-fixed"; + regulator-name = "+VDD_5V_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&sys_3v3_reg>; }; sound { diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts index a02ec5082287..4899e05a0d9c 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts @@ -9,87 +9,75 @@ model = "NVIDIA Tegra30 Cardhu A02 evaluation board"; compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30"; - sdhci@78000400 { + mmc@78000400 { status = "okay"; power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; keep-power-in-suspend; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - ddr_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - }; + ddr_reg: regulator@100 { + compatible = "regulator-fixed"; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + }; - sys_3v3_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "sys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - }; + sys_3v3_reg: regulator@101 { + compatible = "regulator-fixed"; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + }; - usb1_vbus_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; + usb1_vbus_reg: regulator@102 { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; - usb3_vbus_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "usb3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; + usb3_vbus_reg: regulator@103 { + compatible = "regulator-fixed"; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; - vdd_5v0_reg: regulator@104 { - compatible = "regulator-fixed"; - reg = <104>; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - }; + vdd_5v0_reg: regulator@104 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + }; - vdd_bl_reg: regulator@105 { - compatible = "regulator-fixed"; - reg = <105>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; - }; + vdd_bl_reg: regulator@105 { + compatible = "regulator-fixed"; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts index 9234988624ec..c1c0ca628af1 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts @@ -11,99 +11,86 @@ model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board"; compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30"; - sdhci@78000400 { + mmc@78000400 { status = "okay"; power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>; bus-width = <4>; keep-power-in-suspend; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - ddr_reg: regulator@100 { - compatible = "regulator-fixed"; - regulator-name = "ddr"; - reg = <100>; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - }; + ddr_reg: regulator@100 { + compatible = "regulator-fixed"; + regulator-name = "ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + }; - sys_3v3_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "sys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - }; + sys_3v3_reg: regulator@101 { + compatible = "regulator-fixed"; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + }; - usb1_vbus_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; + usb1_vbus_reg: regulator@102 { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; - usb3_vbus_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "usb3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; + usb3_vbus_reg: regulator@103 { + compatible = "regulator-fixed"; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; - vdd_5v0_reg: regulator@104 { - compatible = "regulator-fixed"; - reg = <104>; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; - }; + vdd_5v0_reg: regulator@104 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; + }; - vdd_bl_reg: regulator@105 { - compatible = "regulator-fixed"; - reg = <105>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; - }; + vdd_bl_reg: regulator@105 { + compatible = "regulator-fixed"; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; + }; - vdd_bl2_reg: regulator@106 { - compatible = "regulator-fixed"; - reg = <106>; - regulator-name = "vdd_bl2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; - }; + vdd_bl2_reg: regulator@106 { + compatible = "regulator-fixed"; + regulator-name = "vdd_bl2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; }; i2c@7000d000 { diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 5ee5d141bd81..dab9989fa760 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -384,7 +384,7 @@ }; }; - sdhci@78000000 { + mmc@78000000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; @@ -392,7 +392,7 @@ bus-width = <4>; }; - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; @@ -418,17 +418,10 @@ default-brightness-level = <6>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; panel: panel { @@ -441,158 +434,139 @@ backlight = <&backlight>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_ac_bat_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_ac_bat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + vdd_ac_bat_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_ac_bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - cam_1v8_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "cam_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; - vin-supply = <&vio_reg>; - }; + cam_1v8_reg: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "cam_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&vio_reg>; + }; - cp_5v_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "cp_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - enable-active-high; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; + cp_5v_reg: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "cp_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; - emmc_3v3_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "emmc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + emmc_3v3_reg: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "emmc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; - modem_3v3_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "modem_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; - }; + modem_3v3_reg: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "modem_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; + }; - pex_hvdd_3v3_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "pex_hvdd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + pex_hvdd_3v3_reg: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "pex_hvdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; - vdd_cam1_ldo_reg: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "vdd_cam1_ldo"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + vdd_cam1_ldo_reg: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "vdd_cam1_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; - vdd_cam2_ldo_reg: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "vdd_cam2_ldo"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + vdd_cam2_ldo_reg: regulator@7 { + compatible = "regulator-fixed"; + regulator-name = "vdd_cam2_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; - vdd_cam3_ldo_reg: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "vdd_cam3_ldo"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + vdd_cam3_ldo_reg: regulator@8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_cam3_ldo"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; - vdd_com_reg: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "vdd_com"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + vdd_com_reg: regulator@9 { + compatible = "regulator-fixed"; + regulator-name = "vdd_com"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; - vdd_fuse_3v3_reg: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "vdd_fuse_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + vdd_fuse_3v3_reg: regulator@10 { + compatible = "regulator-fixed"; + regulator-name = "vdd_fuse_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; - vdd_pnl1_reg: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "vdd_pnl1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + vdd_pnl1_reg: regulator@11 { + compatible = "regulator-fixed"; + regulator-name = "vdd_pnl1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; - vdd_vid_reg: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "vddio_vid"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; + vdd_vid_reg: regulator@12 { + compatible = "regulator-fixed"; + regulator-name = "vddio_vid"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; }; sound { diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 8e106e784dce..7d4a6ca4936a 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -98,7 +98,7 @@ }; /* SD/MMC */ - sdhci@78000200 { + mmc@78000200 { status = "okay"; bus-width = <4>; cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index adba554381c7..e36aa3ce6c3d 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -527,7 +527,7 @@ }; /* Colibri USBH_OC */ - spi2-cs2-n-pw3, { + spi2-cs2-n-pw3 { nvidia,pins = "spi2_cs2_n_pw3"; nvidia,function = "spi2_alt"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; @@ -723,6 +723,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_module_3v3_audio>; VDDD-supply = <®_1v8_vio>; VDDIO-supply = <®_module_3v3>; @@ -933,7 +934,7 @@ }; /* eMMC */ - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi index 5c40ef49894f..d682f7437146 100644 --- a/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi +++ b/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi @@ -2,799 +2,799 @@ / { cpu0_opp_table: cpu_opp_table0 { - opp@51000000_800 { + opp@51000000,800 { opp-microvolt = <800000 800000 1250000>; }; - opp@51000000_850 { + opp@51000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@51000000_912 { + opp@51000000,912 { opp-microvolt = <912000 912000 1250000>; }; - opp@102000000_800 { + opp@102000000,800 { opp-microvolt = <800000 800000 1250000>; }; - opp@102000000_850 { + opp@102000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@102000000_912 { + opp@102000000,912 { opp-microvolt = <912000 912000 1250000>; }; - opp@204000000_800 { + opp@204000000,800 { opp-microvolt = <800000 800000 1250000>; }; - opp@204000000_850 { + opp@204000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@204000000_912 { + opp@204000000,912 { opp-microvolt = <912000 912000 1250000>; }; - opp@312000000_850 { + opp@312000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@312000000_912 { + opp@312000000,912 { opp-microvolt = <912000 912000 1250000>; }; - opp@340000000_800 { + opp@340000000,800 { opp-microvolt = <800000 800000 1250000>; }; - opp@340000000_850 { + opp@340000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@370000000_800 { + opp@370000000,800 { opp-microvolt = <800000 800000 1250000>; }; - opp@456000000_850 { + opp@456000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@456000000_912 { + opp@456000000,912 { opp-microvolt = <912000 912000 1250000>; }; - opp@475000000_800 { + opp@475000000,800 { opp-microvolt = <800000 800000 1250000>; }; - opp@475000000_850 { + opp@475000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@475000000_850_0_1 { + opp@475000000,850,0,1 { opp-microvolt = <850000 850000 1250000>; }; - opp@475000000_850_0_4 { + opp@475000000,850,0,4 { opp-microvolt = <850000 850000 1250000>; }; - opp@475000000_850_0_7 { + opp@475000000,850,0,7 { opp-microvolt = <850000 850000 1250000>; }; - opp@475000000_850_0_8 { + opp@475000000,850,0,8 { opp-microvolt = <850000 850000 1250000>; }; - opp@608000000_850 { + opp@608000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@608000000_912 { + opp@608000000,912 { opp-microvolt = <912000 912000 1250000>; }; - opp@620000000_850 { + opp@620000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850 { + opp@640000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_1_1 { + opp@640000000,850,1,1 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_2_1 { + opp@640000000,850,2,1 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_3_1 { + opp@640000000,850,3,1 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_1_4 { + opp@640000000,850,1,4 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_2_4 { + opp@640000000,850,2,4 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_3_4 { + opp@640000000,850,3,4 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_1_7 { + opp@640000000,850,1,7 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_2_7 { + opp@640000000,850,2,7 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_3_7 { + opp@640000000,850,3,7 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_4_7 { + opp@640000000,850,4,7 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_1_8 { + opp@640000000,850,1,8 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_2_8 { + opp@640000000,850,2,8 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_3_8 { + opp@640000000,850,3,8 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_4_8 { + opp@640000000,850,4,8 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_900 { + opp@640000000,900 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_850 { + opp@760000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_850_3_1 { + opp@760000000,850,3,1 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_850_3_2 { + opp@760000000,850,3,2 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_850_3_3 { + opp@760000000,850,3,3 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_850_3_4 { + opp@760000000,850,3,4 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_850_3_7 { + opp@760000000,850,3,7 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_850_4_7 { + opp@760000000,850,4,7 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_850_3_8 { + opp@760000000,850,3,8 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_850_4_8 { + opp@760000000,850,4,8 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_850_0_10 { + opp@760000000,850,0,10 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_900 { + opp@760000000,900 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_1_1 { + opp@760000000,900,1,1 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_2_1 { + opp@760000000,900,2,1 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_1_2 { + opp@760000000,900,1,2 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_2_2 { + opp@760000000,900,2,2 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_1_3 { + opp@760000000,900,1,3 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_2_3 { + opp@760000000,900,2,3 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_1_4 { + opp@760000000,900,1,4 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_2_4 { + opp@760000000,900,2,4 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_1_7 { + opp@760000000,900,1,7 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_2_7 { + opp@760000000,900,2,7 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_1_8 { + opp@760000000,900,1,8 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_2_8 { + opp@760000000,900,2,8 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_912 { + opp@760000000,912 { opp-microvolt = <912000 912000 1250000>; }; - opp@760000000_975 { + opp@760000000,975 { opp-microvolt = <975000 975000 1250000>; }; - opp@816000000_850 { + opp@816000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@816000000_912 { + opp@816000000,912 { opp-microvolt = <912000 912000 1250000>; }; - opp@860000000_850 { + opp@860000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@860000000_900 { + opp@860000000,900 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_2_1 { + opp@860000000,900,2,1 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_3_1 { + opp@860000000,900,3,1 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_2_2 { + opp@860000000,900,2,2 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_3_2 { + opp@860000000,900,3,2 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_2_3 { + opp@860000000,900,2,3 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_3_3 { + opp@860000000,900,3,3 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_2_4 { + opp@860000000,900,2,4 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_3_4 { + opp@860000000,900,3,4 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_2_7 { + opp@860000000,900,2,7 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_3_7 { + opp@860000000,900,3,7 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_4_7 { + opp@860000000,900,4,7 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_2_8 { + opp@860000000,900,2,8 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_3_8 { + opp@860000000,900,3,8 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_4_8 { + opp@860000000,900,4,8 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_975 { + opp@860000000,975 { opp-microvolt = <975000 975000 1250000>; }; - opp@860000000_975_1_1 { + opp@860000000,975,1,1 { opp-microvolt = <975000 975000 1250000>; }; - opp@860000000_975_1_2 { + opp@860000000,975,1,2 { opp-microvolt = <975000 975000 1250000>; }; - opp@860000000_975_1_3 { + opp@860000000,975,1,3 { opp-microvolt = <975000 975000 1250000>; }; - opp@860000000_975_1_4 { + opp@860000000,975,1,4 { opp-microvolt = <975000 975000 1250000>; }; - opp@860000000_975_1_7 { + opp@860000000,975,1,7 { opp-microvolt = <975000 975000 1250000>; }; - opp@860000000_975_1_8 { + opp@860000000,975,1,8 { opp-microvolt = <975000 975000 1250000>; }; - opp@860000000_1000 { + opp@860000000,1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@910000000_900 { + opp@910000000,900 { opp-microvolt = <900000 900000 1250000>; }; - opp@1000000000_900 { + opp@1000000000,900 { opp-microvolt = <900000 900000 1250000>; }; - opp@1000000000_975 { + opp@1000000000,975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_2_1 { + opp@1000000000,975,2,1 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_3_1 { + opp@1000000000,975,3,1 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_2_2 { + opp@1000000000,975,2,2 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_3_2 { + opp@1000000000,975,3,2 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_2_3 { + opp@1000000000,975,2,3 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_3_3 { + opp@1000000000,975,3,3 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_2_4 { + opp@1000000000,975,2,4 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_3_4 { + opp@1000000000,975,3,4 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_2_7 { + opp@1000000000,975,2,7 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_3_7 { + opp@1000000000,975,3,7 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_4_7 { + opp@1000000000,975,4,7 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_2_8 { + opp@1000000000,975,2,8 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_3_8 { + opp@1000000000,975,3,8 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_4_8 { + opp@1000000000,975,4,8 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_1000 { + opp@1000000000,1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1000000000_1025 { + opp@1000000000,1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1100000000_900 { + opp@1100000000,900 { opp-microvolt = <900000 900000 1250000>; }; - opp@1100000000_975 { + opp@1100000000,975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000_975_3_1 { + opp@1100000000,975,3,1 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000_975_3_2 { + opp@1100000000,975,3,2 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000_975_3_3 { + opp@1100000000,975,3,3 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000_975_3_4 { + opp@1100000000,975,3,4 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000_975_3_7 { + opp@1100000000,975,3,7 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000_975_4_7 { + opp@1100000000,975,4,7 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000_975_3_8 { + opp@1100000000,975,3,8 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000_975_4_8 { + opp@1100000000,975,4,8 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000_1000 { + opp@1100000000,1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1100000000_1000_2_1 { + opp@1100000000,1000,2,1 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1100000000_1000_2_2 { + opp@1100000000,1000,2,2 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1100000000_1000_2_3 { + opp@1100000000,1000,2,3 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1100000000_1000_2_4 { + opp@1100000000,1000,2,4 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1100000000_1000_2_7 { + opp@1100000000,1000,2,7 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1100000000_1000_2_8 { + opp@1100000000,1000,2,8 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1100000000_1025 { + opp@1100000000,1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1100000000_1075 { + opp@1100000000,1075 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1150000000_975 { + opp@1150000000,975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1200000000_975 { + opp@1200000000,975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1200000000_1000 { + opp@1200000000,1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000_1000_3_1 { + opp@1200000000,1000,3,1 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000_1000_3_2 { + opp@1200000000,1000,3,2 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000_1000_3_3 { + opp@1200000000,1000,3,3 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000_1000_3_4 { + opp@1200000000,1000,3,4 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000_1000_3_7 { + opp@1200000000,1000,3,7 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000_1000_4_7 { + opp@1200000000,1000,4,7 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000_1000_3_8 { + opp@1200000000,1000,3,8 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000_1000_4_8 { + opp@1200000000,1000,4,8 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000_1025 { + opp@1200000000,1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1200000000_1025_2_1 { + opp@1200000000,1025,2,1 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1200000000_1025_2_2 { + opp@1200000000,1025,2,2 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1200000000_1025_2_3 { + opp@1200000000,1025,2,3 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1200000000_1025_2_4 { + opp@1200000000,1025,2,4 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1200000000_1025_2_7 { + opp@1200000000,1025,2,7 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1200000000_1025_2_8 { + opp@1200000000,1025,2,8 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1200000000_1050 { + opp@1200000000,1050 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1200000000_1075 { + opp@1200000000,1075 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1200000000_1100 { + opp@1200000000,1100 { opp-microvolt = <1100000 1100000 1250000>; }; - opp@1300000000_1000 { + opp@1300000000,1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1300000000_1000_4_7 { + opp@1300000000,1000,4,7 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1300000000_1000_4_8 { + opp@1300000000,1000,4,8 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1300000000_1025 { + opp@1300000000,1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1300000000_1025_3_1 { + opp@1300000000,1025,3,1 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1300000000_1025_3_7 { + opp@1300000000,1025,3,7 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1300000000_1025_3_8 { + opp@1300000000,1025,3,8 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1300000000_1050 { + opp@1300000000,1050 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_2_1 { + opp@1300000000,1050,2,1 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_3_2 { + opp@1300000000,1050,3,2 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_3_3 { + opp@1300000000,1050,3,3 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_3_4 { + opp@1300000000,1050,3,4 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_3_5 { + opp@1300000000,1050,3,5 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_3_6 { + opp@1300000000,1050,3,6 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_2_7 { + opp@1300000000,1050,2,7 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_2_8 { + opp@1300000000,1050,2,8 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_3_12 { + opp@1300000000,1050,3,12 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_3_13 { + opp@1300000000,1050,3,13 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1075 { + opp@1300000000,1075 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1300000000_1075_2_2 { + opp@1300000000,1075,2,2 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1300000000_1075_2_3 { + opp@1300000000,1075,2,3 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1300000000_1075_2_4 { + opp@1300000000,1075,2,4 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1300000000_1100 { + opp@1300000000,1100 { opp-microvolt = <1100000 1100000 1250000>; }; - opp@1300000000_1125 { + opp@1300000000,1125 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1300000000_1150 { + opp@1300000000,1150 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1300000000_1175 { + opp@1300000000,1175 { opp-microvolt = <1175000 1175000 1250000>; }; - opp@1400000000_1100 { + opp@1400000000,1100 { opp-microvolt = <1100000 1100000 1250000>; }; - opp@1400000000_1125 { + opp@1400000000,1125 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1400000000_1150 { + opp@1400000000,1150 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1400000000_1150_2_4 { + opp@1400000000,1150,2,4 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1400000000_1175 { + opp@1400000000,1175 { opp-microvolt = <1175000 1175000 1250000>; }; - opp@1400000000_1237 { + opp@1400000000,1237 { opp-microvolt = <1237000 1237000 1250000>; }; - opp@1500000000_1125 { + opp@1500000000,1125 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1500000000_1125_4_5 { + opp@1500000000,1125,4,5 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1500000000_1125_4_6 { + opp@1500000000,1125,4,6 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1500000000_1125_4_12 { + opp@1500000000,1125,4,12 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1500000000_1125_4_13 { + opp@1500000000,1125,4,13 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1500000000_1150 { + opp@1500000000,1150 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1500000000_1150_3_5 { + opp@1500000000,1150,3,5 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1500000000_1150_3_6 { + opp@1500000000,1150,3,6 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1500000000_1150_3_12 { + opp@1500000000,1150,3,12 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1500000000_1150_3_13 { + opp@1500000000,1150,3,13 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1500000000_1200 { + opp@1500000000,1200 { opp-microvolt = <1200000 1200000 1250000>; }; - opp@1500000000_1237 { + opp@1500000000,1237 { opp-microvolt = <1237000 1237000 1250000>; }; - opp@1600000000_1212 { + opp@1600000000,1212 { opp-microvolt = <1212000 1212000 1250000>; }; - opp@1600000000_1237 { + opp@1600000000,1237 { opp-microvolt = <1237000 1237000 1250000>; }; - opp@1700000000_1212 { + opp@1700000000,1212 { opp-microvolt = <1212000 1212000 1250000>; }; - opp@1700000000_1237 { + opp@1700000000,1237 { opp-microvolt = <1237000 1237000 1250000>; }; }; diff --git a/arch/arm/boot/dts/tegra30-cpu-opp.dtsi b/arch/arm/boot/dts/tegra30-cpu-opp.dtsi index d64fc262585e..8e434f6713cd 100644 --- a/arch/arm/boot/dts/tegra30-cpu-opp.dtsi +++ b/arch/arm/boot/dts/tegra30-cpu-opp.dtsi @@ -5,1195 +5,1195 @@ compatible = "operating-points-v2"; opp-shared; - opp@51000000_800 { + opp@51000000,800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x31FE>; opp-hz = /bits/ 64 <51000000>; }; - opp@51000000_850 { + opp@51000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C01>; opp-hz = /bits/ 64 <51000000>; }; - opp@51000000_912 { + opp@51000000,912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <51000000>; }; - opp@102000000_800 { + opp@102000000,800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x31FE>; opp-hz = /bits/ 64 <102000000>; }; - opp@102000000_850 { + opp@102000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C01>; opp-hz = /bits/ 64 <102000000>; }; - opp@102000000_912 { + opp@102000000,912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <102000000>; }; - opp@204000000_800 { + opp@204000000,800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x31FE>; opp-hz = /bits/ 64 <204000000>; }; - opp@204000000_850 { + opp@204000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C01>; opp-hz = /bits/ 64 <204000000>; }; - opp@204000000_912 { + opp@204000000,912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <204000000>; }; - opp@312000000_850 { + opp@312000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C00>; opp-hz = /bits/ 64 <312000000>; }; - opp@312000000_912 { + opp@312000000,912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <312000000>; }; - opp@340000000_800 { + opp@340000000,800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0192>; opp-hz = /bits/ 64 <340000000>; }; - opp@340000000_850 { + opp@340000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0F 0x0001>; opp-hz = /bits/ 64 <340000000>; }; - opp@370000000_800 { + opp@370000000,800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x306C>; opp-hz = /bits/ 64 <370000000>; }; - opp@456000000_850 { + opp@456000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C00>; opp-hz = /bits/ 64 <456000000>; }; - opp@456000000_912 { + opp@456000000,912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <456000000>; }; - opp@475000000_800 { + opp@475000000,800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x31FE>; opp-hz = /bits/ 64 <475000000>; }; - opp@475000000_850 { + opp@475000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0F 0x0001>; opp-hz = /bits/ 64 <475000000>; }; - opp@475000000_850_0_1 { + opp@475000000,850,0,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0002>; opp-hz = /bits/ 64 <475000000>; }; - opp@475000000_850_0_4 { + opp@475000000,850,0,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0010>; opp-hz = /bits/ 64 <475000000>; }; - opp@475000000_850_0_7 { + opp@475000000,850,0,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0080>; opp-hz = /bits/ 64 <475000000>; }; - opp@475000000_850_0_8 { + opp@475000000,850,0,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0100>; opp-hz = /bits/ 64 <475000000>; }; - opp@608000000_850 { + opp@608000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0400>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000_912 { + opp@608000000,912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <608000000>; }; - opp@620000000_850 { + opp@620000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x306C>; opp-hz = /bits/ 64 <620000000>; }; - opp@640000000_850 { + opp@640000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0F 0x0001>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_1_1 { + opp@640000000,850,1,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0002>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_2_1 { + opp@640000000,850,2,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_3_1 { + opp@640000000,850,3,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0002>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_1_4 { + opp@640000000,850,1,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0010>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_2_4 { + opp@640000000,850,2,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_3_4 { + opp@640000000,850,3,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0010>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_1_7 { + opp@640000000,850,1,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0080>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_2_7 { + opp@640000000,850,2,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0080>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_3_7 { + opp@640000000,850,3,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0080>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_4_7 { + opp@640000000,850,4,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0080>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_1_8 { + opp@640000000,850,1,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0100>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_2_8 { + opp@640000000,850,2,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0100>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_3_8 { + opp@640000000,850,3,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0100>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_4_8 { + opp@640000000,850,4,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0100>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_900 { + opp@640000000,900 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <640000000>; }; - opp@760000000_850 { + opp@760000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x3461>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850_3_1 { + opp@760000000,850,3,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0002>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850_3_2 { + opp@760000000,850,3,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850_3_3 { + opp@760000000,850,3,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0008>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850_3_4 { + opp@760000000,850,3,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0010>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850_3_7 { + opp@760000000,850,3,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0080>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850_4_7 { + opp@760000000,850,4,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0080>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850_3_8 { + opp@760000000,850,3,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0100>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850_4_8 { + opp@760000000,850,4,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0100>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850_0_10 { + opp@760000000,850,0,10 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0400>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900 { + opp@760000000,900 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_1_1 { + opp@760000000,900,1,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0002>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_2_1 { + opp@760000000,900,2,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_1_2 { + opp@760000000,900,1,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0004>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_2_2 { + opp@760000000,900,2,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_1_3 { + opp@760000000,900,1,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0008>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_2_3 { + opp@760000000,900,2,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0008>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_1_4 { + opp@760000000,900,1,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0010>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_2_4 { + opp@760000000,900,2,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_1_7 { + opp@760000000,900,1,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0080>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_2_7 { + opp@760000000,900,2,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0080>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_1_8 { + opp@760000000,900,1,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0100>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_2_8 { + opp@760000000,900,2,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0100>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_912 { + opp@760000000,912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_975 { + opp@760000000,975 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <760000000>; }; - opp@816000000_850 { + opp@816000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0400>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000_912 { + opp@816000000,912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <816000000>; }; - opp@860000000_850 { + opp@860000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0C 0x0001>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900 { + opp@860000000,900 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0001>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_2_1 { + opp@860000000,900,2,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_3_1 { + opp@860000000,900,3,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0002>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_2_2 { + opp@860000000,900,2,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_3_2 { + opp@860000000,900,3,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_2_3 { + opp@860000000,900,2,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0008>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_3_3 { + opp@860000000,900,3,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0008>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_2_4 { + opp@860000000,900,2,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_3_4 { + opp@860000000,900,3,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0010>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_2_7 { + opp@860000000,900,2,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0080>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_3_7 { + opp@860000000,900,3,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0080>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_4_7 { + opp@860000000,900,4,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0080>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_2_8 { + opp@860000000,900,2,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0100>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_3_8 { + opp@860000000,900,3,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0100>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_4_8 { + opp@860000000,900,4,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0100>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_975 { + opp@860000000,975 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_975_1_1 { + opp@860000000,975,1,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0002>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_975_1_2 { + opp@860000000,975,1,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0004>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_975_1_3 { + opp@860000000,975,1,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0008>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_975_1_4 { + opp@860000000,975,1,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0010>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_975_1_7 { + opp@860000000,975,1,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0080>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_975_1_8 { + opp@860000000,975,1,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0100>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_1000 { + opp@860000000,1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <860000000>; }; - opp@910000000_900 { + opp@910000000,900 { clock-latency-ns = <100000>; opp-supported-hw = <0x18 0x3060>; opp-hz = /bits/ 64 <910000000>; }; - opp@1000000000_900 { + opp@1000000000,900 { clock-latency-ns = <100000>; opp-supported-hw = <0x0C 0x0001>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975 { + opp@1000000000,975 { clock-latency-ns = <100000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_2_1 { + opp@1000000000,975,2,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_3_1 { + opp@1000000000,975,3,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0002>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_2_2 { + opp@1000000000,975,2,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_3_2 { + opp@1000000000,975,3,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_2_3 { + opp@1000000000,975,2,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0008>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_3_3 { + opp@1000000000,975,3,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0008>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_2_4 { + opp@1000000000,975,2,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_3_4 { + opp@1000000000,975,3,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0010>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_2_7 { + opp@1000000000,975,2,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0080>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_3_7 { + opp@1000000000,975,3,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0080>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_4_7 { + opp@1000000000,975,4,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0080>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_2_8 { + opp@1000000000,975,2,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0100>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_3_8 { + opp@1000000000,975,3,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0100>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_4_8 { + opp@1000000000,975,4,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0100>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_1000 { + opp@1000000000,1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x019E>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_1025 { + opp@1000000000,1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1100000000_900 { + opp@1100000000,900 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0001>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_975 { + opp@1100000000,975 { clock-latency-ns = <100000>; opp-supported-hw = <0x06 0x0001>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_975_3_1 { + opp@1100000000,975,3,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0002>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_975_3_2 { + opp@1100000000,975,3,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_975_3_3 { + opp@1100000000,975,3,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0008>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_975_3_4 { + opp@1100000000,975,3,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0010>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_975_3_7 { + opp@1100000000,975,3,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0080>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_975_4_7 { + opp@1100000000,975,4,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0080>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_975_3_8 { + opp@1100000000,975,3,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0100>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_975_4_8 { + opp@1100000000,975,4,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0100>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_1000 { + opp@1100000000,1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_1000_2_1 { + opp@1100000000,1000,2,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_1000_2_2 { + opp@1100000000,1000,2,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_1000_2_3 { + opp@1100000000,1000,2,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0008>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_1000_2_4 { + opp@1100000000,1000,2,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_1000_2_7 { + opp@1100000000,1000,2,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0080>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_1000_2_8 { + opp@1100000000,1000,2,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0100>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_1025 { + opp@1100000000,1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x019E>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_1075 { + opp@1100000000,1075 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1150000000_975 { + opp@1150000000,975 { clock-latency-ns = <100000>; opp-supported-hw = <0x18 0x3060>; opp-hz = /bits/ 64 <1150000000>; }; - opp@1200000000_975 { + opp@1200000000,975 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0001>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1000 { + opp@1200000000,1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1000_3_1 { + opp@1200000000,1000,3,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0002>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1000_3_2 { + opp@1200000000,1000,3,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1000_3_3 { + opp@1200000000,1000,3,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0008>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1000_3_4 { + opp@1200000000,1000,3,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0010>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1000_3_7 { + opp@1200000000,1000,3,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0080>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1000_4_7 { + opp@1200000000,1000,4,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0080>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1000_3_8 { + opp@1200000000,1000,3,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0100>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1000_4_8 { + opp@1200000000,1000,4,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0100>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1025 { + opp@1200000000,1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0001>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1025_2_1 { + opp@1200000000,1025,2,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1025_2_2 { + opp@1200000000,1025,2,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1025_2_3 { + opp@1200000000,1025,2,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0008>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1025_2_4 { + opp@1200000000,1025,2,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1025_2_7 { + opp@1200000000,1025,2,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0080>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1025_2_8 { + opp@1200000000,1025,2,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0100>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1050 { + opp@1200000000,1050 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x019E>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1075 { + opp@1200000000,1075 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1100 { + opp@1200000000,1100 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1300000000_1000 { + opp@1300000000,1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0001>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1000_4_7 { + opp@1300000000,1000,4,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0080>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1000_4_8 { + opp@1300000000,1000,4,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0100>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1025 { + opp@1300000000,1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1025_3_1 { + opp@1300000000,1025,3,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0002>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1025_3_7 { + opp@1300000000,1025,3,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0080>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1025_3_8 { + opp@1300000000,1025,3,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0100>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050 { + opp@1300000000,1050 { clock-latency-ns = <100000>; opp-supported-hw = <0x12 0x3061>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_2_1 { + opp@1300000000,1050,2,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_3_2 { + opp@1300000000,1050,3,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_3_3 { + opp@1300000000,1050,3,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0008>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_3_4 { + opp@1300000000,1050,3,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0010>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_3_5 { + opp@1300000000,1050,3,5 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0020>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_3_6 { + opp@1300000000,1050,3,6 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0040>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_2_7 { + opp@1300000000,1050,2,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0080>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_2_8 { + opp@1300000000,1050,2,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0100>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_3_12 { + opp@1300000000,1050,3,12 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x1000>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_3_13 { + opp@1300000000,1050,3,13 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x2000>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1075 { + opp@1300000000,1075 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0182>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1075_2_2 { + opp@1300000000,1075,2,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1075_2_3 { + opp@1300000000,1075,2,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0008>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1075_2_4 { + opp@1300000000,1075,2,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1100 { + opp@1300000000,1100 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x001C>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1125 { + opp@1300000000,1125 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1150 { + opp@1300000000,1150 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0182>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1175 { + opp@1300000000,1175 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0010>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1400000000_1100 { + opp@1400000000,1100 { clock-latency-ns = <100000>; opp-supported-hw = <0x18 0x307C>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000_1125 { + opp@1400000000,1125 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x000C>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000_1150 { + opp@1400000000,1150 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x000C>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000_1150_2_4 { + opp@1400000000,1150,2,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000_1175 { + opp@1400000000,1175 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0010>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000_1237 { + opp@1400000000,1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0010>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1500000000_1125 { + opp@1500000000,1125 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0010>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1125_4_5 { + opp@1500000000,1125,4,5 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0020>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1125_4_6 { + opp@1500000000,1125,4,6 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0040>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1125_4_12 { + opp@1500000000,1125,4,12 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x1000>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1125_4_13 { + opp@1500000000,1125,4,13 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x2000>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1150 { + opp@1500000000,1150 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1150_3_5 { + opp@1500000000,1150,3,5 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0020>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1150_3_6 { + opp@1500000000,1150,3,6 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0040>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1150_3_12 { + opp@1500000000,1150,3,12 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x1000>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1150_3_13 { + opp@1500000000,1150,3,13 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x2000>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1200 { + opp@1500000000,1200 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0010>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1237 { + opp@1500000000,1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0010>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1600000000_1212 { + opp@1600000000,1212 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x3060>; opp-hz = /bits/ 64 <1600000000>; }; - opp@1600000000_1237 { + opp@1600000000,1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x3060>; opp-hz = /bits/ 64 <1600000000>; }; - opp@1700000000_1212 { + opp@1700000000,1212 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x3060>; opp-hz = /bits/ 64 <1700000000>; }; - opp@1700000000_1237 { + opp@1700000000,1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x3060>; opp-hz = /bits/ 64 <1700000000>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index d2d05f1da274..aeae8c092d41 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -20,12 +20,12 @@ pcie@3000 { compatible = "nvidia,tegra30-pcie"; device_type = "pci"; - reg = <0x00003000 0x00000800 /* PADS registers */ - 0x00003800 0x00000200 /* AFI registers */ - 0x10000000 0x10000000>; /* configuration space */ + reg = <0x00003000 0x00000800>, /* PADS registers */ + <0x00003800 0x00000200>, /* AFI registers */ + <0x10000000 0x10000000>; /* configuration space */ reg-names = "pads", "afi", "cs"; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ - GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ interrupt-names = "intr", "msi"; #interrupt-cells = <1>; @@ -36,12 +36,12 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ - 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ - 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ - 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ - 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ + ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */ + <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */ + <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */ + <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */ + <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */ + <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ clocks = <&tegra_car TEGRA30_CLK_PCIE>, <&tegra_car TEGRA30_CLK_AFI>, @@ -97,25 +97,27 @@ }; }; - iram@40000000 { + sram@40000000 { compatible = "mmio-sram"; reg = <0x40000000 0x40000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40000000 0x40000>; - vde_pool: vde@400 { + vde_pool: sram@400 { reg = <0x400 0x3fc00>; pool; }; }; host1x@50000000 { - compatible = "nvidia,tegra30-host1x", "simple-bus"; + compatible = "nvidia,tegra30-host1x"; reg = <0x50000000 0x00024000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ + interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA30_CLK_HOST1X>; + clock-names = "host1x"; resets = <&tegra_car 28>; reset-names = "host1x"; iommus = <&mc TEGRA_SWGROUP_HC>; @@ -183,8 +185,8 @@ gr3d@54180000 { compatible = "nvidia,tegra30-gr3d"; reg = <0x54180000 0x00040000>; - clocks = <&tegra_car TEGRA30_CLK_GR3D - &tegra_car TEGRA30_CLK_GR3D2>; + clocks = <&tegra_car TEGRA30_CLK_GR3D>, + <&tegra_car TEGRA30_CLK_GR3D2>; clock-names = "3d", "3d2"; resets = <&tegra_car 24>, <&tegra_car 98>; @@ -195,7 +197,7 @@ }; dc@54200000 { - compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra30-dc"; reg = <0x54200000 0x00040000>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_DISP1>, @@ -255,11 +257,24 @@ dsi@54300000 { compatible = "nvidia,tegra30-dsi"; reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA30_CLK_DSIA>; + clocks = <&tegra_car TEGRA30_CLK_DSIA>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; resets = <&tegra_car 48>; reset-names = "dsi"; status = "disabled"; }; + + dsi@54400000 { + compatible = "nvidia,tegra30-dsi"; + reg = <0x54400000 0x00040000>; + clocks = <&tegra_car TEGRA30_CLK_DSIB>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; + resets = <&tegra_car 84>; + reset-names = "dsi"; + status = "disabled"; + }; }; timer@50040600 { @@ -273,8 +288,8 @@ intc: interrupt-controller@50041000 { compatible = "arm,cortex-a9-gic"; - reg = <0x50041000 0x1000 - 0x50040100 0x0100>; + reg = <0x50041000 0x1000>, + <0x50040100 0x0100>; interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&intc>; @@ -404,15 +419,15 @@ vde@6001a000 { compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde"; - reg = <0x6001a000 0x1000 /* Syntax Engine */ - 0x6001b000 0x1000 /* Video Bitstream Engine */ - 0x6001c000 0x100 /* Macroblock Engine */ - 0x6001c200 0x100 /* Post-processing Engine */ - 0x6001c400 0x100 /* Motion Compensation Engine */ - 0x6001c600 0x100 /* Transform Engine */ - 0x6001c800 0x100 /* Pixel prediction block */ - 0x6001ca00 0x100 /* Video DMA */ - 0x6001d800 0x400>; /* Video frame controls */ + reg = <0x6001a000 0x1000>, /* Syntax Engine */ + <0x6001b000 0x1000>, /* Video Bitstream Engine */ + <0x6001c000 0x100>, /* Macroblock Engine */ + <0x6001c200 0x100>, /* Post-processing Engine */ + <0x6001c400 0x100>, /* Motion Compensation Engine */ + <0x6001c600 0x100>, /* Transform Engine */ + <0x6001c800 0x100>, /* Pixel prediction block */ + <0x6001ca00 0x100>, /* Video DMA */ + <0x6001d800 0x400>; /* Video frame controls */ reg-names = "sxe", "bsev", "mbe", "ppe", "mce", "tfe", "ppb", "vdma", "frameid"; iram = <&vde_pool>; /* IRAM region */ @@ -428,14 +443,14 @@ apbmisc@70000800 { compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; - reg = <0x70000800 0x64 /* Chip revision */ - 0x70000008 0x04>; /* Strapping options */ + reg = <0x70000800 0x64>, /* Chip revision */ + <0x70000008 0x04>; /* Strapping options */ }; pinmux: pinmux@70000868 { compatible = "nvidia,tegra30-pinmux"; - reg = <0x70000868 0xd4 /* Pad control registers */ - 0x70003000 0x3e4>; /* Mux registers */ + reg = <0x70000868 0x0d4>, /* Pad control registers */ + <0x70003000 0x3e4>; /* Mux registers */ }; /* @@ -770,8 +785,8 @@ ahub@70080000 { compatible = "nvidia,tegra30-ahub"; - reg = <0x70080000 0x200 - 0x70080200 0x100>; + reg = <0x70080000 0x200>, + <0x70080200 0x100>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, <&tegra_car TEGRA30_CLK_APBIF>; @@ -851,41 +866,45 @@ }; }; - sdhci@78000000 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + mmc@78000000 { + compatible = "nvidia,tegra30-sdhci"; reg = <0x78000000 0x200>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; + clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; status = "disabled"; }; - sdhci@78000200 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + mmc@78000200 { + compatible = "nvidia,tegra30-sdhci"; reg = <0x78000200 0x200>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; + clock-names = "sdhci"; resets = <&tegra_car 9>; reset-names = "sdhci"; status = "disabled"; }; - sdhci@78000400 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + mmc@78000400 { + compatible = "nvidia,tegra30-sdhci"; reg = <0x78000400 0x200>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; status = "disabled"; }; - sdhci@78000600 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + mmc@78000600 { + compatible = "nvidia,tegra30-sdhci"; reg = <0x78000600 0x200>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; + clock-names = "sdhci"; resets = <&tegra_car 15>; reset-names = "sdhci"; status = "disabled"; @@ -906,7 +925,8 @@ phy1: usb-phy@7d000000 { compatible = "nvidia,tegra30-usb-phy"; - reg = <0x7d000000 0x4000 0x7d000000 0x4000>; + reg = <0x7d000000 0x4000>, + <0x7d000000 0x4000>; phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USBD>, <&tegra_car TEGRA30_CLK_PLL_U>, @@ -914,6 +934,7 @@ clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 22>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <9>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; @@ -943,7 +964,8 @@ phy2: usb-phy@7d004000 { compatible = "nvidia,tegra30-usb-phy"; - reg = <0x7d004000 0x4000 0x7d000000 0x4000>; + reg = <0x7d004000 0x4000>, + <0x7d000000 0x4000>; phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USB2>, <&tegra_car TEGRA30_CLK_PLL_U>, @@ -951,6 +973,7 @@ clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <9>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; @@ -979,7 +1002,8 @@ phy3: usb-phy@7d008000 { compatible = "nvidia,tegra30-usb-phy"; - reg = <0x7d008000 0x4000 0x7d000000 0x4000>; + reg = <0x7d008000 0x4000>, + <0x7d000000 0x4000>; phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USB3>, <&tegra_car TEGRA30_CLK_PLL_U>, @@ -987,6 +1011,7 @@ clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 59>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; diff --git a/arch/arm/boot/dts/twl6030_omap4.dtsi b/arch/arm/boot/dts/twl6030_omap4.dtsi index fc498d0bde8b..5730e46b0067 100644 --- a/arch/arm/boot/dts/twl6030_omap4.dtsi +++ b/arch/arm/boot/dts/twl6030_omap4.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ &twl { diff --git a/arch/arm/boot/dts/uniphier-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ld4-ref.dts index f2d060f403cc..c46c2e8a10a7 100644 --- a/arch/arm/boot/dts/uniphier-ld4-ref.dts +++ b/arch/arm/boot/dts/uniphier-ld4-ref.dts @@ -20,7 +20,7 @@ aliases { serial0 = &serial0; - serial1 = &serial1; + serial1 = &serialsc; serial2 = &serial2; serial3 = &serial3; i2c0 = &i2c0; @@ -39,6 +39,10 @@ interrupts = <1 8>; }; +&serialsc { + interrupts = <1 8>; +}; + &serial0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ld6b-ref.dts index 079cadc11e6c..5bc7fe11b517 100644 --- a/arch/arm/boot/dts/uniphier-ld6b-ref.dts +++ b/arch/arm/boot/dts/uniphier-ld6b-ref.dts @@ -22,6 +22,7 @@ serial0 = &serial0; serial1 = &serial1; serial2 = &serial2; + serial3 = &serialsc; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -42,6 +43,10 @@ interrupts = <4 8>; }; +&serialsc { + interrupts = <4 8>; +}; + &serial0 { status = "okay"; }; @@ -76,7 +81,7 @@ }; &mdio { - ethphy: ethphy@0 { + ethphy: ethernet-phy@0 { reg = <0>; }; }; diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi index bfdfb764b25b..c0fd029b37e5 100644 --- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi +++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi @@ -126,6 +126,11 @@ function = "nand"; }; + pinctrl_pcie: pcie { + groups = "pcie"; + function = "pcie"; + }; + pinctrl_sd: sd { groups = "sd"; function = "sd"; diff --git a/arch/arm/boot/dts/uniphier-pro4-ace.dts b/arch/arm/boot/dts/uniphier-pro4-ace.dts index 64246fad325c..27ff2b7b9d0e 100644 --- a/arch/arm/boot/dts/uniphier-pro4-ace.dts +++ b/arch/arm/boot/dts/uniphier-pro4-ace.dts @@ -87,7 +87,7 @@ }; &mdio { - ethphy: ethphy@1 { + ethphy: ethernet-phy@1 { reg = <1>; }; }; diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/uniphier-pro4-ref.dts index 181442c48532..3b9b61314d01 100644 --- a/arch/arm/boot/dts/uniphier-pro4-ref.dts +++ b/arch/arm/boot/dts/uniphier-pro4-ref.dts @@ -22,7 +22,7 @@ serial0 = &serial0; serial1 = &serial1; serial2 = &serial2; - serial3 = &serial3; + serial3 = &serialsc; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -42,6 +42,10 @@ interrupts = <2 8>; }; +&serialsc { + interrupts = <2 8>; +}; + &serial0 { status = "okay"; }; @@ -84,7 +88,7 @@ }; &mdio { - ethphy: ethphy@0 { + ethphy: ethernet-phy@0 { reg = <0>; }; }; diff --git a/arch/arm/boot/dts/uniphier-pro4-sanji.dts b/arch/arm/boot/dts/uniphier-pro4-sanji.dts index 5396556dee58..7b6faf2e795e 100644 --- a/arch/arm/boot/dts/uniphier-pro4-sanji.dts +++ b/arch/arm/boot/dts/uniphier-pro4-sanji.dts @@ -82,7 +82,7 @@ }; &mdio { - ethphy: ethphy@1 { + ethphy: ethernet-phy@1 { reg = <1>; }; }; diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index feadb4a378eb..3525125832dd 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -613,6 +613,36 @@ }; }; + pcie_ep: pcie-ep@66000000 { + compatible = "socionext,uniphier-pro5-pcie-ep", + "snps,dw-pcie-ep"; + status = "disabled"; + reg-names = "dbi", "dbi2", "link", "addr_space"; + reg = <0x66000000 0x1000>, <0x66001000 0x1000>, + <0x66010000 0x10000>, <0x67000000 0x400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 24>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 24>; + num-ib-windows = <16>; + num-ob-windows = <16>; + num-lanes = <4>; + phy-names = "pcie-phy"; + phys = <&pcie_phy>; + }; + + pcie_phy: phy@66038000 { + compatible = "socionext,uniphier-pro5-pcie-phy"; + reg = <0x66038000 0x4000>; + #phy-cells = <0>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 24>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 24>; + }; + nand: nand-controller@68000000 { compatible = "socionext,uniphier-denali-nand-v5b"; status = "disabled"; diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts index 8e9ac579aa9a..759384b60663 100644 --- a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts +++ b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts @@ -87,7 +87,7 @@ }; &mdio { - ethphy: ethphy@1 { + ethphy: ethernet-phy@1 { reg = <1>; }; }; diff --git a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts index 8eacc7bdecb7..7e08a459f7d8 100644 --- a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts +++ b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts @@ -88,7 +88,7 @@ }; &mdio { - ethphy: ethphy@1 { + ethphy: ethernet-phy@1 { reg = <1>; }; }; diff --git a/arch/arm/boot/dts/uniphier-sld8-ref.dts b/arch/arm/boot/dts/uniphier-sld8-ref.dts index cf9ea0b15065..6db949ec7411 100644 --- a/arch/arm/boot/dts/uniphier-sld8-ref.dts +++ b/arch/arm/boot/dts/uniphier-sld8-ref.dts @@ -20,7 +20,7 @@ aliases { serial0 = &serial0; - serial1 = &serial1; + serial1 = &serialsc; serial2 = &serial2; serial3 = &serial3; i2c0 = &i2c0; @@ -39,6 +39,10 @@ interrupts = <0 8>; }; +&serialsc { + interrupts = <0 8>; +}; + &serial0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/uniphier-support-card.dtsi b/arch/arm/boot/dts/uniphier-support-card.dtsi index bf441c2eff79..444802fee9fb 100644 --- a/arch/arm/boot/dts/uniphier-support-card.dtsi +++ b/arch/arm/boot/dts/uniphier-support-card.dtsi @@ -8,26 +8,19 @@ &system_bus { status = "okay"; ranges = <1 0x00000000 0x42000000 0x02000000>; + interrupt-parent = <&gpio>; - support_card: support-card@1,1f00000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 1 0x01f00000 0x00100000>; - interrupt-parent = <&gpio>; - - ethsc: ethernet@0 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <0x00000000 0x1000>; - phy-mode = "mii"; - reg-io-width = <4>; - }; + ethsc: ethernet@1,1f00000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <1 0x01f00000 0x1000>; + phy-mode = "mii"; + reg-io-width = <4>; + }; - serialsc: uart@b0000 { - compatible = "ns16550a"; - reg = <0x000b0000 0x20>; - clock-frequency = <12288000>; - reg-shift = <1>; - }; + serialsc: serial@1,1fb0000 { + compatible = "ns16550a"; + reg = <1 0x01fb0000 0x20>; + clock-frequency = <12288000>; + reg-shift = <1>; }; }; diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index e6308fb76183..a88ee5294d35 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -100,79 +100,6 @@ }; }; - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* MCC static memory clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk0"; - }; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 65000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - v2m_oscclk2: oscclk2 { - /* IO FPGA peripheral clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <24000000 24000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk2"; - }; - - volt-vio { - /* Logic level voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO"; - regulator-always-on; - label = "VIO"; - }; - - temp-mcc { - /* MCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "MCC"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; - bus@8000000 { motherboard-bus { model = "V2M-P1"; @@ -435,6 +362,79 @@ }; }; }; + + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + oscclk0 { + /* MCC static memory clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <25000000 60000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk0"; + }; + + v2m_oscclk1: oscclk1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 65000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + v2m_oscclk2: oscclk2 { + /* IO FPGA peripheral clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <24000000 24000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk2"; + }; + + volt-vio { + /* Logic level voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VIO"; + regulator-always-on; + label = "VIO"; + }; + + temp-mcc { + /* MCC internal operating temperature */ + compatible = "arm,vexpress-temp"; + arm,vexpress-sysreg,func = <4 0>; + label = "MCC"; + }; + + reset { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts index ce1920c052fc..64e0e9509226 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -158,6 +158,8 @@ mdio1: mdio { #address-cells = <1>; #size-cells = <0>; + clock-frequency = <12500000>; + suppress-preamble; status = "okay"; switch0: switch0@0 { diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts index 778e02c000d1..de79dcfd32e6 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts @@ -164,7 +164,7 @@ port@9 { reg = <9>; label = "sff2"; - phy-mode = "sgmii"; + phy-mode = "1000base-x"; managed = "in-band-status"; sfp = <&sff2>; }; diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi index 95d0060fb56c..f8299f33a692 100644 --- a/arch/arm/boot/dts/vf610-zii-dev.dtsi +++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi @@ -137,6 +137,8 @@ mdio1: mdio { #address-cells = <1>; #size-cells = <0>; + clock-frequency = <12500000>; + suppress-preamble; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts index b642520199ba..040a1f8b6130 100644 --- a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts +++ b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts @@ -186,7 +186,7 @@ port@2 { reg = <2>; label = "eth_fc_1000_2"; - phy-mode = "sgmii"; + phy-mode = "1000base-x"; managed = "in-band-status"; sfp = <&sff1>; }; @@ -194,7 +194,7 @@ port@3 { reg = <3>; label = "eth_fc_1000_3"; - phy-mode = "sgmii"; + phy-mode = "1000base-x"; managed = "in-band-status"; sfp = <&sff2>; }; @@ -202,7 +202,7 @@ port@4 { reg = <4>; label = "eth_fc_1000_4"; - phy-mode = "sgmii"; + phy-mode = "1000base-x"; managed = "in-band-status"; sfp = <&sff3>; }; @@ -210,7 +210,7 @@ port@5 { reg = <5>; label = "eth_fc_1000_5"; - phy-mode = "sgmii"; + phy-mode = "1000base-x"; managed = "in-band-status"; sfp = <&sff4>; }; @@ -218,7 +218,7 @@ port@6 { reg = <6>; label = "eth_fc_1000_6"; - phy-mode = "sgmii"; + phy-mode = "1000base-x"; managed = "in-band-status"; sfp = <&sff5>; }; @@ -226,7 +226,7 @@ port@7 { reg = <7>; label = "eth_fc_1000_7"; - phy-mode = "sgmii"; + phy-mode = "1000base-x"; managed = "in-band-status"; sfp = <&sff6>; }; @@ -234,7 +234,7 @@ port@9 { reg = <9>; label = "eth_fc_1000_1"; - phy-mode = "sgmii"; + phy-mode = "1000base-x"; managed = "in-band-status"; sfp = <&sff0>; }; @@ -269,7 +269,7 @@ port@2 { reg = <2>; label = "eth_fc_1000_8"; - phy-mode = "sgmii"; + phy-mode = "1000base-x"; managed = "in-band-status"; sfp = <&sff7>; }; @@ -277,7 +277,7 @@ port@3 { reg = <3>; label = "eth_fc_1000_9"; - phy-mode = "sgmii"; + phy-mode = "1000base-x"; managed = "in-band-status"; sfp = <&sff8>; }; @@ -285,7 +285,7 @@ port@4 { reg = <4>; label = "eth_fc_1000_10"; - phy-mode = "sgmii"; + phy-mode = "1000base-x"; managed = "in-band-status"; sfp = <&sff9>; }; diff --git a/arch/arm/boot/dts/vf610-zii-spb4.dts b/arch/arm/boot/dts/vf610-zii-spb4.dts index 55b4201e27f6..9e5187ba3fa6 100644 --- a/arch/arm/boot/dts/vf610-zii-spb4.dts +++ b/arch/arm/boot/dts/vf610-zii-spb4.dts @@ -119,6 +119,8 @@ mdio1: mdio { #address-cells = <1>; #size-cells = <0>; + clock-frequency = <12500000>; + suppress-preamble; status = "okay"; switch0: switch0@0 { @@ -207,6 +209,18 @@ }; }; +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + watchdog@38 { + compatible = "zii,rave-wdt"; + reg = <0x38>; + }; +}; + &snvsrtc { status = "disabled"; }; @@ -324,6 +338,13 @@ >; }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + VF610_PAD_PTB16__I2C1_SCL 0x37ff + VF610_PAD_PTB17__I2C1_SDA 0x37ff + >; + }; + pinctrl_leds_debug: pinctrl-leds-debug { fsl,pins = < VF610_PAD_PTD3__GPIO_82 0x31c2 diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts index a6c22a79779e..569614b08f04 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts @@ -81,6 +81,8 @@ non-removable; no-1-8-v; keep-power-in-suspend; + no-sdio; + no-sd; status = "okay"; }; @@ -88,6 +90,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1>; bus-width = <4>; + no-sdio; status = "okay"; }; @@ -105,6 +108,8 @@ mdio1: mdio { #address-cells = <1>; #size-cells = <0>; + clock-frequency = <12500000>; + suppress-preamble; status = "okay"; switch0: switch0@0 { diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index 3d05c894bdc0..b6b0f302b7b4 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -133,6 +133,8 @@ mdio1: mdio { #address-cells = <1>; #size-cells = <0>; + clock-frequency = <12500000>; + suppress-preamble; status = "okay"; switch0: switch0@0 { @@ -226,6 +228,18 @@ }; }; +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + watchdog@38 { + compatible = "zii,rave-wdt"; + reg = <0x38>; + }; +}; + &snvsrtc { status = "disabled"; }; diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index 7fd39817f8ab..956182d08e74 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -10,7 +10,7 @@ }; &aips0 { - L2: l2-cache@40006000 { + L2: cache-controller@40006000 { compatible = "arm,pl310-cache"; reg = <0x40006000 0x1000>; cache-unified; diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index 2d547e7b21ad..0fe03aa0367f 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -729,6 +729,28 @@ dma-names = "rx","tx"; status = "disabled"; }; + + crypto: crypto@400f0000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x400f0000 0x9000>; + ranges = <0 0x400f0000 0x9000>; + clocks = <&clks VF610_CLK_CAAM>; + clock-names = "ipg"; + + sec_jr0: jr0@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr1@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; + }; + }; }; }; }; diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 374fbff8eaa6..6e8b5ff0859c 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -166,7 +166,9 @@ CONFIG_DEVFREQ_THERMAL=y CONFIG_THERMAL_EMULATION=y CONFIG_WATCHDOG=y CONFIG_S3C2410_WATCHDOG=y -CONFIG_MFD_CROS_EC=y +CONFIG_MFD_CROS_EC_DEV=y +CONFIG_CHROME_PLATFORMS=y +CONFIG_CROS_EC=y CONFIG_MFD_MAX14577=y CONFIG_MFD_MAX77686=y CONFIG_MFD_MAX77693=y diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 87e6400c436b..cb335478ac37 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -217,6 +217,7 @@ CONFIG_SPI=y CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y CONFIG_SPI_FSL_DSPI=y +CONFIG_PINCTRL_IMX8MM=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_SIOX=m CONFIG_GPIO_MAX732X=y @@ -406,6 +407,8 @@ CONFIG_STAGING=y CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_IMX_MEDIA=y CONFIG_COMMON_CLK_PWM=y +CONFIG_CLK_IMX8MM=y +CONFIG_SOC_IMX8M=y CONFIG_IIO=y CONFIG_MMA8452=y CONFIG_IMX7D_ADC=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 95543914d3c7..e9e76e32f10f 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -314,6 +314,7 @@ CONFIG_INPUT_MAX77693_HAPTIC=m CONFIG_INPUT_MAX8997_HAPTIC=m CONFIG_INPUT_CPCAP_PWRBUTTON=m CONFIG_INPUT_AXP20X_PEK=m +CONFIG_INPUT_DA9063_ONKEY=m CONFIG_INPUT_ADXL34X=m CONFIG_INPUT_STPMIC1_ONKEY=y CONFIG_SERIO_AMBAKMI=y @@ -520,6 +521,7 @@ CONFIG_TEGRA_WATCHDOG=m CONFIG_MESON_WATCHDOG=y CONFIG_DIGICOLOR_WATCHDOG=y CONFIG_RENESAS_WDT=m +CONFIG_RENESAS_RZAWDT=m CONFIG_STPMIC1_WATCHDOG=y CONFIG_BCM47XX_WDT=y CONFIG_BCM2835_WDT=y @@ -618,6 +620,7 @@ CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_VIDEO_MMP_CAMERA=m CONFIG_VIDEO_ASPEED=m CONFIG_VIDEO_STM32_DCMI=m +CONFIG_VIDEO_RENESAS_CEU=m CONFIG_VIDEO_SAMSUNG_EXYNOS4_IS=m CONFIG_VIDEO_S5P_FIMC=m CONFIG_VIDEO_S5P_MIPI_CSIS=m @@ -640,6 +643,8 @@ CONFIG_VIDEO_VIVID=m CONFIG_CEC_PLATFORM_DRIVERS=y CONFIG_CEC_SAMSUNG_S5P=m CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_ADV7604=m +CONFIG_VIDEO_ADV7604_CEC=y CONFIG_VIDEO_ML86V7667=m CONFIG_IMX_IPUV3_CORE=m CONFIG_DRM=y @@ -901,6 +906,7 @@ CONFIG_RTC_DRV_EFI=m CONFIG_RTC_DRV_DIGICOLOR=m CONFIG_RTC_DRV_S3C=m CONFIG_RTC_DRV_SA1100=m +CONFIG_RTC_DRV_SH=m CONFIG_RTC_DRV_PL031=y CONFIG_RTC_DRV_AT91RM9200=m CONFIG_RTC_DRV_AT91SAM9=m @@ -945,7 +951,7 @@ CONFIG_SERIO_NVEC_PS2=y CONFIG_NVEC_POWER=y CONFIG_NVEC_PAZ00=y CONFIG_STAGING_BOARD=y -CONFIG_MFD_CROS_EC=m +CONFIG_MFD_CROS_EC_DEV=m CONFIG_CROS_EC_I2C=m CONFIG_CROS_EC_SPI=m CONFIG_COMMON_CLK_MAX77686=y @@ -1126,3 +1132,6 @@ CONFIG_CMA_SIZE_MBYTES=64 CONFIG_PRINTK_TIME=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y +CONFIG_CHROME_PLATFORMS=y +CONFIG_CROS_EC=m +CONFIG_CROS_EC_CHARDEV=m diff --git a/arch/arm/configs/pxa_defconfig b/arch/arm/configs/pxa_defconfig index e6559e3350e6..1dc7e9d7a294 100644 --- a/arch/arm/configs/pxa_defconfig +++ b/arch/arm/configs/pxa_defconfig @@ -391,7 +391,9 @@ CONFIG_SA1100_WATCHDOG=m CONFIG_MFD_AS3711=y CONFIG_MFD_BCM590XX=m CONFIG_MFD_AXP20X=y -CONFIG_MFD_CROS_EC=m +CONFIG_MFD_CROS_EC_DEV=m +CONFIG_CHROME_PLATFORMS=y +CONFIG_CROS_EC=m CONFIG_CROS_EC_I2C=m CONFIG_CROS_EC_SPI=m CONFIG_MFD_ASIC3=y diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index 8e1f78c19920..7b7e333157fe 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -49,9 +49,14 @@ CONFIG_IP_PNP_RARP=y # CONFIG_INET6_XFRM_MODE_TUNNEL is not set # CONFIG_INET6_XFRM_MODE_BEET is not set CONFIG_IPV6_SIT_6RD=y +CONFIG_BRIDGE=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_NET_DSA=m +CONFIG_VLAN_8021Q=m CONFIG_CAN=y CONFIG_CAN_AT91=y CONFIG_CAN_M_CAN=y +CONFIG_CAN_M_CAN_PLATFORM=y CONFIG_CFG80211=y CONFIG_MAC80211=y CONFIG_MAC80211_LEDS=y @@ -80,6 +85,8 @@ CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y # CONFIG_SCSI_LOWLEVEL is not set CONFIG_NETDEVICES=y +CONFIG_NET_DSA_MICROCHIP_KSZ9477=m +CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m CONFIG_MACB=y # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_CIRRUS is not set @@ -165,6 +172,7 @@ CONFIG_SND_SOC=y CONFIG_SND_ATMEL_SOC=y CONFIG_SND_ATMEL_SOC_WM8904=y # CONFIG_HID_GENERIC is not set +CONFIG_SND_ATMEL_SOC_CLASSD=y CONFIG_SND_ATMEL_SOC_PDMIC=y CONFIG_SND_ATMEL_SOC_TSE850_PCM5142=m CONFIG_SND_ATMEL_SOC_I2S=y diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 9cf3143025e1..bbedc42bb2d9 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -13,8 +13,6 @@ CONFIG_SMP=y CONFIG_SCHED_MC=y CONFIG_NR_CPUS=8 CONFIG_HIGHMEM=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y CONFIG_KEXEC=y CONFIG_CPU_FREQ=y @@ -67,6 +65,7 @@ CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_EDT_FT5X06=y CONFIG_TOUCHSCREEN_ST1232=y CONFIG_INPUT_MISC=y +CONFIG_INPUT_DA9063_ONKEY=y CONFIG_INPUT_ADXL34X=y # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_8250=y @@ -90,6 +89,7 @@ CONFIG_PINCTRL_RZA1=y CONFIG_PINCTRL_RZA2=y CONFIG_GPIO_EM=y CONFIG_GPIO_RCAR=y +CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCF857X=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_RMOBILE=y @@ -101,6 +101,7 @@ CONFIG_RCAR_THERMAL=y CONFIG_WATCHDOG=y CONFIG_DA9063_WATCHDOG=y CONFIG_RENESAS_WDT=y +CONFIG_RENESAS_RZAWDT=y CONFIG_MFD_AS3711=y CONFIG_MFD_DA9063=y CONFIG_REGULATOR_FIXED_VOLTAGE=y @@ -109,18 +110,19 @@ CONFIG_REGULATOR_DA9210=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MAX8973=y CONFIG_MEDIA_SUPPORT=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_CONTROLLER=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_RENESAS_CEU=y CONFIG_VIDEO_RCAR_VIN=y CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_RENESAS_FDP1=y CONFIG_VIDEO_RENESAS_JPU=y CONFIG_VIDEO_RENESAS_VSP1=y -# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set CONFIG_VIDEO_ADV7180=y CONFIG_VIDEO_ADV7604=y +CONFIG_VIDEO_ADV7604_CEC=y CONFIG_VIDEO_ML86V7667=y CONFIG_DRM=y CONFIG_DRM_RCAR_DU=y @@ -168,6 +170,7 @@ CONFIG_RTC_DRV_BQ32K=y CONFIG_RTC_DRV_S35390A=y CONFIG_RTC_DRV_RX8581=y CONFIG_RTC_DRV_DA9063=y +CONFIG_RTC_DRV_SH=y CONFIG_DMADEVICES=y CONFIG_RCAR_DMAC=y CONFIG_RENESAS_USB_DMAC=y diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig index b105ce7120cc..244126172fd6 100644 --- a/arch/arm/configs/sunxi_defconfig +++ b/arch/arm/configs/sunxi_defconfig @@ -3,20 +3,19 @@ CONFIG_HIGH_RES_TIMERS=y CONFIG_CGROUPS=y CONFIG_BLK_DEV_INITRD=y CONFIG_PERF_EVENTS=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y CONFIG_ARCH_SUNXI=y CONFIG_SMP=y CONFIG_NR_CPUS=8 -CONFIG_AEABI=y CONFIG_HIGHMEM=y -CONFIG_CMA=y CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CPU_FREQ=y CONFIG_CPUFREQ_DT=y CONFIG_VFP=y CONFIG_NEON=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_CMA=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -24,9 +23,6 @@ CONFIG_INET=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_DIAG is not set # CONFIG_IPV6 is not set CONFIG_CAN=y @@ -34,14 +30,12 @@ CONFIG_CAN_SUN4I=y # CONFIG_WIRELESS is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y -CONFIG_DMA_CMA=y CONFIG_BLK_DEV_SD=y CONFIG_ATA=y CONFIG_AHCI_SUNXI=y CONFIG_NETDEVICES=y CONFIG_SUN4I_EMAC=y # CONFIG_NET_VENDOR_ARC is not set -# CONFIG_NET_CADENCE is not set # CONFIG_NET_VENDOR_BROADCOM is not set # CONFIG_NET_VENDOR_CIRRUS is not set # CONFIG_NET_VENDOR_FARADAY is not set @@ -65,6 +59,7 @@ CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_SUN4I=y CONFIG_INPUT_MISC=y CONFIG_INPUT_AXP20X_PEK=y +CONFIG_SERIO_SUN4I_PS2=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=8 @@ -95,19 +90,37 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_AXP20X=y CONFIG_REGULATOR_GPIO=y -CONFIG_MEDIA_SUPPORT=y CONFIG_RC_CORE=y CONFIG_RC_DEVICES=y CONFIG_IR_SUNXI=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_SUN4I_CSI=y +CONFIG_VIDEO_SUN6I_CSI=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_SUN8I_DEINTERLACE=y +CONFIG_VIDEO_SUN8I_ROTATE=y CONFIG_DRM=y CONFIG_DRM_SUN4I=y +CONFIG_DRM_SUN4I_HDMI_CEC=y +CONFIG_DRM_SUN8I_DW_HDMI=y +CONFIG_DRM_PANEL_LVDS=y +CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_SIMPLE_BRIDGE=y +CONFIG_DRM_LIMA=y CONFIG_FB_SIMPLE=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PWM=y CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_SOC=y CONFIG_SND_SUN4I_CODEC=y +CONFIG_SND_SUN8I_CODEC=y CONFIG_SND_SUN8I_CODEC_ANALOG=y +CONFIG_SND_SUN4I_I2S=y +CONFIG_SND_SUN4I_SPDIF=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD_PLATFORM=y @@ -132,15 +145,18 @@ CONFIG_RTC_DRV_AC100=y CONFIG_RTC_DRV_SUNXI=y CONFIG_DMADEVICES=y CONFIG_DMA_SUN6I=y +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y +CONFIG_VIDEO_SUNXI=y +CONFIG_VIDEO_SUNXI_CEDRUS=y +CONFIG_MAILBOX=y # CONFIG_IOMMU_SUPPORT is not set -CONFIG_EXTCON=y CONFIG_IIO=y CONFIG_AXP20X_ADC=y CONFIG_PWM=y CONFIG_PWM_SUN4I=y CONFIG_PHY_SUN4I_USB=y CONFIG_PHY_SUN9I_USB=y -CONFIG_NVMEM=y CONFIG_NVMEM_SUNXI_SID=y CONFIG_EXT4_FS=y CONFIG_VFAT_FS=y @@ -151,8 +167,10 @@ CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y +CONFIG_CRYPTO_DEV_SUN4I_SS=y +CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y +CONFIG_CRYPTO_DEV_SUN8I_CE=y +CONFIG_CRYPTO_DEV_SUN8I_SS=y +CONFIG_DMA_CMA=y CONFIG_PRINTK_TIME=y CONFIG_DEBUG_FS=y -CONFIG_CRYPTO_DEV_ALLWINNER=y -CONFIG_CRYPTO_DEV_SUN8I_CE=y -CONFIG_CRYPTO_DEV_SUN4I_SS=y diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index aa94369bdd0f..fff5fae0db30 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -10,6 +10,8 @@ CONFIG_RT_GROUP_SCHED=y CONFIG_CGROUP_FREEZER=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_DEBUG=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y CONFIG_BLK_DEV_INITRD=y # CONFIG_ELF_CORE is not set CONFIG_EMBEDDED=y @@ -18,11 +20,13 @@ CONFIG_SLAB=y CONFIG_ARCH_TEGRA=y CONFIG_SMP=y CONFIG_HIGHMEM=y +CONFIG_SECCOMP=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_KEXEC=y CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPUFREQ_DT=y CONFIG_CPU_IDLE=y CONFIG_ARM_TEGRA_CPUIDLE=y @@ -63,11 +67,17 @@ CONFIG_BT_RFCOMM=y CONFIG_BT_BNEP=y CONFIG_BT_HIDP=y CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_BCM=y CONFIG_CFG80211=y CONFIG_MAC80211=y CONFIG_RFKILL=y CONFIG_RFKILL_INPUT=y CONFIG_RFKILL_GPIO=y +CONFIG_NFC=y +CONFIG_NFC_HCI=y +CONFIG_NFC_SHDLC=y +CONFIG_NFC_PN544_I2C=y CONFIG_PCI=y CONFIG_PCIEPORTBUS=y CONFIG_PCI_MSI=y @@ -106,20 +116,24 @@ CONFIG_INPUT_JOYDEV=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y CONFIG_KEYBOARD_TEGRA=y +CONFIG_KEYBOARD_CAP11XX=y CONFIG_KEYBOARD_CROS_EC=y CONFIG_MOUSE_PS2_ELANTECH=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ATMEL_MXT=y +CONFIG_TOUCHSCREEN_ELAN=y CONFIG_TOUCHSCREEN_WM97XX=y # CONFIG_TOUCHSCREEN_WM9705 is not set # CONFIG_TOUCHSCREEN_WM9713 is not set CONFIG_TOUCHSCREEN_STMPE=y CONFIG_INPUT_MISC=y +CONFIG_INPUT_GPIO_VIBRA=y # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_TEGRA=y +CONFIG_SERIAL_DEV_BUS=y # CONFIG_HW_RANDOM is not set # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y @@ -131,10 +145,12 @@ CONFIG_SPI_TEGRA114=y CONFIG_SPI_TEGRA20_SFLASH=y CONFIG_SPI_TEGRA20_SLINK=y CONFIG_PINCTRL_AS3722=y +CONFIG_PINCTRL_MAX77620=y CONFIG_PINCTRL_PALMAS=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_MAX77620=y CONFIG_GPIO_PALMAS=y CONFIG_GPIO_TPS6586X=y CONFIG_GPIO_TPS65910=y @@ -142,13 +158,21 @@ CONFIG_POWER_RESET=y CONFIG_POWER_RESET_AS3722=y CONFIG_POWER_RESET_GPIO=y CONFIG_BATTERY_SBS=y +CONFIG_BATTERY_BQ27XXX=y +CONFIG_CHARGER_GPIO=y +CONFIG_CHARGER_SMB347=y CONFIG_CHARGER_TPS65090=y CONFIG_SENSORS_LM90=y CONFIG_SENSORS_LM95245=y +CONFIG_THERMAL=y +CONFIG_THERMAL_STATISTICS=y +CONFIG_CPU_THERMAL=y CONFIG_WATCHDOG=y +CONFIG_MAX77620_WATCHDOG=y CONFIG_TEGRA_WATCHDOG=y CONFIG_MFD_AS3722=y -CONFIG_MFD_CROS_EC=y +CONFIG_MFD_CROS_EC_DEV=y +CONFIG_MFD_MAX77620=y CONFIG_MFD_MAX8907=y CONFIG_MFD_STMPE=y CONFIG_MFD_PALMAS=y @@ -159,6 +183,7 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_AS3722=y CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_MAX77620=y CONFIG_REGULATOR_MAX8907=y CONFIG_REGULATOR_PALMAS=y CONFIG_REGULATOR_TPS51632=y @@ -174,7 +199,10 @@ CONFIG_USB_GSPCA=y CONFIG_DRM=y CONFIG_DRM_NOUVEAU=m CONFIG_DRM_TEGRA=y +CONFIG_DRM_TEGRA_STAGING=y +CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_LVDS_CODEC=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_GENERIC is not set @@ -238,6 +266,7 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_AS3722=y CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_MAX8907=y +CONFIG_RTC_DRV_MAX77686=y CONFIG_RTC_DRV_PALMAS=y CONFIG_RTC_DRV_TPS6586X=y CONFIG_RTC_DRV_TPS65910=y @@ -259,11 +288,18 @@ CONFIG_ARCH_TEGRA_2x_SOC=y CONFIG_ARCH_TEGRA_3x_SOC=y CONFIG_ARCH_TEGRA_114_SOC=y CONFIG_ARCH_TEGRA_124_SOC=y +CONFIG_PM_DEVFREQ=y +CONFIG_ARM_TEGRA_DEVFREQ=y +CONFIG_ARM_TEGRA20_DEVFREQ=y CONFIG_MEMORY=y CONFIG_IIO=y +CONFIG_KXCJK1013=y CONFIG_MPU3050_I2C=y +CONFIG_INV_MPU6050_I2C=y +CONFIG_AL3010=y CONFIG_SENSORS_ISL29018=y CONFIG_SENSORS_ISL29028=y +CONFIG_AK8974=y CONFIG_AK8975=y CONFIG_PWM=y CONFIG_PWM_TEGRA=y @@ -282,6 +318,13 @@ CONFIG_TMPFS_POSIX_ACL=y CONFIG_SQUASHFS=y CONFIG_SQUASHFS_LZO=y CONFIG_SQUASHFS_XZ=y +CONFIG_PSTORE=y +CONFIG_PSTORE_LZO_COMPRESS=y +CONFIG_PSTORE_LZ4_COMPRESS=y +CONFIG_PSTORE_LZ4HC_COMPRESS=y +CONFIG_PSTORE_842_COMPRESS=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y CONFIG_NFS_FS=y CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y diff --git a/arch/arm/crypto/crc32-ce-core.S b/arch/arm/crypto/crc32-ce-core.S index 5cbd4a6fedad..3f13a76b9066 100644 --- a/arch/arm/crypto/crc32-ce-core.S +++ b/arch/arm/crypto/crc32-ce-core.S @@ -39,7 +39,7 @@ * CRC32 polynomial:0x04c11db7(BE)/0xEDB88320(LE) * PCLMULQDQ is a new instruction in Intel SSE4.2, the reference can be found * at: - * http://www.intel.com/products/processor/manuals/ + * https://www.intel.com/products/processor/manuals/ * Intel(R) 64 and IA-32 Architectures Software Developer's Manual * Volume 2B: Instruction Set Reference, N-Z * diff --git a/arch/arm/crypto/ghash-ce-glue.c b/arch/arm/crypto/ghash-ce-glue.c index a00fd329255f..f13401f3e669 100644 --- a/arch/arm/crypto/ghash-ce-glue.c +++ b/arch/arm/crypto/ghash-ce-glue.c @@ -16,6 +16,7 @@ #include <crypto/gf128mul.h> #include <linux/cpufeature.h> #include <linux/crypto.h> +#include <linux/jump_label.h> #include <linux/module.h> MODULE_DESCRIPTION("GHASH hash function using ARMv8 Crypto Extensions"); @@ -27,12 +28,8 @@ MODULE_ALIAS_CRYPTO("ghash"); #define GHASH_DIGEST_SIZE 16 struct ghash_key { - u64 h[2]; - u64 h2[2]; - u64 h3[2]; - u64 h4[2]; - be128 k; + u64 h[][2]; }; struct ghash_desc_ctx { @@ -46,16 +43,12 @@ struct ghash_async_ctx { }; asmlinkage void pmull_ghash_update_p64(int blocks, u64 dg[], const char *src, - struct ghash_key const *k, - const char *head); + u64 const h[][2], const char *head); asmlinkage void pmull_ghash_update_p8(int blocks, u64 dg[], const char *src, - struct ghash_key const *k, - const char *head); + u64 const h[][2], const char *head); -static void (*pmull_ghash_update)(int blocks, u64 dg[], const char *src, - struct ghash_key const *k, - const char *head); +static __ro_after_init DEFINE_STATIC_KEY_FALSE(use_p64); static int ghash_init(struct shash_desc *desc) { @@ -70,7 +63,10 @@ static void ghash_do_update(int blocks, u64 dg[], const char *src, { if (likely(crypto_simd_usable())) { kernel_neon_begin(); - pmull_ghash_update(blocks, dg, src, key, head); + if (static_branch_likely(&use_p64)) + pmull_ghash_update_p64(blocks, dg, src, key->h, head); + else + pmull_ghash_update_p8(blocks, dg, src, key->h, head); kernel_neon_end(); } else { be128 dst = { cpu_to_be64(dg[1]), cpu_to_be64(dg[0]) }; @@ -161,25 +157,26 @@ static int ghash_setkey(struct crypto_shash *tfm, const u8 *inkey, unsigned int keylen) { struct ghash_key *key = crypto_shash_ctx(tfm); - be128 h; if (keylen != GHASH_BLOCK_SIZE) return -EINVAL; /* needed for the fallback */ memcpy(&key->k, inkey, GHASH_BLOCK_SIZE); - ghash_reflect(key->h, &key->k); + ghash_reflect(key->h[0], &key->k); - h = key->k; - gf128mul_lle(&h, &key->k); - ghash_reflect(key->h2, &h); + if (static_branch_likely(&use_p64)) { + be128 h = key->k; - gf128mul_lle(&h, &key->k); - ghash_reflect(key->h3, &h); + gf128mul_lle(&h, &key->k); + ghash_reflect(key->h[1], &h); - gf128mul_lle(&h, &key->k); - ghash_reflect(key->h4, &h); + gf128mul_lle(&h, &key->k); + ghash_reflect(key->h[2], &h); + gf128mul_lle(&h, &key->k); + ghash_reflect(key->h[3], &h); + } return 0; } @@ -195,7 +192,7 @@ static struct shash_alg ghash_alg = { .base.cra_driver_name = "ghash-ce-sync", .base.cra_priority = 300 - 1, .base.cra_blocksize = GHASH_BLOCK_SIZE, - .base.cra_ctxsize = sizeof(struct ghash_key), + .base.cra_ctxsize = sizeof(struct ghash_key) + sizeof(u64[2]), .base.cra_module = THIS_MODULE, }; @@ -354,10 +351,10 @@ static int __init ghash_ce_mod_init(void) if (!(elf_hwcap & HWCAP_NEON)) return -ENODEV; - if (elf_hwcap2 & HWCAP2_PMULL) - pmull_ghash_update = pmull_ghash_update_p64; - else - pmull_ghash_update = pmull_ghash_update_p8; + if (elf_hwcap2 & HWCAP2_PMULL) { + ghash_alg.base.cra_ctxsize += 3 * sizeof(u64[2]); + static_branch_enable(&use_p64); + } err = crypto_register_shash(&ghash_alg); if (err) diff --git a/arch/arm/crypto/sha1-armv4-large.S b/arch/arm/crypto/sha1-armv4-large.S index f82cd8cf5a09..1c8b685149f2 100644 --- a/arch/arm/crypto/sha1-armv4-large.S +++ b/arch/arm/crypto/sha1-armv4-large.S @@ -13,7 +13,7 @@ @ Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL @ project. The module is, however, dual licensed under OpenSSL and @ CRYPTOGAMS licenses depending on where you obtain it. For further -@ details see http://www.openssl.org/~appro/cryptogams/. +@ details see https://www.openssl.org/~appro/cryptogams/. @ ==================================================================== @ sha1_block procedure for ARMv4. diff --git a/arch/arm/crypto/sha256-armv4.pl b/arch/arm/crypto/sha256-armv4.pl index a03cf4dfb781..9f96ff48e4a8 100644 --- a/arch/arm/crypto/sha256-armv4.pl +++ b/arch/arm/crypto/sha256-armv4.pl @@ -13,7 +13,7 @@ # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL # project. The module is, however, dual licensed under OpenSSL and # CRYPTOGAMS licenses depending on where you obtain it. For further -# details see http://www.openssl.org/~appro/cryptogams/. +# details see https://www.openssl.org/~appro/cryptogams/. # ==================================================================== # SHA256 block procedure for ARMv4. May 2007. diff --git a/arch/arm/crypto/sha256-core.S_shipped b/arch/arm/crypto/sha256-core.S_shipped index 054aae0edfce..ea04b2ab0c33 100644 --- a/arch/arm/crypto/sha256-core.S_shipped +++ b/arch/arm/crypto/sha256-core.S_shipped @@ -12,7 +12,7 @@ @ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL @ project. The module is, however, dual licensed under OpenSSL and @ CRYPTOGAMS licenses depending on where you obtain it. For further -@ details see http://www.openssl.org/~appro/cryptogams/. +@ details see https://www.openssl.org/~appro/cryptogams/. @ ==================================================================== @ SHA256 block procedure for ARMv4. May 2007. diff --git a/arch/arm/crypto/sha512-armv4.pl b/arch/arm/crypto/sha512-armv4.pl index 788c17b56ecc..69df68981acd 100644 --- a/arch/arm/crypto/sha512-armv4.pl +++ b/arch/arm/crypto/sha512-armv4.pl @@ -13,7 +13,7 @@ # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL # project. The module is, however, dual licensed under OpenSSL and # CRYPTOGAMS licenses depending on where you obtain it. For further -# details see http://www.openssl.org/~appro/cryptogams/. +# details see https://www.openssl.org/~appro/cryptogams/. # ==================================================================== # SHA512 block procedure for ARMv4. September 2007. @@ -43,7 +43,7 @@ # terms it's 22.6 cycles per byte, which is disappointing result. # Technical writers asserted that 3-way S4 pipeline can sustain # multiple NEON instructions per cycle, but dual NEON issue could -# not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html +# not be observed, see https://www.openssl.org/~appro/Snapdragon-S4.html # for further details. On side note Cortex-A15 processes one byte in # 16 cycles. diff --git a/arch/arm/crypto/sha512-core.S_shipped b/arch/arm/crypto/sha512-core.S_shipped index 710ea309769e..cb147db5cbfe 100644 --- a/arch/arm/crypto/sha512-core.S_shipped +++ b/arch/arm/crypto/sha512-core.S_shipped @@ -12,7 +12,7 @@ @ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL @ project. The module is, however, dual licensed under OpenSSL and @ CRYPTOGAMS licenses depending on where you obtain it. For further -@ details see http://www.openssl.org/~appro/cryptogams/. +@ details see https://www.openssl.org/~appro/cryptogams/. @ ==================================================================== @ SHA512 block procedure for ARMv4. September 2007. @@ -42,7 +42,7 @@ @ terms it's 22.6 cycles per byte, which is disappointing result. @ Technical writers asserted that 3-way S4 pipeline can sustain @ multiple NEON instructions per cycle, but dual NEON issue could -@ not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html +@ not be observed, see https://www.openssl.org/~appro/Snapdragon-S4.html @ for further details. On side note Cortex-A15 processes one byte in @ 16 cycles. diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h index 75bb2c543e59..455eb19a5ac1 100644 --- a/arch/arm/include/asm/atomic.h +++ b/arch/arm/include/asm/atomic.h @@ -15,8 +15,6 @@ #include <asm/barrier.h> #include <asm/cmpxchg.h> -#define ATOMIC_INIT(i) { (i) } - #ifdef __KERNEL__ /* diff --git a/arch/arm/include/asm/efi.h b/arch/arm/include/asm/efi.h index 84dc0ba822f5..5dcf3c6011b7 100644 --- a/arch/arm/include/asm/efi.h +++ b/arch/arm/include/asm/efi.h @@ -87,4 +87,11 @@ static inline unsigned long efi_get_max_initrd_addr(unsigned long dram_base, return dram_base + SZ_512M; } +struct efi_arm_entry_state { + u32 cpsr_before_ebs; + u32 sctlr_before_ebs; + u32 cpsr_after_ebs; + u32 sctlr_after_ebs; +}; + #endif /* _ASM_ARM_EFI_H */ diff --git a/arch/arm/include/asm/percpu.h b/arch/arm/include/asm/percpu.h index f44f448537f2..e2fcb3cfd3de 100644 --- a/arch/arm/include/asm/percpu.h +++ b/arch/arm/include/asm/percpu.h @@ -5,6 +5,8 @@ #ifndef _ASM_ARM_PERCPU_H_ #define _ASM_ARM_PERCPU_H_ +register unsigned long current_stack_pointer asm ("sp"); + /* * Same as asm-generic/percpu.h, except that we store the per cpu offset * in the TPIDRPRW. TPIDRPRW only exists on V6K and V7 diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index 3609a6980c34..536b6b979f63 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -76,11 +76,6 @@ struct thread_info { } /* - * how to get the current stack pointer in C - */ -register unsigned long current_stack_pointer asm ("sp"); - -/* * how to get the thread information struct from C */ static inline struct thread_info *current_thread_info(void) __attribute_const__; diff --git a/arch/arm/include/asm/topology.h b/arch/arm/include/asm/topology.h index 435aba289fc5..e0593cf095d0 100644 --- a/arch/arm/include/asm/topology.h +++ b/arch/arm/include/asm/topology.h @@ -16,8 +16,9 @@ /* Enable topology flag updates */ #define arch_update_cpu_topology topology_update_cpu_topology -/* Replace task scheduler's default thermal pressure retrieve API */ +/* Replace task scheduler's default thermal pressure API */ #define arch_scale_thermal_pressure topology_get_thermal_pressure +#define arch_set_thermal_pressure topology_set_thermal_pressure #else diff --git a/arch/arm/include/asm/vdso/gettimeofday.h b/arch/arm/include/asm/vdso/gettimeofday.h index 36dc18553ed8..1b207cf07697 100644 --- a/arch/arm/include/asm/vdso/gettimeofday.h +++ b/arch/arm/include/asm/vdso/gettimeofday.h @@ -7,6 +7,7 @@ #ifndef __ASSEMBLY__ +#include <asm/barrier.h> #include <asm/errno.h> #include <asm/unistd.h> #include <asm/vdso/cp15.h> diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c index c036a4a2f8e2..a1570c8bab25 100644 --- a/arch/arm/kernel/asm-offsets.c +++ b/arch/arm/kernel/asm-offsets.c @@ -31,15 +31,6 @@ #if defined(__APCS_26__) #error Sorry, your compiler targets APCS-26 but this kernel requires APCS-32 #endif -/* - * GCC 4.8.0-4.8.2: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58854 - * miscompiles find_get_entry(), and can result in EXT3 and EXT4 - * filesystem corruption (possibly other FS too). - */ -#if defined(GCC_VERSION) && GCC_VERSION >= 40800 && GCC_VERSION < 40803 -#error Your compiler is too buggy; it is known to miscompile kernels -#error and result in filesystem corruption and oopses. -#endif int main(void) { diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c index 10499d44964a..9a79ef6b1876 100644 --- a/arch/arm/kernel/ftrace.c +++ b/arch/arm/kernel/ftrace.c @@ -84,7 +84,8 @@ static int ftrace_modify_code(unsigned long pc, unsigned long old, old = __opcode_to_mem_arm(old); if (validate) { - if (probe_kernel_read(&replaced, (void *)pc, MCOUNT_INSN_SIZE)) + if (copy_from_kernel_nofault(&replaced, (void *)pc, + MCOUNT_INSN_SIZE)) return -EFAULT; if (replaced != old) diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 02ca7adf5375..7fff88e61252 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -683,6 +683,12 @@ static void disable_single_step(struct perf_event *bp) arch_install_hw_breakpoint(bp); } +static int watchpoint_fault_on_uaccess(struct pt_regs *regs, + struct arch_hw_breakpoint *info) +{ + return !user_mode(regs) && info->ctrl.privilege == ARM_BREAKPOINT_USER; +} + static void watchpoint_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) { @@ -742,16 +748,27 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr, } pr_debug("watchpoint fired: address = 0x%x\n", info->trigger); + + /* + * If we triggered a user watchpoint from a uaccess routine, + * then handle the stepping ourselves since userspace really + * can't help us with this. + */ + if (watchpoint_fault_on_uaccess(regs, info)) + goto step; + perf_bp_event(wp, regs); /* - * If no overflow handler is present, insert a temporary - * mismatch breakpoint so we can single-step over the - * watchpoint trigger. + * Defer stepping to the overflow handler if one is installed. + * Otherwise, insert a temporary mismatch breakpoint so that + * we can single-step over the watchpoint trigger. */ - if (is_default_overflow_handler(wp)) - enable_single_step(wp, instruction_pointer(regs)); + if (!is_default_overflow_handler(wp)) + goto unlock; +step: + enable_single_step(wp, instruction_pointer(regs)); unlock: rcu_read_unlock(); } diff --git a/arch/arm/kernel/kgdb.c b/arch/arm/kernel/kgdb.c index 6a95b9296640..7bd30c0a4280 100644 --- a/arch/arm/kernel/kgdb.c +++ b/arch/arm/kernel/kgdb.c @@ -236,7 +236,7 @@ int kgdb_arch_set_breakpoint(struct kgdb_bkpt *bpt) /* patch_text() only supports int-sized breakpoints */ BUILD_BUG_ON(sizeof(int) != BREAK_INSTR_SIZE); - err = probe_kernel_read(bpt->saved_instr, (char *)bpt->bpt_addr, + err = copy_from_kernel_nofault(bpt->saved_instr, (char *)bpt->bpt_addr, BREAK_INSTR_SIZE); if (err) return err; diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 58eaa1f60e16..3395be186c7d 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -225,9 +225,8 @@ void release_thread(struct task_struct *dead_task) asmlinkage void ret_from_fork(void) __asm__("ret_from_fork"); -int -copy_thread_tls(unsigned long clone_flags, unsigned long stack_start, - unsigned long stk_sz, struct task_struct *p, unsigned long tls) +int copy_thread(unsigned long clone_flags, unsigned long stack_start, + unsigned long stk_sz, struct task_struct *p, unsigned long tls) { struct thread_info *thread = task_thread_info(p); struct pt_regs *childregs = task_pt_regs(p); diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 65a3b1e75480..17d5a785df28 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -396,7 +396,7 @@ int is_valid_bugaddr(unsigned long pc) u32 insn = __opcode_to_mem_arm(BUG_INSTR_VALUE); #endif - if (probe_kernel_address((unsigned *)pc, bkpt)) + if (get_kernel_nofault(bkpt, (void *)pc)) return 0; return bkpt == insn; diff --git a/arch/arm/kernel/vdso.c b/arch/arm/kernel/vdso.c index 6bfdca4769a7..fddd08a6e063 100644 --- a/arch/arm/kernel/vdso.c +++ b/arch/arm/kernel/vdso.c @@ -184,6 +184,7 @@ static void __init patch_vdso(void *ehdr) if (!cntvct_ok) { vdso_nullpatch_one(&einfo, "__vdso_gettimeofday"); vdso_nullpatch_one(&einfo, "__vdso_clock_gettime"); + vdso_nullpatch_one(&einfo, "__vdso_clock_gettime64"); } } diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot index cec195d4fcba..5dde7328a7a9 100644 --- a/arch/arm/mach-at91/Makefile.boot +++ b/arch/arm/mach-at91/Makefile.boot @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only # Empty file waiting for deletion once Makefile.boot isn't needed any more. # Patch waits for application at -# http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 . +# https://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 . diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 074bde64064e..2aab043441e8 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -592,13 +592,13 @@ static void __init at91_pm_sram_init(void) sram_pool = gen_pool_get(&pdev->dev, NULL); if (!sram_pool) { pr_warn("%s: sram pool unavailable!\n", __func__); - return; + goto out_put_device; } sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz); if (!sram_base) { pr_warn("%s: unable to alloc sram!\n", __func__); - return; + goto out_put_device; } sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); @@ -606,12 +606,17 @@ static void __init at91_pm_sram_init(void) at91_pm_suspend_in_sram_sz, false); if (!at91_suspend_sram_fn) { pr_warn("SRAM: Could not map\n"); - return; + goto out_put_device; } /* Copy the pm suspend handler to SRAM */ at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); + return; + +out_put_device: + put_device(&pdev->dev); + return; } static bool __init at91_is_pm_mode_active(int pm_mode) diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 6aa938b949db..1df0ee01ee02 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -53,6 +53,7 @@ config ARCH_BCM_NSP select ARM_ERRATA_754322 select ARM_ERRATA_775420 select ARM_ERRATA_764369 if SMP + select ARM_TIMER_SP804 select THERMAL select THERMAL_OF help diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index d028d38a44bf..f56ff8c24043 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -201,15 +201,13 @@ config MACH_MITYOMAPL138 help Say Y here to select the Critical Link MityDSP-L138/MityARM-1808 System on Module. Information on this SoM may be found at - http://www.mitydsp.com + https://www.mitydsp.com config MACH_OMAPL138_HAWKBOARD bool "TI AM1808 / OMAPL-138 Hawkboard platform" depends on ARCH_DAVINCI_DA850 help Say Y here to select the TI AM1808 / OMAPL-138 Hawkboard platform . - Information of this board may be found at - http://www.hawkboard.org/ config DAVINCI_MUX bool "DAVINCI multiplexing support" diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index a273ab25c668..1076886938b6 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -266,7 +266,7 @@ static struct mtd_partition da830_evm_nand_partitions[] = { } }; -/* flash bbt decriptors */ +/* flash bbt descriptors */ static uint8_t da830_evm_nand_bbt_pattern[] = { 'B', 'b', 't', '0' }; static uint8_t da830_evm_nand_mirror_pattern[] = { '1', 't', 'b', 'B' }; diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 5b3549f1236c..6751292e5f8f 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -1,7 +1,7 @@ /* * TI DA850/OMAP-L138 EVM board * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/ * * Derived from: arch/arm/mach-davinci/board-da830-evm.c * Original Copyrights follow: diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 4600b617f9b4..dd7d60f4139a 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -267,20 +267,15 @@ static int evm_sw_setup(struct i2c_client *client, int gpio, evm_sw_gpio[i] = gpio++; status = gpio_direction_input(evm_sw_gpio[i]); - if (status) { - gpio_free(evm_sw_gpio[i]); - evm_sw_gpio[i] = -EINVAL; + if (status) goto out_free; - } status = gpio_export(evm_sw_gpio[i], 0); - if (status) { - gpio_free(evm_sw_gpio[i]); - evm_sw_gpio[i] = -EINVAL; + if (status) goto out_free; - } } - return status; + return 0; + out_free: for (i = 0; i < 4; ++i) { if (evm_sw_gpio[i] != -EINVAL) { diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c index dfce421c0579..3382b93d9a2a 100644 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -1,7 +1,7 @@ /* * Critical Link MityOMAP-L138 SoM * - * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com + * Copyright (C) 2010 Critical Link LLC - https://www.criticallink.com * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c index ce99f782811a..6cf46bbc7e1d 100644 --- a/arch/arm/mach-davinci/board-neuros-osd2.c +++ b/arch/arm/mach-davinci/board-neuros-osd2.c @@ -214,7 +214,7 @@ static __init void davinci_ntosd2_init(void) * Mux the pins to be GPIOs, VLYNQEN is already done at startup. * The AEAWx are five new AEAW pins that can be muxed by separately. * They are a bitmask for GPIO management. According TI - * documentation (http://www.ti.com/lit/gpn/tms320dm6446) to employ + * documentation (https://www.ti.com/lit/gpn/tms320dm6446) to employ * gpio(10,11,12,13) for leds any combination of bits works except * four last. So we are to reset all five. */ diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c index 5390a8630cf0..6c79039002c9 100644 --- a/arch/arm/mach-davinci/board-omapl138-hawk.c +++ b/arch/arm/mach-davinci/board-omapl138-hawk.c @@ -3,7 +3,7 @@ * * Initial code: Syed Mohammed Khasim * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c index b795f671bd03..dd38785536d5 100644 --- a/arch/arm/mach-davinci/cpuidle.c +++ b/arch/arm/mach-davinci/cpuidle.c @@ -2,7 +2,7 @@ /* * CPU idle for DaVinci SoCs * - * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/ + * Copyright (C) 2009 Texas Instruments Incorporated. https://www.ti.com/ * * Derived from Marvell Kirkwood CPU idle code * (arch/arm/mach-kirkwood/cpuidle.c) diff --git a/arch/arm/mach-davinci/cpuidle.h b/arch/arm/mach-davinci/cpuidle.h index 74f088b0edfb..0d9193aefab5 100644 --- a/arch/arm/mach-davinci/cpuidle.h +++ b/arch/arm/mach-davinci/cpuidle.h @@ -1,7 +1,7 @@ /* * TI DaVinci cpuidle platform support * - * 2009 (C) Texas Instruments, Inc. http://www.ti.com/ + * 2009 (C) Texas Instruments, Inc. https://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 73b7cc53f966..68156e7239a6 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -1,7 +1,7 @@ /* * TI DA850/OMAP-L138 chip specific setup * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/ * * Derived from: arch/arm/mach-davinci/da830.c * Original Copyrights follow: diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c index 9c0dd028d5ad..0cd2f30aeb9c 100644 --- a/arch/arm/mach-davinci/da8xx-dt.c +++ b/arch/arm/mach-davinci/da8xx-dt.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * * Modified from mach-omap/omap2/board-generic.c */ diff --git a/arch/arm/mach-davinci/include/mach/pm.h b/arch/arm/mach-davinci/include/mach/pm.h index 37b19bf35a85..5a5f0ecc0704 100644 --- a/arch/arm/mach-davinci/include/mach/pm.h +++ b/arch/arm/mach-davinci/include/mach/pm.h @@ -1,7 +1,7 @@ /* * TI DaVinci platform support for power management. * - * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/ + * Copyright (C) 2009 Texas Instruments, Inc. https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c index e33c6bcb4598..323ee4e657c4 100644 --- a/arch/arm/mach-davinci/pm.c +++ b/arch/arm/mach-davinci/pm.c @@ -2,7 +2,7 @@ /* * DaVinci Power Management Routines * - * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/ + * Copyright (C) 2009 Texas Instruments, Inc. https://www.ti.com/ */ #include <linux/pm.h> diff --git a/arch/arm/mach-davinci/sleep.S b/arch/arm/mach-davinci/sleep.S index 71262dcdbca3..d5affab4396d 100644 --- a/arch/arm/mach-davinci/sleep.S +++ b/arch/arm/mach-davinci/sleep.S @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * (C) Copyright 2009, Texas Instruments, Inc. http://www.ti.com/ + * (C) Copyright 2009, Texas Instruments, Inc. https://www.ti.com/ */ /* replicated define because linux/bitops.h cannot be included in assembly */ diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 76838255b5fa..f185cd3d4c62 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -118,6 +118,7 @@ config SOC_EXYNOS5800 bool "Samsung EXYNOS5800" default y depends on SOC_EXYNOS5420 + select EXYNOS_REGULATOR_COUPLER config EXYNOS_MCPM bool diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 7a8d1555db40..36c37444485a 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -193,7 +193,7 @@ static void __init exynos_dt_fixup(void) } DT_MACHINE_START(EXYNOS_DT, "Samsung Exynos (Flattened Device Tree)") - .l2c_aux_val = 0x3c400001, + .l2c_aux_val = 0x3c400000, .l2c_aux_mask = 0xc20fffff, .smp = smp_ops(exynos_smp_ops), .map_io = exynos_init_io, diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c index 9a681b421ae1..cd861c57d5ad 100644 --- a/arch/arm/mach-exynos/mcpm-exynos.c +++ b/arch/arm/mach-exynos/mcpm-exynos.c @@ -26,6 +26,7 @@ #define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30) static void __iomem *ns_sram_base_addr __ro_after_init; +static bool secure_firmware __ro_after_init; /* * The common v7_exit_coherency_flush API could not be used because of the @@ -58,15 +59,16 @@ static void __iomem *ns_sram_base_addr __ro_after_init; static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) { unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER); + bool state; pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER || cluster >= EXYNOS5420_NR_CLUSTERS) return -EINVAL; - if (!exynos_cpu_power_state(cpunr)) { - exynos_cpu_power_up(cpunr); - + state = exynos_cpu_power_state(cpunr); + exynos_cpu_power_up(cpunr); + if (!state && secure_firmware) { /* * This assumes the cluster number of the big cores(Cortex A15) * is 0 and the Little cores(Cortex A7) is 1. @@ -258,6 +260,8 @@ static int __init exynos_mcpm_init(void) return -ENOMEM; } + secure_firmware = exynos_secure_firmware_available(); + /* * To increase the stability of KFC reset we need to program * the PMU SPARE3 register diff --git a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig index 1730ee809869..844aa585b966 100644 --- a/arch/arm/mach-footbridge/Kconfig +++ b/arch/arm/mach-footbridge/Kconfig @@ -22,7 +22,7 @@ config ARCH_PERSONAL_SERVER select ISA select ISA_DMA select FORCE_PCI - ---help--- + help Say Y here if you intend to run this kernel on the Compaq Personal Server. diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h index f89f4ae0e1ca..583a1d773d68 100644 --- a/arch/arm/mach-imx/devices-imx27.h +++ b/arch/arm/mach-imx/devices-imx27.h @@ -75,11 +75,11 @@ extern const struct imx_mxc_w1_data imx27_mxc_w1_data; imx_add_mxc_w1(&imx27_mxc_w1_data) extern const struct imx_spi_imx_data imx27_cspi_data[]; -#define imx27_add_cspi(id, pdata) \ - imx_add_spi_imx(&imx27_cspi_data[id], pdata) -#define imx27_add_spi_imx0(pdata) imx27_add_cspi(0, pdata) -#define imx27_add_spi_imx1(pdata) imx27_add_cspi(1, pdata) -#define imx27_add_spi_imx2(pdata) imx27_add_cspi(2, pdata) +#define imx27_add_cspi(id, gtable) \ + imx_add_spi_imx(&imx27_cspi_data[id], gtable) +#define imx27_add_spi_imx0(gtable) imx27_add_cspi(0, gtable) +#define imx27_add_spi_imx1(gtable) imx27_add_cspi(1, gtable) +#define imx27_add_spi_imx2(gtable) imx27_add_cspi(2, gtable) extern const struct imx_pata_imx_data imx27_pata_imx_data; #define imx27_add_pata_imx() \ diff --git a/arch/arm/mach-imx/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h index 5a4ba35a47ed..f7cc62372532 100644 --- a/arch/arm/mach-imx/devices-imx31.h +++ b/arch/arm/mach-imx/devices-imx31.h @@ -69,11 +69,11 @@ extern const struct imx_mxc_w1_data imx31_mxc_w1_data; imx_add_mxc_w1(&imx31_mxc_w1_data) extern const struct imx_spi_imx_data imx31_cspi_data[]; -#define imx31_add_cspi(id, pdata) \ - imx_add_spi_imx(&imx31_cspi_data[id], pdata) -#define imx31_add_spi_imx0(pdata) imx31_add_cspi(0, pdata) -#define imx31_add_spi_imx1(pdata) imx31_add_cspi(1, pdata) -#define imx31_add_spi_imx2(pdata) imx31_add_cspi(2, pdata) +#define imx31_add_cspi(id, gtable) \ + imx_add_spi_imx(&imx31_cspi_data[id], gtable) +#define imx31_add_spi_imx0(gtable) imx31_add_cspi(0, gtable) +#define imx31_add_spi_imx1(gtable) imx31_add_cspi(1, gtable) +#define imx31_add_spi_imx2(gtable) imx31_add_cspi(2, gtable) extern const struct imx_pata_imx_data imx31_pata_imx_data; #define imx31_add_pata_imx() \ diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h index 2a685adec1df..327a1de7dce1 100644 --- a/arch/arm/mach-imx/devices/devices-common.h +++ b/arch/arm/mach-imx/devices/devices-common.h @@ -6,6 +6,7 @@ #include <linux/kernel.h> #include <linux/platform_device.h> #include <linux/init.h> +#include <linux/gpio/machine.h> #include <linux/platform_data/dma-imx-sdma.h> extern struct device mxc_aips_bus; @@ -276,7 +277,6 @@ struct platform_device *__init imx_add_sdhci_esdhc_imx( const struct imx_sdhci_esdhc_imx_data *data, const struct esdhc_platform_data *pdata); -#include <linux/platform_data/spi-imx.h> struct imx_spi_imx_data { const char *devid; int id; @@ -285,10 +285,9 @@ struct imx_spi_imx_data { int irq; }; struct platform_device *__init imx_add_spi_imx( - const struct imx_spi_imx_data *data, - const struct spi_imx_master *pdata); + const struct imx_spi_imx_data *data, struct gpiod_lookup_table *gtable); struct platform_device *imx_add_imx_dma(char *name, resource_size_t iobase, - int irq, int irq_err); + int irq); struct platform_device *imx_add_imx_sdma(char *name, resource_size_t iobase, int irq, struct sdma_platform_data *pdata); diff --git a/arch/arm/mach-imx/devices/platform-gpio-mxc.c b/arch/arm/mach-imx/devices/platform-gpio-mxc.c index 78628ef12672..355de845224c 100644 --- a/arch/arm/mach-imx/devices/platform-gpio-mxc.c +++ b/arch/arm/mach-imx/devices/platform-gpio-mxc.c @@ -24,7 +24,8 @@ struct platform_device *__init mxc_register_gpio(char *name, int id, .flags = IORESOURCE_IRQ, }, }; + unsigned int nres; - return platform_device_register_resndata(&mxc_aips_bus, - name, id, res, ARRAY_SIZE(res), NULL, 0); + nres = irq_high ? ARRAY_SIZE(res) : ARRAY_SIZE(res) - 1; + return platform_device_register_resndata(&mxc_aips_bus, name, id, res, nres, NULL, 0); } diff --git a/arch/arm/mach-imx/devices/platform-imx-dma.c b/arch/arm/mach-imx/devices/platform-imx-dma.c index 26b47b36257b..12656f24ad0d 100644 --- a/arch/arm/mach-imx/devices/platform-imx-dma.c +++ b/arch/arm/mach-imx/devices/platform-imx-dma.c @@ -6,7 +6,7 @@ #include "devices-common.h" struct platform_device __init __maybe_unused *imx_add_imx_dma(char *name, - resource_size_t iobase, int irq, int irq_err) + resource_size_t iobase, int irq) { struct resource res[] = { { @@ -17,10 +17,6 @@ struct platform_device __init __maybe_unused *imx_add_imx_dma(char *name, .start = irq, .end = irq, .flags = IORESOURCE_IRQ, - }, { - .start = irq_err, - .end = irq_err, - .flags = IORESOURCE_IRQ, }, }; diff --git a/arch/arm/mach-imx/devices/platform-spi_imx.c b/arch/arm/mach-imx/devices/platform-spi_imx.c index f2cafa52c187..27747bf628a3 100644 --- a/arch/arm/mach-imx/devices/platform-spi_imx.c +++ b/arch/arm/mach-imx/devices/platform-spi_imx.c @@ -3,6 +3,7 @@ * Copyright (C) 2009-2010 Pengutronix * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> */ +#include <linux/gpio/machine.h> #include "../hardware.h" #include "devices-common.h" @@ -57,8 +58,7 @@ const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { #endif /* ifdef CONFIG_SOC_IMX35 */ struct platform_device *__init imx_add_spi_imx( - const struct imx_spi_imx_data *data, - const struct spi_imx_master *pdata) + const struct imx_spi_imx_data *data, struct gpiod_lookup_table *gtable) { struct resource res[] = { { @@ -71,7 +71,8 @@ struct platform_device *__init imx_add_spi_imx( .flags = IORESOURCE_IRQ, }, }; - + if (gtable) + gpiod_add_lookup_table(gtable); return imx_add_platform_device(data->devid, data->id, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); + res, ARRAY_SIZE(res), NULL, 0); } diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index 1da5f07952ac..2db4475b7f85 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c @@ -303,18 +303,34 @@ static struct imx_ssi_platform_data mx27_3ds_ssi_pdata = { }; /* SPI */ -static int spi1_chipselect[] = {SPI1_SS0}; - -static const struct spi_imx_master spi1_pdata __initconst = { - .chipselect = spi1_chipselect, - .num_chipselect = ARRAY_SIZE(spi1_chipselect), +static struct gpiod_lookup_table mx27_spi1_gpiod_table = { + .dev_id = "imx27-cspi.0", /* Actual device name for spi1 */ + .table = { + /* + * The i.MX27 has the i.MX21 GPIO controller, the SPI1 CS GPIO + * SPI1_SS0 is numbered IMX_GPIO_NR(4, 28). + * + * This is in "bank 4" which is subtracted by one in the macro + * so this is actually bank 3 on "imx21-gpio.3". + */ + GPIO_LOOKUP_IDX("imx21-gpio.3", 28, "cs", 0, GPIO_ACTIVE_LOW), + { }, + }, }; -static int spi2_chipselect[] = {SPI2_SS0}; - -static const struct spi_imx_master spi2_pdata __initconst = { - .chipselect = spi2_chipselect, - .num_chipselect = ARRAY_SIZE(spi2_chipselect), +static struct gpiod_lookup_table mx27_spi2_gpiod_table = { + .dev_id = "imx27-cspi.1", /* Actual device name for spi2 */ + .table = { + /* + * The i.MX27 has the i.MX21 GPIO controller, the SPI2 CS GPIO + * SPI2_SS0 is numbered IMX_GPIO_NR(4, 21). + * + * This is in "bank 4" which is subtracted by one in the macro + * so this is actually bank 3 on "imx21-gpio.3". + */ + GPIO_LOOKUP_IDX("imx21-gpio.3", 21, "cs", 0, GPIO_ACTIVE_LOW), + { }, + }, }; static struct imx_fb_videomode mx27_3ds_modes[] = { @@ -397,8 +413,8 @@ static void __init mx27pdk_init(void) imx27_add_imx_keypad(&mx27_3ds_keymap_data); imx27_add_imx2_wdt(); - imx27_add_spi_imx1(&spi2_pdata); - imx27_add_spi_imx0(&spi1_pdata); + imx27_add_spi_imx1(&mx27_spi2_gpiod_table); + imx27_add_spi_imx0(&mx27_spi1_gpiod_table); imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data); imx27_add_imx_fb(&mx27_3ds_fb_data); diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c index e81386190479..23e63d3b4c6a 100644 --- a/arch/arm/mach-imx/mach-mx31_3ds.c +++ b/arch/arm/mach-imx/mach-mx31_3ds.c @@ -378,15 +378,6 @@ static struct imx_ssi_platform_data mx31_3ds_ssi_pdata = { .flags = IMX_SSI_DMA | IMX_SSI_NET, }; -/* SPI */ -static const struct spi_imx_master spi0_pdata __initconst = { - .num_chipselect = 3, -}; - -static const struct spi_imx_master spi1_pdata __initconst = { - .num_chipselect = 3, -}; - static struct spi_board_info mx31_3ds_spi_devs[] __initdata = { { .modalias = "mc13783", @@ -561,14 +552,14 @@ static void __init mx31_3ds_init(void) imx31_add_imx_uart0(&uart_pdata); imx31_add_mxc_nand(&mx31_3ds_nand_board_info); - imx31_add_spi_imx1(&spi1_pdata); + imx31_add_spi_imx1(NULL); imx31_add_imx_keypad(&mx31_3ds_keymap_data); imx31_add_imx2_wdt(); imx31_add_imx_i2c0(&mx31_3ds_i2c0_data); - imx31_add_spi_imx0(&spi0_pdata); + imx31_add_spi_imx0(NULL); imx31_add_ipu_core(); imx31_add_mx3_sdc_fb(&mx3fb_pdata); diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c index 8f725248299e..4b955ccc92cd 100644 --- a/arch/arm/mach-imx/mach-mx31lilly.c +++ b/arch/arm/mach-imx/mach-mx31lilly.c @@ -215,16 +215,6 @@ static void __init lilly1131_usb_init(void) imx31_add_mxc_ehci_hs(2, &usbh2_pdata); } -/* SPI */ - -static const struct spi_imx_master spi0_pdata __initconst = { - .num_chipselect = 3, -}; - -static const struct spi_imx_master spi1_pdata __initconst = { - .num_chipselect = 3, -}; - static struct mc13xxx_platform_data mc13783_pdata __initdata = { .flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN, }; @@ -281,8 +271,8 @@ static void __init mx31lilly_board_init(void) mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1"); mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2"); - imx31_add_spi_imx0(&spi0_pdata); - imx31_add_spi_imx1(&spi1_pdata); + imx31_add_spi_imx0(NULL); + imx31_add_spi_imx1(NULL); regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); } diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c index c0055f57c02d..aaccf52f7ac1 100644 --- a/arch/arm/mach-imx/mach-mx31lite.c +++ b/arch/arm/mach-imx/mach-mx31lite.c @@ -73,11 +73,6 @@ static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; -/* SPI */ -static const struct spi_imx_master spi0_pdata __initconst = { - .num_chipselect = 3, -}; - static const struct mxc_nand_platform_data mx31lite_nand_board_info __initconst = { .width = 1, @@ -111,16 +106,6 @@ static struct platform_device smsc911x_device = { }, }; -/* - * SPI - * - * The MC13783 is the only hard-wired SPI device on the module. - */ - -static const struct spi_imx_master spi1_pdata __initconst = { - .num_chipselect = 1, -}; - static struct mc13xxx_platform_data mc13783_pdata __initdata = { .flags = MC13XXX_USE_RTC, }; @@ -246,13 +231,13 @@ static void __init mx31lite_init(void) "mx31lite"); imx31_add_imx_uart0(&uart_pdata); - imx31_add_spi_imx0(&spi0_pdata); + imx31_add_spi_imx0(NULL); /* NOR and NAND flash */ platform_device_register(&physmap_flash_device); imx31_add_mxc_nand(&mx31lite_nand_board_info); - imx31_add_spi_imx1(&spi1_pdata); + imx31_add_spi_imx1(NULL); regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); } diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c index 36f08f45b0ca..96845a4eaf57 100644 --- a/arch/arm/mach-imx/mach-mx31moboard.c +++ b/arch/arm/mach-imx/mach-mx31moboard.c @@ -143,10 +143,6 @@ static const struct imxi2c_platform_data moboard_i2c1_data __initconst = { .bitrate = 100000, }; -static const struct spi_imx_master moboard_spi1_pdata __initconst = { - .num_chipselect = 3, -}; - static struct regulator_consumer_supply sdhc_consumers[] = { { .dev_name = "imx31-mmc.0", @@ -287,10 +283,6 @@ static struct spi_board_info moboard_spi_board_info[] __initdata = { }, }; -static const struct spi_imx_master moboard_spi2_pdata __initconst = { - .num_chipselect = 2, -}; - #define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0) #define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1) @@ -514,8 +506,8 @@ static void __init mx31moboard_init(void) imx31_add_imx_i2c0(&moboard_i2c0_data); imx31_add_imx_i2c1(&moboard_i2c1_data); - imx31_add_spi_imx1(&moboard_spi1_pdata); - imx31_add_spi_imx2(&moboard_spi2_pdata); + imx31_add_spi_imx1(NULL); + imx31_add_spi_imx2(NULL); mx31moboard_init_cam(); diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index 2e28e1b5cddf..27a3678e0658 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -14,6 +14,7 @@ #include <linux/irq.h> #include <linux/delay.h> #include <linux/gpio.h> +#include <linux/gpio/machine.h> #include <linux/usb/otg.h> #include <linux/usb/ulpi.h> @@ -188,11 +189,19 @@ static struct spi_board_info pca100_spi_board_info[] __initdata = { }, }; -static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1}; - -static const struct spi_imx_master pca100_spi0_data __initconst = { - .chipselect = pca100_spi_cs, - .num_chipselect = ARRAY_SIZE(pca100_spi_cs), +static struct gpiod_lookup_table pca100_spi0_gpiod_table = { + .dev_id = "imx27-cspi.0", /* Actual device name for spi0 */ + .table = { + /* + * The i.MX27 has the i.MX21 GPIO controller, port D is + * bank 3 and thus named "imx21-gpio.3". + * SPI1_SS0 is GPIO_PORTD + 28 + * SPI1_SS1 is GPIO_PORTD + 27 + */ + GPIO_LOOKUP_IDX("imx21-gpio.3", 28, "cs", 0, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("imx21-gpio.3", 27, "cs", 1, GPIO_ACTIVE_LOW), + { }, + }, }; static void pca100_ac97_warm_reset(struct snd_ac97 *ac97) @@ -362,7 +371,7 @@ static void __init pca100_init(void) mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN); spi_register_board_info(pca100_spi_board_info, ARRAY_SIZE(pca100_spi_board_info)); - imx27_add_spi_imx0(&pca100_spi0_data); + imx27_add_spi_imx0(&pca100_spi0_gpiod_table); imx27_add_imx_fb(&pca100_fb_data); diff --git a/arch/arm/mach-imx/mach-pcm037_eet.c b/arch/arm/mach-imx/mach-pcm037_eet.c index 51f5142920cf..8b0e03a595c1 100644 --- a/arch/arm/mach-imx/mach-pcm037_eet.c +++ b/arch/arm/mach-imx/mach-pcm037_eet.c @@ -52,11 +52,6 @@ static struct spi_board_info pcm037_spi_dev[] = { }, }; -/* Platform Data for MXC CSPI */ -static const struct spi_imx_master pcm037_spi1_pdata __initconst = { - .num_chipselect = 2, -}; - /* GPIO-keys input device */ static struct gpio_keys_button pcm037_gpio_keys[] = { { @@ -163,7 +158,7 @@ int __init pcm037_eet_init_devices(void) /* SPI */ spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev)); - imx31_add_spi_imx0(&pcm037_spi1_pdata); + imx31_add_spi_imx0(NULL); imx_add_gpio_keys(&pcm037_gpio_keys_platform_data); diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c index 50a2edac8513..b834026e4615 100644 --- a/arch/arm/mach-imx/mm-imx21.c +++ b/arch/arm/mach-imx/mm-imx21.c @@ -78,8 +78,7 @@ void __init imx21_soc_init(void) mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); pinctrl_provide_dummies(); - imx_add_imx_dma("imx21-dma", MX21_DMA_BASE_ADDR, - MX21_INT_DMACH0, 0); /* No ERR irq */ + imx_add_imx_dma("imx21-dma", MX21_DMA_BASE_ADDR, MX21_INT_DMACH0); platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res, ARRAY_SIZE(imx21_audmux_res)); } diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c index 4e4125140025..2717614f101d 100644 --- a/arch/arm/mach-imx/mm-imx27.c +++ b/arch/arm/mach-imx/mm-imx27.c @@ -79,8 +79,7 @@ void __init imx27_soc_init(void) mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); pinctrl_provide_dummies(); - imx_add_imx_dma("imx27-dma", MX27_DMA_BASE_ADDR, - MX27_INT_DMACH0, 0); /* No ERR irq */ + imx_add_imx_dma("imx27-dma", MX27_DMA_BASE_ADDR, MX27_INT_DMACH0); /* imx27 has the imx21 type audmux */ platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res, ARRAY_SIZE(imx27_audmux_res)); diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c index f057df813f83..e9962b48e30c 100644 --- a/arch/arm/mach-imx/pm-imx5.c +++ b/arch/arm/mach-imx/pm-imx5.c @@ -295,14 +295,14 @@ static int __init imx_suspend_alloc_ocram( if (!ocram_pool) { pr_warn("%s: ocram pool unavailable!\n", __func__); ret = -ENODEV; - goto put_node; + goto put_device; } ocram_base = gen_pool_alloc(ocram_pool, size); if (!ocram_base) { pr_warn("%s: unable to alloc ocram!\n", __func__); ret = -ENOMEM; - goto put_node; + goto put_device; } phys = gen_pool_virt_to_phys(ocram_pool, ocram_base); @@ -312,6 +312,8 @@ static int __init imx_suspend_alloc_ocram( if (virt_out) *virt_out = virt; +put_device: + put_device(&pdev->dev); put_node: of_node_put(node); diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c index dd34dff13762..40c74b4c4d73 100644 --- a/arch/arm/mach-imx/pm-imx6.c +++ b/arch/arm/mach-imx/pm-imx6.c @@ -493,14 +493,14 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) if (!ocram_pool) { pr_warn("%s: ocram pool unavailable!\n", __func__); ret = -ENODEV; - goto put_node; + goto put_device; } ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE); if (!ocram_base) { pr_warn("%s: unable to alloc ocram!\n", __func__); ret = -ENOMEM; - goto put_node; + goto put_device; } ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base); @@ -523,7 +523,7 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat); if (ret) { pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret); - goto put_node; + goto put_device; } ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat); @@ -570,7 +570,7 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) &imx6_suspend, MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info)); - goto put_node; + goto put_device; pl310_cache_map_failed: iounmap(pm_info->gpc_base.vbase); @@ -580,6 +580,8 @@ iomuxc_map_failed: iounmap(pm_info->src_base.vbase); src_map_failed: iounmap(pm_info->mmdc_base.vbase); +put_device: + put_device(&pdev->dev); put_node: of_node_put(node); diff --git a/arch/arm/mach-mstar/Kconfig b/arch/arm/mach-mstar/Kconfig new file mode 100644 index 000000000000..52744fe32368 --- /dev/null +++ b/arch/arm/mach-mstar/Kconfig @@ -0,0 +1,26 @@ +menuconfig ARCH_MSTARV7 + bool "MStar/Sigmastar Armv7 SoC Support" + depends on ARCH_MULTI_V7 + select ARM_GIC + select ARM_HEAVY_MB + help + Support for newer MStar/Sigmastar SoC families that are + based on Armv7 cores like the Cortex A7 and share the same + basic hardware like the infinity and mercury series. + +if ARCH_MSTARV7 + +config MACH_INFINITY + bool "MStar/Sigmastar infinity SoC support" + default ARCH_MSTARV7 + help + Support for MStar/Sigmastar infinity IP camera SoCs. + +config MACH_MERCURY + bool "MStar/Sigmastar mercury SoC support" + default ARCH_MSTARV7 + help + Support for MStar/Sigmastar mercury dash camera SoCs. + Note that older Mercury2 SoCs are ARM9 based and not supported. + +endif diff --git a/arch/arm/mach-mstar/Makefile b/arch/arm/mach-mstar/Makefile new file mode 100644 index 000000000000..93b0391ede7e --- /dev/null +++ b/arch/arm/mach-mstar/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_ARCH_MSTARV7) += mstarv7.o diff --git a/arch/arm/mach-mstar/mstarv7.c b/arch/arm/mach-mstar/mstarv7.c new file mode 100644 index 000000000000..81a4cbcab206 --- /dev/null +++ b/arch/arm/mach-mstar/mstarv7.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree support for MStar/Sigmastar Armv7 SoCs + * + * Copyright (c) 2020 thingy.jp + * Author: Daniel Palmer <daniel@thingy.jp> + */ + +#include <linux/init.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/io.h> + +/* + * In the u-boot code the area these registers are in is + * called "L3 bridge" and there are register descriptions + * for something in the same area called "AXI". + * + * It's not exactly known what this is but the vendor code + * for both u-boot and linux share calls to "flush the miu pipe". + * This seems to be to force pending CPU writes to memory so that + * the state is right before DMA capable devices try to read + * descriptors and data the CPU has prepared. Without doing this + * ethernet doesn't work reliably for example. + */ + +#define MSTARV7_L3BRIDGE_FLUSH 0x14 +#define MSTARV7_L3BRIDGE_STATUS 0x40 +#define MSTARV7_L3BRIDGE_FLUSH_TRIGGER BIT(0) +#define MSTARV7_L3BRIDGE_STATUS_DONE BIT(12) + +static void __iomem *l3bridge; + +static const char * const mstarv7_board_dt_compat[] __initconst = { + "mstar,infinity", + "mstar,infinity3", + "mstar,mercury5", + NULL, +}; + +/* + * This may need locking to deal with situations where an interrupt + * happens while we are in here and mb() gets called by the interrupt handler. + * + * The vendor code did have a spin lock but it doesn't seem to be needed and + * removing it hasn't caused any side effects so far. + * + * [writel|readl]_relaxed have to be used here because otherwise + * we'd end up right back in here. + */ +static void mstarv7_mb(void) +{ + /* toggle the flush miu pipe fire bit */ + writel_relaxed(0, l3bridge + MSTARV7_L3BRIDGE_FLUSH); + writel_relaxed(MSTARV7_L3BRIDGE_FLUSH_TRIGGER, l3bridge + + MSTARV7_L3BRIDGE_FLUSH); + while (!(readl_relaxed(l3bridge + MSTARV7_L3BRIDGE_STATUS) + & MSTARV7_L3BRIDGE_STATUS_DONE)) { + /* wait for flush to complete */ + } +} + +static void __init mstarv7_init(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "mstar,l3bridge"); + l3bridge = of_iomap(np, 0); + if (l3bridge) + soc_mb = mstarv7_mb; + else + pr_warn("Failed to install memory barrier, DMA will be broken!\n"); +} + +DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)") + .dt_compat = mstarv7_board_dt_compat, + .init_machine = mstarv7_init, +MACHINE_END diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 948da556162e..9536b8f3c07d 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -146,7 +146,7 @@ config MACH_SX1 Support for the Siemens SX1 phone. To boot the kernel, you'll need a SX1 compatible bootloader; check out http://forum.oslik.ru and - http://www.handhelds.org/moin/moin.cgi/SiemensSX1 + https://www.handhelds.org/moin/moin.cgi/SiemensSX1 for more information. Say Y here if you have such a phone, say NO otherwise. diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c index 0ad8bdc2ed61..2bf659fb6099 100644 --- a/arch/arm/mach-omap1/dma.c +++ b/arch/arm/mach-omap1/dma.c @@ -10,7 +10,7 @@ * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ * Converted DMA library into platform driver * - G, Manjunath Kondaiah <manjugk@ti.com> */ diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c index 312a0924d786..3ec08bd5d8a0 100644 --- a/arch/arm/mach-omap1/gpio15xx.c +++ b/arch/arm/mach-omap1/gpio15xx.c @@ -1,7 +1,7 @@ /* * OMAP15xx specific gpio init * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ * * Author: * Charulatha V <charu@ti.com> diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c index 5b7a29b294d4..500cfd416c42 100644 --- a/arch/arm/mach-omap1/gpio16xx.c +++ b/arch/arm/mach-omap1/gpio16xx.c @@ -1,7 +1,7 @@ /* * OMAP16xx specific gpio init * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ * * Author: * Charulatha V <charu@ti.com> diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c index 0e5f68de23bf..aeb81c18ffcc 100644 --- a/arch/arm/mach-omap1/gpio7xx.c +++ b/arch/arm/mach-omap1/gpio7xx.c @@ -1,7 +1,7 @@ /* * OMAP7xx specific gpio init * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ * * Author: * Charulatha V <charu@ti.com> diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c index 4447210c9b0d..97fc2096b970 100644 --- a/arch/arm/mach-omap1/timer.c +++ b/arch/arm/mach-omap1/timer.c @@ -6,7 +6,7 @@ * device model. It also has a low level function to change the timer * input clock source. * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ * Tarun Kanti DebBarma <tarun.kanti@ti.com> * Thara Gopinath <thara@ti.com> * diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 188ea5258c99..1d119b974f5f 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -775,19 +775,23 @@ static const char * __init omap_get_family(void) return kasprintf(GFP_KERNEL, "Unknown"); } -static ssize_t omap_get_type(struct device *dev, - struct device_attribute *attr, - char *buf) +static ssize_t +type_show(struct device *dev, struct device_attribute *attr, char *buf) { return sprintf(buf, "%s\n", omap_types[omap_type()]); } -static struct device_attribute omap_soc_attr = - __ATTR(type, S_IRUGO, omap_get_type, NULL); +static DEVICE_ATTR_RO(type); + +static struct attribute *omap_soc_attrs[] = { + &dev_attr_type.attr, + NULL +}; + +ATTRIBUTE_GROUPS(omap_soc); void __init omap_soc_device_init(void) { - struct device *parent; struct soc_device *soc_dev; struct soc_device_attribute *soc_dev_attr; @@ -798,14 +802,12 @@ void __init omap_soc_device_init(void) soc_dev_attr->machine = soc_name; soc_dev_attr->family = omap_get_family(); soc_dev_attr->revision = soc_rev; + soc_dev_attr->custom_attr_group = omap_soc_groups[0]; soc_dev = soc_device_register(soc_dev_attr); if (IS_ERR(soc_dev)) { kfree(soc_dev_attr); return; } - - parent = soc_device_to_device(soc_dev); - device_create_file(parent, &omap_soc_attr); } #endif /* CONFIG_SOC_BUS */ diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 82706af307de..15b29a179c8a 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -3435,7 +3435,7 @@ static int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh, regs = ioremap(data->module_pa, data->module_size); if (!regs) - return -ENOMEM; + goto out_free_sysc; } /* @@ -3445,13 +3445,13 @@ static int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh, if (oh->class->name && strcmp(oh->class->name, data->name)) { class = kmemdup(oh->class, sizeof(*oh->class), GFP_KERNEL); if (!class) - return -ENOMEM; + goto out_unmap; } if (list_empty(&oh->slave_ports)) { oi = kcalloc(1, sizeof(*oi), GFP_KERNEL); if (!oi) - return -ENOMEM; + goto out_free_class; /* * Note that we assume interconnect interface clocks will be @@ -3478,6 +3478,14 @@ static int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh, spin_unlock_irqrestore(&oh->_lock, flags); return 0; + +out_free_class: + kfree(class); +out_unmap: + iounmap(regs); +out_free_sysc: + kfree(sysc); + return -ENOMEM; } static const struct omap_hwmod_reset omap24xx_reset_quirks[] = { @@ -3489,7 +3497,7 @@ static const struct omap_hwmod_reset dra7_reset_quirks[] = { }; static const struct omap_hwmod_reset omap_reset_quirks[] = { - { .match = "dss", .len = 3, .reset = omap_dss_reset, }, + { .match = "dss_core", .len = 8, .reset = omap_dss_reset, }, { .match = "hdq1w", .len = 5, .reset = omap_hdq1w_reset, }, { .match = "i2c", .len = 3, .reset = omap_i2c_reset, }, { .match = "wd_timer", .len = 8, .reset = omap2_wd_timer_reset, }, diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index ca02f91237e3..b6c7d98a9eff 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -2342,44 +2342,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_core -> AES */ -static struct omap_hwmod_class_sysconfig omap3_aes_sysc = { - .rev_offs = 0x44, - .sysc_offs = 0x48, - .syss_offs = 0x4c, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap3xxx_aes_sysc_fields, -}; - -static struct omap_hwmod_class omap3xxx_aes_class = { - .name = "aes", - .sysc = &omap3_aes_sysc, -}; - - -static struct omap_hwmod omap3xxx_aes_hwmod = { - .name = "aes", - .main_clk = "aes2_ick", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT, - }, - }, - .class = &omap3xxx_aes_class, -}; - - -static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_aes_hwmod, - .clk = "aes2_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* * 'ssi' class * synchronous serial interface (multichannel and full-duplex serial if) @@ -2473,20 +2435,11 @@ static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = { NULL, }; -static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = { - &omap3xxx_l4_core__aes, - NULL, -}; - static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l4_core__sham, NULL }; -static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = { - &omap3xxx_l4_core__aes, - NULL -}; /* * Apparently the SHA/MD5 and AES accelerator IP blocks are @@ -2501,11 +2454,6 @@ static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = { NULL }; -static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = { - /* &omap3xxx_l4_core__aes, */ - NULL, -}; - /* 3430ES1-only hwmod links */ static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { &omap3430es1_dss__l3, @@ -2641,7 +2589,6 @@ int __init omap3xxx_hwmod_init(void) { int r; struct omap_hwmod_ocp_if **h = NULL, **h_sham = NULL; - struct omap_hwmod_ocp_if **h_aes = NULL; struct device_node *bus; unsigned int rev; @@ -2664,16 +2611,13 @@ int __init omap3xxx_hwmod_init(void) rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { h = omap34xx_hwmod_ocp_ifs; h_sham = omap34xx_sham_hwmod_ocp_ifs; - h_aes = omap34xx_aes_hwmod_ocp_ifs; } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { h = am35xx_hwmod_ocp_ifs; h_sham = am35xx_sham_hwmod_ocp_ifs; - h_aes = am35xx_aes_hwmod_ocp_ifs; } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2) { h = omap36xx_hwmod_ocp_ifs; h_sham = omap36xx_sham_hwmod_ocp_ifs; - h_aes = omap36xx_aes_hwmod_ocp_ifs; } else { WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); return -EINVAL; @@ -2696,11 +2640,6 @@ int __init omap3xxx_hwmod_init(void) goto put_node; } - if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) { - r = omap_hwmod_register_links(h_aes); - if (r < 0) - goto put_node; - } of_node_put(bus); /* diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index 3f338732ee6c..b88d12de68a2 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c @@ -85,49 +85,6 @@ static struct omap_hwmod am43xx_control_hwmod = { }, }; -static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE | - SYSC_HAS_SIDLEMODE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP | MSTANDBY_FORCE | - MSTANDBY_NO | MSTANDBY_SMART | - MSTANDBY_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = { - .name = "usb_otg_ss", - .sysc = &am43xx_usb_otg_ss_sysc, -}; - -static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = { - .name = "usb_otg_ss0", - .class = &am43xx_usb_otg_ss_hwmod_class, - .clkdm_name = "l3s_clkdm", - .main_clk = "l3s_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = { - .name = "usb_otg_ss1", - .class = &am43xx_usb_otg_ss_hwmod_class, - .clkdm_name = "l3s_clkdm", - .main_clk = "l3s_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - /* Interfaces */ static struct omap_hwmod_ocp_if am43xx_l3_main__emif = { .master = &am33xx_l3_main_hwmod, @@ -178,20 +135,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = { - .master = &am33xx_l3_s_hwmod, - .slave = &am43xx_usb_otg_ss0_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = { - .master = &am33xx_l3_s_hwmod, - .slave = &am43xx_usb_otg_ss1_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am33xx_mpu__l3_main, &am33xx_mpu__prcm, @@ -211,8 +154,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am43xx_l4_wkup__smartreflex1, &am33xx_l3_s__gpmc, &am33xx_l3_main__ocmc, - &am43xx_l3_s__usbotgss0, - &am43xx_l3_s__usbotgss1, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index de13c46b984f..665ca74a834a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -640,154 +640,6 @@ static struct omap_hwmod omap44xx_sl2if_hwmod = { }; /* - * 'usb_host_fs' class - * full-speed usb host controller - */ - -/* The IP is not compliant to type1 / type2 scheme */ -static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0210, - .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs, -}; - -static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = { - .name = "usb_host_fs", - .sysc = &omap44xx_usb_host_fs_sysc, -}; - -/* usb_host_fs */ -static struct omap_hwmod omap44xx_usb_host_fs_hwmod = { - .name = "usb_host_fs", - .class = &omap44xx_usb_host_fs_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .main_clk = "usb_host_fs_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * 'usb_host_hs' class - * high-speed multi-port usb host controller - */ - -static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | - MSTANDBY_SMART | MSTANDBY_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { - .name = "usb_host_hs", - .sysc = &omap44xx_usb_host_hs_sysc, -}; - -/* usb_host_hs */ -static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { - .name = "usb_host_hs", - .class = &omap44xx_usb_host_hs_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .main_clk = "usb_host_hs_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - - /* - * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock - * id: i660 - * - * Description: - * In the following configuration : - * - USBHOST module is set to smart-idle mode - * - PRCM asserts idle_req to the USBHOST module ( This typically - * happens when the system is going to a low power mode : all ports - * have been suspended, the master part of the USBHOST module has - * entered the standby state, and SW has cut the functional clocks) - * - an USBHOST interrupt occurs before the module is able to answer - * idle_ack, typically a remote wakeup IRQ. - * Then the USB HOST module will enter a deadlock situation where it - * is no more accessible nor functional. - * - * Workaround: - * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE - */ - - /* - * Errata: USB host EHCI may stall when entering smart-standby mode - * Id: i571 - * - * Description: - * When the USBHOST module is set to smart-standby mode, and when it is - * ready to enter the standby state (i.e. all ports are suspended and - * all attached devices are in suspend mode), then it can wrongly assert - * the Mstandby signal too early while there are still some residual OCP - * transactions ongoing. If this condition occurs, the internal state - * machine may go to an undefined state and the USB link may be stuck - * upon the next resume. - * - * Workaround: - * Don't use smart standby; use only force standby, - * hence HWMOD_SWSUP_MSTANDBY - */ - - .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, -}; - -/* - * 'usb_tll_hs' class - * usb_tll_hs module is the adapter on the usb_host_hs ports - */ - -static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { - .name = "usb_tll_hs", - .sysc = &omap44xx_usb_tll_hs_sysc, -}; - -static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { - .name = "usb_tll_hs", - .class = &omap44xx_usb_tll_hs_hwmod_class, - .clkdm_name = "l3_init_clkdm", - .main_clk = "usb_tll_hs_ick", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - -/* * interfaces */ @@ -895,22 +747,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* usb_host_fs -> l3_main_2 */ -static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = { - .master = &omap44xx_usb_host_fs_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* usb_host_hs -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { - .master = &omap44xx_usb_host_hs_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main_1 -> l3_main_3 */ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { .master = &omap44xx_l3_main_1_hwmod, @@ -1119,30 +955,6 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_cfg -> usb_host_fs */ -static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_usb_host_fs_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> usb_host_hs */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_usb_host_hs_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> usb_tll_hs */ -static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { - .master = &omap44xx_l4_cfg_hwmod, - .slave = &omap44xx_usb_tll_hs_hwmod, - .clk = "l4_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* mpu -> emif1 */ static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = { .master = &omap44xx_mpu_hwmod, @@ -1173,8 +985,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_iva__l3_main_2, &omap44xx_l3_main_1__l3_main_2, &omap44xx_l4_cfg__l3_main_2, - /* &omap44xx_usb_host_fs__l3_main_2, */ - &omap44xx_usb_host_hs__l3_main_2, &omap44xx_l3_main_1__l3_main_3, &omap44xx_l3_main_2__l3_main_3, &omap44xx_l4_cfg__l3_main_3, @@ -1201,9 +1011,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_wkup__prm, &omap44xx_l4_wkup__scrm, /* &omap44xx_l3_main_2__sl2if, */ - /* &omap44xx_l4_cfg__usb_host_fs, */ - &omap44xx_l4_cfg__usb_host_hs, - &omap44xx_l4_cfg__usb_tll_hs, &omap44xx_mpu__emif1, &omap44xx_mpu__emif2, NULL, diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index 4cb194ac7a7e..7c38c1ba58ac 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -267,158 +267,6 @@ static struct omap_hwmod omap54xx_mpu_hwmod = { }; /* - * 'usb_host_hs' class - * high-speed multi-port usb host controller - */ - -static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | - MSTANDBY_SMART | MSTANDBY_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = { - .name = "usb_host_hs", - .sysc = &omap54xx_usb_host_hs_sysc, -}; - -static struct omap_hwmod omap54xx_usb_host_hs_hwmod = { - .name = "usb_host_hs", - .class = &omap54xx_usb_host_hs_hwmod_class, - .clkdm_name = "l3init_clkdm", - /* - * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock - * id: i660 - * - * Description: - * In the following configuration : - * - USBHOST module is set to smart-idle mode - * - PRCM asserts idle_req to the USBHOST module ( This typically - * happens when the system is going to a low power mode : all ports - * have been suspended, the master part of the USBHOST module has - * entered the standby state, and SW has cut the functional clocks) - * - an USBHOST interrupt occurs before the module is able to answer - * idle_ack, typically a remote wakeup IRQ. - * Then the USB HOST module will enter a deadlock situation where it - * is no more accessible nor functional. - * - * Workaround: - * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE - */ - - /* - * Errata: USB host EHCI may stall when entering smart-standby mode - * Id: i571 - * - * Description: - * When the USBHOST module is set to smart-standby mode, and when it is - * ready to enter the standby state (i.e. all ports are suspended and - * all attached devices are in suspend mode), then it can wrongly assert - * the Mstandby signal too early while there are still some residual OCP - * transactions ongoing. If this condition occurs, the internal state - * machine may go to an undefined state and the USB link may be stuck - * upon the next resume. - * - * Workaround: - * Don't use smart standby; use only force standby, - * hence HWMOD_SWSUP_MSTANDBY - */ - - .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, - .main_clk = "l3init_60m_fclk", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * 'usb_tll_hs' class - * usb_tll_hs module is the adapter on the usb_host_hs ports - */ - -static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = { - .name = "usb_tll_hs", - .sysc = &omap54xx_usb_tll_hs_sysc, -}; - -static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = { - .name = "usb_tll_hs", - .class = &omap54xx_usb_tll_hs_hwmod_class, - .clkdm_name = "l3init_clkdm", - .main_clk = "l4_root_clk_div", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - -/* - * 'usb_otg_ss' class - * 2.0 super speed (usb_otg_ss) controller - */ - -static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE | - SYSC_HAS_SIDLEMODE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | - MSTANDBY_SMART | MSTANDBY_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = { - .name = "usb_otg_ss", - .sysc = &omap54xx_usb_otg_ss_sysc, -}; - -/* usb_otg_ss */ -static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = { - { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" }, -}; - -static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = { - .name = "usb_otg_ss", - .class = &omap54xx_usb_otg_ss_hwmod_class, - .clkdm_name = "l3init_clkdm", - .flags = HWMOD_SWSUP_SIDLE, - .main_clk = "dpll_core_h13x2_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, - .opt_clks = usb_otg_ss_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks), -}; - -/* * 'sata' class * sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx) */ @@ -619,30 +467,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_cfg -> usb_host_hs */ -static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = { - .master = &omap54xx_l4_cfg_hwmod, - .slave = &omap54xx_usb_host_hs_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> usb_tll_hs */ -static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = { - .master = &omap54xx_l4_cfg_hwmod, - .slave = &omap54xx_usb_tll_hs_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_cfg -> usb_otg_ss */ -static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = { - .master = &omap54xx_l4_cfg_hwmod, - .slave = &omap54xx_usb_otg_ss_hwmod, - .clk = "dpll_core_h13x2_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { &omap54xx_l3_main_1__dmm, &omap54xx_l3_main_3__l3_instr, @@ -663,9 +487,6 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { &omap54xx_mpu__emif1, &omap54xx_mpu__emif2, &omap54xx_l4_cfg__mpu, - &omap54xx_l4_cfg__usb_host_hs, - &omap54xx_l4_cfg__usb_tll_hs, - &omap54xx_l4_cfg__usb_otg_ss, &omap54xx_l4_cfg__sata, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 07b7458deae4..adb07848de96 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -492,101 +492,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = { }; /* - * 'usb_otg_ss' class - * - */ - -static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE | - SYSC_HAS_SIDLEMODE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | - MSTANDBY_SMART | MSTANDBY_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = { - .name = "usb_otg_ss", - .sysc = &dra7xx_usb_otg_ss_sysc, -}; - -/* usb_otg_ss1 */ -static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = { - { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" }, -}; - -static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = { - .name = "usb_otg_ss1", - .class = &dra7xx_usb_otg_ss_hwmod_class, - .clkdm_name = "l3init_clkdm", - .main_clk = "dpll_core_h13x2_ck", - .flags = HWMOD_CLKDM_NOAUTO, - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, - .opt_clks = usb_otg_ss1_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks), -}; - -/* usb_otg_ss2 */ -static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = { - { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" }, -}; - -static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = { - .name = "usb_otg_ss2", - .class = &dra7xx_usb_otg_ss_hwmod_class, - .clkdm_name = "l3init_clkdm", - .main_clk = "dpll_core_h13x2_ck", - .flags = HWMOD_CLKDM_NOAUTO, - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, - .opt_clks = usb_otg_ss2_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks), -}; - -/* usb_otg_ss3 */ -static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = { - .name = "usb_otg_ss3", - .class = &dra7xx_usb_otg_ss_hwmod_class, - .clkdm_name = "l3init_clkdm", - .main_clk = "dpll_core_h13x2_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - -/* usb_otg_ss4 */ -static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = { - .name = "usb_otg_ss4", - .class = &dra7xx_usb_otg_ss_hwmod_class, - .clkdm_name = "l3init_clkdm", - .main_clk = "dpll_core_h13x2_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - -/* * 'vcp' class * */ @@ -813,38 +718,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_per3 -> usb_otg_ss1 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = { - .master = &dra7xx_l4_per3_hwmod, - .slave = &dra7xx_usb_otg_ss1_hwmod, - .clk = "dpll_core_h13x2_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per3 -> usb_otg_ss2 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = { - .master = &dra7xx_l4_per3_hwmod, - .slave = &dra7xx_usb_otg_ss2_hwmod, - .clk = "dpll_core_h13x2_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per3 -> usb_otg_ss3 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = { - .master = &dra7xx_l4_per3_hwmod, - .slave = &dra7xx_usb_otg_ss3_hwmod, - .clk = "dpll_core_h13x2_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per3 -> usb_otg_ss4 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = { - .master = &dra7xx_l4_per3_hwmod, - .slave = &dra7xx_usb_otg_ss4_hwmod, - .clk = "dpll_core_h13x2_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main_1 -> vcp1 */ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = { .master = &dra7xx_l3_main_1_hwmod, @@ -900,9 +773,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_cfg__pciess2, &dra7xx_l3_main_1__qspi, &dra7xx_l4_cfg__sata, - &dra7xx_l4_per3__usb_otg_ss1, - &dra7xx_l4_per3__usb_otg_ss2, - &dra7xx_l4_per3__usb_otg_ss3, &dra7xx_l3_main_1__vcp1, &dra7xx_l4_per2__vcp1, &dra7xx_l3_main_1__vcp2, @@ -911,20 +781,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { }; /* SoC variant specific hwmod links */ -static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = { - &dra7xx_l4_per3__usb_otg_ss4, - NULL, -}; - -static struct omap_hwmod_ocp_if *acd_76x_hwmod_ocp_ifs[] __initdata = { - NULL, -}; - -static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = { - &dra7xx_l4_per3__usb_otg_ss4, - NULL, -}; - static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = { NULL, }; @@ -942,21 +798,14 @@ int __init dra7xx_hwmod_init(void) ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); if (!ret && soc_is_dra74x()) { - ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs); - if (!ret) - ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs); + ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs); } else if (!ret && soc_is_dra72x()) { ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs); if (!ret && !of_machine_is_compatible("ti,dra718")) ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs); } else if (!ret && soc_is_dra76x()) { - ret = omap_hwmod_register_links(dra76x_hwmod_ocp_ifs); - - if (!ret && soc_is_dra76x_acd()) { - ret = omap_hwmod_register_links(acd_76x_hwmod_ocp_ifs); - } else if (!ret && soc_is_dra76x_abz()) { + if (!ret && soc_is_dra76x_abz()) ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs); - } } return ret; diff --git a/arch/arm/mach-rpc/ecard.c b/arch/arm/mach-rpc/ecard.c index 75cfad2cb143..827b50f1c73e 100644 --- a/arch/arm/mach-rpc/ecard.c +++ b/arch/arm/mach-rpc/ecard.c @@ -63,7 +63,7 @@ struct ecard_request { struct completion *complete; }; -struct expcard_blacklist { +struct expcard_quirklist { unsigned short manufacturer; unsigned short product; const char *type; @@ -79,7 +79,7 @@ static void atomwide_3p_quirk(ecard_t *ec); /* List of descriptions of cards which don't have an extended * identification, or chunk directories containing a description. */ -static struct expcard_blacklist __initdata blacklist[] = { +static struct expcard_quirklist quirklist[] __initdata = { { MANU_ACORN, PROD_ACORN_ETHER1, "Acorn Ether1" }, { MANU_ATOMWIDE, PROD_ATOMWIDE_3PSERIAL, NULL, atomwide_3p_quirk }, }; @@ -935,13 +935,13 @@ static int __init ecard_probe(int slot, unsigned irq, card_type_t type) ec->fiqmask = 4; } - for (i = 0; i < ARRAY_SIZE(blacklist); i++) - if (blacklist[i].manufacturer == ec->cid.manufacturer && - blacklist[i].product == ec->cid.product) { - if (blacklist[i].type) - ec->card_desc = blacklist[i].type; - if (blacklist[i].init) - blacklist[i].init(ec); + for (i = 0; i < ARRAY_SIZE(quirklist); i++) + if (quirklist[i].manufacturer == ec->cid.manufacturer && + quirklist[i].product == ec->cid.product) { + if (quirklist[i].type) + ec->card_desc = quirklist[i].type; + if (quirklist[i].init) + quirklist[i].init(ec); break; } diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index c5c06d98b147..7673dde9671a 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -267,7 +267,7 @@ config MACH_TCT_HAMMER select S3C_DEV_USB_HOST help Say Y here if you are using the TinCanTools Hammer Board - <http://www.tincantools.com> + <https://www.tincantools.com> config MACH_VR1000 bool "Thorcom VR1000" diff --git a/arch/arm/mach-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c index 58e30cad386c..75064dfaceb1 100644 --- a/arch/arm/mach-s3c24xx/common-smdk.c +++ b/arch/arm/mach-s3c24xx/common-smdk.c @@ -14,6 +14,7 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/gpio.h> +#include <linux/gpio/machine.h> #include <linux/device.h> #include <linux/platform_device.h> @@ -44,29 +45,53 @@ /* LED devices */ +static struct gpiod_lookup_table smdk_led4_gpio_table = { + .dev_id = "s3c24xx_led.0", + .table = { + GPIO_LOOKUP("GPF", 4, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN), + { }, + }, +}; + +static struct gpiod_lookup_table smdk_led5_gpio_table = { + .dev_id = "s3c24xx_led.1", + .table = { + GPIO_LOOKUP("GPF", 5, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN), + { }, + }, +}; + +static struct gpiod_lookup_table smdk_led6_gpio_table = { + .dev_id = "s3c24xx_led.2", + .table = { + GPIO_LOOKUP("GPF", 6, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN), + { }, + }, +}; + +static struct gpiod_lookup_table smdk_led7_gpio_table = { + .dev_id = "s3c24xx_led.3", + .table = { + GPIO_LOOKUP("GPF", 7, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN), + { }, + }, +}; + static struct s3c24xx_led_platdata smdk_pdata_led4 = { - .gpio = S3C2410_GPF(4), - .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, .name = "led4", .def_trigger = "timer", }; static struct s3c24xx_led_platdata smdk_pdata_led5 = { - .gpio = S3C2410_GPF(5), - .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, .name = "led5", .def_trigger = "nand-disk", }; static struct s3c24xx_led_platdata smdk_pdata_led6 = { - .gpio = S3C2410_GPF(6), - .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, .name = "led6", }; static struct s3c24xx_led_platdata smdk_pdata_led7 = { - .gpio = S3C2410_GPF(7), - .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, .name = "led7", }; @@ -179,27 +204,25 @@ static struct platform_device __initdata *smdk_devs[] = { &smdk_led7, }; -static const struct gpio smdk_led_gpios[] = { - { S3C2410_GPF(4), GPIOF_OUT_INIT_HIGH, NULL }, - { S3C2410_GPF(5), GPIOF_OUT_INIT_HIGH, NULL }, - { S3C2410_GPF(6), GPIOF_OUT_INIT_HIGH, NULL }, - { S3C2410_GPF(7), GPIOF_OUT_INIT_HIGH, NULL }, -}; - void __init smdk_machine_init(void) { - /* Configure the LEDs (even if we have no LED support)*/ - - int ret = gpio_request_array(smdk_led_gpios, - ARRAY_SIZE(smdk_led_gpios)); - if (!WARN_ON(ret < 0)) - gpio_free_array(smdk_led_gpios, ARRAY_SIZE(smdk_led_gpios)); - if (machine_is_smdk2443()) smdk_nand_info.twrph0 = 50; s3c_nand_set_platdata(&smdk_nand_info); + /* Disable pull-up on the LED lines */ + s3c_gpio_setpull(S3C2410_GPF(4), S3C_GPIO_PULL_NONE); + s3c_gpio_setpull(S3C2410_GPF(5), S3C_GPIO_PULL_NONE); + s3c_gpio_setpull(S3C2410_GPF(6), S3C_GPIO_PULL_NONE); + s3c_gpio_setpull(S3C2410_GPF(7), S3C_GPIO_PULL_NONE); + + /* Add lookups for the lines */ + gpiod_add_lookup_table(&smdk_led4_gpio_table); + gpiod_add_lookup_table(&smdk_led5_gpio_table); + gpiod_add_lookup_table(&smdk_led6_gpio_table); + gpiod_add_lookup_table(&smdk_led7_gpio_table); + platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs)); s3c_pm_init(); diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c index e1c372e5447b..f4710052843a 100644 --- a/arch/arm/mach-s3c24xx/mach-h1940.c +++ b/arch/arm/mach-s3c24xx/mach-h1940.c @@ -3,7 +3,7 @@ // Copyright (c) 2003-2005 Simtec Electronics // Ben Dooks <ben@simtec.co.uk> // -// http://www.handhelds.org/projects/h1940.html +// https://www.handhelds.org/projects/h1940.html #include <linux/kernel.h> #include <linux/types.h> diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c index 9035f868fb34..235749448311 100644 --- a/arch/arm/mach-s3c24xx/mach-mini2440.c +++ b/arch/arm/mach-s3c24xx/mach-mini2440.c @@ -6,7 +6,7 @@ // Weibing <http://weibing.blogbus.com> and // Michel Pollet <buserror@gmail.com> // -// For product information, visit http://code.google.com/p/mini2440/ +// For product information, visit https://code.google.com/p/mini2440/ #include <linux/kernel.h> #include <linux/types.h> @@ -402,37 +402,68 @@ static struct platform_device mini2440_button_device = { /* LEDS */ +static struct gpiod_lookup_table mini2440_led1_gpio_table = { + .dev_id = "s3c24xx_led.1", + .table = { + GPIO_LOOKUP("GPB", 5, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN), + { }, + }, +}; + +static struct gpiod_lookup_table mini2440_led2_gpio_table = { + .dev_id = "s3c24xx_led.2", + .table = { + GPIO_LOOKUP("GPB", 6, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN), + { }, + }, +}; + +static struct gpiod_lookup_table mini2440_led3_gpio_table = { + .dev_id = "s3c24xx_led.3", + .table = { + GPIO_LOOKUP("GPB", 7, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN), + { }, + }, +}; + +static struct gpiod_lookup_table mini2440_led4_gpio_table = { + .dev_id = "s3c24xx_led.4", + .table = { + GPIO_LOOKUP("GPB", 8, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN), + { }, + }, +}; + +static struct gpiod_lookup_table mini2440_backlight_gpio_table = { + .dev_id = "s3c24xx_led.5", + .table = { + GPIO_LOOKUP("GPG", 4, NULL, GPIO_ACTIVE_HIGH), + { }, + }, +}; + static struct s3c24xx_led_platdata mini2440_led1_pdata = { .name = "led1", - .gpio = S3C2410_GPB(5), - .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, .def_trigger = "heartbeat", }; static struct s3c24xx_led_platdata mini2440_led2_pdata = { .name = "led2", - .gpio = S3C2410_GPB(6), - .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, .def_trigger = "nand-disk", }; static struct s3c24xx_led_platdata mini2440_led3_pdata = { .name = "led3", - .gpio = S3C2410_GPB(7), - .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, .def_trigger = "mmc0", }; static struct s3c24xx_led_platdata mini2440_led4_pdata = { .name = "led4", - .gpio = S3C2410_GPB(8), - .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, .def_trigger = "", }; static struct s3c24xx_led_platdata mini2440_led_backlight_pdata = { .name = "backlight", - .gpio = S3C2410_GPG(4), .def_trigger = "backlight", }; @@ -714,6 +745,20 @@ static void __init mini2440_init(void) i2c_register_board_info(0, mini2440_i2c_devs, ARRAY_SIZE(mini2440_i2c_devs)); + /* Disable pull-up on the LED lines */ + s3c_gpio_setpull(S3C2410_GPB(5), S3C_GPIO_PULL_NONE); + s3c_gpio_setpull(S3C2410_GPB(6), S3C_GPIO_PULL_NONE); + s3c_gpio_setpull(S3C2410_GPB(7), S3C_GPIO_PULL_NONE); + s3c_gpio_setpull(S3C2410_GPB(8), S3C_GPIO_PULL_NONE); + s3c_gpio_setpull(S3C2410_GPG(4), S3C_GPIO_PULL_NONE); + + /* Add lookups for the lines */ + gpiod_add_lookup_table(&mini2440_led1_gpio_table); + gpiod_add_lookup_table(&mini2440_led2_gpio_table); + gpiod_add_lookup_table(&mini2440_led3_gpio_table); + gpiod_add_lookup_table(&mini2440_led4_gpio_table); + gpiod_add_lookup_table(&mini2440_backlight_gpio_table); + platform_add_devices(mini2440_devices, ARRAY_SIZE(mini2440_devices)); if (features.count) /* the optional features */ diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c index d856f23939af..998ccff3c174 100644 --- a/arch/arm/mach-s3c24xx/mach-n30.c +++ b/arch/arm/mach-s3c24xx/mach-n30.c @@ -9,7 +9,7 @@ // Copyright (c) 2005-2008 Christer Weinigel <christer@weinigel.se> // // There is a wiki with more information about the n30 port at -// http://handhelds.org/moin/moin.cgi/AcerN30Documentation . +// https://handhelds.org/moin/moin.cgi/AcerN30Documentation . #include <linux/kernel.h> #include <linux/types.h> @@ -45,6 +45,7 @@ #include <plat/cpu.h> #include <plat/devs.h> +#include <plat/gpio-cfg.h> #include <linux/platform_data/mmc-s3cmci.h> #include <linux/platform_data/usb-s3c2410_udc.h> #include <plat/samsung-time.h> @@ -246,17 +247,33 @@ static struct platform_device n35_button_device = { }; /* This is the bluetooth LED on the device. */ + +static struct gpiod_lookup_table n30_blue_led_gpio_table = { + .dev_id = "s3c24xx_led.1", + .table = { + GPIO_LOOKUP("GPG", 6, NULL, GPIO_ACTIVE_HIGH), + { }, + }, +}; + static struct s3c24xx_led_platdata n30_blue_led_pdata = { .name = "blue_led", - .gpio = S3C2410_GPG(6), .def_trigger = "", }; /* This is the blue LED on the device. Originally used to indicate GPS activity * by flashing. */ + +static struct gpiod_lookup_table n35_blue_led_gpio_table = { + .dev_id = "s3c24xx_led.1", + .table = { + GPIO_LOOKUP("GPD", 8, NULL, GPIO_ACTIVE_HIGH), + { }, + }, +}; + static struct s3c24xx_led_platdata n35_blue_led_pdata = { .name = "blue_led", - .gpio = S3C2410_GPD(8), .def_trigger = "", }; @@ -264,17 +281,30 @@ static struct s3c24xx_led_platdata n35_blue_led_pdata = { * red, blinking green or solid green when the battery is low, * charging or full respectively. By driving GPD9 low, it's possible * to force the LED to blink red, so call that warning LED. */ + +static struct gpiod_lookup_table n30_warning_led_gpio_table = { + .dev_id = "s3c24xx_led.2", + .table = { + GPIO_LOOKUP("GPD", 9, NULL, GPIO_ACTIVE_LOW), + { }, + }, +}; + static struct s3c24xx_led_platdata n30_warning_led_pdata = { .name = "warning_led", - .flags = S3C24XX_LEDF_ACTLOW, - .gpio = S3C2410_GPD(9), .def_trigger = "", }; +static struct gpiod_lookup_table n35_warning_led_gpio_table = { + .dev_id = "s3c24xx_led.2", + .table = { + GPIO_LOOKUP("GPD", 9, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN), + { }, + }, +}; + static struct s3c24xx_led_platdata n35_warning_led_pdata = { .name = "warning_led", - .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, - .gpio = S3C2410_GPD(9), .def_trigger = "", }; @@ -577,6 +607,12 @@ static void __init n30_init(void) S3C2410_MISCCR_USBSUSPND0 | S3C2410_MISCCR_USBSUSPND1, 0x0); + /* Disable pull-up and add GPIO tables */ + s3c_gpio_setpull(S3C2410_GPG(6), S3C_GPIO_PULL_NONE); + s3c_gpio_setpull(S3C2410_GPD(9), S3C_GPIO_PULL_NONE); + gpiod_add_lookup_table(&n30_blue_led_gpio_table); + gpiod_add_lookup_table(&n30_warning_led_gpio_table); + platform_add_devices(n30_devices, ARRAY_SIZE(n30_devices)); } @@ -594,6 +630,12 @@ static void __init n30_init(void) S3C2410_MISCCR_USBSUSPND1, S3C2410_MISCCR_USBSUSPND0); + /* Disable pull-up and add GPIO tables */ + s3c_gpio_setpull(S3C2410_GPD(8), S3C_GPIO_PULL_NONE); + s3c_gpio_setpull(S3C2410_GPD(9), S3C_GPIO_PULL_NONE); + gpiod_add_lookup_table(&n35_blue_led_gpio_table); + gpiod_add_lookup_table(&n35_warning_led_gpio_table); + platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices)); } } diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c index 5d48e5b6e738..ff9e3197309b 100644 --- a/arch/arm/mach-s3c24xx/mach-qt2410.c +++ b/arch/arm/mach-s3c24xx/mach-qt2410.c @@ -177,9 +177,15 @@ static struct platform_device qt2410_cs89x0 = { /* LED */ +static struct gpiod_lookup_table qt2410_led_gpio_table = { + .dev_id = "s3c24xx_led.0", + .table = { + GPIO_LOOKUP("GPB", 0, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN), + { }, + }, +}; + static struct s3c24xx_led_platdata qt2410_pdata_led = { - .gpio = S3C2410_GPB(0), - .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, .name = "led", .def_trigger = "timer", }; @@ -338,6 +344,8 @@ static void __init qt2410_machine_init(void) s3c_i2c0_set_platdata(NULL); gpiod_add_lookup_table(&qt2410_spi_gpiod_table); + s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE); + gpiod_add_lookup_table(&qt2410_led_gpio_table); platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices)); s3c_pm_init(); } diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c index 529c6faf862f..995f1ff34a1b 100644 --- a/arch/arm/mach-s3c24xx/mach-rx3715.c +++ b/arch/arm/mach-s3c24xx/mach-rx3715.c @@ -3,7 +3,7 @@ // Copyright (c) 2003-2004 Simtec Electronics // Ben Dooks <ben@simtec.co.uk> // -// http://www.handhelds.org/projects/rx3715.html +// https://www.handhelds.org/projects/rx3715.html #include <linux/kernel.h> #include <linux/types.h> diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c index 853e74f9b8b5..6a3fb2becc7c 100644 --- a/arch/arm/mach-s3c24xx/mach-vr1000.c +++ b/arch/arm/mach-s3c24xx/mach-vr1000.c @@ -13,6 +13,7 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/gpio.h> +#include <linux/gpio/machine.h> #include <linux/dm9000.h> #include <linux/i2c.h> @@ -40,6 +41,7 @@ #include <plat/cpu.h> #include <plat/devs.h> +#include <plat/gpio-cfg.h> #include <plat/samsung-time.h> #include "bast.h" @@ -223,21 +225,42 @@ static struct platform_device vr1000_dm9k1 = { /* LEDS */ +static struct gpiod_lookup_table vr1000_led1_gpio_table = { + .dev_id = "s3c24xx_led.1", + .table = { + GPIO_LOOKUP("GPB", 0, NULL, GPIO_ACTIVE_HIGH), + { }, + }, +}; + +static struct gpiod_lookup_table vr1000_led2_gpio_table = { + .dev_id = "s3c24xx_led.2", + .table = { + GPIO_LOOKUP("GPB", 1, NULL, GPIO_ACTIVE_HIGH), + { }, + }, +}; + +static struct gpiod_lookup_table vr1000_led3_gpio_table = { + .dev_id = "s3c24xx_led.3", + .table = { + GPIO_LOOKUP("GPB", 2, NULL, GPIO_ACTIVE_HIGH), + { }, + }, +}; + static struct s3c24xx_led_platdata vr1000_led1_pdata = { .name = "led1", - .gpio = S3C2410_GPB(0), .def_trigger = "", }; static struct s3c24xx_led_platdata vr1000_led2_pdata = { .name = "led2", - .gpio = S3C2410_GPB(1), .def_trigger = "", }; static struct s3c24xx_led_platdata vr1000_led3_pdata = { .name = "led3", - .gpio = S3C2410_GPB(2), .def_trigger = "", }; @@ -317,6 +340,15 @@ static void __init vr1000_init_time(void) static void __init vr1000_init(void) { s3c_i2c0_set_platdata(NULL); + + /* Disable pull-up on LED lines and register GPIO lookups */ + s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE); + s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_NONE); + s3c_gpio_setpull(S3C2410_GPB(2), S3C_GPIO_PULL_NONE); + gpiod_add_lookup_table(&vr1000_led1_gpio_table); + gpiod_add_lookup_table(&vr1000_led2_gpio_table); + gpiod_add_lookup_table(&vr1000_led3_gpio_table); + platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices)); i2c_register_board_info(0, vr1000_i2c_devs, diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c index aa265ede5730..2012fa8c28cf 100644 --- a/arch/arm/mach-sa1100/assabet.c +++ b/arch/arm/mach-sa1100/assabet.c @@ -652,7 +652,7 @@ static void __init map_sa1100_gpio_regs( void ) */ static void __init get_assabet_scr(void) { - unsigned long uninitialized_var(scr), i; + unsigned long scr, i; GPDR |= 0x3fc; /* Configure GPIO 9:2 as outputs */ GPSR = 0x3fc; /* Write 0xFF to GPIO 9:2 */ diff --git a/arch/arm/mach-socfpga/pm.c b/arch/arm/mach-socfpga/pm.c index 6ed887cf8dc9..365c0428b21b 100644 --- a/arch/arm/mach-socfpga/pm.c +++ b/arch/arm/mach-socfpga/pm.c @@ -49,14 +49,14 @@ static int socfpga_setup_ocram_self_refresh(void) if (!ocram_pool) { pr_warn("%s: ocram pool unavailable!\n", __func__); ret = -ENODEV; - goto put_node; + goto put_device; } ocram_base = gen_pool_alloc(ocram_pool, socfpga_sdram_self_refresh_sz); if (!ocram_base) { pr_warn("%s: unable to alloc ocram!\n", __func__); ret = -ENOMEM; - goto put_node; + goto put_device; } ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base); @@ -67,7 +67,7 @@ static int socfpga_setup_ocram_self_refresh(void) if (!suspend_ocram_base) { pr_warn("%s: __arm_ioremap_exec failed!\n", __func__); ret = -ENOMEM; - goto put_node; + goto put_device; } /* Copy the code that puts DDR in self refresh to ocram */ @@ -81,6 +81,8 @@ static int socfpga_setup_ocram_self_refresh(void) if (!socfpga_sdram_self_refresh_in_ocram) ret = -EFAULT; +put_device: + put_device(&pdev->dev); put_node: of_node_put(np); diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c index dcb98937fcf5..ffecbf29646f 100644 --- a/arch/arm/mach-sti/board-dt.c +++ b/arch/arm/mach-sti/board-dt.c @@ -20,14 +20,6 @@ static const char *const stih41x_dt_match[] __initconst = { NULL }; -static void sti_l2_write_sec(unsigned long val, unsigned reg) -{ - /* - * We can't write to secure registers as we are in non-secure - * mode, until we have some SMI service available. - */ -} - DT_MACHINE_START(STM, "STi SoC with Flattened Device Tree") .dt_compat = stih41x_dt_match, .l2c_aux_val = L2C_AUX_CTRL_SHARED_OVERRIDE | @@ -36,5 +28,4 @@ DT_MACHINE_START(STM, "STi SoC with Flattened Device Tree") L2C_AUX_CTRL_WAY_SIZE(4), .l2c_aux_mask = 0xc0000fff, .smp = smp_ops(sti_smp_ops), - .l2c_write_sec = sti_l2_write_sec, MACHINE_END diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index 84718eddae60..f4bfc1cac91a 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c @@ -774,7 +774,7 @@ static int alignment_get_arm(struct pt_regs *regs, u32 *ip, u32 *inst) if (user_mode(regs)) fault = get_user(instr, ip); else - fault = probe_kernel_address(ip, instr); + fault = get_kernel_nofault(instr, ip); *inst = __mem_to_opcode_arm(instr); @@ -789,7 +789,7 @@ static int alignment_get_thumb(struct pt_regs *regs, u16 *ip, u16 *inst) if (user_mode(regs)) fault = get_user(instr, ip); else - fault = probe_kernel_address(ip, instr); + fault = get_kernel_nofault(instr, ip); *inst = __mem_to_opcode_thumb16(instr); @@ -799,7 +799,7 @@ static int alignment_get_thumb(struct pt_regs *regs, u16 *ip, u16 *inst) static int do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) { - union offset_union uninitialized_var(offset); + union offset_union offset; unsigned long instrptr; int (*handler)(unsigned long addr, u32 instr, struct pt_regs *regs); unsigned int type; diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 628028bfbb92..bcd82614c25d 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -966,7 +966,7 @@ void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md, pud_t *pud; p4d = p4d_alloc(mm, pgd_offset(mm, md->virtual), md->virtual); - if (!WARN_ON(!p4d)) + if (WARN_ON(!p4d)) return; pud = pud_alloc(mm, p4d, md->virtual); if (WARN_ON(!pud)) diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 7d859994ff95..b2e9e822426f 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -16,7 +16,7 @@ * * Support functions for the OMAP internal DMA channels. * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ * Converted DMA library into DMA platform driver. * - G, Manjunath Kondaiah <manjugk@ti.com> */ diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index 26a531ebb6e9..734f0be4f14a 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c @@ -442,6 +442,7 @@ static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) struct orion_gpio_chip *ochip = gpiochip_get_data(chip); u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; + const char *label; int i; out = readl_relaxed(GPIO_OUT(ochip)); @@ -453,15 +454,10 @@ static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) edg_msk = readl_relaxed(GPIO_EDGE_MASK(ochip)); lvl_msk = readl_relaxed(GPIO_LEVEL_MASK(ochip)); - for (i = 0; i < chip->ngpio; i++) { - const char *label; + for_each_requested_gpio(chip, i, label) { u32 msk; bool is_out; - label = gpiochip_is_requested(chip, i); - if (!label) - continue; - msk = 1 << i; is_out = !(io_conf & msk); diff --git a/arch/arm/tools/syscall.tbl b/arch/arm/tools/syscall.tbl index d5cae5ffede0..7e8ee4adf269 100644 --- a/arch/arm/tools/syscall.tbl +++ b/arch/arm/tools/syscall.tbl @@ -449,6 +449,7 @@ 433 common fspick sys_fspick 434 common pidfd_open sys_pidfd_open 435 common clone3 sys_clone3 +436 common close_range sys_close_range 437 common openat2 sys_openat2 438 common pidfd_getfd sys_pidfd_getfd 439 common faccessat2 sys_faccessat2 diff --git a/arch/arm/vdso/Makefile b/arch/arm/vdso/Makefile index d3c9f03e7e79..a54f70731d9f 100644 --- a/arch/arm/vdso/Makefile +++ b/arch/arm/vdso/Makefile @@ -29,7 +29,7 @@ CPPFLAGS_vdso.lds += -P -C -U$(ARCH) CFLAGS_REMOVE_vdso.o = -pg # Force -O2 to avoid libgcc dependencies -CFLAGS_REMOVE_vgettimeofday.o = -pg -Os +CFLAGS_REMOVE_vgettimeofday.o = -pg -Os $(GCC_PLUGINS_CFLAGS) ifeq ($(c-gettimeofday-y),) CFLAGS_vgettimeofday.o = -O2 else diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c index fd4e1ce1daf9..e93145d72c26 100644 --- a/arch/arm/xen/enlighten.c +++ b/arch/arm/xen/enlighten.c @@ -241,7 +241,6 @@ static int __init fdt_find_hyper_node(unsigned long node, const char *uname, * see Documentation/devicetree/bindings/arm/xen.txt for the * documentation of the Xen Device Tree format. */ -#define GRANT_TABLE_PHYSADDR 0 void __init xen_early_init(void) { of_scan_flat_dt(fdt_find_hyper_node, NULL); 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