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-rw-r--r--arch/arm64/boot/dts/allwinner/axp803.dtsi10
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts14
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts41
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts25
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi160
-rw-r--r--arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi1
-rw-r--r--arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts7
-rw-r--r--arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts6
-rw-r--r--arch/arm64/boot/dts/amlogic/Makefile1
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-a1.dtsi1
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-axg.dtsi1
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi6
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-g12a.dtsi5
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts722
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi42
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-g12b.dtsi5
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gx.dtsi1
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi14
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts1
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxl.dtsi14
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts1
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts1
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-sm1.dtsi5
-rw-r--r--arch/arm64/boot/dts/apple/Makefile6
-rw-r--r--arch/arm64/boot/dts/apple/multi-die-cpp.h22
-rw-r--r--arch/arm64/boot/dts/apple/t6000-j314s.dts18
-rw-r--r--arch/arm64/boot/dts/apple/t6000-j316s.dts18
-rw-r--r--arch/arm64/boot/dts/apple/t6000.dtsi18
-rw-r--r--arch/arm64/boot/dts/apple/t6001-j314c.dts18
-rw-r--r--arch/arm64/boot/dts/apple/t6001-j316c.dts18
-rw-r--r--arch/arm64/boot/dts/apple/t6001-j375c.dts18
-rw-r--r--arch/arm64/boot/dts/apple/t6001.dtsi63
-rw-r--r--arch/arm64/boot/dts/apple/t6002-j375d.dts50
-rw-r--r--arch/arm64/boot/dts/apple/t6002.dtsi301
-rw-r--r--arch/arm64/boot/dts/apple/t600x-common.dtsi374
-rw-r--r--arch/arm64/boot/dts/apple/t600x-die0.dtsi361
-rw-r--r--arch/arm64/boot/dts/apple/t600x-dieX.dtsi121
-rw-r--r--arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi45
-rw-r--r--arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi114
-rw-r--r--arch/arm64/boot/dts/apple/t600x-j375.dtsi117
-rw-r--r--arch/arm64/boot/dts/apple/t600x-nvme.dtsi42
-rw-r--r--arch/arm64/boot/dts/apple/t600x-pmgr.dtsi2012
-rw-r--r--arch/arm64/boot/dts/apple/t8103-j456.dts2
-rw-r--r--arch/arm64/boot/dts/apple/t8103-j457.dts2
-rw-r--r--arch/arm64/boot/dts/apple/t8103-jxxx.dtsi4
-rw-r--r--arch/arm64/boot/dts/apple/t8103-pmgr.dtsi2
-rw-r--r--arch/arm64/boot/dts/apple/t8103.dtsi322
-rw-r--r--arch/arm64/boot/dts/arm/corstone1000.dtsi1
-rw-r--r--arch/arm64/boot/dts/arm/foundation-v8.dtsi6
-rw-r--r--arch/arm64/boot/dts/arm/fvp-base-revc.dts73
-rw-r--r--arch/arm64/boot/dts/arm/juno-r1.dts2
-rw-r--r--arch/arm64/boot/dts/arm/juno-r2.dts2
-rw-r--r--arch/arm64/boot/dts/arm/juno.dts2
-rw-r--r--arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts1
-rw-r--r--arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts1
-rw-r--r--arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi6
-rw-r--r--arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi1
-rw-r--r--arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi1
-rw-r--r--arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi1
-rw-r--r--arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi1
-rw-r--r--arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi1
-rw-r--r--arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi20
-rw-r--r--arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts2
-rw-r--r--arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts2
-rw-r--r--arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi1
-rw-r--r--arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi4
-rw-r--r--arch/arm64/boot/dts/freescale/Makefile2
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dtso (renamed from arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts)0
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dtso (renamed from arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts)0
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtso (renamed from arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts)0
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dtso (renamed from arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts)0
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dtso (renamed from arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts)0
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtso (renamed from arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts)0
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi1
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi1
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi1
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi4
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi4
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi8
-rw-r--r--arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi39
-rw-r--r--arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi164
-rw-r--r--arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi17
-rw-r--r--arch/arm64/boot/dts/freescale/imx8dxl-evk.dts107
-rw-r--r--arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi20
-rw-r--r--arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi10
-rw-r--r--arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi46
-rw-r--r--arch/arm64/boot/dts/freescale/imx8dxl.dtsi7
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi6
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts24
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-evk.dts6
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi6
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts146
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi480
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi4
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi4
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-phg.dts266
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi6
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi6
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi30
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dtso (renamed from arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts)0
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtso (renamed from arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts)0
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtso (renamed from arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts)0
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dtso (renamed from arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts)0
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dtso (renamed from arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts)0
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtso (renamed from arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts)0
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtso (renamed from arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts)0
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtso (renamed from arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts)0
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts54
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts66
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts42
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts54
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi16
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm.dtsi6
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi6
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts6
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mn-evk.dts3
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi47
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts62
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mn.dtsi7
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi31
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mp-evk.dts111
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts159
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts48
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi1
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi49
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mp.dtsi34
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mq-evk.dts9
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts22
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi6
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi2
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mq.dtsi16
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi38
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qm.dtsi2
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi2
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi25
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qxp.dtsi1
-rw-r--r--arch/arm64/boot/dts/freescale/imx8ulp.dtsi1
-rw-r--r--arch/arm64/boot/dts/freescale/imx93.dtsi111
-rw-r--r--arch/arm64/boot/dts/freescale/mba8mx.dtsi1
-rw-r--r--arch/arm64/boot/dts/freescale/s32g2.dtsi2
-rw-r--r--arch/arm64/boot/dts/freescale/s32v234.dtsi2
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi3660.dtsi2
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi6220.dtsi2
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip05.dtsi4
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip06.dtsi4
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip07.dtsi16
-rw-r--r--arch/arm64/boot/dts/intel/socfpga_agilex.dtsi1
-rw-r--r--arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts1
-rw-r--r--arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts1
-rw-r--r--arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi1
-rw-r--r--arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts4
-rw-r--r--arch/arm64/boot/dts/marvell/armada-37xx.dtsi5
-rw-r--r--arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi1
-rw-r--r--arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi2
-rw-r--r--arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi2
-rw-r--r--arch/arm64/boot/dts/marvell/armada-ap80x.dtsi5
-rw-r--r--arch/arm64/boot/dts/mediatek/Makefile1
-rw-r--r--arch/arm64/boot/dts/mediatek/mt2712-evb.dts12
-rw-r--r--arch/arm64/boot/dts/mediatek/mt2712e.dtsi28
-rw-r--r--arch/arm64/boot/dts/mediatek/mt6779.dtsi10
-rw-r--r--arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts88
-rw-r--r--arch/arm64/boot/dts/mediatek/mt6795.dtsi109
-rw-r--r--arch/arm64/boot/dts/mediatek/mt6797.dtsi2
-rw-r--r--arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts1
-rw-r--r--arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts1
-rw-r--r--arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts135
-rw-r--r--arch/arm64/boot/dts/mediatek/mt7986a.dtsi74
-rw-r--r--arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts57
-rw-r--r--arch/arm64/boot/dts/mediatek/mt7986b.dtsi3
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi6
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8186.dtsi3
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8192.dtsi3
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi86
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8195.dtsi233
-rw-r--r--arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi6
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra132-norrin.dts2
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra132.dtsi1
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra186.dtsi12
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi2
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi4
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi2
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra194.dtsi70
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi5
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts4
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210.dtsi61
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi8
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts21
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi14
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra234.dtsi666
-rw-r--r--arch/arm64/boot/dts/qcom/Makefile27
-rw-r--r--arch/arm64/boot/dts/qcom/apq8016-sbc.dts16
-rw-r--r--arch/arm64/boot/dts/qcom/apq8096-db820c.dts114
-rw-r--r--arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts70
-rw-r--r--arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts11
-rw-r--r--arch/arm64/boot/dts/qcom/ipq6018.dtsi25
-rw-r--r--arch/arm64/boot/dts/qcom/ipq8074-hk01.dts10
-rw-r--r--arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts3
-rw-r--r--arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts3
-rw-r--r--arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi21
-rw-r--r--arch/arm64/boot/dts/qcom/ipq8074.dtsi134
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts80
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts24
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts24
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts22
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts8
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-pins.dtsi276
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi2
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi112
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts14
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts10
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi28
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts2
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts2
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts45
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts47
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916.dtsi17
-rw-r--r--arch/arm64/boot/dts/qcom/msm8953.dtsi314
-rw-r--r--arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-kugo.dts35
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-rw-r--r--arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi4
-rw-r--r--arch/arm64/boot/dts/ti/k3-am625-sk.dts81
-rw-r--r--arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi2
-rw-r--r--arch/arm64/boot/dts/ti/k3-am64-main.dtsi44
-rw-r--r--arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi6
-rw-r--r--arch/arm64/boot/dts/ti/k3-am642-evm.dts119
-rw-r--r--arch/arm64/boot/dts/ti/k3-am642-sk.dts142
-rw-r--r--arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi101
-rw-r--r--arch/arm64/boot/dts/ti/k3-am65-main.dtsi207
-rw-r--r--arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi85
-rw-r--r--arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi2
-rw-r--r--arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi1
-rw-r--r--arch/arm64/boot/dts/ti/k3-am654-base-board.dts113
-rw-r--r--arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi4
-rw-r--r--arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts48
-rw-r--r--arch/arm64/boot/dts/ti/k3-j7200-main.dtsi29
-rw-r--r--arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi8
-rw-r--r--arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi42
-rw-r--r--arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts1055
-rw-r--r--arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts143
-rw-r--r--arch/arm64/boot/dts/ti/k3-j721e-main.dtsi125
-rw-r--r--arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi11
-rw-r--r--arch/arm64/boot/dts/ti/k3-j721e-sk.dts205
-rw-r--r--arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi33
-rw-r--r--arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts132
-rw-r--r--arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi79
-rw-r--r--arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi9
-rw-r--r--arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi98
466 files changed, 36710 insertions, 7336 deletions
diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi b/arch/arm64/boot/dts/allwinner/axp803.dtsi
index 578ef368e2b4..a6b4b87f185d 100644
--- a/arch/arm64/boot/dts/allwinner/axp803.dtsi
+++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi
@@ -25,16 +25,6 @@
compatible = "x-powers,axp803-gpio", "x-powers,axp813-gpio";
gpio-controller;
#gpio-cells = <2>;
-
- gpio0_ldo: gpio0-ldo-pin {
- pins = "GPIO0";
- function = "ldo";
- };
-
- gpio1_ldo: gpio1-ldo-pin {
- pins = "GPIO1";
- function = "ldo";
- };
};
battery_power_supply: battery-power {
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
index 620cb3ef5f6c..50ed2e9f10ed 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
@@ -406,6 +406,20 @@
status = "okay";
};
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8723cs-bt";
+ device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */
+ enable-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+ host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+ };
+};
+
&usb_otg {
dr_mode = "host";
};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
index 02893f3ac99d..cb8600d0ea1e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
@@ -49,8 +49,24 @@
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
+
+ reg_usb1_vbus: regulator-usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&reg_vcc5v>;
+ enable-active-high;
+ gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
+ };
};
+&ehci1 {
+ status = "okay";
+};
+
+/* USB 2 & 3 are on headers only. */
+
&emac0 {
pinctrl-names = "default";
pinctrl-0 = <&ext_rgmii_pins>;
@@ -76,6 +92,10 @@
status = "okay";
};
+&ohci1 {
+ status = "okay";
+};
+
&r_rsb {
status = "okay";
@@ -211,3 +231,24 @@
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
+
+&usbotg {
+ /*
+ * PHY0 pins are connected to a USB-C socket, but a role switch
+ * is not implemented: both CC pins are pulled to GND.
+ * The VBUS pins power the device, so a fixed peripheral mode
+ * is the best choice.
+ * The board can be powered via GPIOs, in this case port0 *can*
+ * act as a host (with a cable/adapter ignoring CC), as VBUS is
+ * then provided by the GPIOs. Any user of this setup would
+ * need to adjust the DT accordingly: dr_mode set to "host",
+ * enabling OHCI0 and EHCI0.
+ */
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
index 6619db34714a..07424c28b696 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
@@ -32,6 +32,14 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
&ir {
status = "okay";
};
@@ -54,6 +62,14 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
&r_rsb {
status = "okay";
@@ -175,3 +191,12 @@
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
+
+&usbotg {
+ dr_mode = "host"; /* USB A type receptable */
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
index 622a1f7d1641..74aed0d232a9 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -504,6 +504,166 @@
};
};
+ usbotg: usb@5100000 {
+ compatible = "allwinner,sun50i-h616-musb",
+ "allwinner,sun8i-h3-musb";
+ reg = <0x05100000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ status = "disabled";
+ };
+
+ usbphy: phy@5100400 {
+ compatible = "allwinner,sun50i-h616-usb-phy";
+ reg = <0x05100400 0x24>,
+ <0x05101800 0x14>,
+ <0x05200800 0x14>,
+ <0x05310800 0x14>,
+ <0x05311800 0x14>;
+ reg-names = "phy_ctrl",
+ "pmu0",
+ "pmu1",
+ "pmu2",
+ "pmu3";
+ clocks = <&ccu CLK_USB_PHY0>,
+ <&ccu CLK_USB_PHY1>,
+ <&ccu CLK_USB_PHY2>,
+ <&ccu CLK_USB_PHY3>,
+ <&ccu CLK_BUS_EHCI2>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy",
+ "usb3_phy",
+ "pmu2_clk";
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY1>,
+ <&ccu RST_USB_PHY2>,
+ <&ccu RST_USB_PHY3>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset",
+ "usb3_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci0: usb@5101000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05101000 0x100>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_BUS_EHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>,
+ <&ccu RST_BUS_EHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@5101400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05101400 0x100>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci1: usb@5200000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05200000 0x100>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_BUS_EHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>,
+ <&ccu RST_BUS_EHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@5200400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05200400 0x100>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci2: usb@5310000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05310000 0x100>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI2>,
+ <&ccu CLK_BUS_EHCI2>,
+ <&ccu CLK_USB_OHCI2>;
+ resets = <&ccu RST_BUS_OHCI2>,
+ <&ccu RST_BUS_EHCI2>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci2: usb@5310400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05310400 0x100>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI2>,
+ <&ccu CLK_USB_OHCI2>;
+ resets = <&ccu RST_BUS_OHCI2>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci3: usb@5311000 {
+ compatible = "allwinner,sun50i-h616-ehci",
+ "generic-ehci";
+ reg = <0x05311000 0x100>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI3>,
+ <&ccu CLK_BUS_EHCI3>,
+ <&ccu CLK_USB_OHCI3>;
+ resets = <&ccu RST_BUS_OHCI3>,
+ <&ccu RST_BUS_EHCI3>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci3: usb@5311400 {
+ compatible = "allwinner,sun50i-h616-ohci",
+ "generic-ohci";
+ reg = <0x05311400 0x100>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI3>,
+ <&ccu CLK_USB_OHCI3>;
+ resets = <&ccu RST_BUS_OHCI3>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
rtc: rtc@7000000 {
compatible = "allwinner,sun50i-h616-rtc";
reg = <0x07000000 0x400>;
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 14c220d87807..55c5e1fdddc7 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -309,6 +309,7 @@
<&clkmgr STRATIX10_SDMMC_CLK>;
clock-names = "biu", "ciu";
iommus = <&smmu 5>;
+ altr,sysmgr-syscon = <&sysmgr 0x28 4>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 48424e459f12..17752ca743e5 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -22,17 +22,17 @@
leds {
compatible = "gpio-leds";
- hps0 {
+ led-hps0 {
label = "hps_led0";
gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
};
- hps1 {
+ led-hps1 {
label = "hps_led1";
gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
};
- hps2 {
+ led-hps2 {
label = "hps_led2";
gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
};
@@ -105,6 +105,7 @@
cap-mmc-highspeed;
broken-cd;
bus-width = <4>;
+ clk-phase-sd-hs = <0>, <135>;
};
&osc1 {
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
index 847a7c01f5af..ede99dcc0558 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
@@ -22,17 +22,17 @@
leds {
compatible = "gpio-leds";
- hps0 {
+ led-hps0 {
label = "hps_led0";
gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
};
- hps1 {
+ led-hps1 {
label = "hps_led1";
gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
};
- hps2 {
+ led-hps2 {
label = "hps_led2";
gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
};
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index e213aeebb774..97b42e2100e0 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gsking-x.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-go-ultra.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index b4000cf65a9a..d2f7cb4e5375 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -36,6 +36,7 @@
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 04f797b5a012..1648e67afbb6 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -105,6 +105,7 @@
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
index 45947c1031c4..9dbd50820b1c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
@@ -1705,6 +1705,12 @@
};
};
+ pmu: pmu@ff638000 {
+ reg = <0x0 0xff638000 0x0 0x100>,
+ <0x0 0xff638c00 0x0 0x100>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>;
+ };
+
aobus: bus@ff800000 {
compatible = "simple-bus";
reg = <0x0 0xff800000 0x0 0x100000>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index fb0ab27d1f64..7677764eeee6 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -50,6 +50,7 @@
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
@@ -133,3 +134,7 @@
};
};
};
+
+&pmu {
+ compatible = "amlogic,g12a-ddr-pmu";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts
new file mode 100644
index 000000000000..1e40709610c5
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts
@@ -0,0 +1,722 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Neil Armstrong <neil.armstrong@linaro.org>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-s922x.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-toacodec.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "hardkernel,odroid-go-ultra", "amlogic,s922x", "amlogic,g12b";
+ model = "Hardkernel ODROID-GO-Ultra";
+
+ aliases {
+ serial0 = &uart_AO;
+ rtc0 = &vrtc;
+ };
+
+ adc-joystick-left {
+ compatible = "adc-joystick";
+ io-channels = <&saradc 2>, <&saradc 3>;
+ poll-interval = <10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ axis@0 {
+ reg = <0>;
+ linux,code = <ABS_Y>;
+ abs-range = <3150 950>;
+ abs-fuzz = <32>;
+ abs-flat = <64>;
+ };
+ axis@1 {
+ reg = <1>;
+ linux,code = <ABS_X>;
+ abs-range = <700 2900>;
+ abs-fuzz = <32>;
+ abs-flat = <64>;
+ };
+ };
+
+ adc-joystick-right {
+ compatible = "adc-joystick";
+ io-channels = <&saradc 0>, <&saradc 1>;
+ poll-interval = <10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ axis@0 {
+ reg = <0>;
+ linux,code = <ABS_RY>;
+ abs-range = <3150 950>;
+ abs-fuzz = <32>;
+ abs-flat = <64>;
+ };
+ axis@1 {
+ reg = <1>;
+ linux,code = <ABS_RX>;
+ abs-range = <800 3000>;
+ abs-fuzz = <32>;
+ abs-flat = <64>;
+ };
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ codec_clk: codec-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <12288000>;
+ clock-output-names = "codec_clk";
+ #clock-cells = <0>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <10>;
+ pinctrl-0 = <&keypad_gpio_pins>;
+ pinctrl-names = "default";
+
+ volume-up-button {
+ label = "VOLUME-UP";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&gpio GPIOX_8 GPIO_ACTIVE_LOW>;
+ };
+ volume-down-button {
+ label = "VOLUME-DOWN";
+ linux,code = <KEY_VOLUMEDOWN>;
+ gpios = <&gpio GPIOX_9 GPIO_ACTIVE_LOW>;
+ };
+ dpad-up-button {
+ label = "DPAD-UP";
+ linux,code = <BTN_DPAD_UP>;
+ gpios = <&gpio GPIOX_0 GPIO_ACTIVE_LOW>;
+ };
+ dpad-down-button {
+ label = "DPAD-DOWN";
+ linux,code = <BTN_DPAD_DOWN>;
+ gpios = <&gpio GPIOX_1 GPIO_ACTIVE_LOW>;
+ };
+ dpad-left-button {
+ label = "DPAD-LEFT";
+ linux,code = <BTN_DPAD_LEFT>;
+ gpios = <&gpio GPIOX_2 GPIO_ACTIVE_LOW>;
+ };
+ dpad-right-button {
+ label = "DPAD-RIGHT";
+ linux,code = <BTN_DPAD_RIGHT>;
+ gpios = <&gpio GPIOX_3 GPIO_ACTIVE_LOW>;
+ };
+ a-button {
+ label = "A";
+ linux,code = <BTN_EAST>;
+ gpios = <&gpio GPIOX_4 GPIO_ACTIVE_LOW>;
+ };
+ b-button {
+ label = "B";
+ linux,code = <BTN_SOUTH>;
+ gpios = <&gpio GPIOX_5 GPIO_ACTIVE_LOW>;
+ };
+ y-button {
+ label = "Y";
+ linux,code = <BTN_WEST>;
+ gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ };
+ x-button {
+ label = "X";
+ linux,code = <BTN_NORTH>;
+ gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
+ };
+ f1-button {
+ label = "F1";
+ linux,code = <BTN_TRIGGER_HAPPY1>;
+ gpios = <&gpio GPIOX_17 GPIO_ACTIVE_LOW>;
+ };
+ f2-button {
+ label = "F2";
+ linux,code = <BTN_TRIGGER_HAPPY2>;
+ gpios = <&gpio GPIOX_10 GPIO_ACTIVE_LOW>;
+ };
+ f3-button {
+ label = "F3";
+ linux,code = <BTN_TRIGGER_HAPPY3>;
+ gpios = <&gpio GPIOX_11 GPIO_ACTIVE_LOW>;
+ };
+ f4-button {
+ label = "F4";
+ linux,code = <BTN_TRIGGER_HAPPY4>;
+ gpios = <&gpio GPIOX_12 GPIO_ACTIVE_LOW>;
+ };
+ f5-button {
+ label = "F5";
+ linux,code = <BTN_TRIGGER_HAPPY5>;
+ gpios = <&gpio GPIOX_13 GPIO_ACTIVE_LOW>;
+ };
+ f6-button {
+ label = "F6";
+ linux,code = <BTN_TRIGGER_HAPPY6>;
+ gpios = <&gpio GPIOX_16 GPIO_ACTIVE_LOW>;
+ };
+ top-left-button {
+ label = "TOP Left";
+ linux,code = <BTN_TL>;
+ gpios = <&gpio GPIOX_14 GPIO_ACTIVE_LOW>;
+ };
+ top-left2-button {
+ label = "TOP Left 2";
+ linux,code = <BTN_TL2>;
+ gpios = <&gpio GPIOX_19 GPIO_ACTIVE_LOW>;
+ };
+ top-right-button {
+ label = "TOP Right";
+ linux,code = <BTN_TR>;
+ gpios = <&gpio GPIOX_15 GPIO_ACTIVE_LOW>;
+ };
+ top-right2-button {
+ label = "TOP Right 2";
+ linux,code = <BTN_TR2>;
+ gpios = <&gpio GPIOX_18 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ vdd_sys: regulator-vdd-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_SYS";
+ regulator-min-microvolt = <3800000>;
+ regulator-max-microvolt = <3800000>;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "Odroid GO Ultra";
+ audio-widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones",
+ "Speaker", "Internal Speakers";
+ audio-aux-devs = <&tdmout_b>, <&tdmin_b>, <&speaker_amp>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT",
+ "TDMIN_B IN 1", "TDM_B Capture",
+ "TDMIN_B IN 4", "TDM_B Loopback",
+ "TODDR_A IN 1", "TDMIN_B OUT",
+ "MICL", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "Speaker Amplifier INL", "HPOL",
+ "Speaker Amplifier INR", "HPOR",
+ "Internal Speakers", "Speaker Amplifier OUTL",
+ "Internal Speakers", "Speaker Amplifier OUTR";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&toddr_a>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&rk817>;
+ };
+ };
+ };
+
+ speaker_amp: speaker-amplifier {
+ compatible = "simple-audio-amplifier";
+ sound-name-prefix = "Speaker Amplifier";
+ VCC-supply = <&hp_5v>;
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu100 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu101 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu102 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu103 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+/* RK817 only supports 12.5mV steps, round up the values */
+&cpu_opp_table_0 {
+ opp-1000000000 {
+ opp-microvolt = <737500>;
+ };
+ opp-1200000000 {
+ opp-microvolt = <737500>;
+ };
+ opp-1398000000 {
+ opp-microvolt = <762500>;
+ };
+ opp-1512000000 {
+ opp-microvolt = <800000>;
+ };
+ opp-1608000000 {
+ opp-microvolt = <837500>;
+ };
+ opp-1704000000 {
+ opp-microvolt = <862500>;
+ };
+ opp-1896000000 {
+ opp-microvolt = <987500>;
+ };
+ opp-1992000000 {
+ opp-microvolt = <1012500>;
+ };
+};
+
+/* RK818 only supports 12.5mV steps, round up the values */
+&cpub_opp_table_1 {
+ opp-1000000000 {
+ opp-microvolt = <775000>;
+ };
+ opp-1200000000 {
+ opp-microvolt = <775000>;
+ };
+ opp-1398000000 {
+ opp-microvolt = <800000>;
+ };
+ opp-1512000000 {
+ opp-microvolt = <825000>;
+ };
+ opp-1608000000 {
+ opp-microvolt = <862500>;
+ };
+ opp-1704000000 {
+ opp-microvolt = <900000>;
+ };
+ opp-1800000000 {
+ opp-microvolt = <987500>;
+ };
+ opp-1908000000 {
+ opp-microvolt = <1025000>;
+ };
+};
+
+&i2c_AO {
+ status = "okay";
+ pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>;
+ pinctrl-names = "default";
+
+ rk818: pmic@1c {
+ compatible = "rockchip,rk818";
+ reg = <0x1c>;
+ interrupt-parent = <&gpio_intc>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_7 */
+
+ vcc1-supply = <&vdd_sys>;
+ vcc2-supply = <&vdd_sys>;
+ vcc3-supply = <&vdd_sys>;
+ vcc4-supply = <&vdd_sys>;
+ vcc6-supply = <&vdd_sys>;
+ vcc7-supply = <&vcc_2v3>;
+ vcc8-supply = <&vcc_2v3>;
+ vcc9-supply = <&vddao_3v3>;
+ boost-supply = <&vdd_sys>;
+ switch-supply = <&vdd_sys>;
+
+ regulators {
+ vddcpu_a: DCDC_REG1 {
+ regulator-name = "vddcpu_a";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <775000>;
+ regulator-max-microvolt = <1025000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <775000>;
+ };
+ };
+
+ vdd_ee: DCDC_REG2 {
+ regulator-name = "vdd_ee";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <875000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <875000>;
+ };
+ };
+
+ vddq_1v1: DCDC_REG3 {
+ regulator-name = "vddq_1v1";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vddao_3v3: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vddao_3v3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ hp_5v: DCDC_BOOST {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "hp_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vddio_ao1v8: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vddio_ao1v8";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vddq_1v8: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vddq_1v8";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vddio_c: LDO_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vddio_c";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_sd: SWITCH_REG {
+ regulator-name = "vcc_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ OTG_SWITCH {
+ regulator-name = "otg_switch";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c3 {
+ status = "okay";
+ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+ pinctrl-names = "default";
+
+ rk817: pmic@20 {
+ compatible = "rockchip,rk817";
+ reg = <0x20>;
+ interrupt-parent = <&gpio_intc>;
+
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_5 */
+
+ vcc1-supply = <&vdd_sys>;
+ vcc2-supply = <&vdd_sys>;
+ vcc3-supply = <&vdd_sys>;
+ vcc4-supply = <&vdd_sys>;
+ vcc5-supply = <&vdd_sys>;
+ vcc6-supply = <&vdd_sys>;
+ vcc7-supply = <&vdd_sys>;
+ vcc8-supply = <&vdd_sys>;
+ vcc9-supply = <&rk817_boost>;
+
+ #sound-dai-cells = <0>;
+ clocks = <&codec_clk>;
+ clock-names = "mclk";
+
+ #clock-cells = <1>;
+
+ regulators {
+ vddcpu_b: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <737500>;
+ regulator-max-microvolt = <1012500>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vddcpu_b";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc_2v3: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2300000>;
+ regulator-max-microvolt = <2400000>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc_2v3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vdd_codec";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_lcd: LDO_REG8 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_lcd";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk817_boost: BOOST {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5400000>;
+ regulator-name = "rk817_boost";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ usb_host: OTG_SWITCH {
+ regulator-name = "usb_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&eth_phy {
+ status = "disabled";
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&periphs_pinctrl {
+ keypad_gpio_pins: keypad-gpio {
+ mux {
+ groups = "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3",
+ "GPIOX_4", "GPIOX_5", "GPIOX_6", "GPIOX_7",
+ "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11",
+ "GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15",
+ "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19";
+ function = "gpio_periphs";
+ bias-pull-up;
+ output-disable;
+ };
+ };
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao1v8>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vddio_c>;
+
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vddio_ao1v8>;
+};
+
+
+&tdmif_b {
+ pinctrl-0 = <&tdm_b_dout0_pins>, <&tdm_b_fs_pins>, <&tdm_b_sclk_pins>, <&tdm_b_din1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD1>,
+ <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD1>;
+ assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_B_SCLK>,
+ <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
+ assigned-clock-rates = <0>, <0>;
+};
+
+&tdmin_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&toddr_a {
+ status = "okay";
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "peripheral";
+};
+
+&usb2_phy0 {
+ status = "okay";
+};
+
+&usb2_phy1 {
+ status = "okay";
+ phy-supply = <&usb_host>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
index fd3fa82e4c33..667d2b774924 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
@@ -39,6 +39,14 @@
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
};
+ fan: gpio-fan {
+ compatible = "gpio-fan";
+ gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_HIGH>;
+ /* Using Dummy Speed */
+ gpio-fan,speed-map = <0 0>, <1 1>;
+ #cooling-cells = <2>;
+ };
+
leds {
compatible = "gpio-leds";
@@ -410,6 +418,40 @@
clock-latency = <50000>;
};
+&cpu_thermal {
+ trips {
+ cpu_active: cpu-active {
+ temperature = <60000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map {
+ trip = <&cpu_active>;
+ cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&ddr_thermal {
+ trips {
+ ddr_active: ddr-active {
+ temperature = <60000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map {
+ trip = <&ddr_active>;
+ cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
&ext_mdio {
external_phy: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
index ee8fcae9f9f0..75ff00fb2e4c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
@@ -105,6 +105,7 @@
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
};
@@ -139,3 +140,7 @@
&mali {
dma-coherent;
};
+
+&pmu {
+ compatible = "amlogic,g12b-ddr-pmu";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 023a52005494..e3c12e0be99d 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -132,6 +132,7 @@
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 7c029f552a23..923d2d8bbb9c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -427,6 +427,20 @@
};
};
+ spi_idle_high_pins: spi-idle-high-pins {
+ mux {
+ groups = "spi_sclk";
+ bias-pull-up;
+ };
+ };
+
+ spi_idle_low_pins: spi-idle-low-pins {
+ mux {
+ groups = "spi_sclk";
+ bias-pull-down;
+ };
+ };
+
spi_ss0_pins: spi-ss0 {
mux {
groups = "spi_ss0";
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
index 6ab1cc125b96..202deb4e2d63 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
@@ -140,7 +140,6 @@
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
- clock-frequency = <32768>;
clock-output-names = "xin32k";
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index c3ac531c4f84..04e9d0f1bde0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -429,6 +429,20 @@
};
};
+ spi_idle_high_pins: spi-idle-high-pins {
+ mux {
+ groups = "spi_sclk";
+ bias-pull-up;
+ };
+ };
+
+ spi_idle_low_pins: spi-idle-low-pins {
+ mux {
+ groups = "spi_sclk";
+ bias-pull-down;
+ };
+ };
+
spi_ss0_pins: spi-ss0 {
mux {
groups = "spi_ss0";
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
index f43c45daf7eb..b21172ece1fa 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
@@ -270,7 +270,6 @@
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
- clock-frequency = <32768>;
clock-output-names = "xin32k";
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts
index b8ef3bd8b840..1703da3235ea 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts
@@ -89,7 +89,6 @@
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
- clock-frequency = <32768>;
clock-output-names = "xin32k";
wakeup-source;
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
index 80737731af3f..56ca0ba2241e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
@@ -88,6 +88,7 @@
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
@@ -520,6 +521,10 @@
power-domains = <&pwrc PWRC_SM1_PCIE_ID>;
};
+&pmu {
+ compatible = "amlogic,sm1-ddr-pmu";
+};
+
&pwrc {
compatible = "amlogic,meson-sm1-pwrc";
};
diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile
index c0510c25ca6a..5a7506ff5ea3 100644
--- a/arch/arm64/boot/dts/apple/Makefile
+++ b/arch/arm64/boot/dts/apple/Makefile
@@ -4,3 +4,9 @@ dtb-$(CONFIG_ARCH_APPLE) += t8103-j293.dtb
dtb-$(CONFIG_ARCH_APPLE) += t8103-j313.dtb
dtb-$(CONFIG_ARCH_APPLE) += t8103-j456.dtb
dtb-$(CONFIG_ARCH_APPLE) += t8103-j457.dtb
+dtb-$(CONFIG_ARCH_APPLE) += t6000-j314s.dtb
+dtb-$(CONFIG_ARCH_APPLE) += t6001-j314c.dtb
+dtb-$(CONFIG_ARCH_APPLE) += t6000-j316s.dtb
+dtb-$(CONFIG_ARCH_APPLE) += t6001-j316c.dtb
+dtb-$(CONFIG_ARCH_APPLE) += t6001-j375c.dtb
+dtb-$(CONFIG_ARCH_APPLE) += t6002-j375d.dtb
diff --git a/arch/arm64/boot/dts/apple/multi-die-cpp.h b/arch/arm64/boot/dts/apple/multi-die-cpp.h
new file mode 100644
index 000000000000..39e8953bf809
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/multi-die-cpp.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR MIT
+ *
+ * C preprocessor macros for t600x multi die support.
+ */
+
+#ifndef __DTS_APPLE_MULTI_DIE_CPP_H
+#define __DTS_APPLE_MULTI_DIE_CPP_H
+
+#ifndef __stringify
+#define __stringify_1(x...) #x
+#define __stringify(x...) __stringify_1(x)
+#endif
+
+#ifndef __concat
+#define __concat_1(x, y...) x ## y
+#define __concat(x, y...) __concat_1(x, y)
+#endif
+
+#define DIE_NODE(a) __concat(a, DIE)
+#define DIE_LABEL(a) __stringify(__concat(a, DIE))
+
+#endif /* !__DTS_APPLE_MULTI_DIE_CPP_H */
diff --git a/arch/arm64/boot/dts/apple/t6000-j314s.dts b/arch/arm64/boot/dts/apple/t6000-j314s.dts
new file mode 100644
index 000000000000..c9e192848fe3
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/t6000-j314s.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * MacBook Pro (14-inch, M1 Pro, 2021)
+ *
+ * target-type: J314s
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+/dts-v1/;
+
+#include "t6000.dtsi"
+#include "t600x-j314-j316.dtsi"
+
+/ {
+ compatible = "apple,j314s", "apple,t6000", "apple,arm-platform";
+ model = "Apple MacBook Pro (14-inch, M1 Pro, 2021)";
+};
diff --git a/arch/arm64/boot/dts/apple/t6000-j316s.dts b/arch/arm64/boot/dts/apple/t6000-j316s.dts
new file mode 100644
index 000000000000..ff1803ce2300
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/t6000-j316s.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * MacBook Pro (16-inch, M1 Pro, 2021)
+ *
+ * target-type: J316s
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+/dts-v1/;
+
+#include "t6000.dtsi"
+#include "t600x-j314-j316.dtsi"
+
+/ {
+ compatible = "apple,j316s", "apple,t6000", "apple,arm-platform";
+ model = "Apple MacBook Pro (16-inch, M1 Pro, 2021)";
+};
diff --git a/arch/arm64/boot/dts/apple/t6000.dtsi b/arch/arm64/boot/dts/apple/t6000.dtsi
new file mode 100644
index 000000000000..89c3b211b116
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/t6000.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Apple T6000 "M1 Pro" SoC
+ *
+ * Other names: H13J, "Jade Chop"
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+/* This chip is just a cut down version of t6001, so include it and disable the missing parts */
+
+#include "t6001.dtsi"
+
+/ {
+ compatible = "apple,t6000", "apple,arm-platform";
+};
+
+/delete-node/ &pmgr_south;
diff --git a/arch/arm64/boot/dts/apple/t6001-j314c.dts b/arch/arm64/boot/dts/apple/t6001-j314c.dts
new file mode 100644
index 000000000000..1761d15b98c1
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/t6001-j314c.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * MacBook Pro (14-inch, M1 Max, 2021)
+ *
+ * target-type: J314c
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+/dts-v1/;
+
+#include "t6001.dtsi"
+#include "t600x-j314-j316.dtsi"
+
+/ {
+ compatible = "apple,j314c", "apple,t6001", "apple,arm-platform";
+ model = "Apple MacBook Pro (14-inch, M1 Max, 2021)";
+};
diff --git a/arch/arm64/boot/dts/apple/t6001-j316c.dts b/arch/arm64/boot/dts/apple/t6001-j316c.dts
new file mode 100644
index 000000000000..750e9beeffc0
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/t6001-j316c.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * MacBook Pro (16-inch, M1 Max, 2021)
+ *
+ * target-type: J316c
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+/dts-v1/;
+
+#include "t6001.dtsi"
+#include "t600x-j314-j316.dtsi"
+
+/ {
+ compatible = "apple,j316c", "apple,t6001", "apple,arm-platform";
+ model = "Apple MacBook Pro (16-inch, M1 Max, 2021)";
+};
diff --git a/arch/arm64/boot/dts/apple/t6001-j375c.dts b/arch/arm64/boot/dts/apple/t6001-j375c.dts
new file mode 100644
index 000000000000..62ea437b58b2
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/t6001-j375c.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Mac Studio (M1 Max, 2022)
+ *
+ * target-type: J375c
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+/dts-v1/;
+
+#include "t6001.dtsi"
+#include "t600x-j375.dtsi"
+
+/ {
+ compatible = "apple,j375c", "apple,t6001", "apple,arm-platform";
+ model = "Apple Mac Studio (M1 Max, 2022)";
+};
diff --git a/arch/arm64/boot/dts/apple/t6001.dtsi b/arch/arm64/boot/dts/apple/t6001.dtsi
new file mode 100644
index 000000000000..620b17e4031f
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/t6001.dtsi
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Apple T6001 "M1 Max" SoC
+ *
+ * Other names: H13J, "Jade"
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/apple-aic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/apple.h>
+
+#include "multi-die-cpp.h"
+
+#include "t600x-common.dtsi"
+
+/ {
+ compatible = "apple,t6001", "apple,arm-platform";
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges;
+ nonposted-mmio;
+
+ // filled via templated includes at the end of the file
+ };
+};
+
+#define DIE
+#define DIE_NO 0
+
+&{/soc} {
+ #include "t600x-die0.dtsi"
+ #include "t600x-dieX.dtsi"
+ #include "t600x-nvme.dtsi"
+};
+
+#include "t600x-gpio-pins.dtsi"
+#include "t600x-pmgr.dtsi"
+
+#undef DIE
+#undef DIE_NO
+
+
+&aic {
+ affinities {
+ e-core-pmu-affinity {
+ apple,fiq-index = <AIC_CPU_PMU_E>;
+ cpus = <&cpu_e00 &cpu_e01>;
+ };
+
+ p-core-pmu-affinity {
+ apple,fiq-index = <AIC_CPU_PMU_P>;
+ cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03
+ &cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/apple/t6002-j375d.dts b/arch/arm64/boot/dts/apple/t6002-j375d.dts
new file mode 100644
index 000000000000..3365429bdc8b
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/t6002-j375d.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Mac Studio (M1 Ultra, 2022)
+ *
+ * target-type: J375d
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+/dts-v1/;
+
+#include "t6002.dtsi"
+#include "t600x-j375.dtsi"
+
+/ {
+ compatible = "apple,j375d", "apple,t6002", "apple,arm-platform";
+ model = "Apple Mac Studio (M1 Ultra, 2022)";
+};
+
+/* USB Type C */
+&i2c0 {
+ /* front-right */
+ hpm4: usb-pd@39 {
+ compatible = "apple,cd321x";
+ reg = <0x39>;
+ interrupt-parent = <&pinctrl_ap>;
+ interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "irq";
+ };
+
+ /* front-left */
+ hpm5: usb-pd@3a {
+ compatible = "apple,cd321x";
+ reg = <0x3a>;
+ interrupt-parent = <&pinctrl_ap>;
+ interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "irq";
+ };
+};
+
+/* delete unused always-on power-domains on die 1 */
+
+/delete-node/ &ps_atc2_usb_aon_die1;
+/delete-node/ &ps_atc2_usb_die1;
+
+/delete-node/ &ps_atc3_usb_aon_die1;
+/delete-node/ &ps_atc3_usb_die1;
+
+/delete-node/ &ps_disp0_cpu0_die1;
+/delete-node/ &ps_disp0_fe_die1;
diff --git a/arch/arm64/boot/dts/apple/t6002.dtsi b/arch/arm64/boot/dts/apple/t6002.dtsi
new file mode 100644
index 000000000000..a963a5011799
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/t6002.dtsi
@@ -0,0 +1,301 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Apple T6002 "M1 Ultra" SoC
+ *
+ * Other names: H13J, "Jade 2C"
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/apple-aic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/apple.h>
+
+#include "multi-die-cpp.h"
+
+#include "t600x-common.dtsi"
+
+/ {
+ compatible = "apple,t6002", "apple,arm-platform";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ cpu-map {
+ cluster3 {
+ core0 {
+ cpu = <&cpu_e10>;
+ };
+ core1 {
+ cpu = <&cpu_e11>;
+ };
+ };
+
+ cluster4 {
+ core0 {
+ cpu = <&cpu_p20>;
+ };
+ core1 {
+ cpu = <&cpu_p21>;
+ };
+ core2 {
+ cpu = <&cpu_p22>;
+ };
+ core3 {
+ cpu = <&cpu_p23>;
+ };
+ };
+
+ cluster5 {
+ core0 {
+ cpu = <&cpu_p30>;
+ };
+ core1 {
+ cpu = <&cpu_p31>;
+ };
+ core2 {
+ cpu = <&cpu_p32>;
+ };
+ core3 {
+ cpu = <&cpu_p33>;
+ };
+ };
+ };
+
+ cpu_e10: cpu@800 {
+ compatible = "apple,icestorm";
+ device_type = "cpu";
+ reg = <0x0 0x800>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_3>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
+ operating-points-v2 = <&icestorm_opp>;
+ capacity-dmips-mhz = <714>;
+ performance-domains = <&cpufreq_e_die1>;
+ };
+
+ cpu_e11: cpu@801 {
+ compatible = "apple,icestorm";
+ device_type = "cpu";
+ reg = <0x0 0x801>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_3>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
+ operating-points-v2 = <&icestorm_opp>;
+ capacity-dmips-mhz = <714>;
+ performance-domains = <&cpufreq_e_die1>;
+ };
+
+ cpu_p20: cpu@10900 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10900>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_4>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ operating-points-v2 = <&firestorm_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p0_die1>;
+ };
+
+ cpu_p21: cpu@10901 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10901>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_4>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ operating-points-v2 = <&firestorm_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p0_die1>;
+ };
+
+ cpu_p22: cpu@10902 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10902>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_4>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ operating-points-v2 = <&firestorm_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p0_die1>;
+ };
+
+ cpu_p23: cpu@10903 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10903>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_4>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ operating-points-v2 = <&firestorm_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p0_die1>;
+ };
+
+ cpu_p30: cpu@10a00 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10a00>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_5>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ operating-points-v2 = <&firestorm_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p1_die1>;
+ };
+
+ cpu_p31: cpu@10a01 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10a01>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_5>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ operating-points-v2 = <&firestorm_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p1_die1>;
+ };
+
+ cpu_p32: cpu@10a02 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10a02>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_5>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ operating-points-v2 = <&firestorm_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p1_die1>;
+ };
+
+ cpu_p33: cpu@10a03 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10a03>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_5>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ operating-points-v2 = <&firestorm_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p1_die1>;
+ };
+
+ l2_cache_3: l2-cache-3 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x400000>;
+ };
+
+ l2_cache_4: l2-cache-4 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0xc00000>;
+ };
+
+ l2_cache_5: l2-cache-5 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0xc00000>;
+ };
+ };
+
+ die0: soc@200000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x2 0x0 0x2 0x0 0x4 0x0>,
+ <0x5 0x80000000 0x5 0x80000000 0x1 0x80000000>,
+ <0x7 0x0 0x7 0x0 0xf 0x80000000>;
+ nonposted-mmio;
+
+ // filled via templated includes at the end of the file
+ };
+
+ die1: soc@2200000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x2 0x0 0x22 0x0 0x4 0x0>,
+ <0x7 0x0 0x27 0x0 0xf 0x80000000>;
+ nonposted-mmio;
+
+ // filled via templated includes at the end of the file
+ };
+};
+
+#define DIE
+#define DIE_NO 0
+
+&die0 {
+ #include "t600x-die0.dtsi"
+ #include "t600x-dieX.dtsi"
+};
+
+#include "t600x-pmgr.dtsi"
+#include "t600x-gpio-pins.dtsi"
+
+#undef DIE
+#undef DIE_NO
+
+#define DIE _die1
+#define DIE_NO 1
+
+&die1 {
+ #include "t600x-dieX.dtsi"
+ #include "t600x-nvme.dtsi"
+};
+
+#include "t600x-pmgr.dtsi"
+
+#undef DIE
+#undef DIE_NO
+
+&aic {
+ affinities {
+ e-core-pmu-affinity {
+ apple,fiq-index = <AIC_CPU_PMU_E>;
+ cpus = <&cpu_e00 &cpu_e01
+ &cpu_e10 &cpu_e11>;
+ };
+
+ p-core-pmu-affinity {
+ apple,fiq-index = <AIC_CPU_PMU_P>;
+ cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03
+ &cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13
+ &cpu_p20 &cpu_p21 &cpu_p22 &cpu_p23
+ &cpu_p30 &cpu_p31 &cpu_p32 &cpu_p33>;
+ };
+ };
+};
+
+&ps_gfx {
+ // On t6002, the die0 GPU power domain needs both AFR power domains
+ power-domains = <&ps_afr>, <&ps_afr_die1>;
+};
diff --git a/arch/arm64/boot/dts/apple/t600x-common.dtsi b/arch/arm64/boot/dts/apple/t600x-common.dtsi
new file mode 100644
index 000000000000..fa8ead699363
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/t600x-common.dtsi
@@ -0,0 +1,374 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Common Apple T6000 / T6001 / T6002 "M1 Pro/Max/Ultra" SoC
+ *
+ * Other names: H13J, "Jade Chop", "Jade", "Jade 2C"
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu_e00>;
+ };
+ core1 {
+ cpu = <&cpu_e01>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu_p00>;
+ };
+ core1 {
+ cpu = <&cpu_p01>;
+ };
+ core2 {
+ cpu = <&cpu_p02>;
+ };
+ core3 {
+ cpu = <&cpu_p03>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&cpu_p10>;
+ };
+ core1 {
+ cpu = <&cpu_p11>;
+ };
+ core2 {
+ cpu = <&cpu_p12>;
+ };
+ core3 {
+ cpu = <&cpu_p13>;
+ };
+ };
+ };
+
+ cpu_e00: cpu@0 {
+ compatible = "apple,icestorm";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
+ operating-points-v2 = <&icestorm_opp>;
+ capacity-dmips-mhz = <714>;
+ performance-domains = <&cpufreq_e>;
+ };
+
+ cpu_e01: cpu@1 {
+ compatible = "apple,icestorm";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
+ operating-points-v2 = <&icestorm_opp>;
+ capacity-dmips-mhz = <714>;
+ performance-domains = <&cpufreq_e>;
+ };
+
+ cpu_p00: cpu@10100 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10100>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ operating-points-v2 = <&firestorm_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p0>;
+ };
+
+ cpu_p01: cpu@10101 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10101>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ operating-points-v2 = <&firestorm_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p0>;
+ };
+
+ cpu_p02: cpu@10102 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10102>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ operating-points-v2 = <&firestorm_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p0>;
+ };
+
+ cpu_p03: cpu@10103 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10103>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ operating-points-v2 = <&firestorm_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p0>;
+ };
+
+ cpu_p10: cpu@10200 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10200>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_2>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ operating-points-v2 = <&firestorm_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p1>;
+ };
+
+ cpu_p11: cpu@10201 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10201>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_2>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ operating-points-v2 = <&firestorm_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p1>;
+ };
+
+ cpu_p12: cpu@10202 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10202>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_2>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ operating-points-v2 = <&firestorm_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p1>;
+ };
+
+ cpu_p13: cpu@10203 {
+ compatible = "apple,firestorm";
+ device_type = "cpu";
+ reg = <0x0 0x10203>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0>; /* To be filled by loader */
+ next-level-cache = <&l2_cache_2>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ operating-points-v2 = <&firestorm_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p1>;
+ };
+
+ l2_cache_0: l2-cache-0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x400000>;
+ };
+
+ l2_cache_1: l2-cache-1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0xc00000>;
+ };
+
+ l2_cache_2: l2-cache-2 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0xc00000>;
+ };
+ };
+
+ icestorm_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+
+ opp01 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-level = <1>;
+ clock-latency-ns = <7500>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <972000000>;
+ opp-level = <2>;
+ clock-latency-ns = <23000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1332000000>;
+ opp-level = <3>;
+ clock-latency-ns = <29000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1704000000>;
+ opp-level = <4>;
+ clock-latency-ns = <40000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <2064000000>;
+ opp-level = <5>;
+ clock-latency-ns = <50000>;
+ };
+ };
+
+ firestorm_opp: opp-table-1 {
+ compatible = "operating-points-v2";
+
+ opp01 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-level = <1>;
+ clock-latency-ns = <8000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <828000000>;
+ opp-level = <2>;
+ clock-latency-ns = <18000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-level = <3>;
+ clock-latency-ns = <19000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-level = <4>;
+ clock-latency-ns = <23000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1524000000>;
+ opp-level = <5>;
+ clock-latency-ns = <24000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1752000000>;
+ opp-level = <6>;
+ clock-latency-ns = <28000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1980000000>;
+ opp-level = <7>;
+ clock-latency-ns = <31000>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-level = <8>;
+ clock-latency-ns = <45000>;
+ };
+ opp09 {
+ opp-hz = /bits/ 64 <2448000000>;
+ opp-level = <9>;
+ clock-latency-ns = <49000>;
+ };
+ opp10 {
+ opp-hz = /bits/ 64 <2676000000>;
+ opp-level = <10>;
+ clock-latency-ns = <53000>;
+ };
+ opp11 {
+ opp-hz = /bits/ 64 <2904000000>;
+ opp-level = <11>;
+ clock-latency-ns = <56000>;
+ };
+ opp12 {
+ opp-hz = /bits/ 64 <3036000000>;
+ opp-level = <12>;
+ clock-latency-ns = <56000>;
+ };
+ /* Not available until CPU deep sleep is implemented
+ opp13 {
+ opp-hz = /bits/ 64 <3132000000>;
+ opp-level = <13>;
+ clock-latency-ns = <56000>;
+ turbo-mode;
+ };
+ opp14 {
+ opp-hz = /bits/ 64 <3168000000>;
+ opp-level = <14>;
+ clock-latency-ns = <56000>;
+ turbo-mode;
+ };
+ opp15 {
+ opp-hz = /bits/ 64 <3228000000>;
+ opp-level = <15>;
+ clock-latency-ns = <56000>;
+ turbo-mode;
+ };
+ */
+ };
+
+ pmu-e {
+ compatible = "apple,icestorm-pmu";
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_FIQ 0 AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pmu-p {
+ compatible = "apple,firestorm-pmu";
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_FIQ 0 AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&aic>;
+ interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
+ interrupts = <AIC_FIQ 0 AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_FIQ 0 AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_FIQ 0 AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_FIQ 0 AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ clkref: clock-ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "clkref";
+ };
+
+ /*
+ * This is a fabulated representation of the input clock
+ * to NCO since we don't know the true clock tree.
+ */
+ nco_clkref: clock-ref-nco {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "nco_ref";
+ };
+};
diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dts/apple/t600x-die0.dtsi
new file mode 100644
index 000000000000..1c41954e3899
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi
@@ -0,0 +1,361 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Devices used on die 0 on the Apple T6002 "M1 Ultra" SoC and present on
+ * Apple T6000 / T6001 "M1 Pro" / "M1 Max".
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+
+ nco: clock-controller@28e03c000 {
+ compatible = "apple,t6000-nco", "apple,nco";
+ reg = <0x2 0x8e03c000 0x0 0x14000>;
+ clocks = <&nco_clkref>;
+ #clock-cells = <1>;
+ };
+
+ aic: interrupt-controller@28e100000 {
+ compatible = "apple,t6000-aic", "apple,aic2";
+ #interrupt-cells = <4>;
+ interrupt-controller;
+ reg = <0x2 0x8e100000 0x0 0xc000>,
+ <0x2 0x8e10c000 0x0 0x4>;
+ reg-names = "core", "event";
+ power-domains = <&ps_aic>;
+ };
+
+ pinctrl_smc: pinctrl@290820000 {
+ compatible = "apple,t6000-pinctrl", "apple,pinctrl";
+ reg = <0x2 0x90820000 0x0 0x4000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_smc 0 0 30>;
+ apple,npins = <30>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 0 743 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 0 744 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 0 745 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 0 746 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 0 747 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 0 748 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 0 749 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wdt: watchdog@2922b0000 {
+ compatible = "apple,t6000-wdt", "apple,wdt";
+ reg = <0x2 0x922b0000 0x0 0x4000>;
+ clocks = <&clkref>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 0 631 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sio_dart_0: iommu@39b004000 {
+ compatible = "apple,t6000-dart";
+ reg = <0x3 0x9b004000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 0 1130 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ power-domains = <&ps_sio_cpu>;
+ };
+
+ sio_dart_1: iommu@39b008000 {
+ compatible = "apple,t6000-dart";
+ reg = <0x3 0x9b008000 0x0 0x8000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 0 1130 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ power-domains = <&ps_sio_cpu>;
+ };
+
+ i2c0: i2c@39b040000 {
+ compatible = "apple,t6000-i2c", "apple,i2c";
+ reg = <0x3 0x9b040000 0x0 0x4000>;
+ clocks = <&clkref>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 0 1119 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ power-domains = <&ps_i2c0>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ i2c1: i2c@39b044000 {
+ compatible = "apple,t6000-i2c", "apple,i2c";
+ reg = <0x3 0x9b044000 0x0 0x4000>;
+ clocks = <&clkref>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 0 1120 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+ power-domains = <&ps_i2c1>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@39b048000 {
+ compatible = "apple,t6000-i2c", "apple,i2c";
+ reg = <0x3 0x9b048000 0x0 0x4000>;
+ clocks = <&clkref>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 0 1121 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+ power-domains = <&ps_i2c2>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@39b04c000 {
+ compatible = "apple,t6000-i2c", "apple,i2c";
+ reg = <0x3 0x9b04c000 0x0 0x4000>;
+ clocks = <&clkref>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 0 1122 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
+ power-domains = <&ps_i2c3>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@39b050000 {
+ compatible = "apple,t6000-i2c", "apple,i2c";
+ reg = <0x3 0x9b050000 0x0 0x4000>;
+ clocks = <&clkref>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 0 1123 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-names = "default";
+ power-domains = <&ps_i2c4>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@39b054000 {
+ compatible = "apple,t6000-i2c", "apple,i2c";
+ reg = <0x3 0x9b054000 0x0 0x4000>;
+ clocks = <&clkref>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 0 1124 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c5_pins>;
+ pinctrl-names = "default";
+ power-domains = <&ps_i2c5>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ status = "disabled";
+ };
+
+ serial0: serial@39b200000 {
+ compatible = "apple,s5l-uart";
+ reg = <0x3 0x9b200000 0x0 0x1000>;
+ reg-io-width = <4>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 0 1097 IRQ_TYPE_LEVEL_HIGH>;
+ /*
+ * TODO: figure out the clocking properly, there may
+ * be a third selectable clock.
+ */
+ clocks = <&clkref>, <&clkref>;
+ clock-names = "uart", "clk_uart_baud0";
+ power-domains = <&ps_uart0>;
+ status = "disabled";
+ };
+
+ admac: dma-controller@39b400000 {
+ compatible = "apple,t6000-admac", "apple,admac";
+ reg = <0x3 0x9b400000 0x0 0x34000>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ interrupts-extended = <0>,
+ <&aic AIC_IRQ 0 1118 IRQ_TYPE_LEVEL_HIGH>,
+ <0>,
+ <0>;
+ iommus = <&sio_dart_0 2>, <&sio_dart_1 2>;
+ power-domains = <&ps_sio_adma>;
+ resets = <&ps_audio_p>;
+ };
+
+ mca: mca@39b600000 {
+ compatible = "apple,t6000-mca", "apple,mca";
+ reg = <0x3 0x9b600000 0x0 0x10000>,
+ <0x3 0x9b500000 0x0 0x20000>;
+ clocks = <&nco 0>, <&nco 1>, <&nco 2>, <&nco 3>;
+ dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>,
+ <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>,
+ <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>,
+ <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>;
+ dma-names = "tx0a", "rx0a", "tx0b", "rx0b",
+ "tx1a", "rx1a", "tx1b", "rx1b",
+ "tx2a", "rx2a", "tx2b", "rx2b",
+ "tx3a", "rx3a", "tx3b", "rx3b";
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 0 1112 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 0 1113 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 0 1114 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 0 1115 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>,
+ <&ps_mca2>, <&ps_mca3>;
+ resets = <&ps_audio_p>;
+ #sound-dai-cells = <1>;
+ };
+
+ pcie0_dart_0: iommu@581008000 {
+ compatible = "apple,t6000-dart";
+ reg = <0x5 0x81008000 0x0 0x4000>;
+ #iommu-cells = <1>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 0 1271 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&ps_apcie_gp_sys>;
+ };
+
+ pcie0_dart_1: iommu@582008000 {
+ compatible = "apple,t6000-dart";
+ reg = <0x5 0x82008000 0x0 0x4000>;
+ #iommu-cells = <1>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 0 1274 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&ps_apcie_gp_sys>;
+ };
+
+ pcie0_dart_2: iommu@583008000 {
+ compatible = "apple,t6000-dart";
+ reg = <0x5 0x83008000 0x0 0x4000>;
+ #iommu-cells = <1>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 0 1277 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&ps_apcie_gp_sys>;
+ };
+
+ pcie0_dart_3: iommu@584008000 {
+ compatible = "apple,t6000-dart";
+ reg = <0x5 0x84008000 0x0 0x4000>;
+ #iommu-cells = <1>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 0 1280 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&ps_apcie_gp_sys>;
+ };
+
+ pcie0: pcie@590000000 {
+ compatible = "apple,t6000-pcie", "apple,pcie";
+ device_type = "pci";
+
+ reg = <0x5 0x90000000 0x0 0x1000000>,
+ <0x5 0x80000000 0x0 0x100000>,
+ <0x5 0x81000000 0x0 0x4000>,
+ <0x5 0x82000000 0x0 0x4000>,
+ <0x5 0x83000000 0x0 0x4000>,
+ <0x5 0x84000000 0x0 0x4000>;
+ reg-names = "config", "rc", "port0", "port1", "port2", "port3";
+
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 0 1270 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 0 1273 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 0 1276 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 0 1279 IRQ_TYPE_LEVEL_HIGH>;
+
+ msi-controller;
+ msi-parent = <&pcie0>;
+ msi-ranges = <&aic AIC_IRQ 0 1581 IRQ_TYPE_EDGE_RISING 32>;
+
+
+ iommu-map = <0x100 &pcie0_dart_0 1 1>,
+ <0x200 &pcie0_dart_1 1 1>,
+ <0x300 &pcie0_dart_2 1 1>,
+ <0x400 &pcie0_dart_3 1 1>;
+ iommu-map-mask = <0xff00>;
+
+ bus-range = <0 4>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x43000000 0x5 0xa0000000 0x5 0xa0000000 0x0 0x20000000>,
+ <0x02000000 0x0 0xc0000000 0x5 0xc0000000 0x0 0x40000000>;
+
+ power-domains = <&ps_apcie_gp_sys>;
+ pinctrl-0 = <&pcie_pins>;
+ pinctrl-names = "default";
+
+ port00: pci@0,0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ reset-gpios = <&pinctrl_ap 4 GPIO_ACTIVE_LOW>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
+ <0 0 0 2 &port00 0 0 0 1>,
+ <0 0 0 3 &port00 0 0 0 2>,
+ <0 0 0 4 &port00 0 0 0 3>;
+ };
+
+ port01: pci@1,0 {
+ device_type = "pci";
+ reg = <0x800 0x0 0x0 0x0 0x0>;
+ reset-gpios = <&pinctrl_ap 5 GPIO_ACTIVE_LOW>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
+ <0 0 0 2 &port01 0 0 0 1>,
+ <0 0 0 3 &port01 0 0 0 2>,
+ <0 0 0 4 &port01 0 0 0 3>;
+ };
+
+ port02: pci@2,0 {
+ device_type = "pci";
+ reg = <0x1000 0x0 0x0 0x0 0x0>;
+ reset-gpios = <&pinctrl_ap 6 GPIO_ACTIVE_LOW>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
+ <0 0 0 2 &port02 0 0 0 1>,
+ <0 0 0 3 &port02 0 0 0 2>,
+ <0 0 0 4 &port02 0 0 0 3>;
+ };
+
+ port03: pci@3,0 {
+ device_type = "pci";
+ reg = <0x1800 0x0 0x0 0x0 0x0>;
+ reset-gpios = <&pinctrl_ap 7 GPIO_ACTIVE_LOW>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &port03 0 0 0 0>,
+ <0 0 0 2 &port03 0 0 0 1>,
+ <0 0 0 3 &port03 0 0 0 2>,
+ <0 0 0 4 &port03 0 0 0 3>;
+ };
+ };
diff --git a/arch/arm64/boot/dts/apple/t600x-dieX.dtsi b/arch/arm64/boot/dts/apple/t600x-dieX.dtsi
new file mode 100644
index 000000000000..a32ff0c9d7b0
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/t600x-dieX.dtsi
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Devices used on both dies on the Apple T6002 "M1 Ultra" and present on
+ * Apple T6000/T6001 "M1 Pro/Max".
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+ DIE_NODE(cpufreq_e): cpufreq@210e20000 {
+ compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
+ reg = <0x2 0x10e20000 0 0x1000>;
+ #performance-domain-cells = <0>;
+ };
+
+ DIE_NODE(cpufreq_p0): cpufreq@211e20000 {
+ compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
+ reg = <0x2 0x11e20000 0 0x1000>;
+ #performance-domain-cells = <0>;
+ };
+
+ DIE_NODE(cpufreq_p1): cpufreq@212e20000 {
+ compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
+ reg = <0x2 0x12e20000 0 0x1000>;
+ #performance-domain-cells = <0>;
+ };
+
+ DIE_NODE(pmgr): power-management@28e080000 {
+ compatible = "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x2 0x8e080000 0 0x4000>;
+ };
+
+ DIE_NODE(pmgr_east): power-management@28e580000 {
+ compatible = "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x2 0x8e580000 0 0xc000>;
+ };
+
+ DIE_NODE(pmgr_south): power-management@28e680000 {
+ compatible = "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x2 0x8e680000 0 0xc000>;
+ };
+
+ DIE_NODE(pinctrl_nub): pinctrl@2921f0000 {
+ compatible = "apple,t6000-pinctrl", "apple,pinctrl";
+ reg = <0x2 0x921f0000 0x0 0x4000>;
+ power-domains = <&DIE_NODE(ps_nub_gpio)>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&DIE_NODE(pinctrl_nub) 0 0 16>;
+ apple,npins = <16>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 623 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 624 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 625 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 626 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 627 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 628 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 629 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ DIE_NODE(pmgr_mini): power-management@292280000 {
+ compatible = "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x2 0x92280000 0 0x4000>;
+ };
+
+ DIE_NODE(pinctrl_aop): pinctrl@293820000 {
+ compatible = "apple,t6000-pinctrl", "apple,pinctrl";
+ reg = <0x2 0x93820000 0x0 0x4000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&DIE_NODE(pinctrl_aop) 0 0 63>;
+ apple,npins = <63>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 567 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 568 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 569 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 570 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 571 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 572 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 573 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ DIE_NODE(pinctrl_ap): pinctrl@39b028000 {
+ compatible = "apple,t6000-pinctrl", "apple,pinctrl";
+ reg = <0x3 0x9b028000 0x0 0x4000>;
+
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 427 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 428 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 429 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 430 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 431 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 432 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 433 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&clkref>;
+ power-domains = <&DIE_NODE(ps_gpio)>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&DIE_NODE(pinctrl_ap) 0 0 255>;
+ apple,npins = <255>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
diff --git a/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi b/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi
new file mode 100644
index 000000000000..b31f1a7a2b3f
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * GPIO pin mappings for Apple T600x SoCs.
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+&pinctrl_ap {
+ i2c0_pins: i2c0-pins {
+ pinmux = <APPLE_PINMUX(92, 1)>,
+ <APPLE_PINMUX(93, 1)>;
+ };
+
+ i2c1_pins: i2c1-pins {
+ pinmux = <APPLE_PINMUX(94, 1)>,
+ <APPLE_PINMUX(95, 1)>;
+ };
+
+ i2c2_pins: i2c2-pins {
+ pinmux = <APPLE_PINMUX(96, 1)>,
+ <APPLE_PINMUX(97, 1)>;
+ };
+
+ i2c3_pins: i2c3-pins {
+ pinmux = <APPLE_PINMUX(98, 1)>,
+ <APPLE_PINMUX(99, 1)>;
+ };
+
+ i2c4_pins: i2c4-pins {
+ pinmux = <APPLE_PINMUX(8, 1)>,
+ <APPLE_PINMUX(9, 1)>;
+ };
+
+ i2c5_pins: i2c5-pins {
+ pinmux = <APPLE_PINMUX(100, 1)>,
+ <APPLE_PINMUX(101, 1)>;
+ };
+
+ pcie_pins: pcie-pins {
+ pinmux = <APPLE_PINMUX(0, 1)>,
+ <APPLE_PINMUX(1, 1)>,
+ <APPLE_PINMUX(2, 1)>,
+ <APPLE_PINMUX(3, 1)>;
+ };
+};
diff --git a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi
new file mode 100644
index 000000000000..34906d522f0a
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * MacBook Pro (14/16-inch, 2021)
+ *
+ * This file contains the parts common to J314 and J316 devices with both t6000 and t6001.
+ *
+ * target-type: J314s / J314c / J316s / J316c
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+/ {
+ aliases {
+ serial0 = &serial0;
+ wifi0 = &wifi0;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ stdout-path = "serial0";
+
+ framebuffer0: framebuffer@0 {
+ compatible = "apple,simple-framebuffer", "simple-framebuffer";
+ reg = <0 0 0 0>; /* To be filled by loader */
+ /* Format properties will be added by loader */
+ status = "disabled";
+ };
+ };
+
+ memory@10000000000 {
+ device_type = "memory";
+ reg = <0x100 0 0x2 0>; /* To be filled by loader */
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
+
+/* USB Type C */
+&i2c0 {
+ hpm0: usb-pd@38 {
+ compatible = "apple,cd321x";
+ reg = <0x38>;
+ interrupt-parent = <&pinctrl_ap>;
+ interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "irq";
+ };
+
+ hpm1: usb-pd@3f {
+ compatible = "apple,cd321x";
+ reg = <0x3f>;
+ interrupt-parent = <&pinctrl_ap>;
+ interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "irq";
+ };
+
+ hpm2: usb-pd@3b {
+ compatible = "apple,cd321x";
+ reg = <0x3b>;
+ interrupt-parent = <&pinctrl_ap>;
+ interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "irq";
+ };
+
+ /* MagSafe port */
+ hpm5: usb-pd@3a {
+ compatible = "apple,cd321x";
+ reg = <0x3a>;
+ interrupt-parent = <&pinctrl_ap>;
+ interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "irq";
+ };
+};
+
+&nco_clkref {
+ clock-frequency = <1068000000>;
+};
+
+/* PCIe devices */
+&port00 {
+ /* WLAN */
+ bus-range = <1 1>;
+ wifi0: wifi@0,0 {
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+ /* To be filled by the loader */
+ local-mac-address = [00 10 18 00 00 10];
+ };
+};
+
+&port01 {
+ /* SD card reader */
+ bus-range = <2 2>;
+ sdhci0: mmc@0,0 {
+ compatible = "pci17a0,9755";
+ reg = <0x20000 0x0 0x0 0x0 0x0>;
+ cd-inverted;
+ wp-inverted;
+ };
+};
+
+&pcie0_dart_2 {
+ status = "disabled";
+};
+
+&pcie0_dart_3 {
+ status = "disabled";
+};
+
+/delete-node/ &port02;
+/delete-node/ &port03;
diff --git a/arch/arm64/boot/dts/apple/t600x-j375.dtsi b/arch/arm64/boot/dts/apple/t600x-j375.dtsi
new file mode 100644
index 000000000000..00d3a9447c89
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/t600x-j375.dtsi
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Mac Studio (2022)
+ *
+ * This file contains the parts common to J375 devices with both t6001 and t6002.
+ *
+ * target-type: J375c / J375d
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+/ {
+ aliases {
+ serial0 = &serial0;
+ wifi0 = &wifi0;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ stdout-path = "serial0";
+
+ framebuffer0: framebuffer@0 {
+ compatible = "apple,simple-framebuffer", "simple-framebuffer";
+ reg = <0 0 0 0>; /* To be filled by loader */
+ /* Format properties will be added by loader */
+ status = "disabled";
+ };
+ };
+
+ memory@10000000000 {
+ device_type = "memory";
+ reg = <0x100 0 0x2 0>; /* To be filled by loader */
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
+
+/* USB Type C */
+&i2c0 {
+ hpm0: usb-pd@38 {
+ compatible = "apple,cd321x";
+ reg = <0x38>;
+ interrupt-parent = <&pinctrl_ap>;
+ interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "irq";
+ };
+
+ hpm1: usb-pd@3f {
+ compatible = "apple,cd321x";
+ reg = <0x3f>;
+ interrupt-parent = <&pinctrl_ap>;
+ interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "irq";
+ };
+
+ hpm2: usb-pd@3b {
+ compatible = "apple,cd321x";
+ reg = <0x3b>;
+ interrupt-parent = <&pinctrl_ap>;
+ interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "irq";
+ };
+
+ hpm3: usb-pd@3c {
+ compatible = "apple,cd321x";
+ reg = <0x3c>;
+ interrupt-parent = <&pinctrl_ap>;
+ interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "irq";
+ };
+};
+
+&nco_clkref {
+ clock-frequency = <1068000000>;
+};
+
+/* PCIe devices */
+&port00 {
+ /* WLAN */
+ bus-range = <1 1>;
+ wifi0: wifi@0,0 {
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+ /* To be filled by the loader */
+ local-mac-address = [00 10 18 00 00 10];
+ };
+};
+
+&port01 {
+ /* SD card reader */
+ bus-range = <2 2>;
+ sdhci0: mmc@0,0 {
+ compatible = "pci17a0,9755";
+ reg = <0x20000 0x0 0x0 0x0 0x0>;
+ cd-inverted;
+ wp-inverted;
+ };
+};
+
+&port02 {
+ /* 10 Gbit Ethernet */
+ bus-range = <3 3>;
+ ethernet0: ethernet@0,0 {
+ reg = <0x30000 0x0 0x0 0x0 0x0>;
+ /* To be filled by the loader */
+ local-mac-address = [00 10 18 00 00 00];
+ };
+};
+
+&port03 {
+ /* USB xHCI */
+ bus-range = <4 4>;
+};
diff --git a/arch/arm64/boot/dts/apple/t600x-nvme.dtsi b/arch/arm64/boot/dts/apple/t600x-nvme.dtsi
new file mode 100644
index 000000000000..7dff738d317e
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/t600x-nvme.dtsi
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * NVMe related devices for Apple T600x SoCs.
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+ DIE_NODE(ans_mbox): mbox@38f408000 {
+ compatible = "apple,t6000-asc-mailbox", "apple,asc-mailbox-v4";
+ reg = <0x3 0x8f408000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ DIE_NO 1069 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 1070 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 1071 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ DIE_NO 1072 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "send-empty", "send-not-empty",
+ "recv-empty", "recv-not-empty";
+ power-domains = <&DIE_NODE(ps_ans2)>;
+ #mbox-cells = <0>;
+ };
+
+ DIE_NODE(sart): sart@393c50000 {
+ compatible = "apple,t6000-sart";
+ reg = <0x3 0x93c50000 0x0 0x10000>;
+ power-domains = <&DIE_NODE(ps_ans2)>;
+ };
+
+ DIE_NODE(nvme): nvme@393cc0000 {
+ compatible = "apple,t6000-nvme-ans2", "apple,nvme-ans2";
+ reg = <0x3 0x93cc0000 0x0 0x40000>, <0x3 0x8f400000 0x0 0x4000>;
+ reg-names = "nvme", "ans";
+ interrupt-parent = <&aic>;
+ /* The NVME interrupt is always routed to die */
+ interrupts = <AIC_IRQ 0 1613 IRQ_TYPE_LEVEL_HIGH>;
+ mboxes = <&DIE_NODE(ans_mbox)>;
+ apple,sart = <&DIE_NODE(sart)>;
+ power-domains = <&DIE_NODE(ps_ans2)>,
+ <&DIE_NODE(ps_apcie_st_sys)>,
+ <&DIE_NODE(ps_apcie_st1_sys)>;
+ power-domain-names = "ans", "apcie0", "apcie1";
+ resets = <&DIE_NODE(ps_ans2)>;
+ };
diff --git a/arch/arm64/boot/dts/apple/t600x-pmgr.dtsi b/arch/arm64/boot/dts/apple/t600x-pmgr.dtsi
new file mode 100644
index 000000000000..0bd44753b76a
--- /dev/null
+++ b/arch/arm64/boot/dts/apple/t600x-pmgr.dtsi
@@ -0,0 +1,2012 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * PMGR Power domains for the Apple T6001 "M1 Max" SoC
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+&DIE_NODE(pmgr) {
+ DIE_NODE(ps_pms_bridge): power-controller@100 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x100 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(pms_bridge);
+ apple,always-on; /* Core device */
+ };
+
+ DIE_NODE(ps_aic): power-controller@108 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x108 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(aic);
+ apple,always-on; /* Core device */
+ };
+
+ DIE_NODE(ps_dwi): power-controller@110 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x110 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dwi);
+ apple,always-on; /* Core device */
+ };
+
+ DIE_NODE(ps_pms): power-controller@118 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x118 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(pms);
+ apple,always-on; /* Core device */
+ };
+
+ DIE_NODE(ps_gpio): power-controller@120 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x120 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(gpio);
+ power-domains = <&DIE_NODE(ps_pms)>, <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_soc_dpe): power-controller@128 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x128 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(soc_dpe);
+ apple,always-on; /* Core device */
+ };
+
+ DIE_NODE(ps_pmgr_soc_ocla): power-controller@130 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x130 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(pmgr_soc_ocla);
+ power-domains = <&DIE_NODE(ps_pms)>;
+ };
+
+ DIE_NODE(ps_pcie0_ref): power-controller@138 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x138 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(pcie0_ref);
+ };
+
+ DIE_NODE(ps_pcie1_ref): power-controller@140 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x140 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(pcie1_ref);
+ };
+
+ DIE_NODE(ps_apcie_st): power-controller@148 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x148 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(apcie_st);
+ power-domains = <&DIE_NODE(ps_pcie1_ref)>;
+ };
+
+ DIE_NODE(ps_apcie_gp): power-controller@150 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x150 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(apcie_gp);
+ power-domains = <&DIE_NODE(ps_pcie0_ref)>;
+ };
+
+ DIE_NODE(ps_devc0_ivdmc): power-controller@180 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x180 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(devc0_ivdmc);
+ };
+
+ DIE_NODE(ps_amcc0): power-controller@188 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x188 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(amcc0);
+ apple,always-on; /* Memory controller */
+ };
+
+ DIE_NODE(ps_amcc2): power-controller@190 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x190 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(amcc2);
+ apple,always-on; /* Memory controller */
+ };
+
+ DIE_NODE(ps_dcs_00): power-controller@198 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x198 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_00);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_01): power-controller@1a0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1a0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_01);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_02): power-controller@1a8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1a8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_02);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_03): power-controller@1b0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1b0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_03);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_08): power-controller@1b8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1b8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_08);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_09): power-controller@1c0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1c0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_09);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_10): power-controller@1c8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1c8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_10);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_11): power-controller@1d0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1d0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_11);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_afi): power-controller@1d8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1d8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afi);
+ apple,always-on; /* Apple Fabric, CPU interface is here */
+ };
+
+ DIE_NODE(ps_afc): power-controller@1e0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1e0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afc);
+ apple,always-on; /* Apple Fabric, CPU interface is here */
+ };
+
+ DIE_NODE(ps_afr): power-controller@1e8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1e8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afr);
+ /* Apple Fabric, media stuff: this can power down */
+ };
+
+ DIE_NODE(ps_afnc1_ioa): power-controller@1f0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1f0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc1_ioa);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afi)>;
+ };
+
+ DIE_NODE(ps_afnc0_ioa): power-controller@1f8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1f8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc0_ioa);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afi)>;
+ };
+
+ DIE_NODE(ps_afnc1_ls): power-controller@200 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x200 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc1_ls);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afnc1_ioa)>;
+ };
+
+ DIE_NODE(ps_afnc0_ls): power-controller@208 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x208 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc0_ls);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afnc0_ioa)>;
+ };
+
+ DIE_NODE(ps_afnc1_lw0): power-controller@210 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x210 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc1_lw0);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afnc1_ls)>;
+ };
+
+ DIE_NODE(ps_afnc1_lw1): power-controller@218 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x218 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc1_lw1);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afnc1_ls)>;
+ };
+
+ DIE_NODE(ps_afnc1_lw2): power-controller@220 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x220 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc1_lw2);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afnc1_ls)>;
+ };
+
+ DIE_NODE(ps_afnc0_lw0): power-controller@228 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x228 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc0_lw0);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afnc0_ls)>;
+ };
+
+ DIE_NODE(ps_scodec): power-controller@230 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x230 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(scodec);
+ power-domains = <&DIE_NODE(ps_afnc1_lw0)>;
+ };
+
+ DIE_NODE(ps_atc0_common): power-controller@238 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x238 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc0_common);
+ power-domains = <&DIE_NODE(ps_afnc1_lw1)>;
+ };
+
+ DIE_NODE(ps_atc1_common): power-controller@240 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x240 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc1_common);
+ power-domains = <&DIE_NODE(ps_afnc1_lw1)>;
+ };
+
+ DIE_NODE(ps_c0_usb31drd): power-controller@248 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x248 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(c0_usb31drd);
+ power-domains = <&DIE_NODE(ps_usb)>;
+ };
+
+ DIE_NODE(ps_c1_usb31drd): power-controller@250 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x250 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(c1_usb31drd);
+ power-domains = <&DIE_NODE(ps_usb)>;
+ };
+
+ DIE_NODE(ps_dispext0_fe): power-controller@258 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x258 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dispext0_fe);
+ power-domains = <&DIE_NODE(ps_afi)>;
+ };
+
+ DIE_NODE(ps_dispext1_fe): power-controller@260 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x260 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dispext1_fe);
+ power-domains = <&DIE_NODE(ps_afi)>;
+ };
+
+ DIE_NODE(ps_ane_sys): power-controller@268 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x268 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(ane_sys);
+ power-domains = <&DIE_NODE(ps_afr)>;
+ };
+
+ DIE_NODE(ps_avd_sys): power-controller@270 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x270 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(avd_sys);
+ power-domains = <&DIE_NODE(ps_afr)>;
+ };
+
+ DIE_NODE(ps_dispext0_cpu0): power-controller@280 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x280 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dispext0_cpu0);
+ power-domains = <&DIE_NODE(ps_dispext0_fe)>;
+ };
+
+ DIE_NODE(ps_dispext1_cpu0): power-controller@2a8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x2a8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dispext1_cpu0);
+ power-domains = <&DIE_NODE(ps_dispext1_fe)>;
+ };
+
+ DIE_NODE(ps_ane_sys_cpu): power-controller@2c8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x2c8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(ane_sys_cpu);
+ power-domains = <&DIE_NODE(ps_ane_sys)>;
+ };
+
+#if DIE_NO == 0
+ /* PMP is only present on die 0 of the M1 Ultra */
+ DIE_NODE(ps_pmp): power-controller@2d8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x2d8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(pmp);
+ };
+#endif
+
+ DIE_NODE(ps_pms_sram): power-controller@2e0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x2e0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(pms_sram);
+ };
+
+ DIE_NODE(ps_apcie_st_sys): power-controller@2e8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x2e8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(apcie_st_sys);
+ power-domains = <&DIE_NODE(ps_apcie_st)>, <&DIE_NODE(ps_ans2)>;
+ };
+
+ DIE_NODE(ps_apcie_st1_sys): power-controller@2f0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x2f0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(apcie_st1_sys);
+ power-domains = <&DIE_NODE(ps_apcie_st)>, <&DIE_NODE(ps_ans2)>;
+ };
+
+ DIE_NODE(ps_atc2_common): power-controller@2f8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x2f8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc2_common);
+ power-domains = <&DIE_NODE(ps_afnc1_lw1)>;
+ };
+
+ DIE_NODE(ps_atc3_common): power-controller@300 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x300 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc3_common);
+ power-domains = <&DIE_NODE(ps_afnc1_lw1)>;
+ };
+
+ DIE_NODE(ps_usb): power-controller@318 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x318 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(usb);
+ power-domains = <&DIE_NODE(ps_afnc1_lw2)>;
+ };
+
+ DIE_NODE(ps_apcie_gp_sys): power-controller@320 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x320 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(apcie_gp_sys);
+ power-domains = <&DIE_NODE(ps_afnc1_lw2)>, <&DIE_NODE(ps_apcie_gp)>;
+ apple,always-on; /* Breaks things if shut down */
+ };
+
+ DIE_NODE(ps_atc0_cio): power-controller@328 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x328 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc0_cio);
+ power-domains = <&DIE_NODE(ps_atc0_common)>;
+ };
+
+ DIE_NODE(ps_atc0_pcie): power-controller@330 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x330 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc0_pcie);
+ power-domains = <&DIE_NODE(ps_atc0_common)>;
+ };
+
+ DIE_NODE(ps_atc1_cio): power-controller@338 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x338 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc1_cio);
+ power-domains = <&DIE_NODE(ps_atc1_common)>;
+ };
+
+ DIE_NODE(ps_atc1_pcie): power-controller@340 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x340 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc1_pcie);
+ power-domains = <&DIE_NODE(ps_atc1_common)>;
+ };
+
+ DIE_NODE(ps_atc2_cio): power-controller@348 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x348 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc2_cio);
+ power-domains = <&DIE_NODE(ps_atc2_common)>;
+ };
+
+ DIE_NODE(ps_atc2_pcie): power-controller@350 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x350 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc2_pcie);
+ power-domains = <&DIE_NODE(ps_atc2_common)>;
+ };
+
+ DIE_NODE(ps_atc3_cio): power-controller@358 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x358 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc3_cio);
+ power-domains = <&DIE_NODE(ps_atc3_common)>;
+ };
+
+ DIE_NODE(ps_atc3_pcie): power-controller@360 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x360 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc3_pcie);
+ power-domains = <&DIE_NODE(ps_atc3_common)>;
+ };
+
+ DIE_NODE(ps_c0_usbctl): power-controller@368 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x368 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(c0_usbctl);
+ power-domains = <&DIE_NODE(ps_usb)>;
+ };
+
+ DIE_NODE(ps_c1_usbctl): power-controller@370 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x370 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(c1_usbctl);
+ power-domains = <&DIE_NODE(ps_usb)>;
+ };
+
+ DIE_NODE(ps_atc0_cio_pcie): power-controller@378 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x378 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc0_cio_pcie);
+ power-domains = <&DIE_NODE(ps_atc0_cio)>;
+ };
+
+ DIE_NODE(ps_atc0_cio_usb): power-controller@380 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x380 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc0_cio_usb);
+ power-domains = <&DIE_NODE(ps_atc0_cio)>;
+ };
+
+ DIE_NODE(ps_atc1_cio_pcie): power-controller@388 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x388 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc1_cio_pcie);
+ power-domains = <&DIE_NODE(ps_atc1_cio)>;
+ };
+
+ DIE_NODE(ps_atc1_cio_usb): power-controller@390 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x390 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc1_cio_usb);
+ power-domains = <&DIE_NODE(ps_atc1_cio)>;
+ };
+
+ DIE_NODE(ps_atc2_cio_pcie): power-controller@398 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x398 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc2_cio_pcie);
+ power-domains = <&DIE_NODE(ps_atc2_cio)>;
+ };
+
+ DIE_NODE(ps_atc2_cio_usb): power-controller@3a0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x3a0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc2_cio_usb);
+ power-domains = <&DIE_NODE(ps_atc2_cio)>;
+ };
+
+ DIE_NODE(ps_atc3_cio_pcie): power-controller@3a8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x3a8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc3_cio_pcie);
+ power-domains = <&DIE_NODE(ps_atc3_cio)>;
+ };
+
+ DIE_NODE(ps_atc3_cio_usb): power-controller@3b0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x3b0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc3_cio_usb);
+ power-domains = <&DIE_NODE(ps_atc3_cio)>;
+ };
+
+ DIE_NODE(ps_trace_fab): power-controller@3b8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x3b8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(trace_fab);
+ };
+};
+
+&DIE_NODE(pmgr_east) {
+ DIE_NODE(ps_clvr_spmi0): power-controller@100 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x100 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(clvr_spmi0);
+ apple,always-on; /* PCPU voltage regulator interface (used by SMC) */
+ };
+
+ DIE_NODE(ps_clvr_spmi1): power-controller@108 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x108 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(clvr_spmi1);
+ apple,always-on; /* GPU voltage regulator interface (used by SMC) */
+ };
+
+ DIE_NODE(ps_clvr_spmi2): power-controller@110 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x110 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(clvr_spmi2);
+ apple,always-on; /* ANE, fabric, AFR voltage regulator interface (used by SMC) */
+ };
+
+ DIE_NODE(ps_clvr_spmi3): power-controller@118 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x118 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(clvr_spmi3);
+ apple,always-on; /* Additional voltage regulator, probably used on T6001 (SMC) */
+ };
+
+ DIE_NODE(ps_clvr_spmi4): power-controller@120 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x120 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(clvr_spmi4);
+ apple,always-on; /* Additional voltage regulator, probably used on T6001 (SMC) */
+ };
+
+ DIE_NODE(ps_ispsens0): power-controller@128 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x128 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(ispsens0);
+ };
+
+ DIE_NODE(ps_ispsens1): power-controller@130 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x130 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(ispsens1);
+ };
+
+ DIE_NODE(ps_ispsens2): power-controller@138 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x138 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(ispsens2);
+ };
+
+ DIE_NODE(ps_ispsens3): power-controller@140 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x140 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(ispsens3);
+ };
+
+ DIE_NODE(ps_afnc2_ioa): power-controller@148 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x148 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc2_ioa);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afi)>;
+ };
+
+ DIE_NODE(ps_afnc2_ls): power-controller@150 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x150 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc2_ls);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afnc2_ioa)>;
+ };
+
+ DIE_NODE(ps_afnc2_lw0): power-controller@158 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x158 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc2_lw0);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afnc2_ls)>;
+ };
+
+ DIE_NODE(ps_afnc2_lw1): power-controller@160 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x160 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc2_lw1);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afnc2_ls)>;
+ };
+
+ DIE_NODE(ps_afnc3_ioa): power-controller@168 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x168 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc3_ioa);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afi)>;
+ };
+
+ DIE_NODE(ps_afnc3_ls): power-controller@170 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x170 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc3_ls);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afnc3_ioa)>;
+ };
+
+ DIE_NODE(ps_afnc3_lw0): power-controller@178 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x178 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc3_lw0);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afnc3_ls)>;
+ };
+
+ DIE_NODE(ps_sio): power-controller@180 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x180 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(sio);
+ power-domains = <&DIE_NODE(ps_afnc2_lw1)>;
+ };
+
+ DIE_NODE(ps_sio_cpu): power-controller@188 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x188 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(sio_cpu);
+ power-domains = <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_fpwm0): power-controller@190 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x190 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(fpwm0);
+ power-domains = <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_fpwm1): power-controller@198 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x198 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(fpwm1);
+ power-domains = <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_fpwm2): power-controller@1a0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1a0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(fpwm2);
+ power-domains = <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_i2c0): power-controller@1a8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1a8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(i2c0);
+ power-domains = <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_i2c1): power-controller@1b0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1b0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(i2c1);
+ power-domains = <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_i2c2): power-controller@1b8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1b8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(i2c2);
+ power-domains = <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_i2c3): power-controller@1c0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1c0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(i2c3);
+ power-domains = <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_i2c4): power-controller@1c8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1c8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(i2c4);
+ power-domains = <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_i2c5): power-controller@1d0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1d0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(i2c5);
+ power-domains = <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_i2c6): power-controller@1d8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1d8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(i2c6);
+ power-domains = <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_i2c7): power-controller@1e0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1e0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(i2c7);
+ power-domains = <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_spi_p): power-controller@1e8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1e8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(spi_p);
+ power-domains = <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_spi0): power-controller@1f0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1f0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(spi0);
+ power-domains = <&DIE_NODE(ps_spi_p)>;
+ };
+
+ DIE_NODE(ps_spi1): power-controller@1f8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1f8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(spi1);
+ power-domains = <&DIE_NODE(ps_spi_p)>;
+ };
+
+ DIE_NODE(ps_spi2): power-controller@200 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x200 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(spi2);
+ power-domains = <&DIE_NODE(ps_spi_p)>;
+ };
+
+ DIE_NODE(ps_spi3): power-controller@208 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x208 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(spi3);
+ power-domains = <&DIE_NODE(ps_spi_p)>;
+ };
+
+ DIE_NODE(ps_spi4): power-controller@210 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x210 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(spi4);
+ power-domains = <&DIE_NODE(ps_spi_p)>;
+ };
+
+ DIE_NODE(ps_sio_spmi0): power-controller@218 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x218 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(sio_spmi0);
+ power-domains = <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_sio_spmi1): power-controller@220 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x220 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(sio_spmi1);
+ power-domains = <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_sio_spmi2): power-controller@228 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x228 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(sio_spmi2);
+ power-domains = <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_uart_p): power-controller@230 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x230 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(uart_p);
+ power-domains = <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_uart_n): power-controller@238 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x238 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(uart_n);
+ power-domains = <&DIE_NODE(ps_uart_p)>;
+ };
+
+ DIE_NODE(ps_uart0): power-controller@240 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x240 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(uart0);
+ power-domains = <&DIE_NODE(ps_uart_p)>;
+ };
+
+ DIE_NODE(ps_uart1): power-controller@248 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x248 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(uart1);
+ power-domains = <&DIE_NODE(ps_uart_p)>;
+ };
+
+ DIE_NODE(ps_uart2): power-controller@250 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x250 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(uart2);
+ power-domains = <&DIE_NODE(ps_uart_p)>;
+ };
+
+ DIE_NODE(ps_uart3): power-controller@258 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x258 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(uart3);
+ power-domains = <&DIE_NODE(ps_uart_p)>;
+ };
+
+ DIE_NODE(ps_uart4): power-controller@260 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x260 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(uart4);
+ power-domains = <&DIE_NODE(ps_uart_p)>;
+ };
+
+ DIE_NODE(ps_uart6): power-controller@268 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x268 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(uart6);
+ power-domains = <&DIE_NODE(ps_uart_p)>;
+ };
+
+ DIE_NODE(ps_uart7): power-controller@270 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x270 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(uart7);
+ power-domains = <&DIE_NODE(ps_uart_p)>;
+ };
+
+ DIE_NODE(ps_audio_p): power-controller@278 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x278 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(audio_p);
+ power-domains = <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_sio_adma): power-controller@280 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x280 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(sio_adma);
+ power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_mca0): power-controller@288 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x288 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(mca0);
+ power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>;
+ };
+
+ DIE_NODE(ps_mca1): power-controller@290 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x290 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(mca1);
+ power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>;
+ };
+
+ DIE_NODE(ps_mca2): power-controller@298 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x298 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(mca2);
+ power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>;
+ };
+
+ DIE_NODE(ps_mca3): power-controller@2a0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x2a0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(mca3);
+ power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>;
+ };
+
+ DIE_NODE(ps_dpa0): power-controller@2a8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x2a8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dpa0);
+ power-domains = <&DIE_NODE(ps_audio_p)>;
+ };
+
+ DIE_NODE(ps_dpa1): power-controller@2b0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x2b0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dpa1);
+ power-domains = <&DIE_NODE(ps_audio_p)>;
+ };
+
+ DIE_NODE(ps_dpa2): power-controller@2b8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x2b8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dpa2);
+ power-domains = <&DIE_NODE(ps_audio_p)>;
+ };
+
+ DIE_NODE(ps_dpa3): power-controller@2c0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x2c0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dpa3);
+ power-domains = <&DIE_NODE(ps_audio_p)>;
+ };
+
+ DIE_NODE(ps_dpa4): power-controller@2c8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x2c8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dpa4);
+ power-domains = <&DIE_NODE(ps_audio_p)>;
+ };
+
+ DIE_NODE(ps_aes): power-controller@2d0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x2d0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(aes);
+ power-domains = <&DIE_NODE(ps_sio)>;
+ };
+
+ DIE_NODE(ps_amcc1): power-controller@2d8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x2d8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(amcc1);
+ apple,always-on; /* Memory controller */
+ };
+
+ DIE_NODE(ps_amcc3): power-controller@2e0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x2e0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(amcc3);
+ apple,always-on; /* Memory controller */
+ };
+
+ DIE_NODE(ps_dcs_04): power-controller@2e8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x2e8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_04);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_05): power-controller@2f0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x2f0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_05);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_06): power-controller@2f8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x2f8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_06);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_07): power-controller@300 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x300 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_07);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_12): power-controller@308 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x308 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_12);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_13): power-controller@310 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x310 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_13);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_14): power-controller@318 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x318 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_14);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_15): power-controller@320 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x320 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_15);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_disp0_fe): power-controller@328 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x328 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(disp0_fe);
+ power-domains = <&DIE_NODE(ps_afnc2_lw0)>;
+ apple,always-on; /* TODO: figure out if we can enable PM here */
+ };
+
+ DIE_NODE(ps_disp0_cpu0): power-controller@350 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x350 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(disp0_cpu0);
+ power-domains = <&DIE_NODE(ps_disp0_fe)>;
+ apple,always-on; /* TODO: figure out if we can enable PM here */
+ apple,min-state = <4>;
+ };
+
+ DIE_NODE(ps_dispdfr_fe): power-controller@378 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x378 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dispdfr_fe);
+ power-domains = <&DIE_NODE(ps_afnc2_lw1)>;
+ };
+
+ DIE_NODE(ps_dispdfr_be): power-controller@380 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x380 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dispdfr_be);
+ power-domains = <&DIE_NODE(ps_dispdfr_fe)>;
+ };
+
+ DIE_NODE(ps_mipi_dsi): power-controller@388 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x388 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(mipi_dsi);
+ power-domains = <&DIE_NODE(ps_dispdfr_be)>;
+ };
+
+ DIE_NODE(ps_jpg): power-controller@390 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x390 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(jpg);
+ power-domains = <&DIE_NODE(ps_afr)>;
+ };
+
+ DIE_NODE(ps_msr0): power-controller@398 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x398 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(msr0);
+ power-domains = <&DIE_NODE(ps_afr)>;
+ };
+
+ DIE_NODE(ps_msr0_ase_core): power-controller@3a0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x3a0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(msr0_ase_core);
+ power-domains = <&DIE_NODE(ps_msr0)>;
+ };
+
+ DIE_NODE(ps_isp_sys): power-controller@3a8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x3a8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(isp_sys);
+ power-domains = <&DIE_NODE(ps_afnc2_lw1)>;
+ };
+
+ DIE_NODE(ps_venc_sys): power-controller@3b0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x3b0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(venc_sys);
+ power-domains = <&DIE_NODE(ps_afr)>;
+ };
+
+ DIE_NODE(ps_ans2): power-controller@3b8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x3b8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(ans2);
+ /*
+ * The ADT makes ps_apcie_st[1]_sys depend on ps_ans2 instead,
+ * but we'd rather have a single power domain for the downstream
+ * device to depend on, so use this node as the child.
+ * This makes more sense anyway (since ANS2 uses APCIE_ST).
+ */
+ power-domains = <&DIE_NODE(ps_afnc2_lw0)>;
+ };
+
+ DIE_NODE(ps_gfx): power-controller@3c0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x3c0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(gfx);
+ power-domains = <&DIE_NODE(ps_afr)>;
+ };
+
+ DIE_NODE(ps_sep): power-controller@c00 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0xc00 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(sep);
+ apple,always-on; /* Locked on */
+ };
+
+ DIE_NODE(ps_venc_dma): power-controller@8000 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x8000 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(venc_dma);
+ power-domains = <&DIE_NODE(ps_venc_sys)>;
+ };
+
+ DIE_NODE(ps_venc_pipe4): power-controller@8008 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x8008 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(venc_pipe4);
+ power-domains = <&DIE_NODE(ps_venc_dma)>;
+ };
+
+ DIE_NODE(ps_venc_pipe5): power-controller@8010 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x8010 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(venc_pipe5);
+ power-domains = <&DIE_NODE(ps_venc_dma)>;
+ };
+
+ DIE_NODE(ps_venc_me0): power-controller@8018 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x8018 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(venc_me0);
+ power-domains = <&DIE_NODE(ps_venc_pipe5)>, <&DIE_NODE(ps_venc_pipe4)>;
+ };
+
+ DIE_NODE(ps_venc_me1): power-controller@8020 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x8020 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(venc_me1);
+ power-domains = <&DIE_NODE(ps_venc_me0)>;
+ };
+};
+
+&DIE_NODE(pmgr_south) {
+ DIE_NODE(ps_amcc4): power-controller@100 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x100 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(amcc4);
+ apple,always-on; /* Memory controller */
+ };
+
+ DIE_NODE(ps_amcc5): power-controller@108 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x108 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(amcc5);
+ apple,always-on; /* Memory controller */
+ };
+
+ DIE_NODE(ps_amcc6): power-controller@110 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x110 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(amcc6);
+ apple,always-on; /* Memory controller */
+ };
+
+ DIE_NODE(ps_amcc7): power-controller@118 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x118 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(amcc7);
+ apple,always-on; /* Memory controller */
+ };
+
+ DIE_NODE(ps_dcs_16): power-controller@120 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x120 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_16);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_17): power-controller@128 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x128 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_17);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_18): power-controller@130 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x130 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_18);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_19): power-controller@138 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x138 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_19);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_20): power-controller@140 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x140 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_20);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_21): power-controller@148 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x148 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_21);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_22): power-controller@150 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x150 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_22);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_23): power-controller@158 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x158 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_23);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_24): power-controller@160 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x160 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_24);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_25): power-controller@168 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x168 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_25);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_26): power-controller@170 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x170 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_26);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_27): power-controller@178 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x178 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_27);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_28): power-controller@180 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x180 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_28);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_29): power-controller@188 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x188 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_29);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_30): power-controller@190 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x190 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_30);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_dcs_31): power-controller@198 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x198 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dcs_31);
+ apple,always-on; /* LPDDR5 interface */
+ };
+
+ DIE_NODE(ps_afnc4_ioa): power-controller@1a0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1a0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc4_ioa);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afi)>;
+ };
+
+ DIE_NODE(ps_afnc4_ls): power-controller@1a8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1a8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc4_ls);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afnc4_ioa)>;
+ };
+
+ DIE_NODE(ps_afnc4_lw0): power-controller@1b0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1b0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc4_lw0);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afnc4_ls)>;
+ };
+
+ DIE_NODE(ps_afnc5_ioa): power-controller@1b8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1b8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc5_ioa);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afi)>;
+ };
+
+ DIE_NODE(ps_afnc5_ls): power-controller@1c0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1c0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc5_ls);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afnc5_ioa)>;
+ };
+
+ DIE_NODE(ps_afnc5_lw0): power-controller@1c8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1c8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(afnc5_lw0);
+ apple,always-on; /* Apple Fabric */
+ power-domains = <&DIE_NODE(ps_afnc5_ls)>;
+ };
+
+ DIE_NODE(ps_dispext2_fe): power-controller@1d0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1d0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dispext2_fe);
+ power-domains = <&DIE_NODE(ps_afnc4_lw0)>;
+ };
+
+ DIE_NODE(ps_dispext2_cpu0): power-controller@1e8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x1e8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dispext2_cpu0);
+ power-domains = <&DIE_NODE(ps_dispext2_fe)>;
+ };
+
+ DIE_NODE(ps_dispext3_fe): power-controller@210 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x210 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dispext3_fe);
+ power-domains = <&DIE_NODE(ps_afnc4_lw0)>;
+ };
+
+ DIE_NODE(ps_dispext3_cpu0): power-controller@228 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x228 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(dispext3_cpu0);
+ power-domains = <&DIE_NODE(ps_dispext3_fe)>;
+ };
+
+ DIE_NODE(ps_msr1): power-controller@250 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x250 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(msr1);
+ power-domains = <&DIE_NODE(ps_afnc5_lw0)>, <&DIE_NODE(ps_afr)>;
+ };
+
+ DIE_NODE(ps_msr1_ase_core): power-controller@258 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x258 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(msr1_ase_core);
+ power-domains = <&DIE_NODE(ps_msr1)>;
+ };
+
+ DIE_NODE(ps_venc1_sys): power-controller@260 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x260 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(venc1_sys);
+ power-domains = <&DIE_NODE(ps_afnc5_lw0)>, <&DIE_NODE(ps_afr)>;
+ };
+
+ /* Seems to be disabled on shipping hardware */
+#if 0
+ DIE_NODE(ps_ane1_sys): power-controller@268 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x268 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(ane1_sys);
+ power-domains = <&DIE_NODE(ps_afnc5_lw0)>;
+ };
+
+ DIE_NODE(ps_ane1_sys_cpu): power-controller@270 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x270 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(ane1_sys_cpu);
+ power-domains = <&DIE_NODE(ps_ane1_sys)>;
+ };
+#endif
+
+ DIE_NODE(ps_venc1_dma): power-controller@8000 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x8000 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(venc1_dma);
+ power-domains = <&DIE_NODE(ps_venc1_sys)>;
+ };
+
+ DIE_NODE(ps_venc1_pipe4): power-controller@8008 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x8008 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(venc1_pipe4);
+ power-domains = <&DIE_NODE(ps_venc1_dma)>;
+ };
+
+ DIE_NODE(ps_venc1_pipe5): power-controller@8010 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x8010 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(venc1_pipe5);
+ power-domains = <&DIE_NODE(ps_venc1_dma)>;
+ };
+
+ DIE_NODE(ps_venc1_me0): power-controller@8018 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x8018 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(venc1_me0);
+ power-domains = <&DIE_NODE(ps_venc1_pipe4)>, <&DIE_NODE(ps_venc1_pipe5)>;
+ };
+
+ DIE_NODE(ps_venc1_me1): power-controller@8020 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x8020 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(venc1_me1);
+ power-domains = <&DIE_NODE(ps_venc1_me0)>;
+ };
+
+ DIE_NODE(ps_prores): power-controller@c000 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0xc000 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(prores);
+ power-domains = <&DIE_NODE(ps_afnc4_lw0)>;
+ };
+};
+
+&DIE_NODE(pmgr_mini) {
+ DIE_NODE(ps_debug): power-controller@58 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x58 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(debug);
+ apple,always-on; /* Core AON device */
+ };
+
+ DIE_NODE(ps_nub_spmi0): power-controller@60 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x60 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(nub_spmi0);
+ apple,always-on; /* Core AON device */
+ };
+
+ DIE_NODE(ps_nub_spmi1): power-controller@68 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x68 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(nub_spmi1);
+ apple,always-on; /* Core AON device */
+ };
+
+ DIE_NODE(ps_nub_aon): power-controller@70 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x70 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(nub_aon);
+ apple,always-on; /* Core AON device */
+ };
+
+ DIE_NODE(ps_msg): power-controller@78 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x78 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(msg);
+ };
+
+ DIE_NODE(ps_nub_gpio): power-controller@80 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x80 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(nub_gpio);
+ apple,always-on; /* Core AON device */
+ };
+
+ DIE_NODE(ps_atc0_usb_aon): power-controller@88 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x88 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc0_usb_aon);
+ apple,always-on; /* Needs to stay on for dwc3 to work */
+ };
+
+ DIE_NODE(ps_atc1_usb_aon): power-controller@90 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x90 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc1_usb_aon);
+ apple,always-on; /* Needs to stay on for dwc3 to work */
+ };
+
+ DIE_NODE(ps_atc2_usb_aon): power-controller@98 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0x98 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc2_usb_aon);
+ apple,always-on; /* Needs to stay on for dwc3 to work */
+ };
+
+ DIE_NODE(ps_atc3_usb_aon): power-controller@a0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0xa0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc3_usb_aon);
+ apple,always-on; /* Needs to stay on for dwc3 to work */
+ };
+
+ DIE_NODE(ps_gp_usb_aon): power-controller@a8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0xa8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(gp_usb_aon);
+ };
+
+ DIE_NODE(ps_nub_fabric): power-controller@b0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0xb0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(nub_fabric);
+ apple,always-on; /* Core AON device */
+ };
+
+ DIE_NODE(ps_nub_sram): power-controller@b8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0xb8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(nub_sram);
+ apple,always-on; /* Core AON device */
+ };
+
+ DIE_NODE(ps_debug_usb): power-controller@c0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0xc0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(debug_usb);
+ apple,always-on; /* Core AON device */
+ power-domains = <&DIE_NODE(ps_debug)>;
+ };
+
+ DIE_NODE(ps_debug_auth): power-controller@c8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0xc8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(debug_auth);
+ apple,always-on; /* Core AON device */
+ power-domains = <&DIE_NODE(ps_debug)>;
+ };
+
+ DIE_NODE(ps_atc0_usb): power-controller@d0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0xd0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc0_usb);
+ power-domains = <&DIE_NODE(ps_atc0_usb_aon)>, <&DIE_NODE(ps_atc0_common)>;
+ };
+
+ DIE_NODE(ps_atc1_usb): power-controller@d8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0xd8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc1_usb);
+ power-domains = <&DIE_NODE(ps_atc1_usb_aon)>, <&DIE_NODE(ps_atc1_common)>;
+ };
+
+ DIE_NODE(ps_atc2_usb): power-controller@e0 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0xe0 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc2_usb);
+ power-domains = <&DIE_NODE(ps_atc2_usb_aon)>, <&DIE_NODE(ps_atc2_common)>;
+ };
+
+ DIE_NODE(ps_atc3_usb): power-controller@e8 {
+ compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
+ reg = <0xe8 4>;
+ #power-domain-cells = <0>;
+ #reset-cells = <0>;
+ label = DIE_LABEL(atc3_usb);
+ power-domains = <&DIE_NODE(ps_atc3_usb_aon)>, <&DIE_NODE(ps_atc3_common)>;
+ };
+};
diff --git a/arch/arm64/boot/dts/apple/t8103-j456.dts b/arch/arm64/boot/dts/apple/t8103-j456.dts
index 8c6bf9592510..83bb4dc32af9 100644
--- a/arch/arm64/boot/dts/apple/t8103-j456.dts
+++ b/arch/arm64/boot/dts/apple/t8103-j456.dts
@@ -14,7 +14,7 @@
/ {
compatible = "apple,j456", "apple,t8103", "apple,arm-platform";
- model = "Apple iMac (24-inch, 4x USB-C, M1, 2020)";
+ model = "Apple iMac (24-inch, 4x USB-C, M1, 2021)";
aliases {
ethernet0 = &ethernet0;
diff --git a/arch/arm64/boot/dts/apple/t8103-j457.dts b/arch/arm64/boot/dts/apple/t8103-j457.dts
index fe7c0aaf7d62..67e433d5f8ba 100644
--- a/arch/arm64/boot/dts/apple/t8103-j457.dts
+++ b/arch/arm64/boot/dts/apple/t8103-j457.dts
@@ -14,7 +14,7 @@
/ {
compatible = "apple,j457", "apple,t8103", "apple,arm-platform";
- model = "Apple iMac (24-inch, 2x USB-C, M1, 2020)";
+ model = "Apple iMac (24-inch, 2x USB-C, M1, 2021)";
aliases {
ethernet0 = &ethernet0;
diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi
index 3d15b8e2a6c1..9706d26f9c64 100644
--- a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi
+++ b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi
@@ -78,3 +78,7 @@
apple,antenna-sku = "XX";
};
};
+
+&nco_clkref {
+ clock-frequency = <900000000>;
+};
diff --git a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi
index a6dbb1f485d8..9645861a858c 100644
--- a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi
+++ b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi
@@ -339,7 +339,7 @@
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "sio_adma";
- power-domains = <&ps_sio>, <&ps_pms>;
+ power-domains = <&ps_sio>, <&ps_pms>, <&ps_audio_p>;
};
ps_aes: power-controller@238 {
diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi
index 51a63b29d404..9859219699f4 100644
--- a/arch/arm64/boot/dts/apple/t8103.dtsi
+++ b/arch/arm64/boot/dts/apple/t8103.dtsi
@@ -22,69 +22,279 @@
#address-cells = <2>;
#size-cells = <0>;
- cpu0: cpu@0 {
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu_e0>;
+ };
+ core1 {
+ cpu = <&cpu_e1>;
+ };
+ core2 {
+ cpu = <&cpu_e2>;
+ };
+ core3 {
+ cpu = <&cpu_e3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu_p0>;
+ };
+ core1 {
+ cpu = <&cpu_p1>;
+ };
+ core2 {
+ cpu = <&cpu_p2>;
+ };
+ core3 {
+ cpu = <&cpu_p3>;
+ };
+ };
+ };
+
+ cpu_e0: cpu@0 {
compatible = "apple,icestorm";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&ecluster_opp>;
+ capacity-dmips-mhz = <714>;
+ performance-domains = <&cpufreq_e>;
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
};
- cpu1: cpu@1 {
+ cpu_e1: cpu@1 {
compatible = "apple,icestorm";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&ecluster_opp>;
+ capacity-dmips-mhz = <714>;
+ performance-domains = <&cpufreq_e>;
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
};
- cpu2: cpu@2 {
+ cpu_e2: cpu@2 {
compatible = "apple,icestorm";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&ecluster_opp>;
+ capacity-dmips-mhz = <714>;
+ performance-domains = <&cpufreq_e>;
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
};
- cpu3: cpu@3 {
+ cpu_e3: cpu@3 {
compatible = "apple,icestorm";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&ecluster_opp>;
+ capacity-dmips-mhz = <714>;
+ performance-domains = <&cpufreq_e>;
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
};
- cpu4: cpu@10100 {
+ cpu_p0: cpu@10100 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10100>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&pcluster_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p>;
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
};
- cpu5: cpu@10101 {
+ cpu_p1: cpu@10101 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10101>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&pcluster_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p>;
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
};
- cpu6: cpu@10102 {
+ cpu_p2: cpu@10102 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10102>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&pcluster_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p>;
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
};
- cpu7: cpu@10103 {
+ cpu_p3: cpu@10103 {
compatible = "apple,firestorm";
device_type = "cpu";
reg = <0x0 0x10103>;
enable-method = "spin-table";
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&pcluster_opp>;
+ capacity-dmips-mhz = <1024>;
+ performance-domains = <&cpufreq_p>;
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ };
+
+ l2_cache_0: l2-cache-0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x400000>;
+ };
+
+ l2_cache_1: l2-cache-1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0xc00000>;
+ };
+ };
+
+ ecluster_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+
+ opp01 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-level = <1>;
+ clock-latency-ns = <7500>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <972000000>;
+ opp-level = <2>;
+ clock-latency-ns = <22000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1332000000>;
+ opp-level = <3>;
+ clock-latency-ns = <27000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1704000000>;
+ opp-level = <4>;
+ clock-latency-ns = <33000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <2064000000>;
+ opp-level = <5>;
+ clock-latency-ns = <50000>;
+ };
+ };
+
+ pcluster_opp: opp-table-1 {
+ compatible = "operating-points-v2";
+
+ opp01 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-level = <1>;
+ clock-latency-ns = <8000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <828000000>;
+ opp-level = <2>;
+ clock-latency-ns = <19000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-level = <3>;
+ clock-latency-ns = <21000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1284000000>;
+ opp-level = <4>;
+ clock-latency-ns = <23000>;
};
+ opp05 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-level = <5>;
+ clock-latency-ns = <24000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1728000000>;
+ opp-level = <6>;
+ clock-latency-ns = <29000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1956000000>;
+ opp-level = <7>;
+ clock-latency-ns = <31000>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <2184000000>;
+ opp-level = <8>;
+ clock-latency-ns = <34000>;
+ };
+ opp09 {
+ opp-hz = /bits/ 64 <2388000000>;
+ opp-level = <9>;
+ clock-latency-ns = <36000>;
+ };
+ opp10 {
+ opp-hz = /bits/ 64 <2592000000>;
+ opp-level = <10>;
+ clock-latency-ns = <51000>;
+ };
+ opp11 {
+ opp-hz = /bits/ 64 <2772000000>;
+ opp-level = <11>;
+ clock-latency-ns = <54000>;
+ };
+ opp12 {
+ opp-hz = /bits/ 64 <2988000000>;
+ opp-level = <12>;
+ clock-latency-ns = <55000>;
+ };
+#if 0
+ /* Not available until CPU deep sleep is implemented */
+ opp13 {
+ opp-hz = /bits/ 64 <3096000000>;
+ opp-level = <13>;
+ clock-latency-ns = <55000>;
+ turbo-mode;
+ };
+ opp14 {
+ opp-hz = /bits/ 64 <3144000000>;
+ opp-level = <14>;
+ clock-latency-ns = <56000>;
+ turbo-mode;
+ };
+ opp15 {
+ opp-hz = /bits/ 64 <3204000000>;
+ opp-level = <15>;
+ clock-latency-ns = <56000>;
+ turbo-mode;
+ };
+#endif
};
timer {
@@ -116,6 +326,16 @@
clock-output-names = "clkref";
};
+ /*
+ * This is a fabulated representation of the input clock
+ * to NCO since we don't know the true clock tree.
+ */
+ nco_clkref: clock-ref-nco {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "nco_ref";
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -124,6 +344,27 @@
ranges;
nonposted-mmio;
+ cpufreq_e: performance-controller@210e20000 {
+ compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
+ reg = <0x2 0x10e20000 0 0x1000>;
+ #performance-domain-cells = <0>;
+ };
+
+ cpufreq_p: performance-controller@211e20000 {
+ compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
+ reg = <0x2 0x11e20000 0 0x1000>;
+ #performance-domain-cells = <0>;
+ };
+
+ sio_dart: iommu@235004000 {
+ compatible = "apple,t8103-dart";
+ reg = <0x2 0x35004000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 635 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ power-domains = <&ps_sio_cpu>;
+ };
+
i2c0: i2c@235010000 {
compatible = "apple,t8103-i2c", "apple,i2c";
reg = <0x2 0x35010000 0x0 0x4000>;
@@ -219,6 +460,61 @@
status = "disabled";
};
+ admac: dma-controller@238200000 {
+ compatible = "apple,t8103-admac", "apple,admac";
+ reg = <0x2 0x38200000 0x0 0x34000>;
+ dma-channels = <24>;
+ interrupts-extended = <0>,
+ <&aic AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>,
+ <0>,
+ <0>;
+ #dma-cells = <1>;
+ iommus = <&sio_dart 2>;
+ power-domains = <&ps_sio_adma>;
+ resets = <&ps_audio_p>;
+ };
+
+ mca: i2s@238400000 {
+ compatible = "apple,t8103-mca", "apple,mca";
+ reg = <0x2 0x38400000 0x0 0x18000>,
+ <0x2 0x38300000 0x0 0x30000>;
+
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 619 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 620 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 621 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 622 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 623 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 624 IRQ_TYPE_LEVEL_HIGH>;
+
+ resets = <&ps_audio_p>;
+ clocks = <&nco 0>, <&nco 1>, <&nco 2>,
+ <&nco 3>, <&nco 4>, <&nco 4>;
+ power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>,
+ <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>;
+ dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>,
+ <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>,
+ <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>,
+ <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>,
+ <&admac 16>, <&admac 17>, <&admac 18>, <&admac 19>,
+ <&admac 20>, <&admac 21>, <&admac 22>, <&admac 23>;
+ dma-names = "tx0a", "rx0a", "tx0b", "rx0b",
+ "tx1a", "rx1a", "tx1b", "rx1b",
+ "tx2a", "rx2a", "tx2b", "rx2b",
+ "tx3a", "rx3a", "tx3b", "rx3b",
+ "tx4a", "rx4a", "tx4b", "rx4b",
+ "tx5a", "rx5a", "tx5b", "rx5b";
+
+ #sound-dai-cells = <1>;
+ };
+
+ nco: clock-controller@23b044000 {
+ compatible = "apple,t8103-nco", "apple,nco";
+ reg = <0x2 0x3b044000 0x0 0x14000>;
+ clocks = <&nco_clkref>;
+ #clock-cells = <1>;
+ };
+
aic: interrupt-controller@23b100000 {
compatible = "apple,t8103-aic", "apple,aic";
#interrupt-cells = <3>;
@@ -229,12 +525,12 @@
affinities {
e-core-pmu-affinity {
apple,fiq-index = <AIC_CPU_PMU_E>;
- cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>;
};
p-core-pmu-affinity {
apple,fiq-index = <AIC_CPU_PMU_P>;
- cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>;
};
};
};
@@ -412,7 +708,7 @@
resets = <&ps_ans2>;
};
- pcie0_dart_0: dart@681008000 {
+ pcie0_dart_0: iommu@681008000 {
compatible = "apple,t8103-dart";
reg = <0x6 0x81008000 0x0 0x4000>;
#iommu-cells = <1>;
@@ -421,7 +717,7 @@
power-domains = <&ps_apcie_gp>;
};
- pcie0_dart_1: dart@682008000 {
+ pcie0_dart_1: iommu@682008000 {
compatible = "apple,t8103-dart";
reg = <0x6 0x82008000 0x0 0x4000>;
#iommu-cells = <1>;
@@ -430,7 +726,7 @@
power-domains = <&ps_apcie_gp>;
};
- pcie0_dart_2: dart@683008000 {
+ pcie0_dart_2: iommu@683008000 {
compatible = "apple,t8103-dart";
reg = <0x6 0x83008000 0x0 0x4000>;
#iommu-cells = <1>;
diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi
index 4e46826f883a..21f1f952e985 100644
--- a/arch/arm64/boot/dts/arm/corstone1000.dtsi
+++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi
@@ -53,6 +53,7 @@
L2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <64>;
diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
index 83e3e7e3984f..029578072d8f 100644
--- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
@@ -58,6 +58,7 @@
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
@@ -84,6 +85,11 @@
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
};
+ spe-pmu {
+ compatible = "arm,statistical-profiling-extension-v1";
+ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
watchdog@2a440000 {
compatible = "arm,sbsa-gwdt";
reg = <0x0 0x2a440000 0 0x1000>,
diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
index 5f6f30c801a7..60472d65a355 100644
--- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts
+++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
@@ -47,48 +47,121 @@
compatible = "arm,armv8";
reg = <0x0 0x000>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&C0_L2>;
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&C0_L2>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x200>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&C0_L2>;
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x300>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&C0_L2>;
};
cpu4: cpu@10000 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x10000>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&C1_L2>;
};
cpu5: cpu@10100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x10100>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&C1_L2>;
};
cpu6: cpu@10200 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x10200>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&C1_L2>;
};
cpu7: cpu@10300 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x10300>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&C1_L2>;
+ };
+ C0_L2: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-level = <2>;
+ cache-unified;
+ };
+
+ C1_L2: l2-cache1 {
+ compatible = "cache";
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-level = <2>;
+ cache-unified;
};
};
diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
index 6451c62146fd..1d90eeebb37d 100644
--- a/arch/arm64/boot/dts/arm/juno-r1.dts
+++ b/arch/arm64/boot/dts/arm/juno-r1.dts
@@ -189,6 +189,7 @@
A57_L2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -197,6 +198,7 @@
A53_L2: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
index 438cd1ff4bd0..d2ada69b0a43 100644
--- a/arch/arm64/boot/dts/arm/juno-r2.dts
+++ b/arch/arm64/boot/dts/arm/juno-r2.dts
@@ -195,6 +195,7 @@
A72_L2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -203,6 +204,7 @@
A53_L2: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index cf4a58211399..5e48a01a5b9f 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -194,6 +194,7 @@
A57_L2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -202,6 +203,7 @@
A53_L2: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
index 258991ad7cc0..ef68f5aae7dd 100644
--- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
@@ -71,6 +71,7 @@
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
index 5b6d9d8e934d..796cd7d02eb5 100644
--- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
+++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
@@ -57,6 +57,7 @@
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
index dac9d3b4e91d..eb2a78f4e033 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
@@ -63,6 +63,7 @@
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
@@ -283,6 +284,11 @@
#address-cells = <1>;
#size-cells = <1>;
+ timer@0 {
+ compatible = "brcm,bcm63138-timer";
+ reg = <0x0 0x28>;
+ };
+
watchdog@28 {
compatible = "brcm,bcm6345-wdt";
reg = <0x28 0x8>;
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
index 3d016c2ce675..d5bc31980f03 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
@@ -51,6 +51,7 @@
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
index 04de96bd0a03..6f805266d3c9 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
@@ -35,6 +35,7 @@
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
index 13629702f70b..b982249b80a2 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
@@ -51,6 +51,7 @@
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
index c3e6197be808..a996d436e977 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
@@ -51,6 +51,7 @@
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
index 0bce6497219f..62c530d4b103 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
@@ -35,6 +35,7 @@
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
index 29a880c6c858..34c7b513d363 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
@@ -50,6 +50,7 @@
};
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
@@ -109,6 +110,25 @@
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x62000>;
+ twd: timer-mfd@400 {
+ compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
+ reg = <0x400 0x4c>;
+ ranges = <0x0 0x400 0x4c>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ timer@0 {
+ compatible = "brcm,bcm63138-timer";
+ reg = <0x0 0x28>;
+ };
+
+ watchdog@28 {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x28 0x8>;
+ };
+ };
+
uart0: serial@640 {
compatible = "brcm,bcm6345-uart";
reg = <0x640 0x18>;
diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts
index e34172e3117e..fbf0392b8371 100644
--- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts
+++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts
@@ -52,7 +52,7 @@
memory {
device_type = "memory";
- reg = <0x000000000 0x80000000 0x00000000 0x40000000>;
+ reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts
index 7bf26f3e36bf..699f7742ce7f 100644
--- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts
+++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts
@@ -49,7 +49,7 @@
memory {
device_type = "memory";
- reg = <0x000000000 0x80000000 0x00000001 0x00000000>;
+ reg = <0x00000000 0x80000000 0x00000001 0x00000000>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
index fda97c47f4e9..18cdbc20f03f 100644
--- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
@@ -79,6 +79,7 @@
CLUSTER0_L2: l2-cache@0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
index 8f8c25e51194..e05901abe957 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
@@ -108,18 +108,22 @@
CLUSTER0_L2: l2-cache@0 {
compatible = "cache";
+ cache-level = <2>;
};
CLUSTER1_L2: l2-cache@100 {
compatible = "cache";
+ cache-level = <2>;
};
CLUSTER2_L2: l2-cache@200 {
compatible = "cache";
+ cache-level = <2>;
};
CLUSTER3_L2: l2-cache@300 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 3ea9edc87909..ef6f364eaa18 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -57,10 +57,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-innocomm-wb15-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl-osm-s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-phg.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dtso
index f826392c23fa..f826392c23fa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dtso
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dtso
index b949cac03742..b949cac03742 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dtso
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtso
index 1dff68d7484b..1dff68d7484b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtso
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dtso
index 19424d349713..19424d349713 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dtso
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dtso
index fb85847f778f..fb85847f778f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dtso
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtso
index 63e46fad22bd..63e46fad22bd 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtso
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index ac1c3a7e5f7a..1b33cabb4e14 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -46,6 +46,7 @@
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 704f72caddd3..b9fd24cdc919 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -84,6 +84,7 @@
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 3d9e29824bb2..a01e3cfec77f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -79,6 +79,7 @@
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index a2cadf757148..1e5d76c4d83d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -95,18 +95,22 @@
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-level = <2>;
};
CPU_PW20: cpu-pw20 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
index c3dc38188c17..c12c86915ec8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
@@ -95,18 +95,22 @@
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-level = <2>;
};
CPU_PW20: cpu-pw20 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 8c76d86cb756..50c19e8405d5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -300,6 +300,7 @@
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -308,6 +309,7 @@
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -316,6 +318,7 @@
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -324,6 +327,7 @@
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -332,6 +336,7 @@
cluster4_l2: l2-cache4 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -340,6 +345,7 @@
cluster5_l2: l2-cache5 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -348,6 +354,7 @@
cluster6_l2: l2-cache6 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -356,6 +363,7 @@
cluster7_l2: l2-cache7 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index 10370d1a6c6d..4852760adeee 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -34,6 +34,35 @@ conn_subsys: bus@5b000000 {
clock-output-names = "conn_ipg_clk";
};
+ usbotg1: usb@5b0d0000 {
+ compatible = "fsl,imx7ulp-usb";
+ reg = <0x5b0d0000 0x200>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,usbphy = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc1 0>;
+ clocks = <&usb2_lpcg 0>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ power-domains = <&pd IMX_SC_R_USB_0>;
+ status = "disabled";
+ };
+
+ usbmisc1: usbmisc@5b0d0200 {
+ #index-cells = <1>;
+ compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc";
+ reg = <0x5b0d0200 0x200>;
+ };
+
+ usbphy1: usbphy@5b100000 {
+ compatible = "fsl,imx7ulp-usbphy";
+ reg = <0x5b100000 0x1000>;
+ clocks = <&usb2_lpcg 1>;
+ power-domains = <&pd IMX_SC_R_USB_0_PHY>;
+ status = "disabled";
+ };
+
usdhc1: mmc@5b010000 {
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
@@ -195,4 +224,14 @@ conn_subsys: bus@5b000000 {
"enet1_lpcg_ipg_s_clk";
power-domains = <&pd IMX_SC_R_ENET_1>;
};
+
+ usb2_lpcg: clock-controller@5b270000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b270000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&conn_ahb_clk>, <&conn_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
+ clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
+ power-domains = <&pd IMX_SC_R_USB_0_PHY>;
+ };
};
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
index d7b4229bb4a2..a943a1e2797f 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -20,6 +20,70 @@ dma_subsys: bus@5a000000 {
clock-output-names = "dma_ipg_clk";
};
+ lpspi0: spi@5a000000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a000000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi0_lpcg 0>,
+ <&spi0_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <20000000>;
+ power-domains = <&pd IMX_SC_R_SPI_0>;
+ status = "disabled";
+ };
+
+ lpspi1: spi@5a010000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a010000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi1_lpcg 0>,
+ <&spi1_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <60000000>;
+ power-domains = <&pd IMX_SC_R_SPI_1>;
+ status = "disabled";
+ };
+
+ lpspi2: spi@5a020000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a020000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi2_lpcg 0>,
+ <&spi2_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <60000000>;
+ power-domains = <&pd IMX_SC_R_SPI_2>;
+ status = "disabled";
+ };
+
+ lpspi3: spi@5a030000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a030000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi3_lpcg 0>,
+ <&spi3_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <60000000>;
+ power-domains = <&pd IMX_SC_R_SPI_3>;
+ status = "disabled";
+ };
+
lpuart0: serial@5a060000 {
reg = <0x5a060000 0x1000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
@@ -60,6 +124,54 @@ dma_subsys: bus@5a000000 {
status = "disabled";
};
+ spi0_lpcg: clock-controller@5a400000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a400000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "spi0_lpcg_clk",
+ "spi0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_0>;
+ };
+
+ spi1_lpcg: clock-controller@5a410000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a410000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "spi1_lpcg_clk",
+ "spi1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_1>;
+ };
+
+ spi2_lpcg: clock-controller@5a420000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a420000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "spi2_lpcg_clk",
+ "spi2_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_2>;
+ };
+
+ spi3_lpcg: clock-controller@5a430000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a430000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "spi3_lpcg_clk",
+ "spi3_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_3>;
+ };
+
uart0_lpcg: clock-controller@5a460000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a460000 0x10000>;
@@ -156,6 +268,34 @@ dma_subsys: bus@5a000000 {
status = "disabled";
};
+ adc0: adc@5a880000 {
+ compatible = "nxp,imx8qxp-adc";
+ reg = <0x5a880000 0x10000>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&adc0_lpcg 0>,
+ <&adc0_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_ADC_0>;
+ status = "disabled";
+ };
+
+ adc1: adc@5a890000 {
+ compatible = "nxp,imx8qxp-adc";
+ reg = <0x5a890000 0x10000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&adc1_lpcg 0>,
+ <&adc1_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_ADC_1>;
+ status = "disabled";
+ };
+
i2c0_lpcg: clock-controller@5ac00000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac00000 0x10000>;
@@ -203,4 +343,28 @@ dma_subsys: bus@5a000000 {
"i2c3_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_I2C_3>;
};
+
+ adc0_lpcg: clock-controller@5ac80000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac80000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "adc0_lpcg_clk",
+ "adc0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_ADC_0>;
+ };
+
+ adc1_lpcg: clock-controller@5ac90000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac90000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "adc1_lpcg_clk",
+ "adc1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_ADC_1>;
+ };
};
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index 6446e6df7a9a..1f3d225e64ec 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -11,7 +11,8 @@ lsio_subsys: bus@5d000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
+ ranges = <0x5d000000 0x0 0x5d000000 0x1000000>,
+ <0x08000000 0x0 0x08000000 0x10000000>;
lsio_mem_clk: clock-lsio-mem {
compatible = "fixed-clock";
@@ -107,6 +108,20 @@ lsio_subsys: bus@5d000000 {
power-domains = <&pd IMX_SC_R_GPIO_7>;
};
+ flexspi0: spi@5d120000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imx8qxp-fspi";
+ reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>;
+ clock-names = "fspi", "fspi_en";
+ power-domains = <&pd IMX_SC_R_FSPI_0>;
+ status = "disabled";
+ };
+
lsio_mu0: mailbox@5d1b0000 {
reg = <0x5d1b0000 0x10000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index ca2a43e0cbf6..280a9c9d8bd9 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -90,6 +90,28 @@
enable-active-high;
off-on-delay-us = <3480>;
};
+
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ mii_select: regulator-4 {
+ compatible = "regulator-fixed";
+ regulator-name = "mii-select";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&scu_gpio 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+};
+
+&adc0 {
+ vref-supply = <&reg_vref_1v8>;
+ status = "okay";
};
&eqos {
@@ -159,6 +181,23 @@
};
};
+&flexspi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+ nxp,fspi-dll-slvdly = <4>;
+ status = "okay";
+
+ mt35xu512aba0: flash@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <133000000>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ };
+};
+
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
@@ -266,6 +305,40 @@
};
};
+&usbphy1 {
+ /* USB eye diagram tests result */
+ fsl,tx-d-cal = <114>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ power-active-high;
+ disable-over-current;
+ status = "okay";
+};
+
+&usbphy2 {
+ /* USB eye diagram tests result */
+ fsl,tx-d-cal = <111>;
+ status = "okay";
+};
+
+&usbotg2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg2>;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ power-active-high;
+ disable-over-current;
+ status = "okay";
+};
+
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
@@ -286,6 +359,21 @@
status = "okay";
};
+&lpspi3 {
+ fsl,spi-num-chipselects = <1>;
+ fsl,spi-only-use-cs1-sel;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi3>;
+ pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ spidev0: spi@0 {
+ reg = <0>;
+ compatible = "rohm,dh2228fv";
+ spi-max-frequency = <30000000>;
+ };
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
@@ -330,6 +418,25 @@
>;
};
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
+ IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
+ IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
+ IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
+ IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
+ IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
+ IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
+ IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
+ IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
+ IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
+ IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
+ IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
+ IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
+ IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
+ >;
+ };
+
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
index 795d1d472fae..6881330ab4c6 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
@@ -11,6 +11,10 @@
clock-frequency = <160000000>;
};
+&adc0 {
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+};
+
&i2c0 {
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
@@ -50,3 +54,19 @@
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
};
+
+&lpspi0 {
+ interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpspi1 {
+ interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpspi2 {
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpspi3 {
+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
index 69c4849f2132..6b416fb760d5 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
@@ -140,3 +140,13 @@
compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
};
+
+&usbotg1 {
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ /*
+ * usbotg1 and usbotg2 share one clock
+ * scfw disable clock access and keep it always on
+ * in case other core (M4) use one of these.
+ */
+ clocks = <&clk_dummy>;
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
index 815bd987b09b..5f4f789e4a73 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
@@ -3,44 +3,90 @@
* Copyright 2019~2020, 2022 NXP
*/
+&flexspi0 {
+ compatible = "nxp,imx8dxl-fspi";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+};
+
&lsio_gpio0 {
compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&iomuxc 0 47 13>,
+ <&iomuxc 13 61 4>,
+ <&iomuxc 19 67 4>,
+ <&iomuxc 24 72 1>;
};
&lsio_gpio1 {
compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&iomuxc 4 74 5>,
+ <&iomuxc 9 80 16>;
};
&lsio_gpio2 {
compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&iomuxc 1 98 2>,
+ <&iomuxc 3 101 1>,
+ <&iomuxc 5 107 8>;
};
&lsio_gpio3 {
compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&iomuxc 0 115 4>,
+ <&iomuxc 9 121 1>,
+ <&iomuxc 10 120 1>,
+ <&iomuxc 11 123 1>,
+ <&iomuxc 12 122 1>,
+ <&iomuxc 13 125 1>,
+ <&iomuxc 14 124 1>,
+ <&iomuxc 16 126 1>,
+ <&iomuxc 17 128 1>,
+ <&iomuxc 18 131 1>,
+ <&iomuxc 19 130 1>,
+ <&iomuxc 20 133 1>,
+ <&iomuxc 21 132 1>,
+ <&iomuxc 22 129 1>,
+ <&iomuxc 23 134 1>;
};
&lsio_gpio4 {
compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&iomuxc 0 0 3>,
+ <&iomuxc 3 4 4>,
+ <&iomuxc 7 9 12>,
+ <&iomuxc 19 22 2>,
+ <&iomuxc 21 25 2>,
+ <&iomuxc 29 29 3>;
};
&lsio_gpio5 {
compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&iomuxc 0 32 3>,
+ <&iomuxc 3 36 6>,
+ <&iomuxc 9 43 3>;
};
&lsio_gpio6 {
compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&iomuxc 0 53 7>,
+ <&iomuxc 8 86 10>,
+ <&iomuxc 19 107 8>;
};
&lsio_gpio7 {
compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&iomuxc 0 0 3>,
+ <&iomuxc 3 4 4>,
+ <&iomuxc 8 22 2>,
+ <&iomuxc 10 25 2>,
+ <&iomuxc 16 44 2>;
};
&lsio_mu0 {
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
index 5ddbda0b4def..0c64b9194621 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
@@ -59,6 +59,7 @@
A35_L2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
@@ -133,6 +134,12 @@
clock-names = "xtal_32KHz", "xtal_24Mhz";
};
+ scu_gpio: gpio {
+ compatible = "fsl,imx8qxp-sc-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
iomuxc: pinctrl {
compatible = "fsl,imx8dxl-iomuxc";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
index cf07987ccc10..201325f566cb 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
@@ -47,15 +47,15 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-25M {
+ opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
- opp-100M {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
- opp-750M {
+ opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
index 778bdbe228d3..24f61db33eba 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
@@ -46,6 +46,12 @@
clock-frequency = <25000000>;
};
+ clk_xtal32k: clk-xtal32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
panel: panel {
backlight = <&backlight>;
power-supply = <&reg_panel_vcc>;
@@ -77,12 +83,11 @@
enable-active-high;
};
- watchdog-gpio {
+ watchdog {
/* TPS3813 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_watchdog_gpio>;
compatible = "linux,wdt-gpio";
- always-enabled;
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
hw_algo = "level";
/* Reset triggers in 2..3 seconds */
@@ -114,15 +119,15 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-25M {
+ opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
- opp-100M {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
- opp-750M {
+ opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
@@ -183,8 +188,6 @@
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <10000>;
- qca,clk-out-frequency = <125000000>;
- qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
qca,keep-pll-enabled;
vddio-supply = <&vddio>;
@@ -271,6 +274,9 @@
pmic: pmic@4b {
compatible = "rohm,bd71847";
reg = <0x4b>;
+ #clock-cells = <0>;
+ clocks = <&clk_xtal32k 0>;
+ clock-output-names = "clk-32k-out";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
@@ -928,6 +934,10 @@
status = "disabled";
};
+&snvs_rtc {
+ clocks = <&pmic>;
+};
+
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index a2b24d4d4e3e..b68954bcc383 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
@@ -23,15 +23,15 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-25M {
+ opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
- opp-100M {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
- opp-750M {
+ opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index 7d6317d95b13..e0b604ac0da4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -56,6 +56,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <20000>;
enable-active-high;
};
@@ -343,6 +344,7 @@
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
+ vcc-supply = <&buck4_reg>;
};
};
@@ -399,6 +401,10 @@
status = "okay";
};
+&usbphynop1 {
+ wakeup-source;
+};
+
&usbotg1 {
dr_mode = "otg";
hnp-disable;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts
new file mode 100644
index 000000000000..055faae79930
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2018 Bang & Olufsen
+ * Copyright 2022 Pengutronix
+ */
+
+/dts-v1/;
+
+#include "imx8mm-innocomm-wb15.dtsi"
+
+/ {
+ model = "InnoComm WB15-EVK";
+ compatible = "innocomm,wb15-evk", "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-0 {
+ label = "debug";
+ gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ reg_vsd_3v3: regulator-vsd-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_vsd_3v3>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_ethphy: regulator-eth-phy {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec_phy_reg>;
+ regulator-name = "PHY_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec_phy>;
+ reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ phy-supply = <&reg_ethphy>;
+ };
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc2 {
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&reg_vsd_3v3>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_fec: fec-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ >;
+ };
+
+ pinctrl_fec_phy: fec-phy-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ >;
+ };
+
+ pinctrl_fec_phy_reg: fec-phy-reg-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x16
+ >;
+ };
+
+ pinctrl_gpio_leds: led-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0xd6
+ >;
+ };
+
+ pinctrl_reg_vsd_3v3: reg-vsd-3v3-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
+ >;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
new file mode 100644
index 000000000000..44e87b1568e7
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
@@ -0,0 +1,480 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2018 Bang & Olufsen
+ */
+
+#include "imx8mm.dtsi"
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+/ {
+ reg_modem: regulator-modem {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_modem_regulator>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "epdev_on";
+ gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_3v3_out: regulator-3v3-out {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3_OUT";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&cpu_alert0 {
+ temperature = <95000>;
+};
+
+&cpu_crit0 {
+ temperature = <105000>;
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25000000 {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ rohm,reset-snvs-powered;
+
+ regulators {
+ buck1_reg: BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <850000>;
+ rohm,dvs-idle-voltage = <850000>;
+ rohm,dvs-suspend-voltage = <850000>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ };
+
+ buck3_reg: BUCK3 {
+ // buck5 in datasheet
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck4_reg: BUCK4 {
+ // buck6 in datasheet
+ regulator-name = "buck4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5_reg: BUCK5 {
+ // buck7 in datasheet
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6_reg: BUCK6 {
+ // buck8 in datasheet
+ regulator-name = "buck6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&pcie_phy {
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
+ fsl,tx-deemph-gen1 = <0x2d>;
+ fsl,tx-deemph-gen2 = <0xf>;
+ status = "okay";
+};
+
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_PHY>,
+ <&clk IMX8MM_CLK_PCIE1_AUX>;
+ clock-names = "pcie", "pcie_bus", "pcie_aux";
+ fsl,max-link-speed = <1>;
+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>;
+ assigned-clock-rates = <10000000>, <250000000>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>;
+ status = "okay";
+};
+
+&uart1 { /* BT */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ assigned-clocks = <&clk IMX8MM_CLK_UART1>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4349-bt";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_modem_bt>;
+ device-wakeup-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ vbat-supply = <&reg_3v3_out>;
+ vddio-supply = <&reg_3v3_out>;
+ clocks = <&osc_32k>;
+ max-speed = <3000000>;
+ clock-names = "extclk";
+ };
+};
+
+&uart2 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ no-sd;
+ no-sdio;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&A53_0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2_reg>;
+};
+
+/delete-node/ &sec_jr1; /* Job ring in use by OP-TEE */
+
+&iomuxc {
+ pinctrl_i2c1: i2c1-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2-gpio-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3: i2c3-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3-gpio-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
+ >;
+ };
+
+ pinctrl_pcie0: pcie0-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61
+ MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x6
+ >;
+ };
+
+ pinctrl_modem_bt: modem-bt-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x19
+ MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x19
+ MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19
+ MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19
+ MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
+ >;
+ };
+
+ pinctrl_modem_regulator: modem-reg-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x41
+ >;
+ };
+
+ pinctrl_pmic: pmic-irq-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
+ >;
+ };
+
+ pinctrl_uart1: uart1-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
+ >;
+ };
+
+ pinctrl_uart2: uart2-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000194
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000196
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_wdog: wdog-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi
index 8d10f5b41297..5172883717d1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi
@@ -47,11 +47,11 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-100M {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
- opp-750M {
+ opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi
index 0679728d2489..1f8326613ee9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi
@@ -46,11 +46,11 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-100M {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
- opp-750M {
+ opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phg.dts b/arch/arm64/boot/dts/freescale/imx8mm-phg.dts
new file mode 100644
index 000000000000..e9447738b104
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-phg.dts
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Fabio Estevam <festevam@denx.de>
+ */
+
+/dts-v1/;
+
+#include "imx8mm-tqma8mqml.dtsi"
+
+/ {
+ model = "Cloos i.MX8MM PHG board";
+ compatible = "cloos,imx8mm-phg", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
+
+ aliases {
+ mmc0 = &usdhc3;
+ mmc1 = &usdhc2;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ beeper {
+ compatible = "gpio-beeper";
+ pinctrl-0 = <&pinctrl_beeper>;
+ gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_led>;
+
+ led-0 {
+ label = "status1";
+ gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-1 {
+ label = "status2";
+ gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-2 {
+ label = "status3";
+ gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-3 {
+ label = "run";
+ gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-4 {
+ label = "powerled";
+ gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_otg_vbus_ctrl>;
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usdhc2_vmmc: regulator-vmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ off-on-delay-us = <12000>;
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&usbphynop1 {
+ power-domains = <&pgc_otg1>;
+};
+
+&usbphynop2 {
+ power-domains = <&pgc_otg2>;
+};
+
+&usbotg1 {
+ dr_mode = "host";
+ vbus-supply = <&reg_usb_otg_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc2 {
+ assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
+ assigned-clock-rates = <400000000>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ no-mmc;
+ no-sdio;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+ vmmc-supply = <&reg_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_beeper: beepergrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x40000002
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x14
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x14
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x14
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x14
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x14
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14
+ MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x10
+ >;
+ };
+
+ pinctrl_gpio_led: gpioledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
+ MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_otg_vbus_ctrl: otgvbusctrlgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x119
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ >;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi
index 995b44efb1b6..92616bc4f71f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi
@@ -53,15 +53,15 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-25M {
+ opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
- opp-100M {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
- opp-750M {
+ opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
index a0bd540f27d3..ae0721b807e1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
@@ -53,15 +53,15 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-25M {
+ opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
- opp-100M {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
- opp-750M {
+ opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
index 66a0d103c90f..9e7d38872157 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
@@ -81,15 +81,15 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-25M {
+ opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
- opp-100M {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
- opp-750M {
+ opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
@@ -119,8 +119,11 @@
&i2c1 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@@ -365,8 +368,11 @@
&i2c2 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
eeprom@52 {
@@ -435,6 +441,13 @@
>;
};
+ pinctrl_i2c1_gpio: i2c1gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@@ -442,6 +455,13 @@
>;
};
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
+ >;
+ };
+
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dtso
index 4eaf8aabcbff..4eaf8aabcbff 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dtso
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtso
index 3ea73a6886ff..3ea73a6886ff 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtso
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtso
index c3cd9f2b0db3..c3cd9f2b0db3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtso
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dtso
index cc0a287226ab..cc0a287226ab 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dtso
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dtso
index f3ece4b7fbbd..f3ece4b7fbbd 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dtso
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtso
index 2fa635e1c1a8..2fa635e1c1a8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtso
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtso
index 3e6404340d52..3e6404340d52 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtso
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtso
index 2c71ab9854cb..2c71ab9854cb 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtso
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
index d3ee6fc4baab..750a1f07ecb7 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
@@ -248,15 +248,15 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-25M {
+ opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
- opp-100M {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
- opp-750M {
+ opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
@@ -326,8 +326,11 @@
&i2c1 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@@ -477,8 +480,11 @@
&i2c2 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic@4b {
@@ -600,8 +606,11 @@
&i2c3 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
leds_gpio: gpio@20 {
@@ -673,8 +682,11 @@
&i2c4 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@@ -852,6 +864,13 @@
>;
};
+ pinctrl_i2c1_gpio: i2c1gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@@ -859,6 +878,13 @@
>;
};
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@@ -866,6 +892,13 @@
>;
};
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
+ >;
+ };
+
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
@@ -873,6 +906,13 @@
>;
};
+ pinctrl_i2c4_gpio: i2c4gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
+ >;
+ };
+
pinctrl_ksz: kszgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
index 31f4c735fe4f..32872b0b1aaf 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
@@ -198,15 +198,15 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-25M {
+ opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
- opp-100M {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
- opp-750M {
+ opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
@@ -261,7 +261,7 @@
&gpio1 {
gpio-line-names = "", "", "", "", "", "", "", "",
- "", "", "", "", "", "m2_reset", "", "m2_wdis#",
+ "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
@@ -283,7 +283,8 @@
&gpio4 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "",
- "", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485",
+ "lte_pwr#", "lte_rst", "lte_int", "",
+ "amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485",
"", "uart1_term", "uart1_half", "app_gpio2",
"mipi_gpio1", "", "", "";
};
@@ -298,8 +299,11 @@
&i2c1 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@@ -566,8 +570,11 @@
&i2c2 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
accelerometer@19 {
@@ -585,16 +592,22 @@
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
/* off-board header */
&i2c4 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@@ -738,14 +751,19 @@
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */
+ MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */
+ MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */
MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */
MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
+ MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
@@ -779,8 +797,6 @@
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
- MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
- MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
>;
};
@@ -797,6 +813,13 @@
>;
};
+ pinctrl_i2c1_gpio: i2c1gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@@ -804,6 +827,13 @@
>;
};
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@@ -811,6 +841,13 @@
>;
};
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
+ >;
+ };
+
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
@@ -818,6 +855,13 @@
>;
};
+ pinctrl_i2c4_gpio: i2c4gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
+ >;
+ };
+
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
index 19f6d2943d26..8ce562246a08 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
@@ -207,15 +207,15 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-25M {
+ opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
- opp-100M {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
- opp-750M {
+ opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
@@ -265,8 +265,11 @@
&i2c1 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@@ -397,8 +400,11 @@
&i2c2 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic@4b {
@@ -520,8 +526,11 @@
&i2c3 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
accelerometer@19 {
@@ -681,6 +690,13 @@
>;
};
+ pinctrl_i2c1_gpio: i2c1gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@@ -688,6 +704,13 @@
>;
};
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@@ -695,6 +718,13 @@
>;
};
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
+ >;
+ };
+
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
index a67771d02146..eceed9816f5d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
@@ -266,15 +266,15 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-25M {
+ opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
- opp-100M {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
- opp-750M {
+ opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
@@ -315,8 +315,11 @@
&i2c1 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@@ -441,8 +444,11 @@
&i2c2 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic@4b {
@@ -564,8 +570,11 @@
&i2c3 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
accelerometer@19 {
@@ -582,8 +591,11 @@
&i2c4 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gpioled: gpio@27 {
@@ -738,6 +750,13 @@
>;
};
+ pinctrl_i2c1_gpio: i2c1gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@@ -745,6 +764,13 @@
>;
};
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@@ -752,6 +778,13 @@
>;
};
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
+ >;
+ };
+
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
@@ -759,6 +792,13 @@
>;
};
+ pinctrl_i2c4_gpio: i2c4gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
+ >;
+ };
+
pinctrl_pcie0: pciegrp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index bcab830c6e95..0d454e0e2f7c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -3,8 +3,8 @@
* Copyright 2022 Toradex
*/
-#include "dt-bindings/phy/phy-imx8-pcie.h"
-#include "dt-bindings/pwm/pwm.h"
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include <dt-bindings/pwm/pwm.h>
#include "imx8mm.dtsi"
/ {
@@ -183,15 +183,15 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-25M {
+ opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
- opp-100M {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
- opp-750M {
+ opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
@@ -610,7 +610,7 @@
compatible = "atmel,maxtouch";
/*
* Verdin GPIO_9_DSI
- * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
+ * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
*/
interrupt-parent = <&gpio3>;
interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
@@ -653,7 +653,8 @@
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
assigned-clock-rates = <10000000>, <250000000>;
- clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
+ <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_PHY>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
pinctrl-names = "default";
@@ -664,6 +665,7 @@
&pcie_phy {
clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
+ clock-names = "ref";
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
fsl,tx-deemph-gen1 = <0x2d>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 50ef92915c67..4ee89fdcf59b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -139,6 +139,7 @@
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
@@ -575,9 +576,10 @@
};
};
- anatop: anatop@30360000 {
- compatible = "fsl,imx8mm-anatop", "syscon";
+ anatop: clock-controller@30360000 {
+ compatible = "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
+ #clock-cells = <1>;
};
snvs: snvs@30370000 {
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
index 1133cded9be2..8a4369d38903 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
@@ -55,15 +55,15 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-25M {
+ opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
- opp-100M {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
- opp-800M {
+ opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
index d8ce217c6016..5110d59b719f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -35,15 +35,15 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-25M {
+ opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
- opp-100M {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
- opp-600M {
+ opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
index 4eb467df5ba7..4839a962a170 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
@@ -47,6 +47,7 @@
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
+ nxp,dvs-standby-voltage = <750000>;
};
buck2: BUCK2 {
@@ -56,8 +57,6 @@
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
- nxp,dvs-run-voltage = <950000>;
- nxp,dvs-standby-voltage = <850000>;
};
buck4: BUCK4{
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index 261c36540079..8fef980c4ab2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -36,6 +36,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <12000>;
enable-active-high;
};
@@ -159,8 +160,11 @@
&i2c2 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
status = "okay";
ptn5110: tcpc@50 {
@@ -195,8 +199,11 @@
&i2c3 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
status = "okay";
pca6416: gpio@20 {
@@ -240,6 +247,15 @@
status = "okay";
};
+&uart1 { /* BT */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ assigned-clocks = <&clk IMX8MN_CLK_UART1>;
+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
@@ -255,6 +271,10 @@
status = "okay";
};
+&usbphynop1 {
+ wakeup-source;
+};
+
&usbotg1 {
dr_mode = "otg";
hnp-disable;
@@ -369,6 +389,13 @@
>;
};
+ pinctrl_i2c2_gpio: i2c2grp-gpio {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
+ MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@@ -376,6 +403,13 @@
>;
};
+ pinctrl_i2c3_gpio: i2c3grp-gpio {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
+ MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
+ >;
+ };
+
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
@@ -419,6 +453,15 @@
>;
};
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
+ MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
+ >;
+ };
+
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts
index dd4302ac1de4..b9444e4a3d2d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts
@@ -189,15 +189,15 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-25M {
+ opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
- opp-100M {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
- opp-750M {
+ opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
@@ -256,7 +256,7 @@
&gpio1 {
gpio-line-names = "", "", "", "", "", "", "", "",
- "", "", "", "", "", "m2_reset", "", "m2_wdis#",
+ "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
@@ -278,7 +278,7 @@
&gpio4 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
- "", "", "", "", "", "app_gpio1", "", "uart1_rs485",
+ "", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485",
"", "uart1_term", "uart1_half", "app_gpio2",
"mipi_gpio1", "", "", "";
};
@@ -297,8 +297,11 @@
&i2c1 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@@ -565,8 +568,11 @@
&i2c2 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
accelerometer@19 {
@@ -584,16 +590,22 @@
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
/* off-board header */
&i2c4 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@@ -689,10 +701,12 @@
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
+ MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */
MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
+ MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */
MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
@@ -726,8 +740,6 @@
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
- MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
- MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
>;
};
@@ -744,6 +756,13 @@
>;
};
+ pinctrl_i2c1_gpio: i2c1gpiogrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
+ MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
@@ -751,6 +770,13 @@
>;
};
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
+ MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@@ -758,6 +784,13 @@
>;
};
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
+ MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
+ >;
+ };
+
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
@@ -765,6 +798,13 @@
>;
};
+ pinctrl_i2c4_gpio: i2c4gpiogrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
+ MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
+ >;
+ };
+
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 67b554ba690c..b7d91df71cc2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -139,6 +139,7 @@
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
@@ -576,10 +577,10 @@
};
};
- anatop: anatop@30360000 {
- compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
- "syscon";
+ anatop: clock-controller@30360000 {
+ compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
+ #clock-cells = <1>;
};
snvs: snvs@30370000 {
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
index 0f13ee362771..6e1192e751f8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
@@ -427,6 +427,24 @@
pinctrl-0 = <&pinctrl_uart2>;
uart-has-rtscts;
status = "okay";
+
+ /*
+ * PLL3 at 320 MHz supplies UART2 root with 64 MHz clock,
+ * which with 16x oversampling yields 4 Mbdps baud base,
+ * which is exactly the maximum rate supported by muRata
+ * 2AE bluetooth UART.
+ */
+ assigned-clocks = <&clk IMX8MP_SYS_PLL3>, <&clk IMX8MP_CLK_UART2>;
+ assigned-clock-parents = <0>, <&clk IMX8MP_SYS_PLL3_OUT>;
+ assigned-clock-rates = <320000000>, <64000000>;
+
+ bluetooth {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_bt>;
+ compatible = "cypress,cyw4373a0-bt";
+ shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ max-speed = <4000000>;
+ };
};
&uart3 {
@@ -849,6 +867,13 @@
>;
};
+ pinctrl_uart2_bt: dhcom-uart2-bt-grp {
+ fsl,pins = <
+ /* BT_REG_EN */
+ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
+ >;
+ };
+
pinctrl_uart3: dhcom-uart3-grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x49
@@ -886,8 +911,6 @@
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
- /* BT_REG_EN */
- MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
/* WL_REG_EN */
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
>;
@@ -901,8 +924,6 @@
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
- /* BT_REG_EN */
- MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
/* WL_REG_EN */
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
>;
@@ -916,8 +937,6 @@
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
- /* BT_REG_EN */
- MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
/* WL_REG_EN */
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index b4c1ef2559f2..d4c7ca16abd0 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -85,6 +85,20 @@
};
};
+&flexspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
&A53_0 {
cpu-supply = <&reg_arm>;
};
@@ -317,6 +331,13 @@
};
};
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -390,10 +411,37 @@
status = "okay";
};
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "okay";
+};
+
&snvs_pwrkey {
status = "okay";
};
+&uart1 { /* BT */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ assigned-clocks = <&clk IMX8MP_CLK_UART1>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
&uart2 {
/* console */
pinctrl-names = "default";
@@ -416,6 +464,15 @@
status = "okay";
};
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ assigned-clocks = <&clk IMX8MP_CLK_UART3>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
&usdhc2 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
assigned-clock-rates = <400000000>;
@@ -515,6 +572,17 @@
>;
};
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
+ MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
+ MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
+ MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
+ MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
+ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
+ >;
+ };
+
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
@@ -528,6 +596,13 @@
>;
};
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
@@ -567,12 +642,39 @@
>;
};
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116
+ >;
+ };
+
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
+ MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
+ MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
+ >;
+ };
+
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
@@ -586,6 +688,15 @@
>;
};
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
+ MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
+ MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
+ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
+ >;
+ };
+
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
index 7bf6f81e87b4..6357f3d96ccd 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
@@ -8,6 +8,7 @@
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <dt-bindings/pwm/pwm.h>
#include "imx8mp-tqma8mpql.dtsi"
@@ -48,6 +49,27 @@
status = "disabled";
};
+ clk_xtal25: clk-xtal25 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ fan0: pwm-fan {
+ compatible = "pwm-fan";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwmfan>;
+ fan-supply = <&reg_pwm_fan>;
+ #cooling-cells = <2>;
+ /* typical 25 kHz -> 40.000 nsec */
+ pwms = <&pwm3 0 40000 PWM_POLARITY_INVERTED>;
+ cooling-levels = <0 32 64 128 196 240>;
+ pulses-per-revolution = <2>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+ status = "disabled";
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -108,6 +130,18 @@
status = "disabled";
};
+ reg_pwm_fan: regulator-pwm-fan {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_regpwmfan>;
+ regulator-name = "FAN_PWR";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&reg_vcc_12v0>;
+ };
+
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -165,6 +199,47 @@
linux,cma-default;
};
};
+
+ thermal-zones {
+ soc-thermal {
+ trips {
+ soc_active0: trip-active0 {
+ temperature = <40000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+
+ soc_active1: trip-active1 {
+ temperature = <48000>;
+ hysteresis = <3000>;
+ type = "active";
+ };
+
+ soc_active2: trip-active2 {
+ temperature = <60000>;
+ hysteresis = <10000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map1 {
+ trip = <&soc_active0>;
+ cooling-device = <&fan0 1 1>;
+ };
+
+ map2 {
+ trip = <&soc_active1>;
+ cooling-device = <&fan0 2 2>;
+ };
+
+ map3 {
+ trip = <&soc_active2>;
+ cooling-device = <&fan0 3 3>;
+ };
+ };
+ };
+ };
};
&ecspi1 {
@@ -340,9 +415,16 @@
"", "", "", "",
"", "", "", "",
"", "", "DP_IRQ", "DSI_EN",
- "HDMI_OC#", "TEMP_EVENT#", "PCIE_CLK_OE#", "",
+ "HDMI_OC#", "TEMP_EVENT#", "PCIE_REFCLK_OE#", "",
"", "", "", "FAN_PWR",
"RTC_EVENT#", "CODEC_RST#", "", "";
+
+ pcie-refclkreq-hog {
+ gpio-hog;
+ gpios = <22 0>;
+ output-high;
+ line-name = "PCIE_REFCLK_OE#";
+ };
};
&gpio5 {
@@ -377,6 +459,13 @@
pagesize = <16>;
vcc-supply = <&reg_vcc_3v3>;
};
+
+ pcieclk: clock-generator@6a {
+ compatible = "renesas,9fgv0241";
+ reg = <0x6a>;
+ clocks = <&clk_xtal25>;
+ #clock-cells = <1>;
+ };
};
&i2c4 {
@@ -407,6 +496,25 @@
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
};
+&pcie_phy {
+ fsl,clkreq-unsupported;
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+ clocks = <&pcieclk 0>;
+ clock-names = "ref";
+ status = "okay";
+};
+
+&pcie {
+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+ <&clk IMX8MP_CLK_HSIO_AXI>,
+ <&clk IMX8MP_CLK_PCIE_ROOT>;
+ clock-names = "pcie", "pcie_bus", "pcie_aux";
+ assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
+ assigned-clock-rates = <10000000>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
+ status = "okay";
+};
+
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
@@ -461,11 +569,23 @@
status = "okay";
};
+&usb3_1 {
+ fsl,disable-port-power-control;
+ fsl,permanently-attached;
+ dr_mode = "host";
+ status = "okay";
+};
+
&usb3_phy0 {
vbus-supply = <&reg_vcc_5v0>;
status = "okay";
};
+&usb3_phy1 {
+ vbus-supply = <&reg_vcc_5v0>;
+ status = "okay";
+};
+
&usb_dwc3_0 {
/* dual role is implemented, but not a full featured OTG */
hnp-disable;
@@ -486,6 +606,31 @@
};
};
+&usb_dwc3_1 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbhub>;
+ status = "okay";
+
+ hub_2_0: hub@1 {
+ compatible = "usb451,8142";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&reg_vcc_3v3>;
+ };
+
+ hub_3_0: hub@2 {
+ compatible = "usb451,8140";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&reg_vcc_3v3>;
+ };
+};
+
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
@@ -685,10 +830,18 @@
fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x14>;
};
+ pinctrl_pwmfan: pwmfangrp {
+ fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x80>; /* FAN RPM */
+ };
+
pinctrl_reg12v0: reg12v0grp {
fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140>; /* VCC12V enable */
};
+ pinctrl_regpwmfan: regpwmfangrp {
+ fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x80>;
+ };
+
/* X61 */
pinctrl_uart1: uart1grp {
fsl,pins = <MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x140>,
@@ -720,6 +873,10 @@
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0>;
};
+ pinctrl_usbhub: usbhubgrp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x10>;
+ };
+
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>,
<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>,
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
index 06b4c93c5876..ceeca4966fc5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
@@ -253,8 +253,11 @@
&i2c1 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
@@ -477,8 +480,11 @@
&i2c2 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
accelerometer@19 {
@@ -556,16 +562,22 @@
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
/* off-board header */
&i2c4 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@@ -800,6 +812,13 @@
>;
};
+ pinctrl_i2c1_gpio: i2c1gpiogrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2
+ MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
@@ -807,6 +826,13 @@
>;
};
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3
+ MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
@@ -814,6 +840,13 @@
>;
};
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3
+ MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3
+ >;
+ };
+
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
@@ -821,6 +854,13 @@
>;
};
+ pinctrl_i2c4_gpio: i2c4gpiogrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3
+ MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3
+ >;
+ };
+
pinctrl_ksz: kszgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
index 4b8f86f63081..80db1ad7c230 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
@@ -116,6 +116,7 @@
/* Verdin USB_2 */
&usb3_1 {
+ fsl,permanently-attached;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
index 5dcd1de586b5..6a1890a4b5d8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
@@ -3,7 +3,8 @@
* Copyright 2022 Toradex
*/
-#include "dt-bindings/pwm/pwm.h"
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include <dt-bindings/pwm/pwm.h>
#include "imx8mp.dtsi"
/ {
@@ -678,8 +679,8 @@
status = "disabled";
};
- lvds_ti_sn65dsi83: bridge@2c {
- compatible = "ti,sn65dsi83";
+ lvds_ti_sn65dsi84: bridge@2c {
+ compatible = "ti,sn65dsi84";
/* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
/* Verdin GPIO_10_DSI (SODIMM 21) */
enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
@@ -712,7 +713,7 @@
compatible = "atmel,maxtouch";
/*
* Verdin GPIO_9_DSI
- * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
+ * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
*/
interrupt-parent = <&gpio4>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
@@ -806,28 +807,45 @@
};
/* Verdin USB_1 */
-&usb3_phy0 {
- vbus-supply = <&reg_usb1_vbus>;
+&usb3_0 {
+ fsl,disable-port-power-control;
+ fsl,over-current-active-low;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_1_oc_n>;
};
&usb_dwc3_0 {
+ /* dual role only, not full featured OTG */
adp-disable;
dr_mode = "otg";
hnp-disable;
maximum-speed = "high-speed";
- over-current-active-low;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb_1_id>;
+ role-switch-default-mode = "peripheral";
srp-disable;
+ usb-role-switch;
+
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+ label = "Type-C";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_1_id>;
+ self-powered;
+ type = "micro";
+ vbus-supply = <&reg_usb1_vbus>;
+ };
};
/* Verdin USB_2 */
+&usb3_1 {
+ fsl,disable-port-power-control;
+};
+
&usb3_phy1 {
vbus-supply = <&reg_usb2_vbus>;
};
&usb_dwc3_1 {
- disable-over-current;
dr_mode = "host";
};
@@ -1045,7 +1063,6 @@
pinctrl_gpio_hog3: gpiohog3grp {
fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x1c4>, /* SODIMM 157 */
/* CSI_1_MCLK */
<MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4>; /* SODIMM 91 */
};
@@ -1220,7 +1237,7 @@
pinctrl_usb1_vbus: usb1vbusgrp {
fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x19>; /* SODIMM 155 */
+ <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x106>; /* SODIMM 155 */
};
/* USB_1_ID */
@@ -1229,9 +1246,15 @@
<MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>; /* SODIMM 161 */
};
+ /* USB_1_OC# */
+ pinctrl_usb_1_oc_n: usb1ocngrp {
+ fsl,pins =
+ <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c4>; /* SODIMM 157 */
+ };
+
pinctrl_usb2_vbus: usb2vbusgrp {
fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19>; /* SODIMM 185 */
+ <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x106>; /* SODIMM 185 */
};
/* On-module Wi-Fi */
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index bb916a0948a8..7a6e6221f421 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -123,6 +123,7 @@
A53_L2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <64>;
@@ -441,10 +442,10 @@
};
};
- anatop: anatop@30360000 {
- compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
- "syscon";
+ anatop: clock-controller@30360000 {
+ compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
+ #clock-cells = <1>;
};
snvs: snvs@30370000 {
@@ -631,6 +632,14 @@
reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
};
+
+ pgc_mlmix: power-domain@24 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
+ clocks = <&clk IMX8MP_CLK_ML_AXI>,
+ <&clk IMX8MP_CLK_ML_AHB>,
+ <&clk IMX8MP_CLK_NPU_ROOT>;
+ };
};
};
};
@@ -705,12 +714,15 @@
ecspi1: spi@30820000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
+ compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30820000 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
<&clk IMX8MP_CLK_ECSPI1_ROOT>;
clock-names = "ipg", "per";
+ assigned-clock-rates = <80000000>;
+ assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
dma-names = "rx", "tx";
status = "disabled";
@@ -719,12 +731,15 @@
ecspi2: spi@30830000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
+ compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30830000 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
<&clk IMX8MP_CLK_ECSPI2_ROOT>;
clock-names = "ipg", "per";
+ assigned-clock-rates = <80000000>;
+ assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
dma-names = "rx", "tx";
status = "disabled";
@@ -733,12 +748,15 @@
ecspi3: spi@30840000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
+ compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30840000 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
<&clk IMX8MP_CLK_ECSPI3_ROOT>;
clock-names = "ipg", "per";
+ assigned-clock-rates = <80000000>;
+ assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
dma-names = "rx", "tx";
status = "disabled";
@@ -1063,11 +1081,11 @@
noc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-200M {
+ opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
};
- opp-1000M {
+ opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 82387b9cb800..78937910f403 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -46,6 +46,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <20000>;
enable-active-high;
};
@@ -163,22 +164,22 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-25M {
+ opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
- opp-100M {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
/*
* On imx8mq B0 PLL can't be bypassed so low bus is 166M
*/
- opp-166M {
+ opp-166000000 {
opp-hz = /bits/ 64 <166935483>;
};
- opp-800M {
+ opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
index 6445c6b90b5b..4c8904fba1c1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
@@ -7,6 +7,7 @@
#include "dt-bindings/input/input.h"
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
#include "dt-bindings/pwm/pwm.h"
#include "dt-bindings/usb/pd.h"
#include "imx8mq.dtsi"
@@ -61,14 +62,13 @@
};
leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
+ compatible = "pwm-leds";
led1 {
- label = "LED 1";
- gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
- default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ max-brightness = <248>;
+ pwms = <&pwm2 0 50000 0>;
};
};
@@ -615,9 +615,9 @@
>;
};
- pinctrl_gpio_leds: gpioledgrp {
+ pinctrl_pwm_led: pwmledgrp {
fsl,pins = <
- MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16
+ MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16
>;
};
@@ -920,6 +920,12 @@
status = "okay";
};
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm_led>;
+ status = "okay";
+};
+
&snvs_pwrkey {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
index ae08556b2ef2..ddf0e330dc7c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
@@ -311,15 +311,15 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-25M {
+ opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
- opp-100M {
+ opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
- opp-800M {
+ opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
index 802ad6e5cef6..9a95e30fb42d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
@@ -220,12 +220,14 @@
reg = <0x53>;
pagesize = <16>;
read-only;
+ vcc-supply = <&reg_vcc3v3>;
};
eeprom0: eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <32>;
+ vcc-supply = <&reg_vcc3v3>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 19eaa523564d..7ce99c084e54 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -179,6 +179,7 @@
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -605,10 +606,11 @@
};
};
- anatop: syscon@30360000 {
- compatible = "fsl,imx8mq-anatop", "syscon";
+ anatop: clock-controller@30360000 {
+ compatible = "fsl,imx8mq-anatop";
reg = <0x30360000 0x10000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
};
snvs: snvs@30370000 {
@@ -1184,7 +1186,7 @@
};
csi1: csi@30a90000 {
- compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
+ compatible = "fsl,imx8mq-csi";
reg = <0x30a90000 0x10000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>;
@@ -1236,7 +1238,7 @@
};
csi2: csi@30b80000 {
- compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
+ compatible = "fsl,imx8mq-csi";
reg = <0x30b80000 0x10000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>;
@@ -1356,15 +1358,15 @@
noc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-133M {
+ opp-133000000 {
opp-hz = /bits/ 64 <133333333>;
};
- opp-400M {
+ opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
};
- opp-800M {
+ opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
index 669aa14ce9f7..b483134f84d1 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
@@ -6,30 +6,68 @@
&lsio_gpio0 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ gpio-ranges = <&iomuxc 0 0 6>,
+ <&iomuxc 6 7 22>,
+ <&iomuxc 28 36 4>;
};
&lsio_gpio1 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ gpio-ranges = <&iomuxc 0 40 4>,
+ <&iomuxc 4 50 12>,
+ <&iomuxc 16 63 8>,
+ <&iomuxc 24 72 8>;
};
&lsio_gpio2 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ gpio-ranges = <&iomuxc 0 80 4>,
+ <&iomuxc 4 85 18>,
+ <&iomuxc 22 104 10>;
};
&lsio_gpio3 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ gpio-ranges = <&iomuxc 0 114 2>,
+ <&iomuxc 2 117 16>,
+ <&iomuxc 18 141 1>,
+ <&iomuxc 19 140 1>,
+ <&iomuxc 20 139 1>,
+ <&iomuxc 21 138 1>,
+ <&iomuxc 22 137 1>,
+ <&iomuxc 23 136 1>,
+ <&iomuxc 24 135 1>,
+ <&iomuxc 25 134 1>,
+ <&iomuxc 26 142 3>,
+ <&iomuxc 29 146 3>;
};
&lsio_gpio4 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ gpio-ranges = <&iomuxc 0 149 3>,
+ <&iomuxc 3 153 4>,
+ <&iomuxc 7 158 6>,
+ <&iomuxc 13 165 6>,
+ <&iomuxc 19 172 8>,
+ <&iomuxc 27 198 5>;
};
&lsio_gpio5 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ gpio-ranges = <&iomuxc 0 203 1>,
+ <&iomuxc 1 205 2>,
+ <&iomuxc 3 210 11>,
+ <&iomuxc 14 223 3>,
+ <&iomuxc 17 227 2>,
+ <&iomuxc 19 230 5>,
+ <&iomuxc 24 236 6>,
+ <&iomuxc 30 243 2>;
};
&lsio_gpio6 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ gpio-ranges = <&iomuxc 0 245 10>,
+ <&iomuxc 10 256 12>;
};
&lsio_gpio7 {
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index c9c2b6536233..41ce8336f29e 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -136,6 +136,7 @@
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
@@ -144,6 +145,7 @@
A72_L2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi
index a08e70fb7c7a..7c334b93db3b 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi
@@ -3,7 +3,7 @@
* Copyright 2019 Toradex
*/
-#include "dt-bindings/input/linux-event-codes.h"
+#include <dt-bindings/input/linux-event-codes.h>
/ {
aliases {
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
index 8e2152c6eb88..8f722b1dd078 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
@@ -6,26 +6,51 @@
&lsio_gpio0 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+ gpio-ranges = <&iomuxc 1 56 12>,
+ <&iomuxc 13 69 4>,
+ <&iomuxc 19 75 4>,
+ <&iomuxc 24 80 1>,
+ <&iomuxc 25 82 7>;
};
&lsio_gpio1 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+ gpio-ranges = <&iomuxc 0 89 9>,
+ <&iomuxc 9 99 16>,
+ <&iomuxc 25 116 7>;
};
&lsio_gpio2 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+ gpio-ranges = <&iomuxc 0 123 1>,
+ <&iomuxc 1 126 2>,
+ <&iomuxc 3 129 1>;
};
&lsio_gpio3 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+ gpio-ranges = <&iomuxc 0 146 4>,
+ <&iomuxc 4 151 13>,
+ <&iomuxc 17 165 8>;
};
&lsio_gpio4 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+ gpio-ranges = <&iomuxc 0 0 3>,
+ <&iomuxc 3 4 4>,
+ <&iomuxc 7 9 6>,
+ <&iomuxc 13 16 6>,
+ <&iomuxc 19 23 2>,
+ <&iomuxc 21 26 2>,
+ <&iomuxc 23 30 6>,
+ <&iomuxc 29 37 3>;
};
&lsio_gpio5 {
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
+ gpio-ranges = <&iomuxc 0 40 3>,
+ <&iomuxc 3 44 6>,
+ <&iomuxc 9 51 3>;
};
&lsio_gpio6 {
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index f4ea18bb95ab..85c0b1d2bac5 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -127,6 +127,7 @@
A35_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 06ce5f19aa8a..32193a43ff49 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -51,6 +51,7 @@
A35_L2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
index 0247866fc86b..5d79663b3b84 100644
--- a/arch/arm64/boot/dts/freescale/imx93.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
@@ -17,6 +17,10 @@
#size-cells = <2>;
aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
@@ -135,6 +139,7 @@
compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
reg = <0x44230000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_MU1_B_GATE>;
#mbox-cells = <2>;
status = "disabled";
};
@@ -145,6 +150,15 @@
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc_24m>;
clock-names = "per";
+ nxp,no-divider;
+ };
+
+ tpm2: pwm@44320000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x44320000 0x10000>;
+ clocks = <&clk IMX93_CLK_TPM2_GATE>;
+ #pwm-cells = <3>;
+ status = "disabled";
};
lpi2c1: i2c@44340000 {
@@ -270,10 +284,35 @@
compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
reg = <0x42440000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_MU2_B_GATE>;
#mbox-cells = <2>;
status = "disabled";
};
+ tpm4: pwm@424f0000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x424f0000 0x10000>;
+ clocks = <&clk IMX93_CLK_TPM4_GATE>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ tpm5: pwm@42500000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x42500000 0x10000>;
+ clocks = <&clk IMX93_CLK_TPM5_GATE>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ tpm6: pwm@42510000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x42510000 0x10000>;
+ clocks = <&clk IMX93_CLK_TPM6_GATE>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
lpi2c3: i2c@42530000 {
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x42530000 0x10000>;
@@ -294,6 +333,30 @@
status = "disabled";
};
+ lpspi3: spi@42550000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+ reg = <0x42550000 0x10000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPSPI3_GATE>,
+ <&clk IMX93_CLK_BUS_WAKEUP>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpspi4: spi@42560000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+ reg = <0x42560000 0x10000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPSPI4_GATE>,
+ <&clk IMX93_CLK_BUS_WAKEUP>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
lpuart3: serial@42570000 {
compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x42570000 0x1000>;
@@ -388,6 +451,54 @@
status = "disabled";
};
+ lpspi5: spi@426f0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+ reg = <0x426f0000 0x10000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPSPI5_GATE>,
+ <&clk IMX93_CLK_BUS_WAKEUP>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpspi6: spi@42700000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+ reg = <0x42700000 0x10000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPSPI6_GATE>,
+ <&clk IMX93_CLK_BUS_WAKEUP>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpspi7: spi@42710000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+ reg = <0x42710000 0x10000>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPSPI7_GATE>,
+ <&clk IMX93_CLK_BUS_WAKEUP>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpspi8: spi@42720000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+ reg = <0x42720000 0x10000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPSPI8_GATE>,
+ <&clk IMX93_CLK_BUS_WAKEUP>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
};
aips3: bus@42800000 {
diff --git a/arch/arm64/boot/dts/freescale/mba8mx.dtsi b/arch/arm64/boot/dts/freescale/mba8mx.dtsi
index 104bdd4e437a..daa37adeff3b 100644
--- a/arch/arm64/boot/dts/freescale/mba8mx.dtsi
+++ b/arch/arm64/boot/dts/freescale/mba8mx.dtsi
@@ -215,6 +215,7 @@
compatible = "nxp,se97b", "atmel,24c02";
reg = <0x57>;
pagesize = <16>;
+ vcc-supply = <&reg_vcc_3v3>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 824d401e7a2c..d8c82da88ca0 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -52,10 +52,12 @@
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi
index ba0b5305d481..3e306218d533 100644
--- a/arch/arm64/boot/dts/freescale/s32v234.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi
@@ -61,10 +61,12 @@
cluster0_l2_cache: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2_cache: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 8343d0cedde3..a57f35eb5ef6 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -203,10 +203,12 @@
A53_L2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
A73_L2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index ae0a7cfeeb47..f6d3202b0d1a 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -186,10 +186,12 @@
CLUSTER0_L2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
CLUSTER1_L2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index 7b2abd10d3d6..5b2b1bfd0d2a 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -211,18 +211,22 @@
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 2f8b03b0d365..291c2ee38288 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -211,18 +211,22 @@
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index 1a16662f8867..b8746fb959b5 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -842,66 +842,82 @@
cluster0_l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
+ cache-level = <2>;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
+ cache-level = <2>;
};
cluster4_l2: l2-cache4 {
compatible = "cache";
+ cache-level = <2>;
};
cluster5_l2: l2-cache5 {
compatible = "cache";
+ cache-level = <2>;
};
cluster6_l2: l2-cache6 {
compatible = "cache";
+ cache-level = <2>;
};
cluster7_l2: l2-cache7 {
compatible = "cache";
+ cache-level = <2>;
};
cluster8_l2: l2-cache8 {
compatible = "cache";
+ cache-level = <2>;
};
cluster9_l2: l2-cache9 {
compatible = "cache";
+ cache-level = <2>;
};
cluster10_l2: l2-cache10 {
compatible = "cache";
+ cache-level = <2>;
};
cluster11_l2: l2-cache11 {
compatible = "cache";
+ cache-level = <2>;
};
cluster12_l2: l2-cache12 {
compatible = "cache";
+ cache-level = <2>;
};
cluster13_l2: l2-cache13 {
compatible = "cache";
+ cache-level = <2>;
};
cluster14_l2: l2-cache14 {
compatible = "cache";
+ cache-level = <2>;
};
cluster15_l2: l2-cache15 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index 7bbec8aafa62..849b46dd8098 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -313,6 +313,7 @@
<&clkmgr AGILEX_SDMMC_CLK>;
clock-names = "biu", "ciu";
iommus = <&smmu 5>;
+ altr,sysmgr-syscon = <&sysmgr 0x28 4>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
index 26cd3c121757..07c3f8876613 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
@@ -83,6 +83,7 @@
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
+ clk-phase-sd-hs = <0>, <135>;
};
&osc1 {
diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
index 62c66e52b656..08c088571270 100644
--- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
@@ -74,6 +74,7 @@
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
+ clk-phase-sd-hs = <0>, <135>;
};
&osc1 {
diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
index 44ed6f963b75..7308f7b6b22c 100644
--- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
@@ -49,6 +49,7 @@
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
index ada164d423f3..cd0988317623 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
@@ -125,9 +125,12 @@
/delete-property/ mrvl,i2c-fast-mode;
status = "okay";
+ /* MCP7940MT-I/MNY RTC */
rtc@6f {
compatible = "microchip,mcp7940x";
reg = <0x6f>;
+ interrupt-parent = <&gpiosb>;
+ interrupts = <5 0>; /* GPIO2_5 */
};
};
@@ -136,6 +139,7 @@
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
status = "okay";
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
+ slot-power-limit-milliwatt = <10000>;
/*
* U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
* contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index df152c72276b..e300145ad1a6 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -35,6 +35,11 @@
reg = <0 0x4000000 0 0x200000>;
no-map;
};
+
+ tee@4400000 {
+ reg = <0 0x4400000 0 0x1000000>;
+ no-map;
+ };
};
cpus {
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
index fcab5173fe67..990f70303fe6 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
@@ -51,6 +51,7 @@
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
index 3db427122f9e..a7b8e001cc9c 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
@@ -81,6 +81,7 @@
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
l2_1: l2-cache1 {
@@ -88,6 +89,7 @@
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
index 68782f161f12..7740098fd108 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
@@ -81,6 +81,7 @@
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
l2_1: l2-cache1 {
@@ -88,6 +89,7 @@
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
index a06a0a889c43..4e6d29ad32eb 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
@@ -41,6 +41,11 @@
reg = <0x0 0x4000000 0x0 0x200000>;
no-map;
};
+
+ tee@4400000 {
+ reg = <0 0x4400000 0 0x1000000>;
+ no-map;
+ };
};
AP_NAME {
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 0ec90cb3ef28..813e735c5b96 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-sony-xperia-m5.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
index 9b1af9c80130..d31a194124c9 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -26,14 +26,14 @@
stdout-path = "serial0:921600n8";
};
- cpus_fixed_vproc0: fixedregulator@0 {
+ cpus_fixed_vproc0: regulator-vproc-buck0 {
compatible = "regulator-fixed";
regulator-name = "vproc_buck0";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
- cpus_fixed_vproc1: fixedregulator@1 {
+ cpus_fixed_vproc1: regulator-vproc-buck1 {
compatible = "regulator-fixed";
regulator-name = "vproc_buck1";
regulator-min-microvolt = <1000000>;
@@ -50,7 +50,7 @@
id-gpio = <&pio 14 GPIO_ACTIVE_HIGH>;
};
- usb_p0_vbus: regulator@2 {
+ usb_p0_vbus: regulator-usb-p0-vbus {
compatible = "regulator-fixed";
regulator-name = "p0_vbus";
regulator-min-microvolt = <5000000>;
@@ -59,7 +59,7 @@
enable-active-high;
};
- usb_p1_vbus: regulator@3 {
+ usb_p1_vbus: regulator-usb-p1-vbus {
compatible = "regulator-fixed";
regulator-name = "p1_vbus";
regulator-min-microvolt = <5000000>;
@@ -68,7 +68,7 @@
enable-active-high;
};
- usb_p2_vbus: regulator@4 {
+ usb_p2_vbus: regulator-usb-p2-vbus {
compatible = "regulator-fixed";
regulator-name = "p2_vbus";
regulator-min-microvolt = <5000000>;
@@ -77,7 +77,7 @@
enable-active-high;
};
- usb_p3_vbus: regulator@5 {
+ usb_p3_vbus: regulator-usb-p3-vbus {
compatible = "regulator-fixed";
regulator-name = "p3_vbus";
regulator-min-microvolt = <5000000>;
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index e6d7453e56e0..92212cddd37e 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -160,70 +160,70 @@
#clock-cells = <0>;
};
- clk26m: oscillator@0 {
+ clk26m: oscillator-26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
- clk32k: oscillator@1 {
+ clk32k: oscillator-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "clk32k";
};
- clkfpc: oscillator@2 {
+ clkfpc: oscillator-50m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "clkfpc";
};
- clkaud_ext_i_0: oscillator@3 {
+ clkaud_ext_i_0: oscillator-aud0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <6500000>;
clock-output-names = "clkaud_ext_i_0";
};
- clkaud_ext_i_1: oscillator@4 {
+ clkaud_ext_i_1: oscillator-aud1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <196608000>;
clock-output-names = "clkaud_ext_i_1";
};
- clkaud_ext_i_2: oscillator@5 {
+ clkaud_ext_i_2: oscillator-aud2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <180633600>;
clock-output-names = "clkaud_ext_i_2";
};
- clki2si0_mck_i: oscillator@6 {
+ clki2si0_mck_i: oscillator-i2s0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <30000000>;
clock-output-names = "clki2si0_mck_i";
};
- clki2si1_mck_i: oscillator@7 {
+ clki2si1_mck_i: oscillator-i2s1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <30000000>;
clock-output-names = "clki2si1_mck_i";
};
- clki2si2_mck_i: oscillator@8 {
+ clki2si2_mck_i: oscillator-i2s2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <30000000>;
clock-output-names = "clki2si2_mck_i";
};
- clktdmin_mclk_i: oscillator@9 {
+ clktdmin_mclk_i: oscillator-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <30000000>;
@@ -266,7 +266,7 @@
reg = <0 0x10005000 0 0x1000>;
};
- pio: pinctrl@10005000 {
+ pio: pinctrl@1000b000 {
compatible = "mediatek,mt2712-pinctrl";
reg = <0 0x1000b000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a>;
@@ -766,9 +766,9 @@
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_MSDC30_0>,
<&pericfg CLK_PERI_MSDC50_0_HCLK_EN>,
- <&pericfg CLK_PERI_MSDC30_0_QTR_EN>,
- <&pericfg CLK_PERI_MSDC50_0_EN>;
- clock-names = "source", "hclk", "bus_clk", "source_cg";
+ <&pericfg CLK_PERI_MSDC50_0_EN>,
+ <&pericfg CLK_PERI_MSDC30_0_QTR_EN>;
+ clock-names = "source", "hclk", "source_cg", "bus_clk";
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
index 9bdf5145966c..5c579e88e749 100644
--- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -88,14 +88,14 @@
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>;
};
- clk26m: oscillator@0 {
+ clk26m: oscillator-26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
- clk32k: oscillator@1 {
+ clk32k: oscillator-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
@@ -117,7 +117,7 @@
compatible = "simple-bus";
ranges;
- gic: interrupt-controller@0c000000 {
+ gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
interrupt-parent = <&gic>;
@@ -138,7 +138,7 @@
};
- sysirq: intpol-controller@0c53a650 {
+ sysirq: intpol-controller@c53a650 {
compatible = "mediatek,mt6779-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
@@ -160,7 +160,7 @@
};
pio: pinctrl@10005000 {
- compatible = "mediatek,mt6779-pinctrl", "syscon";
+ compatible = "mediatek,mt6779-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x11c20000 0 0x1000>,
<0 0x11d10000 0 0x1000>,
diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
new file mode 100644
index 000000000000..d3415527d389
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022, Collabora Ltd
+ * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+/dts-v1/;
+#include "mt6795.dtsi"
+
+/ {
+ model = "Sony Xperia M5";
+ compatible = "sony,xperia-m5", "mediatek,mt6795";
+ chassis-type = "handset";
+
+ aliases {
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x1e800000>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 128 KiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@43000000 {
+ reg = <0 0x43000000 0 0x30000>;
+ no-map;
+ };
+
+ /* preloader and bootloader regions cannot be touched */
+ preloader-region@44800000 {
+ reg = <0 0x44800000 0 0x100000>;
+ no-map;
+ };
+
+ bootloader-region@46000000 {
+ reg = <0 0x46000000 0 0x400000>;
+ no-map;
+ };
+ };
+};
+
+&pio {
+ uart0_pins: uart0-pins {
+ pins-rx {
+ pinmux = <PINMUX_GPIO113__FUNC_URXD0>;
+ bias-pull-up;
+ input-enable;
+ };
+ pins-tx {
+ pinmux = <PINMUX_GPIO114__FUNC_UTXD0>;
+ output-high;
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ pins-rx {
+ pinmux = <PINMUX_GPIO31__FUNC_URXD2>;
+ bias-pull-up;
+ input-enable;
+ };
+ pins-tx {
+ pinmux = <PINMUX_GPIO32__FUNC_UTXD2>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+};
+
+&uart2 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 46f0e54be766..bb575837e4ce 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -6,7 +6,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mediatek,mt6795-clk.h>
#include <dt-bindings/pinctrl/mt6795-pinfunc.h>
+#include <dt-bindings/reset/mediatek,mt6795-resets.h>
/ {
compatible = "mediatek,mt6795";
@@ -192,6 +194,26 @@
compatible = "simple-bus";
ranges;
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt6795-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt6795-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt6795-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
pio: pinctrl@10005000 {
compatible = "mediatek,mt6795-pinctrl";
reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
@@ -292,7 +314,10 @@
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&clk26m>;
+ clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 0>, <&apdma 1>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -301,16 +326,48 @@
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&clk26m>;
+ clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 2>, <&apdma 3>;
+ dma-names = "tx", "rx";
status = "disabled";
};
+ apdma: dma-controller@11000380 {
+ compatible = "mediatek,mt6795-uart-dma",
+ "mediatek,mt6577-uart-dma";
+ reg = <0 0x11000380 0 0x60>,
+ <0 0x11000400 0 0x60>,
+ <0 0x11000480 0 0x60>,
+ <0 0x11000500 0 0x60>,
+ <0 0x11000580 0 0x60>,
+ <0 0x11000600 0 0x60>,
+ <0 0x11000680 0 0x60>,
+ <0 0x11000700 0 0x60>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
+ dma-requests = <8>;
+ clocks = <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "apdma";
+ mediatek,dma-33bits;
+ #dma-cells = <1>;
+ };
+
uart2: serial@11004000 {
compatible = "mediatek,mt6795-uart",
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&clk26m>;
+ clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 4>, <&apdma 5>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -319,7 +376,51 @@
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&clk26m>;
+ clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 6>, <&apdma 7>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt6795-mmc";
+ reg = <0 0x11230000 0 0x1000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_0>,
+ <&topckgen CLK_TOP_MSDC50_0_H_SEL>,
+ <&topckgen CLK_TOP_MSDC50_0_SEL>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt6795-mmc";
+ reg = <0 0x11240000 0 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_1>,
+ <&topckgen CLK_TOP_AXI_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+
+ mmc2: mmc@11250000 {
+ compatible = "mediatek,mt6795-mmc";
+ reg = <0 0x11250000 0 0x1000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_2>,
+ <&topckgen CLK_TOP_AXI_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+
+ mmc3: mmc@11260000 {
+ compatible = "mediatek,mt6795-mmc";
+ reg = <0 0x11260000 0 0x1000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_3>,
+ <&topckgen CLK_TOP_AXI_SEL>;
+ clock-names = "source", "hclk";
status = "disabled";
};
};
diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
index 15616231022a..c3677d77e0a4 100644
--- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
@@ -95,7 +95,7 @@
};
};
- clk26m: oscillator@0 {
+ clk26m: oscillator-26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
index d3f9eab2b784..af3fe61e4093 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -235,7 +235,6 @@
bus-width = <4>;
max-frequency = <50000000>;
cap-sd-highspeed;
- r_smpl = <1>;
cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
index 36722cabe626..b74e774c6eba 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -208,7 +208,6 @@
bus-width = <4>;
max-frequency = <50000000>;
cap-sd-highspeed;
- r_smpl = <1>;
cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
index afe37b702eef..9b83925893b7 100644
--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
@@ -9,7 +9,7 @@
/ {
model = "MediaTek MT7986a RFB";
- compatible = "mediatek,mt7986a-rfb";
+ compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
aliases {
serial0 = &uart0;
@@ -25,6 +25,10 @@
};
};
+&crypto {
+ status = "okay";
+};
+
&eth {
status = "okay";
@@ -54,6 +58,88 @@
};
};
+&pio {
+ spi_flash_pins: spi-flash-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ };
+
+ spic_pins: spic-pins {
+ mux {
+ function = "spi";
+ groups = "spi1_2";
+ };
+ };
+
+ uart1_pins: uart1-pins {
+ mux {
+ function = "uart";
+ groups = "uart1";
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ mux {
+ function = "uart";
+ groups = "uart2";
+ };
+ };
+
+ wf_2g_5g_pins: wf-2g-5g-pins {
+ mux {
+ function = "wifi";
+ groups = "wf_2g", "wf_5g";
+ };
+ conf {
+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+ "WF1_TOP_CLK", "WF1_TOP_DATA";
+ drive-strength = <4>;
+ };
+ };
+
+ wf_dbdc_pins: wf-dbdc-pins {
+ mux {
+ function = "wifi";
+ groups = "wf_dbdc";
+ };
+ conf {
+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+ "WF0_TOP_CLK", "WF0_TOP_DATA";
+ drive-strength = <4>;
+ };
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_flash_pins>;
+ cs-gpios = <0>, <0>;
+ status = "okay";
+ spi_nand: spi_nand@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ spi-tx-buswidth = <4>;
+ spi-rx-buswidth = <4>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spic_pins>;
+ cs-gpios = <0>, <0>;
+ status = "okay";
+};
+
&switch {
ports {
#address-cells = <1>;
@@ -121,50 +207,3 @@
pinctrl-0 = <&wf_2g_5g_pins>;
pinctrl-1 = <&wf_dbdc_pins>;
};
-
-&pio {
- uart1_pins: uart1-pins {
- mux {
- function = "uart";
- groups = "uart1";
- };
- };
-
- uart2_pins: uart2-pins {
- mux {
- function = "uart";
- groups = "uart2";
- };
- };
-
- wf_2g_5g_pins: wf-2g-5g-pins {
- mux {
- function = "wifi";
- groups = "wf_2g", "wf_5g";
- };
- conf {
- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
- "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
- "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
- "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
- "WF1_TOP_CLK", "WF1_TOP_DATA";
- drive-strength = <4>;
- };
- };
-
- wf_dbdc_pins: wf-dbdc-pins {
- mux {
- function = "wifi";
- groups = "wf_dbdc";
- };
- conf {
- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
- "WF0_TOP_CLK", "WF0_TOP_DATA";
- drive-strength = <4>;
- };
- };
-};
diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
index 72e0d9722e07..ed703025a7cc 100644
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -10,11 +10,12 @@
#include <dt-bindings/reset/mt7986-resets.h>
/ {
+ compatible = "mediatek,mt7986a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
- clk40m: oscillator@0 {
+ clk40m: oscillator-40m {
compatible = "fixed-clock";
clock-frequency = <40000000>;
#clock-cells = <0>;
@@ -112,6 +113,12 @@
#clock-cells = <1>;
};
+ wed_pcie: wed-pcie@10003000 {
+ compatible = "mediatek,mt7986-wed-pcie",
+ "syscon";
+ reg = <0 0x10003000 0 0x10>;
+ };
+
topckgen: topckgen@1001b000 {
compatible = "mediatek,mt7986-topckgen", "syscon";
reg = <0 0x1001B000 0 0x1000>;
@@ -168,7 +175,7 @@
#clock-cells = <1>;
};
- trng: trng@1020f000 {
+ trng: rng@1020f000 {
compatible = "mediatek,mt7986-rng",
"mediatek,mt7623-rng";
reg = <0 0x1020f000 0 0x100>;
@@ -177,6 +184,21 @@
status = "disabled";
};
+ crypto: crypto@10320000 {
+ compatible = "inside-secure,safexcel-eip97";
+ reg = <0 0x10320000 0 0x40000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ring0", "ring1", "ring2", "ring3";
+ clocks = <&infracfg CLK_INFRA_EIP97_CK>;
+ clock-names = "infra_eip97_ck";
+ assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt7986-uart",
"mediatek,mt6577-uart";
@@ -218,6 +240,48 @@
status = "disabled";
};
+ i2c0: i2c@11008000 {
+ compatible = "mediatek,mt7986-i2c";
+ reg = <0 0x11008000 0 0x90>,
+ <0 0x10217080 0 0x80>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ clock-div = <5>;
+ clocks = <&infracfg CLK_INFRA_I2C0_CK>,
+ <&infracfg CLK_INFRA_AP_DMA_CK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi0: spi@1100a000 {
+ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x1100a000 0 0x100>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI0_CK>,
+ <&infracfg CLK_INFRA_SPI0_HCK_CK>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
+ status = "disabled";
+ };
+
+ spi1: spi@1100b000 {
+ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x1100b000 0 0x100>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
+ <&topckgen CLK_TOP_SPIM_MST_SEL>,
+ <&infracfg CLK_INFRA_SPI1_CK>,
+ <&infracfg CLK_INFRA_SPI1_HCK_CK>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
+ status = "disabled";
+ };
+
ethsys: syscon@15000000 {
#address-cells = <1>;
#size-cells = <1>;
@@ -228,12 +292,6 @@
#reset-cells = <1>;
};
- wed_pcie: wed-pcie@10003000 {
- compatible = "mediatek,mt7986-wed-pcie",
- "syscon";
- reg = <0 0x10003000 0 0x10>;
- };
-
wed0: wed@15010000 {
compatible = "mediatek,mt7986-wed",
"syscon";
diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
index 3443013b5971..243760cd3011 100644
--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
@@ -9,7 +9,7 @@
/ {
model = "MediaTek MT7986b RFB";
- compatible = "mediatek,mt7986b-rfb";
+ compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
aliases {
serial0 = &uart0;
@@ -25,7 +25,7 @@
};
};
-&uart0 {
+&crypto {
status = "okay";
};
@@ -99,14 +99,21 @@
};
};
-&wifi {
- status = "okay";
- pinctrl-names = "default", "dbdc";
- pinctrl-0 = <&wf_2g_5g_pins>;
- pinctrl-1 = <&wf_dbdc_pins>;
-};
-
&pio {
+ spi_flash_pins: spi-flash-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ };
+
+ spic_pins: spic-pins {
+ mux {
+ function = "spi";
+ groups = "spi1_2";
+ };
+ };
+
wf_2g_5g_pins: wf-2g-5g-pins {
mux {
function = "wifi";
@@ -138,3 +145,35 @@
};
};
};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_flash_pins>;
+ cs-gpios = <0>, <0>;
+ status = "okay";
+ spi_nand: spi_nand@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ spi-tx-buswidth = <4>;
+ spi-rx-buswidth = <4>;
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spic_pins>;
+ cs-gpios = <0>, <0>;
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&wifi {
+ status = "okay";
+ pinctrl-names = "default", "dbdc";
+ pinctrl-0 = <&wf_2g_5g_pins>;
+ pinctrl-1 = <&wf_dbdc_pins>;
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
index 23923b9f8944..db5189664c29 100644
--- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
@@ -5,6 +5,9 @@
*/
#include "mt7986a.dtsi"
+/ {
+ compatible = "mediatek,mt7986b";
+};
&pio {
compatible = "mediatek,mt7986b-pinctrl";
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
index b4b86bb1f1a7..7fc4c592a908 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
@@ -221,11 +221,6 @@
};
};
-&afe {
- i2s3-share = "I2S2";
- i2s0-share = "I2S5";
-};
-
&auxadc {
status = "okay";
};
@@ -378,7 +373,6 @@
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
max-frequency = <200000000>;
- drv-type = <2>;
cap-sd-highspeed;
sd-uhs-sdr50;
sd-uhs-sdr104;
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 64693c17af9e..c326aeb33a10 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -198,16 +198,19 @@
l2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 6b20376191a7..424fc89cc6f7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -169,16 +169,19 @@
l2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
idle-states {
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 9b62e161db26..560103e29017 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -120,6 +120,78 @@
};
};
+&dp_intf0 {
+ status = "okay";
+
+ port {
+ dp_intf0_out: endpoint {
+ remote-endpoint = <&edp_in>;
+ };
+ };
+};
+
+&dp_intf1 {
+ status = "okay";
+
+ port {
+ dp_intf1_out: endpoint {
+ remote-endpoint = <&dptx_in>;
+ };
+ };
+};
+
+&edp_tx {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&edptx_pins_default>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ edp_in: endpoint {
+ remote-endpoint = <&dp_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ edp_out: endpoint {
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+};
+
+&dp_tx {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&dptx_pin>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dptx_in: endpoint {
+ remote-endpoint = <&dp_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dptx_out: endpoint {
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+};
+
&i2c0 {
status = "okay";
@@ -479,6 +551,20 @@
};
};
+ edptx_pins_default: edptx-default-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO7__FUNC_EDP_TX_HPD>;
+ bias-pull-up;
+ };
+ };
+
+ dptx_pin: dptx-default-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>;
+ bias-pull-up;
+ };
+ };
+
i2c0_pins: i2c0-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 905d1a90b406..5d31536f4c48 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -13,6 +13,7 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/power/mt8195-power.h>
+#include <dt-bindings/reset/mt8195-resets.h>
/ {
compatible = "mediatek,mt8195";
@@ -36,7 +37,7 @@
enable-method = "psci";
performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
- capacity-dmips-mhz = <578>;
+ capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
@@ -49,7 +50,7 @@
enable-method = "psci";
performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
- capacity-dmips-mhz = <578>;
+ capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
@@ -62,7 +63,7 @@
enable-method = "psci";
performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
- capacity-dmips-mhz = <578>;
+ capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
@@ -75,7 +76,7 @@
enable-method = "psci";
performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
- capacity-dmips-mhz = <578>;
+ capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
@@ -213,16 +214,19 @@
l2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
+ cache-level = <2>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
+ cache-level = <3>;
};
};
@@ -1182,6 +1186,110 @@
status = "disabled";
};
+ pcie0: pcie@112f0000 {
+ compatible = "mediatek,mt8195-pcie",
+ "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0 0x112f0000 0 0x4000>;
+ reg-names = "pcie-mac";
+ interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0x20000000
+ 0x0 0x20000000 0 0x200000>,
+ <0x82000000 0 0x20200000
+ 0x0 0x20200000 0 0x3e00000>;
+
+ iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
+ iommu-map-mask = <0x0>;
+
+ clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
+ <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
+ <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
+ <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
+ <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
+ <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
+ clock-names = "pl_250m", "tl_26m", "tl_96m",
+ "tl_32k", "peri_26m", "peri_mem";
+ assigned-clocks = <&topckgen CLK_TOP_TL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
+
+ phys = <&pciephy>;
+ phy-names = "pcie-phy";
+
+ power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
+
+ resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>;
+ reset-names = "mac";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ status = "disabled";
+
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pcie1: pcie@112f8000 {
+ compatible = "mediatek,mt8195-pcie",
+ "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0 0x112f8000 0 0x4000>;
+ reg-names = "pcie-mac";
+ interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0x24000000
+ 0x0 0x24000000 0 0x200000>,
+ <0x82000000 0 0x24200000
+ 0x0 0x24200000 0 0x3e00000>;
+
+ iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
+ iommu-map-mask = <0x0>;
+
+ clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
+ <&clk26m>,
+ <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
+ <&clk26m>,
+ <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
+ /* Designer has connect pcie1 with peri_mem_p0 clock */
+ <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
+ clock-names = "pl_250m", "tl_26m", "tl_96m",
+ "tl_32k", "peri_26m", "peri_mem";
+ assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
+
+ phys = <&u3port1 PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
+
+ resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>;
+ reset-names = "mac";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ status = "disabled";
+
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
nor_flash: spi@1132c000 {
compatible = "mediatek,mt8195-nor",
"mediatek,mt8173-nor";
@@ -1241,6 +1349,37 @@
reg = <0x189 0x2>;
bits = <7 5>;
};
+ pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
+ reg = <0x190 0x1>;
+ bits = <0 4>;
+ };
+ pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
+ reg = <0x190 0x1>;
+ bits = <4 4>;
+ };
+ pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
+ reg = <0x191 0x1>;
+ bits = <0 4>;
+ };
+ pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
+ reg = <0x191 0x1>;
+ bits = <4 4>;
+ };
+ pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
+ reg = <0x192 0x1>;
+ bits = <0 4>;
+ };
+ pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
+ reg = <0x192 0x1>;
+ bits = <4 4>;
+ };
+ pciephy_glb_intr: pciephy-glb-intr@193 {
+ reg = <0x193 0x1>;
+ bits = <0 4>;
+ };
+ dp_calibration: dp-data@1ac {
+ reg = <0x1ac 0x10>;
+ };
};
u3phy2: t-phy@11c40000 {
@@ -1461,6 +1600,23 @@
};
};
+ pciephy: phy@11e80000 {
+ compatible = "mediatek,mt8195-pcie-phy";
+ reg = <0 0x11e80000 0 0x10000>;
+ reg-names = "sif";
+ nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
+ <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>,
+ <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>,
+ <&pciephy_rx_ln1>;
+ nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
+ "tx_ln0_nmos", "rx_ln0",
+ "tx_ln1_pmos", "tx_ln1_nmos",
+ "rx_ln1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
ufsphy: ufs-phy@11fa0000 {
compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
reg = <0 0x11fa0000 0 0xc000>;
@@ -1959,6 +2115,30 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
};
+ venc: video-codec@1a020000 {
+ compatible = "mediatek,mt8195-vcodec-enc";
+ reg = <0 0x1a020000 0 0x10000>;
+ iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>,
+ <&iommu_vdo M4U_PORT_L19_VENC_REC>,
+ <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>,
+ <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>,
+ <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>,
+ <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>,
+ <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>,
+ <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>,
+ <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>;
+ interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,scp = <&scp>;
+ clocks = <&vencsys CLK_VENC_VENC>;
+ clock-names = "venc_sel";
+ assigned-clocks = <&topckgen CLK_TOP_VENC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+ };
+
vencsys_core1: clock-controller@1b000000 {
compatible = "mediatek,mt8195-vencsys_core1";
reg = <0 0x1b000000 0 0x1000>;
@@ -2067,6 +2247,17 @@
mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
};
+ dp_intf0: dp-intf@1c015000 {
+ compatible = "mediatek,mt8195-dp-intf";
+ reg = <0 0x1c015000 0 0x1000>;
+ interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys0 CLK_VDO0_DP_INTF0>,
+ <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
+ <&apmixedsys CLK_APMIXED_TVDPLL1>;
+ clock-names = "engine", "pixel", "pll";
+ status = "disabled";
+ };
+
mutex: mutex@1c016000 {
compatible = "mediatek,mt8195-disp-mutex";
reg = <0 0x1c016000 0 0x1000>;
@@ -2155,5 +2346,39 @@
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
};
+
+ dp_intf1: dp-intf@1c113000 {
+ compatible = "mediatek,mt8195-dp-intf";
+ reg = <0 0x1c113000 0 0x1000>;
+ interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
+ <&vdosys1 CLK_VDO1_DPINTF>,
+ <&apmixedsys CLK_APMIXED_TVDPLL2>;
+ clock-names = "engine", "pixel", "pll";
+ status = "disabled";
+ };
+
+ edp_tx: edp-tx@1c500000 {
+ compatible = "mediatek,mt8195-edp-tx";
+ reg = <0 0x1c500000 0 0x8000>;
+ nvmem-cells = <&dp_calibration>;
+ nvmem-cell-names = "dp_calibration_data";
+ power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
+ interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
+ max-linkrate-mhz = <8100>;
+ status = "disabled";
+ };
+
+ dp_tx: dp-tx@1c600000 {
+ compatible = "mediatek,mt8195-dp-tx";
+ reg = <0 0x1c600000 0 0x8000>;
+ nvmem-cells = <&dp_calibration>;
+ nvmem-cell-names = "dp_calibration_data";
+ power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
+ interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
+ max-linkrate-mhz = <8100>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
index 8ee1529683a3..ec8dfb3d1c6d 100644
--- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
+++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
@@ -17,7 +17,7 @@
};
firmware {
- optee: optee@4fd00000 {
+ optee: optee {
compatible = "linaro,optee-tz";
method = "smc";
};
@@ -209,7 +209,7 @@
};
};
- i2c0_pins_a: i2c0@0 {
+ i2c0_pins_a: i2c0 {
pins1 {
pinmux = <MT8516_PIN_58_SDA0__FUNC_SDA0_0>,
<MT8516_PIN_59_SCL0__FUNC_SCL0_0>;
@@ -217,7 +217,7 @@
};
};
- i2c2_pins_a: i2c2@0 {
+ i2c2_pins_a: i2c2 {
pins1 {
pinmux = <MT8516_PIN_60_SDA2__FUNC_SDA2_0>,
<MT8516_PIN_61_SCL2__FUNC_SCL2_0>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
index d461da0b8049..3e8dee85d55f 100644
--- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts
@@ -62,7 +62,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinmux_default>;
- pinmux_default: pinmux@0 {
+ pinmux_default: pinmux {
dap_mclk1_pw4 {
nvidia,pins = "dap_mclk1_pw4";
nvidia,function = "extperiph1";
diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
index 3673f79adf1a..858fc01cecb6 100644
--- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
@@ -393,7 +393,6 @@
reg = <0x0 0x7000a000 0x0 0x100>;
#pwm-cells = <2>;
clocks = <&tegra_car TEGRA124_CLK_PWM>;
- clock-names = "pwm";
resets = <&tegra_car 17>;
reset-names = "pwm";
status = "disabled";
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 6602fe421ee8..b3f1494c02c1 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -78,7 +78,8 @@
reg = <0x0 0x2600000 0x0 0x210000>;
resets = <&bpmp TEGRA186_RESET_GPCDMA>;
reset-names = "gpcdma";
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
@@ -112,6 +113,7 @@
#dma-cells = <1>;
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
+ dma-channel-mask = <0xfffffffe>;
status = "okay";
};
@@ -790,7 +792,6 @@
compatible = "nvidia,tegra186-pwm";
reg = <0x0 0x3280000 0x0 0x10000>;
clocks = <&bpmp TEGRA186_CLK_PWM1>;
- clock-names = "pwm";
resets = <&bpmp TEGRA186_RESET_PWM1>;
reset-names = "pwm";
status = "disabled";
@@ -801,7 +802,6 @@
compatible = "nvidia,tegra186-pwm";
reg = <0x0 0x3290000 0x0 0x10000>;
clocks = <&bpmp TEGRA186_CLK_PWM2>;
- clock-names = "pwm";
resets = <&bpmp TEGRA186_RESET_PWM2>;
reset-names = "pwm";
status = "disabled";
@@ -812,7 +812,6 @@
compatible = "nvidia,tegra186-pwm";
reg = <0x0 0x32a0000 0x0 0x10000>;
clocks = <&bpmp TEGRA186_CLK_PWM3>;
- clock-names = "pwm";
resets = <&bpmp TEGRA186_RESET_PWM3>;
reset-names = "pwm";
status = "disabled";
@@ -823,7 +822,6 @@
compatible = "nvidia,tegra186-pwm";
reg = <0x0 0x32c0000 0x0 0x10000>;
clocks = <&bpmp TEGRA186_CLK_PWM5>;
- clock-names = "pwm";
resets = <&bpmp TEGRA186_RESET_PWM5>;
reset-names = "pwm";
status = "disabled";
@@ -834,7 +832,6 @@
compatible = "nvidia,tegra186-pwm";
reg = <0x0 0x32d0000 0x0 0x10000>;
clocks = <&bpmp TEGRA186_CLK_PWM6>;
- clock-names = "pwm";
resets = <&bpmp TEGRA186_RESET_PWM6>;
reset-names = "pwm";
status = "disabled";
@@ -845,7 +842,6 @@
compatible = "nvidia,tegra186-pwm";
reg = <0x0 0x32e0000 0x0 0x10000>;
clocks = <&bpmp TEGRA186_CLK_PWM7>;
- clock-names = "pwm";
resets = <&bpmp TEGRA186_RESET_PWM7>;
reset-names = "pwm";
status = "disabled";
@@ -856,7 +852,6 @@
compatible = "nvidia,tegra186-pwm";
reg = <0x0 0x32f0000 0x0 0x10000>;
clocks = <&bpmp TEGRA186_CLK_PWM8>;
- clock-names = "pwm";
resets = <&bpmp TEGRA186_RESET_PWM8>;
reset-names = "pwm";
status = "disabled";
@@ -1274,7 +1269,6 @@
compatible = "nvidia,tegra186-pwm";
reg = <0x0 0xc340000 0x0 0x10000>;
clocks = <&bpmp TEGRA186_CLK_PWM4>;
- clock-names = "pwm";
resets = <&bpmp TEGRA186_RESET_PWM4>;
reset-names = "pwm";
status = "disabled";
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
index b0f9393dd39c..cd272d407e01 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
@@ -23,7 +23,7 @@
};
chosen {
- bootargs = "console=ttyS0,115200n8";
+ bootargs = "console=ttyTCU0,115200n8";
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
index 273a1ef716b6..f212f6aced04 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
@@ -2117,8 +2117,8 @@
"usb-b-connector";
label = "micro-USB";
type = "micro";
- vbus-gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 1)
- GPIO_ACTIVE_LOW>;
+ vbus-gpios = <&gpio TEGRA194_MAIN_GPIO(Z, 1)
+ GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi
index 0bd66f9c620b..0751edddf7d5 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi
@@ -20,7 +20,7 @@
};
chosen {
- bootargs = "console=ttyS0,115200n8";
+ bootargs = "console=ttyTCU0,115200n8";
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 41f3a7e188d0..4afcbd60e144 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -86,6 +86,7 @@
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pinmux 0 0 169>;
};
cbb-noc@2300000 {
@@ -142,7 +143,8 @@
reg = <0x2600000 0x210000>;
resets = <&bpmp TEGRA194_RESET_GPCDMA>;
reset-names = "gpcdma";
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
@@ -176,6 +178,7 @@
#dma-cells = <1>;
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
+ dma-channel-mask = <0xfffffffe>;
status = "okay";
};
@@ -626,12 +629,10 @@
pinmux: pinmux@2430000 {
compatible = "nvidia,tegra194-pinmux";
- reg = <0x2430000 0x17000>,
- <0xc300000 0x4000>;
-
+ reg = <0x2430000 0x17000>;
status = "okay";
- pex_rst_c5_out_state: pex_rst_c5_out {
+ pex_rst_c5_out_state: pinmux-pex-rst-c5-out {
pex_rst {
nvidia,pins = "pex_l5_rst_n_pgg1";
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
@@ -642,7 +643,7 @@
};
};
- clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
+ clkreq_c5_bi_dir_state: pinmux-clkreq-c5-bi-dir {
clkreq {
nvidia,pins = "pex_l5_clkreq_n_pgg0";
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
@@ -935,7 +936,6 @@
<&bpmp TEGRA194_CLK_QSPI0_PM>;
clock-names = "qspi", "qspi_out";
resets = <&bpmp TEGRA194_RESET_QSPI0>;
- reset-names = "qspi";
status = "disabled";
};
@@ -949,7 +949,6 @@
<&bpmp TEGRA194_CLK_QSPI1_PM>;
clock-names = "qspi", "qspi_out";
resets = <&bpmp TEGRA194_RESET_QSPI1>;
- reset-names = "qspi";
status = "disabled";
};
@@ -958,7 +957,6 @@
"nvidia,tegra186-pwm";
reg = <0x3280000 0x10000>;
clocks = <&bpmp TEGRA194_CLK_PWM1>;
- clock-names = "pwm";
resets = <&bpmp TEGRA194_RESET_PWM1>;
reset-names = "pwm";
status = "disabled";
@@ -970,7 +968,6 @@
"nvidia,tegra186-pwm";
reg = <0x3290000 0x10000>;
clocks = <&bpmp TEGRA194_CLK_PWM2>;
- clock-names = "pwm";
resets = <&bpmp TEGRA194_RESET_PWM2>;
reset-names = "pwm";
status = "disabled";
@@ -982,7 +979,6 @@
"nvidia,tegra186-pwm";
reg = <0x32a0000 0x10000>;
clocks = <&bpmp TEGRA194_CLK_PWM3>;
- clock-names = "pwm";
resets = <&bpmp TEGRA194_RESET_PWM3>;
reset-names = "pwm";
status = "disabled";
@@ -994,7 +990,6 @@
"nvidia,tegra186-pwm";
reg = <0x32c0000 0x10000>;
clocks = <&bpmp TEGRA194_CLK_PWM5>;
- clock-names = "pwm";
resets = <&bpmp TEGRA194_RESET_PWM5>;
reset-names = "pwm";
status = "disabled";
@@ -1006,7 +1001,6 @@
"nvidia,tegra186-pwm";
reg = <0x32d0000 0x10000>;
clocks = <&bpmp TEGRA194_CLK_PWM6>;
- clock-names = "pwm";
resets = <&bpmp TEGRA194_RESET_PWM6>;
reset-names = "pwm";
status = "disabled";
@@ -1018,7 +1012,6 @@
"nvidia,tegra186-pwm";
reg = <0x32e0000 0x10000>;
clocks = <&bpmp TEGRA194_CLK_PWM7>;
- clock-names = "pwm";
resets = <&bpmp TEGRA194_RESET_PWM7>;
reset-names = "pwm";
status = "disabled";
@@ -1030,7 +1023,6 @@
"nvidia,tegra186-pwm";
reg = <0x32f0000 0x10000>;
clocks = <&bpmp TEGRA194_CLK_PWM8>;
- clock-names = "pwm";
resets = <&bpmp TEGRA194_RESET_PWM8>;
reset-names = "pwm";
status = "disabled";
@@ -1154,7 +1146,7 @@
};
hda@3510000 {
- compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
+ compatible = "nvidia,tegra194-hda";
reg = <0x3510000 0x10000>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA194_CLK_HDA>,
@@ -1366,6 +1358,16 @@
status = "disabled";
};
+ hte_lic: hardware-timestamp@3aa0000 {
+ compatible = "nvidia,tegra194-gte-lic";
+ reg = <0x3aa0000 0x10000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ nvidia,int-threshold = <1>;
+ nvidia,slices = <11>;
+ #timestamp-cells = <1>;
+ status = "okay";
+ };
+
hsp_top0: hsp@3c00000 {
compatible = "nvidia,tegra194-hsp";
reg = <0x03c00000 0xa0000>;
@@ -1579,6 +1581,16 @@
#mbox-cells = <2>;
};
+ hte_aon: hardware-timestamp@c1e0000 {
+ compatible = "nvidia,tegra194-gte-aon";
+ reg = <0xc1e0000 0x10000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ nvidia,int-threshold = <1>;
+ nvidia,slices = <3>;
+ #timestamp-cells = <1>;
+ status = "okay";
+ };
+
gen2_i2c: i2c@c240000 {
compatible = "nvidia,tegra194-i2c";
reg = <0x0c240000 0x10000>;
@@ -1660,6 +1672,14 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-range = <&pinmux_aon 0 0 30>;
+ };
+
+ pinmux_aon: pinmux@c300000 {
+ compatible = "nvidia,tegra194-pinmux-aon";
+ reg = <0xc300000 0x4000>;
+
+ status = "okay";
};
pwm4: pwm@c340000 {
@@ -1667,7 +1687,6 @@
"nvidia,tegra186-pwm";
reg = <0xc340000 0x10000>;
clocks = <&bpmp TEGRA194_CLK_PWM4>;
- clock-names = "pwm";
resets = <&bpmp TEGRA194_RESET_PWM4>;
reset-names = "pwm";
status = "disabled";
@@ -1895,7 +1914,7 @@
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x15000000 0x15000000 0x01000000>;
+ ranges = <0x14800000 0x14800000 0x02800000>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
interconnect-names = "dma-mem";
iommus = <&smmu TEGRA194_SID_HOST1X>;
@@ -3029,36 +3048,51 @@
};
l2c_0: l2-cache0 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <2>;
next-level-cache = <&l3c>;
};
l2c_1: l2-cache1 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <2>;
next-level-cache = <&l3c>;
};
l2c_2: l2-cache2 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <2>;
next-level-cache = <&l3c>;
};
l2c_3: l2-cache3 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <2>;
next-level-cache = <&l3c>;
};
l3c: l3-cache {
+ compatible = "cache";
+ cache-unified;
cache-size = <4194304>;
cache-line-size = <64>;
+ cache-level = <3>;
cache-sets = <4096>;
};
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
index a44c56c1e56e..dd9a17922fe5 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
@@ -1293,14 +1293,14 @@
};
};
- dvfs_pwm_active_state: dvfs_pwm_active {
+ dvfs_pwm_active_state: pinmux-dvfs-pwm-active {
dvfs_pwm_pbb1 {
nvidia,pins = "dvfs_pwm_pbb1";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
};
- dvfs_pwm_inactive_state: dvfs_pwm_inactive {
+ dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive {
dvfs_pwm_pbb1 {
nvidia,pins = "dvfs_pwm_pbb1";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
@@ -1368,6 +1368,7 @@
#size-cells = <0>;
ethernet@1 {
+ compatible = "usb955,9ff";
reg = <1>;
};
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
index 37678c337a34..2041371ea7ff 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
@@ -109,14 +109,14 @@
};
pinmux@700008d4 {
- dvfs_pwm_active_state: dvfs_pwm_active {
+ dvfs_pwm_active_state: pinmux-dvfs-pwm-active {
dvfs_pwm_pbb1 {
nvidia,pins = "dvfs_pwm_pbb1";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
};
- dvfs_pwm_inactive_state: dvfs_pwm_inactive {
+ dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive {
dvfs_pwm_pbb1 {
nvidia,pins = "dvfs_pwm_pbb1";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 724e87450605..bc0cacb20d7a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -554,42 +554,48 @@
compatible = "nvidia,tegra210-pinmux";
reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
<0x0 0x70003000 0x0 0x294>; /* Mux registers */
- sdmmc1_3v3_drv: sdmmc1-3v3-drv {
+
+ sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv {
sdmmc1 {
nvidia,pins = "drive_sdmmc1";
nvidia,pull-down-strength = <0x8>;
nvidia,pull-up-strength = <0x8>;
};
};
- sdmmc1_1v8_drv: sdmmc1-1v8-drv {
+
+ sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv {
sdmmc1 {
nvidia,pins = "drive_sdmmc1";
nvidia,pull-down-strength = <0x4>;
nvidia,pull-up-strength = <0x3>;
};
};
- sdmmc2_1v8_drv: sdmmc2-1v8-drv {
+
+ sdmmc2_1v8_drv: pinmux-sdmmc2-1v8-drv {
sdmmc2 {
nvidia,pins = "drive_sdmmc2";
nvidia,pull-down-strength = <0x10>;
nvidia,pull-up-strength = <0x10>;
};
};
- sdmmc3_3v3_drv: sdmmc3-3v3-drv {
+
+ sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv {
sdmmc3 {
nvidia,pins = "drive_sdmmc3";
nvidia,pull-down-strength = <0x8>;
nvidia,pull-up-strength = <0x8>;
};
};
- sdmmc3_1v8_drv: sdmmc3-1v8-drv {
+
+ sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv {
sdmmc3 {
nvidia,pins = "drive_sdmmc3";
nvidia,pull-down-strength = <0x4>;
nvidia,pull-up-strength = <0x3>;
};
};
- sdmmc4_1v8_drv: sdmmc4-1v8-drv {
+
+ sdmmc4_1v8_drv: pinmux-sdmmc4-1v8-drv {
sdmmc4 {
nvidia,pins = "drive_sdmmc4";
nvidia,pull-down-strength = <0x10>;
@@ -667,7 +673,6 @@
reg = <0x0 0x7000a000 0x0 0x100>;
#pwm-cells = <2>;
clocks = <&tegra_car TEGRA210_CLK_PWM>;
- clock-names = "pwm";
resets = <&tegra_car 17>;
reset-names = "pwm";
status = "disabled";
@@ -912,35 +917,33 @@
};
};
- sdmmc1_3v3: sdmmc1-3v3 {
- pins = "sdmmc1";
- power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
- };
+ pinmux {
+ sdmmc1_3v3: sdmmc1-3v3 {
+ pins = "sdmmc1";
+ power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
+ };
- sdmmc1_1v8: sdmmc1-1v8 {
- pins = "sdmmc1";
- power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
- };
+ sdmmc1_1v8: sdmmc1-1v8 {
+ pins = "sdmmc1";
+ power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
+ };
- sdmmc3_3v3: sdmmc3-3v3 {
- pins = "sdmmc3";
- power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
- };
+ sdmmc3_3v3: sdmmc3-3v3 {
+ pins = "sdmmc3";
+ power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
+ };
- sdmmc3_1v8: sdmmc3-1v8 {
- pins = "sdmmc3";
- power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
- };
+ sdmmc3_1v8: sdmmc3-1v8 {
+ pins = "sdmmc3";
+ power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
+ };
- pex_dpd_disable: pex_en {
- pex-dpd-disable {
+ pex_dpd_disable: pex-dpd-disable {
pins = "pex-bias", "pex-clk1", "pex-clk2";
low-power-disable;
};
- };
- pex_dpd_enable: pex_dis {
- pex-dpd-enable {
+ pex_dpd_enable: pex-dpd-enable {
pins = "pex-bias", "pex-clk1", "pex-clk2";
low-power-enable;
};
@@ -1865,7 +1868,6 @@
<&tegra_car TEGRA210_CLK_QSPI_PM>;
clock-names = "qspi", "qspi_out";
resets = <&tegra_car 211>;
- reset-names = "qspi";
dmas = <&apbdma 5>, <&apbdma 5>;
dma-names = "rx", "tx";
status = "disabled";
@@ -2005,6 +2007,7 @@
L2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi
index 9e4d72cfa69f..8b86ea9cb50c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi
@@ -39,7 +39,6 @@
regulator-max-microvolt = <12000000>;
gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>;
regulator-boot-on;
- enable-active-low;
};
bus@0 {
@@ -55,6 +54,13 @@
};
};
+ mmc@3400000 {
+ status = "okay";
+ bus-width = <4>;
+ cd-gpios = <&gpio TEGRA234_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>;
+ disable-wp;
+ };
+
mmc@3460000 {
status = "okay";
bus-width = <8>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
index 57ab75328814..96aa2267b06d 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
@@ -2007,6 +2007,17 @@
status = "okay";
};
+ serial@31d0000 {
+ current-speed = <115200>;
+ status = "okay";
+ };
+
+ pwm@32a0000 {
+ assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+ status = "okay";
+ };
+
hda@3510000 {
nvidia,model = "NVIDIA Jetson AGX Orin HDA";
status = "okay";
@@ -2014,7 +2025,7 @@
};
chosen {
- bootargs = "console=ttyS0,115200n8";
+ bootargs = "console=ttyTCU0,115200n8";
stdout-path = "serial0:115200n8";
};
@@ -2184,4 +2195,12 @@
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
"p2u-5", "p2u-6", "p2u-7";
};
+
+ pwm-fan {
+ compatible = "pwm-fan";
+ pwms = <&pwm3 0 45334>;
+
+ cooling-levels = <0 95 178 255>;
+ #cooling-cells = <2>;
+ };
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi
index a85993c85e45..e76894574d32 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi
@@ -2,4 +2,18 @@
/ {
compatible = "nvidia,p3737-0000";
+
+ bus@0 {
+ pwm@3280000 {
+ status = "okay";
+ };
+
+ pwm@32c0000 {
+ status = "okay";
+ };
+
+ pwm@32f0000 {
+ status = "okay";
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 0170bfa8a467..eaf05ee9acd1 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/memory/tegra234-mc.h>
#include <dt-bindings/power/tegra234-powergate.h>
#include <dt-bindings/reset/tegra234-reset.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
/ {
compatible = "nvidia,tegra234";
@@ -27,7 +28,8 @@
reg = <0x2600000 0x210000>;
resets = <&bpmp TEGRA234_RESET_GPCDMA>;
reset-names = "gpcdma";
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
@@ -60,6 +62,7 @@
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+ dma-channel-mask = <0xfffffffe>;
dma-coherent;
};
@@ -564,7 +567,7 @@
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x15000000 0x15000000 0x01000000>;
+ ranges = <0x14800000 0x14800000 0x02000000>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>;
interconnect-names = "dma-mem";
iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>;
@@ -603,6 +606,42 @@
iommus = <&smmu_niso1 TEGRA234_SID_VIC>;
dma-coherent;
};
+
+ nvdec@15480000 {
+ compatible = "nvidia,tegra234-nvdec";
+ reg = <0x15480000 0x00040000>;
+ clocks = <&bpmp TEGRA234_CLK_NVDEC>,
+ <&bpmp TEGRA234_CLK_FUSE>,
+ <&bpmp TEGRA234_CLK_TSEC_PKA>;
+ clock-names = "nvdec", "fuse", "tsec_pka";
+ resets = <&bpmp TEGRA234_RESET_NVDEC>;
+ reset-names = "nvdec";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
+ dma-coherent;
+
+ nvidia,memory-controller = <&mc>;
+
+ /*
+ * Placeholder values that firmware needs to update with the real
+ * offsets parsed from the microcode headers.
+ */
+ nvidia,bl-manifest-offset = <0>;
+ nvidia,bl-data-offset = <0>;
+ nvidia,bl-code-offset = <0>;
+ nvidia,os-manifest-offset = <0>;
+ nvidia,os-data-offset = <0>;
+ nvidia,os-code-offset = <0>;
+
+ /*
+ * Firmware needs to set this to "okay" once the above values have
+ * been updated.
+ */
+ status = "disabled";
+ };
};
gpio: gpio@2200000 {
@@ -836,6 +875,13 @@
dma-names = "rx", "tx";
};
+ uarti: serial@31d0000 {
+ compatible = "arm,sbsa-uart";
+ reg = <0x31d0000 0x10000>;
+ interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
dp_aux_ch3_i2c: i2c@31e0000 {
compatible = "nvidia,tegra194-i2c";
reg = <0x31e0000 0x100>;
@@ -865,22 +911,79 @@
<&bpmp TEGRA234_CLK_QSPI0_PM>;
clock-names = "qspi", "qspi_out";
resets = <&bpmp TEGRA234_RESET_QSPI0>;
- reset-names = "qspi";
status = "disabled";
};
pwm1: pwm@3280000 {
- compatible = "nvidia,tegra194-pwm",
- "nvidia,tegra186-pwm";
+ compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
reg = <0x3280000 0x10000>;
clocks = <&bpmp TEGRA234_CLK_PWM1>;
- clock-names = "pwm";
resets = <&bpmp TEGRA234_RESET_PWM1>;
reset-names = "pwm";
status = "disabled";
#pwm-cells = <2>;
};
+ pwm2: pwm@3290000 {
+ compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
+ reg = <0x3290000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM2>;
+ resets = <&bpmp TEGRA234_RESET_PWM2>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm3: pwm@32a0000 {
+ compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
+ reg = <0x32a0000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM3>;
+ resets = <&bpmp TEGRA234_RESET_PWM3>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm5: pwm@32c0000 {
+ compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
+ reg = <0x32c0000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM5>;
+ resets = <&bpmp TEGRA234_RESET_PWM5>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm6: pwm@32d0000 {
+ compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
+ reg = <0x32d0000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM6>;
+ resets = <&bpmp TEGRA234_RESET_PWM6>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm7: pwm@32e0000 {
+ compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
+ reg = <0x32e0000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM7>;
+ resets = <&bpmp TEGRA234_RESET_PWM7>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
+ pwm8: pwm@32f0000 {
+ compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
+ reg = <0x32f0000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM8>;
+ resets = <&bpmp TEGRA234_RESET_PWM8>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
spi@3300000 {
compatible = "nvidia,tegra234-qspi";
reg = <0x3300000 0x1000>;
@@ -891,7 +994,41 @@
<&bpmp TEGRA234_CLK_QSPI1_PM>;
clock-names = "qspi", "qspi_out";
resets = <&bpmp TEGRA234_RESET_QSPI1>;
- reset-names = "qspi";
+ status = "disabled";
+ };
+
+ mmc@3400000 {
+ compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
+ reg = <0x03400000 0x20000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
+ <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
+ clock-names = "sdhci", "tmclk";
+ assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
+ <&bpmp TEGRA234_CLK_PLLC4_MUXED>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>,
+ <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>;
+ resets = <&bpmp TEGRA234_RESET_SDMMC1>;
+ reset-names = "sdhci";
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>;
+ pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+ pinctrl-0 = <&sdmmc1_3v3>;
+ pinctrl-1 = <&sdmmc1_1v8>;
+ nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
+ nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>;
+ nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
+ nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
+ nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
+ nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
+ nvidia,default-tap = <14>;
+ nvidia,default-trim = <0x8>;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-ddr50;
+ sd-uhs-sdr104;
status = "disabled";
};
@@ -925,7 +1062,7 @@
};
hda@3510000 {
- compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda";
+ compatible = "nvidia,tegra234-hda";
reg = <0x3510000 0x10000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA234_CLK_AZA_BIT>,
@@ -967,6 +1104,198 @@
#mbox-cells = <2>;
};
+ p2u_hsio_0: phy@3e00000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03e00000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_hsio_1: phy@3e10000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03e10000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_hsio_2: phy@3e20000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03e20000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_hsio_3: phy@3e30000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03e30000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_hsio_4: phy@3e40000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03e40000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_hsio_5: phy@3e50000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03e50000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_hsio_6: phy@3e60000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03e60000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_hsio_7: phy@3e70000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03e70000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_nvhs_0: phy@3e90000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03e90000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_nvhs_1: phy@3ea0000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03ea0000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_nvhs_2: phy@3eb0000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03eb0000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_nvhs_3: phy@3ec0000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03ec0000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_nvhs_4: phy@3ed0000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03ed0000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_nvhs_5: phy@3ee0000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03ee0000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_nvhs_6: phy@3ef0000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03ef0000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_nvhs_7: phy@3f00000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03f00000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_gbe_0: phy@3f20000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03f20000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_gbe_1: phy@3f30000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03f30000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_gbe_2: phy@3f40000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03f40000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_gbe_3: phy@3f50000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03f50000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_gbe_4: phy@3f60000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03f60000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_gbe_5: phy@3f70000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03f70000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_gbe_6: phy@3f80000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03f80000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_gbe_7: phy@3f90000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03f90000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
ethernet@6800000 {
compatible = "nvidia,tegra234-mgbe";
reg = <0x06800000 0x10000>,
@@ -1259,198 +1588,6 @@
status = "okay";
};
- p2u_hsio_0: phy@3e00000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03e00000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_hsio_1: phy@3e10000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03e10000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_hsio_2: phy@3e20000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03e20000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_hsio_3: phy@3e30000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03e30000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_hsio_4: phy@3e40000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03e40000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_hsio_5: phy@3e50000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03e50000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_hsio_6: phy@3e60000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03e60000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_hsio_7: phy@3e70000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03e70000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_nvhs_0: phy@3e90000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03e90000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_nvhs_1: phy@3ea0000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03ea0000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_nvhs_2: phy@3eb0000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03eb0000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_nvhs_3: phy@3ec0000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03ec0000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_nvhs_4: phy@3ed0000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03ed0000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_nvhs_5: phy@3ee0000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03ee0000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_nvhs_6: phy@3ef0000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03ef0000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_nvhs_7: phy@3f00000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03f00000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_gbe_0: phy@3f20000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03f20000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_gbe_1: phy@3f30000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03f30000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_gbe_2: phy@3f40000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03f40000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_gbe_3: phy@3f50000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03f50000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_gbe_4: phy@3f60000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03f60000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_gbe_5: phy@3f70000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03f70000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_gbe_6: phy@3f80000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03f80000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
- p2u_gbe_7: phy@3f90000 {
- compatible = "nvidia,tegra234-p2u";
- reg = <0x03f90000 0x10000>;
- reg-names = "ctl";
-
- #phy-cells = <0>;
- };
-
hsp_aon: hsp@c150000 {
compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
reg = <0x0c150000 0x90000>;
@@ -1488,7 +1625,6 @@
gen8_i2c: i2c@c250000 {
compatible = "nvidia,tegra194-i2c";
reg = <0xc250000 0x100>;
- nvidia,hw-instance-id = <0x7>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clock-frequency = <400000>;
@@ -1530,6 +1666,16 @@
gpio-controller;
};
+ pwm4: pwm@c340000 {
+ compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
+ reg = <0xc340000 0x10000>;
+ clocks = <&bpmp TEGRA234_CLK_PWM4>;
+ resets = <&bpmp TEGRA234_RESET_PWM4>;
+ reset-names = "pwm";
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+
pmc: pmc@c360000 {
compatible = "nvidia,tegra234-pmc";
reg = <0x0c360000 0x10000>,
@@ -1541,6 +1687,26 @@
#interrupt-cells = <2>;
interrupt-controller;
+
+ sdmmc1_3v3: sdmmc1-3v3 {
+ pins = "sdmmc1-hv";
+ power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
+ };
+
+ sdmmc1_1v8: sdmmc1-1v8 {
+ pins = "sdmmc1-hv";
+ power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
+ };
+
+ sdmmc3_3v3: sdmmc3-3v3 {
+ pins = "sdmmc3-hv";
+ power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
+ };
+
+ sdmmc3_1v8: sdmmc3-1v8 {
+ pins = "sdmmc3-hv";
+ power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
+ };
};
aon-fabric@c600000 {
@@ -1576,7 +1742,7 @@
interrupt-controller;
};
- smmu_iso: iommu@10000000{
+ smmu_iso: iommu@10000000 {
compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
reg = <0x10000000 0x1000000>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
@@ -1879,8 +2045,9 @@
reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
- <0x00 0x2a080000 0x0 0x00040000>; /* DBI reg space (256K) */
- reg-names = "appl", "config", "atu_dma", "dbi";
+ <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
+ reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
#address-cells = <3>;
#size-cells = <2>;
@@ -1932,8 +2099,9 @@
reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
- <0x00 0x2c080000 0x0 0x00040000>; /* DBI reg space (256K) */
- reg-names = "appl", "config", "atu_dma", "dbi";
+ <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
+ reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
#address-cells = <3>;
#size-cells = <2>;
@@ -1965,7 +2133,7 @@
bus-range = <0x0 0xff>;
- ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
+ ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */
<0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
<0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
@@ -1985,8 +2153,9 @@
reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
- <0x00 0x2e080000 0x0 0x00040000>; /* DBI reg space (256K) */
- reg-names = "appl", "config", "atu_dma", "dbi";
+ <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
+ reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
#address-cells = <3>;
#size-cells = <2>;
@@ -2038,8 +2207,9 @@
reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
- <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
- reg-names = "appl", "config", "atu_dma", "dbi";
+ <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */
+ reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
#address-cells = <3>;
#size-cells = <2>;
@@ -2091,8 +2261,9 @@
reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
- <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
- reg-names = "appl", "config", "atu_dma", "dbi";
+ <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */
+ reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
#address-cells = <3>;
#size-cells = <2>;
@@ -2144,8 +2315,9 @@
reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
- <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
- reg-names = "appl", "config", "atu_dma", "dbi";
+ <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
+ reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
#address-cells = <3>;
#size-cells = <2>;
@@ -2178,7 +2350,7 @@
bus-range = <0x0 0xff>;
ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
- <0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
+ <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
<0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>,
@@ -2197,8 +2369,9 @@
reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
- <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
- reg-names = "appl", "config", "atu_dma", "dbi";
+ <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
+ reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
#address-cells = <3>;
#size-cells = <2>;
@@ -2250,8 +2423,9 @@
reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
- <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
- reg-names = "appl", "config", "atu_dma", "dbi";
+ <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
+ reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
#address-cells = <3>;
#size-cells = <2>;
@@ -2303,8 +2477,9 @@
reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
- <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
- reg-names = "appl", "config", "atu_dma", "dbi";
+ <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
+ reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
#address-cells = <3>;
#size-cells = <2>;
@@ -2336,7 +2511,7 @@
bus-range = <0x0 0xff>;
- ranges = <0x43000000 0x27 0x40000000 0x27 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */
+ ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */
<0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
<0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
@@ -2356,8 +2531,9 @@
reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
- <0x00 0x3c080000 0x0 0x00040000>; /* DBI reg space (256K) */
- reg-names = "appl", "config", "atu_dma", "dbi";
+ <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
+ reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
#address-cells = <3>;
#size-cells = <2>;
@@ -2409,8 +2585,9 @@
reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
- <0x00 0x3e080000 0x0 0x00040000>; /* DBI reg space (256K) */
- reg-names = "appl", "config", "atu_dma", "dbi";
+ <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
+ reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
#address-cells = <3>;
#size-cells = <2>;
@@ -2442,7 +2619,7 @@
bus-range = <0x0 0xff>;
- ranges = <0x43000000 0x2e 0x40000000 0x2e 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */
+ ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */
<0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
<0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
@@ -2905,117 +3082,150 @@
};
l2c0_0: l2-cache00 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c0>;
};
l2c0_1: l2-cache01 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c0>;
};
l2c0_2: l2-cache02 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c0>;
};
l2c0_3: l2-cache03 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c0>;
};
l2c1_0: l2-cache10 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c1>;
};
l2c1_1: l2-cache11 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c1>;
};
l2c1_2: l2-cache12 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c1>;
};
l2c1_3: l2-cache13 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c1>;
};
l2c2_0: l2-cache20 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c2>;
};
l2c2_1: l2-cache21 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c2>;
};
l2c2_2: l2-cache22 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c2>;
};
l2c2_3: l2-cache23 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c2>;
};
l3c0: l3-cache0 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <3>;
};
l3c1: l3-cache1 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <3>;
};
l3c2: l3-cache2 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <3>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index d7669a7cee9f..3e79496292e7 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -21,6 +21,8 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-grandmax.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8956-sony-xperia-loire-kugo.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8956-sony-xperia-loire-suzu.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-10.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-octagon-talkman.dtb
@@ -33,12 +35,14 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-satsuki.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-sumire.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-suzuran.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8996-oneplus3.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8996-oneplus3t.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-dora.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-kagura.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-keyaki.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-gemini.dtb
-dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-natrium.dtb
-dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-scorpio.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8996pro-xiaomi-natrium.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8996pro-xiaomi-scorpio.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-fxtec-pro1.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb
@@ -49,11 +53,14 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-oneplus-dumpling.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-lilac.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb
@@ -87,6 +94,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-parade.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-ti.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-parade.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-ti.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel360-lte.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel360-wifi.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb
@@ -104,11 +113,14 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd.dtb
-dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-evoker-r0.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-evoker.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-evoker-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r0.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r1-lte.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb
@@ -122,25 +134,31 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c-navigation-mezzanine.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-enchilada.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sdm845-samsung-starqltechn.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akari.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akatsuki.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-apollo.dtb
-dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium-ebbg.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium-tianma.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb
@@ -159,3 +177,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts
index 1b613098fb4a..ef5b39ba1238 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts
@@ -718,14 +718,14 @@
"USR_LED_2_CTRL", /* GPIO 120 */
"SB_HS_ID";
- msmgpio_leds: msmgpio-leds {
+ msmgpio_leds: msmgpio-leds-state {
pins = "gpio21", "gpio120";
function = "gpio";
output-low;
};
- usb_id_default: usb-id-default {
+ usb_id_default: usb-id-default-state {
pins = "gpio121";
function = "gpio";
@@ -734,7 +734,7 @@
bias-pull-up;
};
- adv7533_int_active: adv533-int-active {
+ adv7533_int_active: adv533-int-active-state {
pins = "gpio31";
function = "gpio";
@@ -742,7 +742,7 @@
bias-disable;
};
- adv7533_int_suspend: adv7533-int-suspend {
+ adv7533_int_suspend: adv7533-int-suspend-state {
pins = "gpio31";
function = "gpio";
@@ -750,7 +750,7 @@
bias-disable;
};
- adv7533_switch_active: adv7533-switch-active {
+ adv7533_switch_active: adv7533-switch-active-state {
pins = "gpio32";
function = "gpio";
@@ -758,7 +758,7 @@
bias-disable;
};
- adv7533_switch_suspend: adv7533-switch-suspend {
+ adv7533_switch_suspend: adv7533-switch-suspend-state {
pins = "gpio32";
function = "gpio";
@@ -766,7 +766,7 @@
bias-disable;
};
- msm_key_volp_n_default: msm-key-volp-n-default {
+ msm_key_volp_n_default: msm-key-volp-n-default-state {
pins = "gpio107";
function = "gpio";
@@ -839,7 +839,7 @@
function = "digital";
output-low;
- power-source = <PM8916_MPP_L5>; // 1.8V
+ power-source = <PM8916_MPP_L5>; /* 1.8V */
};
pm8916_mpps_leds: pm8916-mpps-state {
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
index 5cdc7ac1a9c0..fe6c415e8229 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
@@ -422,82 +422,46 @@
"NC", /* GPIO_148 */
"NC"; /* GPIO_149 */
- sdc2_cd_on: sdc2_cd_on {
- mux {
- pins = "gpio38";
- function = "gpio";
- };
-
- config {
- pins = "gpio38";
- bias-pull-up; /* pull up */
- drive-strength = <16>; /* 16 MA */
- };
+ sdc2_cd_on: sdc2-cd-on-state {
+ pins = "gpio38";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <16>;
};
- sdc2_cd_off: sdc2_cd_off {
- mux {
- pins = "gpio38";
- function = "gpio";
- };
-
- config {
- pins = "gpio38";
- bias-pull-up; /* pull up */
- drive-strength = <2>; /* 2 MA */
- };
+ sdc2_cd_off: sdc2-cd-off-state {
+ pins = "gpio38";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <2>;
};
- hdmi_hpd_active: hdmi_hpd_active {
- mux {
- pins = "gpio34";
- function = "hdmi_hot";
- };
-
- config {
- pins = "gpio34";
- bias-pull-down;
- drive-strength = <16>;
- };
+ hdmi_hpd_active: hdmi-hpd-active-state {
+ pins = "gpio34";
+ function = "hdmi_hot";
+ bias-pull-down;
+ drive-strength = <16>;
};
- hdmi_hpd_suspend: hdmi_hpd_suspend {
- mux {
- pins = "gpio34";
- function = "hdmi_hot";
- };
-
- config {
- pins = "gpio34";
- bias-pull-down;
- drive-strength = <2>;
- };
+ hdmi_hpd_suspend: hdmi-hpd-suspend-state {
+ pins = "gpio34";
+ function = "hdmi_hot";
+ bias-pull-down;
+ drive-strength = <2>;
};
- hdmi_ddc_active: hdmi_ddc_active {
- mux {
- pins = "gpio32", "gpio33";
- function = "hdmi_ddc";
- };
-
- config {
- pins = "gpio32", "gpio33";
- drive-strength = <2>;
- bias-pull-up;
- };
+ hdmi_ddc_active: hdmi-ddc-active-state {
+ pins = "gpio32", "gpio33";
+ function = "hdmi_ddc";
+ drive-strength = <2>;
+ bias-pull-up;
};
- hdmi_ddc_suspend: hdmi_ddc_suspend {
- mux {
- pins = "gpio32", "gpio33";
- function = "hdmi_ddc";
- };
-
- config {
- pins = "gpio32", "gpio33";
- drive-strength = <2>;
- bias-pull-down;
- };
+ hdmi_ddc_suspend: hdmi-ddc-suspend-state {
+ pins = "gpio32", "gpio33";
+ function = "hdmi_ddc";
+ drive-strength = <2>;
+ bias-pull-down;
};
};
@@ -560,7 +524,7 @@
pins = "gpio5";
function = PMIC_GPIO_FUNC_NORMAL;
output-low;
- power-source = <2>; // PM8994_GPIO_S4, 1.8V
+ power-source = <PM8994_GPIO_S4>; /* 1.8V */
};
};
@@ -569,7 +533,7 @@
pins = "gpio19";
function = PMIC_GPIO_FUNC_NORMAL;
output-low;
- power-source = <PM8994_GPIO_S4>; // 1.8V
+ power-source = <PM8994_GPIO_S4>; /* 1.8V */
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
bias-pull-down;
};
@@ -580,7 +544,7 @@
pins = "gpio8";
function = PMIC_GPIO_FUNC_NORMAL;
output-low;
- power-source = <PM8994_GPIO_S4>; // 1.8V
+ power-source = <PM8994_GPIO_S4>; /* 1.8V */
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
bias-pull-down;
};
@@ -590,7 +554,7 @@
pinconf {
pins = "gpio15";
function = "func1";
- power-source = <PM8994_GPIO_S4>; // 1.8V
+ power-source = <PM8994_GPIO_S4>; /* 1.8V */
};
};
@@ -602,7 +566,7 @@
drive-push-pull;
bias-pull-up;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
- power-source = <PM8994_GPIO_S4>; // 1.8V
+ power-source = <PM8994_GPIO_S4>; /* 1.8V */
};
};
@@ -623,7 +587,7 @@
input-enable;
bias-pull-down;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
- power-source = <PM8994_GPIO_S4>; // 1.8V
+ power-source = <PM8994_GPIO_S4>; /* 1.8V */
};
};
};
@@ -679,7 +643,7 @@
input-enable;
bias-pull-down;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
- power-source = <PM8994_GPIO_S4>; // 1.8V
+ power-source = <PM8994_GPIO_S4>; /* 1.8V */
};
};
};
@@ -751,7 +715,7 @@
};
&rpm_requests {
- pm8994-regulators {
+ regulators-0 {
compatible = "qcom,rpm-pm8994-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -963,7 +927,7 @@
};
};
- pmi8994-regulators {
+ regulators-1 {
compatible = "qcom,rpm-pmi8994-regulators";
vdd_s1-supply = <&vph_pwr>;
diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts
index 92f264891d84..71e0a500599c 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts
+++ b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts
@@ -104,65 +104,27 @@
status = "okay";
};
-&tlmm {
- sdc2_pins_default: sdc2-pins-default {
- clk {
- pins = "sdc2_clk";
- bias-disable;
- drive-strength = <16>;
- };
-
- cmd {
- pins = "sdc2_cmd";
- bias-pull-up;
- drive-strength = <10>;
- };
-
- data {
- pins = "sdc2_data";
- bias-pull-up;
- drive-strength = <10>;
- };
+&sdc2_state_on {
+ cd-pins {
+ pins = "gpio38";
+ function = "gpio";
- cd {
- pins = "gpio38";
- function = "gpio";
-
- bias-pull-up;
- drive-strength = <16>;
- };
+ bias-pull-up;
+ drive-strength = <16>;
};
+};
- sdc2_pins_sleep: sdc2-pins-sleep {
- clk {
- pins = "sdc2_clk";
- bias-disable;
- drive-strength = <2>;
- };
-
- cmd {
- pins = "sdc2_cmd";
- bias-pull-up;
- drive-strength = <2>;
- };
-
- data {
- pins = "sdc2_data";
- bias-pull-up;
- drive-strength = <2>;
- };
-
- cd {
- pins = "gpio38";
- function = "gpio";
- bias-pull-up;
- drive-strength = <2>;
- };
+&sdc2_state_off {
+ cd-pins {
+ pins = "gpio38";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <2>;
};
};
&rpm_requests {
- pm8994-regulators {
+ regulators-0 {
compatible = "qcom,rpm-pm8994-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -372,10 +334,6 @@
vmmc-supply = <&vreg_l21a_2p95>;
vqmmc-supply = <&vreg_l13a_2p95>;
-
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdc2_pins_default>;
- pinctrl-1 = <&sdc2_pins_sleep>;
};
&ufshc {
diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
index 1ba2eca33c7b..2aee8594b280 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
@@ -19,7 +19,6 @@
chosen {
stdout-path = "serial0:115200n8";
- bootargs-append = " swiotlb=1";
};
};
@@ -37,6 +36,8 @@
&blsp1_spi1 {
cs-select = <0>;
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
status = "okay";
flash@0 {
@@ -49,13 +50,13 @@
};
&tlmm {
- i2c_1_pins: i2c-1-pins {
+ i2c_1_pins: i2c-1-state {
pins = "gpio42", "gpio43";
function = "blsp2_i2c";
drive-strength = <8>;
};
- spi_0_pins: spi-0-pins {
+ spi_0_pins: spi-0-state {
pins = "gpio38", "gpio39", "gpio40", "gpio41";
function = "blsp0_spi";
drive-strength = <8>;
@@ -80,9 +81,9 @@
};
&qusb_phy_1 {
- status = "ok";
+ status = "okay";
};
&usb2 {
- status = "ok";
+ status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index a7c7ca980a71..5d453f11acd9 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -218,14 +218,14 @@
interrupt-controller;
#interrupt-cells = <2>;
- serial_3_pins: serial3-pinmux {
+ serial_3_pins: serial3-state {
pins = "gpio44", "gpio45";
function = "blsp2_uart";
drive-strength = <8>;
bias-pull-down;
};
- qpic_pins: qpic-pins {
+ qpic_pins: qpic-state {
pins = "gpio1", "gpio3", "gpio4",
"gpio5", "gpio6", "gpio7",
"gpio8", "gpio10", "gpio11",
@@ -348,7 +348,7 @@
status = "disabled";
};
- qpic_nand: nand@79b0000 {
+ qpic_nand: nand-controller@79b0000 {
compatible = "qcom,ipq6018-nand";
reg = <0x0 0x079b0000 0x0 0x10000>;
#address-cells = <1>;
@@ -406,7 +406,8 @@
pcie_phy0: phy@84200 {
reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */
<0x0 0x84400 0x0 0x200>, /* Serdes Rx */
- <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */
+ <0x0 0x84800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
+ <0x0 0x84c00 0x0 0xf4>; /* pcs_misc */
#phy-cells = <0>;
clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
@@ -511,14 +512,6 @@
clock-names = "xo";
};
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
timer@b120000 {
#address-cells = <1>;
#size-cells = <1>;
@@ -770,6 +763,14 @@
};
};
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
wcss: wcss-smp2p {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 7143c936de61..ca3f96646b90 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -1,8 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
-/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
*/
#include "ipq8074.dtsi"
+#include "pmp8074.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
@@ -51,12 +54,12 @@
&pcie0 {
status = "okay";
- perst-gpios = <&tlmm 61 0x1>;
+ perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
};
&pcie1 {
status = "okay";
- perst-gpios = <&tlmm 58 0x1>;
+ perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
&pcie_phy0 {
@@ -84,6 +87,7 @@
&sdhc_1 {
status = "okay";
+ vqmmc-supply = <&l11>;
};
&qusb_phy_0 {
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
index 2bfcf42aeabc..cc1992ca0519 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
index 7da39f1d979b..d7f0efda6b8e 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
*/
#include "ipq8074-hk10.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
index db4b87944cdf..651a231554e0 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
@@ -5,6 +5,7 @@
/dts-v1/;
#include "ipq8074.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
@@ -22,7 +23,7 @@
};
&blsp1_spi1 {
- status = "ok";
+ status = "okay";
flash@0 {
#address-cells = <1>;
@@ -34,33 +35,33 @@
};
&blsp1_uart5 {
- status = "ok";
+ status = "okay";
};
&pcie0 {
- status = "ok";
- perst-gpios = <&tlmm 58 0x1>;
+ status = "okay";
+ perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
&pcie1 {
- status = "ok";
- perst-gpios = <&tlmm 61 0x1>;
+ status = "okay";
+ perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
};
&pcie_phy0 {
- status = "ok";
+ status = "okay";
};
&pcie_phy1 {
- status = "ok";
+ status = "okay";
};
&qpic_bam {
- status = "ok";
+ status = "okay";
};
&qpic_nand {
- status = "ok";
+ status = "okay";
nand@0 {
reg = <0>;
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index a721cdd80489..4e51d8e3df04 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -129,10 +129,10 @@
status = "disabled";
usb1_ssphy: phy@58200 {
- reg = <0x00058200 0x130>, /* Tx */
+ reg = <0x00058200 0x130>, /* Tx */
<0x00058400 0x200>, /* Rx */
- <0x00058800 0x1f8>, /* PCS */
- <0x00058600 0x044>; /* PCS misc*/
+ <0x00058800 0x1f8>, /* PCS */
+ <0x00058600 0x044>; /* PCS misc */
#phy-cells = <0>;
#clock-cells = <0>;
clocks = <&gcc GCC_USB1_PIPE_CLK>;
@@ -172,10 +172,10 @@
status = "disabled";
usb0_ssphy: phy@78200 {
- reg = <0x00078200 0x130>, /* Tx */
+ reg = <0x00078200 0x130>, /* Tx */
<0x00078400 0x200>, /* Rx */
- <0x00078800 0x1f8>, /* PCS */
- <0x00078600 0x044>; /* PCS misc*/
+ <0x00078800 0x1f8>, /* PCS */
+ <0x00078600 0x044>; /* PCS misc */
#phy-cells = <0>;
#clock-cells = <0>;
clocks = <&gcc GCC_USB0_PIPE_CLK>;
@@ -273,6 +273,16 @@
status = "disabled";
};
+ tsens: thermal-sensor@4a9000 {
+ compatible = "qcom,ipq8074-tsens";
+ reg = <0x4a9000 0x1000>, /* TM */
+ <0x4a8000 0x1000>; /* SROT */
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "combined";
+ #qcom,sensors = <16>;
+ #thermal-sensor-cells = <1>;
+ };
+
cryptobam: dma-controller@704000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x00704000 0x20000>;
@@ -307,35 +317,35 @@
interrupt-controller;
#interrupt-cells = <0x2>;
- serial_4_pins: serial4-pinmux {
+ serial_4_pins: serial4-state {
pins = "gpio23", "gpio24";
function = "blsp4_uart1";
drive-strength = <8>;
bias-disable;
};
- i2c_0_pins: i2c-0-pinmux {
+ i2c_0_pins: i2c-0-state {
pins = "gpio42", "gpio43";
function = "blsp1_i2c";
drive-strength = <8>;
bias-disable;
};
- spi_0_pins: spi-0-pins {
+ spi_0_pins: spi-0-state {
pins = "gpio38", "gpio39", "gpio40", "gpio41";
function = "blsp0_spi";
drive-strength = <8>;
bias-disable;
};
- hsuart_pins: hsuart-pins {
+ hsuart_pins: hsuart-state {
pins = "gpio46", "gpio47", "gpio48", "gpio49";
function = "blsp2_uart";
drive-strength = <8>;
bias-disable;
};
- qpic_pins: qpic-pins {
+ qpic_pins: qpic-state {
pins = "gpio1", "gpio3", "gpio4",
"gpio5", "gpio6", "gpio7",
"gpio8", "gpio10", "gpio11",
@@ -350,9 +360,11 @@
gcc: gcc@1800000 {
compatible = "qcom,gcc-ipq8074";
reg = <0x01800000 0x80000>;
- #clock-cells = <0x1>;
+ clocks = <&xo>, <&sleep_clk>;
+ clock-names = "xo", "sleep_clk";
+ #clock-cells = <1>;
#power-domain-cells = <1>;
- #reset-cells = <0x1>;
+ #reset-cells = <1>;
};
tcsr_mutex: hwlock@1905000 {
@@ -669,11 +681,21 @@
apcs_glb: mailbox@b111000 {
compatible = "qcom,ipq8074-apcs-apps-global";
reg = <0x0b111000 0x1000>;
+ clocks = <&a53pll>, <&xo>;
+ clock-names = "pll", "xo";
#clock-cells = <1>;
#mbox-cells = <1>;
};
+ a53pll: clock@b116000 {
+ compatible = "qcom,ipq8074-a53pll";
+ reg = <0x0b116000 0x40>;
+ #clock-cells = <0>;
+ clocks = <&xo>;
+ clock-names = "xo";
+ };
+
timer@b120000 {
#address-cells = <1>;
#size-cells = <1>;
@@ -865,4 +887,90 @@
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
+
+ thermal-zones {
+ nss-top-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 4>;
+ };
+
+ nss0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 5>;
+ };
+
+ nss1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 6>;
+ };
+
+ wcss-phya0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 7>;
+ };
+
+ wcss-phya1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 8>;
+ };
+
+ cpu0_thermal: cpu0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 9>;
+ };
+
+ cpu1_thermal: cpu1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 10>;
+ };
+
+ cpu2_thermal: cpu2-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 11>;
+ };
+
+ cpu3_thermal: cpu3-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 12>;
+ };
+
+ cluster_thermal: cluster-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 13>;
+ };
+
+ wcss-phyb0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 14>;
+ };
+
+ wcss-phyb1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 15>;
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts
index 3dc9619fde6e..701a5585d77e 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts
@@ -5,6 +5,7 @@
#include "msm8916-pm8916.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
/ {
model = "Alcatel OneTouch Idol 3 (4.7)";
@@ -34,6 +35,19 @@
};
};
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_leds_default>;
+
+ led-0 {
+ gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "torch";
+ function = LED_FUNCTION_TORCH;
+ };
+ };
+
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&msmgpio 69 GPIO_ACTIVE_HIGH>;
@@ -116,6 +130,27 @@
};
};
+&blsp_i2c6 {
+ status = "okay";
+
+ led-controller@68 {
+ compatible = "si-en,sn3190";
+ reg = <0x68>;
+ shutdown-gpios = <&msmgpio 89 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_enable_default &led_shutdown_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ led-max-microamp = <5000>;
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_WHITE>;
+ };
+ };
+};
+
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
@@ -260,7 +295,7 @@
};
&msmgpio {
- accel_int_default: accel-int-default {
+ accel_int_default: accel-int-default-state {
pins = "gpio31";
function = "gpio";
@@ -268,7 +303,7 @@
bias-disable;
};
- gpio_keys_default: gpio-keys-default {
+ gpio_keys_default: gpio-keys-default-state {
pins = "gpio107";
function = "gpio";
@@ -276,7 +311,15 @@
bias-pull-up;
};
- gyro_int_default: gyro-int-default {
+ gpio_leds_default: gpio-leds-default-state {
+ pins = "gpio32";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ gyro_int_default: gyro-int-default-state {
pins = "gpio97", "gpio98";
function = "gpio";
@@ -284,7 +327,30 @@
bias-disable;
};
- mag_reset_default: mag-reset-default {
+ /*
+ * The OEM wired an additional GPIO to be asserted so that
+ * the si-en,sn3190 LED IC works. Since this GPIO is not
+ * part of the IC datasheet nor supported by the driver,
+ * force it asserted here.
+ */
+ led_enable_default: led-enable-default-state {
+ pins = "gpio102";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+
+ led_shutdown_default: led-shutdown-default-state {
+ pins = "gpio89";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ mag_reset_default: mag-reset-default-state {
pins = "gpio8";
function = "gpio";
@@ -292,7 +358,7 @@
bias-disable;
};
- proximity_int_default: proximity-int-default {
+ proximity_int_default: proximity-int-default-state {
pins = "gpio12";
function = "gpio";
@@ -300,7 +366,7 @@
bias-pull-up;
};
- ts_int_reset_default: ts-int-reset-default {
+ ts_int_reset_default: ts-int-reset-default-state {
pins = "gpio13", "gpio100";
function = "gpio";
@@ -308,7 +374,7 @@
bias-disable;
};
- usb_id_default: usb-id-default {
+ usb_id_default: usb-id-default-state {
pins = "gpio69";
function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts
index dd92070a1211..3618704a5330 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts
@@ -263,7 +263,7 @@
};
&msmgpio {
- gpio_keys_default: gpio-keys-default {
+ gpio_keys_default: gpio-keys-default-state {
pins = "gpio107", "gpio117";
function = "gpio";
@@ -271,7 +271,7 @@
bias-pull-up;
};
- imu_default: imu-default {
+ imu_default: imu-default-state {
pins = "gpio36";
function = "gpio";
@@ -279,7 +279,7 @@
bias-disable;
};
- mag_reset_default: mag-reset-default {
+ mag_reset_default: mag-reset-default-state {
pins = "gpio112";
function = "gpio";
@@ -287,7 +287,7 @@
bias-disable;
};
- sd_vmmc_en_default: sd-vmmc-en-default {
+ sd_vmmc_en_default: sd-vmmc-en-default-state {
pins = "gpio87";
function = "gpio";
@@ -295,14 +295,16 @@
bias-disable;
};
- touchscreen_default: touchscreen-default {
- pins = "gpio13";
- function = "gpio";
+ touchscreen_default: touchscreen-default-state {
+ touch-pins {
+ pins = "gpio13";
+ function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
+ drive-strength = <2>;
+ bias-pull-up;
+ };
- reset {
+ reset-pins {
pins = "gpio12";
function = "gpio";
@@ -311,7 +313,7 @@
};
};
- usb_id_default: usb-id-default {
+ usb_id_default: usb-id-default-state {
pins = "gpio110";
function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts
index 9e470c67274e..8c07eca900d3 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
-// Copyright (C) 2021 Stephan Gerhold
+/*
+ * Copyright (C) 2021 Stephan Gerhold
+ */
/dts-v1/;
@@ -414,7 +416,7 @@
};
&msmgpio {
- accel_irq_default: accel-irq-default {
+ accel_irq_default: accel-irq-default-state {
pins = "gpio115";
function = "gpio";
@@ -422,7 +424,7 @@
bias-disable;
};
- gpio_keys_default: gpio-keys-default {
+ gpio_keys_default: gpio-keys-default-state {
pins = "gpio107";
function = "gpio";
@@ -430,7 +432,7 @@
bias-pull-up;
};
- gpio_leds_default: gpio-leds-default {
+ gpio_leds_default: gpio-leds-default-state {
pins = "gpio8", "gpio9", "gpio10";
function = "gpio";
@@ -438,7 +440,7 @@
bias-disable;
};
- nfc_default: nfc-default {
+ nfc_default: nfc-default-state {
pins = "gpio2", "gpio20", "gpio21";
function = "gpio";
@@ -446,7 +448,7 @@
bias-disable;
};
- mag_reset_default: mag-reset-default {
+ mag_reset_default: mag-reset-default-state {
pins = "gpio36";
function = "gpio";
@@ -454,7 +456,7 @@
bias-disable;
};
- prox_irq_default: prox-irq-default {
+ prox_irq_default: prox-irq-default-state {
pins = "gpio113";
function = "gpio";
@@ -462,7 +464,7 @@
bias-disable;
};
- reg_lcd_en_default: reg-lcd-en-default {
+ reg_lcd_en_default: reg-lcd-en-default-state {
pins = "gpio32", "gpio97";
function = "gpio";
@@ -470,7 +472,7 @@
bias-disable;
};
- sdhc2_cd_default: sdhc2-cd-default {
+ sdhc2_cd_default: sdhc2-cd-default-state {
pins = "gpio56";
function = "gpio";
@@ -478,7 +480,7 @@
bias-disable;
};
- ts_irq_default: ts-irq-default {
+ ts_irq_default: ts-irq-default-state {
pins = "gpio13";
function = "gpio";
@@ -486,7 +488,7 @@
bias-disable;
};
- usb_id_default: usb-id-default {
+ usb_id_default: usb-id-default-state {
pins = "gpio117";
function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts
index d85e7f7c0835..d1e8cf2f50c0 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts
@@ -22,7 +22,7 @@
};
reserved-memory {
- // wcnss.mdt is not relocatable, so it must be loaded at 0x8b600000
+ /* wcnss.mdt is not relocatable, so it must be loaded at 0x8b600000 */
/delete-node/ wcnss@89300000;
wcnss_mem: wcnss@8b600000 {
@@ -204,12 +204,12 @@
rmi4-f01@1 {
reg = <0x1>;
- syna,nosleep-mode = <1>; // Allow sleeping
+ syna,nosleep-mode = <1>; /* Allow sleeping */
};
rmi4-f12@12 {
reg = <0x12>;
- syna,sensor-type = <1>; // Touchscreen
+ syna,sensor-type = <1>; /* Touchscreen */
};
};
};
@@ -367,7 +367,7 @@
};
&msmgpio {
- accel_int_default: accel-int-default {
+ accel_int_default: accel-int-default-state {
pins = "gpio116";
function = "gpio";
@@ -375,7 +375,7 @@
bias-disable;
};
- camera_flash_default: camera-flash-default {
+ camera_flash_default: camera-flash-default-state {
pins = "gpio31", "gpio32";
function = "gpio";
@@ -383,7 +383,7 @@
bias-disable;
};
- ctp_pwr_en_default: ctp-pwr-en-default {
+ ctp_pwr_en_default: ctp-pwr-en-default-state {
pins = "gpio17";
function = "gpio";
@@ -391,7 +391,7 @@
bias-disable;
};
- gpio_keys_default: gpio-keys-default {
+ gpio_keys_default: gpio-keys-default-state {
pins = "gpio107";
function = "gpio";
@@ -399,7 +399,7 @@
bias-pull-up;
};
- gyro_int_default: gyro-int-default {
+ gyro_int_default: gyro-int-default-state {
pins = "gpio22", "gpio23";
function = "gpio";
@@ -407,7 +407,7 @@
bias-disable;
};
- light_int_default: light-int-default {
+ light_int_default: light-int-default-state {
pins = "gpio115";
function = "gpio";
@@ -415,7 +415,7 @@
bias-disable;
};
- magn_int_default: magn-int-default {
+ magn_int_default: magn-int-default-state {
pins = "gpio113";
function = "gpio";
@@ -423,7 +423,7 @@
bias-disable;
};
- tp_int_default: tp-int-default {
+ tp_int_default: tp-int-default-state {
pins = "gpio13";
function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts
index b4812f093b17..3899e11b9843 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts
@@ -234,7 +234,7 @@
};
&msmgpio {
- button_backlight_default: button-backlight-default {
+ button_backlight_default: button-backlight-default-state {
pins = "gpio17";
function = "gpio";
@@ -242,7 +242,7 @@
bias-disable;
};
- gpio_keys_default: gpio-keys-default {
+ gpio_keys_default: gpio-keys-default-state {
pins = "gpio107";
function = "gpio";
@@ -250,7 +250,7 @@
bias-pull-up;
};
- mag_reset_default: mag-reset-default {
+ mag_reset_default: mag-reset-default-state {
pins = "gpio111";
function = "gpio";
@@ -258,7 +258,7 @@
bias-disable;
};
- usb_id_default: usb-id-default {
+ usb_id_default: usb-id-default-state {
pins = "gpio110";
function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
index 7dedb91b9930..33dfcf318a81 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -5,8 +5,8 @@
&msmgpio {
- blsp1_uart1_default: blsp1-uart1-default {
- // TX, RX, CTS_N, RTS_N
+ blsp1_uart1_default: blsp1-uart1-default-state {
+ /* TX, RX, CTS_N, RTS_N */
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "blsp_uart1";
@@ -14,7 +14,7 @@
bias-disable;
};
- blsp1_uart1_sleep: blsp1-uart1-sleep {
+ blsp1_uart1_sleep: blsp1-uart1-sleep-state {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "gpio";
@@ -22,7 +22,7 @@
bias-pull-down;
};
- blsp1_uart2_default: blsp1-uart2-default {
+ blsp1_uart2_default: blsp1-uart2-default-state {
pins = "gpio4", "gpio5";
function = "blsp_uart2";
@@ -30,7 +30,7 @@
bias-disable;
};
- blsp1_uart2_sleep: blsp1-uart2-sleep {
+ blsp1_uart2_sleep: blsp1-uart2-sleep-state {
pins = "gpio4", "gpio5";
function = "gpio";
@@ -38,14 +38,15 @@
bias-pull-down;
};
- spi1_default: spi1-default {
- pins = "gpio0", "gpio1", "gpio3";
- function = "blsp_spi1";
+ spi1_default: spi1-default-state {
+ spi-pins {
+ pins = "gpio0", "gpio1", "gpio3";
+ function = "blsp_spi1";
- drive-strength = <12>;
- bias-disable;
-
- cs {
+ drive-strength = <12>;
+ bias-disable;
+ };
+ cs-pins {
pins = "gpio2";
function = "gpio";
@@ -55,7 +56,7 @@
};
};
- spi1_sleep: spi1-sleep {
+ spi1_sleep: spi1-sleep-state {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "gpio";
@@ -63,14 +64,15 @@
bias-pull-down;
};
- spi2_default: spi2-default {
- pins = "gpio4", "gpio5", "gpio7";
- function = "blsp_spi2";
+ spi2_default: spi2-default-state {
+ spi-pins {
+ pins = "gpio4", "gpio5", "gpio7";
+ function = "blsp_spi2";
- drive-strength = <12>;
- bias-disable;
-
- cs {
+ drive-strength = <12>;
+ bias-disable;
+ };
+ cs-pins {
pins = "gpio6";
function = "gpio";
@@ -80,7 +82,7 @@
};
};
- spi2_sleep: spi2-sleep {
+ spi2_sleep: spi2-sleep-state {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
function = "gpio";
@@ -88,14 +90,15 @@
bias-pull-down;
};
- spi3_default: spi3-default {
- pins = "gpio8", "gpio9", "gpio11";
- function = "blsp_spi3";
+ spi3_default: spi3-default-state {
+ spi-pins {
+ pins = "gpio8", "gpio9", "gpio11";
+ function = "blsp_spi3";
- drive-strength = <12>;
- bias-disable;
-
- cs {
+ drive-strength = <12>;
+ bias-disable;
+ };
+ cs-pins {
pins = "gpio10";
function = "gpio";
@@ -105,7 +108,7 @@
};
};
- spi3_sleep: spi3-sleep {
+ spi3_sleep: spi3-sleep-state {
pins = "gpio8", "gpio9", "gpio10", "gpio11";
function = "gpio";
@@ -113,14 +116,15 @@
bias-pull-down;
};
- spi4_default: spi4-default {
- pins = "gpio12", "gpio13", "gpio15";
- function = "blsp_spi4";
-
- drive-strength = <12>;
- bias-disable;
+ spi4_default: spi4-default-state {
+ spi-pins {
+ pins = "gpio12", "gpio13", "gpio15";
+ function = "blsp_spi4";
- cs {
+ drive-strength = <12>;
+ bias-disable;
+ };
+ cs-pins {
pins = "gpio14";
function = "gpio";
@@ -130,7 +134,7 @@
};
};
- spi4_sleep: spi4-sleep {
+ spi4_sleep: spi4-sleep-state {
pins = "gpio12", "gpio13", "gpio14", "gpio15";
function = "gpio";
@@ -138,14 +142,15 @@
bias-pull-down;
};
- spi5_default: spi5-default {
- pins = "gpio16", "gpio17", "gpio19";
- function = "blsp_spi5";
+ spi5_default: spi5-default-state {
+ spi-pins {
+ pins = "gpio16", "gpio17", "gpio19";
+ function = "blsp_spi5";
- drive-strength = <12>;
- bias-disable;
-
- cs {
+ drive-strength = <12>;
+ bias-disable;
+ };
+ cs-pins {
pins = "gpio18";
function = "gpio";
@@ -155,7 +160,7 @@
};
};
- spi5_sleep: spi5-sleep {
+ spi5_sleep: spi5-sleep-state {
pins = "gpio16", "gpio17", "gpio18", "gpio19";
function = "gpio";
@@ -163,14 +168,15 @@
bias-pull-down;
};
- spi6_default: spi6-default {
- pins = "gpio20", "gpio21", "gpio23";
- function = "blsp_spi6";
-
- drive-strength = <12>;
- bias-disable;
+ spi6_default: spi6-default-state {
+ spi-pins {
+ pins = "gpio20", "gpio21", "gpio23";
+ function = "blsp_spi6";
- cs {
+ drive-strength = <12>;
+ bias-disable;
+ };
+ cs-pins {
pins = "gpio22";
function = "gpio";
@@ -180,7 +186,7 @@
};
};
- spi6_sleep: spi6-sleep {
+ spi6_sleep: spi6-sleep-state {
pins = "gpio20", "gpio21", "gpio22", "gpio23";
function = "gpio";
@@ -188,7 +194,7 @@
bias-pull-down;
};
- i2c1_default: i2c1-default {
+ i2c1_default: i2c1-default-state {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
@@ -196,7 +202,7 @@
bias-disable;
};
- i2c1_sleep: i2c1-sleep {
+ i2c1_sleep: i2c1-sleep-state {
pins = "gpio2", "gpio3";
function = "gpio";
@@ -204,7 +210,7 @@
bias-disable;
};
- i2c2_default: i2c2-default {
+ i2c2_default: i2c2-default-state {
pins = "gpio6", "gpio7";
function = "blsp_i2c2";
@@ -212,7 +218,7 @@
bias-disable;
};
- i2c2_sleep: i2c2-sleep {
+ i2c2_sleep: i2c2-sleep-state {
pins = "gpio6", "gpio7";
function = "gpio";
@@ -220,7 +226,7 @@
bias-disable;
};
- i2c3_default: i2c3-default {
+ i2c3_default: i2c3-default-state {
pins = "gpio10", "gpio11";
function = "blsp_i2c3";
@@ -228,7 +234,7 @@
bias-disable;
};
- i2c3_sleep: i2c3-sleep {
+ i2c3_sleep: i2c3-sleep-state {
pins = "gpio10", "gpio11";
function = "gpio";
@@ -236,7 +242,7 @@
bias-disable;
};
- i2c4_default: i2c4-default {
+ i2c4_default: i2c4-default-state {
pins = "gpio14", "gpio15";
function = "blsp_i2c4";
@@ -244,7 +250,7 @@
bias-disable;
};
- i2c4_sleep: i2c4-sleep {
+ i2c4_sleep: i2c4-sleep-state {
pins = "gpio14", "gpio15";
function = "gpio";
@@ -252,7 +258,7 @@
bias-disable;
};
- i2c5_default: i2c5-default {
+ i2c5_default: i2c5-default-state {
pins = "gpio18", "gpio19";
function = "blsp_i2c5";
@@ -260,7 +266,7 @@
bias-disable;
};
- i2c5_sleep: i2c5-sleep {
+ i2c5_sleep: i2c5-sleep-state {
pins = "gpio18", "gpio19";
function = "gpio";
@@ -268,7 +274,7 @@
bias-disable;
};
- i2c6_default: i2c6-default {
+ i2c6_default: i2c6-default-state {
pins = "gpio22", "gpio23";
function = "blsp_i2c6";
@@ -276,7 +282,7 @@
bias-disable;
};
- i2c6_sleep: i2c6-sleep {
+ i2c6_sleep: i2c6-sleep-state {
pins = "gpio22", "gpio23";
function = "gpio";
@@ -284,14 +290,14 @@
bias-disable;
};
- pmx-sdc1-clk {
- sdc1_clk_on: clk-on {
+ pmx-sdc1-clk-state {
+ sdc1_clk_on: clk-on-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
- sdc1_clk_off: clk-off {
+ sdc1_clk_off: clk-off-pins {
pins = "sdc1_clk";
bias-disable;
@@ -299,14 +305,14 @@
};
};
- pmx-sdc1-cmd {
- sdc1_cmd_on: cmd-on {
+ pmx-sdc1-cmd-state {
+ sdc1_cmd_on: cmd-on-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
- sdc1_cmd_off: cmd-off {
+ sdc1_cmd_off: cmd-off-pins {
pins = "sdc1_cmd";
bias-pull-up;
@@ -314,14 +320,14 @@
};
};
- pmx-sdc1-data {
- sdc1_data_on: data-on {
+ pmx-sdc1-data-state {
+ sdc1_data_on: data-on-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
- sdc1_data_off: data-off {
+ sdc1_data_off: data-off-pins {
pins = "sdc1_data";
bias-pull-up;
@@ -329,14 +335,14 @@
};
};
- pmx-sdc2-clk {
- sdc2_clk_on: clk-on {
+ pmx-sdc2-clk-state {
+ sdc2_clk_on: clk-on-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
- sdc2_clk_off: clk-off {
+ sdc2_clk_off: clk-off-pins {
pins = "sdc2_clk";
bias-disable;
@@ -344,14 +350,14 @@
};
};
- pmx-sdc2-cmd {
- sdc2_cmd_on: cmd-on {
+ pmx-sdc2-cmd-state {
+ sdc2_cmd_on: cmd-on-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
- sdc2_cmd_off: cmd-off {
+ sdc2_cmd_off: cmd-off-pins {
pins = "sdc2_cmd";
bias-pull-up;
@@ -359,14 +365,14 @@
};
};
- pmx-sdc2-data {
- sdc2_data_on: data-on {
+ pmx-sdc2-data-state {
+ sdc2_data_on: data-on-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
- sdc2_data_off: data-off {
+ sdc2_data_off: data-off-pins {
pins = "sdc2_data";
bias-pull-up;
@@ -374,15 +380,15 @@
};
};
- pmx-sdc2-cd-pin {
- sdc2_cd_on: cd-on {
+ pmx-sdc2-cd-pin-state {
+ sdc2_cd_on: cd-on-pins {
pins = "gpio38";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
- sdc2_cd_off: cd-off {
+ sdc2_cd_off: cd-off-pins {
pins = "gpio38";
function = "gpio";
@@ -391,8 +397,8 @@
};
};
- cdc-pdm-lines {
- cdc_pdm_lines_act: pdm-lines-on {
+ cdc-pdm-lines-state {
+ cdc_pdm_lines_act: pdm-lines-on-pins {
pins = "gpio63", "gpio64", "gpio65", "gpio66",
"gpio67", "gpio68";
function = "cdc_pdm0";
@@ -400,7 +406,7 @@
drive-strength = <8>;
bias-disable;
};
- cdc_pdm_lines_sus: pdm-lines-off {
+ cdc_pdm_lines_sus: pdm-lines-off-pins {
pins = "gpio63", "gpio64", "gpio65", "gpio66",
"gpio67", "gpio68";
function = "cdc_pdm0";
@@ -410,15 +416,15 @@
};
};
- ext-pri-tlmm-lines {
- ext_pri_tlmm_lines_act: ext-pa-on {
+ ext-pri-tlmm-lines-state {
+ ext_pri_tlmm_lines_act: ext-pa-on-pins {
pins = "gpio113", "gpio114", "gpio115", "gpio116";
function = "pri_mi2s";
drive-strength = <8>;
bias-disable;
};
- ext_pri_tlmm_lines_sus: ext-pa-off {
+ ext_pri_tlmm_lines_sus: ext-pa-off-pins {
pins = "gpio113", "gpio114", "gpio115", "gpio116";
function = "pri_mi2s";
@@ -427,15 +433,15 @@
};
};
- ext-pri-ws-line {
- ext_pri_ws_act: ext-pa-on {
+ ext-pri-ws-line-state {
+ ext_pri_ws_act: ext-pa-on-pins {
pins = "gpio110";
function = "pri_mi2s_ws";
drive-strength = <8>;
bias-disable;
};
- ext_pri_ws_sus: ext-pa-off {
+ ext_pri_ws_sus: ext-pa-off-pins {
pins = "gpio110";
function = "pri_mi2s_ws";
@@ -444,15 +450,15 @@
};
};
- ext-mclk-tlmm-lines {
- ext_mclk_tlmm_lines_act: mclk-lines-on {
+ ext-mclk-tlmm-lines-state {
+ ext_mclk_tlmm_lines_act: mclk-lines-on-pins {
pins = "gpio116";
function = "pri_mi2s";
drive-strength = <8>;
bias-disable;
};
- ext_mclk_tlmm_lines_sus: mclk-lines-off {
+ ext_mclk_tlmm_lines_sus: mclk-lines-off-pins {
pins = "gpio116";
function = "pri_mi2s";
@@ -462,15 +468,15 @@
};
/* secondary Mi2S */
- ext-sec-tlmm-lines {
- ext_sec_tlmm_lines_act: tlmm-lines-on {
+ ext-sec-tlmm-lines-state {
+ ext_sec_tlmm_lines_act: tlmm-lines-on-pins {
pins = "gpio112", "gpio117", "gpio118", "gpio119";
function = "sec_mi2s";
drive-strength = <8>;
bias-disable;
};
- ext_sec_tlmm_lines_sus: tlmm-lines-off {
+ ext_sec_tlmm_lines_sus: tlmm-lines-off-pins {
pins = "gpio112", "gpio117", "gpio118", "gpio119";
function = "sec_mi2s";
@@ -479,40 +485,38 @@
};
};
- cdc-dmic-lines {
- cdc_dmic_lines_act: dmic-lines-on {
- clk {
- pins = "gpio0";
- function = "dmic0_clk";
+ cdc_dmic_lines_act: cdc-dmic-lines-on-state {
+ clk-pins {
+ pins = "gpio0";
+ function = "dmic0_clk";
- drive-strength = <8>;
- };
- data {
- pins = "gpio1";
- function = "dmic0_data";
+ drive-strength = <8>;
+ };
+ data-pins {
+ pins = "gpio1";
+ function = "dmic0_data";
- drive-strength = <8>;
- };
+ drive-strength = <8>;
};
- cdc_dmic_lines_sus: dmic-lines-off {
- clk {
- pins = "gpio0";
- function = "dmic0_clk";
+ };
+ cdc_dmic_lines_sus: cdc-dmic-lines-off-state {
+ clk-pins {
+ pins = "gpio0";
+ function = "dmic0_clk";
- drive-strength = <2>;
- bias-disable;
- };
- data {
- pins = "gpio1";
- function = "dmic0_data";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ data-pins {
+ pins = "gpio1";
+ function = "dmic0_data";
- drive-strength = <2>;
- bias-disable;
- };
+ drive-strength = <2>;
+ bias-disable;
};
};
- wcnss_pin_a: wcnss-active {
+ wcnss_pin_a: wcnss-active-state {
pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
function = "wcss_wlan";
@@ -520,7 +524,7 @@
bias-pull-up;
};
- cci0_default: cci0-default {
+ cci0_default: cci0-default-state {
pins = "gpio29", "gpio30";
function = "cci_i2c";
@@ -528,22 +532,22 @@
bias-disable;
};
- camera_front_default: camera-front-default {
- pwdn {
+ camera_front_default: camera-front-default-state {
+ pwdn-pins {
pins = "gpio33";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
- rst {
+ rst-pins {
pins = "gpio28";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
- mclk1 {
+ mclk1-pins {
pins = "gpio27";
function = "cam_mclk1";
@@ -552,22 +556,22 @@
};
};
- camera_rear_default: camera-rear-default {
- pwdn {
+ camera_rear_default: camera-rear-default-state {
+ pwdn-pins {
pins = "gpio34";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
- rst {
+ rst-pins {
pins = "gpio35";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
- mclk0 {
+ mclk0-pins {
pins = "gpio26";
function = "cam_mclk0";
diff --git a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi
index 539823b2c36e..8cac23b5240c 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi
@@ -47,7 +47,7 @@
};
&rpm_requests {
- smd_rpm_regulators: pm8916-regulators {
+ smd_rpm_regulators: regulators {
compatible = "qcom,rpm-pm8916-regulators";
/* pm8916_s1 is managed by rpmpd (MSM8916_VDDCX) */
diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
index 3255bd3fcb55..d600916a0e55 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
@@ -23,6 +23,17 @@
};
};
+ clk_pwm: pwm {
+ compatible = "clk-pwm";
+ #pwm-cells = <2>;
+
+ clocks = <&gcc GCC_GP2_CLK>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&motor_pwm_default>;
+ status = "disabled";
+ };
+
gpio-keys {
compatible = "gpio-keys";
@@ -61,6 +72,24 @@
};
};
+ /*
+ * NOTE: A5 connects GPIO 76 to a reglator powering the motor
+ * driver IC but A3 connects the same signal to an ENABLE pin of
+ * the driver.
+ */
+ reg_motor_vdd: regulator-motor-vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "motor_vdd";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+
+ gpio = <&msmgpio 76 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&motor_en_default>;
+ };
+
reg_vdd_tsp_a: regulator-vdd-tsp-a {
compatible = "regulator-fixed";
regulator-name = "vdd_tsp_a";
@@ -144,7 +173,7 @@
interrupt-parent = <&msmgpio>;
interrupts = <21 IRQ_TYPE_EDGE_RISING>;
- en-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>;
+ en-gpios = <&msmgpio 20 GPIO_ACTIVE_LOW>;
wake-gpios = <&msmgpio 49 GPIO_ACTIVE_HIGH>;
clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>;
@@ -153,6 +182,16 @@
pinctrl-0 = <&nfc_default &nfc_clk_req>;
};
};
+
+ vibrator: vibrator {
+ compatible = "pwm-vibrator";
+
+ pwms = <&clk_pwm 0 100000>;
+ pwm-names = "enable";
+
+ vcc-supply = <&reg_motor_vdd>;
+ status = "disabled";
+ };
};
&blsp_i2c2 {
@@ -348,7 +387,7 @@
};
&msmgpio {
- accel_int_default: accel-int-default {
+ accel_int_default: accel-int-default-state {
pins = "gpio115";
function = "gpio";
@@ -356,7 +395,7 @@
bias-disable;
};
- fg_alert_default: fg-alert-default {
+ fg_alert_default: fg-alert-default-state {
pins = "gpio121";
function = "gpio";
@@ -364,7 +403,7 @@
bias-disable;
};
- gpio_keys_default: gpio-keys-default {
+ gpio_keys_default: gpio-keys-default-state {
pins = "gpio107", "gpio109";
function = "gpio";
@@ -372,7 +411,7 @@
bias-pull-up;
};
- gpio_hall_sensor_default: gpio-hall-sensor-default {
+ gpio_hall_sensor_default: gpio-hall-sensor-default-state {
pins = "gpio52";
function = "gpio";
@@ -380,47 +419,60 @@
bias-disable;
};
- mdss {
- mdss_default: mdss-default {
- pins = "gpio25";
- function = "gpio";
+ mdss_default: mdss-default-state {
+ pins = "gpio25";
+ function = "gpio";
- drive-strength = <8>;
- bias-disable;
- };
- mdss_sleep: mdss-sleep {
- pins = "gpio25";
- function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ mdss_sleep: mdss-sleep-state {
+ pins = "gpio25";
+ function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- };
+ drive-strength = <2>;
+ bias-pull-down;
};
- muic_i2c_default: muic-i2c-default {
- pins = "gpio105", "gpio106";
+ motor_en_default: motor-en-default-stae {
+ pins = "gpio76";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- muic_int_default: muic-int-default {
- pins = "gpio12";
+ motor_pwm_default: motor-pwm-default-state {
+ pins = "gpio50";
+ function = "gcc_gp2_clk_a";
+ };
+
+ muic_i2c_default: muic-i2c-default-state {
+ pins = "gpio105", "gpio106";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- nfc_default: nfc-default {
- pins = "gpio20", "gpio49";
+ muic_int_default: muic-int-default-state {
+ pins = "gpio12";
function = "gpio";
drive-strength = <2>;
bias-disable;
+ };
+
+ nfc_default: nfc-default-state {
+ nfc-pins {
+ pins = "gpio20", "gpio49";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
- irq {
+ irq-pins {
pins = "gpio21";
function = "gpio";
@@ -429,7 +481,7 @@
};
};
- nfc_i2c_default: nfc-i2c-default {
+ nfc_i2c_default: nfc-i2c-default-state {
pins = "gpio0", "gpio1";
function = "gpio";
@@ -437,7 +489,7 @@
bias-disable;
};
- tkey_default: tkey-default {
+ tkey_default: tkey-default-state {
pins = "gpio98";
function = "gpio";
@@ -445,7 +497,7 @@
bias-disable;
};
- tkey_i2c_default: tkey-i2c-default {
+ tkey_i2c_default: tkey-i2c-default-state {
pins = "gpio16", "gpio17";
function = "gpio";
@@ -453,7 +505,7 @@
bias-disable;
};
- tsp_en_default: tsp-en-default {
+ tsp_en_default: tsp-en-default-state {
pins = "gpio73";
function = "gpio";
@@ -461,7 +513,7 @@
bias-disable;
};
- ts_int_default: ts-int-default {
+ ts_int_default: ts-int-default-state {
pins = "gpio13";
function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
index 6db5f78ca286..c691cca2eb45 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
@@ -81,6 +81,10 @@
};
};
+&clk_pwm {
+ status = "okay";
+};
+
&dsi0 {
panel@0 {
reg = <0>;
@@ -104,8 +108,12 @@
remote-endpoint = <&panel_in>;
};
+&vibrator {
+ status = "okay";
+};
+
&msmgpio {
- panel_vdd3_default: panel-vdd3-default {
+ panel_vdd3_default: panel-vdd3-default-state {
pins = "gpio9";
function = "gpio";
@@ -113,7 +121,7 @@
bias-disable;
};
- tkey_en_default: tkey-en-default {
+ tkey_en_default: tkey-en-default-state {
pins = "gpio86";
function = "gpio";
@@ -121,7 +129,7 @@
bias-disable;
};
- tkey_led_en_default: tkey-led-en-default {
+ tkey_led_en_default: tkey-led-en-default-state {
pins = "gpio60";
function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts
index 5fb8ecd0c9ca..3dd819458785 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts
@@ -50,6 +50,10 @@
};
};
+&clk_pwm {
+ status = "okay";
+};
+
&pronto {
iris {
compatible = "qcom,wcn3660b";
@@ -61,8 +65,12 @@
vdd-supply = <&reg_touch_key>;
};
+&vibrator {
+ status = "okay";
+};
+
&msmgpio {
- tkey_en_default: tkey-en-default {
+ tkey_en_default: tkey-en-default-state {
pins = "gpio97";
function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi
index 542010fdfb8a..c95f0b4bc61f 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi
@@ -26,19 +26,6 @@
};
};
- reg_motor_vdd: regulator-motor-vdd {
- compatible = "regulator-fixed";
- regulator-name = "motor_vdd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&msmgpio 76 GPIO_ACTIVE_HIGH>;
- enable-active-high;
-
- pinctrl-names = "default";
- pinctrl-0 = <&motor_en_default>;
- };
-
reg_touch_key: regulator-touch-key {
compatible = "regulator-fixed";
regulator-name = "touch_key";
@@ -61,21 +48,18 @@
/delete-node/ magnetometer@12;
};
+&reg_motor_vdd {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+};
+
&touchkey {
vcc-supply = <&reg_touch_key>;
vdd-supply = <&reg_touch_key>;
};
&msmgpio {
- motor_en_default: motor-en-default {
- pins = "gpio76";
- function = "gpio";
-
- drive-strength = <2>;
- bias-disable;
- };
-
- tkey_en_default: tkey-en-default {
+ tkey_en_default: tkey-en-default-state {
pins = "gpio97";
function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts
index bc7134698978..a3d572d851ef 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts
@@ -46,7 +46,7 @@
};
&msmgpio {
- gpio_leds_default: gpio-led-default {
+ gpio_leds_default: gpio-led-default-state {
pins = "gpio60";
function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts
index eabeed18cfaa..7ac49a021563 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts
@@ -199,7 +199,7 @@
};
&msmgpio {
- gpio_keys_default: gpio-keys-default {
+ gpio_keys_default: gpio-keys-default-state {
pins = "gpio107", "gpio109";
function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts
index bbd6bb3f4fd7..d4984b3af802 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
-// Copyright (C) 2019 Stephan Gerhold
+/*
+ * Copyright (C) 2019 Stephan Gerhold
+ */
/dts-v1/;
@@ -422,7 +424,7 @@
};
&msmgpio {
- fg_alert_default: fg-alert-default {
+ fg_alert_default: fg-alert-default-state {
pins = "gpio121";
function = "gpio";
@@ -430,7 +432,7 @@
bias-disable;
};
- gpio_keys_default: gpio-keys-default {
+ gpio_keys_default: gpio-keys-default-state {
pins = "gpio107", "gpio109";
function = "gpio";
@@ -438,7 +440,7 @@
bias-pull-up;
};
- gpio_hall_sensor_default: gpio-hall-sensor-default {
+ gpio_hall_sensor_default: gpio-hall-sensor-default-state {
pins = "gpio52";
function = "gpio";
@@ -446,7 +448,7 @@
bias-disable;
};
- imu_irq_default: imu-irq-default {
+ imu_irq_default: imu-irq-default-state {
pins = "gpio115";
function = "gpio";
@@ -454,7 +456,7 @@
bias-disable;
};
- muic_i2c_default: muic-i2c-default {
+ muic_i2c_default: muic-i2c-default-state {
pins = "gpio105", "gpio106";
function = "gpio";
@@ -462,7 +464,7 @@
bias-disable;
};
- muic_irq_default: muic-irq-default {
+ muic_irq_default: muic-irq-default-state {
pins = "gpio12";
function = "gpio";
@@ -470,14 +472,15 @@
bias-disable;
};
- nfc_default: nfc-default {
- pins = "gpio20", "gpio49";
- function = "gpio";
-
- drive-strength = <2>;
- bias-disable;
+ nfc_default: nfc-default-state {
+ nfc-pins {
+ pins = "gpio20", "gpio49";
+ function = "gpio";
- irq {
+ drive-strength = <2>;
+ bias-disable;
+ };
+ irq-pins {
pins = "gpio21";
function = "gpio";
@@ -486,7 +489,7 @@
};
};
- nfc_i2c_default: nfc-i2c-default {
+ nfc_i2c_default: nfc-i2c-default-state {
pins = "gpio0", "gpio1";
function = "gpio";
@@ -494,7 +497,7 @@
bias-disable;
};
- tkey_default: tkey-default {
+ tkey_default: tkey-default-state {
pins = "gpio98";
function = "gpio";
@@ -502,7 +505,7 @@
bias-disable;
};
- tkey_en_default: tkey-en-default {
+ tkey_en_default: tkey-en-default-state {
pins = "gpio86";
function = "gpio";
@@ -510,7 +513,7 @@
bias-disable;
};
- tkey_i2c_default: tkey-i2c-default {
+ tkey_i2c_default: tkey-i2c-default-state {
pins = "gpio16", "gpio17";
function = "gpio";
@@ -518,7 +521,7 @@
bias-disable;
};
- tkey_led_en_default: tkey-led-en-default {
+ tkey_led_en_default: tkey-led-en-default-state {
pins = "gpio60";
function = "gpio";
@@ -526,7 +529,7 @@
bias-disable;
};
- tsp_en_default: tsp-en-default {
+ tsp_en_default: tsp-en-default-state {
pins = "gpio73";
function = "gpio";
@@ -534,7 +537,7 @@
bias-disable;
};
- tsp_irq_default: tsp-irq-default {
+ tsp_irq_default: tsp-irq-default-state {
pins = "gpio13";
function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts
index 84a352dcf9a2..a87be1d95b14 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
-// Copyright (C) 2020 Stephan Gerhold
+/*
+ * Copyright (C) 2020 Stephan Gerhold
+ */
/dts-v1/;
@@ -21,6 +23,20 @@
stdout-path = "serial0";
};
+ flash-led-controller {
+ compatible = "ocs,ocp8110";
+ enable-gpios = <&msmgpio 31 GPIO_ACTIVE_HIGH>;
+ flash-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&camera_flash_default>;
+
+ flash_led: led {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
@@ -272,7 +288,15 @@
};
&msmgpio {
- gpio_keys_default: gpio-keys-default {
+ camera_flash_default: camera-flash-default-state {
+ pins = "gpio31", "gpio32";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ gpio_keys_default: gpio-keys-default-state {
pins = "gpio107";
function = "gpio";
@@ -280,7 +304,7 @@
bias-pull-up;
};
- imu_default: imu-default {
+ imu_default: imu-default-state {
pins = "gpio115";
function = "gpio";
@@ -288,14 +312,15 @@
bias-disable;
};
- touchscreen_default: touchscreen-default {
- pins = "gpio13";
- function = "gpio";
-
- drive-strength = <2>;
- bias-pull-up;
+ touchscreen_default: touchscreen-default-state {
+ touchscreen-pins {
+ pins = "gpio13";
+ function = "gpio";
- reset {
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ reset-pins {
pins = "gpio12";
function = "gpio";
@@ -304,7 +329,7 @@
};
};
- usb_id_default: usb-id-default {
+ usb_id_default: usb-id-default-state {
pins = "gpio110";
function = "gpio";
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index a831064700ee..2ca8e977fc2a 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -1046,7 +1046,6 @@
"pixel",
"core";
phys = <&dsi_phy0>;
- phy-names = "dsi-phy";
#address-cells = <1>;
#size-cells = <0>;
@@ -1070,7 +1069,7 @@
};
};
- dsi_phy0: dsi-phy@1a98300 {
+ dsi_phy0: phy@1a98300 {
compatible = "qcom,dsi-phy-28nm-lp";
reg = <0x01a98300 0xd4>,
<0x01a98500 0x280>,
@@ -1264,21 +1263,21 @@
clock-names = "iface", "bus";
qcom,iommu-secure-id = <17>;
- // vfe:
+ /* VFE */
iommu-ctx@3000 {
compatible = "qcom,msm-iommu-v1-sec";
reg = <0x3000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
};
- // mdp_0:
+ /* MDP_0 */
iommu-ctx@4000 {
compatible = "qcom,msm-iommu-v1-ns";
reg = <0x4000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
};
- // venus_ns:
+ /* VENUS_NS */
iommu-ctx@5000 {
compatible = "qcom,msm-iommu-v1-sec";
reg = <0x5000 0x1000>;
@@ -1297,14 +1296,14 @@
clock-names = "iface", "bus";
qcom,iommu-secure-id = <18>;
- // gfx3d_user:
+ /* GFX3D_USER */
iommu-ctx@1000 {
compatible = "qcom,msm-iommu-v1-ns";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
};
- // gfx3d_priv:
+ /* GFX3D_PRIV */
iommu-ctx@2000 {
compatible = "qcom,msm-iommu-v1-ns";
reg = <0x2000 0x1000>;
@@ -1345,7 +1344,7 @@
};
mpss: remoteproc@4080000 {
- compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil";
+ compatible = "qcom,msm8916-mss-pil";
reg = <0x04080000 0x100>,
<0x04020000 0x040>;
@@ -1438,7 +1437,7 @@
lpass: audio-controller@7708000 {
status = "disabled";
- compatible = "qcom,lpass-cpu-apq8016";
+ compatible = "qcom,apq8016-lpass-cpu";
/*
* Note: Unlike the name would suggest, the SEC_I2S_CLK
diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index 6b992a6d56c1..32349174c4bd 100644
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -460,229 +460,229 @@
interrupt-controller;
#interrupt-cells = <2>;
- uart_console_active: uart-console-active-pins {
+ uart_console_active: uart-console-active-state {
pins = "gpio4", "gpio5";
function = "blsp_uart2";
drive-strength = <2>;
bias-disable;
};
- uart_console_sleep: uart-console-sleep-pins {
+ uart_console_sleep: uart-console-sleep-state {
pins = "gpio4", "gpio5";
function = "blsp_uart2";
drive-strength = <2>;
bias-pull-down;
};
- sdc1_clk_on: sdc1-clk-on-pins {
+ sdc1_clk_on: sdc1-clk-on-state {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
- sdc1_clk_off: sdc1-clk-off-pins {
+ sdc1_clk_off: sdc1-clk-off-state {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
- sdc1_cmd_on: sdc1-cmd-on-pins {
+ sdc1_cmd_on: sdc1-cmd-on-state {
pins = "sdc1_cmd";
bias-disable;
drive-strength = <10>;
};
- sdc1_cmd_off: sdc1-cmd-off-pins {
+ sdc1_cmd_off: sdc1-cmd-off-state {
pins = "sdc1_cmd";
bias-disable;
drive-strength = <2>;
};
- sdc1_data_on: sdc1-data-on-pins {
+ sdc1_data_on: sdc1-data-on-state {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
- sdc1_data_off: sdc1-data-off-pins {
+ sdc1_data_off: sdc1-data-off-state {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
- sdc1_rclk_on: sdc1-rclk-on-pins {
+ sdc1_rclk_on: sdc1-rclk-on-state {
pins = "sdc1_rclk";
bias-pull-down;
};
- sdc1_rclk_off: sdc1-rclk-off-pins {
+ sdc1_rclk_off: sdc1-rclk-off-state {
pins = "sdc1_rclk";
bias-pull-down;
};
- sdc2_clk_on: sdc2-clk-on-pins {
+ sdc2_clk_on: sdc2-clk-on-state {
pins = "sdc2_clk";
drive-strength = <16>;
bias-disable;
};
- sdc2_clk_off: sdc2-clk-off-pins {
+ sdc2_clk_off: sdc2-clk-off-state {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
- sdc2_cmd_on: sdc2-cmd-on-pins {
+ sdc2_cmd_on: sdc2-cmd-on-state {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
- sdc2_cmd_off: sdc2-cmd-off-pins {
+ sdc2_cmd_off: sdc2-cmd-off-state {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
- sdc2_data_on: sdc2-data-on-pins {
+ sdc2_data_on: sdc2-data-on-state {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
- sdc2_data_off: sdc2-data-off-pins {
+ sdc2_data_off: sdc2-data-off-state {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
};
- sdc2_cd_on: cd-on-pins {
+ sdc2_cd_on: cd-on-state {
pins = "gpio133";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
- sdc2_cd_off: cd-off-pins {
+ sdc2_cd_off: cd-off-state {
pins = "gpio133";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- gpio_key_default: gpio-key-default-pins {
+ gpio_key_default: gpio-key-default-state {
pins = "gpio85";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
- i2c_1_default: i2c-1-default-pins {
+ i2c_1_default: i2c-1-default-state {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
drive-strength = <2>;
bias-disable;
};
- i2c_1_sleep: i2c-1-sleep-pins {
+ i2c_1_sleep: i2c-1-sleep-state {
pins = "gpio2", "gpio3";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- i2c_2_default: i2c-2-default-pins {
+ i2c_2_default: i2c-2-default-state {
pins = "gpio6", "gpio7";
function = "blsp_i2c2";
drive-strength = <2>;
bias-disable;
};
- i2c_2_sleep: i2c-2-sleep-pins {
+ i2c_2_sleep: i2c-2-sleep-state {
pins = "gpio6", "gpio7";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- i2c_3_default: i2c-3-default-pins {
+ i2c_3_default: i2c-3-default-state {
pins = "gpio10", "gpio11";
function = "blsp_i2c3";
drive-strength = <2>;
bias-disable;
};
- i2c_3_sleep: i2c-3-sleep-pins {
+ i2c_3_sleep: i2c-3-sleep-state {
pins = "gpio10", "gpio11";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- i2c_4_default: i2c-4-default-pins {
+ i2c_4_default: i2c-4-default-state {
pins = "gpio14", "gpio15";
function = "blsp_i2c4";
drive-strength = <2>;
bias-disable;
};
- i2c_4_sleep: i2c-4-sleep-pins {
+ i2c_4_sleep: i2c-4-sleep-state {
pins = "gpio14", "gpio15";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- i2c_5_default: i2c-5-default-pins {
+ i2c_5_default: i2c-5-default-state {
pins = "gpio18", "gpio19";
function = "blsp_i2c5";
drive-strength = <2>;
bias-disable;
};
- i2c_5_sleep: i2c-5-sleep-pins {
+ i2c_5_sleep: i2c-5-sleep-state {
pins = "gpio18", "gpio19";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- i2c_6_default: i2c-6-default-pins {
+ i2c_6_default: i2c-6-default-state {
pins = "gpio22", "gpio23";
function = "blsp_i2c6";
drive-strength = <2>;
bias-disable;
};
- i2c_6_sleep: i2c-6-sleep-pins {
+ i2c_6_sleep: i2c-6-sleep-state {
pins = "gpio22", "gpio23";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- i2c_7_default: i2c-7-default-pins {
+ i2c_7_default: i2c-7-default-state {
pins = "gpio135", "gpio136";
function = "blsp_i2c7";
drive-strength = <2>;
bias-disable;
};
- i2c_7_sleep: i2c-7-sleep-pins {
+ i2c_7_sleep: i2c-7-sleep-state {
pins = "gpio135", "gpio136";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- i2c_8_default: i2c-8-default-pins {
+ i2c_8_default: i2c-8-default-state {
pins = "gpio98", "gpio99";
function = "blsp_i2c8";
drive-strength = <2>;
bias-disable;
};
- i2c_8_sleep: i2c-8-sleep-pins {
+ i2c_8_sleep: i2c-8-sleep-state {
pins = "gpio98", "gpio99";
function = "gpio";
drive-strength = <2>;
@@ -726,6 +726,250 @@
reg = <0x193f044 0x4>;
};
+ mdss: mdss@1a00000 {
+ compatible = "qcom,mdss";
+
+ reg = <0x1a00000 0x1000>,
+ <0x1ab0000 0x1040>;
+ reg-names = "mdss_phys",
+ "vbif_phys";
+
+ power-domains = <&gcc MDSS_GDSC>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_VSYNC_CLK>,
+ <&gcc GCC_MDSS_MDP_CLK>;
+ clock-names = "iface",
+ "bus",
+ "vsync",
+ "core";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ status = "disabled";
+
+ mdp: mdp@1a01000 {
+ compatible = "qcom,msm8953-mdp5", "qcom,mdp5";
+ reg = <0x1a01000 0x89000>;
+ reg-names = "mdp_phys";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ power-domains = <&gcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_MDP_CLK>,
+ <&gcc GCC_MDSS_VSYNC_CLK>;
+ clock-names = "iface",
+ "bus",
+ "core",
+ "vsync";
+
+ iommus = <&apps_iommu 0x15>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdp5_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdp5_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+
+ dsi0: dsi@1a94000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0x1a94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ assigned-clocks = <&gcc BYTE0_CLK_SRC>,
+ <&gcc PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi0_phy 0>,
+ <&dsi0_phy 1>;
+
+ clocks = <&gcc GCC_MDSS_MDP_CLK>,
+ <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_BYTE0_CLK>,
+ <&gcc GCC_MDSS_PCLK0_CLK>,
+ <&gcc GCC_MDSS_ESC0_CLK>;
+ clock-names = "mdp_core",
+ "iface",
+ "bus",
+ "byte",
+ "pixel",
+ "core";
+
+ phys = <&dsi0_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&mdp5_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi0_phy: phy@1a94400 {
+ compatible = "qcom,dsi-phy-14nm-8953";
+ reg = <0x1a94400 0x100>,
+ <0x1a94500 0x300>,
+ <0x1a94800 0x188>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
+ dsi1: dsi@1a96000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0x1a96000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <5>;
+
+ assigned-clocks = <&gcc BYTE1_CLK_SRC>,
+ <&gcc PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&dsi1_phy 0>,
+ <&dsi1_phy 1>;
+
+ clocks = <&gcc GCC_MDSS_MDP_CLK>,
+ <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_BYTE1_CLK>,
+ <&gcc GCC_MDSS_PCLK1_CLK>,
+ <&gcc GCC_MDSS_ESC1_CLK>;
+ clock-names = "mdp_core",
+ "iface",
+ "bus",
+ "byte",
+ "pixel",
+ "core";
+
+ phys = <&dsi1_phy>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi1_in: endpoint {
+ remote-endpoint = <&mdp5_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi1_phy: phy@1a96400 {
+ compatible = "qcom,dsi-phy-14nm-8953";
+ reg = <0x1a96400 0x100>,
+ <0x1a96500 0x300>,
+ <0x1a96800 0x188>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+ };
+
+ apps_iommu: iommu@1e00000 {
+ compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1";
+ ranges = <0 0x1e20000 0x20000>;
+
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
+ <&gcc GCC_APSS_TCU_ASYNC_CLK>;
+ clock-names = "iface", "bus";
+
+ qcom,iommu-secure-id = <17>;
+
+ #address-cells = <1>;
+ #iommu-cells = <1>;
+ #size-cells = <1>;
+
+ /* VFE */
+ iommu-ctx@14000 {
+ compatible = "qcom,msm-iommu-v1-ns";
+ reg = <0x14000 0x1000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ /* MDP_0 */
+ iommu-ctx@15000 {
+ compatible = "qcom,msm-iommu-v1-ns";
+ reg = <0x15000 0x1000>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ /* VENUS_NS */
+ iommu-ctx@16000 {
+ compatible = "qcom,msm-iommu-v1-ns";
+ reg = <0x16000 0x1000>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
spmi_bus: spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x200f000 0x1000>,
diff --git a/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-kugo.dts b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-kugo.dts
new file mode 100644
index 000000000000..3fb8e23e4330
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-kugo.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
+ * <angelogioacchino.delregno@somainline.org>
+ * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org>
+ * Copyright (c) 2022, Marijn Suijten <marijn.suijten@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "msm8956-sony-xperia-loire.dtsi"
+
+/ {
+ model = "Sony Xperia X Compact";
+ compatible = "sony,kugo-row", "qcom,msm8956";
+ chassis-type = "handset";
+};
+
+&blsp2_i2c2 {
+ status = "okay";
+
+ /* FUSB301 USB-C Controller */
+};
+
+&blsp2_i2c4 {
+ status = "okay";
+
+ /* ST STMVL53L0 ToF @ 29 */
+ /* AMS TCS349 RGBCIR @ 72 */
+};
+
+&pm8950_l1 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-suzu.dts b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-suzu.dts
new file mode 100644
index 000000000000..87d657f6806b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-suzu.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
+ * <angelogioacchino.delregno@somainline.org>
+ * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org>
+ * Copyright (c) 2022, Marijn Suijten <marijn.suijten@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "msm8956-sony-xperia-loire.dtsi"
+
+/ {
+ model = "Sony Xperia X";
+ compatible = "sony,suzu-row", "qcom,msm8956";
+ chassis-type = "handset";
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi
new file mode 100644
index 000000000000..67baced639c9
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
+ * <angelogioacchino.delregno@somainline.org>
+ * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org>
+ * Copyright (c) 2022, Marijn Suijten <marijn.suijten@somainline.org>
+ */
+
+#include "msm8956.dtsi"
+
+#include "pm8004.dtsi"
+#include "pm8950.dtsi"
+#include "pmi8950.dtsi"
+
+/ {
+ qcom,msm-id = <266 0x10001>; /* MSM8956 v1.1 */
+ qcom,board-id = <8 0>;
+
+ aliases {
+ mmc0 = &sdhc_1; /* SDC1 eMMC slot */
+ mmc1 = &sdhc_2; /* SDC2 SD card slot */
+ mmc2 = &sdhc_3; /* SDC3 SDIO card slot */
+ serial0 = &blsp2_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ cont-splash@83000000 {
+ reg = <0x0 0x83000000 0x0 0x2800000>;
+ };
+
+ ramoops@57f00000 {
+ compatible = "ramoops";
+ reg = <0 0x57f00000 0 0x100000>;
+ record-size = <0x20000>;
+ console-size = <0x40000>;
+ ftrace-size = <0x20000>;
+ pmsg-size = <0x20000>;
+ ecc-size = <16>;
+ };
+ };
+
+ usbphy_1p2: regulator-usbphy-1p2 {
+ compatible = "regulator-fixed";
+ regulator-name = "usbphy-1p2";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ vin-supply = <&vph_pwr>;
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph-pwr";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&blsp1_i2c4 {
+ status = "okay";
+
+ /* Synaptics RMI4 @ 2c */
+};
+
+&blsp2_uart2 {
+ status = "okay";
+};
+
+&gcc {
+ vdd_gfx-supply = <&pm8004_s5>;
+};
+
+&otg {
+ status = "okay";
+};
+
+&pm8004_spmi_regulators {
+ vdd_s2-supply = <&vph_pwr>;
+ vdd_s5-supply = <&vph_pwr>;
+
+ /* Cluster 1 supply */
+ pm8004_s2: s2 {
+ /* regulator-min-microvolt = <500000>; */
+ /* Set .95V to prevent unstabilities until CPR for this SoC is done */
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1165000>;
+ regulator-name = "vdd_apc1";
+ /* Set always on until the CPU PLL is done */
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8004_s5: s5 {
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1165000>;
+ regulator-enable-ramp-delay = <500>;
+ regulator-name = "vdd_gfx";
+ /* Hack this on until the gpu driver is ready for it */
+ regulator-always-on;
+ };
+};
+
+&pm8950_spmi_regulators {
+ vdd_s5-supply = <&vph_pwr>;
+
+ /* Cluster 0 supply */
+ pm8950_spmi_s5: s5 {
+ /* Set .95V to prevent unstabilities until CPR for this SoC is done */
+ /* regulator-min-microvolt = <790000>; */
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1165000>;
+ regulator-name = "vdd_apc0";
+ /* Set always on until the CPU PLL is done */
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&rpm_requests {
+ pm8950_regulators: regulators {
+ compatible = "qcom,rpm-pm8950-regulators";
+
+ vdd_s1-supply = <&vph_pwr>;
+ vdd_s2-supply = <&vph_pwr>;
+ vdd_s3-supply = <&vph_pwr>;
+ vdd_s4-supply = <&vph_pwr>;
+ vdd_s6-supply = <&vph_pwr>;
+ vdd_l1_l19-supply = <&pm8950_s3>;
+ vdd_l2_l23-supply = <&pm8950_s3>;
+ vdd_l3-supply = <&pm8950_s3>;
+ vdd_l5_l6_l7_l16-supply = <&pm8950_s4>;
+ vdd_l8_l11_l12_l17_l22-supply = <&vph_pwr>;
+
+ pm8950_s1: s1 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1162500>;
+ };
+
+ pm8950_s3: s3 {
+ regulator-min-microvolt = <1325000>;
+ regulator-max-microvolt = <1325000>;
+ regulator-always-on;
+ };
+
+ pm8950_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ pm8950_l1: l1 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ pm8950_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8950_l3: l3 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8950_l5: l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-system-load = <290000>;
+ regulator-allow-set-load;
+ };
+
+ pm8950_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8950_l7: l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8950_l8: l8 {
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-system-load = <130000>;
+ regulator-allow-set-load;
+ };
+
+ pm8950_l9: l9 {
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2400000>;
+ };
+
+ pm8950_l10: l10 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ pm8950_l11: l11 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-system-load = <60000>;
+ regulator-allow-set-load;
+ };
+
+ pm8950_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-system-load = <100000>;
+ regulator-allow-set-load;
+ };
+
+ pm8950_l13: l13 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+
+ pm8950_l14: l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8950_l15: l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8950_l16: l16 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8950_l17: l17 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ pm8950_l22: l22 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8950_l23: l23 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ };
+};
+
+&sdhc_1 {
+ /* Toshiba THGBMHG8C4LBAU7 (032G34) */
+ bus-width = <8>;
+ non-removable;
+ vmmc-supply = <&pm8950_l8>;
+ vqmmc-supply = <&pm8950_l5>;
+ status = "okay";
+};
+
+&sdhc_2 {
+ bus-width = <4>;
+ cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <&pm8950_l11>;
+ vqmmc-supply = <&pm8950_l12>;
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <0 4>;
+};
+
+&usb_hs_phy {
+ vdd-supply = <&usbphy_1p2>;
+ vdda1p8-supply = <&pm8950_l7>;
+ vdda3p3-supply = <&pm8950_l13>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8956.dtsi b/arch/arm64/boot/dts/qcom/msm8956.dtsi
new file mode 100644
index 000000000000..e432512d8716
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8956.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
+ * <angelogioacchino.delregno@collabora.com>
+ * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org>
+ * Copyright (c) 2022, Marijn Suijten <marijn.suijten@somainline.org>
+ */
+
+#include "msm8976.dtsi"
+
+&pmu {
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+};
+
+/*
+ * You might be wondering.. why is it so empty out there?
+ * Well, the SoCs are almost identical.
+ */
diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi
new file mode 100644
index 000000000000..05dcb30b0779
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
@@ -0,0 +1,1198 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
+ * <angelogioacchino.delregno@collabora.com>
+ * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org>
+ * Copyright (c) 2022, Marijn Suijten <marijn.suijten@somainline.org>
+ */
+
+#include <dt-bindings/clock/qcom,gcc-msm8976.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+
+/ {
+ interrupt-parent = <&intc>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ enable-method = "psci";
+ cpu-idle-states = <&little_cpu_sleep_0>;
+ capacity-dmips-mhz = <573>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ enable-method = "psci";
+ cpu-idle-states = <&little_cpu_sleep_0>;
+ capacity-dmips-mhz = <573>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ enable-method = "psci";
+ cpu-idle-states = <&little_cpu_sleep_0>;
+ capacity-dmips-mhz = <573>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ enable-method = "psci";
+ cpu-idle-states = <&little_cpu_sleep_0>;
+ capacity-dmips-mhz = <573>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ CPU4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+ capacity-dmips-mhz = <1024>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ CPU5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+ capacity-dmips-mhz = <1024>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ CPU6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x102>;
+ enable-method = "psci";
+ cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+ capacity-dmips-mhz = <1024>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ CPU7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x103>;
+ enable-method = "psci";
+ cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+ capacity-dmips-mhz = <1024>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+
+ core1 {
+ cpu = <&CPU5>;
+ };
+
+ core2 {
+ cpu = <&CPU6>;
+ };
+
+ core3 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ little_cpu_sleep_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "little-power-collapse";
+ arm,psci-suspend-param = <0x40000003>;
+ entry-latency-us = <181>;
+ exit-latency-us = <149>;
+ min-residency-us = <703>;
+ local-timer-stop;
+ };
+
+ big_cpu_sleep_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "big-retention";
+ arm,psci-suspend-param = <0x00000002>;
+ entry-latency-us = <142>;
+ exit-latency-us = <99>;
+ min-residency-us = <242>;
+ };
+
+ big_cpu_sleep_1: cpu-sleep-1-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "big-power-collapse";
+ arm,psci-suspend-param = <0x40000003>;
+ entry-latency-us = <158>;
+ exit-latency-us = <144>;
+ min-residency-us = <863>;
+ local-timer-stop;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ firmware {
+ scm: scm {
+ compatible = "qcom,scm-msm8976", "qcom,scm";
+ clocks = <&gcc GCC_CRYPTO_CLK>,
+ <&gcc GCC_CRYPTO_AXI_CLK>,
+ <&gcc GCC_CRYPTO_AHB_CLK>;
+ clock-names = "core", "bus", "iface";
+ #reset-cells = <1>;
+
+ qcom,dload-mode = <&tcsr 0x6100>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0x80000000 0x0 0x0>;
+ };
+
+ pmu: pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ext-region@85b00000 {
+ reg = <0x0 0x85b00000 0x0 0x500000>;
+ no-map;
+ };
+
+ smem@86300000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x86300000 0x0 0x100000>;
+ no-map;
+
+ hwlocks = <&tcsr_mutex 3>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ };
+
+ reserved@86400000 {
+ reg = <0x0 0x86400000 0x0 0x800000>;
+ no-map;
+ };
+
+ mpss_mem: mpss@86c00000 {
+ reg = <0x0 0x86c00000 0x0 0x5600000>;
+ no-map;
+ };
+
+ lpass_mem: lpass@8c200000 {
+ reg = <0x0 0x8c200000 0x0 0x1800000>;
+ no-map;
+ };
+
+ venus_mem: memory@8da00000 {
+ reg = <0x0 0x8da00000 0x0 0x2600000>;
+ no-map;
+ };
+
+ tz-apps@8dd00000 {
+ reg = <0x0 0x8dd00000 0x0 0x1400000>;
+ no-map;
+ };
+ };
+
+ smp2p-hexagon {
+ compatible = "qcom,smp2p";
+ interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 8 10>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+ qcom,smem = <443>, <429>;
+
+ adsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+
+ #qcom,smem-state-cells = <1>;
+ };
+
+ adsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-modem {
+ compatible = "qcom,smp2p";
+ interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 8 13>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+ qcom,smem = <435>, <428>;
+
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-wcnss {
+ compatible = "qcom,smp2p";
+ interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 8 17>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <4>;
+ qcom,smem = <451>, <431>;
+
+ wcnss_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+
+ #qcom,smem-state-cells = <1>;
+ };
+
+ wcnss_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smd {
+ compatible = "qcom,smd";
+
+ rpm {
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 8 0>;
+ qcom,smd-edge = <15>;
+
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-msm8976";
+ qcom,smd-channels = "rpm_requests";
+
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc";
+ #clock-cells = <1>;
+ };
+
+ rpmpd: power-controller {
+ compatible = "qcom,msm8976-rpmpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmpd_opp_table>;
+
+ rpmpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmpd_opp_ret: opp1 {
+ opp-level = <RPM_SMD_LEVEL_RETENTION>;
+ };
+
+ rpmpd_opp_ret_plus: opp2 {
+ opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
+ };
+
+ rpmpd_opp_min_svs: opp3 {
+ opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
+ };
+
+ rpmpd_opp_low_svs: opp4 {
+ opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
+ };
+
+ rpmpd_opp_svs: opp5 {
+ opp-level = <RPM_SMD_LEVEL_SVS>;
+ };
+
+ rpmpd_opp_svs_plus: opp6 {
+ opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
+ };
+
+ rpmpd_opp_nom: opp7 {
+ opp-level = <RPM_SMD_LEVEL_NOM>;
+ };
+
+ rpmpd_opp_nom_plus: opp8 {
+ opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
+ };
+
+ rpmpd_opp_turbo: opp9 {
+ opp-level = <RPM_SMD_LEVEL_TURBO>;
+ };
+
+ rpmpd_opp_turbo_no_cpr: opp10 {
+ opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
+ };
+
+ rpmpd_opp_turbo_high: opp111 {
+ opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>;
+ };
+ };
+ };
+ };
+ };
+ };
+
+ smsm {
+ compatible = "qcom,smsm";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ipc-1 = <&apcs 8 12>;
+ qcom,ipc-2 = <&apcs 8 9>;
+ qcom,ipc-3 = <&apcs 8 18>;
+
+ apps_smsm: apps@0 {
+ reg = <0>;
+ #qcom,smem-state-cells = <1>;
+ };
+
+ hexagon_smsm: hexagon@1 {
+ reg = <1>;
+ interrupts = <0 290 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ wcnss_smsm: wcnss@6 {
+ reg = <6>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ soc: soc@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ rng@22000 {
+ compatible = "qcom,prng";
+ reg = <0x00022000 0x140>;
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "core";
+ };
+
+ rpm_msg_ram: sram@60000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0x00060000 0x8000>;
+ };
+
+ usb_hs_phy: phy@6c000 {
+ compatible = "qcom,usb-hs-28nm-femtophy";
+ reg = <0x0006c000 0x200>;
+ #phy-cells = <0>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+ clock-names = "ref", "ahb", "sleep";
+ resets = <&gcc RST_QUSB2_PHY_BCR>,
+ <&gcc RST_USB2_HS_PHY_ONLY_BCR>;
+ reset-names = "phy", "por";
+ status = "disabled";
+ };
+
+ qfprom: qfprom@a4000 {
+ compatible = "qcom,msm8976-qfprom", "qcom,qfprom";
+ reg = <0x000a4000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ tsens_caldata: caldata@218 {
+ reg = <0x218 0x18>;
+ };
+ };
+
+ tsens: thermal-sensor@4a9000 {
+ compatible = "qcom,msm8976-tsens", "qcom,tsens-v1";
+ reg = <0x004a9000 0x1000>, /* TM */
+ <0x004a8000 0x1000>; /* SROT */
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
+ nvmem-cells = <&tsens_caldata>;
+ nvmem-cell-names = "calib";
+ #qcom,sensors = <11>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,msm8976-pinctrl";
+ reg = <0x01000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&tlmm 0 0 145>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ spi1_default: spi0-default-state {
+ spi-pins {
+ pins = "gpio0", "gpio1", "gpio3";
+ function = "blsp_spi1";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ cs-pins {
+ pins = "gpio2";
+ function = "blsp_spi1";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ spi1_sleep: spi0-sleep-state {
+ spi-pins {
+ pins = "gpio0", "gpio1", "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cs-pins {
+ pins = "gpio2";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ blsp1_i2c2_default: blsp1-i2c2-default-state {
+ pins = "gpio6", "gpio7";
+ function = "blsp_i2c2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
+ pins = "gpio6", "gpio7";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp1_i2c4_default: blsp1-i2c4-default-state {
+ pins = "gpio14", "gpio15";
+ function = "blsp_i2c4";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
+ pins = "gpio14", "gpio15";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp2_uart2_active: blsp2-uart2-active-state {
+ pins = "gpio20", "gpio21";
+ function = "blsp_uart6";
+ drive-strength = <4>;
+ bias-disable;
+ };
+
+ blsp2_uart2_sleep: blsp2-uart2-sleep-state {
+ pins = "gpio20", "gpio21";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ /* 4 (not 6!) interfaces per QUP, BLSP2 indexes are numbered (n)+4 */
+ blsp2_i2c2_default: blsp2-i2c2-default-state {
+ pins = "gpio22", "gpio23";
+ function = "blsp_i2c6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
+ pins = "gpio22", "gpio23";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp2_i2c4_default: blsp2-i2c4-default-state {
+ pins = "gpio18", "gpio19";
+ function = "blsp_i2c8";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
+ pins = "gpio18", "gpio19";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ gcc: clock-controller@1800000 {
+ compatible = "qcom,gcc-msm8976";
+ reg = <0x01800000 0x80000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+
+ assigned-clocks = <&gcc GPLL3>;
+ assigned-clock-rates = <1100000000>;
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ clock-names = "xo",
+ "xo_a",
+ "dsi0pll",
+ "dsi0pllbyte",
+ "dsi1pll",
+ "dsi1pllbyte";
+ };
+
+ tcsr_mutex: hwlock@1905000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x01905000 0x20000>;
+ #hwlock-cells = <1>;
+ };
+
+ tcsr: syscon@1937000 {
+ compatible = "qcom,msm8976-tcsr", "syscon";
+ reg = <0x01937000 0x30000>;
+ };
+
+ spmi_bus: spmi@200f000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x0200f000 0x1000>,
+ <0x02400000 0x800000>,
+ <0x02c00000 0x800000>,
+ <0x03800000 0x200000>,
+ <0x0200a000 0x2100>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+ qcom,channel = <0>;
+ qcom,ee = <0>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
+ sdhc_1: mmc@7824000 {
+ compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
+ reg = <0x07824900 0x500>, <0x07824000 0x800>;
+ reg-names = "hc", "core";
+
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "core", "xo";
+ status = "disabled";
+ };
+
+ sdhc_2: mmc@7864000 {
+ compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
+ reg = <0x07864900 0x11c>, <0x07864000 0x800>;
+ reg-names = "hc", "core";
+
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "core", "xo";
+ status = "disabled";
+ };
+
+ blsp1_dma: dma-controller@7884000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x07884000 0x1f000>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ blsp1_uart1: serial@78af000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x078af000 0x200>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ blsp1_uart2: serial@78b0000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x078b0000 0x200>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ blsp1_spi1: spi@78b5000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x078b5000 0x500>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi1_default>;
+ pinctrl-1 = <&spi1_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp1_i2c2: i2c@78b6000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x078b6000 0x500>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ clock-frequency = <400000>;
+ dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_i2c2_default>;
+ pinctrl-1 = <&blsp1_i2c2_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp1_i2c4: i2c@78b8000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x078b8000 0x500>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ clock-frequency = <400000>;
+ dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_i2c4_default>;
+ pinctrl-1 = <&blsp1_i2c4_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ otg: usb@78db000 {
+ compatible = "qcom,ci-hdrc";
+ reg = <0x078db000 0x200>,
+ <0x078db200 0x200>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_USB_HS_AHB_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>;
+ clock-names = "iface", "core";
+ assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
+ assigned-clock-rates = <80000000>;
+ resets = <&gcc RST_USB_HS_BCR>;
+ reset-names = "core";
+ ahb-burst-config = <0>;
+ dr_mode = "peripheral";
+ phy_type = "ulpi";
+ phy-names = "usb-phy";
+ phys = <&usb_hs_phy>;
+ status = "disabled";
+ #reset-cells = <1>;
+ };
+
+ sdhc_3: mmc@7a24000 {
+ compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
+ reg = <0x07a24900 0x11c>, <0x07a24000 0x800>;
+ reg-names = "hc", "core";
+
+ interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC3_AHB_CLK>,
+ <&gcc GCC_SDCC3_APPS_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "core", "xo";
+
+ status = "disabled";
+ };
+
+ blsp2_dma: dma-controller@7ac4000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x07ac4000 0x1f000>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ blsp2_uart2: serial@7af0000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x07af0000 0x200>;
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ blsp2_i2c2: i2c@7af6000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x07af6000 0x600>;
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
+ clock-frequency = <400000>;
+ dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_i2c2_default>;
+ pinctrl-1 = <&blsp2_i2c2_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp2_i2c4: i2c@7af8000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x07af8000 0x600>;
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
+ clock-frequency = <400000>;
+ dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_i2c4_default>;
+ pinctrl-1 = <&blsp2_i2c4_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ intc: interrupt-controller@b000000 {
+ compatible = "qcom,msm-qgic2";
+ reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ apcs: mailbox@b011000 {
+ compatible = "qcom,msm8976-apcs-kpss-global", "syscon";
+ reg = <0x0b011000 0x1000>;
+ #mbox-cells = <1>;
+ };
+
+ timer@b120000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0b120000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <19200000>;
+
+ frame@b121000 {
+ reg = <0x0b121000 0x1000>, <0x0b122000 0x1000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <0>;
+ };
+
+ frame@b123000 {
+ reg = <0x0b123000 0x1000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <1>;
+ status = "disabled";
+ };
+
+ frame@b124000 {
+ reg = <0x0b124000 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <2>;
+ status = "disabled";
+ };
+
+ frame@b125000 {
+ reg = <0x0b125000 0x1000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <3>;
+ status = "disabled";
+ };
+
+ frame@b126000 {
+ reg = <0x0b126000 0x1000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <4>;
+ status = "disabled";
+ };
+
+ frame@b127000 {
+ reg = <0x0b127000 0x1000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <5>;
+ status = "disabled";
+ };
+
+ frame@b128000 {
+ reg = <0x0b128000 0x1000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <6>;
+ status = "disabled";
+ };
+ };
+
+ imem: sram@8600000 {
+ compatible = "qcom,msm8976-imem", "syscon", "simple-mfd";
+ reg = <0x08600000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0x08600000 0x1000>;
+
+ pil-reloc@94c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x94c 0xc8>;
+ };
+ };
+ };
+
+ thermal-zones {
+ aoss0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 0>;
+
+ trips {
+ aoss0_alert0: trip-point0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ modem-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 1>;
+ trips {
+ modem_alert0: trip-point0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ qdsp-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 2>;
+ trips {
+ qdsp_alert0: trip-point0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ cam-isp-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 3>;
+ trips {
+ cam_isp_alert0: trip-point0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ cpu4-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 4>;
+
+ trips {
+ cpu4_alert0: trip-point0 {
+ temperature = <50000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ cpu4_alert1: trip-point1 {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu4_crit: cpu-crit {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu5-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 5>;
+
+ trips {
+ cpu5_alert0: trip-point0 {
+ temperature = <50000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ cpu5_alert1: trip-point1 {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu5_crit: cpu-crit {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu6-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 6>;
+
+ trips {
+ cpu6_alert0: trip-point0 {
+ temperature = <50000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ cpu6_alert1: trip-point1 {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu6_crit: cpu-crit {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu7-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 7>;
+
+ trips {
+ cpu7_alert0: trip-point0 {
+ temperature = <50000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ cpu7_alert1: trip-point1 {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu7_crit: cpu-crit {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ big-l2-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 8>;
+
+ trips {
+ l2_alert0: trip-point0 {
+ temperature = <50000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ l2_alert1: trip-point1 {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ l2_crit: l2-crit {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 9>;
+
+ trips {
+ cpu0_alert0: trip-point0 {
+ temperature = <50000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ cpu0_alert1: trip-point1 {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu0_crit: cpu-crit {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 10>;
+
+ trips {
+ gpu_alert0: trip-point0 {
+ temperature = <50000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ gpu_alert1: trip-point1 {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ gpu_crit: gpu-crit {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <19200000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts
index 7e6bce4af441..4159fc35571a 100644
--- a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts
+++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) Jean Thomas <virgule@jeanthomas.me>
+/*
+ * Copyright (c) Jean Thomas <virgule@jeanthomas.me>
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts
index e6a5ebd30e2f..ad9702dd171b 100644
--- a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts
+++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) Jean Thomas <virgule@jeanthomas.me>
+/*
+ * Copyright (c) Jean Thomas <virgule@jeanthomas.me>
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi
index 71e373b11de9..87c90e93667f 100644
--- a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2015, LGE Inc. All rights reserved.
+/*
+ * Copyright (c) 2015, LGE Inc. All rights reserved.
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Petr Vorel <petr.vorel@gmail.com>
*/
@@ -58,7 +59,7 @@
};
&rpm_requests {
- pm8994_regulators: pm8994-regulators {
+ pm8994_regulators: regulators-0 {
compatible = "qcom,rpm-pm8994-regulators";
vdd_l1-supply = <&pm8994_s1>;
@@ -236,9 +237,11 @@
};
pm8994_l26: l26 {
- /* TODO: value from downstream
- regulator-min-microvolt = <987500>;
- fails to apply */
+ /*
+ * TODO: value from downstream
+ * regulator-min-microvolt = <987500>;
+ * fails to apply
+ */
};
pm8994_l27: l27 {
@@ -252,19 +255,19 @@
};
pm8994_l29: l29 {
- /* TODO: Unsupported voltage range.
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- qcom,init-voltage = <2800000>;
- */
+ /*
+ * TODO: Unsupported voltage range.
+ * regulator-min-microvolt = <2800000>;
+ * regulator-max-microvolt = <2800000>;
+ */
};
pm8994_l30: l30 {
- /* TODO: get this verified
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- qcom,init-voltage = <1800000>;
- */
+ /*
+ * TODO: get this verified
+ * regulator-min-microvolt = <1800000>;
+ * regulator-max-microvolt = <1800000>;
+ */
};
pm8994_l31: l31 {
@@ -273,15 +276,15 @@
};
pm8994_l32: l32 {
- /* TODO: get this verified
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- qcom,init-voltage = <1800000>;
- */
+ /*
+ * TODO: get this verified
+ * regulator-min-microvolt = <1800000>;
+ * regulator-max-microvolt = <1800000>;
+ */
};
};
- pmi8994_regulators: pmi8994-regulators {
+ pmi8994_regulators: regulators-1 {
compatible = "qcom,rpm-pmi8994-regulators";
vdd_s1-supply = <&vph_pwr>;
diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
index c4e87d0aec42..b242c272d2af 100644
--- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
+++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
@@ -153,7 +153,7 @@
};
&rpm_requests {
- pm8994-regulators {
+ regulators-0 {
compatible = "qcom,rpm-pm8994-regulators";
vdd_l1-supply = <&pm8994_s7>;
@@ -363,7 +363,7 @@
pm8994_lvs2: lvs2 {};
};
- pmi8994_regulators: pmi8994-regulators {
+ pmi8994_regulators: regulators-1 {
compatible = "qcom,rpm-pmi8994-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_bst_byp-supply = <&vph_pwr>;
diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
index 750643763a76..10adb4986ef1 100644
--- a/arch/arm64/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
*/
#include "msm8994.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts
index dbfbb77e9ff5..85abff0e9b3f 100644
--- a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts
+++ b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2015, Huawei Inc. All rights reserved.
+/*
+ * Copyright (c) 2015, Huawei Inc. All rights reserved.
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2022, Petr Vorel <petr.vorel@gmail.com>
*/
diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi
index f9d8bd09e074..9b67f0d3820c 100644
--- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi
@@ -551,7 +551,7 @@
&rpm_requests {
/* These values were taken from the original firmware ACPI tables */
- pm8994_regulators: pm8994-regulators {
+ pm8994_regulators: regulators-0 {
compatible = "qcom,rpm-pm8994-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -835,7 +835,7 @@
vreg_lvs2a_1p8: lvs2 { };
};
- pmi8994_regulators: pmi8994-regulators {
+ pmi8994_regulators: regulators-1 {
compatible = "qcom,rpm-pmi8994-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -881,28 +881,28 @@
};
&tlmm {
- grip_default: grip-default {
+ grip_default: grip-default-state {
pins = "gpio39";
function = "gpio";
drive-strength = <6>;
bias-pull-down;
};
- grip_sleep: grip-sleep {
+ grip_sleep: grip-sleep-state {
pins = "gpio39";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- hall_front_default: hall-front-default {
+ hall_front_default: hall-front-default-state {
pins = "gpio42";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- hall_back_default: hall-back-default {
+ hall_back_default: hall-back-default-state {
pins = "gpio75";
function = "gpio";
drive-strength = <2>;
diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi
index ff60b7004d26..f3d153c34918 100644
--- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi
@@ -186,7 +186,7 @@
&rpm_requests {
/* PMI8994 should probe first, because pmi8994_bby supplies some of PM8994's regulators */
- pmi8994_regulators: pmi8994-regulators {
+ pmi8994_regulators: regulators-0 {
compatible = "qcom,rpm-pmi8994-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -205,7 +205,7 @@
};
};
- pm8994_regulators: pm8994-regulators {
+ pm8994_regulators: regulators-1 {
compatible = "qcom,rpm-pm8994-regulators";
vdd_s3-supply = <&vph_pwr>;
@@ -477,15 +477,17 @@
};
&tlmm {
- ts_int_active: ts-int-active {
+ ts_int_active: ts-int-active-state {
pins = "gpio42";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
- ts_reset_active: ts-reset-active {
+ ts_reset_active: ts-reset-active-state {
pins = "gpio109";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
output-low;
diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
index ded5b7ceeaf9..9ff9d35496d2 100644
--- a/arch/arm64/boot/dts/qcom/msm8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -553,7 +554,6 @@
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- spi-max-frequency = <19200000>;
dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
@@ -691,7 +691,6 @@
clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
- spi-max-frequency = <19200000>;
dmas = <&blsp2_dma 18>, <&blsp2_dma 19>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
@@ -773,254 +772,256 @@
interrupt-controller;
#interrupt-cells = <2>;
- blsp1_uart2_default: blsp1-uart2-default {
- function = "blsp_uart2";
+ blsp1_uart2_default: blsp1-uart2-default-state {
pins = "gpio4", "gpio5";
+ function = "blsp_uart2";
drive-strength = <16>;
bias-disable;
};
- blsp1_uart2_sleep: blsp1-uart2-sleep {
- function = "gpio";
+ blsp1_uart2_sleep: blsp1-uart2-sleep-state {
pins = "gpio4", "gpio5";
+ function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- blsp2_uart2_default: blsp2-uart2-default {
+ blsp2_uart2_default: blsp2-uart2-default-state {
+ pins = "gpio45", "gpio46", "gpio47", "gpio48";
function = "blsp_uart8";
- pins = "gpio45", "gpio46",
- "gpio47", "gpio48";
drive-strength = <16>;
bias-disable;
};
- blsp2_uart2_sleep: blsp2-uart2-sleep {
+ blsp2_uart2_sleep: blsp2-uart2-sleep-state {
+ pins = "gpio45", "gpio46", "gpio47", "gpio48";
function = "gpio";
- pins = "gpio45", "gpio46",
- "gpio47", "gpio48";
drive-strength = <2>;
bias-disable;
};
- i2c1_default: i2c1-default {
- function = "blsp_i2c1";
+ i2c1_default: i2c1-default-state {
pins = "gpio2", "gpio3";
+ function = "blsp_i2c1";
drive-strength = <2>;
bias-disable;
};
- i2c1_sleep: i2c1-sleep {
- function = "gpio";
+ i2c1_sleep: i2c1-sleep-state {
pins = "gpio2", "gpio3";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
- i2c2_default: i2c2-default {
- function = "blsp_i2c2";
+ i2c2_default: i2c2-default-state {
pins = "gpio6", "gpio7";
+ function = "blsp_i2c2";
drive-strength = <2>;
bias-disable;
};
- i2c2_sleep: i2c2-sleep {
- function = "gpio";
+ i2c2_sleep: i2c2-sleep-state {
pins = "gpio6", "gpio7";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
- i2c4_default: i2c4-default {
- function = "blsp_i2c4";
+ i2c4_default: i2c4-default-state {
pins = "gpio19", "gpio20";
+ function = "blsp_i2c4";
drive-strength = <2>;
bias-disable;
};
- i2c4_sleep: i2c4-sleep {
- function = "gpio";
+ i2c4_sleep: i2c4-sleep-state {
pins = "gpio19", "gpio20";
+ function = "gpio";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
- i2c5_default: i2c5-default {
- function = "blsp_i2c5";
+ i2c5_default: i2c5-default-state {
pins = "gpio23", "gpio24";
+ function = "blsp_i2c5";
drive-strength = <2>;
bias-disable;
};
- i2c5_sleep: i2c5-sleep {
- function = "gpio";
+ i2c5_sleep: i2c5-sleep-state {
pins = "gpio23", "gpio24";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
- i2c6_default: i2c6-default {
- function = "blsp_i2c6";
+ i2c6_default: i2c6-default-state {
pins = "gpio28", "gpio27";
+ function = "blsp_i2c6";
drive-strength = <2>;
bias-disable;
};
- i2c6_sleep: i2c6-sleep {
- function = "gpio";
+ i2c6_sleep: i2c6-sleep-state {
pins = "gpio28", "gpio27";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
- i2c7_default: i2c7-default {
- function = "blsp_i2c7";
+ i2c7_default: i2c7-default-state {
pins = "gpio44", "gpio43";
+ function = "blsp_i2c7";
drive-strength = <2>;
bias-disable;
};
- i2c7_sleep: i2c7-sleep {
- function = "gpio";
+ i2c7_sleep: i2c7-sleep-state {
pins = "gpio44", "gpio43";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
- blsp2_spi10_default: blsp2-spi10-default {
- default {
- function = "blsp_spi10";
+ blsp2_spi10_default: blsp2-spi10-default-state {
+ default-pins {
pins = "gpio53", "gpio54", "gpio55";
+ function = "blsp_spi10";
drive-strength = <10>;
bias-pull-down;
};
- cs {
+
+ cs-pins {
+ pins = "gpio67";
function = "gpio";
- pins = "gpio55";
drive-strength = <2>;
bias-disable;
};
};
- blsp2_spi10_sleep: blsp2-spi10-sleep {
+ blsp2_spi10_sleep: blsp2-spi10-sleep-state {
pins = "gpio53", "gpio54", "gpio55";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
- i2c11_default: i2c11-default {
- function = "blsp_i2c11";
+ i2c11_default: i2c11-default-state {
pins = "gpio83", "gpio84";
+ function = "blsp_i2c11";
drive-strength = <2>;
bias-disable;
};
- i2c11_sleep: i2c11-sleep {
- function = "gpio";
+ i2c11_sleep: i2c11-sleep-state {
pins = "gpio83", "gpio84";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
- blsp1_spi1_default: blsp1-spi1-default {
- default {
- function = "blsp_spi1";
+ blsp1_spi1_default: blsp1-spi1-default-state {
+ default-pins {
pins = "gpio0", "gpio1", "gpio3";
+ function = "blsp_spi1";
drive-strength = <10>;
bias-pull-down;
};
- cs {
- function = "gpio";
+
+ cs-pins {
pins = "gpio8";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
- blsp1_spi1_sleep: blsp1-spi1-sleep {
+ blsp1_spi1_sleep: blsp1-spi1-sleep-state {
pins = "gpio0", "gpio1", "gpio3";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
- sdc1_clk_on: clk-on {
+ sdc1_clk_on: clk-on-state {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
- sdc1_clk_off: clk-off {
+ sdc1_clk_off: clk-off-state {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
- sdc1_cmd_on: cmd-on {
+ sdc1_cmd_on: cmd-on-state {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <8>;
};
- sdc1_cmd_off: cmd-off {
+ sdc1_cmd_off: cmd-off-state {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
- sdc1_data_on: data-on {
+ sdc1_data_on: data-on-state {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <8>;
};
- sdc1_data_off: data-off {
+ sdc1_data_off: data-off-state {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
- sdc1_rclk_on: rclk-on {
+ sdc1_rclk_on: rclk-on-state {
pins = "sdc1_rclk";
bias-pull-down;
};
- sdc1_rclk_off: rclk-off {
+ sdc1_rclk_off: rclk-off-state {
pins = "sdc1_rclk";
bias-pull-down;
};
- sdc2_clk_on: sdc2-clk-on {
+ sdc2_clk_on: sdc2-clk-on-state {
pins = "sdc2_clk";
bias-disable;
drive-strength = <10>;
};
- sdc2_clk_off: sdc2-clk-off {
+ sdc2_clk_off: sdc2-clk-off-state {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
- sdc2_cmd_on: sdc2-cmd-on {
+ sdc2_cmd_on: sdc2-cmd-on-state {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
- sdc2_cmd_off: sdc2-cmd-off {
+ sdc2_cmd_off: sdc2-cmd-off-state {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
- sdc2_data_on: sdc2-data-on {
+ sdc2_data_on: sdc2-data-on-state {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
- sdc2_data_off: sdc2-data-off {
+ sdc2_data_off: sdc2-data-off-state {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi
new file mode 100644
index 000000000000..20f5c103c63b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi
@@ -0,0 +1,787 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022, Harry Austen <hpausten@protonmail.com>
+ */
+
+#include "msm8996.dtsi"
+#include "pm8994.dtsi"
+#include "pmi8994.dtsi"
+#include "pmi8996.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/sound/qcom,q6afe.h>
+#include <dt-bindings/sound/qcom,q6asm.h>
+#include <dt-bindings/sound/qcom,wcd9335.h>
+
+/ {
+ aliases {
+ serial0 = &blsp1_uart2;
+ serial1 = &blsp2_uart2;
+ };
+
+ battery: battery {
+ compatible = "simple-battery";
+
+ constant-charge-current-max-microamp = <3000000>;
+ voltage-min-design-microvolt = <3400000>;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ clocks {
+ div1_mclk: div1-clk {
+ compatible = "gpio-gate-clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&audio_mclk>;
+ #clock-cells = <0>;
+ clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
+ enable-gpios = <&pm8994_gpios 15 GPIO_ACTIVE_HIGH>;
+ };
+
+ divclk4: div4-clk {
+ compatible = "fixed-clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&divclk4_pin_a>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "divclk4";
+ };
+ };
+
+ reserved-memory {
+ ramoops@ac000000 {
+ compatible = "ramoops";
+ reg = <0 0xac000000 0 0x200000>;
+ record-size = <0x20000>;
+ console-size = <0x100000>;
+ pmsg-size = <0x80000>;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ wlan_en: wlan-en-regulator {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_en_gpios>;
+ regulator-name = "wlan-en-regulator";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&pm8994_gpios 8 GPIO_ACTIVE_HIGH>;
+
+ /* WLAN card specific delay */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+};
+
+&adsp_pil {
+ status = "okay";
+};
+
+&blsp1_i2c3 {
+ status = "okay";
+
+ tfa9890_amp: audio-codec@36 {
+ compatible = "nxp,tfa9890";
+ reg = <0x36>;
+ #sound-dai-cells = <0>;
+ };
+};
+
+&blsp1_i2c6 {
+ status = "okay";
+
+ bq27541: fuel-gauge@55 {
+ compatible = "ti,bq27541";
+ reg = <0x55>;
+ };
+};
+
+&blsp1_uart2 {
+ label = "BT-UART";
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,qca6174-bt";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_en_gpios>;
+ enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
+ clocks = <&divclk4>;
+ };
+};
+
+&blsp2_i2c1 {
+ status = "okay";
+};
+
+&blsp2_i2c6 {
+ status = "okay";
+
+ synaptics_rmi4_i2c: touchscreen@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&touch_default>;
+ pinctrl-1 = <&touch_suspend>;
+ vdd-supply = <&vreg_l22a_3p0>;
+ vio-supply = <&vreg_s4a_1p8>;
+ syna,reset-delay-ms = <200>;
+ syna,startup-delay-ms = <200>;
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f12@12 {
+ reg = <0x12>;
+ syna,sensor-type = <1>;
+ touchscreen-x-mm = <68>;
+ touchscreen-y-mm = <122>;
+ };
+ };
+};
+
+&blsp2_uart2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_uart2_2pins_default>;
+ pinctrl-1 = <&blsp2_uart2_2pins_sleep>;
+ status = "okay";
+};
+
+&camss {
+ vdda-supply = <&vreg_l2a_1p25>;
+};
+
+&dsi0 {
+ vdda-supply = <&vreg_l2a_1p25>;
+ vcca-supply = <&vreg_l22a_3p0>;
+ status = "okay";
+};
+
+&dsi0_out {
+ data-lanes = <0 1 2 3>;
+};
+
+&dsi0_phy {
+ vdda-supply = <&vreg_l2a_1p25>;
+ vcca-supply = <&vreg_l28a_0p925>;
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&hsusb_phy1 {
+ vdd-supply = <&vreg_l28a_0p925>;
+ vdda-pll-supply = <&vreg_l12a_1p8>;
+ vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
+ status = "okay";
+};
+
+&hsusb_phy2 {
+ vdd-supply = <&vreg_l28a_0p925>;
+ vdda-pll-supply = <&vreg_l12a_1p8>;
+ vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
+ status = "okay";
+};
+
+&mdp {
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mmcc {
+ vdd-gfx-supply = <&vdd_gfx>;
+};
+
+&mss_pil {
+ pll-supply = <&vreg_l12a_1p8>;
+ status = "okay";
+};
+
+&pcie0 {
+ perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+ vddpe-3v3-supply = <&wlan_en>;
+ vdda-supply = <&vreg_l28a_0p925>;
+ status = "okay";
+};
+
+&pcie_phy {
+ vdda-phy-supply = <&vreg_l28a_0p925>;
+ vdda-pll-supply = <&vreg_l12a_1p8>;
+ status = "okay";
+};
+
+&pm8994_gpios {
+ bt_en_gpios: bt-en-gpios-state {
+ pins = "gpio19";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ output-low;
+ power-source = <PM8994_GPIO_S4>;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+ bias-pull-down;
+ };
+
+ wlan_en_gpios: wlan-en-gpios-state {
+ pins = "gpio8";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ output-low;
+ power-source = <PM8994_GPIO_S4>;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+ bias-pull-down;
+ };
+
+ audio_mclk: divclk1-state {
+ pins = "gpio15";
+ function = PMIC_GPIO_FUNC_FUNC1;
+ power-source = <PM8994_GPIO_S4>;
+ };
+
+ divclk4_pin_a: divclk4-state {
+ pins = "gpio18";
+ function = PMIC_GPIO_FUNC_FUNC2;
+ bias-disable;
+ power-source = <PM8994_GPIO_S4>;
+ };
+};
+
+&pm8994_spmi_regulators {
+ qcom,saw-reg = <&saw3>;
+
+ s9 {
+ qcom,saw-slave;
+ };
+
+ s10 {
+ qcom,saw-slave;
+ };
+
+ s11 {
+ qcom,saw-leader;
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1140000>;
+ regulator-max-step-microvolt = <150000>;
+ regulator-always-on;
+ };
+};
+
+&pmi8994_spmi_regulators {
+ vdd_gfx: s2 {
+ regulator-name = "vdd-gfx";
+ regulator-min-microvolt = <980000>;
+ regulator-max-microvolt = <1230000>;
+ };
+};
+
+&q6asmdai {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dai@0 {
+ reg = <0>;
+ };
+
+ dai@1 {
+ reg = <1>;
+ };
+
+ dai@2 {
+ reg = <2>;
+ };
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-pm8994-regulators";
+
+ vreg_s3a_1p3: s3 {
+ regulator-name = "vreg_s3a_1p3";
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ vreg_s4a_1p8: s4 {
+ regulator-name = "vreg_s4a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vreg_s5a_2p15: s5 {
+ regulator-name = "vreg_s5a_2p15";
+ regulator-min-microvolt = <2150000>;
+ regulator-max-microvolt = <2150000>;
+ };
+
+ vreg_s7a_0p8: s7 {
+ regulator-name = "vreg_s7a_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ };
+
+ vreg_l1a_1p0: l1 {
+ regulator-name = "vreg_l1a_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ vreg_l2a_1p25: l2 {
+ regulator-name = "vreg_l2a_1p25";
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l3a_1p1: l3 {
+ regulator-name = "vreg_l3a_1p1";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ vreg_l4a_1p225: l4 {
+ regulator-name = "vreg_l4a_1p225";
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ vreg_l6a_1p2: l6 {
+ regulator-name = "vreg_l6a_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_l7a_1p8: l7 {
+ regulator-name = "vreg_l7a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vreg_l9a_1p8: l9 {
+ regulator-name = "vreg_l9a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vreg_l10a_1p8: l10 {
+ regulator-name = "vreg_l10a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vreg_l11a_1p15: l11 {
+ regulator-name = "vreg_l11a_1p15";
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ vreg_l12a_1p8: l12 {
+ regulator-name = "vreg_l12a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l13a_2p95: l13 {
+ regulator-name = "vreg_l13a_2p95";
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ vreg_l16a_2p7: l16 {
+ regulator-name = "vreg_l16a_2p7";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ vreg_l17a_2p6: l17 {
+ regulator-name = "vreg_l17a_2p6";
+ regulator-min-microvolt = <2600000>;
+ regulator-max-microvolt = <2600000>;
+ };
+
+ vreg_l18a_3p3: l18 {
+ regulator-name = "vreg_l18a_3p3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vreg_l19a_3p0: l19 {
+ regulator-name = "vreg_l19a_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ vreg_l20a_2p95: l20 {
+ regulator-name = "vreg_l20a_2p95";
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l21a_2p95: l21 {
+ regulator-name = "vreg_l21a_2p95";
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-allow-set-load;
+ regulator-system-load = <200000>;
+ };
+
+ vreg_l22a_3p0: l22 {
+ regulator-name = "vreg_l22a_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vreg_l23a_2p8: l23 {
+ regulator-name = "vreg_l23a_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ vreg_l24a_3p075: l24 {
+ regulator-name = "vreg_l24a_3p075";
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+
+ vreg_l25a_1p2: l25 {
+ regulator-name = "vreg_l25a_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-allow-set-load;
+ regulator-always-on;
+ };
+
+ vreg_l27a_1p2: l27 {
+ regulator-name = "vreg_l27a_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_l28a_0p925: l28 {
+ regulator-name = "vreg_l28a_0p925";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <925000>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l29a_2p8: l29 {
+ regulator-name = "vreg_l29a_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ vreg_l30a_1p8: l30 {
+ regulator-name = "vreg_l30a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vreg_l32a_1p8: l32 {
+ regulator-name = "vreg_l32a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+};
+
+&slpi_pil {
+ status = "okay";
+};
+
+&sound {
+ compatible = "qcom,apq8096-sndcard";
+ model = "OnePlus3";
+ audio-routing = "RX_BIAS", "MCLK",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Headset Mic",
+ "AMIC4", "MIC BIAS1",
+ "MIC BIAS1", "Primary Mic",
+ "AMIC5", "MIC BIAS3",
+ "MIC BIAS3", "Noise Mic";
+
+ mm1-dai-link {
+ link-name = "MultiMedia1";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
+ };
+ };
+
+ mm2-dai-link {
+ link-name = "MultiMedia2";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
+ };
+ };
+
+ mm3-dai-link {
+ link-name = "MultiMedia3";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
+ };
+ };
+
+ mm4-dai-link {
+ link-name = "MultiMedia4";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA4>;
+ };
+ };
+
+ mm5-dai-link {
+ link-name = "MultiMedia5";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA5>;
+ };
+ };
+
+ mm6-dai-link {
+ link-name = "MultiMedia6";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA6>;
+ };
+ };
+
+ mm7-dai-link {
+ link-name = "MultiMedia7";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA7>;
+ };
+ };
+
+ mm8-dai-link {
+ link-name = "MultiMedia8";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA8>;
+ };
+ };
+
+ mm9-dai-link {
+ link-name = "MultiMedia9";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA9>;
+ };
+ };
+
+ mm10-dai-link {
+ link-name = "MultiMedia10";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA10>;
+ };
+ };
+
+ mm11-dai-link {
+ link-name = "MultiMedia11";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA11>;
+ };
+ };
+
+ mm12-dai-link {
+ link-name = "MultiMedia12";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA12>;
+ };
+ };
+
+ mm13-dai-link {
+ link-name = "MultiMedia13";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA13>;
+ };
+ };
+
+ mm14-dai-link {
+ link-name = "MultiMedia14";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA14>;
+ };
+ };
+
+ mm15-dai-link {
+ link-name = "MultiMedia15";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA15>;
+ };
+ };
+
+ mm16-dai-link {
+ link-name = "MultiMedia16";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA16>;
+ };
+ };
+
+ slim-dai-link {
+ link-name = "SLIM Playback";
+
+ cpu {
+ sound-dai = <&q6afedai SLIMBUS_6_RX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&wcd9335 AIF4_PB>;
+ };
+ };
+
+ slimcap-dai-link {
+ link-name = "SLIM Capture";
+
+ cpu {
+ sound-dai = <&q6afedai SLIMBUS_0_TX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&wcd9335 AIF1_CAP>;
+ };
+ };
+
+ speaker-dai-link {
+ link-name = "Speaker";
+
+ cpu {
+ sound-dai = <&q6afedai QUATERNARY_MI2S_RX>;
+ };
+
+ codec {
+ sound-dai = <&tfa9890_amp>;
+ };
+ };
+};
+
+&tlmm {
+ gpio-reserved-ranges = <81 4>;
+
+ mdss_dsi_active: mdss-dsi-active-state {
+ pins = "gpio8";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ mdss_dsi_suspend: mdss-dsi-suspend-state {
+ pins = "gpio8";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ mdss_te_active: mdss-te-active-state {
+ pins = "gpio10";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ mdss_te_suspend: mdss-te-suspend-state {
+ pins = "gpio10";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ touch_default: touch-default-state {
+ pins = "gpio89", "gpio125", "gpio49";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ touch_suspend: touch-suspend-state {
+ pins = "gpio89", "gpio125", "gpio49";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&ufsphy {
+ vdda-phy-supply = <&vreg_l28a_0p925>;
+ vdda-pll-supply = <&vreg_l12a_1p8>;
+ vddp-ref-clk-supply = <&vreg_l25a_1p2>;
+
+ status = "okay";
+};
+
+&ufshc {
+ vcc-supply = <&vreg_l20a_2p95>;
+ vccq-supply = <&vreg_l25a_1p2>;
+ vccq2-supply = <&vreg_s4a_1p8>;
+
+ vcc-max-microamp = <600000>;
+ vccq-max-microamp = <450000>;
+ vccq2-max-microamp = <450000>;
+
+ status = "okay";
+};
+
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc3 {
+ phys = <&hsusb_phy1>;
+ phy-names = "usb2-phy";
+
+ maximum-speed = "high-speed";
+};
+
+&venus {
+ status = "okay";
+};
+
+&wcd9335 {
+ clock-names = "mclk", "slimbus";
+ clocks = <&div1_mclk>,
+ <&rpmcc RPM_SMD_BB_CLK1>;
+
+ vdd-buck-supply = <&vreg_s4a_1p8>;
+ vdd-buck-sido-supply = <&vreg_s4a_1p8>;
+ vdd-tx-supply = <&vreg_s4a_1p8>;
+ vdd-rx-supply = <&vreg_s4a_1p8>;
+ vdd-io-supply = <&vreg_s4a_1p8>;
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts b/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts
new file mode 100644
index 000000000000..1bdc1b134305
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022, Harry Austen <hpausten@protonmail.com>
+ */
+
+/dts-v1/;
+
+#include "msm8996-oneplus-common.dtsi"
+
+/ {
+ model = "OnePlus 3";
+ compatible = "oneplus,oneplus3", "qcom,msm8996";
+ chassis-type = "handset";
+ qcom,board-id = <8 0 15801 15>, <8 0 15801 16>;
+ qcom,msm-id = <246 0x30001>;
+};
+
+&adsp_pil {
+ firmware-name = "qcom/msm8996/oneplus3/adsp.mbn";
+};
+
+&battery {
+ charge-full-design-microamp-hours = <3000000>;
+ voltage-max-design-microvolt = <4350000>;
+};
+
+&gpu {
+ zap-shader {
+ firmware-name = "qcom/msm8996/oneplus3/a530_zap.mbn";
+ };
+};
+
+&mss_pil {
+ firmware-name = "qcom/msm8996/oneplus3/mba.mbn",
+ "qcom/msm8996/oneplus3/modem.mbn";
+};
+
+&slpi_pil {
+ firmware-name = "qcom/msm8996/oneplus3/slpi.mbn";
+};
+
+&venus {
+ firmware-name = "qcom/msm8996/oneplus3/venus.mbn";
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts b/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts
new file mode 100644
index 000000000000..34f837dd0c12
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022, Harry Austen <hpausten@protonmail.com>
+ */
+
+/dts-v1/;
+
+#include "msm8996-oneplus-common.dtsi"
+
+/ {
+ model = "OnePlus 3T";
+ compatible = "oneplus,oneplus3t", "qcom,msm8996";
+ chassis-type = "handset";
+ qcom,board-id = <8 0 15811 26>,
+ <8 0 15811 27>,
+ <8 0 15811 28>;
+};
+
+&adsp_pil {
+ firmware-name = "qcom/msm8996/oneplus3t/adsp.mbn";
+};
+
+&battery {
+ charge-full-design-microamp-hours = <3400000>;
+ voltage-max-design-microvolt = <4400000>;
+};
+
+&gpu {
+ zap-shader {
+ firmware-name = "qcom/msm8996/oneplus3t/a530_zap.mbn";
+ };
+};
+
+&mss_pil {
+ firmware-name = "qcom/msm8996/oneplus3t/mba.mbn",
+ "qcom/msm8996/oneplus3t/modem.mbn";
+};
+
+&slpi_pil {
+ firmware-name = "qcom/msm8996/oneplus3t/slpi.mbn";
+};
+
+&venus {
+ firmware-name = "qcom/msm8996/oneplus3t/venus.mbn";
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
index ca7c8d2e1d3d..dec361b93cce 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
@@ -629,7 +629,7 @@
};
&rpm_requests {
- pm8994-regulators {
+ regulators-0 {
compatible = "qcom,rpm-pm8994-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -847,28 +847,28 @@
pinctrl-0 = <&sw_service_gpio>;
pinctrl-names = "default";
- disp_reset_n_gpio: disp-reset-n {
+ disp_reset_n_gpio: disp-reset-n-state {
pins = "gpio8";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- mdp_vsync_p_gpio: mdp-vsync-p {
+ mdp_vsync_p_gpio: mdp-vsync-p-state {
pins = "gpio10";
function = "mdp_vsync";
drive-strength = <2>;
bias-disable;
};
- sw_service_gpio: sw-service-gpio {
+ sw_service_gpio: sw-service-gpio-state {
pins = "gpio16";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
- usb_detect: usb-detect {
+ usb_detect: usb-detect-state {
pins = "gpio25";
function = "gpio";
drive-strength = <2>;
@@ -876,7 +876,7 @@
output-high;
};
- uim_detect_en: uim-detect-en {
+ uim_detect_en: uim-detect-en-state {
pins = "gpio29";
function = "gpio";
drive-strength = <2>;
@@ -884,14 +884,14 @@
output-high;
};
- tray_det_pin: tray-det {
+ tray_det_pin: tray-det-state {
pins = "gpio40";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- tp_vddio_en: tp-vddio-en {
+ tp_vddio_en: tp-vddio-en-state {
pins = "gpio50";
function = "gpio";
drive-strength = <2>;
@@ -899,7 +899,7 @@
output-high;
};
- lcd_vddio_en: lcd-vddio-en {
+ lcd_vddio_en: lcd-vddio-en-state {
pins = "gpio51";
function = "gpio";
drive-strength = <2>;
@@ -907,15 +907,14 @@
output-low;
};
- wl_host_wake: wl-host-wake {
+ wl_host_wake: wl-host-wake-state {
pins = "gpio79";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
- input-high;
};
- wl_reg_on: wl-reg-on {
+ wl_reg_on: wl-reg-on-state {
pins = "gpio84";
function = "gpio";
drive-strength = <2>;
@@ -923,20 +922,20 @@
output-low;
};
- ts_reset_n: ts-rst-n {
+ ts_reset_n: ts-rst-n-state {
pins = "gpio89";
function = "gpio";
drive-strength = <2>;
};
- touch_int_n: touch-int-n {
+ touch_int_n: touch-int-n-state {
pins = "gpio125";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
- touch_int_sleep: touch-int-sleep {
+ touch_int_sleep: touch-int-sleep-state {
pins = "gpio125";
function = "gpio";
drive-strength = <2>;
diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
index 77819186086a..5b47b8de69da 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
@@ -3,9 +3,6 @@
* Copyright (c) 2020, Yassine Oudjana <y.oudjana@protonmail.com>
*/
-/dts-v1/;
-
-#include "msm8996.dtsi"
#include "pm8994.dtsi"
#include "pmi8994.dtsi"
#include <dt-bindings/input/input.h>
@@ -413,7 +410,7 @@
};
&rpm_requests {
- pm8994-regulators {
+ regulators-0 {
compatible = "qcom,rpm-pm8994-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -598,7 +595,7 @@
};
};
- pmi8994-regulators {
+ regulators-1 {
compatible = "qcom,rpm-pmi8994-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -694,35 +691,35 @@
};
&tlmm {
- mdss_dsi_default: mdss_dsi_default {
+ mdss_dsi_default: mdss-dsi-default-state {
pins = "gpio8";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
- mdss_dsi_sleep: mdss_dsi_sleep {
+ mdss_dsi_sleep: mdss-dsi-sleep-state {
pins = "gpio8";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- mdss_te_default: mdss_te_default {
+ mdss_te_default: mdss-te-default-state {
pins = "gpio10";
function = "mdp_vsync";
drive-strength = <2>;
bias-pull-down;
};
- mdss_te_sleep: mdss_te_sleep {
+ mdss_te_sleep: mdss-te-sleep-state {
pins = "gpio10";
function = "mdp_vsync";
drive-strength = <2>;
bias-pull-down;
};
- nfc_default: nfc_default {
+ nfc_default: nfc-default-state {
pins = "gpio12", "gpio21";
function = "gpio";
drive-strength = <16>;
diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts
index 4e5264f4116a..d8734913482f 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts
+++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts
@@ -5,6 +5,7 @@
/dts-v1/;
+#include "msm8996.dtsi"
#include "msm8996-xiaomi-common.dtsi"
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
@@ -219,7 +220,7 @@
};
&rpm_requests {
- pm8994-regulators {
+ regulators-0 {
vreg_l17a_2p8: l17 {
regulator-name = "vreg_l17a_2p8";
regulator-min-microvolt = <2500000>;
@@ -445,28 +446,28 @@
"RFFE1_DATA", /* GPIO_148 */
"RFFE1_CLK"; /* GPIO_149 */
- touchscreen_default: touchscreen_default {
+ touchscreen_default: touchscreen-default-state {
pins = "gpio89", "gpio125";
function = "gpio";
drive-strength = <10>;
bias-pull-up;
};
- touchscreen_sleep: touchscreen_sleep {
+ touchscreen_sleep: touchscreen-sleep-state {
pins = "gpio89", "gpio125";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- vibrator_default: vibrator_default {
+ vibrator_default: vibrator-default-state {
pins = "gpio93";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
- vibrator_sleep: vibrator_sleep {
+ vibrator_sleep: vibrator-sleep-state {
pins = "gpio93";
function = "gpio";
drive-strength = <2>;
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index aba717644391..d31464204f69 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -144,82 +145,92 @@
/* Nominal fmax for now */
opp-307200000 {
opp-hz = /bits/ 64 <307200000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-422400000 {
opp-hz = /bits/ 64 <422400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-556800000 {
opp-hz = /bits/ 64 <556800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-844800000 {
opp-hz = /bits/ 64 <844800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-960000000 {
opp-hz = /bits/ 64 <960000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1228800000 {
opp-hz = /bits/ 64 <1228800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1324800000 {
opp-hz = /bits/ 64 <1324800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xd>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-supported-hw = <0x2>;
clock-latency-ns = <200000>;
};
opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xd>;
clock-latency-ns = <200000>;
};
opp-1478400000 {
opp-hz = /bits/ 64 <1478400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x9>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-supported-hw = <0x04>;
clock-latency-ns = <200000>;
};
opp-1593600000 {
opp-hz = /bits/ 64 <1593600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x9>;
clock-latency-ns = <200000>;
};
};
@@ -232,127 +243,137 @@
/* Nominal fmax for now */
opp-307200000 {
opp-hz = /bits/ 64 <307200000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-403200000 {
opp-hz = /bits/ 64 <403200000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-556800000 {
opp-hz = /bits/ 64 <556800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-806400000 {
opp-hz = /bits/ 64 <806400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-883200000 {
opp-hz = /bits/ 64 <883200000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-940800000 {
opp-hz = /bits/ 64 <940800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1248000000 {
opp-hz = /bits/ 64 <1248000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1324800000 {
opp-hz = /bits/ 64 <1324800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1478400000 {
opp-hz = /bits/ 64 <1478400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1555200000 {
opp-hz = /bits/ 64 <1555200000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1632000000 {
opp-hz = /bits/ 64 <1632000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1708800000 {
opp-hz = /bits/ 64 <1708800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1785600000 {
opp-hz = /bits/ 64 <1785600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-supported-hw = <0xe>;
clock-latency-ns = <200000>;
};
opp-1824000000 {
opp-hz = /bits/ 64 <1824000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ opp-supported-hw = <0x4>;
clock-latency-ns = <200000>;
};
opp-1920000000 {
opp-hz = /bits/ 64 <1920000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
opp-1996800000 {
opp-hz = /bits/ 64 <1996800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
opp-2073600000 {
opp-hz = /bits/ 64 <2073600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
opp-2150400000 {
opp-hz = /bits/ 64 <2150400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
};
@@ -860,9 +881,9 @@
<&gcc GPLL0>,
<&dsi0_phy 1>,
<&dsi0_phy 0>,
- <0>,
- <0>,
- <0>;
+ <&dsi1_phy 1>,
+ <&dsi1_phy 0>,
+ <&hdmi_phy>;
clock-names = "xo",
"gcc_mmss_noc_cfg_ahb_clk",
"gpll0",
@@ -993,7 +1014,6 @@
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
phys = <&dsi0_phy>;
- phy-names = "dsi";
status = "disabled";
#address-cells = <1>;
@@ -1018,7 +1038,7 @@
};
};
- dsi0_phy: dsi-phy@994400 {
+ dsi0_phy: phy@994400 {
compatible = "qcom,dsi-phy-14nm";
reg = <0x00994400 0x100>,
<0x00994500 0x300>,
@@ -1061,7 +1081,6 @@
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
phys = <&dsi1_phy>;
- phy-names = "dsi";
status = "disabled";
#address-cells = <1>;
@@ -1086,7 +1105,7 @@
};
};
- dsi1_phy: dsi-phy@996400 {
+ dsi1_phy: phy@996400 {
compatible = "qcom,dsi-phy-14nm";
reg = <0x00996400 0x100>,
<0x00996500 0x300>,
@@ -1145,7 +1164,7 @@
};
};
- hdmi_phy: hdmi-phy@9a0600 {
+ hdmi_phy: phy@9a0600 {
#phy-cells = <0>;
compatible = "qcom,hdmi-phy-8996";
reg = <0x009a0600 0x1c4>,
@@ -1213,17 +1232,17 @@
compatible = "operating-points-v2";
/*
- * 624Mhz and 560Mhz are only available on speed
- * bin (1 << 0). All the rest are available on
- * all bins of the hardware
+ * 624Mhz is only available on speed bins 0 and 3.
+ * 560Mhz is only available on speed bins 0, 2 and 3.
+ * All the rest are available on all bins of the hardware.
*/
opp-624000000 {
opp-hz = /bits/ 64 <624000000>;
- opp-supported-hw = <0x01>;
+ opp-supported-hw = <0x09>;
};
opp-560000000 {
opp-hz = /bits/ 64 <560000000>;
- opp-supported-hw = <0x01>;
+ opp-supported-hw = <0x0d>;
};
opp-510000000 {
opp-hz = /bits/ 64 <510000000>;
@@ -1262,15 +1281,15 @@
interrupt-controller;
#interrupt-cells = <2>;
- blsp1_spi1_default: blsp1-spi1-default {
- spi {
+ blsp1_spi1_default: blsp1-spi1-default-state {
+ spi-pins {
pins = "gpio0", "gpio1", "gpio3";
function = "blsp_spi1";
drive-strength = <12>;
bias-disable;
};
- cs {
+ cs-pins {
pins = "gpio2";
function = "gpio";
drive-strength = <16>;
@@ -1279,42 +1298,56 @@
};
};
- blsp1_spi1_sleep: blsp1-spi1-sleep {
+ blsp1_spi1_sleep: blsp1-spi1-sleep-state {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- blsp2_uart2_2pins_default: blsp2-uart1-2pins {
+ blsp2_uart2_2pins_default: blsp2-uart2-2pins-state {
pins = "gpio4", "gpio5";
function = "blsp_uart8";
drive-strength = <16>;
bias-disable;
};
- blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
+ blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state {
pins = "gpio4", "gpio5";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- blsp2_i2c2_default: blsp2-i2c2 {
+ blsp2_i2c2_default: blsp2-i2c2-state {
pins = "gpio6", "gpio7";
function = "blsp_i2c8";
drive-strength = <16>;
bias-disable;
};
- blsp2_i2c2_sleep: blsp2-i2c2-sleep {
+ blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
pins = "gpio6", "gpio7";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- cci0_default: cci0-default {
+ blsp1_i2c6_default: blsp1-i2c6-state {
+ pins = "gpio27", "gpio28";
+ function = "blsp_i2c6";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
+ pins = "gpio27", "gpio28";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci0_default: cci0-default-state {
pins = "gpio17", "gpio18";
function = "cci_i2c";
drive-strength = <16>;
@@ -1322,22 +1355,22 @@
};
camera0_state_on:
- camera_rear_default: camera-rear-default {
- camera0_mclk: mclk0 {
+ camera_rear_default: camera-rear-default-state {
+ camera0_mclk: mclk0-pins {
pins = "gpio13";
function = "cam_mclk";
drive-strength = <16>;
bias-disable;
};
- camera0_rst: rst {
+ camera0_rst: rst-pins {
pins = "gpio25";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
- camera0_pwdn: pwdn {
+ camera0_pwdn: pwdn-pins {
pins = "gpio26";
function = "gpio";
drive-strength = <16>;
@@ -1345,7 +1378,7 @@
};
};
- cci1_default: cci1-default {
+ cci1_default: cci1-default-state {
pins = "gpio19", "gpio20";
function = "cci_i2c";
drive-strength = <16>;
@@ -1353,22 +1386,22 @@
};
camera1_state_on:
- camera_board_default: camera-board-default {
- mclk1 {
+ camera_board_default: camera-board-default-state {
+ mclk1-pins {
pins = "gpio14";
function = "cam_mclk";
drive-strength = <16>;
bias-disable;
};
- pwdn {
+ pwdn-pins {
pins = "gpio98";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
- rst {
+ rst-pins {
pins = "gpio104";
function = "gpio";
drive-strength = <16>;
@@ -1377,22 +1410,22 @@
};
camera2_state_on:
- camera_front_default: camera-front-default {
- camera2_mclk: mclk2 {
+ camera_front_default: camera-front-default-state {
+ camera2_mclk: mclk2-pins {
pins = "gpio15";
function = "cam_mclk";
drive-strength = <16>;
bias-disable;
};
- camera2_rst: rst {
+ camera2_rst: rst-pins {
pins = "gpio23";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
- pwdn {
+ pwdn-pins {
pins = "gpio133";
function = "gpio";
drive-strength = <16>;
@@ -1400,22 +1433,22 @@
};
};
- pcie0_state_on: pcie0-state-on {
- perst {
+ pcie0_state_on: pcie0-state-on-state {
+ perst-pins {
pins = "gpio35";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- clkreq {
+ clkreq-pins {
pins = "gpio36";
function = "pci_e0";
drive-strength = <2>;
bias-pull-up;
};
- wake {
+ wake-pins {
pins = "gpio37";
function = "gpio";
drive-strength = <2>;
@@ -1423,22 +1456,22 @@
};
};
- pcie0_state_off: pcie0-state-off {
- perst {
+ pcie0_state_off: pcie0-state-off-state {
+ perst-pins {
pins = "gpio35";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- clkreq {
+ clkreq-pins {
pins = "gpio36";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- wake {
+ wake-pins {
pins = "gpio37";
function = "gpio";
drive-strength = <2>;
@@ -1446,63 +1479,63 @@
};
};
- blsp1_uart2_default: blsp1-uart2-default {
+ blsp1_uart2_default: blsp1-uart2-default-state {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "blsp_uart2";
drive-strength = <16>;
bias-disable;
};
- blsp1_uart2_sleep: blsp1-uart2-sleep {
+ blsp1_uart2_sleep: blsp1-uart2-sleep-state {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c3_default: blsp1-i2c2-default {
+ blsp1_i2c3_default: blsp1-i2c3-default-state {
pins = "gpio47", "gpio48";
function = "blsp_i2c3";
drive-strength = <16>;
bias-disable;
};
- blsp1_i2c3_sleep: blsp1-i2c2-sleep {
+ blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
pins = "gpio47", "gpio48";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- blsp2_uart3_4pins_default: blsp2-uart2-4pins {
+ blsp2_uart3_4pins_default: blsp2-uart3-4pins-state {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
function = "blsp_uart9";
drive-strength = <16>;
bias-disable;
};
- blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
+ blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
function = "blsp_uart9";
drive-strength = <2>;
bias-disable;
};
- blsp2_i2c3_default: blsp2-i2c3 {
+ blsp2_i2c3_default: blsp2-i2c3-state-state {
pins = "gpio51", "gpio52";
function = "blsp_i2c9";
drive-strength = <16>;
bias-disable;
};
- blsp2_i2c3_sleep: blsp2-i2c3-sleep {
+ blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
pins = "gpio51", "gpio52";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- wcd_intr_default: wcd-intr-default{
+ wcd_intr_default: wcd-intr-default-state {
pins = "gpio54";
function = "gpio";
drive-strength = <2>;
@@ -1510,21 +1543,21 @@
input-enable;
};
- blsp2_i2c1_default: blsp2-i2c1 {
+ blsp2_i2c1_default: blsp2-i2c1-state {
pins = "gpio55", "gpio56";
function = "blsp_i2c7";
drive-strength = <16>;
bias-disable;
};
- blsp2_i2c1_sleep: blsp2-i2c0-sleep {
+ blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
pins = "gpio55", "gpio56";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- blsp2_i2c5_default: blsp2-i2c5 {
+ blsp2_i2c5_default: blsp2-i2c5-state {
pins = "gpio60", "gpio61";
function = "blsp_i2c11";
drive-strength = <2>;
@@ -1533,7 +1566,7 @@
/* Sleep state for BLSP2_I2C5 is missing.. */
- cdc_reset_active: cdc-reset-active {
+ cdc_reset_active: cdc-reset-active-state {
pins = "gpio64";
function = "gpio";
drive-strength = <16>;
@@ -1541,7 +1574,7 @@
output-high;
};
- cdc_reset_sleep: cdc-reset-sleep {
+ cdc_reset_sleep: cdc-reset-sleep-state {
pins = "gpio64";
function = "gpio";
drive-strength = <16>;
@@ -1549,15 +1582,15 @@
output-low;
};
- blsp2_spi6_default: blsp2-spi5-default {
- spi {
+ blsp2_spi6_default: blsp2-spi6-default-state {
+ spi-pins {
pins = "gpio85", "gpio86", "gpio88";
function = "blsp_spi12";
drive-strength = <12>;
bias-disable;
};
- cs {
+ cs-pins {
pins = "gpio87";
function = "gpio";
drive-strength = <16>;
@@ -1566,43 +1599,43 @@
};
};
- blsp2_spi6_sleep: blsp2-spi5-sleep {
+ blsp2_spi6_sleep: blsp2-spi6-sleep-state {
pins = "gpio85", "gpio86", "gpio87", "gpio88";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- blsp2_i2c6_default: blsp2-i2c6 {
+ blsp2_i2c6_default: blsp2-i2c6-state {
pins = "gpio87", "gpio88";
function = "blsp_i2c12";
drive-strength = <16>;
bias-disable;
};
- blsp2_i2c6_sleep: blsp2-i2c6-sleep {
+ blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
pins = "gpio87", "gpio88";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- pcie1_state_on: pcie1-state-on {
- perst {
+ pcie1_state_on: pcie1-on-state {
+ perst-pins {
pins = "gpio130";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- clkreq {
+ clkreq-pins {
pins = "gpio131";
function = "pci_e1";
drive-strength = <2>;
bias-pull-up;
};
- wake {
+ wake-pins {
pins = "gpio132";
function = "gpio";
drive-strength = <2>;
@@ -1610,16 +1643,16 @@
};
};
- pcie1_state_off: pcie1-state-off {
+ pcie1_state_off: pcie1-off-state {
/* Perst is missing? */
- clkreq {
+ clkreq-pins {
pins = "gpio131";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- wake {
+ wake-pins {
pins = "gpio132";
function = "gpio";
drive-strength = <2>;
@@ -1627,22 +1660,22 @@
};
};
- pcie2_state_on: pcie2-state-on {
- perst {
+ pcie2_state_on: pcie2-on-state {
+ perst-pins {
pins = "gpio114";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- clkreq {
+ clkreq-pins {
pins = "gpio115";
function = "pci_e2";
drive-strength = <2>;
bias-pull-up;
};
- wake {
+ wake-pins {
pins = "gpio116";
function = "gpio";
drive-strength = <2>;
@@ -1650,16 +1683,16 @@
};
};
- pcie2_state_off: pcie2-state-off {
+ pcie2_state_off: pcie2-off-state {
/* Perst is missing? */
- clkreq {
+ clkreq-pins {
pins = "gpio115";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- wake {
+ wake-pins {
pins = "gpio116";
function = "gpio";
drive-strength = <2>;
@@ -1667,90 +1700,90 @@
};
};
- sdc1_state_on: sdc1-state-on {
- clk {
+ sdc1_state_on: sdc1-on-state {
+ clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
- cmd {
+ cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
- data {
+ data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
- rclk {
+ rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
- sdc1_state_off: sdc1-state-off {
- clk {
+ sdc1_state_off: sdc1-off-state {
+ clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
- cmd {
+ cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
- data {
+ data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
- rclk {
+ rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
- sdc2_state_on: sdc2-clk-on {
- clk {
+ sdc2_state_on: sdc2-on-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
- cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
- data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
};
- sdc2_state_off: sdc2-clk-off {
- clk {
+ sdc2_state_off: sdc2-off-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
- cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
- data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
@@ -1995,10 +2028,6 @@
lanes-per-direction = <1>;
#reset-cells = <1>;
status = "disabled";
-
- ufs_variant {
- compatible = "qcom,ufs_variant";
- };
};
ufsphy: phy@627000 {
@@ -2205,9 +2234,9 @@
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
- clocks = <&mmcc GPU_AHB_CLK>,
- <&gcc GCC_MMSS_BIMC_GFX_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>,
+ <&mmcc GPU_AHB_CLK>;
+ clock-names = "bus", "iface";
power-domains = <&mmcc GPU_GDSC>;
};
@@ -2272,9 +2301,9 @@
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
- clocks = <&mmcc SMMU_MDP_AHB_CLK>,
- <&mmcc SMMU_MDP_AXI_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&mmcc SMMU_MDP_AXI_CLK>,
+ <&mmcc SMMU_MDP_AHB_CLK>;
+ clock-names = "bus", "iface";
power-domains = <&mmcc MDSS_GDSC>;
};
@@ -2292,9 +2321,9 @@
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
- clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
- <&mmcc SMMU_VIDEO_AXI_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&mmcc SMMU_VIDEO_AXI_CLK>,
+ <&mmcc SMMU_VIDEO_AHB_CLK>;
+ clock-names = "bus", "iface";
#iommu-cells = <1>;
status = "okay";
};
@@ -2308,10 +2337,9 @@
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
- clocks = <&mmcc SMMU_VFE_AHB_CLK>,
- <&mmcc SMMU_VFE_AXI_CLK>;
- clock-names = "iface",
- "bus";
+ clocks = <&mmcc SMMU_VFE_AXI_CLK>,
+ <&mmcc SMMU_VFE_AHB_CLK>;
+ clock-names = "bus", "iface";
#iommu-cells = <1>;
};
@@ -2336,9 +2364,9 @@
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
- <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>,
+ <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>;
+ clock-names = "bus", "iface";
};
slpi_pil: remoteproc@1c00000 {
@@ -3127,6 +3155,23 @@
status = "disabled";
};
+ blsp1_i2c6: i2c@757a000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x757a000 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_i2c6_default>;
+ pinctrl-1 = <&blsp1_i2c6_sleep>;
+ dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
blsp2_dma: dma-controller@7584000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07584000 0x2b000>;
@@ -3309,27 +3354,25 @@
qcom,num-ees = <2>;
};
- slim_msm: slim@91c0000 {
+ slim_msm: slim-ngd@91c0000 {
compatible = "qcom,slim-ngd-v1.5.0";
reg = <0x091c0000 0x2C000>;
- reg-names = "ctrl";
interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&slimbam 3>, <&slimbam 4>,
- <&slimbam 5>, <&slimbam 6>;
- dma-names = "rx", "tx", "tx2", "rx2";
+ dmas = <&slimbam 3>, <&slimbam 4>;
+ dma-names = "rx", "tx";
#address-cells = <1>;
#size-cells = <0>;
- ngd@1 {
+ slim@1 {
reg = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <0>;
- tasha_ifd: tas-ifd {
+ tasha_ifd: tas-ifd@0,0 {
compatible = "slim217,1a0";
reg = <0 0>;
};
- wcd9335: codec@1{
+ wcd9335: codec@1,0 {
pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
pinctrl-names = "default";
@@ -3342,7 +3385,7 @@
interrupt-names = "intr1", "intr2";
interrupt-controller;
#interrupt-cells = <1>;
- reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
slim-ifc-dev = <&tasha_ifd>;
@@ -3393,12 +3436,12 @@
#address-cells = <1>;
#size-cells = <0>;
- q6core {
+ service@3 {
reg = <APR_SVC_ADSP_CORE>;
compatible = "qcom,q6core";
};
- q6afe: q6afe {
+ q6afe: service@4 {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
q6afedai: dais {
@@ -3406,13 +3449,13 @@
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
- hdmi@1 {
+ dai@1 {
reg = <1>;
};
};
};
- q6asm: q6asm {
+ q6asm: service@7 {
compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>;
q6asmdai: dais {
@@ -3424,7 +3467,7 @@
};
};
- q6adm: q6adm {
+ q6adm: service@8 {
compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>;
q6routing: routing {
diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts
index ff4673ee9e81..d18d0b0eda95 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts
+++ b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts
@@ -5,6 +5,7 @@
/dts-v1/;
+#include "msm8996pro.dtsi"
#include "msm8996-xiaomi-common.dtsi"
#include "pmi8996.dtsi"
#include <dt-bindings/sound/qcom,q6afe.h>
@@ -12,7 +13,7 @@
/ {
model = "Xiaomi Mi 5s Plus";
- compatible = "xiaomi,natrium", "qcom,msm8996";
+ compatible = "xiaomi,natrium", "qcom,msm8996pro", "qcom,msm8996";
chassis-type = "handset";
qcom,msm-id = <305 0x10000>;
qcom,board-id = <47 0>;
@@ -164,7 +165,7 @@
};
&rpm_requests {
- pm8994-regulators {
+ regulators-0 {
vreg_l3a_0p875: l3 {
regulator-name = "vreg_l3a_0p875";
regulator-min-microvolt = <850000>;
@@ -398,14 +399,14 @@
"RFFE1_DATA", /* GPIO_148 */
"RFFE1_CLK"; /* GPIO_149 */
- touchscreen_default: touchscreen-default {
+ touchscreen_default: touchscreen-default-state {
pins = "gpio89", "gpio125";
function = "gpio";
drive-strength = <10>;
bias-pull-up;
};
- touchscreen_sleep: touchscreen-sleep {
+ touchscreen_sleep: touchscreen-sleep-state {
pins = "gpio89", "gpio125";
function = "gpio";
drive-strength = <2>;
diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts
index 79be5fb1295b..5e3b9130e9c2 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts
+++ b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts
@@ -5,6 +5,7 @@
/dts-v1/;
+#include "msm8996pro.dtsi"
#include "msm8996-xiaomi-common.dtsi"
#include "pmi8996.dtsi"
#include <dt-bindings/sound/qcom,q6afe.h>
@@ -13,7 +14,7 @@
/ {
model = "Xiaomi Mi Note 2";
- compatible = "xiaomi,scorpio", "qcom,msm8996";
+ compatible = "xiaomi,scorpio", "qcom,msm8996pro", "qcom,msm8996";
chassis-type = "handset";
qcom,msm-id = <305 0x10000>;
qcom,board-id = <34 0>;
@@ -216,7 +217,7 @@
};
&rpm_requests {
- pm8994-regulators {
+ regulators-0 {
vreg_l3a_0p875: l3 {
regulator-name = "vreg_l3a_0p875";
regulator-min-microvolt = <850000>;
@@ -468,28 +469,28 @@
"RFFE1_DATA", /* GPIO_148 */
"RFFE1_CLK"; /* GPIO_149 */
- touchkey_default: touchkey_default {
+ touchkey_default: touchkey-default-state {
pins = "gpio77";
function = "gpio";
drive-strength = <16>;
bias-pull-up;
};
- touchkey_sleep: touchkey_sleep {
+ touchkey_sleep: touchkey-sleep-state {
pins = "gpio77";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- touchscreen_default: touchscreen_default {
+ touchscreen_default: touchscreen-default-state {
pins = "gpio75", "gpio125";
function = "gpio";
drive-strength = <10>;
bias-pull-up;
};
- touchscreen_sleep: touchscreen_sleep {
+ touchscreen_sleep: touchscreen-sleep-state {
pins = "gpio75", "gpio125";
function = "gpio";
drive-strength = <2>;
diff --git a/arch/arm64/boot/dts/qcom/msm8996pro.dtsi b/arch/arm64/boot/dts/qcom/msm8996pro.dtsi
new file mode 100644
index 000000000000..a679a9c0cf99
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8996pro.dtsi
@@ -0,0 +1,291 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022, Linaro Limited
+ */
+
+#include "msm8996.dtsi"
+
+/ {
+ /delete-node/ opp-table-cluster0;
+ /delete-node/ opp-table-cluster1;
+
+ /*
+ * On MSM8996 Pro the cpufreq driver shifts speed bins into the high
+ * nibble of supported hw, so speed bin 0 becomes 0x10, speed bin 1
+ * becomes 0x20, speed 2 becomes 0x40.
+ */
+
+ cluster0_opp: opp-table-cluster0 {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+ opp-shared;
+
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-460800000 {
+ opp-hz = /bits/ 64 <460800000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-537600000 {
+ opp-hz = /bits/ 64 <537600000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-614400000 {
+ opp-hz = /bits/ 64 <614400000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-691200000 {
+ opp-hz = /bits/ 64 <691200000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-768000000 {
+ opp-hz = /bits/ 64 <768000000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-844800000 {
+ opp-hz = /bits/ 64 <844800000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-902400000 {
+ opp-hz = /bits/ 64 <902400000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-979200000 {
+ opp-hz = /bits/ 64 <979200000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1132800000 {
+ opp-hz = /bits/ 64 <1132800000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1209600000 {
+ opp-hz = /bits/ 64 <1209600000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1286400000 {
+ opp-hz = /bits/ 64 <1286400000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1440000000 {
+ opp-hz = /bits/ 64 <1440000000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1516800000 {
+ opp-hz = /bits/ 64 <1516800000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1593600000 {
+ opp-hz = /bits/ 64 <1593600000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1996800000 {
+ opp-hz = /bits/ 64 <1996800000>;
+ opp-supported-hw = <0x20>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2188800000 {
+ opp-hz = /bits/ 64 <2188800000>;
+ opp-supported-hw = <0x10>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
+ cluster1_opp: opp-table-cluster1 {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+ opp-shared;
+
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-460800000 {
+ opp-hz = /bits/ 64 <460800000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-537600000 {
+ opp-hz = /bits/ 64 <537600000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-614400000 {
+ opp-hz = /bits/ 64 <614400000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-691200000 {
+ opp-hz = /bits/ 64 <691200000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-748800000 {
+ opp-hz = /bits/ 64 <748800000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-825600000 {
+ opp-hz = /bits/ 64 <825600000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-902400000 {
+ opp-hz = /bits/ 64 <902400000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-979200000 {
+ opp-hz = /bits/ 64 <979200000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1132800000 {
+ opp-hz = /bits/ 64 <1132800000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1209600000 {
+ opp-hz = /bits/ 64 <1209600000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1286400000 {
+ opp-hz = /bits/ 64 <1286400000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1440000000 {
+ opp-hz = /bits/ 64 <1440000000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1516800000 {
+ opp-hz = /bits/ 64 <1516800000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1593600000 {
+ opp-hz = /bits/ 64 <1593600000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1670400000 {
+ opp-hz = /bits/ 64 <1670400000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1747200000 {
+ opp-hz = /bits/ 64 <1747200000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1824000000 {
+ opp-hz = /bits/ 64 <1824000000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ opp-supported-hw = <0x70>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1977600000 {
+ opp-hz = /bits/ 64 <1977600000>;
+ opp-supported-hw = <0x30>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2054400000 {
+ opp-hz = /bits/ 64 <2054400000>;
+ opp-supported-hw = <0x30>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2150400000 {
+ opp-hz = /bits/ 64 <2150400000>;
+ opp-supported-hw = <0x30>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2246400000 {
+ opp-hz = /bits/ 64 <2246400000>;
+ opp-supported-hw = <0x10>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2342400000 {
+ opp-hz = /bits/ 64 <2342400000>;
+ opp-supported-hw = <0x10>;
+ clock-latency-ns = <200000>;
+ };
+ };
+};
+
+&gpu_opp_table {
+ /*
+ * Unlike CPU opp tables, the GPU driver does not shift speed bins.
+ *
+ * 652.8 Mhz is available on speed bin 0 only.
+ * 624 Mhz and 560 Mhz are available on speed bins 0 and 1.
+ * All the rest are available on all bins of the hardware (like on
+ * plain 8996).
+ */
+
+ opp-652800000 {
+ opp-hz = /bits/ 64 <652800000>;
+ opp-supported-hw = <0x01>;
+ };
+ opp-624000000 {
+ opp-hz = /bits/ 64 <624000000>;
+ opp-supported-hw = <0x03>;
+ };
+ opp-560000000 {
+ opp-hz = /bits/ 64 <560000000>;
+ opp-supported-hw = <0x03>;
+ };
+ /* The rest is inherited from msm8996 */
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi b/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi
index 7928b8197474..3b7172aa4037 100644
--- a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi
@@ -35,7 +35,7 @@
};
&blsp1_uart3_on {
- rx {
+ rx-pins {
/delete-property/ bias-disable;
/*
* Configure a pull-up on 45 (RX). This is needed to
@@ -46,7 +46,7 @@
bias-pull-up;
};
- cts {
+ cts-pins {
/delete-property/ bias-disable;
/*
* Configure a pull-down on 47 (CTS) to match the pull
@@ -137,7 +137,7 @@
};
&rpm_requests {
- pm8998-regulators {
+ regulators-0 {
compatible = "qcom,rpm-pm8998-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -357,8 +357,9 @@
&tlmm {
gpio-reserved-ranges = <0 4>, <81 4>;
- touchpad: touchpad-pin {
+ touchpad: touchpad-pin-state {
pins = "gpio123";
+ function = "gpio";
bias-pull-up;
};
};
diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts
index 429ba57e20f7..310f7a2df1e8 100644
--- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts
+++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts
@@ -216,7 +216,7 @@
};
&blsp1_uart3_on {
- rx {
+ rx-pins {
/delete-property/ bias-disable;
/*
* Configure a pull-up on 45 (RX). This is needed to
@@ -227,7 +227,7 @@
bias-pull-up;
};
- cts {
+ cts-pins {
/delete-property/ bias-disable;
/*
* Configure a pull-down on 47 (CTS) to match the pull
@@ -310,15 +310,11 @@
};
&funnel4 {
- // FIXME: Figure out why clock late_initcall crashes the board with
- // this enabled.
- // status = "okay";
+ /* FIXME: Figure out why clock late_initcall crashes the board with this enabled. */
};
&funnel5 {
- // FIXME: Figure out why clock late_initcall crashes the board with
- // this enabled.
- // status = "okay";
+ /* FIXME: Figure out why clock late_initcall crashes the board with this enabled. */
};
&pcie0 {
@@ -390,7 +386,7 @@
};
&rpm_requests {
- pm8998-regulators {
+ regulators-0 {
compatible = "qcom,rpm-pm8998-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -588,7 +584,7 @@
};
- pmi8998-regulators {
+ regulators-1 {
compatible = "qcom,rpm-pmi8998-regulators";
vdd_bob-supply = <&vph_pwr>;
@@ -615,14 +611,14 @@
&tlmm {
gpio-reserved-ranges = <0 4>;
- mdp_vsync_n: mdp-vsync-n {
+ mdp_vsync_n: mdp-vsync-n-state {
pins = "gpio10";
function = "mdp_vsync_a";
bias-pull-down;
drive-strength = <2>;
};
- gpio_kb_pins_extra: gpio-kb-pins-extra {
+ gpio_kb_pins_extra: gpio-kb-pins-extra-state {
pins = "gpio21", "gpio32", "gpio33", "gpio114",
"gpio128", "gpio129";
function = "gpio";
@@ -630,21 +626,21 @@
bias-pull-up;
};
- ts_vio_default: ts-vio-def {
+ ts_vio_default: ts-vio-def-state {
pins = "gpio81";
function = "gpio";
bias-disable;
drive-strength = <2>;
};
- ts_rst_n: ts-rst-n {
+ ts_rst_n: ts-rst-n-state {
pins = "gpio89";
function = "gpio";
bias-pull-up;
drive-strength = <8>;
};
- hall_sensor1_default: hall-sensor1-def {
+ hall_sensor1_default: hall-sensor1-def-state {
pins = "gpio124";
function = "gpio";
bias-disable;
@@ -652,7 +648,7 @@
input-enable;
};
- ts_int_n: ts-int-n {
+ ts_int_n: ts-int-n-state {
pins = "gpio125";
function = "gpio";
bias-disable;
diff --git a/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts b/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts
index cf81c33a9d7e..a105143bee4a 100644
--- a/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts
+++ b/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts
@@ -28,8 +28,8 @@
};
&remoteproc_mss {
- firmware-name = "qcom/LENOVO/81F1/qcdsp1v28998.mbn",
- "qcom/LENOVO/81F1/qcdsp28998.mbn";
+ firmware-name = "qcom/msm8998/LENOVO/81F1/qcdsp1v28998.mbn",
+ "qcom/msm8998/LENOVO/81F1/qcdsp28998.mbn";
};
&sdhc2 {
diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts
index a3ca58100aee..453a1c9e9808 100644
--- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts
@@ -46,7 +46,7 @@
};
&blsp1_uart3_on {
- rx {
+ rx-pins {
/delete-property/ bias-disable;
/*
* Configure a pull-up on 45 (RX). This is needed to
@@ -57,7 +57,7 @@
bias-pull-up;
};
- cts {
+ cts-pins {
/delete-property/ bias-disable;
/*
* Configure a pull-down on 47 (CTS) to match the pull
@@ -124,15 +124,11 @@
};
&funnel4 {
- // FIXME: Figure out why clock late_initcall crashes the board with
- // this enabled.
- // status = "okay";
+ /* FIXME: Figure out why clock late_initcall crashes the board with this enabled. */
};
&funnel5 {
- // FIXME: Figure out why clock late_initcall crashes the board with
- // this enabled.
- // status = "okay";
+ /* FIXME: Figure out why clock late_initcall crashes the board with this enabled. */
};
&pcie0 {
@@ -168,7 +164,7 @@
};
&rpm_requests {
- pm8998-regulators {
+ regulators-0 {
compatible = "qcom,rpm-pm8998-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -366,7 +362,7 @@
};
- pmi8998-regulators {
+ regulators-1 {
compatible = "qcom,rpm-pmi8998-regulators";
vdd_bob-supply = <&vph_pwr>;
diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts b/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts
index ef2a88a64d32..9fb1fb9b8529 100644
--- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts
+++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts
@@ -22,7 +22,7 @@
pinctrl-names = "default";
pinctrl-0 = <&button_backlight_default>;
- button-backlight {
+ led-keypad-backlight {
gpios = <&pmi8998_gpio 5 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_KBD_BACKLIGHT;
@@ -33,11 +33,9 @@
&pmi8998_gpio {
button_backlight_default: button-backlight-state {
- pinconf {
- pins = "gpio5";
- function = "normal";
- bias-pull-down;
- qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
- };
+ pins = "gpio5";
+ function = "gpio";
+ bias-pull-down;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi
index 62bda23791bb..7d4a67d07501 100644
--- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi
@@ -233,7 +233,7 @@
};
&blsp1_uart3_on {
- rx {
+ rx-pins {
/delete-property/ bias-disable;
/*
* Configure a pull-up on 46 (RX). This is needed to
@@ -244,7 +244,7 @@
bias-pull-up;
};
- cts {
+ cts-pins {
/delete-property/ bias-disable;
/*
* Configure a pull-down on 47 (CTS) to match the pull
@@ -279,6 +279,10 @@
};
};
+&pmi8998_rradc {
+ status = "okay";
+};
+
&qusb2phy {
status = "okay";
@@ -288,7 +292,7 @@
};
&rpm_requests {
- pm8998-regulators {
+ regulators-0 {
compatible = "qcom,rpm-pm8998-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -477,7 +481,7 @@
vreg_lvs2a_1p8: lvs2 { };
};
- pmi8998-regulators {
+ regulators-1 {
compatible = "qcom,rpm-pmi8998-regulators";
vdd_bob-supply = <&vph_pwr>;
@@ -492,7 +496,7 @@
&tlmm {
gpio-reserved-ranges = <0 4>, <81 4>;
- hall_sensor_default: hall-sensor-default {
+ hall_sensor_default: hall-sensor-default-state {
pins = "gpio124";
function = "gpio";
drive-strength = <2>;
@@ -500,28 +504,28 @@
input-enable;
};
- ts_int_active: ts-int-active {
+ ts_int_active: ts-int-active-state {
pins = "gpio125";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
- ts_reset_active: ts-reset-active {
+ ts_reset_active: ts-reset-active-state {
pins = "gpio89";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
- nfc_int_active: nfc-int-active {
+ nfc_int_active: nfc-int-active-state {
pins = "gpio92";
function = "gpio";
drive-strength = <6>;
bias-pull-up;
};
- nfc_enable_active: nfc-enable-active {
+ nfc_enable_active: nfc-enable-active-state {
pins = "gpio12", "gpio116";
function = "gpio";
drive-strength = <6>;
diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi
index d08639082247..5da87baa2b23 100644
--- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi
@@ -375,7 +375,7 @@
};
&rpm_requests {
- pm8998-regulators {
+ regulators-0 {
compatible = "qcom,rpm-pm8998-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -410,135 +410,166 @@
regulator-min-microvolt = <1352000>;
regulator-max-microvolt = <1352000>;
};
+
vreg_s4a_1p8: s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-system-load = <100000>;
regulator-allow-set-load;
};
+
vreg_s5a_2p04: s5 {
regulator-min-microvolt = <1904000>;
regulator-max-microvolt = <2032000>;
};
+
vreg_s7a_1p025: s7 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1028000>;
};
+
vreg_l1a_0p875: l1 {
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
regulator-system-load = <73400>;
regulator-allow-set-load;
};
+
vreg_l2a_1p2: l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-system-load = <12560>;
regulator-allow-set-load;
};
+
vreg_l3a_1p0: l3 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
+
vreg_l5a_0p8: l5 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
};
+
vreg_l6a_1p8: l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
+
vreg_l7a_1p8: l7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
+
vreg_l8a_1p2: l8 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
+
vreg_l9a_1p8: l9 {
regulator-min-microvolt = <1808000>;
regulator-max-microvolt = <2960000>;
};
+
vreg_l10a_1p8: l10 {
regulator-min-microvolt = <1808000>;
regulator-max-microvolt = <2960000>;
};
+
vreg_l11a_1p0: l11 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
+
vreg_l12a_1p8: l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
+
vreg_l13a_2p95: l13 {
regulator-min-microvolt = <1808000>;
regulator-max-microvolt = <2960000>;
regulator-allow-set-load;
};
+
vreg_l14a_1p85: l14 {
regulator-min-microvolt = <1848000>;
regulator-max-microvolt = <1856000>;
regulator-system-load = <32000>;
regulator-allow-set-load;
};
+
vreg_l15a_1p8: l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
+
vreg_l16a_2p7: l16 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2704000>;
};
+
vreg_l17a_1p3: l17 {
regulator-min-microvolt = <1304000>;
regulator-max-microvolt = <1304000>;
};
- vreg_l18a_2p85: l18 {};
+
+ vreg_l18a_2p85: l18 { };
+
vreg_l19a_2p7: l19 {
regulator-min-microvolt = <2696000>;
regulator-max-microvolt = <2704000>;
};
+
vreg_l20a_2p95: l20 {
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <2960000>;
regulator-system-load = <10000>;
regulator-allow-set-load;
};
+
vreg_l21a_2p95: l21 {
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <2960000>;
regulator-system-load = <800000>;
regulator-allow-set-load;
};
+
vreg_l22a_2p85: l22 { };
+
vreg_l23a_3p3: l23 {
regulator-min-microvolt = <3312000>;
regulator-max-microvolt = <3312000>;
};
+
vreg_l24a_3p075: l24 {
regulator-min-microvolt = <3088000>;
regulator-max-microvolt = <3088000>;
};
+
vreg_l25a_3p3: l25 {
regulator-min-microvolt = <3104000>;
regulator-max-microvolt = <3312000>;
};
+
vreg_l26a_1p2: l26 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-allow-set-load;
};
+
vreg_l28_3p0: l28 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
+
vreg_lvs1a_1p8: lvs1 { };
+
vreg_lvs2a_1p8: lvs2 { };
};
- pmi8998-regulators {
+ regulators-1 {
compatible = "qcom,rpm-pmi8998-regulators";
vdd_bob-supply = <&vph_pwr>;
@@ -565,14 +596,14 @@
&tlmm {
gpio-reserved-ranges = <0 4>, <81 4>;
- mdp_vsync_n: mdp-vsync-n {
+ mdp_vsync_n: mdp-vsync-n-state {
pins = "gpio10";
function = "mdp_vsync_a";
drive-strength = <2>;
bias-pull-down;
};
- nfc_ven: nfc-ven {
+ nfc_ven: nfc-ven-state {
pins = "gpio12";
function = "gpio";
bias-disable;
@@ -580,42 +611,42 @@
output-low;
};
- msm_mclk0_default: msm-mclk0-active {
+ msm_mclk0_default: msm-mclk0-active-state {
pins = "gpio13";
function = "cam_mclk";
drive-strength = <2>;
bias-disable;
};
- msm_mclk1_default: msm-mclk1-active {
+ msm_mclk1_default: msm-mclk1-active-state {
pins = "gpio14";
function = "cam_mclk";
drive-strength = <2>;
bias-disable;
};
- cci0_default: cci0-default {
+ cci0_default: cci0-default-state {
pins = "gpio18", "gpio19";
function = "cci_i2c";
bias-disable;
drive-strength = <2>;
};
- cci1_default: cci1-default {
+ cci1_default: cci1-default-state {
pins = "gpio19", "gpio20";
function = "cci_i2c";
bias-disable;
drive-strength = <2>;
};
- cam0_vdig_default: cam0-vdig-default {
+ cam0_vdig_default: cam0-vdig-default-state {
pins = "gpio21";
function = "gpio";
bias-disable;
drive-strength = <2>;
};
- tof_int: tof-int {
+ tof_int: tof-int-state {
pins = "gpio22";
function = "gpio";
bias-pull-up;
@@ -623,28 +654,28 @@
input-enable;
};
- cam1_vdig_default: cam1-vdig-default {
+ cam1_vdig_default: cam1-vdig-default-state {
pins = "gpio25";
function = "gpio";
bias-disable;
drive-strength = <2>;
};
- usb_extcon_active: usb-extcon-active {
+ usb_extcon_active: usb-extcon-active-state {
pins = "gpio38";
function = "gpio";
bias-disable;
drive-strength = <16>;
};
- tof_reset: tof-reset {
+ tof_reset: tof-reset-state {
pins = "gpio27";
function = "gpio";
bias-disable;
drive-strength = <2>;
};
- hall_sensor0_default: acc-cover-open {
+ hall_sensor0_default: acc-cover-open-state {
pins = "gpio124";
function = "gpio";
bias-disable;
@@ -652,14 +683,14 @@
input-enable;
};
- ts_int_n: ts-int-n {
+ ts_int_n: ts-int-n-state {
pins = "gpio125";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
- usb_vbus_active: usb-vbus-active {
+ usb_vbus_active: usb-vbus-active-state {
pins = "gpio128";
function = "gpio";
bias-disable;
@@ -667,7 +698,7 @@
output-low;
};
- ts_vddio_en: ts-vddio-en-default {
+ ts_vddio_en: ts-vddio-en-default-state {
pins = "gpio133";
function = "gpio";
bias-disable;
diff --git a/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts b/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts
new file mode 100644
index 000000000000..b1aac7311ef9
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts
@@ -0,0 +1,711 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Xiaomi Mi 6 (sagit) device tree source based on msm8998-mtp.dtsi
+ *
+ * Copyright (c) 2022, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Degdag Mohamed <degdagmohamed@gmail.com>
+ * Copyright (c) 2022, Dzmitry Sankouski <dsankouski@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "msm8998.dtsi"
+#include "pm8005.dtsi"
+#include "pm8998.dtsi"
+#include "pmi8998.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+/*
+ * Delete following upstream (msm8998.dtsi) reserved
+ * memory mappings which are different in this device.
+ */
+/delete-node/ &adsp_mem;
+/delete-node/ &mpss_mem;
+/delete-node/ &venus_mem;
+/delete-node/ &mba_mem;
+/delete-node/ &slpi_mem;
+/delete-node/ &ipa_fw_mem;
+/delete-node/ &ipa_gsi_mem;
+/delete-node/ &gpu_mem;
+/delete-node/ &wlan_msa_mem;
+
+/ {
+ model = "Xiaomi Mi 6";
+ compatible = "xiaomi,sagit", "qcom,msm8998";
+ chassis-type = "handset";
+ /* Required for bootloader to select correct board */
+ qcom,board-id = <30 0>;
+
+ reserved-memory {
+ /*
+ * Xiaomi's ADSP firmware requires 30 MiB in total, so increase the adsp_mem
+ * region by 4 MiB to account for this while relocating the other now
+ * conflicting memory nodes accordingly.
+ */
+ adsp_mem: memory@8b200000 {
+ reg = <0x0 0x8b200000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ mpss_mem: memory@8d000000 {
+ reg = <0x0 0x8d000000 0x0 0x7000000>;
+ no-map;
+ };
+
+ venus_mem: memory@94000000 {
+ reg = <0x0 0x94000000 0x0 0x500000>;
+ no-map;
+ };
+
+ mba_mem: memory@94500000 {
+ reg = <0x0 0x94500000 0x0 0x200000>;
+ no-map;
+ };
+
+ slpi_mem: memory@94700000 {
+ reg = <0x0 0x94700000 0x0 0xf00000>;
+ no-map;
+ };
+
+ ipa_fw_mem: memory@95600000 {
+ reg = <0x0 0x95600000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: memory@95610000 {
+ reg = <0x0 0x95610000 0x0 0x5000>;
+ no-map;
+ };
+
+ gpu_mem: memory@95615000 {
+ reg = <0x0 0x95615000 0x0 0x100000>;
+ no-map;
+ };
+
+ wlan_msa_mem: memory@95715000 {
+ reg = <0x0 0x95715000 0x0 0x100000>;
+ no-map;
+ };
+
+ /* Bootloader display framebuffer region */
+ cont_splash_mem: memory@9d400000 {
+ reg = <0x0 0x9d400000 0x0 0x2400000>;
+ no-map;
+ };
+
+ /* For getting crash logs using Android downstream kernels */
+ ramoops@ac000000 {
+ compatible = "ramoops";
+ reg = <0x0 0xac000000 0x0 0x200000>;
+ console-size = <0x80000>;
+ pmsg-size = <0x40000>;
+ record-size = <0x8000>;
+ ftrace-size = <0x20000>;
+ };
+
+ /*
+ * The following memory regions on downstream are "dynamically allocated"
+ * but given the same addresses every time. Hard code them as these addresses
+ * are where the Xiaomi signed firmware expects them to be.
+ */
+ ipa_fws_region: memory@f7800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0xf7800000 0x0 0x5000>;
+ no-map;
+ };
+
+ zap_shader_region: memory@f7900000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0xf7900000 0x0 0x2000>;
+ no-map;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ label = "Volume buttons";
+ autorepeat;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&vol_up_key_default>;
+
+ key-vol-up {
+ label = "Volume up";
+ gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <15>;
+ wakeup-source;
+ };
+ };
+
+ gpio-hall-sensor {
+ compatible = "gpio-keys";
+ label = "Hall effect sensor";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&hall_sensor_default_state>;
+
+ event-hall-sensor {
+ label = "Hall Effect Sensor";
+ gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ disp_vddts_vreg: disp-vddts-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "disp-vddts-regulator";
+ gpio = <&tlmm 50 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+};
+
+&blsp1_i2c5 {
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+
+ touchscreen@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <125 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&ts_active_state>;
+ pinctrl-1 = <&ts_int_suspend_state &ts_reset_suspend_state>;
+
+ vdd-supply = <&disp_vddts_vreg>;
+ vio-supply = <&vreg_l6a_1p8>;
+
+ syna,reset-delay-ms = <20>;
+ syna,startup-delay-ms = <20>;
+
+ rmi4-f01@1 {
+ reg = <0x01>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f12@12 {
+ reg = <0x12>;
+ touchscreen-x-mm = <64>;
+ touchscreen-y-mm = <114>;
+ syna,sensor-type = <1>;
+ syna,rezero-wait-ms = <20>;
+ };
+
+ rmi4-f1a@1a {
+ reg = <0x1a>;
+ syna,codes = <KEY_BACK KEY_APPSELECT>;
+ };
+ };
+};
+
+&blsp1_i2c5_sleep {
+ /delete-property/ bias-pull-up;
+ bias-disable;
+};
+
+&blsp1_uart3 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn3990-bt";
+
+ vddio-supply = <&vreg_s4a_1p8>;
+ vddxo-supply = <&vreg_l7a_1p8>;
+ vddrf-supply = <&vreg_l17a_1p3>;
+ vddch0-supply = <&vreg_l25a_3p3>;
+ max-speed = <3200000>;
+ };
+};
+
+&blsp1_uart3_on {
+ rx-pins {
+ /delete-property/ bias-disable;
+ /*
+ * Configure a pull-up on 46 (RX). This is needed to
+ * avoid garbage data when the TX pin of the Bluetooth
+ * module is in tri-state (module powered off or not
+ * driving the signal yet).
+ */
+ bias-pull-up;
+ };
+
+ cts-pins {
+ /delete-property/ bias-disable;
+ /*
+ * Configure a pull-down on 47 (CTS) to match the pull
+ * of the Bluetooth module.
+ */
+ bias-pull-down;
+ };
+};
+
+&blsp2_uart1 {
+ status = "okay";
+};
+
+&pm8005_regulators {
+ compatible = "qcom,pm8005-regulators";
+
+ vdd_s1-supply = <&vph_pwr>;
+
+ pm8005_s1: s1 { /* VDD_GFX supply */
+ regulator-min-microvolt = <524000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-enable-ramp-delay = <500>;
+
+ /* hack until we rig up the gpu consumer */
+ regulator-always-on;
+ };
+};
+
+&pm8998_gpio {
+ vol_up_key_default: vol-up-key-default-state {
+ pins = "gpio6";
+ function = "normal";
+ bias-pull-up;
+ input-enable;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+ };
+
+ audio_mclk_pin: audio-mclk-pin-active-state {
+ pins = "gpio13";
+ function = "func2";
+ power-source = <0>;
+ };
+};
+
+&qusb2phy {
+ vdd-supply = <&vreg_l1a_0p875>;
+ vdda-pll-supply = <&vreg_l12a_1p8>;
+ vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
+ status = "okay";
+};
+
+&rpm_requests {
+ regulators-0 {
+ compatible = "qcom,rpm-pm8998-regulators";
+
+ vdd_s1-supply = <&vph_pwr>;
+ vdd_s2-supply = <&vph_pwr>;
+ vdd_s3-supply = <&vph_pwr>;
+ vdd_s4-supply = <&vph_pwr>;
+ vdd_s5-supply = <&vph_pwr>;
+ vdd_s6-supply = <&vph_pwr>;
+ vdd_s7-supply = <&vph_pwr>;
+ vdd_s8-supply = <&vph_pwr>;
+ vdd_s9-supply = <&vph_pwr>;
+ vdd_s10-supply = <&vph_pwr>;
+ vdd_s11-supply = <&vph_pwr>;
+ vdd_s12-supply = <&vph_pwr>;
+ vdd_s13-supply = <&vph_pwr>;
+ vdd_l1_l27-supply = <&vreg_s7a_1p025>;
+ vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>;
+ vdd_l3_l11-supply = <&vreg_s7a_1p025>;
+ vdd_l4_l5-supply = <&vreg_s7a_1p025>;
+ vdd_l6-supply = <&vreg_s5a_2p04>;
+ vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>;
+ vdd_l9-supply = <&vreg_bob>;
+ vdd_l10_l23_l25-supply = <&vreg_bob>;
+ vdd_l13_l19_l21-supply = <&vreg_bob>;
+ vdd_l16_l28-supply = <&vreg_bob>;
+ vdd_l18_l22-supply = <&vreg_bob>;
+ vdd_l20_l24-supply = <&vreg_bob>;
+ vdd_l26-supply = <&vreg_s3a_1p35>;
+ vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>;
+
+ vreg_s3a_1p35: s3 {
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ };
+
+ vreg_s4a_1p8: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-set-load;
+ };
+
+ vreg_s5a_2p04: s5 {
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2040000>;
+ };
+
+ vreg_s7a_1p025: s7 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1028000>;
+ };
+
+ vreg_l1a_0p875: l1 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ };
+
+ vreg_l2a_1p2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_l3a_1p0: l3 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ vreg_l5a_0p8: l5 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ };
+
+ vreg_l6a_1p8: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vreg_l7a_1p8: l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vreg_l8a_1p2: l8 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_l9a_1p8: l9 {
+ regulator-min-microvolt = <1808000>;
+ regulator-max-microvolt = <2960000>;
+ };
+
+ vreg_l10a_1p8: l10 {
+ regulator-min-microvolt = <1808000>;
+ regulator-max-microvolt = <2960000>;
+ };
+
+ vreg_l11a_1p0: l11 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ vreg_l12a_1p8: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vreg_l13a_2p95: l13 {
+ regulator-min-microvolt = <1808000>;
+ regulator-max-microvolt = <2960000>;
+ };
+
+ vreg_l14a_1p8: l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vreg_l15a_1p8: l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vreg_l16a_2p7: l16 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2704000>;
+ };
+
+ vreg_l17a_1p3: l17 {
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ };
+
+ vreg_l18a_2p7: l18 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2704000>;
+ };
+
+ vreg_l19a_3p0: l19 {
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ };
+
+ vreg_l20a_2p95: l20 {
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l21a_2p95: l21 {
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-system-load = <800000>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l22a_2p85: l22 {
+ regulator-min-microvolt = <2864000>;
+ regulator-max-microvolt = <2864000>;
+ };
+
+ vreg_l23a_3p3: l23 {
+ regulator-min-microvolt = <3312000>;
+ regulator-max-microvolt = <3312000>;
+ };
+
+ vreg_l24a_3p075: l24 {
+ regulator-min-microvolt = <3088000>;
+ regulator-max-microvolt = <3088000>;
+ };
+
+ vreg_l25a_3p3: l25 {
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3312000>;
+ };
+
+ vreg_l26a_1p2: l26 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l28_3p0: l28 {
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ };
+
+ vreg_lvs1a_1p8: lvs1 { };
+
+ vreg_lvs2a_1p8: lvs2 { };
+ };
+
+ regulators-1 {
+ compatible = "qcom,rpm-pmi8998-regulators";
+
+ vdd_bob-supply = <&vph_pwr>;
+
+ vreg_bob: bob {
+ regulator-min-microvolt = <3312000>;
+ regulator-max-microvolt = <3600000>;
+ };
+ };
+};
+
+&tlmm {
+ gpio-reserved-ranges = <0 4>, <81 4>;
+
+ cci1_default_state: cci1-default-state {
+ pins = "gpio19", "gpio20";
+ function = "cci_i2c";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cdc_reset_n_state: cdc-reset-n-state {
+ pins = "gpio64";
+ function = "gpio";
+ bias-pull-down;
+ drive-strength = <16>;
+ output-high;
+ };
+
+ hall_sensor_default_state: hall-sensor-default-state {
+ pins = "gpio124";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ input-enable;
+ };
+
+ mdss_dsi_active_state: mdss-dsi-active-state {
+ pins = "gpio94";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ mdss_dsi_suspend_state: mdss-dsi-suspend-state {
+ pins = "gpio94";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ mdss_te_active_state: mdss-te-active-state {
+ pins = "gpio10";
+ function = "mdp_vsync_a";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ mdss_te_suspend_state: mdss-te-suspend-state {
+ pins = "gpio10";
+ function = "mdp_vsync_a";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ msm_mclk0_active_state: msm-mclk0-active-state {
+ pins = "gpio13";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ msm_mclk0_suspend_state: msm-mclk0-suspend-state {
+ pins = "gpio13";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ msm_mclk1_active_state: msm-mclk1-active-state {
+ pins = "gpio14";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ msm_mclk1_suspend_state: msm-mclk1-suspend-state {
+ pins = "gpio14";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ nfc_int_active_state: nfc-int-active-state {
+ pins = "gpio92";
+ function = "gpio";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ nfc_int_suspend_state: nfc-int-suspend-state {
+ pins = "gpio92";
+ function = "gpio";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ nfc_enable_active_state: nfc-enable-active-state {
+ pins = "gpio12", "gpio116";
+ function = "gpio";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ nfc_enable_suspend_state: nfc-enable-suspend-state {
+ pins = "gpio12", "gpio116";
+ function = "gpio";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ ts_active_state: ts-active-state {
+ pins = "gpio89", "gpio125";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-pull-up;
+ input-enable;
+ };
+
+ ts_int_suspend_state: ts-int-suspend-state {
+ pins = "gpio125";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ ts_reset_suspend_state: ts-reset-suspend-state {
+ pins = "gpio89";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wcd_int_n_state: wcd-int-n-state {
+ pins = "gpio54";
+ function = "gpio";
+ bias-pull-down;
+ drive-strength = <2>;
+ input-enable;
+ };
+
+ wsa_leftspk_pwr_n_state: wsa-leftspk-pwr-n-state {
+ pins = "gpio65";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <2>;
+ output-low;
+ };
+
+ wsa_rightspk_pwr_n_state: wsa-rightspk-pwr-n-state {
+ pins = "gpio66";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <2>;
+ output-low;
+ };
+};
+
+&pm8998_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
+&ufshc {
+ vcc-supply = <&vreg_l20a_2p95>;
+ vccq-supply = <&vreg_l26a_1p2>;
+ vccq2-supply = <&vreg_s4a_1p8>;
+ vcc-max-microamp = <750000>;
+ vccq-max-microamp = <560000>;
+ vccq2-max-microamp = <750000>;
+ status = "okay";
+};
+
+&ufsphy {
+ vdda-phy-supply = <&vreg_l1a_0p875>;
+ vdda-pll-supply = <&vreg_l2a_1p2>;
+ vddp-ref-clk-supply = <&vreg_l26a_1p2>;
+ status = "okay";
+};
+
+&usb3 {
+ /* Disable USB3 clock requirement as the device only supports USB2 */
+ qcom,select-utmi-as-pipe-clk;
+ status = "okay";
+};
+
+&usb3_dwc3 {
+ /* Drop the unused USB 3 PHY */
+ phys = <&qusb2phy>;
+ phy-names = "usb2-phy";
+
+ /* Fastest mode for USB 2 */
+ maximum-speed = "high-speed";
+
+ /* Force to peripheral until we can switch modes */
+ dr_mode = "peripheral";
+};
+
+&wifi {
+ vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
+ vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
+ vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
+ vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index f05f16ac5cc1..539382dab0ad 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -900,7 +900,7 @@
};
pcie0: pci@1c00000 {
- compatible = "qcom,pcie-msm8996";
+ compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
reg = <0x01c00000 0x2000>,
<0x1b000000 0xf1d>,
<0x1b000f20 0xa8>,
@@ -929,11 +929,11 @@
<0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
- <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
- <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_0_AUX_CLK>;
- clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
+ clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
power-domains = <&gcc PCIE_0_GDSC>;
iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
@@ -1056,81 +1056,82 @@
compatible = "qcom,msm8998-pinctrl";
reg = <0x03400000 0xc00000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&tlmm 0 0 150>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- sdc2_on: sdc2-on {
- clk {
+ sdc2_on: sdc2-on-state {
+ clk-pins {
pins = "sdc2_clk";
drive-strength = <16>;
bias-disable;
};
- cmd {
+ cmd-pins {
pins = "sdc2_cmd";
drive-strength = <10>;
bias-pull-up;
};
- data {
+ data-pins {
pins = "sdc2_data";
drive-strength = <10>;
bias-pull-up;
};
};
- sdc2_off: sdc2-off {
- clk {
+ sdc2_off: sdc2-off-state {
+ clk-pins {
pins = "sdc2_clk";
drive-strength = <2>;
bias-disable;
};
- cmd {
+ cmd-pins {
pins = "sdc2_cmd";
drive-strength = <2>;
bias-pull-up;
};
- data {
+ data-pins {
pins = "sdc2_data";
drive-strength = <2>;
bias-pull-up;
};
};
- sdc2_cd: sdc2-cd {
+ sdc2_cd: sdc2-cd-state {
pins = "gpio95";
function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
- blsp1_uart3_on: blsp1-uart3-on {
- tx {
+ blsp1_uart3_on: blsp1-uart3-on-state {
+ tx-pins {
pins = "gpio45";
function = "blsp_uart3_a";
drive-strength = <2>;
bias-disable;
};
- rx {
+ rx-pins {
pins = "gpio46";
function = "blsp_uart3_a";
drive-strength = <2>;
bias-disable;
};
- cts {
+ cts-pins {
pins = "gpio47";
function = "blsp_uart3_a";
drive-strength = <2>;
bias-disable;
};
- rfr {
+ rfr-pins {
pins = "gpio48";
function = "blsp_uart3_a";
drive-strength = <2>;
@@ -1138,168 +1139,168 @@
};
};
- blsp1_i2c1_default: blsp1-i2c1-default {
+ blsp1_i2c1_default: blsp1-i2c1-default-state {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c1_sleep: blsp1-i2c1-sleep {
+ blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
drive-strength = <2>;
bias-pull-up;
};
- blsp1_i2c2_default: blsp1-i2c2-default {
+ blsp1_i2c2_default: blsp1-i2c2-default-state {
pins = "gpio32", "gpio33";
function = "blsp_i2c2";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c2_sleep: blsp1-i2c2-sleep {
+ blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
pins = "gpio32", "gpio33";
function = "blsp_i2c2";
drive-strength = <2>;
bias-pull-up;
};
- blsp1_i2c3_default: blsp1-i2c3-default {
+ blsp1_i2c3_default: blsp1-i2c3-default-state {
pins = "gpio47", "gpio48";
function = "blsp_i2c3";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c3_sleep: blsp1-i2c3-sleep {
+ blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
pins = "gpio47", "gpio48";
function = "blsp_i2c3";
drive-strength = <2>;
bias-pull-up;
};
- blsp1_i2c4_default: blsp1-i2c4-default {
+ blsp1_i2c4_default: blsp1-i2c4-default-state {
pins = "gpio10", "gpio11";
function = "blsp_i2c4";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c4_sleep: blsp1-i2c4-sleep {
+ blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
pins = "gpio10", "gpio11";
function = "blsp_i2c4";
drive-strength = <2>;
bias-pull-up;
};
- blsp1_i2c5_default: blsp1-i2c5-default {
+ blsp1_i2c5_default: blsp1-i2c5-default-state {
pins = "gpio87", "gpio88";
function = "blsp_i2c5";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c5_sleep: blsp1-i2c5-sleep {
+ blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
pins = "gpio87", "gpio88";
function = "blsp_i2c5";
drive-strength = <2>;
bias-pull-up;
};
- blsp1_i2c6_default: blsp1-i2c6-default {
+ blsp1_i2c6_default: blsp1-i2c6-default-state {
pins = "gpio43", "gpio44";
function = "blsp_i2c6";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c6_sleep: blsp1-i2c6-sleep {
+ blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
pins = "gpio43", "gpio44";
function = "blsp_i2c6";
drive-strength = <2>;
bias-pull-up;
};
/* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
- blsp2_i2c1_default: blsp2-i2c1-default {
+ blsp2_i2c1_default: blsp2-i2c1-default-state {
pins = "gpio55", "gpio56";
function = "blsp_i2c7";
drive-strength = <2>;
bias-disable;
};
- blsp2_i2c1_sleep: blsp2-i2c1-sleep {
+ blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
pins = "gpio55", "gpio56";
function = "blsp_i2c7";
drive-strength = <2>;
bias-pull-up;
};
- blsp2_i2c2_default: blsp2-i2c2-default {
+ blsp2_i2c2_default: blsp2-i2c2-default-state {
pins = "gpio6", "gpio7";
function = "blsp_i2c8";
drive-strength = <2>;
bias-disable;
};
- blsp2_i2c2_sleep: blsp2-i2c2-sleep {
+ blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
pins = "gpio6", "gpio7";
function = "blsp_i2c8";
drive-strength = <2>;
bias-pull-up;
};
- blsp2_i2c3_default: blsp2-i2c3-default {
+ blsp2_i2c3_default: blsp2-i2c3-default-state {
pins = "gpio51", "gpio52";
function = "blsp_i2c9";
drive-strength = <2>;
bias-disable;
};
- blsp2_i2c3_sleep: blsp2-i2c3-sleep {
+ blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
pins = "gpio51", "gpio52";
function = "blsp_i2c9";
drive-strength = <2>;
bias-pull-up;
};
- blsp2_i2c4_default: blsp2-i2c4-default {
+ blsp2_i2c4_default: blsp2-i2c4-default-state {
pins = "gpio67", "gpio68";
function = "blsp_i2c10";
drive-strength = <2>;
bias-disable;
};
- blsp2_i2c4_sleep: blsp2-i2c4-sleep {
+ blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
pins = "gpio67", "gpio68";
function = "blsp_i2c10";
drive-strength = <2>;
bias-pull-up;
};
- blsp2_i2c5_default: blsp2-i2c5-default {
+ blsp2_i2c5_default: blsp2-i2c5-default-state {
pins = "gpio60", "gpio61";
function = "blsp_i2c11";
drive-strength = <2>;
bias-disable;
};
- blsp2_i2c5_sleep: blsp2-i2c5-sleep {
+ blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
pins = "gpio60", "gpio61";
function = "blsp_i2c11";
drive-strength = <2>;
bias-pull-up;
};
- blsp2_i2c6_default: blsp2-i2c6-default {
+ blsp2_i2c6_default: blsp2-i2c6-default-state {
pins = "gpio83", "gpio84";
function = "blsp_i2c12";
drive-strength = <2>;
bias-disable;
};
- blsp2_i2c6_sleep: blsp2-i2c6-sleep {
+ blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
pins = "gpio83", "gpio84";
function = "blsp_i2c12";
drive-strength = <2>;
@@ -1903,7 +1904,7 @@
cpu = <&CPU4>;
- port{
+ port {
etm4_out: endpoint {
remote-endpoint = <&apss_funnel_in4>;
};
@@ -1920,7 +1921,7 @@
cpu = <&CPU5>;
- port{
+ port {
etm5_out: endpoint {
remote-endpoint = <&apss_funnel_in5>;
};
@@ -1937,7 +1938,7 @@
cpu = <&CPU6>;
- port{
+ port {
etm6_out: endpoint {
remote-endpoint = <&apss_funnel_in6>;
};
@@ -1954,7 +1955,7 @@
cpu = <&CPU7>;
- port{
+ port {
etm7_out: endpoint {
remote-endpoint = <&apss_funnel_in7>;
};
diff --git a/arch/arm64/boot/dts/qcom/pm6125.dtsi b/arch/arm64/boot/dts/qcom/pm6125.dtsi
new file mode 100644
index 000000000000..1c8ccda26ffb
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm6125.dtsi
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+ thermal-zones {
+ pm6125-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm6125_temp>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+&spmi_bus {
+ pmic@0 {
+ compatible = "qcom,pm6125", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm6125_pon: pon@800 {
+ compatible = "qcom,pm8998-pon";
+ reg = <0x800>;
+ mode-bootloader = <0x2>;
+ mode-recovery = <0x1>;
+
+ pon_pwrkey: pwrkey {
+ compatible = "qcom,pm8941-pwrkey";
+ interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ linux,code = <KEY_POWER>;
+ bias-pull-up;
+ status = "disabled";
+ };
+
+ pon_resin: resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ status = "disabled";
+ };
+ };
+
+ pm6125_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <&pm6125_adc ADC5_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm6125_adc: adc@3100 {
+ compatible = "qcom,spmi-adc5";
+ reg = <0x3100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+
+ ref-gnd@0 {
+ reg = <ADC5_REF_GND>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vref-1p25@1 {
+ reg = <ADC5_1P25VREF>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ die-temp@6 {
+ reg = <ADC5_DIE_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vph-pwr@83 {
+ reg = <ADC5_VPH_PWR>;
+ qcom,pre-scaling = <1 3>;
+ };
+
+ vcoin@85 {
+ reg = <ADC5_VCOIN>;
+ qcom,pre-scaling = <1 3>;
+ };
+
+ xo-therm@4c {
+ reg = <ADC5_XO_THERM_100K_PU>;
+ qcom,pre-scaling = <1 1>;
+ qcom,hw-settle-time = <200>;
+ qcom,ratiometric;
+ };
+ };
+
+ pm6125_adc_tm: adc-tm@3500 {
+ compatible = "qcom,spmi-adc-tm5";
+ reg = <0x3500>;
+ interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #thermal-sensor-cells = <1>;
+ status = "disabled";
+ };
+
+ pm6125_rtc: rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>, <0x6100>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ pm6125_gpio: gpio@c000 {
+ compatible = "qcom,pm6125-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ gpio-ranges = <&pm6125_gpio 0 0 9>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmic@1 {
+ compatible = "qcom,pm6125", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi
index 8a4972e6a24c..3d91fb405ca2 100644
--- a/arch/arm64/boot/dts/qcom/pm6150.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
-// Copyright (c) 2019, The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
@@ -86,7 +88,7 @@
status = "disabled";
};
- pm6150_gpio: gpios@c000 {
+ pm6150_gpio: gpio@c000 {
compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi
index f02c223ef448..90aac61ad264 100644
--- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi
@@ -1,10 +1,43 @@
// SPDX-License-Identifier: BSD-3-Clause
-// Copyright (c) 2019, The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
+/ {
+ thermal-zones {
+ pm6150l-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm6150l_temp>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+
+ trip2 {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
&spmi_bus {
pm6150l_lsid4: pmic@4 {
compatible = "qcom,pm6150l", "qcom,spmi-pmic";
@@ -12,6 +45,13 @@
#address-cells = <1>;
#size-cells = <0>;
+ pm6150l_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
pm6150l_adc: adc@3100 {
compatible = "qcom,spmi-adc5";
reg = <0x3100>;
@@ -55,7 +95,7 @@
status = "disabled";
};
- pm6150l_gpio: gpios@c000 {
+ pm6150l_gpio: gpio@c000 {
compatible = "qcom,pm6150l-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
diff --git a/arch/arm64/boot/dts/qcom/pm6350.dtsi b/arch/arm64/boot/dts/qcom/pm6350.dtsi
index ecf9b9919182..3a2a841e83f1 100644
--- a/arch/arm64/boot/dts/qcom/pm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm6350.dtsi
@@ -3,8 +3,40 @@
* Copyright (c) 2021, Luca Weiss <luca@z3ntu.xyz>
*/
+#include <dt-bindings/input/input.h>
#include <dt-bindings/spmi/spmi.h>
+/ {
+ thermal-zones {
+ pm6350-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm6350_temp>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+
+ trip2 {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
&spmi_bus {
pmic@0 {
compatible = "qcom,pm6350", "qcom,spmi-pmic";
@@ -35,7 +67,14 @@
};
};
- pm6350_gpios: gpios@c000 {
+ pm6350_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm6350_gpios: gpio@c000 {
compatible = "qcom,pm6350-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi
index e1622b16c08b..fc0eccaccdf6 100644
--- a/arch/arm64/boot/dts/qcom/pm660.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm660.dtsi
@@ -163,14 +163,14 @@
qcom,pre-scaling = <1 3>;
};
- vcoin: vcoin@83 {
+ vcoin: vcoin@85 {
reg = <ADC5_VCOIN>;
qcom,decimation = <1024>;
qcom,pre-scaling = <1 3>;
};
};
- pm660_gpios: gpios@c000 {
+ pm660_gpios: gpio@c000 {
compatible = "qcom,pm660-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi
index 8aa0a5078772..f9b3864bd3b9 100644
--- a/arch/arm64/boot/dts/qcom/pm660l.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi
@@ -48,7 +48,7 @@
#thermal-sensor-cells = <0>;
};
- pm660l_gpios: gpios@c000 {
+ pm660l_gpios: gpio@c000 {
compatible = "qcom,pm660l-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
diff --git a/arch/arm64/boot/dts/qcom/pm7325.dtsi b/arch/arm64/boot/dts/qcom/pm7325.dtsi
index e7f64a9ddc9c..d1c5476af5ee 100644
--- a/arch/arm64/boot/dts/qcom/pm7325.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm7325.dtsi
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
-// Copyright (c) 2021, The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
@@ -18,7 +20,7 @@
#thermal-sensor-cells = <0>;
};
- pm7325_gpios: gpios@8800 {
+ pm7325_gpios: gpio@8800 {
compatible = "qcom,pm7325-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
diff --git a/arch/arm64/boot/dts/qcom/pm8005.dtsi b/arch/arm64/boot/dts/qcom/pm8005.dtsi
index 50fb6c753bf8..8d4b081b4e9d 100644
--- a/arch/arm64/boot/dts/qcom/pm8005.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8005.dtsi
@@ -11,7 +11,7 @@
#address-cells = <1>;
#size-cells = <0>;
- pm8005_gpio: gpios@c000 {
+ pm8005_gpio: gpio@c000 {
compatible = "qcom,pm8005-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi
index cdded791d96e..66752cc063d6 100644
--- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi
@@ -53,7 +53,7 @@
status = "disabled";
};
- pm8150b_vbus: dcdc@1100 {
+ pm8150b_vbus: usb-vbus-regulator@1100 {
compatible = "qcom,pm8150b-vbus-reg";
status = "disabled";
reg = <0x1100>;
diff --git a/arch/arm64/boot/dts/qcom/pm8450a.dtsi b/arch/arm64/boot/dts/qcom/pm8450a.dtsi
new file mode 100644
index 000000000000..34fc72896761
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm8450a.dtsi
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited
+ */
+
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+ pm8450a: pmic@0 {
+ compatible = "qcom,pm8150", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8450a_gpios: gpio@c000 {
+ compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ gpio-ranges = <&pm8450a_gpios 0 0 10>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pm8450c: pmic@4 {
+ compatible = "qcom,pm8150", "qcom,spmi-pmic";
+ reg = <0x4 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8450c_gpios: gpio@c000 {
+ compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ gpio-ranges = <&pm8450c_gpios 0 0 10>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pm8450e: pmic@8 {
+ compatible = "qcom,pm8150", "qcom,spmi-pmic";
+ reg = <0x8 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8450e_gpios: gpio@c000 {
+ compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ gpio-ranges = <&pm8450e_gpios 0 0 10>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pm8450g: pmic@c {
+ compatible = "qcom,pm8150", "qcom,spmi-pmic";
+ reg = <0xc SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8450g_gpios: gpio@c000 {
+ compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ gpio-ranges = <&pm8450g_gpios 0 0 10>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi
index 606c2a6d1f0f..08f9ca006e72 100644
--- a/arch/arm64/boot/dts/qcom/pm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi
@@ -107,7 +107,7 @@
#interrupt-cells = <2>;
};
- pm8916_gpios: gpios@c000 {
+ pm8916_gpios: gpio@c000 {
compatible = "qcom,pm8916-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
diff --git a/arch/arm64/boot/dts/qcom/pm8950.dtsi b/arch/arm64/boot/dts/qcom/pm8950.dtsi
new file mode 100644
index 000000000000..07c3896bd36f
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm8950.dtsi
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022, AngeloGioacchino Del Regno
+ * <angelogioacchino.delregno@somainline.org>
+ * Copyright (c) 2022, Marijn Suijten <marijn.suijten@somainline.org>
+ */
+
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+ pmic@0 {
+ compatible = "qcom,pm8950", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pon@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x0800>;
+ mode-bootloader = <0x2>;
+ mode-recovery = <0x1>;
+
+ pwrkey {
+ compatible = "qcom,pm8941-pwrkey";
+ interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = <KEY_POWER>;
+ };
+ };
+
+ pm8950_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <&pm8950_vadc VADC_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8950_vadc: adc@3100 {
+ compatible = "qcom,spmi-vadc";
+ reg = <0x3100>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ vcoin@5 {
+ reg = <VADC_VCOIN>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vph-pwr@7 {
+ reg = <VADC_VSYS>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ die-temp@8 {
+ reg = <VADC_DIE_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref-625mv@9 {
+ reg = <VADC_REF_625MV>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref-1250mv@a {
+ reg = <VADC_REF_1250MV>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref-buf-625mv@c {
+ reg = <VADC_SPARE1>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref-gnd@e {
+ reg = <VADC_GND_REF>;
+ };
+
+ ref-vdd@f {
+ reg = <VADC_VDD_VADC>;
+ };
+
+ pa-therm1@11 {
+ reg = <VADC_P_MUX2_1_1>;
+ qcom,pre-scaling = <1 1>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ case-therm@13 {
+ reg = <VADC_P_MUX4_1_1>;
+ qcom,pre-scaling = <1 1>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ xo-therm@32 {
+ reg = <VADC_LR_MUX3_XO_THERM>;
+ qcom,pre-scaling = <1 1>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ pa-therm0@36 {
+ reg = <VADC_LR_MUX7_HW_ID>;
+ qcom,pre-scaling = <1 1>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ xo-therm-buf@3c {
+ reg = <VADC_LR_MUX3_BUF_XO_THERM>;
+ qcom,pre-scaling = <1 1>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+ };
+
+ rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+ };
+
+ pm8950_mpps: mpps@a000 {
+ compatible = "qcom,pm8950-mpp", "qcom,spmi-mpp";
+ reg = <0xa000>;
+ gpio-controller;
+ gpio-ranges = <&pm8950_mpps 0 0 4>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pm8950_gpio: gpio@c000 {
+ compatible = "qcom,pm8950-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ gpio-ranges = <&pm8950_gpio 0 0 8>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmic@1 {
+ compatible = "qcom,pm8950", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8950_spmi_regulators: regulators {
+ compatible = "qcom,pm8950-regulators";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi
index e92e5ac414d3..672094c8ca58 100644
--- a/arch/arm64/boot/dts/qcom/pm8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi
@@ -108,7 +108,7 @@
};
};
- pm8994_gpios: gpios@c000 {
+ pm8994_gpios: gpio@c000 {
compatible = "qcom,pm8994-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi
index d09f2954b6f9..6a5854333b2b 100644
--- a/arch/arm64/boot/dts/qcom/pm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi
@@ -52,6 +52,14 @@
bias-pull-up;
linux,code = <KEY_POWER>;
};
+
+ pm8998_resin: resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <GIC_SPI 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ status = "disabled";
+ };
};
pm8998_temp: temp-alarm@2400 {
@@ -63,7 +71,7 @@
#thermal-sensor-cells = <0>;
};
- pm8998_coincell: coincell@2800 {
+ pm8998_coincell: charger@2800 {
compatible = "qcom,pm8941-coincell";
reg = <0x2800>;
@@ -101,7 +109,7 @@
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
- pm8998_gpio: gpios@c000 {
+ pm8998_gpio: gpio@c000 {
compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
diff --git a/arch/arm64/boot/dts/qcom/pmi8950.dtsi b/arch/arm64/boot/dts/qcom/pmi8950.dtsi
new file mode 100644
index 000000000000..32d27e2187e3
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmi8950.dtsi
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2019, AngeloGioacchino Del Regno <kholk11@gmail.com>
+
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+ pmic@2 {
+ compatible = "qcom,pmi8950", "qcom,spmi-pmic";
+ reg = <0x2 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmi8950_vadc: adc@3100 {
+ compatible = "qcom,spmi-vadc";
+ reg = <0x3100>;
+ interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ adc-chan@0 {
+ reg = <VADC_USBIN>;
+ qcom,pre-scaling = <1 4>;
+ label = "usbin";
+ };
+
+ adc-chan@1 {
+ reg = <VADC_DCIN>;
+ qcom,pre-scaling = <1 4>;
+ label = "dcin";
+ };
+
+ adc-chan@2 {
+ reg = <VADC_VCHG_SNS>;
+ qcom,pre-scaling = <1 1>;
+ label = "vchg_sns";
+ };
+
+ adc-chan@9 {
+ reg = <VADC_REF_625MV>;
+ qcom,pre-scaling = <1 1>;
+ label = "ref_625mv";
+ };
+
+ adc-chan@a {
+ reg = <VADC_REF_1250MV>;
+ qcom,pre-scaling = <1 1>;
+ label = "ref_1250v";
+ };
+
+ adc-chan@d {
+ reg = <VADC_SPARE2>;
+ qcom,pre-scaling = <1 1>;
+ label = "chg_temp";
+ };
+ };
+
+ pmi8950_mpps: mpps@a000 {
+ compatible = "qcom,pmi8950-mpp", "qcom,spmi-mpp";
+ reg = <0xa000>;
+ gpio-controller;
+ gpio-ranges = <&pmi8950_mpps 0 0 4>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pmi8950_gpio: gpio@c000 {
+ compatible = "qcom,pmi8950-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ gpio-ranges = <&pmi8950_gpio 0 0 2>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmic@3 {
+ compatible = "qcom,pmi8950", "qcom,spmi-pmic";
+ reg = <0x3 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmi8950_wled: leds@d800 {
+ compatible = "qcom,pmi8950-wled";
+ reg = <0xd800>, <0xd900>;
+ interrupts = <0x3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "short";
+ label = "backlight";
+
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi
index 542c215dde10..a0af91698d49 100644
--- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi
@@ -10,7 +10,7 @@
#address-cells = <1>;
#size-cells = <0>;
- pmi8994_gpios: gpios@c000 {
+ pmi8994_gpios: gpio@c000 {
compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi
index 3852a012bb0f..cd1caeae8281 100644
--- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi
@@ -9,7 +9,7 @@
#address-cells = <1>;
#size-cells = <0>;
- pmi8998_gpio: gpios@c000 {
+ pmi8998_gpio: gpio@c000 {
compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
@@ -18,6 +18,14 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ pmi8998_rradc: adc@4500 {
+ compatible = "qcom,pmi8998-rradc";
+ reg = <0x4500>;
+ #io-channel-cells = <1>;
+
+ status = "disabled";
+ };
};
pmi8998_lsid1: pmic@3 {
diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi
index a7ec9d11946d..32f5e6af8c11 100644
--- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi
@@ -8,27 +8,33 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
+/* (Sadly) this PMIC can be configured to be at different SIDs */
+#ifndef PMK8350_SID
+ #define PMK8350_SID 0
+#endif
+
&spmi_bus {
- pmk8350: pmic@0 {
+ pmk8350: pmic@PMK8350_SID {
compatible = "qcom,pmk8350", "qcom,spmi-pmic";
- reg = <0x0 SPMI_USID>;
+ reg = <PMK8350_SID SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmk8350_pon: pon@1300 {
compatible = "qcom,pm8998-pon";
- reg = <0x1300>;
+ reg = <0x1300>, <0x800>;
+ reg-names = "hlos", "pbs";
pon_pwrkey: pwrkey {
compatible = "qcom,pmk8350-pwrkey";
- interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
+ interrupts = <PMK8350_SID 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
linux,code = <KEY_POWER>;
status = "disabled";
};
pon_resin: resin {
compatible = "qcom,pmk8350-resin";
- interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
+ interrupts = <PMK8350_SID 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
status = "disabled";
};
};
@@ -38,14 +44,14 @@
reg = <0x3100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <PMK8350_SID 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
#io-channel-cells = <1>;
};
pmk8350_adc_tm: adc-tm@3400 {
compatible = "qcom,adc-tm7";
reg = <0x3400>;
- interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <PMK8350_SID 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#thermal-sensor-cells = <1>;
@@ -56,7 +62,7 @@
compatible = "qcom,pmk8350-rtc";
reg = <0x6100>, <0x6200>;
reg-names = "rtc", "alarm";
- interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <PMK8350_SID 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/qcom/pmp8074.dtsi b/arch/arm64/boot/dts/qcom/pmp8074.dtsi
new file mode 100644
index 000000000000..ceb2e6358b3d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
+
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&spmi_bus {
+ pmic@0 {
+ compatible = "qcom,pmp8074", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmp8074_adc: adc@3100 {
+ compatible = "qcom,spmi-adc-rev2";
+ reg = <0x3100>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ ref-gnd@0 {
+ reg = <ADC5_REF_GND>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vref-1p25@1 {
+ reg = <ADC5_1P25VREF>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vref-vadc@2 {
+ reg = <ADC5_VREF_VADC>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pmic_die: die-temp@6 {
+ reg = <ADC5_DIE_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ xo_therm: xo-temp@76 {
+ reg = <ADC5_XO_THERM_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm1: thermistor1@77 {
+ reg = <ADC5_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm2: thermistor2@78 {
+ reg = <ADC5_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm3: thermistor3@79 {
+ reg = <ADC5_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vph-pwr@131 {
+ reg = <ADC5_VPH_PWR>;
+ qcom,pre-scaling = <1 3>;
+ };
+ };
+
+ pmp8074_rtc: rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+ allow-set-time;
+ status = "disabled";
+ };
+
+ pmp8074_gpios: gpio@c000 {
+ compatible = "qcom,pmp8074-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmp8074_gpios 0 0 12>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmic@1 {
+ compatible = "qcom,pmp8074", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+
+ regulators {
+ compatible = "qcom,pmp8074-regulators";
+
+ s3: s3 {
+ regulator-name = "vdd_s3";
+ regulator-min-microvolt = <592000>;
+ regulator-max-microvolt = <1064000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ s4: s4 {
+ regulator-name = "vdd_s4";
+ regulator-min-microvolt = <712000>;
+ regulator-max-microvolt = <992000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ l11: l11 {
+ regulator-name = "l11";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi
index 634b0681d04c..ffe9e33808d0 100644
--- a/arch/arm64/boot/dts/qcom/pms405.dtsi
+++ b/arch/arm64/boot/dts/qcom/pms405.dtsi
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
-// Copyright (c) 2018, Linaro Limited
+/*
+ * Copyright (c) 2018, Linaro Limited
+ */
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/input/linux-event-codes.h>
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts b/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts
index 937eb4555ffe..fc29b194cd34 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
-// Copyright (c) 2018, Linaro Limited
+/*
+ * Copyright (c) 2018, Linaro Limited
+ */
/dts-v1/;
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts
index 08d5d51221cf..59702ba24f35 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
-// Copyright (c) 2018, Linaro Limited
+/*
+ * Copyright (c) 2018, Linaro Limited
+ */
/dts-v1/;
@@ -37,54 +39,54 @@
};
&tlmm {
- ethernet_defaults: ethernet-defaults {
- int {
+ ethernet_defaults: ethernet-defaults-state {
+ int-pins {
pins = "gpio61";
function = "rgmii_int";
bias-disable;
drive-strength = <2>;
};
- mdc {
+ mdc-pins {
pins = "gpio76";
function = "rgmii_mdc";
bias-pull-up;
};
- mdio {
+ mdio-pins {
pins = "gpio75";
function = "rgmii_mdio";
bias-pull-up;
};
- tx {
+ tx-pins {
pins = "gpio67", "gpio66", "gpio65", "gpio64";
function = "rgmii_tx";
bias-pull-up;
drive-strength = <16>;
};
- rx {
+ rx-pins {
pins = "gpio73", "gpio72", "gpio71", "gpio70";
function = "rgmii_rx";
bias-disable;
drive-strength = <2>;
};
- tx-ctl {
+ tx-ctl-pins {
pins = "gpio68";
function = "rgmii_ctl";
bias-pull-up;
drive-strength = <16>;
};
- rx-ctl {
+ rx-ctl-pins {
pins = "gpio74";
function = "rgmii_ctl";
bias-disable;
drive-strength = <2>;
};
- tx-ck {
+ tx-ck-pins {
pins = "gpio63";
function = "rgmii_ck";
bias-pull-up;
drive-strength = <16>;
};
- rx-ck {
+ rx-ck-pins {
pins = "gpio69";
function = "rgmii_ck";
bias-disable;
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index 1678ef0f8684..04c82d1624eb 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
-// Copyright (c) 2018, Linaro Limited
+/*
+ * Copyright (c) 2018, Linaro Limited
+ */
#include <dt-bindings/gpio/gpio.h>
#include "qcs404.dtsi"
@@ -125,7 +127,7 @@
};
&rpm_requests {
- pms405-regulators {
+ regulators {
compatible = "qcom,rpm-pms405-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -229,7 +231,7 @@
};
&tlmm {
- perst_state: perst {
+ perst_state: perst-state {
pins = "gpio43";
function = "gpio";
@@ -238,68 +240,63 @@
output-low;
};
- sdc1_on: sdc1-on {
- clk {
+ sdc1_on: sdc1-on-state {
+ clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
- cmd {
+ cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
- data {
+ data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
- rclk {
+ rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
- sdc1_off: sdc1-off {
- clk {
+ sdc1_off: sdc1-off-state {
+ clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
- cmd {
+ cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
- data {
+ data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
- rclk {
+ rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
- usb3_id_pin: usb3-id-pin {
- pinmux {
- pins = "gpio116";
- function = "gpio";
- };
+ usb3_id_pin: usb3-id-state {
+ pins = "gpio116";
+ function = "gpio";
- pinconf {
- pins = "gpio116";
- drive-strength = <2>;
- bias-pull-up;
- input-enable;
- };
+ drive-strength = <2>;
+ bias-pull-up;
+ input-enable;
};
};
@@ -366,31 +363,28 @@
/* PINCTRL - additions to nodes defined in qcs404.dtsi */
&blsp1_uart2_default {
- rx {
+ rx-pins {
drive-strength = <2>;
bias-disable;
};
- tx {
+ tx-pins {
drive-strength = <2>;
bias-disable;
};
};
&blsp1_uart3_default {
- cts {
- pins = "gpio84";
+ cts-pins {
bias-disable;
};
- rts-tx {
- pins = "gpio85", "gpio82";
+ rts-tx-pins {
drive-strength = <2>;
bias-disable;
};
- rx {
- pins = "gpio83";
+ rx-pins {
bias-pull-up;
};
};
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 80f2d05595fa..a5324eecb50a 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
-// Copyright (c) 2018, Linaro Limited
+/*
+ * Copyright (c) 2018, Linaro Limited
+ */
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
@@ -593,118 +595,130 @@
interrupt-controller;
#interrupt-cells = <2>;
- blsp1_i2c0_default: blsp1-i2c0-default {
+ blsp1_i2c0_default: blsp1-i2c0-default-state {
pins = "gpio32", "gpio33";
function = "blsp_i2c0";
};
- blsp1_i2c1_default: blsp1-i2c1-default {
+ blsp1_i2c1_default: blsp1-i2c1-default-state {
pins = "gpio24", "gpio25";
function = "blsp_i2c1";
};
- blsp1_i2c2_default: blsp1-i2c2-default {
- sda {
+ blsp1_i2c2_default: blsp1-i2c2-default-state {
+ sda-pins {
pins = "gpio19";
function = "blsp_i2c_sda_a2";
};
- scl {
+ scl-pins {
pins = "gpio20";
function = "blsp_i2c_scl_a2";
};
};
- blsp1_i2c3_default: blsp1-i2c3-default {
+ blsp1_i2c3_default: blsp1-i2c3-default-state {
pins = "gpio84", "gpio85";
function = "blsp_i2c3";
};
- blsp1_i2c4_default: blsp1-i2c4-default {
+ blsp1_i2c4_default: blsp1-i2c4-default-state {
pins = "gpio117", "gpio118";
function = "blsp_i2c4";
};
- blsp1_uart0_default: blsp1-uart0-default {
+ blsp1_uart0_default: blsp1-uart0-default-state {
pins = "gpio30", "gpio31", "gpio32", "gpio33";
function = "blsp_uart0";
};
- blsp1_uart1_default: blsp1-uart1-default {
+ blsp1_uart1_default: blsp1-uart1-default-state {
pins = "gpio22", "gpio23";
function = "blsp_uart1";
};
- blsp1_uart2_default: blsp1-uart2-default {
- rx {
+ blsp1_uart2_default: blsp1-uart2-default-state {
+ rx-pins {
pins = "gpio18";
function = "blsp_uart_rx_a2";
};
- tx {
+ tx-pins {
pins = "gpio17";
function = "blsp_uart_tx_a2";
};
};
- blsp1_uart3_default: blsp1-uart3-default {
- pins = "gpio82", "gpio83", "gpio84", "gpio85";
- function = "blsp_uart3";
+ blsp1_uart3_default: blsp1-uart3-default-state {
+ cts-pins {
+ pins = "gpio84";
+ function = "blsp_uart3";
+ };
+
+ rts-tx-pins {
+ pins = "gpio85", "gpio82";
+ function = "blsp_uart3";
+ };
+
+ rx-pins {
+ pins = "gpio83";
+ function = "blsp_uart3";
+ };
};
- blsp2_i2c0_default: blsp2-i2c0-default {
+ blsp2_i2c0_default: blsp2-i2c0-default-state {
pins = "gpio28", "gpio29";
function = "blsp_i2c5";
};
- blsp1_spi0_default: blsp1-spi0-default {
+ blsp1_spi0_default: blsp1-spi0-default-state {
pins = "gpio30", "gpio31", "gpio32", "gpio33";
function = "blsp_spi0";
};
- blsp1_spi1_default: blsp1-spi1-default {
- mosi {
+ blsp1_spi1_default: blsp1-spi1-default-state {
+ mosi-pins {
pins = "gpio22";
function = "blsp_spi_mosi_a1";
};
- miso {
+ miso-pins {
pins = "gpio23";
function = "blsp_spi_miso_a1";
};
- cs_n {
+ cs-n-pins {
pins = "gpio24";
function = "blsp_spi_cs_n_a1";
};
- clk {
+ clk-pins {
pins = "gpio25";
function = "blsp_spi_clk_a1";
};
};
- blsp1_spi2_default: blsp1-spi2-default {
+ blsp1_spi2_default: blsp1-spi2-default-state {
pins = "gpio17", "gpio18", "gpio19", "gpio20";
function = "blsp_spi2";
};
- blsp1_spi3_default: blsp1-spi3-default {
+ blsp1_spi3_default: blsp1-spi3-default-state {
pins = "gpio82", "gpio83", "gpio84", "gpio85";
function = "blsp_spi3";
};
- blsp1_spi4_default: blsp1-spi4-default {
+ blsp1_spi4_default: blsp1-spi4-default-state {
pins = "gpio37", "gpio38", "gpio117", "gpio118";
function = "blsp_spi4";
};
- blsp2_spi0_default: blsp2-spi0-default {
+ blsp2_spi0_default: blsp2-spi0-default-state {
pins = "gpio26", "gpio27", "gpio28", "gpio29";
function = "blsp_spi5";
};
- blsp2_uart0_default: blsp2-uart0-default {
+ blsp2_uart0_default: blsp2-uart0-default-state {
pins = "gpio26", "gpio27", "gpio28", "gpio29";
function = "blsp_uart5";
};
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5-vision-mezzanine.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5-vision-mezzanine.dts
new file mode 100644
index 000000000000..bb149e577914
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5-vision-mezzanine.dts
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022, Linaro Ltd.
+ */
+
+/dts-v1/;
+
+#include "qrb5165-rb5.dts"
+
+&camcc {
+ status = "okay";
+};
+
+&camss {
+ vdda-phy-supply = <&vreg_l5a_0p88>;
+ vdda-pll-supply = <&vreg_l9a_1p2>;
+ status = "okay";
+
+ ports {
+ /* The port index denotes CSIPHY id i.e. csiphy2 */
+ port@2 {
+ csiphy2_ep: endpoint {
+ clock-lanes = <7>;
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&imx577_ep>;
+ };
+ };
+ };
+};
+
+&cci1 {
+ status = "okay";
+};
+
+&cci1_i2c0 {
+ camera@1a {
+ compatible = "sony,imx577";
+ reg = <0x1a>;
+
+ reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "suspend";
+ pinctrl-0 = <&cam2_default>;
+ pinctrl-1 = <&cam2_suspend>;
+
+ clocks = <&camcc CAM_CC_MCLK2_CLK>;
+ assigned-clocks = <&camcc CAM_CC_MCLK2_CLK>;
+ assigned-clock-rates = <24000000>;
+
+ dovdd-supply = <&vreg_l7f_1p8>;
+ avdd-supply = <&vdc_5v>;
+ dvdd-supply = <&vdc_5v>;
+
+ port {
+ imx577_ep: endpoint {
+ clock-lanes = <1>;
+ link-frequencies = /bits/ 64 <600000000>;
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&csiphy2_ep>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
index bf8077a1cf9a..8c64cb060e21 100644
--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
@@ -867,7 +867,7 @@
};
&q6afedai {
- qi2s@16 {
+ dai@16 {
reg = <PRIMARY_MI2S_RX>;
qcom,sd-lines = <0 1 2 3>;
};
@@ -875,7 +875,7 @@
/* TERT I2S Uses 1 I2S SD Lines for audio on LT9611 HDMI Bridge */
&q6afedai {
- qi2s@20 {
+ dai@20 {
reg = <TERTIARY_MI2S_RX>;
qcom,sd-lines = <0>;
};
@@ -904,7 +904,7 @@
cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
bus-width = <4>;
no-sdio;
- no-emmc;
+ no-mmc;
};
&sound {
@@ -1007,7 +1007,7 @@
};
&swr0 {
- left_spkr: wsa8810-left{
+ left_spkr: speaker@0,3 {
compatible = "sdw10217211000";
reg = <0 3>;
powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>;
@@ -1016,7 +1016,7 @@
#sound-dai-cells = <0>;
};
- right_spkr: wsa8810-right{
+ right_spkr: speaker@0,4 {
compatible = "sdw10217211000";
reg = <0 4>;
powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>;
@@ -1210,33 +1210,33 @@
"HST_WLAN_UART_TX",
"HST_WLAN_UART_RX";
- lt9611_irq_pin: lt9611-irq {
+ lt9611_irq_pin: lt9611-irq-state {
pins = "gpio63";
function = "gpio";
bias-disable;
};
- sdc2_default_state: sdc2-default {
- clk {
+ sdc2_default_state: sdc2-default-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
- cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
- data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
};
- sdc2_card_det_n: sd-card-det-n {
+ sdc2_card_det_n: sd-card-det-n-state {
pins = "gpio77";
function = "gpio";
bias-pull-up;
diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
index 4dee790f1049..f41dcc379dce 100644
--- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
@@ -136,9 +136,8 @@
regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
- regulator-allowed-modes =
- <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a_1p8: ldo7 {
@@ -154,9 +153,8 @@
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
- regulator-allowed-modes =
- <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11a_0p8: ldo11 {
@@ -263,9 +261,8 @@
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
- regulator-allowed-modes =
- <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c_1p8: ldo7 {
@@ -281,9 +278,8 @@
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
- regulator-allowed-modes =
- <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10c_3p3: ldo10 {
@@ -397,7 +393,7 @@
vmmc-supply = <&vreg_l17a_2p96>; /* Card power line */
bus-width = <4>;
no-sdio;
- no-emmc;
+ no-mmc;
};
&uart2 {
@@ -488,26 +484,26 @@
&tlmm {
gpio-reserved-ranges = <0 4>;
- sdc2_on: sdc2_on {
- clk {
+ sdc2_on: sdc2-on-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable; /* No pull */
drive-strength = <16>; /* 16 MA */
};
- cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
- data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
- sd-cd {
+ sd-cd-pins {
pins = "gpio96";
function = "gpio";
bias-pull-up; /* pull up */
@@ -515,26 +511,26 @@
};
};
- sdc2_off: sdc2_off {
- clk {
+ sdc2_off: sdc2-off-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable; /* No pull */
drive-strength = <2>; /* 2 MA */
};
- cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
- data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
- sd-cd {
+ sd-cd-pins {
pins = "gpio96";
function = "gpio";
bias-pull-up; /* pull up */
@@ -542,66 +538,62 @@
};
};
- usb2phy_ac_en1_default: usb2phy_ac_en1_default {
- mux {
- pins = "gpio113";
- function = "usb2phy_ac";
- bias-disable;
- drive-strength = <2>;
- };
+ usb2phy_ac_en1_default: usb2phy-ac-en1-default-state {
+ pins = "gpio113";
+ function = "usb2phy_ac";
+ bias-disable;
+ drive-strength = <2>;
};
- usb2phy_ac_en2_default: usb2phy_ac_en2_default {
- mux {
- pins = "gpio123";
- function = "usb2phy_ac";
- bias-disable;
- drive-strength = <2>;
- };
+ usb2phy_ac_en2_default: usb2phy-ac-en2-default-state {
+ pins = "gpio123";
+ function = "usb2phy_ac";
+ bias-disable;
+ drive-strength = <2>;
};
- ethernet_defaults: ethernet-defaults {
- mdc {
+ ethernet_defaults: ethernet-defaults-state {
+ mdc-pins {
pins = "gpio7";
function = "rgmii";
bias-pull-up;
};
- mdio {
+ mdio-pins {
pins = "gpio59";
function = "rgmii";
bias-pull-up;
};
- rgmii-rx {
+ rgmii-rx-pins {
pins = "gpio117", "gpio118", "gpio119", "gpio120", "gpio115", "gpio116";
function = "rgmii";
bias-disable;
drive-strength = <2>;
};
- rgmii-tx {
+ rgmii-tx-pins {
pins = "gpio122", "gpio4", "gpio5", "gpio6", "gpio114", "gpio121";
function = "rgmii";
bias-pull-up;
drive-strength = <16>;
};
- phy-intr {
+ phy-intr-pins {
pins = "gpio124";
function = "emac_phy";
bias-disable;
drive-strength = <8>;
};
- pps {
+ pps-pins {
pins = "gpio81";
function = "emac_pps";
bias-disable;
drive-strength = <8>;
};
- phy-reset {
+ phy-reset-pins {
pins = "gpio79";
function = "gpio";
bias-pull-up;
diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
index 2c62ba6a49c5..84cb6f3eeb56 100644
--- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
@@ -57,6 +57,13 @@
regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
+
+ vreg_l11a: ldo11 {
+ regulator-name = "vreg_l11a";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
};
pmm8540-c-regulators {
@@ -83,9 +90,8 @@
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
- regulator-allowed-modes =
- <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4c: ldo4 {
@@ -101,9 +107,8 @@
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
- regulator-allowed-modes =
- <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c: ldo7 {
@@ -119,9 +124,8 @@
regulator-max-microvolt = <2504000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
- regulator-allowed-modes =
- <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l17c: ldo17 {
@@ -130,9 +134,8 @@
regulator-max-microvolt = <2504000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
- regulator-allowed-modes =
- <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
};
@@ -163,6 +166,76 @@
};
};
+&pcie2a {
+ perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2a_default>;
+
+ status = "okay";
+};
+
+&pcie2a_phy {
+ vdda-phy-supply = <&vreg_l11a>;
+ vdda-pll-supply = <&vreg_l3a>;
+
+ status = "okay";
+};
+
+&pcie3a {
+ num-lanes = <2>;
+
+ perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3a_default>;
+
+ status = "okay";
+};
+
+&pcie3a_phy {
+ vdda-phy-supply = <&vreg_l11a>;
+ vdda-pll-supply = <&vreg_l3a>;
+
+ status = "okay";
+};
+
+&pcie3b {
+ perst-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3b_default>;
+
+ status = "okay";
+};
+
+&pcie3b_phy {
+ vdda-phy-supply = <&vreg_l11a>;
+ vdda-pll-supply = <&vreg_l3a>;
+
+ status = "okay";
+};
+
+&pcie4 {
+ perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie4_default>;
+
+ status = "okay";
+};
+
+&pcie4_phy {
+ vdda-phy-supply = <&vreg_l11a>;
+ vdda-pll-supply = <&vreg_l3a>;
+
+ status = "okay";
+};
+
&qup2 {
status = "okay";
};
@@ -194,6 +267,14 @@
#address-cells = <1>;
#size-cells = <0>;
+ rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+ wakeup-source;
+ };
+
pm8450a_gpios: gpio@c000 {
compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
@@ -392,3 +473,97 @@
};
/* PINCTRL */
+
+&tlmm {
+ pcie2a_default: pcie2a-default-state {
+ clkreq-n-pins {
+ pins = "gpio142";
+ function = "pcie2a_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio143";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-n-pins {
+ pins = "gpio145";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie3a_default: pcie3a-default-state {
+ clkreq-n-pins {
+ pins = "gpio150";
+ function = "pcie3a_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio151";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-n-pins {
+ pins = "gpio56";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie3b_default: pcie3b-default-state {
+ clkreq-n-pins {
+ pins = "gpio152";
+ function = "pcie3b_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio153";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-n-pins {
+ pins = "gpio130";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie4_default: pcie4-default-state {
+ clkreq-n-pins {
+ pins = "gpio140";
+ function = "pcie4_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio141";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-n-pins {
+ pins = "gpio139";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
new file mode 100644
index 000000000000..6c547f1b13dc
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "sa8540p.dtsi"
+#include "pm8450a.dtsi"
+
+/ {
+ model = "Qualcomm SA8540P Ride";
+ compatible = "qcom,sa8540p-ride", "qcom,sa8540p";
+
+ aliases {
+ serial0 = &qup2_uart17;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8150-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vreg_l3a: ldo3 {
+ regulator-name = "vreg_l3a";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1208000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5a: ldo5 {
+ regulator-name = "vreg_l5a";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7a: ldo7 {
+ regulator-name = "vreg_l7a";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11a: ldo11 {
+ regulator-name = "vreg_l11a";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13a: ldo13 {
+ regulator-name = "vreg_l13a";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8150-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vreg_l1c: ldo1 {
+ regulator-name = "vreg_l1c";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c: ldo2 {
+ regulator-name = "vreg_l2c";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4c: ldo4 {
+ regulator-name = "vreg_l4c";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1208000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6c: ldo6 {
+ regulator-name = "vreg_l6c";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l7c: ldo7 {
+ regulator-name = "vreg_l7c";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17c: ldo17 {
+ regulator-name = "vreg_l17c";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8150-rpmh-regulators";
+ qcom,pmic-id = "g";
+
+ vreg_l3g: ldo3 {
+ regulator-name = "vreg_l3g";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7g: ldo7 {
+ regulator-name = "vreg_l7g";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8g: ldo8 {
+ regulator-name = "vreg_l8g";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&pcie3a {
+ ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>,
+ <0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>;
+
+ perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3a_default>;
+
+ status = "okay";
+};
+
+&pcie3a_phy {
+ vdda-phy-supply = <&vreg_l11a>;
+ vdda-pll-supply = <&vreg_l3a>;
+
+ status = "okay";
+};
+
+&qup2 {
+ status = "okay";
+};
+
+&qup2_uart17 {
+ compatible = "qcom,geni-debug-uart";
+ status = "okay";
+};
+
+&remoteproc_nsp0 {
+ firmware-name = "qcom/sa8540p/cdsp.mbn";
+ status = "okay";
+};
+
+&remoteproc_nsp1 {
+ firmware-name = "qcom/sa8540p/cdsp1.mbn";
+ status = "okay";
+};
+
+&tlmm {
+ pcie3a_default: pcie3a-default-state {
+ perst-pins {
+ pins = "gpio151";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq-pins {
+ pins = "gpio150";
+ function = "pcie3a_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-pins {
+ pins = "gpio56";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l17c>;
+ vccq-supply = <&vreg_l6c>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l8g>;
+ vdda-pll-supply = <&vreg_l3g>;
+
+ status = "okay";
+};
+
+&usb_0 {
+ status = "okay";
+};
+
+&usb_0_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_0_hsphy {
+ vdda-pll-supply = <&vreg_l5a>;
+ vdda18-supply = <&vreg_l7a>;
+ vdda33-supply = <&vreg_l13a>;
+
+ status = "okay";
+};
+
+&usb_0_qmpphy {
+ vdda-phy-supply = <&vreg_l3a>;
+ vdda-pll-supply = <&vreg_l5a>;
+
+ status = "okay";
+};
+
+&usb_2_hsphy0 {
+ vdda-pll-supply = <&vreg_l5a>;
+ vdda18-supply = <&vreg_l7g>;
+ vdda33-supply = <&vreg_l13a>;
+
+ status = "okay";
+};
+
+&usb_2_qmpphy0 {
+ vdda-phy-supply = <&vreg_l3a>;
+ vdda-pll-supply = <&vreg_l5a>;
+
+ status = "okay";
+};
+
+&xo_board_clk {
+ clock-frequency = <38400000>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi
index 8ea2886fbab2..a88452c20d05 100644
--- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi
@@ -14,59 +14,81 @@
compatible = "operating-points-v2";
opp-shared;
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-peak-kBps = <(300000 * 32)>;
+ };
opp-403200000 {
opp-hz = /bits/ 64 <403200000>;
+ opp-peak-kBps = <(384000 * 32)>;
};
opp-499200000 {
opp-hz = /bits/ 64 <499200000>;
+ opp-peak-kBps = <(480000 * 32)>;
};
opp-595200000 {
opp-hz = /bits/ 64 <595200000>;
+ opp-peak-kBps = <(576000 * 32)>;
};
opp-710400000 {
opp-hz = /bits/ 64 <710400000>;
+ opp-peak-kBps = <(672000 * 32)>;
};
opp-806400000 {
opp-hz = /bits/ 64 <806400000>;
+ opp-peak-kBps = <(768000 * 32)>;
};
opp-902400000 {
opp-hz = /bits/ 64 <902400000>;
+ opp-peak-kBps = <(864000 * 32)>;
};
opp-1017600000 {
opp-hz = /bits/ 64 <1017600000>;
+ opp-peak-kBps = <(960000 * 32)>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
+ opp-peak-kBps = <(1075200 * 32)>;
};
opp-1209600000 {
opp-hz = /bits/ 64 <1209600000>;
+ opp-peak-kBps = <(1171200 * 32)>;
};
opp-1324800000 {
opp-hz = /bits/ 64 <1324800000>;
+ opp-peak-kBps = <(1286400 * 32)>;
};
opp-1440000000 {
opp-hz = /bits/ 64 <1440000000>;
+ opp-peak-kBps = <(1382400 * 32)>;
};
opp-1555200000 {
opp-hz = /bits/ 64 <1555200000>;
+ opp-peak-kBps = <(1497600 * 32)>;
};
opp-1670400000 {
opp-hz = /bits/ 64 <1670400000>;
+ opp-peak-kBps = <(1593600 * 32)>;
};
opp-1785600000 {
opp-hz = /bits/ 64 <1785600000>;
+ opp-peak-kBps = <(1708800 * 32)>;
};
opp-1881600000 {
opp-hz = /bits/ 64 <1881600000>;
+ opp-peak-kBps = <(1708800 * 32)>;
};
opp-2016000000 {
opp-hz = /bits/ 64 <2016000000>;
+ opp-peak-kBps = <(1708800 * 32)>;
};
opp-2131200000 {
opp-hz = /bits/ 64 <2131200000>;
+ opp-peak-kBps = <(1708800 * 32)>;
};
opp-2246400000 {
opp-hz = /bits/ 64 <2246400000>;
+ opp-peak-kBps = <(1708800 * 32)>;
};
};
@@ -76,58 +98,134 @@
opp-825600000 {
opp-hz = /bits/ 64 <825600000>;
+ opp-peak-kBps = <(300000 * 32)>;
};
opp-940800000 {
opp-hz = /bits/ 64 <940800000>;
+ opp-peak-kBps = <(864000 * 32)>;
};
opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
+ opp-peak-kBps = <(960000 * 32)>;
};
opp-1171200000 {
opp-hz = /bits/ 64 <1171200000>;
+ opp-peak-kBps = <(1171200 * 32)>;
};
opp-1286400000 {
opp-hz = /bits/ 64 <1286400000>;
+ opp-peak-kBps = <(1286400 * 32)>;
};
opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
+ opp-peak-kBps = <(1382400 * 32)>;
};
opp-1516800000 {
opp-hz = /bits/ 64 <1516800000>;
+ opp-peak-kBps = <(1497600 * 32)>;
};
opp-1632000000 {
opp-hz = /bits/ 64 <1632000000>;
+ opp-peak-kBps = <(1593600 * 32)>;
};
opp-1747200000 {
opp-hz = /bits/ 64 <1747200000>;
+ opp-peak-kBps = <(1593600 * 32)>;
};
opp-1862400000 {
opp-hz = /bits/ 64 <1862400000>;
+ opp-peak-kBps = <(1708800 * 32)>;
};
opp-1977600000 {
opp-hz = /bits/ 64 <1977600000>;
+ opp-peak-kBps = <(1708800 * 32)>;
};
opp-2073600000 {
opp-hz = /bits/ 64 <2073600000>;
+ opp-peak-kBps = <(1708800 * 32)>;
};
opp-2169600000 {
opp-hz = /bits/ 64 <2169600000>;
+ opp-peak-kBps = <(1708800 * 32)>;
};
opp-2284800000 {
opp-hz = /bits/ 64 <2284800000>;
+ opp-peak-kBps = <(1708800 * 32)>;
};
opp-2380800000 {
opp-hz = /bits/ 64 <2380800000>;
+ opp-peak-kBps = <(1708800 * 32)>;
};
opp-2496000000 {
opp-hz = /bits/ 64 <2496000000>;
+ opp-peak-kBps = <(1708800 * 32)>;
};
opp-2592000000 {
opp-hz = /bits/ 64 <2592000000>;
+ opp-peak-kBps = <(1708800 * 32)>;
};
};
};
+&pcie2a {
+ compatible = "qcom,pcie-sa8540p";
+
+ linux,pci-domain = <0>;
+
+ interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+};
+
+&pcie2b {
+ compatible = "qcom,pcie-sa8540p";
+
+ linux,pci-domain = <1>;
+
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+};
+
+&pcie3a {
+ compatible = "qcom,pcie-sa8540p";
+ reg = <0x0 0x01c10000 0x0 0x3000>,
+ <0x0 0x40000000 0x0 0xf1d>,
+ <0x0 0x40000f20 0x0 0xa8>,
+ <0x0 0x40001000 0x0 0x1000>,
+ <0x0 0x40100000 0x0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+
+ ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1d00000>;
+
+ linux,pci-domain = <2>;
+
+ interrupts = <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&pcie3b {
+ compatible = "qcom,pcie-sa8540p";
+
+ linux,pci-domain = <3>;
+
+ interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+};
+
+&pcie4 {
+ compatible = "qcom,pcie-sa8540p";
+
+ linux,pci-domain = <4>;
+
+ interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+};
+
&rpmhpd {
compatible = "qcom,sa8540p-rpmhpd";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
index 9dee131b1e24..70fd9ff8dfa2 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -481,287 +481,261 @@
};
&qspi_clk {
- pinconf {
- pins = "gpio63";
- bias-disable;
- };
+ bias-disable;
};
&qspi_cs0 {
- pinconf {
- pins = "gpio68";
- bias-disable;
- };
+ bias-disable;
};
&qspi_data01 {
- pinconf {
- pins = "gpio64", "gpio65";
-
- /* High-Z when no transfers; nice to park the lines */
- bias-pull-up;
- };
+ /* High-Z when no transfers; nice to park the lines */
+ bias-pull-up;
};
&qup_i2c2_default {
- pinconf {
- pins = "gpio15", "gpio16";
- drive-strength = <2>;
+ drive-strength = <2>;
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
&qup_i2c4_default {
- pinconf {
- pins = "gpio115", "gpio116";
- drive-strength = <2>;
+ drive-strength = <2>;
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
&qup_i2c7_default {
- pinconf {
- pins = "gpio6", "gpio7";
- drive-strength = <2>;
+ drive-strength = <2>;
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
&qup_i2c9_default {
- pinconf {
- pins = "gpio46", "gpio47";
- drive-strength = <2>;
+ drive-strength = <2>;
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
-&qup_uart3_default {
- pinconf-cts {
- /*
- * Configure a pull-down on CTS to match the pull of
- * the Bluetooth module.
- */
- pins = "gpio38";
- bias-pull-down;
- };
+&qup_uart3_cts {
+ /*
+ * Configure a pull-down on CTS to match the pull of
+ * the Bluetooth module.
+ */
+ bias-pull-down;
+};
- pinconf-rts {
- /* We'll drive RTS, so no pull */
- pins = "gpio39";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_uart3_rts {
+ /* We'll drive RTS, so no pull */
+ drive-strength = <2>;
+ bias-disable;
+};
- pinconf-tx {
- /* We'll drive TX, so no pull */
- pins = "gpio40";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_uart3_tx {
+ /* We'll drive TX, so no pull */
+ drive-strength = <2>;
+ bias-disable;
+};
- pinconf-rx {
- /*
- * Configure a pull-up on RX. This is needed to avoid
- * garbage data when the TX pin of the Bluetooth module is
- * in tri-state (module powered off or not driving the
- * signal yet).
- */
- pins = "gpio41";
- bias-pull-up;
- };
+&qup_uart3_rx {
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module is
+ * in tri-state (module powered off or not driving the
+ * signal yet).
+ */
+ bias-pull-up;
};
-&qup_uart8_default {
- pinconf-tx {
- pins = "gpio44";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_uart8_tx {
+ drive-strength = <2>;
+ bias-disable;
+};
- pinconf-rx {
- pins = "gpio45";
- drive-strength = <2>;
- bias-pull-up;
- };
+&qup_uart8_rx {
+ drive-strength = <2>;
+ bias-pull-up;
};
-&qup_spi0_default {
- pinconf {
- pins = "gpio34", "gpio35", "gpio36", "gpio37";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_spi0_spi {
+ drive-strength = <2>;
+ bias-disable;
};
-&qup_spi6_default {
- pinconf {
- pins = "gpio59", "gpio60", "gpio61", "gpio62";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_spi0_cs {
+ drive-strength = <2>;
+ bias-disable;
};
-&qup_spi10_default {
- pinconf {
- pins = "gpio86", "gpio87", "gpio88", "gpio89";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_spi6_spi {
+ drive-strength = <2>;
+ bias-disable;
};
-&tlmm {
- qup_uart3_sleep: qup-uart3-sleep {
- pinmux {
- pins = "gpio38", "gpio39",
- "gpio40", "gpio41";
- function = "gpio";
- };
+&qup_spi6_cs {
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_spi10_spi {
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_spi10_cs {
+ drive-strength = <2>;
+ bias-disable;
+};
- pinconf-cts {
+&tlmm {
+ qup_uart3_sleep: qup-uart3-sleep-state {
+ cts-pins {
/*
* Configure a pull-down on CTS to match the pull of
* the Bluetooth module.
*/
pins = "gpio38";
+ function = "gpio";
bias-pull-down;
};
- pinconf-rts {
+ rts-pins {
/*
* Configure pull-down on RTS. As RTS is active low
* signal, pull it low to indicate the BT SoC that it
* can wakeup the system anytime from suspend state by
* pulling RX low (by sending wakeup bytes).
*/
- pins = "gpio39";
- bias-pull-down;
+ pins = "gpio39";
+ function = "gpio";
+ bias-pull-down;
};
- pinconf-tx {
+ tx-pins {
/*
* Configure pull-up on TX when it isn't actively driven
* to prevent BT SoC from receiving garbage during sleep.
*/
pins = "gpio40";
+ function = "gpio";
bias-pull-up;
};
- pinconf-rx {
+ rx-pins {
/*
* Configure a pull-up on RX. This is needed to avoid
* garbage data when the TX pin of the Bluetooth module
* is floating which may cause spurious wakeups.
*/
pins = "gpio41";
+ function = "gpio";
bias-pull-up;
};
};
- sdc1_on: sdc1-on {
- pinconf-clk {
+ sdc1_on: sdc1-on-state {
+ clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
- pinconf-cmd {
+ cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
- pinconf-data {
+ data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
- pinconf-rclk {
+ rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
- sdc1_off: sdc1-off {
- pinconf-clk {
+ sdc1_off: sdc1-off-state {
+ clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
- pinconf-cmd {
+ cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
- pinconf-data {
+ data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
- pinconf-rclk {
+ rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
- sdc2_on: sdc2-on {
- pinconf-clk {
+ sdc2_on: sdc2-on-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
- pinconf-cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
- pinconf-data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
- pinconf-sd-cd {
+ sd-cd-pins {
pins = "gpio69";
+ function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
};
- sdc2_off: sdc2-off {
- pinconf-clk {
+ sdc2_off: sdc2-off-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
- pinconf-cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
- pinconf-data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
};
- pinconf-sd-cd {
+ sd-cd-pins {
pins = "gpio69";
+ function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
index 7ee407f7b6bb..8b8ea8af165d 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
@@ -181,23 +181,15 @@ ap_ts_pen_1v8: &i2c4 {
/* PINCTRL - modifications to sc7180-trogdor.dtsi */
&en_pp3300_dx_edp {
- pinmux {
- pins = "gpio67";
- };
-
- pinconf {
- pins = "gpio67";
- };
+ pins = "gpio67";
};
&ts_reset_l {
- pinconf {
- /*
- * We want reset state by default and it will be up to the
- * driver to disable this when it's ready.
- */
- output-low;
- };
+ /*
+ * We want reset state by default and it will be up to the
+ * driver to disable this when it's ready.
+ */
+ output-low;
};
/* PINCTRL - board-specific pinctrl */
@@ -327,16 +319,10 @@ ap_ts_pen_1v8: &i2c4 {
"DP_HOT_PLUG_DET",
"EC_IN_RW_ODL";
- dmic_clk_en: dmic_clk_en {
- pinmux {
- pins = "gpio83";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio83";
- drive-strength = <8>;
- bias-pull-up;
- };
+ dmic_clk_en: dmic-clk-en-state {
+ pins = "gpio83";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
index 1bd6c7dcd9e9..d3cf64c16dcd 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
@@ -10,22 +10,22 @@
/ {
/* BOARD-SPECIFIC TOP LEVEL NODES */
- max98360a_1: max98360a_1 {
+ max98360a_1: amplifier-1 {
compatible = "maxim,max98360a";
#sound-dai-cells = <0>;
};
- max98360a_2: max98360a_2 {
+ max98360a_2: amplifier-2 {
compatible = "maxim,max98360a";
#sound-dai-cells = <0>;
};
- max98360a_3: max98360a_3 {
+ max98360a_3: amplifier-3 {
compatible = "maxim,max98360a";
#sound-dai-cells = <0>;
};
- pp3300_touch: pp3300-touch {
+ pp3300_touch: pp3300-touch-regulator {
compatible = "regulator-fixed";
regulator-name = "pp3300_touch";
@@ -180,30 +180,19 @@ ap_ts_pen_1v8: &i2c4 {
/* PINCTRL - modifications to sc7180-trogdor.dtsi */
&en_pp3300_dx_edp {
- pinmux {
- pins = "gpio67";
- };
-
- pinconf {
- pins = "gpio67";
- };
+ pins = "gpio67";
};
-&sec_mi2s_active{
- pinmux {
- pins = "gpio49", "gpio50", "gpio51", "gpio52";
- function = "mi2s_1";
- };
+&sec_mi2s_active {
+ pins = "gpio49", "gpio50", "gpio51", "gpio52";
};
&ts_reset_l {
- pinconf {
- /*
- * We want reset state by default and it will be up to the
- * driver to disable this when it's ready.
- */
- output-low;
- };
+ /*
+ * We want reset state by default and it will be up to the
+ * driver to disable this when it's ready.
+ */
+ output-low;
};
/* PINCTRL - board-specific pinctrl */
@@ -333,16 +322,10 @@ ap_ts_pen_1v8: &i2c4 {
"DP_HOT_PLUG_DET",
"EC_IN_RW_ODL";
- en_pp3300_touch: en-pp3300-touch {
- pinmux {
- pins = "gpio87";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio87";
- drive-strength = <2>;
- bias-disable;
- };
+ en_pp3300_touch: en-pp3300-touch-state {
+ pins = "gpio87";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts
index 1a62e8d435ab..3abd6222fe46 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts
@@ -29,16 +29,10 @@
};
&tlmm {
- en_fp_rails: en-fp-rails {
- pinmux {
- pins = "gpio74";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio74";
- drive-strength = <2>;
- bias-disable;
- };
+ en_fp_rails: en-fp-rails-state {
+ pins = "gpio74";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi
index 74f0e07ea5cf..315ac5eb5f78 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi
@@ -11,6 +11,7 @@
&alc5682 {
compatible = "realtek,rt5682s";
+ /delete-property/ VBAT-supply;
realtek,dmic1-clk-pin = <2>;
realtek,dmic-clk-rate-hz = <2048000>;
};
@@ -87,13 +88,7 @@ ap_ts_pen_1v8: &i2c4 {
/* PINCTRL - modifications to sc7180-trogdor.dtsi */
&en_pp3300_dx_edp {
- pinmux {
- pins = "gpio67";
- };
-
- pinconf {
- pins = "gpio67";
- };
+ pins = "gpio67";
};
/* PINCTRL - board-specific pinctrl */
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
index 002663d752da..269007d73162 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
@@ -75,21 +75,13 @@ ap_ts_pen_1v8: &i2c4 {
/* PINCTRL - modifications to sc7180-trogdor.dtsi */
&trackpad_int_1v8_odl {
- pinmux {
- pins = "gpio58";
- };
-
- pinconf {
- pins = "gpio58";
- };
+ pins = "gpio58";
};
&ts_reset_l {
- pinconf {
- /* This pin is not connected on -rev0, pull up to park. */
- /delete-property/bias-disable;
- bias-pull-up;
- };
+ /* This pin is not connected on -rev0, pull up to park. */
+ /delete-property/bias-disable;
+ bias-pull-up;
};
/* PINCTRL - board-specific pinctrl */
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi
index 7bc8402c018e..f4c1f3813664 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi
@@ -24,30 +24,13 @@
/* PINCTRL - modifications to sc7180-trogdor-mrbland.dtsi */
&avdd_lcd_en {
- pinmux {
- pins = "gpio80";
- };
-
- pinconf {
- pins = "gpio80";
- };
+ pins = "gpio80";
};
&mipi_1800_en {
- pinmux {
- pins = "gpio81";
- };
-
- pinconf {
- pins = "gpio81";
- };
+ pins = "gpio81";
};
-&vdd_reset_1800 {
- pinmux {
- pins = "gpio76";
- };
- pinconf {
- pins = "gpio76";
- };
+&vdd_reset_1800 {
+ pins = "gpio76";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi
index 97cba7f8064f..ed12ee35f06b 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi
@@ -13,7 +13,7 @@
/delete-node/ &usb_c1;
/ {
- avdd_lcd: avdd-lcd {
+ avdd_lcd: avdd-lcd-regulator {
compatible = "regulator-fixed";
regulator-name = "avdd_lcd";
@@ -25,7 +25,7 @@
vin-supply = <&pp5000_a>;
};
- avee_lcd: avee-lcd {
+ avee_lcd: avee-lcd-regulator {
compatible = "regulator-fixed";
regulator-name = "avee_lcd";
@@ -37,7 +37,7 @@
vin-supply = <&pp5000_a>;
};
- v1p8_mipi: v1p8-mipi {
+ v1p8_mipi: v1p8-mipi-regulator {
compatible = "regulator-fixed";
regulator-name = "v1p8_mipi";
@@ -160,13 +160,7 @@ pp3300_disp_on: &pp3300_dx_edp {
*/
tp_en: &en_pp3300_dx_edp {
- pinmux {
- pins = "gpio85";
- };
-
- pinconf {
- pins = "gpio85";
- };
+ pins = "gpio85";
};
/* PINCTRL - board-specific pinctrl */
@@ -296,55 +290,31 @@ tp_en: &en_pp3300_dx_edp {
"DP_HOT_PLUG_DET",
"EC_IN_RW_ODL";
- avdd_lcd_en: avdd-lcd-en {
- pinmux {
- pins = "gpio88";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio88";
- drive-strength = <2>;
- bias-disable;
- };
+ avdd_lcd_en: avdd-lcd-en-state {
+ pins = "gpio88";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- avee_lcd_en: avee-lcd-en {
- pinmux {
- pins = "gpio21";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio21";
- drive-strength = <2>;
- bias-disable;
- };
+ avee_lcd_en: avee-lcd-en-state {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- mipi_1800_en: mipi-1800-en {
- pinmux {
- pins = "gpio86";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio86";
- drive-strength = <2>;
- bias-disable;
- };
+ mipi_1800_en: mipi-1800-en-state {
+ pins = "gpio86";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- vdd_reset_1800: vdd-reset-1800 {
- pinmux {
- pins = "gpio87";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio87";
- drive-strength = <2>;
- bias-disable;
- };
+ vdd_reset_1800: vdd-reset-1800-state {
+ pins = "gpio87";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi
index 6a84fba178d6..ebd6765e2afa 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi
@@ -8,7 +8,7 @@
#include <dt-bindings/gpio/gpio.h>
/ {
- pp3300_brij_ps8640: pp3300-brij-ps8640 {
+ pp3300_brij_ps8640: pp3300-brij-ps8640-regulator {
compatible = "regulator-fixed";
status = "okay";
regulator-name = "pp3300_brij_ps8640";
@@ -83,29 +83,17 @@ edp_brij_i2c: &i2c2 {
};
&tlmm {
- edp_brij_ps8640_rst: edp-brij-ps8640-rst {
- pinmux {
- pins = "gpio11";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio11";
- drive-strength = <2>;
- bias-disable;
- };
+ edp_brij_ps8640_rst: edp-brij-ps8640-rst-state {
+ pins = "gpio11";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- en_pp3300_edp_brij_ps8640: en-pp3300-edp-brij-ps8640 {
- pinmux {
- pins = "gpio32";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio32";
- drive-strength = <2>;
- bias-disable;
- };
+ en_pp3300_edp_brij_ps8640: en-pp3300-edp-brij-ps8640-state {
+ pins = "gpio32";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi
index 56d787785fd5..d06cc4ea3375 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi
@@ -84,13 +84,7 @@
};
&en_pp3300_dx_edp {
- pinmux {
- pins = "gpio67";
- };
-
- pinconf {
- pins = "gpio67";
- };
+ pins = "gpio67";
};
/* PINCTRL - board-specific pinctrl */
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360-lte.dts
new file mode 100644
index 000000000000..021bcafcf815
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360-lte.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Pazquel board device tree source
+ *
+ * Copyright 2021 Google LLC.
+ */
+
+/dts-v1/;
+
+#include "sc7180-trogdor.dtsi"
+#include "sc7180-trogdor-parade-ps8640.dtsi"
+#include "sc7180-trogdor-pazquel360.dtsi"
+#include "sc7180-trogdor-lte-sku.dtsi"
+
+/ {
+ model = "Google Pazquel (Parade,LTE)";
+ compatible = "google,pazquel-sku22", "google,pazquel-sku20", "qcom,sc7180";
+};
+
+&ap_sar_sensor_i2c {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360-wifi.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360-wifi.dts
new file mode 100644
index 000000000000..defd84c5354a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360-wifi.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Pazquel board device tree source
+ *
+ * Copyright 2022 Google LLC.
+ */
+
+/dts-v1/;
+
+#include "sc7180-trogdor.dtsi"
+#include "sc7180-trogdor-parade-ps8640.dtsi"
+#include "sc7180-trogdor-pazquel360.dtsi"
+
+/ {
+ model = "Google Pazquel (Parade,WIFI-only)";
+ compatible = "google,pazquel-sku21", "qcom,sc7180";
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi
new file mode 100644
index 000000000000..5702325d0c7b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Pazquel board device tree source
+ *
+ * Copyright 2021 Google LLC.
+ */
+
+/* This file must be included after sc7180-trogdor.dtsi */
+#include "sc7180-trogdor-pazquel.dtsi"
+
+&alc5682 {
+ compatible = "realtek,rt5682s";
+ realtek,dmic1-clk-pin = <2>;
+ realtek,dmic-clk-rate-hz = <2048000>;
+};
+
+&keyboard_controller {
+ function-row-physmap = <
+ MATRIX_KEY(0x00, 0x02, 0) /* T1 */
+ MATRIX_KEY(0x03, 0x02, 0) /* T2 */
+ MATRIX_KEY(0x02, 0x02, 0) /* T3 */
+ MATRIX_KEY(0x01, 0x02, 0) /* T4 */
+ MATRIX_KEY(0x03, 0x04, 0) /* T5 */
+ MATRIX_KEY(0x02, 0x04, 0) /* T6 */
+ MATRIX_KEY(0x01, 0x04, 0) /* T7 */
+ MATRIX_KEY(0x02, 0x09, 0) /* T8 */
+ MATRIX_KEY(0x01, 0x09, 0) /* T9 */
+ MATRIX_KEY(0x00, 0x04, 0) /* T10 */
+ MATRIX_KEY(0x03, 0x09, 0) /* T11 */
+ >;
+ linux,keymap = <
+ MATRIX_KEY(0x00, 0x02, KEY_BACK)
+ MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
+ MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
+ MATRIX_KEY(0x01, 0x02, KEY_SCALE)
+ MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
+ MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
+ MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
+ MATRIX_KEY(0x02, 0x09, KEY_MUTE)
+ MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
+ MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
+ MATRIX_KEY(0x03, 0x09, KEY_SLEEP)
+ CROS_STD_MAIN_KEYMAP
+ >;
+};
+
+&sound {
+ compatible = "google,sc7180-trogdor";
+ model = "sc7180-rt5682s-max98357a-1mic";
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi
index a7582fb547ee..6c5287bd27d6 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi
@@ -312,15 +312,9 @@ ap_ts_pen_1v8: &i2c4 {
"DP_HOT_PLUG_DET",
"EC_IN_RW_ODL";
- dmic_sel: dmic-sel {
- pinmux {
- pins = "gpio86";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio86";
- bias-pull-down;
- };
+ dmic_sel: dmic-sel-state {
+ pins = "gpio86";
+ function = "gpio";
+ bias-pull-down;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi
index 695b04fe7221..cb41ccdaccfd 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi
@@ -13,7 +13,7 @@
/delete-node/ &usb_c1;
/ {
- ppvar_lcd: ppvar-lcd {
+ ppvar_lcd: ppvar-lcd-regulator {
compatible = "regulator-fixed";
regulator-name = "ppvar_lcd";
@@ -25,7 +25,7 @@
vin-supply = <&pp5000_a>;
};
- v1p8_disp: v1p8-disp {
+ v1p8_disp: v1p8-disp-regulator {
compatible = "regulator-fixed";
regulator-name = "v1p8_disp";
@@ -147,13 +147,7 @@ pp3300_disp_on: &pp3300_dx_edp {
*/
tp_en: &en_pp3300_dx_edp {
- pinmux {
- pins = "gpio67";
- };
-
- pinconf {
- pins = "gpio67";
- };
+ pins = "gpio67";
};
/* PINCTRL - board-specific pinctrl */
@@ -283,42 +277,24 @@ tp_en: &en_pp3300_dx_edp {
"DP_HOT_PLUG_DET",
"EC_IN_RW_ODL";
- lcd_rst: lcd-rst {
- pinmux {
- pins = "gpio87";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio87";
- drive-strength = <2>;
- bias-disable;
- };
+ lcd_rst: lcd-rst-state {
+ pins = "gpio87";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- ppvar_lcd_en: ppvar-lcd-en {
- pinmux {
- pins = "gpio88";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio88";
- drive-strength = <2>;
- bias-disable;
- };
+ ppvar_lcd_en: ppvar-lcd-en-state {
+ pins = "gpio88";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- pp1800_disp_on: pp1800-disp-on {
- pinmux {
- pins = "gpio86";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio86";
- drive-strength = <2>;
- bias-disable;
- };
+ pp1800_disp_on: pp1800-disp-on-state {
+ pins = "gpio86";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts
index bc097d1b1b23..671b3691f1bb 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts
@@ -63,13 +63,7 @@ ap_ts_pen_1v8: &i2c4 {
/* PINCTRL - modifications to sc7180-trogdor.dtsi */
&trackpad_int_1v8_odl {
- pinmux {
- pins = "gpio58";
- };
-
- pinconf {
- pins = "gpio58";
- };
+ pins = "gpio58";
};
/* PINCTRL - board-specific pinctrl */
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi
index f869e6a343c1..65333709e529 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi
@@ -76,16 +76,10 @@ edp_brij_i2c: &i2c2 {
};
&tlmm {
- edp_brij_irq: edp-brij-irq {
- pinmux {
- pins = "gpio11";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio11";
- drive-strength = <2>;
- bias-pull-down;
- };
+ edp_brij_irq: edp-brij-irq-state {
+ pins = "gpio11";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi
index db29e0cba29d..7f272c6e95f6 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi
@@ -24,30 +24,13 @@
/* PINCTRL - modifications to sc7180-trogdor-wormdingler.dtsi */
&avdd_lcd_en {
- pinmux {
- pins = "gpio80";
- };
-
- pinconf {
- pins = "gpio80";
- };
+ pins = "gpio80";
};
&mipi_1800_en {
- pinmux {
- pins = "gpio81";
- };
-
- pinconf {
- pins = "gpio81";
- };
+ pins = "gpio81";
};
-&vdd_reset_1800 {
- pinmux {
- pins = "gpio76";
- };
- pinconf {
- pins = "gpio76";
- };
+&vdd_reset_1800 {
+ pins = "gpio76";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dts
index aa605885c371..6225ab8329c3 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dts
@@ -19,6 +19,7 @@
&alc5682 {
compatible = "realtek,rt5682s";
+ /delete-property/ VBAT-supply;
realtek,dmic1-clk-pin = <2>;
realtek,dmic-clk-rate-hz = <2048000>;
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dts
index 7116c44c8d85..b40b068dad6a 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dts
@@ -19,6 +19,7 @@
&alc5682 {
compatible = "realtek,rt5682s";
+ /delete-property/ VBAT-supply;
realtek,dmic1-clk-pin = <2>;
realtek,dmic-clk-rate-hz = <2048000>;
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi
index 6312108e8b3e..9832e752da35 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi
@@ -10,7 +10,7 @@
#include "sc7180-trogdor.dtsi"
/ {
- avdd_lcd: avdd-lcd {
+ avdd_lcd: avdd-lcd-regulator {
compatible = "regulator-fixed";
regulator-name = "avdd_lcd";
@@ -22,7 +22,7 @@
vin-supply = <&pp5000_a>;
};
- avee_lcd: avee-lcd {
+ avee_lcd: avee-lcd-regulator {
compatible = "regulator-fixed";
regulator-name = "avee_lcd";
@@ -35,7 +35,7 @@
};
pp1800_ts:
- v1p8_mipi: v1p8-mipi {
+ v1p8_mipi: v1p8-mipi-regulator {
compatible = "regulator-fixed";
regulator-name = "v1p8_mipi";
@@ -222,13 +222,7 @@ pp3300_disp_on: &pp3300_dx_edp {
*/
tp_en: &en_pp3300_dx_edp {
- pinmux {
- pins = "gpio85";
- };
-
- pinconf {
- pins = "gpio85";
- };
+ pins = "gpio85";
};
/* PINCTRL - board-specific pinctrl */
@@ -358,55 +352,31 @@ tp_en: &en_pp3300_dx_edp {
"DP_HOT_PLUG_DET",
"EC_IN_RW_ODL";
- avdd_lcd_en: avdd-lcd-en {
- pinmux {
- pins = "gpio88";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio88";
- drive-strength = <2>;
- bias-disable;
- };
+ avdd_lcd_en: avdd-lcd-en-state {
+ pins = "gpio88";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- avee_lcd_en: avee-lcd-en {
- pinmux {
- pins = "gpio21";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio21";
- drive-strength = <2>;
- bias-disable;
- };
+ avee_lcd_en: avee-lcd-en-state {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- mipi_1800_en: mipi-1800-en {
- pinmux {
- pins = "gpio86";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio86";
- drive-strength = <2>;
- bias-disable;
- };
+ mipi_1800_en: mipi-1800-en-state {
+ pins = "gpio86";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- vdd_reset_1800: vdd-reset-1800 {
- pinmux {
- pins = "gpio87";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio87";
- drive-strength = <2>;
- bias-disable;
- };
+ vdd_reset_1800: vdd-reset-1800-state {
+ pins = "gpio87";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
index eae22e6e97c1..f1defb94d670 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
@@ -354,7 +354,7 @@
pwmleds {
compatible = "pwm-leds";
- keyboard_backlight: keyboard-backlight {
+ keyboard_backlight: led-0 {
status = "disabled";
label = "cros_ec::kbd_backlight";
function = LED_FUNCTION_KBD_BACKLIGHT;
@@ -768,6 +768,8 @@ hp_i2c: &i2c9 {
interrupts = <28 IRQ_TYPE_EDGE_BOTH>;
AVDD-supply = <&pp1800_alc5682>;
+ DBVDD-supply = <&pp1800_alc5682>;
+ LDO1-IN-supply = <&pp1800_alc5682>;
MICVDD-supply = <&pp3300_codec>;
VBAT-supply = <&pp3300_audio>;
@@ -880,27 +882,30 @@ hp_i2c: &i2c9 {
};
&spi0 {
- pinctrl-0 = <&qup_spi0_cs_gpio_init_high>, <&qup_spi0_cs_gpio>;
+ pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs_gpio>;
cs-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
};
&spi6 {
- pinctrl-0 = <&qup_spi6_cs_gpio_init_high>, <&qup_spi6_cs_gpio>;
+ pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs_gpio>;
cs-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
};
ap_spi_fp: &spi10 {
- pinctrl-0 = <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>;
+ pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs_gpio>;
cs-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
cros_ec_fp: ec@0 {
- compatible = "google,cros-ec-spi";
+ compatible = "google,cros-ec-fp", "google,cros-ec-spi";
reg = <0>;
interrupt-parent = <&tlmm>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
- pinctrl-0 = <&fp_to_ap_irq_l>;
+ pinctrl-0 = <&fp_to_ap_irq_l>, <&fp_rst_l>, <&fpmcu_boot0>;
+ boot0-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
spi-max-frequency = <3000000>;
+ vdd-supply = <&pp3300_fp_tp>;
};
};
@@ -997,175 +1002,141 @@ ap_spi_fp: &spi10 {
/* PINCTRL - additions to nodes defined in sc7180.dtsi */
&dp_hot_plug_det {
- pinconf {
- pins = "gpio117";
- bias-disable;
- };
+ bias-disable;
};
&pri_mi2s_active {
- pinconf {
- pins = "gpio53", "gpio54", "gpio55", "gpio56";
- drive-strength = <2>;
- bias-pull-down;
- };
+ drive-strength = <2>;
+ bias-pull-down;
};
&pri_mi2s_mclk_active {
- pinconf {
- pins = "gpio57";
- drive-strength = <2>;
- bias-pull-down;
- };
+ drive-strength = <2>;
+ bias-pull-down;
};
&qspi_cs0 {
- pinconf {
- pins = "gpio68";
- bias-disable;
- };
+ bias-disable;
};
&qspi_clk {
- pinconf {
- pins = "gpio63";
- drive-strength = <8>;
- bias-disable;
- };
+ drive-strength = <8>;
+ bias-disable;
};
&qspi_data01 {
- pinconf {
- pins = "gpio64", "gpio65";
-
- /* High-Z when no transfers; nice to park the lines */
- bias-pull-up;
- };
+ /* High-Z when no transfers; nice to park the lines */
+ bias-pull-up;
};
&qup_i2c2_default {
- pinconf {
- pins = "gpio15", "gpio16";
- drive-strength = <2>;
+ drive-strength = <2>;
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
&qup_i2c4_default {
- pinconf {
- pins = "gpio115", "gpio116";
- drive-strength = <2>;
+ drive-strength = <2>;
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
&qup_i2c5_default {
- pinconf {
- pins = "gpio25", "gpio26";
- drive-strength = <2>;
+ drive-strength = <2>;
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
&qup_i2c7_default {
- pinconf {
- pins = "gpio6", "gpio7";
- drive-strength = <2>;
+ drive-strength = <2>;
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
&qup_i2c9_default {
- pinconf {
- pins = "gpio46", "gpio47";
- drive-strength = <2>;
+ drive-strength = <2>;
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
+};
+
+&qup_spi0_spi {
+ drive-strength = <2>;
+ bias-disable;
};
&qup_spi0_cs_gpio {
- pinconf {
- pins = "gpio34", "gpio35", "gpio36", "gpio37";
- drive-strength = <2>;
- bias-disable;
- };
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_spi6_spi {
+ drive-strength = <2>;
+ bias-disable;
};
&qup_spi6_cs_gpio {
- pinconf {
- pins = "gpio59", "gpio60", "gpio61", "gpio62";
- drive-strength = <2>;
- bias-disable;
- };
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_spi10_spi {
+ drive-strength = <2>;
+ bias-disable;
};
&qup_spi10_cs_gpio {
- pinconf {
- pins = "gpio86", "gpio87", "gpio88", "gpio89";
- drive-strength = <2>;
- bias-disable;
- };
+ drive-strength = <2>;
+ bias-disable;
};
-&qup_uart3_default {
- pinconf-cts {
- /*
- * Configure a pull-down on CTS to match the pull of
- * the Bluetooth module.
- */
- pins = "gpio38";
- bias-pull-down;
- };
+&qup_uart3_cts {
+ /*
+ * Configure a pull-down on CTS to match the pull of
+ * the Bluetooth module.
+ */
+ bias-pull-down;
+};
- pinconf-rts-tx {
- /* We'll drive RTS and TX, so no pull */
- pins = "gpio39", "gpio40";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_uart3_rts {
+ /* We'll drive RTS, so no pull */
+ drive-strength = <2>;
+ bias-disable;
+};
- pinconf-rx {
- /*
- * Configure a pull-up on RX. This is needed to avoid
- * garbage data when the TX pin of the Bluetooth module is
- * in tri-state (module powered off or not driving the
- * signal yet).
- */
- pins = "gpio41";
- bias-pull-up;
- };
+&qup_uart3_tx {
+ /* We'll drive TX, so no pull */
+ drive-strength = <2>;
+ bias-disable;
};
-&qup_uart8_default {
- pinconf-tx {
- pins = "gpio44";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_uart3_rx {
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module is
+ * in tri-state (module powered off or not driving the
+ * signal yet).
+ */
+ bias-pull-up;
+};
- pinconf-rx {
- pins = "gpio45";
- drive-strength = <2>;
- bias-pull-up;
- };
+&qup_uart8_tx {
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_uart8_rx {
+ drive-strength = <2>;
+ bias-pull-up;
};
&sec_mi2s_active {
- pinconf {
- pins = "gpio49", "gpio50", "gpio51";
- drive-strength = <2>;
- bias-pull-down;
- };
+ drive-strength = <2>;
+ bias-pull-down;
};
/* PINCTRL - board-specific pinctrl */
@@ -1196,468 +1167,337 @@ ap_spi_fp: &spi10 {
pinctrl-names = "default";
pinctrl-0 = <&bios_flash_wp_l>, <&ap_suspend_l_neuter>;
- amp_en: amp-en {
- pinmux {
- pins = "gpio23";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio23";
- bias-pull-down;
- };
+ amp_en: amp-en-state {
+ pins = "gpio23";
+ function = "gpio";
+ bias-pull-down;
};
- ap_ec_int_l: ap-ec-int-l {
- pinmux {
- pins = "gpio94";
- function = "gpio";
- input-enable;
- };
-
- pinconf {
- pins = "gpio94";
- bias-pull-up;
- };
+ ap_ec_int_l: ap-ec-int-l-state {
+ pins = "gpio94";
+ function = "gpio";
+ input-enable;
+ bias-pull-up;
};
- ap_edp_bklten: ap-edp-bklten {
- pinmux {
- pins = "gpio12";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
+ ap_edp_bklten: ap-edp-bklten-state {
+ pins = "gpio12";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
- /* Force backlight to be disabled to match state at boot. */
- output-low;
- };
+ /* Force backlight to be disabled to match state at boot. */
+ output-low;
};
- ap_suspend_l_neuter: ap-suspend-l-neuter {
- pinmux {
- pins = "gpio27";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio27";
- bias-disable;
- };
+ ap_suspend_l_neuter: ap-suspend-l-neuter-state {
+ pins = "gpio27";
+ function = "gpio";
+ bias-disable;
};
- bios_flash_wp_l: bios-flash-wp-l {
- pinmux {
- pins = "gpio66";
- function = "gpio";
- input-enable;
- };
-
- pinconf {
- pins = "gpio66";
- bias-disable;
- };
+ bios_flash_wp_l: bios-flash-wp-l-state {
+ pins = "gpio66";
+ function = "gpio";
+ input-enable;
+ bias-disable;
};
- edp_brij_en: edp-brij-en {
- pinmux {
- pins = "gpio104";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio104";
- drive-strength = <2>;
- bias-disable;
- };
+ edp_brij_en: edp-brij-en-state {
+ pins = "gpio104";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- en_pp3300_codec: en-pp3300-codec {
- pinmux {
- pins = "gpio83";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio83";
- drive-strength = <2>;
- bias-disable;
- };
+ en_pp3300_codec: en-pp3300-codec-state {
+ pins = "gpio83";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- en_pp3300_dx_edp: en-pp3300-dx-edp {
- pinmux {
- pins = "gpio30";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio30";
- drive-strength = <2>;
- bias-disable;
- };
+ en_pp3300_dx_edp: en-pp3300-dx-edp-state {
+ pins = "gpio30";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- en_pp3300_hub: en-pp3300-hub {
- pinmux {
- pins = "gpio84";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio84";
- drive-strength = <2>;
- bias-disable;
- };
+ en_pp3300_hub: en-pp3300-hub-state {
+ pins = "gpio84";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- fp_to_ap_irq_l: fp-to-ap-irq-l {
- pinmux {
- pins = "gpio4";
- function = "gpio";
- input-enable;
- };
-
- pinconf {
- pins = "gpio4";
-
- /* Has external pullup */
- bias-disable;
- };
+ fp_rst_l: fp-rst-l-state {
+ pins = "gpio22";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <2>;
};
- h1_ap_int_odl: h1-ap-int-odl {
- pinmux {
- pins = "gpio42";
- function = "gpio";
- input-enable;
- };
+ fp_to_ap_irq_l: fp-to-ap-irq-l-state {
+ pins = "gpio4";
+ function = "gpio";
+ input-enable;
- pinconf {
- pins = "gpio42";
- bias-pull-up;
- };
+ /* Has external pullup */
+ bias-disable;
};
- hp_irq: hp-irq {
- pinmux {
- pins = "gpio28";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio28";
- bias-pull-up;
- };
+ fpmcu_boot0: fpmcu-boot0-state {
+ pins = "gpio10";
+ function = "gpio";
+ bias-disable;
};
- pen_irq_l: pen-irq-l {
- pinmux {
- pins = "gpio21";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio21";
-
- /* Has external pullup */
- bias-disable;
- };
+ h1_ap_int_odl: h1-ap-int-odl-state {
+ pins = "gpio42";
+ function = "gpio";
+ input-enable;
+ bias-pull-up;
};
- pen_pdct_l: pen-pdct-l {
- pinmux {
- pins = "gpio52";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio52";
-
- /* Has external pullup */
- bias-disable;
- };
+ hp_irq: hp-irq-state {
+ pins = "gpio28";
+ function = "gpio";
+ bias-pull-up;
};
- pen_rst_odl: pen-rst-odl {
- pinmux {
- pins = "gpio18";
- function = "gpio";
- };
+ pen_irq_l: pen-irq-l-state {
+ pins = "gpio21";
+ function = "gpio";
- pinconf {
- pins = "gpio18";
- bias-disable;
- drive-strength = <2>;
-
- /*
- * The pen driver doesn't currently support
- * driving this reset line. By specifying
- * output-high here we're relying on the fact
- * that this pin has a default pulldown at boot
- * (which makes sure the pen was in reset if it
- * was powered) and then we set it high here to
- * take it out of reset. Better would be if the
- * pen driver could control this and we could
- * remove "output-high" here.
- */
- output-high; /* TODO: Remove this? */
- };
+ /* Has external pullup */
+ bias-disable;
};
- p_sensor_int_l: p-sensor-int-l {
- pinmux {
- pins = "gpio24";
- function = "gpio";
- input-enable;
- };
+ pen_pdct_l: pen-pdct-l-state-state {
+ pins = "gpio52";
+ function = "gpio";
- pinconf {
- pins = "gpio24";
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
- qup_spi0_cs_gpio_init_high: qup-spi0-cs-gpio-init-high {
- pinconf {
- pins = "gpio37";
- output-high;
- };
- };
+ pen_rst_odl: pen-rst-odl-state {
+ pins = "gpio18";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <2>;
- qup_spi6_cs_gpio_init_high: qup-spi6-cs-gpio-init-high {
- pinconf {
- pins = "gpio62";
- output-high;
- };
+ /*
+ * The pen driver doesn't currently support
+ * driving this reset line. By specifying
+ * output-high here we're relying on the fact
+ * that this pin has a default pulldown at boot
+ * (which makes sure the pen was in reset if it
+ * was powered) and then we set it high here to
+ * take it out of reset. Better would be if the
+ * pen driver could control this and we could
+ * remove "output-high" here.
+ */
+ output-high; /* TODO: Remove this? */
};
- qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high {
- pinconf {
- pins = "gpio89";
- output-high;
- };
- };
+ p_sensor_int_l: p-sensor-int-l-state {
+ pins = "gpio24";
+ function = "gpio";
+ input-enable;
- qup_uart3_sleep: qup-uart3-sleep {
- pinmux {
- pins = "gpio38", "gpio39",
- "gpio40", "gpio41";
- function = "gpio";
- };
+ /* Has external pullup */
+ bias-disable;
+ };
- pinconf-cts {
+ qup_uart3_sleep: qup-uart3-sleep-state {
+ cts-pins {
/*
* Configure a pull-down on CTS to match the pull of
* the Bluetooth module.
*/
pins = "gpio38";
+ function = "gpio";
bias-pull-down;
};
- pinconf-rts {
+ rts-pins {
/*
* Configure pull-down on RTS. As RTS is active low
* signal, pull it low to indicate the BT SoC that it
* can wakeup the system anytime from suspend state by
* pulling RX low (by sending wakeup bytes).
*/
- pins = "gpio39";
- bias-pull-down;
+ pins = "gpio39";
+ function = "gpio";
+ bias-pull-down;
};
- pinconf-tx {
+ tx-pins {
/*
* Configure pull-up on TX when it isn't actively driven
* to prevent BT SoC from receiving garbage during sleep.
*/
pins = "gpio40";
+ function = "gpio";
bias-pull-up;
};
- pinconf-rx {
+ rx-pins {
/*
* Configure a pull-up on RX. This is needed to avoid
* garbage data when the TX pin of the Bluetooth module
* is floating which may cause spurious wakeups.
*/
pins = "gpio41";
+ function = "gpio";
bias-pull-up;
};
};
/* Named trackpad_int_1v8_odl on earlier revision schematics */
trackpad_int_1v8_odl:
- tp_int_odl: tp-int-odl {
- pinmux {
- pins = "gpio0";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio0";
+ tp_int_odl: tp-int-odl-state {
+ pins = "gpio0";
+ function = "gpio";
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
- ts_int_l: ts-int-l {
- pinmux {
- pins = "gpio9";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio9";
- bias-pull-up;
- };
+ ts_int_l: ts-int-l-state {
+ pins = "gpio9";
+ function = "gpio";
+ bias-pull-up;
};
- ts_reset_l: ts-reset-l {
- pinmux {
- pins = "gpio8";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio8";
- bias-disable;
- drive-strength = <2>;
- };
+ ts_reset_l: ts-reset-l-state {
+ pins = "gpio8";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <2>;
};
- sdc1_on: sdc1-on {
- pinconf-clk {
+ sdc1_on: sdc1-on-state {
+ clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
- pinconf-cmd {
+ cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <16>;
};
- pinconf-data {
+ data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <16>;
};
- pinconf-rclk {
+ rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
- sdc1_off: sdc1-off {
- pinconf-clk {
+ sdc1_off: sdc1-off-state {
+ clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
- pinconf-cmd {
+ cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
- pinconf-data {
+ data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
- pinconf-rclk {
+ rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
- sdc2_on: sdc2-on {
- pinconf-clk {
+ sdc2_on: sdc2-on-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
- pinconf-cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
- pinconf-data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
- pinconf-sd-cd {
+ sd-cd-pins {
pins = "gpio69";
+ function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
};
- sdc2_off: sdc2-off {
- pinconf-clk {
+ sdc2_off: sdc2-off-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
- pinconf-cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
- pinconf-data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
};
- pinconf-sd-cd {
+ sd-cd-pins {
pins = "gpio69";
+ function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
};
- uf_cam_en: uf-cam-en {
- pinmux {
- pins = "gpio6";
- function = "gpio";
- };
+ uf_cam_en: uf-cam-en-state {
+ pins = "gpio6";
+ function = "gpio";
+ drive-strength = <2>;
- pinconf {
- pins = "gpio6";
- drive-strength = <2>;
- /* External pull down */
- bias-disable;
- };
+ /* External pull down */
+ bias-disable;
};
- wf_cam_en: wf-cam-en {
- pinmux {
- pins = "gpio7";
- function = "gpio";
- };
+ wf_cam_en: wf-cam-en-state {
+ pins = "gpio7";
+ function = "gpio";
+ drive-strength = <2>;
- pinconf {
- pins = "gpio7";
- drive-strength = <2>;
- /* External pull down */
- bias-disable;
- };
+ /* External pull down */
+ bias-disable;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 58976a1ba06b..f71cf21a8dd8 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -662,6 +662,7 @@
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
+ power-domains = <&rpmhpd SC7180_CX>;
};
qfprom: efuse@784000 {
@@ -795,7 +796,7 @@
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi0_default>;
+ pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -849,7 +850,7 @@
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi1_default>;
+ pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -939,7 +940,7 @@
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi3_default>;
+ pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1029,7 +1030,7 @@
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi5_default>;
+ pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1096,7 +1097,7 @@
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi6_default>;
+ pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1186,7 +1187,7 @@
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi8_default>;
+ pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1276,7 +1277,7 @@
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi10_default>;
+ pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1330,7 +1331,7 @@
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi11_default>;
+ pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1486,410 +1487,443 @@
gpio-ranges = <&tlmm 0 0 120>;
wakeup-parent = <&pdc>;
- dp_hot_plug_det: dp-hot-plug-det {
- pinmux {
- pins = "gpio117";
- function = "dp_hot";
- };
+ dp_hot_plug_det: dp-hot-plug-det-state {
+ pins = "gpio117";
+ function = "dp_hot";
};
- qspi_clk: qspi-clk {
- pinmux {
- pins = "gpio63";
- function = "qspi_clk";
- };
+ qspi_clk: qspi-clk-state {
+ pins = "gpio63";
+ function = "qspi_clk";
};
- qspi_cs0: qspi-cs0 {
- pinmux {
- pins = "gpio68";
- function = "qspi_cs";
- };
+ qspi_cs0: qspi-cs0-state {
+ pins = "gpio68";
+ function = "qspi_cs";
};
- qspi_cs1: qspi-cs1 {
- pinmux {
- pins = "gpio72";
- function = "qspi_cs";
- };
+ qspi_cs1: qspi-cs1-state {
+ pins = "gpio72";
+ function = "qspi_cs";
};
- qspi_data01: qspi-data01 {
- pinmux-data {
- pins = "gpio64", "gpio65";
- function = "qspi_data";
- };
+ qspi_data01: qspi-data01-state {
+ pins = "gpio64", "gpio65";
+ function = "qspi_data";
};
- qspi_data12: qspi-data12 {
- pinmux-data {
- pins = "gpio66", "gpio67";
- function = "qspi_data";
- };
+ qspi_data12: qspi-data12-state {
+ pins = "gpio66", "gpio67";
+ function = "qspi_data";
};
- qup_i2c0_default: qup-i2c0-default {
- pinmux {
- pins = "gpio34", "gpio35";
- function = "qup00";
- };
+ qup_i2c0_default: qup-i2c0-default-state {
+ pins = "gpio34", "gpio35";
+ function = "qup00";
};
- qup_i2c1_default: qup-i2c1-default {
- pinmux {
- pins = "gpio0", "gpio1";
- function = "qup01";
- };
+ qup_i2c1_default: qup-i2c1-default-state {
+ pins = "gpio0", "gpio1";
+ function = "qup01";
};
- qup_i2c2_default: qup-i2c2-default {
- pinmux {
- pins = "gpio15", "gpio16";
- function = "qup02_i2c";
- };
+ qup_i2c2_default: qup-i2c2-default-state {
+ pins = "gpio15", "gpio16";
+ function = "qup02_i2c";
};
- qup_i2c3_default: qup-i2c3-default {
- pinmux {
- pins = "gpio38", "gpio39";
- function = "qup03";
- };
+ qup_i2c3_default: qup-i2c3-default-state {
+ pins = "gpio38", "gpio39";
+ function = "qup03";
};
- qup_i2c4_default: qup-i2c4-default {
- pinmux {
- pins = "gpio115", "gpio116";
- function = "qup04_i2c";
- };
+ qup_i2c4_default: qup-i2c4-default-state {
+ pins = "gpio115", "gpio116";
+ function = "qup04_i2c";
};
- qup_i2c5_default: qup-i2c5-default {
- pinmux {
- pins = "gpio25", "gpio26";
- function = "qup05";
- };
+ qup_i2c5_default: qup-i2c5-default-state {
+ pins = "gpio25", "gpio26";
+ function = "qup05";
};
- qup_i2c6_default: qup-i2c6-default {
- pinmux {
- pins = "gpio59", "gpio60";
- function = "qup10";
- };
+ qup_i2c6_default: qup-i2c6-default-state {
+ pins = "gpio59", "gpio60";
+ function = "qup10";
};
- qup_i2c7_default: qup-i2c7-default {
- pinmux {
- pins = "gpio6", "gpio7";
- function = "qup11_i2c";
- };
+ qup_i2c7_default: qup-i2c7-default-state {
+ pins = "gpio6", "gpio7";
+ function = "qup11_i2c";
};
- qup_i2c8_default: qup-i2c8-default {
- pinmux {
- pins = "gpio42", "gpio43";
- function = "qup12";
- };
+ qup_i2c8_default: qup-i2c8-default-state {
+ pins = "gpio42", "gpio43";
+ function = "qup12";
};
- qup_i2c9_default: qup-i2c9-default {
- pinmux {
- pins = "gpio46", "gpio47";
- function = "qup13_i2c";
- };
+ qup_i2c9_default: qup-i2c9-default-state {
+ pins = "gpio46", "gpio47";
+ function = "qup13_i2c";
};
- qup_i2c10_default: qup-i2c10-default {
- pinmux {
- pins = "gpio86", "gpio87";
- function = "qup14";
- };
+ qup_i2c10_default: qup-i2c10-default-state {
+ pins = "gpio86", "gpio87";
+ function = "qup14";
};
- qup_i2c11_default: qup-i2c11-default {
- pinmux {
- pins = "gpio53", "gpio54";
- function = "qup15";
- };
+ qup_i2c11_default: qup-i2c11-default-state {
+ pins = "gpio53", "gpio54";
+ function = "qup15";
+ };
+
+ qup_spi0_spi: qup-spi0-spi-state {
+ pins = "gpio34", "gpio35", "gpio36";
+ function = "qup00";
+ };
+
+ qup_spi0_cs: qup-spi0-cs-state {
+ pins = "gpio37";
+ function = "qup00";
+ };
+
+ qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
+ pins = "gpio37";
+ function = "gpio";
+ };
+
+ qup_spi1_spi: qup-spi1-spi-state {
+ pins = "gpio0", "gpio1", "gpio2";
+ function = "qup01";
+ };
+
+ qup_spi1_cs: qup-spi1-cs-state {
+ pins = "gpio3";
+ function = "qup01";
+ };
+
+ qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
+ pins = "gpio3";
+ function = "gpio";
+ };
+
+ qup_spi3_spi: qup-spi3-spi-state {
+ pins = "gpio38", "gpio39", "gpio40";
+ function = "qup03";
+ };
+
+ qup_spi3_cs: qup-spi3-cs-state {
+ pins = "gpio41";
+ function = "qup03";
};
- qup_spi0_default: qup-spi0-default {
- pinmux {
- pins = "gpio34", "gpio35",
- "gpio36", "gpio37";
+ qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
+ pins = "gpio41";
+ function = "gpio";
+ };
+
+ qup_spi5_spi: qup-spi5-spi-state {
+ pins = "gpio25", "gpio26", "gpio27";
+ function = "qup05";
+ };
+
+ qup_spi5_cs: qup-spi5-cs-state {
+ pins = "gpio28";
+ function = "qup05";
+ };
+
+ qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
+ pins = "gpio28";
+ function = "gpio";
+ };
+
+ qup_spi6_spi: qup-spi6-spi-state {
+ pins = "gpio59", "gpio60", "gpio61";
+ function = "qup10";
+ };
+
+ qup_spi6_cs: qup-spi6-cs-state {
+ pins = "gpio62";
+ function = "qup10";
+ };
+
+ qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
+ pins = "gpio62";
+ function = "gpio";
+ };
+
+ qup_spi8_spi: qup-spi8-spi-state {
+ pins = "gpio42", "gpio43", "gpio44";
+ function = "qup12";
+ };
+
+ qup_spi8_cs: qup-spi8-cs-state {
+ pins = "gpio45";
+ function = "qup12";
+ };
+
+ qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
+ pins = "gpio45";
+ function = "gpio";
+ };
+
+ qup_spi10_spi: qup-spi10-spi-state {
+ pins = "gpio86", "gpio87", "gpio88";
+ function = "qup14";
+ };
+
+ qup_spi10_cs: qup-spi10-cs-state {
+ pins = "gpio89";
+ function = "qup14";
+ };
+
+ qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
+ pins = "gpio89";
+ function = "gpio";
+ };
+
+ qup_spi11_spi: qup-spi11-spi-state {
+ pins = "gpio53", "gpio54", "gpio55";
+ function = "qup15";
+ };
+
+ qup_spi11_cs: qup-spi11-cs-state {
+ pins = "gpio56";
+ function = "qup15";
+ };
+
+ qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
+ pins = "gpio56";
+ function = "gpio";
+ };
+
+ qup_uart0_default: qup-uart0-default-state {
+ qup_uart0_cts: cts-pins {
+ pins = "gpio34";
function = "qup00";
};
- };
- qup_spi0_cs_gpio: qup-spi0-cs-gpio {
- pinmux {
- pins = "gpio34", "gpio35",
- "gpio36";
+ qup_uart0_rts: rts-pins {
+ pins = "gpio35";
function = "qup00";
};
- pinmux-cs {
+ qup_uart0_tx: tx-pins {
+ pins = "gpio36";
+ function = "qup00";
+ };
+
+ qup_uart0_rx: rx-pins {
pins = "gpio37";
- function = "gpio";
+ function = "qup00";
};
};
- qup_spi1_default: qup-spi1-default {
- pinmux {
- pins = "gpio0", "gpio1",
- "gpio2", "gpio3";
+ qup_uart1_default: qup-uart1-default-state {
+ qup_uart1_cts: cts-pins {
+ pins = "gpio0";
function = "qup01";
};
- };
- qup_spi1_cs_gpio: qup-spi1-cs-gpio {
- pinmux {
- pins = "gpio0", "gpio1",
- "gpio2";
+ qup_uart1_rts: rts-pins {
+ pins = "gpio1";
function = "qup01";
};
- pinmux-cs {
- pins = "gpio3";
- function = "gpio";
+ qup_uart1_tx: tx-pins {
+ pins = "gpio2";
+ function = "qup01";
};
- };
- qup_spi3_default: qup-spi3-default {
- pinmux {
- pins = "gpio38", "gpio39",
- "gpio40", "gpio41";
- function = "qup03";
+ qup_uart1_rx: rx-pins {
+ pins = "gpio3";
+ function = "qup01";
};
};
- qup_spi3_cs_gpio: qup-spi3-cs-gpio {
- pinmux {
- pins = "gpio38", "gpio39",
- "gpio40";
- function = "qup03";
+ qup_uart2_default: qup-uart2-default-state {
+ qup_uart2_tx: tx-pins {
+ pins = "gpio15";
+ function = "qup02_uart";
};
- pinmux-cs {
- pins = "gpio41";
- function = "gpio";
+ qup_uart2_rx: rx-pins {
+ pins = "gpio16";
+ function = "qup02_uart";
};
};
- qup_spi5_default: qup-spi5-default {
- pinmux {
- pins = "gpio25", "gpio26",
- "gpio27", "gpio28";
- function = "qup05";
+ qup_uart3_default: qup-uart3-default-state {
+ qup_uart3_cts: cts-pins {
+ pins = "gpio38";
+ function = "qup03";
};
- };
- qup_spi5_cs_gpio: qup-spi5-cs-gpio {
- pinmux {
- pins = "gpio25", "gpio26",
- "gpio27";
- function = "qup05";
+ qup_uart3_rts: rts-pins {
+ pins = "gpio39";
+ function = "qup03";
};
- pinmux-cs {
- pins = "gpio28";
- function = "gpio";
+ qup_uart3_tx: tx-pins {
+ pins = "gpio40";
+ function = "qup03";
};
- };
- qup_spi6_default: qup-spi6-default {
- pinmux {
- pins = "gpio59", "gpio60",
- "gpio61", "gpio62";
- function = "qup10";
+ qup_uart3_rx: rx-pins {
+ pins = "gpio41";
+ function = "qup03";
};
};
- qup_spi6_cs_gpio: qup-spi6-cs-gpio {
- pinmux {
- pins = "gpio59", "gpio60",
- "gpio61";
- function = "qup10";
+ qup_uart4_default: qup-uart4-default-state {
+ qup_uart4_tx: tx-pins {
+ pins = "gpio115";
+ function = "qup04_uart";
};
- pinmux-cs {
- pins = "gpio62";
- function = "gpio";
+ qup_uart4_rx: rx-pins {
+ pins = "gpio116";
+ function = "qup04_uart";
};
};
- qup_spi8_default: qup-spi8-default {
- pinmux {
- pins = "gpio42", "gpio43",
- "gpio44", "gpio45";
- function = "qup12";
+ qup_uart5_default: qup-uart5-default-state {
+ qup_uart5_cts: cts-pins {
+ pins = "gpio25";
+ function = "qup05";
};
- };
- qup_spi8_cs_gpio: qup-spi8-cs-gpio {
- pinmux {
- pins = "gpio42", "gpio43",
- "gpio44";
- function = "qup12";
+ qup_uart5_rts: rts-pins {
+ pins = "gpio26";
+ function = "qup05";
};
- pinmux-cs {
- pins = "gpio45";
- function = "gpio";
+ qup_uart5_tx: tx-pins {
+ pins = "gpio27";
+ function = "qup05";
};
- };
- qup_spi10_default: qup-spi10-default {
- pinmux {
- pins = "gpio86", "gpio87",
- "gpio88", "gpio89";
- function = "qup14";
+ qup_uart5_rx: rx-pins {
+ pins = "gpio28";
+ function = "qup05";
};
};
- qup_spi10_cs_gpio: qup-spi10-cs-gpio {
- pinmux {
- pins = "gpio86", "gpio87",
- "gpio88";
- function = "qup14";
+ qup_uart6_default: qup-uart6-default-state {
+ qup_uart6_cts: cts-pins {
+ pins = "gpio59";
+ function = "qup10";
};
- pinmux-cs {
- pins = "gpio89";
- function = "gpio";
+ qup_uart6_rts: rts-pins {
+ pins = "gpio60";
+ function = "qup10";
};
- };
- qup_spi11_default: qup-spi11-default {
- pinmux {
- pins = "gpio53", "gpio54",
- "gpio55", "gpio56";
- function = "qup15";
+ qup_uart6_tx: tx-pins {
+ pins = "gpio61";
+ function = "qup10";
+ };
+
+ qup_uart6_rx: rx-pins {
+ pins = "gpio62";
+ function = "qup10";
};
};
- qup_spi11_cs_gpio: qup-spi11-cs-gpio {
- pinmux {
- pins = "gpio53", "gpio54",
- "gpio55";
- function = "qup15";
+ qup_uart7_default: qup-uart7-default-state {
+ qup_uart7_tx: tx-pins {
+ pins = "gpio6";
+ function = "qup11_uart";
};
- pinmux-cs {
- pins = "gpio56";
- function = "gpio";
+ qup_uart7_rx: rx-pins {
+ pins = "gpio7";
+ function = "qup11_uart";
};
};
- qup_uart0_default: qup-uart0-default {
- pinmux {
- pins = "gpio34", "gpio35",
- "gpio36", "gpio37";
- function = "qup00";
+ qup_uart8_default: qup-uart8-default-state {
+ qup_uart8_tx: tx-pins {
+ pins = "gpio44";
+ function = "qup12";
};
- };
- qup_uart1_default: qup-uart1-default {
- pinmux {
- pins = "gpio0", "gpio1",
- "gpio2", "gpio3";
- function = "qup01";
+ qup_uart8_rx: rx-pins {
+ pins = "gpio45";
+ function = "qup12";
};
};
- qup_uart2_default: qup-uart2-default {
- pinmux {
- pins = "gpio15", "gpio16";
- function = "qup02_uart";
+ qup_uart9_default: qup-uart9-default-state {
+ qup_uart9_tx: tx-pins {
+ pins = "gpio46";
+ function = "qup13_uart";
};
- };
- qup_uart3_default: qup-uart3-default {
- pinmux {
- pins = "gpio38", "gpio39",
- "gpio40", "gpio41";
- function = "qup03";
+ qup_uart9_rx: rx-pins {
+ pins = "gpio47";
+ function = "qup13_uart";
};
};
- qup_uart4_default: qup-uart4-default {
- pinmux {
- pins = "gpio115", "gpio116";
- function = "qup04_uart";
+ qup_uart10_default: qup-uart10-default-state {
+ qup_uart10_cts: cts-pins {
+ pins = "gpio86";
+ function = "qup14";
};
- };
- qup_uart5_default: qup-uart5-default {
- pinmux {
- pins = "gpio25", "gpio26",
- "gpio27", "gpio28";
- function = "qup05";
+ qup_uart10_rts: rts-pins {
+ pins = "gpio87";
+ function = "qup14";
};
- };
- qup_uart6_default: qup-uart6-default {
- pinmux {
- pins = "gpio59", "gpio60",
- "gpio61", "gpio62";
- function = "qup10";
+ qup_uart10_tx: tx-pins {
+ pins = "gpio88";
+ function = "qup14";
};
- };
- qup_uart7_default: qup-uart7-default {
- pinmux {
- pins = "gpio6", "gpio7";
- function = "qup11_uart";
+ qup_uart10_rx: rx-pins {
+ pins = "gpio89";
+ function = "qup14";
};
};
- qup_uart8_default: qup-uart8-default {
- pinmux {
- pins = "gpio44", "gpio45";
- function = "qup12";
+ qup_uart11_default: qup-uart11-default-state {
+ qup_uart11_cts: cts-pins {
+ pins = "gpio53";
+ function = "qup15";
};
- };
- qup_uart9_default: qup-uart9-default {
- pinmux {
- pins = "gpio46", "gpio47";
- function = "qup13_uart";
+ qup_uart11_rts: rts-pins {
+ pins = "gpio54";
+ function = "qup15";
};
- };
- qup_uart10_default: qup-uart10-default {
- pinmux {
- pins = "gpio86", "gpio87",
- "gpio88", "gpio89";
- function = "qup14";
+ qup_uart11_tx: tx-pins {
+ pins = "gpio55";
+ function = "qup15";
};
- };
- qup_uart11_default: qup-uart11-default {
- pinmux {
- pins = "gpio53", "gpio54",
- "gpio55", "gpio56";
+ qup_uart11_rx: rx-pins {
+ pins = "gpio56";
function = "qup15";
};
};
- sec_mi2s_active: sec-mi2s-active {
- pinmux {
- pins = "gpio49", "gpio50", "gpio51";
- function = "mi2s_1";
- };
+ sec_mi2s_active: sec-mi2s-active-state {
+ pins = "gpio49", "gpio50", "gpio51";
+ function = "mi2s_1";
};
- pri_mi2s_active: pri-mi2s-active {
- pinmux {
- pins = "gpio53", "gpio54", "gpio55", "gpio56";
- function = "mi2s_0";
- };
+ pri_mi2s_active: pri-mi2s-active-state {
+ pins = "gpio53", "gpio54", "gpio55", "gpio56";
+ function = "mi2s_0";
};
- pri_mi2s_mclk_active: pri-mi2s-mclk-active {
- pinmux {
- pins = "gpio57";
- function = "lpass_ext";
- };
+ pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
+ pins = "gpio57";
+ function = "lpass_ext";
};
};
@@ -2775,6 +2809,7 @@
"dm_hs_phy_irq", "dp_hs_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
resets = <&gcc GCC_USB30_PRIM_BCR>;
@@ -2782,6 +2817,8 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
interconnect-names = "usb-ddr", "apps-usb";
+ wakeup-source;
+
usb_1_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xe000>;
@@ -3012,7 +3049,6 @@
power-domains = <&rpmhpd SC7180_CX>;
phys = <&dsi_phy>;
- phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
@@ -3057,7 +3093,7 @@
};
};
- dsi_phy: dsi-phy@ae94400 {
+ dsi_phy: phy@ae94400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0 0x0ae94400 0 0x200>,
<0 0x0ae94600 0 0x280>,
@@ -3522,7 +3558,7 @@
};
osm_l3: interconnect@18321000 {
- compatible = "qcom,sc7180-osm-l3";
+ compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3";
reg = <0 0x18321000 0 0x1400>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
index 25f31c81b2b7..16fb20369c01 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
@@ -39,20 +39,10 @@
no-map;
};
- mpss_mem: memory@8b800000 {
- reg = <0x0 0x8b800000 0x0 0xf600000>;
- no-map;
- };
-
wpss_mem: memory@9ae00000 {
reg = <0x0 0x9ae00000 0x0 0x1900000>;
no-map;
};
-
- mba_mem: memory@9c700000 {
- reg = <0x0 0x9c700000 0x0 0x200000>;
- no-map;
- };
};
};
@@ -88,11 +78,6 @@
firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt";
};
-/* Increase the size from 2.5MB to 8MB */
-&rmtfs_mem {
- reg = <0x0 0x9c900000 0x0 0x800000>;
-};
-
&wifi {
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
index dddb505e220b..1185141f348e 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
@@ -118,25 +118,25 @@ ap_ts_pen_1v8: &i2c13 {
};
&tlmm {
- tp_int_odl: tp-int-odl {
+ tp_int_odl: tp-int-odl-state {
pins = "gpio7";
function = "gpio";
bias-disable;
};
- ts_int_l: ts-int-l {
+ ts_int_l: ts-int-l-state {
pins = "gpio55";
function = "gpio";
bias-pull-up;
};
- ts_reset_l: ts-reset-l {
+ ts_reset_l: ts-reset-l-state {
pins = "gpio54";
function = "gpio";
bias-disable;
};
- us_euro_hs_sel: us-euro-hs-sel {
+ us_euro_hs_sel: us-euro-hs-sel-state {
pins = "gpio81";
function = "gpio";
bias-pull-down;
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi
new file mode 100644
index 000000000000..1ca11a14104d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ *
+ * This file defines the common audio settings for the child boards
+ * using rt5682 codec and having 3 dmics connected to sc7280.
+ *
+ * Copyright 2022 Google LLC.
+ */
+
+/ {
+ /* BOARD-SPECIFIC TOP LEVEL NODES */
+ sound: sound {
+ compatible = "google,sc7280-herobrine";
+ model = "sc7280-rt5682-max98360a-3mic";
+
+ audio-routing = "VA DMIC0", "vdd-micb",
+ "VA DMIC1", "vdd-micb",
+ "VA DMIC2", "vdd-micb",
+ "VA DMIC3", "vdd-micb",
+
+ "Headphone Jack", "HPOL",
+ "Headphone Jack", "HPOR";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dai-link@0 {
+ link-name = "MAX98360";
+ reg = <0>;
+
+ cpu {
+ sound-dai = <&lpass_cpu MI2S_SECONDARY>;
+ };
+
+ codec {
+ sound-dai = <&max98360a>;
+ };
+ };
+
+ dai-link@1 {
+ link-name = "DisplayPort";
+ reg = <1>;
+
+ cpu {
+ sound-dai = <&lpass_cpu LPASS_DP_RX>;
+ };
+
+ codec {
+ sound-dai = <&mdss_dp>;
+ };
+ };
+
+ dai-link@2 {
+ link-name = "ALC5682";
+ reg = <2>;
+
+ cpu {
+ sound-dai = <&lpass_cpu MI2S_PRIMARY>;
+ };
+
+ codec {
+ sound-dai = <&alc5682 0 /* aif1 */>;
+ };
+ };
+
+ dai-link@4 {
+ link-name = "DMIC";
+ reg = <4>;
+
+ cpu {
+ sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>;
+ };
+
+ codec {
+ sound-dai = <&lpass_va_macro 0>;
+ };
+ };
+ };
+};
+
+hp_i2c: &i2c2 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ alc5682: codec@1a {
+ compatible = "realtek,rt5682s";
+ reg = <0x1a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_irq>;
+
+ #sound-dai-cells = <1>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <101 IRQ_TYPE_EDGE_BOTH>;
+
+ AVDD-supply = <&pp1800_alc5682>;
+ MICVDD-supply = <&pp3300_codec>;
+
+ realtek,dmic1-data-pin = <1>;
+ realtek,dmic1-clk-pin = <2>;
+ realtek,jd-src = <1>;
+ realtek,dmic-clk-rate-hz = <2048000>;
+ };
+};
+
+&lpass_cpu {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mi2s0_data0>, <&mi2s0_data1>, <&mi2s0_mclk>, <&mi2s0_sclk>, <&mi2s0_ws>,
+ <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "okay";
+
+ dai-link@0 {
+ reg = <MI2S_PRIMARY>;
+ qcom,playback-sd-lines = <1>;
+ qcom,capture-sd-lines = <0>;
+ };
+
+ dai-link@1 {
+ reg = <MI2S_SECONDARY>;
+ qcom,playback-sd-lines = <0>;
+ };
+
+ dai-link@5 {
+ reg = <LPASS_DP_RX>;
+ };
+
+ dai-link@25 {
+ reg = <LPASS_CDC_DMA_VA_TX0>;
+ };
+};
+
+&lpass_va_macro {
+ vdd-micb-supply = <&pp1800_l2c>;
+ pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>, <&lpass_dmic23_clk>,
+ <&lpass_dmic23_data>;
+
+ status = "okay";
+};
+
+/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
+
+&lpass_dmic01_clk {
+ drive-strength = <8>;
+ bias-disable;
+};
+
+&lpass_dmic01_data {
+ bias-pull-down;
+};
+
+&lpass_dmic23_clk {
+ drive-strength = <8>;
+ bias-disable;
+};
+
+&lpass_dmic23_data {
+ bias-pull-down;
+};
+
+&mi2s0_data0 {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&mi2s0_data1 {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&mi2s0_mclk {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&mi2s0_sclk {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&mi2s0_ws {
+ drive-strength = <6>;
+ bias-disable;
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi
new file mode 100644
index 000000000000..af685bc35e10
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ *
+ * This file defines the common audio settings for the child boards
+ * using rt5682 codec.
+ *
+ * Copyright 2022 Google LLC.
+ */
+
+/ {
+ /* BOARD-SPECIFIC TOP LEVEL NODES */
+ sound: sound {
+ compatible = "google,sc7280-herobrine";
+ model = "sc7280-rt5682-max98360a-1mic";
+
+ audio-routing = "Headphone Jack", "HPOL",
+ "Headphone Jack", "HPOR";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dai-link@0 {
+ link-name = "MAX98360";
+ reg = <0>;
+
+ cpu {
+ sound-dai = <&lpass_cpu MI2S_SECONDARY>;
+ };
+
+ codec {
+ sound-dai = <&max98360a>;
+ };
+ };
+
+ dai-link@1 {
+ link-name = "ALC5682";
+ reg = <1>;
+
+ cpu {
+ sound-dai = <&lpass_cpu MI2S_PRIMARY>;
+ };
+
+ codec {
+ sound-dai = <&alc5682 0 /* aif1 */>;
+ };
+ };
+ };
+};
+
+hp_i2c: &i2c2 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ alc5682: codec@1a {
+ compatible = "realtek,rt5682s";
+ reg = <0x1a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_irq>;
+
+ #sound-dai-cells = <1>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <101 IRQ_TYPE_EDGE_BOTH>;
+
+ AVDD-supply = <&pp1800_alc5682>;
+ MICVDD-supply = <&pp3300_codec>;
+
+ realtek,dmic1-data-pin = <1>;
+ realtek,dmic1-clk-pin = <2>;
+ realtek,jd-src = <1>;
+ realtek,dmic-clk-rate-hz = <2048000>;
+ };
+};
+
+&lpass_cpu {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mi2s0_data0>, <&mi2s0_data1>, <&mi2s0_mclk>, <&mi2s0_sclk>, <&mi2s0_ws>,
+ <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "okay";
+
+ dai-link@0 {
+ reg = <MI2S_PRIMARY>;
+ qcom,playback-sd-lines = <1>;
+ qcom,capture-sd-lines = <0>;
+ };
+
+ dai-link@1 {
+ reg = <MI2S_SECONDARY>;
+ qcom,playback-sd-lines = <0>;
+ };
+};
+
+/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
+
+&mi2s0_data0 {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&mi2s0_data1 {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&mi2s0_mclk {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&mi2s0_sclk {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&mi2s0_ws {
+ drive-strength = <6>;
+ bias-disable;
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi
index c72e53aaf997..ae2552094cda 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi
@@ -167,10 +167,6 @@
bias-disable;
};
-&lpass_dmic01_clk_sleep {
- drive-strength = <2>;
-};
-
&lpass_dmic01_data {
bias-pull-down;
};
@@ -180,10 +176,6 @@
bias-disable;
};
-&lpass_dmic23_clk_sleep {
- drive-strength = <2>;
-};
-
&lpass_dmic23_data {
bias-pull-down;
};
@@ -194,30 +186,18 @@
bias-disable;
};
-&lpass_rx_swr_clk_sleep {
- bias-pull-down;
-};
-
&lpass_rx_swr_data {
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
-&lpass_rx_swr_data_sleep {
- bias-pull-down;
-};
-
&lpass_tx_swr_clk {
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
-&lpass_tx_swr_clk_sleep {
- bias-pull-down;
-};
-
&lpass_tx_swr_data {
drive-strength = <2>;
slew-rate = <1>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
index f0f26af1e421..4e0b013e25f4 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
@@ -372,5 +372,6 @@ ap_ts_pen_1v8: &i2c13 {
"", /* 170 */
"MOS_BLE_UART_TX",
"MOS_BLE_UART_RX",
+ "",
"";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-lte.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-lte.dts
new file mode 100644
index 000000000000..14f20e705869
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-lte.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Evoker board device tree source
+ *
+ * Copyright 2022 Google LLC.
+ */
+
+/dts-v1/;
+
+#include "sc7280-herobrine-evoker.dtsi"
+#include "sc7280-herobrine-lte-sku.dtsi"
+
+/ {
+ model = "Google Evoker with LTE";
+ compatible = "google,evoker-sku512", "qcom,sc7280";
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dts
new file mode 100644
index 000000000000..4f781fe25c9c
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Evoker board device tree source
+ *
+ * Copyright 2022 Google LLC.
+ */
+
+/dts-v1/;
+
+#include "sc7280-herobrine-evoker.dtsi"
+#include "sc7280-herobrine-wifi-sku.dtsi"
+
+/ {
+ model = "Google Evoker";
+ compatible = "google,evoker", "qcom,sc7280";
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi
index ccbe50b6249a..3d639c70a06e 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi
@@ -5,14 +5,8 @@
* Copyright 2022 Google LLC.
*/
-/dts-v1/;
-
#include "sc7280-herobrine.dtsi"
-
-/ {
- model = "Google Evoker";
- compatible = "google,evoker", "qcom,sc7280";
-};
+#include "sc7280-herobrine-audio-rt5682-3mic.dtsi"
/*
* ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES
@@ -30,16 +24,15 @@ ap_tp_i2c: &i2c0 {
status = "okay";
clock-frequency = <400000>;
- trackpad: trackpad@2c {
- compatible = "hid-over-i2c";
- reg = <0x2c>;
+ trackpad: trackpad@15 {
+ compatible = "elan,ekth3000";
+ reg = <0x15>;
pinctrl-names = "default";
pinctrl-0 = <&tp_int_odl>;
interrupt-parent = <&tlmm>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
- hid-descr-addr = <0x20>;
vcc-supply = <&pp3300_z1>;
wakeup-source;
@@ -50,9 +43,9 @@ ts_i2c: &i2c13 {
status = "okay";
clock-frequency = <400000>;
- ap_ts: touchscreen@10 {
- compatible = "elan,ekth6915";
- reg = <0x10>;
+ ap_ts: touchscreen@5d {
+ compatible = "goodix,gt7986u", "goodix,gt7375p";
+ reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>;
@@ -61,7 +54,7 @@ ts_i2c: &i2c13 {
reset-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
- vcc33-supply = <&ts_avdd>;
+ vdd-supply = <&ts_avdd>;
};
};
@@ -328,6 +321,5 @@ ts_i2c: &i2c13 {
"MOS_BLE_UART_TX",
"MOS_BLE_UART_RX",
"",
- "",
"";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts
index c1a671968725..b04888a98203 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts
@@ -8,6 +8,7 @@
/dts-v1/;
#include "sc7280-herobrine.dtsi"
+#include "sc7280-herobrine-audio-rt5682.dtsi"
#include "sc7280-herobrine-lte-sku.dtsi"
/ {
@@ -47,10 +48,6 @@
/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
-&ap_spi_fp {
- status = "okay";
-};
-
/*
* Although the trackpad is really part of the herobrine baseboard, we'll
* put the actual definition in the board device tree since different boards
@@ -358,6 +355,5 @@ ts_i2c: &i2c13 {
"MOS_BLE_UART_TX",
"MOS_BLE_UART_RX",
"",
- "",
"";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi
index a92eeccd2b2a..ad66e5e9db4e 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi
@@ -6,6 +6,20 @@
*/
/* Modem setup is different on Chrome setups than typical Qualcomm setup */
+/ {
+ reserved-memory {
+ mpss_mem: memory@8b800000 {
+ reg = <0x0 0x8b800000 0x0 0xf600000>;
+ no-map;
+ };
+
+ mba_mem: memory@9c700000 {
+ reg = <0x0 0x9c700000 0x0 0x200000>;
+ no-map;
+ };
+ };
+};
+
&remoteproc_mpss {
compatible = "qcom,sc7280-mss-pil";
iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
@@ -15,3 +29,8 @@
"qcom/sc7280-herobrine/modem/qdsp6sw.mbn";
status = "okay";
};
+
+/* Increase the size from 2.5MB to 8MB */
+&rmtfs_mem {
+ reg = <0x0 0x9c900000 0x0 0x800000>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1-lte.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1-lte.dts
index f1017809e5da..d71cc4bbc4b3 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1-lte.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1-lte.dts
@@ -5,7 +5,9 @@
* Copyright 2022 Google LLC.
*/
-#include "sc7280-herobrine-villager-r1.dts"
+/dts-v1/;
+
+#include "sc7280-herobrine-villager-r1.dtsi"
#include "sc7280-herobrine-lte-sku.dtsi"
/ {
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dts
index cfc648726930..edb52f12f0ea 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dts
@@ -7,37 +7,10 @@
/dts-v1/;
-#include "sc7280-herobrine-villager.dtsi"
-#include "sc7280-herobrine-audio-wcd9385.dtsi"
+#include "sc7280-herobrine-villager-r1.dtsi"
+#include "sc7280-herobrine-wifi-sku.dtsi"
/ {
model = "Google Villager (rev1+)";
compatible = "google,villager", "qcom,sc7280";
};
-
-&lpass_va_macro {
- vdd-micb-supply = <&pp1800_l2c>;
-};
-
-&sound {
- audio-routing =
- "IN1_HPHL", "HPHL_OUT",
- "IN2_HPHR", "HPHR_OUT",
- "AMIC1", "MIC BIAS1",
- "AMIC2", "MIC BIAS2",
- "VA DMIC0", "vdd-micb",
- "VA DMIC1", "vdd-micb",
- "VA DMIC2", "vdd-micb",
- "VA DMIC3", "vdd-micb",
- "TX SWR_ADC0", "ADC1_OUTPUT",
- "TX SWR_ADC1", "ADC2_OUTPUT",
- "TX SWR_ADC2", "ADC3_OUTPUT",
- "TX SWR_DMIC0", "DMIC1_OUTPUT",
- "TX SWR_DMIC1", "DMIC2_OUTPUT",
- "TX SWR_DMIC2", "DMIC3_OUTPUT",
- "TX SWR_DMIC3", "DMIC4_OUTPUT",
- "TX SWR_DMIC4", "DMIC5_OUTPUT",
- "TX SWR_DMIC5", "DMIC6_OUTPUT",
- "TX SWR_DMIC6", "DMIC7_OUTPUT",
- "TX SWR_DMIC7", "DMIC8_OUTPUT";
-};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dtsi
new file mode 100644
index 000000000000..b25df5a99161
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Villager board device tree source
+ *
+ * Copyright 2022 Google LLC.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "sc7280-herobrine-villager.dtsi"
+#include "sc7280-herobrine-audio-wcd9385.dtsi"
+
+&lpass_va_macro {
+ vdd-micb-supply = <&pp1800_l2c>;
+};
+
+&sound {
+ audio-routing =
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC1", "MIC BIAS1",
+ "AMIC2", "MIC BIAS2",
+ "VA DMIC0", "vdd-micb",
+ "VA DMIC1", "vdd-micb",
+ "VA DMIC2", "vdd-micb",
+ "VA DMIC3", "vdd-micb",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT";
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi
index 4566722bf4dd..17553e0fd6fd 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi
@@ -78,16 +78,6 @@ ts_i2c: &i2c13 {
status = "okay";
};
-/* For nvme */
-&pcie1 {
- status = "okay";
-};
-
-/* For nvme */
-&pcie1_phy {
- status = "okay";
-};
-
&pwmleds {
status = "okay";
};
@@ -321,6 +311,5 @@ ts_i2c: &i2c13 {
"MOS_BLE_UART_TX",
"MOS_BLE_UART_RX",
"",
- "",
"";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-wifi-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-wifi-sku.dtsi
new file mode 100644
index 000000000000..2febd6126d4c
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-wifi-sku.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Google Herobrine dts fragment for WIFI SKUs
+ *
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/* WIFI SKUs save 256M by not having modem/mba/rmtfs memory regions defined. */
+
+/delete-node/ &remoteproc_mpss;
+/delete-node/ &rmtfs_mem;
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-lte.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-lte.dts
new file mode 100644
index 000000000000..c9fe64529555
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-lte.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Zombie board device tree source
+ *
+ * Copyright 2022 Google LLC.
+ */
+
+/dts-v1/;
+
+#include "sc7280-herobrine-zombie.dtsi"
+#include "sc7280-herobrine-lte-sku.dtsi"
+
+/ {
+ model = "Google Zombie with LTE";
+ compatible = "google,zombie-sku512", "qcom,sc7280";
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie.dts
new file mode 100644
index 000000000000..0246c12b2f40
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Zombie board device tree source
+ *
+ * Copyright 2022 Google LLC.
+ */
+
+/dts-v1/;
+
+#include "sc7280-herobrine-zombie.dtsi"
+#include "sc7280-herobrine-wifi-sku.dtsi"
+
+/ {
+ model = "Google Zombie";
+ compatible = "google,zombie", "qcom,sc7280";
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie.dtsi
new file mode 100644
index 000000000000..7fc0b6bfc0d6
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie.dtsi
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Zombie board device tree source
+ *
+ * Copyright 2022 Google LLC.
+ */
+
+#include "sc7280-herobrine.dtsi"
+#include "sc7280-herobrine-audio-rt5682.dtsi"
+
+/*
+ * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES
+ *
+ * Sort order matches the order in the parent files (parents before children).
+ */
+
+&pp3300_codec {
+ status = "okay";
+};
+
+/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
+
+ap_tp_i2c: &i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ trackpad: trackpad@15 {
+ compatible = "hid-over-i2c";
+ reg = <0x15>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&tp_int_odl>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+
+ hid-descr-addr = <0x01>;
+ vdd-supply = <&pp3300_z1>;
+
+ wakeup-source;
+ };
+};
+
+&ap_sar_sensor_i2c {
+ status = "okay";
+};
+
+&ap_sar_sensor0 {
+ status = "okay";
+};
+
+&ap_sar_sensor1 {
+ status = "okay";
+};
+
+&mdss_edp {
+ status = "okay";
+};
+
+&mdss_edp_phy {
+ status = "okay";
+};
+
+/* For nvme */
+&pcie1 {
+ status = "okay";
+};
+
+/* For nvme */
+&pcie1_phy {
+ status = "okay";
+};
+
+&pm8350c_pwm_backlight{
+ /* Set the PWM period to 200 microseconds (5kHz duty cycle) */
+ pwms = <&pm8350c_pwm 3 200000>;
+};
+
+&pwmleds {
+ status = "okay";
+};
+
+/* For eMMC */
+&sdhc_1 {
+ status = "okay";
+};
+
+/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
+
+&ts_rst_conn {
+ bias-disable;
+};
+
+/* PINCTRL - BOARD-SPECIFIC */
+
+/*
+ * Methodology for gpio-line-names:
+ * - If a pin goes to herobrine board and is named it gets that name.
+ * - If a pin goes to herobrine board and is not named, it gets no name.
+ * - If a pin is totally internal to Qcard then it gets Qcard name.
+ * - If a pin is not hooked up on Qcard, it gets no name.
+ */
+
+&pm8350c_gpios {
+ gpio-line-names = "FLASH_STROBE_1", /* 1 */
+ "AP_SUSPEND",
+ "PM8008_1_RST_N",
+ "",
+ "",
+ "",
+ "PMIC_EDP_BL_EN",
+ "PMIC_EDP_BL_PWM",
+ "";
+};
+
+&tlmm {
+ gpio-line-names = "AP_TP_I2C_SDA", /* 0 */
+ "AP_TP_I2C_SCL",
+ "SSD_RST_L",
+ "PE_WAKE_ODL",
+ "AP_SAR_SDA",
+ "AP_SAR_SCL",
+ "PRB_SC_GPIO_6",
+ "TP_INT_ODL",
+ "HP_I2C_SDA",
+ "HP_I2C_SCL",
+
+ "GNSS_L1_EN", /* 10 */
+ "GNSS_L5_EN",
+ "SPI_AP_MOSI",
+ "SPI_AP_MISO",
+ "SPI_AP_CLK",
+ "SPI_AP_CS0_L",
+ /*
+ * AP_FLASH_WP is crossystem ABI. Schematics
+ * call it BIOS_FLASH_WP_OD.
+ */
+ "AP_FLASH_WP",
+ "",
+ "AP_EC_INT_L",
+ "",
+
+ "UF_CAM_RST_L", /* 20 */
+ "WF_CAM_RST_L",
+ "UART_AP_TX_DBG_RX",
+ "UART_DBG_TX_AP_RX",
+ "",
+ "PM8008_IRQ_1",
+ "HOST2WLAN_SOL",
+ "WLAN2HOST_SOL",
+ "MOS_BT_UART_CTS",
+ "MOS_BT_UART_RFR",
+
+ "MOS_BT_UART_TX", /* 30 */
+ "MOS_BT_UART_RX",
+ "PRB_SC_GPIO_32",
+ "HUB_RST_L",
+ "",
+ "",
+ "AP_SPI_FP_MISO",
+ "AP_SPI_FP_MOSI",
+ "AP_SPI_FP_CLK",
+ "AP_SPI_FP_CS_L",
+
+ "AP_EC_SPI_MISO", /* 40 */
+ "AP_EC_SPI_MOSI",
+ "AP_EC_SPI_CLK",
+ "AP_EC_SPI_CS_L",
+ "LCM_RST_L",
+ "EARLY_EUD_N",
+ "",
+ "DP_HOT_PLUG_DET",
+ "IO_BRD_MLB_ID0",
+ "IO_BRD_MLB_ID1",
+
+ "IO_BRD_MLB_ID2", /* 50 */
+ "SSD_EN",
+ "TS_I2C_SDA_CONN",
+ "TS_I2C_CLK_CONN",
+ "TS_RST_CONN",
+ "TS_INT_CONN",
+ "AP_I2C_TPM_SDA",
+ "AP_I2C_TPM_SCL",
+ "PRB_SC_GPIO_58",
+ "PRB_SC_GPIO_59",
+
+ "EDP_HOT_PLUG_DET_N", /* 60 */
+ "FP_TO_AP_IRQ_L",
+ "",
+ "AMP_EN",
+ "CAM0_MCLK_GPIO_64",
+ "CAM1_MCLK_GPIO_65",
+ "WF_CAM_MCLK",
+ "PRB_SC_GPIO_67",
+ "FPMCU_BOOT0",
+ "UF_CAM_SDA",
+
+ "UF_CAM_SCL", /* 70 */
+ "",
+ "",
+ "WF_CAM_SDA",
+ "WF_CAM_SCL",
+ "",
+ "",
+ "EN_FP_RAILS",
+ "FP_RST_L",
+ "PCIE1_CLKREQ_ODL",
+
+ "EN_PP3300_DX_EDP", /* 80 */
+ "US_EURO_HS_SEL",
+ "FORCED_USB_BOOT",
+ "WCD_RESET_N",
+ "MOS_WLAN_EN",
+ "MOS_BT_EN",
+ "MOS_SW_CTRL",
+ "MOS_PCIE0_RST",
+ "MOS_PCIE0_CLKREQ_N",
+ "MOS_PCIE0_WAKE_N",
+
+ "MOS_LAA_AS_EN", /* 90 */
+ "SD_CD_ODL",
+ "",
+ "",
+ "MOS_BT_WLAN_SLIMBUS_CLK",
+ "MOS_BT_WLAN_SLIMBUS_DAT0",
+ "HP_MCLK",
+ "HP_BCLK",
+ "HP_DOUT",
+ "HP_DIN",
+
+ "HP_LRCLK", /* 100 */
+ "HP_IRQ",
+ "",
+ "",
+ "GSC_AP_INT_ODL",
+ "EN_PP3300_CODEC",
+ "AMP_BCLK",
+ "AMP_DIN",
+ "AMP_LRCLK",
+ "UIM1_DATA_GPIO_109",
+
+ "UIM1_CLK_GPIO_110", /* 110 */
+ "UIM1_RESET_GPIO_111",
+ "PRB_SC_GPIO_112",
+ "UIM0_DATA",
+ "UIM0_CLK",
+ "UIM0_RST",
+ "UIM0_PRESENT_ODL",
+ "SDM_RFFE0_CLK",
+ "SDM_RFFE0_DATA",
+ "WF_CAM_EN",
+
+ "FASTBOOT_SEL_0", /* 120 */
+ "SC_GPIO_121",
+ "FASTBOOT_SEL_1",
+ "SC_GPIO_123",
+ "FASTBOOT_SEL_2",
+ "SM_RFFE4_CLK_GRFC_8",
+ "SM_RFFE4_DATA_GRFC_9",
+ "WLAN_COEX_UART1_RX",
+ "WLAN_COEX_UART1_TX",
+ "PRB_SC_GPIO_129",
+
+ "LCM_ID0", /* 130 */
+ "LCM_ID1",
+ "",
+ "SDR_QLINK_REQ",
+ "SDR_QLINK_EN",
+ "QLINK0_WMSS_RESET_N",
+ "SMR526_QLINK1_REQ",
+ "SMR526_QLINK1_EN",
+ "SMR526_QLINK1_WMSS_RESET_N",
+ "PRB_SC_GPIO_139",
+
+ "SAR1_IRQ_ODL", /* 140 */
+ "SAR0_IRQ_ODL",
+ "PRB_SC_GPIO_142",
+ "",
+ "WCD_SWR_TX_CLK",
+ "WCD_SWR_TX_DATA0",
+ "WCD_SWR_TX_DATA1",
+ "WCD_SWR_RX_CLK",
+ "WCD_SWR_RX_DATA0",
+ "WCD_SWR_RX_DATA1",
+
+ "DMIC01_CLK", /* 150 */
+ "DMIC01_DATA",
+ "DMIC23_CLK",
+ "DMIC23_DATA",
+ "",
+ "",
+ "EC_IN_RW_ODL",
+ "HUB_EN",
+ "WCD_SWR_TX_DATA2",
+ "",
+
+ "", /* 160 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+
+ "", /* 170 */
+ "MOS_BLE_UART_TX",
+ "MOS_BLE_UART_RX",
+ "",
+ "";
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
index c11e37160f34..27f479ff9d80 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
@@ -307,7 +307,7 @@
pwmleds: pwmleds {
compatible = "pwm-leds";
status = "disabled";
- keyboard_backlight: keyboard-backlight {
+ keyboard_backlight: led-0 {
label = "cros_ec::kbd_backlight";
function = LED_FUNCTION_KBD_BACKLIGHT;
pwms = <&cros_ec_pwm 0>;
@@ -503,13 +503,16 @@ ap_spi_fp: &spi9 {
cs-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
cros_ec_fp: ec@0 {
- compatible = "google,cros-ec-spi";
+ compatible = "google,cros-ec-fp", "google,cros-ec-spi";
reg = <0>;
interrupt-parent = <&tlmm>;
interrupts = <61 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&fp_to_ap_irq_l>, <&fp_rst_l>, <&fpmcu_boot0>;
+ boot0-gpios = <&tlmm 68 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>;
spi-max-frequency = <3000000>;
+ vdd-supply = <&pp3300_fp_mcu>;
};
};
@@ -627,6 +630,13 @@ ap_ec_spi: &spi10 {
&usb_1_hsphy {
status = "okay";
+
+ qcom,hs-rise-fall-time-bp = <0>;
+ qcom,squelch-detector-bp = <(-2090)>;
+ qcom,hs-disconnect-bp = <1743>;
+ qcom,hs-amplitude-bp = <1780>;
+ qcom,hs-crossover-voltage-microvolt = <(-31000)>;
+ qcom,hs-output-impedance-micro-ohms = <2600000>;
};
&usb_1_qmpphy {
@@ -639,6 +649,21 @@ ap_ec_spi: &spi10 {
bias-disable;
};
+&mi2s1_data0 {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&mi2s1_sclk {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&mi2s1_ws {
+ drive-strength = <6>;
+ bias-disable;
+};
+
&pcie1_clkreq_n {
bias-pull-up;
drive-strength = <2>;
@@ -744,27 +769,27 @@ ap_ec_spi: &spi10 {
pinctrl-names = "default";
pinctrl-0 = <&bios_flash_wp_od>;
- amp_en: amp-en-pins {
+ amp_en: amp-en-state {
pins = "gpio63";
function = "gpio";
bias-disable;
drive-strength = <2>;
};
- ap_ec_int_l: ap-ec-int-l-pins {
+ ap_ec_int_l: ap-ec-int-l-state {
pins = "gpio18";
function = "gpio";
bias-pull-up;
};
- bios_flash_wp_od: bios-flash-wp-od-pins {
+ bios_flash_wp_od: bios-flash-wp-od-state {
pins = "gpio16";
function = "gpio";
/* Has external pull */
bias-disable;
};
- en_fp_rails: en-fp-rails-pins {
+ en_fp_rails: en-fp-rails-state {
pins = "gpio77";
function = "gpio";
bias-disable;
@@ -772,60 +797,60 @@ ap_ec_spi: &spi10 {
output-high;
};
- en_pp3300_codec: en-pp3300-codec-pins {
+ en_pp3300_codec: en-pp3300-codec-state {
pins = "gpio105";
function = "gpio";
bias-disable;
drive-strength = <2>;
};
- en_pp3300_dx_edp: en-pp3300-dx-edp-pins {
+ en_pp3300_dx_edp: en-pp3300-dx-edp-state {
pins = "gpio80";
function = "gpio";
bias-disable;
drive-strength = <2>;
};
- fp_rst_l: fp-rst-l-pins {
+ fp_rst_l: fp-rst-l-state {
pins = "gpio78";
function = "gpio";
bias-disable;
drive-strength = <2>;
};
- fp_to_ap_irq_l: fp-to-ap-irq-l-pins {
+ fp_to_ap_irq_l: fp-to-ap-irq-l-state {
pins = "gpio61";
function = "gpio";
/* Has external pullup */
bias-disable;
};
- fpmcu_boot0: fpmcu-boot0-pins {
+ fpmcu_boot0: fpmcu-boot0-state {
pins = "gpio68";
function = "gpio";
bias-disable;
};
- gsc_ap_int_odl: gsc-ap-int-odl-pins {
+ gsc_ap_int_odl: gsc-ap-int-odl-state {
pins = "gpio104";
function = "gpio";
bias-pull-up;
};
- hp_irq: hp-irq-pins {
+ hp_irq: hp-irq-state {
pins = "gpio101";
function = "gpio";
bias-pull-up;
};
- hub_en: hub-en-pins {
+ hub_en: hub-en-state {
pins = "gpio157";
function = "gpio";
bias-disable;
drive-strength = <2>;
};
- pe_wake_odl: pe-wake-odl-pins {
+ pe_wake_odl: pe-wake-odl-state {
pins = "gpio3";
function = "gpio";
/* Has external pull */
@@ -834,45 +859,45 @@ ap_ec_spi: &spi10 {
};
/* For ap_spi_fp */
- qup_spi9_cs_gpio_init_high: qup-spi9-cs-gpio-init-high-pins {
+ qup_spi9_cs_gpio_init_high: qup-spi9-cs-gpio-init-high-state {
pins = "gpio39";
function = "gpio";
output-high;
};
/* For ap_ec_spi */
- qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-pins {
+ qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-state {
pins = "gpio43";
function = "gpio";
output-high;
};
- sar0_irq_odl: sar0-irq-odl-pins {
+ sar0_irq_odl: sar0-irq-odl-state {
pins = "gpio141";
function = "gpio";
bias-pull-up;
};
- sar1_irq_odl: sar1-irq-odl-pins {
+ sar1_irq_odl: sar1-irq-odl-state {
pins = "gpio140";
function = "gpio";
bias-pull-up;
};
- sd_cd_odl: sd-cd-odl-pins {
+ sd_cd_odl: sd-cd-odl-state {
pins = "gpio91";
function = "gpio";
bias-pull-up;
};
- ssd_en: ssd-en-pins {
+ ssd_en: ssd-en-state {
pins = "gpio51";
function = "gpio";
bias-disable;
drive-strength = <2>;
};
- ssd_rst_l: ssd-rst-l-pins {
+ ssd_rst_l: ssd-rst-l-state {
pins = "gpio2";
function = "gpio";
bias-disable;
@@ -880,14 +905,14 @@ ap_ec_spi: &spi10 {
output-low;
};
- tp_int_odl: tp-int-odl-pins {
+ tp_int_odl: tp-int-odl-state {
pins = "gpio7";
function = "gpio";
/* Has external pullup */
bias-disable;
};
- wf_cam_en: wf-cam-en-pins {
+ wf_cam_en: wf-cam-en-state {
pins = "gpio119";
function = "gpio";
/* Has external pulldown */
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi
index 7f5143e9bb80..3cfeb118d379 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi
@@ -79,27 +79,29 @@ ap_h1_spi: &spi14 {
};
&tlmm {
- ap_ec_int_l: ap-ec-int-l-pins {
+ ap_ec_int_l: ap-ec-int-l-state {
pins = "gpio18";
function = "gpio";
input-enable;
bias-pull-up;
};
- h1_ap_int_odl: h1-ap-int-odl-pins {
+ h1_ap_int_odl: h1-ap-int-odl-state {
pins = "gpio104";
function = "gpio";
input-enable;
bias-pull-up;
};
- qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-pins {
+ qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-state {
pins = "gpio43";
+ function = "gpio";
output-high;
};
- qup_spi14_cs_gpio_init_high: qup-spi14-cs-gpio-init-high-pins {
+ qup_spi14_cs_gpio_init_high: qup-spi14-cs-gpio-init-high-state {
pins = "gpio59";
+ function = "gpio";
output-high;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
index 7559164cdda0..ba64316b4427 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -10,7 +10,6 @@
#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
#include "sc7280-idp.dtsi"
#include "pmr735a.dtsi"
-#include "sc7280-herobrine-lte-sku.dtsi"
/ {
model = "Qualcomm Technologies, Inc. sc7280 IDP SKU1 platform";
@@ -61,11 +60,6 @@
vddio-supply = <&vreg_l19b_1p8>;
};
-&ipa {
- status = "okay";
- modem-init;
-};
-
&pmk8350_rtc {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index cd432a2856a7..f7efb9966afd 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -13,6 +13,7 @@
#include "pmk8350.dtsi"
#include "sc7280-chrome-common.dtsi"
+#include "sc7280-herobrine-lte-sku.dtsi"
/ {
aliases {
@@ -34,7 +35,7 @@
pinctrl-0 = <&wcd_reset_n>;
pinctrl-1 = <&wcd_reset_n_sleep>;
- reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
qcom,rx-device = <&wcd_rx>;
qcom,tx-device = <&wcd_tx>;
@@ -522,6 +523,12 @@
vdda-pll-supply = <&vreg_l10c_0p8>;
vdda33-supply = <&vreg_l2b_3p0>;
vdda18-supply = <&vreg_l1c_1p8>;
+ qcom,hs-rise-fall-time-bp = <0>;
+ qcom,squelch-detector-bp = <(-2090)>;
+ qcom,hs-disconnect-bp = <1743>;
+ qcom,hs-amplitude-bp = <1780>;
+ qcom,hs-crossover-voltage-microvolt = <(-31000)>;
+ qcom,hs-output-impedance-micro-ohms = <2600000>;
};
&usb_1_qmpphy {
@@ -569,10 +576,6 @@
bias-disable;
};
-&lpass_dmic01_clk_sleep {
- drive-strength = <2>;
-};
-
&lpass_dmic01_data {
bias-pull-down;
};
@@ -582,10 +585,6 @@
bias-disable;
};
-&lpass_dmic23_clk_sleep {
- drive-strength = <2>;
-};
-
&lpass_dmic23_data {
bias-pull-down;
};
@@ -596,30 +595,18 @@
bias-disable;
};
-&lpass_rx_swr_clk_sleep {
- bias-pull-down;
-};
-
&lpass_rx_swr_data {
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
-&lpass_rx_swr_data_sleep {
- bias-pull-down;
-};
-
&lpass_tx_swr_clk {
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
-&lpass_tx_swr_clk_sleep {
- bias-pull-down;
-};
-
&lpass_tx_swr_data {
drive-strength = <2>;
slew-rate = <1>;
@@ -747,24 +734,24 @@
};
&tlmm {
- amp_en: amp-en {
+ amp_en: amp-en-state {
pins = "gpio63";
bias-pull-down;
drive-strength = <2>;
};
- bt_en: bt-en-pins {
+ bt_en: bt-en-state {
pins = "gpio85";
function = "gpio";
output-low;
bias-disable;
};
- nvme_pwren: nvme-pwren-pins {
+ nvme_pwren: nvme-pwren-state {
function = "gpio";
};
- pcie1_reset_n: pcie1-reset-n-pins {
+ pcie1_reset_n: pcie1-reset-n-state {
pins = "gpio2";
function = "gpio";
@@ -773,7 +760,7 @@
bias-disable;
};
- pcie1_wake_n: pcie1-wake-n-pins {
+ pcie1_wake_n: pcie1-wake-n-state {
pins = "gpio3";
function = "gpio";
@@ -781,7 +768,7 @@
bias-pull-up;
};
- qup_uart7_sleep_cts: qup-uart7-sleep-cts-pins {
+ qup_uart7_sleep_cts: qup-uart7-sleep-cts-state {
pins = "gpio28";
function = "gpio";
/*
@@ -794,7 +781,7 @@
bias-bus-hold;
};
- qup_uart7_sleep_rts: qup-uart7-sleep-rts-pins {
+ qup_uart7_sleep_rts: qup-uart7-sleep-rts-state {
pins = "gpio29";
function = "gpio";
/*
@@ -806,7 +793,7 @@
bias-pull-down;
};
- qup_uart7_sleep_tx: qup-uart7-sleep-tx-pins {
+ qup_uart7_sleep_tx: qup-uart7-sleep-tx-state {
pins = "gpio30";
function = "gpio";
/*
@@ -816,7 +803,7 @@
bias-pull-up;
};
- qup_uart7_sleep_rx: qup-uart7-sleep-rx-pins {
+ qup_uart7_sleep_rx: qup-uart7-sleep-rx-state {
pins = "gpio31";
function = "gpio";
/*
@@ -827,25 +814,25 @@
bias-pull-up;
};
- sd_cd: sd-cd-pins {
+ sd_cd: sd-cd-state {
pins = "gpio91";
function = "gpio";
bias-pull-up;
};
- sw_ctrl: sw-ctrl-pins {
+ sw_ctrl: sw-ctrl-state {
pins = "gpio86";
function = "gpio";
bias-pull-down;
};
- wcd_reset_n: wcd-reset-n {
+ wcd_reset_n: wcd-reset-n-state {
pins = "gpio83";
function = "gpio";
drive-strength = <8>;
};
- wcd_reset_n_sleep: wcd-reset-n-sleep {
+ wcd_reset_n_sleep: wcd-reset-n-sleep-state {
pins = "gpio83";
function = "gpio";
drive-strength = <8>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
index 4b8c676b0bb1..df49564ae6dc 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
@@ -37,7 +37,7 @@
pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>;
pinctrl-1 = <&wcd_reset_n_sleep>, <&us_euro_hs_sel>;
- reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
us-euro-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
qcom,rx-device = <&wcd_rx>;
@@ -595,7 +595,7 @@ mos_bt_uart: &uart7 {
};
&tlmm {
- mos_bt_en: mos-bt-en-pins {
+ mos_bt_en: mos-bt-en-state {
pins = "gpio85";
function = "gpio";
drive-strength = <2>;
@@ -603,7 +603,7 @@ mos_bt_uart: &uart7 {
};
/* For mos_bt_uart */
- qup_uart7_sleep_cts: qup-uart7-sleep-cts-pins {
+ qup_uart7_sleep_cts: qup-uart7-sleep-cts-state {
pins = "gpio28";
function = "gpio";
/*
@@ -617,7 +617,7 @@ mos_bt_uart: &uart7 {
};
/* For mos_bt_uart */
- qup_uart7_sleep_rts: qup-uart7-sleep-rts-pins {
+ qup_uart7_sleep_rts: qup-uart7-sleep-rts-state {
pins = "gpio29";
function = "gpio";
/*
@@ -630,7 +630,7 @@ mos_bt_uart: &uart7 {
};
/* For mos_bt_uart */
- qup_uart7_sleep_rx: qup-uart7-sleep-rx-pins {
+ qup_uart7_sleep_rx: qup-uart7-sleep-rx-state {
pins = "gpio31";
function = "gpio";
/*
@@ -642,7 +642,7 @@ mos_bt_uart: &uart7 {
};
/* For mos_bt_uart */
- qup_uart7_sleep_tx: qup-uart7-sleep-tx-pins {
+ qup_uart7_sleep_tx: qup-uart7-sleep-tx-state {
pins = "gpio30";
function = "gpio";
/*
@@ -652,32 +652,32 @@ mos_bt_uart: &uart7 {
bias-pull-up;
};
- ts_int_conn: ts-int-conn-pins {
+ ts_int_conn: ts-int-conn-state {
pins = "gpio55";
function = "gpio";
bias-pull-up;
};
- ts_rst_conn: ts-rst-conn-pins {
+ ts_rst_conn: ts-rst-conn-state {
pins = "gpio54";
function = "gpio";
drive-strength = <2>;
};
- us_euro_hs_sel: us-euro-hs-sel {
+ us_euro_hs_sel: us-euro-hs-sel-state {
pins = "gpio81";
function = "gpio";
bias-pull-down;
drive-strength = <2>;
};
- wcd_reset_n: wcd-reset-n {
+ wcd_reset_n: wcd-reset-n-state {
pins = "gpio83";
function = "gpio";
drive-strength = <8>;
};
- wcd_reset_n_sleep: wcd-reset-n-sleep {
+ wcd_reset_n_sleep: wcd-reset-n-sleep-state {
pins = "gpio83";
function = "gpio";
drive-strength = <8>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 4cdc88d33944..0adf13399e64 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -752,6 +752,17 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ wlan_smp2p_out: wlan-ap-to-wpss {
+ qcom,entry-name = "wlan";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ wlan_smp2p_in: wlan-wpss-to-ap {
+ qcom,entry-name = "wlan";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
};
pmu {
@@ -920,7 +931,7 @@
gpi_dma0: dma-controller@900000 {
#dma-cells = <3>;
- compatible = "qcom,sc7280-gpi-dma";
+ compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0 0x00900000 0 0x60000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
@@ -967,6 +978,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1025,6 +1038,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1083,6 +1098,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1141,6 +1158,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1199,6 +1218,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1257,6 +1278,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1315,6 +1338,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
<&gpi_dma0 1 6 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1373,6 +1398,8 @@
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
<&gpi_dma0 1 7 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1419,7 +1446,7 @@
gpi_dma1: dma-controller@a00000 {
#dma-cells = <3>;
- compatible = "qcom,sc7280-gpi-dma";
+ compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0 0x00a00000 0 0x60000>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
@@ -1466,6 +1493,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1524,6 +1553,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1582,6 +1613,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1640,6 +1673,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1698,6 +1733,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1756,6 +1793,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
<&gpi_dma1 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1814,6 +1853,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
<&gpi_dma1 1 6 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -1872,6 +1913,8 @@
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7280_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
<&gpi_dma1 1 7 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
@@ -2004,6 +2047,8 @@
qcom,rproc = <&remoteproc_wpss>;
memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
status = "disabled";
+ qcom,smem-states = <&wlan_smp2p_out 0>;
+ qcom,smem-state-names = "wlan-smp2p-out";
};
pcie1: pci@1c08000 {
@@ -2285,7 +2330,6 @@
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
- qcom,port-offset = <1>;
#sound-dai-cells = <1>;
#address-cells = <2>;
@@ -2434,84 +2478,42 @@
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 15>;
- #clock-cells = <1>;
-
- lpass_dmic01_clk: dmic01-clk {
- pins = "gpio6";
- function = "dmic1_clk";
- };
-
- lpass_dmic01_clk_sleep: dmic01-clk-sleep {
+ lpass_dmic01_clk: dmic01-clk-state {
pins = "gpio6";
function = "dmic1_clk";
};
- lpass_dmic01_data: dmic01-data {
+ lpass_dmic01_data: dmic01-data-state {
pins = "gpio7";
function = "dmic1_data";
};
- lpass_dmic01_data_sleep: dmic01-data-sleep {
- pins = "gpio7";
- function = "dmic1_data";
- };
-
- lpass_dmic23_clk: dmic23-clk {
- pins = "gpio8";
- function = "dmic2_clk";
- };
-
- lpass_dmic23_clk_sleep: dmic23-clk-sleep {
+ lpass_dmic23_clk: dmic23-clk-state {
pins = "gpio8";
function = "dmic2_clk";
};
- lpass_dmic23_data: dmic23-data {
+ lpass_dmic23_data: dmic23-data-state {
pins = "gpio9";
function = "dmic2_data";
};
- lpass_dmic23_data_sleep: dmic23-data-sleep {
- pins = "gpio9";
- function = "dmic2_data";
- };
-
- lpass_rx_swr_clk: rx-swr-clk {
+ lpass_rx_swr_clk: rx-swr-clk-state {
pins = "gpio3";
function = "swr_rx_clk";
};
- lpass_rx_swr_clk_sleep: rx-swr-clk-sleep {
- pins = "gpio3";
- function = "swr_rx_clk";
- };
-
- lpass_rx_swr_data: rx-swr-data {
+ lpass_rx_swr_data: rx-swr-data-state {
pins = "gpio4", "gpio5";
function = "swr_rx_data";
};
- lpass_rx_swr_data_sleep: rx-swr-data-sleep {
- pins = "gpio4", "gpio5";
- function = "swr_rx_data";
- };
-
- lpass_tx_swr_clk: tx-swr-clk {
- pins = "gpio0";
- function = "swr_tx_clk";
- };
-
- lpass_tx_swr_clk_sleep: tx-swr-clk-sleep {
+ lpass_tx_swr_clk: tx-swr-clk-state {
pins = "gpio0";
function = "swr_tx_clk";
};
- lpass_tx_swr_data: tx-swr-data {
- pins = "gpio1", "gpio2", "gpio14";
- function = "swr_tx_data";
- };
-
- lpass_tx_swr_data_sleep: tx-swr-data-sleep {
+ lpass_tx_swr_data: tx-swr-data-state {
pins = "gpio1", "gpio2", "gpio14";
function = "swr_tx_data";
};
@@ -3924,11 +3926,13 @@
"iface",
"bus";
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
+
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SC7280_CX>;
phys = <&mdss_dsi_phy>;
- phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
@@ -4259,791 +4263,791 @@
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
- dp_hot_plug_det: dp-hot-plug-det-pins {
+ dp_hot_plug_det: dp-hot-plug-det-state {
pins = "gpio47";
function = "dp_hot";
};
- edp_hot_plug_det: edp-hot-plug-det-pins {
+ edp_hot_plug_det: edp-hot-plug-det-state {
pins = "gpio60";
function = "edp_hot";
};
- mi2s0_data0: mi2s0-data0-pins {
+ mi2s0_data0: mi2s0-data0-state {
pins = "gpio98";
function = "mi2s0_data0";
};
- mi2s0_data1: mi2s0-data1-pins {
+ mi2s0_data1: mi2s0-data1-state {
pins = "gpio99";
function = "mi2s0_data1";
};
- mi2s0_mclk: mi2s0-mclk-pins {
+ mi2s0_mclk: mi2s0-mclk-state {
pins = "gpio96";
function = "pri_mi2s";
};
- mi2s0_sclk: mi2s0-sclk-pins {
+ mi2s0_sclk: mi2s0-sclk-state {
pins = "gpio97";
function = "mi2s0_sck";
};
- mi2s0_ws: mi2s0-ws-pins {
+ mi2s0_ws: mi2s0-ws-state {
pins = "gpio100";
function = "mi2s0_ws";
};
- mi2s1_data0: mi2s1-data0-pins {
+ mi2s1_data0: mi2s1-data0-state {
pins = "gpio107";
function = "mi2s1_data0";
};
- mi2s1_sclk: mi2s1-sclk-pins {
+ mi2s1_sclk: mi2s1-sclk-state {
pins = "gpio106";
function = "mi2s1_sck";
};
- mi2s1_ws: mi2s1-ws-pins {
+ mi2s1_ws: mi2s1-ws-state {
pins = "gpio108";
function = "mi2s1_ws";
};
- pcie1_clkreq_n: pcie1-clkreq-n-pins {
+ pcie1_clkreq_n: pcie1-clkreq-n-state {
pins = "gpio79";
function = "pcie1_clkreqn";
};
- qspi_clk: qspi-clk-pins {
+ qspi_clk: qspi-clk-state {
pins = "gpio14";
function = "qspi_clk";
};
- qspi_cs0: qspi-cs0-pins {
+ qspi_cs0: qspi-cs0-state {
pins = "gpio15";
function = "qspi_cs";
};
- qspi_cs1: qspi-cs1-pins {
+ qspi_cs1: qspi-cs1-state {
pins = "gpio19";
function = "qspi_cs";
};
- qspi_data01: qspi-data01-pins {
+ qspi_data01: qspi-data01-state {
pins = "gpio12", "gpio13";
function = "qspi_data";
};
- qspi_data12: qspi-data12-pins {
+ qspi_data12: qspi-data12-state {
pins = "gpio16", "gpio17";
function = "qspi_data";
};
- qup_i2c0_data_clk: qup-i2c0-data-clk-pins {
+ qup_i2c0_data_clk: qup-i2c0-data-clk-state {
pins = "gpio0", "gpio1";
function = "qup00";
};
- qup_i2c1_data_clk: qup-i2c1-data-clk-pins {
+ qup_i2c1_data_clk: qup-i2c1-data-clk-state {
pins = "gpio4", "gpio5";
function = "qup01";
};
- qup_i2c2_data_clk: qup-i2c2-data-clk-pins {
+ qup_i2c2_data_clk: qup-i2c2-data-clk-state {
pins = "gpio8", "gpio9";
function = "qup02";
};
- qup_i2c3_data_clk: qup-i2c3-data-clk-pins {
+ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
pins = "gpio12", "gpio13";
function = "qup03";
};
- qup_i2c4_data_clk: qup-i2c4-data-clk-pins {
+ qup_i2c4_data_clk: qup-i2c4-data-clk-state {
pins = "gpio16", "gpio17";
function = "qup04";
};
- qup_i2c5_data_clk: qup-i2c5-data-clk-pins {
+ qup_i2c5_data_clk: qup-i2c5-data-clk-state {
pins = "gpio20", "gpio21";
function = "qup05";
};
- qup_i2c6_data_clk: qup-i2c6-data-clk-pins {
+ qup_i2c6_data_clk: qup-i2c6-data-clk-state {
pins = "gpio24", "gpio25";
function = "qup06";
};
- qup_i2c7_data_clk: qup-i2c7-data-clk-pins {
+ qup_i2c7_data_clk: qup-i2c7-data-clk-state {
pins = "gpio28", "gpio29";
function = "qup07";
};
- qup_i2c8_data_clk: qup-i2c8-data-clk-pins {
+ qup_i2c8_data_clk: qup-i2c8-data-clk-state {
pins = "gpio32", "gpio33";
function = "qup10";
};
- qup_i2c9_data_clk: qup-i2c9-data-clk-pins {
+ qup_i2c9_data_clk: qup-i2c9-data-clk-state {
pins = "gpio36", "gpio37";
function = "qup11";
};
- qup_i2c10_data_clk: qup-i2c10-data-clk-pins {
+ qup_i2c10_data_clk: qup-i2c10-data-clk-state {
pins = "gpio40", "gpio41";
function = "qup12";
};
- qup_i2c11_data_clk: qup-i2c11-data-clk-pins {
+ qup_i2c11_data_clk: qup-i2c11-data-clk-state {
pins = "gpio44", "gpio45";
function = "qup13";
};
- qup_i2c12_data_clk: qup-i2c12-data-clk-pins {
+ qup_i2c12_data_clk: qup-i2c12-data-clk-state {
pins = "gpio48", "gpio49";
function = "qup14";
};
- qup_i2c13_data_clk: qup-i2c13-data-clk-pins {
+ qup_i2c13_data_clk: qup-i2c13-data-clk-state {
pins = "gpio52", "gpio53";
function = "qup15";
};
- qup_i2c14_data_clk: qup-i2c14-data-clk-pins {
+ qup_i2c14_data_clk: qup-i2c14-data-clk-state {
pins = "gpio56", "gpio57";
function = "qup16";
};
- qup_i2c15_data_clk: qup-i2c15-data-clk-pins {
+ qup_i2c15_data_clk: qup-i2c15-data-clk-state {
pins = "gpio60", "gpio61";
function = "qup17";
};
- qup_spi0_data_clk: qup-spi0-data-clk-pins {
+ qup_spi0_data_clk: qup-spi0-data-clk-state {
pins = "gpio0", "gpio1", "gpio2";
function = "qup00";
};
- qup_spi0_cs: qup-spi0-cs-pins {
+ qup_spi0_cs: qup-spi0-cs-state {
pins = "gpio3";
function = "qup00";
};
- qup_spi0_cs_gpio: qup-spi0-cs-gpio-pins {
+ qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
pins = "gpio3";
function = "gpio";
};
- qup_spi1_data_clk: qup-spi1-data-clk-pins {
+ qup_spi1_data_clk: qup-spi1-data-clk-state {
pins = "gpio4", "gpio5", "gpio6";
function = "qup01";
};
- qup_spi1_cs: qup-spi1-cs-pins {
+ qup_spi1_cs: qup-spi1-cs-state {
pins = "gpio7";
function = "qup01";
};
- qup_spi1_cs_gpio: qup-spi1-cs-gpio-pins {
+ qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
pins = "gpio7";
function = "gpio";
};
- qup_spi2_data_clk: qup-spi2-data-clk-pins {
+ qup_spi2_data_clk: qup-spi2-data-clk-state {
pins = "gpio8", "gpio9", "gpio10";
function = "qup02";
};
- qup_spi2_cs: qup-spi2-cs-pins {
+ qup_spi2_cs: qup-spi2-cs-state {
pins = "gpio11";
function = "qup02";
};
- qup_spi2_cs_gpio: qup-spi2-cs-gpio-pins {
+ qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
pins = "gpio11";
function = "gpio";
};
- qup_spi3_data_clk: qup-spi3-data-clk-pins {
+ qup_spi3_data_clk: qup-spi3-data-clk-state {
pins = "gpio12", "gpio13", "gpio14";
function = "qup03";
};
- qup_spi3_cs: qup-spi3-cs-pins {
+ qup_spi3_cs: qup-spi3-cs-state {
pins = "gpio15";
function = "qup03";
};
- qup_spi3_cs_gpio: qup-spi3-cs-gpio-pins {
+ qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
pins = "gpio15";
function = "gpio";
};
- qup_spi4_data_clk: qup-spi4-data-clk-pins {
+ qup_spi4_data_clk: qup-spi4-data-clk-state {
pins = "gpio16", "gpio17", "gpio18";
function = "qup04";
};
- qup_spi4_cs: qup-spi4-cs-pins {
+ qup_spi4_cs: qup-spi4-cs-state {
pins = "gpio19";
function = "qup04";
};
- qup_spi4_cs_gpio: qup-spi4-cs-gpio-pins {
+ qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
pins = "gpio19";
function = "gpio";
};
- qup_spi5_data_clk: qup-spi5-data-clk-pins {
+ qup_spi5_data_clk: qup-spi5-data-clk-state {
pins = "gpio20", "gpio21", "gpio22";
function = "qup05";
};
- qup_spi5_cs: qup-spi5-cs-pins {
+ qup_spi5_cs: qup-spi5-cs-state {
pins = "gpio23";
function = "qup05";
};
- qup_spi5_cs_gpio: qup-spi5-cs-gpio-pins {
+ qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
pins = "gpio23";
function = "gpio";
};
- qup_spi6_data_clk: qup-spi6-data-clk-pins {
+ qup_spi6_data_clk: qup-spi6-data-clk-state {
pins = "gpio24", "gpio25", "gpio26";
function = "qup06";
};
- qup_spi6_cs: qup-spi6-cs-pins {
+ qup_spi6_cs: qup-spi6-cs-state {
pins = "gpio27";
function = "qup06";
};
- qup_spi6_cs_gpio: qup-spi6-cs-gpio-pins {
+ qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
pins = "gpio27";
function = "gpio";
};
- qup_spi7_data_clk: qup-spi7-data-clk-pins {
+ qup_spi7_data_clk: qup-spi7-data-clk-state {
pins = "gpio28", "gpio29", "gpio30";
function = "qup07";
};
- qup_spi7_cs: qup-spi7-cs-pins {
+ qup_spi7_cs: qup-spi7-cs-state {
pins = "gpio31";
function = "qup07";
};
- qup_spi7_cs_gpio: qup-spi7-cs-gpio-pins {
+ qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
pins = "gpio31";
function = "gpio";
};
- qup_spi8_data_clk: qup-spi8-data-clk-pins {
+ qup_spi8_data_clk: qup-spi8-data-clk-state {
pins = "gpio32", "gpio33", "gpio34";
function = "qup10";
};
- qup_spi8_cs: qup-spi8-cs-pins {
+ qup_spi8_cs: qup-spi8-cs-state {
pins = "gpio35";
function = "qup10";
};
- qup_spi8_cs_gpio: qup-spi8-cs-gpio-pins {
+ qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
pins = "gpio35";
function = "gpio";
};
- qup_spi9_data_clk: qup-spi9-data-clk-pins {
+ qup_spi9_data_clk: qup-spi9-data-clk-state {
pins = "gpio36", "gpio37", "gpio38";
function = "qup11";
};
- qup_spi9_cs: qup-spi9-cs-pins {
+ qup_spi9_cs: qup-spi9-cs-state {
pins = "gpio39";
function = "qup11";
};
- qup_spi9_cs_gpio: qup-spi9-cs-gpio-pins {
+ qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
pins = "gpio39";
function = "gpio";
};
- qup_spi10_data_clk: qup-spi10-data-clk-pins {
+ qup_spi10_data_clk: qup-spi10-data-clk-state {
pins = "gpio40", "gpio41", "gpio42";
function = "qup12";
};
- qup_spi10_cs: qup-spi10-cs-pins {
+ qup_spi10_cs: qup-spi10-cs-state {
pins = "gpio43";
function = "qup12";
};
- qup_spi10_cs_gpio: qup-spi10-cs-gpio-pins {
+ qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
pins = "gpio43";
function = "gpio";
};
- qup_spi11_data_clk: qup-spi11-data-clk-pins {
+ qup_spi11_data_clk: qup-spi11-data-clk-state {
pins = "gpio44", "gpio45", "gpio46";
function = "qup13";
};
- qup_spi11_cs: qup-spi11-cs-pins {
+ qup_spi11_cs: qup-spi11-cs-state {
pins = "gpio47";
function = "qup13";
};
- qup_spi11_cs_gpio: qup-spi11-cs-gpio-pins {
+ qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
pins = "gpio47";
function = "gpio";
};
- qup_spi12_data_clk: qup-spi12-data-clk-pins {
+ qup_spi12_data_clk: qup-spi12-data-clk-state {
pins = "gpio48", "gpio49", "gpio50";
function = "qup14";
};
- qup_spi12_cs: qup-spi12-cs-pins {
+ qup_spi12_cs: qup-spi12-cs-state {
pins = "gpio51";
function = "qup14";
};
- qup_spi12_cs_gpio: qup-spi12-cs-gpio-pins {
+ qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
pins = "gpio51";
function = "gpio";
};
- qup_spi13_data_clk: qup-spi13-data-clk-pins {
+ qup_spi13_data_clk: qup-spi13-data-clk-state {
pins = "gpio52", "gpio53", "gpio54";
function = "qup15";
};
- qup_spi13_cs: qup-spi13-cs-pins {
+ qup_spi13_cs: qup-spi13-cs-state {
pins = "gpio55";
function = "qup15";
};
- qup_spi13_cs_gpio: qup-spi13-cs-gpio-pins {
+ qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
pins = "gpio55";
function = "gpio";
};
- qup_spi14_data_clk: qup-spi14-data-clk-pins {
+ qup_spi14_data_clk: qup-spi14-data-clk-state {
pins = "gpio56", "gpio57", "gpio58";
function = "qup16";
};
- qup_spi14_cs: qup-spi14-cs-pins {
+ qup_spi14_cs: qup-spi14-cs-state {
pins = "gpio59";
function = "qup16";
};
- qup_spi14_cs_gpio: qup-spi14-cs-gpio-pins {
+ qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
pins = "gpio59";
function = "gpio";
};
- qup_spi15_data_clk: qup-spi15-data-clk-pins {
+ qup_spi15_data_clk: qup-spi15-data-clk-state {
pins = "gpio60", "gpio61", "gpio62";
function = "qup17";
};
- qup_spi15_cs: qup-spi15-cs-pins {
+ qup_spi15_cs: qup-spi15-cs-state {
pins = "gpio63";
function = "qup17";
};
- qup_spi15_cs_gpio: qup-spi15-cs-gpio-pins {
+ qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
pins = "gpio63";
function = "gpio";
};
- qup_uart0_cts: qup-uart0-cts-pins {
+ qup_uart0_cts: qup-uart0-cts-state {
pins = "gpio0";
function = "qup00";
};
- qup_uart0_rts: qup-uart0-rts-pins {
+ qup_uart0_rts: qup-uart0-rts-state {
pins = "gpio1";
function = "qup00";
};
- qup_uart0_tx: qup-uart0-tx-pins {
+ qup_uart0_tx: qup-uart0-tx-state {
pins = "gpio2";
function = "qup00";
};
- qup_uart0_rx: qup-uart0-rx-pins {
+ qup_uart0_rx: qup-uart0-rx-state {
pins = "gpio3";
function = "qup00";
};
- qup_uart1_cts: qup-uart1-cts-pins {
+ qup_uart1_cts: qup-uart1-cts-state {
pins = "gpio4";
function = "qup01";
};
- qup_uart1_rts: qup-uart1-rts-pins {
+ qup_uart1_rts: qup-uart1-rts-state {
pins = "gpio5";
function = "qup01";
};
- qup_uart1_tx: qup-uart1-tx-pins {
+ qup_uart1_tx: qup-uart1-tx-state {
pins = "gpio6";
function = "qup01";
};
- qup_uart1_rx: qup-uart1-rx-pins {
+ qup_uart1_rx: qup-uart1-rx-state {
pins = "gpio7";
function = "qup01";
};
- qup_uart2_cts: qup-uart2-cts-pins {
+ qup_uart2_cts: qup-uart2-cts-state {
pins = "gpio8";
function = "qup02";
};
- qup_uart2_rts: qup-uart2-rts-pins {
+ qup_uart2_rts: qup-uart2-rts-state {
pins = "gpio9";
function = "qup02";
};
- qup_uart2_tx: qup-uart2-tx-pins {
+ qup_uart2_tx: qup-uart2-tx-state {
pins = "gpio10";
function = "qup02";
};
- qup_uart2_rx: qup-uart2-rx-pins {
+ qup_uart2_rx: qup-uart2-rx-state {
pins = "gpio11";
function = "qup02";
};
- qup_uart3_cts: qup-uart3-cts-pins {
+ qup_uart3_cts: qup-uart3-cts-state {
pins = "gpio12";
function = "qup03";
};
- qup_uart3_rts: qup-uart3-rts-pins {
+ qup_uart3_rts: qup-uart3-rts-state {
pins = "gpio13";
function = "qup03";
};
- qup_uart3_tx: qup-uart3-tx-pins {
+ qup_uart3_tx: qup-uart3-tx-state {
pins = "gpio14";
function = "qup03";
};
- qup_uart3_rx: qup-uart3-rx-pins {
+ qup_uart3_rx: qup-uart3-rx-state {
pins = "gpio15";
function = "qup03";
};
- qup_uart4_cts: qup-uart4-cts-pins {
+ qup_uart4_cts: qup-uart4-cts-state {
pins = "gpio16";
function = "qup04";
};
- qup_uart4_rts: qup-uart4-rts-pins {
+ qup_uart4_rts: qup-uart4-rts-state {
pins = "gpio17";
function = "qup04";
};
- qup_uart4_tx: qup-uart4-tx-pins {
+ qup_uart4_tx: qup-uart4-tx-state {
pins = "gpio18";
function = "qup04";
};
- qup_uart4_rx: qup-uart4-rx-pins {
+ qup_uart4_rx: qup-uart4-rx-state {
pins = "gpio19";
function = "qup04";
};
- qup_uart5_cts: qup-uart5-cts-pins {
+ qup_uart5_cts: qup-uart5-cts-state {
pins = "gpio20";
function = "qup05";
};
- qup_uart5_rts: qup-uart5-rts-pins {
+ qup_uart5_rts: qup-uart5-rts-state {
pins = "gpio21";
function = "qup05";
};
- qup_uart5_tx: qup-uart5-tx-pins {
+ qup_uart5_tx: qup-uart5-tx-state {
pins = "gpio22";
function = "qup05";
};
- qup_uart5_rx: qup-uart5-rx-pins {
+ qup_uart5_rx: qup-uart5-rx-state {
pins = "gpio23";
function = "qup05";
};
- qup_uart6_cts: qup-uart6-cts-pins {
+ qup_uart6_cts: qup-uart6-cts-state {
pins = "gpio24";
function = "qup06";
};
- qup_uart6_rts: qup-uart6-rts-pins {
+ qup_uart6_rts: qup-uart6-rts-state {
pins = "gpio25";
function = "qup06";
};
- qup_uart6_tx: qup-uart6-tx-pins {
+ qup_uart6_tx: qup-uart6-tx-state {
pins = "gpio26";
function = "qup06";
};
- qup_uart6_rx: qup-uart6-rx-pins {
+ qup_uart6_rx: qup-uart6-rx-state {
pins = "gpio27";
function = "qup06";
};
- qup_uart7_cts: qup-uart7-cts-pins {
+ qup_uart7_cts: qup-uart7-cts-state {
pins = "gpio28";
function = "qup07";
};
- qup_uart7_rts: qup-uart7-rts-pins {
+ qup_uart7_rts: qup-uart7-rts-state {
pins = "gpio29";
function = "qup07";
};
- qup_uart7_tx: qup-uart7-tx-pins {
+ qup_uart7_tx: qup-uart7-tx-state {
pins = "gpio30";
function = "qup07";
};
- qup_uart7_rx: qup-uart7-rx-pins {
+ qup_uart7_rx: qup-uart7-rx-state {
pins = "gpio31";
function = "qup07";
};
- qup_uart8_cts: qup-uart8-cts-pins {
+ qup_uart8_cts: qup-uart8-cts-state {
pins = "gpio32";
function = "qup10";
};
- qup_uart8_rts: qup-uart8-rts-pins {
+ qup_uart8_rts: qup-uart8-rts-state {
pins = "gpio33";
function = "qup10";
};
- qup_uart8_tx: qup-uart8-tx-pins {
+ qup_uart8_tx: qup-uart8-tx-state {
pins = "gpio34";
function = "qup10";
};
- qup_uart8_rx: qup-uart8-rx-pins {
+ qup_uart8_rx: qup-uart8-rx-state {
pins = "gpio35";
function = "qup10";
};
- qup_uart9_cts: qup-uart9-cts-pins {
+ qup_uart9_cts: qup-uart9-cts-state {
pins = "gpio36";
function = "qup11";
};
- qup_uart9_rts: qup-uart9-rts-pins {
+ qup_uart9_rts: qup-uart9-rts-state {
pins = "gpio37";
function = "qup11";
};
- qup_uart9_tx: qup-uart9-tx-pins {
+ qup_uart9_tx: qup-uart9-tx-state {
pins = "gpio38";
function = "qup11";
};
- qup_uart9_rx: qup-uart9-rx-pins {
+ qup_uart9_rx: qup-uart9-rx-state {
pins = "gpio39";
function = "qup11";
};
- qup_uart10_cts: qup-uart10-cts-pins {
+ qup_uart10_cts: qup-uart10-cts-state {
pins = "gpio40";
function = "qup12";
};
- qup_uart10_rts: qup-uart10-rts-pins {
+ qup_uart10_rts: qup-uart10-rts-state {
pins = "gpio41";
function = "qup12";
};
- qup_uart10_tx: qup-uart10-tx-pins {
+ qup_uart10_tx: qup-uart10-tx-state {
pins = "gpio42";
function = "qup12";
};
- qup_uart10_rx: qup-uart10-rx-pins {
+ qup_uart10_rx: qup-uart10-rx-state {
pins = "gpio43";
function = "qup12";
};
- qup_uart11_cts: qup-uart11-cts-pins {
+ qup_uart11_cts: qup-uart11-cts-state {
pins = "gpio44";
function = "qup13";
};
- qup_uart11_rts: qup-uart11-rts-pins {
+ qup_uart11_rts: qup-uart11-rts-state {
pins = "gpio45";
function = "qup13";
};
- qup_uart11_tx: qup-uart11-tx-pins {
+ qup_uart11_tx: qup-uart11-tx-state {
pins = "gpio46";
function = "qup13";
};
- qup_uart11_rx: qup-uart11-rx-pins {
+ qup_uart11_rx: qup-uart11-rx-state {
pins = "gpio47";
function = "qup13";
};
- qup_uart12_cts: qup-uart12-cts-pins {
+ qup_uart12_cts: qup-uart12-cts-state {
pins = "gpio48";
function = "qup14";
};
- qup_uart12_rts: qup-uart12-rts-pins {
+ qup_uart12_rts: qup-uart12-rts-state {
pins = "gpio49";
function = "qup14";
};
- qup_uart12_tx: qup-uart12-tx-pins {
+ qup_uart12_tx: qup-uart12-tx-state {
pins = "gpio50";
function = "qup14";
};
- qup_uart12_rx: qup-uart12-rx-pins {
+ qup_uart12_rx: qup-uart12-rx-state {
pins = "gpio51";
function = "qup14";
};
- qup_uart13_cts: qup-uart13-cts-pins {
+ qup_uart13_cts: qup-uart13-cts-state {
pins = "gpio52";
function = "qup15";
};
- qup_uart13_rts: qup-uart13-rts-pins {
+ qup_uart13_rts: qup-uart13-rts-state {
pins = "gpio53";
function = "qup15";
};
- qup_uart13_tx: qup-uart13-tx-pins {
+ qup_uart13_tx: qup-uart13-tx-state {
pins = "gpio54";
function = "qup15";
};
- qup_uart13_rx: qup-uart13-rx-pins {
+ qup_uart13_rx: qup-uart13-rx-state {
pins = "gpio55";
function = "qup15";
};
- qup_uart14_cts: qup-uart14-cts-pins {
+ qup_uart14_cts: qup-uart14-cts-state {
pins = "gpio56";
function = "qup16";
};
- qup_uart14_rts: qup-uart14-rts-pins {
+ qup_uart14_rts: qup-uart14-rts-state {
pins = "gpio57";
function = "qup16";
};
- qup_uart14_tx: qup-uart14-tx-pins {
+ qup_uart14_tx: qup-uart14-tx-state {
pins = "gpio58";
function = "qup16";
};
- qup_uart14_rx: qup-uart14-rx-pins {
+ qup_uart14_rx: qup-uart14-rx-state {
pins = "gpio59";
function = "qup16";
};
- qup_uart15_cts: qup-uart15-cts-pins {
+ qup_uart15_cts: qup-uart15-cts-state {
pins = "gpio60";
function = "qup17";
};
- qup_uart15_rts: qup-uart15-rts-pins {
+ qup_uart15_rts: qup-uart15-rts-state {
pins = "gpio61";
function = "qup17";
};
- qup_uart15_tx: qup-uart15-tx-pins {
+ qup_uart15_tx: qup-uart15-tx-state {
pins = "gpio62";
function = "qup17";
};
- qup_uart15_rx: qup-uart15-rx-pins {
+ qup_uart15_rx: qup-uart15-rx-state {
pins = "gpio63";
function = "qup17";
};
- sdc1_clk: sdc1-clk-pins {
+ sdc1_clk: sdc1-clk-state {
pins = "sdc1_clk";
};
- sdc1_cmd: sdc1-cmd-pins {
+ sdc1_cmd: sdc1-cmd-state {
pins = "sdc1_cmd";
};
- sdc1_data: sdc1-data-pins {
+ sdc1_data: sdc1-data-state {
pins = "sdc1_data";
};
- sdc1_rclk: sdc1-rclk-pins {
+ sdc1_rclk: sdc1-rclk-state {
pins = "sdc1_rclk";
};
- sdc1_clk_sleep: sdc1-clk-sleep-pins {
+ sdc1_clk_sleep: sdc1-clk-sleep-state {
pins = "sdc1_clk";
drive-strength = <2>;
bias-bus-hold;
};
- sdc1_cmd_sleep: sdc1-cmd-sleep-pins {
+ sdc1_cmd_sleep: sdc1-cmd-sleep-state {
pins = "sdc1_cmd";
drive-strength = <2>;
bias-bus-hold;
};
- sdc1_data_sleep: sdc1-data-sleep-pins {
+ sdc1_data_sleep: sdc1-data-sleep-state {
pins = "sdc1_data";
drive-strength = <2>;
bias-bus-hold;
};
- sdc1_rclk_sleep: sdc1-rclk-sleep-pins {
+ sdc1_rclk_sleep: sdc1-rclk-sleep-state {
pins = "sdc1_rclk";
drive-strength = <2>;
bias-bus-hold;
};
- sdc2_clk: sdc2-clk-pins {
+ sdc2_clk: sdc2-clk-state {
pins = "sdc2_clk";
};
- sdc2_cmd: sdc2-cmd-pins {
+ sdc2_cmd: sdc2-cmd-state {
pins = "sdc2_cmd";
};
- sdc2_data: sdc2-data-pins {
+ sdc2_data: sdc2-data-state {
pins = "sdc2_data";
};
- sdc2_clk_sleep: sdc2-clk-sleep-pins {
+ sdc2_clk_sleep: sdc2-clk-sleep-state {
pins = "sdc2_clk";
drive-strength = <2>;
bias-bus-hold;
};
- sdc2_cmd_sleep: sdc2-cmd-sleep-pins {
+ sdc2_cmd_sleep: sdc2-cmd-sleep-state {
pins = "sdc2_cmd";
drive-strength = <2>;
bias-bus-hold;
};
- sdc2_data_sleep: sdc2-data-sleep-pins {
+ sdc2_data_sleep: sdc2-data-sleep-state {
pins = "sdc2_data";
drive-strength = <2>;
bias-bus-hold;
@@ -5314,7 +5318,7 @@
};
epss_l3: interconnect@18590000 {
- compatible = "qcom,sc7280-epss-l3";
+ compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3";
reg = <0 0x18590000 0 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
@@ -5322,7 +5326,7 @@
};
cpufreq_hw: cpufreq@18591000 {
- compatible = "qcom,cpufreq-epss";
+ compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss";
reg = <0 0x18591000 0 0x1000>,
<0 0x18592000 0 0x1000>,
<0 0x18593000 0 0x1000>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
index 5e30349efd20..551768f97729 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
@@ -37,7 +37,7 @@
vreg_edp_bl: regulator-edp-bl {
compatible = "regulator-fixed";
- regulator-name = "VREG_EDP_BL";
+ regulator-name = "VBL9";
regulator-min-microvolt = <3600000>;
regulator-max-microvolt = <3600000>;
@@ -50,10 +50,24 @@
regulator-boot-on;
};
+ vreg_nvme: regulator-nvme {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VCC3_SSD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 135 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&nvme_reg_en>;
+ };
+
vreg_misc_3p3: regulator-misc-3p3 {
compatible = "regulator-fixed";
- regulator-name = "VREG_MISC_3P3";
+ regulator-name = "VCC3B";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -66,6 +80,38 @@
regulator-boot-on;
regulator-always-on;
};
+
+ vreg_wlan: regulator-wlan {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VCC_WLAN_3R9";
+ regulator-min-microvolt = <3900000>;
+ regulator-max-microvolt = <3900000>;
+
+ gpio = <&pmr735a_gpios 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&hastings_reg_en>;
+
+ regulator-boot-on;
+ };
+
+ vreg_wwan: regulator-wwan {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VCC3B_WAN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&pmc8280_2_gpios 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wwan_sw_en>;
+
+ regulator-boot-on;
+ };
};
&apps_rsc {
@@ -124,9 +170,8 @@
regulator-max-microvolt = <2504000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
- regulator-allowed-modes =
- <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13c: ldo13 {
@@ -149,9 +194,8 @@
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
- regulator-allowed-modes =
- <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4d: ldo4 {
@@ -184,6 +228,63 @@
};
};
+&pcie2a {
+ perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+
+ vddpe-3v3-supply = <&vreg_nvme>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2a_default>;
+
+ status = "okay";
+};
+
+&pcie2a_phy {
+ vdda-phy-supply = <&vreg_l6d>;
+ vdda-pll-supply = <&vreg_l4d>;
+
+ status = "okay";
+};
+
+&pcie3a {
+ perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
+ vddpe-3v3-supply = <&vreg_wwan>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3a_default>;
+
+ status = "okay";
+};
+
+&pcie3a_phy {
+ vdda-phy-supply = <&vreg_l6d>;
+ vdda-pll-supply = <&vreg_l4d>;
+
+ status = "okay";
+};
+
+&pcie4 {
+ perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
+ vddpe-3v3-supply = <&vreg_wlan>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie4_default>;
+
+ status = "okay";
+};
+
+&pcie4_phy {
+ vdda-phy-supply = <&vreg_l6d>;
+ vdda-pll-supply = <&vreg_l4d>;
+
+ status = "okay";
+};
+
&pmc8280c_lpg {
status = "okay";
};
@@ -369,6 +470,13 @@
};
};
+&pmc8280_2_gpios {
+ wwan_sw_en: wwan-sw-en-state {
+ pins = "gpio1";
+ function = "normal";
+ };
+};
+
&pmc8280c_gpios {
edp_bl_pwm: edp-bl-pwm-state {
pins = "gpio8";
@@ -376,29 +484,112 @@
};
};
+&pmr735a_gpios {
+ hastings_reg_en: hastings-reg-en-state {
+ pins = "gpio1";
+ function = "normal";
+ };
+};
+
&tlmm {
gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
kybd_default: kybd-default-state {
- disable {
+ disable-pins {
pins = "gpio102";
function = "gpio";
output-low;
};
- int-n {
+ int-n-pins {
pins = "gpio104";
function = "gpio";
bias-disable;
};
- reset {
+ reset-pins {
pins = "gpio105";
function = "gpio";
bias-disable;
};
};
+ nvme_reg_en: nvme-reg-en-state {
+ pins = "gpio135";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie2a_default: pcie2a-default-state {
+ clkreq-n-pins {
+ pins = "gpio142";
+ function = "pcie2a_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio143";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-n-pins {
+ pins = "gpio145";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie3a_default: pcie3a-default-state {
+ clkreq-n-pins {
+ pins = "gpio150";
+ function = "pcie3a_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio151";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-n-pins {
+ pins = "gpio148";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie4_default: pcie4-default-state {
+ clkreq-n-pins {
+ pins = "gpio140";
+ function = "pcie4_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio141";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-n-pins {
+ pins = "gpio139";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
qup0_i2c4_default: qup0-i2c4-default-state {
pins = "gpio171", "gpio172";
function = "qup4";
@@ -416,7 +607,7 @@
};
tpad_default: tpad-default-state {
- int-n {
+ int-n-pins {
pins = "gpio182";
function = "gpio";
bias-disable;
@@ -424,13 +615,13 @@
};
ts0_default: ts0-default-state {
- int-n {
+ int-n-pins {
pins = "gpio175";
function = "gpio";
bias-disable;
};
- reset-n {
+ reset-n-pins {
pins = "gpio99";
function = "gpio";
output-high;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index b2b744bb8a53..568c6be1ceaa 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -7,6 +7,11 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sc8280xp.dtsi"
@@ -26,6 +31,67 @@
pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>;
};
+ thermal-zones {
+ skin-temp-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+ thermal-sensors = <&pmk8280_adc_tm 5>;
+
+ trips {
+ skin_temp_alert0: trip-point0 {
+ temperature = <55000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ skin_temp_alert1: trip-point1 {
+ temperature = <58000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ skin-temp-crit {
+ temperature = <73000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&skin_temp_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+
+ map1 {
+ trip = <&skin_temp_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&hall_int_n_default>;
+
+ switch-lid {
+ gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ wakeup-source;
+ wakeup-event-action = <EV_ACT_DEASSERTED>;
+ };
+ };
+
vreg_edp_bl: regulator-edp-bl {
compatible = "regulator-fixed";
@@ -58,6 +124,54 @@
regulator-boot-on;
regulator-always-on;
};
+
+ vreg_nvme: regulator-nvme {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VCC3_SSD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 135 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&nvme_reg_en>;
+
+ regulator-boot-on;
+ };
+
+ vreg_wlan: regulator-wlan {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VCC_WLAN_3R9";
+ regulator-min-microvolt = <3900000>;
+ regulator-max-microvolt = <3900000>;
+
+ gpio = <&pmr735a_gpios 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&hastings_reg_en>;
+
+ regulator-boot-on;
+ };
+
+ vreg_wwan: regulator-wwan {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VCC3B_WAN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&pmc8280_2_gpios 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wwan_sw_en>;
+
+ regulator-boot-on;
+ };
};
&apps_rsc {
@@ -95,7 +209,7 @@
regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-boot-on;
- regulator-always-on; // FIXME: VDD_A_EDP_0_0P9
+ regulator-always-on; /* FIXME: VDD_A_EDP_0_0P9 */
};
};
@@ -145,6 +259,13 @@
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
+ vreg_l6d: ldo6 {
+ regulator-name = "vreg_l6d";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
vreg_l7d: ldo7 {
regulator-name = "vreg_l7d";
regulator-min-microvolt = <3072000>;
@@ -161,14 +282,221 @@
};
};
+&pcie2a {
+ perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+
+ vddpe-3v3-supply = <&vreg_nvme>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2a_default>;
+
+ status = "okay";
+};
+
+&pcie2a_phy {
+ vdda-phy-supply = <&vreg_l6d>;
+ vdda-pll-supply = <&vreg_l4d>;
+
+ status = "okay";
+};
+
+&pcie3a {
+ perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
+ vddpe-3v3-supply = <&vreg_wwan>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3a_default>;
+
+ status = "okay";
+};
+
+&pcie3a_phy {
+ vdda-phy-supply = <&vreg_l6d>;
+ vdda-pll-supply = <&vreg_l4d>;
+
+ status = "okay";
+};
+
+&pcie4 {
+ perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
+ vddpe-3v3-supply = <&vreg_wlan>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie4_default>;
+
+ status = "okay";
+};
+
+&pcie4_phy {
+ vdda-phy-supply = <&vreg_l6d>;
+ vdda-pll-supply = <&vreg_l4d>;
+
+ status = "okay";
+};
+
&pmc8280c_lpg {
status = "okay";
};
+&pmk8280_adc_tm {
+ status = "okay";
+
+ sys-therm@0 {
+ reg = <0>;
+ io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
+ qcom,hw-settle-time-us = <200>;
+ qcom,avg-samples = <2>;
+ qcom,ratiometric;
+ };
+
+ sys-therm@1 {
+ reg = <1>;
+ io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
+ qcom,hw-settle-time-us = <200>;
+ qcom,avg-samples = <2>;
+ qcom,ratiometric;
+ };
+
+ sys-therm@2 {
+ reg = <2>;
+ io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
+ qcom,hw-settle-time-us = <200>;
+ qcom,avg-samples = <2>;
+ qcom,ratiometric;
+ };
+
+ sys-therm@3 {
+ reg = <3>;
+ io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
+ qcom,hw-settle-time-us = <200>;
+ qcom,avg-samples = <2>;
+ qcom,ratiometric;
+ };
+
+ sys-therm@4 {
+ reg = <4>;
+ io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
+ qcom,hw-settle-time-us = <200>;
+ qcom,avg-samples = <2>;
+ qcom,ratiometric;
+ };
+
+ sys-therm@5 {
+ reg = <5>;
+ io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM2_100K_PU(3)>;
+ qcom,hw-settle-time-us = <200>;
+ qcom,avg-samples = <2>;
+ qcom,ratiometric;
+ };
+
+ sys-therm@6 {
+ reg = <6>;
+ io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM3_100K_PU(3)>;
+ qcom,hw-settle-time-us = <200>;
+ qcom,avg-samples = <2>;
+ qcom,ratiometric;
+ };
+
+ sys-therm@7 {
+ reg = <7>;
+ io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM4_100K_PU(3)>;
+ qcom,hw-settle-time-us = <200>;
+ qcom,avg-samples = <2>;
+ qcom,ratiometric;
+ };
+};
+
&pmk8280_pon_pwrkey {
status = "okay";
};
+&pmk8280_pon_resin {
+ status = "okay";
+};
+
+&pmk8280_vadc {
+ status = "okay";
+
+ pmic-die-temp@3 {
+ reg = <PMK8350_ADC7_DIE_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ xo-therm@44 {
+ reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ qcom,hw-settle-time = <200>;
+ qcom,ratiometric;
+ };
+
+ pmic-die-temp@103 {
+ reg = <PM8350_ADC7_DIE_TEMP(1)>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ sys-therm@144 {
+ reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
+ qcom,hw-settle-time = <200>;
+ qcom,ratiometric;
+ };
+
+ sys-therm@145 {
+ reg = <PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
+ qcom,hw-settle-time = <200>;
+ qcom,ratiometric;
+ };
+
+ sys-therm@146 {
+ reg = <PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
+ qcom,hw-settle-time = <200>;
+ qcom,ratiometric;
+ };
+
+ sys-therm@147 {
+ reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
+ qcom,hw-settle-time = <200>;
+ qcom,ratiometric;
+ };
+
+ pmic-die-temp@303 {
+ reg = <PM8350_ADC7_DIE_TEMP(3)>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ sys-therm@344 {
+ reg = <PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
+ qcom,hw-settle-time = <200>;
+ qcom,ratiometric;
+ };
+
+ sys-therm@345 {
+ reg = <PM8350_ADC7_AMUX_THM2_100K_PU(3)>;
+ qcom,hw-settle-time = <200>;
+ qcom,ratiometric;
+ };
+
+ sys-therm@346 {
+ reg = <PM8350_ADC7_AMUX_THM3_100K_PU(3)>;
+ qcom,hw-settle-time = <200>;
+ qcom,ratiometric;
+ };
+
+ sys-therm@347 {
+ reg = <PM8350_ADC7_AMUX_THM4_100K_PU(3)>;
+ qcom,hw-settle-time = <200>;
+ qcom,ratiometric;
+ };
+
+ pmic-die-temp@403 {
+ reg = <PMR735A_ADC7_DIE_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
&qup0 {
status = "okay";
};
@@ -339,6 +667,13 @@
};
};
+&pmc8280_2_gpios {
+ wwan_sw_en: wwan-sw-en-state {
+ pins = "gpio1";
+ function = "normal";
+ };
+};
+
&pmc8280c_gpios {
edp_bl_pwm: edp-bl-pwm-state {
pins = "gpio8";
@@ -346,29 +681,119 @@
};
};
+&pmr735a_gpios {
+ hastings_reg_en: hastings-reg-en-state {
+ pins = "gpio1";
+ function = "normal";
+ };
+};
+
&tlmm {
gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
+ hall_int_n_default: hall-int-n-state {
+ pins = "gpio107";
+ function = "gpio";
+ input-enable;
+ bias-disable;
+ };
+
kybd_default: kybd-default-state {
- disable {
+ disable-pins {
pins = "gpio102";
function = "gpio";
output-low;
};
- int-n {
+ int-n-pins {
pins = "gpio104";
function = "gpio";
bias-disable;
};
- reset {
+ reset-pins {
pins = "gpio105";
function = "gpio";
bias-disable;
};
};
+ nvme_reg_en: nvme-reg-en-state {
+ pins = "gpio135";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie2a_default: pcie2a-default-state {
+ clkreq-n-pins {
+ pins = "gpio142";
+ function = "pcie2a_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio143";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-n-pins {
+ pins = "gpio145";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie3a_default: pcie3a-default-state {
+ clkreq-n-pins {
+ pins = "gpio150";
+ function = "pcie3a_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio151";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-n-pins {
+ pins = "gpio148";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie4_default: pcie4-default-state {
+ clkreq-n-pins {
+ pins = "gpio140";
+ function = "pcie4_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio141";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-n-pins {
+ pins = "gpio139";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
qup0_i2c4_default: qup0-i2c4-default-state {
pins = "gpio171", "gpio172";
function = "qup4";
@@ -384,7 +809,7 @@
};
tpad_default: tpad-default-state {
- int-n {
+ int-n-pins {
pins = "gpio182";
function = "gpio";
bias-disable;
@@ -392,13 +817,13 @@
};
ts0_default: ts0-default-state {
- int-n {
+ int-n-pins {
pins = "gpio175";
function = "gpio";
bias-disable;
};
- reset-n {
+ reset-n-pins {
pins = "gpio99";
function = "gpio";
output-high;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi
index 24836b6b9bbc..f2c0b71b5d8e 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi
@@ -7,6 +7,50 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
+/ {
+ thermal-zones {
+ pm8280_1_thermal: pm8280-1-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm8280_1_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ pm8280_2_thermal: pm8280-2-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm8280_2_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
&spmi_bus {
pmk8280: pmic@0 {
compatible = "qcom,pmk8350", "qcom,spmi-pmic";
@@ -24,6 +68,32 @@
linux,code = <KEY_POWER>;
status = "disabled";
};
+
+ pmk8280_pon_resin: resin {
+ compatible = "qcom,pmk8350-resin";
+ interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
+ status = "disabled";
+ };
+ };
+
+ pmk8280_vadc: adc@3100 {
+ compatible = "qcom,spmi-adc7";
+ reg = <0x3100>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
+ pmk8280_adc_tm: adc-tm@3400 {
+ compatible = "qcom,spmi-adc-tm5-gen2";
+ reg = <0x3400>;
+ interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #thermal-sensor-cells = <1>;
+ status = "disabled";
};
};
@@ -33,6 +103,13 @@
#address-cells = <1>;
#size-cells = <0>;
+ pm8280_1_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
pmc8280_1_gpios: gpio@8800 {
compatible = "qcom,pm8350-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
@@ -78,6 +155,13 @@
#address-cells = <1>;
#size-cells = <0>;
+ pm8280_2_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
pmc8280_2_gpios: gpio@8800 {
compatible = "qcom,pm8350-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 212d63d5cbf2..109c9d2b684d 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
@@ -38,66 +39,87 @@
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
+ opp-peak-kBps = <(300000 * 32)>;
};
opp-403200000 {
opp-hz = /bits/ 64 <403200000>;
+ opp-peak-kBps = <(384000 * 32)>;
};
opp-499200000 {
opp-hz = /bits/ 64 <499200000>;
+ opp-peak-kBps = <(480000 * 32)>;
};
opp-595200000 {
opp-hz = /bits/ 64 <595200000>;
+ opp-peak-kBps = <(576000 * 32)>;
};
opp-691200000 {
opp-hz = /bits/ 64 <691200000>;
+ opp-peak-kBps = <(672000 * 32)>;
};
opp-806400000 {
opp-hz = /bits/ 64 <806400000>;
+ opp-peak-kBps = <(768000 * 32)>;
};
opp-902400000 {
opp-hz = /bits/ 64 <902400000>;
+ opp-peak-kBps = <(864000 * 32)>;
};
opp-1017600000 {
opp-hz = /bits/ 64 <1017600000>;
+ opp-peak-kBps = <(960000 * 32)>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
+ opp-peak-kBps = <(1075200 * 32)>;
};
opp-1209600000 {
opp-hz = /bits/ 64 <1209600000>;
+ opp-peak-kBps = <(1171200 * 32)>;
};
opp-1324800000 {
opp-hz = /bits/ 64 <1324800000>;
+ opp-peak-kBps = <(1267200 * 32)>;
};
opp-1440000000 {
opp-hz = /bits/ 64 <1440000000>;
+ opp-peak-kBps = <(1363200 * 32)>;
};
opp-1555200000 {
opp-hz = /bits/ 64 <1555200000>;
+ opp-peak-kBps = <(1536000 * 32)>;
};
opp-1670400000 {
opp-hz = /bits/ 64 <1670400000>;
+ opp-peak-kBps = <(1612800 * 32)>;
};
opp-1785600000 {
opp-hz = /bits/ 64 <1785600000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
opp-1881600000 {
opp-hz = /bits/ 64 <1881600000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
opp-1996800000 {
opp-hz = /bits/ 64 <1996800000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
opp-2112000000 {
opp-hz = /bits/ 64 <2112000000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
opp-2227200000 {
opp-hz = /bits/ 64 <2227200000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
opp-2342400000 {
opp-hz = /bits/ 64 <2342400000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
opp-2438400000 {
opp-hz = /bits/ 64 <2438400000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
};
@@ -107,66 +129,87 @@
opp-825600000 {
opp-hz = /bits/ 64 <825600000>;
+ opp-peak-kBps = <(768000 * 32)>;
};
opp-940800000 {
opp-hz = /bits/ 64 <940800000>;
+ opp-peak-kBps = <(864000 * 32)>;
};
opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
+ opp-peak-kBps = <(960000 * 32)>;
};
opp-1171200000 {
opp-hz = /bits/ 64 <1171200000>;
+ opp-peak-kBps = <(1171200 * 32)>;
};
opp-1286400000 {
opp-hz = /bits/ 64 <1286400000>;
+ opp-peak-kBps = <(1267200 * 32)>;
};
opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
+ opp-peak-kBps = <(1363200 * 32)>;
};
opp-1516800000 {
opp-hz = /bits/ 64 <1516800000>;
+ opp-peak-kBps = <(1459200 * 32)>;
};
opp-1632000000 {
opp-hz = /bits/ 64 <1632000000>;
+ opp-peak-kBps = <(1612800 * 32)>;
};
opp-1747200000 {
opp-hz = /bits/ 64 <1747200000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
opp-1862400000 {
opp-hz = /bits/ 64 <1862400000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
opp-1977600000 {
opp-hz = /bits/ 64 <1977600000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
opp-2073600000 {
opp-hz = /bits/ 64 <2073600000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
opp-2169600000 {
opp-hz = /bits/ 64 <2169600000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
opp-2284800000 {
opp-hz = /bits/ 64 <2284800000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
opp-2400000000 {
opp-hz = /bits/ 64 <2400000000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
opp-2496000000 {
opp-hz = /bits/ 64 <2496000000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
opp-2592000000 {
opp-hz = /bits/ 64 <2592000000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
opp-2688000000 {
opp-hz = /bits/ 64 <2688000000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
opp-2803200000 {
opp-hz = /bits/ 64 <2803200000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
opp-2899200000 {
opp-hz = /bits/ 64 <2899200000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
opp-2995200000 {
opp-hz = /bits/ 64 <2995200000>;
+ opp-peak-kBps = <(1689600 * 32)>;
};
};
@@ -185,6 +228,7 @@
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
@@ -206,6 +250,7 @@
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
@@ -224,6 +269,7 @@
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
@@ -242,6 +288,7 @@
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
@@ -260,6 +307,7 @@
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
@@ -278,6 +326,7 @@
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
@@ -296,6 +345,7 @@
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
@@ -314,6 +364,7 @@
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
@@ -729,11 +780,11 @@
<0>,
<0>,
<0>,
- <0>,
- <0>,
- <0>,
- <0>,
- <0>,
+ <&pcie2a_phy>,
+ <&pcie2b_phy>,
+ <&pcie3a_phy>,
+ <&pcie3b_phy>,
+ <&pcie4_phy>,
<0>,
<0>;
power-domains = <&rpmhpd SC8280XP_CX>;
@@ -839,12 +890,505 @@
status = "disabled";
};
+ pcie4: pcie@1c00000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-sc8280xp";
+ reg = <0x0 0x01c00000 0x0 0x3000>,
+ <0x0 0x30000000 0x0 0xf1d>,
+ <0x0 0x30000f20 0x0 0xa8>,
+ <0x0 0x30001000 0x0 0x1000>,
+ <0x0 0x30100000 0x0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>,
+ <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
+ bus-range = <0x00 0xff>;
+
+ dma-coherent;
+
+ linux,pci-domain = <6>;
+ num-lanes = <1>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
+ <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
+ <&gcc GCC_CNOC_PCIE4_QX_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "noc_aggr_4",
+ "noc_aggr_south_sf",
+ "cnoc_qx";
+
+ assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_4_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc PCIE_4_GDSC>;
+
+ phys = <&pcie4_phy>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+ };
+
+ pcie4_phy: phy@1c06000 {
+ compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
+ reg = <0x0 0x01c06000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
+ <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_4_CLKREF_CLK>,
+ <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_4_PIPE_CLK>,
+ <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "rchng",
+ "pipe", "pipediv2";
+
+ assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc PCIE_4_GDSC>;
+
+ resets = <&gcc GCC_PCIE_4_PHY_BCR>;
+ reset-names = "phy";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_4_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ pcie3b: pcie@1c08000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-sc8280xp";
+ reg = <0x0 0x01c08000 0x0 0x3000>,
+ <0x0 0x32000000 0x0 0xf1d>,
+ <0x0 0x32000f20 0x0 0xa8>,
+ <0x0 0x32001000 0x0 0x1000>,
+ <0x0 0x32100000 0x0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>,
+ <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
+ bus-range = <0x00 0xff>;
+
+ dma-coherent;
+
+ linux,pci-domain = <5>;
+ num-lanes = <2>;
+
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
+ <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "noc_aggr_4",
+ "noc_aggr_south_sf";
+
+ assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_3B_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc PCIE_3B_GDSC>;
+
+ phys = <&pcie3b_phy>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+ };
+
+ pcie3b_phy: phy@1c0e000 {
+ compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
+ reg = <0x0 0x01c0e000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
+ <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
+ <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_3B_PIPE_CLK>,
+ <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "rchng",
+ "pipe", "pipediv2";
+
+ assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc PCIE_3B_GDSC>;
+
+ resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
+ reset-names = "phy";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_3b_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ pcie3a: pcie@1c10000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-sc8280xp";
+ reg = <0x0 0x01c10000 0x0 0x3000>,
+ <0x0 0x34000000 0x0 0xf1d>,
+ <0x0 0x34000f20 0x0 0xa8>,
+ <0x0 0x34001000 0x0 0x1000>,
+ <0x0 0x34100000 0x0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>,
+ <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
+ bus-range = <0x00 0xff>;
+
+ dma-coherent;
+
+ linux,pci-domain = <4>;
+ num-lanes = <4>;
+
+ interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
+ <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "noc_aggr_4",
+ "noc_aggr_south_sf";
+
+ assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_3A_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc PCIE_3A_GDSC>;
+
+ phys = <&pcie3a_phy>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+ };
+
+ pcie3a_phy: phy@1c14000 {
+ compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
+ reg = <0x0 0x01c14000 0x0 0x2000>,
+ <0x0 0x01c16000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
+ <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
+ <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_3A_PIPE_CLK>,
+ <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "rchng",
+ "pipe", "pipediv2";
+
+ assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc PCIE_3A_GDSC>;
+
+ resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
+ reset-names = "phy";
+
+ qcom,4ln-config-sel = <&tcsr 0xa044 1>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_3a_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ pcie2b: pcie@1c18000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-sc8280xp";
+ reg = <0x0 0x01c18000 0x0 0x3000>,
+ <0x0 0x38000000 0x0 0xf1d>,
+ <0x0 0x38000f20 0x0 0xa8>,
+ <0x0 0x38001000 0x0 0x1000>,
+ <0x0 0x38100000 0x0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>,
+ <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
+ bus-range = <0x00 0xff>;
+
+ dma-coherent;
+
+ linux,pci-domain = <3>;
+ num-lanes = <2>;
+
+ interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
+ <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "noc_aggr_4",
+ "noc_aggr_south_sf";
+
+ assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_2B_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc PCIE_2B_GDSC>;
+
+ phys = <&pcie2b_phy>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+ };
+
+ pcie2b_phy: phy@1c1e000 {
+ compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
+ reg = <0x0 0x01c1e000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
+ <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
+ <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_2B_PIPE_CLK>,
+ <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "rchng",
+ "pipe", "pipediv2";
+
+ assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc PCIE_2B_GDSC>;
+
+ resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
+ reset-names = "phy";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_2b_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ pcie2a: pcie@1c20000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-sc8280xp";
+ reg = <0x0 0x01c20000 0x0 0x3000>,
+ <0x0 0x3c000000 0x0 0xf1d>,
+ <0x0 0x3c000f20 0x0 0xa8>,
+ <0x0 0x3c001000 0x0 0x1000>,
+ <0x0 0x3c100000 0x0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
+ <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
+ bus-range = <0x00 0xff>;
+
+ dma-coherent;
+
+ linux,pci-domain = <2>;
+ num-lanes = <4>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
+ <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "noc_aggr_4",
+ "noc_aggr_south_sf";
+
+ assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_2A_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc PCIE_2A_GDSC>;
+
+ phys = <&pcie2a_phy>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+ };
+
+ pcie2a_phy: phy@1c24000 {
+ compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
+ reg = <0x0 0x01c24000 0x0 0x2000>,
+ <0x0 0x01c26000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
+ <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
+ <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_2A_PIPE_CLK>,
+ <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "rchng",
+ "pipe", "pipediv2";
+
+ assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc PCIE_2A_GDSC>;
+
+ resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
+ reset-names = "phy";
+
+ qcom,4ln-config-sel = <&tcsr 0xa044 0>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_2a_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
ufs_mem_hc: ufs@1d84000 {
compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
+ phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
@@ -855,12 +1399,13 @@
required-opps = <&rpmhpd_opp_nom>;
iommus = <&apps_smmu 0xe0 0x0>;
+ dma-coherent;
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_REF_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
@@ -885,27 +1430,20 @@
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sc8280xp-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x1c8>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- clock-names = "ref",
- "ref_aux";
- clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>,
+ reg = <0 0x01d87000 0 0x1000>;
+
+ clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+ clock-names = "ref", "ref_aux";
+
+ power-domains = <&gcc UFS_PHY_GDSC>;
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
- status = "disabled";
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x108>,
- <0 0x01d87600 0 0x1e0>,
- <0 0x01d87c00 0 0x1dc>,
- <0 0x01d87800 0 0x108>,
- <0 0x01d87a00 0 0x1e0>;
- #phy-cells = <0>;
- };
+ #phy-cells = <0>;
+
+ status = "disabled";
};
ufs_card_hc: ufs@1da4000 {
@@ -913,7 +1451,7 @@
"jedec,ufs-2.0";
reg = <0 0x01da4000 0 0x3000>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_card_phy_lanes>;
+ phys = <&ufs_card_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
@@ -923,12 +1461,13 @@
power-domains = <&gcc UFS_CARD_GDSC>;
iommus = <&apps_smmu 0x4a0 0x0>;
+ dma-coherent;
clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
<&gcc GCC_UFS_CARD_AHB_CLK>,
<&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_REF_CLKREF_CLK>,
<&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
@@ -953,28 +1492,20 @@
ufs_card_phy: phy@1da7000 {
compatible = "qcom,sc8280xp-qmp-ufs-phy";
- reg = <0 0x01da7000 0 0x1c8>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- clock-names = "ref",
- "ref_aux";
- clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>,
+ reg = <0 0x01da7000 0 0x1000>;
+
+ clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
<&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
+ clock-names = "ref", "ref_aux";
+
+ power-domains = <&gcc UFS_CARD_GDSC>;
resets = <&ufs_card_hc 0>;
reset-names = "ufsphy";
- status = "disabled";
+ #phy-cells = <0>;
- ufs_card_phy_lanes: phy@1da7400 {
- reg = <0 0x01da7400 0 0x108>,
- <0 0x01da7600 0 0x1e0>,
- <0 0x01da7c00 0 0x1dc>,
- <0 0x01da7800 0 0x108>,
- <0 0x01da7a00 0 0x1e0>;
- #phy-cells = <0>;
- };
+ status = "disabled";
};
tcsr_mutex: hwlock@1f40000 {
@@ -983,6 +1514,11 @@
#hwlock-cells = <1>;
};
+ tcsr: syscon@1fc0000 {
+ compatible = "qcom,sc8280xp-tcsr", "syscon";
+ reg = <0x0 0x01fc0000 0x0 0x30000>;
+ };
+
usb_0_hsphy: phy@88e5000 {
compatible = "qcom,sc8280xp-usb-hs-phy",
"qcom,usb-snps-hs-5nm-phy";
@@ -1048,70 +1584,52 @@
status = "disabled";
};
- usb_2_qmpphy0: phy-wrapper@88ef000 {
+ usb_2_qmpphy0: phy@88ef000 {
compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
- reg = <0 0x088ef000 0 0x1c8>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x088ef000 0 0x2000>;
clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_MP0_CLKREF_CLK>,
- <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>;
- clock-names = "aux", "ref_clk_src", "ref", "com_aux";
+ <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
+ clock-names = "aux", "ref", "com_aux", "pipe";
resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
<&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
- reset-names = "phy", "common";
+ reset-names = "phy", "phy_phy";
power-domains = <&gcc USB30_MP_GDSC>;
- status = "disabled";
+ #clock-cells = <0>;
+ clock-output-names = "usb2_phy0_pipe_clk";
- usb_2_ssphy0: phy@88efe00 {
- reg = <0 0x088efe00 0 0x160>,
- <0 0x088f0000 0 0x1ec>,
- <0 0x088ef200 0 0x1f0>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb2_phy0_pipe_clk";
- };
+ #phy-cells = <0>;
+
+ status = "disabled";
};
- usb_2_qmpphy1: phy-wrapper@88f1000 {
+ usb_2_qmpphy1: phy@88f1000 {
compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
- reg = <0 0x088f1000 0 0x1c8>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x088f1000 0 0x2000>;
clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_MP1_CLKREF_CLK>,
- <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>;
- clock-names = "aux", "ref_clk_src", "ref", "com_aux";
+ <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
+ clock-names = "aux", "ref", "com_aux", "pipe";
resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
<&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
- reset-names = "phy", "common";
+ reset-names = "phy", "phy_phy";
power-domains = <&gcc USB30_MP_GDSC>;
- status = "disabled";
+ #clock-cells = <0>;
+ clock-output-names = "usb2_phy1_pipe_clk";
- usb_2_ssphy1: phy@88f1e00 {
- reg = <0 0x088f1e00 0 0x160>,
- <0 0x088f2000 0 0x1ec>,
- <0 0x088f1200 0 0x1f0>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb2_phy1_pipe_clk";
- };
+ #phy-cells = <0>;
+
+ status = "disabled";
};
remoteproc_adsp: remoteproc@3000000 {
@@ -1245,6 +1763,97 @@
};
};
+ pmu@9091000 {
+ compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+ reg = <0 0x9091000 0 0x1000>;
+
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
+
+ operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+ llcc_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <762000>;
+ };
+ opp-1 {
+ opp-peak-kBps = <1720000>;
+ };
+ opp-2 {
+ opp-peak-kBps = <2086000>;
+ };
+ opp-3 {
+ opp-peak-kBps = <2597000>;
+ };
+ opp-4 {
+ opp-peak-kBps = <2929000>;
+ };
+ opp-5 {
+ opp-peak-kBps = <3879000>;
+ };
+ opp-6 {
+ opp-peak-kBps = <5161000>;
+ };
+ opp-7 {
+ opp-peak-kBps = <5931000>;
+ };
+ opp-8 {
+ opp-peak-kBps = <6515000>;
+ };
+ opp-9 {
+ opp-peak-kBps = <7980000>;
+ };
+ opp-10 {
+ opp-peak-kBps = <8136000>;
+ };
+ opp-11 {
+ opp-peak-kBps = <10437000>;
+ };
+ opp-12 {
+ opp-peak-kBps = <12191000>;
+ };
+ };
+ };
+
+ pmu@90b6400 {
+ compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,msm8998-bwmon";
+ reg = <0 0x090b6400 0 0x600>;
+
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+ cpu_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <2288000>;
+ };
+ opp-1 {
+ opp-peak-kBps = <4577000>;
+ };
+ opp-2 {
+ opp-peak-kBps = <7110000>;
+ };
+ opp-3 {
+ opp-peak-kBps = <9155000>;
+ };
+ opp-4 {
+ opp-peak-kBps = <12298000>;
+ };
+ opp-5 {
+ opp-peak-kBps = <14236000>;
+ };
+ opp-6 {
+ opp-peak-kBps = <15258001>;
+ };
+ };
+ };
+
system-cache-controller@9200000 {
compatible = "qcom,sc8280xp-llcc";
reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>;
@@ -1456,6 +2065,11 @@
#clock-cells = <0>;
};
+ sram@c3f0000 {
+ compatible = "qcom,rpmh-stats";
+ reg = <0 0x0c3f0000 0 0x400>;
+ };
+
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0 0x0c440000 0 0x1100>,
@@ -1786,6 +2400,16 @@
};
};
+ epss_l3: interconnect@18590000 {
+ compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
+ reg = <0 0x18590000 0 0x1000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
reg = <0 0x18591000 0 0x1000>,
diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
index 28050bc5f081..7c81918eee66 100644
--- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
+++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
@@ -99,7 +99,7 @@
};
&adsp_pil {
- firmware-name = "qcom/ifc6560/adsp.mbn";
+ firmware-name = "qcom/sda660/adsp.mbn";
};
&blsp_i2c6 {
@@ -231,7 +231,7 @@
};
&rpm_requests {
- pm660-regulators {
+ regulators-0 {
compatible = "qcom,rpm-pm660-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -313,7 +313,7 @@
};
};
- pm660l-regulators {
+ regulators-1 {
compatible = "qcom,rpm-pm660l-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -401,16 +401,18 @@
};
&sdc2_state_on {
- sd-cd {
+ sd-cd-pins {
pins = "gpio54";
+ function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
};
&sdc2_state_off {
- sd-cd {
+ sd-cd-pins {
pins = "gpio54";
+ function = "gpio";
bias-disable;
drive-strength = <2>;
};
@@ -436,7 +438,7 @@
cd-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
no-sdio;
- no-emmc;
+ no-mmc;
};
&tlmm {
diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi
index 09c07800793a..3d2b08d551d0 100644
--- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi
@@ -155,7 +155,7 @@
};
&adsp_pil {
- firmware-name = "adsp.mdt";
+ firmware-name = "qcom/sdm630/Sony/nile/adsp.mdt";
};
&blsp_i2c1 {
@@ -260,7 +260,7 @@
};
&rpm_requests {
- pm660l-regulators {
+ regulators-0 {
compatible = "qcom,rpm-pm660l-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -394,7 +394,7 @@
};
};
- pm660-regulators {
+ regulators-1 {
compatible = "qcom,rpm-pm660-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -577,16 +577,18 @@
};
&sdc2_state_on {
- sd-cd {
+ sd-cd-pins {
pins = "gpio54";
+ function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
};
&sdc2_state_off {
- sd-cd {
+ sd-cd-pins {
pins = "gpio54";
+ function = "gpio";
bias-disable;
drive-strength = <2>;
};
@@ -615,33 +617,35 @@
&tlmm {
gpio-reserved-ranges = <8 4>;
- ts_int_active: ts-int-active {
+ ts_int_active: ts-int-active-state {
pins = "gpio45";
+ function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
- ts_lcd_id_active: ts-lcd-id-active {
+ ts_lcd_id_active: ts-lcd-id-active-state {
pins = "gpio56";
+ function = "gpio";
drive-strength = <8>;
bias-disable;
};
- imx300_vana_default: imx300-vana-default {
+ imx300_vana_default: imx300-vana-default-state {
pins = "gpio50";
function = "gpio";
bias-disable;
drive-strength = <2>;
};
- imx219_vana_default: imx219-vana-default {
+ imx219_vana_default: imx219-vana-default-state {
pins = "gpio51";
function = "gpio";
bias-disable;
drive-strength = <2>;
};
- cam_vdig_default: cam-vdig-default {
+ cam_vdig_default: cam-vdig-default-state {
pins = "gpio52";
function = "gpio";
bias-disable;
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index b51b85f583e5..13e6a4fbba27 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -721,33 +721,36 @@
interrupt-controller;
#interrupt-cells = <2>;
- blsp1_uart1_default: blsp1-uart1-default {
+ blsp1_uart1_default: blsp1-uart1-default-state {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "blsp_uart1";
drive-strength = <2>;
bias-disable;
};
- blsp1_uart1_sleep: blsp1-uart1-sleep {
+ blsp1_uart1_sleep: blsp1-uart1-sleep-state {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
- blsp1_uart2_default: blsp1-uart2-default {
+ blsp1_uart2_default: blsp1-uart2-default-state {
pins = "gpio4", "gpio5";
+ function = "blsp_uart2";
drive-strength = <2>;
bias-disable;
};
- blsp2_uart1_default: blsp2-uart1-active {
- tx-rts {
+ blsp2_uart1_default: blsp2-uart1-active-state {
+ tx-rts-pins {
pins = "gpio16", "gpio19";
function = "blsp_uart5";
drive-strength = <2>;
bias-disable;
};
- rx {
+ rx-pins {
/*
* Avoid garbage data while BT module
* is powered off or not driving signal
@@ -758,7 +761,7 @@
bias-pull-up;
};
- cts {
+ cts-pins {
/* Match the pull of the BT module */
pins = "gpio18";
function = "blsp_uart5";
@@ -767,244 +770,232 @@
};
};
- blsp2_uart1_sleep: blsp2-uart1-sleep {
- tx {
+ blsp2_uart1_sleep: blsp2-uart1-sleep-state {
+ tx-pins {
pins = "gpio16";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
- rx-cts-rts {
+ rx-cts-rts-pins {
pins = "gpio17", "gpio18", "gpio19";
function = "gpio";
drive-strength = <2>;
- bias-no-pull;
+ bias-disable;
};
};
- i2c1_default: i2c1-default {
+ i2c1_default: i2c1-default-state {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
drive-strength = <2>;
bias-disable;
};
- i2c1_sleep: i2c1-sleep {
+ i2c1_sleep: i2c1-sleep-state {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
drive-strength = <2>;
bias-pull-up;
};
- i2c2_default: i2c2-default {
+ i2c2_default: i2c2-default-state {
pins = "gpio6", "gpio7";
function = "blsp_i2c2";
drive-strength = <2>;
bias-disable;
};
- i2c2_sleep: i2c2-sleep {
+ i2c2_sleep: i2c2-sleep-state {
pins = "gpio6", "gpio7";
function = "blsp_i2c2";
drive-strength = <2>;
bias-pull-up;
};
- i2c3_default: i2c3-default {
+ i2c3_default: i2c3-default-state {
pins = "gpio10", "gpio11";
function = "blsp_i2c3";
drive-strength = <2>;
bias-disable;
};
- i2c3_sleep: i2c3-sleep {
+ i2c3_sleep: i2c3-sleep-state {
pins = "gpio10", "gpio11";
function = "blsp_i2c3";
drive-strength = <2>;
bias-pull-up;
};
- i2c4_default: i2c4-default {
+ i2c4_default: i2c4-default-state {
pins = "gpio14", "gpio15";
function = "blsp_i2c4";
drive-strength = <2>;
bias-disable;
};
- i2c4_sleep: i2c4-sleep {
+ i2c4_sleep: i2c4-sleep-state {
pins = "gpio14", "gpio15";
function = "blsp_i2c4";
drive-strength = <2>;
bias-pull-up;
};
- i2c5_default: i2c5-default {
+ i2c5_default: i2c5-default-state {
pins = "gpio18", "gpio19";
function = "blsp_i2c5";
drive-strength = <2>;
bias-disable;
};
- i2c5_sleep: i2c5-sleep {
+ i2c5_sleep: i2c5-sleep-state {
pins = "gpio18", "gpio19";
function = "blsp_i2c5";
drive-strength = <2>;
bias-pull-up;
};
- i2c6_default: i2c6-default {
+ i2c6_default: i2c6-default-state {
pins = "gpio22", "gpio23";
function = "blsp_i2c6";
drive-strength = <2>;
bias-disable;
};
- i2c6_sleep: i2c6-sleep {
+ i2c6_sleep: i2c6-sleep-state {
pins = "gpio22", "gpio23";
function = "blsp_i2c6";
drive-strength = <2>;
bias-pull-up;
};
- i2c7_default: i2c7-default {
+ i2c7_default: i2c7-default-state {
pins = "gpio26", "gpio27";
function = "blsp_i2c7";
drive-strength = <2>;
bias-disable;
};
- i2c7_sleep: i2c7-sleep {
+ i2c7_sleep: i2c7-sleep-state {
pins = "gpio26", "gpio27";
function = "blsp_i2c7";
drive-strength = <2>;
bias-pull-up;
};
- i2c8_default: i2c8-default {
+ i2c8_default: i2c8-default-state {
pins = "gpio30", "gpio31";
- function = "blsp_i2c8";
+ function = "blsp_i2c8_a";
drive-strength = <2>;
bias-disable;
};
- i2c8_sleep: i2c8-sleep {
+ i2c8_sleep: i2c8-sleep-state {
pins = "gpio30", "gpio31";
- function = "blsp_i2c8";
+ function = "blsp_i2c8_a";
drive-strength = <2>;
bias-pull-up;
};
- cci0_default: cci0_default {
- pinmux {
- pins = "gpio36","gpio37";
- function = "cci_i2c";
- };
-
- pinconf {
- pins = "gpio36","gpio37";
- bias-pull-up;
- drive-strength = <2>;
- };
+ cci0_default: cci0-default-state {
+ pins = "gpio36","gpio37";
+ function = "cci_i2c";
+ bias-pull-up;
+ drive-strength = <2>;
};
- cci1_default: cci1_default {
- pinmux {
- pins = "gpio38","gpio39";
- function = "cci_i2c";
- };
-
- pinconf {
- pins = "gpio38","gpio39";
- bias-pull-up;
- drive-strength = <2>;
- };
+ cci1_default: cci1-default-state {
+ pins = "gpio38","gpio39";
+ function = "cci_i2c";
+ bias-pull-up;
+ drive-strength = <2>;
};
- sdc1_state_on: sdc1-on {
- clk {
+ sdc1_state_on: sdc1-on-state {
+ clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
- cmd {
+ cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
- data {
+ data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
- rclk {
+ rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
- sdc1_state_off: sdc1-off {
- clk {
+ sdc1_state_off: sdc1-off-state {
+ clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
- cmd {
+ cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
- data {
+ data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
- rclk {
+ rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
- sdc2_state_on: sdc2-on {
- clk {
+ sdc2_state_on: sdc2-on-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
- cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
- data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
};
- sdc2_state_off: sdc2-off {
- clk {
+ sdc2_state_off: sdc2-off-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
- cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
- data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
@@ -1616,7 +1607,6 @@
"core";
phys = <&dsi0_phy>;
- phy-names = "dsi";
status = "disabled";
@@ -1639,7 +1629,7 @@
};
};
- dsi0_phy: dsi-phy@c994400 {
+ dsi0_phy: phy@c994400 {
compatible = "qcom,dsi-phy-14nm-660";
reg = <0x0c994400 0x100>,
<0x0c994500 0x300>,
@@ -2224,12 +2214,12 @@
#address-cells = <1>;
#size-cells = <0>;
- q6core {
+ service@3 {
reg = <APR_SVC_ADSP_CORE>;
compatible = "qcom,q6core";
};
- q6afe: apr-service@4 {
+ q6afe: service@4 {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
q6afedai: dais {
@@ -2240,7 +2230,7 @@
};
};
- q6asm: apr-service@7 {
+ q6asm: service@7 {
compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>;
q6asmdai: dais {
@@ -2252,7 +2242,7 @@
};
};
- q6adm: apr-service@8 {
+ q6adm: service@8 {
compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>;
q6routing: routing {
diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts
index 891e314bc782..3fb513cad0a9 100644
--- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts
+++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts
@@ -49,6 +49,20 @@
vdda-phy-dpdm-supply = <&pm8953_l13>;
};
+&i2c_3 {
+ status = "okay";
+
+ touchscreen@48 {
+ compatible = "himax,hx83112b";
+ reg = <0x48>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <65 IRQ_TYPE_LEVEL_LOW>;
+ touchscreen-size-x = <1080>;
+ touchscreen-size-y = <2160>;
+ reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
+ };
+};
+
&pm8953_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
@@ -69,7 +83,7 @@
};
&rpm_requests {
- pm8953-regulators {
+ regulators {
compatible = "qcom,rpm-pm8953-regulators";
vdd_l1-supply = <&pm8953_s3>;
diff --git a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts
index 58f687fc49e0..9702e5f59a1d 100644
--- a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts
+++ b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts
@@ -19,7 +19,7 @@
};
&sdc2_state_on {
- clk {
+ clk-pins {
drive-strength = <14>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts
index a3559f6e34a5..8fb2d1788742 100644
--- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts
+++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts
@@ -111,7 +111,7 @@
};
&rpm_requests {
- pm660l-regulators {
+ regulators-0 {
compatible = "qcom,rpm-pm660l-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -206,7 +206,7 @@
};
};
- pm660-regulators {
+ regulators-1 {
compatible = "qcom,rpm-pm660-regulators";
vdd_s1-supply = <&vph_pwr>;
@@ -372,16 +372,18 @@
};
&sdc2_state_on {
- sd-cd {
+ sd-cd-pins {
pins = "gpio54";
+ function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
};
&sdc2_state_off {
- sd-cd {
+ sd-cd-pins {
pins = "gpio54";
+ function = "gpio";
bias-disable;
drive-strength = <2>;
};
diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi
index 43220af1b685..d52123cb5cd3 100644
--- a/arch/arm64/boot/dts/qcom/sdm660.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi
@@ -190,7 +190,6 @@
"core";
phys = <&dsi1_phy>;
- phy-names = "dsi";
status = "disabled";
@@ -213,7 +212,7 @@
};
};
- dsi1_phy: dsi-phy@c996400 {
+ dsi1_phy: phy@c996400 {
compatible = "qcom,dsi-phy-14nm-660";
reg = <0x0c996400 0x100>,
<0x0c996500 0x300>,
diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
new file mode 100644
index 000000000000..cf2ae540db12
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
@@ -0,0 +1,531 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device tree for Google Pixel 3a, adapted from google-blueline device tree,
+ * xiaomi-lavender device tree, and oneplus-common device tree.
+ *
+ * Copyright (c) 2022, Richard Acayan. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include "sdm670.dtsi"
+#include "pm660.dtsi"
+#include "pm660l.dtsi"
+
+/delete-node/ &mpss_region;
+/delete-node/ &venus_mem;
+/delete-node/ &wlan_msa_mem;
+/delete-node/ &cdsp_mem;
+/delete-node/ &mba_region;
+/delete-node/ &adsp_mem;
+/delete-node/ &ipa_fw_mem;
+/delete-node/ &ipa_gsi_mem;
+/delete-node/ &gpu_mem;
+
+/ {
+ model = "Google Pixel 3a";
+ compatible = "google,sargo", "qcom,sdm670";
+
+ aliases { };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer@9c000000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x9c000000 0 (1080 * 2220 * 4)>;
+ width = <1080>;
+ height = <2220>;
+ stride = <(1080 * 4)>;
+ format = "a8r8g8b8";
+ };
+ };
+
+ clocks {
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32764>;
+ };
+
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <38400000>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&vol_up_pin>;
+
+ key-vol-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mpss_region: mpss@8b000000 {
+ reg = <0 0x8b000000 0 0x9800000>;
+ no-map;
+ };
+
+ venus_mem: venus@94800000 {
+ reg = <0 0x94800000 0 0x500000>;
+ no-map;
+ };
+
+ wlan_msa_mem: wlan-msa@94d00000 {
+ reg = <0 0x94d00000 0 0x100000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp@94e00000 {
+ reg = <0 0x94e00000 0 0x800000>;
+ no-map;
+ };
+
+ mba_region: mba@95600000 {
+ reg = <0 0x95600000 0 0x200000>;
+ no-map;
+ };
+
+ adsp_mem: adsp@95800000 {
+ reg = <0 0x95800000 0 0x2200000>;
+ no-map;
+ };
+
+ ipa_fw_mem: ipa-fw@97a00000 {
+ reg = <0 0x97a00000 0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi@97a10000 {
+ reg = <0 0x97a10000 0 0x5000>;
+ no-map;
+ };
+
+ gpu_mem: gpu@97a15000 {
+ reg = <0 0x97a15000 0 0x2000>;
+ no-map;
+ };
+
+ framebuffer-region@9c000000 {
+ reg = <0 0x9c000000 0 0x2400000>;
+ no-map;
+ };
+
+ /* Also includes ramoops regions */
+ debug_info_mem: debug-info@a1800000 {
+ reg = <0 0xa1800000 0 0x411000>;
+ no-map;
+ };
+ };
+
+ /*
+ * The touchscreen regulator seems to be controlled somehow by a gpio.
+ * Model it as a fixed regulator and keep it on. Without schematics we
+ * don't know how this is actually wired up...
+ */
+ ts_1p8_supply: ts-1p8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "ts_1p8_supply";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&pm660_gpios 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3312000>;
+ regulator-max-microvolt = <3312000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /*
+ * Supply map from xiaomi-lavender specifies this as the supply for
+ * ldob1, ldob9, ldob10, ldoa2, and ldoa3, while downstream specifies
+ * this as a power domain. Set this as a fixed regulator with the same
+ * voltage as lavender until display is needed to avoid unneccessarily
+ * using a deprecated binding (regulator-fixed-domain).
+ */
+ vreg_s2b_1p05: vreg-s2b-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s2b";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm660-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ vdd-l1-l6-l7-supply = <&vreg_s6a_0p87>;
+ vdd-l2-l3-supply = <&vreg_s2b_1p05>;
+ vdd-l5-supply = <&vreg_s2b_1p05>;
+ vdd-l8-l9-l10-l11-l12-l13-l14-supply = <&vreg_s4a_2p04>;
+ vdd-l15-l16-l17-l18-l19-supply = <&vreg_bob>;
+
+ /*
+ * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed
+ * by the Core Power Reduction hardened (CPRh) and the
+ * Operating State Manager (OSM) HW automatically.
+ */
+
+ vreg_s4a_2p04: smps4 {
+ regulator-min-microvolt = <1808000>;
+ regulator-max-microvolt = <2040000>;
+ regulator-enable-ramp-delay = <200>;
+ };
+
+ vreg_s6a_0p87: smps6 {
+ regulator-min-microvolt = <1224000>;
+ regulator-max-microvolt = <1352000>;
+ regulator-enable-ramp-delay = <150>;
+ };
+
+ /* LDOs */
+ vreg_l1a_1p225: ldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l2a_1p0: ldo2 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l3a_1p0: ldo3 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l5a_0p848: ldo5 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l6a_1p3: ldo6 {
+ regulator-min-microvolt = <1248000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l7a_1p2: ldo7 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l8a_1p8: ldo8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l9a_1p8: ldo9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l10a_1p8: ldo10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l11a_1p8: ldo11 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l12a_1p8: ldo12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l13a_1p8: ldo13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l14a_1p8: ldo14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l15a_1p8: ldo15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l16a_2p7: ldo16 {
+ regulator-min-microvolt = <2696000>;
+ regulator-max-microvolt = <2696000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l17a_1p8: ldo17 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l19a_3p3: ldo19 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm660l-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ vdd-l1-l9-l10-supply = <&vreg_s2b_1p05>;
+ vdd-l2-supply = <&vreg_bob>;
+ vdd-l3-l5-l7-l8-supply = <&vreg_bob>;
+ vdd-l4-l6-supply = <&vreg_bob>;
+ vdd-bob-supply = <&vph_pwr>;
+
+ /* LDOs */
+ vreg_l1b_0p925: ldo1 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <900000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l2b_2p95: ldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l3b_3p0: ldo3 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l4b_2p95: ldo4 {
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l5b_2p95: ldo5 {
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l6b_3p3: ldo6 {
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l7b_3p125: ldo7 {
+ regulator-min-microvolt = <3088000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l8b_3p3: ldo8 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ /*
+ * Downstream specifies a fixed voltage of 3.312 V, but the
+ * PMIC4 BOB ranges don't support that. Widen the range a
+ * little to avoid adding a new BOB regulator type.
+ */
+ vreg_bob: bob {
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3328000>;
+ regulator-enable-ramp-delay = <500>;
+ };
+ };
+
+};
+
+&gcc {
+ protected-clocks = <GCC_QSPI_CORE_CLK>,
+ <GCC_QSPI_CORE_CLK_SRC>,
+ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&i2c9 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ synaptics-rmi4-i2c@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+ interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_default>;
+
+ vio-supply = <&ts_1p8_supply>;
+
+ syna,reset-delay-ms = <200>;
+ syna,startup-delay-ms = <200>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rmi4-f01@1 {
+ reg = <0x01>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f12@12 {
+ reg = <0x12>;
+ touchscreen-x-mm = <62>;
+ touchscreen-y-mm = <127>;
+ syna,sensor-type = <1>;
+ };
+ };
+};
+
+&pm660l_gpios {
+ vol_up_pin: vol-up-state {
+ pins = "gpio7";
+ function = "normal";
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+ input-enable;
+ bias-pull-up;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&sdhc_1 {
+ supports-cqe;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-ddr-1_8v;
+
+ qcom,ddr-config = <0xc3040873>;
+
+ vmmc-supply = <&vreg_l4b_2p95>;
+ vqmmc-supply = <&vreg_l8a_1p8>;
+
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <0 4>, <81 4>;
+
+ touchscreen_default: ts-default-state {
+ ts-reset-pins {
+ pins = "gpio99";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ output-high;
+ };
+
+ ts-irq-pins {
+ pins = "gpio125";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ ts-switch-pins {
+ pins = "gpio135";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l1b_0p925>;
+ vdda-pll-supply = <&vreg_l10a_1p8>;
+ vdda-phy-dpdm-supply = <&vreg_l7b_3p125>;
+
+ status = "okay";
+};
+
+&usb_1 {
+ qcom,select-utmi-as-pipe-clk;
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ /* Only peripheral works for now */
+ dr_mode = "peripheral";
+
+ /* Do not assume that sdm670.dtsi will never support USB 3.0 */
+ phys = <&usb_1_hsphy>;
+ phy-names = "usb2-phy";
+ maximum-speed = "high-speed";
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
new file mode 100644
index 000000000000..47363fde64ac
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -0,0 +1,1160 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SDM670 SoC device tree source, adapted from SDM845 SoC device tree
+ *
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Richard Acayan. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy-qcom-qusb2.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases { };
+
+ chosen { };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,kryo360";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo360";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD1>;
+ power-domain-names = "psci";
+ next-level-cache = <&L2_100>;
+ L2_100: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "qcom,kryo360";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD2>;
+ power-domain-names = "psci";
+ next-level-cache = <&L2_200>;
+ L2_200: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "qcom,kryo360";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD3>;
+ power-domain-names = "psci";
+ next-level-cache = <&L2_300>;
+ L2_300: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "qcom,kryo360";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD4>;
+ power-domain-names = "psci";
+ next-level-cache = <&L2_400>;
+ L2_400: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "qcom,kryo360";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD5>;
+ power-domain-names = "psci";
+ next-level-cache = <&L2_500>;
+ L2_500: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU6: cpu@600 {
+ device_type = "cpu";
+ compatible = "qcom,kryo360";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD6>;
+ power-domain-names = "psci";
+ next-level-cache = <&L2_600>;
+ L2_600: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU7: cpu@700 {
+ device_type = "cpu";
+ compatible = "qcom,kryo360";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD7>;
+ power-domain-names = "psci";
+ next-level-cache = <&L2_700>;
+ L2_700: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+
+ core4 {
+ cpu = <&CPU4>;
+ };
+
+ core5 {
+ cpu = <&CPU5>;
+ };
+
+ core6 {
+ cpu = <&CPU6>;
+ };
+
+ core7 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "little-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <702>;
+ exit-latency-us = <915>;
+ min-residency-us = <1617>;
+ local-timer-stop;
+ };
+
+ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "big-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <526>;
+ exit-latency-us = <1854>;
+ min-residency-us = <2380>;
+ local-timer-stop;
+ };
+ };
+
+ domain-idle-states {
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x4100c244>;
+ entry-latency-us = <3263>;
+ exit-latency-us = <6562>;
+ min-residency-us = <9825>;
+ };
+ };
+ };
+
+ firmware {
+ scm {
+ compatible = "qcom,scm-sdm670", "qcom,scm";
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0x80000000 0x0 0x0>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ CPU_PD0: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD1: power-domain-cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD2: power-domain-cpu2 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD3: power-domain-cpu3 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD4: power-domain-cpu4 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD5: power-domain-cpu5 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD6: power-domain-cpu6 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ };
+
+ CPU_PD7: power-domain-cpu7 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ };
+
+ CLUSTER_PD: power-domain-cluster {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&CLUSTER_SLEEP_0>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: hyp-mem@85700000 {
+ reg = <0 0x85700000 0 0x600000>;
+ no-map;
+ };
+
+ xbl_mem: xbl-mem@85e00000 {
+ reg = <0 0x85e00000 0 0x100000>;
+ no-map;
+ };
+
+ aop_mem: aop-mem@85fc0000 {
+ reg = <0 0x85fc0000 0 0x20000>;
+ no-map;
+ };
+
+ aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
+ compatible = "qcom,cmd-db";
+ reg = <0 0x85fe0000 0 0x20000>;
+ no-map;
+ };
+
+ camera_mem: camera-mem@8ab00000 {
+ reg = <0 0x8ab00000 0 0x500000>;
+ no-map;
+ };
+
+ mpss_region: mpss@8b000000 {
+ reg = <0 0x8b000000 0 0x7e00000>;
+ no-map;
+ };
+
+ venus_mem: venus@92e00000 {
+ reg = <0 0x92e00000 0 0x500000>;
+ no-map;
+ };
+
+ wlan_msa_mem: wlan-msa@93300000 {
+ reg = <0 0x93300000 0 0x100000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp@93400000 {
+ reg = <0 0x93400000 0 0x800000>;
+ no-map;
+ };
+
+ mba_region: mba@93c00000 {
+ reg = <0 0x93c00000 0 0x200000>;
+ no-map;
+ };
+
+ adsp_mem: adsp@93e00000 {
+ reg = <0 0x93e00000 0 0x1e00000>;
+ no-map;
+ };
+
+ ipa_fw_mem: ipa-fw@95c00000 {
+ reg = <0 0x95c00000 0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi@95c10000 {
+ reg = <0 0x95c10000 0 0x5000>;
+ no-map;
+ };
+
+ gpu_mem: gpu@95c15000 {
+ reg = <0 0x95c15000 0 0x2000>;
+ no-map;
+ };
+
+ spss_mem: spss@97b00000 {
+ reg = <0 0x97b00000 0 0x100000>;
+ no-map;
+ };
+
+ qseecom_mem: qseecom@9e400000 {
+ reg = <0 0x9e400000 0 0x1400000>;
+ no-map;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ soc: soc@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0 0x10 0>;
+ dma-ranges = <0 0 0 0 0x10 0>;
+ compatible = "simple-bus";
+
+ gcc: clock-controller@100000 {
+ compatible = "qcom,gcc-sdm670";
+ reg = <0 0x00100000 0 0x1f0000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ clock-names = "bi_tcxo",
+ "bi_tcxo_ao",
+ "sleep_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ sdhc_1: mmc@7c4000 {
+ compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0 0x007c4000 0 0x1000>,
+ <0 0x007c5000 0 0x1000>,
+ <0 0x007c8000 0 0x8000>;
+ reg-names = "hc", "cqhci", "ice";
+
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
+ clock-names = "iface", "core", "xo", "ice", "bus";
+
+ iommus = <&apps_smmu 0x140 0xf>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc1_state_on>;
+ pinctrl-1 = <&sdc1_state_off>;
+ power-domains = <&rpmhpd SDM670_CX>;
+
+ bus-width = <8>;
+ non-removable;
+
+ status = "disabled";
+ };
+
+ gpi_dma0: dma-controller@800000 {
+ #dma-cells = <3>;
+ compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
+ reg = <0 0x00800000 0 0x60000>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <13>;
+ dma-channel-mask = <0xfa>;
+ iommus = <&apps_smmu 0x16 0x0>;
+ status = "disabled";
+ };
+
+ qupv3_id_0: geniqup@8c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0 0x008c0000 0 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x3 0x0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ i2c0: i2c@880000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00880000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c0_default>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c1: i2c@884000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00884000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c1_default>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c2: i2c@888000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00888000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c2_default>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c3: i2c@88c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0088c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c3_default>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c4: i2c@890000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00890000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c4_default>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c5: i2c@894000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00894000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c5_default>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c6: i2c@898000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00898000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c6_default>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c7: i2c@89c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0089c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c7_default>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 7 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
+ gpi_dma1: dma-controller@a00000 {
+ #dma-cells = <3>;
+ compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
+ reg = <0 0x00a00000 0 0x60000>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <13>;
+ dma-channel-mask = <0xfa>;
+ iommus = <&apps_smmu 0x6d6 0x0>;
+ status = "disabled";
+ };
+
+ qupv3_id_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0 0x00ac0000 0 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x6c3 0x0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ i2c8: i2c@a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a80000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c8_default>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c9: i2c@a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a84000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c9_default>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c10: i2c@a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a88000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c10_default>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c11: i2c@a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a8c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c11_default>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c12: i2c@a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a90000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c12_default>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c13: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a94000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c13_default>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c14: i2c@a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a98000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c14_default>;
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c15: i2c@a9c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a9c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c15_default>;
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 7 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
+ tlmm: pinctrl@3400000 {
+ compatible = "qcom,sdm670-tlmm";
+ reg = <0 0x03400000 0 0xc00000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 151>;
+
+ qup_i2c0_default: qup-i2c0-default-state {
+ pins = "gpio0", "gpio1";
+ function = "qup0";
+ };
+
+ qup_i2c1_default: qup-i2c1-default-state {
+ pins = "gpio17", "gpio18";
+ function = "qup1";
+ };
+
+ qup_i2c2_default: qup-i2c2-default-state {
+ pins = "gpio27", "gpio28";
+ function = "qup2";
+ };
+
+ qup_i2c3_default: qup-i2c3-default-state {
+ pins = "gpio41", "gpio42";
+ function = "qup3";
+ };
+
+ qup_i2c4_default: qup-i2c4-default-state {
+ pins = "gpio89", "gpio90";
+ function = "qup4";
+ };
+
+ qup_i2c5_default: qup-i2c5-default-state {
+ pins = "gpio85", "gpio86";
+ function = "qup5";
+ };
+
+ qup_i2c6_default: qup-i2c6-default-state {
+ pins = "gpio45", "gpio46";
+ function = "qup6";
+ };
+
+ qup_i2c7_default: qup-i2c7-default-state {
+ pins = "gpio93", "gpio94";
+ function = "qup7";
+ };
+
+ qup_i2c8_default: qup-i2c8-default-state {
+ pins = "gpio65", "gpio66";
+ function = "qup8";
+ };
+
+ qup_i2c9_default: qup-i2c9-default-state {
+ pins = "gpio6", "gpio7";
+ function = "qup9";
+ };
+
+ qup_i2c10_default: qup-i2c10-default-state {
+ pins = "gpio55", "gpio56";
+ function = "qup10";
+ };
+
+ qup_i2c11_default: qup-i2c11-default-state {
+ pins = "gpio31", "gpio32";
+ function = "qup11";
+ };
+
+ qup_i2c12_default: qup-i2c12-default-state {
+ pins = "gpio49", "gpio50";
+ function = "qup12";
+ };
+
+ qup_i2c13_default: qup-i2c13-default-state {
+ pins = "gpio105", "gpio106";
+ function = "qup13";
+ };
+
+ qup_i2c14_default: qup-i2c14-default-state {
+ pins = "gpio33", "gpio34";
+ function = "qup14";
+ };
+
+ qup_i2c15_default: qup-i2c15-default-state {
+ pins = "gpio81", "gpio82";
+ function = "qup15";
+ };
+
+ sdc1_state_on: sdc1-on-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_state_off: sdc1-off-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+ };
+
+ usb_1_hsphy: phy@88e2000 {
+ compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy";
+ reg = <0 0x088e2000 0 0x400>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_1: usb@a6f8800 {
+ compatible = "qcom,sdm670-dwc3", "qcom,dwc3";
+ reg = <0 0x0a6f8800 0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <150000000>;
+
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq", "ss_phy_irq",
+ "dm_hs_phy_irq", "dp_hs_phy_irq";
+
+ power-domains = <&gcc USB30_PRIM_GDSC>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ status = "disabled";
+
+ usb_1_dwc3: usb@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a600000 0 0xcd00>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x740 0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ phys = <&usb_1_hsphy>;
+ phy-names = "usb2-phy";
+ };
+ };
+
+ spmi_bus: spmi@c440000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0 0x0c440000 0 0x1100>,
+ <0 0x0c600000 0 0x2000000>,
+ <0 0x0e600000 0 0x100000>,
+ <0 0x0e700000 0 0xa0000>,
+ <0 0x0c40a000 0 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+ reg = <0 0x15000000 0 0x80000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ apps_rsc: rsc@179c0000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0 0x179c0000 0 0x10000>,
+ <0 0x179d0000 0 0x10000>,
+ <0 0x179e0000 0 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ label = "apps_rsc";
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>,
+ <SLEEP_TCS 3>,
+ <WAKE_TCS 3>,
+ <CONTROL_TCS 1>;
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sdm670-rpmh-clk";
+ #clock-cells = <1>;
+ clock-names = "xo";
+ clocks = <&xo_board>;
+ };
+
+ rpmhpd: power-controller {
+ compatible = "qcom,sdm670-rpmhpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp1 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_min_svs: opp2 {
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+
+ rpmhpd_opp_low_svs: opp3 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_svs: opp4 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l1: opp5 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_nom: opp6 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp7 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp8 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp9 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp10 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+ };
+ };
+ };
+
+ intc: interrupt-controller@17a00000 {
+ compatible = "arm,gic-v3";
+ reg = <0 0x17a00000 0 0x10000>, /* GICD */
+ <0 0x17a60000 0 0x100000>; /* GICR * 8 */
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <3>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
index b5eb8f7eca1d..ca676e04687b 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
@@ -16,7 +16,7 @@
/ {
aliases {
bluetooth0 = &bluetooth;
- hsuart0 = &uart6;
+ serial1 = &uart6;
serial0 = &uart9;
wifi0 = &wifi;
};
@@ -860,6 +860,8 @@ ap_ts_i2c: &i2c14 {
&uart6 {
status = "okay";
+ pinctrl-0 = <&qup_uart6_4pin>;
+
bluetooth: wcn3990-bt {
compatible = "qcom,wcn3990-bt";
vddio-supply = <&src_pp1800_s4a>;
@@ -1079,41 +1081,6 @@ ap_ts_i2c: &i2c14 {
};
};
-&qup_uart6_default {
- /* Change pinmux to all 4 pins since CTS and RTS are connected */
- pinmux {
- pins = "gpio45", "gpio46",
- "gpio47", "gpio48";
- };
-
- pinconf-cts {
- /*
- * Configure a pull-down on 45 (CTS) to match the pull of
- * the Bluetooth module.
- */
- pins = "gpio45";
- bias-pull-down;
- };
-
- pinconf-rts-tx {
- /* We'll drive 46 (RTS) and 47 (TX), so no pull */
- pins = "gpio46", "gpio47";
- drive-strength = <2>;
- bias-disable;
- };
-
- pinconf-rx {
- /*
- * Configure a pull-up on 48 (RX). This is needed to avoid
- * garbage data when the TX pin of the Bluetooth module is
- * in tri-state (module powered off or not driving the
- * signal yet).
- */
- pins = "gpio48";
- bias-pull-up;
- };
-};
-
&qup_uart9_default {
pinconf-tx {
pins = "gpio4";
@@ -1341,7 +1308,7 @@ ap_ts_i2c: &i2c14 {
};
pen_rst_l: pen-rst-l {
- pinmux {
+ pinmux {
pins = "gpio23";
function = "gpio";
};
@@ -1408,7 +1375,7 @@ ap_ts_i2c: &i2c14 {
};
ts_int_l: ts-int-l {
- pinmux {
+ pinmux {
pins = "gpio125";
function = "gpio";
};
@@ -1420,7 +1387,7 @@ ap_ts_i2c: &i2c14 {
};
ts_reset_l: ts-reset-l {
- pinmux {
+ pinmux {
pins = "gpio118";
function = "gpio";
};
@@ -1436,7 +1403,7 @@ ap_ts_i2c: &i2c14 {
config {
pins = "gpio126";
function = "gpio";
- bias-no-pull;
+ bias-disable;
drive-strength = <2>;
output-low;
};
@@ -1446,7 +1413,7 @@ ap_ts_i2c: &i2c14 {
config {
pins = "gpio126";
function = "gpio";
- bias-no-pull;
+ bias-disable;
drive-strength = <2>;
output-high;
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dts
new file mode 100644
index 000000000000..a21caa6f3fa2
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dts
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022, Linaro Ltd.
+ */
+
+/dts-v1/;
+
+#include "sdm845-db845c.dts"
+
+&camss {
+ vdda-phy-supply = <&vreg_l1a_0p875>;
+ vdda-pll-supply = <&vreg_l26a_1p2>;
+
+ status = "okay";
+
+ ports {
+ port@0 {
+ csiphy0_ep: endpoint {
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&ov8856_ep>;
+ };
+ };
+ };
+};
+
+&cci {
+ status = "okay";
+};
+
+&cci_i2c0 {
+ camera@10 {
+ compatible = "ovti,ov8856";
+ reg = <0x10>;
+
+ /* CAM0_RST_N */
+ reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cam0_default>;
+
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "xvclk";
+ clock-frequency = <19200000>;
+
+ /*
+ * The &vreg_s4a_1p8 trace is powered on as a,
+ * so it is represented by a fixed regulator.
+ *
+ * The 2.8V vdda-supply and 1.2V vddd-supply regulators
+ * both have to be enabled through the power management
+ * gpios.
+ */
+ dovdd-supply = <&vreg_lvs1a_1p8>;
+ avdd-supply = <&cam0_avdd_2v8>;
+ dvdd-supply = <&cam0_dvdd_1v2>;
+
+ port {
+ ov8856_ep: endpoint {
+ link-frequencies = /bits/ 64
+ <360000000 180000000>;
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&csiphy0_ep>;
+ };
+ };
+ };
+};
+
+&cci_i2c1 {
+ camera@60 {
+ compatible = "ovti,ov7251";
+
+ /* I2C address as per ov7251.txt linux documentation */
+ reg = <0x60>;
+
+ /* CAM3_RST_N */
+ enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cam3_default>;
+
+ clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "xclk";
+ clock-frequency = <24000000>;
+
+ /*
+ * The &vreg_s4a_1p8 trace always powered on.
+ *
+ * The 2.8V vdda-supply regulator is enabled when the
+ * vreg_s4a_1p8 trace is pulled high.
+ * It too is represented by a fixed regulator.
+ *
+ * No 1.2V vddd-supply regulator is used.
+ */
+ vdddo-supply = <&vreg_lvs1a_1p8>;
+ vdda-supply = <&cam3_avdd_2v8>;
+
+ status = "disabled";
+
+ port {
+ ov7251_ep: endpoint {
+ data-lanes = <0 1>;
+/* remote-endpoint = <&csiphy3_ep>; */
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
index 132417e2d11e..f41c6d600ea8 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
@@ -22,7 +22,7 @@
aliases {
serial0 = &uart9;
- hsuart0 = &uart6;
+ serial1 = &uart6;
};
chosen {
@@ -120,9 +120,11 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- // TODO: make it possible to drive same GPIO from two clients
- // gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>;
- // enable-active-high;
+ /*
+ * TODO: make it possible to drive same GPIO from two clients
+ * gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ * enable-active-high;
+ */
};
pcie0_1p05v: pcie-0-1p05v-regulator {
@@ -133,9 +135,11 @@
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
- // TODO: make it possible to drive same GPIO from two clients
- // gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>;
- // enable-active-high;
+ /*
+ * TODO: make it possible to drive same GPIO from two clients
+ * gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>;
+ * enable-active-high;
+ */
};
cam0_dvdd_1v2: reg_cam0_dvdd_1v2 {
@@ -195,9 +199,11 @@
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <500000>;
- // TODO: make it possible to drive same GPIO from two clients
- // gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>;
- // enable-active-high;
+ /*
+ * TODO: make it possible to drive same GPIO from two clients
+ * gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ * enable-active-high;
+ */
};
vbat: vbat-regulator {
@@ -649,9 +655,13 @@
};
};
+&pmi8998_rradc {
+ status = "okay";
+};
+
/* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */
&q6afedai {
- qi2s@22 {
+ dai@22 {
reg = <QUATERNARY_MI2S_RX>;
qcom,sd-lines = <0 1 2 3>;
};
@@ -986,6 +996,8 @@
&uart6 {
status = "okay";
+ pinctrl-0 = <&qup_uart6_4pin>;
+
bluetooth {
compatible = "qcom,wcn3990-bt";
@@ -1076,7 +1088,7 @@
status = "okay";
};
-&wcd9340{
+&wcd9340 {
pinctrl-0 = <&wcd_intr_default>;
pinctrl-names = "default";
clock-names = "extclk";
@@ -1089,7 +1101,7 @@
vdd-io-supply = <&vreg_s4a_1p8>;
swm: swm@c85 {
- left_spkr: wsa8810-left{
+ left_spkr: speaker@0,1 {
compatible = "sdw10217201000";
reg = <0 1>;
powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>;
@@ -1098,7 +1110,7 @@
#sound-dai-cells = <0>;
};
- right_spkr: wsa8810-right{
+ right_spkr: speaker@0,2 {
compatible = "sdw10217201000";
powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>;
reg = <0 2>;
@@ -1123,10 +1135,13 @@
/* PINCTRL - additions to nodes defined in sdm845.dtsi */
&qup_spi2_default {
- drive-strength = <16>;
+ pinconf {
+ pins = "gpio27", "gpio28", "gpio29", "gpio30";
+ drive-strength = <16>;
+ };
};
-&qup_uart3_default{
+&qup_uart3_default {
pinmux {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "qup3";
@@ -1141,29 +1156,6 @@
};
};
-&qup_uart6_default {
- pinmux {
- pins = "gpio45", "gpio46", "gpio47", "gpio48";
- function = "qup6";
- };
-
- cts {
- pins = "gpio45";
- bias-disable;
- };
-
- rts-tx {
- pins = "gpio46", "gpio47";
- drive-strength = <2>;
- bias-disable;
- };
-
- rx {
- pins = "gpio48";
- bias-pull-up;
- };
-};
-
&qup_uart9_default {
pinconf-tx {
pins = "gpio4";
@@ -1182,105 +1174,6 @@
};
-&cci {
- status = "okay";
-};
-
-&camss {
- vdda-phy-supply = <&vreg_l1a_0p875>;
- vdda-pll-supply = <&vreg_l26a_1p2>;
-
- status = "ok";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- csiphy0_ep: endpoint {
- data-lanes = <0 1 2 3>;
- remote-endpoint = <&ov8856_ep>;
- };
- };
- };
-};
-
-&cci_i2c0 {
- camera@10 {
- compatible = "ovti,ov8856";
- reg = <0x10>;
-
- // CAM0_RST_N
- reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&cam0_default>;
-
- clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
- clock-names = "xvclk";
- clock-frequency = <19200000>;
-
- /* The &vreg_s4a_1p8 trace is powered on as a,
- * so it is represented by a fixed regulator.
- *
- * The 2.8V vdda-supply and 1.2V vddd-supply regulators
- * both have to be enabled through the power management
- * gpios.
- */
- dovdd-supply = <&vreg_lvs1a_1p8>;
- avdd-supply = <&cam0_avdd_2v8>;
- dvdd-supply = <&cam0_dvdd_1v2>;
-
- status = "ok";
-
- port {
- ov8856_ep: endpoint {
- link-frequencies = /bits/ 64
- <360000000 180000000>;
- data-lanes = <1 2 3 4>;
- remote-endpoint = <&csiphy0_ep>;
- };
- };
- };
-};
-
-&cci_i2c1 {
- camera@60 {
- compatible = "ovti,ov7251";
-
- // I2C address as per ov7251.txt linux documentation
- reg = <0x60>;
-
- // CAM3_RST_N
- enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&cam3_default>;
-
- clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
- clock-names = "xclk";
- clock-frequency = <24000000>;
-
- /* The &vreg_s4a_1p8 trace always powered on.
- *
- * The 2.8V vdda-supply regulator is enabled when the
- * vreg_s4a_1p8 trace is pulled high.
- * It too is represented by a fixed regulator.
- *
- * No 1.2V vddd-supply regulator is used.
- */
- vdddo-supply = <&vreg_lvs1a_1p8>;
- vdda-supply = <&cam3_avdd_2v8>;
-
- status = "disable";
-
- port {
- ov7251_ep: endpoint {
- data-lanes = <0 1>;
-// remote-endpoint = <&csiphy3_ep>;
- };
- };
- };
-};
-
/* PINCTRL - additions to nodes defined in sdm845.dtsi */
&qup_spi0_default {
config {
diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi
index 20f275f8694d..1eb423e4be24 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi
@@ -604,7 +604,7 @@
};
&pm8998_gpio {
- vol_up_pin_a: vol-up-active-pins {
+ vol_up_pin_a: vol-up-active-state {
pins = "gpio6";
function = "normal";
input-enable;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
index 392461c29e76..42cf4dd5ea28 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
@@ -19,7 +19,7 @@
/ {
aliases {
serial0 = &uart9;
- hsuart0 = &uart6;
+ serial1 = &uart6;
};
chosen {
@@ -50,7 +50,8 @@
};
reserved-memory {
- /* The rmtfs_mem needs to be guarded due to "XPU limitations"
+ /*
+ * The rmtfs_mem needs to be guarded due to "XPU limitations"
* it is otherwise possible for an allocation adjacent to the
* rmtfs_mem region to trigger an XPU violation, causing a crash.
*/
@@ -433,7 +434,7 @@
status = "okay";
};
-/* Modem/wifi*/
+/* Modem/wifi */
&mss_pil {
status = "okay";
firmware-name = "qcom/sdm845/oneplus6/mba.mbn", "qcom/sdm845/oneplus6/modem.mbn";
@@ -461,6 +462,10 @@
};
};
+&pmi8998_rradc {
+ status = "okay";
+};
+
&qupv3_id_1 {
status = "okay";
};
@@ -500,35 +505,11 @@
};
};
-/*
- * Prevent garbage data on bluetooth UART lines
- */
-&qup_uart6_default {
- pinmux {
- pins = "gpio45", "gpio46", "gpio47", "gpio48";
- function = "qup6";
- };
-
- cts {
- pins = "gpio45";
- bias-pull-down;
- };
-
- rts-tx {
- pins = "gpio46", "gpio47";
- drive-strength = <2>;
- bias-disable;
- };
-
- rx {
- pins = "gpio48";
- bias-pull-up;
- };
-};
-
&uart6 {
status = "okay";
+ pinctrl-0 = <&qup_uart6_4pin>;
+
bluetooth {
compatible = "qcom,wcn3990-bt";
diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts
new file mode 100644
index 000000000000..e742c27fe91f
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts
@@ -0,0 +1,460 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SDM845 Samsung S9 (SM-G9600) (starqltechn / star2qltechn) common device tree source
+ *
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sdm845.dtsi"
+
+/ {
+ chassis-type = "handset";
+ model = "Samsung Galaxy S9 SM-G9600";
+ compatible = "samsung,starqltechn", "qcom,sdm845";
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ framebuffer: framebuffer@9d400000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;//2400000
+ width = <1440>;
+ height = <2960>;
+ stride = <(1440 * 4)>;
+ format = "a8r8g8b8";
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ /*
+ * Apparently RPMh does not provide support for PM8998 S4 because it
+ * is always-on; model it as a fixed regulator.
+ */
+ vreg_s4a_1p8: pm8998-smps4 {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s4a_1p8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ vin-supply = <&vph_pwr>;
+ };
+
+ reserved-memory {
+ memory@9d400000 {
+ reg = <0x0 0x9d400000 0x0 0x02400000>;
+ no-map;
+ };
+
+ memory@a1300000 {
+ compatible = "ramoops";
+ reg = <0x0 0xa1300000 0x0 0x100000>;
+ record-size = <0x40000>;
+ console-size = <0x40000>;
+ ftrace-size = <0x40000>;
+ pmsg-size = <0x40000>;
+ };
+ };
+};
+
+
+&apps_rsc {
+ pm8998-rpmh-regulators {
+ compatible = "qcom,pm8998-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+ vdd-s11-supply = <&vph_pwr>;
+ vdd-s12-supply = <&vph_pwr>;
+ vdd-s13-supply = <&vph_pwr>;
+ vdd-l1-l27-supply = <&vreg_s7a_1p025>;
+ vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
+ vdd-l3-l11-supply = <&vreg_s7a_1p025>;
+ vdd-l4-l5-supply = <&vreg_s7a_1p025>;
+ vdd-l6-supply = <&vph_pwr>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
+ vdd-l26-supply = <&vreg_s3a_1p35>;
+ vin-lvs-1-2-supply = <&vreg_s4a_1p8>;
+
+ vreg_s2a_1p125: smps2 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ vreg_s3a_1p35: smps3 {
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ };
+
+ vreg_s5a_2p04: smps5 {
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2040000>;
+ };
+
+ vreg_s7a_1p025: smps7 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1028000>;
+ };
+
+ vdd_qusb_hs0:
+ vdda_hp_pcie_core:
+ vdda_mipi_csi0_0p9:
+ vdda_mipi_csi1_0p9:
+ vdda_mipi_csi2_0p9:
+ vdda_mipi_dsi0_pll:
+ vdda_mipi_dsi1_pll:
+ vdda_qlink_lv:
+ vdda_qlink_lv_ck:
+ vdda_qrefs_0p875:
+ vdda_pcie_core:
+ vdda_pll_cc_ebi01:
+ vdda_pll_cc_ebi23:
+ vdda_sp_sensor:
+ vdda_ufs1_core:
+ vdda_ufs2_core:
+ vdda_usb1_ss_core:
+ vdda_usb2_ss_core:
+ vreg_l1a_0p875: ldo1 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vddpx_10:
+ vreg_l2a_1p2: ldo2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-always-on;
+ };
+
+ vreg_l3a_1p0: ldo3 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_wcss_cx:
+ vdd_wcss_mx:
+ vdda_wcss_pll:
+ vreg_l5a_0p8: ldo5 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vddpx_13:
+ vreg_l6a_1p8: ldo6 {
+ regulator-min-microvolt = <1856000>;
+ regulator-max-microvolt = <1856000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7a_1p8: ldo7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8a_1p2: ldo8 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1248000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9a_1p8: ldo9 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10a_1p8: ldo10 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11a_1p0: ldo11 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1048000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_qfprom:
+ vdd_qfprom_sp:
+ vdda_apc1_cs_1p8:
+ vdda_gfx_cs_1p8:
+ vdda_qrefs_1p8:
+ vdda_qusb_hs0_1p8:
+ vddpx_11:
+ vreg_l12a_1p8: ldo12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vddpx_2:
+ vreg_l13a_2p95: ldo13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14a_1p88: ldo14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15a_1p8: ldo15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16a_2p7: ldo16 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2704000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17a_1p3: ldo17 {
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18a_2p7: ldo18 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l19a_3p0: ldo19 {
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l20a_2p95: ldo20 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l21a_2p95: ldo21 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l22a_2p85: ldo22 {
+ regulator-min-microvolt = <2864000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l23a_3p3: ldo23 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdda_qusb_hs0_3p1:
+ vreg_l24a_3p075: ldo24 {
+ regulator-min-microvolt = <3088000>;
+ regulator-max-microvolt = <3088000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l25a_3p3: ldo25 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdda_hp_pcie_1p2:
+ vdda_hv_ebi0:
+ vdda_hv_ebi1:
+ vdda_hv_ebi2:
+ vdda_hv_ebi3:
+ vdda_mipi_csi_1p25:
+ vdda_mipi_dsi0_1p2:
+ vdda_mipi_dsi1_1p2:
+ vdda_pcie_1p2:
+ vdda_ufs1_1p2:
+ vdda_ufs2_1p2:
+ vdda_usb1_ss_1p2:
+ vdda_usb2_ss_1p2:
+ vreg_l26a_1p2: ldo26 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l28a_3p0: ldo28 {
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_lvs1a_1p8: lvs1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vreg_lvs2a_1p8: lvs2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+
+ pm8005-rpmh-regulators {
+ compatible = "qcom,pm8005-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ vreg_s3c_0p6: smps3 {
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <600000>;
+ };
+ };
+};
+
+&gcc {
+ protected-clocks = <GCC_QSPI_CORE_CLK>,
+ <GCC_QSPI_CORE_CLK_SRC>,
+ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <GCC_LPASS_Q6_AXI_CLK>,
+ <GCC_LPASS_SWAY_CLK>;
+};
+
+&i2c10 {
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&uart9 {
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l20a_2p95>;
+ vcc-max-microamp = <600000>;
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vdda_ufs1_core>;
+ vdda-pll-supply = <&vdda_ufs1_1p2>;
+ status = "okay";
+};
+
+&sdhc_2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdc2_clk_state &sdc2_cmd_state &sdc2_data_state &sd_card_det_n_state>;
+ cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vreg_l21a_2p95>;
+ vqmmc-supply = <&vddpx_2>;
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ /* Until we have Type C hooked up we'll force this as peripheral. */
+ dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vdda_usb1_ss_core>;
+ vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
+ vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
+
+ qcom,imp-res-offset-value = <8>;
+ qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
+ qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
+ qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ vdda-phy-supply = <&vdda_usb1_ss_1p2>;
+ vdda-pll-supply = <&vdda_usb1_ss_core>;
+ status = "okay";
+};
+
+&wifi {
+ vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
+ vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
+ vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
+ vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <0 4>, <27 4>, <81 4>, <85 4>;
+
+ sdc2_clk_state: sdc2-clk-state {
+ pins = "sdc2_clk";
+ bias-disable;
+
+ /*
+ * It seems that mmc_test reports errors if drive
+ * strength is not 16 on clk, cmd, and data pins.
+ */
+ drive-strength = <16>;
+ };
+
+ sdc2_cmd_state: sdc2-cmd-state {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <16>;
+ };
+
+ sdc2_data_state: sdc2-data-state {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <16>;
+ };
+
+ sd_card_det_n_state: sd-card-det-n-state {
+ pins = "gpio126";
+ function = "gpio";
+ bias-pull-up;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
index 83261c9bb4f2..bb77ccfdc68c 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
@@ -23,6 +23,7 @@
aliases {
display0 = &framebuffer0;
serial0 = &uart9;
+ serial1 = &uart6;
};
chosen {
@@ -693,9 +694,17 @@
&uart6 {
status = "okay";
+ pinctrl-0 = <&qup_uart6_4pin>;
+
bluetooth {
compatible = "qcom,wcn3990-bt";
+ /*
+ * This path is relative to the qca/
+ * subdir under lib/firmware.
+ */
+ firmware-name = "axolotl/crnv21.bin";
+
vddio-supply = <&vreg_s4a_1p8>;
vddxo-supply = <&vreg_l7a_1p8>;
vddrf-supply = <&vreg_l17a_1p3>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi
index 51ee42e3c995..87dd0fc36747 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi
@@ -376,7 +376,7 @@
pinctrl-names = "default";
bus-width = <4>;
no-sdio;
- no-emmc;
+ no-mmc;
};
&tlmm {
diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi
index 0f470cf1ed1c..eb6b2b676eca 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi
@@ -26,8 +26,6 @@
/delete-node/ &rmtfs_mem;
/ {
- model = "Xiaomi Pocophone F1";
- compatible = "xiaomi,beryllium", "qcom,sdm845";
chassis-type = "handset";
/* required for bootloader to select correct board */
@@ -35,7 +33,7 @@
qcom,msm-id = <321 0x20001>;
aliases {
- hsuart0 = &uart6;
+ serial1 = &uart6;
};
gpio-keys {
@@ -221,8 +219,7 @@
status = "okay";
vdda-supply = <&vreg_l26a_1p2>;
- panel@0 {
- compatible = "tianma,fhd-video";
+ display_panel: panel@0 {
reg = <0>;
vddio-supply = <&vreg_l14a_1p8>;
vddpos-supply = <&lab>;
@@ -234,8 +231,10 @@
backlight = <&pmi8998_wled>;
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+
port {
- tianma_nt36672a_in_0: endpoint {
+ panel_in_0: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
@@ -243,7 +242,7 @@
};
&dsi0_out {
- remote-endpoint = <&tianma_nt36672a_in_0>;
+ remote-endpoint = <&panel_in_0>;
data-lanes = <0 1 2 3>;
};
@@ -336,9 +335,13 @@
};
};
+&pmi8998_rradc {
+ status = "okay";
+};
+
/* QUAT I2S Uses 1 I2S SD Line for audio on TAS2559/60 amplifiers */
&q6afedai {
- qi2s@22 {
+ dai@22 {
reg = <QUATERNARY_MI2S_RX>;
qcom,sd-lines = <0>;
};
@@ -481,6 +484,8 @@
&uart6 {
status = "okay";
+ pinctrl-0 = <&qup_uart6_4pin>;
+
bluetooth {
compatible = "qcom,wcn3990-bt";
@@ -567,28 +572,3 @@
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
vdd-3.3-ch1-supply = <&vreg_l23a_3p3>;
};
-
-/* PINCTRL - additions to nodes defined in sdm845.dtsi */
-
-&qup_uart6_default {
- pinmux {
- pins = "gpio45", "gpio46", "gpio47", "gpio48";
- function = "qup6";
- };
-
- cts {
- pins = "gpio45";
- bias-disable;
- };
-
- rts-tx {
- pins = "gpio46", "gpio47";
- drive-strength = <2>;
- bias-disable;
- };
-
- rx {
- pins = "gpio48";
- bias-pull-up;
- };
-};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts
new file mode 100644
index 000000000000..76931ebad065
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "sdm845-xiaomi-beryllium-common.dtsi"
+
+/ {
+ model = "Xiaomi Pocophone F1 (EBBG)";
+ compatible = "xiaomi,beryllium-ebbg", "qcom,sdm845";
+};
+
+&display_panel {
+ compatible = "ebbg,ft8719";
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts
new file mode 100644
index 000000000000..8e176111e599
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "sdm845-xiaomi-beryllium-common.dtsi"
+
+/ {
+ model = "Xiaomi Pocophone F1 (Tianma)";
+ compatible = "xiaomi,beryllium", "qcom,sdm845";
+};
+
+&display_panel {
+ compatible = "tianma,fhd-video";
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts
index afc17e4d403f..38ba809a95cd 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts
@@ -456,9 +456,6 @@
&i2c14 {
clock-frequency = <400000>;
- dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
- <&gpi_dma1 1 6 QCOM_GPI_I2C>;
- dma-names = "tx", "rx";
status = "okay";
touchscreen@20 {
@@ -544,8 +541,8 @@
};
&q6afedai {
- qi2s@22 {
- reg = <22>;
+ dai@22 {
+ reg = <QUATERNARY_MI2S_RX>;
qcom,sd-lines = <0>;
};
};
@@ -628,7 +625,7 @@
};
wcd_intr_default: wcd-intr-default {
- pins = "goui54";
+ pins = "gpio54";
function = "gpio";
input-enable;
bias-pull-down;
@@ -639,6 +636,8 @@
&uart6 {
status = "okay";
+ pinctrl-0 = <&qup_uart6_4pin>;
+
bluetooth {
compatible = "qcom,wcn3990-bt";
@@ -735,28 +734,3 @@
qcom,snoc-host-cap-skip-quirk;
status = "okay";
};
-
-/* PINCTRL - additions to nodes defined in sdm845.dtsi */
-
-&qup_uart6_default {
- pinmux {
- pins = "gpio45", "gpio46", "gpio47", "gpio48";
- function = "qup6";
- };
-
- cts {
- pins = "gpio45";
- bias-disable;
- };
-
- rts-tx {
- pins = "gpio46", "gpio47";
- drive-strength = <2>;
- bias-disable;
- };
-
- rx {
- pins = "gpio48";
- bias-pull-up;
- };
-};
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index d761da47220d..65032b94b46d 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -767,13 +767,13 @@
#size-cells = <0>;
qcom,intents = <512 20>;
- apr-service@3 {
+ service@3 {
reg = <APR_SVC_ADSP_CORE>;
compatible = "qcom,q6core";
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
};
- q6afe: apr-service@4 {
+ q6afe: service@4 {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
@@ -785,7 +785,7 @@
};
};
- q6asm: apr-service@7 {
+ q6asm: service@7 {
compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
@@ -798,7 +798,7 @@
};
};
- q6adm: apr-service@8 {
+ q6adm: service@8 {
compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
@@ -3008,6 +3008,28 @@
};
};
+ qup_uart6_4pin: qup-uart6-4pin-state {
+
+ cts-pins {
+ pins = "gpio45";
+ function = "qup6";
+ bias-pull-down;
+ };
+
+ rts-tx-pins {
+ pins = "gpio46", "gpio47";
+ function = "qup6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx-pins {
+ pins = "gpio48";
+ function = "qup6";
+ bias-pull-up;
+ };
+ };
+
qup_uart7_default: qup-uart7-default {
pinmux {
pins = "gpio95", "gpio96";
@@ -3823,33 +3845,29 @@
status = "disabled";
};
- slim: slim@171c0000 {
+ slim: slim-ngd@171c0000 {
compatible = "qcom,slim-ngd-v2.1.0";
reg = <0 0x171c0000 0 0x2c000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- qcom,apps-ch-pipes = <0x780000>;
- qcom,ea-pc = <0x270>;
- status = "okay";
- dmas = <&slimbam 3>, <&slimbam 4>,
- <&slimbam 5>, <&slimbam 6>;
- dma-names = "rx", "tx", "tx2", "rx2";
+ dmas = <&slimbam 3>, <&slimbam 4>;
+ dma-names = "rx", "tx";
iommus = <&apps_smmu 0x1806 0x0>;
#address-cells = <1>;
#size-cells = <0>;
- ngd@1 {
+ slim@1 {
reg = <1>;
#address-cells = <2>;
#size-cells = <0>;
- wcd9340_ifd: ifd@0{
+ wcd9340_ifd: ifd@0,0 {
compatible = "slim217,250";
reg = <0 0>;
};
- wcd9340: codec@1{
+ wcd9340: codec@1,0 {
compatible = "slim217,250";
reg = <1 0>;
slim-ifc-dev = <&wcd9340_ifd>;
@@ -3959,9 +3977,10 @@
};
usb_1_qmpphy: phy@88e9000 {
- compatible = "qcom,sdm845-qmp-usb3-phy";
+ compatible = "qcom,sdm845-qmp-usb3-dp-phy";
reg = <0 0x088e9000 0 0x18c>,
- <0 0x088e8000 0 0x10>;
+ <0 0x088e8000 0 0x38>,
+ <0 0x088ea000 0 0x40>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
@@ -3973,11 +3992,11 @@
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "com_aux";
- resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
- <&gcc GCC_USB3_PHY_PRIM_BCR>;
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
reset-names = "phy", "common";
- usb_1_ssphy: phy@88e9200 {
+ usb_1_ssphy: usb3-phy@88e9200 {
reg = <0 0x088e9200 0 0x128>,
<0 0x088e9400 0 0x200>,
<0 0x088e9c00 0 0x218>,
@@ -3990,6 +4009,16 @@
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
+
+ dp_phy: dp-phy@88ea200 {
+ reg = <0 0x088ea200 0 0x200>,
+ <0 0x088ea400 0 0x200>,
+ <0 0x088eaa00 0 0x200>,
+ <0 0x088ea600 0 0x200>,
+ <0 0x088ea800 0 0x200>;
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+ };
};
usb_2_qmpphy: phy@88eb000 {
@@ -4339,6 +4368,22 @@
ports {
#address-cells = <1>;
#size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ };
};
};
@@ -4483,13 +4528,20 @@
port@0 {
reg = <0>;
- dpu_intf1_out: endpoint {
- remote-endpoint = <&dsi0_in>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&dp_in>;
};
};
port@1 {
reg = <1>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
dpu_intf2_out: endpoint {
remote-endpoint = <&dsi1_in>;
};
@@ -4521,6 +4573,77 @@
};
};
+ mdss_dp: displayport-controller@ae90000 {
+ status = "disabled";
+ compatible = "qcom,sdm845-dp";
+
+ reg = <0 0xae90000 0 0x200>,
+ <0 0xae90200 0 0x200>,
+ <0 0xae90400 0 0x600>,
+ <0 0xae90a00 0 0x600>,
+ <0 0xae91000 0 0x600>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <12>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ clock-names = "core_iface", "core_aux", "ctrl_link",
+ "ctrl_link_iface", "stream_pixel";
+ #clock-cells = <1>;
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
+ phys = <&dp_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd SDM845_CX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ dp_in: endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_out: endpoint { };
+ };
+ };
+
+ dp_opp_table: dp-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-162000000 {
+ opp-hz = /bits/ 64 <162000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
dsi0: dsi@ae94000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0 0x0ae94000 0 0x400>;
@@ -4548,7 +4671,6 @@
power-domains = <&rpmhpd SDM845_CX>;
phys = <&dsi0_phy>;
- phy-names = "dsi";
status = "disabled";
@@ -4574,7 +4696,7 @@
};
};
- dsi0_phy: dsi-phy@ae94400 {
+ dsi0_phy: phy@ae94400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0 0x0ae94400 0 0x200>,
<0 0x0ae94600 0 0x280>,
@@ -4620,7 +4742,6 @@
power-domains = <&rpmhpd SDM845_CX>;
phys = <&dsi1_phy>;
- phy-names = "dsi";
status = "disabled";
@@ -4646,7 +4767,7 @@
};
};
- dsi1_phy: dsi-phy@ae96400 {
+ dsi1_phy: phy@ae96400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0 0x0ae96400 0 0x200>,
<0 0x0ae96600 0 0x280>,
@@ -4812,8 +4933,8 @@
<&dsi0_phy 1>,
<&dsi1_phy 0>,
<&dsi1_phy 1>,
- <0>,
- <0>;
+ <&dp_phy 0>,
+ <&dp_phy 1>;
clock-names = "bi_tcxo",
"gcc_disp_gpll0_clk_src",
"gcc_disp_gpll0_div_clk_src",
@@ -5197,7 +5318,7 @@
};
osm_l3: interconnect@17d41000 {
- compatible = "qcom,sdm845-osm-l3";
+ compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
reg = <0 0x17d41000 0 0x1400>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
index be59a8ba9c1f..f32b7445f7c9 100644
--- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
+++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
@@ -487,8 +487,10 @@
};
&qup_i2c12_default {
- drive-strength = <2>;
- bias-disable;
+ pinmux {
+ drive-strength = <2>;
+ bias-disable;
+ };
};
&qup_uart6_default {
@@ -783,7 +785,7 @@
qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
swm: swm@c85 {
- left_spkr: wsa8810-left{
+ left_spkr: speaker@0,3 {
compatible = "sdw10217211000";
reg = <0 3>;
powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>;
@@ -792,7 +794,7 @@
#sound-dai-cells = <0>;
};
- right_spkr: wsa8810-right{
+ right_spkr: speaker@0,4 {
compatible = "sdw10217211000";
powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>;
reg = <0 4>;
diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts
index f954fe5cb61a..daca1e0ad62a 100644
--- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts
+++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts
@@ -43,7 +43,7 @@
#size-cells = <2>;
ranges;
- // Firmware initialized the display at 1280p instead of 1440p
+ /* Firmware initialized the display at 1280p instead of 1440p */
framebuffer0: framebuffer@80400000 {
compatible = "simple-framebuffer";
reg = <0 0x80400000 0 (1920 * 1280 * 4)>;
@@ -124,7 +124,7 @@
};
&adsp_pas {
- firmware-name = "qcom/samsung/w737/qcadsp850.mbn";
+ firmware-name = "qcom/sdm850/samsung/w737/qcadsp850.mbn";
status = "okay";
};
@@ -336,7 +336,7 @@
};
&cdsp_pas {
- firmware-name = "qcom/samsung/w737/qccdsp850.mbn";
+ firmware-name = "qcom/sdm850/samsung/w737/qccdsp850.mbn";
status = "okay";
};
@@ -385,7 +385,7 @@
&ipa {
status = "okay";
memory-region = <&ipa_fw_mem>;
- firmware-name = "qcom/samsung/w737/ipa_fws.elf";
+ firmware-name = "qcom/sdm850/samsung/w737/ipa_fws.elf";
};
/* No idea why it causes an SError when enabled */
@@ -395,7 +395,7 @@
&mss_pil {
status = "okay";
- firmware-name = "qcom/samsung/w737/qcdsp1v2850.mbn", "qcom/samsung/w737/qcdsp2850.mbn";
+ firmware-name = "qcom/sdm850/samsung/w737/qcdsp1v2850.mbn", "qcom/sdm850/samsung/w737/qcdsp2850.mbn";
};
&qup_i2c10_default {
@@ -415,8 +415,10 @@
};
&qup_i2c12_default {
- drive-strength = <2>;
- bias-disable;
+ pinmux {
+ drive-strength = <2>;
+ bias-disable;
+ };
};
&qup_uart6_default {
@@ -574,7 +576,7 @@
};
pen_rst_l: pen-rst-l {
- pinmux {
+ pinmux {
pins = "gpio21";
function = "gpio";
};
@@ -696,7 +698,7 @@
&venus {
status = "okay";
- firmware-name = "qcom/samsung/w737/qcvss850.mbn";
+ firmware-name = "qcom/sdm850/samsung/w737/qcvss850.mbn";
};
&wcd9340{
@@ -715,7 +717,7 @@
qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
swm: swm@c85 {
- left_spkr: wsa8810-left{
+ left_spkr: speaker@0,3 {
compatible = "sdw10217211000";
reg = <0 3>;
powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>;
@@ -724,7 +726,7 @@
#sound-dai-cells = <0>;
};
- right_spkr: wsa8810-right{
+ right_spkr: speaker@0,4 {
compatible = "sdw10217211000";
powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>;
reg = <0 4>;
diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
new file mode 100644
index 000000000000..a3f1c7c41fd7
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "sm4250.dtsi"
+
+/ {
+ model = "OnePlus Nord N100";
+ compatible = "oneplus,billie2", "qcom,sm4250";
+
+ /* required for bootloader to select correct board */
+ qcom,msm-id = <0x1a1 0x10000 0x1bc 0x10000>;
+ qcom,board-id = <0x1000b 0x00>;
+
+ aliases {
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ stdout-path = "framebuffer0";
+
+ framebuffer0: framebuffer@9d400000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x5c000000 0 (1600 * 720 * 4)>;
+ width = <720>;
+ height = <1600>;
+ stride = <(720 * 4)>;
+ format = "a8r8g8b8";
+ };
+ };
+};
+
+&reserved_memory {
+ bootloader_log_mem: memory@5fff7000 {
+ reg = <0x0 0x5fff7000 0x0 0x8000>;
+ no-map;
+ };
+
+ ramoops@cbe00000 {
+ compatible = "ramoops";
+ reg = <0x0 0xcbe00000 0x0 0x400000>;
+ record-size = <0x40000>;
+ pmsg-size = <0x200000>;
+ console-size = <0x40000>;
+ ftrace-size = <0x40000>;
+ };
+
+ param_mem: memory@cc200000 {
+ reg = <0x0 0xcc200000 0x0 0x100000>;
+ no-map;
+ };
+
+ mtp_mem: memory@cc300000 {
+ reg = <0x00 0xcc300000 0x00 0xb00000>;
+ no-map;
+ };
+};
+
+&rpm_requests {
+ regulators-0 {
+ compatible = "qcom,rpm-pm6125-regulators";
+
+ vreg_s6a: s6 {
+ regulator-min-microvolt = <320000>;
+ regulator-max-microvolt = <1456000>;
+ };
+
+ vreg_s7a: s7 {
+ regulator-min-microvolt = <1280000>;
+ regulator-max-microvolt = <2040000>;
+ };
+
+ vreg_s8a: s8 {
+ regulator-min-microvolt = <1064000>;
+ regulator-max-microvolt = <1304000>;
+ };
+
+ vreg_l1a: l1 {
+ regulator-min-microvolt = <952000>;
+ regulator-max-microvolt = <1152000>;
+ };
+
+ vreg_l4a: l4 {
+ regulator-min-microvolt = <488000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ vreg_l5a: l5 {
+ regulator-min-microvolt = <1648000>;
+ regulator-max-microvolt = <3056000>;
+ };
+
+ vreg_l6a: l6 {
+ regulator-min-microvolt = <576000>;
+ regulator-max-microvolt = <656000>;
+ };
+
+ vreg_l7a: l7 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1304000>;
+ };
+
+ vreg_l8a: l8 {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <728000>;
+ };
+
+ vreg_l9a: l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ vreg_l10a: l10 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1904000>;
+ };
+
+ vreg_l11a: l11 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1952000>;
+ };
+
+ vreg_l12a: l12 {
+ regulator-min-microvolt = <1624000>;
+ regulator-max-microvolt = <1984000>;
+ };
+
+ vreg_l13a: l13 {
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <1952000>;
+ };
+
+ vreg_l14a: l14 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1904000>;
+ };
+
+ vreg_l15a: l15 {
+ regulator-min-microvolt = <2920000>;
+ regulator-max-microvolt = <3232000>;
+ };
+
+ vreg_l16a: l16 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1904000>;
+ };
+
+ vreg_l17a: l17 {
+ regulator-min-microvolt = <1152000>;
+ regulator-max-microvolt = <1304000>;
+ };
+
+ vreg_l18a: l18 {
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1304000>;
+ };
+
+ vreg_l19a: l19 {
+ regulator-min-microvolt = <1624000>;
+ regulator-max-microvolt = <3304000>;
+ };
+
+ vreg_l20a: l20 {
+ regulator-min-microvolt = <1624000>;
+ regulator-max-microvolt = <3304000>;
+ };
+
+ vreg_l21a: l21 {
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <3544000>;
+ };
+
+ vreg_l22a: l22 {
+ regulator-min-microvolt = <2952000>;
+ regulator-max-microvolt = <3304000>;
+ };
+
+ vreg_l23a: l23 {
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3304000>;
+ };
+
+ vreg_l24a: l24 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <3544000>;
+ };
+ };
+};
+
+&sleep_clk {
+ clock-frequency = <32764>;
+};
+
+&sdhc_2 {
+ vmmc-supply = <&vreg_l22a>;
+ vqmmc-supply = <&vreg_l5a>;
+
+ cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
+
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <14 4>;
+};
+
+&ufs_mem_hc {
+ vcc-supply = <&vreg_l24a>;
+ vcc-max-microamp = <600000>;
+ vccq2-supply = <&vreg_l11a>;
+ vccq2-max-microamp = <600000>;
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l4a>;
+ vdda-pll-supply = <&vreg_l12a>;
+ vddp-ref-clk-supply = <&vreg_l18a>;
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l4a>;
+ vdda-pll-supply = <&vreg_l12a>;
+ vdda-phy-dpdm-supply = <&vreg_l15a>;
+ status = "okay";
+};
+
+&xo_board {
+ clock-frequency = <19200000>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sm4250.dtsi b/arch/arm64/boot/dts/qcom/sm4250.dtsi
new file mode 100644
index 000000000000..c5add8f44fc0
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm4250.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com>
+ */
+
+#include "sm6115.dtsi"
+
+&CPU0 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU1 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU2 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU3 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU4 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU5 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU6 {
+ compatible = "qcom,kryo240";
+};
+
+&CPU7 {
+ compatible = "qcom,kryo240";
+};
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
new file mode 100644
index 000000000000..572bf04adf90
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -0,0 +1,1425 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com>
+ */
+
+#include <dt-bindings/clock/qcom,gcc-sm6115.h>
+#include <dt-bindings/clock/qcom,sm6115-dispcc.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x0>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x1>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x2>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x3>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ };
+
+ CPU4: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ next-level-cache = <&L2_1>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ L2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ CPU5: cpu@101 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x101>;
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ };
+
+ CPU6: cpu@102 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x102>;
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ };
+
+ CPU7: cpu@103 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x103>;
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+
+ core1 {
+ cpu = <&CPU5>;
+ };
+
+ core2 {
+ cpu = <&CPU6>;
+ };
+
+ core3 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+ };
+
+ firmware {
+ scm: scm {
+ compatible = "qcom,scm-sm6115", "qcom,scm";
+ #reset-cells = <1>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0 0x80000000 0 0>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: memory@45700000 {
+ reg = <0x0 0x45700000 0x0 0x600000>;
+ no-map;
+ };
+
+ xbl_aop_mem: memory@45e00000 {
+ reg = <0x0 0x45e00000 0x0 0x140000>;
+ no-map;
+ };
+
+ sec_apps_mem: memory@45fff000 {
+ reg = <0x0 0x45fff000 0x0 0x1000>;
+ no-map;
+ };
+
+ smem_mem: memory@46000000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x46000000 0x0 0x200000>;
+ no-map;
+
+ hwlocks = <&tcsr_mutex 3>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ };
+
+ cdsp_sec_mem: memory@46200000 {
+ reg = <0x0 0x46200000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ pil_modem_mem: memory@4ab00000 {
+ reg = <0x0 0x4ab00000 0x0 0x6900000>;
+ no-map;
+ };
+
+ pil_video_mem: memory@51400000 {
+ reg = <0x0 0x51400000 0x0 0x500000>;
+ no-map;
+ };
+
+ wlan_msa_mem: memory@51900000 {
+ reg = <0x0 0x51900000 0x0 0x100000>;
+ no-map;
+ };
+
+ pil_cdsp_mem: memory@51a00000 {
+ reg = <0x0 0x51a00000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ pil_adsp_mem: memory@53800000 {
+ reg = <0x0 0x53800000 0x0 0x2800000>;
+ no-map;
+ };
+
+ pil_ipa_fw_mem: memory@56100000 {
+ reg = <0x0 0x56100000 0x0 0x10000>;
+ no-map;
+ };
+
+ pil_ipa_gsi_mem: memory@56110000 {
+ reg = <0x0 0x56110000 0x0 0x5000>;
+ no-map;
+ };
+
+ pil_gpu_mem: memory@56115000 {
+ reg = <0x0 0x56115000 0x0 0x2000>;
+ no-map;
+ };
+
+ cont_splash_memory: memory@5c000000 {
+ reg = <0x0 0x5c000000 0x0 0x00f00000>;
+ no-map;
+ };
+
+ dfps_data_memory: memory@5cf00000 {
+ reg = <0x0 0x5cf00000 0x0 0x0100000>;
+ no-map;
+ };
+
+ removed_mem: memory@60000000 {
+ reg = <0x0 0x60000000 0x0 0x3900000>;
+ no-map;
+ };
+ };
+
+ rpm-glink {
+ compatible = "qcom,glink-rpm";
+
+ interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
+
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-sm6115";
+ qcom,glink-channels = "rpm_requests";
+
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc";
+ #clock-cells = <1>;
+ };
+
+ rpmpd: power-controller {
+ compatible = "qcom,sm6115-rpmpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmpd_opp_table>;
+
+ rpmpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmpd_opp_min_svs: opp1 {
+ opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
+ };
+
+ rpmpd_opp_low_svs: opp2 {
+ opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
+ };
+
+ rpmpd_opp_svs: opp3 {
+ opp-level = <RPM_SMD_LEVEL_SVS>;
+ };
+
+ rpmpd_opp_svs_plus: opp4 {
+ opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
+ };
+
+ rpmpd_opp_nom: opp5 {
+ opp-level = <RPM_SMD_LEVEL_NOM>;
+ };
+
+ rpmpd_opp_nom_plus: opp6 {
+ opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
+ };
+
+ rpmpd_opp_turbo: opp7 {
+ opp-level = <RPM_SMD_LEVEL_TURBO>;
+ };
+
+ rpmpd_opp_turbo_plus: opp8 {
+ opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
+ };
+ };
+ };
+ };
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+
+ tcsr_mutex: hwlock@340000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x00340000 0x20000>;
+ #hwlock-cells = <1>;
+ };
+
+ tlmm: pinctrl@500000 {
+ compatible = "qcom,sm6115-tlmm";
+ reg = <0x00500000 0x400000>, <0x00900000 0x400000>, <0x00d00000 0x400000>;
+ reg-names = "west", "south", "east";
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ gpio-ranges = <&tlmm 0 0 121>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ qup_i2c0_default: qup-i2c0-default-state {
+ pins = "gpio0", "gpio1";
+ function = "qup0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c1_default: qup-i2c1-default-state {
+ pins = "gpio4", "gpio5";
+ function = "qup1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c2_default: qup-i2c2-default-state {
+ pins = "gpio6", "gpio7";
+ function = "qup2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c3_default: qup-i2c3-default-state {
+ pins = "gpio8", "gpio9";
+ function = "qup3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c4_default: qup-i2c4-default-state {
+ pins = "gpio12", "gpio13";
+ function = "qup4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c5_default: qup-i2c5-default-state {
+ pins = "gpio14", "gpio15";
+ function = "qup5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi0_default: qup-spi0-default-state {
+ pins = "gpio0", "gpio1","gpio2", "gpio3";
+ function = "qup0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi1_default: qup-spi1-default-state {
+ pins = "gpio4", "gpio5", "gpio69", "gpio70";
+ function = "qup1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi2_default: qup-spi2-default-state {
+ pins = "gpio6", "gpio7", "gpio71", "gpio80";
+ function = "qup2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi3_default: qup-spi3-default-state {
+ pins = "gpio8", "gpio9", "gpio10", "gpio11";
+ function = "qup3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi4_default: qup-spi4-default-state {
+ pins = "gpio12", "gpio13", "gpio96", "gpio97";
+ function = "qup4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi5_default: qup-spi5-default-state {
+ pins = "gpio14", "gpio15", "gpio16", "gpio17";
+ function = "qup5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sdc1_state_on: sdc1-on-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_state_off: sdc1-off-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc2_state_on: sdc2-on-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ sd-cd-pins {
+ pins = "gpio88";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
+
+ sdc2_state_off: sdc2-off-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ sd-cd-pins {
+ pins = "gpio88";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <2>;
+ };
+ };
+ };
+
+ gcc: clock-controller@1400000 {
+ compatible = "qcom,gcc-sm6115";
+ reg = <0x01400000 0x1f0000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
+ clock-names = "bi_tcxo", "sleep_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ usb_1_hsphy: phy@1613000 {
+ compatible = "qcom,sm6115-qusb2-phy";
+ reg = <0x01613000 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ nvmem-cells = <&qusb2_hstx_trim>;
+
+ status = "disabled";
+ };
+
+ qfprom@1b40000 {
+ compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
+ reg = <0x01b40000 0x7000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qusb2_hstx_trim: hstx-trim@25b {
+ reg = <0x25b 0x1>;
+ bits = <1 4>;
+ };
+ };
+
+ rng: rng@1b53000 {
+ compatible = "qcom,prng-ee";
+ reg = <0x01b53000 0x1000>;
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "core";
+ };
+
+ spmi_bus: spmi@1c40000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x01c40000 0x1100>,
+ <0x01e00000 0x2000000>,
+ <0x03e00000 0x100000>,
+ <0x03f00000 0xa0000>,
+ <0x01c0a000 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
+ tsens0: thermal-sensor@4410000 {
+ compatible = "qcom,sm6115-tsens", "qcom,tsens-v2";
+ reg = <0x04411000 0x1ff>, /* TM */
+ <0x04410000 0x8>; /* SROT */
+ #qcom,sensors = <16>;
+ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ rpm_msg_ram: sram@45f0000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0x045f0000 0x7000>;
+ };
+
+ sram@4690000 {
+ compatible = "qcom,rpm-stats";
+ reg = <0x04690000 0x10000>;
+ };
+
+ sdhc_1: mmc@4744000 {
+ compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x04744000 0x1000>, <0x04745000 0x1000>, <0x04748000 0x8000>;
+ reg-names = "hc", "cqhci", "ice";
+
+ interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&xo_board>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "iface", "core", "xo", "ice";
+
+ pinctrl-0 = <&sdc1_state_on>;
+ pinctrl-1 = <&sdc1_state_off>;
+ pinctrl-names = "default", "sleep";
+
+ bus-width = <8>;
+ status = "disabled";
+ };
+
+ sdhc_2: mmc@4784000 {
+ compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x04784000 0x1000>;
+ reg-names = "hc";
+
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>;
+ clock-names = "iface", "core", "xo";
+
+ pinctrl-0 = <&sdc2_state_on>;
+ pinctrl-1 = <&sdc2_state_off>;
+ pinctrl-names = "default", "sleep";
+
+ power-domains = <&rpmpd SM6115_VDDCX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+ iommus = <&apps_smmu 0x00a0 0x0>;
+ resets = <&gcc GCC_SDCC2_BCR>;
+
+ bus-width = <4>;
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
+ status = "disabled";
+
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ };
+ };
+ };
+
+ ufs_mem_hc: ufs@4804000 {
+ compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
+ reg = <0x04804000 0x3000>, <0x04810000 0x8000>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufs_mem_phy_lanes>;
+ phy-names = "ufsphy";
+ lanes-per-direction = <1>;
+ #reset-cells = <1>;
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+ iommus = <&apps_smmu 0x100 0>;
+
+ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+ clock-names = "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "ice_core_clk";
+
+ freq-table-hz = <50000000 200000000>,
+ <0 0>,
+ <0 0>,
+ <37500000 150000000>,
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+
+ status = "disabled";
+ };
+
+ ufs_mem_phy: phy@4807000 {
+ compatible = "qcom,sm6115-qmp-ufs-phy";
+ reg = <0x04807000 0x1c4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+ clock-names = "ref", "ref_aux";
+
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+ status = "disabled";
+
+ ufs_mem_phy_lanes: phy@4807400 {
+ reg = <0x4807400 0x098>,
+ <0x4807600 0x130>,
+ <0x4807c00 0x16c>;
+ #phy-cells = <0>;
+ };
+ };
+
+ gpi_dma0: dma-controller@4a00000 {
+ compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x04a00000 0x60000>;
+ interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <10>;
+ dma-channel-mask = <0xf>;
+ iommus = <&apps_smmu 0xf6 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
+ qupv3_id_0: geniqup@4ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x04ac0000 0x2000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ iommus = <&apps_smmu 0xe3 0x0>;
+ ranges;
+ status = "disabled";
+
+ i2c0: i2c@4a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x04a80000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c0_default>;
+ interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi0: spi@4a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x04a80000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi0_default>;
+ interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@4a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x04a84000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c1_default>;
+ interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@4a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x04a84000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi1_default>;
+ interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@4a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x04a88000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c2_default>;
+ interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@4a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x04a88000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi2_default>;
+ interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@4a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x04a8c000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c3_default>;
+ interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi3: spi@4a8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x04a8c000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi3_default>;
+ interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@4a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x04a90000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c4_default>;
+ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi4: spi@4a90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x04a90000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi4_default>;
+ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@4a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x04a94000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c5_default>;
+ interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi5: spi@4a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x04a94000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi5_default>;
+ interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ usb_1: usb@4ef8800 {
+ compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
+ reg = <0x04ef8800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
+ clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <66666667>;
+
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq", "ss_phy_irq";
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+ power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+ qcom,select-utmi-as-pipe-clk;
+ status = "disabled";
+
+ usb_1_dwc3: usb@4e00000 {
+ compatible = "snps,dwc3";
+ reg = <0x04e00000 0xcd00>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb_1_hsphy>;
+ phy-names = "usb2-phy";
+ iommus = <&apps_smmu 0x120 0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x10>;
+ snps,usb3_lpm_capable;
+ maximum-speed = "high-speed";
+ dr_mode = "peripheral";
+ };
+ };
+
+ mdss: display-subsystem@5e00000 {
+ compatible = "qcom,sm6115-mdss";
+ reg = <0x05e00000 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x420 0x2>,
+ <&apps_smmu 0x421 0x0>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ status = "disabled";
+
+ mdp: display-controller@5e01000 {
+ compatible = "qcom,sm6115-dpu";
+ reg = <0x05e01000 0x8f000>,
+ <0x05eb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "iface",
+ "core",
+ "lut",
+ "rot",
+ "vsync";
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmpd SM6115_VDDCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmpd_opp_min_svs>;
+ };
+
+ opp-192000000 {
+ opp-hz = /bits/ 64 <192000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ };
+
+ opp-256000000 {
+ opp-hz = /bits/ 64 <256000000>;
+ required-opps = <&rpmpd_opp_svs>;
+ };
+
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ required-opps = <&rpmpd_opp_svs_plus>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ };
+ };
+ };
+
+ dsi0: dsi@5e94000 {
+ compatible = "qcom,dsi-ctrl-6g-qcm2290";
+ reg = <0x05e94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmpd SM6115_VDDCX>;
+ phys = <&dsi0_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+
+ dsi_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmpd_opp_min_svs>;
+ };
+
+ opp-164000000 {
+ opp-hz = /bits/ 64 <164000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ };
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmpd_opp_svs>;
+ };
+ };
+ };
+
+ dsi0_phy: phy@5e94400 {
+ compatible = "qcom,dsi-phy-14nm-2290";
+ reg = <0x05e94400 0x100>,
+ <0x05e94500 0x300>,
+ <0x05e94800 0x188>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+ };
+
+ dispcc: clock-controller@5f00000 {
+ compatible = "qcom,sm6115-dispcc";
+ reg = <0x05f00000 0x20000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&sleep_clk>,
+ <&dsi0_phy 0>,
+ <&dsi0_phy 1>,
+ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ apps_smmu: iommu@c600000 {
+ compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0c600000 0x80000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wifi: wifi@c800000 {
+ compatible = "qcom,wcn3990-wifi";
+ reg = <0x0c800000 0x800000>;
+ reg-names = "membase";
+ memory-region = <&wlan_msa_mem>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x1a0 0x1>;
+ qcom,msa-fixed-perm;
+ status = "disabled";
+ };
+
+ apcs_glb: mailbox@f111000 {
+ compatible = "qcom,sm6115-apcs-hmss-global";
+ reg = <0x0f111000 0x1000>;
+
+ #mbox-cells = <1>;
+ };
+
+ timer@f120000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0f120000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <19200000>;
+
+ frame@f121000 {
+ reg = <0x0f121000 0x1000>, <0x0f122000 0x1000>;
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ frame@f123000 {
+ reg = <0x0f123000 0x1000>;
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ frame@f124000 {
+ reg = <0x0f124000 0x1000>;
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ frame@f125000 {
+ reg = <0x0f125000 0x1000>;
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ frame@f126000 {
+ reg = <0x0f126000 0x1000>;
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ frame@f127000 {
+ reg = <0x0f127000 0x1000>;
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ frame@f128000 {
+ reg = <0x0f128000 0x1000>;
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ intc: interrupt-controller@f200000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0f200000 0x10000>, <0x0f300000 0x100000>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x20000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cpufreq_hw: cpufreq@f521000 {
+ compatible = "qcom,cpufreq-hw";
+ reg = <0x0f521000 0x1000>, <0x0f523000 0x1000>;
+
+ reg-names = "freq-domain0", "freq-domain1";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #freq-domain-cells = <1>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
index 6a8b88cc4385..0de6c5b7f742 100644
--- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
+++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
@@ -6,9 +6,10 @@
/dts-v1/;
#include "sm6125.dtsi"
+#include "pm6125.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
/* required for bootloader to select correct board */
@@ -80,15 +81,175 @@
no-map;
};
};
+
+ thermal-zones {
+ rf-pa0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm6125_adc_tm 0>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ quiet-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <5000>;
+ thermal-sensors = <&pm6125_adc_tm 1>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ xo-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm6125_adc_tm 2>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ rf-pa1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm6125_adc_tm 3>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+ };
};
&hsusb_phy1 {
status = "okay";
};
+&pm6125_adc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm &rf_pa1_therm>;
+
+ rf-pa0-therm@4d {
+ reg = <ADC5_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ quiet-therm@4e {
+ reg = <ADC5_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ camera-flash-therm@52 {
+ reg = <ADC5_GPIO1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ emmc-ufs-therm@54 {
+ reg = <ADC5_GPIO3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ rf-pa1-therm@55 {
+ reg = <ADC5_GPIO4_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm6125_adc_tm {
+ status = "okay";
+
+ rf-pa0-therm@0 {
+ reg = <0>;
+ io-channels = <&pm6125_adc ADC5_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ quiet-therm@1 {
+ reg = <1>;
+ io-channels = <&pm6125_adc ADC5_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ xo-therm@2 {
+ reg = <2>;
+ io-channels = <&pm6125_adc ADC5_XO_THERM_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ rf-pa1-therm@3 {
+ reg = <3>;
+ io-channels = <&pm6125_adc ADC5_GPIO4_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+};
+
+&pm6125_gpio {
+ camera_flash_therm: camera-flash-therm-state {
+ pins = "gpio3";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-high-impedance;
+ };
+
+ emmc_ufs_therm: emmc-ufs-therm-state {
+ pins = "gpio6";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-high-impedance;
+ };
+
+ rf_pa1_therm: rf-pa1-therm-state {
+ pins = "gpio7";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-high-impedance;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+ linux,code = <KEY_VOLUMEUP>;
+};
+
&sdc2_off_state {
sd-cd-pins {
pins = "gpio98";
+ function = "gpio";
drive-strength = <2>;
bias-disable;
};
@@ -97,6 +258,7 @@
&sdc2_on_state {
sd-cd-pins {
pins = "gpio98";
+ function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 1fe3fa3ad877..7e25a4f85594 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -407,13 +407,13 @@
};
sdc2_on_state: sdc2-on-state {
- clk {
+ clk-pins {
pins = "sdc2_clk";
drive-strength = <16>;
bias-disable;
};
- cmd-pins-pins {
+ cmd-pins {
pins = "sdc2_cmd";
drive-strength = <10>;
bias-pull-up;
@@ -458,7 +458,7 @@
sdhc_1: mmc@4744000 {
compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
- reg-names = "hc", "core";
+ reg-names = "hc", "cqhci";
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
@@ -476,6 +476,8 @@
bus-width = <8>;
non-removable;
+ supports-cqe;
+
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts
index 36911b9a5c04..94f77d376662 100644
--- a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts
+++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts
@@ -4,7 +4,10 @@
*/
/dts-v1/;
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm6350.dtsi"
+#include "pm6350.dtsi"
/ {
model = "Sony Xperia 10 III";
@@ -28,16 +31,348 @@
clocks = <&gcc GCC_DISP_AXI_CLK>;
};
};
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_state>;
+
+ key-volume-down {
+ label = "volume_down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ gpios = <&pm6350_gpios 2 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ touch_en_vreg: touch-en-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_en_vreg";
+ gpio = <&tlmm 10 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&pm6350_l6>;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm6350-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ pm6350_s1: smps1 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_s2: smps2 {
+ regulator-min-microvolt = <1503000>;
+ regulator-max-microvolt = <2048000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_l2: ldo2 {
+ regulator-min-microvolt = <1503000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_l3: ldo3 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_l4: ldo4 {
+ regulator-min-microvolt = <352000>;
+ regulator-max-microvolt = <801000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_l5: ldo5 {
+ regulator-min-microvolt = <1503000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_l6: ldo6 {
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_l7: ldo7 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_l8: ldo8 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_l9: ldo9 {
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3401000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_l11: ldo11 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_l12: ldo12 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_l13: ldo13 {
+ regulator-min-microvolt = <570000>;
+ regulator-max-microvolt = <650000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_l14: ldo14 {
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_l15: ldo15 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1305000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_l16: ldo16 {
+ regulator-min-microvolt = <830000>;
+ regulator-max-microvolt = <921000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_l18: ldo18 {
+ regulator-min-microvolt = <788000>;
+ regulator-max-microvolt = <1049000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_l19: ldo19 {
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1305000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_l20: ldo20 {
+ regulator-min-microvolt = <530000>;
+ regulator-max-microvolt = <801000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_l21: ldo21 {
+ regulator-min-microvolt = <751000>;
+ regulator-max-microvolt = <825000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6350_l22: ldo22 {
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1305000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm6150l-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ pm6150l_s8: smps8 {
+ regulator-min-microvolt = <313000>;
+ regulator-max-microvolt = <1395000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6150l_l1: ldo1 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6150l_l2: ldo2 {
+ regulator-min-microvolt = <1170000>;
+ regulator-max-microvolt = <1305000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6150l_l3: ldo3 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1299000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6150l_l4: ldo4 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6150l_l5: ldo5 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6150l_l6: ldo6 {
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+
+ };
+
+ pm6150l_l7: ldo7 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6150l_l8: ldo8 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6150l_l9: ldo9 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+
+ };
+
+ pm6150l_l10: ldo10 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3401000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6150l_l11: ldo11 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3401000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm6150l_bob: bob {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <5492000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-bypass;
+ };
+ };
+};
+
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&i2c8 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ touchscreen@48 {
+ compatible = "samsung,s6sy761";
+ reg = <0x48>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <22 0x2008>;
+ vdd-supply = <&pm6350_l11>;
+ avdd-supply = <&touch_en_vreg>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_int_default &ts_active>;
+ };
+};
+
+&pm6350_gpios {
+ gpio_keys_state: gpio-keys-state {
+ key-volume-down-pins {
+ pins = "gpio2";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ power-source = <0>;
+ bias-disable;
+ input-enable;
+ };
+ };
+};
+
+&pm6350_resin {
+ linux,code = <KEY_VOLUMEUP>;
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&sdc2_off_state {
+ sd-cd-pins {
+ pins = "gpio94";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&sdc2_on_state {
+ sd-cd-pins {
+ pins = "gpio94";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
};
&sdhc_2 {
status = "okay";
+ vmmc-supply = <&pm6150l_l9>;
+ vqmmc-supply = <&pm6150l_l6>;
+
cd-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>;
};
&tlmm {
gpio-reserved-ranges = <13 4>, <45 2>, <56 2>;
+
+ ts_active: ts-active-state {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ ts_int_default: ts-int-default-state {
+ pins = "gpio22";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ input-enable;
+ };
};
&usb_1 {
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index c39de7d3ace0..43324bf291c3 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -485,11 +485,13 @@
interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
+ iommus = <&apps_smmu 0x60 0x0>;
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "core", "xo";
+ resets = <&gcc GCC_SDCC1_BCR>;
qcom,dll-config = <0x000f642c>;
qcom,ddr-config = <0x80040868>;
power-domains = <&rpmhpd SM6350_CX>;
@@ -1063,15 +1065,21 @@
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
+ iommus = <&apps_smmu 0x560 0x0>;
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "core", "xo";
+ resets = <&gcc GCC_SDCC2_BCR>;
interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
interconnect-names = "sdhc-ddr", "cpu-sdhc";
+ pinctrl-0 = <&sdc2_on_state>;
+ pinctrl-1 = <&sdc2_off_state>;
+ pinctrl-names = "default", "sleep";
+
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
power-domains = <&rpmhpd SM6350_CX>;
@@ -1148,15 +1156,11 @@
dp_phy: dp-phy@88ea200 {
reg = <0 0x088ea200 0 0x200>,
<0 0x088ea400 0 0x200>,
- <0 0x088eac00 0 0x400>,
+ <0 0x088eaa00 0 0x200>,
<0 0x088ea600 0 0x200>,
- <0 0x088ea800 0 0x200>,
- <0 0x088eaa00 0 0x100>;
+ <0 0x088ea800 0 0x200>;
#phy-cells = <0>;
#clock-cells = <1>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_phy_pipe_clk_src";
};
};
@@ -1314,6 +1318,46 @@
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 157>;
+ sdc2_off_state: sdc2-off-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_on_state: sdc2-on-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+
qup_uart9_default: qup-uart9-default-state {
pins = "gpio25", "gpio26";
function = "qup13_f2";
diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts
new file mode 100644
index 000000000000..b691c3834b6b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts
@@ -0,0 +1,406 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+/dts-v1/;
+
+/* PMK8350 is configured to use SID6 instead of 0 */
+#define PMK8350_SID 6
+
+#include <dt-bindings/gpio/gpio.h>
+#include "sm6375.dtsi"
+#include "pm6125.dtsi"
+#include "pmk8350.dtsi"
+#include "pmr735a.dtsi"
+
+/* PM6125 PON is used and we can't have duplicate labels */
+/delete-node/ &pmk8350_pon;
+
+/ {
+ model = "Sony Xperia 10 IV";
+ compatible = "sony,pdx225", "qcom,sm6375";
+ chassis-type = "handset";
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer: framebuffer@85200000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x85200000 0 0xc00000>;
+
+ width = <1080>;
+ height = <2520>;
+ stride = <(1080 * 4)>;
+ format = "a8r8g8b8";
+ /*
+ * That's (going to be) a lot of clocks, but it's necessary due
+ * to unused clk cleanup & no panel driver yet
+ */
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_THROTTLE_CORE_CLK>,
+ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
+ };
+ };
+
+ reserved-memory {
+ cont_splash_mem: memory@85200000 {
+ reg = <0 0x85200000 0 0xc00000>;
+ no-map;
+ };
+
+ ramoops@ffc40000 {
+ compatible = "ramoops";
+ reg = <0 0xffc40000 0 0xb0000>;
+ record-size = <0x10000>;
+ console-size = <0x60000>;
+ ftrace-size = <0x10000>;
+ pmsg-size = <0x20000>;
+ ecc-size = <16>;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&sdc2_off_state {
+ sd-cd-pins {
+ pins = "gpio94";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&sdc2_on_state {
+ sd-cd-pins {
+ pins = "gpio94";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+};
+
+&sdhc_2 {
+ status = "okay";
+
+ vmmc-supply = <&pm6125_l22>;
+ vqmmc-supply = <&pm6125_l5>;
+
+ cd-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>;
+};
+
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&i2c8 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ touchscreen@48 {
+ compatible = "samsung,s6sy761";
+ reg = <0x48>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <22 0x2008>;
+
+ vdd-supply = <&pm6125_l13>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_int_default &ts_avdd_default>;
+ };
+};
+
+&pmk8350_adc_tm {
+ status = "okay";
+};
+
+&pmk8350_rtc {
+ status = "okay";
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEUP>;
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/Sony/murray/adsp.mbn";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/Sony/murray/cdsp.mbn";
+ status = "okay";
+};
+
+&rpm_requests {
+ regulators-0 {
+ compatible = "qcom,rpm-pm6125-regulators";
+
+ pm6125_s5: s5 {
+ regulator-min-microvolt = <382000>;
+ regulator-max-microvolt = <1120000>;
+ };
+
+ pm6125_s6: s6 {
+ regulator-min-microvolt = <320000>;
+ regulator-max-microvolt = <1374000>;
+ };
+
+ pm6125_s7: s7 {
+ regulator-min-microvolt = <1574000>;
+ regulator-max-microvolt = <2040000>;
+ };
+
+ /*
+ * S8 is VDD_GFX
+ * L1 is VDD_LPI_CX
+ */
+
+ pm6125_l2: l2 {
+ regulator-min-microvolt = <1170000>;
+ regulator-max-microvolt = <1304000>;
+ };
+
+ pm6125_l3: l3 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm6125_l4: l4 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm6125_l5: l5 {
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-allow-set-load;
+ };
+
+ pm6125_l6: l6 {
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1304000>;
+ };
+
+ pm6125_l7: l7 {
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm6125_l8: l8 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1304000>;
+ };
+
+ pm6125_l9: l9 {
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ pm6125_l10: l10 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ };
+
+ pm6125_l11: l11 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ };
+
+ pm6125_l12: l12 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ pm6125_l13: l13 {
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1980000>;
+ };
+
+ pm6125_l14: l14 {
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ };
+
+ pm6125_l15: l15 {
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3544000>;
+ };
+
+ pm6125_l16: l16 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ };
+
+ /* L17 is VDD_LPI_MX */
+
+ pm6125_l18: l18 {
+ regulator-min-microvolt = <830000>;
+ regulator-max-microvolt = <920000>;
+ };
+
+ pm6125_l19: l19 {
+ regulator-min-microvolt = <1624000>;
+ regulator-max-microvolt = <3304000>;
+ };
+
+ pm6125_l20: l20 {
+ regulator-min-microvolt = <1624000>;
+ regulator-max-microvolt = <3304000>;
+ };
+
+ pm6125_l21: l21 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ pm6125_l22: l22 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-allow-set-load;
+ };
+
+ pm6125_l23: l23 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ pm6125_l24: l24 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <3544000>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,rpm-pmr735a-regulators";
+
+ /*
+ * S1 is VDD_MX
+ * S2 is VDD_CX
+ */
+
+ pmr735a_l1: l1 {
+ regulator-min-microvolt = <570000>;
+ regulator-max-microvolt = <650000>;
+ };
+
+ pmr735a_l2: l2 {
+ regulator-min-microvolt = <352000>;
+ regulator-max-microvolt = <796000>;
+ };
+
+ pmr735a_l3: l3 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pmr735a_l4: l4 {
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ pmr735a_l5: l5 {
+ regulator-min-microvolt = <751000>;
+ regulator-max-microvolt = <824000>;
+ };
+
+ pmr735a_l6: l6 {
+ regulator-min-microvolt = <504000>;
+ regulator-max-microvolt = <868000>;
+ };
+
+ pmr735a_l7: l7 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ };
+ };
+};
+
+&sdc2_off_state {
+ sd-cd-pins {
+ pins = "gpio94";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&sdc2_on_state {
+ sd-cd-pins {
+ pins = "gpio94";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+};
+
+&sdhc_2 {
+ status = "okay";
+
+ vmmc-supply = <&pm6125_l22>;
+ vqmmc-supply = <&pm6125_l5>;
+
+ cd-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>;
+};
+
+&tlmm {
+ gpio-reserved-ranges = <13 4>;
+
+ ts_int_default: ts-int-default-state {
+ pins = "gpio22";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ ts_avdd_default: ts-avdd-default-state {
+ pins = "gpio59";
+ function = "gpio";
+ drive-strength = <8>;
+ output-high;
+ };
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+ status = "okay";
+};
+
+&xo_board_clk {
+ clock-frequency = <19200000>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi
new file mode 100644
index 000000000000..12cf5dbe5bd6
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi
@@ -0,0 +1,1396 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,sm6375-gcc.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board_clk: xo-board-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,kryo660";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
+ #cooling-cells = <2>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo660";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_100>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ power-domains = <&CPU_PD1>;
+ power-domain-names = "psci";
+ #cooling-cells = <2>;
+ L2_100: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "qcom,kryo660";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&L2_200>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ power-domains = <&CPU_PD2>;
+ power-domain-names = "psci";
+ #cooling-cells = <2>;
+ L2_200: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "qcom,kryo660";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&L2_300>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ power-domains = <&CPU_PD3>;
+ power-domain-names = "psci";
+ #cooling-cells = <2>;
+ L2_300: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "qcom,kryo660";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ next-level-cache = <&L2_400>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ power-domains = <&CPU_PD4>;
+ power-domain-names = "psci";
+ #cooling-cells = <2>;
+ L2_400: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "qcom,kryo660";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ next-level-cache = <&L2_500>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ power-domains = <&CPU_PD5>;
+ power-domain-names = "psci";
+ #cooling-cells = <2>;
+ L2_500: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+
+ };
+
+ CPU6: cpu@600 {
+ device_type = "cpu";
+ compatible = "qcom,kryo660";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ next-level-cache = <&L2_600>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ power-domains = <&CPU_PD6>;
+ power-domain-names = "psci";
+ #cooling-cells = <2>;
+ L2_600: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU7: cpu@700 {
+ device_type = "cpu";
+ compatible = "qcom,kryo660";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ next-level-cache = <&L2_700>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ power-domains = <&CPU_PD7>;
+ power-domain-names = "psci";
+ #cooling-cells = <2>;
+ L2_700: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+
+ core4 {
+ cpu = <&CPU4>;
+ };
+
+ core5 {
+ cpu = <&CPU5>;
+ };
+
+ core6 {
+ cpu = <&CPU6>;
+ };
+
+ core7 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "silver-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <702>;
+ exit-latency-us = <915>;
+ min-residency-us = <4001>;
+ local-timer-stop;
+ };
+
+ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "gold-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <526>;
+ exit-latency-us = <1854>;
+ min-residency-us = <5555>;
+ local-timer-stop;
+ };
+ };
+
+ domain-idle-states {
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ idle-state-name = "cluster-power-collapse";
+ arm,psci-suspend-param = <0x41000044>;
+ entry-latency-us = <2752>;
+ exit-latency-us = <3048>;
+ min-residency-us = <6118>;
+ local-timer-stop;
+ };
+ };
+ };
+
+ firmware {
+ scm {
+ compatible = "qcom,scm-sm6375", "qcom,scm";
+ clocks = <&rpmcc RPM_SMD_CE1_CLK>;
+ clock-names = "core";
+ #reset-cells = <1>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0x80000000 0x0 0x0>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ CPU_PD0: cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD1: cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD2: cpu2 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD3: cpu3 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD4: cpu4 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD5: cpu5 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD6: cpu6 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ };
+
+ CPU_PD7: cpu7 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ };
+
+ CLUSTER_PD: cpu-cluster0 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&CLUSTER_SLEEP_0>;
+ };
+ };
+
+ qup_opp_table: opp-table-qup {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmpd_opp_svs>;
+ };
+
+ opp-128000000 {
+ opp-hz = /bits/ 64 <128000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ };
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: hypervisor@80000000 {
+ reg = <0 0x80000000 0 0x600000>;
+ no-map;
+ };
+
+ xbl_aop_mem: xbl-aop@80700000 {
+ reg = <0 0x80700000 0 0x100000>;
+ no-map;
+ };
+
+ reserved_xbl_uefi: xbl-uefi-res@80880000 {
+ reg = <0 0x80880000 0 0x14000>;
+ no-map;
+ };
+
+ smem_mem: smem@80900000 {
+ compatible = "qcom,smem";
+ reg = <0 0x80900000 0 0x200000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
+ };
+
+ fw_mem: fw@80b00000 {
+ reg = <0 0x80b00000 0 0x100000>;
+ no-map;
+ };
+
+ cdsp_secure_heap_mem: cdsp-sec-heap@80c00000 {
+ reg = <0 0x80c00000 0 0x1e00000>;
+ no-map;
+ };
+
+ dfps_data_mem: dpfs-data@85e00000 {
+ reg = <0 0x85e00000 0 0x100000>;
+ no-map;
+ };
+
+ pil_wlan_mem: pil-wlan@86500000 {
+ reg = <0 0x86500000 0 0x200000>;
+ no-map;
+ };
+
+ pil_adsp_mem: pil-adsp@86700000 {
+ reg = <0 0x86700000 0 0x2000000>;
+ no-map;
+ };
+
+ pil_cdsp_mem: pil-cdsp@88700000 {
+ reg = <0 0x88700000 0 0x1e00000>;
+ no-map;
+ };
+
+ pil_video_mem: pil-video@8a500000 {
+ reg = <0 0x8a500000 0 0x500000>;
+ no-map;
+ };
+
+ pil_ipa_fw_mem: pil-ipa-fw@8aa00000 {
+ reg = <0 0x8aa00000 0 0x10000>;
+ no-map;
+ };
+
+ pil_ipa_gsi_mem: pil-ipa-gsi@8aa10000 {
+ reg = <0 0x8aa10000 0 0xa000>;
+ no-map;
+ };
+
+ pil_gpu_micro_code_mem: pil-gpu-ucode@8aa1a000 {
+ reg = <0 0x8aa1a000 0 0x2000>;
+ no-map;
+ };
+
+ pil_mpss_wlan_mem: pil-mpss-wlan@8b800000 {
+ reg = <0 0x8b800000 0 0x10000000>;
+ no-map;
+ };
+
+ removed_mem: removed@c0000000 {
+ reg = <0 0xc0000000 0 0x5100000>;
+ no-map;
+ };
+
+ debug_mem: debug@ffb00000 {
+ reg = <0 0xffb00000 0 0xc0000>;
+ no-map;
+ };
+
+ last_log_mem: lastlog@ffbc0000 {
+ reg = <0 0xffbc0000 0 0x80000>;
+ no-map;
+ };
+
+ cmdline_region: cmdline@ffd00000 {
+ reg = <0 0xffd00000 0 0x1000>;
+ no-map;
+ };
+ };
+
+ rpm-glink {
+ compatible = "qcom,glink-rpm";
+ interrupts-extended = <&ipcc IPCC_CLIENT_AOP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-sm6375";
+ qcom,glink-channels = "rpm_requests";
+
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc";
+ clocks = <&xo_board_clk>;
+ clock-names = "xo";
+ #clock-cells = <1>;
+ };
+
+ rpmpd: power-controller {
+ compatible = "qcom,sm6375-rpmpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmpd_opp_table>;
+
+ rpmpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmpd_opp_ret: opp1 {
+ opp-level = <RPM_SMD_LEVEL_RETENTION>;
+ };
+
+ rpmpd_opp_min_svs: opp2 {
+ opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
+ };
+
+ rpmpd_opp_low_svs: opp3 {
+ opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
+ };
+
+ rpmpd_opp_svs: opp4 {
+ opp-level = <RPM_SMD_LEVEL_SVS>;
+ };
+
+ rpmpd_opp_svs_plus: opp5 {
+ opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
+ };
+
+ rpmpd_opp_nom: opp6 {
+ opp-level = <RPM_SMD_LEVEL_NOM>;
+ };
+
+ rpmpd_opp_nom_plus: opp7 {
+ opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
+ };
+
+ rpmpd_opp_turbo: opp8 {
+ opp-level = <RPM_SMD_LEVEL_TURBO>;
+ };
+
+ rpmpd_opp_turbo_no_cpr: opp9 {
+ opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
+ };
+ };
+ };
+ };
+ };
+
+ smp2p-adsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ smp2p_adsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_adsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ smp2p_cdsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_cdsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ soc: soc@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0 0x10 0>;
+ dma-ranges = <0 0 0 0 0x10 0>;
+ compatible = "simple-bus";
+
+ ipcc: mailbox@208000 {
+ compatible = "qcom,sm6375-ipcc", "qcom,ipcc";
+ reg = <0 0x00208000 0 0x1000>;
+ interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #mbox-cells = <2>;
+ };
+
+ tcsr_mutex: hwlock@340000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x0 0x00340000 0x0 0x40000>;
+ #hwlock-cells = <1>;
+ };
+
+ tlmm: pinctrl@500000 {
+ compatible = "qcom,sm6375-tlmm";
+ reg = <0 0x00500000 0 0x800000>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&tlmm 0 0 157>;
+ /* TODO: Hook up MPM as wakeup-parent when it's there */
+ interrupt-controller;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ #gpio-cells = <2>;
+
+ sdc2_off_state: sdc2-off-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_on_state: sdc2-on-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+
+ qup_i2c0_default: qup-i2c0-default-state {
+ pins = "gpio0", "gpio1";
+ function = "qup00";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c1_default: qup-i2c1-default-state {
+ pins = "gpio61", "gpio62";
+ function = "qup01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c2_default: qup-i2c2-default-state {
+ pins = "gpio45", "gpio46";
+ function = "qup02";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c8_default: qup-i2c8-default-state {
+ pins = "gpio19", "gpio20";
+ /* TLMM, GCC and vendor DT all have different indices.. */
+ function = "qup12";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c10_default: qup-i2c10-default-state {
+ pins = "gpio4", "gpio5";
+ function = "qup10";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi0_default: qup-spi0-default-state {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "qup00";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ gcc: clock-controller@1400000 {
+ compatible = "qcom,sm6375-gcc";
+ reg = <0 0x01400000 0 0x1f0000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
+ <&sleep_clk>;
+ #power-domain-cells = <1>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ usb_1_hsphy: phy@162b000 {
+ compatible = "qcom,sm6375-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy";
+ reg = <0 0x0162b000 0 0x400>;
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "ref";
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spmi_bus: spmi@1c40000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0 0x01c40000 0 0x1100>,
+ <0 0x01e00000 0 0x2000000>,
+ <0 0x03e00000 0 0x100000>,
+ <0 0x03f00000 0 0xa0000>,
+ <0 0x01c0a000 0 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
+ rpm_msg_ram: sram@45f0000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0 0x045f0000 0 0x7000>;
+ };
+
+ sdhc_2: mmc@4784000 {
+ compatible = "qcom,sm6375-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0 0x04784000 0 0x1000>;
+
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "core", "xo";
+ resets = <&gcc GCC_SDCC2_BCR>;
+ iommus = <&apps_smmu 0x40 0x0>;
+
+ pinctrl-0 = <&sdc2_on_state>;
+ pinctrl-1 = <&sdc2_off_state>;
+ pinctrl-names = "default", "sleep";
+
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
+ power-domains = <&rpmpd SM6375_VDDCX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+ bus-width = <4>;
+
+ status = "disabled";
+
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmpd_opp_svs_plus>;
+ };
+ };
+ };
+
+ gpi_dma0: dma-controller@4a00000 {
+ compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0 0x04a00000 0 0x60000>;
+ interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <10>;
+ dma-channel-mask = <0x1f>;
+ iommus = <&apps_smmu 0x16 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
+ qupv3_id_0: geniqup@4ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x04ac0000 0x0 0x2000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x3 0x0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ i2c0: i2c@4a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x04a80000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c0_default>;
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi0: spi@4a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x04a80000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi0_default>;
+ power-domains = <&rpmpd SM6375_VDDCX>;
+ operating-points-v2 = <&qup_opp_table>;
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@4a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x04a84000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c1_default>;
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@4a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x04a84000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmpd SM6375_VDDCX>;
+ operating-points-v2 = <&qup_opp_table>;
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@4a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x04a88000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c2_default>;
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@4a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x04a88000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmpd SM6375_VDDCX>;
+ operating-points-v2 = <&qup_opp_table>;
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ /*
+ * As per GCC, QUP3/4/5/11 also exist, but are not even defined downstream.
+ * There is a comment in the included DTSI of another SoC saying that they
+ * are not "bolled out" (probably meaning not routed to solder balls)
+ * TLMM driver however, suggests there are as many as 15 QUPs in total!
+ * Most of which don't even have pin configurations for.. Sad stuff!
+ */
+ };
+
+ gpi_dma1: dma-controller@4c00000 {
+ compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0 0x04c00000 0 0x60000>;
+ interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <10>;
+ dma-channel-mask = <0x1f>;
+ iommus = <&apps_smmu 0xd6 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
+ qupv3_id_1: geniqup@4cc0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x04cc0000 0x0 0x2000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ iommus = <&apps_smmu 0xc3 0x0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ i2c6: i2c@4c80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x04c80000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi6: spi@4c80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x04c80000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmpd SM6375_VDDCX>;
+ operating-points-v2 = <&qup_opp_table>;
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@4c84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x04c84000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi7: spi@4c84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x04c84000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmpd SM6375_VDDCX>;
+ operating-points-v2 = <&qup_opp_table>;
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@4c88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x04c88000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c8_default>;
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi8: spi@4c88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x04c88000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmpd SM6375_VDDCX>;
+ operating-points-v2 = <&qup_opp_table>;
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c9: i2c@4c8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x04c8c000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi9: spi@4c8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x04c8c000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmpd SM6375_VDDCX>;
+ operating-points-v2 = <&qup_opp_table>;
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c10: i2c@4c90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x04c90000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c10_default>;
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi10: spi@4c90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x04c90000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmpd SM6375_VDDCX>;
+ operating-points-v2 = <&qup_opp_table>;
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ usb_1: usb@4ef8800 {
+ compatible = "qcom,sm6375-dwc3", "qcom,dwc3";
+ reg = <0 0x04ef8800 0 0x400>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "xo";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <133333333>;
+
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq",
+ "ss_phy_irq",
+ "dm_hs_phy_irq",
+ "dp_hs_phy_irq";
+
+ power-domains = <&gcc USB30_PRIM_GDSC>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ /*
+ * This property is there to allow USB2 to work, as
+ * USB3 is not implemented yet - (re)move it when
+ * proper support is in place.
+ */
+ qcom,select-utmi-as-pipe-clk;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ usb_1_dwc3: usb@4e00000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x04e00000 0 0xcd00>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ maximum-speed = "high-speed";
+ phys = <&usb_1_hsphy>;
+ phy-names = "usb2-phy";
+ iommus = <&apps_smmu 0xe0 0x0>;
+
+ /* Yes, this impl *does* have an unfunny number of quirks.. */
+ snps,hird-threshold = /bits/ 8 <0x10>;
+ snps,usb2-gadget-lpm-disable;
+ snps,dis_u2_susphy_quirk;
+ snps,is-utmi-l1-suspend;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,usb3_lpm_capable;
+ snps,has-lpm-erratum;
+ tx-fifo-resize;
+ };
+ };
+
+ remoteproc_adsp: remoteproc@a400000 {
+ compatible = "qcom,sm6375-adsp-pas";
+ reg = <0 0x0a400000 0 0x100>;
+
+ interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready",
+ "handover", "stop-ack";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+
+ power-domains = <&rpmpd SM6375_VDD_LPI_CX>,
+ <&rpmpd SM6375_VDD_LPI_MX>;
+ power-domain-names = "lcx", "lmx";
+
+ memory-region = <&pil_adsp_mem>;
+
+ qcom,smem-states = <&smp2p_adsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "lpass";
+ qcom,remote-pid = <2>;
+ };
+ };
+
+ remoteproc_cdsp: remoteproc@b000000 {
+ compatible = "qcom,sm6375-cdsp-pas";
+ reg = <0x0 0x0b000000 0x0 0x100000>;
+
+ interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready",
+ "handover", "stop-ack";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+
+ power-domains = <&rpmpd SM6375_VDDCX>;
+
+ memory-region = <&pil_cdsp_mem>;
+
+ qcom,smem-states = <&smp2p_cdsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ label = "cdsp";
+ qcom,remote-pid = <5>;
+ };
+ };
+
+ apps_smmu: iommu@c600000 {
+ compatible = "qcom,sm6375-smmu-500", "arm,mmu-500";
+ reg = <0 0x0c600000 0 0x100000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+
+ power-domains = <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC>,
+ <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC>,
+ <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>;
+ #global-interrupts = <1>;
+ #iommu-cells = <2>;
+ };
+
+ intc: interrupt-controller@f200000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */
+ <0x0 0x0f240000 0x0 0x100000>; /* GICR * 8 */
+ interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #redistributor-regions = <1>;
+ #interrupt-cells = <3>;
+ redistributor-stride = <0 0x20000>;
+ interrupt-controller;
+ };
+
+ timer@f420000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0 0x0f420000 0 0x1000>;
+ ranges = <0 0 0 0x20000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ frame@f421000 {
+ reg = <0x0f421000 0x1000>, <0x0f422000 0x1000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <0>;
+ };
+
+ frame@f423000 {
+ reg = <0x0f243000 0x1000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <1>;
+ status = "disabled";
+ };
+
+ frame@f425000 {
+ reg = <0x0f425000 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <2>;
+ status = "disabled";
+ };
+
+ frame@f427000 {
+ reg = <0x0f427000 0x1000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <3>;
+ status = "disabled";
+ };
+
+ frame@f429000 {
+ reg = <0x0f429000 0x1000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <4>;
+ status = "disabled";
+ };
+
+ frame@f42b000 {
+ reg = <0x0f42b000 0x1000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <5>;
+ status = "disabled";
+ };
+
+ frame@f42d000 {
+ reg = <0x0f42d000 0x1000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <6>;
+ status = "disabled";
+ };
+ };
+
+ cpufreq_hw: cpufreq@fd91000 {
+ compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss";
+ reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>;
+ reg-names = "freq-domain0", "freq-domain1";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
+ #freq-domain-cells = <1>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
index 30c94fd4fe61..c456e9594ea5 100644
--- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
+++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
@@ -279,8 +279,11 @@
vreg_l6e: ldo6 {
regulator-min-microvolt = <1700000>;
- regulator-max-microvolt = <3544000>;
+ regulator-max-microvolt = <2950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7e: ldo7 {
@@ -297,8 +300,11 @@
vreg_l9e: ldo9 {
regulator-min-microvolt = <2700000>;
- regulator-max-microvolt = <3544000>;
+ regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10e: ldo10 {
@@ -424,6 +430,33 @@
status = "okay";
};
+&sdc2_off_state {
+ sd-cd-pins {
+ pins = "gpio94";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&sdc2_on_state {
+ sd-cd-pins {
+ pins = "gpio94";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+};
+
+&sdhc_2 {
+ vmmc-supply = <&vreg_l9e>;
+ vqmmc-supply = <&vreg_l6e>;
+
+ cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
&tlmm {
gpio-reserved-ranges = <13 4>, <56 2>;
};
diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
index bb278ecac3fa..5397fba9417b 100644
--- a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
+++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
@@ -475,7 +475,7 @@
&tlmm {
gpio-reserved-ranges = <126 4>;
- da7280_intr_default: da7280-intr-default {
+ da7280_intr_default: da7280-intr-default-state {
pins = "gpio42";
function = "gpio";
bias-pull-up;
diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi
index fb6e5a140c9f..c958a8b16730 100644
--- a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi
@@ -348,9 +348,8 @@
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
- regulator-allowed-modes =
- <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c_3p0: ldo7 {
@@ -370,9 +369,8 @@
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
- regulator-allowed-modes =
- <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10c_3p3: ldo10 {
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index cef8c4f4f0ff..a0c57fb798d3 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -887,7 +887,7 @@
};
gpi_dma0: dma-controller@800000 {
- compatible = "qcom,sm8150-gpi-dma";
+ compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
reg = <0 0x800000 0 0x60000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
@@ -1222,7 +1222,7 @@
};
gpi_dma1: dma-controller@a00000 {
- compatible = "qcom,sm8150-gpi-dma";
+ compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
reg = <0 0xa00000 0 0x60000>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
@@ -1471,7 +1471,7 @@
};
gpi_dma2: dma-controller@c00000 {
- compatible = "qcom,sm8150-gpi-dma";
+ compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
reg = <0 0xc00000 0 0x60000>;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
@@ -2032,11 +2032,11 @@
status = "disabled";
ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x108>,
- <0 0x01d87600 0 0x1e0>,
- <0 0x01d87c00 0 0x1dc>,
- <0 0x01d87800 0 0x108>,
- <0 0x01d87a00 0 0x1e0>;
+ reg = <0 0x01d87400 0 0x16c>,
+ <0 0x01d87600 0 0x200>,
+ <0 0x01d87c00 0 0x200>,
+ <0 0x01d87800 0 0x16c>,
+ <0 0x01d87a00 0 0x200>;
#phy-cells = <0>;
};
};
@@ -2074,8 +2074,8 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&rpmhpd 3>,
- <&rpmhpd 2>;
+ power-domains = <&rpmhpd SM8150_LCX>,
+ <&rpmhpd SM8150_LMX>;
power-domain-names = "lcx", "lmx";
memory-region = <&slpi_mem>;
@@ -2276,422 +2276,302 @@
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
- qup_i2c0_default: qup-i2c0-default {
- mux {
- pins = "gpio0", "gpio1";
- function = "qup0";
- };
-
- config {
- pins = "gpio0", "gpio1";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c0_default: qup-i2c0-default-state {
+ pins = "gpio0", "gpio1";
+ function = "qup0";
+ drive-strength = <0x02>;
+ bias-disable;
};
- qup_spi0_default: qup-spi0-default {
+ qup_spi0_default: qup-spi0-default-state {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "qup0";
drive-strength = <6>;
bias-disable;
};
- qup_i2c1_default: qup-i2c1-default {
- mux {
- pins = "gpio114", "gpio115";
- function = "qup1";
- };
-
- config {
- pins = "gpio114", "gpio115";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c1_default: qup-i2c1-default-state {
+ pins = "gpio114", "gpio115";
+ function = "qup1";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi1_default: qup-spi1-default {
+ qup_spi1_default: qup-spi1-default-state {
pins = "gpio114", "gpio115", "gpio116", "gpio117";
function = "qup1";
drive-strength = <6>;
bias-disable;
};
- qup_i2c2_default: qup-i2c2-default {
- mux {
- pins = "gpio126", "gpio127";
- function = "qup2";
- };
-
- config {
- pins = "gpio126", "gpio127";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c2_default: qup-i2c2-default-state {
+ pins = "gpio126", "gpio127";
+ function = "qup2";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi2_default: qup-spi2-default {
+ qup_spi2_default: qup-spi2-default-state {
pins = "gpio126", "gpio127", "gpio128", "gpio129";
function = "qup2";
drive-strength = <6>;
bias-disable;
};
- qup_i2c3_default: qup-i2c3-default {
- mux {
- pins = "gpio144", "gpio145";
- function = "qup3";
- };
-
- config {
- pins = "gpio144", "gpio145";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c3_default: qup-i2c3-default-state {
+ pins = "gpio144", "gpio145";
+ function = "qup3";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi3_default: qup-spi3-default {
+ qup_spi3_default: qup-spi3-default-state {
pins = "gpio144", "gpio145", "gpio146", "gpio147";
function = "qup3";
drive-strength = <6>;
bias-disable;
};
- qup_i2c4_default: qup-i2c4-default {
- mux {
- pins = "gpio51", "gpio52";
- function = "qup4";
- };
-
- config {
- pins = "gpio51", "gpio52";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c4_default: qup-i2c4-default-state {
+ pins = "gpio51", "gpio52";
+ function = "qup4";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi4_default: qup-spi4-default {
+ qup_spi4_default: qup-spi4-default-state {
pins = "gpio51", "gpio52", "gpio53", "gpio54";
function = "qup4";
drive-strength = <6>;
bias-disable;
};
- qup_i2c5_default: qup-i2c5-default {
- mux {
- pins = "gpio121", "gpio122";
- function = "qup5";
- };
-
- config {
- pins = "gpio121", "gpio122";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c5_default: qup-i2c5-default-state {
+ pins = "gpio121", "gpio122";
+ function = "qup5";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi5_default: qup-spi5-default {
+ qup_spi5_default: qup-spi5-default-state {
pins = "gpio119", "gpio120", "gpio121", "gpio122";
function = "qup5";
drive-strength = <6>;
bias-disable;
};
- qup_i2c6_default: qup-i2c6-default {
- mux {
- pins = "gpio6", "gpio7";
- function = "qup6";
- };
-
- config {
- pins = "gpio6", "gpio7";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c6_default: qup-i2c6-default-state {
+ pins = "gpio6", "gpio7";
+ function = "qup6";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi6_default: qup-spi6_default {
+ qup_spi6_default: qup-spi6_default-state {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
function = "qup6";
drive-strength = <6>;
bias-disable;
};
- qup_i2c7_default: qup-i2c7-default {
- mux {
- pins = "gpio98", "gpio99";
- function = "qup7";
- };
-
- config {
- pins = "gpio98", "gpio99";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c7_default: qup-i2c7-default-state {
+ pins = "gpio98", "gpio99";
+ function = "qup7";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi7_default: qup-spi7_default {
+ qup_spi7_default: qup-spi7_default-state {
pins = "gpio98", "gpio99", "gpio100", "gpio101";
function = "qup7";
drive-strength = <6>;
bias-disable;
};
- qup_i2c8_default: qup-i2c8-default {
- mux {
- pins = "gpio88", "gpio89";
- function = "qup8";
- };
-
- config {
- pins = "gpio88", "gpio89";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c8_default: qup-i2c8-default-state {
+ pins = "gpio88", "gpio89";
+ function = "qup8";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi8_default: qup-spi8-default {
+ qup_spi8_default: qup-spi8-default-state {
pins = "gpio88", "gpio89", "gpio90", "gpio91";
function = "qup8";
drive-strength = <6>;
bias-disable;
};
- qup_i2c9_default: qup-i2c9-default {
- mux {
- pins = "gpio39", "gpio40";
- function = "qup9";
- };
-
- config {
- pins = "gpio39", "gpio40";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c9_default: qup-i2c9-default-state {
+ pins = "gpio39", "gpio40";
+ function = "qup9";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi9_default: qup-spi9-default {
+ qup_spi9_default: qup-spi9-default-state {
pins = "gpio39", "gpio40", "gpio41", "gpio42";
function = "qup9";
drive-strength = <6>;
bias-disable;
};
- qup_i2c10_default: qup-i2c10-default {
- mux {
- pins = "gpio9", "gpio10";
- function = "qup10";
- };
-
- config {
- pins = "gpio9", "gpio10";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c10_default: qup-i2c10-default-state {
+ pins = "gpio9", "gpio10";
+ function = "qup10";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi10_default: qup-spi10-default {
+ qup_spi10_default: qup-spi10-default-state {
pins = "gpio9", "gpio10", "gpio11", "gpio12";
function = "qup10";
drive-strength = <6>;
bias-disable;
};
- qup_i2c11_default: qup-i2c11-default {
- mux {
- pins = "gpio94", "gpio95";
- function = "qup11";
- };
-
- config {
- pins = "gpio94", "gpio95";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c11_default: qup-i2c11-default-state {
+ pins = "gpio94", "gpio95";
+ function = "qup11";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi11_default: qup-spi11-default {
+ qup_spi11_default: qup-spi11-default-state {
pins = "gpio92", "gpio93", "gpio94", "gpio95";
function = "qup11";
drive-strength = <6>;
bias-disable;
};
- qup_i2c12_default: qup-i2c12-default {
- mux {
- pins = "gpio83", "gpio84";
- function = "qup12";
- };
-
- config {
- pins = "gpio83", "gpio84";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c12_default: qup-i2c12-default-state {
+ pins = "gpio83", "gpio84";
+ function = "qup12";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi12_default: qup-spi12-default {
+ qup_spi12_default: qup-spi12-default-state {
pins = "gpio83", "gpio84", "gpio85", "gpio86";
function = "qup12";
drive-strength = <6>;
bias-disable;
};
- qup_i2c13_default: qup-i2c13-default {
- mux {
- pins = "gpio43", "gpio44";
- function = "qup13";
- };
-
- config {
- pins = "gpio43", "gpio44";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c13_default: qup-i2c13-default-state {
+ pins = "gpio43", "gpio44";
+ function = "qup13";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi13_default: qup-spi13-default {
+ qup_spi13_default: qup-spi13-default-state {
pins = "gpio43", "gpio44", "gpio45", "gpio46";
function = "qup13";
drive-strength = <6>;
bias-disable;
};
- qup_i2c14_default: qup-i2c14-default {
- mux {
- pins = "gpio47", "gpio48";
- function = "qup14";
- };
-
- config {
- pins = "gpio47", "gpio48";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c14_default: qup-i2c14-default-state {
+ pins = "gpio47", "gpio48";
+ function = "qup14";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi14_default: qup-spi14-default {
+ qup_spi14_default: qup-spi14-default-state {
pins = "gpio47", "gpio48", "gpio49", "gpio50";
function = "qup14";
drive-strength = <6>;
bias-disable;
};
- qup_i2c15_default: qup-i2c15-default {
- mux {
- pins = "gpio27", "gpio28";
- function = "qup15";
- };
-
- config {
- pins = "gpio27", "gpio28";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c15_default: qup-i2c15-default-state {
+ pins = "gpio27", "gpio28";
+ function = "qup15";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi15_default: qup-spi15-default {
+ qup_spi15_default: qup-spi15-default-state {
pins = "gpio27", "gpio28", "gpio29", "gpio30";
function = "qup15";
drive-strength = <6>;
bias-disable;
};
- qup_i2c16_default: qup-i2c16-default {
- mux {
- pins = "gpio86", "gpio85";
- function = "qup16";
- };
-
- config {
- pins = "gpio86", "gpio85";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c16_default: qup-i2c16-default-state {
+ pins = "gpio86", "gpio85";
+ function = "qup16";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi16_default: qup-spi16-default {
+ qup_spi16_default: qup-spi16-default-state {
pins = "gpio83", "gpio84", "gpio85", "gpio86";
function = "qup16";
drive-strength = <6>;
bias-disable;
};
- qup_i2c17_default: qup-i2c17-default {
- mux {
- pins = "gpio55", "gpio56";
- function = "qup17";
- };
-
- config {
- pins = "gpio55", "gpio56";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c17_default: qup-i2c17-default-state {
+ pins = "gpio55", "gpio56";
+ function = "qup17";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi17_default: qup-spi17-default {
+ qup_spi17_default: qup-spi17-default-state {
pins = "gpio55", "gpio56", "gpio57", "gpio58";
function = "qup17";
drive-strength = <6>;
bias-disable;
};
- qup_i2c18_default: qup-i2c18-default {
- mux {
- pins = "gpio23", "gpio24";
- function = "qup18";
- };
-
- config {
- pins = "gpio23", "gpio24";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c18_default: qup-i2c18-default-state {
+ pins = "gpio23", "gpio24";
+ function = "qup18";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi18_default: qup-spi18-default {
+ qup_spi18_default: qup-spi18-default-state {
pins = "gpio23", "gpio24", "gpio25", "gpio26";
function = "qup18";
drive-strength = <6>;
bias-disable;
};
- qup_i2c19_default: qup-i2c19-default {
- mux {
- pins = "gpio57", "gpio58";
- function = "qup19";
- };
-
- config {
- pins = "gpio57", "gpio58";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c19_default: qup-i2c19-default-state {
+ pins = "gpio57", "gpio58";
+ function = "qup19";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi19_default: qup-spi19-default {
+ qup_spi19_default: qup-spi19-default-state {
pins = "gpio55", "gpio56", "gpio57", "gpio58";
function = "qup19";
drive-strength = <6>;
bias-disable;
};
- pcie0_default_state: pcie0-default {
- perst {
+ pcie0_default_state: pcie0-default-state {
+ perst-pins {
pins = "gpio35";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- clkreq {
+ clkreq-pins {
pins = "gpio36";
function = "pci_e0";
drive-strength = <2>;
bias-pull-up;
};
- wake {
+ wake-pins {
pins = "gpio37";
function = "gpio";
drive-strength = <2>;
@@ -2699,22 +2579,22 @@
};
};
- pcie1_default_state: pcie1-default {
- perst {
+ pcie1_default_state: pcie1-default-state {
+ perst-pins {
pins = "gpio102";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- clkreq {
+ clkreq-pins {
pins = "gpio103";
function = "pci_e1";
drive-strength = <2>;
bias-pull-up;
};
- wake {
+ wake-pins {
pins = "gpio104";
function = "gpio";
drive-strength = <2>;
@@ -2739,8 +2619,8 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&rpmhpd 7>,
- <&rpmhpd 0>;
+ power-domains = <&rpmhpd SM8150_CX>,
+ <&rpmhpd SM8150_MSS>;
power-domain-names = "cx", "mss";
memory-region = <&mpss_mem>;
@@ -3366,7 +3246,7 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&rpmhpd 7>;
+ power-domains = <&rpmhpd SM8150_CX>;
memory-region = <&cdsp_mem>;
@@ -3867,7 +3747,7 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&rpmhpd 7>;
+ power-domains = <&rpmhpd SM8150_CX>;
memory-region = <&adsp_mem>;
@@ -4010,6 +3890,7 @@
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
+ power-domains = <&CLUSTER_PD>;
rpmhcc: clock-controller {
compatible = "qcom,sm8150-rpmh-clk";
@@ -4078,7 +3959,7 @@
};
osm_l3: interconnect@18321000 {
- compatible = "qcom,sm8150-osm-l3";
+ compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3";
reg = <0 0x18321000 0 0x1400>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts
index a102aa5efa32..3ed8c84e25b8 100644
--- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts
@@ -635,7 +635,7 @@
wcd938x: codec {
compatible = "qcom,wcd9380-codec";
#sound-dai-cells = <1>;
- reset-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
vdd-buck-supply = <&vreg_s4a_1p8>;
vdd-rxtx-supply = <&vreg_s4a_1p8>;
vdd-io-supply = <&vreg_s4a_1p8>;
@@ -757,7 +757,7 @@
};
&swr0 {
- left_spkr: wsa8810-right@0,3{
+ left_spkr: speaker@0,3 {
compatible = "sdw10217211000";
reg = <0 3>;
powerdown-gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
@@ -766,7 +766,7 @@
#sound-dai-cells = <0>;
};
- right_spkr: wsa8810-left@0,4{
+ right_spkr: speaker@0,4 {
compatible = "sdw10217211000";
reg = <0 4>;
powerdown-gpios = <&tlmm 127 GPIO_ACTIVE_HIGH>;
@@ -799,31 +799,19 @@
&tlmm {
gpio-reserved-ranges = <28 4>, <40 4>;
- wcd938x_reset_default: wcd938x_reset_default {
- mux {
- pins = "gpio32";
- function = "gpio";
- };
-
- config {
- pins = "gpio32";
- drive-strength = <16>;
- output-high;
- };
+ wcd938x_reset_default: wcd938x-reset-default-state {
+ pins = "gpio32";
+ function = "gpio";
+ drive-strength = <16>;
+ output-high;
};
- wcd938x_reset_sleep: wcd938x_reset_sleep {
- mux {
- pins = "gpio32";
- function = "gpio";
- };
-
- config {
- pins = "gpio32";
- drive-strength = <16>;
- bias-disable;
- output-low;
- };
+ wcd938x_reset_sleep: wcd938x-reset-sleep-state {
+ pins = "gpio32";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi
index 5428aab3058d..09a31f707639 100644
--- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi
@@ -317,9 +317,8 @@
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
- regulator-allowed-modes =
- <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c_2p85: ldo7 {
@@ -342,9 +341,8 @@
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
- regulator-allowed-modes =
- <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10c_3p3: ldo10 {
@@ -440,7 +438,16 @@
status = "okay";
clock-frequency = <400000>;
- /* NXP PN553 NFC @ 28 */
+ nfc@28 {
+ compatible = "nxp,nxp-nci-i2c";
+ reg = <0x28>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <111 IRQ_TYPE_EDGE_RISING>;
+
+ enable-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
+ firmware-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
+ };
};
&i2c2 {
@@ -578,7 +585,7 @@
vqmmc-supply = <&vreg_l6c_2p9>;
bus-width = <4>;
no-sdio;
- no-emmc;
+ no-mmc;
};
&slpi {
@@ -588,49 +595,49 @@
&tlmm {
gpio-reserved-ranges = <40 4>, <52 4>;
- sdc2_default_state: sdc2-default {
- clk {
+ sdc2_default_state: sdc2-default-state {
+ clk-pins {
pins = "sdc2_clk";
drive-strength = <16>;
bias-disable;
};
- cmd {
+ cmd-pins {
pins = "sdc2_cmd";
drive-strength = <16>;
bias-pull-up;
};
- data {
+ data-pins {
pins = "sdc2_data";
drive-strength = <16>;
bias-pull-up;
};
};
- mdm2ap_default: mdm2ap-default {
+ mdm2ap_default: mdm2ap-default-state {
pins = "gpio1", "gpio3";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
- ts_int_default: ts-int-default {
+ ts_int_default: ts-int-default-state {
pins = "gpio39";
function = "gpio";
drive-strength = <2>;
- bias-disabled;
+ bias-disable;
input-enable;
};
- ap2mdm_default: ap2mdm-default {
+ ap2mdm_default: ap2mdm-default-state {
pins = "gpio56", "gpio57";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
- sdc2_card_det_n: sd-card-det-n {
+ sdc2_card_det_n: sd-card-det-n-state {
pins = "gpio77";
function = "gpio";
bias-pull-up;
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index e276eed1f8e2..dab5579946f3 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -937,7 +937,7 @@
};
gpi_dma2: dma-controller@800000 {
- compatible = "qcom,sm8250-gpi-dma";
+ compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
reg = <0 0x00800000 0 0x70000>;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
@@ -1188,7 +1188,7 @@
};
gpi_dma0: dma-controller@900000 {
- compatible = "qcom,sm8250-gpi-dma";
+ compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
reg = <0 0x00900000 0 0x70000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
@@ -1506,7 +1506,7 @@
};
gpi_dma1: dma-controller@a00000 {
- compatible = "qcom,sm8250-gpi-dma";
+ compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
reg = <0 0x00a00000 0 0x70000>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
@@ -2180,11 +2180,11 @@
status = "disabled";
ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x108>,
- <0 0x01d87600 0 0x1e0>,
- <0 0x01d87c00 0 0x1dc>,
- <0 0x01d87800 0 0x108>,
- <0 0x01d87a00 0 0x1e0>;
+ reg = <0 0x01d87400 0 0x16c>,
+ <0 0x01d87600 0 0x200>,
+ <0 0x01d87c00 0 0x200>,
+ <0 0x01d87800 0 0x16c>,
+ <0 0x01d87a00 0 0x200>;
#phy-cells = <0>;
};
};
@@ -2361,7 +2361,6 @@
qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>;
- qcom,port-offset = <1>;
#sound-dai-cells = <1>;
#address-cells = <2>;
#size-cells = <0>;
@@ -2389,8 +2388,8 @@
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "audio";
- wsa_swr_active: wsa-swr-active-pins {
- clk {
+ wsa_swr_active: wsa-swr-active-state {
+ clk-pins {
pins = "gpio10";
function = "wsa_swr_clk";
drive-strength = <2>;
@@ -2398,7 +2397,7 @@
bias-disable;
};
- data {
+ data-pins {
pins = "gpio11";
function = "wsa_swr_data";
drive-strength = <2>;
@@ -2408,8 +2407,8 @@
};
};
- wsa_swr_sleep: wsa-swr-sleep-pins {
- clk {
+ wsa_swr_sleep: wsa-swr-sleep-state {
+ clk-pins {
pins = "gpio10";
function = "wsa_swr_clk";
drive-strength = <2>;
@@ -2417,7 +2416,7 @@
bias-pull-down;
};
- data {
+ data-pins {
pins = "gpio11";
function = "wsa_swr_data";
drive-strength = <2>;
@@ -2427,14 +2426,14 @@
};
};
- dmic01_active: dmic01-active-pins {
- clk {
+ dmic01_active: dmic01-active-state {
+ clk-pins {
pins = "gpio6";
function = "dmic1_clk";
drive-strength = <8>;
output-high;
};
- data {
+ data-pins {
pins = "gpio7";
function = "dmic1_data";
drive-strength = <8>;
@@ -2442,8 +2441,8 @@
};
};
- dmic01_sleep: dmic01-sleep-pins {
- clk {
+ dmic01_sleep: dmic01-sleep-state {
+ clk-pins {
pins = "gpio6";
function = "dmic1_clk";
drive-strength = <2>;
@@ -2451,17 +2450,17 @@
output-low;
};
- data {
+ data-pins {
pins = "gpio7";
function = "dmic1_data";
drive-strength = <2>;
- pull-down;
+ bias-pull-down;
input-enable;
};
};
- rx_swr_active: rx_swr-active-pins {
- clk {
+ rx_swr_active: rx-swr-active-state {
+ clk-pins {
pins = "gpio3";
function = "swr_rx_clk";
drive-strength = <2>;
@@ -2469,7 +2468,7 @@
bias-disable;
};
- data {
+ data-pins {
pins = "gpio4", "gpio5";
function = "swr_rx_data";
drive-strength = <2>;
@@ -2478,8 +2477,8 @@
};
};
- tx_swr_active: tx_swr-active-pins {
- clk {
+ tx_swr_active: tx-swr-active-state {
+ clk-pins {
pins = "gpio0";
function = "swr_tx_clk";
drive-strength = <2>;
@@ -2487,7 +2486,7 @@
bias-disable;
};
- data {
+ data-pins {
pins = "gpio1", "gpio2";
function = "swr_tx_data";
drive-strength = <2>;
@@ -2496,8 +2495,8 @@
};
};
- tx_swr_sleep: tx_swr-sleep-pins {
- clk {
+ tx_swr_sleep: tx-swr-sleep-state {
+ clk-pins {
pins = "gpio0";
function = "swr_tx_clk";
drive-strength = <2>;
@@ -2505,7 +2504,7 @@
bias-pull-down;
};
- data1 {
+ data1-pins {
pins = "gpio1";
function = "swr_tx_data";
drive-strength = <2>;
@@ -2513,7 +2512,7 @@
bias-bus-hold;
};
- data2 {
+ data2-pins {
pins = "gpio2";
function = "swr_tx_data";
drive-strength = <2>;
@@ -2730,6 +2729,503 @@
};
};
+ stm@6002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint = <&funnel0_in7>;
+ };
+ };
+ };
+ };
+
+ funnel@6041000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06041000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel_in0_out_funnel_merg: endpoint {
+ remote-endpoint = <&funnel_merg_in_funnel_in0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@7 {
+ reg = <7>;
+ funnel0_in7: endpoint {
+ remote-endpoint = <&stm_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6042000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06042000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_in1_out_funnel_merg: endpoint {
+ remote-endpoint = <&funnel_merg_in_funnel_in1>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@4 {
+ reg = <4>;
+ funnel_in1_in_funnel_apss_merg: endpoint {
+ remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@6045000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06045000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel_merg_out_funnel_swao: endpoint {
+ remote-endpoint = <&funnel_swao_in_funnel_merg>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_merg_in_funnel_in0: endpoint {
+ remote-endpoint = <&funnel_in0_out_funnel_merg>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_merg_in_funnel_in1: endpoint {
+ remote-endpoint = <&funnel_in1_out_funnel_merg>;
+ };
+ };
+ };
+ };
+
+ replicator@6046000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0 0x06046000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ replicator_out: endpoint {
+ remote-endpoint = <&etr_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ replicator_cx_in_swao_out: endpoint {
+ remote-endpoint = <&replicator_swao_out_cx_in>;
+ };
+ };
+ };
+ };
+
+ etr@6048000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x06048000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ etr_in: endpoint {
+ remote-endpoint = <&replicator_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6b04000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0 0x06b04000 0 0x1000>;
+ reg-names = "funnel-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel_swao_out_etf: endpoint {
+ remote-endpoint = <&etf_in_funnel_swao_out>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@7 {
+ reg = <7>;
+ funnel_swao_in_funnel_merg: endpoint {
+ remote-endpoint= <&funnel_merg_out_funnel_swao>;
+ };
+ };
+ };
+
+ };
+
+ etf@6b05000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x06b05000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etf_out: endpoint {
+ remote-endpoint = <&replicator_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ etf_in_funnel_swao_out: endpoint {
+ remote-endpoint = <&funnel_swao_out_etf>;
+ };
+ };
+ };
+ };
+
+ replicator@6b06000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0 0x06b06000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ replicator_swao_out_cx_in: endpoint {
+ remote-endpoint = <&replicator_cx_in_swao_out>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ replicator_in: endpoint {
+ remote-endpoint = <&etf_out>;
+ };
+ };
+ };
+ };
+
+ etm@7040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07040000 0 0x1000>;
+
+ cpu = <&CPU0>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint = <&apss_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ etm@7140000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07140000 0 0x1000>;
+
+ cpu = <&CPU1>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint = <&apss_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ etm@7240000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07240000 0 0x1000>;
+
+ cpu = <&CPU2>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint = <&apss_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ etm@7340000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07340000 0 0x1000>;
+
+ cpu = <&CPU3>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint = <&apss_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ etm@7440000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07440000 0 0x1000>;
+
+ cpu = <&CPU4>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint = <&apss_funnel_in4>;
+ };
+ };
+ };
+ };
+
+ etm@7540000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07540000 0 0x1000>;
+
+ cpu = <&CPU5>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint = <&apss_funnel_in5>;
+ };
+ };
+ };
+ };
+
+ etm@7640000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07640000 0 0x1000>;
+
+ cpu = <&CPU6>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint = <&apss_funnel_in6>;
+ };
+ };
+ };
+ };
+
+ etm@7740000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07740000 0 0x1000>;
+
+ cpu = <&CPU7>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint = <&apss_funnel_in7>;
+ };
+ };
+ };
+ };
+
+ funnel@7800000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x07800000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel_apss_out_funnel_apss_merg: endpoint {
+ remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ apss_funnel_in0: endpoint {
+ remote-endpoint = <&etm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ apss_funnel_in1: endpoint {
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ apss_funnel_in2: endpoint {
+ remote-endpoint = <&etm2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ apss_funnel_in3: endpoint {
+ remote-endpoint = <&etm3_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ apss_funnel_in4: endpoint {
+ remote-endpoint = <&etm4_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ apss_funnel_in5: endpoint {
+ remote-endpoint = <&etm5_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ apss_funnel_in6: endpoint {
+ remote-endpoint = <&etm6_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ apss_funnel_in7: endpoint {
+ remote-endpoint = <&etm7_out>;
+ };
+ };
+ };
+ };
+
+ funnel@7810000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x07810000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port {
+ funnel_apss_merg_out_funnel_in1: endpoint {
+ remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_apss_merg_in_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
+ };
+ };
+ };
+ };
+
cdsp: remoteproc@8300000 {
compatible = "qcom,sm8250-cdsp-pas";
reg = <0 0x08300000 0 0x10000>;
@@ -2892,15 +3388,11 @@
dp_phy: dp-phy@88ea200 {
reg = <0 0x088ea200 0 0x200>,
<0 0x088ea400 0 0x200>,
- <0 0x088eac00 0 0x400>,
+ <0 0x088eaa00 0 0x200>,
<0 0x088ea600 0 0x200>,
- <0 0x088ea800 0 0x200>,
- <0 0x088eaa00 0 0x100>;
+ <0 0x088ea800 0 0x200>;
#phy-cells = <0>;
#clock-cells = <1>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_phy_pipe_clk_src";
};
};
@@ -3416,6 +3908,35 @@
"cam_hf_0_mnoc",
"cam_sf_0_mnoc",
"cam_sf_icp_mnoc";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ };
+
+ port@4 {
+ reg = <4>;
+ };
+
+ port@5 {
+ reg = <5>;
+ };
+ };
};
camcc: clock-controller@ad00000 {
@@ -3556,7 +4077,6 @@
power-domains = <&rpmhpd SM8250_MMCX>;
phys = <&dsi0_phy>;
- phy-names = "dsi";
status = "disabled";
@@ -3601,7 +4121,7 @@
};
};
- dsi0_phy: dsi-phy@ae94400 {
+ dsi0_phy: phy@ae94400 {
compatible = "qcom,dsi-phy-7nm";
reg = <0 0x0ae94400 0 0x200>,
<0 0x0ae94600 0 0x280>,
@@ -3648,7 +4168,6 @@
power-domains = <&rpmhpd SM8250_MMCX>;
phys = <&dsi1_phy>;
- phy-names = "dsi";
status = "disabled";
@@ -3674,7 +4193,7 @@
};
};
- dsi1_phy: dsi-phy@ae96400 {
+ dsi1_phy: phy@ae96400 {
compatible = "qcom,dsi-phy-7nm";
reg = <0 0x0ae96400 0 0x200>,
<0 0x0ae96600 0 0x280>,
@@ -3799,8 +4318,41 @@
gpio-ranges = <&tlmm 0 0 181>;
wakeup-parent = <&pdc>;
- cci0_default: cci0-default {
- cci0_i2c0_default: cci0-i2c0-default {
+ cam2_default: cam2-default-state {
+ rst-pins {
+ pins = "gpio78";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ mclk-pins {
+ pins = "gpio96";
+ function = "cam_mclk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ cam2_suspend: cam2-suspend-state {
+ rst-pins {
+ pins = "gpio78";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ output-low;
+ };
+
+ mclk-pins {
+ pins = "gpio96";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ cci0_default: cci0-default-state {
+ cci0_i2c0_default: cci0-i2c0-default-pins {
/* SDA, SCL */
pins = "gpio101", "gpio102";
function = "cci_i2c";
@@ -3809,7 +4361,7 @@
drive-strength = <2>; /* 2 mA */
};
- cci0_i2c1_default: cci0-i2c1-default {
+ cci0_i2c1_default: cci0-i2c1-default-pins {
/* SDA, SCL */
pins = "gpio103", "gpio104";
function = "cci_i2c";
@@ -3819,8 +4371,8 @@
};
};
- cci0_sleep: cci0-sleep {
- cci0_i2c0_sleep: cci0-i2c0-sleep {
+ cci0_sleep: cci0-sleep-state {
+ cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
/* SDA, SCL */
pins = "gpio101", "gpio102";
function = "cci_i2c";
@@ -3829,7 +4381,7 @@
bias-pull-down;
};
- cci0_i2c1_sleep: cci0-i2c1-sleep {
+ cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
/* SDA, SCL */
pins = "gpio103", "gpio104";
function = "cci_i2c";
@@ -3839,8 +4391,8 @@
};
};
- cci1_default: cci1-default {
- cci1_i2c0_default: cci1-i2c0-default {
+ cci1_default: cci1-default-state {
+ cci1_i2c0_default: cci1-i2c0-default-pins {
/* SDA, SCL */
pins = "gpio105","gpio106";
function = "cci_i2c";
@@ -3849,7 +4401,7 @@
drive-strength = <2>; /* 2 mA */
};
- cci1_i2c1_default: cci1-i2c1-default {
+ cci1_i2c1_default: cci1-i2c1-default-pins {
/* SDA, SCL */
pins = "gpio107","gpio108";
function = "cci_i2c";
@@ -3859,8 +4411,8 @@
};
};
- cci1_sleep: cci1-sleep {
- cci1_i2c0_sleep: cci1-i2c0-sleep {
+ cci1_sleep: cci1-sleep-state {
+ cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
/* SDA, SCL */
pins = "gpio105","gpio106";
function = "cci_i2c";
@@ -3869,7 +4421,7 @@
drive-strength = <2>; /* 2 mA */
};
- cci1_i2c1_sleep: cci1-i2c1-sleep {
+ cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
/* SDA, SCL */
pins = "gpio107","gpio108";
function = "cci_i2c";
@@ -3879,22 +4431,22 @@
};
};
- pri_mi2s_active: pri-mi2s-active {
- sclk {
+ pri_mi2s_active: pri-mi2s-active-state {
+ sclk-pins {
pins = "gpio138";
function = "mi2s0_sck";
drive-strength = <8>;
bias-disable;
};
- ws {
+ ws-pins {
pins = "gpio141";
function = "mi2s0_ws";
drive-strength = <8>;
output-high;
};
- data0 {
+ data0-pins {
pins = "gpio139";
function = "mi2s0_data0";
drive-strength = <8>;
@@ -3902,7 +4454,7 @@
output-high;
};
- data1 {
+ data1-pins {
pins = "gpio140";
function = "mi2s0_data1";
drive-strength = <8>;
@@ -3910,632 +4462,500 @@
};
};
- qup_i2c0_default: qup-i2c0-default {
- mux {
- pins = "gpio28", "gpio29";
- function = "qup0";
- };
-
- config {
- pins = "gpio28", "gpio29";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c0_default: qup-i2c0-default-state {
+ pins = "gpio28", "gpio29";
+ function = "qup0";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_i2c1_default: qup-i2c1-default {
- pinmux {
- pins = "gpio4", "gpio5";
- function = "qup1";
- };
-
- config {
- pins = "gpio4", "gpio5";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c1_default: qup-i2c1-default-state {
+ pins = "gpio4", "gpio5";
+ function = "qup1";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_i2c2_default: qup-i2c2-default {
- mux {
- pins = "gpio115", "gpio116";
- function = "qup2";
- };
-
- config {
- pins = "gpio115", "gpio116";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c2_default: qup-i2c2-default-state {
+ pins = "gpio115", "gpio116";
+ function = "qup2";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_i2c3_default: qup-i2c3-default {
- mux {
- pins = "gpio119", "gpio120";
- function = "qup3";
- };
-
- config {
- pins = "gpio119", "gpio120";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c3_default: qup-i2c3-default-state {
+ pins = "gpio119", "gpio120";
+ function = "qup3";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_i2c4_default: qup-i2c4-default {
- mux {
- pins = "gpio8", "gpio9";
- function = "qup4";
- };
-
- config {
- pins = "gpio8", "gpio9";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c4_default: qup-i2c4-default-state {
+ pins = "gpio8", "gpio9";
+ function = "qup4";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_i2c5_default: qup-i2c5-default {
- mux {
- pins = "gpio12", "gpio13";
- function = "qup5";
- };
-
- config {
- pins = "gpio12", "gpio13";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c5_default: qup-i2c5-default-state {
+ pins = "gpio12", "gpio13";
+ function = "qup5";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_i2c6_default: qup-i2c6-default {
- mux {
- pins = "gpio16", "gpio17";
- function = "qup6";
- };
-
- config {
- pins = "gpio16", "gpio17";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c6_default: qup-i2c6-default-state {
+ pins = "gpio16", "gpio17";
+ function = "qup6";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_i2c7_default: qup-i2c7-default {
- mux {
- pins = "gpio20", "gpio21";
- function = "qup7";
- };
-
- config {
- pins = "gpio20", "gpio21";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c7_default: qup-i2c7-default-state {
+ pins = "gpio20", "gpio21";
+ function = "qup7";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_i2c8_default: qup-i2c8-default {
- mux {
- pins = "gpio24", "gpio25";
- function = "qup8";
- };
-
- config {
- pins = "gpio24", "gpio25";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c8_default: qup-i2c8-default-state {
+ pins = "gpio24", "gpio25";
+ function = "qup8";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_i2c9_default: qup-i2c9-default {
- mux {
- pins = "gpio125", "gpio126";
- function = "qup9";
- };
-
- config {
- pins = "gpio125", "gpio126";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c9_default: qup-i2c9-default-state {
+ pins = "gpio125", "gpio126";
+ function = "qup9";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_i2c10_default: qup-i2c10-default {
- mux {
- pins = "gpio129", "gpio130";
- function = "qup10";
- };
-
- config {
- pins = "gpio129", "gpio130";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c10_default: qup-i2c10-default-state {
+ pins = "gpio129", "gpio130";
+ function = "qup10";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_i2c11_default: qup-i2c11-default {
- mux {
- pins = "gpio60", "gpio61";
- function = "qup11";
- };
-
- config {
- pins = "gpio60", "gpio61";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c11_default: qup-i2c11-default-state {
+ pins = "gpio60", "gpio61";
+ function = "qup11";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_i2c12_default: qup-i2c12-default {
- mux {
- pins = "gpio32", "gpio33";
- function = "qup12";
- };
-
- config {
- pins = "gpio32", "gpio33";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c12_default: qup-i2c12-default-state {
+ pins = "gpio32", "gpio33";
+ function = "qup12";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_i2c13_default: qup-i2c13-default {
- mux {
- pins = "gpio36", "gpio37";
- function = "qup13";
- };
-
- config {
- pins = "gpio36", "gpio37";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c13_default: qup-i2c13-default-state {
+ pins = "gpio36", "gpio37";
+ function = "qup13";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_i2c14_default: qup-i2c14-default {
- mux {
- pins = "gpio40", "gpio41";
- function = "qup14";
- };
-
- config {
- pins = "gpio40", "gpio41";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c14_default: qup-i2c14-default-state {
+ pins = "gpio40", "gpio41";
+ function = "qup14";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_i2c15_default: qup-i2c15-default {
- mux {
- pins = "gpio44", "gpio45";
- function = "qup15";
- };
-
- config {
- pins = "gpio44", "gpio45";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c15_default: qup-i2c15-default-state {
+ pins = "gpio44", "gpio45";
+ function = "qup15";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_i2c16_default: qup-i2c16-default {
- mux {
- pins = "gpio48", "gpio49";
- function = "qup16";
- };
-
- config {
- pins = "gpio48", "gpio49";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c16_default: qup-i2c16-default-state {
+ pins = "gpio48", "gpio49";
+ function = "qup16";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_i2c17_default: qup-i2c17-default {
- mux {
- pins = "gpio52", "gpio53";
- function = "qup17";
- };
-
- config {
- pins = "gpio52", "gpio53";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c17_default: qup-i2c17-default-state {
+ pins = "gpio52", "gpio53";
+ function = "qup17";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_i2c18_default: qup-i2c18-default {
- mux {
- pins = "gpio56", "gpio57";
- function = "qup18";
- };
-
- config {
- pins = "gpio56", "gpio57";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c18_default: qup-i2c18-default-state {
+ pins = "gpio56", "gpio57";
+ function = "qup18";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_i2c19_default: qup-i2c19-default {
- mux {
- pins = "gpio0", "gpio1";
- function = "qup19";
- };
-
- config {
- pins = "gpio0", "gpio1";
- drive-strength = <2>;
- bias-disable;
- };
+ qup_i2c19_default: qup-i2c19-default-state {
+ pins = "gpio0", "gpio1";
+ function = "qup19";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi0_cs: qup-spi0-cs {
+ qup_spi0_cs: qup-spi0-cs-state {
pins = "gpio31";
function = "qup0";
};
- qup_spi0_cs_gpio: qup-spi0-cs-gpio {
+ qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
pins = "gpio31";
function = "gpio";
};
- qup_spi0_data_clk: qup-spi0-data-clk {
+ qup_spi0_data_clk: qup-spi0-data-clk-state {
pins = "gpio28", "gpio29",
"gpio30";
function = "qup0";
};
- qup_spi1_cs: qup-spi1-cs {
+ qup_spi1_cs: qup-spi1-cs-state {
pins = "gpio7";
function = "qup1";
};
- qup_spi1_cs_gpio: qup-spi1-cs-gpio {
+ qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
pins = "gpio7";
function = "gpio";
};
- qup_spi1_data_clk: qup-spi1-data-clk {
+ qup_spi1_data_clk: qup-spi1-data-clk-state {
pins = "gpio4", "gpio5",
"gpio6";
function = "qup1";
};
- qup_spi2_cs: qup-spi2-cs {
+ qup_spi2_cs: qup-spi2-cs-state {
pins = "gpio118";
function = "qup2";
};
- qup_spi2_cs_gpio: qup-spi2-cs-gpio {
+ qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
pins = "gpio118";
function = "gpio";
};
- qup_spi2_data_clk: qup-spi2-data-clk {
+ qup_spi2_data_clk: qup-spi2-data-clk-state {
pins = "gpio115", "gpio116",
"gpio117";
function = "qup2";
};
- qup_spi3_cs: qup-spi3-cs {
+ qup_spi3_cs: qup-spi3-cs-state {
pins = "gpio122";
function = "qup3";
};
- qup_spi3_cs_gpio: qup-spi3-cs-gpio {
+ qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
pins = "gpio122";
function = "gpio";
};
- qup_spi3_data_clk: qup-spi3-data-clk {
+ qup_spi3_data_clk: qup-spi3-data-clk-state {
pins = "gpio119", "gpio120",
"gpio121";
function = "qup3";
};
- qup_spi4_cs: qup-spi4-cs {
+ qup_spi4_cs: qup-spi4-cs-state {
pins = "gpio11";
function = "qup4";
};
- qup_spi4_cs_gpio: qup-spi4-cs-gpio {
+ qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
pins = "gpio11";
function = "gpio";
};
- qup_spi4_data_clk: qup-spi4-data-clk {
+ qup_spi4_data_clk: qup-spi4-data-clk-state {
pins = "gpio8", "gpio9",
"gpio10";
function = "qup4";
};
- qup_spi5_cs: qup-spi5-cs {
+ qup_spi5_cs: qup-spi5-cs-state {
pins = "gpio15";
function = "qup5";
};
- qup_spi5_cs_gpio: qup-spi5-cs-gpio {
+ qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
pins = "gpio15";
function = "gpio";
};
- qup_spi5_data_clk: qup-spi5-data-clk {
+ qup_spi5_data_clk: qup-spi5-data-clk-state {
pins = "gpio12", "gpio13",
"gpio14";
function = "qup5";
};
- qup_spi6_cs: qup-spi6-cs {
+ qup_spi6_cs: qup-spi6-cs-state {
pins = "gpio19";
function = "qup6";
};
- qup_spi6_cs_gpio: qup-spi6-cs-gpio {
+ qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
pins = "gpio19";
function = "gpio";
};
- qup_spi6_data_clk: qup-spi6-data-clk {
+ qup_spi6_data_clk: qup-spi6-data-clk-state {
pins = "gpio16", "gpio17",
"gpio18";
function = "qup6";
};
- qup_spi7_cs: qup-spi7-cs {
+ qup_spi7_cs: qup-spi7-cs-state {
pins = "gpio23";
function = "qup7";
};
- qup_spi7_cs_gpio: qup-spi7-cs-gpio {
+ qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
pins = "gpio23";
function = "gpio";
};
- qup_spi7_data_clk: qup-spi7-data-clk {
+ qup_spi7_data_clk: qup-spi7-data-clk-state {
pins = "gpio20", "gpio21",
"gpio22";
function = "qup7";
};
- qup_spi8_cs: qup-spi8-cs {
+ qup_spi8_cs: qup-spi8-cs-state {
pins = "gpio27";
function = "qup8";
};
- qup_spi8_cs_gpio: qup-spi8-cs-gpio {
+ qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
pins = "gpio27";
function = "gpio";
};
- qup_spi8_data_clk: qup-spi8-data-clk {
+ qup_spi8_data_clk: qup-spi8-data-clk-state {
pins = "gpio24", "gpio25",
"gpio26";
function = "qup8";
};
- qup_spi9_cs: qup-spi9-cs {
+ qup_spi9_cs: qup-spi9-cs-state {
pins = "gpio128";
function = "qup9";
};
- qup_spi9_cs_gpio: qup-spi9-cs-gpio {
+ qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
pins = "gpio128";
function = "gpio";
};
- qup_spi9_data_clk: qup-spi9-data-clk {
+ qup_spi9_data_clk: qup-spi9-data-clk-state {
pins = "gpio125", "gpio126",
"gpio127";
function = "qup9";
};
- qup_spi10_cs: qup-spi10-cs {
+ qup_spi10_cs: qup-spi10-cs-state {
pins = "gpio132";
function = "qup10";
};
- qup_spi10_cs_gpio: qup-spi10-cs-gpio {
+ qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
pins = "gpio132";
function = "gpio";
};
- qup_spi10_data_clk: qup-spi10-data-clk {
+ qup_spi10_data_clk: qup-spi10-data-clk-state {
pins = "gpio129", "gpio130",
"gpio131";
function = "qup10";
};
- qup_spi11_cs: qup-spi11-cs {
+ qup_spi11_cs: qup-spi11-cs-state {
pins = "gpio63";
function = "qup11";
};
- qup_spi11_cs_gpio: qup-spi11-cs-gpio {
+ qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
pins = "gpio63";
function = "gpio";
};
- qup_spi11_data_clk: qup-spi11-data-clk {
+ qup_spi11_data_clk: qup-spi11-data-clk-state {
pins = "gpio60", "gpio61",
"gpio62";
function = "qup11";
};
- qup_spi12_cs: qup-spi12-cs {
+ qup_spi12_cs: qup-spi12-cs-state {
pins = "gpio35";
function = "qup12";
};
- qup_spi12_cs_gpio: qup-spi12-cs-gpio {
+ qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
pins = "gpio35";
function = "gpio";
};
- qup_spi12_data_clk: qup-spi12-data-clk {
+ qup_spi12_data_clk: qup-spi12-data-clk-state {
pins = "gpio32", "gpio33",
"gpio34";
function = "qup12";
};
- qup_spi13_cs: qup-spi13-cs {
+ qup_spi13_cs: qup-spi13-cs-state {
pins = "gpio39";
function = "qup13";
};
- qup_spi13_cs_gpio: qup-spi13-cs-gpio {
+ qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
pins = "gpio39";
function = "gpio";
};
- qup_spi13_data_clk: qup-spi13-data-clk {
+ qup_spi13_data_clk: qup-spi13-data-clk-state {
pins = "gpio36", "gpio37",
"gpio38";
function = "qup13";
};
- qup_spi14_cs: qup-spi14-cs {
+ qup_spi14_cs: qup-spi14-cs-state {
pins = "gpio43";
function = "qup14";
};
- qup_spi14_cs_gpio: qup-spi14-cs-gpio {
+ qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
pins = "gpio43";
function = "gpio";
};
- qup_spi14_data_clk: qup-spi14-data-clk {
+ qup_spi14_data_clk: qup-spi14-data-clk-state {
pins = "gpio40", "gpio41",
"gpio42";
function = "qup14";
};
- qup_spi15_cs: qup-spi15-cs {
+ qup_spi15_cs: qup-spi15-cs-state {
pins = "gpio47";
function = "qup15";
};
- qup_spi15_cs_gpio: qup-spi15-cs-gpio {
+ qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
pins = "gpio47";
function = "gpio";
};
- qup_spi15_data_clk: qup-spi15-data-clk {
+ qup_spi15_data_clk: qup-spi15-data-clk-state {
pins = "gpio44", "gpio45",
"gpio46";
function = "qup15";
};
- qup_spi16_cs: qup-spi16-cs {
+ qup_spi16_cs: qup-spi16-cs-state {
pins = "gpio51";
function = "qup16";
};
- qup_spi16_cs_gpio: qup-spi16-cs-gpio {
+ qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
pins = "gpio51";
function = "gpio";
};
- qup_spi16_data_clk: qup-spi16-data-clk {
+ qup_spi16_data_clk: qup-spi16-data-clk-state {
pins = "gpio48", "gpio49",
"gpio50";
function = "qup16";
};
- qup_spi17_cs: qup-spi17-cs {
+ qup_spi17_cs: qup-spi17-cs-state {
pins = "gpio55";
function = "qup17";
};
- qup_spi17_cs_gpio: qup-spi17-cs-gpio {
+ qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
pins = "gpio55";
function = "gpio";
};
- qup_spi17_data_clk: qup-spi17-data-clk {
+ qup_spi17_data_clk: qup-spi17-data-clk-state {
pins = "gpio52", "gpio53",
"gpio54";
function = "qup17";
};
- qup_spi18_cs: qup-spi18-cs {
+ qup_spi18_cs: qup-spi18-cs-state {
pins = "gpio59";
function = "qup18";
};
- qup_spi18_cs_gpio: qup-spi18-cs-gpio {
+ qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
pins = "gpio59";
function = "gpio";
};
- qup_spi18_data_clk: qup-spi18-data-clk {
+ qup_spi18_data_clk: qup-spi18-data-clk-state {
pins = "gpio56", "gpio57",
"gpio58";
function = "qup18";
};
- qup_spi19_cs: qup-spi19-cs {
+ qup_spi19_cs: qup-spi19-cs-state {
pins = "gpio3";
function = "qup19";
};
- qup_spi19_cs_gpio: qup-spi19-cs-gpio {
+ qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
pins = "gpio3";
function = "gpio";
};
- qup_spi19_data_clk: qup-spi19-data-clk {
+ qup_spi19_data_clk: qup-spi19-data-clk-state {
pins = "gpio0", "gpio1",
"gpio2";
function = "qup19";
};
- qup_uart2_default: qup-uart2-default {
- mux {
- pins = "gpio117", "gpio118";
- function = "qup2";
- };
+ qup_uart2_default: qup-uart2-default-state {
+ pins = "gpio117", "gpio118";
+ function = "qup2";
};
- qup_uart6_default: qup-uart6-default {
- mux {
- pins = "gpio16", "gpio17",
- "gpio18", "gpio19";
- function = "qup6";
- };
+ qup_uart6_default: qup-uart6-default-state {
+ pins = "gpio16", "gpio17", "gpio18", "gpio19";
+ function = "qup6";
};
- qup_uart12_default: qup-uart12-default {
- mux {
- pins = "gpio34", "gpio35";
- function = "qup12";
- };
+ qup_uart12_default: qup-uart12-default-state {
+ pins = "gpio34", "gpio35";
+ function = "qup12";
};
- qup_uart17_default: qup-uart17-default {
- mux {
- pins = "gpio52", "gpio53",
- "gpio54", "gpio55";
- function = "qup17";
- };
+ qup_uart17_default: qup-uart17-default-state {
+ pins = "gpio52", "gpio53", "gpio54", "gpio55";
+ function = "qup17";
};
- qup_uart18_default: qup-uart18-default {
- mux {
- pins = "gpio58", "gpio59";
- function = "qup18";
- };
+ qup_uart18_default: qup-uart18-default-state {
+ pins = "gpio58", "gpio59";
+ function = "qup18";
};
- tert_mi2s_active: tert-mi2s-active {
- sck {
+ tert_mi2s_active: tert-mi2s-active-state {
+ sck-pins {
pins = "gpio133";
function = "mi2s2_sck";
drive-strength = <8>;
bias-disable;
};
- data0 {
+ data0-pins {
pins = "gpio134";
function = "mi2s2_data0";
drive-strength = <8>;
@@ -4543,7 +4963,7 @@
output-high;
};
- ws {
+ ws-pins {
pins = "gpio135";
function = "mi2s2_ws";
drive-strength = <8>;
@@ -4551,42 +4971,42 @@
};
};
- sdc2_sleep_state: sdc2-sleep {
- clk {
+ sdc2_sleep_state: sdc2-sleep-state {
+ clk-pins {
pins = "sdc2_clk";
drive-strength = <2>;
bias-disable;
};
- cmd {
+ cmd-pins {
pins = "sdc2_cmd";
drive-strength = <2>;
bias-pull-up;
};
- data {
+ data-pins {
pins = "sdc2_data";
drive-strength = <2>;
bias-pull-up;
};
};
- pcie0_default_state: pcie0-default {
- perst {
+ pcie0_default_state: pcie0-default-state {
+ perst-pins {
pins = "gpio79";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- clkreq {
+ clkreq-pins {
pins = "gpio80";
function = "pci_e0";
drive-strength = <2>;
bias-pull-up;
};
- wake {
+ wake-pins {
pins = "gpio81";
function = "gpio";
drive-strength = <2>;
@@ -4594,22 +5014,22 @@
};
};
- pcie1_default_state: pcie1-default {
- perst {
+ pcie1_default_state: pcie1-default-state {
+ perst-pins {
pins = "gpio82";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- clkreq {
+ clkreq-pins {
pins = "gpio83";
function = "pci_e1";
drive-strength = <2>;
bias-pull-up;
};
- wake {
+ wake-pins {
pins = "gpio84";
function = "gpio";
drive-strength = <2>;
@@ -4617,22 +5037,22 @@
};
};
- pcie2_default_state: pcie2-default {
- perst {
+ pcie2_default_state: pcie2-default-state {
+ perst-pins {
pins = "gpio85";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- clkreq {
+ clkreq-pins {
pins = "gpio86";
function = "pci_e2";
drive-strength = <2>;
bias-pull-up;
};
- wake {
+ wake-pins {
pins = "gpio87";
function = "gpio";
drive-strength = <2>;
@@ -4791,13 +5211,13 @@
#address-cells = <1>;
#size-cells = <0>;
- apr-service@3 {
+ service@3 {
reg = <APR_SVC_ADSP_CORE>;
compatible = "qcom,q6core";
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
};
- q6afe: apr-service@4 {
+ q6afe: service@4 {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
@@ -4808,13 +5228,13 @@
#sound-dai-cells = <1>;
};
- q6afecc: cc {
+ q6afecc: clock-controller {
compatible = "qcom,q6afe-clocks";
#clock-cells = <2>;
};
};
- q6asm: apr-service@7 {
+ q6asm: service@7 {
compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
@@ -4827,7 +5247,7 @@
};
};
- q6adm: apr-service@8 {
+ q6adm: service@8 {
compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>;
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
@@ -4956,6 +5376,7 @@
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
<WAKE_TCS 3>, <CONTROL_TCS 1>;
+ power-domains = <&CLUSTER_PD>;
rpmhcc: clock-controller {
compatible = "qcom,sm8250-rpmh-clk";
@@ -5020,7 +5441,7 @@
};
epss_l3: interconnect@18590000 {
- compatible = "qcom,sm8250-epss-l3";
+ compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
reg = <0 0x18590000 0 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 69ae6503c2f6..26a608144886 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -107,9 +107,8 @@
regulator-max-microvolt = <888000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
- regulator-allowed-modes =
- <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6b_1p2: ldo6 {
@@ -118,9 +117,8 @@
regulator-max-microvolt = <1208000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
- regulator-allowed-modes =
- <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7b_2p96: ldo7 {
@@ -129,9 +127,8 @@
regulator-max-microvolt = <2504000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
- regulator-allowed-modes =
- <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9b_1p2: ldo9 {
@@ -140,9 +137,8 @@
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
- regulator-allowed-modes =
- <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts
index d21bbeb603a6..c74c973a69d2 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts
@@ -11,3 +11,209 @@
model = "Sony Xperia 1 III";
compatible = "sony,pdx215-generic", "qcom,sm8350";
};
+
+&tlmm {
+ gpio-line-names = "APPS_I2C_0_SDA", /* GPIO_0 */
+ "APPS_I2C_0_SCL",
+ "UWIDEC_PWR_EN",
+ "HAP_RST_N",
+ "WLC_I2C_SDA",
+ "WLC_I2C_SCL",
+ "PM8008_1_RESET_N",
+ "WLC_INT_N",
+ "OIS_TELE_I2C_SDA",
+ "OIS_TELE_I2C_SCL",
+ "PM8350_OPTION", /* GPIO_10 */
+ "NC",
+ "APPS_I2C_1_SDA",
+ "APPS_I2C_1_SCL",
+ "NC",
+ "NC",
+ "CAM1_RESET_N",
+ "LEO_CAM0_RESET_N",
+ "DEBUG_UART_TX",
+ "DEBUG_UART_RX",
+ "TS_I2C_SDA", /* GPIO_20 */
+ "TS_I2C_SCL",
+ "TS_RESET_N",
+ "TS_INT_N",
+ "DISP_RESET_N",
+ "SW_SERVICE",
+ "DISP_ERR_FG",
+ "TX_GTR_THRES_IN",
+ "NC",
+ "NC",
+ "NC", /* GPIO_30 */
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "SPK_AMP_INT_N",
+ "SPK_AMP_RESET_N",
+ "FP_INT_N",
+ "FP_RESET_N",
+ "NC", /* GPIO_40 */
+ "NC",
+ "DEBUG_GPIO0",
+ "FORCE_USB_BOOT",
+ "FP_SPI_MISO",
+ "FP_SPI_MOSI",
+ "FP_SPI_CLK",
+ "FP_SPI_CS_N",
+ "SPK_AMP_I2C_SDA",
+ "SPK_AMP_I2C_SCL",
+ "NC", /* GPIO_50 */
+ "HAP_INT_N",
+ "CAMSENSOR_I2C_SDA",
+ "CAMSENSOR_I2C_SCL",
+ "SBU_SW_OE",
+ "SBU_SW_SEL",
+ "NFC_ESE_SPI_MISO",
+ "NFC_ESE_SPI_MOSI",
+ "NFC_ESE_SPI_CLK",
+ "NFC_ESE_SPI_CS",
+ "NFC_I2C_SDA", /* GPIO_60 */
+ "NFC_I2C_SCL",
+ "NFC_EN",
+ "NFC_CLK_REQ",
+ "HST_WLAN_EN",
+ "HST_BT_EN",
+ "HW_ID_0",
+ "HW_ID_1",
+ "HST_BT_UART_CTS",
+ "HST_BT_UART_RFR",
+ "HST_BT_UART_TX", /* GPIO_70 */
+ "HST_BT_UART_RX",
+ "HAP_I2C_SDA",
+ "HAP_I2C_SCL",
+ "RF_LCD_ID_EN",
+ "RF_ID_EXTENSION",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "HALL_INT_N", /* GPIO_80 */
+ "USB_CC_DIR",
+ "DISP_VSYNC",
+ "NC",
+ "NC",
+ "CAM_SOF_TELE",
+ "NFC_DWL_REQ",
+ "NFC_IRQ",
+ "WCD_RST_N",
+ "ALS_PROX_INT_N",
+ "NC", /* GPIO_90 */
+ "NC",
+ "TRAY_DET",
+ "UDON_SWITCH_SEL",
+ "PCIE0_RESET_N",
+ "PCIE0_CLK_REQ_N",
+ "PCIE0_WAKE_N",
+ "CAM_SOF",
+ "RF_ID_EXTENSION_2",
+ "RGBC_IR_INT",
+ "CAM_MCLK0", /* GPIO_100 */
+ "CAM_MCLK1",
+ "CAM_MCLK2",
+ "CAM_MCLK3",
+ "CAM_MCLK4",
+ "NC",
+ "CAM2_RESET_N",
+ "CCI_I2C0_SDA",
+ "CCI_I2C0_SCL",
+ "CCI_I2C1_SDA",
+ "CCI_I2C1_SCL", /* GPIO_110 */
+ "CCI_I2C2_SDA",
+ "CCI_I2C2_SCL",
+ "CCI_I2C3_SDA",
+ "CCI_I2C3_SCL",
+ "NC",
+ "PM8008_1_IRQ",
+ "CAM3_RESET_N",
+ "IMU1_INT",
+ "EXT_VD0_XVS",
+ "NC", /* GPIO_120 */
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "HAP_I2S_CLK",
+ "HAP_I2S_DOUT",
+ "HAP_TRG1",
+ "HAP_I2S_SYNC",
+ "HST_BT_WLAN_SLIMBUS_CLK",
+ "HST_BT_WLAN_SLIMBUS_DAT0", /* GPIO_130 */
+ "NC",
+ "UIM2_DETECT_EN",
+ "UIM2_DATA",
+ "UIM2_CLK",
+ "UIM2_RESET",
+ "UIM2_PRESENT",
+ "UIM1_DATA",
+ "UIM1_CLK",
+ "UIM1_RESET",
+ "TRAY_DET", /* GPIO_140 */
+ "SM_RFFE0_CLK",
+ "SM_RFFE0_DATA",
+ "SM_RFFE1_CLK",
+ "SM_RFFE1_DATA",
+ "SM_MSS_GRFC4",
+ "SM_MSS_GRFC5",
+ "SM_MSS_GRFC6",
+ "SM_MSS_GRFC7",
+ "SM_RFFE4_CLK",
+ "SM_RFFE4_DATA", /* GPIO_150 */
+ "WLAN_COEX_UART1_RX",
+ "WLAN_COEX_UART1_TX",
+ "HST_SW_CTRL",
+ "DISP_VDDR_EN",
+ "NC",
+ "NC",
+ "PA_INDICATOR_OR",
+ "TOF_RST_N",
+ "QLINK0_REQ",
+ "QLINK0_EN", /* GPIO_160 */
+ "QLINK0_WMSS_RESET_N",
+ "QLINK1_REQ",
+ "QLINK1_EN",
+ "QLINK1_WMSS_RESET_N",
+ "PM8008_2_IRQ",
+ "TELEC_PWR_EN",
+ "PM8008_2_RESET_N",
+ "WCD_SWR_TX_CLK",
+ "WCD_SWR_TX_DATA0",
+ "WCD_SWR_TX_DATA1", /* GPIO_170 */
+ "WCD_SWR_RX_CLK",
+ "WCD_SWR_RX_DATA0",
+ "WCD_SWR_RX_DATA1",
+ "SM_DMIC1_CLK",
+ "SM_DMIC1_DATA",
+ "SM_DMIC2_CLK",
+ "SM_DMIC2_DATA",
+ "SPK_AMP_I2S_CLK",
+ "SPK_AMP_I2S_WS",
+ "SPK_AMP_I2S_ASP_DIN", /* GPIO_180 */
+ "SPK_AMP_I2S_ASP_DOUT",
+ "WCD_SWR_TX_DATA2",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "IMU_SPI_MISO",
+ "IMU_SPI_MOSI",
+ "IMU_SPI_CLK",
+ "IMU_SPI_CS_N", /* GPIO_190 */
+ "MAG_I2C_SDA",
+ "MAG_I2C_SCL",
+ "SENSOR_I2C_SDA",
+ "SENSOR_I2C_SCL",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "HST_BLE_UART_TX",
+ "HST_BLE_UART_RX", /* GPIO_200 */
+ "HST_WLAN_UART_TX",
+ "HST_WLAN_UART_RX";
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi
index b3c9952ac173..1f2d660f8f86 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
*/
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm8350.dtsi"
#include "pm8350.dtsi"
#include "pm8350b.dtsi"
@@ -73,16 +74,366 @@
no-map;
};
};
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&adsp {
status = "okay";
- firmware-name = "qcom/adsp.mbn";
+ firmware-name = "qcom/sm8350/Sony/sagami/adsp.mbn";
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8350-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+ vdd-s11-supply = <&vph_pwr>;
+ vdd-s12-supply = <&vph_pwr>;
+
+ vdd-l1-l4-supply = <&pm8350_s11>;
+ vdd-l2-l7-supply = <&vreg_bob>;
+ vdd-l3-l5-supply = <&vreg_bob>;
+ vdd-l6-l9-l10-supply = <&pm8350_s11>;
+
+ /*
+ * ARC regulators:
+ * S5 - mx.lvl
+ * S6 - gfx.lvl
+ * S9 - mxc.lvl
+ */
+
+ pm8350_s10: smps10 {
+ regulator-name = "pm8350_s10";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350_s11: smps11 {
+ regulator-name = "pm8350_s11";
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350_s12: smps12 {
+ regulator-name = "pm8350_s12";
+ regulator-min-microvolt = <1224000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350_l1: ldo1 {
+ regulator-name = "pm8350_l1";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350_l2: ldo2 {
+ regulator-name = "pm8350_l2";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350_l3: ldo3 {
+ regulator-name = "pm8350_l3";
+ regulator-min-microvolt = <904000>;
+ regulator-max-microvolt = <904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L4 - lmx.lvl (ARC) */
+
+ pm8350_l5: ldo5 {
+ regulator-name = "pm8350_l5";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <888000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ pm8350_l6: ldo6 {
+ regulator-name = "pm8350_l6";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1208000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ pm8350_l7: ldo7 {
+ regulator-name = "pm8350_l7";
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ /* L8 - lcx.lvl (ARC) */
+
+ pm8350_l9: ldo9 {
+ regulator-name = "pm8350_l9";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8350c-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+
+ vdd-l1-l12-supply = <&pm8350c_s1>;
+ vdd-l2-l8-supply = <&pm8350c_s1>;
+ vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
+ vdd-l6-l9-l11-supply = <&vreg_bob>;
+ vdd-l10-supply = <&pm8350_s12>;
+
+ vdd-bob-supply = <&vph_pwr>;
+
+ pm8350c_s1: smps1 {
+ regulator-name = "pm8350c_s1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1952000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* S2 - ebi.lvl (ARC) */
+
+ pm8350c_s3: smps3 {
+ regulator-name = "pm8350c_s3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <704000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /*
+ * ARC regulators:
+ * S4 - mss.lvl
+ * S6 - cx.lvl
+ * S8 - mmcx.lvl
+ */
+
+ pm8350c_s10: smps10 {
+ regulator-name = "pm8350c_s10";
+ regulator-min-microvolt = <1048000>;
+ regulator-max-microvolt = <1128000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l1: ldo1 {
+ regulator-name = "pm8350c_l1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l2: ldo2 {
+ regulator-name = "pm8350c_l2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l3: ldo3 {
+ regulator-name = "pm8350c_l3";
+ regulator-min-microvolt = <3304000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l4: ldo4 {
+ regulator-name = "pm8350c_l4";
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l5: ldo5 {
+ regulator-name = "pm8350c_l5";
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l6: ldo6 {
+ regulator-name = "pm8350c_l6";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l7: ldo7 {
+ regulator-name = "pm8350c_l7";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l8: ldo8 {
+ regulator-name = "pm8350c_l8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l9: ldo9 {
+ regulator-name = "pm8350c_l9";
+ regulator-min-microvolt = <2960000>;
+ /* Originally max = 3008000 but SDHCI expects 2960000 */
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l10: ldo10 {
+ regulator-name = "pm8350c_l10";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l11: ldo11 {
+ regulator-name = "pm8350c_l11";
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l12: ldo12 {
+ regulator-name = "pm8350c_l12";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l13: ldo13 {
+ regulator-name = "pm8350c_l13";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob: bob {
+ regulator-name = "vreg_bob";
+ regulator-min-microvolt = <3400000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ /* TODO: Add pm8350b (just one ldo) once the driver part is in */
+
+ regulators-2 {
+ compatible = "qcom,pmr735a-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+
+ vdd-l1-l2-supply = <&pmr735a_s2>;
+ vdd-l3-supply = <&pmr735a_s1>;
+ vdd-l4-supply = <&pm8350c_s1>;
+ vdd-l5-l6-supply = <&pm8350c_s1>;
+ vdd-l7-bob-supply = <&vreg_bob>;
+
+ pmr735a_s1: smps1 {
+ regulator-name = "pmr735a_s1";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1280000>;
+ };
+
+ pmr735a_s2: smps2 {
+ regulator-name = "pmr735a_s2";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <976000>;
+ };
+
+ pmr735a_s3: smps3 {
+ regulator-name = "pmr735a_s3";
+ regulator-min-microvolt = <2208000>;
+ regulator-max-microvolt = <2352000>;
+ };
+
+ pmr735a_l1: ldo1 {
+ regulator-name = "pmr735a_l1";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
+ };
+
+ pmr735a_l2: ldo2 {
+ regulator-name = "pmr735a_l2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pmr735a_l3: ldo3 {
+ regulator-name = "pmr735a_l3";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pmr735a_l4: ldo4 {
+ regulator-name = "pmr735a_l4";
+ regulator-min-microvolt = <1776000>;
+ regulator-max-microvolt = <1872000>;
+ };
+
+ pmr735a_l5: ldo5 {
+ regulator-name = "pmr735a_l5";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ };
+
+ pmr735a_l6: ldo6 {
+ regulator-name = "pmr735a_l6";
+ regulator-min-microvolt = <480000>;
+ regulator-max-microvolt = <904000>;
+ };
+
+ pmr735a_l7: ldo7 {
+ regulator-name = "pmr735a_l7";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+ };
};
&cdsp {
status = "okay";
- firmware-name = "qcom/cdsp.mbn";
+ firmware-name = "qcom/sm8350/Sony/sagami/cdsp.mbn";
};
&i2c1 {
@@ -175,12 +526,12 @@
&ipa {
status = "okay";
memory-region = <&pil_ipa_fw_mem>;
- firmware-name = "qcom/ipa_fws.mbn";
+ firmware-name = "qcom/sm8350/Sony/sagami/ipa_fws.mbn";
};
&mpss {
status = "okay";
- firmware-name = "qcom/modem.mbn";
+ firmware-name = "qcom/sm8350/Sony/sagami/modem.mbn";
};
&pmk8350_rtc {
@@ -208,9 +559,21 @@
status = "okay";
};
+&sdhc_2 {
+ cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_default_state &sdc2_card_det_active>;
+ pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_sleep>;
+ vmmc-supply = <&pm8350c_l9>;
+ vqmmc-supply = <&pm8350c_l6>;
+ no-sdio;
+ no-mmc;
+ status = "okay";
+};
+
&slpi {
status = "okay";
- firmware-name = "qcom/slpi.mbn";
+ firmware-name = "qcom/sm8350/Sony/sagami/slpi.mbn";
};
&spi14 {
@@ -221,6 +584,209 @@
&tlmm {
gpio-reserved-ranges = <44 4>;
+ gpio-line-names = "APPS_I2C_0_SDA", /* GPIO_0 */
+ "APPS_I2C_0_SCL",
+ "UWIDEC_PWR_EN",
+ "HAP_RST_N",
+ "NC",
+ "NC",
+ "PM8008_1_RESET_N",
+ "NC",
+ "OIS_TELE_I2C_SDA",
+ "OIS_TELE_I2C_SCL",
+ "PM8350_OPTION", /* GPIO_10 */
+ "NC",
+ "APPS_I2C_1_SDA",
+ "APPS_I2C_1_SCL",
+ "NC",
+ "NC",
+ "CAM1_RESET_N",
+ "LEO_CAM0_RESET_N",
+ "DEBUG_UART_TX",
+ "DEBUG_UART_RX",
+ "TS_I2C_SDA", /* GPIO_20 */
+ "TS_I2C_SCL",
+ "TS_RESET_N",
+ "TS_INT_N",
+ "DISP_RESET_N",
+ "SW_SERVICE",
+ "DISP_ERR_FG",
+ "TX_GTR_THRES_IN",
+ "NC",
+ "NC",
+ "NC", /* GPIO_30 */
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "SPK_AMP_INT_N",
+ "SPK_AMP_RESET_N",
+ "FP_INT_N",
+ "FP_RESET_N",
+ "NC", /* GPIO_40 */
+ "NC",
+ "DEBUG_GPIO0",
+ "FORCE_USB_BOOT",
+ "FP_SPI_MISO",
+ "FP_SPI_MOSI",
+ "FP_SPI_CLK",
+ "FP_SPI_CS_N",
+ "SPK_AMP_I2C_SDA",
+ "SPK_AMP_I2C_SCL",
+ "NC", /* GPIO_50 */
+ "HAP_INT_N",
+ "CAMSENSOR_I2C_SDA",
+ "CAMSENSOR_I2C_SCL",
+ "SBU_SW_OE",
+ "SBU_SW_SEL",
+ "NFC_ESE_SPI_MISO",
+ "NFC_ESE_SPI_MOSI",
+ "NFC_ESE_SPI_CLK",
+ "NFC_ESE_SPI_CS",
+ "NFC_I2C_SDA", /* GPIO_60 */
+ "NFC_I2C_SCL",
+ "NFC_EN",
+ "NFC_CLK_REQ",
+ "HST_WLAN_EN",
+ "HST_BT_EN",
+ "HW_ID_0",
+ "HW_ID_1",
+ "HST_BT_UART_CTS",
+ "HST_BT_UART_RFR",
+ "HST_BT_UART_TX", /* GPIO_70 */
+ "HST_BT_UART_RX",
+ "HAP_I2C_SDA",
+ "HAP_I2C_SCL",
+ "RF_LCD_ID_EN",
+ "RF_ID_EXTENSION",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "HALL_INT_N", /* GPIO_80 */
+ "USB_CC_DIR",
+ "DISP_VSYNC",
+ "NC",
+ "NC",
+ "CAM_SOF_TELE",
+ "NFC_DWL_REQ",
+ "NFC_IRQ",
+ "WCD_RST_N",
+ "ALS_PROX_INT_N",
+ "NC", /* GPIO_90 */
+ "NC",
+ "TRAY_DET",
+ "UDON_SWITCH_SEL",
+ "PCIE0_RESET_N",
+ "PCIE0_CLK_REQ_N",
+ "PCIE0_WAKE_N",
+ "CAM_SOF",
+ "RF_ID_EXTENSION_2",
+ "RGBC_IR_INT",
+ "CAM_MCLK0", /* GPIO_100 */
+ "CAM_MCLK1",
+ "CAM_MCLK2",
+ "CAM_MCLK3",
+ "NC",
+ "NC",
+ "CAM2_RESET_N",
+ "CCI_I2C0_SDA",
+ "CCI_I2C0_SCL",
+ "CCI_I2C1_SDA",
+ "CCI_I2C1_SCL", /* GPIO_110 */
+ "CCI_I2C2_SDA",
+ "CCI_I2C2_SCL",
+ "CCI_I2C3_SDA",
+ "CCI_I2C3_SCL",
+ "NC",
+ "PM8008_1_IRQ",
+ "CAM3_RESET_N",
+ "IMU1_INT",
+ "EXT_VD0_XVS",
+ "NC", /* GPIO_120 */
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "HAP_I2S_CLK",
+ "HAP_I2S_DOUT",
+ "HAP_TRG1",
+ "HAP_I2S_SYNC",
+ "HST_BT_WLAN_SLIMBUS_CLK",
+ "HST_BT_WLAN_SLIMBUS_DAT0", /* GPIO_130 */
+ "NC",
+ "UIM2_DETECT_EN",
+ "UIM2_DATA",
+ "UIM2_CLK",
+ "UIM2_RESET",
+ "UIM2_PRESENT",
+ "UIM1_DATA",
+ "UIM1_CLK",
+ "UIM1_RESET",
+ "TRAY_DET", /* GPIO_140 */
+ "SM_RFFE0_CLK",
+ "SM_RFFE0_DATA",
+ "SM_RFFE1_CLK",
+ "SM_RFFE1_DATA",
+ "SM_MSS_GRFC4",
+ "SM_MSS_GRFC5",
+ "SM_MSS_GRFC6",
+ "SM_MSS_GRFC7",
+ "SM_RFFE4_CLK",
+ "SM_RFFE4_DATA", /* GPIO_150 */
+ "WLAN_COEX_UART1_RX",
+ "WLAN_COEX_UART1_TX",
+ "HST_SW_CTRL",
+ "DISP_VDDR_EN",
+ "NC",
+ "NC",
+ "PA_INDICATOR_OR",
+ "NC",
+ "QLINK0_REQ",
+ "QLINK0_EN", /* GPIO_160 */
+ "QLINK0_WMSS_RESET_N",
+ "NC",
+ "NC",
+ "NC",
+ "PM8008_2_IRQ",
+ "TELEC_PWR_EN",
+ "PM8008_2_RESET_N",
+ "WCD_SWR_TX_CLK",
+ "WCD_SWR_TX_DATA0",
+ "WCD_SWR_TX_DATA1", /* GPIO_170 */
+ "WCD_SWR_RX_CLK",
+ "WCD_SWR_RX_DATA0",
+ "WCD_SWR_RX_DATA1",
+ "SM_DMIC1_CLK",
+ "SM_DMIC1_DATA",
+ "SM_DMIC2_CLK",
+ "SM_DMIC2_DATA",
+ "SPK_AMP_I2S_CLK",
+ "SPK_AMP_I2S_WS",
+ "SPK_AMP_I2S_ASP_DIN", /* GPIO_180 */
+ "SPK_AMP_I2S_ASP_DOUT",
+ "WCD_SWR_TX_DATA2",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "IMU_SPI_MISO",
+ "IMU_SPI_MOSI",
+ "IMU_SPI_CLK",
+ "IMU_SPI_CS_N", /* GPIO_190 */
+ "MAG_I2C_SDA",
+ "MAG_I2C_SCL",
+ "SENSOR_I2C_SDA",
+ "SENSOR_I2C_SCL",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "HST_BLE_UART_TX",
+ "HST_BLE_UART_RX", /* GPIO_200 */
+ "HST_WLAN_UART_TX",
+ "HST_WLAN_UART_RX";
ts_int_default: ts-int-default-state {
pins = "gpio23";
@@ -229,31 +795,45 @@
bias-disable;
input-enable;
};
+
+ sdc2_card_det_active: sd-card-det-active-state {
+ pins = "gpio92";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sdc2_card_det_sleep: sd-card-det-sleep-state {
+ pins = "gpio92";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
};
/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */
&ufs_mem_hc { status = "disabled"; };
&ufs_mem_phy { status = "disabled"; };
-/* TODO: Make USB3 work (perhaps needs regulators for higher-current operation?) */
&usb_1 {
status = "okay";
-
- qcom,select-utmi-as-pipe-clk;
};
&usb_1_dwc3 {
dr_mode = "peripheral";
-
- maximum-speed = "high-speed";
- phys = <&usb_1_hsphy>;
- phy-names = "usb2-phy";
};
&usb_1_hsphy {
status = "okay";
+
+ vdda-pll-supply = <&pm8350_l5>;
+ vdda18-supply = <&pm8350c_l1>;
+ vdda33-supply = <&pm8350_l2>;
};
&usb_1_qmpphy {
status = "okay";
+
+ vdda-phy-supply = <&pm8350_l6>;
+ vdda-pll-supply = <&pm8350_l1>;
};
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index a86d9ea93b9d..245dce24ec59 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -678,7 +678,7 @@
};
gpi_dma2: dma-controller@800000 {
- compatible = "qcom,sm8350-gpi-dma";
+ compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0 0x00800000 0 0x60000>;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
@@ -904,7 +904,7 @@
};
gpi_dma0: dma-controller@900000 {
- compatible = "qcom,sm8350-gpi-dma";
+ compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0 0x09800000 0 0x60000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
@@ -1209,7 +1209,7 @@
};
gpi_dma1: dma-controller@a00000 {
- compatible = "qcom,sm8350-gpi-dma";
+ compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0 0x00a00000 0 0x60000>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
@@ -1761,6 +1761,46 @@
gpio-ranges = <&tlmm 0 0 204>;
wakeup-parent = <&pdc>;
+ sdc2_default_state: sdc2-default-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_sleep_state: sdc2-sleep-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
qup_uart3_default_state: qup-uart3-default-state {
rx-pins {
pins = "gpio18";
@@ -2004,6 +2044,7 @@
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
<WAKE_TCS 3>, <CONTROL_TCS 0>;
+ power-domains = <&CLUSTER_PD>;
rpmhcc: clock-controller {
compatible = "qcom,sm8350-rpmh-clk";
@@ -2142,11 +2183,11 @@
status = "disabled";
ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x108>,
- <0 0x01d87600 0 0x1e0>,
- <0 0x01d87c00 0 0x1dc>,
- <0 0x01d87800 0 0x108>,
- <0 0x01d87a00 0 0x1e0>;
+ reg = <0 0x01d87400 0 0x188>,
+ <0 0x01d87600 0 0x200>,
+ <0 0x01d87c00 0 0x200>,
+ <0 0x01d87800 0 0x188>,
+ <0 0x01d87a00 0 0x200>;
#phy-cells = <0>;
};
};
@@ -2221,7 +2262,7 @@
cdsp: remoteproc@98900000 {
compatible = "qcom,sm8350-cdsp-pas";
- reg = <0 0x098900000 0 0x1400000>;
+ reg = <0 0x98900000 0 0x1400000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -2328,6 +2369,45 @@
};
};
+ sdhc_2: sdhci@8804000 {
+ compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0 0x08804000 0 0x1000>;
+
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "core", "xo";
+ resets = <&gcc GCC_SDCC2_BCR>;
+ interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
+ interconnect-names = "sdhc-ddr","cpu-sdhc";
+ iommus = <&apps_smmu 0x4a0 0x0>;
+ power-domains = <&rpmhpd SM8350_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+ bus-width = <4>;
+ dma-coherent;
+
+ status = "disabled";
+
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
usb_1_hsphy: phy@88e3000 {
compatible = "qcom,sm8350-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
index 38ccd44620d0..4de3e1f1c39c 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "sm8450.dtsi"
/ {
@@ -394,8 +395,181 @@
status = "okay";
};
+&sdhc_2 {
+ cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>;
+ vmmc-supply = <&vreg_l9c_2p96>;
+ vqmmc-supply = <&vreg_l6c_1p8>;
+ no-sdio;
+ no-mmc;
+ status = "okay";
+};
+
+&soc {
+ wcd938x: codec {
+ compatible = "qcom,wcd9380-codec";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wcd_default>;
+
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+ qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+ qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+ qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+ qcom,rx-device = <&wcd_rx>;
+ qcom,tx-device = <&wcd_tx>;
+
+ reset-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <1>;
+
+ vdd-buck-supply = <&vreg_s10b_1p8>;
+ vdd-rxtx-supply = <&vreg_s10b_1p8>;
+ vdd-io-supply = <&vreg_s10b_1p8>;
+ vdd-mic-bias-supply = <&vreg_bob>;
+ };
+};
+
+&sound {
+ compatible = "qcom,sm8450-sndcard";
+ model = "SM8450-HDK";
+ audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC2", "MIC BIAS2",
+ "VA DMIC0", "MIC BIAS1",
+ "VA DMIC1", "MIC BIAS1",
+ "VA DMIC2", "MIC BIAS3",
+ "TX DMIC0", "MIC BIAS1",
+ "TX DMIC1", "MIC BIAS2",
+ "TX DMIC2", "MIC BIAS3",
+ "TX SWR_ADC1", "ADC2_OUTPUT";
+
+ wcd-playback-dai-link {
+ link-name = "WCD Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wcd-capture-dai-link {
+ link-name = "WCD Capture";
+
+ cpu {
+ sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+ };
+
+ codec {
+ sound-dai = <&wcd938x 1>, <&swr2 0>, <&txmacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wsa-dai-link {
+ link-name = "WSA Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&wsamacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ va-dai-link {
+ link-name = "VA Capture";
+
+ cpu {
+ sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+ };
+
+ codec {
+ sound-dai = <&vamacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+};
+
+&swr0 {
+ left_spkr: speaker@0,1 {
+ compatible = "sdw10217020200";
+ reg = <0 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spkr_1_sd_n_active>;
+ powerdown-gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrLeft";
+ #thermal-sensor-cells = <0>;
+ vdd-supply = <&vreg_s10b_1p8>;
+ };
+
+ right_spkr: speaker@0,2 {
+ compatible = "sdw10217020200";
+ reg = <0 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spkr_2_sd_n_active>;
+ powerdown-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrRight";
+ #thermal-sensor-cells = <0>;
+ vdd-supply = <&vreg_s10b_1p8>;
+ };
+};
+
+&swr1 {
+ status = "okay";
+
+ wcd_rx: codec@0,4 {
+ compatible = "sdw20217010d00";
+ reg = <0 4>;
+ qcom,rx-port-mapping = <1 2 3 4 5>;
+ };
+};
+
+&swr2 {
+ status = "okay";
+
+ wcd_tx: codec@0,3 {
+ compatible = "sdw20217010d00";
+ reg = <0 3>;
+ qcom,tx-port-mapping = <1 1 2 3>;
+ };
+};
+
&tlmm {
gpio-reserved-ranges = <28 4>, <36 4>;
+
+ sdc2_card_det_n: sd-card-det-n-state {
+ pins = "gpio92";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
};
&uart7 {
@@ -442,3 +616,34 @@
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l1b_0p91>;
};
+
+&vamacro {
+ pinctrl-0 = <&dmic01_default>, <&dmic02_default>;
+ pinctrl-names = "default";
+ vdd-micb-supply = <&vreg_s10b_1p8>;
+ qcom,dmic-sample-rate = <600000>;
+};
+
+&tlmm {
+ spkr_1_sd_n_active: spkr-1-sd-n-active-state {
+ pins = "gpio1";
+ function = "gpio";
+ drive-strength = <4>;
+ bias-disable;
+ output-low;
+ };
+
+ spkr_2_sd_n_active: spkr-2-sd-n-active-state {
+ pins = "gpio89";
+ function = "gpio";
+ drive-strength = <4>;
+ bias-disable;
+ output-low;
+ };
+
+ wcd_default: wcd-default-state {
+ pins = "gpio43";
+ function = "gpio";
+ bias-disable;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
index e58fc7399799..ee62514fff68 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts
@@ -388,6 +388,18 @@
firmware-name = "qcom/sm8450/slpi.mbn";
};
+&sdhc_2 {
+ cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>;
+ vmmc-supply = <&vreg_l9c_2p96>;
+ vqmmc-supply = <&vreg_l6c_1p8>;
+ no-sdio;
+ no-mmc;
+ status = "okay";
+};
+
&spi4 {
status = "okay";
};
@@ -402,6 +414,13 @@
&tlmm {
gpio-reserved-ranges = <28 4>, <36 4>;
+
+ sdc2_card_det_n: sd-card-det-n-state {
+ pins = "gpio92";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
};
&uart7 {
diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts
index d68765eb6d4f..b83500316a81 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts
@@ -1,634 +1,227 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org>
+ * Copyright (c) 2022, Linaro Limited
*/
/dts-v1/;
-#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
-#include "sm8450.dtsi"
-
-/delete-node/ &adsp_mem;
-/delete-node/ &rmtfs_mem;
-/delete-node/ &video_mem;
+#include "sm8450-sony-xperia-nagara.dtsi"
/ {
model = "Sony Xperia 1 IV";
compatible = "sony,pdx223", "qcom,sm8450";
- chassis-type = "handset";
-
- aliases {
- serial0 = &uart7;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- reserved-memory {
- adsp_mem: memory@85700000 {
- reg = <0x0 0x85700000 0x0 0x2800000>;
- no-map;
- };
-
- video_mem: memory@9fd00000 {
- reg = <0x0 0x9fd00000 0x0 0x700000>;
- no-map;
- };
-
- rmtfs_mem: memory@f3300000 {
- compatible = "qcom,rmtfs-mem";
- reg = <0x0 0xf3300000 0x0 0x280000>;
- no-map;
-
- qcom,client-id = <1>;
- qcom,vmid = <15>;
- };
-
- ramoops@ffc00000 {
- compatible = "ramoops";
- reg = <0 0xffc00000 0 0x200000>;
- console-size = <0x40000>;
- record-size = <0x1000>;
- ecc-size = <16>;
- no-map;
- };
- };
-
- /* Sadly, the voltages for these GPIO regulators are unknown. */
- imx650_vana_vreg: imx650-vana-regulator {
- compatible = "regulator-fixed";
- regulator-name = "imx650_vana_vreg";
- gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vph_pwr: vph-pwr-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vph_pwr";
- regulator-min-microvolt = <3700000>;
- regulator-max-microvolt = <3700000>;
-
- regulator-always-on;
- regulator-boot-on;
- };
-};
-
-&apps_rsc {
- pm8350-rpmh-regulators {
- compatible = "qcom,pm8350-rpmh-regulators";
- qcom,pmic-id = "b";
-
- vdd-s1-supply = <&vph_pwr>;
- vdd-s2-supply = <&vph_pwr>;
- vdd-s3-supply = <&vph_pwr>;
- vdd-s4-supply = <&vph_pwr>;
- vdd-s5-supply = <&vph_pwr>;
- vdd-s6-supply = <&vph_pwr>;
- vdd-s7-supply = <&vph_pwr>;
- vdd-s8-supply = <&vph_pwr>;
- vdd-s9-supply = <&vph_pwr>;
- vdd-s10-supply = <&vph_pwr>;
- vdd-s11-supply = <&vph_pwr>;
- vdd-s12-supply = <&vph_pwr>;
-
- vdd-l1-l4-supply = <&pm8350_s11>;
- vdd-l2-l7-supply = <&vreg_bob>;
- vdd-l3-l5-supply = <&vreg_bob>;
- vdd-l6-l9-l10-supply = <&pm8350_s12>;
-
- /*
- * ARC regulators:
- * s5 - gfx.lvl
- * l8 - lcx.lvl
- */
-
- pm8350_s10: smps10 {
- regulator-name = "pm8350_s10";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- pm8350_s11: smps11 {
- regulator-name = "pm8350_s11";
- regulator-min-microvolt = <848000>;
- regulator-max-microvolt = <1104000>;
- };
-
- pm8350_s12: smps12 {
- regulator-name = "pm8350_s12";
- regulator-min-microvolt = <1224000>;
- regulator-max-microvolt = <1400000>;
- };
-
- pm8350_l1: ldo1 {
- regulator-name = "pm8350_l1";
- regulator-min-microvolt = <912000>;
- regulator-max-microvolt = <920000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- pm8350_l2: ldo2 {
- regulator-name = "pm8350_l2";
- regulator-min-microvolt = <3072000>;
- regulator-max-microvolt = <3072000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- pm8350_l3: ldo3 {
- regulator-name = "pm8350_l3";
- regulator-min-microvolt = <904000>;
- regulator-max-microvolt = <904000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- pm8350_l5: ldo5 {
- regulator-name = "pm8350_l5";
- regulator-min-microvolt = <880000>;
- regulator-max-microvolt = <912000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- pm8350_l6: ldo6 {
- regulator-name = "pm8350_l6";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- pm8350_l7: ldo7 {
- regulator-name = "pm8350_l7";
- regulator-min-microvolt = <2504000>;
- regulator-max-microvolt = <2504000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- pm8350_l9: ldo9 {
- regulator-name = "pm8350_l9";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
- };
-
- pm8350c-rpmh-regulators {
- compatible = "qcom,pm8350c-rpmh-regulators";
- qcom,pmic-id = "c";
-
- vdd-s1-supply = <&vph_pwr>;
- vdd-s2-supply = <&vph_pwr>;
- vdd-s3-supply = <&vph_pwr>;
- vdd-s4-supply = <&vph_pwr>;
- vdd-s5-supply = <&vph_pwr>;
- vdd-s6-supply = <&vph_pwr>;
- vdd-s7-supply = <&vph_pwr>;
- vdd-s8-supply = <&vph_pwr>;
- vdd-s9-supply = <&vph_pwr>;
- vdd-s10-supply = <&vph_pwr>;
-
- vdd-l1-l12-supply = <&vreg_bob>;
- vdd-l2-l8-supply = <&vreg_bob>;
- vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
- vdd-l6-l9-l11-supply = <&vreg_bob>;
- vdd-l10-supply = <&pm8350_s12>;
-
- vdd-bob-supply = <&vph_pwr>;
-
- /*
- * ARC regulators:
- * s2 - mxc.lvl
- * s4 - mss.lvl
- * s6 - cx.lvl
- */
-
- pm8350c_s1: smps1 {
- regulator-name = "pm8350c_s1";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2024000>;
- };
-
- pm8350c_s10: smps10 {
- regulator-name = "pm8350c_s10";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1100000>;
- };
-
- vreg_bob: bob {
- regulator-name = "vreg_bob";
- regulator-min-microvolt = <3400000>;
- regulator-max-microvolt = <3960000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
- };
-
- pm8350c_l1: ldo1 {
- regulator-name = "pm8350c_l1";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- pm8350c_l2: ldo2 {
- regulator-name = "pm8350c_l2";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- pm8350c_l3: ldo3 {
- regulator-name = "pm8350c_l3";
- regulator-min-microvolt = <3296000>;
- regulator-max-microvolt = <3304000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- pm8350c_l4: ldo4 {
- regulator-name = "pm8350c_l4";
- regulator-min-microvolt = <1704000>;
- regulator-max-microvolt = <3000000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- pm8350c_l5: ldo5 {
- regulator-name = "pm8350c_l5";
- regulator-min-microvolt = <1704000>;
- regulator-max-microvolt = <3000000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- pm8350c_l6: ldo6 {
- regulator-name = "pm8350c_l6";
- regulator-min-microvolt = <2960000>;
- /* Originally max = 3008000 but SDHCI expects 2960000 */
- regulator-max-microvolt = <2960000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- pm8350c_l7: ldo7 {
- regulator-name = "pm8350c_l7";
- regulator-min-microvolt = <3008000>;
- regulator-max-microvolt = <3008000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- pm8350c_l8: ldo8 {
- regulator-name = "pm8350c_l8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- pm8350c_l9: ldo9 {
- regulator-name = "pm8350c_l9";
- regulator-min-microvolt = <2960000>;
- /* Originally max = 3008000 but SDHCI expects 2960000 */
- regulator-max-microvolt = <2960000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- pm8350c_l10: ldo10 {
- regulator-name = "pm8350c_l10";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- pm8350c_l12: ldo12 {
- regulator-name = "pm8350c_l12";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1968000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- pm8350c_l13: ldo13 {
- regulator-name = "pm8350c_l13";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
- };
-
- pm8450-rpmh-regulators {
- compatible = "qcom,pm8450-rpmh-regulators";
- qcom,pmic-id = "h";
-
- vdd-s1-supply = <&vph_pwr>;
- vdd-s2-supply = <&vph_pwr>;
- vdd-s3-supply = <&vph_pwr>;
- vdd-s4-supply = <&vph_pwr>;
- vdd-s5-supply = <&vph_pwr>;
- vdd-s6-supply = <&vph_pwr>;
-
- vdd-l2-supply = <&vreg_bob>;
- vdd-l3-supply = <&vreg_bob>;
- vdd-l4-supply = <&vreg_bob>;
-
- /*
- * ARC regulators:
- * S2 - ebi.lvl
- * S4 - mmcx.lvl
- * S6 - mx.lvl
- * L1 - lmx.lvl
- */
-
- pm8450_s3: smps3 {
- regulator-name = "pm8450_s3";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <600000>;
- };
-
- pm8450_l2: ldo2 {
- regulator-name = "pm8450_l2";
- regulator-min-microvolt = <880000>;
- regulator-max-microvolt = <912000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- pm8450_l3: ldo3 {
- regulator-name = "pm8450_l3";
- regulator-min-microvolt = <912000>;
- regulator-max-microvolt = <912000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
- };
-
- pmr735a-rpmh-regulators {
- compatible = "qcom,pmr735a-rpmh-regulators";
- qcom,pmic-id = "e";
-
- vdd-s1-supply = <&vph_pwr>;
- vdd-s2-supply = <&vph_pwr>;
- vdd-s3-supply = <&vph_pwr>;
-
- vdd-l1-l2-supply = <&pmr735a_s2>;
- vdd-l3-supply = <&pmr735a_s1>;
- vdd-l4-supply = <&pm8350c_s1>;
- vdd-l5-l6-supply = <&pm8350c_s1>;
- vdd-l7-bob-supply = <&vreg_bob>;
-
- pmr735a_s1: smps1 {
- regulator-name = "pmr735a_s1";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1296000>;
- };
-
- pmr735a_s2: smps2 {
- regulator-name = "pmr735a_s2";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1040000>;
- };
-
- pmr735a_s3: smps3 {
- regulator-name = "pmr735a_s3";
- regulator-min-microvolt = <435000>;
- regulator-max-microvolt = <2352000>;
- };
-
- pmr735a_l1: ldo1 {
- regulator-name = "pmr735a_l1";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <800000>;
- };
-
- pmr735a_l2: ldo2 {
- regulator-name = "pmr735a_l2";
- regulator-min-microvolt = <480000>;
- regulator-max-microvolt = <912000>;
- };
-
- pmr735a_l3: ldo3 {
- regulator-name = "pmr735a_l3";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- pmr735a_l4: ldo4 {
- regulator-name = "pmr735a_l4";
- regulator-min-microvolt = <1776000>;
- regulator-max-microvolt = <1776000>;
- };
-
- pmr735a_l5: ldo5 {
- regulator-name = "pmr735a_l5";
- regulator-min-microvolt = <880000>;
- regulator-max-microvolt = <880000>;
- };
-
- pmr735a_l6: ldo6 {
- regulator-name = "pmr735a_l6";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
-
- pmr735a_l7: ldo7 {
- regulator-name = "pmr735a_l7";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- };
- };
-};
-
-&gpi_dma0 {
- status = "okay";
-};
-
-&gpi_dma1 {
- status = "okay";
-};
-
-&gpi_dma2 {
- status = "okay";
-};
-
-/* I2C4 is used, it hosts a Samsung touchscreen, but GPI DMA is broken.. */
-
-&i2c5 {
- clock-frequency = <400000>;
- status = "okay";
-
- /* Dialog SLG51000 CMIC @ 75 */
-};
-
-&i2c9 {
- clock-frequency = <400000>;
- status = "okay";
-
- /* NXP SN1X0 NFC @ 28 */
-};
-
-&i2c13 {
- clock-frequency = <400000>;
- status = "okay";
-
- /* Richwave RTC6226 FM Radio Receiver @ 64 */
-};
-
-&i2c14 {
- clock-frequency = <1000000>;
- status = "okay";
-
- cs35l41_l: speaker-amp@40 {
- compatible = "cirrus,cs35l41";
- reg = <0x40>;
- interrupt-parent = <&tlmm>;
- interrupts = <182 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&tlmm 183 GPIO_ACTIVE_HIGH>;
- cirrus,boost-peak-milliamp = <4000>;
- cirrus,boost-ind-nanohenry = <1000>;
- cirrus,boost-cap-microfarad = <15>;
- cirrus,gpio2-src-select = <2>;
- cirrus,gpio2-output-enable;
- cirrus,asp-sdout-hiz = <3>;
- #sound-dai-cells = <1>;
- };
-
- cs35l41_r: speaker-amp@41 {
- compatible = "cirrus,cs35l41";
- reg = <0x41>;
- interrupt-parent = <&tlmm>;
- interrupts = <182 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&tlmm 183 GPIO_ACTIVE_HIGH>;
- cirrus,boost-peak-milliamp = <4000>;
- cirrus,boost-ind-nanohenry = <1000>;
- cirrus,boost-cap-microfarad = <15>;
- cirrus,gpio2-src-select = <2>;
- cirrus,gpio2-output-enable;
- cirrus,asp-sdout-hiz = <3>;
- #sound-dai-cells = <1>;
- };
-};
-
-&i2c15 {
- clock-frequency = <400000>;
- status = "okay";
-
- /* AMS TCS3490 RGB+IR color sensor @ 72 */
-};
-
-&i2c19 {
- clock-frequency = <1000000>;
- status = "okay";
-
- /* Cirrus Logic CS40L25A boosted haptics driver @ 40 */
-};
-
-&pcie0 {
- max-link-speed = <2>;
- status = "okay";
-};
-
-&pcie0_phy {
- vdda-phy-supply = <&pm8350_l5>;
- vdda-pll-supply = <&pm8350_l6>;
- status = "okay";
-};
-
-&remoteproc_adsp {
- firmware-name = "qcom/adsp.mbn";
- status = "okay";
-};
-
-&remoteproc_cdsp {
- firmware-name = "qcom/cdsp.mbn";
- status = "okay";
-};
-
-&remoteproc_slpi {
- firmware-name = "qcom/slpi.mbn";
- status = "okay";
-};
-
-&qupv3_id_0 {
- status = "okay";
-};
-
-&qupv3_id_1 {
- status = "okay";
-};
-
-&qupv3_id_2 {
- status = "okay";
-};
-
-&sdhc_2 {
- cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;
- pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>;
- vmmc-supply = <&pm8350c_l9>;
- vqmmc-supply = <&pm8350c_l6>;
- /* Forbid SDR104/SDR50 - broken hw! */
- sdhci-caps-mask = <0x3 0x0>;
- no-sdio;
- no-mmc;
- status = "okay";
-};
-
-&spi10 {
- status = "okay";
-
- /* NXP SN1X0 NFC Secure Element @ 0 */
};
&tlmm {
- gpio-reserved-ranges = <28 4>;
-
- sdc2_default_state: sdc2-default-state {
- clk-pins {
- pins = "sdc2_clk";
- drive-strength = <16>;
- bias-disable;
- };
-
- cmd-pins {
- pins = "sdc2_cmd";
- drive-strength = <16>;
- bias-pull-up;
- };
-
- data-pins {
- pins = "sdc2_data";
- drive-strength = <16>;
- bias-pull-up;
- };
- };
-
- ts_int_default: ts-int-default-state {
- pins = "gpio23";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- input-enable;
- };
-
- sdc2_card_det_n: sd-card-det-n-state {
- pins = "gpio92";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
-};
-
-&uart7 {
- status = "okay";
-};
-
-&usb_1 {
- status = "okay";
-};
-
-&usb_1_dwc3 {
- dr_mode = "peripheral";
-};
-
-&usb_1_hsphy {
- vdda-pll-supply = <&pm8350_l5>;
- vdda18-supply = <&pm8350c_l1>;
- vdda33-supply = <&pm8350_l2>;
- status = "okay";
-};
-
-&usb_1_qmpphy {
- vdda-phy-supply = <&pm8350_l6>;
- vdda-pll-supply = <&pm8350_l1>;
- status = "okay";
+ gpio-line-names = "NC", /* GPIO_0 */
+ "NC",
+ "NC",
+ "NC",
+ "WLC_I2C_SDA",
+ "WLC_I2C_SCL",
+ "NC",
+ "PM8010_1_RESET_N",
+ "WLC_INT_N",
+ "NC",
+ "NC", /* GPIO_10 */
+ "PM8010_2_RESET_N",
+ "DISP_ERR_FG",
+ "HALL_INT_N",
+ "ALS_PROX_INT_N",
+ "IMU1_INT",
+ "TS_I2C_SDA",
+ "TS_I2C_SCL",
+ "DISP_RESET_N",
+ "DISP_VDDR_EN",
+ "TS_RESET_N", /* GPIO_20 */
+ "TS_INT_N",
+ "NC",
+ "TELEC_PWR_EN",
+ "CAM1_RESET_N",
+ "LEO_CAM0_RESET_N",
+ "DEBUG_UART_TX",
+ "DEBUG_UART_RX",
+ "FP_SPI_MISO",
+ "FP_SPI_MOSI",
+ "FP_SPI_CLK", /* GPIO_30 */
+ "FP_SPI_CS_N",
+ "NFC_I2C_SDA",
+ "NFC_I2C_SCL",
+ "NFC_EN",
+ "NFC_CLK_REQ",
+ "NFC_ESE_SPI_MISO",
+ "NFC_ESE_SPI_MOSI",
+ "NFC_ESE_SPI_CLK",
+ "NFC_ESE_SPI_CS",
+ "FP_INT_N", /* GPIO_40 */
+ "NC",
+ "FP_RESET_N",
+ "WCD_RST_N",
+ "NC",
+ "NFC_DWL_REQ",
+ "NFC_IRQ",
+ "FORCE_USB_BOOT",
+ "APPS_I2C_1_SDA",
+ "APPS_I2C_1_SCL",
+ "SBU_SW_OE", /* GPIO_50 */
+ "SBU_SW_SEL",
+ "SPK_AMP_I2C_SDA",
+ "SPK_AMP_I2C_SCL",
+ "NC",
+ "NC",
+ "CAMSENSOR_I2C_SDA",
+ "CAMSENSOR_I2C_SCL",
+ "GNSS_ELNA_EN0",
+ "NC",
+ "NC", /* GPIO_60 */
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "RGBC_IR_INT",
+ "NC",
+ "NC",
+ "NC",
+ "NC", /* GPIO_70 */
+ "NC",
+ "HAP_I2C_SDA",
+ "HAP_I2C_SCL",
+ "HAP_RST_N",
+ "HAP_INT_N",
+ "HST_BT_UART_CTS",
+ "HST_BT_UART_RFR",
+ "HST_BT_UART_TX",
+ "HST_BT_UART_RX",
+ "HST_WLAN_EN", /* GPIO_80 */
+ "HST_BT_EN",
+ "HST_SW_CTRL",
+ "NC",
+ "NC",
+ "NC",
+ "DISP_VSYNC",
+ "NC",
+ "NC",
+ "HW_ID_0",
+ "HW_ID_1", /* GPIO_90 */
+ "USB_CC_DIR",
+ "TRAY_DET",
+ "SW_SERVICE",
+ "PCIE0_RESET_N",
+ "PCIE0_CLK_REQ_N",
+ "PCIE0_WAKE_N",
+ "OIS_ENABLE_WIDE",
+ "DEBUG_GPIO0",
+ "NC",
+ "CAM_MCLK0", /* GPIO_100 */
+ "CAM_MCLK1",
+ "CAM_MCLK2",
+ "CAM_MCLK3",
+ "NC",
+ "NC",
+ "TOF_RST_N",
+ "CAM_SOF",
+ "NC",
+ "AFEXPTMG_TELE",
+ "CCI_I2C0_SDA", /* GPIO_110 */
+ "CCI_I2C0_SCL",
+ "CCI_I2C1_SDA",
+ "CCI_I2C1_SCL",
+ "CCI_I2C2_SDA",
+ "CCI_I2C2_SCL",
+ "NC",
+ "CAM2_RESET_N",
+ "NC",
+ "EXT_VD0_XVS",
+ "CAM3_RESET_N", /* GPIO_120 */
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "RF_ID_EXTENSION_2",
+ "HAP_I2S_CLK",
+ "HAP_I2S_DOUT",
+ "HAP_TRG1",
+ "HAP_I2S_SYNC",
+ "UIM1_DATA", /* GPIO_130 */
+ "UIM1_CLK",
+ "UIM1_RESET",
+ "TRAY_DET",
+ "UIM2_DATA",
+ "UIM2_CLK",
+ "UIM2_RESET",
+ "UIM2_PRESENT",
+ "SM_RFFE0_CLK",
+ "SM_RFFE0_DATA",
+ "SM_RFFE1_CLK", /* GPIO_140 */
+ "SM_RFFE1_DATA",
+ "SM_MSS_GRFC4",
+ "HST_AS_EN",
+ "LAA_RX_EN",
+ "NC",
+ "SM_RFFE4_CLK",
+ "SM_RFFE4_DATA",
+ "WLAN_COEX_UART1_RX",
+ "WLAN_COEX_UART1_TX",
+ "RF_LCD_ID_EN", /* GPIO_150 */
+ "RF_ID_EXTENSION",
+ "SM_MSS_GRFC12",
+ "NFC_COLD_RST",
+ "NC",
+ "NC",
+ "SDR1_QLINK0_REQ",
+ "SDR1_QLINK0_EN",
+ "SDR1_QLINK0_WMSS_RESET_N",
+ "QLINK1_REQ",
+ "QLINK1_EN", /* GPIO_160 */
+ "QLINK1_WMSS_RESET_N",
+ "SDR2_QLINK2_REQ",
+ "SDR2_QLINK2_EN",
+ "SDR2_QLINK2_WMSS_RESET_N",
+ "WCD_SWR_TX_CLK",
+ "WCD_SWR_TX_DATA0",
+ "WCD_SWR_TX_DATA1",
+ "WCD_SWR_RX_CLK",
+ "WCD_SWR_RX_DATA0",
+ "WCD_SWR_RX_DATA1", /* GPIO_170 */
+ "SM_DMIC1_CLK",
+ "SM_DMIC1_DATA",
+ "SM_DMIC2_CLK",
+ "SM_DMIC2_DATA",
+ "SPK_AMP_I2S_CLK",
+ "SPK_AMP_I2S_WS",
+ "NC",
+ "NC",
+ "WCD_SWR_TX_DATA2",
+ "SPK_AMP_I2S_ASP_DIN", /* GPIO_180 */
+ "SPK_AMP_I2S_ASP_DOUT",
+ "SPK_AMP_INT_N",
+ "SPK_AMP_RESET_N",
+ "HST_BT_WLAN_SLIMBUS_CLK",
+ "HST_BT_WLAN_SLIMBUS_DAT0",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "MAG_I2C_SDA", /* GPIO_190 */
+ "MAG_I2C_SCL",
+ "IMU_SPI_MISO",
+ "IMU_SPI_MOSI",
+ "IMU_SPI_CLK",
+ "IMU_SPI_CS_N",
+ "SENSOR_I2C_SDA",
+ "SENSOR_I2C_SCL",
+ "OIS_TELE_I2C_SDA",
+ "OIS_TELE_I2C_SCL",
+ "NC", /* GPIO_200 */
+ "OIS_ENABLE_TELE",
+ "HST_BLE_UART_TX",
+ "HST_BLE_UART_RX",
+ "HSTP_CLK_CFG_SEL",
+ "NC",
+ "APPS_I2C_0_SDA",
+ "APPS_I2C_0_SCL",
+ "CCI_I2C3_SDA",
+ "CCI_I2C3_SCL";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts
new file mode 100644
index 000000000000..13c2fc4bccfc
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts
@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org>
+ * Copyright (c) 2022, Linaro Limited
+ */
+
+/dts-v1/;
+
+#include "sm8450-sony-xperia-nagara.dtsi"
+
+/ {
+ model = "Sony Xperia 5 IV";
+ compatible = "sony,pdx224", "qcom,sm8450";
+
+ imx563_vdig_vreg: imx563-vdig-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "imx563_vdig_vreg";
+ gpio = <&tlmm 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&tlmm {
+ gpio-line-names = "TELE_SPI_MISO", /* GPIO_0 */
+ "TELE_SPI_MOSI", /* SONY says NC, but it only makes sense this way.. */
+ "TELE_SPI_CLK",
+ "TELE_SPI_CS_N",
+ "WLC_I2C_SDA",
+ "WLC_I2C_SCL",
+ "NC",
+ "PM8010_1_RESET_N",
+ "WLC_INT_N",
+ "NC",
+ "NC", /* GPIO_10 */
+ "NC",
+ "DISP_ERR_FG",
+ "HALL_INT_N",
+ "ALS_PROX_INT_N",
+ "IMU1_INT",
+ "TS_I2C_SDA",
+ "TS_I2C_SCL",
+ "DISP_RESET_N",
+ "DISP_VDDR_EN",
+ "TS_RESET_N", /* GPIO_20 */
+ "TS_INT_N",
+ "UWIDEC_PWR_EN",
+ "TELEC_PWR_EN",
+ "CAM1_RESET_N",
+ "LEO_CAM0_RESET_N",
+ "DEBUG_UART_TX",
+ "DEBUG_UART_RX",
+ "FP_SPI_MISO",
+ "FP_SPI_MOSI",
+ "FP_SPI_CLK", /* GPIO_30 */
+ "FP_SPI_CS_N",
+ "NFC_I2C_SDA",
+ "NFC_I2C_SCL",
+ "NFC_EN",
+ "NFC_CLK_REQ",
+ "NFC_ESE_SPI_MISO",
+ "NFC_ESE_SPI_MOSI",
+ "NFC_ESE_SPI_CLK",
+ "NFC_ESE_SPI_CS",
+ "FP_INT_N", /* GPIO_40 */
+ "NC",
+ "FP_RESET_N",
+ "WCD_RST_N",
+ "NC",
+ "NFC_DWL_REQ",
+ "NFC_IRQ",
+ "FORCE_USB_BOOT",
+ "APPS_I2C_1_SDA",
+ "APPS_I2C_1_SCL",
+ "SBU_SW_OE", /* GPIO_50 */
+ "SBU_SW_SEL",
+ "SPK_AMP_I2C_SDA",
+ "SPK_AMP_I2C_SCL",
+ "NC",
+ "NC",
+ "CAMSENSOR_I2C_SDA",
+ "CAMSENSOR_I2C_SCL",
+ "GNSS_ELNA_EN0",
+ "NC",
+ "NC", /* GPIO_60 */
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "RGBC_IR_INT",
+ "NC",
+ "NC",
+ "NC",
+ "NC", /* GPIO_70 */
+ "NC",
+ "HAP_I2C_SDA",
+ "HAP_I2C_SCL",
+ "HAP_RST_N",
+ "HAP_INT_N",
+ "HST_BT_UART_CTS",
+ "HST_BT_UART_RFR",
+ "HST_BT_UART_TX",
+ "HST_BT_UART_RX",
+ "HST_WLAN_EN", /* GPIO_80 */
+ "HST_BT_EN",
+ "HST_SW_CTRL",
+ "NC",
+ "NC",
+ "NC",
+ "DISP_VSYNC",
+ "NC",
+ "NC",
+ "HW_ID_0",
+ "HW_ID_1", /* GPIO_90 */
+ "USB_CC_DIR",
+ "TRAY_DET",
+ "SW_SERVICE",
+ "PCIE0_RESET_N",
+ "PCIE0_CLK_REQ_N",
+ "PCIE0_WAKE_N",
+ "OIS_ENABLE_WIDE",
+ "DEBUG_GPIO0",
+ "NC",
+ "CAM_MCLK0", /* GPIO_100 */
+ "CAM_MCLK1",
+ "CAM_MCLK2",
+ "CAM_MCLK3",
+ "NC",
+ "NC",
+ "NC", /* SONY didn't rename this, but there's no ToF so it's likely NC */
+ "CAM_SOF",
+ "NC",
+ "AFEXPTMG_TELE",
+ "CCI_I2C0_SDA", /* GPIO_110 */
+ "CCI_I2C0_SCL",
+ "CCI_I2C1_SDA",
+ "CCI_I2C1_SCL",
+ "CCI_I2C2_SDA",
+ "CCI_I2C2_SCL",
+ "NC",
+ "CAM2_RESET_N",
+ "NC",
+ "EXT_VD0_XVS",
+ "CAM3_RESET_N", /* GPIO_120 */
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "RF_ID_EXTENSION_2",
+ "HAP_I2S_CLK",
+ "HAP_I2S_DOUT",
+ "HAP_TRG1",
+ "HAP_I2S_SYNC",
+ "UIM1_DATA", /* GPIO_130 */
+ "UIM1_CLK",
+ "UIM1_RESET",
+ "TRAY_DET",
+ "UIM2_DATA",
+ "UIM2_CLK",
+ "UIM2_RESET",
+ "UIM2_PRESENT",
+ "SM_RFFE0_CLK",
+ "SM_RFFE0_DATA",
+ "SM_RFFE1_CLK", /* GPIO_140 */
+ "SM_RFFE1_DATA",
+ "SM_MSS_GRFC4",
+ "HST_AS_EN",
+ "LAA_RX_EN",
+ "NC",
+ "SM_RFFE4_CLK",
+ "SM_RFFE4_DATA",
+ "WLAN_COEX_UART1_RX",
+ "WLAN_COEX_UART1_TX",
+ "RF_LCD_ID_EN", /* GPIO_150 */
+ "RF_ID_EXTENSION",
+ "SM_MSS_GRFC12",
+ "NFC_COLD_RST",
+ "NC",
+ "NC",
+ "SDR1_QLINK0_REQ",
+ "SDR1_QLINK0_EN",
+ "SDR1_QLINK0_WMSS_RESET_N",
+ "NC",
+ "NC", /* GPIO_160 */
+ "NC",
+ "SDR2_QLINK2_REQ",
+ "SDR2_QLINK2_EN",
+ "SDR2_QLINK2_WMSS_RESET_N",
+ "WCD_SWR_TX_CLK",
+ "WCD_SWR_TX_DATA0",
+ "WCD_SWR_TX_DATA1",
+ "WCD_SWR_RX_CLK",
+ "WCD_SWR_RX_DATA0",
+ "WCD_SWR_RX_DATA1", /* GPIO_170 */
+ "SM_DMIC1_CLK",
+ "SM_DMIC1_DATA",
+ "SM_DMIC2_CLK",
+ "SM_DMIC2_DATA",
+ "SPK_AMP_I2S_CLK",
+ "SPK_AMP_I2S_WS",
+ "NC",
+ "NC",
+ "WCD_SWR_TX_DATA2",
+ "SPK_AMP_I2S_ASP_DIN", /* GPIO_180 */
+ "SPK_AMP_I2S_ASP_DOUT",
+ "SPK_AMP_INT_N",
+ "SPK_AMP_RESET_N",
+ "HST_BT_WLAN_SLIMBUS_CLK",
+ "HST_BT_WLAN_SLIMBUS_DAT0",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "MAG_I2C_SDA", /* GPIO_190 */
+ "MAG_I2C_SCL",
+ "IMU_SPI_MISO",
+ "IMU_SPI_MOSI",
+ "IMU_SPI_CLK",
+ "IMU_SPI_CS_N",
+ "SENSOR_I2C_SDA",
+ "SENSOR_I2C_SCL",
+ "OIS_TELE_I2C_SDA",
+ "OIS_TELE_I2C_SCL",
+ "NC", /* GPIO_200 */
+ "OIS_ENABLE_TELE",
+ "HST_BLE_UART_TX",
+ "HST_BLE_UART_RX",
+ "HSTP_CLK_CFG_SEL",
+ "NC",
+ "APPS_I2C_0_SDA",
+ "APPS_I2C_0_SCL",
+ "CCI_I2C3_SDA",
+ "CCI_I2C3_SCL";
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
new file mode 100644
index 000000000000..38256226d229
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
@@ -0,0 +1,631 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8450.dtsi"
+
+/delete-node/ &adsp_mem;
+/delete-node/ &rmtfs_mem;
+/delete-node/ &video_mem;
+
+/ {
+ chassis-type = "handset";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ adsp_mem: memory@85700000 {
+ reg = <0x0 0x85700000 0x0 0x2800000>;
+ no-map;
+ };
+
+ video_mem: memory@9fd00000 {
+ reg = <0x0 0x9fd00000 0x0 0x700000>;
+ no-map;
+ };
+
+ rmtfs_mem: memory@f3300000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0 0xf3300000 0x0 0x280000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <15>;
+ };
+
+ ramoops@ffc00000 {
+ compatible = "ramoops";
+ reg = <0 0xffc00000 0 0x200000>;
+ console-size = <0x40000>;
+ record-size = <0x1000>;
+ ecc-size = <16>;
+ no-map;
+ };
+ };
+
+ /* Sadly, the voltages for these GPIO regulators are unknown. */
+ imx650_vana_vreg: imx650-vana-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "imx650_vana_vreg";
+ gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&apps_rsc {
+ pm8350-rpmh-regulators {
+ compatible = "qcom,pm8350-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+ vdd-s11-supply = <&vph_pwr>;
+ vdd-s12-supply = <&vph_pwr>;
+
+ vdd-l1-l4-supply = <&pm8350_s11>;
+ vdd-l2-l7-supply = <&vreg_bob>;
+ vdd-l3-l5-supply = <&vreg_bob>;
+ vdd-l6-l9-l10-supply = <&pm8350_s12>;
+
+ /*
+ * ARC regulators:
+ * s5 - gfx.lvl
+ * l8 - lcx.lvl
+ */
+
+ pm8350_s10: smps10 {
+ regulator-name = "pm8350_s10";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8350_s11: smps11 {
+ regulator-name = "pm8350_s11";
+ regulator-min-microvolt = <848000>;
+ regulator-max-microvolt = <1104000>;
+ };
+
+ pm8350_s12: smps12 {
+ regulator-name = "pm8350_s12";
+ regulator-min-microvolt = <1224000>;
+ regulator-max-microvolt = <1400000>;
+ };
+
+ pm8350_l1: ldo1 {
+ regulator-name = "pm8350_l1";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350_l2: ldo2 {
+ regulator-name = "pm8350_l2";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350_l3: ldo3 {
+ regulator-name = "pm8350_l3";
+ regulator-min-microvolt = <904000>;
+ regulator-max-microvolt = <904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350_l5: ldo5 {
+ regulator-name = "pm8350_l5";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350_l6: ldo6 {
+ regulator-name = "pm8350_l6";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350_l7: ldo7 {
+ regulator-name = "pm8350_l7";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350_l9: ldo9 {
+ regulator-name = "pm8350_l9";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pm8350c-rpmh-regulators {
+ compatible = "qcom,pm8350c-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+
+ vdd-l1-l12-supply = <&vreg_bob>;
+ vdd-l2-l8-supply = <&vreg_bob>;
+ vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
+ vdd-l6-l9-l11-supply = <&vreg_bob>;
+ vdd-l10-supply = <&pm8350_s12>;
+
+ vdd-bob-supply = <&vph_pwr>;
+
+ /*
+ * ARC regulators:
+ * s2 - mxc.lvl
+ * s4 - mss.lvl
+ * s6 - cx.lvl
+ */
+
+ pm8350c_s1: smps1 {
+ regulator-name = "pm8350c_s1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2024000>;
+ };
+
+ pm8350c_s10: smps10 {
+ regulator-name = "pm8350c_s10";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ vreg_bob: bob {
+ regulator-name = "vreg_bob";
+ regulator-min-microvolt = <3400000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ pm8350c_l1: ldo1 {
+ regulator-name = "pm8350c_l1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l2: ldo2 {
+ regulator-name = "pm8350c_l2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l3: ldo3 {
+ regulator-name = "pm8350c_l3";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l4: ldo4 {
+ regulator-name = "pm8350c_l4";
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l5: ldo5 {
+ regulator-name = "pm8350c_l5";
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l6: ldo6 {
+ regulator-name = "pm8350c_l6";
+ regulator-min-microvolt = <2960000>;
+ /* Originally max = 3008000 but SDHCI expects 2960000 */
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l7: ldo7 {
+ regulator-name = "pm8350c_l7";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l8: ldo8 {
+ regulator-name = "pm8350c_l8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l9: ldo9 {
+ regulator-name = "pm8350c_l9";
+ regulator-min-microvolt = <2960000>;
+ /* Originally max = 3008000 but SDHCI expects 2960000 */
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l10: ldo10 {
+ regulator-name = "pm8350c_l10";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l12: ldo12 {
+ regulator-name = "pm8350c_l12";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1968000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8350c_l13: ldo13 {
+ regulator-name = "pm8350c_l13";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pm8450-rpmh-regulators {
+ compatible = "qcom,pm8450-rpmh-regulators";
+ qcom,pmic-id = "h";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ vdd-l2-supply = <&vreg_bob>;
+ vdd-l3-supply = <&vreg_bob>;
+ vdd-l4-supply = <&vreg_bob>;
+
+ /*
+ * ARC regulators:
+ * S2 - ebi.lvl
+ * S4 - mmcx.lvl
+ * S6 - mx.lvl
+ * L1 - lmx.lvl
+ */
+
+ pm8450_s3: smps3 {
+ regulator-name = "pm8450_s3";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <600000>;
+ };
+
+ pm8450_l2: ldo2 {
+ regulator-name = "pm8450_l2";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ pm8450_l3: ldo3 {
+ regulator-name = "pm8450_l3";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pmr735a-rpmh-regulators {
+ compatible = "qcom,pmr735a-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+
+ vdd-l1-l2-supply = <&pmr735a_s2>;
+ vdd-l3-supply = <&pmr735a_s1>;
+ vdd-l4-supply = <&pm8350c_s1>;
+ vdd-l5-l6-supply = <&pm8350c_s1>;
+ vdd-l7-bob-supply = <&vreg_bob>;
+
+ pmr735a_s1: smps1 {
+ regulator-name = "pmr735a_s1";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1296000>;
+ };
+
+ pmr735a_s2: smps2 {
+ regulator-name = "pmr735a_s2";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1040000>;
+ };
+
+ pmr735a_s3: smps3 {
+ regulator-name = "pmr735a_s3";
+ regulator-min-microvolt = <435000>;
+ regulator-max-microvolt = <2352000>;
+ };
+
+ pmr735a_l1: ldo1 {
+ regulator-name = "pmr735a_l1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ };
+
+ pmr735a_l2: ldo2 {
+ regulator-name = "pmr735a_l2";
+ regulator-min-microvolt = <480000>;
+ regulator-max-microvolt = <912000>;
+ };
+
+ pmr735a_l3: ldo3 {
+ regulator-name = "pmr735a_l3";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pmr735a_l4: ldo4 {
+ regulator-name = "pmr735a_l4";
+ regulator-min-microvolt = <1776000>;
+ regulator-max-microvolt = <1776000>;
+ };
+
+ pmr735a_l5: ldo5 {
+ regulator-name = "pmr735a_l5";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ };
+
+ pmr735a_l6: ldo6 {
+ regulator-name = "pmr735a_l6";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pmr735a_l7: ldo7 {
+ regulator-name = "pmr735a_l7";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+ };
+};
+
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpi_dma2 {
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ touchscreen@48 {
+ compatible = "samsung,s6sy761";
+ reg = <0x48>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <21 0x2008>;
+ vdd-supply = <&pm8350c_l2>;
+ avdd-supply = <&pm8350c_l3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_reset_default &ts_int_default>;
+ };
+};
+
+&i2c5 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ /* Dialog SLG51000 CMIC @ 75 */
+};
+
+&i2c9 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ /* NXP SN1X0 NFC @ 28 */
+};
+
+&i2c13 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ /* Richwave RTC6226 FM Radio Receiver @ 64 */
+};
+
+&i2c14 {
+ clock-frequency = <1000000>;
+ status = "okay";
+
+ cs35l41_l: speaker-amp@40 {
+ compatible = "cirrus,cs35l41";
+ reg = <0x40>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <182 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&tlmm 183 GPIO_ACTIVE_HIGH>;
+ cirrus,boost-peak-milliamp = <4000>;
+ cirrus,boost-ind-nanohenry = <1000>;
+ cirrus,boost-cap-microfarad = <15>;
+ cirrus,gpio2-src-select = <2>;
+ cirrus,gpio2-output-enable;
+ cirrus,asp-sdout-hiz = <3>;
+ #sound-dai-cells = <1>;
+ };
+
+ cs35l41_r: speaker-amp@41 {
+ compatible = "cirrus,cs35l41";
+ reg = <0x41>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <182 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&tlmm 183 GPIO_ACTIVE_HIGH>;
+ cirrus,boost-peak-milliamp = <4000>;
+ cirrus,boost-ind-nanohenry = <1000>;
+ cirrus,boost-cap-microfarad = <15>;
+ cirrus,gpio2-src-select = <2>;
+ cirrus,gpio2-output-enable;
+ cirrus,asp-sdout-hiz = <3>;
+ #sound-dai-cells = <1>;
+ };
+};
+
+&i2c15 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ /* AMS TCS3490 RGB+IR color sensor @ 72 */
+};
+
+&i2c19 {
+ clock-frequency = <1000000>;
+ status = "okay";
+
+ /* Cirrus Logic CS40L25A boosted haptics driver @ 40 */
+};
+
+&pcie0 {
+ max-link-speed = <2>;
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&pm8350_l5>;
+ vdda-pll-supply = <&pm8350_l6>;
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm8350/Sony/nagara/adsp.mbn";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/sm8350/Sony/nagara/cdsp.mbn";
+ status = "okay";
+};
+
+&remoteproc_slpi {
+ firmware-name = "qcom/sm8350/Sony/nagara/slpi.mbn";
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&qupv3_id_2 {
+ status = "okay";
+};
+
+&sdhc_2 {
+ cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>;
+ vmmc-supply = <&pm8350c_l9>;
+ vqmmc-supply = <&pm8350c_l6>;
+ no-sdio;
+ no-mmc;
+ status = "okay";
+};
+
+&spi10 {
+ status = "okay";
+
+ /* NXP SN1X0 NFC Secure Element @ 0 */
+};
+
+&tlmm {
+ gpio-reserved-ranges = <28 4>;
+
+ ts_reset_default: ts-reset-default-state {
+ pins = "gpio20";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+
+ ts_int_default: ts-int-default-state {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ input-enable;
+ };
+
+ sdc2_card_det_n: sd-card-det-n-state {
+ pins = "gpio92";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+ vdda-pll-supply = <&pm8350_l5>;
+ vdda18-supply = <&pm8350c_l1>;
+ vdda33-supply = <&pm8350_l2>;
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ vdda-phy-supply = <&pm8350_l6>;
+ vdda-pll-supply = <&pm8350_l1>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index d32f08df743d..570475040d95 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -7,12 +7,15 @@
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8450-camcc.h>
+#include <dt-bindings/clock/qcom,sm8450-dispcc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/interconnect/qcom,sm8450.h>
+#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -51,6 +54,7 @@
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
+ clocks = <&cpufreq_hw 0>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -70,6 +74,7 @@
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
+ clocks = <&cpufreq_hw 0>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -86,6 +91,7 @@
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
+ clocks = <&cpufreq_hw 0>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -102,6 +108,7 @@
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
+ clocks = <&cpufreq_hw 0>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -118,6 +125,7 @@
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
+ clocks = <&cpufreq_hw 1>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -134,6 +142,7 @@
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
+ clocks = <&cpufreq_hw 1>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -151,6 +160,7 @@
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
+ clocks = <&cpufreq_hw 1>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -167,6 +177,7 @@
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 2>;
#cooling-cells = <2>;
+ clocks = <&cpufreq_hw 2>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -730,7 +741,7 @@
};
gpi_dma2: dma-controller@800000 {
- compatible = "qcom,sm8450-gpi-dma";
+ compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
#dma-cells = <3>;
reg = <0 0x800000 0 0x60000>;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
@@ -791,7 +802,6 @@
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
- spi-max-frequency = <50000000>;
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
interconnect-names = "qup-core", "qup-config";
@@ -831,7 +841,6 @@
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
- spi-max-frequency = <50000000>;
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
interconnect-names = "qup-core", "qup-config";
@@ -871,7 +880,6 @@
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
- spi-max-frequency = <50000000>;
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
interconnect-names = "qup-core", "qup-config";
@@ -911,7 +919,6 @@
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
- spi-max-frequency = <50000000>;
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
interconnect-names = "qup-core", "qup-config";
@@ -951,7 +958,6 @@
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
- spi-max-frequency = <50000000>;
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
interconnect-names = "qup-core", "qup-config";
@@ -1004,7 +1010,6 @@
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
- spi-max-frequency = <50000000>;
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
interconnect-names = "qup-core", "qup-config";
@@ -1044,7 +1049,6 @@
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
- spi-max-frequency = <50000000>;
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
interconnect-names = "qup-core", "qup-config";
@@ -1058,7 +1062,7 @@
};
gpi_dma0: dma-controller@900000 {
- compatible = "qcom,sm8450-gpi-dma";
+ compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
#dma-cells = <3>;
reg = <0 0x900000 0 0x60000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
@@ -1394,7 +1398,7 @@
};
gpi_dma1: dma-controller@a00000 {
- compatible = "qcom,sm8450-gpi-dma";
+ compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
#dma-cells = <3>;
reg = <0 0xa00000 0 0x60000>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
@@ -2095,9 +2099,212 @@
};
};
+ wsa2macro: codec@31e0000 {
+ compatible = "qcom,sm8450-lpass-wsa-macro";
+ reg = <0 0x031e0000 0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&vamacro>;
+ clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
+ assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ assigned-clock-rates = <19200000>, <19200000>;
+
+ #clock-cells = <0>;
+ clock-output-names = "wsa2-mclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wsa2_swr_active>;
+ #sound-dai-cells = <1>;
+ };
+
+ /* WSA2 */
+ swr4: soundwire-controller@31f0000 {
+ compatible = "qcom,soundwire-v1.7.0";
+ reg = <0 0x031f0000 0 0x2000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&wsa2macro>;
+ clock-names = "iface";
+
+ qcom,din-ports = <2>;
+ qcom,dout-ports = <6>;
+
+ qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
+ qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
+ qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+
+ rxmacro: codec@3200000 {
+ compatible = "qcom,sm8450-lpass-rx-macro";
+ reg = <0 0x3200000 0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&vamacro>;
+ clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
+
+ assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ assigned-clock-rates = <19200000>, <19200000>;
+
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rx_swr_active>;
+ #sound-dai-cells = <1>;
+ };
+
+ swr1: soundwire-controller@3210000 {
+ compatible = "qcom,soundwire-v1.7.0";
+ reg = <0 0x3210000 0 0x2000>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rxmacro>;
+ clock-names = "iface";
+ label = "RX";
+ qcom,din-ports = <0>;
+ qcom,dout-ports = <5>;
+
+ qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
+ qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
+ qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
+ qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+
+ txmacro: codec@3220000 {
+ compatible = "qcom,sm8450-lpass-tx-macro";
+ reg = <0 0x3220000 0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&vamacro>;
+ clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
+ assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ assigned-clock-rates = <19200000>, <19200000>;
+
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&tx_swr_active>;
+ #sound-dai-cells = <1>;
+ };
+
+ wsamacro: codec@3240000 {
+ compatible = "qcom,sm8450-lpass-wsa-macro";
+ reg = <0 0x03240000 0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&vamacro>;
+ clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
+
+ assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ assigned-clock-rates = <19200000>, <19200000>;
+
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wsa_swr_active>;
+ #sound-dai-cells = <1>;
+ };
+
+ /* WSA */
+ swr0: soundwire-controller@3250000 {
+ compatible = "qcom,soundwire-v1.7.0";
+ reg = <0 0x03250000 0 0x2000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&wsamacro>;
+ clock-names = "iface";
+
+ qcom,din-ports = <2>;
+ qcom,dout-ports = <6>;
+
+ qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
+ qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
+ qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+
+ swr2: soundwire-controller@33b0000 {
+ compatible = "qcom,soundwire-v1.7.0";
+ reg = <0 0x33b0000 0 0x2000>;
+ interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "core", "wake";
+
+ clocks = <&vamacro>;
+ clock-names = "iface";
+ label = "TX";
+
+ qcom,din-ports = <4>;
+ qcom,dout-ports = <0>;
+ qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
+ qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+
+ vamacro: codec@33f0000 {
+ compatible = "qcom,sm8450-lpass-va-macro";
+ reg = <0 0x033f0000 0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "mclk", "macro", "dcodec", "npl";
+ assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ assigned-clock-rates = <19200000>;
+
+ #clock-cells = <0>;
+ clock-output-names = "fsgen";
+ #sound-dai-cells = <1>;
+ };
+
remoteproc_adsp: remoteproc@30000000 {
compatible = "qcom,sm8450-adsp-pas";
- reg = <0 0x030000000 0 0x100>;
+ reg = <0 0x30000000 0 0x100>;
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -2133,6 +2340,45 @@
label = "lpass";
qcom,remote-pid = <2>;
+ gpr {
+ compatible = "qcom,gpr";
+ qcom,glink-channels = "adsp_apps";
+ qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+ qcom,intents = <512 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ q6apm: service@1 {
+ compatible = "qcom,q6apm";
+ reg = <GPR_APM_MODULE_IID>;
+ #sound-dai-cells = <0>;
+ qcom,protection-domain = "avs/audio",
+ "msm/adsp/audio_pd";
+
+ q6apmdai: dais {
+ compatible = "qcom,q6apm-dais";
+ iommus = <&apps_smmu 0x1801 0x0>;
+ };
+
+ q6apmbedai: bedais {
+ compatible = "qcom,q6apm-lpass-dais";
+ #sound-dai-cells = <1>;
+ };
+ };
+
+ q6prm: service@2 {
+ compatible = "qcom,q6prm";
+ reg = <GPR_PRM_MODULE_IID>;
+ qcom,protection-domain = "avs/audio",
+ "msm/adsp/audio_pd";
+
+ q6prmcc: clock-controller {
+ compatible = "qcom,q6prm-lpass-clocks";
+ #clock-cells = <2>;
+ };
+ };
+ };
+
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
@@ -2163,7 +2409,7 @@
remoteproc_cdsp: remoteproc@32300000 {
compatible = "qcom,sm8450-cdsp-pas";
- reg = <0 0x032300000 0 0x1400000>;
+ reg = <0 0x32300000 0 0x1400000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -2283,8 +2529,8 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
- power-domains = <&rpmhpd 0>,
- <&rpmhpd 12>;
+ power-domains = <&rpmhpd SM8450_CX>,
+ <&rpmhpd SM8450_MSS>;
power-domain-names = "cx", "mss";
memory-region = <&mpss_mem>;
@@ -2307,6 +2553,84 @@
};
};
+ cci0: cci@ac15000 {
+ compatible = "qcom,sm8450-cci";
+ reg = <0 0xac15000 0 0x1000>;
+ interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK_SRC>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci",
+ "cci_src";
+ pinctrl-0 = <&cci0_default &cci1_default>;
+ pinctrl-1 = <&cci0_sleep &cci1_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@ac16000 {
+ compatible = "qcom,sm8450-cci";
+ reg = <0 0xac16000 0 0x1000>;
+ interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK_SRC>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci",
+ "cci_src";
+ pinctrl-0 = <&cci2_default &cci3_default>;
+ pinctrl-1 = <&cci2_sleep &cci3_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
camcc: clock-controller@ade0000 {
compatible = "qcom,sm8450-camcc";
reg = <0 0x0ade0000 0 0x20000>;
@@ -2322,6 +2646,33 @@
status = "disabled";
};
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,sm8450-dispcc";
+ reg = <0 0x0af00000 0 0x20000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&sleep_clk>,
+ <0>, /* dsi0 */
+ <0>,
+ <0>, /* dsi1 */
+ <0>,
+ <0>, /* dp0 */
+ <0>,
+ <0>, /* dp1 */
+ <0>,
+ <0>, /* dp2 */
+ <0>,
+ <0>, /* dp3 */
+ <0>;
+ power-domains = <&rpmhpd SM8450_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ status = "disabled";
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8450-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
@@ -2384,6 +2735,26 @@
gpio-ranges = <&tlmm 0 0 211>;
wakeup-parent = <&pdc>;
+ sdc2_default_state: sdc2-default-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+
sdc2_sleep_state: sdc2-sleep-state {
clk-pins {
pins = "sdc2_clk";
@@ -2404,6 +2775,70 @@
};
};
+ cci0_default: cci0-default-state {
+ /* SDA, SCL */
+ pins = "gpio110", "gpio111";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci0_sleep: cci0-sleep-state {
+ /* SDA, SCL */
+ pins = "gpio110", "gpio111";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci1_default: cci1-default-state {
+ /* SDA, SCL */
+ pins = "gpio112", "gpio113";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci1_sleep: cci1-sleep-state {
+ /* SDA, SCL */
+ pins = "gpio112", "gpio113";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci2_default: cci2-default-state {
+ /* SDA, SCL */
+ pins = "gpio114", "gpio115";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci2_sleep: cci2-sleep-state {
+ /* SDA, SCL */
+ pins = "gpio114", "gpio115";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci3_default: cci3-default-state {
+ /* SDA, SCL */
+ pins = "gpio208", "gpio209";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci3_sleep: cci3-sleep-state {
+ /* SDA, SCL */
+ pins = "gpio208", "gpio209";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
pcie0_default_state: pcie0-default-state {
perst-pins {
pins = "gpio94";
@@ -2800,6 +3235,123 @@
};
+ lpass_tlmm: pinctrl@3440000{
+ compatible = "qcom,sm8450-lpass-lpi-pinctrl";
+ reg = <0 0x3440000 0x0 0x20000>,
+ <0 0x34d0000 0x0 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 23>;
+
+ clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "audio";
+
+ tx_swr_active: tx-swr-active-state {
+ clk-pins {
+ pins = "gpio0";
+ function = "swr_tx_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio1", "gpio2", "gpio14";
+ function = "swr_tx_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_active: rx-swr-active-state {
+ clk-pins {
+ pins = "gpio3";
+ function = "swr_rx_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio4", "gpio5";
+ function = "swr_rx_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ dmic01_default: dmic01-default-state {
+ clk-pins {
+ pins = "gpio6";
+ function = "dmic1_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ data-pins {
+ pins = "gpio7";
+ function = "dmic1_data";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ dmic02_default: dmic02-default-state {
+ clk-pins {
+ pins = "gpio8";
+ function = "dmic2_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ data-pins {
+ pins = "gpio9";
+ function = "dmic2_data";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ wsa_swr_active: wsa-swr-active-state {
+ clk-pins {
+ pins = "gpio10";
+ function = "wsa_swr_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio11";
+ function = "wsa_swr_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ wsa2_swr_active: wsa2-swr-active-state {
+ clk-pins {
+ pins = "gpio15";
+ function = "wsa2_swr_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio16";
+ function = "wsa2_swr_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
@@ -2999,6 +3551,7 @@
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
<WAKE_TCS 2>, <CONTROL_TCS 0>;
+ power-domains = <&CLUSTER_PD>;
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
@@ -3075,6 +3628,7 @@
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
#freq-domain-cells = <1>;
+ #clock-cells = <1>;
};
gem_noc: interconnect@19100000 {
@@ -3161,16 +3715,16 @@
status = "disabled";
ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x108>,
- <0 0x01d87600 0 0x1e0>,
- <0 0x01d87c00 0 0x1dc>,
- <0 0x01d87800 0 0x108>,
- <0 0x01d87a00 0 0x1e0>;
+ reg = <0 0x01d87400 0 0x188>,
+ <0 0x01d87600 0 0x200>,
+ <0 0x01d87c00 0 0x200>,
+ <0 0x01d87800 0 0x188>,
+ <0 0x01d87a00 0 0x200>;
#phy-cells = <0>;
};
};
- sdhc_2: sdhci@8804000 {
+ sdhc_2: mmc@8804000 {
compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
@@ -3192,6 +3746,9 @@
bus-width = <4>;
dma-coherent;
+ /* Forbid SDR104/SDR50 - broken hw! */
+ sdhci-caps-mask = <0x3 0x0>;
+
status = "disabled";
sdhc2_opp_table: opp-table {
@@ -3274,6 +3831,9 @@
};
};
+ sound: sound {
+ };
+
thermal-zones {
aoss0-thermal {
polling-delay-passive = <0>;
diff --git a/arch/arm64/boot/dts/renesas/condor-common.dtsi b/arch/arm64/boot/dts/renesas/condor-common.dtsi
index dfbe35bf46e0..7c34d14dcd7e 100644
--- a/arch/arm64/boot/dts/renesas/condor-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/condor-common.dtsi
@@ -21,6 +21,7 @@
chosen {
stdout-path = "serial0:115200n8";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
};
d1_8v: regulator-2 {
diff --git a/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dts b/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso
index 258f8668ca36..258f8668ca36 100644
--- a/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dts
+++ b/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index ed9400f903c9..41fbb9998cf8 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -656,7 +656,7 @@
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779a0",
- "renesas,etheravb-rcar-gen3";
+ "renesas,etheravb-rcar-gen4";
reg = <0 0xe6800000 0 0x800>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
@@ -704,7 +704,7 @@
avb1: ethernet@e6810000 {
compatible = "renesas,etheravb-r8a779a0",
- "renesas,etheravb-rcar-gen3";
+ "renesas,etheravb-rcar-gen4";
reg = <0 0xe6810000 0 0x800>;
interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
@@ -752,7 +752,7 @@
avb2: ethernet@e6820000 {
compatible = "renesas,etheravb-r8a779a0",
- "renesas,etheravb-rcar-gen3";
+ "renesas,etheravb-rcar-gen4";
reg = <0 0xe6820000 0 0x1000>;
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
@@ -800,7 +800,7 @@
avb3: ethernet@e6830000 {
compatible = "renesas,etheravb-r8a779a0",
- "renesas,etheravb-rcar-gen3";
+ "renesas,etheravb-rcar-gen4";
reg = <0 0xe6830000 0 0x1000>;
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
@@ -848,7 +848,7 @@
avb4: ethernet@e6840000 {
compatible = "renesas,etheravb-r8a779a0",
- "renesas,etheravb-rcar-gen3";
+ "renesas,etheravb-rcar-gen4";
reg = <0 0xe6840000 0 0x1000>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
@@ -896,7 +896,7 @@
avb5: ethernet@e6850000 {
compatible = "renesas,etheravb-r8a779a0",
- "renesas,etheravb-rcar-gen3";
+ "renesas,etheravb-rcar-gen4";
reg = <0 0xe6850000 0 0x1000>;
interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
@@ -1019,7 +1019,7 @@
msiof0: spi@e6e90000 {
compatible = "renesas,msiof-r8a779a0",
- "renesas,rcar-gen3-msiof";
+ "renesas,rcar-gen4-msiof";
reg = <0 0xe6e90000 0 0x0064>;
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 618>;
@@ -1034,7 +1034,7 @@
msiof1: spi@e6ea0000 {
compatible = "renesas,msiof-r8a779a0",
- "renesas,rcar-gen3-msiof";
+ "renesas,rcar-gen4-msiof";
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 619>;
@@ -1049,7 +1049,7 @@
msiof2: spi@e6c00000 {
compatible = "renesas,msiof-r8a779a0",
- "renesas,rcar-gen3-msiof";
+ "renesas,rcar-gen4-msiof";
reg = <0 0xe6c00000 0 0x0064>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 620>;
@@ -1064,7 +1064,7 @@
msiof3: spi@e6c10000 {
compatible = "renesas,msiof-r8a779a0",
- "renesas,rcar-gen3-msiof";
+ "renesas,rcar-gen4-msiof";
reg = <0 0xe6c10000 0 0x0064>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
@@ -1079,7 +1079,7 @@
msiof4: spi@e6c20000 {
compatible = "renesas,msiof-r8a779a0",
- "renesas,rcar-gen3-msiof";
+ "renesas,rcar-gen4-msiof";
reg = <0 0xe6c20000 0 0x0064>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
@@ -1094,7 +1094,7 @@
msiof5: spi@e6c28000 {
compatible = "renesas,msiof-r8a779a0",
- "renesas,rcar-gen3-msiof";
+ "renesas,rcar-gen4-msiof";
reg = <0 0xe6c28000 0 0x0064>;
interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
index a45df1041705..045d70535519 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
@@ -12,13 +12,13 @@
compatible = "renesas,spider-cpu", "renesas,r8a779f0";
aliases {
- serial0 = &scif3;
+ serial0 = &hscif0;
serial1 = &scif0;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
- stdout-path = "serial0:115200n8";
+ stdout-path = "serial0:1843200n8";
};
memory@48000000 {
@@ -59,6 +59,14 @@
clock-frequency = <32768>;
};
+&hscif0 {
+ pinctrl-0 = <&hscif0_pins>;
+ pinctrl-names = "default";
+
+ uart-has-rtscts;
+ status = "okay";
+};
+
&i2c4 {
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "default";
@@ -99,6 +107,11 @@
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
+ hscif0_pins: hscif0 {
+ groups = "hscif0_data", "hscif0_ctrl";
+ function = "hscif0";
+ };
+
i2c4_pins: i2c4 {
groups = "i2c4";
function = "i2c4";
@@ -115,11 +128,6 @@
function = "scif0";
};
- scif3_pins: scif3 {
- groups = "scif3_data", "scif3_ctrl";
- function = "scif3";
- };
-
scif_clk_pins: scif_clk {
groups = "scif_clk";
function = "scif_clk";
@@ -139,14 +147,6 @@
status = "okay";
};
-&scif3 {
- pinctrl-0 = <&scif3_pins>;
- pinctrl-names = "default";
-
- uart-has-rtscts;
- status = "okay";
-};
-
&scif_clk {
clock-frequency = <24000000>;
};
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi
index 15e8d1ebf575..33c1015e9ab3 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi
@@ -5,6 +5,10 @@
* Copyright (C) 2021 Renesas Electronics Corp.
*/
+&eth_serdes {
+ status = "okay";
+};
+
&i2c4 {
eeprom@52 {
compatible = "rohm,br24g01", "atmel,24c01";
@@ -13,3 +17,89 @@
pagesize = <8>;
};
};
+
+&pfc {
+ tsn0_pins: tsn0 {
+ groups = "tsn0_mdio_b", "tsn0_link_b";
+ function = "tsn0";
+ power-source = <1800>;
+ };
+
+ tsn1_pins: tsn1 {
+ groups = "tsn1_mdio_b", "tsn1_link_b";
+ function = "tsn1";
+ power-source = <1800>;
+ };
+
+ tsn2_pins: tsn2 {
+ groups = "tsn2_mdio_b", "tsn2_link_b";
+ function = "tsn2";
+ power-source = <1800>;
+ };
+};
+
+&rswitch {
+ pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ phy-handle = <&u101>;
+ phy-mode = "sgmii";
+ phys = <&eth_serdes 0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ u101: ethernet-phy@1 {
+ reg = <1>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupt-parent = <&gpio3>;
+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+ };
+ port@1 {
+ reg = <1>;
+ phy-handle = <&u201>;
+ phy-mode = "sgmii";
+ phys = <&eth_serdes 1>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ u201: ethernet-phy@2 {
+ reg = <2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupt-parent = <&gpio3>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+ };
+ port@2 {
+ reg = <2>;
+ phy-handle = <&u301>;
+ phy-mode = "sgmii";
+ phys = <&eth_serdes 2>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ u301: ethernet-phy@3 {
+ reg = <3>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupt-parent = <&gpio3>;
+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index c2f152bcf10e..67a4f2d4480d 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -469,6 +469,16 @@
status = "disabled";
};
+ eth_serdes: phy@e6444000 {
+ compatible = "renesas,r8a779f0-ether-serdes";
+ reg = <0 0xe6444000 0 0x2800>;
+ clocks = <&cpg CPG_MOD 1506>;
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 1506>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
i2c0: i2c@e6500000 {
compatible = "renesas,i2c-r8a779f0",
"renesas,rcar-gen4-i2c";
@@ -577,7 +587,7 @@
reg = <0 0xe6540000 0 0x60>;
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 514>,
- <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x31>, <&dmac0 0x30>,
@@ -594,7 +604,7 @@
reg = <0 0xe6550000 0 0x60>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 515>,
- <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x33>, <&dmac0 0x32>,
@@ -611,7 +621,7 @@
reg = <0 0xe6560000 0 0x60>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 516>,
- <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x35>, <&dmac0 0x34>,
@@ -628,7 +638,7 @@
reg = <0 0xe66a0000 0 0x60>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 517>,
- <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x37>, <&dmac0 0x36>,
@@ -651,13 +661,113 @@
status = "disabled";
};
+ rswitch: ethernet@e6880000 {
+ compatible = "renesas,r8a779f0-ether-switch";
+ reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>;
+ reg-names = "base", "secure_base";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mfwd_error", "race_error",
+ "coma_error", "gwca0_error",
+ "gwca1_error", "etha0_error",
+ "etha1_error", "etha2_error",
+ "gptp0_status", "gptp1_status",
+ "mfwd_status", "race_status",
+ "coma_status", "gwca0_status",
+ "gwca1_status", "etha0_status",
+ "etha1_status", "etha2_status",
+ "rmac0_status", "rmac1_status",
+ "rmac2_status",
+ "gwca0_rxtx0", "gwca0_rxtx1",
+ "gwca0_rxtx2", "gwca0_rxtx3",
+ "gwca0_rxtx4", "gwca0_rxtx5",
+ "gwca0_rxtx6", "gwca0_rxtx7",
+ "gwca1_rxtx0", "gwca1_rxtx1",
+ "gwca1_rxtx2", "gwca1_rxtx3",
+ "gwca1_rxtx4", "gwca1_rxtx5",
+ "gwca1_rxtx6", "gwca1_rxtx7",
+ "gwca0_rxts0", "gwca0_rxts1",
+ "gwca1_rxts0", "gwca1_rxts1",
+ "rmac0_mdio", "rmac1_mdio",
+ "rmac2_mdio",
+ "rmac0_phy", "rmac1_phy",
+ "rmac2_phy";
+ clocks = <&cpg CPG_MOD 1505>;
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 1505>;
+ status = "disabled";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ phys = <&eth_serdes 0>;
+ };
+ port@1 {
+ reg = <1>;
+ phys = <&eth_serdes 1>;
+ };
+ port@2 {
+ reg = <2>;
+ phys = <&eth_serdes 2>;
+ };
+ };
+ };
+
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a779f0",
"renesas,rcar-gen4-scif", "renesas,scif";
reg = <0 0xe6e60000 0 64>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 702>,
- <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x51>, <&dmac0 0x50>,
@@ -674,7 +784,7 @@
reg = <0 0xe6e68000 0 64>;
interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>,
- <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x53>, <&dmac0 0x52>,
@@ -691,7 +801,7 @@
reg = <0 0xe6c50000 0 64>;
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 704>,
- <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x57>, <&dmac0 0x56>,
@@ -708,7 +818,7 @@
reg = <0 0xe6c40000 0 64>;
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 705>,
- <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x59>, <&dmac0 0x58>,
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
index 895f0bd9f754..c10740aee9f6 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
@@ -96,6 +96,24 @@
device_type = "memory";
reg = <0x6 0x00000000 0x1 0x00000000>;
};
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
&avb0 {
@@ -135,6 +153,17 @@
status = "okay";
clock-frequency = <400000>;
+ io_expander_a: gpio@20 {
+ compatible = "onnn,pca9654";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
eeprom@50 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "cpu-board";
@@ -143,6 +172,23 @@
};
};
+&mmc0 {
+ pinctrl-0 = <&mmc_pins>;
+ pinctrl-1 = <&mmc_pins>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_1p8v>;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
+ no-sd;
+ no-sdio;
+ non-removable;
+ full-pwr-cycle-in-suspend;
+ status = "okay";
+};
+
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
@@ -180,17 +226,56 @@
bias-pull-up;
};
+ mmc_pins: mmc {
+ groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
+ function = "mmc";
+ power-source = <1800>;
+ };
+
+ qspi0_pins: qspi0 {
+ groups = "qspi0_ctrl", "qspi0_data4";
+ function = "qspi0";
+ };
+
scif_clk_pins: scif_clk {
groups = "scif_clk";
function = "scif_clk";
};
};
-&scif_clk {
- clock-frequency = <24000000>;
+&rpc {
+ pinctrl-0 = <&qspi0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ flash@0 {
+ compatible = "spansion,s25fs512s", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot@0 {
+ reg = <0x0 0x1200000>;
+ read-only;
+ };
+ user@1200000 {
+ reg = <0x1200000 0x2e00000>;
+ };
+ };
+ };
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
+
+&scif_clk {
+ clock-frequency = <24000000>;
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index d70f0600ae5a..45d8d927ad26 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -14,18 +14,138 @@
#address-cells = <2>;
#size-cells = <2>;
+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <825000>;
+ clock-latency-ns = <500000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <825000>;
+ clock-latency-ns = <500000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <825000>;
+ clock-latency-ns = <500000>;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <825000>;
+ clock-latency-ns = <500000>;
+ opp-suspend;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&a76_0>;
+ };
+ core1 {
+ cpu = <&a76_1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&a76_2>;
+ };
+ core1 {
+ cpu = <&a76_3>;
+ };
+ };
+ };
+
a76_0: cpu@0 {
compatible = "arm,cortex-a76";
reg = <0>;
device_type = "cpu";
power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
+ next-level-cache = <&L3_CA76_0>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ a76_1: cpu@100 {
+ compatible = "arm,cortex-a76";
+ reg = <0x100>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A779G0_PD_A1E0D0C1>;
+ next-level-cache = <&L3_CA76_0>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ a76_2: cpu@10000 {
+ compatible = "arm,cortex-a76";
+ reg = <0x10000>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A779G0_PD_A1E0D1C0>;
+ next-level-cache = <&L3_CA76_1>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ a76_3: cpu@10100 {
+ compatible = "arm,cortex-a76";
+ reg = <0x10100>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A779G0_PD_A1E0D1C1>;
+ next-level-cache = <&L3_CA76_1>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ local-timer-stop;
+ entry-latency-us = <400>;
+ exit-latency-us = <500>;
+ min-residency-us = <4000>;
+ };
+ };
+
+ L3_CA76_0: cache-controller-0 {
+ compatible = "cache";
+ power-domains = <&sysc R8A779G0_PD_A2E0D0>;
+ cache-unified;
+ cache-level = <3>;
+ };
+
+ L3_CA76_1: cache-controller-1 {
+ compatible = "cache";
+ power-domains = <&sysc R8A779G0_PD_A2E0D1>;
+ cache-unified;
+ cache-level = <3>;
};
};
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -214,6 +334,76 @@
#interrupt-cells = <2>;
};
+ cmt0: timer@e60f0000 {
+ compatible = "renesas,r8a779g0-cmt0",
+ "renesas,rcar-gen4-cmt0";
+ reg = <0 0xe60f0000 0 0x1004>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 910>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a779g0-cmt1",
+ "renesas,rcar-gen4-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 911>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
+ status = "disabled";
+ };
+
+ cmt2: timer@e6140000 {
+ compatible = "renesas,r8a779g0-cmt1",
+ "renesas,rcar-gen4-cmt1";
+ reg = <0 0xe6140000 0 0x1004>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 912>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
+ status = "disabled";
+ };
+
+ cmt3: timer@e6148000 {
+ compatible = "renesas,r8a779g0-cmt1",
+ "renesas,rcar-gen4-cmt1";
+ reg = <0 0xe6148000 0 0x1004>;
+ interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 913>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 913>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a779g0-cpg-mssr";
reg = <0 0xe6150000 0 0x4000>;
@@ -235,12 +425,96 @@
#power-domain-cells = <1>;
};
+ intc_ex: interrupt-controller@e61c0000 {
+ compatible = "renesas,intc-ex-r8a779g0", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 611>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 611>;
+ };
+
+ tmu0: timer@e61e0000 {
+ compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
+ reg = <0 0xe61e0000 0 0x30>;
+ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 713>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 713>;
+ status = "disabled";
+ };
+
+ tmu1: timer@e6fc0000 {
+ compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
+ reg = <0 0xe6fc0000 0 0x30>;
+ interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 714>;
+ status = "disabled";
+ };
+
+ tmu2: timer@e6fd0000 {
+ compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
+ reg = <0 0xe6fd0000 0 0x30>;
+ interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 715>;
+ status = "disabled";
+ };
+
+ tmu3: timer@e6fe0000 {
+ compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
+ reg = <0 0xe6fe0000 0 0x30>;
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+ };
+
+ tmu4: timer@ffc00000 {
+ compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
+ reg = <0 0xffc00000 0 0x30>;
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 717>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 717>;
+ status = "disabled";
+ };
+
i2c0: i2c@e6500000 {
compatible = "renesas,i2c-r8a779g0",
"renesas,rcar-gen4-i2c";
reg = <0 0xe6500000 0 0x40>;
interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 518>;
+ dmas = <&dmac0 0x91>, <&dmac0 0x90>,
+ <&dmac1 0x91>, <&dmac1 0x90>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 518>;
i2c-scl-internal-delay-ns = <110>;
@@ -255,6 +529,9 @@
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 519>;
+ dmas = <&dmac0 0x93>, <&dmac0 0x92>,
+ <&dmac1 0x93>, <&dmac1 0x92>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 519>;
i2c-scl-internal-delay-ns = <110>;
@@ -269,6 +546,9 @@
reg = <0 0xe6510000 0 0x40>;
interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 520>;
+ dmas = <&dmac0 0x95>, <&dmac0 0x94>,
+ <&dmac1 0x95>, <&dmac1 0x94>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 520>;
i2c-scl-internal-delay-ns = <110>;
@@ -283,6 +563,9 @@
reg = <0 0xe66d0000 0 0x40>;
interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 521>;
+ dmas = <&dmac0 0x97>, <&dmac0 0x96>,
+ <&dmac1 0x97>, <&dmac1 0x96>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 521>;
i2c-scl-internal-delay-ns = <110>;
@@ -297,6 +580,9 @@
reg = <0 0xe66d8000 0 0x40>;
interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 522>;
+ dma-names = "tx", "rx", "tx", "rx";
+ dmas = <&dmac0 0x99>, <&dmac0 0x98>,
+ <&dmac1 0x99>, <&dmac1 0x98>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 522>;
i2c-scl-internal-delay-ns = <110>;
@@ -311,6 +597,9 @@
reg = <0 0xe66e0000 0 0x40>;
interrupts = <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 523>;
+ dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
+ <&dmac1 0x9b>, <&dmac1 0x9a>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 523>;
i2c-scl-internal-delay-ns = <110>;
@@ -321,19 +610,72 @@
hscif0: serial@e6540000 {
compatible = "renesas,hscif-r8a779g0",
- "renesas,rcar-gen4-hscif",
- "renesas,hscif";
- reg = <0 0xe6540000 0 96>;
+ "renesas,rcar-gen4-hscif", "renesas,hscif";
+ reg = <0 0xe6540000 0 0x60>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 514>,
- <&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>,
+ <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x31>, <&dmac0 0x30>,
+ <&dmac1 0x31>, <&dmac1 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 514>;
status = "disabled";
};
+ hscif1: serial@e6550000 {
+ compatible = "renesas,hscif-r8a779g0",
+ "renesas,rcar-gen4-hscif", "renesas,hscif";
+ reg = <0 0xe6550000 0 0x60>;
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 515>,
+ <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x33>, <&dmac0 0x32>,
+ <&dmac1 0x33>, <&dmac1 0x32>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 515>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e6560000 {
+ compatible = "renesas,hscif-r8a779g0",
+ "renesas,rcar-gen4-hscif", "renesas,hscif";
+ reg = <0 0xe6560000 0 0x60>;
+ interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 516>,
+ <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x35>, <&dmac0 0x34>,
+ <&dmac1 0x35>, <&dmac1 0x34>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 516>;
+ status = "disabled";
+ };
+
+ hscif3: serial@e66a0000 {
+ compatible = "renesas,hscif-r8a779g0",
+ "renesas,rcar-gen4-hscif", "renesas,hscif";
+ reg = <0 0xe66a0000 0 0x60>;
+ interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 517>,
+ <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x37>, <&dmac0 0x36>,
+ <&dmac1 0x37>, <&dmac1 0x36>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 517>;
+ status = "disabled";
+ };
+
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779g0",
"renesas,etheravb-rcar-gen4";
@@ -475,6 +817,381 @@
status = "disabled";
};
+ pwm0: pwm@e6e30000 {
+ compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+ reg = <0 0xe6e30000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@e6e34000 {
+ compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+ reg = <0 0xe6e34000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@e6e35000 {
+ compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+ reg = <0 0xe6e35000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@e6e36000 {
+ compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+ reg = <0 0xe6e36000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ pwm7: pwm@e6e37000 {
+ compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+ reg = <0 0xe6e37000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ pwm8: pwm@e6e38000 {
+ compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+ reg = <0 0xe6e38000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ pwm9: pwm@e6e39000 {
+ compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
+ reg = <0 0xe6e39000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a779g0",
+ "renesas,rcar-gen4-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 702>,
+ <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x51>, <&dmac0 0x50>,
+ <&dmac1 0x51>, <&dmac1 0x50>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 702>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a779g0",
+ "renesas,rcar-gen4-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>,
+ <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x53>, <&dmac0 0x52>,
+ <&dmac1 0x53>, <&dmac1 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+ };
+
+ scif3: serial@e6c50000 {
+ compatible = "renesas,scif-r8a779g0",
+ "renesas,rcar-gen4-scif", "renesas,scif";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 704>,
+ <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x57>, <&dmac0 0x56>,
+ <&dmac1 0x57>, <&dmac1 0x56>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6c40000 {
+ compatible = "renesas,scif-r8a779g0",
+ "renesas,rcar-gen4-scif", "renesas,scif";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 705>,
+ <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x59>, <&dmac0 0x58>,
+ <&dmac1 0x59>, <&dmac1 0x58>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 705>;
+ status = "disabled";
+ };
+
+ tpu: pwm@e6e80000 {
+ compatible = "renesas,tpu-r8a779g0", "renesas,tpu";
+ reg = <0 0xe6e80000 0 0x148>;
+ interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 718>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 718>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ msiof0: spi@e6e90000 {
+ compatible = "renesas,msiof-r8a779g0",
+ "renesas,rcar-gen4-msiof";
+ reg = <0 0xe6e90000 0 0x0064>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 618>;
+ dmas = <&dmac0 0x41>, <&dmac0 0x40>,
+ <&dmac1 0x41>, <&dmac1 0x40>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 618>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6ea0000 {
+ compatible = "renesas,msiof-r8a779g0",
+ "renesas,rcar-gen4-msiof";
+ reg = <0 0xe6ea0000 0 0x0064>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 619>;
+ dmas = <&dmac0 0x43>, <&dmac0 0x42>,
+ <&dmac1 0x43>, <&dmac1 0x42>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 619>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof2: spi@e6c00000 {
+ compatible = "renesas,msiof-r8a779g0",
+ "renesas,rcar-gen4-msiof";
+ reg = <0 0xe6c00000 0 0x0064>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 620>;
+ dmas = <&dmac0 0x45>, <&dmac0 0x44>,
+ <&dmac1 0x45>, <&dmac1 0x44>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 620>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof3: spi@e6c10000 {
+ compatible = "renesas,msiof-r8a779g0",
+ "renesas,rcar-gen4-msiof";
+ reg = <0 0xe6c10000 0 0x0064>;
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 621>;
+ dmas = <&dmac0 0x47>, <&dmac0 0x46>,
+ <&dmac1 0x47>, <&dmac1 0x46>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 621>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof4: spi@e6c20000 {
+ compatible = "renesas,msiof-r8a779g0",
+ "renesas,rcar-gen4-msiof";
+ reg = <0 0xe6c20000 0 0x0064>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 622>;
+ dmas = <&dmac0 0x49>, <&dmac0 0x48>,
+ <&dmac1 0x49>, <&dmac1 0x48>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 622>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof5: spi@e6c28000 {
+ compatible = "renesas,msiof-r8a779g0",
+ "renesas,rcar-gen4-msiof";
+ reg = <0 0xe6c28000 0 0x0064>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 623>;
+ dmas = <&dmac0 0x4b>, <&dmac0 0x4a>,
+ <&dmac1 0x4b>, <&dmac1 0x4a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 623>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ dmac0: dma-controller@e7350000 {
+ compatible = "renesas,dmac-r8a779g0",
+ "renesas,rcar-gen4-dmac";
+ reg = <0 0xe7350000 0 0x1000>,
+ <0 0xe7300000 0 0x10000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3", "ch4",
+ "ch5", "ch6", "ch7", "ch8", "ch9",
+ "ch10", "ch11", "ch12", "ch13",
+ "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 709>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 709>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ dmac1: dma-controller@e7351000 {
+ compatible = "renesas,dmac-r8a779g0",
+ "renesas,rcar-gen4-dmac";
+ reg = <0 0xe7351000 0 0x1000>,
+ <0 0xe7310000 0 0x10000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3", "ch4",
+ "ch5", "ch6", "ch7", "ch8", "ch9",
+ "ch10", "ch11", "ch12", "ch13",
+ "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 710>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 710>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ mmc0: mmc@ee140000 {
+ compatible = "renesas,sdhi-r8a779g0",
+ "renesas,rcar-gen4-sdhi";
+ reg = <0 0xee140000 0 0x2000>;
+ interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 706>,
+ <&cpg CPG_CORE R8A779G0_CLK_SD0H>;
+ clock-names = "core", "clkh";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 706>;
+ max-frequency = <200000000>;
+ status = "disabled";
+ };
+
+ rpc: spi@ee200000 {
+ compatible = "renesas,r8a779g0-rpc-if",
+ "renesas,rcar-gen4-rpc-if";
+ reg = <0 0xee200000 0 0x200>,
+ <0 0x08000000 0 0x04000000>,
+ <0 0xee208000 0 0x100>;
+ reg-names = "regs", "dirmap", "wbuf";
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 629>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 629>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
@@ -483,7 +1200,7 @@
reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
prr: chipid@fff00044 {
@@ -494,9 +1211,9 @@
timer {
compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 689aa4ba416b..3f7d451b1199 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -1,11 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
- * Device Tree Source for the RZ/G2UL SoC
+ * Device Tree Source for the RZ/Five and RZ/G2UL SoCs
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
-#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a07g043-cpg.h>
/ {
@@ -69,36 +68,8 @@
};
};
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a55";
- reg = <0>;
- device_type = "cpu";
- #cooling-cells = <2>;
- next-level-cache = <&L3_CA55>;
- enable-method = "psci";
- clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
- operating-points-v2 = <&cluster0_opp>;
- };
-
- L3_CA55: cache-controller-0 {
- compatible = "cache";
- cache-unified;
- cache-size = <0x40000>;
- };
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
soc: soc {
compatible = "simple-bus";
- interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -107,10 +78,10 @@
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x10049c00 0 0x400>;
- interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(326) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(327) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(328) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(329) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
@@ -128,10 +99,10 @@
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x1004a000 0 0x400>;
- interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(330) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(331) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(332) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(333) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
@@ -149,10 +120,10 @@
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x1004a400 0 0x400>;
- interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(334) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(335) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(336) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(337) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>,
@@ -170,10 +141,10 @@
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x1004a800 0 0x400>;
- interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(338) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(339) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(340) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(341) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>,
@@ -190,9 +161,9 @@
spi0: spi@1004ac00 {
compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
reg = <0 0x1004ac00 0 0x400>;
- interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(415) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(413) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(414) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>;
resets = <&cpg R9A07G043_RSPI0_RST>;
@@ -208,9 +179,9 @@
spi1: spi@1004b000 {
compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
reg = <0 0x1004b000 0 0x400>;
- interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(418) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(416) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(417) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>;
resets = <&cpg R9A07G043_RSPI1_RST>;
@@ -226,9 +197,9 @@
spi2: spi@1004b400 {
compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
reg = <0 0x1004b400 0 0x400>;
- interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(421) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(419) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(420) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>;
resets = <&cpg R9A07G043_RSPI2_RST>;
@@ -245,12 +216,12 @@
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004b800 0 0x400>;
- interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(380) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(382) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(383) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(381) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
@@ -264,12 +235,12 @@
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004bc00 0 0x400>;
- interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(385) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(387) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(388) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(386) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>;
@@ -283,12 +254,12 @@
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004c000 0 0x400>;
- interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(390) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(392) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(393) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(391) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>;
@@ -302,12 +273,12 @@
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004c400 0 0x400>;
- interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(395) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(397) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(398) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(396) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>;
@@ -321,12 +292,12 @@
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004c800 0 0x400>;
- interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(400) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(402) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(403) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(401) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>;
@@ -339,10 +310,10 @@
sci0: serial@1004d000 {
compatible = "renesas,r9a07g043-sci", "renesas,sci";
reg = <0 0x1004d000 0 0x400>;
- interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(405) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(406) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(407) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(408) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>;
clock-names = "fck";
@@ -354,10 +325,10 @@
sci1: serial@1004d400 {
compatible = "renesas,r9a07g043-sci", "renesas,sci";
reg = <0 0x1004d400 0 0x400>;
- interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(409) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(410) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(411) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(412) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
clock-names = "fck";
@@ -369,14 +340,14 @@
canfd: can@10050000 {
compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd";
reg = <0 0x10050000 0 0x8000>;
- interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(426) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(427) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(422) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(424) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(428) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(423) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(425) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(429) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "g_err", "g_recc",
"ch0_err", "ch0_rec", "ch0_trx",
"ch1_err", "ch1_rec", "ch1_trx";
@@ -405,14 +376,14 @@
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058000 0 0x400>;
- interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(350) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(348) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(349) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(352) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(353) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(351) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(354) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(355) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>;
@@ -427,14 +398,14 @@
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058400 0 0x400>;
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(358) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(356) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(357) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(360) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(361) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(359) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(362) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(363) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>;
@@ -449,14 +420,14 @@
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058800 0 0x400>;
- interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(366) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(364) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(365) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(368) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(369) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(367) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(370) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(371) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>;
@@ -471,14 +442,14 @@
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058c00 0 0x400>;
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(374) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(372) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(373) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(376) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(377) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(375) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(378) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(379) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>;
@@ -491,7 +462,7 @@
adc: adc@10059000 {
compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc";
reg = <0 0x10059000 0 0x400>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(347) IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>,
<&cpg CPG_MOD R9A07G043_ADC_PCLK>;
clock-names = "adclk", "pclk";
@@ -551,12 +522,6 @@
sysc: system-controller@11020000 {
compatible = "renesas,r9a07g043-sysc";
reg = <0 0x11020000 0 0x10000>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "lpm_int", "ca55stbydone_int",
- "cm33stbyr_int", "ca55_deny";
status = "disabled";
};
@@ -578,23 +543,23 @@
"renesas,rz-dmac";
reg = <0 0x11820000 0 0x10000>,
<0 0x11830000 0 0x10000>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(141) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(125) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(126) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(127) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(128) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(129) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(130) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(132) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(133) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(134) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(135) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(136) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(137) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(138) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(139) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(140) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -609,22 +574,12 @@
dma-channels = <16>;
};
- gic: interrupt-controller@11900000 {
- compatible = "arm,gic-v3";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0x11900000 0 0x40000>,
- <0x0 0x11940000 0 0x60000>;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
- };
-
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a07g043",
"renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(104) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(105) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>,
<&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>,
<&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
@@ -639,8 +594,8 @@
compatible = "renesas,sdhi-r9a07g043",
"renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c10000 0 0x10000>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(106) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(107) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>,
<&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>,
<&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
@@ -655,9 +610,9 @@
compatible = "renesas,r9a07g043-gbeth",
"renesas,rzg2l-gbeth";
reg = <0 0x11c20000 0 0x10000>;
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(85) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(86) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mux", "fil", "arp_ns";
phy-mode = "rgmii";
clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>,
@@ -675,9 +630,9 @@
compatible = "renesas,r9a07g043-gbeth",
"renesas,rzg2l-gbeth";
reg = <0 0x11c30000 0 0x10000>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(87) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(88) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(89) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mux", "fil", "arp_ns";
phy-mode = "rgmii";
clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>,
@@ -705,7 +660,7 @@
ohci0: usb@11c50000 {
compatible = "generic-ohci";
reg = <0 0x11c50000 0 0x100>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
resets = <&phyrst 0>,
@@ -719,7 +674,7 @@
ohci1: usb@11c70000 {
compatible = "generic-ohci";
reg = <0 0x11c70000 0 0x100>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(96) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
resets = <&phyrst 1>,
@@ -733,7 +688,7 @@
ehci0: usb@11c50100 {
compatible = "generic-ehci";
reg = <0 0x11c50100 0 0x100>;
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
resets = <&phyrst 0>,
@@ -748,7 +703,7 @@
ehci1: usb@11c70100 {
compatible = "generic-ehci";
reg = <0 0x11c70100 0 0x100>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(97) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
resets = <&phyrst 1>,
@@ -764,7 +719,7 @@
compatible = "renesas,usb2-phy-r9a07g043",
"renesas,rzg2l-usb2-phy";
reg = <0 0x11c50200 0 0x700>;
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(94) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
resets = <&phyrst 0>;
@@ -777,7 +732,7 @@
compatible = "renesas,usb2-phy-r9a07g043",
"renesas,rzg2l-usb2-phy";
reg = <0 0x11c70200 0 0x700>;
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(99) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
resets = <&phyrst 1>;
@@ -790,10 +745,10 @@
compatible = "renesas,usbhs-r9a07g043",
"renesas,rza2-usbhs";
reg = <0 0x11c60000 0 0x10000>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(100) IRQ_TYPE_EDGE_RISING>,
+ <SOC_PERIPHERAL_IRQ(101) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(102) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(103) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>;
resets = <&phyrst 0>,
@@ -812,34 +767,19 @@
clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>,
<&cpg CPG_MOD R9A07G043_WDT0_CLK>;
clock-names = "pclk", "oscclk";
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(49) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G043_WDT0_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
- wdt2: watchdog@12800400 {
- compatible = "renesas,r9a07g043-wdt",
- "renesas,rzg2l-wdt";
- reg = <0 0x12800400 0 0x400>;
- clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>,
- <&cpg CPG_MOD R9A07G043_WDT2_CLK>;
- clock-names = "pclk", "oscclk";
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "wdt", "perrout";
- resets = <&cpg R9A07G043_WDT2_PRESETN>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
ostm0: timer@12801000 {
compatible = "renesas,r9a07g043-ostm",
"renesas,ostm";
reg = <0x0 0x12801000 0x0 0x400>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>;
resets = <&cpg R9A07G043_OSTM0_PRESETZ>;
power-domains = <&cpg>;
@@ -850,7 +790,7 @@
compatible = "renesas,r9a07g043-ostm",
"renesas,ostm";
reg = <0x0 0x12801400 0x0 0x400>;
- interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>;
resets = <&cpg R9A07G043_OSTM1_PRESETZ>;
power-domains = <&cpg>;
@@ -861,7 +801,7 @@
compatible = "renesas,r9a07g043-ostm",
"renesas,ostm";
reg = <0x0 0x12801800 0x0 0x400>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(48) IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>;
resets = <&cpg R9A07G043_OSTM2_PRESETZ>;
power-domains = <&cpg>;
@@ -899,12 +839,4 @@
};
};
};
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
- };
};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
new file mode 100644
index 000000000000..6af5f3bca2d1
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2UL SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
+
+#include "r9a07g043.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ reg = <0>;
+ device_type = "cpu";
+ #cooling-cells = <2>;
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ L3_CA55: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-size = <0x40000>;
+ cache-level = <3>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
+
+&soc {
+ interrupt-parent = <&gic>;
+
+ gic: interrupt-controller@11900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0x11900000 0 0x40000>,
+ <0x0 0x11940000 0 0x60000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&sysc {
+ interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>,
+ <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "lpm_int", "ca55stbydone_int",
+ "cm33stbyr_int", "ca55_deny";
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
index 059885a01ede..01483b4302c2 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
@@ -17,7 +17,7 @@
#define SW_SW0_DEV_SEL 1
#define SW_ET0_EN_N 1
-#include "r9a07g043.dtsi"
+#include "r9a07g043u.dtsi"
#include "rzg2ul-smarc-som.dtsi"
#include "rzg2ul-smarc.dtsi"
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 2283d4fb8736..487536696d90 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -109,6 +109,7 @@
compatible = "cache";
cache-unified;
cache-size = <0x40000>;
+ cache-level = <3>;
};
};
@@ -644,7 +645,6 @@
reg = <0 0x11030000 0 0x10000>;
gpio-controller;
#gpio-cells = <2>;
- #address-cells = <2>;
#interrupt-cells = <2>;
interrupt-parent = <&irqc>;
interrupt-controller;
@@ -994,21 +994,6 @@
status = "disabled";
};
- wdt2: watchdog@12800400 {
- compatible = "renesas,r9a07g044-wdt",
- "renesas,rzg2l-wdt";
- reg = <0 0x12800400 0 0x400>;
- clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>,
- <&cpg CPG_MOD R9A07G044_WDT2_CLK>;
- clock-names = "pclk", "oscclk";
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "wdt", "perrout";
- resets = <&cpg R9A07G044_WDT2_PRESETN>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
ostm0: timer@12801000 {
compatible = "renesas,r9a07g044-ostm",
"renesas,ostm";
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
index fc34058002e2..f67a6f125d9c 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
@@ -6,7 +6,37 @@
*/
/dts-v1/;
+
+/*
+ * DIP-Switch SW1 setting on SoM
+ * 1 : High; 0: Low
+ * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD)
+ * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1)
+ * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1)
+ * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0)
+ * Please change below macros according to SW1 setting
+ */
+
+#define SW_SD0_DEV_SEL 1
+
+#define SW_SCIF_CAN 0
+#if (SW_SCIF_CAN)
+/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */
+#define SW_RSPI_CAN 0
+#else
+/* Please set SW_RSPI_CAN. Default value is 1 */
+#define SW_RSPI_CAN 1
+#endif
+
+#if (SW_SCIF_CAN && SW_RSPI_CAN)
+#error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing"
+#endif
+
+/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */
+#define PMOD1_SER0 1
+
#include "r9a07g044c2.dtsi"
+#include "rzg2lc-smarc-som.dtsi"
#include "rzg2lc-smarc.dtsi"
/ {
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 358d4c34465f..304ade54425b 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -109,6 +109,7 @@
compatible = "cache";
cache-unified;
cache-size = <0x40000>;
+ cache-level = <3>;
};
};
@@ -650,7 +651,6 @@
reg = <0 0x11030000 0 0x10000>;
gpio-controller;
#gpio-cells = <2>;
- #address-cells = <2>;
#interrupt-cells = <2>;
interrupt-parent = <&irqc>;
interrupt-controller;
@@ -1000,21 +1000,6 @@
status = "disabled";
};
- wdt2: watchdog@12800400 {
- compatible = "renesas,r9a07g054-wdt",
- "renesas,rzg2l-wdt";
- reg = <0 0x12800400 0 0x400>;
- clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>,
- <&cpg CPG_MOD R9A07G054_WDT2_CLK>;
- clock-names = "pclk", "oscclk";
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "wdt", "perrout";
- resets = <&cpg R9A07G054_WDT2_PRESETN>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
ostm0: timer@12801000 {
compatible = "renesas,r9a07g054-ostm",
"renesas,ostm";
diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
index 5c15d73d059f..11e1d51c7c0e 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
@@ -83,3 +83,7 @@
&uart0 {
status = "okay";
};
+
+&wdt0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
index fb1a97202c38..0373ec409d54 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
@@ -37,8 +37,15 @@
compatible = "arm,cortex-a53";
reg = <0>;
device_type = "cpu";
+ next-level-cache = <&L2_CA53>;
clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
};
+
+ L2_CA53: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
};
soc: soc {
@@ -48,7 +55,7 @@
#size-cells = <2>;
ranges;
- gic: interrupt-controller@82000000 {
+ gic: interrupt-controller@82010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
@@ -123,10 +130,15 @@
#power-domain-cells = <0>;
};
+ sys: system-controller@a3f03000 {
+ compatible = "renesas,r9a09g011-sys";
+ reg = <0 0xa3f03000 0 0x400>;
+ };
+
i2c0: i2c@a4030000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "renesas,i2c-r9a09g011", "renesas,rzv2m-i2c";
+ compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c";
reg = <0 0xa4030000 0 0x80>;
interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
@@ -140,7 +152,7 @@
i2c2: i2c@a4030100 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "renesas,i2c-r9a09g011", "renesas,rzv2m-i2c";
+ compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c";
reg = <0 0xa4030100 0 0x80>;
interrupts = <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 238 IRQ_TYPE_EDGE_RISING>;
@@ -161,6 +173,19 @@
status = "disabled";
};
+ wdt0: watchdog@a4050000 {
+ compatible = "renesas,r9a09g011-wdt",
+ "renesas,rzv2m-wdt";
+ reg = <0 0xa4050000 0 0x80>;
+ clocks = <&cpg CPG_MOD R9A09G011_WDT0_PCLK>,
+ <&cpg CPG_MOD R9A09G011_WDT0_CLK>;
+ clock-names = "pclk", "oscclk";
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cpg R9A09G011_WDT0_PRESETN>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
pinctrl: pinctrl@b6250000 {
compatible = "renesas,r9a09g011-pinctrl";
reg = <0 0xb6250000 0 0x800>;
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
index c4faff092380..fbbb4f03440b 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
@@ -351,8 +351,3 @@
status = "okay";
timeout-sec = <60>;
};
-
-&wdt2 {
- status = "okay";
- timeout-sec = <60>;
-};
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
index 78e6e2376b01..8a0d56872de7 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
@@ -276,8 +276,3 @@
status = "okay";
timeout-sec = <60>;
};
-
-&wdt2 {
- status = "okay";
- timeout-sec = <60>;
-};
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
index 6be25a8a28db..b6bd27196d88 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
@@ -8,37 +8,9 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
-/*
- * DIP-Switch SW1 setting on SoM
- * 1 : High; 0: Low
- * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD)
- * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1)
- * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1)
- * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0)
- * Please change below macros according to SW1 setting
- */
-
-#define SW_SD0_DEV_SEL 1
-
-#define SW_SCIF_CAN 0
-#if (SW_SCIF_CAN)
-/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */
-#define SW_RSPI_CAN 0
-#else
-/* Please set SW_RSPI_CAN. Default value is 1 */
-#define SW_RSPI_CAN 1
-#endif
-
-#if (SW_SCIF_CAN && SW_RSPI_CAN)
-#error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing"
-#endif
-
-#include "rzg2lc-smarc-som.dtsi"
#include "rzg2lc-smarc-pinfunction.dtsi"
#include "rz-smarc-common.dtsi"
-/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */
-#define PMOD1_SER0 1
/ {
aliases {
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi
index bd8bc858c28c..58923dc83faa 100644
--- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi
@@ -99,6 +99,13 @@
input-enable;
};
+ spi1_pins: spi1 {
+ pinmux = <RZG2L_PORT_PINMUX(4, 0, 2)>, /* CK */
+ <RZG2L_PORT_PINMUX(4, 1, 2)>, /* MOSI */
+ <RZG2L_PORT_PINMUX(4, 2, 2)>, /* MISO */
+ <RZG2L_PORT_PINMUX(4, 3, 2)>; /* SSL */
+ };
+
ssi1_pins: ssi1 {
pinmux = <RZG2L_PORT_PINMUX(3, 0, 2)>, /* BCK */
<RZG2L_PORT_PINMUX(3, 1, 2)>, /* RCK */
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
index 2a0feb53f0dc..931efc07d6fb 100644
--- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
@@ -221,13 +221,6 @@
pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
};
};
-
- spi1_pins: rspi1 {
- pinmux = <RZG2L_PORT_PINMUX(4, 0, 2)>, /* CK */
- <RZG2L_PORT_PINMUX(4, 1, 2)>, /* MOSI */
- <RZG2L_PORT_PINMUX(4, 2, 2)>, /* MISO */
- <RZG2L_PORT_PINMUX(4, 3, 2)>; /* SSL */
- };
};
#if (SW_SW0_DEV_SEL)
diff --git a/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dts b/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso
index c83a30adc6ad..c83a30adc6ad 100644
--- a/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dts
+++ b/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 8c15593c0ca4..0a76a2ebb5f6 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -3,11 +3,15 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2-of10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-anbernic-rg351m.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2-v11.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go3.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
@@ -62,13 +66,19 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353p.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353v.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353vs.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-model-a.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts
new file mode 100644
index 000000000000..08a3ad3e7ae9
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH
+ */
+
+/dts-v1/;
+#include "px30-ringneck.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Theobroma Systems PX30-uQ7 SoM on Haikou devkit";
+ compatible = "tsd,px30-ringneck-haikou", "rockchip,px30";
+
+ aliases {
+ mmc2 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&haikou_keys_pin>;
+ pinctrl-names = "default";
+
+ button-batlow-n {
+ label = "BATLOW#";
+ linux,code = <KEY_BATTERY>;
+ gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
+ };
+
+ button-slp-btn-n {
+ label = "SLP_BTN#";
+ linux,code = <KEY_SLEEP>;
+ gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
+ };
+
+ button-wake-n {
+ label = "WAKE#";
+ linux,code = <KEY_WAKEUP>;
+ gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+
+ switch-lid-btn-n {
+ label = "LID_BTN#";
+ linux,code = <SW_LID>;
+ linux,input-type = <EV_SW>;
+ gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>;
+
+ sd_card_led: led-1 {
+ gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc2";
+ function = LED_FUNCTION_SD;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+
+ i2s0-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "Haikou,I2S-codec";
+ simple-audio-card,mclk-fs = <512>;
+
+ simple-audio-card,codec {
+ clocks = <&sgtl5000_clk>;
+ sound-dai = <&sgtl5000>;
+ };
+
+ simple-audio-card,cpu {
+ bitclock-master;
+ frame-master;
+ sound-dai = <&i2s0_8ch>;
+ };
+ };
+
+ sgtl5000_clk: sgtl5000-oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
+ dc_12v: dc-12v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc3v3_baseboard: vcc3v3-baseboard-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_baseboard";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_baseboard: vcc5v0-baseboard-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_baseboard";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vdda_codec: vdda-codec-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdda_codec";
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_baseboard>;
+ };
+
+ vddd_codec: vddd-codec-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vddd_codec";
+ regulator-boot-on;
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1600000>;
+ vin-supply = <&vcc5v0_baseboard>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&sgtl5000_clk>;
+ #sound-dai-cells = <0>;
+ VDDA-supply = <&vdda_codec>;
+ VDDIO-supply = <&vcc3v3_baseboard>;
+ VDDD-supply = <&vddd_codec>;
+ };
+};
+
+&i2c3 {
+ eeprom@50 {
+ reg = <0x50>;
+ compatible = "atmel,24c01";
+ pagesize = <8>;
+ size = <128>;
+ vcc-supply = <&vcc3v3_baseboard>;
+ };
+};
+
+&i2s0_8ch {
+ status = "okay";
+};
+
+&gmac {
+ status = "okay";
+};
+
+&pinctrl {
+ haikou {
+ haikou_keys_pin: haikou-keys-pin {
+ rockchip,pins =
+ /* WAKE# */
+ <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* SLP_BTN# */
+ <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* LID_BTN */
+ <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* BATLOW# */
+ <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* BIOS_DISABLE# */
+ <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ sd_card_led_pin: sd-card-led-pin {
+ rockchip,pins =
+ <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&sdmmc {
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ vmmc-supply = <&vcc3v3_baseboard>;
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&u2phy_otg {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-0 = <&uart5_xfer>;
+ status = "okay";
+};
+
+&usb20_otg {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi
new file mode 100644
index 000000000000..12397755830b
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi
@@ -0,0 +1,382 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH
+ */
+
+/dts-v1/;
+#include "px30.dtsi"
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ mmc0 = &emmc;
+ mmc1 = &sdio;
+ rtc0 = &rtc_twi;
+ rtc1 = &rk809;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ pinctrl-0 = <&emmc_reset>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&module_led_pin>;
+ status = "okay";
+
+ module_led: led-0 {
+ gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_HEARTBEAT;
+ linux,default-trigger = "heartbeat";
+ color = <LED_COLOR_ID_AMBER>;
+ };
+ };
+
+ vcc5v0_sys: vccsys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ supports-emmc;
+ mmc-pwrseq = <&emmc_pwrseq>;
+ non-removable;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_emmc>;
+
+ status = "okay";
+};
+
+/* On-module TI DP83825I PHY but no connector, enable in carrierboard */
+&gmac {
+ snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 50000 50000>;
+ phy-supply = <&vcc_3v3>;
+ clock_in_out = "output";
+};
+
+&gpio2 {
+ /*
+ * The Qseven BIOS_DISABLE signal on the PX30-µQ7 keeps the on-module
+ * eMMC powered-down initially (in fact it keeps the reset signal
+ * asserted). BIOS_DISABLE_OVERRIDE pin allows to re-enable eMMC after
+ * the SPL has been booted from SD Card.
+ */
+ bios-disable-override-hog {
+ gpios = <RK_PB5 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "bios_disable_override";
+ gpio-hog;
+ };
+
+ /*
+ * The BIOS_DISABLE hog is a feedback pin for the actual status of the
+ * signal, ignoring the BIOS_DISABLE_OVERRIDE logic. This usually
+ * represents the state of a switch on the baseboard.
+ */
+ bios-disable-n-hog {
+ gpios = <RK_PC2 GPIO_ACTIVE_LOW>;
+ line-name = "bios_disable";
+ input;
+ gpio-hog;
+ };
+};
+
+&gpu {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pmic_int>;
+ pinctrl-names = "default";
+ #clock-cells = <0>;
+ clock-output-names = "xin32k";
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc_3v3>;
+ vcc6-supply = <&vcc_3v3>;
+ vcc7-supply = <&vcc_3v3>;
+ vcc9-supply = <&vcc5v0_sys>;
+
+ regulators {
+ vdd_log: DCDC_REG1 {
+ regulator-name = "vdd_log";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_3v0_1v8: vcc_emmc: DCDC_REG4 {
+ regulator-name = "vcc_3v0_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+
+ vcc_3v3: DCDC_REG5 {
+ regulator-name = "vcc_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_1v8: LDO_REG2 {
+ regulator-name = "vcc_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_1v0: LDO_REG3 {
+ regulator-name = "vcc_1v0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_lcd: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vcc_lcd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc_1v8_lcd: LDO_REG8 {
+ regulator-name = "vcc_1v8_lcd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG9 {
+ regulator-name = "vcca_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ /* SE05x is limited to Fast Mode */
+ clock-frequency = <400000>;
+
+ fan: fan@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ #cooling-cells = <2>;
+ };
+
+ rtc_twi: rtc@6f {
+ compatible = "isil,isl1208";
+ reg = <0x6f>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2s0_8ch {
+ rockchip,trcm-sync-tx-only;
+
+ pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_lrcktx
+ &i2s0_8ch_sdo0 &i2s0_8ch_sdi0>;
+};
+
+&io_domains {
+ vccio1-supply = <&vcc_3v3>;
+ vccio2-supply = <&vccio_sd>;
+ vccio3-supply = <&vcc_3v3>;
+ vccio4-supply = <&vcc_3v3>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_emmc>;
+ vccio-oscgpi-supply = <&vcc_3v3>;
+
+ status = "okay";
+};
+
+&pinctrl {
+ emmc {
+ emmc_reset: emmc-reset {
+ rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ module_led_pin: module-led-pin {
+ rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic-int {
+ rockchip,pins =
+ <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc {
+ vqmmc-supply = <&vccio_sd>;
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy {
+ status = "okay";
+};
+
+&u2phy_host {
+ status = "okay";
+};
+
+/* Mule UCAN */
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
index 2dfa67f1cd67..dd228a256a32 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -96,6 +96,7 @@
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dts b/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dts
new file mode 100644
index 000000000000..61b31688b469
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Hardkernel Co., Ltd
+ * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
+ * Copyright (c) 2022 Maya Matuszczyk <maccraft123mc@gmail.com>
+ */
+
+/dts-v1/;
+#include "rk3326-odroid-go.dtsi"
+
+/ {
+ model = "Anbernic RG351M";
+ compatible = "anbernic,rg351m", "rockchip,rk3326";
+
+ vibrator {
+ compatible = "pwm-vibrator";
+ pwms = <&pwm0 0 1000000 0>;
+ pwm-names = "enable";
+ };
+};
+
+/delete-node/ &builtin_gamepad;
+/delete-node/ &vcc_host; /* conflicts with pwm vibration motor */
+
+&internal_display {
+ compatible = "elida,kd35t133";
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+/delete-node/ &rk817_charger;
diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi
new file mode 100644
index 000000000000..fbc6bfbaa5c1
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi
@@ -0,0 +1,600 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Hardkernel Co., Ltd
+ * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
+ * Copyright (c) 2022 Maya Matuszczyk <maccraft123mc@gmail.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3326.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ power-supply = <&vcc_bl>;
+ pwms = <&pwm1 0 25000 0>;
+ };
+
+ builtin_gamepad: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&btn_pins>;
+
+ button-sw1 {
+ gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
+ label = "DPAD-UP";
+ linux,code = <BTN_DPAD_UP>;
+ };
+ button-sw2 {
+ gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>;
+ label = "DPAD-DOWN";
+ linux,code = <BTN_DPAD_DOWN>;
+ };
+ button-sw3 {
+ gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
+ label = "DPAD-LEFT";
+ linux,code = <BTN_DPAD_LEFT>;
+ };
+ button-sw4 {
+ gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
+ label = "DPAD-RIGHT";
+ linux,code = <BTN_DPAD_RIGHT>;
+ };
+ button-sw5 {
+ gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>;
+ label = "BTN-A";
+ linux,code = <BTN_EAST>;
+ };
+ button-sw6 {
+ gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "BTN-B";
+ linux,code = <BTN_SOUTH>;
+ };
+ button-sw7 {
+ gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
+ label = "BTN-Y";
+ linux,code = <BTN_WEST>;
+ };
+ button-sw8 {
+ gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
+ label = "BTN-X";
+ linux,code = <BTN_NORTH>;
+ };
+ btn_f1: button-sw9 {
+ gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
+ label = "F1";
+ linux,code = <BTN_TRIGGER_HAPPY1>;
+ };
+ btn_f2: button-sw10 {
+ gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>;
+ label = "F2";
+ linux,code = <BTN_TRIGGER_HAPPY2>;
+ };
+ btn_f3: button-sw11 {
+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
+ label = "F3";
+ linux,code = <BTN_TRIGGER_HAPPY3>;
+ };
+ btn_f4: button-sw12 {
+ gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>;
+ label = "F4";
+ linux,code = <BTN_TRIGGER_HAPPY4>;
+ };
+ btn_f5: button-sw13 {
+ gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>;
+ label = "F5";
+ linux,code = <BTN_TRIGGER_HAPPY5>;
+ };
+ btn_f6: button-sw14 {
+ gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "F6";
+ linux,code = <BTN_TRIGGER_HAPPY6>;
+ };
+ button-sw15 {
+ gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
+ label = "TOP-LEFT";
+ linux,code = <BTN_TL>;
+ };
+ button-sw16 {
+ gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
+ label = "TOP-RIGHT";
+ linux,code = <BTN_TR>;
+ };
+ };
+
+ leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blue_led_pin>;
+
+ blue_led: led-0 {
+ label = "blue:heartbeat";
+ gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ rk817-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "Analog";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphones",
+ "Speaker", "Speaker";
+ simple-audio-card,routing =
+ "MICL", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "Speaker", "SPKO";
+
+ simple-audio-card,codec {
+ sound-dai = <&rk817>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_2ch>;
+ };
+ };
+
+ vccsys: vccsys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v8_sys";
+ regulator-always-on;
+ regulator-min-microvolt = <3800000>;
+ regulator-max-microvolt = <3800000>;
+ };
+
+ vcc_host: vcc_host {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&usb_midu>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cru {
+ assigned-clocks = <&cru PLL_NPLL>,
+ <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+ <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
+ <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>,
+ <&cru PLL_CPLL>;
+
+ assigned-clock-rates = <1188000000>,
+ <200000000>, <200000000>,
+ <150000000>, <150000000>,
+ <100000000>, <200000000>,
+ <17000000>;
+};
+
+&display_subsystem {
+ status = "okay";
+};
+
+&dsi {
+ status = "okay";
+
+ ports {
+ mipi_out: port@1 {
+ reg = <1>;
+
+ mipi_out_panel: endpoint {
+ remote-endpoint = <&mipi_in_panel>;
+ };
+ };
+ };
+
+ internal_display: panel@0 {
+ reg = <0>;
+ backlight = <&backlight>;
+ iovcc-supply = <&vcc_lcd>;
+ reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+ rotation = <270>;
+ vdd-supply = <&vcc_lcd>;
+
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
+ };
+};
+
+&dsi_dphy {
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_logic>;
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ i2c-scl-falling-time-ns = <16>;
+ i2c-scl-rising-time-ns = <280>;
+ status = "okay";
+
+ rk817: pmic@20 {
+ compatible = "rockchip,rk817";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+ clock-output-names = "rk808-clkout1", "xin32k";
+ clock-names = "mclk";
+ clocks = <&cru SCLK_I2S1_OUT>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>;
+ wakeup-source;
+ #clock-cells = <1>;
+ #sound-dai-cells = <0>;
+
+ vcc1-supply = <&vccsys>;
+ vcc2-supply = <&vccsys>;
+ vcc3-supply = <&vccsys>;
+ vcc4-supply = <&vccsys>;
+ vcc5-supply = <&vccsys>;
+ vcc6-supply = <&vccsys>;
+ vcc7-supply = <&vccsys>;
+ vcc8-supply = <&vccsys>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <6001>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_3v3: DCDC_REG4 {
+ regulator-name = "vcc_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_1v8: LDO_REG2 {
+ regulator-name = "vcc_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_1v0: LDO_REG3 {
+ regulator-name = "vdd_1v0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG4 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_sd: LDO_REG6 {
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_bl: LDO_REG7 {
+ regulator-name = "vcc_bl";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_lcd: LDO_REG8 {
+ regulator-name = "vcc_lcd";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <2800000>;
+ };
+ };
+
+ LDO_REG9 {
+ /* unused */
+ };
+
+ usb_midu: BOOST {
+ regulator-name = "usb_midu";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5400000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+
+ rk817_charger: charger {
+ rockchip,resistor-sense-micro-ohms = <10000>;
+ rockchip,sleep-enter-current-microamp = <300000>;
+ rockchip,sleep-filter-current-microamp = <100000>;
+ };
+
+ rk817_codec: codec {
+ rockchip,mic-in-differential;
+ };
+ };
+};
+
+/* EXT Header(P2): 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */
+&i2c1 {
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+/* I2S 1 Channel Used */
+&i2s1_2ch {
+ status = "okay";
+};
+
+&io_domains {
+ vccio1-supply = <&vcc_3v3>;
+ vccio2-supply = <&vccio_sd>;
+ vccio3-supply = <&vcc_3v3>;
+ vccio4-supply = <&vcc_3v3>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc {
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&sfc {
+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <108000000>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy {
+ status = "okay";
+
+ u2phy_host: host-port {
+ status = "okay";
+ };
+
+ u2phy_otg: otg-port {
+ status = "disabled";
+ };
+};
+
+&usb20_otg {
+ status = "okay";
+};
+
+/* EXT Header(P2): 2(RXD:GPIO1.C0),3(TXD:.C1),4(CTS:.C2),5(RTS:.C3) */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer &uart1_cts>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m1_xfer>;
+ status = "okay";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&pinctrl {
+ btns {
+ btn_pins: btn-pins {
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ headphone {
+ hp_det: hp-det {
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ leds {
+ blue_led_pin: blue-led-pin {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ dc_det: dc-det {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pmic_int: pmic-int {
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ soc_slppin_gpio: soc_slppin_gpio {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
+ };
+
+ soc_slppin_rst: soc_slppin_rst {
+ rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>;
+ };
+
+ soc_slppin_slp: soc_slppin_slp {
+ rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2-v11.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2-v11.dts
new file mode 100644
index 000000000000..139c898e590e
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2-v11.dts
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Hardkernel Co., Ltd
+ * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
+ * Copyright (c) 2022 Maya Matuszczyk <maccraft123mc@gmail.com>
+ */
+
+/dts-v1/;
+#include "rk3326-odroid-go.dtsi"
+
+/ {
+ model = "ODROID-GO Advance Black Edition";
+ compatible = "hardkernel,rk3326-odroid-go2-v11", "rockchip,rk3326";
+
+ aliases {
+ mmc1 = &sdio;
+ };
+
+ analog_sticks: adc-joystick {
+ compatible = "adc-joystick";
+ io-channels = <&saradc 1>,
+ <&saradc 2>;
+ poll-interval = <60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ axis@0 {
+ reg = <0>;
+ abs-flat = <10>;
+ abs-fuzz = <10>;
+ abs-range = <172 772>;
+ linux,code = <ABS_X>;
+ };
+
+ axis@1 {
+ reg = <1>;
+ abs-flat = <10>;
+ abs-fuzz = <10>;
+ abs-range = <278 815>;
+ linux,code = <ABS_Y>;
+ };
+ };
+
+ battery: battery {
+ compatible = "simple-battery";
+ charge-full-design-microamp-hours = <3000000>;
+ charge-term-current-microamp = <300000>;
+ constant-charge-current-max-microamp = <2000000>;
+ constant-charge-voltage-max-microvolt = <4200000>;
+ factory-internal-resistance-micro-ohms = <180000>;
+ voltage-max-design-microvolt = <4100000>;
+ voltage-min-design-microvolt = <3500000>;
+
+ ocv-capacity-celsius = <20>;
+ ocv-capacity-table-0 = <4046950 100>, <4001920 95>, <3967900 90>, <3919950 85>,
+ <3888450 80>, <3861850 75>, <3831540 70>, <3799130 65>,
+ <3768190 60>, <3745650 55>, <3726610 50>, <3711630 45>,
+ <3696720 40>, <3685660 35>, <3674950 30>, <3663050 25>,
+ <3649470 20>, <3635260 15>, <3616920 10>, <3592440 5>,
+ <3574170 0>;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_pwrseq_pins>;
+ reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&builtin_gamepad {
+ button-sw20 {
+ gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ label = "TOP-LEFT 2";
+ linux,code = <BTN_TL2>;
+ };
+ button-sw21 {
+ gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
+ label = "TOP-RIGHT 2";
+ linux,code = <BTN_TR2>;
+ };
+};
+
+&internal_display {
+ compatible = "elida,kd35t133";
+};
+
+&rk817 {
+ regulators {
+ vcc_wifi: LDO_REG9 {
+ regulator-name = "vcc_wifi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+ };
+};
+
+&rk817_charger {
+ monitored-battery = <&battery>;
+};
+
+&sdio {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ vmmc-supply = <&vcc_wifi>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ esp8089: wifi@1 {
+ compatible = "esp,esp8089";
+ reg = <1>;
+ };
+};
+
+&pinctrl {
+ btns {
+ btn_pins: btn-pins {
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ wifi {
+ wifi_pwrseq_pins: wifi-pwrseq-pins {
+ rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PB6 RK_FUNC_GPIO &pcfg_output_high>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
index 72899a714310..4702183b673c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
@@ -2,30 +2,21 @@
/*
* Copyright (c) 2019 Hardkernel Co., Ltd
* Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
+ * Copyright (c) 2022 Maya Matuszczyk <maccraft123mc@gmail.com>
*/
/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rk3326.dtsi"
+#include "rk3326-odroid-go.dtsi"
/ {
model = "ODROID-GO Advance";
compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326";
- aliases {
- mmc0 = &sdmmc;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- adc-joystick {
+ analog_sticks: adc-joystick {
compatible = "adc-joystick";
io-channels = <&saradc 1>,
<&saradc 2>;
+ poll-interval = <60>;
#address-cells = <1>;
#size-cells = <0>;
@@ -46,12 +37,6 @@
};
};
- backlight: backlight {
- compatible = "pwm-backlight";
- power-supply = <&vcc_bl>;
- pwms = <&pwm1 0 25000 0>;
- };
-
battery: battery {
compatible = "simple-battery";
charge-full-design-microamp-hours = <3000000>;
@@ -63,606 +48,19 @@
voltage-min-design-microvolt = <3500000>;
ocv-capacity-celsius = <20>;
- ocv-capacity-table-0 = <4046950 100>, <4001920 95>, <3967900 90>, <3919950 85>,
+ ocv-capacity-table-0 = <4046950 100>, <4001920 95>, <3967900 90>, <3919950 85>,
<3888450 80>, <3861850 75>, <3831540 70>, <3799130 65>,
<3768190 60>, <3745650 55>, <3726610 50>, <3711630 45>,
<3696720 40>, <3685660 35>, <3674950 30>, <3663050 25>,
<3649470 20>, <3635260 15>, <3616920 10>, <3592440 5>,
<3574170 0>;
};
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&btn_pins>;
-
- /*
- * *** ODROIDGO2-Advance Switch layout ***
- * |------------------------------------------------|
- * | sw15 sw16 |
- * |------------------------------------------------|
- * | sw1 |-------------------| sw8 |
- * | sw3 sw4 | | sw7 sw5 |
- * | sw2 | LCD Display | sw6 |
- * | | | |
- * | |-------------------| |
- * | sw9 sw10 sw11 sw12 sw13 sw14 |
- * |------------------------------------------------|
- */
-
- button-sw1 {
- gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
- label = "DPAD-UP";
- linux,code = <BTN_DPAD_UP>;
- };
- button-sw2 {
- gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>;
- label = "DPAD-DOWN";
- linux,code = <BTN_DPAD_DOWN>;
- };
- button-sw3 {
- gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
- label = "DPAD-LEFT";
- linux,code = <BTN_DPAD_LEFT>;
- };
- button-sw4 {
- gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
- label = "DPAD-RIGHT";
- linux,code = <BTN_DPAD_RIGHT>;
- };
- button-sw5 {
- gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>;
- label = "BTN-A";
- linux,code = <BTN_EAST>;
- };
- button-sw6 {
- gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
- label = "BTN-B";
- linux,code = <BTN_SOUTH>;
- };
- button-sw7 {
- gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
- label = "BTN-Y";
- linux,code = <BTN_WEST>;
- };
- button-sw8 {
- gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
- label = "BTN-X";
- linux,code = <BTN_NORTH>;
- };
- button-sw9 {
- gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
- label = "F1";
- linux,code = <BTN_TRIGGER_HAPPY1>;
- };
- button-sw10 {
- gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>;
- label = "F2";
- linux,code = <BTN_TRIGGER_HAPPY2>;
- };
- button-sw11 {
- gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
- label = "F3";
- linux,code = <BTN_TRIGGER_HAPPY3>;
- };
- button-sw12 {
- gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>;
- label = "F4";
- linux,code = <BTN_TRIGGER_HAPPY4>;
- };
- button-sw13 {
- gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>;
- label = "F5";
- linux,code = <BTN_TRIGGER_HAPPY5>;
- };
- button-sw14 {
- gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>;
- label = "F6";
- linux,code = <BTN_TRIGGER_HAPPY6>;
- };
- button-sw15 {
- gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
- label = "TOP-LEFT";
- linux,code = <BTN_TL>;
- };
- button-sw16 {
- gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
- label = "TOP-RIGHT";
- linux,code = <BTN_TR>;
- };
- };
-
- leds: gpio-leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&blue_led_pin>;
-
- blue_led: led-0 {
- label = "blue:heartbeat";
- gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- rk817-sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "Analog";
- simple-audio-card,format = "i2s";
- simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
- simple-audio-card,mclk-fs = <256>;
- simple-audio-card,widgets =
- "Microphone", "Mic Jack",
- "Headphone", "Headphones",
- "Speaker", "Speaker";
- simple-audio-card,routing =
- "MICL", "Mic Jack",
- "Headphones", "HPOL",
- "Headphones", "HPOR",
- "Speaker", "SPKO";
-
- simple-audio-card,codec {
- sound-dai = <&rk817>;
- };
-
- simple-audio-card,cpu {
- sound-dai = <&i2s1_2ch>;
- };
- };
-
- vccsys: vccsys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v8_sys";
- regulator-always-on;
- regulator-min-microvolt = <3800000>;
- regulator-max-microvolt = <3800000>;
- };
-
- vcc_host: vcc_host {
- compatible = "regulator-fixed";
- regulator-name = "vcc_host";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
-
- gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&usb_midu>;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_arm>;
-};
-
-&cru {
- assigned-clocks = <&cru PLL_NPLL>,
- <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
- <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
- <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>,
- <&cru PLL_CPLL>;
-
- assigned-clock-rates = <1188000000>,
- <200000000>, <200000000>,
- <150000000>, <150000000>,
- <100000000>, <200000000>,
- <17000000>;
};
-&display_subsystem {
- status = "okay";
+&internal_display {
+ compatible = "elida,kd35t133";
};
-&dsi {
- status = "okay";
-
- ports {
- mipi_out: port@1 {
- reg = <1>;
-
- mipi_out_panel: endpoint {
- remote-endpoint = <&mipi_in_panel>;
- };
- };
- };
-
- panel@0 {
- compatible = "elida,kd35t133";
- reg = <0>;
- backlight = <&backlight>;
- iovcc-supply = <&vcc_lcd>;
- reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
- rotation = <270>;
- vdd-supply = <&vcc_lcd>;
-
- port {
- mipi_in_panel: endpoint {
- remote-endpoint = <&mipi_out_panel>;
- };
- };
- };
-};
-
-&dsi_dphy {
- status = "okay";
-};
-
-&gpu {
- mali-supply = <&vdd_logic>;
- status = "okay";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
- i2c-scl-falling-time-ns = <16>;
- i2c-scl-rising-time-ns = <280>;
- status = "okay";
-
- rk817: pmic@20 {
- compatible = "rockchip,rk817";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
- clock-output-names = "rk808-clkout1", "xin32k";
- clock-names = "mclk";
- clocks = <&cru SCLK_I2S1_OUT>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>;
- wakeup-source;
- #clock-cells = <1>;
- #sound-dai-cells = <0>;
-
- vcc1-supply = <&vccsys>;
- vcc2-supply = <&vccsys>;
- vcc3-supply = <&vccsys>;
- vcc4-supply = <&vccsys>;
- vcc5-supply = <&vccsys>;
- vcc6-supply = <&vccsys>;
- vcc7-supply = <&vccsys>;
- vcc8-supply = <&vccsys>;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-name = "vdd_logic";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1150000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vdd_arm: DCDC_REG2 {
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <950000>;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_3v3: DCDC_REG4 {
- regulator-name = "vcc_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_1v8: LDO_REG2 {
- regulator-name = "vcc_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vdd_1v0: LDO_REG3 {
- regulator-name = "vdd_1v0";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc3v3_pmu: LDO_REG4 {
- regulator-name = "vcc3v3_pmu";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_sd: LDO_REG6 {
- regulator-name = "vcc_sd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_bl: LDO_REG7 {
- regulator-name = "vcc_bl";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_lcd: LDO_REG8 {
- regulator-name = "vcc_lcd";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <2800000>;
- };
- };
-
- vcc_cam: LDO_REG9 {
- regulator-name = "vcc_cam";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- usb_midu: BOOST {
- regulator-name = "usb_midu";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5400000>;
- regulator-always-on;
- regulator-boot-on;
- };
- };
-
- rk817_charger: charger {
- monitored-battery = <&battery>;
- rockchip,resistor-sense-micro-ohms = <10000>;
- rockchip,sleep-enter-current-microamp = <300000>;
- rockchip,sleep-filter-current-microamp = <100000>;
- };
-
- rk817_codec: codec {
- rockchip,mic-in-differential;
- };
- };
-};
-
-/* EXT Header(P2): 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */
-&i2c1 {
- clock-frequency = <400000>;
- status = "okay";
-};
-
-/* I2S 1 Channel Used */
-&i2s1_2ch {
- status = "okay";
-};
-
-&io_domains {
- vccio1-supply = <&vcc_3v3>;
- vccio2-supply = <&vccio_sd>;
- vccio3-supply = <&vcc_3v3>;
- vccio4-supply = <&vcc_3v3>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_3v3>;
- status = "okay";
-};
-
-&pmu_io_domains {
- pmuio1-supply = <&vcc3v3_pmu>;
- pmuio2-supply = <&vcc3v3_pmu>;
- status = "okay";
-};
-
-&pwm1 {
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcc_1v8>;
- status = "okay";
-};
-
-&sdmmc {
- cap-sd-highspeed;
- card-detect-delay = <200>;
- cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_sd>;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-};
-
-&sfc {
- pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <108000000>;
- spi-rx-bus-width = <2>;
- spi-tx-bus-width = <1>;
- };
-};
-
-&tsadc {
- status = "okay";
-};
-
-&u2phy {
- status = "okay";
-
- u2phy_host: host-port {
- status = "okay";
- };
-
- u2phy_otg: otg-port {
- status = "disabled";
- };
-};
-
-&usb20_otg {
- status = "okay";
-};
-
-/* EXT Header(P2): 2(RXD:GPIO1.C0),3(TXD:.C1),4(CTS:.C2),5(RTS:.C3) */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_xfer &uart1_cts>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2m1_xfer>;
- status = "okay";
-};
-
-&vopb {
- status = "okay";
-};
-
-&vopb_mmu {
- status = "okay";
-};
-
-&pinctrl {
- btns {
- btn_pins: btn-pins {
- rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
- <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- headphone {
- hp_det: hp-det {
- rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
- };
- };
-
- leds {
- blue_led_pin: blue-led-pin {
- rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- dc_det: dc-det {
- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- pmic_int: pmic-int {
- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- soc_slppin_gpio: soc_slppin_gpio {
- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
- };
-
- soc_slppin_rst: soc_slppin_rst {
- rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>;
- };
-
- soc_slppin_slp: soc_slppin_slp {
- rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
- };
- };
+&rk817_charger {
+ monitored-battery = <&battery>;
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts
new file mode 100644
index 000000000000..842efbaf1a6a
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Hardkernel Co., Ltd
+ * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
+ * Copyright (c) 2022 Maya Matuszczyk <maccraft123mc@gmail.com>
+ */
+
+/dts-v1/;
+#include "rk3326-odroid-go.dtsi"
+
+/ {
+ model = "ODROID-GO Super";
+ compatible = "hardkernel,rk3326-odroid-go3", "rockchip,rk3326";
+
+ joystick_mux_controller: mux-controller {
+ compatible = "gpio-mux";
+ pinctrl = <&mux_en_pins>;
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>,
+ <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+ };
+
+ joystick_mux: adc-mux {
+ compatible = "io-channel-mux";
+ io-channels = <&saradc 1>;
+ io-channel-names = "parent";
+ #io-channel-cells = <1>;
+
+ mux-controls = <&joystick_mux_controller>;
+ channels = "0", "1", "2", "3";
+ };
+
+ analog_sticks: adc-joystick {
+ compatible = "adc-joystick";
+ io-channels = <&joystick_mux 0>,
+ <&joystick_mux 1>,
+ <&joystick_mux 2>,
+ <&joystick_mux 3>;
+ poll-interval = <60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ axis@0 {
+ reg = <0>;
+ abs-flat = <10>;
+ abs-fuzz = <10>;
+ abs-range = <180 800>;
+ linux,code = <ABS_X>;
+ };
+
+ axis@1 {
+ reg = <1>;
+ abs-flat = <10>;
+ abs-fuzz = <10>;
+ abs-range = <180 800>;
+ linux,code = <ABS_RX>;
+ };
+
+ axis@2 {
+ reg = <2>;
+ abs-flat = <10>;
+ abs-fuzz = <10>;
+ abs-range = <180 800>;
+ linux,code = <ABS_Y>;
+ };
+
+ axis@3 {
+ reg = <3>;
+ abs-flat = <10>;
+ abs-fuzz = <10>;
+ abs-range = <180 800>;
+ linux,code = <ABS_RY>;
+ };
+ };
+
+ battery: battery {
+ compatible = "simple-battery";
+ charge-full-design-microamp-hours = <4000000>;
+ charge-term-current-microamp = <300000>;
+ constant-charge-current-max-microamp = <2000000>;
+ constant-charge-voltage-max-microvolt = <4200000>;
+ factory-internal-resistance-micro-ohms = <180000>;
+ voltage-max-design-microvolt = <4100000>;
+ voltage-min-design-microvolt = <3500000>;
+
+ ocv-capacity-celsius = <20>;
+ ocv-capacity-table-0 = <4046950 100>, <4001920 95>, <3967900 90>, <3919950 85>,
+ <3888450 80>, <3861850 75>, <3831540 70>, <3799130 65>,
+ <3768190 60>, <3745650 55>, <3726610 50>, <3711630 45>,
+ <3696720 40>, <3685660 35>, <3674950 30>, <3663050 25>,
+ <3649470 20>, <3635260 15>, <3616920 10>, <3592440 5>,
+ <3574170 0>;
+ };
+
+ gpio-keys-vol {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-0 = <&btn_pins_vol>;
+ pinctrl-names = "default";
+
+ button-vol-down {
+ gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>;
+ label = "VOLUMEDOWN";
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+
+ button-volume-up {
+ gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
+ label = "VOLUMEUP";
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+};
+
+/* f1 and f2 conflict with volume buttons */
+/delete-node/ &btn_f1;
+/delete-node/ &btn_f2;
+
+&builtin_gamepad {
+ button-sw19 {
+ gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
+ label = "SELECT";
+ linux,code = <BTN_SELECT>;
+ };
+ /* note that TR2 and TL2 are swapped */
+ button-sw20 {
+ gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ label = "TOP-RIGHT 2";
+ linux,code = <BTN_TR2>;
+ };
+ button-sw21 {
+ gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
+ label = "TOP-LEFT 2";
+ linux,code = <BTN_TL2>;
+ };
+ button-sw22 {
+ gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
+ label = "START";
+ linux,code = <BTN_START>;
+ };
+};
+
+&internal_display {
+ status = "disabled";
+};
+
+&rk817_charger {
+ monitored-battery = <&battery>;
+};
+
+&pinctrl {
+ btns {
+ btn_pins: btn-pins {
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
+ <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ btn_pins_vol: btn-pins-vol {
+ rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
+ <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ joystick {
+ mux_en_pins: mux-pins {
+ rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_output_low>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 49ae15708a0b..6d7a7bf72ac7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -102,6 +102,7 @@
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
@@ -1025,6 +1026,17 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ crypto: crypto@ff060000 {
+ compatible = "rockchip,rk3328-crypto";
+ reg = <0x0 0xff060000 0x0 0x4000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>,
+ <&cru SCLK_CRYPTO>;
+ clock-names = "hclk_master", "hclk_slave", "sclk";
+ resets = <&cru SRST_CRYPTO>;
+ reset-names = "crypto-rst";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3328-pinctrl";
rockchip,grf = <&grf>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
index 2e058c315025..04403a76238b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
@@ -81,6 +81,27 @@
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc3v3_sys>;
};
+
+ wifi_pwrseq: sdio-wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk818 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h_pin>;
+ /*
+ * Wait between power-on and SDIO access for CYP43455
+ * POR circuit.
+ */
+ post-power-on-delay-ms = <110>;
+ /*
+ * Wait between consecutive toggles for CYP43455 CBUCK
+ * regulator discharge.
+ */
+ power-off-delay-us = <10000>;
+
+ /* WL_REG_ON on module */
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
};
&cpu_l0 {
@@ -360,11 +381,45 @@
};
};
+ sdio-pwrseq {
+ wifi_enable_h_pin: wifi-enable-h-pin {
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
sound {
vcc1v8_codec_en: vcc1v8-codec-en {
rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
+
+ wireless-bluetooth {
+ bt_wake_pin: bt-wake-pin {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_pin: bt-host-wake-pin {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_reset_pin: bt-reset-pin {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdio0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ status = "okay";
};
&sdmmc {
@@ -393,6 +448,27 @@
status = "okay";
};
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ clocks = <&rk818 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+ max-speed = <1500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_pin &bt_wake_pin &bt_reset_pin>;
+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+ vbat-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc_1v8>;
+ };
+};
+
&uart2 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
index f9884902f874..309c35d7fca8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
@@ -601,6 +601,12 @@
status = "okay";
};
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
&u2phy0 {
status = "okay";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
index 94e39ed63397..c920ddf44baf 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
@@ -128,6 +128,8 @@
};
&hdmi {
+ avdd-0v9-supply = <&vcca0v9_hdmi>;
+ avdd-1v8-supply = <&vcca1v8_hdmi>;
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 92c2207e686c..4391aea25984 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -582,6 +582,26 @@
status = "disabled";
};
+ crypto0: crypto@ff8b0000 {
+ compatible = "rockchip,rk3399-crypto";
+ reg = <0x0 0xff8b0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>;
+ clock-names = "hclk_master", "hclk_slave", "sclk";
+ resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>;
+ reset-names = "master", "lave", "crypto";
+ };
+
+ crypto1: crypto@ff8b8000 {
+ compatible = "rockchip,rk3399-crypto";
+ reg = <0x0 0xff8b8000 0x0 0x4000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>;
+ clock-names = "hclk_master", "hclk_slave", "sclk";
+ resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>;
+ reset-names = "master", "slave", "crypto";
+ };
+
i2c1: i2c@ff110000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff110000 0x0 0x1000>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts
index 7a20e2d6876a..63cff402f3a8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts
@@ -5,7 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/pinctrl/rockchip.h>
-#include "rk3566-anbernic-rgxx3.dtsi"
+#include "rk3566-anbernic-rg353x.dtsi"
/ {
model = "RG353P";
@@ -18,26 +18,66 @@
mmc3 = &sdmmc2;
};
- backlight: backlight {
- compatible = "pwm-backlight";
- power-supply = <&vcc_sys>;
- pwms = <&pwm4 0 25000 0>;
+ battery: battery {
+ compatible = "simple-battery";
+ charge-full-design-microamp-hours = <3472000>;
+ charge-term-current-microamp = <300000>;
+ constant-charge-current-max-microamp = <2000000>;
+ constant-charge-voltage-max-microvolt = <4200000>;
+ factory-internal-resistance-micro-ohms = <117000>;
+ voltage-max-design-microvolt = <4172000>;
+ voltage-min-design-microvolt = <3400000>;
+
+ ocv-capacity-celsius = <20>;
+ ocv-capacity-table-0 = <4172000 100>, <4054000 95>, <3984000 90>, <3926000 85>,
+ <3874000 80>, <3826000 75>, <3783000 70>, <3746000 65>,
+ <3714000 60>, <3683000 55>, <3650000 50>, <3628000 45>,
+ <3612000 40>, <3600000 35>, <3587000 30>, <3571000 25>,
+ <3552000 20>, <3525000 15>, <3492000 10>, <3446000 5>,
+ <3400000 0>;
};
-};
-&gpio_keys_control {
- button-a {
- gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
- label = "EAST";
- linux,code = <BTN_EAST>;
+ /* Channels reversed for both headphones and speakers. */
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "rk817_ext";
+ simple-audio-card,aux-devs = <&spk_amp>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphones",
+ "Speaker", "Internal Speakers";
+ simple-audio-card,routing =
+ "MICL", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "Internal Speakers", "Speaker Amp OUTL",
+ "Internal Speakers", "Speaker Amp OUTR",
+ "Speaker Amp INL", "HPOL",
+ "Speaker Amp INR", "HPOR";
+ simple-audio-card,pin-switches = "Internal Speakers";
+
+ simple-audio-card,codec {
+ sound-dai = <&rk817>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
};
- button-left {
- gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
- label = "DPAD-LEFT";
- linux,code = <BTN_DPAD_LEFT>;
+ spk_amp: audio-amplifier {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&spk_amp_enable_h>;
+ pinctrl-names = "default";
+ sound-name-prefix = "Speaker Amp";
};
+};
+&gpio_keys_control {
button-r1 {
gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
label = "TR";
@@ -49,27 +89,6 @@
label = "TR2";
linux,code = <BTN_TR2>;
};
-
- button-right {
- gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>;
- label = "DPAD-RIGHT";
- linux,code = <BTN_DPAD_RIGHT>;
- };
-
- button-y {
- gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
- label = "WEST";
- linux,code = <BTN_WEST>;
- };
-};
-
-&i2c0 {
- /* This hardware is physically present but unused. */
- power-monitor@62 {
- compatible = "cellwise,cw2015";
- reg = <0x62>;
- status = "disabled";
- };
};
&i2c2 {
@@ -78,8 +97,22 @@
status = "okay";
};
-&pwm4 {
- status = "okay";
+&pinctrl {
+ audio-amplifier {
+ spk_amp_enable_h: spk-amp-enable-h {
+ rockchip,pins =
+ <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&rk817 {
+ rk817_charger: charger {
+ monitored-battery = <&battery>;
+ rockchip,resistor-sense-micro-ohms = <10000>;
+ rockchip,sleep-enter-current-microamp = <300000>;
+ rockchip,sleep-filter-current-microamp = <100000>;
+ };
};
&sdhci {
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353v.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353v.dts
new file mode 100644
index 000000000000..885234a023e1
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353v.dts
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566-anbernic-rg353x.dtsi"
+
+/ {
+ model = "RG353V";
+ compatible = "anbernic,rg353v", "rockchip,rk3566";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
+ mmc2 = &sdmmc1;
+ mmc3 = &sdmmc2;
+ };
+
+ battery: battery {
+ compatible = "simple-battery";
+ charge-full-design-microamp-hours = <3151000>;
+ charge-term-current-microamp = <300000>;
+ constant-charge-current-max-microamp = <2000000>;
+ constant-charge-voltage-max-microvolt = <4200000>;
+ factory-internal-resistance-micro-ohms = <117000>;
+ voltage-max-design-microvolt = <4172000>;
+ voltage-min-design-microvolt = <3400000>;
+
+ ocv-capacity-celsius = <20>;
+ ocv-capacity-table-0 = <4172000 100>, <4054000 95>, <3984000 90>, <3926000 85>,
+ <3874000 80>, <3826000 75>, <3783000 70>, <3746000 65>,
+ <3714000 60>, <3683000 55>, <3650000 50>, <3628000 45>,
+ <3612000 40>, <3600000 35>, <3587000 30>, <3571000 25>,
+ <3552000 20>, <3525000 15>, <3492000 10>, <3446000 5>,
+ <3400000 0>;
+ };
+
+ /* Channels reversed for headphones. */
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "rk817_int";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphones",
+ "Speaker", "Internal Speakers";
+ simple-audio-card,routing =
+ "MICL", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "Internal Speakers", "SPKO";
+
+ simple-audio-card,codec {
+ sound-dai = <&rk817>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+ };
+};
+
+&gpio_keys_control {
+ button-r1 {
+ gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
+ label = "TR";
+ linux,code = <BTN_TR>;
+ };
+
+ button-r2 {
+ gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
+ label = "TR2";
+ linux,code = <BTN_TR2>;
+ };
+};
+
+&i2c2 {
+ pintctrl-names = "default";
+ pinctrl-0 = <&i2c2m1_xfer>;
+ status = "okay";
+};
+
+&pinctrl {
+ touch {
+ touch_rst: touch-rst {
+ rockchip,pins =
+ <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&rk817 {
+ rk817_charger: charger {
+ monitored-battery = <&battery>;
+ rockchip,resistor-sense-micro-ohms = <10000>;
+ rockchip,sleep-enter-current-microamp = <300000>;
+ rockchip,sleep-filter-current-microamp = <100000>;
+ };
+};
+
+&sdhci {
+ pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, <&emmc_datastrobe>, <&emmc_rstnout>;
+ pinctrl-names = "default";
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353vs.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353vs.dts
new file mode 100644
index 000000000000..a7dc462fe21f
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353vs.dts
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566-anbernic-rg353x.dtsi"
+
+/ {
+ model = "RG353VS";
+ compatible = "anbernic,rg353vs", "rockchip,rk3566";
+
+ aliases {
+ mmc0 = &sdmmc0;
+ mmc1 = &sdmmc1;
+ mmc2 = &sdmmc2;
+ };
+
+ battery: battery {
+ compatible = "simple-battery";
+ charge-full-design-microamp-hours = <3151000>;
+ charge-term-current-microamp = <300000>;
+ constant-charge-current-max-microamp = <2000000>;
+ constant-charge-voltage-max-microvolt = <4200000>;
+ factory-internal-resistance-micro-ohms = <117000>;
+ voltage-max-design-microvolt = <4172000>;
+ voltage-min-design-microvolt = <3400000>;
+
+ ocv-capacity-celsius = <20>;
+ ocv-capacity-table-0 = <4172000 100>, <4054000 95>, <3984000 90>, <3926000 85>,
+ <3874000 80>, <3826000 75>, <3783000 70>, <3746000 65>,
+ <3714000 60>, <3683000 55>, <3650000 50>, <3628000 45>,
+ <3612000 40>, <3600000 35>, <3587000 30>, <3571000 25>,
+ <3552000 20>, <3525000 15>, <3492000 10>, <3446000 5>,
+ <3400000 0>;
+ };
+
+ /* Channels reversed for headphones. */
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "rk817_int";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphones",
+ "Speaker", "Internal Speakers";
+ simple-audio-card,routing =
+ "MICL", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "Internal Speakers", "SPKO";
+
+ simple-audio-card,codec {
+ sound-dai = <&rk817>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+ };
+};
+
+&gpio_keys_control {
+ button-r1 {
+ gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
+ label = "TR";
+ linux,code = <BTN_TR>;
+ };
+
+ button-r2 {
+ gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
+ label = "TR2";
+ linux,code = <BTN_TR2>;
+ };
+};
+
+&rk817 {
+ rk817_charger: charger {
+ monitored-battery = <&battery>;
+ rockchip,resistor-sense-micro-ohms = <10000>;
+ rockchip,sleep-enter-current-microamp = <300000>;
+ rockchip,sleep-filter-current-microamp = <100000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi
new file mode 100644
index 000000000000..65a80d1f6d91
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566-anbernic-rgxx3.dtsi"
+
+/ {
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ power-supply = <&vcc_sys>;
+ pwms = <&pwm4 0 25000 0>;
+ };
+};
+
+&cru {
+ assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
+ assigned-clock-rates = <1200000000>, <200000000>, <241500000>;
+};
+
+&gpio_keys_control {
+ button-a {
+ gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
+ label = "EAST";
+ linux,code = <BTN_EAST>;
+ };
+
+ button-left {
+ gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
+ label = "DPAD-LEFT";
+ linux,code = <BTN_DPAD_LEFT>;
+ };
+
+ button-right {
+ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "DPAD-RIGHT";
+ linux,code = <BTN_DPAD_RIGHT>;
+ };
+
+ button-y {
+ gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
+ label = "WEST";
+ linux,code = <BTN_WEST>;
+ };
+};
+
+&i2c0 {
+ /* This hardware is physically present but unused. */
+ power-monitor@62 {
+ compatible = "cellwise,cw2015";
+ reg = <0x62>;
+ status = "disabled";
+ };
+};
+
+&pwm4 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
index 3dc01549a5b4..5dafcc86296b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
@@ -17,6 +17,25 @@
mmc2 = &sdmmc2;
};
+ battery: battery {
+ compatible = "simple-battery";
+ charge-full-design-microamp-hours = <3472000>;
+ charge-term-current-microamp = <300000>;
+ constant-charge-current-max-microamp = <2000000>;
+ constant-charge-voltage-max-microvolt = <4200000>;
+ factory-internal-resistance-micro-ohms = <117000>;
+ voltage-max-design-microvolt = <4172000>;
+ voltage-min-design-microvolt = <3400000>;
+
+ ocv-capacity-celsius = <20>;
+ ocv-capacity-table-0 = <4172000 100>, <4054000 95>, <3984000 90>, <3926000 85>,
+ <3874000 80>, <3826000 75>, <3783000 70>, <3746000 65>,
+ <3714000 60>, <3683000 55>, <3650000 50>, <3628000 45>,
+ <3612000 40>, <3600000 35>, <3587000 30>, <3571000 25>,
+ <3552000 20>, <3525000 15>, <3492000 10>, <3446000 5>,
+ <3400000 0>;
+ };
+
gpio_spi: spi {
compatible = "spi-gpio";
pinctrl-names = "default";
@@ -29,6 +48,50 @@
cs-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
num-chipselects = <0>;
};
+
+ /* Channels reversed for both headphones and speakers. */
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "rk817_ext";
+ simple-audio-card,aux-devs = <&spk_amp>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphones",
+ "Speaker", "Internal Speakers";
+ simple-audio-card,routing =
+ "MICL", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "Internal Speakers", "Speaker Amp OUTL",
+ "Internal Speakers", "Speaker Amp OUTR",
+ "Speaker Amp INL", "HPOL",
+ "Speaker Amp INR", "HPOR";
+ simple-audio-card,pin-switches = "Internal Speakers";
+
+ simple-audio-card,codec {
+ sound-dai = <&rk817>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+ };
+
+ spk_amp: audio-amplifier {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&spk_amp_enable_h>;
+ pinctrl-names = "default";
+ sound-name-prefix = "Speaker Amp";
+ };
+};
+
+&cru {
+ assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
+ assigned-clock-rates = <1200000000>, <200000000>, <500000000>;
};
&gpio_keys_control {
@@ -76,6 +139,13 @@
};
&pinctrl {
+ audio-amplifier {
+ spk_amp_enable_h: spk-amp-enable-h {
+ rockchip,pins =
+ <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
gpio-spi {
spi_pins: spi-pins {
rockchip,pins =
@@ -85,3 +155,12 @@
};
};
};
+
+&rk817 {
+ rk817_charger: charger {
+ monitored-battery = <&battery>;
+ rockchip,resistor-sense-micro-ohms = <10000>;
+ rockchip,sleep-enter-current-microamp = <300000>;
+ rockchip,sleep-filter-current-microamp = <100000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi
index 2b455143b86d..41262a69d33e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi
@@ -22,6 +22,7 @@
<&adc_mux 3>;
pinctrl-0 = <&joy_mux_en>;
pinctrl-names = "default";
+ poll-interval = <60>;
#address-cells = <1>;
#size-cells = <0>;
@@ -217,37 +218,6 @@
};
};
- /* Channels reversed for both headphones and speakers. */
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "anbernic_rk817";
- simple-audio-card,aux-devs = <&spk_amp>;
- simple-audio-card,format = "i2s";
- simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
- simple-audio-card,mclk-fs = <256>;
- simple-audio-card,widgets =
- "Microphone", "Mic Jack",
- "Headphone", "Headphones",
- "Speaker", "Internal Speakers";
- simple-audio-card,routing =
- "MICL", "Mic Jack",
- "Headphones", "HPOL",
- "Headphones", "HPOR",
- "Internal Speakers", "Speaker Amp OUTL",
- "Internal Speakers", "Speaker Amp OUTR",
- "Speaker Amp INL", "HPOL",
- "Speaker Amp INR", "HPOR";
- simple-audio-card,pin-switches = "Internal Speakers";
-
- simple-audio-card,codec {
- sound-dai = <&rk817>;
- };
-
- simple-audio-card,cpu {
- sound-dai = <&i2s1_8ch>;
- };
- };
-
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk817 1>;
@@ -258,14 +228,6 @@
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>;
};
- spk_amp: audio-amplifier {
- compatible = "simple-audio-amplifier";
- enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&spk_amp_enable_h>;
- pinctrl-names = "default";
- sound-name-prefix = "Speaker Amp";
- };
-
vcc3v3_lcd0_n: regulator-vcc3v3-lcd0 {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
@@ -607,13 +569,6 @@
};
&pinctrl {
- audio-amplifier {
- spk_amp_enable_h: spk-amp-enable-h {
- rockchip,pins =
- <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
gpio-btns {
btn_pins_ctrl: btn-pins-ctrl {
rockchip,pins =
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts b/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
new file mode 100644
index 000000000000..4c7f9abd594f
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
@@ -0,0 +1,503 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Author: Piotr Oniszczuk piotr.oniszczuk@gmail.com
+ * Based on Quartz64 DT by: Peter Geis pgwipeout@gmail.com
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3566.dtsi"
+
+/ {
+ model = "Rockchip RK3566 BOX DEMO Board";
+ compatible = "rockchip,rk3566-box-demo", "rockchip,rk3566";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdmmc1;
+ mmc2 = &sdhci;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&ir_int>;
+ linux,rc-map-name = "rc-beelink-gs1";
+ status = "okay";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_work: led-0 {
+ gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_BLUE>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_work_en>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ status = "okay";
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&pmucru CLK_RTC_32K>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h &wifi_32k>;
+ reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
+ };
+
+ spdif_dit: spdif-dit {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+ };
+
+ spdif_sound: spdif-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "SPDIF";
+
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_dit>;
+ };
+ };
+
+ vcc12v0_dcin: regulator-vcc12v0-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v0_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc5v0_sys: regulator-vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v0_dcin>;
+ };
+
+ vcc3v3_sys: regulator-vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc12v0_dcin>;
+ };
+
+ vcc_3v3: regulator-vcc-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc5v0_usb_host: regulator-vcc5v0-usb-host {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_host_en>;
+ regulator-name = "vcc5v0_usb_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb2_otg: regulator-vcc5v0-usb2-otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb2_otg_en>;
+ regulator-name = "vcc5v0_usb_otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcca_1v8: regulator-vcca-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vdda_0v9: regulator-vdda-0v9 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vdd_fixed: regulator-vdd-fixed {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_fixed";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <950000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vdd_cpu: regulator-vdd-cpu {
+ compatible = "pwm-regulator";
+ pwms = <&pwm0 0 5000 1>;
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-settling-time-up-us = <250>;
+ pwm-supply = <&vcc5v0_sys>;
+ };
+
+ vdd_logic: regulator-vdd-logic {
+ compatible = "pwm-regulator";
+ pwms = <&pwm1 0 5000 1>;
+ regulator-name = "vdd_logic";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-settling-time-up-us = <250>;
+ pwm-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&combphy2 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_rgmii_bus
+ &gmac1m1_clkinout>;
+ snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+
+ tx_delay = <0x4f>;
+ rx_delay = <0x2d>;
+ phy-handle = <&rgmii_phy1>;
+ status = "okay";
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ };
+};
+
+&hdmi {
+ assigned-clocks = <&cru CLK_HDMI_CEC>;
+ assigned-clock-rates = <32768>;
+ avdd-0v9-supply = <&vdda_0v9>;
+ avdd-1v8-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&i2s0_8ch {
+ status = "okay";
+};
+
+&i2s1_8ch {
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wifi_32k: wifi-32k {
+ rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb_host_en: vcc5v0_usb_host_en {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc5v0_usb2_otg_en: vcc5v0_usb2_otg_en {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ };
+
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ led {
+ led_work_en: led_work_en {
+ rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ vmmc-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&spdif {
+ status = "okay";
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
+};
+
+&tsadc {
+ /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-mode = <1>;
+ /* tshut polarity 0:LOW 1:HIGH */
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
+ status = "okay";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&pmucru CLK_RTC_32K>;
+ clock-names = "ext_clock";
+ device-wake-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+ host-wake-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+ vbat-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcca_1v8>;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
+
+&vpu {
+ status = "okay";
+};
+
+&vdpu_mmu {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ vbus-supply = <&vcc5v0_usb2_otg>;
+ status = "okay";
+};
+
+&usb2phy1_host {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
index 9fd262334d77..61c7a3ad7387 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
@@ -82,6 +82,18 @@
vin-supply = <&usb_5v>;
};
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_enable_h>;
+ regulator-name = "vcc3v3_pcie";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
vcc3v3_sys: vcc3v3-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
@@ -122,6 +134,10 @@
status = "okay";
};
+&combphy2 {
+ status = "okay";
+};
+
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
@@ -443,6 +459,14 @@
};
};
+&pcie2x1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_reset_h>;
+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
@@ -464,6 +488,16 @@
};
};
+ pcie {
+ pcie_enable_h: pcie-enable-h {
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie_reset_h: pcie-reset-h {
+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
pmic_int: pmic_int {
rockchip,pins =
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts
new file mode 100644
index 000000000000..4e49bebf548b
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+#include "rk3566-soquartz.dtsi"
+
+/ {
+ model = "PINE64 RK3566 SOQuartz on Blade carrier board";
+ compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566";
+
+ /* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */
+ vcc3v0_sd: vcc3v0-sd-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v0_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ /* labeled VCC_SSD in schematic */
+ vcc3v3_pcie_p: vcc3v3-pcie-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie_p";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vbus>;
+ };
+
+ vcc5v_dcin: vcc5v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&combphy2 {
+ phy-supply = <&vcc3v3_sys>;
+ status = "okay";
+};
+
+&gmac1 {
+ status = "okay";
+};
+
+/*
+ * i2c1 is exposed on CM1 / Module1A
+ * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
+ * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
+ */
+&i2c1 {
+ status = "okay";
+
+};
+
+/*
+ * i2c2 is exposed on CM1 / Module1A - to PI40
+ * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
+ * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
+ */
+&i2c2 {
+ status = "disabled";
+};
+
+/*
+ * i2c3 is exposed on CM1 / Module1A - to PI40
+ * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
+ * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
+ */
+&i2c3 {
+ status = "disabled";
+};
+
+/*
+ * i2c4 is exposed on CM2 / Module1B - to PI40
+ * pin 45 - GPIO24 - i2c4_scl_m1
+ * pin 47 - GPIO23 - i2c4_sda_m1
+ */
+&i2c4 {
+ status = "disabled";
+};
+
+/*
+ * i2s1_8ch is exposed on CM1 / Module1A - to PI40
+ * pin 24 - GPIO26 - i2s1_sdi1_m1
+ * pin 25 - GPIO21 - i2s1_sdo0_m1
+ * pin 26 - GPIO19 - i2s1_lrck_tx_m1
+ * pin 27 - GPIO20 - i2s1_sdi0_m1
+ * pin 29 - GPIO16 - i2s1_sdi3_m1
+ * pin 30 - GPIO6 - i2s1_sdi2_m1
+ * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3
+ * pin 41 - GPIO25 - i2s1_sdo2_m1
+ * pin 49 - GPIO18 - i2s1_sclk_tx_m1
+ * pin 50 - GPIO17 - i2s1_mclk_m1
+ * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2
+ */
+&i2s1_8ch {
+ status = "disabled";
+};
+
+&led_diy {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ linux,default-trigger = "disk-activity";
+ status = "okay";
+};
+
+&led_work {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ linux,default-trigger = "heartbeat";
+ status = "okay";
+};
+
+&pcie2x1 {
+ vpcie3v3-supply = <&vcc3v3_pcie_p>;
+ status = "okay";
+};
+
+&rgmii_phy1 {
+ status = "okay";
+};
+
+/*
+ * saradc is exposed on CM1 / Module1A - to J2
+ * pin 94 - AIN1 - saradc_vin3
+ * pin 96 - AIN0 - saradc_vin2
+ */
+&saradc {
+ status = "disabled";
+};
+
+&sdmmc0 {
+ vmmc-supply = <&vcc3v0_sd>;
+ status = "okay";
+};
+
+/*
+ * spi3 is exposed on CM1 / Module1A - to PI40
+ * pin 37 - GPIO7 - spi3_cs1_m0
+ * pin 38 - GPIO11 - spi3_clk_m0
+ * pin 39 - GPIO8 - spi3_cs0_m0
+ * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch
+ * pin 44 - GPIO10 - spi3_mosi_m0
+ */
+&spi3 {
+ status = "disabled";
+};
+
+/*
+ * uart2 is exposed on CM1 / Module1A - to PI40
+ * pin 51 - GPIO15 - uart2_rx_m0
+ * pin 55 - GPIO14 - uart2_tx_m0
+ */
+&uart2 {
+ status = "okay";
+};
+
+/*
+ * uart7 is exposed on CM1 / Module1A - to PI40
+ * pin 46 - GPIO22 - uart7_tx_m2
+ * pin 47 - GPIO23 - uart7_rx_m2
+ */
+&uart7 {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vbus>;
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
+&vbus {
+ vin-supply = <&vcc5v_dcin>;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
index e00568a6be5c..263ce40770dd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
@@ -30,6 +30,12 @@
};
};
+/* phy for pcie */
+&combphy2 {
+ phy-supply = <&vcc3v3_sys>;
+ status = "okay";
+};
+
&gmac1 {
status = "okay";
};
@@ -105,6 +111,11 @@
status = "okay";
};
+&pcie2x1 {
+ vpcie3v3-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
&rgmii_phy1 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts
new file mode 100644
index 000000000000..2208dbfb7f0a
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-soquartz.dtsi"
+
+/ {
+ model = "PINE64 RK3566 SOQuartz on Model A carrier board";
+ compatible = "pine64,soquartz-model-a", "pine64,soquartz", "rockchip,rk3566";
+
+ /* labeled DCIN_12V in schematic */
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ /*
+ * Labelled VCC3V0_SD in schematic to not conflict with PMIC
+ * regulator, it's 3.3v in actuality
+ */
+ vcc3v0_sd: vcc3v0-sd-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v0_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc12v_pcie: vcc12v-pcie-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_pcie";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+};
+
+/* phy for pcie */
+&combphy2 {
+ phy-supply = <&vcc3v3_sys>;
+ status = "okay";
+};
+
+&gmac1 {
+ status = "okay";
+};
+
+/*
+ * i2c1 is exposed on CM1 / Module1A
+ * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
+ * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
+ */
+&i2c1 {
+ status = "okay";
+
+ /*
+ * the rtc interrupt is tied to PMIC_PWRON,
+ * it will force reset the board if triggered.
+ */
+ pcf85063: rtc@51 {
+ compatible = "nxp,pcf85063";
+ reg = <0x51>;
+ };
+};
+
+/*
+ * i2c2 is exposed on CM1 / Module1A - to PI40
+ * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
+ * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
+ */
+&i2c2 {
+ status = "disabled";
+};
+
+/*
+ * i2c3 is exposed on CM1 / Module1A - to PI40
+ * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
+ * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
+ */
+&i2c3 {
+ status = "disabled";
+};
+
+/*
+ * i2c4 is exposed on CM2 / Module1B - to PI40
+ * pin 45 - GPIO24 - i2c4_scl_m1
+ * pin 47 - GPIO23 - i2c4_sda_m1
+ */
+&i2c4 {
+ status = "disabled";
+};
+
+/*
+ * i2s1_8ch is exposed on CM1 / Module1A - to PI40
+ * pin 24 - GPIO26 - i2s1_sdi1_m1
+ * pin 25 - GPIO21 - i2s1_sdo0_m1
+ * pin 26 - GPIO19 - i2s1_lrck_tx_m1
+ * pin 27 - GPIO20 - i2s1_sdi0_m1
+ * pin 29 - GPIO16 - i2s1_sdi3_m1
+ * pin 30 - GPIO6 - i2s1_sdi2_m1
+ * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3
+ * pin 41 - GPIO25 - i2s1_sdo2_m1
+ * pin 49 - GPIO18 - i2s1_sclk_tx_m1
+ * pin 50 - GPIO17 - i2s1_mclk_m1
+ * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2
+ */
+&i2s1_8ch {
+ status = "disabled";
+};
+
+&led_diy {
+ status = "okay";
+};
+
+&led_work {
+ status = "okay";
+};
+
+&pcie2x1 {
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
+&rgmii_phy1 {
+ status = "okay";
+};
+
+&rgmii_phy1 {
+ status = "okay";
+};
+
+/*
+ * saradc is exposed on CM1 / Module1A - to J2
+ * pin 94 - AIN1 - saradc_vin3
+ * pin 96 - AIN0 - saradc_vin2
+ */
+&saradc {
+ status = "disabled";
+};
+
+/*
+ * vmmc-supply is vcc3v3_sd on v1.0 and vcc3v0_sd on v1.1+
+ * the soquartz SoM has SDMMC_PWR (CM1 pin 75) hardwired to vcc3v3_sys,
+ * so we use vcc3v3_sd here to ensure the regulator is enabled on older boards.
+ */
+&sdmmc0 {
+ vmmc-supply = <&vcc3v3_sd>;
+ status = "okay";
+};
+
+/*
+ * spi3 is exposed on CM1 / Module1A - to PI40
+ * pin 37 - GPIO7 - spi3_cs1_m0
+ * pin 38 - GPIO11 - spi3_clk_m0
+ * pin 39 - GPIO8 - spi3_cs0_m0
+ * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch
+ * pin 44 - GPIO10 - spi3_mosi_m0
+ */
+&spi3 {
+ status = "disabled";
+};
+
+/*
+ * uart2 is exposed on CM1 / Module1A - to PI40
+ * pin 51 - GPIO15 - uart2_rx_m0
+ * pin 55 - GPIO14 - uart2_tx_m0
+ */
+&uart2 {
+ status = "okay";
+};
+
+/*
+ * uart7 is exposed on CM1 / Module1A - to PI40
+ * pin 46 - GPIO22 - uart7_tx_m2
+ * pin 47 - GPIO23 - uart7_rx_m2
+ */
+&uart7 {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_usb>;
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
+&vbus {
+ vin-supply = <&vcc5v0_usb>;
+};
+
+&vcc3v3_sd {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
index 5bcd4be32964..ce7165d7f1a1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3566.dtsi"
/ {
@@ -28,6 +29,17 @@
#clock-cells = <0>;
};
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -143,6 +155,33 @@
status = "disabled";
};
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ avdd-0v9-supply = <&vdda0v9_image>;
+ avdd-1v8-supply = <&vcca1v8_image>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
@@ -411,6 +450,10 @@
status = "disabled";
};
+&i2s0_8ch {
+ status = "okay";
+};
+
/*
* i2s1_8ch is exposed on CM1 / Module1A
* pin 24 - i2s1_sdi1_m1
@@ -444,6 +487,12 @@
};
};
+&pcie2x1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_reset_h>;
+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+};
+
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
@@ -469,6 +518,15 @@
};
};
+ pcie {
+ pcie_clkreq_h: pcie-clkreq-h {
+ rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ pcie_reset_h: pcie-reset-h {
+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -614,3 +672,20 @@
&usb_host0_xhci {
status = "disabled";
};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
new file mode 100644
index 000000000000..59ecf868dbd0
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
@@ -0,0 +1,744 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Hardkernel Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+ model = "Hardkernel ODROID-M1";
+ compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac0;
+ i2c0 = &i2c3;
+ i2c3 = &i2c0;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
+ serial0 = &uart1;
+ serial1 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ dc_12v: dc-12v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_receiver_pin>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_power: led-0 {
+ gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_RED>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_power_pin>;
+ };
+ led_work: led-1 {
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_BLUE>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_work_pin>;
+ };
+ };
+
+ rk809-sound {
+ compatible = "simple-audio-card";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_det_pin>;
+ simple-audio-card,name = "Analog RK817";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets =
+ "Headphone", "Headphones",
+ "Speaker", "Speaker";
+ simple-audio-card,routing =
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "Speaker", "SPKO";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&rk809>;
+ };
+ };
+
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie";
+ enable-active-high;
+ gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc3v3_pcie_en_pin>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_usb_host: vcc5v0-usb-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb_host";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_host_en_pin>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb_otg";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_otg_en_pin>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy0 {
+ /* Used for USB3 */
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&combphy1 {
+ /* Used for USB3 */
+ phy-supply = <&vcc5v0_usb_otg>;
+ status = "okay";
+};
+
+&combphy2 {
+ /* used for SATA */
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac0 {
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+ assigned-clock-rates = <0>, <125000000>;
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy0>;
+ phy-mode = "rgmii";
+ phy-supply = <&vcc3v3_sys>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus>;
+ status = "okay";
+
+ tx_delay = <0x4f>;
+ rx_delay = <0x2d>;
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ avdd-0v9-supply = <&vdda0v9_image>;
+ avdd-1v8-supply = <&vcca1v8_image>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc3v3_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+ #clock-cells = <1>;
+ clock-names = "mclk";
+ clocks = <&cru I2S1_MCLKOUT_TX>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
+ rockchip,system-power-controller;
+ #sound-dai-cells = <0>;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-always-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2s0_8ch {
+ status = "okay";
+};
+
+&i2s1_8ch {
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+&mdio0 {
+ rgmii_phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_reset_pin>;
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
+&pinctrl {
+ fspi {
+ fspi_dual_io_pins: fspi-dual-io-pins {
+ rockchip,pins =
+ /* fspi_clk */
+ <1 RK_PD0 1 &pcfg_pull_none>,
+ /* fspi_cs0n */
+ <1 RK_PD3 1 &pcfg_pull_none>,
+ /* fspi_d0 */
+ <1 RK_PD1 1 &pcfg_pull_none>,
+ /* fspi_d1 */
+ <1 RK_PD2 1 &pcfg_pull_none>;
+ };
+ };
+
+ ir-receiver {
+ ir_receiver_pin: ir-receiver-pin {
+ /* external pullup to VCC3V3_SYS */
+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ led_power_pin: led-power-pin {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ led_work_pin: led-work-pin {
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ pcie_reset_pin: pcie-reset-pin {
+ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin {
+ rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ rk809 {
+ hp_det_pin: hp-det-pin {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ vcc5v0_usb_otg_en_pin: vcc5v0-usb-dr-en-pin {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_3v3>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ sd-uhs-sdr50;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&sfc {
+ /* Dual I/O mode as the D2 pin conflicts with the eMMC */
+ pinctrl-0 = <&fspi_dual_io_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "SPL";
+ reg = <0x0 0xe0000>;
+ };
+ partition@e0000 {
+ label = "U-Boot Env";
+ reg = <0xe0000 0x20000>;
+ };
+ partition@100000 {
+ label = "U-Boot";
+ reg = <0x100000 0x200000>;
+ };
+ partition@300000 {
+ label = "splash";
+ reg = <0x300000 0x100000>;
+ };
+ partition@400000 {
+ label = "Filesystem";
+ reg = <0x400000 0xc00000>;
+ };
+ };
+ };
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_usb_otg>;
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb2phy1_host {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
index 539ef8cc7792..a1c5fdf7d68f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
@@ -32,6 +32,13 @@
};
};
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
leds {
compatible = "gpio-leds";
@@ -60,13 +67,55 @@
};
};
- vcc12v_dcin: vcc12v-dcin {
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable>;
+ post-power-on-delay-ms = <100>;
+ power-off-delay-us = <5000000>;
+ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
};
+ pcie30_avdd0v9: pcie30-avdd0v9-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ /* pi6c pcie clock generator */
+ vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pi6c_03";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -79,7 +128,7 @@
vin-supply = <&vcc5v0_sys>;
};
- vcc3v3_sys: vcc3v3-sys {
+ vcc3v3_sys: vcc3v3-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
@@ -89,7 +138,7 @@
vin-supply = <&vcc12v_dcin>;
};
- vcc5v0_sys: vcc5v0-sys {
+ vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
@@ -99,7 +148,7 @@
vin-supply = <&vcc12v_dcin>;
};
- vcc5v0_usb: vcc5v0-usb {
+ vcc5v0_usb: vcc5v0-usb-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
regulator-always-on;
@@ -109,7 +158,7 @@
vin-supply = <&vcc12v_dcin>;
};
- vcc5v0_usb_host: vcc5v0-usb-host {
+ vcc5v0_usb_host: vcc5v0-usb-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
@@ -144,7 +193,7 @@
vin-supply = <&vcc5v0_usb>;
};
- vcc_cam: vcc-cam {
+ vcc_cam: vcc-cam-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
@@ -160,7 +209,7 @@
};
};
- vcc_mipi: vcc-mipi {
+ vcc_mipi: vcc-mipi-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
@@ -207,16 +256,17 @@
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
- assigned-clock-rates = <0>, <125000000>;
- clock_in_out = "output";
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
+ clock_in_out = "input";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
+ &gmac1m1_clkinout
&gmac1m1_rgmii_bus>;
status = "okay";
};
@@ -525,6 +575,11 @@
status = "okay";
};
+&i2s2_2ch {
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
@@ -545,6 +600,19 @@
status = "okay";
};
+&pcie30phy {
+ phy-supply = <&vcc3v3_pi6c_03>;
+ status = "okay";
+};
+
+&pcie3x2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie30x2m1_pins>;
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
&pinctrl {
cam {
vcc_cam_en: vcc_cam_en {
@@ -604,6 +672,26 @@
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ bt {
+ bt_enable: bt-enable {
+ rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake: bt-host-wake {
+ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bt_wake: bt-wake {
+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable: wifi-enable {
+ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&pmu_io_domains {
@@ -648,12 +736,50 @@
status = "okay";
};
+&sdmmc2 {
+ supports-sdio;
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rk809 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>;
+ vbat-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc_1v8>;
+ /* vddio comes from regulator on module, use IO bank voltage instead */
+ };
+};
+
&uart2 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 164708f1eb67..5706c3e24f0a 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -1049,20 +1049,6 @@
status = "disabled";
};
- spdif: spdif@fe460000 {
- compatible = "rockchip,rk3568-spdif";
- reg = <0x0 0xfe460000 0x0 0x1000>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "mclk", "hclk";
- clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
- dmas = <&dmac1 1>;
- dma-names = "tx";
- pinctrl-names = "default";
- pinctrl-0 = <&spdifm0_tx>;
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
i2s0_8ch: i2s@fe400000 {
compatible = "rockchip,rk3568-i2s-tdm";
reg = <0x0 0xfe400000 0x0 0x1000>;
@@ -1105,6 +1091,28 @@
status = "disabled";
};
+ i2s2_2ch: i2s@fe420000 {
+ compatible = "rockchip,rk3568-i2s-tdm";
+ reg = <0x0 0xfe420000 0x0 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
+ assigned-clock-rates = <1188000000>;
+ clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
+ dmas = <&dmac1 4>, <&dmac1 5>;
+ dma-names = "tx", "rx";
+ resets = <&cru SRST_M_I2S2_2CH>;
+ reset-names = "m";
+ rockchip,grf = <&grf>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s2m0_sclktx
+ &i2s2m0_lrcktx
+ &i2s2m0_sdi
+ &i2s2m0_sdo>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
i2s3_2ch: i2s@fe430000 {
compatible = "rockchip,rk3568-i2s-tdm";
reg = <0x0 0xfe430000 0x0 0x1000>;
@@ -1142,6 +1150,20 @@
status = "disabled";
};
+ spdif: spdif@fe460000 {
+ compatible = "rockchip,rk3568-spdif";
+ reg = <0x0 0xfe460000 0x0 0x1000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "mclk", "hclk";
+ clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
+ dmas = <&dmac1 1>;
+ dma-names = "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdifm0_tx>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
dmac0: dma-controller@fe530000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xfe530000 0x0 0x4000>;
diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
index d0abb9aa0e9e..e3852c946352 100644
--- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
@@ -55,14 +55,14 @@
samsung,pins = "gpf5-0";
samsung,pin-function = <FSD_PIN_FUNC_2>;
samsung,pin-pud = <FSD_PIN_PULL_NONE>;
- samsung,pin-drv = <FSD_PIN_DRV_LV2>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
ufs_refclk_out: ufs-refclk-out-pins {
samsung,pins = "gpf5-1";
samsung,pin-function = <FSD_PIN_FUNC_2>;
samsung,pin-pud = <FSD_PIN_PULL_NONE>;
- samsung,pin-drv = <FSD_PIN_DRV_LV2>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
};
@@ -239,105 +239,105 @@
samsung,pins = "gpb6-1";
samsung,pin-function = <FSD_PIN_FUNC_2>;
samsung,pin-pud = <FSD_PIN_PULL_UP>;
- samsung,pin-drv = <FSD_PIN_DRV_LV2>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
pwm1_out: pwm1-out-pins {
samsung,pins = "gpb6-5";
samsung,pin-function = <FSD_PIN_FUNC_2>;
samsung,pin-pud = <FSD_PIN_PULL_UP>;
- samsung,pin-drv = <FSD_PIN_DRV_LV2>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
hs_i2c0_bus: hs-i2c0-bus-pins {
samsung,pins = "gpb0-0", "gpb0-1";
samsung,pin-function = <FSD_PIN_FUNC_2>;
samsung,pin-pud = <FSD_PIN_PULL_UP>;
- samsung,pin-drv = <FSD_PIN_DRV_LV1>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
hs_i2c1_bus: hs-i2c1-bus-pins {
samsung,pins = "gpb0-2", "gpb0-3";
samsung,pin-function = <FSD_PIN_FUNC_2>;
samsung,pin-pud = <FSD_PIN_PULL_UP>;
- samsung,pin-drv = <FSD_PIN_DRV_LV1>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
hs_i2c2_bus: hs-i2c2-bus-pins {
samsung,pins = "gpb0-4", "gpb0-5";
samsung,pin-function = <FSD_PIN_FUNC_2>;
samsung,pin-pud = <FSD_PIN_PULL_UP>;
- samsung,pin-drv = <FSD_PIN_DRV_LV1>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
hs_i2c3_bus: hs-i2c3-bus-pins {
samsung,pins = "gpb0-6", "gpb0-7";
samsung,pin-function = <FSD_PIN_FUNC_2>;
samsung,pin-pud = <FSD_PIN_PULL_UP>;
- samsung,pin-drv = <FSD_PIN_DRV_LV1>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
hs_i2c4_bus: hs-i2c4-bus-pins {
samsung,pins = "gpb1-0", "gpb1-1";
samsung,pin-function = <FSD_PIN_FUNC_2>;
samsung,pin-pud = <FSD_PIN_PULL_UP>;
- samsung,pin-drv = <FSD_PIN_DRV_LV1>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
hs_i2c5_bus: hs-i2c5-bus-pins {
samsung,pins = "gpb1-2", "gpb1-3";
samsung,pin-function = <FSD_PIN_FUNC_2>;
samsung,pin-pud = <FSD_PIN_PULL_UP>;
- samsung,pin-drv = <FSD_PIN_DRV_LV1>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
hs_i2c6_bus: hs-i2c6-bus-pins {
samsung,pins = "gpb1-4", "gpb1-5";
samsung,pin-function = <FSD_PIN_FUNC_2>;
samsung,pin-pud = <FSD_PIN_PULL_UP>;
- samsung,pin-drv = <FSD_PIN_DRV_LV1>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
hs_i2c7_bus: hs-i2c7-bus-pins {
samsung,pins = "gpb1-6", "gpb1-7";
samsung,pin-function = <FSD_PIN_FUNC_2>;
samsung,pin-pud = <FSD_PIN_PULL_UP>;
- samsung,pin-drv = <FSD_PIN_DRV_LV1>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
uart0_data: uart0-data-pins {
samsung,pins = "gpb7-0", "gpb7-1";
samsung,pin-function = <FSD_PIN_FUNC_2>;
samsung,pin-pud = <FSD_PIN_PULL_NONE>;
- samsung,pin-drv = <FSD_PIN_DRV_LV1>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
uart1_data: uart1-data-pins {
samsung,pins = "gpb7-4", "gpb7-5";
samsung,pin-function = <FSD_PIN_FUNC_2>;
samsung,pin-pud = <FSD_PIN_PULL_NONE>;
- samsung,pin-drv = <FSD_PIN_DRV_LV1>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
spi0_bus: spi0-bus-pins {
samsung,pins = "gpb4-0", "gpb4-2", "gpb4-3";
samsung,pin-function = <FSD_PIN_FUNC_2>;
samsung,pin-pud = <FSD_PIN_PULL_UP>;
- samsung,pin-drv = <FSD_PIN_DRV_LV1>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
spi1_bus: spi1-bus-pins {
samsung,pins = "gpb4-4", "gpb4-6", "gpb4-7";
samsung,pin-function = <FSD_PIN_FUNC_2>;
samsung,pin-pud = <FSD_PIN_PULL_UP>;
- samsung,pin-drv = <FSD_PIN_DRV_LV1>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
spi2_bus: spi2-bus-pins {
samsung,pins = "gpb5-0", "gpb5-2", "gpb5-3";
samsung,pin-function = <FSD_PIN_FUNC_2>;
samsung,pin-pud = <FSD_PIN_PULL_UP>;
- samsung,pin-drv = <FSD_PIN_DRV_LV1>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
};
diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.h b/arch/arm64/boot/dts/tesla/fsd-pinctrl.h
index 6ffbda362493..c397d02208a0 100644
--- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.h
+++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.h
@@ -16,9 +16,9 @@
#define FSD_PIN_PULL_UP 3
#define FSD_PIN_DRV_LV1 0
-#define FSD_PIN_DRV_LV2 2
-#define FSD_PIN_DRV_LV3 1
-#define FSD_PIN_DRV_LV4 3
+#define FSD_PIN_DRV_LV2 1
+#define FSD_PIN_DRV_LV4 2
+#define FSD_PIN_DRV_LV6 3
#define FSD_PIN_FUNC_INPUT 0
#define FSD_PIN_FUNC_OUTPUT 1
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 4555a5be2257..cf7c509538a4 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
index 03660476364f..072903649d6e 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
@@ -192,6 +192,102 @@
pinctrl-single,function-mask = <0xffffffff>;
};
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 36 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 36 2>;
+ assigned-clock-parents = <&k3_clks 36 3>;
+ power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 37 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 37 2>;
+ assigned-clock-parents = <&k3_clks 37 3>;
+ power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 38 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 38 2>;
+ assigned-clock-parents = <&k3_clks 38 3>;
+ power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 39 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 39 2>;
+ assigned-clock-parents = <&k3_clks 39 3>;
+ power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 40 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 40 2>;
+ assigned-clock-parents = <&k3_clks 40 3>;
+ power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 41 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 41 2>;
+ assigned-clock-parents = <&k3_clks 41 3>;
+ power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 42 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 42 2>;
+ assigned-clock-parents = <&k3_clks 42 3>;
+ power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 43 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 43 2>;
+ assigned-clock-parents = <&k3_clks 43 3>;
+ power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
@@ -199,6 +295,7 @@
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart1: serial@2810000 {
@@ -208,6 +305,7 @@
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 152 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart2: serial@2820000 {
@@ -217,6 +315,7 @@
power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 153 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart3: serial@2830000 {
@@ -226,6 +325,7 @@
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 154 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart4: serial@2840000 {
@@ -235,6 +335,7 @@
power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 155 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart5: serial@2850000 {
@@ -244,6 +345,7 @@
power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 156 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart6: serial@2860000 {
@@ -253,6 +355,7 @@
power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 158 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_i2c0: i2c@20000000 {
@@ -264,6 +367,7 @@
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 102 2>;
clock-names = "fck";
+ status = "disabled";
};
main_i2c1: i2c@20010000 {
@@ -275,6 +379,7 @@
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 103 2>;
clock-names = "fck";
+ status = "disabled";
};
main_i2c2: i2c@20020000 {
@@ -286,6 +391,7 @@
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 104 2>;
clock-names = "fck";
+ status = "disabled";
};
main_i2c3: i2c@20030000 {
@@ -297,6 +403,7 @@
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 105 2>;
clock-names = "fck";
+ status = "disabled";
};
main_spi0: spi@20100000 {
@@ -307,6 +414,7 @@
#size-cells = <0>;
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 172 0>;
+ status = "disabled";
};
main_spi1: spi@20110000 {
@@ -317,6 +425,7 @@
#size-cells = <0>;
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 173 0>;
+ status = "disabled";
};
main_spi2: spi@20120000 {
@@ -327,6 +436,7 @@
#size-cells = <0>;
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 174 0>;
+ status = "disabled";
};
main_gpio_intr: interrupt-controller@a00000 {
@@ -393,6 +503,7 @@
ti,otap-del-sel-mmc-hs = <0x0>;
ti,otap-del-sel-ddr52 = <0x9>;
ti,otap-del-sel-hs200 = <0x6>;
+ status = "disabled";
};
sdhci1: mmc@fa00000 {
@@ -416,6 +527,7 @@
ti,itap-del-sel-sdr25 = <0x0>;
ti,clkbuf-sel = <0x7>;
bus-width = <4>;
+ status = "disabled";
};
sdhci2: mmc@fa20000 {
@@ -438,6 +550,7 @@
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
ti,clkbuf-sel = <0x7>;
+ status = "disabled";
};
fss: bus@fc00000 {
@@ -462,6 +575,7 @@
power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
};
@@ -520,6 +634,7 @@
clocks = <&k3_clks 13 0>;
clock-names = "fck";
bus_freq = <1000000>;
+ status = "disabled";
};
cpts@3d000 {
@@ -557,6 +672,7 @@
power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 51 0>;
clock-names = "fck";
+ status = "disabled";
};
ecap1: pwm@23110000 {
@@ -566,6 +682,7 @@
power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 52 0>;
clock-names = "fck";
+ status = "disabled";
};
ecap2: pwm@23120000 {
@@ -575,6 +692,7 @@
power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 53 0>;
clock-names = "fck";
+ status = "disabled";
};
main_mcan0: can@20701000 {
@@ -589,6 +707,7 @@
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
epwm0: pwm@23000000 {
@@ -598,6 +717,7 @@
power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
epwm1: pwm@23010000 {
@@ -607,6 +727,7 @@
power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
epwm2: pwm@23020000 {
@@ -616,5 +737,6 @@
power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi
index f56c803560f2..a427231527c3 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi
@@ -14,6 +14,51 @@
pinctrl-single,function-mask = <0xffffffff>;
};
+ /*
+ * The MCU domain timer interrupts are routed only to the ESM module,
+ * and not currently available for Linux. The MCU domain timers are
+ * of limited use without interrupts, and likely reserved by the ESM.
+ */
+ mcu_timer0: timer@4800000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4800000 0x00 0x400>;
+ clocks = <&k3_clks 35 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer1: timer@4810000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4810000 0x00 0x400>;
+ clocks = <&k3_clks 48 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer2: timer@4820000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4820000 0x00 0x400>;
+ clocks = <&k3_clks 49 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer3: timer@4830000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4830000 0x00 0x400>;
+ clocks = <&k3_clks 50 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
@@ -21,6 +66,7 @@
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 0>;
clock-names = "fclk";
+ status = "disabled";
};
mcu_i2c0: i2c@4900000 {
@@ -32,6 +78,7 @@
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 106 2>;
clock-names = "fck";
+ status = "disabled";
};
mcu_spi0: spi@4b00000 {
@@ -42,6 +89,7 @@
#size-cells = <0>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 147 0>;
+ status = "disabled";
};
mcu_spi1: spi@4b10000 {
@@ -52,6 +100,7 @@
#size-cells = <0>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 148 0>;
+ status = "disabled";
};
mcu_gpio_intr: interrupt-controller@4210000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
index 4090134676cf..38dced6b4fef 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
@@ -26,16 +26,18 @@
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "fclk";
+ status = "disabled";
};
wkup_i2c0: i2c@2b200000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x02b200000 0x00 0x100>;
+ reg = <0x00 0x2b200000 0x00 0x100>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 107 4>;
clock-names = "fck";
+ status = "disabled";
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts
index 93a5f0817efc..18ca56cedc63 100644
--- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts
@@ -282,11 +282,8 @@
status = "reserved";
};
-&mcu_uart0 {
- status = "disabled";
-};
-
&main_uart0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
@@ -296,41 +293,15 @@
status = "reserved";
};
-&main_uart2 {
- status = "disabled";
-};
-
-&main_uart3 {
- status = "disabled";
-};
-
-&main_uart4 {
- status = "disabled";
-};
-
-&main_uart5 {
- status = "disabled";
-};
-
-&main_uart6 {
- status = "disabled";
-};
-
-&mcu_i2c0 {
- status = "disabled";
-};
-
-&wkup_i2c0 {
- status = "disabled";
-};
-
&main_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
};
&main_i2c1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
@@ -363,15 +334,8 @@
};
};
-&main_i2c2 {
- status = "disabled";
-};
-
-&main_i2c3 {
- status = "disabled";
-};
-
&sdhci0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
ti,driver-strength-ohm = <50>;
@@ -380,6 +344,7 @@
&sdhci1 {
/* SD/MMC */
+ status = "okay";
vmmc-supply = <&vdd_mmc1>;
vqmmc-supply = <&vdd_sd_dv>;
pinctrl-names = "default";
@@ -390,8 +355,7 @@
&cpsw3g {
pinctrl-names = "default";
- pinctrl-0 = <&main_mdio1_pins_default
- &main_rgmii1_pins_default
+ pinctrl-0 = <&main_rgmii1_pins_default
&main_rgmii2_pins_default>;
};
@@ -406,6 +370,10 @@
};
&cpsw3g_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mdio1_pins_default>;
+
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
@@ -429,6 +397,7 @@
};
&ospi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
@@ -486,31 +455,3 @@
};
};
};
-
-&ecap0 {
- status = "disabled";
-};
-
-&ecap1 {
- status = "disabled";
-};
-
-&ecap2 {
- status = "disabled";
-};
-
-&main_mcan0 {
- status = "disabled";
-};
-
-&epwm0 {
- status = "disabled";
-};
-
-&epwm1 {
- status = "disabled";
-};
-
-&epwm2 {
- status = "disabled";
-};
diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
index 99afac40e8d4..81d984414fd4 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
@@ -31,7 +31,7 @@
wkup_i2c0: i2c@2b200000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x02b200000 0x00 0x100>;
+ reg = <0x00 0x2b200000 0x00 0x100>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index d6aa23681bbe..5e8036f32d79 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -237,6 +237,7 @@
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart1: serial@2810000 {
@@ -248,6 +249,7 @@
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 152 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart2: serial@2820000 {
@@ -259,6 +261,7 @@
power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 153 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart3: serial@2830000 {
@@ -270,6 +273,7 @@
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 154 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart4: serial@2840000 {
@@ -281,6 +285,7 @@
power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 155 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart5: serial@2850000 {
@@ -292,6 +297,7 @@
power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 156 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart6: serial@2860000 {
@@ -303,6 +309,7 @@
power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 158 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_i2c0: i2c@20000000 {
@@ -314,6 +321,7 @@
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 102 2>;
clock-names = "fck";
+ status = "disabled";
};
main_i2c1: i2c@20010000 {
@@ -325,6 +333,7 @@
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 103 2>;
clock-names = "fck";
+ status = "disabled";
};
main_i2c2: i2c@20020000 {
@@ -336,6 +345,7 @@
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 104 2>;
clock-names = "fck";
+ status = "disabled";
};
main_i2c3: i2c@20030000 {
@@ -347,6 +357,7 @@
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 105 2>;
clock-names = "fck";
+ status = "disabled";
};
main_spi0: spi@20100000 {
@@ -359,6 +370,7 @@
clocks = <&k3_clks 141 0>;
dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
dma-names = "tx0", "rx0";
+ status = "disabled";
};
main_spi1: spi@20110000 {
@@ -369,6 +381,7 @@
#size-cells = <0>;
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 142 0>;
+ status = "disabled";
};
main_spi2: spi@20120000 {
@@ -379,6 +392,7 @@
#size-cells = <0>;
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 143 0>;
+ status = "disabled";
};
main_spi3: spi@20130000 {
@@ -389,6 +403,7 @@
#size-cells = <0>;
power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 144 0>;
+ status = "disabled";
};
main_spi4: spi@20140000 {
@@ -399,6 +414,7 @@
#size-cells = <0>;
power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 145 0>;
+ status = "disabled";
};
main_gpio_intr: interrupt-controller@a00000 {
@@ -536,6 +552,7 @@
clocks = <&k3_clks 13 0>;
clock-names = "fck";
bus_freq = <1000000>;
+ status = "disabled";
};
cpts@3d000 {
@@ -612,7 +629,7 @@
assigned-clocks = <&k3_clks 0 0>;
assigned-clock-parents = <&k3_clks 0 3>;
assigned-clock-rates = <60000000>;
- clock-names = "adc_tsc_fck";
+ clock-names = "fck";
adc {
#io-channel-cells = <1>;
@@ -855,6 +872,7 @@
ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
<0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
+ status = "disabled";
};
pcie0_ep: pcie-ep@f102000 {
@@ -873,6 +891,7 @@
clocks = <&k3_clks 114 0>;
clock-names = "fck";
max-functions = /bits/ 8 <1>;
+ status = "disabled";
};
epwm0: pwm@23000000 {
@@ -882,6 +901,7 @@
power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
epwm1: pwm@23010000 {
@@ -891,6 +911,7 @@
power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
epwm2: pwm@23020000 {
@@ -900,6 +921,7 @@
power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
epwm3: pwm@23030000 {
@@ -909,6 +931,7 @@
power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
epwm4: pwm@23040000 {
@@ -918,6 +941,7 @@
power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
epwm5: pwm@23050000 {
@@ -927,6 +951,7 @@
power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
epwm6: pwm@23060000 {
@@ -936,6 +961,7 @@
power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
epwm7: pwm@23070000 {
@@ -945,6 +971,7 @@
power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
epwm8: pwm@23080000 {
@@ -954,6 +981,7 @@
power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>;
clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ecap0: pwm@23100000 {
@@ -963,6 +991,7 @@
power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 51 0>;
clock-names = "fck";
+ status = "disabled";
};
ecap1: pwm@23110000 {
@@ -972,6 +1001,7 @@
power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 52 0>;
clock-names = "fck";
+ status = "disabled";
};
ecap2: pwm@23120000 {
@@ -981,6 +1011,7 @@
power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 53 0>;
clock-names = "fck";
+ status = "disabled";
};
main_rti0: watchdog@e000000 {
@@ -1138,6 +1169,7 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
@@ -1278,6 +1310,7 @@
clocks = <&k3_clks 82 0>;
clock-names = "fck";
bus_freq = <1000000>;
+ status = "disabled";
};
};
@@ -1293,6 +1326,7 @@
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan1: can@20711000 {
@@ -1307,6 +1341,7 @@
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
crypto: crypto@40900000 {
@@ -1324,7 +1359,6 @@
compatible = "inside-secure,safexcel-eip76";
reg = <0x00 0x40910000 0x00 0x7d>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 133 1>;
status = "disabled"; /* Used by OP-TEE */
};
};
@@ -1334,8 +1368,8 @@
power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 80 0>;
clock-names = "fck";
- reg = <0x00 0x03b000000 0x00 0x400>,
- <0x00 0x050000000 0x00 0x8000000>;
+ reg = <0x00 0x3b000000 0x00 0x400>,
+ <0x00 0x50000000 0x00 0x8000000>;
reg-names = "cfg", "data";
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
gpmc,num-cs = <3>;
@@ -1346,6 +1380,7 @@
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
+ status = "disabled";
};
elm0: ecc@25010000 {
@@ -1355,5 +1390,6 @@
power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 54 0>;
clock-names = "fck";
+ status = "disabled";
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
index 02d4285acbb8..38ddf0b3b8a0 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
@@ -14,6 +14,7 @@
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 0>;
clock-names = "fclk";
+ status = "disabled";
};
mcu_uart1: serial@4a10000 {
@@ -24,6 +25,7 @@
power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 160 0>;
clock-names = "fclk";
+ status = "disabled";
};
mcu_i2c0: i2c@4900000 {
@@ -35,6 +37,7 @@
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 106 2>;
clock-names = "fck";
+ status = "disabled";
};
mcu_i2c1: i2c@4910000 {
@@ -46,6 +49,7 @@
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 107 2>;
clock-names = "fck";
+ status = "disabled";
};
mcu_spi0: spi@4b00000 {
@@ -56,6 +60,7 @@
#size-cells = <0>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 147 0>;
+ status = "disabled";
};
mcu_spi1: spi@4b10000 {
@@ -66,6 +71,7 @@
#size-cells = <0>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 148 0>;
+ status = "disabled";
};
mcu_gpio_intr: interrupt-controller@4210000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 5cf913860f80..39feea78a084 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -325,6 +325,7 @@
};
&main_uart0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
@@ -334,35 +335,8 @@
status = "reserved";
};
-&main_uart2 {
- status = "disabled";
-};
-
-&main_uart3 {
- status = "disabled";
-};
-
-&main_uart4 {
- status = "disabled";
-};
-
-&main_uart5 {
- status = "disabled";
-};
-
-&main_uart6 {
- status = "disabled";
-};
-
-&mcu_uart0 {
- status = "disabled";
-};
-
-&mcu_uart1 {
- status = "disabled";
-};
-
&main_i2c1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
@@ -405,23 +379,8 @@
status = "reserved";
};
-&mcu_i2c0 {
- status = "disabled";
-};
-
-&mcu_i2c1 {
- status = "disabled";
-};
-
-&mcu_spi0 {
- status = "disabled";
-};
-
-&mcu_spi1 {
- status = "disabled";
-};
-
&main_spi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_spi0_pins_default>;
ti,pindir-d0-out-d1-in;
@@ -466,8 +425,7 @@
&cpsw3g {
pinctrl-names = "default";
- pinctrl-0 = <&mdio1_pins_default
- &rgmii1_pins_default
+ pinctrl-0 = <&rgmii1_pins_default
&rgmii2_pins_default>;
};
@@ -482,6 +440,10 @@
};
&cpsw3g_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio1_pins_default>;
+
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
@@ -594,6 +556,7 @@
};
&pcie0_rc {
+ status = "okay";
reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
@@ -604,83 +567,25 @@
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
- status = "disabled";
};
&ecap0 {
+ status = "okay";
/* PWM is available on Pin 1 of header J12 */
pinctrl-names = "default";
pinctrl-0 = <&main_ecap0_pins_default>;
};
-&ecap1 {
- status = "disabled";
-};
-
-&ecap2 {
- status = "disabled";
-};
-
-&epwm0 {
- status = "disabled";
-};
-
-&epwm1 {
- status = "disabled";
-};
-
-&epwm2 {
- status = "disabled";
-};
-
-&epwm3 {
- status = "disabled";
-};
-
-&epwm4 {
- status = "disabled";
-};
-
-&epwm5 {
- status = "disabled";
-};
-
-&epwm6 {
- status = "disabled";
-};
-
-&epwm7 {
- status = "disabled";
-};
-
-&epwm8 {
- status = "disabled";
-};
-
-&icssg0_mdio {
- status = "disabled";
-};
-
-&icssg1_mdio {
- status = "disabled";
-};
-
&main_mcan0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mcan0_pins_default>;
phys = <&transceiver1>;
};
&main_mcan1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mcan1_pins_default>;
phys = <&transceiver2>;
};
-
-&gpmc0 {
- status = "disabled";
-};
-
-&elm0 {
- status = "disabled";
-};
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 738d0cf6c40a..2e2d40da360a 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -338,15 +338,8 @@
};
};
-&mcu_uart0 {
- status = "disabled";
-};
-
-&mcu_uart1 {
- status = "disabled";
-};
-
&main_uart0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
@@ -356,35 +349,8 @@
status = "reserved";
};
-&main_uart2 {
- status = "disabled";
-};
-
-&main_uart3 {
- status = "disabled";
-};
-
-&main_uart4 {
- status = "disabled";
-};
-
-&main_uart5 {
- status = "disabled";
-};
-
-&main_uart6 {
- status = "disabled";
-};
-
-&mcu_i2c0 {
- status = "disabled";
-};
-
-&mcu_i2c1 {
- status = "disabled";
-};
-
&main_i2c1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
@@ -409,18 +375,6 @@
};
};
-&main_i2c3 {
- status = "disabled";
-};
-
-&mcu_spi0 {
- status = "disabled";
-};
-
-&mcu_spi1 {
- status = "disabled";
-};
-
/* mcu_gpio0 is reserved for mcu firmware usage */
&mcu_gpio0 {
status = "reserved";
@@ -485,8 +439,7 @@
&cpsw3g {
pinctrl-names = "default";
- pinctrl-0 = <&mdio1_pins_default
- &rgmii1_pins_default
+ pinctrl-0 = <&rgmii1_pins_default
&rgmii2_pins_default>;
};
@@ -501,6 +454,10 @@
};
&cpsw3g_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio1_pins_default>;
+
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
@@ -603,92 +560,9 @@
<&main_r5fss1_core1_memory_region>;
};
-&pcie0_rc {
- status = "disabled";
-};
-
-&pcie0_ep {
- status = "disabled";
-};
-
&ecap0 {
+ status = "okay";
/* PWM is available on Pin 1 of header J3 */
pinctrl-names = "default";
pinctrl-0 = <&main_ecap0_pins_default>;
};
-
-&ecap1 {
- status = "disabled";
-};
-
-&ecap2 {
- status = "disabled";
-};
-
-&epwm0 {
- status = "disabled";
-};
-
-&epwm1 {
- status = "disabled";
-};
-
-&epwm2 {
- status = "disabled";
-};
-
-&epwm3 {
- status = "disabled";
-};
-
-&epwm4 {
- /*
- * EPWM4_A, EPWM4_B is available on Pin 32 and 33 on J4 (RPi hat)
- * But RPi Hat will be used for other use cases, so marking epwm4 as disabled.
- */
- status = "disabled";
-};
-
-&epwm5 {
- /*
- * EPWM5_A, EPWM5_B is available on Pin 29 and 31 on J4 (RPi hat)
- * But RPi Hat will be used for other use cases, so marking epwm5 as disabled.
- */
- status = "disabled";
-};
-
-&epwm6 {
- status = "disabled";
-};
-
-&epwm7 {
- status = "disabled";
-};
-
-&epwm8 {
- status = "disabled";
-};
-
-&icssg0_mdio {
- status = "disabled";
-};
-
-&icssg1_mdio {
- status = "disabled";
-};
-
-&main_mcan0 {
- status = "disabled";
-};
-
-&main_mcan1 {
- status = "disabled";
-};
-
-&gpmc0 {
- status = "disabled";
-};
-
-&elm0 {
- status = "disabled";
-};
diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
index 32b797237581..3cced26b520a 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
@@ -360,15 +360,13 @@
};
&main_uart1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
-&main_uart2 {
- status = "disabled";
-};
-
&mcu_uart0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&arduino_uart_pins_default>;
};
@@ -413,12 +411,14 @@
};
&wkup_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
};
&mcu_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_i2c0_pins_default>;
clock-frequency = <400000>;
@@ -478,6 +478,7 @@
};
&main_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
@@ -495,18 +496,21 @@
};
&main_i2c1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
};
&main_i2c2 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c2_pins_default>;
clock-frequency = <400000>;
};
&main_i2c3 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c3_pins_default>;
clock-frequency = <400000>;
@@ -546,6 +550,7 @@
};
&ecap0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins_default>;
};
@@ -570,6 +575,7 @@
};
&mcu_spi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_spi0_pins_default>;
@@ -626,15 +632,8 @@
};
};
-&pcie0_rc {
- status = "disabled";
-};
-
-&pcie0_ep {
- status = "disabled";
-};
-
&pcie1_rc {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&minipcie_pins_default>;
@@ -644,19 +643,8 @@
reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
};
-&m_can0 {
- status = "disabled";
-};
-
-&m_can1 {
- status = "disabled";
-};
-
-&pcie1_ep {
- status = "disabled";
-};
-
&mailbox0_cluster0 {
+ status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
@@ -666,6 +654,7 @@
};
&mailbox0_cluster1 {
+ status = "okay";
interrupts = <432>;
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
@@ -674,46 +663,6 @@
};
};
-&mailbox0_cluster2 {
- status = "disabled";
-};
-
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
-&mailbox0_cluster4 {
- status = "disabled";
-};
-
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
&mcu_r5fss0_core0 {
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
@@ -725,27 +674,3 @@
<&mcu_r5fss0_core1_memory_region>;
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
};
-
-&icssg0_mdio {
- status = "disabled";
-};
-
-&icssg1_mdio {
- status = "disabled";
-};
-
-&icssg2_mdio {
- status = "disabled";
-};
-
-&mcasp0 {
- status = "disabled";
-};
-
-&mcasp1 {
- status = "disabled";
-};
-
-&mcasp2 {
- status = "disabled";
-};
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 4005a73cfea9..1adba2f2c153 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -91,6 +91,7 @@
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart1: serial@2810000 {
@@ -99,6 +100,7 @@
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart2: serial@2820000 {
@@ -107,6 +109,7 @@
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
crypto: crypto@4e00000 {
@@ -120,17 +123,33 @@
dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
<&main_udmap 0x4003>;
dma-names = "tx", "rx1", "rx2";
- dma-coherent;
rng: rng@4e10000 {
compatible = "inside-secure,safexcel-eip76";
reg = <0x0 0x4e10000 0x0 0x7d>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 136 1>;
status = "disabled"; /* Used by OP-TEE */
};
};
+ /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
+ main_timerio_input: pinctrl@104200 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x104200 0x0 0x30>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000001ff>;
+ };
+
+ /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
+ main_timerio_output: pinctrl@104280 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x104280 0x0 0x20>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ };
+
main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
reg = <0x0 0x11c000 0x0 0x2e4>;
@@ -156,6 +175,7 @@
clock-names = "fck";
clocks = <&k3_clks 110 1>;
power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c1: i2c@2010000 {
@@ -167,6 +187,7 @@
clock-names = "fck";
clocks = <&k3_clks 111 1>;
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c2: i2c@2020000 {
@@ -178,6 +199,7 @@
clock-names = "fck";
clocks = <&k3_clks 112 1>;
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c3: i2c@2030000 {
@@ -189,6 +211,7 @@
clock-names = "fck";
clocks = <&k3_clks 113 1>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
ecap0: pwm@3100000 {
@@ -198,6 +221,7 @@
power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 39 0>;
clock-names = "fck";
+ status = "disabled";
};
main_spi0: spi@2100000 {
@@ -210,6 +234,7 @@
#size-cells = <0>;
dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
dma-names = "tx0", "rx0";
+ status = "disabled";
};
main_spi1: spi@2110000 {
@@ -222,6 +247,7 @@
#size-cells = <0>;
assigned-clocks = <&k3_clks 137 1>;
assigned-clock-rates = <48000000>;
+ status = "disabled";
};
main_spi2: spi@2120000 {
@@ -232,6 +258,7 @@
power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
main_spi3: spi@2130000 {
@@ -242,6 +269,7 @@
power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
main_spi4: spi@2140000 {
@@ -252,6 +280,151 @@
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
+ };
+
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 23 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 23 0>;
+ assigned-clock-parents = <&k3_clks 23 1>;
+ power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 24 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 24 0>;
+ assigned-clock-parents = <&k3_clks 24 1>;
+ power-domains = <&k3_pds 24 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 27 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 27 0>;
+ assigned-clock-parents = <&k3_clks 27 1>;
+ power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 28 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 28 0>;
+ assigned-clock-parents = <&k3_clks 28 1>;
+ power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 29 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 29 0>;
+ assigned-clock-parents = <&k3_clks 29 1>;
+ power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 30 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 30 0>;
+ assigned-clock-parents = <&k3_clks 30 1>;
+ power-domains = <&k3_pds 30 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 31 0>;
+ assigned-clocks = <&k3_clks 31 0>;
+ assigned-clock-parents = <&k3_clks 31 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 31 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 32 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 32 0>;
+ assigned-clock-parents = <&k3_clks 32 1>;
+ power-domains = <&k3_pds 32 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer8: timer@2480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2480000 0x00 0x400>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 33 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 33 0>;
+ assigned-clock-parents = <&k3_clks 33 1>;
+ power-domains = <&k3_pds 33 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer9: timer@2490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2490000 0x00 0x400>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 34 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 34 0>;
+ assigned-clock-parents = <&k3_clks 34 1>;
+ power-domains = <&k3_pds 34 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer10: timer@24a0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24a0000 0x00 0x400>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 25 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 25 0>;
+ assigned-clock-parents = <&k3_clks 25 1>;
+ power-domains = <&k3_pds 25 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer11: timer@24b0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24b0000 0x00 0x400>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 26 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 26 0>;
+ assigned-clock-parents = <&k3_clks 26 1>;
+ power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
};
sdhci0: mmc@4f80000 {
@@ -342,7 +515,7 @@
dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
compatible = "syscon";
- reg = <0x0000041e0 0x14>;
+ reg = <0x000041e0 0x14>;
};
ehrpwm_tbclk: clock@4140 {
@@ -501,6 +674,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster1: mailbox@31f81000 {
@@ -510,6 +684,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster2: mailbox@31f82000 {
@@ -519,6 +694,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster3: mailbox@31f83000 {
@@ -528,6 +704,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster4: mailbox@31f84000 {
@@ -537,6 +714,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster5: mailbox@31f85000 {
@@ -546,6 +724,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster6: mailbox@31f86000 {
@@ -555,6 +734,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster7: mailbox@31f87000 {
@@ -564,6 +744,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster8: mailbox@31f88000 {
@@ -573,6 +754,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster9: mailbox@31f89000 {
@@ -582,6 +764,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster10: mailbox@31f8a000 {
@@ -591,6 +774,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster11: mailbox@31f8b000 {
@@ -600,6 +784,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
ringacc: ringacc@3c000000 {
@@ -707,6 +892,7 @@
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
device_type = "pci";
+ status = "disabled";
};
pcie0_ep: pcie-ep@5500000 {
@@ -720,6 +906,7 @@
max-link-speed = <2>;
dma-coherent;
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
};
pcie1_rc: pcie@5600000 {
@@ -740,6 +927,7 @@
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
msi-map = <0x0 &gic_its 0x10000 0x10000>;
device_type = "pci";
+ status = "disabled";
};
pcie1_ep: pcie-ep@5600000 {
@@ -753,6 +941,7 @@
max-link-speed = <2>;
dma-coherent;
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
};
mcasp0: mcasp@2b00000 {
@@ -770,6 +959,7 @@
clocks = <&k3_clks 104 0>;
clock-names = "fck";
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp1: mcasp@2b10000 {
@@ -787,6 +977,7 @@
clocks = <&k3_clks 105 0>;
clock-names = "fck";
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp2: mcasp@2b20000 {
@@ -804,6 +995,7 @@
clocks = <&k3_clks 106 0>;
clock-names = "fck";
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
cal: cal@6f03000 {
@@ -874,6 +1066,7 @@
power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm1: pwm@3010000 {
@@ -883,6 +1076,7 @@
power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm2: pwm@3020000 {
@@ -892,6 +1086,7 @@
power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm3: pwm@3030000 {
@@ -901,6 +1096,7 @@
power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm4: pwm@3040000 {
@@ -910,6 +1106,7 @@
power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm5: pwm@3050000 {
@@ -919,6 +1116,7 @@
power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
icssg0: icssg@b000000 {
@@ -1059,6 +1257,7 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
@@ -1200,6 +1399,7 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
@@ -1341,6 +1541,7 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
index 8d592bf41d6f..5dfa31840e9c 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -20,13 +20,32 @@
};
};
+ /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
+ mcu_timerio_input: pinctrl@40f04200 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x40f04200 0x0 0x10>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000101>;
+ };
+
+ /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
+ mcu_timerio_output: pinctrl@40f04280 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x40f04280 0x0 0x8>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000003>;
+ };
+
mcu_uart0: serial@40a00000 {
compatible = "ti,am654-uart";
- reg = <0x00 0x40a00000 0x00 0x100>;
- interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <96000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ reg = <0x00 0x40a00000 0x00 0x100>;
+ interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <96000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_ram: sram@41c00000 {
@@ -46,6 +65,7 @@
clock-names = "fck";
clocks = <&k3_clks 114 1>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_spi0: spi@40300000 {
@@ -56,6 +76,7 @@
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
mcu_spi1: spi@40310000 {
@@ -66,6 +87,7 @@
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
mcu_spi2: spi@40320000 {
@@ -76,6 +98,7 @@
power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
tscadc0: tscadc@40200000 {
@@ -85,7 +108,7 @@
clocks = <&k3_clks 0 2>;
assigned-clocks = <&k3_clks 0 2>;
assigned-clock-rates = <60000000>;
- clock-names = "adc_tsc_fck";
+ clock-names = "fck";
dmas = <&mcu_udmap 0x7100>,
<&mcu_udmap 0x7101 >;
dma-names = "fifo0", "fifo1";
@@ -103,7 +126,7 @@
clocks = <&k3_clks 1 2>;
assigned-clocks = <&k3_clks 1 2>;
assigned-clock-rates = <60000000>;
- clock-names = "adc_tsc_fck";
+ clock-names = "fck";
dmas = <&mcu_udmap 0x7102>,
<&mcu_udmap 0x7103>;
dma-names = "fifo0", "fifo1";
@@ -114,6 +137,51 @@
};
};
+ /*
+ * The MCU domain timer interrupts are routed only to the ESM module,
+ * and not currently available for Linux. The MCU domain timers are
+ * of limited use without interrupts, and likely reserved by the ESM.
+ */
+ mcu_timer0: timer@40400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40400000 0x00 0x400>;
+ clocks = <&k3_clks 35 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer1: timer@40410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40410000 0x00 0x400>;
+ clocks = <&k3_clks 36 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer2: timer@40420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40420000 0x00 0x400>;
+ clocks = <&k3_clks 37 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer3: timer@40430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40430000 0x00 0x400>;
+ clocks = <&k3_clks 38 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
mcu_navss: bus@28380000 {
compatible = "simple-mfd";
#address-cells = <2>;
@@ -172,6 +240,7 @@
<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
m_can1: mcan@40568000 {
@@ -187,6 +256,7 @@
<GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
fss: fss@47000000 {
@@ -273,6 +343,7 @@
clocks = <&k3_clks 5 10>;
clock-names = "fck";
bus_freq = <1000000>;
+ status = "disabled";
};
cpts@3d000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
index fa11d7142006..fd2b998ebddc 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
@@ -54,6 +54,7 @@
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
wkup_i2c0: i2c@42120000 {
@@ -65,6 +66,7 @@
clock-names = "fck";
clocks = <&k3_clks 115 1>;
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
intr_wkup_gpio: interrupt-controller@42200000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi
index 4a9bf7d7c07d..cd43fd11a5c2 100644
--- a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi
@@ -50,6 +50,7 @@
};
&main_uart0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index 5850582dd4ed..592ab2b54cb3 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -271,13 +271,20 @@
status = "reserved";
};
+&mcu_uart0 {
+ status = "okay";
+ /* Default pinmux */
+};
+
&main_uart0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
&wkup_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
@@ -296,7 +303,13 @@
};
};
+&mcu_i2c0 {
+ status = "okay";
+ /* Default pinmux */
+};
+
&main_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
@@ -310,23 +323,27 @@
};
&main_i2c1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
};
&main_i2c2 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c2_pins_default>;
clock-frequency = <400000>;
};
&ecap0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins_default>;
};
&main_spi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_spi0_pins_default>;
#address-cells = <1>;
@@ -398,31 +415,8 @@
status = "disabled";
};
-&pcie0_rc {
- status = "disabled";
-};
-
-&pcie0_ep {
- status = "disabled";
-};
-
-&pcie1_rc {
- status = "disabled";
-};
-
-&pcie1_ep {
- status = "disabled";
-};
-
-&m_can0 {
- status = "disabled";
-};
-
-&m_can1 {
- status = "disabled";
-};
-
&mailbox0_cluster0 {
+ status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
@@ -432,6 +426,7 @@
};
&mailbox0_cluster1 {
+ status = "okay";
interrupts = <432>;
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
@@ -440,46 +435,6 @@
};
};
-&mailbox0_cluster2 {
- status = "disabled";
-};
-
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
-&mailbox0_cluster4 {
- status = "disabled";
-};
-
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
&mcu_r5fss0_core0 {
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
@@ -512,10 +467,14 @@
&mcu_cpsw {
pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+ pinctrl-0 = <&mcu_cpsw_pins_default>;
};
&davinci_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mdio_pins_default>;
+
phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
@@ -528,30 +487,6 @@
phy-handle = <&phy0>;
};
-&mcasp0 {
- status = "disabled";
-};
-
-&mcasp1 {
- status = "disabled";
-};
-
-&mcasp2 {
- status = "disabled";
-};
-
&dss {
status = "disabled";
};
-
-&icssg0_mdio {
- status = "disabled";
-};
-
-&icssg1_mdio {
- status = "disabled";
-};
-
-&icssg2_mdio {
- status = "disabled";
-};
diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi
index d25e8b26187f..0f67e1ec0fb8 100644
--- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi
@@ -50,7 +50,3 @@
ti,driver-strength-ohm = <50>;
disable-wp;
};
-
-&main_uart0 {
- status = "disabled";
-};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 7e8552fd2b6a..6240856e4863 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -154,51 +154,27 @@
status = "reserved";
};
+&mcu_uart0 {
+ status = "okay";
+ /* Default pinmux */
+};
+
&main_uart0 {
+ status = "okay";
/* Shared with ATF on this platform */
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
+&main_uart1 {
+ status = "okay";
+ /* Default pinmux */
+};
+
&main_uart2 {
/* MAIN UART 2 is used by R5F firmware */
status = "reserved";
};
-&main_uart3 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart4 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart5 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart6 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart7 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart8 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart9 {
- /* UART not brought out */
- status = "disabled";
-};
-
&main_gpio2 {
status = "disabled";
};
@@ -234,6 +210,7 @@
};
&main_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
@@ -261,6 +238,7 @@
* The i2c1 of the CPB (as it is labeled) is not connected to j7200.
*/
&main_i2c1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 80a57916bcb3..138381f43ce4 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -142,6 +142,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster1: mailbox@31f81000 {
@@ -151,6 +152,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster2: mailbox@31f82000 {
@@ -160,6 +162,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster3: mailbox@31f83000 {
@@ -169,6 +172,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster4: mailbox@31f84000 {
@@ -178,6 +182,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster5: mailbox@31f85000 {
@@ -187,6 +192,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster6: mailbox@31f86000 {
@@ -196,6 +202,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster7: mailbox@31f87000 {
@@ -205,6 +212,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster8: mailbox@31f88000 {
@@ -214,6 +222,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster9: mailbox@31f89000 {
@@ -223,6 +232,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster10: mailbox@31f8a000 {
@@ -232,6 +242,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster11: mailbox@31f8b000 {
@@ -241,6 +252,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
main_ringacc: ringacc@3c000000 {
@@ -319,6 +331,7 @@
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart1: serial@2810000 {
@@ -330,6 +343,7 @@
power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 278 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart2: serial@2820000 {
@@ -341,6 +355,7 @@
power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 279 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart3: serial@2830000 {
@@ -352,6 +367,7 @@
power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 280 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart4: serial@2840000 {
@@ -363,6 +379,7 @@
power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 281 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart5: serial@2850000 {
@@ -374,6 +391,7 @@
power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 282 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart6: serial@2860000 {
@@ -385,6 +403,7 @@
power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 283 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart7: serial@2870000 {
@@ -396,6 +415,7 @@
power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 284 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart8: serial@2880000 {
@@ -407,6 +427,7 @@
power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 285 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart9: serial@2890000 {
@@ -418,6 +439,7 @@
power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 286 2>;
clock-names = "fclk";
+ status = "disabled";
};
main_i2c0: i2c@2000000 {
@@ -429,6 +451,7 @@
clock-names = "fck";
clocks = <&k3_clks 187 1>;
power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
+ status = "disabled";
};
main_i2c1: i2c@2010000 {
@@ -440,6 +463,7 @@
clock-names = "fck";
clocks = <&k3_clks 188 1>;
power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c2: i2c@2020000 {
@@ -451,6 +475,7 @@
clock-names = "fck";
clocks = <&k3_clks 189 1>;
power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c3: i2c@2030000 {
@@ -462,6 +487,7 @@
clock-names = "fck";
clocks = <&k3_clks 190 1>;
power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c4: i2c@2040000 {
@@ -473,6 +499,7 @@
clock-names = "fck";
clocks = <&k3_clks 191 1>;
power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c5: i2c@2050000 {
@@ -484,6 +511,7 @@
clock-names = "fck";
clocks = <&k3_clks 192 1>;
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c6: i2c@2060000 {
@@ -495,6 +523,7 @@
clock-names = "fck";
clocks = <&k3_clks 193 1>;
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_sdhci0: mmc@4f80000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index e5be78a58682..fe669deba489 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -79,6 +79,7 @@
power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 287 2>;
clock-names = "fclk";
+ status = "disabled";
};
mcu_uart0: serial@40a00000 {
@@ -90,6 +91,7 @@
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 2>;
clock-names = "fclk";
+ status = "disabled";
};
wkup_gpio_intr: interrupt-controller@42200000 {
@@ -249,6 +251,7 @@
clock-names = "fck";
clocks = <&k3_clks 194 1>;
power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_i2c1: i2c@40b10000 {
@@ -260,6 +263,7 @@
clock-names = "fck";
clocks = <&k3_clks 195 1>;
power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
wkup_i2c0: i2c@42120000 {
@@ -271,6 +275,7 @@
clock-names = "fck";
clocks = <&k3_clks 197 1>;
power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
+ status = "disabled";
};
fss: syscon@47000000 {
@@ -325,7 +330,7 @@
clocks = <&k3_clks 0 1>;
assigned-clocks = <&k3_clks 0 3>;
assigned-clock-rates = <60000000>;
- clock-names = "adc_tsc_fck";
+ clock-names = "fck";
dmas = <&main_udmap 0x7400>,
<&main_udmap 0x7401>;
dma-names = "fifo0", "fifo1";
@@ -386,7 +391,6 @@
dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
<&mcu_udmap 0x7503>;
dma-names = "tx", "rx1", "rx2";
- dma-coherent;
rng: rng@40910000 {
compatible = "inside-secure,safexcel-eip76";
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
index 2d615c3e9fa1..fa44ed4c17d5 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
@@ -144,6 +144,7 @@
};
&mailbox0_cluster0 {
+ status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
@@ -158,6 +159,7 @@
};
&mailbox0_cluster1 {
+ status = "okay";
interrupts = <432>;
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
@@ -171,46 +173,6 @@
};
};
-&mailbox0_cluster2 {
- status = "disabled";
-};
-
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
-&mailbox0_cluster4 {
- status = "disabled";
-};
-
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
&mcu_r5fss0_core0 {
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
new file mode 100644
index 000000000000..37c24b077b6a
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
@@ -0,0 +1,1055 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * https://beagleboard.org/ai-64
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation
+ * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+/dts-v1/;
+
+#include "k3-j721e.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
+
+/ {
+ compatible = "beagle,j721e-beagleboneai64", "ti,j721e";
+ model = "BeagleBoard.org BeagleBone AI-64";
+
+ aliases {
+ serial2 = &main_uart0;
+ mmc0 = &main_sdhci0;
+ mmc1 = &main_sdhci1;
+ i2c0 = &wkup_i2c0;
+ i2c1 = &main_i2c6;
+ i2c2 = &main_i2c2;
+ i2c3 = &main_i2c4;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 4G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000000 0x80000000>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c66_1_dma_memory_region: c66-dma-memory@a6000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c66_0_memory_region: c66-memory@a6100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c66_0_dma_memory_region: c66-dma-memory@a7000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c66_1_memory_region: c66-memory@a7100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c71_0_dma_memory_region: c71-dma-memory@a8000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa8000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c71_0_memory_region: c71-memory@a8100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa8100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@aa000000 {
+ reg = <0x00 0xaa000000 0x00 0x01c00000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_pwr_pins_default>;
+
+ button-1 {
+ label = "BOOT";
+ linux,code = <BTN_0>;
+ gpios = <&wkup_gpio0 0 GPIO_ACTIVE_LOW>;
+ };
+
+ button-2 {
+ label = "POWER";
+ linux,code = <KEY_POWER>;
+ gpios = <&wkup_gpio0 4 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_default>;
+
+ led-0 {
+ gpios = <&main_gpio0 96 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_HEARTBEAT;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ gpios = <&main_gpio0 95 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ linux,default-trigger = "mmc0";
+ };
+
+ led-2 {
+ gpios = <&main_gpio0 97 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_CPU;
+ linux,default-trigger = "cpu";
+ };
+
+ led-3 {
+ gpios = <&main_gpio0 110 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ linux,default-trigger = "mmc1";
+ };
+
+ led-4 {
+ gpios = <&main_gpio0 109 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_WLAN;
+ default-state = "off";
+ };
+ };
+
+ evm_12v0: regulator-0 {
+ /* main supply */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: regulator-1 {
+ /* Output of LMS140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_5v0: regulator-2 {
+ /* Output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_mmc1: regulator-3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd_pwr_en_pins_default>;
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vsys_3v3>;
+ gpio = <&main_gpio0 82 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_sd_dv_alt: regulator-4 {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
+ regulator-name = "tlv71033";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ vin-supply = <&vsys_5v0>;
+ gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
+ };
+
+ dp_pwr_3v3: regulator-5 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp0_3v3_en_pins_default>;
+ regulator-name = "dp-pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; /* DP0_PWR_SW_EN */
+ enable-active-high;
+ };
+
+ dp0: connector {
+ compatible = "dp-connector";
+ label = "DP0";
+ type = "full-size";
+ dp-pwr-supply = <&dp_pwr_3v3>;
+
+ port {
+ dp_connector_in: endpoint {
+ remote-endpoint = <&dp0_out>;
+ };
+ };
+ };
+};
+
+&main_pmx0 {
+ led_pins_default: led-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */
+ J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */
+ J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
+ J721E_IOPAD(0x1bc, PIN_INPUT, 7) /* (V24) MDIO0_MDC.GPIO0_110 */
+ J721E_IOPAD(0x1b8, PIN_INPUT, 7) /* (V26) MDIO0_MDIO.GPIO0_109 */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
+ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
+ J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
+ J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
+ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
+ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
+ >;
+ };
+
+ main_uart0_pins_default: main-uart0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
+ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
+ >;
+ };
+
+ sd_pwr_en_pins_default: sd-pwr-en-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
+ >;
+ };
+
+ vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
+ >;
+ };
+
+ main_usbss0_pins_default: main-usbss0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */
+ >;
+ };
+
+ main_usbss1_pins_default: main-usbss1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */
+ >;
+ };
+
+ dp0_3v3_en_pins_default:dp0-3v3-en-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */
+ >;
+ };
+
+ dp0_pins_default: dp0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */
+ >;
+ };
+
+ main_i2c0_pins_default: main-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
+ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
+ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
+ >;
+ };
+
+ main_i2c2_pins_default: main-i2c2-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x208, PIN_INPUT_PULLUP, 4) /* (W5) MCAN0_RX.I2C2_SCL */
+ J721E_IOPAD(0x20c, PIN_INPUT_PULLUP, 4) /* (W6) MCAN0_TX.I2C2_SDA */
+ J721E_IOPAD(0x138, PIN_INPUT, 7) /* (AE25) PRG0_PRU1_GPO14.GPIO0_77 */
+ J721E_IOPAD(0x13c, PIN_INPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */
+ >;
+ };
+
+ main_i2c3_pins_default: main-i2c3-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
+ J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
+ >;
+ };
+
+ main_i2c4_pins_default: main-i2c4-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1e0, PIN_INPUT_PULLUP, 2) /* (Y5) SPI1_D0.I2C4_SCL */
+ J721E_IOPAD(0x1dc, PIN_INPUT_PULLUP, 2) /* (Y1) SPI1_CLK.I2C4_SDA */
+ J721E_IOPAD(0x30, PIN_INPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */
+ J721E_IOPAD(0x34, PIN_INPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */
+ >;
+ };
+
+ main_i2c5_pins_default: main-i2c5-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
+ J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
+ >;
+ };
+
+ main_i2c6_pins_default: main-i2c6-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
+ J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
+ J721E_IOPAD(0x74, PIN_INPUT, 7) /* (AC21) PRG1_PRU1_GPO7.GPIO0_28 */
+ J721E_IOPAD(0xa4, PIN_INPUT, 7) /* (AH22) PRG1_PRU1_GPO19.GPIO0_40 */
+ >;
+ };
+
+ csi0_gpio_pins_default: csi0-gpio-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
+ J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
+ >;
+ };
+
+ csi1_gpio_pins_default: csi1-gpio-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
+ J721E_IOPAD(0x1b0, PIN_INPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
+ >;
+ };
+
+ pcie1_rst_pins_default: pcie1-rst-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */
+ >;
+ };
+};
+
+&wkup_pmx0 {
+ eeprom_wp_pins_default: eeprom-wp-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */
+ >;
+ };
+
+ mcu_adc0_pins_default: mcu-adc0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */
+ J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */
+ J721E_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K28) MCU_ADC0_AIN2 */
+ J721E_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (L28) MCU_ADC0_AIN3 */
+ J721E_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN4 */
+ J721E_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (K27) MCU_ADC0_AIN5 */
+ J721E_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K29) MCU_ADC0_AIN6 */
+ >;
+ };
+
+ mcu_adc1_pins_default: mcu-adc1-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */
+ >;
+ };
+
+ mikro_bus_pins_default: mikro-bus-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */
+ J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */
+ J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 7) /* SDA (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */
+ J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* SCL (G27) WKUP_GPIO0_8.MCU_I2C1_SCL */
+ J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 7) /* SCL (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */
+
+ J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* MOSI (F28) WKUP_GPIO0_2.MCU_SPI1_D1 */
+ J721E_WKUP_IOPAD(0xb4, PIN_INPUT, 7) /* MISO (F25) WKUP_GPIO0_1.MCU_SPI1_D0 */
+ J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* CLK (F26) WKUP_GPIO0_0.MCU_SPI1_CLK */
+ J721E_WKUP_IOPAD(0xbc, PIN_INPUT, 7) /* CS (F27) WKUP_GPIO0_3.MCU_SPI1_CS0 */
+
+ J721E_WKUP_IOPAD(0x44, PIN_INPUT, 7) /* RX (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */
+ J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* TX (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */
+
+ J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* INT (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */
+ J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /* RST (E22) MCU_OSPI1_CSn1.WKUP_GPIO0_37 */
+ J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* PWM (H27) WKUP_GPIO0_11 */
+ J721E_WKUP_IOPAD(0xac, PIN_INPUT, 7) /* AN (C29) MCU_MCAN0_RX.WKUP_GPIO0_59 */
+ >;
+ };
+
+ mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
+ J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
+ J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
+ J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
+ J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
+ J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
+ J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
+ J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
+ J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
+ J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
+ J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
+ J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
+ >;
+ };
+
+ mcu_mdio_pins_default: mcu-mdio1-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
+ J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
+ >;
+ };
+
+ sw_pwr_pins_default: sw-pwr-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */
+ >;
+ };
+
+ wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
+ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
+ >;
+ };
+
+ mcu_usbss1_pins_default: mcu-usbss1-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */
+ >;
+ };
+};
+
+&wkup_uart0 {
+ /* Wakeup UART is used by TIFS firmware. */
+ status = "reserved";
+};
+
+&main_uart0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+ /* Shared with ATF on this platform */
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
+&main_sdhci0 {
+ /* eMMC */
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_sdhci1 {
+ /* SD Card */
+ vmmc-supply = <&vdd_mmc1>;
+ vqmmc-supply = <&vdd_sd_dv_alt>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_sdhci2 {
+ /* Unused */
+ status = "disabled";
+};
+
+&ospi0 {
+ /* Unused */
+ status = "disabled";
+};
+
+&ospi1 {
+ /* Unused */
+ status = "disabled";
+};
+
+&main_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_pins_default &csi1_gpio_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c2 {
+ /* BBB Header: P9.19 and P9.20 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c2_pins_default>;
+ clock-frequency = <100000>;
+};
+
+&main_i2c3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c3_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c4 {
+ /* BBB Header: P9.24 and P9.26 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c4_pins_default>;
+ clock-frequency = <100000>;
+};
+
+&main_i2c5 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c5_pins_default &csi0_gpio_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c6 {
+ /* BBB Header: P9.17 and P9.18 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c6_pins_default>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&wkup_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>;
+ clock-frequency = <400000>;
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ };
+};
+
+&main_gpio2 {
+ /* Unused */
+ status = "disabled";
+};
+
+&main_gpio3 {
+ /* Unused */
+ status = "disabled";
+};
+
+&main_gpio4 {
+ /* Unused */
+ status = "disabled";
+};
+
+&main_gpio5 {
+ /* Unused */
+ status = "disabled";
+};
+
+&main_gpio6 {
+ /* Unused */
+ status = "disabled";
+};
+
+&main_gpio7 {
+ /* Unused */
+ status = "disabled";
+};
+
+&wkup_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_adc0_pins_default &mcu_adc1_pins_default &mikro_bus_pins_default>;
+};
+
+&wkup_gpio1 {
+ /* Unused */
+ status = "disabled";
+};
+
+&usb_serdes_mux {
+ idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
+};
+
+&serdes_ln_ctrl {
+ idle-states = <J721E_SERDES0_LANE0_IP4_UNUSED>, <J721E_SERDES0_LANE1_IP4_UNUSED>,
+ <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
+ <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>,
+ <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
+ <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
+ <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+};
+
+&serdes_wiz3 {
+ typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_LOW>;
+ typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
+};
+
+&serdes3 {
+ serdes3_usb_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
+ };
+};
+
+&serdes4 {
+ torrent_phy_dp: phy@0 {
+ reg = <0>;
+ resets = <&serdes_wiz4 1>;
+ cdns,phy-type = <PHY_TYPE_DP>;
+ cdns,num-lanes = <4>;
+ cdns,max-bit-rate = <5400>;
+ #phy-cells = <0>;
+ };
+};
+
+&mhdp {
+ phys = <&torrent_phy_dp>;
+ phy-names = "dpphy";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp0_pins_default>;
+};
+
+&usbss0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "peripheral";
+ maximum-speed = "super-speed";
+ phys = <&serdes3_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
+&serdes2 {
+ serdes2_usb_link: phy@1 {
+ reg = <1>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz2 2>;
+ };
+};
+
+&usbss1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss1_pins_default &mcu_usbss1_pins_default>;
+ ti,vbus-divider;
+};
+
+&usb1 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ phys = <&serdes2_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
+&tscadc0 {
+ /* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6>;
+ };
+};
+
+&tscadc1 {
+ /* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */
+ adc {
+ ti,adc-channels = <0>;
+ };
+};
+
+&mcu_cpsw {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_cpsw_pins_default>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mdio_pins_default>;
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&phy0>;
+};
+
+&dss {
+ /*
+ * These clock assignments are chosen to enable the following outputs:
+ *
+ * VP0 - DisplayPort SST
+ * VP1 - DPI0
+ * VP2 - DSI
+ * VP3 - DPI1
+ */
+
+ assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */
+ <&k3_clks 152 4>, /* VP 2 pixel clock */
+ <&k3_clks 152 9>, /* VP 3 pixel clock */
+ <&k3_clks 152 13>; /* VP 4 pixel clock */
+ assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
+ <&k3_clks 152 6>, /* PLL19_HSDIV0 */
+ <&k3_clks 152 11>, /* PLL18_HSDIV0 */
+ <&k3_clks 152 18>; /* PLL23_HSDIV0 */
+};
+
+&dss_ports {
+ port {
+ dpi0_out: endpoint {
+ remote-endpoint = <&dp0_in>;
+ };
+ };
+};
+
+&dp0_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ dp0_out: endpoint {
+ remote-endpoint = <&dp_connector_in>;
+ };
+ };
+};
+
+&serdes0 {
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&serdes1 {
+ serdes1_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
+ };
+};
+
+&pcie0_rc {
+ /* Unused */
+ status = "disabled";
+};
+
+&pcie1_rc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_rst_pins_default>;
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+ max-link-speed = <3>;
+ reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie2_rc {
+ /* Unused */
+ status = "disabled";
+};
+
+&pcie0_ep {
+ status = "disabled";
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
+&pcie1_ep {
+ status = "disabled";
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+};
+
+&pcie2_ep {
+ /* Unused */
+ status = "disabled";
+};
+
+&pcie3_rc {
+ /* Unused */
+ status = "disabled";
+};
+
+&pcie3_ep {
+ /* Unused */
+ status = "disabled";
+};
+
+&icssg0_mdio {
+ /* Unused */
+ status = "disabled";
+};
+
+&icssg1_mdio {
+ /* Unused */
+ status = "disabled";
+};
+
+&ufs_wrapper {
+ status = "disabled";
+};
+
+&mailbox0_cluster0 {
+ interrupts = <436>;
+
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ interrupts = <432>;
+
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster2 {
+ interrupts = <428>;
+
+ mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster3 {
+ interrupts = <424>;
+
+ mbox_c66_0: mbox-c66-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_c66_1: mbox-c66-1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster4 {
+ interrupts = <420>;
+
+ mbox_c71_0: mbox-c71-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+};
+
+&mcu_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+ memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+ <&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
+&c66_0 {
+ mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+ memory-region = <&c66_0_dma_memory_region>,
+ <&c66_0_memory_region>;
+};
+
+&c66_1 {
+ mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+ memory-region = <&c66_1_dma_memory_region>,
+ <&c66_1_memory_region>;
+};
+
+&c71_0 {
+ mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+ memory-region = <&c71_0_dma_memory_region>,
+ <&c71_0_memory_region>;
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index b1691ac3442d..7db0603125aa 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -96,7 +96,7 @@
<3300000 0x1>;
};
- sound0: sound@0 {
+ sound0: sound-0 {
compatible = "ti,j721e-cpb-audio";
model = "j721e-cpb";
@@ -370,38 +370,30 @@
status = "reserved";
};
-&main_uart0 {
- power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
-};
-
-&main_uart3 {
- /* UART not brought out */
- status = "disabled";
+&mcu_uart0 {
+ status = "okay";
+ /* Default pinmux */
};
-&main_uart5 {
- /* UART not brought out */
- status = "disabled";
+&main_uart0 {
+ status = "okay";
+ /* Shared with ATF on this platform */
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
-&main_uart6 {
- /* UART not brought out */
- status = "disabled";
+&main_uart1 {
+ status = "okay";
+ /* Default pinmux */
};
-&main_uart7 {
- /* UART not brought out */
- status = "disabled";
+&main_uart2 {
+ status = "okay";
+ /* Default pinmux */
};
-&main_uart8 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart9 {
- /* UART not brought out */
- status = "disabled";
+&main_uart4 {
+ status = "okay";
+ /* Default pinmux */
};
&main_gpio2 {
@@ -537,6 +529,7 @@
};
&main_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
@@ -573,6 +566,7 @@
};
&main_i2c1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
@@ -598,6 +592,7 @@
};
&main_i2c3 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c3_pins_default>;
clock-frequency = <400000>;
@@ -636,6 +631,7 @@
};
&main_i2c6 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c6_pins_default>;
clock-frequency = <400000>;
@@ -713,47 +709,8 @@
};
};
-&mcasp0 {
- status = "disabled";
-};
-
-&mcasp1 {
- status = "disabled";
-};
-
-&mcasp2 {
- status = "disabled";
-};
-
-&mcasp3 {
- status = "disabled";
-};
-
-&mcasp4 {
- status = "disabled";
-};
-
-&mcasp5 {
- status = "disabled";
-};
-
-&mcasp6 {
- status = "disabled";
-};
-
-&mcasp7 {
- status = "disabled";
-};
-
-&mcasp8 {
- status = "disabled";
-};
-
-&mcasp9 {
- status = "disabled";
-};
-
&mcasp10 {
+ status = "okay";
#sound-dai-cells = <0>;
pinctrl-names = "default";
@@ -771,10 +728,6 @@
rx-num-evt = <0>;
};
-&mcasp11 {
- status = "disabled";
-};
-
&cmn_refclk1 {
clock-frequency = <100000000>;
};
@@ -925,73 +878,29 @@
};
&mcu_mcan0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan0_pins_default>;
phys = <&transceiver1>;
};
&mcu_mcan1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan1_pins_default>;
phys = <&transceiver2>;
};
&main_mcan0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mcan0_pins_default>;
phys = <&transceiver3>;
};
-&main_mcan1 {
- status = "disabled";
-};
-
&main_mcan2 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mcan2_pins_default>;
phys = <&transceiver4>;
};
-
-&main_mcan3 {
- status = "disabled";
-};
-
-&main_mcan4 {
- status = "disabled";
-};
-
-&main_mcan5 {
- status = "disabled";
-};
-
-&main_mcan6 {
- status = "disabled";
-};
-
-&main_mcan7 {
- status = "disabled";
-};
-
-&main_mcan8 {
- status = "disabled";
-};
-
-&main_mcan9 {
- status = "disabled";
-};
-
-&main_mcan10 {
- status = "disabled";
-};
-
-&main_mcan11 {
- status = "disabled";
-};
-
-&main_mcan12 {
- status = "disabled";
-};
-
-&main_mcan13 {
- status = "disabled";
-};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 917c9dc99efa..c935622f0102 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -66,7 +66,73 @@
#mux-control-cells = <1>;
mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
<0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
- };
+ };
+
+ ehrpwm_tbclk: clock-controller@4140 {
+ compatible = "ti,am654-ehrpwm-tbclk", "syscon";
+ reg = <0x4140 0x18>;
+ #clock-cells = <1>;
+ };
+ };
+
+ main_ehrpwm0: pwm@3000000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3000000 0x00 0x100>;
+ power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ main_ehrpwm1: pwm@3010000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3010000 0x00 0x100>;
+ power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ main_ehrpwm2: pwm@3020000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3020000 0x00 0x100>;
+ power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ main_ehrpwm3: pwm@3030000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3030000 0x00 0x100>;
+ power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ main_ehrpwm4: pwm@3040000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3040000 0x00 0x100>;
+ power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ main_ehrpwm5: pwm@3050000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x3050000 0x00 0x100>;
+ power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
};
gic500: interrupt-controller@1800000 {
@@ -176,6 +242,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster1: mailbox@31f81000 {
@@ -185,6 +252,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster2: mailbox@31f82000 {
@@ -194,6 +262,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster3: mailbox@31f83000 {
@@ -203,6 +272,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster4: mailbox@31f84000 {
@@ -212,6 +282,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster5: mailbox@31f85000 {
@@ -221,6 +292,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster6: mailbox@31f86000 {
@@ -230,6 +302,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster7: mailbox@31f87000 {
@@ -239,6 +312,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster8: mailbox@31f88000 {
@@ -248,6 +322,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster9: mailbox@31f89000 {
@@ -257,6 +332,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster10: mailbox@31f8a000 {
@@ -266,6 +342,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster11: mailbox@31f8b000 {
@@ -275,6 +352,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
main_ringacc: ringacc@3c000000 {
@@ -337,13 +415,11 @@
dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
<&main_udmap 0x4001>;
dma-names = "tx", "rx1", "rx2";
- dma-coherent;
rng: rng@4e10000 {
compatible = "inside-secure,safexcel-eip76";
reg = <0x0 0x4e10000 0x0 0x7d>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 264 2>;
};
};
@@ -840,6 +916,7 @@
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart1: serial@2810000 {
@@ -851,6 +928,7 @@
power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 278 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart2: serial@2820000 {
@@ -862,6 +940,7 @@
power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 279 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart3: serial@2830000 {
@@ -873,6 +952,7 @@
power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 280 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart4: serial@2840000 {
@@ -884,6 +964,7 @@
power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 281 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart5: serial@2850000 {
@@ -895,6 +976,7 @@
power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 282 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart6: serial@2860000 {
@@ -906,6 +988,7 @@
power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 283 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart7: serial@2870000 {
@@ -917,6 +1000,7 @@
power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 284 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart8: serial@2880000 {
@@ -928,6 +1012,7 @@
power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 285 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_uart9: serial@2890000 {
@@ -939,6 +1024,7 @@
power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 286 0>;
clock-names = "fclk";
+ status = "disabled";
};
main_gpio0: gpio@600000 {
@@ -1219,6 +1305,7 @@
clock-names = "fck";
clocks = <&k3_clks 187 0>;
power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
+ status = "disabled";
};
main_i2c1: i2c@2010000 {
@@ -1230,6 +1317,7 @@
clock-names = "fck";
clocks = <&k3_clks 188 0>;
power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c2: i2c@2020000 {
@@ -1241,6 +1329,7 @@
clock-names = "fck";
clocks = <&k3_clks 189 0>;
power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c3: i2c@2030000 {
@@ -1252,6 +1341,7 @@
clock-names = "fck";
clocks = <&k3_clks 190 0>;
power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c4: i2c@2040000 {
@@ -1263,6 +1353,7 @@
clock-names = "fck";
clocks = <&k3_clks 191 0>;
power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c5: i2c@2050000 {
@@ -1274,6 +1365,7 @@
clock-names = "fck";
clocks = <&k3_clks 192 0>;
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c6: i2c@2060000 {
@@ -1285,6 +1377,7 @@
clock-names = "fck";
clocks = <&k3_clks 193 0>;
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
ufs_wrapper: ufs-wrapper@4e80000 {
@@ -1408,6 +1501,7 @@
clocks = <&k3_clks 174 1>;
clock-names = "fck";
power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp1: mcasp@2b10000 {
@@ -1425,6 +1519,7 @@
clocks = <&k3_clks 175 1>;
clock-names = "fck";
power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp2: mcasp@2b20000 {
@@ -1442,6 +1537,7 @@
clocks = <&k3_clks 176 1>;
clock-names = "fck";
power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp3: mcasp@2b30000 {
@@ -1459,6 +1555,7 @@
clocks = <&k3_clks 177 1>;
clock-names = "fck";
power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp4: mcasp@2b40000 {
@@ -1476,6 +1573,7 @@
clocks = <&k3_clks 178 1>;
clock-names = "fck";
power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp5: mcasp@2b50000 {
@@ -1493,6 +1591,7 @@
clocks = <&k3_clks 179 1>;
clock-names = "fck";
power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp6: mcasp@2b60000 {
@@ -1510,6 +1609,7 @@
clocks = <&k3_clks 180 1>;
clock-names = "fck";
power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp7: mcasp@2b70000 {
@@ -1527,6 +1627,7 @@
clocks = <&k3_clks 181 1>;
clock-names = "fck";
power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp8: mcasp@2b80000 {
@@ -1544,6 +1645,7 @@
clocks = <&k3_clks 182 1>;
clock-names = "fck";
power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp9: mcasp@2b90000 {
@@ -1561,6 +1663,7 @@
clocks = <&k3_clks 183 1>;
clock-names = "fck";
power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp10: mcasp@2ba0000 {
@@ -1578,6 +1681,7 @@
clocks = <&k3_clks 184 1>;
clock-names = "fck";
power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp11: mcasp@2bb0000 {
@@ -1595,6 +1699,7 @@
clocks = <&k3_clks 185 1>;
clock-names = "fck";
power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
watchdog0: watchdog@2200000 {
@@ -2027,6 +2132,7 @@
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan1: can@2711000 {
@@ -2041,6 +2147,7 @@
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan2: can@2721000 {
@@ -2055,6 +2162,7 @@
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan3: can@2731000 {
@@ -2069,6 +2177,7 @@
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan4: can@2741000 {
@@ -2083,6 +2192,7 @@
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan5: can@2751000 {
@@ -2097,6 +2207,7 @@
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan6: can@2761000 {
@@ -2111,6 +2222,7 @@
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan7: can@2771000 {
@@ -2125,6 +2237,7 @@
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan8: can@2781000 {
@@ -2139,6 +2252,7 @@
<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan9: can@2791000 {
@@ -2153,6 +2267,7 @@
<GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan10: can@27a1000 {
@@ -2167,6 +2282,7 @@
<GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan11: can@27b1000 {
@@ -2181,6 +2297,7 @@
<GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan12: can@27c1000 {
@@ -2195,6 +2312,7 @@
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan13: can@27d1000 {
@@ -2209,5 +2327,6 @@
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index df08724bbf1c..8ac78034d5d6 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -79,6 +79,7 @@
power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 287 0>;
clock-names = "fclk";
+ status = "disabled";
};
mcu_uart0: serial@40a00000 {
@@ -90,6 +91,7 @@
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 0>;
clock-names = "fclk";
+ status = "disabled";
};
wkup_gpio_intr: interrupt-controller@42200000 {
@@ -145,6 +147,7 @@
clock-names = "fck";
clocks = <&k3_clks 194 0>;
power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_i2c1: i2c@40b10000 {
@@ -156,6 +159,7 @@
clock-names = "fck";
clocks = <&k3_clks 195 0>;
power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
wkup_i2c0: i2c@42120000 {
@@ -167,6 +171,7 @@
clock-names = "fck";
clocks = <&k3_clks 197 0>;
power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
+ status = "disabled";
};
fss: fss@47000000 {
@@ -216,7 +221,7 @@
clocks = <&k3_clks 0 1>;
assigned-clocks = <&k3_clks 0 3>;
assigned-clock-rates = <60000000>;
- clock-names = "adc_tsc_fck";
+ clock-names = "fck";
dmas = <&main_udmap 0x7400>,
<&main_udmap 0x7401>;
dma-names = "fifo0", "fifo1";
@@ -235,7 +240,7 @@
clocks = <&k3_clks 1 1>;
assigned-clocks = <&k3_clks 1 3>;
assigned-clock-rates = <60000000>;
- clock-names = "adc_tsc_fck";
+ clock-names = "fck";
dmas = <&main_udmap 0x7402>,
<&main_udmap 0x7403>;
dma-names = "fifo0", "fifo1";
@@ -403,6 +408,7 @@
<GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
mcu_mcan1: can@40568000 {
@@ -417,5 +423,6 @@
<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
index 80358cba6954..4640d280c85c 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
@@ -400,6 +400,47 @@
J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */
>;
};
+
+ main_i2c5_pins_default: main-i2c5-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
+ J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
+ >;
+ };
+
+ rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
+ J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */
+ J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
+ J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */
+ J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
+ J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
+ J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
+ J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */
+ J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */
+ J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */
+ J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */
+ J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */
+ J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */
+ J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */
+ J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
+ J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */
+ J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
+ J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */
+ J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */
+ J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */
+ J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */
+ J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */
+ J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */
+ >;
+ };
+
+ rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */
+ >;
+ };
};
&wkup_pmx0 {
@@ -475,46 +516,22 @@
status = "reserved";
};
+&mcu_uart0 {
+ status = "okay";
+ /* Default pinmux */
+};
+
&main_uart0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
/* Shared with ATF on this platform */
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
-&main_uart2 {
- /* Brought out on RPi header */
- status = "disabled";
-};
-
-&main_uart3 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart5 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart6 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart7 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart8 {
- /* UART not brought out */
- status = "disabled";
-};
-
-&main_uart9 {
- /* Brought out on M.2 E Key */
- status = "disabled";
+&main_uart1 {
+ status = "okay";
+ /* Default pinmux */
};
&main_sdhci0 {
@@ -561,6 +578,7 @@
};
&main_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
@@ -588,18 +606,15 @@
};
&main_i2c1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
/* i2c1 is used for DVI DDC, so we need to use 100kHz */
clock-frequency = <100000>;
};
-&main_i2c2 {
- /* Unused */
- status = "disabled";
-};
-
&main_i2c3 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c3_pins_default>;
clock-frequency = <400000>;
@@ -626,19 +641,22 @@
};
};
-&main_i2c4 {
- /* Unused */
- status = "disabled";
-};
-
&main_i2c5 {
/* Brought out on RPi Header */
- status = "disabled";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c5_pins_default>;
+ clock-frequency = <400000>;
};
-&main_i2c6 {
- /* Unused */
- status = "disabled";
+&main_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rpi_header_gpio0_pins_default>;
+};
+
+&main_gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rpi_header_gpio1_pins_default>;
};
&main_gpio2 {
@@ -837,66 +855,6 @@
};
};
-&mcasp0 {
- /* Unused */
- status = "disabled";
-};
-
-&mcasp1 {
- /* Unused */
- status = "disabled";
-};
-
-&mcasp2 {
- /* Unused */
- status = "disabled";
-};
-
-&mcasp3 {
- /* Unused */
- status = "disabled";
-};
-
-&mcasp4 {
- /* Unused */
- status = "disabled";
-};
-
-&mcasp5 {
- /* Unused */
- status = "disabled";
-};
-
-&mcasp6 {
- /* Brought out on RPi header */
- status = "disabled";
-};
-
-&mcasp7 {
- /* Unused */
- status = "disabled";
-};
-
-&mcasp8 {
- /* Unused */
- status = "disabled";
-};
-
-&mcasp9 {
- /* Unused */
- status = "disabled";
-};
-
-&mcasp10 {
- /* Unused */
- status = "disabled";
-};
-
-&mcasp11 {
- /* Brought out on M.2 E Key */
- status = "disabled";
-};
-
&serdes0 {
serdes0_pcie_link: phy@0 {
reg = <0>;
@@ -984,6 +942,7 @@
};
&mailbox0_cluster0 {
+ status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
@@ -998,6 +957,7 @@
};
&mailbox0_cluster1 {
+ status = "okay";
interrupts = <432>;
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
@@ -1012,6 +972,7 @@
};
&mailbox0_cluster2 {
+ status = "okay";
interrupts = <428>;
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
@@ -1026,6 +987,7 @@
};
&mailbox0_cluster3 {
+ status = "okay";
interrupts = <424>;
mbox_c66_0: mbox-c66-0 {
@@ -1040,6 +1002,7 @@
};
&mailbox0_cluster4 {
+ status = "okay";
interrupts = <420>;
mbox_c71_0: mbox-c71-0 {
@@ -1048,34 +1011,6 @@
};
};
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
&mcu_r5fss0_core0 {
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index e36335232cf8..e289d5b44356 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -186,6 +186,7 @@
};
&mailbox0_cluster0 {
+ status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
@@ -200,6 +201,7 @@
};
&mailbox0_cluster1 {
+ status = "okay";
interrupts = <432>;
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
@@ -214,6 +216,7 @@
};
&mailbox0_cluster2 {
+ status = "okay";
interrupts = <428>;
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
@@ -228,6 +231,7 @@
};
&mailbox0_cluster3 {
+ status = "okay";
interrupts = <424>;
mbox_c66_0: mbox-c66-0 {
@@ -242,6 +246,7 @@
};
&mailbox0_cluster4 {
+ status = "okay";
interrupts = <420>;
mbox_c71_0: mbox-c71-0 {
@@ -250,34 +255,6 @@
};
};
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
&mcu_r5fss0_core0 {
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index b210cc07c539..a7aa6cf08acd 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -219,49 +219,19 @@
status = "reserved";
};
-&main_uart0 {
- status = "disabled";
-};
-
-&main_uart1 {
- status = "disabled";
-};
-
-&main_uart2 {
- status = "disabled";
-};
-
-&main_uart3 {
- status = "disabled";
-};
-
-&main_uart4 {
- status = "disabled";
-};
-
-&main_uart5 {
- status = "disabled";
-};
-
-&main_uart6 {
- status = "disabled";
-};
-
-&main_uart7 {
- status = "disabled";
+&mcu_uart0 {
+ status = "okay";
+ /* Default pinmux */
};
&main_uart8 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart8_pins_default>;
/* Shared with TFA on this platform */
power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
};
-&main_uart9 {
- status = "disabled";
-};
-
&main_i2c0 {
clock-frequency = <400000>;
@@ -291,30 +261,6 @@
};
};
-&main_i2c1 {
- status = "disabled";
-};
-
-&main_i2c2 {
- status = "disabled";
-};
-
-&main_i2c3 {
- status = "disabled";
-};
-
-&main_i2c4 {
- status = "disabled";
-};
-
-&main_i2c5 {
- status = "disabled";
-};
-
-&main_i2c6 {
- status = "disabled";
-};
-
&main_sdhci0 {
/* eMMC */
non-removable;
@@ -351,81 +297,15 @@
};
&mcu_mcan0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan0_pins_default>;
phys = <&transceiver1>;
};
&mcu_mcan1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan1_pins_default>;
phys = <&transceiver2>;
};
-
-&main_mcan0 {
- status = "disabled";
-};
-
-&main_mcan1 {
- status = "disabled";
-};
-
-&main_mcan2 {
- status = "disabled";
-};
-
-&main_mcan3 {
- status = "disabled";
-};
-
-&main_mcan4 {
- status = "disabled";
-};
-
-&main_mcan5 {
- status = "disabled";
-};
-
-&main_mcan6 {
- status = "disabled";
-};
-
-&main_mcan7 {
- status = "disabled";
-};
-
-&main_mcan8 {
- status = "disabled";
-};
-
-&main_mcan9 {
- status = "disabled";
-};
-
-&main_mcan10 {
- status = "disabled";
-};
-
-&main_mcan11 {
- status = "disabled";
-};
-
-&main_mcan12 {
- status = "disabled";
-};
-
-&main_mcan13 {
- status = "disabled";
-};
-
-&main_mcan14 {
- status = "disabled";
-};
-
-&main_mcan15 {
- status = "disabled";
-};
-
-&main_mcan17 {
- status = "disabled";
-};
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 34e7d577ae13..8915132efcc1 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -60,7 +60,7 @@
#interrupt-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <148>;
- ti,interrupt-ranges = <8 360 56>;
+ ti,interrupt-ranges = <8 392 56>;
};
main_pmx0: pinctrl@11c000 {
@@ -72,6 +72,25 @@
pinctrl-single,function-mask = <0xffffffff>;
};
+ main_crypto: crypto@4e00000 {
+ compatible = "ti,j721e-sa2ul";
+ reg = <0x00 0x04e00000 0x00 0x1200>;
+ power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
+
+ dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
+ <&main_udmap 0x4a41>;
+ dma-names = "tx", "rx1", "rx2";
+
+ rng: rng@4e10000 {
+ compatible = "inside-secure,safexcel-eip76";
+ reg = <0x00 0x04e10000 0x00 0x7d>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x200>;
@@ -80,6 +99,7 @@
clocks = <&k3_clks 146 3>;
clock-names = "fclk";
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart1: serial@2810000 {
@@ -90,6 +110,7 @@
clocks = <&k3_clks 350 3>;
clock-names = "fclk";
power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart2: serial@2820000 {
@@ -100,6 +121,7 @@
clocks = <&k3_clks 351 3>;
clock-names = "fclk";
power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart3: serial@2830000 {
@@ -110,6 +132,7 @@
clocks = <&k3_clks 352 3>;
clock-names = "fclk";
power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart4: serial@2840000 {
@@ -120,6 +143,7 @@
clocks = <&k3_clks 353 3>;
clock-names = "fclk";
power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart5: serial@2850000 {
@@ -130,6 +154,7 @@
clocks = <&k3_clks 354 3>;
clock-names = "fclk";
power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart6: serial@2860000 {
@@ -140,6 +165,7 @@
clocks = <&k3_clks 355 3>;
clock-names = "fclk";
power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart7: serial@2870000 {
@@ -150,6 +176,7 @@
clocks = <&k3_clks 356 3>;
clock-names = "fclk";
power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart8: serial@2880000 {
@@ -160,6 +187,7 @@
clocks = <&k3_clks 357 3>;
clock-names = "fclk";
power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart9: serial@2890000 {
@@ -170,6 +198,7 @@
clocks = <&k3_clks 358 3>;
clock-names = "fclk";
power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_gpio0: gpio@600000 {
@@ -256,6 +285,7 @@
clocks = <&k3_clks 215 1>;
clock-names = "fck";
power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c2: i2c@2020000 {
@@ -267,6 +297,7 @@
clocks = <&k3_clks 216 1>;
clock-names = "fck";
power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c3: i2c@2030000 {
@@ -278,6 +309,7 @@
clocks = <&k3_clks 217 1>;
clock-names = "fck";
power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c4: i2c@2040000 {
@@ -289,6 +321,7 @@
clocks = <&k3_clks 218 1>;
clock-names = "fck";
power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c5: i2c@2050000 {
@@ -300,6 +333,7 @@
clocks = <&k3_clks 219 1>;
clock-names = "fck";
power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c6: i2c@2060000 {
@@ -311,6 +345,7 @@
clocks = <&k3_clks 220 1>;
clock-names = "fck";
power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_sdhci0: mmc@4f80000 {
@@ -428,6 +463,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster1: mailbox@31f81000 {
@@ -437,6 +473,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster2: mailbox@31f82000 {
@@ -446,6 +483,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster3: mailbox@31f83000 {
@@ -455,6 +493,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster4: mailbox@31f84000 {
@@ -464,6 +503,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster5: mailbox@31f85000 {
@@ -473,6 +513,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster6: mailbox@31f86000 {
@@ -482,6 +523,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster7: mailbox@31f87000 {
@@ -491,6 +533,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster8: mailbox@31f88000 {
@@ -500,6 +543,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster9: mailbox@31f89000 {
@@ -509,6 +553,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster10: mailbox@31f8a000 {
@@ -518,6 +563,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster11: mailbox@31f8b000 {
@@ -527,6 +573,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster0: mailbox@31f90000 {
@@ -536,6 +583,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster1: mailbox@31f91000 {
@@ -545,6 +593,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster2: mailbox@31f92000 {
@@ -554,6 +603,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster3: mailbox@31f93000 {
@@ -563,6 +613,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster4: mailbox@31f94000 {
@@ -572,6 +623,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster5: mailbox@31f95000 {
@@ -581,6 +633,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster6: mailbox@31f96000 {
@@ -590,6 +643,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster7: mailbox@31f97000 {
@@ -599,6 +653,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster8: mailbox@31f98000 {
@@ -608,6 +663,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster9: mailbox@31f99000 {
@@ -617,6 +673,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster10: mailbox@31f9a000 {
@@ -626,6 +683,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
mailbox1_cluster11: mailbox@31f9b000 {
@@ -635,6 +693,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
};
main_ringacc: ringacc@3c000000 {
@@ -698,6 +757,7 @@
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan1: can@2711000 {
@@ -712,6 +772,7 @@
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan2: can@2721000 {
@@ -726,6 +787,7 @@
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan3: can@2731000 {
@@ -740,6 +802,7 @@
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan4: can@2741000 {
@@ -754,6 +817,7 @@
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan5: can@2751000 {
@@ -768,6 +832,7 @@
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan6: can@2761000 {
@@ -782,6 +847,7 @@
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan7: can@2771000 {
@@ -796,6 +862,7 @@
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan8: can@2781000 {
@@ -810,6 +877,7 @@
<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan9: can@2791000 {
@@ -824,6 +892,7 @@
<GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan10: can@27a1000 {
@@ -838,6 +907,7 @@
<GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan11: can@27b1000 {
@@ -852,6 +922,7 @@
<GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan12: can@27c1000 {
@@ -866,6 +937,7 @@
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan13: can@27d1000 {
@@ -880,6 +952,7 @@
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan14: can@2681000 {
@@ -894,6 +967,7 @@
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan15: can@2691000 {
@@ -908,6 +982,7 @@
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan16: can@26a1000 {
@@ -922,6 +997,7 @@
<GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
main_mcan17: can@26b1000 {
@@ -936,5 +1012,6 @@
<GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index 4d1bfabd1313..0af242aa9816 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -65,7 +65,7 @@
#interrupt-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <125>;
- ti,interrupt-ranges = <16 928 16>;
+ ti,interrupt-ranges = <16 960 16>;
};
mcu_conf: syscon@40f00000 {
@@ -91,6 +91,7 @@
clocks = <&k3_clks 359 3>;
clock-names = "fclk";
power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_uart0: serial@40a00000 {
@@ -101,6 +102,7 @@
clocks = <&k3_clks 149 3>;
clock-names = "fclk";
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
wkup_gpio0: gpio@42110000 {
@@ -144,6 +146,7 @@
clocks = <&k3_clks 223 1>;
clock-names = "fck";
power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_i2c0: i2c@40b00000 {
@@ -155,6 +158,7 @@
clocks = <&k3_clks 221 1>;
clock-names = "fck";
power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_i2c1: i2c@40b10000 {
@@ -166,6 +170,7 @@
clocks = <&k3_clks 222 1>;
clock-names = "fck";
power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_mcan0: can@40528000 {
@@ -180,6 +185,7 @@
<GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
mcu_mcan1: can@40568000 {
@@ -194,6 +200,7 @@
<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
mcu_navss: bus@28380000{
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
index 76f0ceacb6d4..6930efff8a5a 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
@@ -56,6 +56,7 @@
};
&main_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
@@ -73,103 +74,8 @@
};
&main_mcan16 {
+ status = "okay";
pinctrl-0 = <&main_mcan16_pins_default>;
pinctrl-names = "default";
phys = <&transceiver0>;
};
-
-&mailbox0_cluster0 {
- status = "disabled";
-};
-
-&mailbox0_cluster1 {
- status = "disabled";
-};
-
-&mailbox0_cluster2 {
- status = "disabled";
-};
-
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
-&mailbox0_cluster4 {
- status = "disabled";
-};
-
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
-&mailbox1_cluster0 {
- status = "disabled";
-};
-
-&mailbox1_cluster1 {
- status = "disabled";
-};
-
-&mailbox1_cluster2 {
- status = "disabled";
-};
-
-&mailbox1_cluster3 {
- status = "disabled";
-};
-
-&mailbox1_cluster4 {
- status = "disabled";
-};
-
-&mailbox1_cluster5 {
- status = "disabled";
-};
-
-&mailbox1_cluster6 {
- status = "disabled";
-};
-
-&mailbox1_cluster7 {
- status = "disabled";
-};
-
-&mailbox1_cluster8 {
- status = "disabled";
-};
-
-&mailbox1_cluster9 {
- status = "disabled";
-};
-
-&mailbox1_cluster10 {
- status = "disabled";
-};
-
-&mailbox1_cluster11 {
- status = "disabled";
-};