diff options
Diffstat (limited to 'arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso')
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 28 |
1 files changed, 19 insertions, 9 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index b610e65e0cdf..603839c82599 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -2,14 +2,15 @@ /* * dts file for KV260 revA Carrier Card * - * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2020 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * SD level shifter: - * "A" – A01 board un-modified (NXP) - * "Y" – A01 board modified with legacy interposer (Nexperia) - * "Z" – A01 board modified with Diode interposer + * "A" - A01 board un-modified (NXP) + * "Y" - A01 board modified with legacy interposer (Nexperia) + * "Z" - A01 board modified with Diode interposer * - * Michal Simek <michal.simek@xilinx.com> + * Michal Simek <michal.simek@amd.com> */ #include <dt-bindings/gpio/gpio.h> @@ -95,13 +96,15 @@ }; &zynqmp_dpsub { - status = "disabled"; + status = "okay"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; }; &zynqmp_dpdma { status = "okay"; + assigned-clock-rates = <600000000>; }; &usb0 { @@ -132,6 +135,8 @@ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; + assigned-clock-rates = <187498123>; + bus-width = <4>; }; &gem3 { /* required by spec */ @@ -144,16 +149,18 @@ mdio: mdio { #address-cells = <1>; #size-cells = <0>; - reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - reset-delay-us = <2>; phy0: ethernet-phy@1 { #phy-cells = <1>; reg = <1>; + compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <100>; + reset-deassert-us = <280>; + reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; }; }; }; @@ -259,19 +266,22 @@ pinctrl_usb0_default: usb0-default { conf { groups = "usb0_0_grp"; - slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = <SLEW_RATE_FAST>; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = <SLEW_RATE_SLOW>; }; mux { |