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Diffstat (limited to 'arch/arm64/boot/dts/renesas/r9a08g045.dtsi')
-rw-r--r--arch/arm64/boot/dts/renesas/r9a08g045.dtsi266
1 files changed, 265 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index be8a0a768c65..0364f89776e6 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -14,6 +14,47 @@
#address-cells = <2>;
#size-cells = <2>;
+ audio_clk1: audio1-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it. */
+ clock-frequency = <0>;
+ };
+
+ audio_clk2: audio2-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it. */
+ clock-frequency = <0>;
+ };
+
+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-137500000 {
+ opp-hz = /bits/ 64 <137500000>;
+ opp-microvolt = <940000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-275000000 {
+ opp-hz = /bits/ 64 <275000000>;
+ opp-microvolt = <940000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ opp-microvolt = <940000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-microvolt = <940000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -26,6 +67,7 @@
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
+ operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {
@@ -73,6 +115,96 @@
status = "disabled";
};
+ scif1: serial@1004bc00 {
+ compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+ reg = <0 0x1004bc00 0 0x400>;
+ interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A08G045_SCIF1_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_SCIF1_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif2: serial@1004c000 {
+ compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+ reg = <0 0x1004c000 0 0x400>;
+ interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A08G045_SCIF2_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_SCIF2_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif3: serial@1004c400 {
+ compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+ reg = <0 0x1004c400 0 0x400>;
+ interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A08G045_SCIF3_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_SCIF3_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif4: serial@1004c800 {
+ compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+ reg = <0 0x1004c800 0 0x400>;
+ interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A08G045_SCIF4_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_SCIF4_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif5: serial@1004e000 {
+ compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+ reg = <0 0x1004e000 0 0x400>;
+ interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A08G045_SCIF5_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_SCIF5_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
rtc: rtc@1004ec00 {
compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3";
reg = <0 0x1004ec00 0 0x400>;
@@ -87,6 +219,59 @@
status = "disabled";
};
+ adc: adc@10058000 {
+ compatible = "renesas,r9a08g045-adc";
+ reg = <0 0x10058000 0 0x1000>;
+ interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&cpg CPG_MOD R9A08G045_ADC_ADCLK>,
+ <&cpg CPG_MOD R9A08G045_ADC_PCLK>;
+ clock-names = "adclk", "pclk";
+ resets = <&cpg R9A08G045_ADC_PRESETN>,
+ <&cpg R9A08G045_ADC_ADRST_N>;
+ reset-names = "presetn", "adrst-n";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ status = "disabled";
+
+ channel@0 {
+ reg = <0>;
+ };
+
+ channel@1 {
+ reg = <1>;
+ };
+
+ channel@2 {
+ reg = <2>;
+ };
+
+ channel@3 {
+ reg = <3>;
+ };
+
+ channel@4 {
+ reg = <4>;
+ };
+
+ channel@5 {
+ reg = <5>;
+ };
+
+ channel@6 {
+ reg = <6>;
+ };
+
+ channel@7 {
+ reg = <7>;
+ };
+
+ channel@8 {
+ reg = <8>;
+ };
+ };
+
vbattb: clock-controller@1005c000 {
compatible = "renesas,r9a08g045-vbattb";
reg = <0 0x1005c000 0 0x1000>;
@@ -187,6 +372,86 @@
status = "disabled";
};
+ ssi0: ssi@100a8000 {
+ compatible = "renesas,r9a08g045-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x100a8000 0 0x400>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx";
+ clocks = <&cpg CPG_MOD R9A08G045_SSI0_PCLK2>,
+ <&cpg CPG_MOD R9A08G045_SSI0_PCLK_SFR>,
+ <&audio_clk1>, <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A08G045_SSI0_RST_M2_REG>;
+ dmas = <&dmac 0x2665>, <&dmac 0x2666>;
+ dma-names = "tx", "rx";
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ ssi1: ssi@100a8400 {
+ compatible = "renesas,r9a08g045-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x100a8400 0 0x400>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx";
+ clocks = <&cpg CPG_MOD R9A08G045_SSI1_PCLK2>,
+ <&cpg CPG_MOD R9A08G045_SSI1_PCLK_SFR>,
+ <&audio_clk1>, <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A08G045_SSI1_RST_M2_REG>;
+ dmas = <&dmac 0x2669>, <&dmac 0x266a>;
+ dma-names = "tx", "rx";
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ ssi2: ssi@100a8800 {
+ compatible = "renesas,r9a08g045-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x100a8800 0 0x400>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx";
+ clocks = <&cpg CPG_MOD R9A08G045_SSI2_PCLK2>,
+ <&cpg CPG_MOD R9A08G045_SSI2_PCLK_SFR>,
+ <&audio_clk1>, <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A08G045_SSI2_RST_M2_REG>;
+ dmas = <&dmac 0x266d>, <&dmac 0x266e>;
+ dma-names = "tx", "rx";
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ ssi3: ssi@100a8c00 {
+ compatible = "renesas,r9a08g045-ssi",
+ "renesas,rz-ssi";
+ reg = <0 0x100a8c00 0 0x400>;
+ interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "int_req", "dma_rx", "dma_tx";
+ clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>,
+ <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>,
+ <&audio_clk1>, <&audio_clk2>;
+ clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+ resets = <&cpg R9A08G045_SSI3_RST_M2_REG>;
+ dmas = <&dmac 0x2671>, <&dmac 0x2672>;
+ dma-names = "tx", "rx";
+ power-domains = <&cpg>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
cpg: clock-controller@11010000 {
compatible = "renesas,r9a08g045-cpg";
reg = <0 0x11010000 0 0x10000>;
@@ -206,7 +471,6 @@
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "lpm_int", "ca55stbydone_int",
"cm33stbyr_int", "ca55_deny";
- status = "disabled";
};
pinctrl: pinctrl@11030000 {
generated by cgit v1.2.3 (git 2.39.0) at 2025-08-12 01:43:53 +0300