summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/qcom/x1e80100.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm64/boot/dts/qcom/x1e80100.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/x1e80100.dtsi3447
1 files changed, 2619 insertions, 828 deletions
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 7e4f46ad8edd..a9a7bb676c6f 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -20,6 +20,7 @@
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@@ -38,7 +39,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
- clock-frequency = <32000>;
+ clock-frequency = <32764>;
#clock-cells = <0>;
};
@@ -71,8 +72,8 @@
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2_0>;
- power-domains = <&cpu_pd0>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&cluster_c4>;
l2_0: l2-cache {
@@ -88,8 +89,8 @@
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&l2_0>;
- power-domains = <&cpu_pd1>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd1>, <&scmi_dvfs 0>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&cluster_c4>;
};
@@ -99,8 +100,8 @@
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&l2_0>;
- power-domains = <&cpu_pd2>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd2>, <&scmi_dvfs 0>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&cluster_c4>;
};
@@ -110,8 +111,8 @@
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&l2_0>;
- power-domains = <&cpu_pd3>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd3>, <&scmi_dvfs 0>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&cluster_c4>;
};
@@ -121,8 +122,8 @@
reg = <0x0 0x10000>;
enable-method = "psci";
next-level-cache = <&l2_1>;
- power-domains = <&cpu_pd4>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd4>, <&scmi_dvfs 1>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&cluster_c4>;
l2_1: l2-cache {
@@ -138,8 +139,8 @@
reg = <0x0 0x10100>;
enable-method = "psci";
next-level-cache = <&l2_1>;
- power-domains = <&cpu_pd5>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd5>, <&scmi_dvfs 1>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&cluster_c4>;
};
@@ -149,8 +150,8 @@
reg = <0x0 0x10200>;
enable-method = "psci";
next-level-cache = <&l2_1>;
- power-domains = <&cpu_pd6>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd6>, <&scmi_dvfs 1>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&cluster_c4>;
};
@@ -160,8 +161,8 @@
reg = <0x0 0x10300>;
enable-method = "psci";
next-level-cache = <&l2_1>;
- power-domains = <&cpu_pd7>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd7>, <&scmi_dvfs 1>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&cluster_c4>;
};
@@ -171,8 +172,8 @@
reg = <0x0 0x20000>;
enable-method = "psci";
next-level-cache = <&l2_2>;
- power-domains = <&cpu_pd8>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd8>, <&scmi_dvfs 2>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&cluster_c4>;
l2_2: l2-cache {
@@ -188,8 +189,8 @@
reg = <0x0 0x20100>;
enable-method = "psci";
next-level-cache = <&l2_2>;
- power-domains = <&cpu_pd9>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd9>, <&scmi_dvfs 2>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&cluster_c4>;
};
@@ -199,8 +200,8 @@
reg = <0x0 0x20200>;
enable-method = "psci";
next-level-cache = <&l2_2>;
- power-domains = <&cpu_pd10>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd10>, <&scmi_dvfs 2>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&cluster_c4>;
};
@@ -210,8 +211,8 @@
reg = <0x0 0x20300>;
enable-method = "psci";
next-level-cache = <&l2_2>;
- power-domains = <&cpu_pd11>;
- power-domain-names = "psci";
+ power-domains = <&cpu_pd11>, <&scmi_dvfs 2>;
+ power-domain-names = "psci", "perf";
cpu-idle-states = <&cluster_c4>;
};
@@ -252,7 +253,7 @@
};
};
- cluster2 {
+ cpu_map_cluster2: cluster2 {
core0 {
cpu = <&cpu8>;
};
@@ -303,6 +304,18 @@
};
};
+ dummy-sink {
+ compatible = "arm,coresight-dummy-sink";
+
+ in-ports {
+ port {
+ eud_in: endpoint {
+ remote-endpoint = <&swao_rep_out1>;
+ };
+ };
+ };
+ };
+
firmware {
scm: scm {
compatible = "qcom,scm-x1e80100", "qcom,scm";
@@ -310,6 +323,21 @@
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
qcom,dload-mode = <&tcsr 0x19000>;
};
+
+ scmi {
+ compatible = "arm,scmi";
+ mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>;
+ mbox-names = "tx", "rx";
+ shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_dvfs: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+ };
};
clk_virt: interconnect-0 {
@@ -677,6 +705,34 @@
};
};
+ qup_opp_table_100mhz: opp-table-qup100mhz {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+ };
+
+ qup_opp_table_120mhz: opp-table-qup120mhz {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-120000000 {
+ opp-hz = /bits/ 64 <120000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+ };
+
smp2p-adsp {
compatible = "qcom,smp2p";
@@ -743,7 +799,7 @@
clocks = <&bi_tcxo_div2>,
<&sleep_clk>,
- <0>,
+ <&pcie3_phy>,
<&pcie4_phy>,
<&pcie5_phy>,
<&pcie6a_phy>,
@@ -823,14 +879,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
<&gpi_dma2 1 0 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -856,14 +915,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_120mhz>;
+
dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
<&gpi_dma2 1 0 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -889,14 +951,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
<&gpi_dma2 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -922,14 +987,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_120mhz>;
+
dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
<&gpi_dma2 1 1 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -955,14 +1023,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
<&gpi_dma2 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -988,14 +1059,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
<&gpi_dma2 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1021,14 +1095,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
<&gpi_dma2 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1054,14 +1131,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
<&gpi_dma2 1 3 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1087,14 +1167,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
<&gpi_dma2 1 4 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1120,14 +1203,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
<&gpi_dma2 1 4 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1153,14 +1239,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
<&gpi_dma2 1 5 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1186,14 +1275,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
<&gpi_dma2 1 5 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1219,11 +1311,14 @@
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "qup-core",
"qup-config";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
pinctrl-0 = <&qup_uart21_default>;
pinctrl-names = "default";
@@ -1241,14 +1336,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
<&gpi_dma2 1 6 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1274,14 +1372,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
<&gpi_dma2 1 6 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1307,14 +1408,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
<&gpi_dma2 1 7 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1340,14 +1444,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
<&gpi_dma2 1 7 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1417,14 +1524,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1450,14 +1560,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_120mhz>;
+
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1483,14 +1596,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1516,14 +1632,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_120mhz>;
+
dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
<&gpi_dma1 1 1 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1549,14 +1668,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1582,14 +1704,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1615,14 +1740,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1648,14 +1776,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1681,14 +1812,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1714,14 +1848,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
<&gpi_dma1 1 4 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1747,14 +1884,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
<&gpi_dma1 1 5 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1780,14 +1920,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
<&gpi_dma1 1 5 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1813,14 +1956,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
<&gpi_dma1 1 6 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1846,14 +1992,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
<&gpi_dma1 1 6 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1868,6 +2017,31 @@
status = "disabled";
};
+ uart14: serial@a98000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a98000 0 0x4000>;
+
+ interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
+ pinctrl-0 = <&qup_uart14_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
i2c15: i2c@a9c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a9c000 0 0x4000>;
@@ -1879,14 +2053,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
<&gpi_dma1 1 7 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -1912,14 +2089,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
<&gpi_dma1 1 7 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -1988,14 +2168,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -2021,14 +2204,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_120mhz>;
+
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -2054,14 +2240,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -2087,14 +2276,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_120mhz>;
+
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -2120,14 +2312,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -2153,11 +2348,14 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "qup-core",
"qup-config";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
pinctrl-0 = <&qup_uart2_default>;
pinctrl-names = "default";
@@ -2175,14 +2373,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -2208,14 +2409,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -2241,14 +2445,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
<&gpi_dma0 1 3 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -2274,14 +2481,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -2307,14 +2517,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
<&gpi_dma0 1 4 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -2340,14 +2553,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -2373,14 +2589,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
<&gpi_dma0 1 5 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -2406,14 +2625,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
<&gpi_dma0 1 6 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -2439,14 +2661,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
<&gpi_dma0 1 6 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -2472,14 +2697,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
<&gpi_dma0 1 7 QCOM_GPI_I2C>;
dma-names = "tx",
@@ -2505,14 +2733,17 @@
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
+
dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
<&gpi_dma0 1 7 QCOM_GPI_SPI>;
dma-names = "tx",
@@ -2906,6 +3137,212 @@
#interconnect-cells = <2>;
};
+ pcie3: pcie@1bd0000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-x1e80100";
+ reg = <0x0 0x01bd0000 0x0 0x3000>,
+ <0x0 0x78000000 0x0 0xf20>,
+ <0x0 0x78000f40 0x0 0xa8>,
+ <0x0 0x78001000 0x0 0x1000>,
+ <0x0 0x78100000 0x0 0x100000>,
+ <0x0 0x01bd3000 0x0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>,
+ <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>,
+ <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>;
+ bus-range = <0x00 0xff>;
+
+ dma-coherent;
+
+ linux,pci-domain = <3>;
+ num-lanes = <8>;
+
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_3_AUX_CLK>,
+ <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_3_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
+ <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "noc_aggr",
+ "cnoc_sf_axi";
+
+ assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&pcie_north_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_3_BCR>,
+ <&gcc GCC_PCIE_3_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
+
+ power-domains = <&gcc GCC_PCIE_3_GDSC>;
+
+ phys = <&pcie3_phy>;
+ phy-names = "pciephy";
+
+ eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555
+ 0x5555 0x5555 0x5555 0x5555>;
+ eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>;
+
+ operating-points-v2 = <&pcie3_opp_table>;
+
+ status = "disabled";
+
+ pcie3_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* GEN 1 x1 */
+ opp-2500000 {
+ opp-hz = /bits/ 64 <2500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <250000 1>;
+ };
+
+ /* GEN 1 x2 and GEN 2 x1 */
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <500000 1>;
+ };
+
+ /* GEN 1 x4 and GEN 2 x2 */
+ opp-10000000 {
+ opp-hz = /bits/ 64 <10000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1000000 1>;
+ };
+
+ /* GEN 1 x8 and GEN 2 x4 */
+ opp-20000000 {
+ opp-hz = /bits/ 64 <20000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <2000000 1>;
+ };
+
+ /* GEN 2 x8 */
+ opp-40000000 {
+ opp-hz = /bits/ 64 <40000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <4000000 1>;
+ };
+
+ /* GEN 3 x1 */
+ opp-8000000 {
+ opp-hz = /bits/ 64 <8000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ opp-peak-kBps = <984500 1>;
+ };
+
+ /* GEN 3 x2 and GEN 4 x1 */
+ opp-16000000 {
+ opp-hz = /bits/ 64 <16000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ opp-peak-kBps = <1969000 1>;
+ };
+
+ /* GEN 3 x4 and GEN 4 x2 */
+ opp-32000000 {
+ opp-hz = /bits/ 64 <32000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ opp-peak-kBps = <3938000 1>;
+ };
+
+ /* GEN 3 x8 and GEN 4 x4 */
+ opp-64000000 {
+ opp-hz = /bits/ 64 <64000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ opp-peak-kBps = <7876000 1>;
+ };
+
+ /* GEN 4 x8 */
+ opp-128000000 {
+ opp-hz = /bits/ 64 <128000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ opp-peak-kBps = <15753000 1>;
+ };
+ };
+ };
+
+ pcie3_phy: phy@1be0000 {
+ compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
+ reg = <0 0x01be0000 0 0x10000>;
+
+ clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
+ <&tcsr TCSR_PCIE_8L_CLKREF_EN>,
+ <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_3_PIPE_CLK>,
+ <&gcc GCC_PCIE_3_PIPEDIV2_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe",
+ "pipediv2";
+
+ resets = <&gcc GCC_PCIE_3_PHY_BCR>,
+ <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>;
+ reset-names = "phy",
+ "phy_nocsr";
+
+ assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie3_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
pcie6a: pci@1bf8000 {
device_type = "pci";
compatible = "qcom,pcie-x1e80100";
@@ -2941,7 +3378,8 @@
<GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
@@ -2949,7 +3387,8 @@
"msi4",
"msi5",
"msi6",
- "msi7";
+ "msi7",
+ "global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
@@ -2978,8 +3417,8 @@
interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>;
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "pcie-mem",
"cpu-pcie";
@@ -2994,6 +3433,9 @@
phys = <&pcie6a_phy>;
phy-names = "pciephy";
+ eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
+ eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
+
status = "disabled";
};
@@ -3068,7 +3510,8 @@
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
@@ -3076,7 +3519,8 @@
"msi4",
"msi5",
"msi6",
- "msi7";
+ "msi7",
+ "global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
@@ -3105,8 +3549,8 @@
interconnects = <&pcie_north_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>;
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "pcie-mem",
"cpu-pcie";
@@ -3121,6 +3565,8 @@
phys = <&pcie5_phy>;
phy-names = "pciephy";
+ eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
+
status = "disabled";
};
@@ -3141,8 +3587,10 @@
"pipe",
"pipediv2";
- resets = <&gcc GCC_PCIE_5_PHY_BCR>;
- reset-names = "phy";
+ resets = <&gcc GCC_PCIE_5_PHY_BCR>,
+ <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>;
+ reset-names = "phy",
+ "phy_nocsr";
assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
@@ -3192,7 +3640,8 @@
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
@@ -3200,7 +3649,8 @@
"msi4",
"msi5",
"msi6",
- "msi7";
+ "msi7",
+ "global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
@@ -3229,8 +3679,8 @@
interconnects = <&pcie_north_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>;
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "pcie-mem",
"cpu-pcie";
@@ -3245,6 +3695,8 @@
phys = <&pcie4_phy>;
phy-names = "pciephy";
+ eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
+
status = "disabled";
pcie4_port0: pcie@0 {
@@ -3275,8 +3727,10 @@
"pipe",
"pipediv2";
- resets = <&gcc GCC_PCIE_4_PHY_BCR>;
- reset-names = "phy";
+ resets = <&gcc GCC_PCIE_4_PHY_BCR>,
+ <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>;
+ reset-names = "phy",
+ "phy_nocsr";
assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
@@ -3330,65 +3784,88 @@
status = "disabled";
- zap-shader {
+ gpu_zap_shader: zap-shader {
memory-region = <&gpu_microcode_mem>;
};
gpu_opp_table: opp-table {
- compatible = "operating-points-v2";
+ compatible = "operating-points-v2-adreno", "operating-points-v2";
+
+ opp-1250000000 {
+ opp-hz = /bits/ 64 <1250000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
+ opp-peak-kBps = <16500000>;
+ qcom,opp-acd-level = <0xa82a5ffd>;
+ };
+
+ opp-1175000000 {
+ opp-hz = /bits/ 64 <1175000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
+ opp-peak-kBps = <14398438>;
+ qcom,opp-acd-level = <0xa82a5ffd>;
+ };
opp-1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
- opp-peak-kBps = <16500000>;
+ opp-peak-kBps = <14398438>;
+ qcom,opp-acd-level = <0xa82a5ffd>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
opp-peak-kBps = <14398438>;
+ qcom,opp-acd-level = <0xa82b5ffd>;
};
opp-925000000 {
opp-hz = /bits/ 64 <925000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
opp-peak-kBps = <14398438>;
+ qcom,opp-acd-level = <0xa82b5ffd>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
opp-peak-kBps = <12449219>;
+ qcom,opp-acd-level = <0xa82c5ffd>;
};
opp-744000000 {
opp-hz = /bits/ 64 <744000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
opp-peak-kBps = <10687500>;
+ qcom,opp-acd-level = <0x882e5ffd>;
};
opp-687000000 {
opp-hz = /bits/ 64 <687000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <8171875>;
+ qcom,opp-acd-level = <0x882e5ffd>;
};
opp-550000000 {
opp-hz = /bits/ 64 <550000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <6074219>;
+ qcom,opp-acd-level = <0xc0285ffd>;
};
opp-390000000 {
opp-hz = /bits/ 64 <390000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-peak-kBps = <3000000>;
+ qcom,opp-acd-level = <0xc0285ffd>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
opp-peak-kBps = <2136719>;
+ qcom,opp-acd-level = <0xc02b5ffd>;
};
};
};
@@ -3518,6 +3995,143 @@
#interconnect-cells = <2>;
};
+ remoteproc_adsp: remoteproc@6800000 {
+ compatible = "qcom,x1e80100-adsp-pas";
+ reg = <0x0 0x06800000 0x0 0x10000>;
+
+ interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_LCX>,
+ <&rpmhpd RPMHPD_LMX>;
+ power-domain-names = "lcx",
+ "lmx";
+
+ interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ memory-region = <&adspslpi_mem>,
+ <&q6_adsp_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_adsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "lpass";
+ qcom,remote-pid = <2>;
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "adsp";
+ qcom,non-secure-domain;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x1003 0x80>,
+ <&apps_smmu 0x1063 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu 0x1004 0x80>,
+ <&apps_smmu 0x1064 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu 0x1005 0x80>,
+ <&apps_smmu 0x1065 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&apps_smmu 0x1006 0x80>,
+ <&apps_smmu 0x1066 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+ iommus = <&apps_smmu 0x1007 0x80>,
+ <&apps_smmu 0x1067 0x0>;
+ dma-coherent;
+ };
+ };
+
+ gpr {
+ compatible = "qcom,gpr";
+ qcom,glink-channels = "adsp_apps";
+ qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+ qcom,intents = <512 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ q6apm: service@1 {
+ compatible = "qcom,q6apm";
+ reg = <GPR_APM_MODULE_IID>;
+ #sound-dai-cells = <0>;
+ qcom,protection-domain = "avs/audio",
+ "msm/adsp/audio_pd";
+
+ q6apmbedai: bedais {
+ compatible = "qcom,q6apm-lpass-dais";
+ #sound-dai-cells = <1>;
+ };
+
+ q6apmdai: dais {
+ compatible = "qcom,q6apm-dais";
+ iommus = <&apps_smmu 0x1001 0x80>,
+ <&apps_smmu 0x1061 0x0>;
+ };
+ };
+
+ q6prm: service@2 {
+ compatible = "qcom,q6prm";
+ reg = <GPR_PRM_MODULE_IID>;
+ qcom,protection-domain = "avs/audio",
+ "msm/adsp/audio_pd";
+
+ q6prmcc: clock-controller {
+ compatible = "qcom,q6prm-lpass-clocks";
+ #clock-cells = <2>;
+ };
+ };
+ };
+ };
+ };
+
lpass_wsa2macro: codec@6aa0000 {
compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
reg = <0 0x06aa0000 0 0x1000>;
@@ -3892,6 +4506,112 @@
#interconnect-cells = <2>;
};
+ sdhc_2: mmc@8804000 {
+ compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0 0x08804000 0 0x1000>;
+
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "core", "xo";
+ iommus = <&apps_smmu 0x520 0>;
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+
+ interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "sdhc-ddr", "cpu-sdhc";
+ bus-width = <4>;
+ dma-coherent;
+
+ status = "disabled";
+
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ sdhc_4: mmc@8844000 {
+ compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0 0x08844000 0 0x1000>;
+
+ interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC4_AHB_CLK>,
+ <&gcc GCC_SDCC4_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "core", "xo";
+ iommus = <&apps_smmu 0x160 0>;
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc4_opp_table>;
+
+ interconnects = <&aggre2_noc MASTER_SDCC_4 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_SDCC_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "sdhc-ddr", "cpu-sdhc";
+ bus-width = <4>;
+ dma-coherent;
+
+ status = "disabled";
+
+ sdhc4_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
usb_2_hsphy: phy@88e0000 {
compatible = "qcom,x1e80100-snps-eusb2-phy",
"qcom,sm8550-snps-eusb2-phy";
@@ -4034,8 +4754,8 @@
interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ALWAYS>;
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "usb-ddr",
"apps-usb";
@@ -4063,6 +4783,8 @@
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,usb3_lpm_capable;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
dma-coherent;
@@ -4118,7 +4840,7 @@
<&gcc GCC_USB20_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 50 IRQ_TYPE_EDGE_BOTH>,
<&pdc 49 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "pwr_event",
@@ -4132,8 +4854,8 @@
interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>;
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "usb-ddr",
"apps-usb";
@@ -4144,11 +4866,15 @@
usb_2_dwc3: usb@a200000 {
compatible = "snps,dwc3";
reg = <0 0x0a200000 0 0xcd00>;
- interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0x14e0 0x0>;
phys = <&usb_2_hsphy>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+
+ dma-coherent;
ports {
#address-cells = <1>;
@@ -4215,8 +4941,8 @@
interconnects = <&usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ALWAYS>;
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "usb-ddr",
"apps-usb";
@@ -4245,6 +4971,8 @@
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,usb3_lpm_capable;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
dma-coherent;
};
@@ -4316,6 +5044,8 @@
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,usb3_lpm_capable;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
dma-coherent;
@@ -4385,8 +5115,8 @@
interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
- <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
- &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>;
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "usb-ddr",
"apps-usb";
@@ -4414,6 +5144,8 @@
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,usb3_lpm_capable;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
dma-coherent;
@@ -5629,6 +6361,34 @@
};
};
+ qup_uart14_default: qup-uart14-default-state {
+ cts-pins {
+ pins = "gpio56";
+ function = "qup1_se6";
+ bias-bus-hold;
+ };
+
+ rts-pins {
+ pins = "gpio57";
+ function = "qup1_se6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tx-pins {
+ pins = "gpio58";
+ function = "qup1_se6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx-pins {
+ pins = "gpio59";
+ function = "qup1_se6";
+ bias-pull-up;
+ };
+ };
+
qup_uart21_default: qup-uart21-default-state {
tx-pins {
pins = "gpio86";
@@ -5644,6 +6404,1487 @@
bias-disable;
};
};
+
+ sdc2_default: sdc2-default-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_sleep: sdc2-sleep-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ stm@10002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0x0 0x10002000 0x0 0x1000>,
+ <0x0 0x16280000 0x0 0x180000>;
+ reg-names = "stm-base",
+ "stm-stimulus-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint = <&funnel0_in7>;
+ };
+ };
+ };
+ };
+
+ tpdm@10003000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10003000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+ status = "disabled";
+
+ out-ports {
+ port {
+ dcc_tpdm_out: endpoint {
+ remote-endpoint = <&qdss_tpda_in0>;
+ };
+ };
+ };
+ };
+
+ tpda@10004000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10004000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ qdss_tpda_in0: endpoint {
+ remote-endpoint = <&dcc_tpdm_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ qdss_tpda_in1: endpoint {
+ remote-endpoint = <&qdss_tpdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ qdss_tpda_out: endpoint {
+ remote-endpoint = <&funnel0_in6>;
+ };
+ };
+ };
+ };
+
+ tpdm@1000f000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1000f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ qdss_tpdm_out: endpoint {
+ remote-endpoint = <&qdss_tpda_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@10041000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10041000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@6 {
+ reg = <6>;
+
+ funnel0_in6: endpoint {
+ remote-endpoint = <&qdss_tpda_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+
+ funnel0_in7: endpoint {
+ remote-endpoint = <&stm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel0_out: endpoint {
+ remote-endpoint = <&qdss_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@10042000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10042000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ funnel1_in2: endpoint {
+ remote-endpoint = <&tmess_funnel_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ funnel1_in5: endpoint {
+ remote-endpoint = <&dlst_funnel_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+
+ funnel1_in6: endpoint {
+ remote-endpoint = <&dlct1_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel1_out: endpoint {
+ remote-endpoint = <&qdss_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@10045000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10045000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ qdss_funnel_in0: endpoint {
+ remote-endpoint = <&funnel0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ qdss_funnel_in1: endpoint {
+ remote-endpoint = <&funnel1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ qdss_funnel_out: endpoint {
+ remote-endpoint = <&aoss_funnel_in7>;
+ };
+ };
+ };
+ };
+
+ tpdm@10800000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10800000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ mxa_tpdm_out: endpoint {
+ remote-endpoint = <&dlct2_tpda_in15>;
+ };
+ };
+ };
+ };
+
+ tpdm@1082c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1082c000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ gcc_tpdm_out: endpoint {
+ remote-endpoint = <&dlct1_tpda_in21>;
+ };
+ };
+ };
+ };
+
+ tpdm@10841000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10841000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ prng_tpdm_out: endpoint {
+ remote-endpoint = <&dlct1_tpda_in19>;
+ };
+ };
+ };
+ };
+
+ tpdm@10844000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10844000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ lpass_cx_tpdm_out: endpoint {
+ remote-endpoint = <&lpass_cx_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@10846000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10846000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ lpass_cx_funnel_in0: endpoint {
+ remote-endpoint = <&lpass_cx_tpdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ lpass_cx_funnel_out: endpoint {
+ remote-endpoint = <&dlct1_tpda_in4>;
+ };
+ };
+ };
+ };
+
+ cti@1098b000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x1098b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ };
+
+ tpdm@109d0000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x109d0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+ status = "disabled";
+
+ out-ports {
+ port {
+ qm_tpdm_out: endpoint {
+ remote-endpoint = <&dlct1_tpda_in20>;
+ };
+ };
+ };
+ };
+
+ tpdm@10ac0000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10ac0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+ status = "disabled";
+
+ out-ports {
+ port {
+ dlst_tpdm0_out: endpoint {
+ remote-endpoint = <&dlst_tpda_in8>;
+ };
+ };
+ };
+ };
+
+ tpdm@10ac1000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10ac1000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ dlst_tpdm1_out: endpoint {
+ remote-endpoint = <&dlst_tpda_in9>;
+ };
+ };
+ };
+ };
+
+ tpda@10ac4000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10ac4000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@8 {
+ reg = <8>;
+
+ dlst_tpda_in8: endpoint {
+ remote-endpoint = <&dlst_tpdm0_out>;
+ };
+ };
+
+ port@9 {
+ reg = <9>;
+
+ dlst_tpda_in9: endpoint {
+ remote-endpoint = <&dlst_tpdm1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ dlst_tpda_out: endpoint {
+ remote-endpoint = <&dlst_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@10ac5000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10ac5000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ dlst_funnel_in0: endpoint {
+ remote-endpoint = <&dlst_tpda_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ dlst_funnel_out: endpoint {
+ remote-endpoint = <&funnel1_in5>;
+ };
+ };
+ };
+ };
+
+ funnel@10b04000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10b04000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@3 {
+ reg = <3>;
+
+ aoss_funnel_in3: endpoint {
+ remote-endpoint = <&ddr_lpi_funnel_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+
+ aoss_funnel_in6: endpoint {
+ remote-endpoint = <&aoss_tpda_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+
+ aoss_funnel_in7: endpoint {
+ remote-endpoint = <&qdss_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ aoss_funnel_out: endpoint {
+ remote-endpoint = <&etf0_in>;
+ };
+ };
+ };
+ };
+
+ etf0: tmc@10b05000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x10b05000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ etf0_in: endpoint {
+ remote-endpoint = <&aoss_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etf0_out: endpoint {
+ remote-endpoint = <&swao_rep_in>;
+ };
+ };
+ };
+ };
+
+ replicator@10b06000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x10b06000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ swao_rep_in: endpoint {
+ remote-endpoint = <&etf0_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ swao_rep_out1: endpoint {
+ remote-endpoint = <&eud_in>;
+ };
+ };
+ };
+ };
+
+ tpda@10b08000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10b08000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ aoss_tpda_in0: endpoint {
+ remote-endpoint = <&aoss_tpdm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ aoss_tpda_in1: endpoint {
+ remote-endpoint = <&aoss_tpdm1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ aoss_tpda_in2: endpoint {
+ remote-endpoint = <&aoss_tpdm2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ aoss_tpda_in3: endpoint {
+ remote-endpoint = <&aoss_tpdm3_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ aoss_tpda_in4: endpoint {
+ remote-endpoint = <&aoss_tpdm4_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ aoss_tpda_out: endpoint {
+ remote-endpoint = <&aoss_funnel_in6>;
+ };
+ };
+ };
+ };
+
+ tpdm@10b09000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10b09000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ aoss_tpdm0_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@10b0a000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10b0a000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ aoss_tpdm1_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in1>;
+ };
+ };
+ };
+ };
+
+ tpdm@10b0b000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10b0b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ aoss_tpdm2_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in2>;
+ };
+ };
+ };
+ };
+
+ tpdm@10b0c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10b0c000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ aoss_tpdm3_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in3>;
+ };
+ };
+ };
+ };
+
+ tpdm@10b0d000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10b0d000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ aoss_tpdm4_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in4>;
+ };
+ };
+ };
+ };
+
+ tpdm@10b20000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10b20000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+ status = "disabled";
+
+ out-ports {
+ port {
+ lpicc_tpdm_out: endpoint {
+ remote-endpoint = <&ddr_lpi_tpda_in>;
+ };
+ };
+ };
+ };
+
+ tpda@10b23000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10b23000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+
+ in-ports {
+ port {
+ ddr_lpi_tpda_in: endpoint {
+ remote-endpoint = <&lpicc_tpdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ddr_lpi_tpda_out: endpoint {
+ remote-endpoint = <&ddr_lpi_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@10b24000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10b24000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+
+ in-ports {
+ port {
+ ddr_lpi_funnel_in0: endpoint {
+ remote-endpoint = <&ddr_lpi_tpda_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ddr_lpi_funnel_out: endpoint {
+ remote-endpoint = <&aoss_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ tpdm@10c08000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10c08000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ mm_tpdm_out: endpoint {
+ remote-endpoint = <&mm_funnel_in4>;
+ };
+ };
+ };
+ };
+
+ funnel@10c0b000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10c0b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@4 {
+ reg = <4>;
+
+ mm_funnel_in4: endpoint {
+ remote-endpoint = <&mm_tpdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ mm_funnel_out: endpoint {
+ remote-endpoint = <&dlct2_tpda_in4>;
+ };
+ };
+ };
+ };
+
+ tpdm@10c28000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10c28000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ dlct1_tpdm_out: endpoint {
+ remote-endpoint = <&dlct1_tpda_in26>;
+ };
+ };
+ };
+ };
+
+ tpdm@10c29000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10c29000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ ipcc_tpdm_out: endpoint {
+ remote-endpoint = <&dlct1_tpda_in27>;
+ };
+ };
+ };
+ };
+
+ tpda@10c2b000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10c2b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@4 {
+ reg = <4>;
+
+ dlct1_tpda_in4: endpoint {
+ remote-endpoint = <&lpass_cx_funnel_out>;
+ };
+ };
+
+ port@13 {
+ reg = <19>;
+
+ dlct1_tpda_in19: endpoint {
+ remote-endpoint = <&prng_tpdm_out>;
+ };
+ };
+
+ port@14 {
+ reg = <20>;
+
+ dlct1_tpda_in20: endpoint {
+ remote-endpoint = <&qm_tpdm_out>;
+ };
+ };
+
+ port@15 {
+ reg = <21>;
+
+ dlct1_tpda_in21: endpoint {
+ remote-endpoint = <&gcc_tpdm_out>;
+ };
+ };
+
+ port@1a {
+ reg = <26>;
+
+ dlct1_tpda_in26: endpoint {
+ remote-endpoint = <&dlct1_tpdm_out>;
+ };
+ };
+
+ port@1b {
+ reg = <27>;
+
+ dlct1_tpda_in27: endpoint {
+ remote-endpoint = <&ipcc_tpdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ dlct1_tpda_out: endpoint {
+ remote-endpoint = <&dlct1_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@10c2c000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10c2c000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dlct1_funnel_in0: endpoint {
+ remote-endpoint = <&dlct1_tpda_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ dlct1_funnel_in4: endpoint {
+ remote-endpoint = <&dlct2_funnel_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ dlct1_funnel_in5: endpoint {
+ remote-endpoint = <&ddr_funnel0_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ dlct1_funnel_out: endpoint {
+ remote-endpoint = <&funnel1_in6>;
+ };
+ };
+ };
+ };
+
+ tpdm@10c38000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10c38000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ dlct2_tpdm0_out: endpoint {
+ remote-endpoint = <&dlct2_tpda_in16>;
+ };
+ };
+ };
+ };
+
+ tpdm@10c39000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10c39000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ dlct2_tpdm1_out: endpoint {
+ remote-endpoint = <&dlct2_tpda_in17>;
+ };
+ };
+ };
+ };
+
+ tpda@10c3c000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10c3c000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@4 {
+ reg = <4>;
+
+ dlct2_tpda_in4: endpoint {
+ remote-endpoint = <&mm_funnel_out>;
+ };
+ };
+
+ port@f {
+ reg = <15>;
+
+ dlct2_tpda_in15: endpoint {
+ remote-endpoint = <&mxa_tpdm_out>;
+ };
+ };
+
+ port@10 {
+ reg = <16>;
+
+ dlct2_tpda_in16: endpoint {
+ remote-endpoint = <&dlct2_tpdm0_out>;
+ };
+ };
+
+ port@11 {
+ reg = <17>;
+
+ dlct2_tpda_in17: endpoint {
+ remote-endpoint = <&dlct2_tpdm1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ dlct2_tpda_out: endpoint {
+ remote-endpoint = <&dlct2_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@10c3d000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10c3d000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ dlct2_funnel_in0: endpoint {
+ remote-endpoint = <&dlct2_tpda_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ dlct2_funnel_out: endpoint {
+ remote-endpoint = <&dlct1_funnel_in4>;
+ };
+ };
+ };
+ };
+
+ tpdm@10cc1000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10cc1000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+ status = "disabled";
+
+ out-ports {
+ port {
+ tmess_tpdm1_out: endpoint {
+ remote-endpoint = <&tmess_tpda_in2>;
+ };
+ };
+ };
+ };
+
+ tpda@10cc4000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10cc4000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ tmess_tpda_in2: endpoint {
+ remote-endpoint = <&tmess_tpdm1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tmess_tpda_out: endpoint {
+ remote-endpoint = <&tmess_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@10cc5000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10cc5000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ tmess_funnel_in0: endpoint {
+ remote-endpoint = <&tmess_tpda_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tmess_funnel_out: endpoint {
+ remote-endpoint = <&funnel1_in2>;
+ };
+ };
+ };
+ };
+
+ funnel@10d04000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10d04000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@6 {
+ reg = <6>;
+
+ ddr_funnel0_in6: endpoint {
+ remote-endpoint = <&ddr_funnel1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ddr_funnel0_out: endpoint {
+ remote-endpoint = <&dlct1_funnel_in5>;
+ };
+ };
+ };
+ };
+
+ tpdm@10d08000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10d08000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ llcc0_tpdm_out: endpoint {
+ remote-endpoint = <&llcc_tpda_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@10d09000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10d09000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ llcc1_tpdm_out: endpoint {
+ remote-endpoint = <&llcc_tpda_in1>;
+ };
+ };
+ };
+ };
+
+ tpdm@10d0a000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10d0a000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ llcc2_tpdm_out: endpoint {
+ remote-endpoint = <&llcc_tpda_in2>;
+ };
+ };
+ };
+ };
+
+ tpdm@10d0b000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10d0b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ llcc3_tpdm_out: endpoint {
+ remote-endpoint = <&llcc_tpda_in3>;
+ };
+ };
+ };
+ };
+
+ tpdm@10d0c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10d0c000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ llcc4_tpdm_out: endpoint {
+ remote-endpoint = <&llcc_tpda_in4>;
+ };
+ };
+ };
+ };
+
+ tpdm@10d0d000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10d0d000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ llcc5_tpdm_out: endpoint {
+ remote-endpoint = <&llcc_tpda_in5>;
+ };
+ };
+ };
+ };
+
+ tpdm@10d0e000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10d0e000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ llcc6_tpdm_out: endpoint {
+ remote-endpoint = <&llcc_tpda_in6>;
+ };
+ };
+ };
+ };
+
+ tpdm@10d0f000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10d0f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ llcc7_tpdm_out: endpoint {
+ remote-endpoint = <&llcc_tpda_in7>;
+ };
+ };
+ };
+ };
+
+ tpda@10d12000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10d12000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ llcc_tpda_in0: endpoint {
+ remote-endpoint = <&llcc0_tpdm_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ llcc_tpda_in1: endpoint {
+ remote-endpoint = <&llcc1_tpdm_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ llcc_tpda_in2: endpoint {
+ remote-endpoint = <&llcc2_tpdm_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ llcc_tpda_in3: endpoint {
+ remote-endpoint = <&llcc3_tpdm_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ llcc_tpda_in4: endpoint {
+ remote-endpoint = <&llcc4_tpdm_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ llcc_tpda_in5: endpoint {
+ remote-endpoint = <&llcc5_tpdm_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+
+ llcc_tpda_in6: endpoint {
+ remote-endpoint = <&llcc6_tpdm_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+
+ llcc_tpda_in7: endpoint {
+ remote-endpoint = <&llcc7_tpdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ llcc_tpda_out: endpoint {
+ remote-endpoint = <&ddr_funnel1_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@10d13000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10d13000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ ddr_funnel1_in0: endpoint {
+ remote-endpoint = <&llcc_tpda_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ddr_funnel1_out: endpoint {
+ remote-endpoint = <&ddr_funnel0_in6>;
+ };
+ };
+ };
};
apps_smmu: iommu@15000000 {
@@ -5754,6 +7995,20 @@
dma-coherent;
};
+ pcie_smmu: iommu@15400000 {
+ compatible = "arm,smmu-v3";
+ reg = <0 0x15400000 0 0x80000>;
+ #iommu-cells = <1>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eventq",
+ "gerror",
+ "cmdq-sync";
+ dma-coherent;
+ status = "reserved"; /* Controlled by Gunyah. */
+ };
+
intc: interrupt-controller@17000000 {
compatible = "arm,gic-v3";
reg = <0 0x17000000 0 0x10000>, /* GICD */
@@ -5780,6 +8035,13 @@
};
};
+ cpucp_mbox: mailbox@17430000 {
+ compatible = "qcom,x1e80100-cpucp-mbox";
+ reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ };
+
apps_rsc: rsc@17500000 {
compatible = "qcom,rpmh-rsc";
reg = <0 0x17500000 0 0x10000>,
@@ -5963,6 +8225,32 @@
};
};
+ sram: sram@18b4e000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x18b4e000 0x0 0x400>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x18b4e000 0x400>;
+
+ cpu_scp_lpri0: scp-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x200>;
+ };
+
+ cpu_scp_lpri1: scp-sram-section@200 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x200 0x200>;
+ };
+ };
+
+ sbsa_watchdog: watchdog@1c840000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0 0x1c840000 0 0x1000>,
+ <0 0x1c850000 0 0x1000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
pmu@24091000 {
compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
reg = <0 0x24091000 0 0x1000>;
@@ -6020,7 +8308,7 @@
};
/* cluster0 */
- pmu@240b3400 {
+ bwmon_cluster0: pmu@240b3400 {
compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
reg = <0 0x240b3400 0 0x600>;
@@ -6030,6 +8318,19 @@
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
operating-points-v2 = <&cpu_bwmon_opp_table>;
+ };
+
+ /* cluster2 */
+ bwmon_cluster2: pmu@240b5400 {
+ compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
+ reg = <0 0x240b5400 0 0x600>;
+
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
cpu_bwmon_opp_table: opp-table {
compatible = "operating-points-v2";
@@ -6060,19 +8361,6 @@
};
};
- /* cluster2 */
- pmu@240b5400 {
- compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
- reg = <0 0x240b5400 0 0x600>;
-
- interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
-
- interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
- &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
-
- operating-points-v2 = <&cpu_bwmon_opp_table>;
- };
-
/* cluster1 */
pmu@240b6400 {
compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
@@ -6111,146 +8399,9 @@
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
};
- remoteproc_adsp: remoteproc@30000000 {
- compatible = "qcom,x1e80100-adsp-pas";
- reg = <0 0x30000000 0 0x100>;
-
- interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
- <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "wdog",
- "fatal",
- "ready",
- "handover",
- "stop-ack";
-
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "xo";
-
- power-domains = <&rpmhpd RPMHPD_LCX>,
- <&rpmhpd RPMHPD_LMX>;
- power-domain-names = "lcx",
- "lmx";
-
- interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
- &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
-
- memory-region = <&adspslpi_mem>,
- <&q6_adsp_dtb_mem>;
-
- qcom,qmp = <&aoss_qmp>;
-
- qcom,smem-states = <&smp2p_adsp_out 0>;
- qcom,smem-state-names = "stop";
-
- status = "disabled";
-
- glink-edge {
- interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
- IPCC_MPROC_SIGNAL_GLINK_QMP
- IRQ_TYPE_EDGE_RISING>;
- mboxes = <&ipcc IPCC_CLIENT_LPASS
- IPCC_MPROC_SIGNAL_GLINK_QMP>;
-
- label = "lpass";
- qcom,remote-pid = <2>;
-
- fastrpc {
- compatible = "qcom,fastrpc";
- qcom,glink-channels = "fastrpcglink-apps-dsp";
- label = "adsp";
- qcom,non-secure-domain;
- #address-cells = <1>;
- #size-cells = <0>;
-
- compute-cb@3 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <3>;
- iommus = <&apps_smmu 0x1003 0x80>,
- <&apps_smmu 0x1063 0x0>;
- dma-coherent;
- };
-
- compute-cb@4 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <4>;
- iommus = <&apps_smmu 0x1004 0x80>,
- <&apps_smmu 0x1064 0x0>;
- dma-coherent;
- };
-
- compute-cb@5 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <5>;
- iommus = <&apps_smmu 0x1005 0x80>,
- <&apps_smmu 0x1065 0x0>;
- dma-coherent;
- };
-
- compute-cb@6 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <6>;
- iommus = <&apps_smmu 0x1006 0x80>,
- <&apps_smmu 0x1066 0x0>;
- dma-coherent;
- };
-
- compute-cb@7 {
- compatible = "qcom,fastrpc-compute-cb";
- reg = <7>;
- iommus = <&apps_smmu 0x1007 0x80>,
- <&apps_smmu 0x1067 0x0>;
- dma-coherent;
- };
- };
-
- gpr {
- compatible = "qcom,gpr";
- qcom,glink-channels = "adsp_apps";
- qcom,domain = <GPR_DOMAIN_ID_ADSP>;
- qcom,intents = <512 20>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- q6apm: service@1 {
- compatible = "qcom,q6apm";
- reg = <GPR_APM_MODULE_IID>;
- #sound-dai-cells = <0>;
- qcom,protection-domain = "avs/audio",
- "msm/adsp/audio_pd";
-
- q6apmbedai: bedais {
- compatible = "qcom,q6apm-lpass-dais";
- #sound-dai-cells = <1>;
- };
-
- q6apmdai: dais {
- compatible = "qcom,q6apm-dais";
- iommus = <&apps_smmu 0x1001 0x80>,
- <&apps_smmu 0x1061 0x0>;
- };
- };
-
- q6prm: service@2 {
- compatible = "qcom,q6prm";
- reg = <GPR_PRM_MODULE_IID>;
- qcom,protection-domain = "avs/audio",
- "msm/adsp/audio_pd";
-
- q6prmcc: clock-controller {
- compatible = "qcom,q6prm-lpass-clocks";
- #clock-cells = <2>;
- };
- };
- };
- };
- };
-
remoteproc_cdsp: remoteproc@32300000 {
compatible = "qcom,x1e80100-cdsp-pas";
- reg = <0 0x32300000 0 0x1400000>;
+ reg = <0x0 0x32300000 0x0 0x10000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -6403,7 +8554,7 @@
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
- thermal-zones {
+ thermal_zones: thermal-zones {
aoss0-thermal {
thermal-sensors = <&tsens0 0>;
@@ -6415,33 +8566,19 @@
};
aoss0-critical {
- temperature = <125000>;
- hysteresis = <0>;
+ temperature = <115000>;
+ hysteresis = <1000>;
type = "critical";
};
};
};
cpu0-0-top-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens0 1>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -6449,25 +8586,11 @@
};
cpu0-0-btm-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens0 2>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -6475,25 +8598,11 @@
};
cpu0-1-top-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens0 3>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -6501,25 +8610,11 @@
};
cpu0-1-btm-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens0 4>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -6527,25 +8622,11 @@
};
cpu0-2-top-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens0 5>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -6553,25 +8634,11 @@
};
cpu0-2-btm-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens0 6>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -6579,25 +8646,11 @@
};
cpu0-3-top-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens0 7>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -6605,25 +8658,11 @@
};
cpu0-3-btm-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens0 8>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -6634,15 +8673,9 @@
thermal-sensors = <&tsens0 9>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
-
cpuss2-critical {
- temperature = <125000>;
- hysteresis = <0>;
+ temperature = <115000>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -6652,15 +8685,9 @@
thermal-sensors = <&tsens0 10>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
-
cpuss2-critical {
- temperature = <125000>;
- hysteresis = <0>;
+ temperature = <115000>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -6677,7 +8704,7 @@
};
mem-critical {
- temperature = <125000>;
+ temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
@@ -6685,15 +8712,19 @@
};
video-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens0 12>;
trips {
trip-point0 {
- temperature = <125000>;
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ video-critical {
+ temperature = <115000>;
hysteresis = <1000>;
- type = "passive";
+ type = "critical";
};
};
};
@@ -6709,33 +8740,19 @@
};
aoss0-critical {
- temperature = <125000>;
- hysteresis = <0>;
+ temperature = <115000>;
+ hysteresis = <1000>;
type = "critical";
};
};
};
cpu1-0-top-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens1 1>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -6743,25 +8760,11 @@
};
cpu1-0-btm-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens1 2>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -6769,25 +8772,11 @@
};
cpu1-1-top-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens1 3>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -6795,25 +8784,11 @@
};
cpu1-1-btm-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens1 4>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -6821,25 +8796,11 @@
};
cpu1-2-top-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens1 5>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -6847,25 +8808,11 @@
};
cpu1-2-btm-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens1 6>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -6873,25 +8820,11 @@
};
cpu1-3-top-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens1 7>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -6899,25 +8832,11 @@
};
cpu1-3-btm-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens1 8>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -6928,15 +8847,9 @@
thermal-sensors = <&tsens1 9>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
-
cpuss2-critical {
- temperature = <125000>;
- hysteresis = <0>;
+ temperature = <115000>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -6946,15 +8859,9 @@
thermal-sensors = <&tsens1 10>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
-
cpuss2-critical {
- temperature = <125000>;
- hysteresis = <0>;
+ temperature = <115000>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -6971,33 +8878,19 @@
};
aoss0-critical {
- temperature = <125000>;
- hysteresis = <0>;
+ temperature = <115000>;
+ hysteresis = <1000>;
type = "critical";
};
};
};
cpu2-0-top-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens2 1>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -7005,25 +8898,11 @@
};
cpu2-0-btm-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens2 2>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -7031,25 +8910,11 @@
};
cpu2-1-top-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens2 3>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -7057,25 +8922,11 @@
};
cpu2-1-btm-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens2 4>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -7083,25 +8934,11 @@
};
cpu2-2-top-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens2 5>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -7109,25 +8946,11 @@
};
cpu2-2-btm-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens2 6>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -7135,25 +8958,11 @@
};
cpu2-3-top-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens2 7>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -7161,25 +8970,11 @@
};
cpu2-3-btm-thermal {
- polling-delay-passive = <250>;
-
thermal-sensors = <&tsens2 8>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- trip-point1 {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
cpu-critical {
- temperature = <110000>;
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -7190,15 +8985,9 @@
thermal-sensors = <&tsens2 9>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
-
cpuss2-critical {
- temperature = <125000>;
- hysteresis = <0>;
+ temperature = <115000>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -7208,15 +8997,9 @@
thermal-sensors = <&tsens2 10>;
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "hot";
- };
-
cpuss2-critical {
- temperature = <125000>;
- hysteresis = <0>;
+ temperature = <115000>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -7233,8 +9016,8 @@
};
aoss0-critical {
- temperature = <125000>;
- hysteresis = <0>;
+ temperature = <115000>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -7251,8 +9034,8 @@
};
nsp0-critical {
- temperature = <125000>;
- hysteresis = <0>;
+ temperature = <115000>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -7269,8 +9052,8 @@
};
nsp1-critical {
- temperature = <125000>;
- hysteresis = <0>;
+ temperature = <115000>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -7287,8 +9070,8 @@
};
nsp2-critical {
- temperature = <125000>;
- hysteresis = <0>;
+ temperature = <115000>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -7305,33 +9088,34 @@
};
nsp3-critical {
- temperature = <125000>;
- hysteresis = <0>;
+ temperature = <115000>;
+ hysteresis = <1000>;
type = "critical";
};
};
};
gpuss-0-thermal {
- polling-delay-passive = <10>;
+ polling-delay-passive = <200>;
thermal-sensors = <&tsens3 5>;
- trips {
- trip-point0 {
- temperature = <85000>;
- hysteresis = <1000>;
- type = "passive";
+ cooling-maps {
+ map0 {
+ trip = <&gpuss0_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
+ };
- trip-point1 {
- temperature = <90000>;
+ trips {
+ gpuss0_alert0: trip-point0 {
+ temperature = <95000>;
hysteresis = <1000>;
- type = "hot";
+ type = "passive";
};
- trip-point2 {
- temperature = <125000>;
+ gpu-critical {
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -7339,25 +9123,26 @@
};
gpuss-1-thermal {
- polling-delay-passive = <10>;
+ polling-delay-passive = <200>;
thermal-sensors = <&tsens3 6>;
- trips {
- trip-point0 {
- temperature = <85000>;
- hysteresis = <1000>;
- type = "passive";
+ cooling-maps {
+ map0 {
+ trip = <&gpuss1_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
+ };
- trip-point1 {
- temperature = <90000>;
+ trips {
+ gpuss1_alert0: trip-point0 {
+ temperature = <95000>;
hysteresis = <1000>;
- type = "hot";
+ type = "passive";
};
- trip-point2 {
- temperature = <125000>;
+ gpu-critical {
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -7365,25 +9150,26 @@
};
gpuss-2-thermal {
- polling-delay-passive = <10>;
+ polling-delay-passive = <200>;
thermal-sensors = <&tsens3 7>;
- trips {
- trip-point0 {
- temperature = <85000>;
- hysteresis = <1000>;
- type = "passive";
+ cooling-maps {
+ map0 {
+ trip = <&gpuss2_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
+ };
- trip-point1 {
- temperature = <90000>;
+ trips {
+ gpuss2_alert0: trip-point0 {
+ temperature = <95000>;
hysteresis = <1000>;
- type = "hot";
+ type = "passive";
};
- trip-point2 {
- temperature = <125000>;
+ gpu-critical {
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -7391,25 +9177,26 @@
};
gpuss-3-thermal {
- polling-delay-passive = <10>;
+ polling-delay-passive = <200>;
thermal-sensors = <&tsens3 8>;
- trips {
- trip-point0 {
- temperature = <85000>;
- hysteresis = <1000>;
- type = "passive";
+ cooling-maps {
+ map0 {
+ trip = <&gpuss3_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
+ };
- trip-point1 {
- temperature = <90000>;
+ trips {
+ gpuss3_alert0: trip-point0 {
+ temperature = <95000>;
hysteresis = <1000>;
- type = "hot";
+ type = "passive";
};
- trip-point2 {
- temperature = <125000>;
+ gpu-critical {
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -7417,25 +9204,26 @@
};
gpuss-4-thermal {
- polling-delay-passive = <10>;
+ polling-delay-passive = <200>;
thermal-sensors = <&tsens3 9>;
- trips {
- trip-point0 {
- temperature = <85000>;
- hysteresis = <1000>;
- type = "passive";
+ cooling-maps {
+ map0 {
+ trip = <&gpuss4_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
+ };
- trip-point1 {
- temperature = <90000>;
+ trips {
+ gpuss4_alert0: trip-point0 {
+ temperature = <95000>;
hysteresis = <1000>;
- type = "hot";
+ type = "passive";
};
- trip-point2 {
- temperature = <125000>;
+ gpu-critical {
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -7443,25 +9231,26 @@
};
gpuss-5-thermal {
- polling-delay-passive = <10>;
+ polling-delay-passive = <200>;
thermal-sensors = <&tsens3 10>;
- trips {
- trip-point0 {
- temperature = <85000>;
- hysteresis = <1000>;
- type = "passive";
+ cooling-maps {
+ map0 {
+ trip = <&gpuss5_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
+ };
- trip-point1 {
- temperature = <90000>;
+ trips {
+ gpuss5_alert0: trip-point0 {
+ temperature = <95000>;
hysteresis = <1000>;
- type = "hot";
+ type = "passive";
};
- trip-point2 {
- temperature = <125000>;
+ gpu-critical {
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -7469,25 +9258,26 @@
};
gpuss-6-thermal {
- polling-delay-passive = <10>;
+ polling-delay-passive = <200>;
thermal-sensors = <&tsens3 11>;
- trips {
- trip-point0 {
- temperature = <85000>;
- hysteresis = <1000>;
- type = "passive";
+ cooling-maps {
+ map0 {
+ trip = <&gpuss6_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
+ };
- trip-point1 {
- temperature = <90000>;
+ trips {
+ gpuss6_alert0: trip-point0 {
+ temperature = <95000>;
hysteresis = <1000>;
- type = "hot";
+ type = "passive";
};
- trip-point2 {
- temperature = <125000>;
+ gpu-critical {
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -7495,25 +9285,26 @@
};
gpuss-7-thermal {
- polling-delay-passive = <10>;
+ polling-delay-passive = <200>;
thermal-sensors = <&tsens3 12>;
- trips {
- trip-point0 {
- temperature = <85000>;
- hysteresis = <1000>;
- type = "passive";
+ cooling-maps {
+ map0 {
+ trip = <&gpuss7_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
+ };
- trip-point1 {
- temperature = <90000>;
+ trips {
+ gpuss7_alert0: trip-point0 {
+ temperature = <95000>;
hysteresis = <1000>;
- type = "hot";
+ type = "passive";
};
- trip-point2 {
- temperature = <125000>;
+ gpu-critical {
+ temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
@@ -7532,7 +9323,7 @@
camera0-critical {
temperature = <115000>;
- hysteresis = <0>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -7550,7 +9341,7 @@
camera0-critical {
temperature = <115000>;
- hysteresis = <0>;
+ hysteresis = <1000>;
type = "critical";
};
};
generated by cgit v1.2.3 (git 2.39.0) at 2025-08-12 01:48:41 +0300