diff options
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sm6125.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm6125.dtsi | 59 |
1 files changed, 32 insertions, 27 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 2b37ce6a9f9c..51286ddbdb10 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -326,8 +326,8 @@ tlmm: pinctrl@500000 { compatible = "qcom,sm6125-tlmm"; reg = <0x00500000 0x400000>, - <0x00900000 0x400000>, - <0x00d00000 0x400000>; + <0x00900000 0x400000>, + <0x00d00000 0x400000>; reg-names = "west", "south", "east"; interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; @@ -380,7 +380,7 @@ status = "disabled"; }; - rpm_msg_ram: memory@45f0000 { + rpm_msg_ram: sram@45f0000 { compatible = "qcom,rpm-msg-ram"; reg = <0x045f0000 0x7000>; }; @@ -391,12 +391,12 @@ reg-names = "hc", "core"; interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>; + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; clock-names = "iface", "core", "xo"; bus-width = <8>; non-removable; @@ -409,12 +409,12 @@ reg-names = "hc"; interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&xo_board>; + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; clock-names = "iface", "core", "xo"; pinctrl-0 = <&sdc2_state_on>; @@ -433,11 +433,11 @@ ranges; clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>; @@ -460,13 +460,18 @@ }; }; + sram@4690000 { + compatible = "qcom,rpm-stats"; + reg = <0x04690000 0x10000>; + }; + spmi_bus: spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0x01c40000 0x1100>, - <0x01e00000 0x2000000>, - <0x03e00000 0x100000>, - <0x03f00000 0xa0000>, - <0x01c0a000 0x26000>; + reg = <0x01c40000 0x1100>, + <0x01e00000 0x2000000>, + <0x03e00000 0x100000>, + <0x03f00000 0xa0000>, + <0x01c0a000 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; @@ -494,22 +499,22 @@ reg = <0x0f120000 0x1000>; clock-frequency = <19200000>; - frame@0f121000 { + frame@f121000 { frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0f121000 0x1000>, <0x0f122000 0x1000>; }; - frame@0f123000 { + frame@f123000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0f123000 0x1000>; status = "disabled"; }; - frame@0f124000 { + frame@f124000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0f124000 0x1000>; @@ -548,7 +553,7 @@ intc: interrupt-controller@f200000 { compatible = "arm,gic-v3"; reg = <0x0f200000 0x20000>, - <0x0f300000 0x100000>; + <0x0f300000 0x100000>; #interrupt-cells = <3>; interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; @@ -558,9 +563,9 @@ timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 1 0xf08 - GIC_PPI 2 0xf08 - GIC_PPI 3 0xf08 - GIC_PPI 0 0xf08>; + GIC_PPI 2 0xf08 + GIC_PPI 3 0xf08 + GIC_PPI 0 0xf08>; clock-frequency = <19200000>; }; }; |